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spark2k06spark2k06
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Initial version
Unstable version: * Hardware interrupts are not executed. * No VHD or SD support. * BASIC ROM execution set in the BIOS, before the OS load routine.
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‎PCXT.qpf

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QUARTUS_VERSION = "17.0"
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PROJECT_REVISION = "PCXT"

‎PCXT.qsf

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# --------------------------------------------------------------------------
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#
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# MiSTer project
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#
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# WARNING WARNING WARNING:
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# Do not add files to project in Quartus IDE! It will mess this file!
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# Add the files manually to files.qip file.
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#
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# --------------------------------------------------------------------------
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set_global_assignment -name TOP_LEVEL_ENTITY sys_top
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name LAST_QUARTUS_VERSION "17.1.0 Standard Edition"
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set_global_assignment -name GENERATE_RBF_FILE ON
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
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set_global_assignment -name SAVE_DISK_SPACE OFF
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set_global_assignment -name SMART_RECOMPILE ON
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
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set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
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set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
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set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
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set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
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set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
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set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
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set_global_assignment -name ALLOW_POWER_UP_DONT_CARE ON
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set_global_assignment -name QII_AUTO_PACKED_REGISTERS NORMAL
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set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON
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set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
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set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
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set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
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set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
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set_global_assignment -name MUX_RESTRUCTURE ON
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set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
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set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS ON
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set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
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set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
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set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION ON
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set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON
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set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
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set_global_assignment -name ECO_OPTIMIZE_TIMING ON
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set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION ON
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set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
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set_global_assignment -name ALM_REGISTER_PACKING_EFFORT MEDIUM
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set_global_assignment -name SEED 1
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#set_global_assignment -name VERILOG_MACRO "MISTER_FB=1"
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#enable it only if 8bit indexed mode is used in core
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#set_global_assignment -name VERILOG_MACRO "MISTER_FB_PALETTE=1"
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#set_global_assignment -name VERILOG_MACRO "MISTER_DUAL_SDRAM=1"
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#do not enable DEBUG_NOHDMI in release!
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#set_global_assignment -name VERILOG_MACRO "MISTER_DEBUG_NOHDMI=1"
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source sys/sys.tcl
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source sys/sys_analog.tcl
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source files.qip
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set_global_assignment -name VERILOG_FILE rtl/common/vram.v
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set_global_assignment -name VERILOG_FILE rtl/common/ram.v
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set_global_assignment -name VERILOG_FILE rtl/common/clk_div3.v
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set_global_assignment -name SDC_FILE PCXT_MiSTer.sdc
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set_global_assignment -name VERILOG_FILE rtl/common/bios.v
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set_global_assignment -name VERILOG_FILE rtl/8088/mcl86_eu_core.v
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set_global_assignment -name VERILOG_FILE rtl/8088/i8088.v
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set_global_assignment -name VERILOG_FILE rtl/8088/eu_rom.v
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set_global_assignment -name VERILOG_FILE rtl/8088/biu_min.v
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set_global_assignment -name VERILOG_FILE rtl/8088/biu_max.v
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set_global_assignment -name CDF_FILE jtag.cdf
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set_global_assignment -name QIP_FILE sys/sys.qip
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set_global_assignment -name SDC_FILE PCXT.sdc
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set_global_assignment -name SYSTEMVERILOG_FILE PCXT.sv
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set_global_assignment -name VERILOG_FILE rtl/system.v
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set_global_assignment -name VERILOG_FILE rtl/common/cga.v
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set_global_assignment -name VERILOG_FILE rtl/common/cga_attrib.v
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set_global_assignment -name VERILOG_FILE rtl/common/cga_pixel.v
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set_global_assignment -name VERILOG_FILE rtl/common/cga_scandoubler.v
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set_global_assignment -name VERILOG_FILE rtl/common/cga_sequencer.v
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set_global_assignment -name VERILOG_FILE rtl/common/cga_vgaport.v
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set_global_assignment -name VERILOG_FILE rtl/common/crtc6845.v
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set_global_assignment -name VERILOG_FILE rtl/common/KB_8042.v
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set_global_assignment -name VERILOG_FILE rtl/common/PIC_8259.v
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set_global_assignment -name VERILOG_FILE rtl/common/timer8253.v
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set_global_assignment -name VERILOG_FILE rtl/common/vga.v
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set_global_assignment -name SIP_FILE pll.sip
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set_global_assignment -name QIP_FILE rtl/pll.qip
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set_global_assignment -name SIP_FILE rtl/pll.sip
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

‎PCXT.sdc

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derive_pll_clocks
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derive_clock_uncertainty
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# core specific constraints

‎PCXT.srf

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{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "Synthesized away node \"emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|outclk_wire\[2\]\"" { } { } 0 14320 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "RST port on the PLL is not properly connected on instance emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[1\].gpll. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock." { } { } 0 0 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "RST port on the PLL is not properly connected on instance emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[0\].gpll. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock." { } { } 0 0 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "Ignored locations or region assignments to the following nodes" { } { } 0 15705 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "RST port on the PLL is not properly connected on instance emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[2\].gpll. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock." { } { } 0 0 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(129): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(134): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "Verilog HDL or VHDL warning at sys_top.v(209): object \"vip_newcfg\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "Verilog HDL or VHDL warning at sys_top.v(594): object \"VSET\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "Ignored filter at sys_top.sdc(17): vip\|output_inst\|vid_clk could not be matched with a net" { } { } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "Ignored create_generated_clock at sys_top.sdc(16): Argument <targets> is an empty collection" { } { } 0 332049 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "Ignored filter at sys_top.sdc(37): VID_CLK could not be matched with a clock" { } { } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_audio:pll_audio\|pll_audio_0002:pll_audio_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "*" { } { } 0 21074 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "*" { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "*" { } { } 0 276027 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "altera_pll.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "altera_cyclonev_pll.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "altera_pll_reconfig_core.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "cyclonev_pll" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}

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