Cortex-A9 PMU event for instructions retired #58
Description
In the A9 TRM, there is a note that events 0x08 (instruction retired) and 0x0E (BR return retired) are not implemented. They are listed in this repository. Is it known that there are any chips that implement this event anyway even though the TRM specifically excludes them? If not, can the xml files here and the json in the data repo be changed to reflect the exclusion of these counters?