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README.md

Milestone 1

Documentation

Reports

If you want more information about the implementation, you could read - or at least try, unfortunately, is in greek language - this report file Milestone 1 or by reading the inline documentation.

Diagrams

Block and timing diagrams are able to be changed:

Usage

Enviroment

This project was developed using Xilinx Vivado 2017.4

Import and Run

In order to import project:

Option 1
  1. Open Vivado 2017.4 and using it open reference project

  2. Open Block Design

  3. From IP Catalog -> Open my_ip in IP Packager editor

  4. Replace myip_v1_1.vhd, myip_v1_1_S00_AXIS.vhd and myip_v1_1_M00_AXIS.vhd with these files (do not forget excepting myip_v1_1_FIFO.vhd if you use copy-paste)

  5. From Sources tab select add source -> Add or create design sources -> Add files -> Select this file

  6. Open Package Ip -> Identification -> Change version

  7. From Package Ip -> File Groups -> Merge changes from File Groups Wizard

  8. From Package Ip -> Review and Package -> Package Ip

  9. Completed

Option 2
  1. Open Vivado 2017.4 and using it open project

If you want to run simulations:

  1. Just select add source from sources tab when you are on IP Packager -> Add or create simulation sources -> Add files -> Select one or more of these test files

  2. Run simulation

  3. File -> Open Waveform Configuration -> Select the associated waveform file

(Simulation screenshots are included here)