If you want more information about the implementation, you could read - or at least try, unfortunately, is in greek language - this report file Milestone 1 or by reading the inline documentation.
Block and timing diagrams are able to be changed:
- For xml files (block diagrams) we have used draw.io
- For json files (timing diagrams) we have used Wavedrom editor
This project was developed using Xilinx Vivado 2017.4
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Open Vivado 2017.4 and using it open reference project
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Open Block Design
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From IP Catalog -> Open my_ip in IP Packager editor
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Replace myip_v1_1.vhd, myip_v1_1_S00_AXIS.vhd and myip_v1_1_M00_AXIS.vhd with these files (do not forget excepting myip_v1_1_FIFO.vhd if you use copy-paste)
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From Sources tab select add source -> Add or create design sources -> Add files -> Select this file
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Open Package Ip -> Identification -> Change version
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From Package Ip -> File Groups -> Merge changes from File Groups Wizard
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From Package Ip -> Review and Package -> Package Ip
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Completed
- Open Vivado 2017.4 and using it open project
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Just select add source from sources tab when you are on IP Packager -> Add or create simulation sources -> Add files -> Select one or more of these test files
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Run simulation
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File -> Open Waveform Configuration -> Select the associated waveform file
(Simulation screenshots are included here)