Workflow of adding instruction in CHERI RISC-V

[SyedFahimuddinAlavi]

A naive question, I want to modify CHERI RISC-V ISA by adding an crypto instruction so compiler should also need to be modified to generate instruction. Is there any document of workflow that how many repositories need to be modified or any similar commits by your group?

[jrtc27]

Well the short answer is you modify the things you need modified. If you want a compiler then you modify the compiler, CHERI LLVM. If you want an OS then you modify the OS, CheriBSD (or bring your own OS, e.g. an RTOS). If you want an emulator then you modify the emulator, QEMU. If you want a formal model then you modify the model, sail-cheri-riscv. If you want an FPGA implementation then you modify an FPGA implementation, one of CHERI Piccolo/Flute/Toooba. So we can't tell you want you need to modify without knowing what you want to do, and at that point such detail will likely answer your own question for you.

[jrtc27]

Also, depending what you're adding, I'm not sure if it'd be particularly interesting to add to CHERI-RISC-V. Crypto instructions are generally purely arithmetic, with no interaction with memory safety or compartmentalisation, so on the surface it sounds like what you're proposing is completely orthogonal to the areas of the ISA affected by CHERI.