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Description
This is a small design doc around a change to the way we load memory and registers.
Problem
Currently, we have separate methods for performing vector x vector operations and vector x value operations, but this has a few issues:
- Requires a separate function for each combination (
vector_x_value,value_x_value,vector_x_vector)- Currently
value_x_vectorops are not implemented, but we do need them :(
- Currently
- Harder to maintain across changes and inflates code-base.
- Requires that slice sizes are both the same, which artificially limits us to pre-broadcasting data before being able to correctly operate on it.
The initial trait idea
To skirt around these issues, the plan is to create a trait that represents a state machine, it knows the start and end bounds of its memory, the end result buffer size, and how it wants to load that data into our SIMD registers.
- This approach potentially allows us at a later stage to implement broadcasting without needlessly allocating, along with supporting strides, etc...
- Allows us to provide a single generic function that can take any pattern of
op(value, value),op(value, vector),op(vector, value),op(vector, vector)
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