forked from jks-prv/Beagle_SDR_GPS
-
Notifications
You must be signed in to change notification settings - Fork 0
/
kiwi.config
337 lines (271 loc) · 9.8 KB
/
kiwi.config
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
// configuration
DEFh CFG_SDR_4RX_4WF 1
DEFh CFG_SDR_8RX_2WF 0
DEFh CFG_GPS_ONLY 0
// options
DEFh ARTIX_7A35 1
DEFh ZYNQ_7007 0
DEFh QUICK_BUILD 0
DEFp FPGA_VER 4'd1
DEFp FW_ID 0x5000
DEFp ADC_BITS 14
DEFp DEFAULT_NSYNC 2 // bits in synchronizers
DEFh USE_MIX_DDS 1
DEFh USE_GEN 0
DEFh USE_HBEAT 0
DEFh USE_LOGGER 1
DEFh USE_CPU_CTR 1
DEFh USE_DEBUG 1
DEFh USE_VIVADO 1
DEFh SERIES_7 1
DEFh SPI_PUMP_CHECK 0
DEFh STACK_CHECK 0
DEFh SND_SEQ_CHECK 0
DEFh SND_TIMING_CK 0
DEFh MEAS_CIC_OUT 0
DEFp FPGA_ID_QUICK 4'd0
DEFp FPGA_ID_RX8_WF2 4'd1
DEFp FPGA_ID_GPS 4'd2
DEFp FPGA_ID_RX4_WF4 4'd3
#if CFG_SDR_4RX_4WF
DEFp NUM_CMDS 41
#if ARTIX_7A35
DEFp GPS_CHANS 12
DEFp RX_CHANS 4
DEFp WF_CHANS 4
DEFp FPGA_ID1 FPGA_ID_RX4_WF4
DEFh USE_RX_SEQ 0 // fixme: tmp due to out-of-brams
#endif
#if ZYNQ_7007
DEFp GPS_CHANS 8
DEFp RX_CHANS 4
DEFp WF_CHANS 4
DEFp FPGA_ID1 FPGA_ID_QUICK
DEFh USE_RX_SEQ 0 // fixme: tmp due to out-of-brams
#endif
#if QUICK_BUILD
DEFp GPS_CHANS 12
DEFp RX_CHANS 3
DEFp WF_CHANS 3
DEFp FPGA_ID1 FPGA_ID_QUICK
DEFh USE_RX_SEQ 0 // fixme: tmp due to out-of-brams
#endif
#endif
#if CFG_SDR_8RX_2WF
DEFp NUM_CMDS 41
#if QUICK_BUILD
DEFp GPS_CHANS 4
DEFp RX_CHANS 2
DEFp WF_CHANS 0
DEFp FPGA_ID1 FPGA_ID_QUICK
DEFh USE_RX_SEQ 0 // fixme: tmp due to out-of-brams
#else
DEFp GPS_CHANS 12
DEFp RX_CHANS 8
DEFp WF_CHANS 2
DEFp FPGA_ID1 FPGA_ID_RX8_WF2
DEFh USE_RX_SEQ 0 // fixme: tmp due to out-of-brams
#endif
#endif
#if GPS_ONLY_BUILD
DEFp NUM_CMDS 30
#if QUICK_BUILD
DEFp GPS_CHANS 4
DEFp RX_CHANS 0
DEFp WF_CHANS 0
DEFp FPGA_ID1 FPGA_ID_QUICK
DEFh USE_RX_SEQ 0 // fixme: tmp due to out-of-brams
#else
DEFp GPS_CHANS 12
DEFp RX_CHANS 0
DEFp WF_CHANS 0
DEFp FPGA_ID1 FPGA_ID_GPS
DEFh USE_RX_SEQ 0 // fixme: tmp due to out-of-brams
#endif
#endif
; ============================================================================
// SPI
DEFh SPI_32 1
DEFp SPIBUF_W 2048 // limited by use of single 2K x 16 (36 kb) BRAM in host.v
DEFp SPIBUF_B SPIBUF_W * 2
// rx
// don't forget to redo the CIC filter compensation when SND_RATE changed
DEFp SND_RATE 12000
DEFp RX1_DECIM 505 // to get near 12000 for integer WSPR sample rate
DEFp RX2_DECIM 11 // 505*11 = 5555, 66.6666M/5555 = 12001.188 Hz
DEFp RXBUF_SIZE_4CH 8192 // given 8k x 16b audio buffer in receiver.v
DEFp RXBUF_SIZE_8CH 16384 // given 16k x 16b audio buffer in receiver.v
#if RX_CHANS 4
// for SPIBUF_W = 2048, RX_CHANS = 4, => NRX_SAMPS = 170
// 1/(12000/NRX_SAMPS) = interrupt every 14 ms / 71 Hz
DEFp RXBUF_SIZE RXBUF_SIZE_4CH
#endif
#if RX_CHANS 8
// for SPIBUF_W = 2048, RX_CHANS = 8, => NRX_SAMPS = 85
// 1/(12000/NRX_SAMPS) = interrupt every 7 ms / 141 Hz
DEFh RXBUF_LARGE 1
DEFp RXBUF_SIZE RXBUF_SIZE_8CH
#endif
DEFp NRX_IQW 3 // 1.5 words (24-bits) per I,Q
DEFp NRX_SPI SPIBUF_W
DEFp NRX_OVHD 3 + 1 + 1 // ticks 3w, count 1w, round up 1w
DEFp NRX_SAMPS NRX_SPI - NRX_OVHD / NRX_IQW / RX_CHANS
DEFp NRX_SAMPS_RPT 8
DEFp NRX_SAMPS_LOOP NRX_SAMPS * RX_CHANS / NRX_SAMPS_RPT
DEFp NRX_SAMPS_LOOP2 NRX_SAMPS_LOOP * NRX_SAMPS_RPT
DEFp NRX_SAMPS_REM NRX_SAMPS * RX_CHANS - NRX_SAMPS_LOOP2
DEFh USE_RX_CIC24 0
#if USE_RX_CIC24
DEFp RX1_BITS 24
DEFp RX2_BITS 23
#else
DEFp RX1_BITS 22
DEFp RX2_BITS 18
//DEFp RX1_BITS 16
//DEFp RX2_BITS 16
#endif
DEFp RXO_BITS 24
DEFp RX1_STAGES 3
DEFp RX2_STAGES 5
// waterfall
DEFh WF_EXISTS WF_CHANS
DEFp MAX_ZOOM 14
DEFp NWF_FFT 8192
DEFp NWF_IQW 2 // 1 word (16-bits) per I,Q
DEFp NWF_NXFER NWF_FFT * NWF_IQW / SPIBUF_W + 1
DEFp NWF_SAMPS NWF_FFT / NWF_NXFER + 1
DEFp NWF_SAMPS_RPT 50
DEFp NWF_SAMPS_LOOP NWF_SAMPS / NWF_SAMPS_RPT
DEFp NWF_SAMPS_LOOP2 NWF_SAMPS_LOOP * NWF_SAMPS_RPT
DEFp NWF_SAMPS_REM NWF_SAMPS - NWF_SAMPS_LOOP2
DEFh USE_WF_1CIC 1
DEFh USE_WF_PRUNE 1
DEFh USE_WF_CIC24 1
DEFh USE_WF_MEM24 0
DEFh USE_WF_NEW 0
DEFp WF1_STAGES 5
DEFp WF2_STAGES 5
#if USE_WF_CIC24
DEFp WF1_BITS 24
DEFp WF2_BITS 24
#else
DEFp WF1_BITS 16
DEFp WF2_BITS 16
#endif
#if USE_WF_MEM24
DEFp WFO_BITS 24
#else
DEFp WFO_BITS 16
#endif
#if USE_WF_1CIC
DEFp WF_1CIC_MAXD 8192
DEFp WF_2CIC_MAXD 0 // to keep Vivado happy
#else
DEFp WF_2CIC_MAXD 128 // 8192 = 128 * 64
DEFp WF_2CIC_POW2 7
DEFp WF_1CIC_MAXD 0 // to keep Vivado happy
#endif
// gps
DEFp MAX_GPS_CHAN 12 // limited by ipcore_bram_gps_4k_12b
DEFp E1B_MODE 0x800
//DEFp GPS_INTEG_BITS 16 // width of EPL I/Q integrators
//DEFp GPS_INTEG_BITS 18 // width of EPL I/Q integrators
DEFp GPS_INTEG_BITS 20 // width of EPL I/Q integrators
#if GPS_INTEG_BITS 16
DEFp FPGA_ID2 4'd8
#else
DEFp FPGA_ID2 4'd0
#endif
DEFp GPS_REPL_BITS 18 // width of clock replicas
DEFp MAX_NAV_BITS 128
DEFp GPS_SAMPS 256
DEFp GPS_IQ_SAMPS 255 // not 256 due to SPI buffer edge bug
DEFp GPS_IQ_SAMPS_W GPS_IQ_SAMPS * 4 // *2 = IQ, *2 = 2 words each
DEFp L1_CODEBITS 10
DEFp L1_CODELEN 1023
DEFp E1B_CODEBITS 12
DEFp E1B_CODELEN 4092
DEFp E1B_CODE_XFER 1 << E1B_CODEBITS / SPIBUF_W
DEFp E1B_CODE_LOOP E1B_CODELEN / E1B_CODE_XFER
// misc
DEFp FPGA_ID FPGA_ID1 + FPGA_ID2
; ============================================================================
// NB: [10:0] (0x400 max) because [11] is used for further decoding
// read reg (rdReg & op[10:0], one hot)
// these 3 must be in these bit positions: see gps.v
DEFb GET_CHAN_IQ 0x001
DEFb GET_SRQ 0x002
DEFb GET_SNAPSHOT 0x004
DEFb HOST_RX 0x008
DEFb GET_RX_SRQ 0x010
DEFb GET_CPU_CTR0 0x020
DEFb GET_CPU_CTR1 0x040
DEFb GET_CPU_CTR2 0x080
DEFb GET_CPU_CTR3 0x100
DEFb GET_STATUS 0x200
// read reg (rdReg2 & op[10:0], one hot)
// write reg (wrReg & op[10:0], one hot)
DEFb HOST_TX 0x001
DEFb SET_MASK 0x002
DEFb SET_CHAN 0x004
DEFb SET_CG_NCO 0x008
DEFb SET_LO_NCO 0x010
DEFb SET_SAT 0x020
DEFb SET_E1B_CODE 0x040
DEFb SET_PAUSE 0x080
// write reg (wrReg2 & op[10:0], one hot)
DEFb SET_CTRL 0x001
DEFb SET_RX_CHAN 0x002
DEFb SET_RX_FREQ 0x004
DEFb SET_RX_FREQ_L 0x008
DEFb SET_RX_NSAMPS 0x010
DEFb SET_GEN 0x020
DEFb SET_GEN_ATTN 0x040
DEFb SET_WF_FREQ 0x080
DEFb SET_WF_DECIM 0x100
DEFb SET_WF_CHAN 0x200
DEFb WF_SAMPLER_RST 0x400
// events (wrEvt & op[10:0], one hot)
DEFb HOST_RST 0x001
DEFb HOST_RDY 0x002
DEFb GPS_SAMPLER_RST 0x004
DEFb GET_GPS_SAMPLES 0x008 // data transfer goes directly to SPI BRAM
DEFb GET_MEMORY 0x010 // causes ecpu data memory (with TOS pointer++) to SPI BRAM transfer
DEFb GET_LOG 0x020 // data transfer goes directly to SPI BRAM
DEFb PUT_LOG 0x040
DEFb LOG_RST 0x080
// events (wrEvt2 & op[10:0], one hot)
DEFb GET_RX_SAMP 0x001 // data transfer goes directly to SPI BRAM
DEFb RX_BUFFER_RST 0x002
DEFb RX_GET_BUF_CTR 0x004 // data transfer goes directly to SPI BRAM
DEFb SET_WF_CONTIN 0x008
DEFb GET_WF_SAMP_I 0x010 // data transfer goes directly to SPI BRAM
DEFb GET_WF_SAMP_Q 0x020 // "
DEFb CLR_RX_OVFL 0x040
DEFb FREEZE_TOS 0x080
DEFb CPU_CTR_CLR 0x100
DEFb CPU_CTR_ENA 0x200
DEFb CPU_CTR_DIS 0x400
// WF_SAMPLER_RST
DEFb WF_SAMP_RD_RST 0x1
DEFb WF_SAMP_WR_RST 0x2
DEFb WF_SAMP_CONTIN 0x4
DEFb WF_SAMP_SYNC 0x8
// GET_STATUS
DEFp STAT_FPGA_ID 0x000f
DEFp STAT_USER 0x00f0
DEFb STAT_DNA_DATA 0x0010
DEFp STAT_FPGA_VER 0x0f00
DEFp STAT_FW_ID 0x7000
DEFb STAT_OVFL 0x8000
// SET_CTRL
DEFb CTRL_OSC_EN 0x0100
DEFb CTRL_EEPROM_WP 0x0200
DEFh HEARTBEAT_IND CTRL_EEPROM_WP
DEFb CTRL_USE_GEN 0x0400
DEFb CTRL_TEST_MODE 0x0800 // unused currently
DEFb CTRL_UNUSED_OUT CTRL_TEST_MODE
DEFb CTRL_INTERRUPT 0x1000
DEFb CTRL_DNA_READ 0x2000
DEFb CTRL_DNA_SHIFT 0x4000
DEFb CTRL_DNA_CLK 0x8000