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Add initial support for riscv64 (#102)
* crash-context: add riscv64 support getcontext ported from Breakpad and portable context structs from libc crate. * sadness-generator: add riscv64 support * crash-handler: add riscv64 support
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6 files changed

+173
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lines changed

‎crash-context/src/linux.rs‎

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Original file line numberDiff line numberDiff line change
@@ -256,6 +256,61 @@ cfg_if::cfg_if! {
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pub arm_cpsr: u32,
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pub fault_address: u32,
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}
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} else if #[cfg(target_arch = "riscv64")] {
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#[repr(C)]
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#[derive(Clone)]
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#[doc(hidden)]
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pub struct ucontext_t {
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pub __uc_flags: u64,
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pub uc_link: *mut ucontext_t,
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pub uc_stack: stack_t,
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pub uc_sigmask: sigset_t,
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pub uc_mcontext: mcontext_t,
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}
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#[repr(C, align(16))]
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#[derive(Clone)]
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#[doc(hidden)]
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pub struct mcontext_t {
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pub __gregs: [u64; 32],
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pub __fpregs: __riscv_mc_fp_state,
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}
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#[repr(C)]
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#[derive(Clone, Copy)]
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#[doc(hidden)]
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pub union __riscv_mc_fp_state {
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pub __f: __riscv_mc_f_ext_state,
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pub __d: __riscv_mc_d_ext_state,
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pub __q: __riscv_mc_q_ext_state,
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}
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#[repr(C)]
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#[derive(Clone, Copy)]
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#[doc(hidden)]
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pub struct __riscv_mc_f_ext_state {
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pub __f: [u32; 32],
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pub __fcsr: u32,
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}
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#[repr(C)]
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#[derive(Clone, Copy)]
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#[doc(hidden)]
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pub struct __riscv_mc_d_ext_state {
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pub __f: [u64; 32],
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pub __fcsr: u32,
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}
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#[repr(C, align(16))]
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#[derive(Clone, Copy)]
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#[doc(hidden)]
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pub struct __riscv_mc_q_ext_state {
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pub __f: [u64; 64],
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pub __fcsr: u32,
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pub __reserved: [u32; 3],
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}
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pub type fpregset_t = __riscv_mc_fp_state;
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}
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}
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‎crash-context/src/linux/getcontext.rs‎

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Original file line numberDiff line numberDiff line change
@@ -20,5 +20,7 @@ cfg_if::cfg_if! {
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mod aarch64;
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} else if #[cfg(target_arch = "arm")] {
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mod arm;
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} else if #[cfg(target_arch = "riscv64")] {
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mod riscv64;
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}
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}

‎crash-context/src/linux/getcontext/riscv64.rs‎

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,96 @@
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// UCONTEXT_SIGMASK_OFFSET = 40
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// MCONTEXT_GREGS_OFFSET = 168
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// MCONTEXT_GREGS_SIZE = 8
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std::arch::global_asm! {
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".text",
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".globl crash_context_getcontext",
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".hidden crash_context_getcontext",
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".type crash_context_getcontext, @function",
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".align 0",
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".cfi_startproc",
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"crash_context_getcontext:",
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// Save general registers
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"sd ra, 0xa8(a0)",
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"sd ra, 0xb0(a0)",
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"sd sp, 0xb8(a0)",
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"sd gp, 0xc0(a0)",
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"sd tp, 0xc8(a0)",
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"sd t0, 0xd0(a0)",
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"sd t1, 0xd8(a0)",
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"sd t2, 0xe0(a0)",
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"sd s0, 0xe8(a0)",
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"sd s1, 0xf0(a0)",
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"sd a0, 0xf8(a0)",
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"sd a1, 0x100(a0)",
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"sd a2, 0x108(a0)",
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"sd a3, 0x110(a0)",
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"sd a4, 0x118(a0)",
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"sd a5, 0x120(a0)",
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"sd a6, 0x128(a0)",
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"sd a7, 0x130(a0)",
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"sd s2, 0x138(a0)",
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"sd s3, 0x140(a0)",
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"sd s4, 0x148(a0)",
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"sd s5, 0x150(a0)",
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"sd s6, 0x158(a0)",
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"sd s7, 0x160(a0)",
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"sd s8, 0x168(a0)",
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"sd s9, 0x170(a0)",
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"sd s10, 0x178(a0)",
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"sd s11, 0x180(a0)",
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"sd t3, 0x188(a0)",
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"sd t4, 0x190(a0)",
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"sd t5, 0x198(a0)",
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"sd t6 , 0x1a0(a0)",
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// Save floating point registers
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"frsr a1", // Save CSR
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"fsd ft0, 0x1a8(a0)",
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"fsd ft1, 0x1b0(a0)",
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"fsd ft2, 0x1b8(a0)",
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"fsd ft3, 0x1c0(a0)",
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"fsd ft4, 0x1c8(a0)",
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"fsd ft5, 0x1d0(a0)",
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"fsd ft6, 0x1d8(a0)",
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"fsd ft7, 0x1e0(a0)",
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"fsd fs0, 0x1e8(a0)",
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"fsd fs1, 0x1f0(a0)",
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"fsd fa0, 0x1f8(a0)",
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"fsd fa1, 0x200(a0)",
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"fsd fa2, 0x208(a0)",
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"fsd fa3, 0x210(a0)",
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"fsd fa4, 0x218(a0)",
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"fsd fa5, 0x220(a0)",
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"fsd fa6, 0x228(a0)",
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"fsd fa7, 0x230(a0)",
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"fsd fs2, 0x238(a0)",
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"fsd fs3, 0x240(a0)",
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"fsd fs4, 0x248(a0)",
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"fsd fs5, 0x250(a0)",
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"fsd fs6, 0x258(a0)",
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"fsd fs7, 0x260(a0)",
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"fsd fs8, 0x268(a0)",
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"fsd fs9, 0x270(a0)",
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"fsd fs10, 0x278(a0)",
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"fsd fs11, 0x280(a0)",
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"fsd ft8, 0x288(a0)",
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"fsd ft9, 0x290(a0)",
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"fsd ft10, 0x298(a0)",
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"fsd ft11, 0x2a0(a0)",
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"sw a1, 0x2a8(a0)",
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"mv a1, zero",
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"add a2, a0, 40", // UCONTEXT_SIGMASK_OFFSET
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"li a3, 8", // _NSIG8
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"mv a0, zero",
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"li a7, 135", // __NR_rt_sigprocmask
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"ecall",
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"mv a0, zero",
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"ret",
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".cfi_endproc",
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".size crash_context_getcontext, . - crash_context_getcontext",
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}

‎crash-handler/src/linux/jmp.rs‎

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Original file line numberDiff line numberDiff line change
@@ -37,6 +37,16 @@ cfg_if::cfg_if! {
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#[doc(hidden)]
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#[allow(non_camel_case_types)]
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pub struct __jmp_buf([u64; 22]);
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} else if #[cfg(target_arch = "riscv64")] {
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#[repr(C)]
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#[doc(hidden)]
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#[allow(non_camel_case_types)]
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pub struct __jmp_buf {
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__pc: u64,
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__regs: [u64; 12],
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__sp: u64,
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__fpregs: [f64; 12],
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}
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}
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}
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‎crash-handler/src/linux/state.rs‎

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@@ -457,6 +457,8 @@ impl HandlerInner {
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if (*fp_ptr).head.magic == crash_context::FPSIMD_MAGIC {
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ptr::copy_nonoverlapping(fp_ptr, &mut cc.float_state, 1);
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}
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} else if #[cfg(target_arch = "riscv64")] {
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cc.float_state = uc_ptr.uc_mcontext.__fpregs;
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} else if #[cfg(not(target_arch = "arm"))] {
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if !uc_ptr.uc_mcontext.fpregs.is_null() {
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ptr::copy_nonoverlapping(uc_ptr.uc_mcontext.fpregs, ((&mut cc.float_state) as *mut crash_context::fpregset_t).cast(), 1);

‎sadness-generator/src/lib.rs‎

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Original file line numberDiff line numberDiff line change
@@ -159,10 +159,11 @@ pub unsafe fn raise_floating_point_exception() -> ! {
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);
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divisor
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}
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#[cfg(any(target_arch = "arm", target_arch = "aarch64"))]
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#[cfg(any(target_arch = "arm", target_arch = "aarch64", target_arch = "riscv64"))]
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{
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// Unfortunately ARM by default will not raise SIGFPE on divide
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// by 0 and just return 0, so we just explicitly raise here for now
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// Unfortunately ARM and RISC-V by default will not raise SIGFPE on
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// divide by 0 and just return 0, so we just explicitly raise here
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// for now
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libc::raise(libc::SIGFPE);
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0
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}
@@ -184,6 +185,8 @@ pub unsafe fn raise_illegal_instruction() -> ! {
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asm!("ud2");
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#[cfg(any(target_arch = "arm", target_arch = "aarch64"))]
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asm!("udf #0");
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#[cfg(target_arch = "riscv64")]
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asm!(".word 0x00000000");
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}
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189192
std::process::abort()
@@ -247,6 +250,8 @@ pub unsafe fn raise_trap() -> ! {
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asm!(".inst 0xe7f001f0");
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#[cfg(target_arch = "aarch64")]
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asm!(".inst 0xd4200000");
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#[cfg(target_arch = "riscv64")]
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asm!("ebreak");
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}
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std::process::abort()

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