Merge branch 'gpc_cache_amo' into gpc_cache_wb

Author: miaochenlu

.github/workflows/cache_test.yml

@@ -0,0 +1,43 @@
+name: GPC DCache Test
+
+on:
+  push:
+    tags: ['*']
+    branches: ['gpc_cache*']
+  pull_request:
+  workflow_dispatch:
+
+jobs:
+  ci:
+    name: ci
+    runs-on: ubuntu-22.04
+    steps:
+      - name: Checkout
+        uses: actions/checkout@v4
+      - name: Cleanup
+        run: sed -i "s/grapecoveDCache[chisel3]/test/g" build.sc
+      - name: Cache Scala
+        uses: coursier/cache-action@v6
+      - name: Setup Scala
+        uses: coursier/setup-action@v1
+        with:
+          jvm: adopt:11
+          apps: sbt mill
+      - name: Setup Dependencies
+        run: |
+          sudo apt-get install ccache
+      - name: Install Verilator
+        run: |
+          sudo apt-get install verilator
+      - name: Init Submodule
+        run: |
+          make init 
+      - name: Cache Test
+        run: |
+          make test_dcache
+          make test_amo
+          make test_lrsc
+          make test_mmio
+          make test_forward
+          make test_bypass
+

.github/workflows/template-cleanup.yml

@@ -4,6 +4,9 @@ test_dcache:
 test_amo:
 	mill -i $(PRJ)[$(CHISEL_VERSION)].test.testOnly $(PRJ).DCacheAMOTest
 
+test_lrsc:
+	mill -i $(PRJ)[$(CHISEL_VERSION)].test.testOnly $(PRJ).DCacheLRSCTest
+
 test_mmio:
 	mill -i $(PRJ)[$(CHISEL_VERSION)].test.testOnly $(PRJ).DCacheMMIOTest
 

.github/workflows/test.yml

@@ -429,7 +429,7 @@ class GPCDCacheImp(outer: BaseDCache) extends BaseDCacheImp(outer) {
   // mshr get store data in s2
   val s2_upgradePermMiss = RegNext(s1_upgradePermMiss)
   val s2_mshrStoreData   = Mux(isAMO(s2_req.cmd), s2_data, Mux(s2_upgradePermMiss, s2_mergeStoreData, s2_req.wdata))
-  val s2_mshrStoreMaskInBytes = Mux(s2_upgradePermMiss, Fill(dataBytes, 1.U), s2_req.wmask)
+  val s2_mshrStoreMaskInBytes = Mux(s2_upgradePermMiss && !isAMO(s2_req.cmd), Fill(dataBytes, 1.U), s2_req.wmask)
 
   mshrs.io.req.valid := s1_mshrAlloc
 
@@ -572,6 +572,7 @@ class GPCDCacheImp(outer: BaseDCache) extends BaseDCacheImp(outer) {
 
   // return resp
   io.nextCycleWb := mshrs.io.nextCycleWb
+  io.nextSource  := mshrs.io.nextSourceId
   io.resp.valid  := s1_cacheResp.valid | mshrsResp.valid
   io.resp.bits   := Mux(s1_cacheResp.valid, s1_cacheResp.bits, mshrsResp.bits)
 

Makefile.test

@@ -41,6 +41,7 @@ class DataExchangeIO extends Bundle {
   val req         = Flipped(Decoupled(new DataExchangeReq))
   val resp        = Valid(new DataExchangeResp)
   val nextCycleWb = Bool() // next cycle occupy wb stage
+  val nextSource  = UInt(MasterSource.width.W)
   val fenceRdy    = Bool()
   val s1_kill     = Input(Bool())
 }

src/main/scala/grapecoveDcache/DCache.scala

@@ -516,8 +516,10 @@ class MSHRFile extends Module() {
     maskArray(replayReg.io.replayIdx) := 0.U
     dataArray(replayReg.io.replayIdx) := 0.U
     dataArrayWriteEna                 := false.B
+    amoDataArrayWriteEna              := false.B
   }.otherwise {
-    dataArrayWriteEna := false.B
+    dataArrayWriteEna    := false.B
+    amoDataArrayWriteEna := false.B
   }
 
   // receive miss addr data at s2

src/main/scala/grapecoveDcache/DataExchangeIO.scala

@@ -36,7 +36,7 @@ class MSHREntryIO extends Bundle() {
   // probe permission
   val probeValid         = Input(Bool())
   val probeLineAddrMatch = Output(Bool())
-  val probePermission    = Input(UInt(TLPermissions.bdWidth.W))
+  val probePermission    = Input(UInt(TLPermissions.cWidth.W))
   val probeState         = Output(UInt(ProbeMSHRState.width.W))
 }
 
@@ -127,7 +127,7 @@ class RefillMSHRFile extends Bundle() {
 
 class ProbeMSHRFile extends Bundle() {
   val valid           = Input(Bool())
-  val probePermission = Input(UInt(TLPermissions.bdWidth.W))
+  val probePermission = Input(UInt(TLPermissions.cWidth.W))
   val lineAddr        = Input(UInt(lineAddrWidth.W))
 
   val pass     = Output(Bool())

src/main/scala/grapecoveDcache/MSHR.scala

@@ -92,9 +92,8 @@ class ProbeQueue(
   io.wbReq.bits.data      := DontCare // FIXME
   io.wbReq.bits.hasData   := false.B
 
-  io.memProbe.ready := (state === s_invalid) &&
-    (!io.lrscAddr.valid ||
-      io.lrscAddr.bits =/= getLineAddr(io.memProbe.bits.address))
-
-  assert(io.memProbe.bits.opcode === TLMessages.Probe || ~io.memProbe.valid)
+  io.memProbe.ready :=
+    (state === s_invalid) &&
+      (!io.lrscAddr.valid ||
+        io.lrscAddr.bits =/= getLineAddr(io.memProbe.bits.address))
 }