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Copy pathprincipals-demo-circuit.falsted-circuitjs.txt
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principals-demo-circuit.falsted-circuitjs.txt
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$ 0 0.0000049999999999999996 10.20027730826997 50 5 43
r 80 144 192 144 0 150
s 608 176 672 176 0 1 false
L 704 176 800 176 0 1 false 5 0
x 378 141 492 144 4 24 Socket\sPin
x -53 149 5 152 4 24 gpioL
x -109 47 36 50 4 24 GPIO\spin\spair
b 558 5 839 264 0
w 608 176 528 176 0
w 240 176 336 176 0
b 247 3 528 248 0
368 0 112 -80 112 0 5
403 -160 80 -112 192 0 10_64_0_4098_1.25_0.1_0_2_10_3
x 265 339 487 342 4 12 Simulate\snoise/random\svalues\son\stest\spin.
x 594 42 743 45 4 24 Test\schip's\spin
L 0 176 -80 176 0 0 false 5 0
x 596 73 730 76 4 12 May\sbe\sany\sof;\sVcc,\sGnd,
x 265 371 517 374 4 12 or\schip's\soutput\spin\sis\sfloating\sin\sa\s"high-Z"\sstate
b -112 80 76 202 0
s 416 176 448 176 0 1 false
x 397 209 465 212 4 12 chip\sinserted
x 399 222 465 225 4 12 when\sclosed
w 400 176 416 176 0
w 448 176 496 176 0
x 266 355 491 358 4 12 This\sbecomes\srelevant\swhen\sZIF\sis\sempty\s
b 394 153 474 190 0
w 400 176 336 176 0
x 267 44 497 47 4 24 ZIF\ssocket\sand\straces
S 80 144 32 144 0 1 false 0 2
w 32 128 0 112 0
w 32 160 0 176 0
w 32 304 0 320 0
w 32 272 0 256 0
S 80 288 32 288 0 1 false 0 2
b -112 224 76 346 0
L 0 320 -80 320 0 0 false 5 0
368 0 256 -80 256 0 5
x -53 293 9 296 4 24 gpioH
r 80 288 192 288 0 10000
w 192 176 192 144 0
w 192 176 192 288 0
w 240 176 192 176 0
b -179 5 105 383 0
x 31 119 52 122 4 10 input
x 28 176 55 179 4 10 output
x 30 318 57 321 4 10 output
x 31 262 52 265 4 10 input
w 336 208 336 176 0
r 368 304 432 304 0 1000000000
R 448 304 480 304 0 6 40 5 0 0 0.5
w 448 304 432 304 0
w 368 304 336 304 0
w 336 304 336 240 0
x 274 76 447 79 4 12 Has\sstray\scapacitance\sand\snoise
x 274 92 449 95 4 12 that's\srelevat\swhen\snot\spopulated
w 336 240 336 208 0
b 247 271 532 395 0
x 558 351 726 354 4 14 leave\sthe\sZIF\ssocket\sempty
x 559 369 793 372 4 14 and\srun\sthe\s"decay()"\stest\sin\sthe\scode\s
x 559 388 786 391 4 14 to\ssee\sthe\seffect\sof\sstray\scapacitance
w 528 176 496 176 0
x -182 411 -39 414 4 12 Four\sGPIO\spin\spair\smodes:
x -183 450 414 453 4 12 -\sDriving\san\sinput:\sSet\sgpioL\sas\soutput,\sgpioH\sas\sinput\s(no-op)\s-\sSet\sgpioL\shigh\sor\slow\sto\sdrive\sthe\stest\schip's\sinput
x -183 433 487 436 4 12 -\sDriving\sVcc\sand\sGnd:\sSet\sgpioL\sas\soutput,\sgpioH\sas\sinput\s(no-op)\s-\sgpioL\sis\sset\shigh\sot\slow\sto\sprovide\s5v\sor\sGnd\sas\sapproriate
x -185 467 773 470 4 12 -\sTesting\san\soutput:\sSet\sgpioL\sas\sinput,\sgpioH\sas\soutput\s-\sgpioH\sis\sacts\sas\sa\spull\sup\sand\sa\spull\sdown\sduring\sthe\stest,\sgpioL\sreads\sthe\sresulting\sstate\sof\sthe\stest\schip's\spin\sduring\sthe\stest
x 595 88 761 91 4 12 a\slogic\sinput,\sa\shigh\sor\slow\slogic
x 597 102 695 105 4 12 a\shigh-z\soutput\spin
x 741 153 830 156 4 12 output\slogic\slevel
x 589 194 770 197 4 12 Open\s\q\sinput,\shi-z\soutput\so\srpower
x 557 335 759 338 4 14 Suggestion:\sIn\sthe\sreal\shardware
x -185 484 848 487 4 12 -\sSample\smode:\sSet\sgpioL\sas\sinput,\sgpioH\sas\sinput\s(no-op)\s-\ssample\sthe\slogic\sstate\sbut\sexpect\sit\sto\sproduce\sunpredicable\svalues\swhen\sthe\ssocket\sis\sempty\s(see\sthe\sdecay()\stest\sdescribed\sin\sgithub)
x 589 210 688 213 4 12 Closed\s\q\slogic\sout\s
w 672 176 704 176 0
o 9 64 3 4098 5 0.1 0 1