invalid lowering of control flow

[simeonschaub]

The following llvm IR was reduced from a more complex example (Let me know if it doesn't make sense anymore, it might be reduced too much now):

target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1"
target triple = "spirv64-unknown-unknown"

define spir_kernel void @_Z24partial_mapreduce_device9reductionI6islessE16CartesianIndicesILi1E5TupleI5OneToI5Int64EEE11BroadcastedI12CLArrayStyleILi1E19UnifiedDeviceMemoryES7_5tupleS3_I13CLDeviceArrayI7Float32Li1ELi1EE9EachIndexIS5_Li1ES6_EEE() {
conversion:
  br i1 false, label %conversion.L114.us_crit_edge, label %L114

conversion.L114.us_crit_edge:                     ; preds = %conversion
  br label %L114.us

L114.us:                                          ; preds = %conversion.L114.us_crit_edge, %L114.us
  br i1 false, label %L114.us, label %L36.us.postloop

L114:                                             ; preds = %L114, %conversion
  br label %L114

L148:                                             ; preds = %L36.us.postloop
  ret void

L36.us.postloop:                                  ; preds = %L36.us.postloop, %L114.us
  br i1 false, label %L148, label %L36.us.postloop, !llvm.loop !0

; uselistorder directives
  uselistorder label %L114.us, { 1, 0 }
}

!0 = distinct !{!0, !1, !2, !3, !4}
!1 = !{!"llvm.loop.unroll.disable"}
!2 = !{!"llvm.loop.vectorize.enable", i1 false}
!3 = !{!"llvm.loop.licm_versioning.disable"}
!4 = !{!"llvm.loop.distribute.enable", i1 false}

It produces the following SPIR-V:

; SPIR-V
; Version: 1.0
; Generator: Khronos LLVM/SPIR-V Translator; 14
; Bound: 18
; Schema: 0
               OpCapability Addresses
               OpCapability Linkage
               OpCapability Kernel
          %1 = OpExtInstImport "OpenCL.std"
               OpMemoryModel Physical64 OpenCL
               OpEntryPoint Kernel %15 "_Z24partial_mapreduce_device9reductionI6islessE16CartesianIndicesILi1E5TupleI5OneToI5Int64EEE11BroadcastedI12CLArrayStyleILi1E19UnifiedDeviceMemoryES7_5tupleS3_I13CLDeviceArrayI7Float32Li1ELi1EE9EachIndexIS5_Li1ES6_EEE"
               OpSource Unknown 0
               OpName %_Z24partial_mapreduce_device9reductionI6islessE16CartesianIndicesILi1E5TupleI5OneToI5Int64EEE11BroadcastedI12CLArrayStyleILi1E19UnifiedDeviceMemoryES7_5tupleS3_I13CLDeviceArrayI7Float32Li1ELi1EE9EachIndexIS5_Li1ES6_EEE "_Z24partial_mapreduce_device9reductionI6islessE16CartesianIndicesILi1E5TupleI5OneToI5Int64EEE11BroadcastedI12CLArrayStyleILi1E19UnifiedDeviceMemoryES7_5tupleS3_I13CLDeviceArrayI7Float32Li1ELi1EE9EachIndexIS5_Li1ES6_EEE"
               OpName %conversion "conversion"
               OpName %L114_preheader "L114.preheader"
               OpName %conversion_L114_us_crit_edge "conversion.L114.us_crit_edge"
               OpName %L114_us "L114.us"
               OpName %L36_us_postloop_preheader "L36.us.postloop.preheader"
               OpName %L114 "L114"
               OpName %L36_us_postloop "L36.us.postloop"
               OpName %L148 "L148"
               OpDecorate %_Z24partial_mapreduce_device9reductionI6islessE16CartesianIndicesILi1E5TupleI5OneToI5Int64EEE11BroadcastedI12CLArrayStyleILi1E19UnifiedDeviceMemoryES7_5tupleS3_I13CLDeviceArrayI7Float32Li1ELi1EE9EachIndexIS5_Li1ES6_EEE LinkageAttributes "_Z24partial_mapreduce_device9reductionI6islessE16CartesianIndicesILi1E5TupleI5OneToI5Int64EEE11BroadcastedI12CLArrayStyleILi1E19UnifiedDeviceMemoryES7_5tupleS3_I13CLDeviceArrayI7Float32Li1ELi1EE9EachIndexIS5_Li1ES6_EEE" Export
       %void = OpTypeVoid
          %3 = OpTypeFunction %void
       %bool = OpTypeBool
      %false = OpConstantFalse %bool
%_Z24partial_mapreduce_device9reductionI6islessE16CartesianIndicesILi1E5TupleI5OneToI5Int64EEE11BroadcastedI12CLArrayStyleILi1E19UnifiedDeviceMemoryES7_5tupleS3_I13CLDeviceArrayI7Float32Li1ELi1EE9EachIndexIS5_Li1ES6_EEE = OpFunction %void None %3
 %conversion = OpLabel
               OpBranchConditional %false %conversion_L114_us_crit_edge %L114_preheader
%L114_preheader = OpLabel
               OpBranch %L114
%conversion_L114_us_crit_edge = OpLabel
               OpBranch %L114_us
    %L114_us = OpLabel
               OpBranchConditional %false %L114_us %L36_us_postloop_preheader
%L36_us_postloop_preheader = OpLabel
               OpBranch %L36_us_postloop
       %L114 = OpLabel
               OpBranch %L114
%L36_us_postloop = OpLabel
               OpLoopMerge %L148 %L36_us_postloop DontUnroll
               OpBranchConditional %false %L148 %L36_us_postloop
       %L148 = OpLabel
               OpLoopMerge %L36_us_postloop %L36_us_postloop DontUnroll
               OpLoopMerge %L36_us_postloop %L36_us_postloop DontUnroll
               OpReturn
               OpFunctionEnd
         %15 = OpFunction %void None %3
         %16 = OpLabel
         %17 = OpFunctionCall %void %_Z24partial_mapreduce_device9reductionI6islessE16CartesianIndicesILi1E5TupleI5OneToI5Int64EEE11BroadcastedI12CLArrayStyleILi1E19UnifiedDeviceMemoryES7_5tupleS3_I13CLDeviceArrayI7Float32Li1ELi1EE9EachIndexIS5_Li1ES6_EEE
               OpReturn
               OpFunctionEnd

which then fails validation with

error: line 22: Block '11[%L36_us_postloop]' is already a merge block for another header
  %_Z24partial_mapreduce_device9reductionI6islessE16CartesianIndicesILi1E5TupleI5OneToI5Int64EEE11BroadcastedI12CLArrayStyleILi1E19UnifiedDeviceMemoryES7_5tupleS3_I13CLDeviceArrayI7Float32Li1ELi1EE9EachIndexIS5_Li1ES6_EEE = OpFunction %void None %3

[MrSidims]

Thanks for the report! There are 2 dedicated PRs: #3277 , #3280 . I remember there were some test failures, but now they are fixed. Will take a look.