diff --git a/logs/Grande-Risco-5_1738762069.2408826.json b/logs/Grande-Risco-5_1738762069.2408826.json new file mode 100644 index 0000000..af39d64 --- /dev/null +++ b/logs/Grande-Risco-5_1738762069.2408826.json @@ -0,0 +1,27 @@ +{ + "name": "Grande-Risco-5", + "folder": "Grande-Risco-5", + "sim_files": [ + "tests/alu_test.v", + "tests/bmu_test.v", + "tests/clk_divider.v", + "tests/core_test.v", + "tests/d_cache_test.v", + "tests/fifo_test.v", + "tests/gpio_test.v", + "tests/i_cache_test.v", + "tests/immediate_generator_test.v", + "tests/mdu_test.v", + "tests/mux_test.v", + "tests/pc_test.v", + "tests/registers_test.v", + "tests/reset_test.v", + "tests/soc_test.v" + ], + "files": [], + "include_dirs": [], + "repository": "https://github.com/JN513/Grande-Risco-5", + "top_module": "", + "extra_flags": [], + "language_version": "2005" +} \ No newline at end of file diff --git a/logs/Grande-Risco-5_1738762175.2768786.json b/logs/Grande-Risco-5_1738762175.2768786.json new file mode 100644 index 0000000..af39d64 --- /dev/null +++ b/logs/Grande-Risco-5_1738762175.2768786.json @@ -0,0 +1,27 @@ +{ + "name": "Grande-Risco-5", + "folder": "Grande-Risco-5", + "sim_files": [ + "tests/alu_test.v", + "tests/bmu_test.v", + "tests/clk_divider.v", + "tests/core_test.v", + "tests/d_cache_test.v", + "tests/fifo_test.v", + "tests/gpio_test.v", + "tests/i_cache_test.v", + "tests/immediate_generator_test.v", + "tests/mdu_test.v", + "tests/mux_test.v", + "tests/pc_test.v", + "tests/registers_test.v", + "tests/reset_test.v", + "tests/soc_test.v" + ], + "files": [], + "include_dirs": [], + "repository": "https://github.com/JN513/Grande-Risco-5", + "top_module": "", + "extra_flags": [], + "language_version": "2005" +} \ No newline at end of file diff --git a/logs/Grande-Risco-5_1738762226.6920555.json b/logs/Grande-Risco-5_1738762226.6920555.json new file mode 100644 index 0000000..af39d64 --- /dev/null +++ b/logs/Grande-Risco-5_1738762226.6920555.json @@ -0,0 +1,27 @@ +{ + "name": "Grande-Risco-5", + "folder": "Grande-Risco-5", + "sim_files": [ + "tests/alu_test.v", + "tests/bmu_test.v", + "tests/clk_divider.v", + "tests/core_test.v", + "tests/d_cache_test.v", + "tests/fifo_test.v", + "tests/gpio_test.v", + "tests/i_cache_test.v", + "tests/immediate_generator_test.v", + "tests/mdu_test.v", + "tests/mux_test.v", + "tests/pc_test.v", + "tests/registers_test.v", + "tests/reset_test.v", + "tests/soc_test.v" + ], + "files": [], + "include_dirs": [], + "repository": "https://github.com/JN513/Grande-Risco-5", + "top_module": "", + "extra_flags": [], + "language_version": "2005" +} \ No newline at end of file diff --git a/logs/Grande-Risco-5_1738762426.004829.json b/logs/Grande-Risco-5_1738762426.004829.json new file mode 100644 index 0000000..af39d64 --- /dev/null +++ b/logs/Grande-Risco-5_1738762426.004829.json @@ -0,0 +1,27 @@ +{ + "name": "Grande-Risco-5", + "folder": "Grande-Risco-5", + "sim_files": [ + "tests/alu_test.v", + "tests/bmu_test.v", + "tests/clk_divider.v", + "tests/core_test.v", + "tests/d_cache_test.v", + "tests/fifo_test.v", + "tests/gpio_test.v", + "tests/i_cache_test.v", + "tests/immediate_generator_test.v", + "tests/mdu_test.v", + "tests/mux_test.v", + "tests/pc_test.v", + "tests/registers_test.v", + "tests/reset_test.v", + "tests/soc_test.v" + ], + "files": [], + "include_dirs": [], + "repository": "https://github.com/JN513/Grande-Risco-5", + "top_module": "", + "extra_flags": [], + "language_version": "2005" +} \ No newline at end of file diff --git a/logs/Grande-Risco-5_1738762740.3252385.json b/logs/Grande-Risco-5_1738762740.3252385.json new file mode 100644 index 0000000..af39d64 --- /dev/null +++ b/logs/Grande-Risco-5_1738762740.3252385.json @@ -0,0 +1,27 @@ +{ + "name": "Grande-Risco-5", + "folder": "Grande-Risco-5", + "sim_files": [ + "tests/alu_test.v", + "tests/bmu_test.v", + "tests/clk_divider.v", + "tests/core_test.v", + "tests/d_cache_test.v", + "tests/fifo_test.v", + "tests/gpio_test.v", + "tests/i_cache_test.v", + "tests/immediate_generator_test.v", + "tests/mdu_test.v", + "tests/mux_test.v", + "tests/pc_test.v", + "tests/registers_test.v", + "tests/reset_test.v", + "tests/soc_test.v" + ], + "files": [], + "include_dirs": [], + "repository": "https://github.com/JN513/Grande-Risco-5", + "top_module": "", + "extra_flags": [], + "language_version": "2005" +} \ No newline at end of file diff --git a/logs/Grande-Risco-5_1738762865.1944978.json b/logs/Grande-Risco-5_1738762865.1944978.json new file mode 100644 index 0000000..1dadca9 --- /dev/null +++ b/logs/Grande-Risco-5_1738762865.1944978.json @@ -0,0 +1,42 @@ +{ + "name": "Grande-Risco-5", + "folder": "Grande-Risco-5", + "sim_files": [ + "tests/alu_test.v", + "tests/bmu_test.v", + "tests/clk_divider.v", + "tests/core_test.v", + "tests/d_cache_test.v", + "tests/fifo_test.v", + "tests/gpio_test.v", + "tests/i_cache_test.v", + "tests/immediate_generator_test.v", + "tests/mdu_test.v", + "tests/mux_test.v", + "tests/pc_test.v", + "tests/registers_test.v", + "tests/reset_test.v", + "tests/soc_test.v" + ], + "files": [ + "src/core/Grande_Risco5.v", + "src/core/Core.v", + "src/core/Alu.v", + "src/core/ALU_Control.v", + "src/core/Branch_Prediction.v", + "src/core/CACHE_Request_Multiplexer.v", + "src/core/DCache.v", + "src/core/FPU.v", + "src/core/ICache.v", + "src/core/Immediate_Generator.v", + "src/core/IR_Decompression.v", + "src/core/MDU.v", + "src/core/MUX.v", + "src/core/Registers.v" + ], + "include_dirs": [], + "repository": "https://github.com/JN513/Grande-Risco-5", + "top_module": "Grande_Risco5", + "extra_flags": [], + "language_version": "2005" +} \ No newline at end of file diff --git a/logs/riscv-steel_1738761540.8530455.json b/logs/riscv-steel_1738761540.8530455.json new file mode 100644 index 0000000..37bb29c --- /dev/null +++ b/logs/riscv-steel_1738761540.8530455.json @@ -0,0 +1,286 @@ +{ + "name": "riscv-steel", + "folder": "riscv-steel", + "sim_files": [ + "hardware/tests/core/verilator/unit_tests.v", + "hardware/tests/core/vivado/unit_tests.v", + "hardware/tests/spi/hardware/unit_tests.v", + "hardware/tests/spi/software/arty_a7/unit_tests.v", + "hardware/tests/top/verilator/mcu_sim.v" + ], + "files": [ + "hardware/rvsteel.v", + "hardware/rvsteel_bus.v", + "hardware/rvsteel_core.v" + ], + "include_dirs": [], + "repository": "https://github.com/riscv-steel/riscv-steel", + "top_module": "rvsteel", + "extra_flags": [], + "language_version": "2005", + "modules": [ + { + "module": "freertos_arty_a7", + "file": "examples/freertos/boards/arty_a7/freertos_arty_a7.v" + }, + { + "module": "freertos_cmod_a7", + "file": "examples/freertos/boards/cmod_a7/freertos_cmod_a7.v" + }, + { + "module": "gpio_arty_a7", + "file": "examples/gpio/boards/arty_a7/gpio_arty_a7.v" + }, + { + "module": "gpio_cmod_a7", + "file": "examples/gpio/boards/cmod_a7/gpio_cmod_a7.v" + }, + { + "module": "hello_world_arty_a7", + "file": "examples/hello_world/boards/arty_a7/hello_world_arty_a7.v" + }, + { + "module": "hello_world_cmod_a7", + "file": "examples/hello_world/boards/cmod_a7/hello_world_cmod_a7.v" + }, + { + "module": "mtimer_arty_a7", + "file": "examples/mtimer/boards/arty_a7/mtimer_arty_a7.v" + }, + { + "module": "mtimer_cmod_a7", + "file": "examples/mtimer/boards/cmod_a7/mtimer_cmod_a7.v" + }, + { + "module": "spi_arty_a7", + "file": "examples/spi/boards/arty_a7/spi_arty_a7.v" + }, + { + "module": "spi_cmod_a7", + "file": "examples/spi/boards/cmod_a7/spi_cmod_a7.v" + }, + { + "module": "uart_arty_a7", + "file": "examples/uart/boards/arty_a7/uart_arty_a7.v" + }, + { + "module": "uart_cmod_a7", + "file": "examples/uart/boards/cmod_a7/uart_cmod_a7.v" + }, + { + "module": "rvsteel", + "file": "hardware/rvsteel.v" + }, + { + "module": "rvsteel_bus", + "file": "hardware/rvsteel_bus.v" + }, + { + "module": "rvsteel_core", + "file": "hardware/rvsteel_core.v" + }, + { + "module": "rvsteel_gpio", + "file": "hardware/rvsteel_gpio.v" + }, + { + "module": "rvsteel_mtimer", + "file": "hardware/rvsteel_mtimer.v" + }, + { + "module": "rvsteel_ram", + "file": "hardware/rvsteel_ram.v" + }, + { + "module": "rvsteel_spi", + "file": "hardware/rvsteel_spi.v" + }, + { + "module": "rvsteel_uart", + "file": "hardware/rvsteel_uart.v" + }, + { + "module": "unit_tests", + "file": "hardware/tests/core/verilator/unit_tests.v" + }, + { + "module": "unit_tests", + "file": "hardware/tests/core/vivado/unit_tests.v" + }, + { + "module": "module", + "file": "hardware/tests/core/vivado/unit_tests.v" + }, + { + "module": "unit_tests", + "file": "hardware/tests/spi/hardware/unit_tests.v" + }, + { + "module": "module", + "file": "hardware/tests/spi/hardware/unit_tests.v" + }, + { + "module": "module", + "file": "hardware/tests/spi/hardware/unit_tests.v" + }, + { + "module": "unit_tests", + "file": "hardware/tests/spi/software/arty_a7/unit_tests.v" + }, + { + "module": "module", + "file": "hardware/tests/spi/software/arty_a7/unit_tests.v" + }, + { + "module": "module", + "file": "hardware/tests/spi/software/arty_a7/unit_tests.v" + }, + { + "module": "mcu_sim", + "file": "hardware/tests/top/verilator/mcu_sim.v" + }, + { + "module": "rvsteel_wrapper", + "file": "templates/baremetal/rvsteel_wrapper.v" + }, + { + "module": "rvsteel_wrapper", + "file": "templates/freertos/rvsteel_wrapper.v" + } + ], + "module_graph": { + "freertos_arty_a7": [], + "freertos_cmod_a7": [], + "gpio_arty_a7": [], + "gpio_cmod_a7": [], + "hello_world_arty_a7": [], + "hello_world_cmod_a7": [], + "mtimer_arty_a7": [], + "mtimer_cmod_a7": [], + "spi_arty_a7": [], + "spi_cmod_a7": [], + "uart_arty_a7": [], + "uart_cmod_a7": [], + "rvsteel": [ + "hello_world_arty_a7", + "hello_world_cmod_a7", + "spi_arty_a7", + "spi_cmod_a7", + "unit_tests", + "mcu_sim", + "rvsteel_wrapper", + "rvsteel_wrapper" + ], + "rvsteel_bus": [ + "rvsteel" + ], + "rvsteel_core": [ + "unit_tests" + ], + "rvsteel_gpio": [ + "rvsteel" + ], + "rvsteel_mtimer": [ + "rvsteel" + ], + "rvsteel_ram": [ + "rvsteel", + "unit_tests" + ], + "rvsteel_spi": [ + "rvsteel", + "unit_tests" + ], + "rvsteel_uart": [ + "rvsteel" + ], + "unit_tests": [], + "module": [ + "unit_tests", + "unit_tests", + "rvsteel_wrapper", + "rvsteel_wrapper" + ], + "mcu_sim": [], + "rvsteel_wrapper": [] + }, + "module_graph_inverse": { + "freertos_arty_a7": [], + "freertos_cmod_a7": [], + "gpio_arty_a7": [], + "gpio_cmod_a7": [], + "hello_world_arty_a7": [ + "rvsteel" + ], + "hello_world_cmod_a7": [ + "rvsteel" + ], + "mtimer_arty_a7": [], + "mtimer_cmod_a7": [], + "spi_arty_a7": [ + "rvsteel" + ], + "spi_cmod_a7": [ + "rvsteel" + ], + "uart_arty_a7": [], + "uart_cmod_a7": [], + "rvsteel": [ + "rvsteel_bus", + "rvsteel_ram", + "rvsteel_uart", + "rvsteel_mtimer", + "rvsteel_gpio", + "rvsteel_spi" + ], + "rvsteel_bus": [], + "rvsteel_core": [], + "rvsteel_gpio": [], + "rvsteel_mtimer": [], + "rvsteel_ram": [], + "rvsteel_spi": [], + "rvsteel_uart": [], + "unit_tests": [ + "rvsteel_ram", + "rvsteel_core", + "rvsteel_spi", + "module", + "rvsteel", + "module" + ], + "module": [], + "mcu_sim": [ + "rvsteel" + ], + "rvsteel_wrapper": [ + "module", + "rvsteel", + "module", + "rvsteel" + ] + }, + "non_tb_files": [ + "examples/freertos/boards/arty_a7/freertos_arty_a7.v", + "examples/freertos/boards/cmod_a7/freertos_cmod_a7.v", + "examples/gpio/boards/arty_a7/gpio_arty_a7.v", + "examples/gpio/boards/cmod_a7/gpio_cmod_a7.v", + "examples/hello_world/boards/arty_a7/hello_world_arty_a7.v", + "examples/hello_world/boards/cmod_a7/hello_world_cmod_a7.v", + "examples/mtimer/boards/arty_a7/mtimer_arty_a7.v", + "examples/mtimer/boards/cmod_a7/mtimer_cmod_a7.v", + "examples/spi/boards/arty_a7/spi_arty_a7.v", + "examples/spi/boards/cmod_a7/spi_cmod_a7.v", + "examples/uart/boards/arty_a7/uart_arty_a7.v", + "examples/uart/boards/cmod_a7/uart_cmod_a7.v", + "hardware/rvsteel.v", + "hardware/rvsteel_bus.v", + "hardware/rvsteel_core.v", + "hardware/rvsteel_gpio.v", + "hardware/rvsteel_mtimer.v", + "hardware/rvsteel_ram.v", + "hardware/rvsteel_spi.v", + "hardware/rvsteel_uart.v", + "templates/baremetal/rvsteel_wrapper.v", + "templates/freertos/rvsteel_wrapper.v" + ] +} \ No newline at end of file diff --git a/utils/run_all.py b/utils/run_all.py index 5ad5eef..17ac788 100644 --- a/utils/run_all.py +++ b/utils/run_all.py @@ -21,18 +21,27 @@ O arquivo de entrada `arquivos.txt` deve conter uma URL por linha. """ +import time import subprocess # Caminho para o arquivo que contém a lista de URLs -FILE_PATH = 'processadores2.txt' +MODEL_PATH = 'models.txt' +FILE_PATH = 'processadores3.txt' # Abrir o arquivo e ler as URLs with open(FILE_PATH, 'r', encoding='utf-8') as file: urls = file.readlines() +# Abrir o arquivo e ler o nome dos modelos +with open(MODEL_PATH, 'r', encoding='utf-8') as file: + models = file.readlines() + # Remover qualquer espaço ou quebra de linha ao final de cada URL urls = [url.strip() for url in urls] +# Remover qualquer espaço ou quebra de linha ao final de cada modelo +models = [model.strip() for model in models] + # Comando base command_base = [ 'proxychains', @@ -42,24 +51,59 @@ '', '-c', '-a', + '-p', + '', + '-m', + '', #'-n', ] # Timeout de 3 minutos (180 segundos) TIMEOUT_SECONDS = 720 +urls_falharam = [] +urls_sucesso = [] + +relatorio = [] + # Para cada URL na lista, executar o comando com timeout -for url in urls: - # Montar o comando com a URL - command_base[3] = url # Substituir a URL no comando - print(f"Executando: {' '.join(command_base)}") - - try: - # Executar o comando com timeout - subprocess.run(command_base, timeout=TIMEOUT_SECONDS, check=True) - except subprocess.TimeoutExpired: - print( - f'Comando para {url} atingiu o tempo limite de {TIMEOUT_SECONDS} segundos.' - ) - except subprocess.CalledProcessError as e: - print(f'Erro ao executar o comando para {url}: {e}') +for model in models: + tempo_inicio = time.time() + command_base[8] = f'{model}.json' + command_base[10] = model + + print(f'Modelo: {model}\n\n') + + for url in urls: + # Montar o comando com a URL + command_base[4] = url # Substituir a URL no comando + print(f"Executando: {' '.join(command_base)}") + + try: + # Executar o comando com timeout + subprocess.run(command_base, timeout=TIMEOUT_SECONDS, check=True) + urls_sucesso.append(url) + except subprocess.TimeoutExpired: + print( + f'Comando para {url} atingiu o tempo limite de {TIMEOUT_SECONDS} segundos.' + ) + urls_falharam.append(url) + except subprocess.CalledProcessError as e: + print(f'Erro ao executar o comando para {url}: {e}') + + tempo_fim = time.time() + print(f'Tempo total de execução: {tempo_fim - tempo_inicio} segundos') + + relatorio.append( + f'Modelo: {model}\nTempo total de execução: {tempo_fim - tempo_inicio} segundos\n\n' + ) + +print('\n') + +print(f'URLs que falharam: {urls_falharam}') +print(f'URLs que tiveram sucesso: {urls_sucesso}') + +with open('relatorio.txt', 'w', encoding='utf-8') as file: + file.writelines(relatorio) + +print("Relatório salvo em 'relatorio.txt'")