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Pavel I. Kryukov edited this page Sep 25, 2018 · 55 revisions

This project is a part of ILab activity at Moscow Institute of Physics and Technology (MIPT) led by Intel employees.

The aim of the project is to teach the students the computer architecture through development of a microprocessor implementing the MIPS instruction set in both functional and performance simulators.

Brief project history

  • 2012: Alexander and Pavel replaced MDSP project with new project "uArchSim". More common MIPS became target ISA instead of complicated MDSP, focus was moved from simulation to computer architecture theory.
  • 2013: Project got new pun name "MIPT-MIPS". Mentors attempted to use FPGA for modeling, but the idea was postponed due to external circumstances.
  • 2014: Alexander and Pavel continued MIPT-MIPS project, adding new lectures material and assignments.
  • 2015: Project moves from GoogleCode SVN to GitHub. Since Alexander started his Digital Design course, the new mentors team consists of Pavel Kryukov and Igor Smirnov.
  • 2016: Project takes a half-year hiatus and starts on February 2017 with brand new assignments.
  • 2017: The focus is moved to development of fast and versatile simulator. Lectures are delivered by Igor Smirnov.
  • 2018: Computer Architecture and Simulation Development courses are diverging. Lectures on Simulation Development are delivered by Kirill Korolev and Oleg Ladin.

Brief simulator changelist

For the full simulator changelist, please check our releases page

  • 2013: Elf parser, functional model
  • 2015: MIPS disassembler, functional model
  • 2016: Performance model, standalone cache simulator
  • 2017: Branch prediction
  • 2018: Instruction cache, data bypass, new instructions

Roadmap

The nearest objective is to create performance model of classical 5-stage MIPS CPU using most of the features described by Hennessy and Patterson:

  • Instruction caches
  • Data bypassing and non-unified pipelines
  • Data caches
  • Interrupts and system calls

Mid-term targets are integration to existing simulation environments

  • Encapsulation of ISA and switch to multi-ISA simulation: MIPS, RISC-V, OpenRISC, and ARM.
  • Visualization with EduMIPS
  • Interactive simulation through GDB
  • Intergration to CEN64 simulation

Then, possible main directions are:

  • Forking project to create model of out-of-order superscalar MIPS, like R10000.
  • Align model with MIPSfpga.
  • Verilog model of 5-stage MIPS CPU aligned with performance model.
  • Multicore/Multithread modeling support with cache coherence models.

Current mentors

Igor Smirnov Kirill Korolev Oleg Ladin Pavel Kryukov
Computer Architecture lectures Software lectures, Code reviews Software lectures, Code reviews Project manager, Code reviews

Legal information

MIPT-MIPS source code is distributed under the terms of MIT License.

The lectures have been created by Alexandr Titov, Pavel Kryukov and Igor Smirnov. The content is distributed under the terms of the CC BY-SA 3.0 License.

Intel and the Intel Logo are registered trademarks in the U.S. and/or other countries.

MIPS is a registered trademark of MIPS Technologies.

Other names and brands may be claimed as the property of others.

Contact info

Pavel Kryukov: [email protected]
Igor Smirnov: [email protected]

MIPT-V / MIPT-MIPS — Cycle-accurate pre-silicon simulation.

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