2-Day Workshop, 31st July 2021 and 1st August 2021
The two day workshop on designing Phase Locked Loop (PLL) using SKY130nm Technology comprised of the following things:
Day 1 : Basics of PLL and Steps for lab setup
Day 2 : PLL simulation (Prelayout and Postlayout)
The day 1 covers the basics of PLL and steps to install ngspice and magic for designing of PLL.
Phase locked loop is a feedback system which generates a high frequency, low noise clock.
Crystal Oscillators and Voltage controlled oscillators are the two ways to generate the clock signal.
Crystal oscillators are the purest form of clock with excellent phase noise. The drawback of crystal oscillators is that it has very low frequency and have very limited tuning range. Hence, Voltage controlled oscillators (VCOs) are used which can generate high frequency clock, but it has poor phase noise. To get a low phase noise, high frequency clock, we use phase locked loop which makes the VCO mimic the crystal to achieve low phase noise, while still getting high frequency clock.
Phase noise is the random fluctuation of the zero crossing of a periodic waveform , that is, untimely arrival of data.
The block diagram of PLL is as shown below:
PLL has five blocks:
- Phase Frequency Detector (PFD)
It detects the phase (and frequency) error between the input reference clock IN (that is, crystal oscillator) and feedback clock FB. It generates two output signals, UP and DN, whose pulse width is proportional to the phase error.
For, detecting the phase error between the input reference clock and the feedback clock, we donot use XOR phase detector as it doesnt correct the frequency errors. Instead, we use Phase Frequency Detector , which will correct both, phase and frequency differences between the input reference clock and the feedback clock.
The basic block diagram of PFD is as shown below:
When falling edge of reference clock leads feedback clock, the UP signal goes high and DN signal remains low. UP signal remains high until it detects the falling edge of the feedback clock. As soon as feedback clock falling edge arrives, UP signal goes low.
When falling edge of feedback clock leads reference clock, the DN signal goes high and UP signal remains low. DN signal remains high until it detects the falling edge of the reference clock. As soon as reference clock falling edge arrives, DN signal goes low.
Dead zone is one of the problem of PFD. The phase difference below which PFD output is not able to reach the desired logical level and fails to turn on the charge pump switches is called the dead zone. Above precision PFDs are present, which overcomes this issues.
- Charge Pump (CP)
The loop filer takes input as voltage/current. Hence, the pulse width modulates signal at the output of PFD have to be transformed to volateg/current. Therefore, we use charge pump circuit.
It generates the error current (ICP) which is proportional to the phase difference od pulse width between UP and DN which inturn is proportional to the input phase error.
Charge pump chagres or discharges the loop filter based upon the UP and DN signals. If UP signal is high, charge pump charges the loop filter. If DN signal is high, charge pump discharges the loop filter.
Charge pump circuit have of charge leakage, which should be reduced as much as possible.
- Loop Filter (LF)
It converts the error current into error voltage. It also controls the loop dynamics and stability of the system.
For the stability purpose, C2 capacitor should be one-tenth of the C1 capacitor. Loop filter bandwidth should be one-tenth of the highes output frequency. 4. Voltage Controlled Oscillator (VCO)
VCO is the heart of PLL and it generates the desired high frequency clock output.
The most common on-chip VCO used is the ring oscillators which consists of odd number of inverters. The period will be twice the number of inverter delays multiplied be the inverter delay. One of the way, to control the frequency of the ring oscillator is to vary the current using the current starving technique. It is important to note that, we should design the VCO is such a way that the range of frequencies we want for the PLL is generated properly by the VCO.
- Frequency Divider (N)
It divides the VCO clock to generate the feedback clock with same frequency as input reference clock.
A toggle flip flop generates the clock which has twice the time period of the input clock given to it, that is we obtain the clock having half the frequency of the input clock provided to the frequency divider. For 8x clock multiplier, we should divide the output clock by 8 to generate feedback clock. For obtaining one-eigth of frequency, we should cascade three toggle flip flops.
- Lock-in range
Range of freuencies which PLL can stay in lock in steady state. It mainly depends on the range of frequencies VCO can produce and is limited by the dead zone of PFD.
- Capture range
Range of frequencies which PLL can lock when started from unlocked condition. Capture range is smaller than the lock-in range. It depends on the loop filter bandwidth.
- Settling time
The time taken by the PLL to lock from an unlocked state is called the settling time. It depends on how quickly charge pump rises to the stable value.
We should use the source code to build any software tool as it gives the latest updates and fixes.
Here, we will use two tools. They are:
Ngspice : for transistor level simulation
Magic : for layout design and parasitic extraction.
From the ubuntu package , we will be downloading Ngspice directly. Magic we will compile it with the source code because we need the latest version of Magic to support Skywater130nm technology node.
Ngspic: ngsice<circuit_file_name>
It plots the results based upon the simulation instruction given in the circuit file after simulating the given circuit file.
Magic: magic - T <Technology_file_from_PDK><the_layout_file_to_open>
It opens the layout file, where we can view the layout and make modifications to it. Magic has many features, out of which we will be using parasitic extraction and gds features.
With the PLL specifications, we will perform SPICE-level circuit development and pre-layout simulation. After the pre-layout simulation we develop layout. Before layout phase we donot know the interconnection or proximity or size of the different circuits. After layout, we can extract the capacitive effect which is called a s the parasitic extraction. After this, we have spice netlist which is more closer to the real worls. Then, we do the post simulation which is more accurate than thr pre-layout simulation.
Its is important to note that, after each simulation step, we should make several changes to bring the working of the circuit much closer to the required specification.
We use the following command to isntall Ngspice:
sudo apt-get install ngspice
Then we fetch the sky130 library which consists of the transistor models which is needed for the simulation.
We will use the source code from opendesigncircuit.com. We can do the git clone and intall the Magic. Then, we should compile it, for that we should install the dependencies form the opendesigncircuit.com. Then we run the ./configure command. The we run the make command. Then we run the command
sudo make install
Then we should install the sky130nm technology information which Magic needs for desiging the layout.
Corner = TT
Supply voltage = 1.8V
Temperature = Room temperature
Input Fmin= 5MHz , Fmax= 12.5MHz
Multiplier = 8x
Jitter (RMS) < 20ns
Duty cycle = 50%
A spice file is a text file with .cr extenstion.
For example, if we want to write code for frequency divider circuit, we write the following command in terminal:
touch FD.cir
and then page will be created where we should write the code for the desired circuit. Don't forget to include the SPICE library file in it.
Similarly we do it for all the blocks of PLL.
After creating the .cr files we run the Ngspice simulation.
Similarly, we run this command for different PLL blocks by appropriately changing the name of the block as per the requirement.
Red: Clock 1
Blue: Clock 2
Orange: Up Signal
Green: Down Signal
Red: Charge pump output voltage
Red: Charge pump output voltage
Leakage: 40uV increase every 1us
Red: Control Voltage
Blue: Output Clock
Red: Output Clock
Blue: Input Clock
Red: Reference Clock
Blue: Output Clock Divided by 8
Yellow: Down Signal
Brown: Up Signal
Pink (top) :Charge pump output
If output doesn't match or mimic properly, first is to observe what kinds of issues you are facing. Always try to debug individual circuits beore simulating the whole circuit.
If signals are coming flat up or the simulation is crashing then check whether the connectivity is done properly or any issues like wrong net names, capitaliszation issues or parameter value issues.
If the signals are coming as expected but mimicing of signal is not happening then verify the following:
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VCO is working within the required range or not.
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Whether the PFD is able to detect small phase differences or not.
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How is the response of charge pump? Is it fast or slow. Too much fluctuations in charging or discharging, then capacitor sizing is the thing where we have to pay the attention to. Also, check if there is charge leakage. If the charge pump is charging when the input is zero, then there is charge leakage issue.
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If nothing works out, then try adjusting the loop filter by using the thumb rule.
In layout, these are the following different colour codes for different components used in layout:
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p-diffusion - plane orange colour
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n-diffusion - plane green colour
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polysilicon - plane red
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n-well - slash lines
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metal1 layer - purple
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local interconnect layer - blue
To connect two transistors, we use interconnect layer. To connect two metal layers, we use the contact/via.
Similarly, we run this command for different PLL blocks by appropriately changing the name of the block as per the requirement.
Area: 49.09um square
Area: 132.29um square
Area: 57.73um square
Area: 49.09um square
Area: 12.12um square
Area: 496.03um square
Similarly, we run this command for different PLL blocks by appropriately changing the name of the block as per the requirement.
Red: Clock 1
Blue: Clock 2
Orange: Up signal
Green: Down signal
Orange: Charge Pump Output Voltage
Red: Up Signal
Blue: Down Signal
Orange: Charge Pump Output Voltage
Red: Up Signal
Blue: Down Signal
Leakage: < 0.05V in 100us
Red: Output Clock
Blue: Control Voltage
Red: Input Clock
Blue: Output Clock
Red: Reference Clock
Blue: Output Clock Divided by 8
Yellow: Down Signal
Brown: Up Signal
Pink (top) :Charge pump output
Tapeout means to send our design to the fab after we prepare it with all the additional support we require.
We should first connect our silicon wafer with the real world. For that we use I/O pads. Then for any kind of serial connectivity like I2C, UART and other peripherals, we should have their designs. Memory also has to be incorporated which takes a lot of space. Testing mechanisms should also be added. Taking care of all of this becomes complicated hence, we should choose a driver to enable our IP to meet the desired requirements to undergo fabrication process. For this we can use Efabless Caravel SoC template.
It will provide the user project area to add our design, and we need not bother about other things on SOC.
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I would like to thank Mr. Kunal Ghosh, co-founder VSD, for providing me with this wonderful 2-day workshop.
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I would like to thank Ms. Lakshmi S, for guiding throughout the workshop about how to design PLL.