Veecom new release: v1.1

Author: Mazin-O3

README.md

@@ -1,6 +1,6 @@
 # Veecom
 
-#### A Simple Yet Powerful RISC-V Computer	
+#### Simple Yet Powerful RISC-V Computer	
 
 ## Table of Contents
 * [Introduction](#intro)<br />
@@ -11,14 +11,15 @@
 * [uBASIC](#ubasic)<br />
 * [Games](#games)<br />
 * [Memory Map](#mmap)<br />
+* [Benchmarks](#bench)<br />
 
 Introduction <a name="intro"></a>
 --- 
 
 Veecom is a 32-bit computer system that combines the simplicity of 8-bit home computers with modern RISC-V technology, offering users a unique and nostalgic computing experience. It features several notable improvements over the RISC-V Computer 2.0. These include a sleek new design, improved CPU microarchitecture, a new Multi-Cycle CPU version, simplified DMA design, a new replacement for the PIA and a simple BASIC interpreter for an engaging programming experience.
 
 <figure align="center">
-    <img src="screenshots/veecom.svg", alt="veecom">
+    <img src="images/veecom.png", alt="veecom">
 </figure>
 
 <br/>
@@ -30,7 +31,7 @@ Veecom's design follows a Memory-Mapped approach, utilizing an Address Decoder t
 The DMA Controller in Veecom is simpler in design and more compact, supporting up to 64KB of data transfer and addressing capability.
 
 <figure align="center">
-    <img src="screenshots/arch_orgi.svg", alt="arch_orgi">
+    <img src="images/arch_orgi.svg", alt="arch_orgi">
 </figure>
 
 <br/>
@@ -43,33 +44,61 @@ Veecom's CPUs are based on the RV32IM variant of the RISC-V ISA, implementing th
 #### Single-Cycle Version
 
 <figure align="center">
-    <img src="screenshots/cpu_single_cycle.svg", alt="cpu_sc">
+    <img src="images/cpu_single_cycle.png", alt="cpu_sc">
 </figure>
 <br/>
 
 #### Multi-Cycle Version
 
 <figure align="center">
-    <img src="screenshots/cpu_multi_cycle.svg", alt="cpu_mc">
+    <img src="images/cpu_multi_cycle.png", alt="cpu_mc">
 </figure>
 <br/>
 
 #### Pipelined Version
 
 <figure align="center">
-    <img src="screenshots/cpu_pipeline.svg", alt="cpu_5pl">
+    <img src="images/cpu_pipelined.png", alt="cpu_5pl">
 </figure>
 
 <br/>
 
+#### Pipelined Version with Branch Prediction
+
+<figure align="center">
+    <img src="images/cpu_pipelined_bp.png", alt="cpu_5pl_bp">
+</figure>
+
+<br/>
+
+#### Branch Predictor
+ 
+The design of this predictor is static branch prediction, featuring a 6-bit Branch History Register `BHSR` and 64-entry Branch Target Buffer `BTB`. It uses an indexing machanisim similar to `GShare predictors`, where the Program Counter `PC` value is XORed with the `BHSR`. This static predictor is a `Taken-Only` design, where only taken branches are stored in the `BTB`.
+
+<figure align="center">
+    <img src="images/branch_predictor.png", alt="via">
+</figure>
+
+<br/>
+
+
+#### Theory vs. Implementation
+
+<figure align="center">
+    <img src="images/theory_vs_implementation.png", alt="impl">
+</figure>
+
+<br/>
+
+
 Versatile Interface Adapter (VIA) <a name="via"></a>
 ---
 
 Inspired by the MOS 6522 VIA, Veecom's VIA features several enhancements and improvements over its predecessor, featuring three 8-bit I/O ports `Port A`, `Port B` and `Port C` that can be used for both input and output without the need for data direction register, allowing for more flexible I/O access (Please refer to [Memory Map](#mmap) section for supported operations).
 Additionally, the VIA features a new 8-bit timer similar to Timer-1 found in the MOS 6522 VIA. it supports multiple operation frequencies (up to `f/16`, with `f/2` set as default) and two operations modes, `One-Shot` and `Free-Run`. 
 
 <figure align="center">
-    <img src="screenshots/via.svg", alt="via">
+    <img src="images/via.png", alt="via">
 </figure>
 
 #### Timer Operation
@@ -93,7 +122,7 @@ The Timer Expired Flag (TXP) indicates if a timer overflow has occurred. Once th
 This 8-bit register controls the operation of the timer, the following figure lists the functions of the command bits.
 
 <figure align="center">
-    <img src="screenshots/timer_ctrl.svg", alt="via">
+    <img src="images/timer_ctrl.svg", alt="via">
 </figure>
 
 <br/>
@@ -108,7 +137,7 @@ The DMA Controller in Veecom is simpler in design and more compact, supporting u
 The DMA Controller is designed for fast and efficient `memory-to-IO` data transfer. It features four 8-bit registers: `DSL`, `DSH`, `DAL` and `DAH`, which control the size and address of the data being transferred (Please refer to [Memory Map](#mmap) section for supported operations). The `DSL` and `DSH` registers determine the size of the data, allowing for 16-bit transfers. The `DAL` and `DAH` registers specify the memory location from which data is fetched. Once the `DAH` register is written, the DMA Controller asserts the `HRQ` (Hold Request) pin, signaling the CPU to halt if it's not currently using the system bus. In response, the CPU acknowledges the request by asserting `HLDA` (Hold Acknowledge) pin. The CPU remains halted until the transfer is completed. 
 
 <figure align="center">
-    <img src="screenshots/dmac.svg", alt="dmac">
+    <img src="images/dmac.png", alt="dmac">
 </figure>
 
 <br/>
@@ -118,6 +147,11 @@ uBASIC <a name="ubasic"></a>
 
 [Veecom uBASIC](https://github.com/MazinCE/Veecom-uBasic) is a derivative of the [uBASIC](https://dunkels.com/adam/ubasic/) interpreter originally authored by Adam Dunkels. This version of uBASIC has been improved to be made fully interactive, with the incorporation of additional commands and performance optimizations.
 
+<figure align="center">
+    <img src="images/ubasic.svg", alt="dmac">
+</figure>
+
+<br/>
 
 #### Key Features
 
@@ -138,7 +172,7 @@ Veecom uBASIC added support for multiple new commands, these include `RUN`, `LIS
     50 GOTO 30
 
 <figure align="center">
-    <img src="screenshots/timer_example.svg", alt="timer_example">
+    <img src="images/timer_example.svg", alt="timer_example">
 </figure>
 <br/>
 
@@ -148,16 +182,16 @@ For more details, please visit [Veecom uBASIC](https://github.com/MazinCE/Veecom
 
 ### Games <a name="games"></a>
 
-#### Lunar Lander (Apple 1 Version 1976)
+#### Lunar Lander (Apple 1 1976)
 
 <figure align="center">
-    <img src="screenshots/lunar_lander.png", alt="lander">
+    <img src="images/lunar_lander.png", alt="lander">
 </figure>
 <br />
 
 #### Hangman
 <figure align="center">
-    <img src="screenshots/hangman.png", alt="hangman">
+    <img src="images/hangman.png", alt="hangman">
 </figure>
 
 <br/>
@@ -166,7 +200,7 @@ Memory Map <a name="mmap"></a>
 ---
 
 | Address |   Symbol  | Description           | Supported Operations |
-| :----:  |   :----   | :----------------     | :---                 |
+| :---    |   :----   | :----------------     | :---:                |
 | 0xFFFF  | TXP       | Timer Expired Flag    | Read                 |
 | 0xFFFF  | TCR       | Timer Control Register| Write                |
 | 0xFFFE  | TVR       | Timer Value Register  | Read/Write           |
@@ -182,3 +216,16 @@ Memory Map <a name="mmap"></a>
 | 0xFFF4  | DAL       | DMA Block Address Lo  | Write                |
 |0x0000 - 0xFFF3 | RAM   | Main Memory        | Read/Write           |    
 
+<br/>
+
+Benchmarks <a name="bench"></a>
+---
+
+The follwing benchmark results were obtained using `riscv64-unknown-elf-gcc (GCC) 10.1.0` with no compiler optimizations applied `-O0`. Each number represents the number of clock cycles taken for execution.
+
+| CPU Model      |  Quick Sort (10 El)  | Matrix Multiplication (4x4) | Memset (100-Integer Buffer) |
+| :---           |   :---:              | :---:                       | :---:                       | 
+| Single-Cycle   | 2322                 | 6601                        | 624                         | 
+| Multi-Cycle    | 6298                 | 19565                       | 1881                        | 
+| Pipelined      | 2426                 | 6891                        | 841                         | 
+| Pipelined w/BP | 2385                 | 6770                        | 643                         |