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CHANGELOG.md

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Changelog

The format is based on Keep a Changelog.

2.13.0-3

Fixed

  • Increate hssi poll timeout from 500 us to 1 s (#3132).

2.13.0-2

Added

  • Add a mechanism for AFUs to set platform macros (#3130).

Fixed

  • Fix buffer comparison in interrupt test mode of host exerciser (#3131).

2.13.0-1

Added

  • Add support for varying HE LB data bus widths to host exerciser (#3110).
  • Add board plugin for JTAG-only PCI development kits (#3120, #3125).

Changed

  • Suggest hssiloopback and hssistats for Agilex-based FPGA cards (#3117).

Removed

  • Remove unsupported SDM hashes and cancel keys from CMC board module (#3099).

Fixed

  • Limit progress bar to 100% in fpgasupdate (#3104).
  • Fix memory use-after-free of static logger object (#3116).
  • Do not check EMIF calibration when simulating host exerciser (#3121).
  • Fix multiplier for board power sensor (#3122).
  • Correctly document status register value in copy engine (#3124).
  • Correctly handle local memory width in host exerciser (#3126).

2.12.0-5

Fixed

  • Bump release number of binary packages to match release tag (#3114, #3115).

2.12.0-4

Fixed

  • Support host exerciser on devices without FPGA management PF (#3108, #3109).

2.12.0-3

Fixed

  • Set PCI SBDF to enumerate FPGA device and accelerator in afu_test (#3103, #3105)

2.12.0-2

Changed

  • Improved error message for buffer allocation failure in host exerciser memory test (#3102).

Fixed

  • Fix Partial Reconfiguration on boards without BMC interface (#3101).

2.12.0-1

Added

  • Add loop count command line input to CXL host exerciser (#3051).
  • Add running pointer and ping-pong tests to CXL host exerciser (#3056).
  • Add opae-mem tool as a replacement for ofs.uio (#3055).
  • Add cxl_hello_fpga sample for CMC (#3052).
  • Add parent/child AFU management to the libopae-c shell (#3072).
  • Add --force and --enable-sriov options to opae.io (#3079).
  • Add support for multi-port AFUs in OPAE vfio plugin (#3080).

Changed

  • Remove latency iterations from write cache hit/miss scenario tests (#3043).
  • Support 16GB memory for MEM_TG in cxl_mem_tg sample (#3058).
  • Remove unsupported loopback command from CXL host exerciser (#3059).
  • Remove redundant host read and write cache miss tests from CXL host exerciser (#3064).
  • Improve fpgametrics output readability (#3075).
  • Replace Bitstream Version with Image Info in bitstreaminfo output (#3076).
  • Improve VFIO device enumeration performance (#3090).
  • Hide confusing log message in pacsign (#3092).

Fixed

  • Fix CXL host exerciser read latency output (#3042).
  • Correct issue pointed out by static analysis (#3044, #3046).
  • Fix uninitialized variable errors in fpgabist (#3053).
  • Fix CXL traffic generator read/write bandwidth and argument checks (#3054).
  • Disallow factory image update if boot page is also factory (#3049).
  • Set FPGA buffer read-only for device bias mode (#3057).
  • Define PCI_STD_NUM_BARS when not found (#3061).
  • Set continuous mode bit for write cache hit/miss tests (#3062).
  • Skip check for factory boot page in fpgasupdate under certain conditions (#3063).
  • Fix segmentation fault in CXL host exerciser in non-root user mode (#3067).
  • Fix running pointer test output in CXL host exerciser (#3068).
  • Only clear AER errors when AER is available (#3073).
  • Fix SEGV when passing NULL buf_addr to fpgaPrepareBuffer() (#3077).
  • Update test completion timeout value in cxl_mem_tg sample (#3081).
  • Fix progress output in fpgasudpate (#3078).
  • Update test completion timeout to 10 seconds in cxl_mem_tg sample (#3086, #3087).
  • Update latency calculations in CXL host exerciser (#3088).
  • Check memory calibration status before running host exerciser (#3094).
  • Fix error handling when vfio-pci driver binding fails in opae.io (#3095).

Security

  • Address issues pointed out by Python scanners (#3036, #3045).