From 7e15c4a12f94dd4e8d79bc03b08bf025cf324a77 Mon Sep 17 00:00:00 2001 From: Matthew Wishek Date: Sat, 25 Oct 2025 23:17:28 -0600 Subject: [PATCH 01/60] Switch from desyrdl to peakrdl for sysrdl --- prbs | 2 +- rdl/Makefile | 43 +- rdl/cocotb/desyrdl/addrmap_ch0.py | 117 - rdl/msk_top_regs.h | 369 - rdl/msk_top_regs.pl | 40 - rdl/msk_top_regs.rdl | 408 - rdl/msk_top_regs_desy.rdl | 208 - rdl/outputs/c-header/msk_top_regs.h | 362 + rdl/{ => outputs/docs}/msk_top_regs.md | 122 +- rdl/{ => outputs/docs}/msk_top_regs.pdf | Bin 115023 -> 113089 bytes rdl/outputs/python/msk_top_regs/__init__.py | 1 + rdl/outputs/python/msk_top_regs/example.py | 13 + .../python/msk_top_regs/lib/__init__.py | 114 + .../python/msk_top_regs/lib/async_memory.py | 626 + .../lib/async_register_and_field.py | 1230 ++ rdl/outputs/python/msk_top_regs/lib/base.py | 942 + .../python/msk_top_regs/lib/base_field.py | 549 + .../python/msk_top_regs/lib/base_register.py | 229 + .../python/msk_top_regs/lib/callbacks.py | 363 + .../python/msk_top_regs/lib/field_encoding.py | 80 + rdl/outputs/python/msk_top_regs/lib/memory.py | 752 + .../msk_top_regs/lib/register_and_field.py | 1189 ++ .../msk_top_regs/lib/utility_functions.py | 83 + .../python/msk_top_regs/reg_model/__init__.py | 1 + .../msk_top_regs/reg_model/msk_top_regs.py | 9451 +++++++++ .../python/msk_top_regs/sim/__init__.py | 1 + .../python/msk_top_regs/sim/msk_top_regs.py | 175 + .../python/msk_top_regs/sim_lib}/__init__.py | 0 .../python/msk_top_regs/sim_lib/_callbacks.py | 79 + .../python/msk_top_regs/sim_lib/base.py | 34 + .../msk_top_regs/sim_lib/dummy_callbacks.py | 256 + .../python/msk_top_regs/sim_lib/field.py | 154 + .../python/msk_top_regs/sim_lib/memory.py | 159 + .../python/msk_top_regs/sim_lib/register.py | 211 + .../python/msk_top_regs/sim_lib/simulator.py | 500 + .../python/msk_top_regs/tests/__init__.py | 1 + .../tests/_msk_top_regs_sim_test_base.py | 50 + .../tests/_msk_top_regs_test_base.py | 121 + .../msk_top_regs/tests/test_msk_top_regs.py | 16576 ++++++++++++++++ .../tests/test_sim_msk_top_regs.py | 7518 +++++++ rdl/outputs/rtl/msk_top_regs.vhd | 2321 +++ rdl/outputs/rtl/msk_top_regs_pkg.vhd | 432 + rdl/src/axi4lite_intf_pkg.vhd | 42 + rdl/src/msk_top_regs.rdl | 552 + rdl/src/reg_utils.vhd | 232 + rdl/src/regblock_udps.rdl | 54 + sim/Makefile | 17 +- sim/desyrdl | 1 - sim/msk_test.py | 164 +- sim/msk_top_nvc.gtkw | 619 +- sim/msk_top_regs | 1 + src/cdc_resync.vhd | 103 + src/msk_top.vhd | 2 - src/msk_top_csr.vhd | 211 +- 54 files changed, 46432 insertions(+), 1448 deletions(-) delete mode 100644 rdl/cocotb/desyrdl/addrmap_ch0.py delete mode 100644 rdl/msk_top_regs.h delete mode 100755 rdl/msk_top_regs.pl delete mode 100644 rdl/msk_top_regs.rdl delete mode 100644 rdl/msk_top_regs_desy.rdl create mode 100644 rdl/outputs/c-header/msk_top_regs.h rename rdl/{ => outputs/docs}/msk_top_regs.md (87%) rename rdl/{ => outputs/docs}/msk_top_regs.pdf (60%) create mode 100644 rdl/outputs/python/msk_top_regs/__init__.py create mode 100644 rdl/outputs/python/msk_top_regs/example.py create mode 100644 rdl/outputs/python/msk_top_regs/lib/__init__.py create mode 100644 rdl/outputs/python/msk_top_regs/lib/async_memory.py create mode 100644 rdl/outputs/python/msk_top_regs/lib/async_register_and_field.py create mode 100644 rdl/outputs/python/msk_top_regs/lib/base.py create mode 100644 rdl/outputs/python/msk_top_regs/lib/base_field.py create mode 100644 rdl/outputs/python/msk_top_regs/lib/base_register.py create mode 100644 rdl/outputs/python/msk_top_regs/lib/callbacks.py create mode 100644 rdl/outputs/python/msk_top_regs/lib/field_encoding.py create mode 100644 rdl/outputs/python/msk_top_regs/lib/memory.py create mode 100644 rdl/outputs/python/msk_top_regs/lib/register_and_field.py create mode 100644 rdl/outputs/python/msk_top_regs/lib/utility_functions.py create mode 100644 rdl/outputs/python/msk_top_regs/reg_model/__init__.py create mode 100644 rdl/outputs/python/msk_top_regs/reg_model/msk_top_regs.py create mode 100644 rdl/outputs/python/msk_top_regs/sim/__init__.py create mode 100644 rdl/outputs/python/msk_top_regs/sim/msk_top_regs.py rename rdl/{cocotb/desyrdl => outputs/python/msk_top_regs/sim_lib}/__init__.py (100%) create mode 100644 rdl/outputs/python/msk_top_regs/sim_lib/_callbacks.py create mode 100644 rdl/outputs/python/msk_top_regs/sim_lib/base.py create mode 100644 rdl/outputs/python/msk_top_regs/sim_lib/dummy_callbacks.py create mode 100644 rdl/outputs/python/msk_top_regs/sim_lib/field.py create mode 100644 rdl/outputs/python/msk_top_regs/sim_lib/memory.py create mode 100644 rdl/outputs/python/msk_top_regs/sim_lib/register.py create mode 100644 rdl/outputs/python/msk_top_regs/sim_lib/simulator.py create mode 100644 rdl/outputs/python/msk_top_regs/tests/__init__.py create mode 100644 rdl/outputs/python/msk_top_regs/tests/_msk_top_regs_sim_test_base.py create mode 100644 rdl/outputs/python/msk_top_regs/tests/_msk_top_regs_test_base.py create mode 100644 rdl/outputs/python/msk_top_regs/tests/test_msk_top_regs.py create mode 100644 rdl/outputs/python/msk_top_regs/tests/test_sim_msk_top_regs.py create mode 100644 rdl/outputs/rtl/msk_top_regs.vhd create mode 100644 rdl/outputs/rtl/msk_top_regs_pkg.vhd create mode 100644 rdl/src/axi4lite_intf_pkg.vhd create mode 100644 rdl/src/msk_top_regs.rdl create mode 100644 rdl/src/reg_utils.vhd create mode 100644 rdl/src/regblock_udps.rdl delete mode 120000 sim/desyrdl create mode 120000 sim/msk_top_regs create mode 100644 src/cdc_resync.vhd diff --git a/prbs b/prbs index 48d9d49..8e42b3e 160000 --- a/prbs +++ b/prbs @@ -1 +1 @@ -Subproject commit 48d9d49b0380a4eb18c13c230182dede94462a28 +Subproject commit 8e42b3ea00644cea5ae34b4ebba2e062bdc58be3 diff --git a/rdl/Makefile b/rdl/Makefile index c9f51ae..901e45d 100644 --- a/rdl/Makefile +++ b/rdl/Makefile @@ -1,21 +1,36 @@ -all: msk_top_regs.pdf msk_top_regs.h msk_top_regs_desy.rdl gen_files_cocotb.txt gen_files_vhdl.txt +#all: msk_top_regs.pdf msk_top_regs.h msk_top_regs_desy.rdl gen_files_cocotb.txt gen_files_vhdl.txt -gen_files_cocotb.txt : msk_top_regs_desy.rdl - desyrdl -i msk_top_regs_desy.rdl -f cocotb +SRCS = src/regblock_udps.rdl src/msk_top_regs.rdl -gen_files_vhdl.txt : msk_top_regs_desy.rdl - desyrdl -i msk_top_regs_desy.rdl -f vhdl +OUTDOCS = outputs/docs +OUTRTL = outputs/rtl +OUTPYTHON = outputs/python +OUTCHEADER = outputs/c-header -msk_top_regs_desy.rdl : msk_top_regs.rdl msk_top_regs.pl - rm msk_top_regs_desy.rdl - ./msk_top_regs.pl msk_top_regs.rdl > msk_top_regs_desy.rdl +all: $(OUTDOCS)/msk_top_regs.pdf \ + $(OUTDOCS)/msk_top_regs.md \ + $(OUTRTL)/msk_top_regs.vhd \ + $(OUTPYTHON)/__init__.py \ + $(OUTCHEADER)/msk_top_regs.h -msk_top_regs.md: msk_top_regs.rdl - peakrdl markdown msk_top_regs.rdl -o msk_top_regs.md +$(OUTDOCS)/msk_top_regs.md: $(SRCS) + peakrdl markdown $(SRCS) -o $(OUTDOCS)/msk_top_regs.md -msk_top_regs.h: msk_top_regs.rdl - peakrdl c-header msk_top_regs.rdl -o msk_top_regs.h +$(OUTCHEADER)/msk_top_regs.h: $(SRCS) + peakrdl c-header $(SRCS) -o outputs/c-header/msk_top_regs.h -msk_top_regs.pdf: msk_top_regs.md - pandoc -o msk_top_regs.pdf msk_top_regs.md +$(OUTRTL)/msk_top_regs.vhd: $(SRCS) + peakrdl regblock-vhdl $(SRCS) -o $(OUTRTL) --cpuif axi4-lite + +$(OUTDOCS)/msk_top_regs.pdf: $(OUTDOCS)/msk_top_regs.md + pandoc -o $(OUTDOCS)/msk_top_regs.pdf $(OUTDOCS)/msk_top_regs.md + +$(OUTPYTHON)/__init__.py: $(SRCS) + peakrdl python $(SRCS) --async -o $(OUTPYTHON) + +clean: + rm outputs/docs/* + rm outputs/c-header/* + rm -r outputs/python/* + rm outputs/rtl/* \ No newline at end of file diff --git a/rdl/cocotb/desyrdl/addrmap_ch0.py b/rdl/cocotb/desyrdl/addrmap_ch0.py deleted file mode 100644 index 300f4d6..0000000 --- a/rdl/cocotb/desyrdl/addrmap_ch0.py +++ /dev/null @@ -1,117 +0,0 @@ - -import numpy as np -import logging - -logging.basicConfig(level=logging.NOTSET) -logger = logging.getLogger() -logger.setLevel(logging.INFO) - - - -class AddrmapItem (): - def __init__(self, name, bus, address, size, bits, fixp, signed, access): - self.name = name - self.bus = bus - self.address = address - self.size = size - self.bits = bits - self.fixp = fixp - self.access = access - self.scaling = 1; - if fixp == "IEEE754": - self.dtype = np.float32 - elif fixp == 0 and signed == 0: - self.dtype = np.uint32 - elif fixp == 0 and signed == 1: - self.dtype = np.int32 - else: - self.scaling = 1/pow(2, fixp) - self.dtype = np.float32 - - async def read(self, count, offset): - data = await self.bus.read_dwords(self.address+offset*4, count) - return np.array(data * self.scaling, dtype=self.dtype) - - async def read_raw(self, count, offset): - data = await self.bus.read_dwords(self.address+offset*4, count) - return np.array(data, dtype=np.uint32) - - async def write(self, value, offset): - val_np = np.array(value) - if val_np.size > 1: - data = np.uint32(np.round(val_np / self.scaling)).tolist() - else: - data = [] - data.append(np.uint32(np.round(val_np / self.scaling)).tolist()) - await self.bus.write_dwords(self.address+offset*4, data) - - async def write_raw(self, value, offset): - val_np = np.array(value) - if val_np.size > 1: - data = np.uint32(np.round(val_np)).tolist() - else: - data = [] - data.append(np.uint32(np.round(val_np)).tolist()) - await self.bus.write_dwords(self.address+offset*4, data) - -class Addrmap: - def __init__(self, bus): - self.addrmap ={} - self.addrmap['msk_top_regs.Hash_ID_Low'] = AddrmapItem("msk_top_regs.Hash_ID_Low", bus, 0, 4, 32, 0, 0, "RO") - self.addrmap['msk_top_regs.Hash_ID_High'] = AddrmapItem("msk_top_regs.Hash_ID_High", bus, 4, 4, 32, 0, 0, "RO") - self.addrmap['msk_top_regs.MSK_Init'] = AddrmapItem("msk_top_regs.MSK_Init", bus, 8, 4, 3, 0, 0, "RW") - self.addrmap['msk_top_regs.MSK_Control'] = AddrmapItem("msk_top_regs.MSK_Control", bus, 12, 4, 5, 0, 0, "RW") - self.addrmap['msk_top_regs.MSK_Status'] = AddrmapItem("msk_top_regs.MSK_Status", bus, 16, 4, 4, 0, 0, "RO") - self.addrmap['msk_top_regs.Tx_Bit_Count'] = AddrmapItem("msk_top_regs.Tx_Bit_Count", bus, 20, 4, 32, 0, 0, "RO") - self.addrmap['msk_top_regs.Tx_Enable_Count'] = AddrmapItem("msk_top_regs.Tx_Enable_Count", bus, 24, 4, 32, 0, 0, "RO") - self.addrmap['msk_top_regs.Fb_FreqWord'] = AddrmapItem("msk_top_regs.Fb_FreqWord", bus, 28, 4, 32, 0, 0, "RW") - self.addrmap['msk_top_regs.TX_F1_FreqWord'] = AddrmapItem("msk_top_regs.TX_F1_FreqWord", bus, 32, 4, 32, 0, 0, "RW") - self.addrmap['msk_top_regs.TX_F2_FreqWord'] = AddrmapItem("msk_top_regs.TX_F2_FreqWord", bus, 36, 4, 32, 0, 0, "RW") - self.addrmap['msk_top_regs.RX_F1_FreqWord'] = AddrmapItem("msk_top_regs.RX_F1_FreqWord", bus, 40, 4, 32, 0, 0, "RW") - self.addrmap['msk_top_regs.RX_F2_FreqWord'] = AddrmapItem("msk_top_regs.RX_F2_FreqWord", bus, 44, 4, 32, 0, 0, "RW") - self.addrmap['msk_top_regs.LPF_Config_0'] = AddrmapItem("msk_top_regs.LPF_Config_0", bus, 48, 4, 32, 0, 0, "RW") - self.addrmap['msk_top_regs.LPF_Config_1'] = AddrmapItem("msk_top_regs.LPF_Config_1", bus, 52, 4, 32, 0, 0, "RW") - self.addrmap['msk_top_regs.Tx_Data_Width'] = AddrmapItem("msk_top_regs.Tx_Data_Width", bus, 56, 4, 8, 0, 0, "RW") - self.addrmap['msk_top_regs.Rx_Data_Width'] = AddrmapItem("msk_top_regs.Rx_Data_Width", bus, 60, 4, 8, 0, 0, "RW") - self.addrmap['msk_top_regs.PRBS_Control'] = AddrmapItem("msk_top_regs.PRBS_Control", bus, 64, 4, 32, 0, 0, "RW") - self.addrmap['msk_top_regs.PRBS_Initial_State'] = AddrmapItem("msk_top_regs.PRBS_Initial_State", bus, 68, 4, 32, 0, 0, "RW") - self.addrmap['msk_top_regs.PRBS_Polynomial'] = AddrmapItem("msk_top_regs.PRBS_Polynomial", bus, 72, 4, 32, 0, 0, "RW") - self.addrmap['msk_top_regs.PRBS_Error_Mask'] = AddrmapItem("msk_top_regs.PRBS_Error_Mask", bus, 76, 4, 32, 0, 0, "RW") - self.addrmap['msk_top_regs.PRBS_Bit_Count'] = AddrmapItem("msk_top_regs.PRBS_Bit_Count", bus, 80, 4, 32, 0, 0, "RO") - self.addrmap['msk_top_regs.PRBS_Error_Count'] = AddrmapItem("msk_top_regs.PRBS_Error_Count", bus, 84, 4, 32, 0, 0, "RO") - self.addrmap['msk_top_regs.LPF_Accum_F1'] = AddrmapItem("msk_top_regs.LPF_Accum_F1", bus, 88, 4, 32, 0, 0, "RO") - self.addrmap['msk_top_regs.LPF_Accum_F2'] = AddrmapItem("msk_top_regs.LPF_Accum_F2", bus, 92, 4, 32, 0, 0, "RO") - self.addrmap['msk_top_regs.axis_xfer_count'] = AddrmapItem("msk_top_regs.axis_xfer_count", bus, 96, 4, 32, 0, 0, "RO") - self.addrmap['msk_top_regs.Rx_Sample_Discard'] = AddrmapItem("msk_top_regs.Rx_Sample_Discard", bus, 100, 4, 16, 0, 0, "RW") - self.addrmap['msk_top_regs.LPF_Config_2'] = AddrmapItem("msk_top_regs.LPF_Config_2", bus, 104, 4, 32, 0, 0, "RW") - self.addrmap['msk_top_regs.f1_nco_adjust'] = AddrmapItem("msk_top_regs.f1_nco_adjust", bus, 108, 4, 32, 0, 0, "RO") - self.addrmap['msk_top_regs.f2_nco_adjust'] = AddrmapItem("msk_top_regs.f2_nco_adjust", bus, 112, 4, 32, 0, 0, "RO") - self.addrmap['msk_top_regs.f1_error'] = AddrmapItem("msk_top_regs.f1_error", bus, 116, 4, 32, 0, 0, "RO") - self.addrmap['msk_top_regs.f2_error'] = AddrmapItem("msk_top_regs.f2_error", bus, 120, 4, 32, 0, 0, "RO") - self.addrmap['msk_top_regs.Tx_Sync_Ctrl'] = AddrmapItem("msk_top_regs.Tx_Sync_Ctrl", bus, 124, 4, 4, 0, 0, "RW") - self.addrmap['msk_top_regs.Tx_Sync_Cnt'] = AddrmapItem("msk_top_regs.Tx_Sync_Cnt", bus, 128, 4, 24, 0, 0, "RW") - self.addrmap['msk_top_regs.lowpass_ema_alpha1'] = AddrmapItem("msk_top_regs.lowpass_ema_alpha1", bus, 132, 4, 18, 0, 0, "RW") - self.addrmap['msk_top_regs.lowpass_ema_alpha2'] = AddrmapItem("msk_top_regs.lowpass_ema_alpha2", bus, 136, 4, 18, 0, 0, "RW") - self.addrmap['msk_top_regs.rx_power'] = AddrmapItem("msk_top_regs.rx_power", bus, 140, 4, 23, 0, 0, "RO") - - def get_path(self, module, name): - path = module + "." + name - if path not in self.addrmap: - msg = f"Cannot find `{path}` in register dict" - logger.error(msg) - assert False - return path - - async def read(self, module, name, count=1, offset=0): - path = self.get_path(module, name) - return await self.addrmap[path].read(count, offset) - - async def write(self, module, name, value, offset=0): - path = self.get_path(module, name) - return await self.addrmap[path].write(value, offset) - async def read_raw(self, module, name, count=1, offset=0): - path = self.get_path(module, name) - return await self.addrmap[path].read_raw(count, offset) - async def write_raw(self, module, name, value, offset=0): - path = self.get_path(module, name) - return await self.addrmap[path].write_raw(value, offset) \ No newline at end of file diff --git a/rdl/msk_top_regs.h b/rdl/msk_top_regs.h deleted file mode 100644 index 1579eaf..0000000 --- a/rdl/msk_top_regs.h +++ /dev/null @@ -1,369 +0,0 @@ -// Generated by PeakRDL-cheader - A free and open-source header generator -// https://github.com/SystemRDL/PeakRDL-cheader - -#ifndef MSK_TOP_REGS_H -#define MSK_TOP_REGS_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -// Reg - msk_hash_lo -#define MSK_HASH_LO__HASH_ID_LO_bm 0xffffffff -#define MSK_HASH_LO__HASH_ID_LO_bp 0 -#define MSK_HASH_LO__HASH_ID_LO_bw 32 -#define MSK_HASH_LO__HASH_ID_LO_reset 0xaaaa5555 - -// Reg - msk_hash_hi -#define MSK_HASH_HI__HASH_ID_HI_bm 0xffffffff -#define MSK_HASH_HI__HASH_ID_HI_bp 0 -#define MSK_HASH_HI__HASH_ID_HI_bw 32 -#define MSK_HASH_HI__HASH_ID_HI_reset 0x5555aaaa - -// Reg - msk_init -#define MSK_INIT__TXRXINIT_bm 0x1 -#define MSK_INIT__TXRXINIT_bp 0 -#define MSK_INIT__TXRXINIT_bw 1 -#define MSK_INIT__TXRXINIT_reset 0x1 -#define MSK_INIT__TXINIT_bm 0x2 -#define MSK_INIT__TXINIT_bp 1 -#define MSK_INIT__TXINIT_bw 1 -#define MSK_INIT__TXINIT_reset 0x1 -#define MSK_INIT__RXINIT_bm 0x4 -#define MSK_INIT__RXINIT_bp 2 -#define MSK_INIT__RXINIT_bw 1 -#define MSK_INIT__RXINIT_reset 0x1 - -// Reg - msk_ctrl -#define MSK_CTRL__PTT_bm 0x1 -#define MSK_CTRL__PTT_bp 0 -#define MSK_CTRL__PTT_bw 1 -#define MSK_CTRL__PTT_reset 0x0 -#define MSK_CTRL__LOOPBACK_ENA_bm 0x2 -#define MSK_CTRL__LOOPBACK_ENA_bp 1 -#define MSK_CTRL__LOOPBACK_ENA_bw 1 -#define MSK_CTRL__LOOPBACK_ENA_reset 0x0 -#define MSK_CTRL__RX_INVERT_bm 0x4 -#define MSK_CTRL__RX_INVERT_bp 2 -#define MSK_CTRL__RX_INVERT_bw 1 -#define MSK_CTRL__RX_INVERT_reset 0x0 -#define MSK_CTRL__CLEAR_COUNTS_bm 0x8 -#define MSK_CTRL__CLEAR_COUNTS_bp 3 -#define MSK_CTRL__CLEAR_COUNTS_bw 1 -#define MSK_CTRL__CLEAR_COUNTS_reset 0x0 -#define MSK_CTRL__DIFF_ENCODER_LOOPBACK_bm 0x10 -#define MSK_CTRL__DIFF_ENCODER_LOOPBACK_bp 4 -#define MSK_CTRL__DIFF_ENCODER_LOOPBACK_bw 1 -#define MSK_CTRL__DIFF_ENCODER_LOOPBACK_reset 0x0 - -// Reg - msk_stat_0 -#define MSK_STAT_0__DEMOD_SYNC_LOCK_bm 0x1 -#define MSK_STAT_0__DEMOD_SYNC_LOCK_bp 0 -#define MSK_STAT_0__DEMOD_SYNC_LOCK_bw 1 -#define MSK_STAT_0__DEMOD_SYNC_LOCK_reset 0x0 -#define MSK_STAT_0__TX_ENABLE_bm 0x2 -#define MSK_STAT_0__TX_ENABLE_bp 1 -#define MSK_STAT_0__TX_ENABLE_bw 1 -#define MSK_STAT_0__TX_ENABLE_reset 0x0 -#define MSK_STAT_0__RX_ENABLE_bm 0x4 -#define MSK_STAT_0__RX_ENABLE_bp 2 -#define MSK_STAT_0__RX_ENABLE_bw 1 -#define MSK_STAT_0__RX_ENABLE_reset 0x0 -#define MSK_STAT_0__TX_AXIS_VALID_bm 0x8 -#define MSK_STAT_0__TX_AXIS_VALID_bp 3 -#define MSK_STAT_0__TX_AXIS_VALID_bw 1 -#define MSK_STAT_0__TX_AXIS_VALID_reset 0x0 - -// Reg - msk_stat_1 -#define MSK_STAT_1__TX_BIT_COUNTER_bm 0xffffffff -#define MSK_STAT_1__TX_BIT_COUNTER_bp 0 -#define MSK_STAT_1__TX_BIT_COUNTER_bw 32 -#define MSK_STAT_1__TX_BIT_COUNTER_reset 0x0 - -// Reg - msk_stat_2 -#define MSK_STAT_2__TX_ENA_COUNTER_bm 0xffffffff -#define MSK_STAT_2__TX_ENA_COUNTER_bp 0 -#define MSK_STAT_2__TX_ENA_COUNTER_bw 32 -#define MSK_STAT_2__TX_ENA_COUNTER_reset 0x0 - -// Reg - config_nco_fw_desc_c4924cc6_name_0c494469 -#define CONFIG_NCO_FW_DESC_C4924CC6_NAME_0C494469__CONFIG_DATA_bm 0xffffffff -#define CONFIG_NCO_FW_DESC_C4924CC6_NAME_0C494469__CONFIG_DATA_bp 0 -#define CONFIG_NCO_FW_DESC_C4924CC6_NAME_0C494469__CONFIG_DATA_bw 32 -#define CONFIG_NCO_FW_DESC_C4924CC6_NAME_0C494469__CONFIG_DATA_reset 0x0 - -// Reg - config_nco_fw_desc_94d7aaf5_name_84dd0c1c -#define CONFIG_NCO_FW_DESC_94D7AAF5_NAME_84DD0C1C__CONFIG_DATA_bm 0xffffffff -#define CONFIG_NCO_FW_DESC_94D7AAF5_NAME_84DD0C1C__CONFIG_DATA_bp 0 -#define CONFIG_NCO_FW_DESC_94D7AAF5_NAME_84DD0C1C__CONFIG_DATA_bw 32 -#define CONFIG_NCO_FW_DESC_94D7AAF5_NAME_84DD0C1C__CONFIG_DATA_reset 0x0 - -// Reg - config_nco_fw_desc_42134a4f_name_d97dbd51 -#define CONFIG_NCO_FW_DESC_42134A4F_NAME_D97DBD51__CONFIG_DATA_bm 0xffffffff -#define CONFIG_NCO_FW_DESC_42134A4F_NAME_D97DBD51__CONFIG_DATA_bp 0 -#define CONFIG_NCO_FW_DESC_42134A4F_NAME_D97DBD51__CONFIG_DATA_bw 32 -#define CONFIG_NCO_FW_DESC_42134A4F_NAME_D97DBD51__CONFIG_DATA_reset 0x0 - -// Reg - config_nco_fw_desc_16fb48c8_name_8d01a20d -#define CONFIG_NCO_FW_DESC_16FB48C8_NAME_8D01A20D__CONFIG_DATA_bm 0xffffffff -#define CONFIG_NCO_FW_DESC_16FB48C8_NAME_8D01A20D__CONFIG_DATA_bp 0 -#define CONFIG_NCO_FW_DESC_16FB48C8_NAME_8D01A20D__CONFIG_DATA_bw 32 -#define CONFIG_NCO_FW_DESC_16FB48C8_NAME_8D01A20D__CONFIG_DATA_reset 0x0 - -// Reg - config_nco_fw_desc_43c0828f_name_bdc60ecf -#define CONFIG_NCO_FW_DESC_43C0828F_NAME_BDC60ECF__CONFIG_DATA_bm 0xffffffff -#define CONFIG_NCO_FW_DESC_43C0828F_NAME_BDC60ECF__CONFIG_DATA_bp 0 -#define CONFIG_NCO_FW_DESC_43C0828F_NAME_BDC60ECF__CONFIG_DATA_bw 32 -#define CONFIG_NCO_FW_DESC_43C0828F_NAME_BDC60ECF__CONFIG_DATA_reset 0x0 - -// Reg - lpf_config_0 -#define LPF_CONFIG_0__LPF_FREEZE_bm 0x1 -#define LPF_CONFIG_0__LPF_FREEZE_bp 0 -#define LPF_CONFIG_0__LPF_FREEZE_bw 1 -#define LPF_CONFIG_0__LPF_FREEZE_reset 0x0 -#define LPF_CONFIG_0__LPF_ZERO_bm 0x2 -#define LPF_CONFIG_0__LPF_ZERO_bp 1 -#define LPF_CONFIG_0__LPF_ZERO_bw 1 -#define LPF_CONFIG_0__LPF_ZERO_reset 0x0 -#define LPF_CONFIG_0__PRBS_RESERVED_bm 0xfc -#define LPF_CONFIG_0__PRBS_RESERVED_bp 2 -#define LPF_CONFIG_0__PRBS_RESERVED_bw 6 -#define LPF_CONFIG_0__PRBS_RESERVED_reset 0x0 -#define LPF_CONFIG_0__LPF_ALPHA_bm 0xffffff00 -#define LPF_CONFIG_0__LPF_ALPHA_bp 8 -#define LPF_CONFIG_0__LPF_ALPHA_bw 24 -#define LPF_CONFIG_0__LPF_ALPHA_reset 0x0 - -// Reg - lpf_config_1 -#define LPF_CONFIG_1__I_GAIN_bm 0xffffff -#define LPF_CONFIG_1__I_GAIN_bp 0 -#define LPF_CONFIG_1__I_GAIN_bw 24 -#define LPF_CONFIG_1__I_GAIN_reset 0x0 -#define LPF_CONFIG_1__I_SHIFT_bm 0xff000000 -#define LPF_CONFIG_1__I_SHIFT_bp 24 -#define LPF_CONFIG_1__I_SHIFT_bw 8 -#define LPF_CONFIG_1__I_SHIFT_reset 0x0 - -// Reg - data_width_desc_58c848dd_name_2fbd8eba -#define DATA_WIDTH_DESC_58C848DD_NAME_2FBD8EBA__DATA_WIDTH_bm 0xff -#define DATA_WIDTH_DESC_58C848DD_NAME_2FBD8EBA__DATA_WIDTH_bp 0 -#define DATA_WIDTH_DESC_58C848DD_NAME_2FBD8EBA__DATA_WIDTH_bw 8 -#define DATA_WIDTH_DESC_58C848DD_NAME_2FBD8EBA__DATA_WIDTH_reset 0x8 - -// Reg - data_width_desc_6097df38_name_4609588b -#define DATA_WIDTH_DESC_6097DF38_NAME_4609588B__DATA_WIDTH_bm 0xff -#define DATA_WIDTH_DESC_6097DF38_NAME_4609588B__DATA_WIDTH_bp 0 -#define DATA_WIDTH_DESC_6097DF38_NAME_4609588B__DATA_WIDTH_bw 8 -#define DATA_WIDTH_DESC_6097DF38_NAME_4609588B__DATA_WIDTH_reset 0x8 - -// Reg - prbs_ctrl -#define PRBS_CTRL__PRBS_SEL_bm 0x1 -#define PRBS_CTRL__PRBS_SEL_bp 0 -#define PRBS_CTRL__PRBS_SEL_bw 1 -#define PRBS_CTRL__PRBS_SEL_reset 0x0 -#define PRBS_CTRL__PRBS_ERROR_INSERT_bm 0x2 -#define PRBS_CTRL__PRBS_ERROR_INSERT_bp 1 -#define PRBS_CTRL__PRBS_ERROR_INSERT_bw 1 -#define PRBS_CTRL__PRBS_ERROR_INSERT_reset 0x0 -#define PRBS_CTRL__PRBS_CLEAR_bm 0x4 -#define PRBS_CTRL__PRBS_CLEAR_bp 2 -#define PRBS_CTRL__PRBS_CLEAR_bw 1 -#define PRBS_CTRL__PRBS_CLEAR_reset 0x0 -#define PRBS_CTRL__PRBS_MANUAL_SYNC_bm 0x8 -#define PRBS_CTRL__PRBS_MANUAL_SYNC_bp 3 -#define PRBS_CTRL__PRBS_MANUAL_SYNC_bw 1 -#define PRBS_CTRL__PRBS_MANUAL_SYNC_reset 0x0 -#define PRBS_CTRL__PRBS_RESERVED_bm 0xfff0 -#define PRBS_CTRL__PRBS_RESERVED_bp 4 -#define PRBS_CTRL__PRBS_RESERVED_bw 12 -#define PRBS_CTRL__PRBS_RESERVED_reset 0x0 -#define PRBS_CTRL__PRBS_SYNC_THRESHOLD_bm 0xffff0000 -#define PRBS_CTRL__PRBS_SYNC_THRESHOLD_bp 16 -#define PRBS_CTRL__PRBS_SYNC_THRESHOLD_bw 16 -#define PRBS_CTRL__PRBS_SYNC_THRESHOLD_reset 0x0 - -// Reg - config_prbs_seed -#define CONFIG_PRBS_SEED__CONFIG_DATA_bm 0xffffffff -#define CONFIG_PRBS_SEED__CONFIG_DATA_bp 0 -#define CONFIG_PRBS_SEED__CONFIG_DATA_bw 32 -#define CONFIG_PRBS_SEED__CONFIG_DATA_reset 0x0 - -// Reg - config_prbs_poly -#define CONFIG_PRBS_POLY__CONFIG_DATA_bm 0xffffffff -#define CONFIG_PRBS_POLY__CONFIG_DATA_bp 0 -#define CONFIG_PRBS_POLY__CONFIG_DATA_bw 32 -#define CONFIG_PRBS_POLY__CONFIG_DATA_reset 0x0 - -// Reg - config_prbs_errmask -#define CONFIG_PRBS_ERRMASK__CONFIG_DATA_bm 0xffffffff -#define CONFIG_PRBS_ERRMASK__CONFIG_DATA_bp 0 -#define CONFIG_PRBS_ERRMASK__CONFIG_DATA_bw 32 -#define CONFIG_PRBS_ERRMASK__CONFIG_DATA_reset 0x0 - -// Reg - stat_32_bits -#define STAT_32_BITS__STATUS_DATA_bm 0xffffffff -#define STAT_32_BITS__STATUS_DATA_bp 0 -#define STAT_32_BITS__STATUS_DATA_bw 32 -#define STAT_32_BITS__STATUS_DATA_reset 0x0 - -// Reg - stat_32_errs -#define STAT_32_ERRS__STATUS_DATA_bm 0xffffffff -#define STAT_32_ERRS__STATUS_DATA_bp 0 -#define STAT_32_ERRS__STATUS_DATA_bw 32 -#define STAT_32_ERRS__STATUS_DATA_reset 0x0 - -// Reg - stat_32_lpf_acc_desc_8cebc7dc_name_f20c6670 -#define STAT_32_LPF_ACC_DESC_8CEBC7DC_NAME_F20C6670__STATUS_DATA_bm 0xffffffff -#define STAT_32_LPF_ACC_DESC_8CEBC7DC_NAME_F20C6670__STATUS_DATA_bp 0 -#define STAT_32_LPF_ACC_DESC_8CEBC7DC_NAME_F20C6670__STATUS_DATA_bw 32 -#define STAT_32_LPF_ACC_DESC_8CEBC7DC_NAME_F20C6670__STATUS_DATA_reset 0x0 - -// Reg - stat_32_lpf_acc_desc_dea6bd99_name_758fd0ce -#define STAT_32_LPF_ACC_DESC_DEA6BD99_NAME_758FD0CE__STATUS_DATA_bm 0xffffffff -#define STAT_32_LPF_ACC_DESC_DEA6BD99_NAME_758FD0CE__STATUS_DATA_bp 0 -#define STAT_32_LPF_ACC_DESC_DEA6BD99_NAME_758FD0CE__STATUS_DATA_bw 32 -#define STAT_32_LPF_ACC_DESC_DEA6BD99_NAME_758FD0CE__STATUS_DATA_reset 0x0 - -// Reg - msk_stat_3 -#define MSK_STAT_3__XFER_COUNT_bm 0xffffffff -#define MSK_STAT_3__XFER_COUNT_bp 0 -#define MSK_STAT_3__XFER_COUNT_bw 32 -#define MSK_STAT_3__XFER_COUNT_reset 0x0 - -// Reg - rx_sample_discard -#define RX_SAMPLE_DISCARD__RX_SAMPLE_DISCARD_bm 0xff -#define RX_SAMPLE_DISCARD__RX_SAMPLE_DISCARD_bp 0 -#define RX_SAMPLE_DISCARD__RX_SAMPLE_DISCARD_bw 8 -#define RX_SAMPLE_DISCARD__RX_SAMPLE_DISCARD_reset 0x0 -#define RX_SAMPLE_DISCARD__RX_NCO_DISCARD_bm 0xff00 -#define RX_SAMPLE_DISCARD__RX_NCO_DISCARD_bp 8 -#define RX_SAMPLE_DISCARD__RX_NCO_DISCARD_bw 8 -#define RX_SAMPLE_DISCARD__RX_NCO_DISCARD_reset 0x0 - -// Reg - lpf_config_2 -#define LPF_CONFIG_2__P_GAIN_bm 0xffffff -#define LPF_CONFIG_2__P_GAIN_bp 0 -#define LPF_CONFIG_2__P_GAIN_bw 24 -#define LPF_CONFIG_2__P_GAIN_reset 0x0 -#define LPF_CONFIG_2__P_SHIFT_bm 0xff000000 -#define LPF_CONFIG_2__P_SHIFT_bp 24 -#define LPF_CONFIG_2__P_SHIFT_bw 8 -#define LPF_CONFIG_2__P_SHIFT_reset 0x0 - -// Reg - observation_data_data_0c017ef4_desc_64ff3689_name_d8ad3b25 -#define OBSERVATION_DATA_DATA_0C017EF4_DESC_64FF3689_NAME_D8AD3B25__DATA_bm 0xffffffff -#define OBSERVATION_DATA_DATA_0C017EF4_DESC_64FF3689_NAME_D8AD3B25__DATA_bp 0 -#define OBSERVATION_DATA_DATA_0C017EF4_DESC_64FF3689_NAME_D8AD3B25__DATA_bw 32 -#define OBSERVATION_DATA_DATA_0C017EF4_DESC_64FF3689_NAME_D8AD3B25__DATA_reset 0x0 - -// Reg - observation_data_data_0515efaa_desc_ebde6d39_name_2c154788 -#define OBSERVATION_DATA_DATA_0515EFAA_DESC_EBDE6D39_NAME_2C154788__DATA_bm 0xffffffff -#define OBSERVATION_DATA_DATA_0515EFAA_DESC_EBDE6D39_NAME_2C154788__DATA_bp 0 -#define OBSERVATION_DATA_DATA_0515EFAA_DESC_EBDE6D39_NAME_2C154788__DATA_bw 32 -#define OBSERVATION_DATA_DATA_0515EFAA_DESC_EBDE6D39_NAME_2C154788__DATA_reset 0x0 - -// Reg - observation_data_data_25a21249_desc_417e1c96_name_3b640507 -#define OBSERVATION_DATA_DATA_25A21249_DESC_417E1C96_NAME_3B640507__DATA_bm 0xffffffff -#define OBSERVATION_DATA_DATA_25A21249_DESC_417E1C96_NAME_3B640507__DATA_bp 0 -#define OBSERVATION_DATA_DATA_25A21249_DESC_417E1C96_NAME_3B640507__DATA_bw 32 -#define OBSERVATION_DATA_DATA_25A21249_DESC_417E1C96_NAME_3B640507__DATA_reset 0x0 - -// Reg - observation_data_data_272a00b6_desc_70869502_name_3de9a0d3 -#define OBSERVATION_DATA_DATA_272A00B6_DESC_70869502_NAME_3DE9A0D3__DATA_bm 0xffffffff -#define OBSERVATION_DATA_DATA_272A00B6_DESC_70869502_NAME_3DE9A0D3__DATA_bp 0 -#define OBSERVATION_DATA_DATA_272A00B6_DESC_70869502_NAME_3DE9A0D3__DATA_bw 32 -#define OBSERVATION_DATA_DATA_272A00B6_DESC_70869502_NAME_3DE9A0D3__DATA_reset 0x0 - -// Reg - tx_sync_ctrl -#define TX_SYNC_CTRL__TX_SYNC_ENA_bm 0x1 -#define TX_SYNC_CTRL__TX_SYNC_ENA_bp 0 -#define TX_SYNC_CTRL__TX_SYNC_ENA_bw 1 -#define TX_SYNC_CTRL__TX_SYNC_ENA_reset 0x0 -#define TX_SYNC_CTRL__TX_SYNC_FORCE_bm 0x2 -#define TX_SYNC_CTRL__TX_SYNC_FORCE_bp 1 -#define TX_SYNC_CTRL__TX_SYNC_FORCE_bw 1 -#define TX_SYNC_CTRL__TX_SYNC_FORCE_reset 0x0 -#define TX_SYNC_CTRL__TX_SYNC_F1_bm 0x4 -#define TX_SYNC_CTRL__TX_SYNC_F1_bp 2 -#define TX_SYNC_CTRL__TX_SYNC_F1_bw 1 -#define TX_SYNC_CTRL__TX_SYNC_F1_reset 0x0 -#define TX_SYNC_CTRL__TX_SYNC_F2_bm 0x8 -#define TX_SYNC_CTRL__TX_SYNC_F2_bp 3 -#define TX_SYNC_CTRL__TX_SYNC_F2_bw 1 -#define TX_SYNC_CTRL__TX_SYNC_F2_reset 0x0 - -// Reg - tx_sync_cnt -#define TX_SYNC_CNT__TX_SYNC_CNT_bm 0xffffff -#define TX_SYNC_CNT__TX_SYNC_CNT_bp 0 -#define TX_SYNC_CNT__TX_SYNC_CNT_bw 24 -#define TX_SYNC_CNT__TX_SYNC_CNT_reset 0x0 - -// Reg - lowpass_ema_alpha -#define LOWPASS_EMA_ALPHA__ALPHA_bm 0x3ffff -#define LOWPASS_EMA_ALPHA__ALPHA_bp 0 -#define LOWPASS_EMA_ALPHA__ALPHA_bw 18 -#define LOWPASS_EMA_ALPHA__ALPHA_reset 0x0 - -// Reg - rx_power -#define RX_POWER__RX_POWER_bm 0x7fffff -#define RX_POWER__RX_POWER_bp 0 -#define RX_POWER__RX_POWER_bw 23 -#define RX_POWER__RX_POWER_reset 0x0 - -// Addrmap - msk_top_regs -typedef struct __attribute__ ((__packed__)) { - uint32_t Hash_ID_Low; - uint32_t Hash_ID_High; - uint32_t MSK_Init; - uint32_t MSK_Control; - uint32_t MSK_Status; - uint32_t Tx_Bit_Count; - uint32_t Tx_Enable_Count; - uint32_t Fb_FreqWord; - uint32_t TX_F1_FreqWord; - uint32_t TX_F2_FreqWord; - uint32_t RX_F1_FreqWord; - uint32_t RX_F2_FreqWord; - uint32_t LPF_Config_0; - uint32_t LPF_Config_1; - uint32_t Tx_Data_Width; - uint32_t Rx_Data_Width; - uint32_t PRBS_Control; - uint32_t PRBS_Initial_State; - uint32_t PRBS_Polynomial; - uint32_t PRBS_Error_Mask; - uint32_t PRBS_Bit_Count; - uint32_t PRBS_Error_Count; - uint32_t LPF_Accum_F1; - uint32_t LPF_Accum_F2; - uint32_t axis_xfer_count; - uint32_t Rx_Sample_Discard; - uint32_t LPF_Config_2; - uint32_t f1_nco_adjust; - uint32_t f2_nco_adjust; - uint32_t f1_error; - uint32_t f2_error; - uint32_t Tx_Sync_Ctrl; - uint32_t Tx_Sync_Cnt; - uint32_t lowpass_ema_alpha1; - uint32_t lowpass_ema_alpha2; - uint32_t rx_power; -} msk_top_regs_t; - -// Addrmap - Pluto_MSK_Modem -typedef struct __attribute__ ((__packed__)) { - uint8_t RESERVED_0_43bfffff[0x43c00000]; - msk_top_regs_t pluto_msk_regs; -} Pluto_MSK_Modem_t; - - -static_assert(sizeof(Pluto_MSK_Modem_t) == 0x43c00090, "Packing error"); - -#ifdef __cplusplus -} -#endif - -#endif /* MSK_TOP_REGS_H */ diff --git a/rdl/msk_top_regs.pl b/rdl/msk_top_regs.pl deleted file mode 100755 index 5d951b3..0000000 --- a/rdl/msk_top_regs.pl +++ /dev/null @@ -1,40 +0,0 @@ -#! /usr/bin/perl - -open(FILE, "msk_top_regs.rdl"); - -while() { - - chomp; - - s/}; \/\/ //; - - $line = "$_\n"; - - if (/^\/\/.*desyrdl/) { - $line = substr $line, 2; - } - - if (/name/) { $line = ""; } - - if (/desc/) { - $line = ""; - $eoc = 1; - } - - if (/;$/) { - if ($eoc == 1) { - $eoc = 0; - $line = ""; - } - } else { - if ($eoc == 1) { - $line = ""; - } - } - - if (/Pluto_MSK_Modem/) { last; } - - print($line); - -} -close FILE; diff --git a/rdl/msk_top_regs.rdl b/rdl/msk_top_regs.rdl deleted file mode 100644 index ebe3ec0..0000000 --- a/rdl/msk_top_regs.rdl +++ /dev/null @@ -1,408 +0,0 @@ -reg msk_hash_lo { - name = "Pluto MSK FPGA Hash ID - Lower 32-bits"; - regwidth = 32; - accesswidth = 32; - field { sw = r; hw = na; } hash_id_lo[31:0] = 0xAAAA5555; - hash_id_lo->desc = "Lower 32-bits of Pluto MSK FPGA Hash ID"; - hash_id_lo->name = "Hash ID Lower 32-bits"; -}; - -reg msk_hash_hi { - name = "Pluto MSK FPGA Hash ID - Upper 32-bits"; - regwidth = 32; - accesswidth = 32; - field { sw = r; hw = na; } hash_id_hi[31:0] = 0x5555AAAA; - hash_id_hi->desc = "Upper 32-bits of Pluto MSK FPGA Hash ID"; - hash_id_hi->name = "Hash ID Upper 32-bits"; -}; - -reg msk_init { - name = "MSK Modem Control 0"; - regwidth = 32; - desc = "Synchronous initialization of MSK Modem functions, does not affect configuration registers."; - field { sw = rw; hw=r; } txrxinit = 1; - txrxinit->desc = "0 -> Normal modem operation - 1 -> Initialize Tx and Rx"; - txrxinit->name = "Tx/Rx Init Enable"; - field { sw = rw; hw=r; } txinit = 1; - txinit->desc = "0 -> Normal Tx operation - 1 -> Initialize Tx"; - txinit->name = "Tx Init Enable"; - field { sw = rw; hw=r; } rxinit = 1; - rxinit->desc = "0 -> Normal Rx operation - 1 -> Initialize Rx"; - rxinit->name = "Rx Init Enable"; -}; - -reg msk_ctrl { - name = "MSK Modem Control 1"; - regwidth = 32; - desc = "MSK Modem Configuration and Control"; - field { sw = rw; hw = r; } ptt = 0; - ptt->desc = "0 -> PTT Disabled - 1 -> PTT Enabled"; - ptt->name = "Push-to-Talk Enable"; - field { sw = rw; hw = r; } loopback_ena = 0; - loopback_ena->desc = "0 -> Modem loopback disabled - 1 -> Modem loopback enabled"; - loopback_ena->name = "Modem Loopback Enable"; - field { sw = rw; hw = r; } rx_invert = 0; - rx_invert->desc = "0 -> Rx data normal - 1 -> Rx data inverted"; - rx_invert->name = "Rx Data Invert Enable"; - field { sw = rw; hw = r; singlepulse = true; } clear_counts = 0; - clear_counts->desc = "Clear Tx Bit Counter and Tx Enable Counter"; - clear_counts->name = "Clear Status Counters"; - field { sw = rw; hw = r; } diff_encoder_loopback = 0; - diff_encoder_loopback->desc = "0 -> Differential Encoder -> Decoder loopback disabled - 1 -> Differential Encoder -> Decoder loopback enabled"; - diff_encoder_loopback->name = "Differential Encoder -> Decoder Loopback Enable"; -}; - -reg msk_stat_0 { - name = "MSK Modem Status 0"; - desc = "Modem status bits"; - regwidth = 32; - field { sw = r; hw = w; } demod_sync_lock=0; - demod_sync_lock->desc = "Demodulator Sync Status - not currently implemented"; - demod_sync_lock->name = "Demodulator Sync Status"; - field { sw = r; hw = w; } tx_enable=0; - tx_enable->name = "AD9363 DAC Interface Tx Enable Input Active"; - tx_enable->desc = "1 -> Data to DAC Enabled - 0 -> Data to DAC Disabled"; - field { sw = r; hw = w; } rx_enable=0; - rx_enable->name = "AD9363 ADC Interface Rx Enable Input Active"; - rx_enable->desc = "1 -> Data from ADC Enabled - 0 -> Data from ADC Disabled"; - field { sw = r; hw = w; } tx_axis_valid=0; - tx_axis_valid->name = "Tx S_AXIS_VALID"; - tx_axis_valid->desc = "1 -> S_AXIS_VALID Enabled - 0 -> S_AXIS_VALID Disabled"; -}; - -reg msk_stat_1 { - name = "MSK Modem Status 1"; - desc = "Modem status data"; - regwidth = 32; - field { sw = r; hw = w; } tx_bit_counter[31:0] = 0; - tx_bit_counter->desc = "Count of data requests made by modem"; - tx_bit_counter->name = "Tx Bit Count"; -}; - -reg msk_stat_2 { - name = "MSK Modem Status 2"; - desc = "Modem status data"; - regwidth = 32; - field { sw = r; hw = w; } tx_ena_counter[31:0] = 0; - tx_ena_counter->desc = "Number of clocks on which Tx Enable is active"; - tx_ena_counter->name = "Tx Enable Count"; -}; - -reg config_nco_fw { - regwidth = 32; - field { sw = rw; hw = r; } config_data[31:0] = 0; - config_data->name = "Frequency Control Word"; - config_data->desc = "Sets the center frequency of the NCO as FW = Fn * 2^32/Fs, where Fn is the desired NCO frequency, and Fs is the NCO sample rate"; -}; - -reg rx_sample_discard { - name = "Rx Sample Discard"; - desc = "Configure samples discard operation for demodulator"; - regwidth = 32; - field { sw = rw; hw = r; } rx_sample_discard[7:0] = 0; - rx_sample_discard->desc = "Number of Rx samples to discard"; - rx_sample_discard->name = "Rx Sample Discard Value"; - field { sw = rw; hw = r; } rx_nco_discard[15:8] = 0; - rx_nco_discard->desc = "Number of NCO samples to discard"; - rx_nco_discard->name = "Rx NCO Sample Discard Value"; -}; - -reg lpf_config_0 { - name = "PI Controller Configuration and Low-pass Filter Configuration"; - desc = "Configure PI controller and low-pass filter"; - regwidth = 32; - field { sw = rw; hw = r; } lpf_freeze = 0; - lpf_freeze->name = "Freeze the accumulator's current value"; - lpf_freeze->desc = "0 -> Normal operation - 1 -> Freeze current value"; - field { sw = rw; hw = r; } lpf_zero = 0; - lpf_zero->name = "Hold the PI Accumulator at zero"; - lpf_zero->desc = "0 -> Normal operation - 1 -> Zero and hold accumulator"; - field { sw = w; hw = r; } prbs_reserved[7:2] = 0; - field { sw = rw; hw = r; } lpf_alpha[31:8] = 0; - lpf_alpha->name = "Lowpass IIR filter alpha"; - lpf_alpha->desc = "Value controls the filter rolloff"; -}; - -reg lpf_config_1 { - name = "PI Controller Configuration Configuration Register 1"; - desc = "Configures PI Controller I-gain and divisor"; - regwidth = 32; - field { sw = rw; hw = r; } i_gain[23:0] = 0; - i_gain->name = "Integral Gain Value"; - i_gain->desc = "Value m of 0-16,777,215 sets the integral multiplier"; - field { sw = rw; hw = r; } i_shift[31:24] = 0; - i_shift->name = "Integral Gain Bit Shift"; - i_shift->desc = "Value n of 0-32 sets the integral divisor as 2^-n"; -}; - -reg lpf_config_2 { - name = "PI Controller Configuration Configuration Register 2"; - desc = "Configures PI Controller I-gain and divisor"; - regwidth = 32; - field { sw = rw; hw = r; } p_gain[23:0] = 0; - p_gain->name = "Proportional Gain Value"; - p_gain->desc = "Value m of 0-16,777,215 sets the proportional multiplier"; - field { sw = rw; hw = r; } p_shift[31:24] = 0; - p_shift->name = "Proportional Gain Bit Shift"; - p_shift->desc = "Value n of 0-32 sets the proportional divisor as 2^-n"; -}; - -reg data_width { - regwidth = 32; - field { sw = rw; hw = r; } data_width[7:0] = 8; - data_width->name = "Modem input/output data width"; - data_width->desc = "Set the data width of the modem input/output"; -}; - -reg prbs_ctrl { - name = "PRBS Control 0"; - desc = "Configures operation of the PRBS Generator and Monitor"; - regwidth = 32; - field { sw = rw; hw = r; } prbs_sel = 0; - prbs_sel->name = "PRBS Data Select"; - prbs_sel->desc = "0 -> Select Normal Tx Data - 1 -> Select PRBS Tx Data"; - field { sw = w; hw = r; singlepulse = true; } prbs_error_insert = 0; - prbs_error_insert->name = "PRBS Error Insert"; - prbs_error_insert->desc = "0 -> 1 : Insert bit error in Tx data (both Normal and PRBS) - 1 -> 0 : Insert bit error in Tx data (both Normal and PRBS)"; - field { sw = w; hw = r; singlepulse = true; } prbs_clear = 0; - prbs_clear->name = "PRBS Clear Counters"; - prbs_clear->desc = "0 -> 1 : Clear PRBS Counters - 1 -> 0 : Clear PRBS Counters"; - field { sw = w; hw = r; singlepulse = true; } prbs_manual_sync = 0; - prbs_manual_sync->name = "PRBS Manual Sync"; - prbs_manual_sync->desc = "0 -> 1 : Synchronize PRBS monitor - 1 -> 0 : Synchronize PRBS monitor"; - field { sw = w; hw = r; } prbs_reserved[15:4] = 0; - field { sw = w; hw = r; } prbs_sync_threshold[31:16] = 0; - prbs_sync_threshold->name = "PRBS Auto Sync Threshold"; - prbs_sync_threshold->desc = "0 : Auto Sync Disabled - N > 0 : Auto sync after N errors"; -}; - -reg config_prbs_seed { - name = "PRBS Control 1"; - desc = "PRBS Initial State"; - regwidth = 32; - field { sw = rw; hw = r; } config_data[31:0] = 0; - config_data->name = "PRBS Seed"; - config_data->desc = "Sets the starting value of the PRBS generator"; -}; - -reg config_prbs_poly { - name = "PRBS Control 2"; - desc = "PRBS Polynomial"; - regwidth = 32; - field { sw = rw; hw = r; } config_data[31:0] = 0; - config_data->name = "PRBS Polynomial"; - config_data->desc = "Bit positions set to '1' indicate polynomial feedback positions"; -}; - -reg config_prbs_errmask { - name = "PRBS Control 3"; - desc = "PRBS Error Mask"; - regwidth = 32; - field { sw = rw; hw = r; } config_data[31:0] = 0; - config_data->name = "PRBS Error Mask"; - config_data->desc = "Bit positions set to '1' indicate bits that are inverted when a bit error is inserted"; -}; - -reg stat_32_bits { - name = "PRBS Status 0"; - desc = "PRBS Bits Received"; - regwidth = 32; - field { sw = r; hw = w; } status_data[31:0] = 0; - status_data->name = "PRBS Bits Received"; - status_data->desc = "Number of bits received by the PRBS monitor since last - BER can be calculated as the ratio of received bits to errored-bits"; -}; - -reg stat_32_errs { - name = "PRBS Status 1"; - desc = "PRBS Bit Errors"; - regwidth = 32; - field { sw = r; hw = w; } status_data[31:0] = 0; - status_data->name = "PRBS Bit Errors"; - status_data->desc = "Number of errored-bits received by the PRBS monitor since last sync - BER can be calculated as the ratio of received bits to errored-bits"; -}; - -reg stat_32_lpf_acc { - regwidth = 32; - field { sw = r; hw = w; } status_data[31:0] = 0; - status_data->name = "PI Controller Accumulator Value"; - status_data->desc = "PI Controller Accumulator Value"; -}; - -reg msk_stat_3 { - name = "MSK Modem Status 3"; - desc = "Modem status data"; - regwidth = 32; - field { sw = r; hw = w; } xfer_count[31:0] = 0; - xfer_count->desc = "Number completed S_AXIS transfers"; - xfer_count->name = "S_AXIS Transfers"; -}; - -reg tx_sync_ctrl { - name = "Transmitter Sync Control"; - desc = "Provides control bits for generation of transmitter synchronization patterns"; - regwidth = 32; - field { sw = rw; hw = r; } tx_sync_ena = 0; - tx_sync_ena->name = "Tx Sync Enable"; - tx_sync_ena->desc = "0 -> Disable sync transmission - 1 -> Enable sync transmission when PTT is asserted"; - field { sw = rw; hw = r; } tx_sync_force = 0; - tx_sync_force->name = "Tx Sync Force"; - tx_sync_force->desc = "0 : Normal operation) - 1 : Transmit synchronization pattern)"; - field { sw = rw; hw = r; } tx_sync_f1 = 0; - tx_sync_f1->name = "Tx F1 Sync Enable"; - tx_sync_f1->desc = "Enables/Disables transmission of F1 tone for receiver synchronization - 0 : F1 tone transmission disabled - 1 : F1 tone transmission enabled - Both F1 and F2 can be enabled at the same time"; - field { sw = rw; hw = r; } tx_sync_f2 = 0; - tx_sync_f2->name = "Tx F2 Sync Enable"; - tx_sync_f2->desc = "Enables/Disables transmission of F2 tone for receiver synchronization - 0 : F2 tone transmission disabled - 1 : F2 tone transmission enabled - Both F1 and F2 can be enabled at the same time"; -}; - -reg tx_sync_cnt { - name = "Transmitter Sync Duration"; - desc = "Sets the duration of the synchronization tones when enabled"; - regwidth = 32; - field { sw = rw; hw = r; } tx_sync_cnt[23:0] = 0; - tx_sync_cnt->name = "Tx sync duration"; - tx_sync_cnt->desc = "Value from 0x00_0000 to 0xFF_FFFF. This value represents the number bit-times the synchronization signal should be sent after PTT is asserted."; -}; - -reg lowpass_ema_alpha { - name = "Exponential Moving Average Alpha"; - desc = "Sets the alpha for the EMA"; - regwidth = 32; - field { sw = rw; hw = r; } alpha[17:0] = 0; - alpha->name = "EMA alpha"; - alpha->desc = "Value from 0x0_0000 to 0x3_FFFF represent the EMA alpha"; -}; - -reg rx_power { - name = "Receive Power"; - desc = "Receive power computed from I/Q ssamples"; - regwidth = 32; - field { sw = r; hw = w; } rx_power[22:0] = 0; - rx_power->name = "Receive Power"; - rx_power->desc = "Value that represent the RMS power of the incoming I;"; -}; - -field data32 { - fieldwidth = 32; - sw = r; - hw = w; -}; - -reg observation_data { - regwidth = 32; - data32 data[31:0] = 0; -}; - -addrmap msk_top_regs { - name="Pluto MSK Registers"; - desc="MSK Modem Configuration and Status Registers"; - lsb0; - default accesswidth=32; - addressing=compact; - -// desyrdl_interface = "AXI4L"; -// desyrdl_access_channel = 0; - - msk_hash_lo Hash_ID_Low; - msk_hash_hi Hash_ID_High; - msk_init MSK_Init; - msk_ctrl MSK_Control; - msk_stat_0 MSK_Status; - msk_stat_1 Tx_Bit_Count; - msk_stat_2 Tx_Enable_Count; - config_nco_fw Fb_FreqWord; - Fb_FreqWord->desc = "Set Modem Data Rate"; - Fb_FreqWord->name = "Bitrate NCO Frequency Control Word"; - config_nco_fw TX_F1_FreqWord; - TX_F1_FreqWord->desc = "Set Modulator F1 Frequency"; - TX_F1_FreqWord->name = "Tx F1 NCO Frequency Control Word"; - config_nco_fw TX_F2_FreqWord; - TX_F2_FreqWord->desc = "Set Modulator F2 Frequency"; - TX_F2_FreqWord->name = "Tx F2 NCO Frequency Control Word"; - config_nco_fw RX_F1_FreqWord; - RX_F1_FreqWord->desc = "Set Demodulator F1 Frequency"; - RX_F1_FreqWord->name = "Rx F1 NCO Frequency Control Word"; - config_nco_fw RX_F2_FreqWord; - RX_F2_FreqWord->desc = "Set Demodulator F2 Frequency"; - RX_F2_FreqWord->name = "Rx F2 NCO Frequency Control Word"; - lpf_config_0 LPF_Config_0; - lpf_config_1 LPF_Config_1; - data_width Tx_Data_Width; - Tx_Data_Width->desc = "Set the parallel data width of the parallel-to-serial converter"; - Tx_Data_Width->name = "Modem Tx Input Data Width"; - data_width Rx_Data_Width; - Rx_Data_Width->desc = "Set the parallel data width of the serial-to-parallel converter"; - Rx_Data_Width->name = "Modem Rx Output Data Width"; - prbs_ctrl PRBS_Control; - config_prbs_seed PRBS_Initial_State; - config_prbs_poly PRBS_Polynomial; - config_prbs_errmask PRBS_Error_Mask; - stat_32_bits PRBS_Bit_Count; - stat_32_errs PRBS_Error_Count; - stat_32_lpf_acc LPF_Accum_F1; - LPF_Accum_F1->name = "F1 PI Controller Accumulator"; - LPF_Accum_F1->desc = "Value of the F1 PI Controller Accumulator"; - stat_32_lpf_acc LPF_Accum_F2; - LPF_Accum_F2->name = "F2 PI Controller Accumulator"; - LPF_Accum_F2->desc = "Value of the F2 PI Controller Accumulator"; - msk_stat_3 axis_xfer_count; - rx_sample_discard Rx_Sample_Discard; - lpf_config_2 LPF_Config_2; - observation_data f1_nco_adjust; - f1_nco_adjust->name = "F1 NCO Frequency Adjust"; - f1_nco_adjust->desc = "Frequency offet applied to the F1 NCO"; - f1_nco_adjust.data->name = "F1 NCO Frequency Adjust"; - f1_nco_adjust.data->desc = "Frequency offet applied to the F1 NCO"; - observation_data f2_nco_adjust; - f2_nco_adjust->name = "F2 NCO Frequency Adjust"; - f2_nco_adjust->desc = "Frequency offet applied to the F2 NCO"; - f2_nco_adjust.data->name = "F2 NCO Frequency Adjust"; - f2_nco_adjust.data->desc = "Frequency offet applied to the F2 NCO"; - observation_data f1_error; - f1_error->name = "F1 Error Value"; - f1_error->desc = "Error value of the F1 Costas loop after each active bit period"; - f1_error.data->name = "F1 Error Value"; - f1_error.data->desc = "Error value of the F1 Costas loop after each active bit period"; - observation_data f2_error; - f2_error->name = "F2 Error Value"; - f2_error->desc = "Error value of the F2 Costas loop after each active bit period"; - f2_error.data->name = "F2 Error Value"; - f2_error.data->desc = "Error value of the F2 Costas loop after each active bit period"; - tx_sync_ctrl Tx_Sync_Ctrl; - tx_sync_cnt Tx_Sync_Cnt; - lowpass_ema_alpha lowpass_ema_alpha1; - lowpass_ema_alpha lowpass_ema_alpha2; - rx_power rx_power; - -}; - -addrmap Pluto_MSK_Modem { - msk_top_regs pluto_msk_regs @0x43C00000; -}; diff --git a/rdl/msk_top_regs_desy.rdl b/rdl/msk_top_regs_desy.rdl deleted file mode 100644 index 3204600..0000000 --- a/rdl/msk_top_regs_desy.rdl +++ /dev/null @@ -1,208 +0,0 @@ -reg msk_hash_lo { - regwidth = 32; - accesswidth = 32; - field { sw = r; hw = na; } hash_id_lo[31:0] = 0xAAAA5555; -}; - -reg msk_hash_hi { - regwidth = 32; - accesswidth = 32; - field { sw = r; hw = na; } hash_id_hi[31:0] = 0x5555AAAA; -}; - -reg msk_init { - regwidth = 32; - field { sw = rw; hw=r; } txrxinit = 1; - field { sw = rw; hw=r; } txinit = 1; - field { sw = rw; hw=r; } rxinit = 1; -}; - -reg msk_ctrl { - regwidth = 32; - field { sw = rw; hw = r; } ptt = 0; - field { sw = rw; hw = r; } loopback_ena = 0; - field { sw = rw; hw = r; } rx_invert = 0; - field { sw = rw; hw = r; singlepulse = true; } clear_counts = 0; - field { sw = rw; hw = r; } diff_encoder_loopback = 0; -}; - -reg msk_stat_0 { - regwidth = 32; - field { sw = r; hw = w; } demod_sync_lock=0; - field { sw = r; hw = w; } tx_enable=0; - field { sw = r; hw = w; } rx_enable=0; - field { sw = r; hw = w; } tx_axis_valid=0; -}; - -reg msk_stat_1 { - regwidth = 32; - field { sw = r; hw = w; } tx_bit_counter[31:0] = 0; -}; - -reg msk_stat_2 { - regwidth = 32; - field { sw = r; hw = w; } tx_ena_counter[31:0] = 0; -}; - -reg config_nco_fw { - regwidth = 32; - field { sw = rw; hw = r; } config_data[31:0] = 0; -}; - -reg rx_sample_discard { - regwidth = 32; - field { sw = rw; hw = r; } rx_sample_discard[7:0] = 0; - field { sw = rw; hw = r; } rx_nco_discard[15:8] = 0; -}; - -reg lpf_config_0 { - regwidth = 32; - field { sw = rw; hw = r; } lpf_freeze = 0; - field { sw = rw; hw = r; } lpf_zero = 0; - field { sw = w; hw = r; } prbs_reserved[7:2] = 0; - field { sw = rw; hw = r; } lpf_alpha[31:8] = 0; -}; - -reg lpf_config_1 { - regwidth = 32; - field { sw = rw; hw = r; } i_gain[23:0] = 0; - field { sw = rw; hw = r; } i_shift[31:24] = 0; -}; - -reg lpf_config_2 { - regwidth = 32; - field { sw = rw; hw = r; } p_gain[23:0] = 0; - field { sw = rw; hw = r; } p_shift[31:24] = 0; -}; - -reg data_width { - regwidth = 32; - field { sw = rw; hw = r; } data_width[7:0] = 8; -}; - -reg prbs_ctrl { - regwidth = 32; - field { sw = rw; hw = r; } prbs_sel = 0; - field { sw = w; hw = r; singlepulse = true; } prbs_error_insert = 0; - field { sw = w; hw = r; singlepulse = true; } prbs_clear = 0; - field { sw = w; hw = r; singlepulse = true; } prbs_manual_sync = 0; - field { sw = w; hw = r; } prbs_reserved[15:4] = 0; - field { sw = w; hw = r; } prbs_sync_threshold[31:16] = 0; -}; - -reg config_prbs_seed { - regwidth = 32; - field { sw = rw; hw = r; } config_data[31:0] = 0; -}; - -reg config_prbs_poly { - regwidth = 32; - field { sw = rw; hw = r; } config_data[31:0] = 0; -}; - -reg config_prbs_errmask { - regwidth = 32; - field { sw = rw; hw = r; } config_data[31:0] = 0; -}; - -reg stat_32_bits { - regwidth = 32; - field { sw = r; hw = w; } status_data[31:0] = 0; -}; - -reg stat_32_errs { - regwidth = 32; - field { sw = r; hw = w; } status_data[31:0] = 0; -}; - -reg stat_32_lpf_acc { - regwidth = 32; - field { sw = r; hw = w; } status_data[31:0] = 0; -}; - -reg msk_stat_3 { - regwidth = 32; - field { sw = r; hw = w; } xfer_count[31:0] = 0; -}; - -reg tx_sync_ctrl { - regwidth = 32; - field { sw = rw; hw = r; } tx_sync_ena = 0; - field { sw = rw; hw = r; } tx_sync_force = 0; - field { sw = rw; hw = r; } tx_sync_f1 = 0; - field { sw = rw; hw = r; } tx_sync_f2 = 0; -}; - -reg tx_sync_cnt { - regwidth = 32; - field { sw = rw; hw = r; } tx_sync_cnt[23:0] = 0; -}; - -reg lowpass_ema_alpha { - regwidth = 32; - field { sw = rw; hw = r; } alpha[17:0] = 0; -}; - -reg rx_power { - regwidth = 32; - field { sw = r; hw = w; } rx_power[22:0] = 0; -}; - -field data32 { - fieldwidth = 32; - sw = r; - hw = w; -}; - -reg observation_data { - regwidth = 32; - data32 data[31:0] = 0; -}; - -addrmap msk_top_regs { - lsb0; - default accesswidth=32; - addressing=compact; - - desyrdl_interface = "AXI4L"; - desyrdl_access_channel = 0; - - msk_hash_lo Hash_ID_Low; - msk_hash_hi Hash_ID_High; - msk_init MSK_Init; - msk_ctrl MSK_Control; - msk_stat_0 MSK_Status; - msk_stat_1 Tx_Bit_Count; - msk_stat_2 Tx_Enable_Count; - config_nco_fw Fb_FreqWord; - config_nco_fw TX_F1_FreqWord; - config_nco_fw TX_F2_FreqWord; - config_nco_fw RX_F1_FreqWord; - config_nco_fw RX_F2_FreqWord; - lpf_config_0 LPF_Config_0; - lpf_config_1 LPF_Config_1; - data_width Tx_Data_Width; - data_width Rx_Data_Width; - prbs_ctrl PRBS_Control; - config_prbs_seed PRBS_Initial_State; - config_prbs_poly PRBS_Polynomial; - config_prbs_errmask PRBS_Error_Mask; - stat_32_bits PRBS_Bit_Count; - stat_32_errs PRBS_Error_Count; - stat_32_lpf_acc LPF_Accum_F1; - stat_32_lpf_acc LPF_Accum_F2; - msk_stat_3 axis_xfer_count; - rx_sample_discard Rx_Sample_Discard; - lpf_config_2 LPF_Config_2; - observation_data f1_nco_adjust; - observation_data f2_nco_adjust; - observation_data f1_error; - observation_data f2_error; - tx_sync_ctrl Tx_Sync_Ctrl; - tx_sync_cnt Tx_Sync_Cnt; - lowpass_ema_alpha lowpass_ema_alpha1; - lowpass_ema_alpha lowpass_ema_alpha2; - rx_power rx_power; - -}; - diff --git a/rdl/outputs/c-header/msk_top_regs.h b/rdl/outputs/c-header/msk_top_regs.h new file mode 100644 index 0000000..1d89a4a --- /dev/null +++ b/rdl/outputs/c-header/msk_top_regs.h @@ -0,0 +1,362 @@ +// Generated by PeakRDL-cheader - A free and open-source header generator +// https://github.com/SystemRDL/PeakRDL-cheader + +#ifndef MSK_TOP_REGS_H +#define MSK_TOP_REGS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +// Reg - msk_top_regs::msk_hash_lo +#define MSK_TOP_REGS__MSK_HASH_LO__HASH_ID_LO_bm 0xffffffff +#define MSK_TOP_REGS__MSK_HASH_LO__HASH_ID_LO_bp 0 +#define MSK_TOP_REGS__MSK_HASH_LO__HASH_ID_LO_bw 32 +#define MSK_TOP_REGS__MSK_HASH_LO__HASH_ID_LO_reset 0xaaaa5555 + +// Reg - msk_top_regs::msk_hash_hi +#define MSK_TOP_REGS__MSK_HASH_HI__HASH_ID_HI_bm 0xffffffff +#define MSK_TOP_REGS__MSK_HASH_HI__HASH_ID_HI_bp 0 +#define MSK_TOP_REGS__MSK_HASH_HI__HASH_ID_HI_bw 32 +#define MSK_TOP_REGS__MSK_HASH_HI__HASH_ID_HI_reset 0x5555aaaa + +// Reg - msk_top_regs::msk_init +#define MSK_TOP_REGS__MSK_INIT__TXRXINIT_bm 0x1 +#define MSK_TOP_REGS__MSK_INIT__TXRXINIT_bp 0 +#define MSK_TOP_REGS__MSK_INIT__TXRXINIT_bw 1 +#define MSK_TOP_REGS__MSK_INIT__TXRXINIT_reset 0x1 +#define MSK_TOP_REGS__MSK_INIT__TXINIT_bm 0x2 +#define MSK_TOP_REGS__MSK_INIT__TXINIT_bp 1 +#define MSK_TOP_REGS__MSK_INIT__TXINIT_bw 1 +#define MSK_TOP_REGS__MSK_INIT__TXINIT_reset 0x1 +#define MSK_TOP_REGS__MSK_INIT__RXINIT_bm 0x4 +#define MSK_TOP_REGS__MSK_INIT__RXINIT_bp 2 +#define MSK_TOP_REGS__MSK_INIT__RXINIT_bw 1 +#define MSK_TOP_REGS__MSK_INIT__RXINIT_reset 0x1 + +// Reg - msk_top_regs::msk_ctrl +#define MSK_TOP_REGS__MSK_CTRL__PTT_bm 0x1 +#define MSK_TOP_REGS__MSK_CTRL__PTT_bp 0 +#define MSK_TOP_REGS__MSK_CTRL__PTT_bw 1 +#define MSK_TOP_REGS__MSK_CTRL__PTT_reset 0x0 +#define MSK_TOP_REGS__MSK_CTRL__LOOPBACK_ENA_bm 0x2 +#define MSK_TOP_REGS__MSK_CTRL__LOOPBACK_ENA_bp 1 +#define MSK_TOP_REGS__MSK_CTRL__LOOPBACK_ENA_bw 1 +#define MSK_TOP_REGS__MSK_CTRL__LOOPBACK_ENA_reset 0x0 +#define MSK_TOP_REGS__MSK_CTRL__RX_INVERT_bm 0x4 +#define MSK_TOP_REGS__MSK_CTRL__RX_INVERT_bp 2 +#define MSK_TOP_REGS__MSK_CTRL__RX_INVERT_bw 1 +#define MSK_TOP_REGS__MSK_CTRL__RX_INVERT_reset 0x0 +#define MSK_TOP_REGS__MSK_CTRL__CLEAR_COUNTS_bm 0x8 +#define MSK_TOP_REGS__MSK_CTRL__CLEAR_COUNTS_bp 3 +#define MSK_TOP_REGS__MSK_CTRL__CLEAR_COUNTS_bw 1 +#define MSK_TOP_REGS__MSK_CTRL__CLEAR_COUNTS_reset 0x0 +#define MSK_TOP_REGS__MSK_CTRL__DIFF_ENCODER_LOOPBACK_bm 0x10 +#define MSK_TOP_REGS__MSK_CTRL__DIFF_ENCODER_LOOPBACK_bp 4 +#define MSK_TOP_REGS__MSK_CTRL__DIFF_ENCODER_LOOPBACK_bw 1 +#define MSK_TOP_REGS__MSK_CTRL__DIFF_ENCODER_LOOPBACK_reset 0x0 + +// Reg - msk_top_regs::msk_stat_0 +#define MSK_TOP_REGS__MSK_STAT_0__DEMOD_SYNC_LOCK_bm 0x1 +#define MSK_TOP_REGS__MSK_STAT_0__DEMOD_SYNC_LOCK_bp 0 +#define MSK_TOP_REGS__MSK_STAT_0__DEMOD_SYNC_LOCK_bw 1 +#define MSK_TOP_REGS__MSK_STAT_0__DEMOD_SYNC_LOCK_reset 0x0 +#define MSK_TOP_REGS__MSK_STAT_0__TX_ENABLE_bm 0x2 +#define MSK_TOP_REGS__MSK_STAT_0__TX_ENABLE_bp 1 +#define MSK_TOP_REGS__MSK_STAT_0__TX_ENABLE_bw 1 +#define MSK_TOP_REGS__MSK_STAT_0__TX_ENABLE_reset 0x0 +#define MSK_TOP_REGS__MSK_STAT_0__RX_ENABLE_bm 0x4 +#define MSK_TOP_REGS__MSK_STAT_0__RX_ENABLE_bp 2 +#define MSK_TOP_REGS__MSK_STAT_0__RX_ENABLE_bw 1 +#define MSK_TOP_REGS__MSK_STAT_0__RX_ENABLE_reset 0x0 +#define MSK_TOP_REGS__MSK_STAT_0__TX_AXIS_VALID_bm 0x8 +#define MSK_TOP_REGS__MSK_STAT_0__TX_AXIS_VALID_bp 3 +#define MSK_TOP_REGS__MSK_STAT_0__TX_AXIS_VALID_bw 1 +#define MSK_TOP_REGS__MSK_STAT_0__TX_AXIS_VALID_reset 0x0 + +// Reg - msk_top_regs::msk_stat_1 +#define MSK_TOP_REGS__MSK_STAT_1__TX_BIT_COUNTER_bm 0xffffffff +#define MSK_TOP_REGS__MSK_STAT_1__TX_BIT_COUNTER_bp 0 +#define MSK_TOP_REGS__MSK_STAT_1__TX_BIT_COUNTER_bw 32 + +// Reg - msk_top_regs::msk_stat_2 +#define MSK_TOP_REGS__MSK_STAT_2__TX_ENA_COUNTER_bm 0xffffffff +#define MSK_TOP_REGS__MSK_STAT_2__TX_ENA_COUNTER_bp 0 +#define MSK_TOP_REGS__MSK_STAT_2__TX_ENA_COUNTER_bw 32 +#define MSK_TOP_REGS__MSK_STAT_2__TX_ENA_COUNTER_reset 0x0 + +// Reg - msk_top_regs::config_nco_fw_desc_c4924cc6_name_0c494469 +#define MSK_TOP_REGS__CONFIG_NCO_FW_DESC_C4924CC6_NAME_0C494469__CONFIG_DATA_bm 0xffffffff +#define MSK_TOP_REGS__CONFIG_NCO_FW_DESC_C4924CC6_NAME_0C494469__CONFIG_DATA_bp 0 +#define MSK_TOP_REGS__CONFIG_NCO_FW_DESC_C4924CC6_NAME_0C494469__CONFIG_DATA_bw 32 +#define MSK_TOP_REGS__CONFIG_NCO_FW_DESC_C4924CC6_NAME_0C494469__CONFIG_DATA_reset 0x0 + +// Reg - msk_top_regs::config_nco_fw_desc_94d7aaf5_name_84dd0c1c +#define MSK_TOP_REGS__CONFIG_NCO_FW_DESC_94D7AAF5_NAME_84DD0C1C__CONFIG_DATA_bm 0xffffffff +#define MSK_TOP_REGS__CONFIG_NCO_FW_DESC_94D7AAF5_NAME_84DD0C1C__CONFIG_DATA_bp 0 +#define MSK_TOP_REGS__CONFIG_NCO_FW_DESC_94D7AAF5_NAME_84DD0C1C__CONFIG_DATA_bw 32 +#define MSK_TOP_REGS__CONFIG_NCO_FW_DESC_94D7AAF5_NAME_84DD0C1C__CONFIG_DATA_reset 0x0 + +// Reg - msk_top_regs::config_nco_fw_desc_42134a4f_name_d97dbd51 +#define MSK_TOP_REGS__CONFIG_NCO_FW_DESC_42134A4F_NAME_D97DBD51__CONFIG_DATA_bm 0xffffffff +#define MSK_TOP_REGS__CONFIG_NCO_FW_DESC_42134A4F_NAME_D97DBD51__CONFIG_DATA_bp 0 +#define MSK_TOP_REGS__CONFIG_NCO_FW_DESC_42134A4F_NAME_D97DBD51__CONFIG_DATA_bw 32 +#define MSK_TOP_REGS__CONFIG_NCO_FW_DESC_42134A4F_NAME_D97DBD51__CONFIG_DATA_reset 0x0 + +// Reg - msk_top_regs::config_nco_fw_desc_16fb48c8_name_8d01a20d +#define MSK_TOP_REGS__CONFIG_NCO_FW_DESC_16FB48C8_NAME_8D01A20D__CONFIG_DATA_bm 0xffffffff +#define MSK_TOP_REGS__CONFIG_NCO_FW_DESC_16FB48C8_NAME_8D01A20D__CONFIG_DATA_bp 0 +#define MSK_TOP_REGS__CONFIG_NCO_FW_DESC_16FB48C8_NAME_8D01A20D__CONFIG_DATA_bw 32 +#define MSK_TOP_REGS__CONFIG_NCO_FW_DESC_16FB48C8_NAME_8D01A20D__CONFIG_DATA_reset 0x0 + +// Reg - msk_top_regs::config_nco_fw_desc_43c0828f_name_bdc60ecf +#define MSK_TOP_REGS__CONFIG_NCO_FW_DESC_43C0828F_NAME_BDC60ECF__CONFIG_DATA_bm 0xffffffff +#define MSK_TOP_REGS__CONFIG_NCO_FW_DESC_43C0828F_NAME_BDC60ECF__CONFIG_DATA_bp 0 +#define MSK_TOP_REGS__CONFIG_NCO_FW_DESC_43C0828F_NAME_BDC60ECF__CONFIG_DATA_bw 32 +#define MSK_TOP_REGS__CONFIG_NCO_FW_DESC_43C0828F_NAME_BDC60ECF__CONFIG_DATA_reset 0x0 + +// Reg - msk_top_regs::lpf_config_0 +#define MSK_TOP_REGS__LPF_CONFIG_0__LPF_FREEZE_bm 0x1 +#define MSK_TOP_REGS__LPF_CONFIG_0__LPF_FREEZE_bp 0 +#define MSK_TOP_REGS__LPF_CONFIG_0__LPF_FREEZE_bw 1 +#define MSK_TOP_REGS__LPF_CONFIG_0__LPF_FREEZE_reset 0x0 +#define MSK_TOP_REGS__LPF_CONFIG_0__LPF_ZERO_bm 0x2 +#define MSK_TOP_REGS__LPF_CONFIG_0__LPF_ZERO_bp 1 +#define MSK_TOP_REGS__LPF_CONFIG_0__LPF_ZERO_bw 1 +#define MSK_TOP_REGS__LPF_CONFIG_0__LPF_ZERO_reset 0x0 +#define MSK_TOP_REGS__LPF_CONFIG_0__PRBS_RESERVED_bm 0xfc +#define MSK_TOP_REGS__LPF_CONFIG_0__PRBS_RESERVED_bp 2 +#define MSK_TOP_REGS__LPF_CONFIG_0__PRBS_RESERVED_bw 6 +#define MSK_TOP_REGS__LPF_CONFIG_0__PRBS_RESERVED_reset 0x0 +#define MSK_TOP_REGS__LPF_CONFIG_0__LPF_ALPHA_bm 0xffffff00 +#define MSK_TOP_REGS__LPF_CONFIG_0__LPF_ALPHA_bp 8 +#define MSK_TOP_REGS__LPF_CONFIG_0__LPF_ALPHA_bw 24 +#define MSK_TOP_REGS__LPF_CONFIG_0__LPF_ALPHA_reset 0x0 + +// Reg - msk_top_regs::lpf_config_1 +#define MSK_TOP_REGS__LPF_CONFIG_1__I_GAIN_bm 0xffffff +#define MSK_TOP_REGS__LPF_CONFIG_1__I_GAIN_bp 0 +#define MSK_TOP_REGS__LPF_CONFIG_1__I_GAIN_bw 24 +#define MSK_TOP_REGS__LPF_CONFIG_1__I_GAIN_reset 0x0 +#define MSK_TOP_REGS__LPF_CONFIG_1__I_SHIFT_bm 0xff000000 +#define MSK_TOP_REGS__LPF_CONFIG_1__I_SHIFT_bp 24 +#define MSK_TOP_REGS__LPF_CONFIG_1__I_SHIFT_bw 8 +#define MSK_TOP_REGS__LPF_CONFIG_1__I_SHIFT_reset 0x0 + +// Reg - msk_top_regs::data_width_desc_58c848dd_name_2fbd8eba +#define MSK_TOP_REGS__DATA_WIDTH_DESC_58C848DD_NAME_2FBD8EBA__DATA_WIDTH_bm 0xff +#define MSK_TOP_REGS__DATA_WIDTH_DESC_58C848DD_NAME_2FBD8EBA__DATA_WIDTH_bp 0 +#define MSK_TOP_REGS__DATA_WIDTH_DESC_58C848DD_NAME_2FBD8EBA__DATA_WIDTH_bw 8 +#define MSK_TOP_REGS__DATA_WIDTH_DESC_58C848DD_NAME_2FBD8EBA__DATA_WIDTH_reset 0x8 + +// Reg - msk_top_regs::data_width_desc_6097df38_name_4609588b +#define MSK_TOP_REGS__DATA_WIDTH_DESC_6097DF38_NAME_4609588B__DATA_WIDTH_bm 0xff +#define MSK_TOP_REGS__DATA_WIDTH_DESC_6097DF38_NAME_4609588B__DATA_WIDTH_bp 0 +#define MSK_TOP_REGS__DATA_WIDTH_DESC_6097DF38_NAME_4609588B__DATA_WIDTH_bw 8 +#define MSK_TOP_REGS__DATA_WIDTH_DESC_6097DF38_NAME_4609588B__DATA_WIDTH_reset 0x8 + +// Reg - msk_top_regs::prbs_ctrl +#define MSK_TOP_REGS__PRBS_CTRL__PRBS_SEL_bm 0x1 +#define MSK_TOP_REGS__PRBS_CTRL__PRBS_SEL_bp 0 +#define MSK_TOP_REGS__PRBS_CTRL__PRBS_SEL_bw 1 +#define MSK_TOP_REGS__PRBS_CTRL__PRBS_SEL_reset 0x0 +#define MSK_TOP_REGS__PRBS_CTRL__PRBS_ERROR_INSERT_bm 0x2 +#define MSK_TOP_REGS__PRBS_CTRL__PRBS_ERROR_INSERT_bp 1 +#define MSK_TOP_REGS__PRBS_CTRL__PRBS_ERROR_INSERT_bw 1 +#define MSK_TOP_REGS__PRBS_CTRL__PRBS_ERROR_INSERT_reset 0x0 +#define MSK_TOP_REGS__PRBS_CTRL__PRBS_CLEAR_bm 0x4 +#define MSK_TOP_REGS__PRBS_CTRL__PRBS_CLEAR_bp 2 +#define MSK_TOP_REGS__PRBS_CTRL__PRBS_CLEAR_bw 1 +#define MSK_TOP_REGS__PRBS_CTRL__PRBS_CLEAR_reset 0x0 +#define MSK_TOP_REGS__PRBS_CTRL__PRBS_MANUAL_SYNC_bm 0x8 +#define MSK_TOP_REGS__PRBS_CTRL__PRBS_MANUAL_SYNC_bp 3 +#define MSK_TOP_REGS__PRBS_CTRL__PRBS_MANUAL_SYNC_bw 1 +#define MSK_TOP_REGS__PRBS_CTRL__PRBS_MANUAL_SYNC_reset 0x0 +#define MSK_TOP_REGS__PRBS_CTRL__PRBS_RESERVED_bm 0xfff0 +#define MSK_TOP_REGS__PRBS_CTRL__PRBS_RESERVED_bp 4 +#define MSK_TOP_REGS__PRBS_CTRL__PRBS_RESERVED_bw 12 +#define MSK_TOP_REGS__PRBS_CTRL__PRBS_RESERVED_reset 0x0 +#define MSK_TOP_REGS__PRBS_CTRL__PRBS_SYNC_THRESHOLD_bm 0xffff0000 +#define MSK_TOP_REGS__PRBS_CTRL__PRBS_SYNC_THRESHOLD_bp 16 +#define MSK_TOP_REGS__PRBS_CTRL__PRBS_SYNC_THRESHOLD_bw 16 +#define MSK_TOP_REGS__PRBS_CTRL__PRBS_SYNC_THRESHOLD_reset 0x0 + +// Reg - msk_top_regs::config_prbs_seed +#define MSK_TOP_REGS__CONFIG_PRBS_SEED__CONFIG_DATA_bm 0xffffffff +#define MSK_TOP_REGS__CONFIG_PRBS_SEED__CONFIG_DATA_bp 0 +#define MSK_TOP_REGS__CONFIG_PRBS_SEED__CONFIG_DATA_bw 32 +#define MSK_TOP_REGS__CONFIG_PRBS_SEED__CONFIG_DATA_reset 0x0 + +// Reg - msk_top_regs::config_prbs_poly +#define MSK_TOP_REGS__CONFIG_PRBS_POLY__CONFIG_DATA_bm 0xffffffff +#define MSK_TOP_REGS__CONFIG_PRBS_POLY__CONFIG_DATA_bp 0 +#define MSK_TOP_REGS__CONFIG_PRBS_POLY__CONFIG_DATA_bw 32 +#define MSK_TOP_REGS__CONFIG_PRBS_POLY__CONFIG_DATA_reset 0x0 + +// Reg - msk_top_regs::config_prbs_errmask +#define MSK_TOP_REGS__CONFIG_PRBS_ERRMASK__CONFIG_DATA_bm 0xffffffff +#define MSK_TOP_REGS__CONFIG_PRBS_ERRMASK__CONFIG_DATA_bp 0 +#define MSK_TOP_REGS__CONFIG_PRBS_ERRMASK__CONFIG_DATA_bw 32 +#define MSK_TOP_REGS__CONFIG_PRBS_ERRMASK__CONFIG_DATA_reset 0x0 + +// Reg - msk_top_regs::stat_32_bits +#define MSK_TOP_REGS__STAT_32_BITS__STATUS_DATA_bm 0xffffffff +#define MSK_TOP_REGS__STAT_32_BITS__STATUS_DATA_bp 0 +#define MSK_TOP_REGS__STAT_32_BITS__STATUS_DATA_bw 32 +#define MSK_TOP_REGS__STAT_32_BITS__STATUS_DATA_reset 0x0 + +// Reg - msk_top_regs::stat_32_errs +#define MSK_TOP_REGS__STAT_32_ERRS__STATUS_DATA_bm 0xffffffff +#define MSK_TOP_REGS__STAT_32_ERRS__STATUS_DATA_bp 0 +#define MSK_TOP_REGS__STAT_32_ERRS__STATUS_DATA_bw 32 +#define MSK_TOP_REGS__STAT_32_ERRS__STATUS_DATA_reset 0x0 + +// Reg - msk_top_regs::stat_32_lpf_acc_desc_8cebc7dc_name_f20c6670 +#define MSK_TOP_REGS__STAT_32_LPF_ACC_DESC_8CEBC7DC_NAME_F20C6670__STATUS_DATA_bm 0xffffffff +#define MSK_TOP_REGS__STAT_32_LPF_ACC_DESC_8CEBC7DC_NAME_F20C6670__STATUS_DATA_bp 0 +#define MSK_TOP_REGS__STAT_32_LPF_ACC_DESC_8CEBC7DC_NAME_F20C6670__STATUS_DATA_bw 32 +#define MSK_TOP_REGS__STAT_32_LPF_ACC_DESC_8CEBC7DC_NAME_F20C6670__STATUS_DATA_reset 0x0 + +// Reg - msk_top_regs::stat_32_lpf_acc_desc_dea6bd99_name_758fd0ce +#define MSK_TOP_REGS__STAT_32_LPF_ACC_DESC_DEA6BD99_NAME_758FD0CE__STATUS_DATA_bm 0xffffffff +#define MSK_TOP_REGS__STAT_32_LPF_ACC_DESC_DEA6BD99_NAME_758FD0CE__STATUS_DATA_bp 0 +#define MSK_TOP_REGS__STAT_32_LPF_ACC_DESC_DEA6BD99_NAME_758FD0CE__STATUS_DATA_bw 32 +#define MSK_TOP_REGS__STAT_32_LPF_ACC_DESC_DEA6BD99_NAME_758FD0CE__STATUS_DATA_reset 0x0 + +// Reg - msk_top_regs::msk_stat_3 +#define MSK_TOP_REGS__MSK_STAT_3__XFER_COUNT_bm 0xffffffff +#define MSK_TOP_REGS__MSK_STAT_3__XFER_COUNT_bp 0 +#define MSK_TOP_REGS__MSK_STAT_3__XFER_COUNT_bw 32 +#define MSK_TOP_REGS__MSK_STAT_3__XFER_COUNT_reset 0x0 + +// Reg - msk_top_regs::rx_sample_discard +#define MSK_TOP_REGS__RX_SAMPLE_DISCARD__RX_SAMPLE_DISCARD_bm 0xff +#define MSK_TOP_REGS__RX_SAMPLE_DISCARD__RX_SAMPLE_DISCARD_bp 0 +#define MSK_TOP_REGS__RX_SAMPLE_DISCARD__RX_SAMPLE_DISCARD_bw 8 +#define MSK_TOP_REGS__RX_SAMPLE_DISCARD__RX_SAMPLE_DISCARD_reset 0x0 +#define MSK_TOP_REGS__RX_SAMPLE_DISCARD__RX_NCO_DISCARD_bm 0xff00 +#define MSK_TOP_REGS__RX_SAMPLE_DISCARD__RX_NCO_DISCARD_bp 8 +#define MSK_TOP_REGS__RX_SAMPLE_DISCARD__RX_NCO_DISCARD_bw 8 +#define MSK_TOP_REGS__RX_SAMPLE_DISCARD__RX_NCO_DISCARD_reset 0x0 + +// Reg - msk_top_regs::lpf_config_2 +#define MSK_TOP_REGS__LPF_CONFIG_2__P_GAIN_bm 0xffffff +#define MSK_TOP_REGS__LPF_CONFIG_2__P_GAIN_bp 0 +#define MSK_TOP_REGS__LPF_CONFIG_2__P_GAIN_bw 24 +#define MSK_TOP_REGS__LPF_CONFIG_2__P_GAIN_reset 0x0 +#define MSK_TOP_REGS__LPF_CONFIG_2__P_SHIFT_bm 0xff000000 +#define MSK_TOP_REGS__LPF_CONFIG_2__P_SHIFT_bp 24 +#define MSK_TOP_REGS__LPF_CONFIG_2__P_SHIFT_bw 8 +#define MSK_TOP_REGS__LPF_CONFIG_2__P_SHIFT_reset 0x0 + +// Reg - msk_top_regs::observation_data_data_0c017ef4_desc_64ff3689_name_d8ad3b25 +#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_0C017EF4_DESC_64FF3689_NAME_D8AD3B25__DATA_bm 0xffffffff +#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_0C017EF4_DESC_64FF3689_NAME_D8AD3B25__DATA_bp 0 +#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_0C017EF4_DESC_64FF3689_NAME_D8AD3B25__DATA_bw 32 +#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_0C017EF4_DESC_64FF3689_NAME_D8AD3B25__DATA_reset 0x0 + +// Reg - msk_top_regs::observation_data_data_0515efaa_desc_ebde6d39_name_2c154788 +#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_0515EFAA_DESC_EBDE6D39_NAME_2C154788__DATA_bm 0xffffffff +#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_0515EFAA_DESC_EBDE6D39_NAME_2C154788__DATA_bp 0 +#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_0515EFAA_DESC_EBDE6D39_NAME_2C154788__DATA_bw 32 +#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_0515EFAA_DESC_EBDE6D39_NAME_2C154788__DATA_reset 0x0 + +// Reg - msk_top_regs::observation_data_data_25a21249_desc_417e1c96_name_3b640507 +#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_25A21249_DESC_417E1C96_NAME_3B640507__DATA_bm 0xffffffff +#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_25A21249_DESC_417E1C96_NAME_3B640507__DATA_bp 0 +#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_25A21249_DESC_417E1C96_NAME_3B640507__DATA_bw 32 +#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_25A21249_DESC_417E1C96_NAME_3B640507__DATA_reset 0x0 + +// Reg - msk_top_regs::observation_data_data_272a00b6_desc_70869502_name_3de9a0d3 +#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_272A00B6_DESC_70869502_NAME_3DE9A0D3__DATA_bm 0xffffffff +#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_272A00B6_DESC_70869502_NAME_3DE9A0D3__DATA_bp 0 +#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_272A00B6_DESC_70869502_NAME_3DE9A0D3__DATA_bw 32 +#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_272A00B6_DESC_70869502_NAME_3DE9A0D3__DATA_reset 0x0 + +// Reg - msk_top_regs::tx_sync_ctrl +#define MSK_TOP_REGS__TX_SYNC_CTRL__TX_SYNC_ENA_bm 0x1 +#define MSK_TOP_REGS__TX_SYNC_CTRL__TX_SYNC_ENA_bp 0 +#define MSK_TOP_REGS__TX_SYNC_CTRL__TX_SYNC_ENA_bw 1 +#define MSK_TOP_REGS__TX_SYNC_CTRL__TX_SYNC_ENA_reset 0x0 +#define MSK_TOP_REGS__TX_SYNC_CTRL__TX_SYNC_FORCE_bm 0x2 +#define MSK_TOP_REGS__TX_SYNC_CTRL__TX_SYNC_FORCE_bp 1 +#define MSK_TOP_REGS__TX_SYNC_CTRL__TX_SYNC_FORCE_bw 1 +#define MSK_TOP_REGS__TX_SYNC_CTRL__TX_SYNC_FORCE_reset 0x0 +#define MSK_TOP_REGS__TX_SYNC_CTRL__TX_SYNC_F1_bm 0x4 +#define MSK_TOP_REGS__TX_SYNC_CTRL__TX_SYNC_F1_bp 2 +#define MSK_TOP_REGS__TX_SYNC_CTRL__TX_SYNC_F1_bw 1 +#define MSK_TOP_REGS__TX_SYNC_CTRL__TX_SYNC_F1_reset 0x0 +#define MSK_TOP_REGS__TX_SYNC_CTRL__TX_SYNC_F2_bm 0x8 +#define MSK_TOP_REGS__TX_SYNC_CTRL__TX_SYNC_F2_bp 3 +#define MSK_TOP_REGS__TX_SYNC_CTRL__TX_SYNC_F2_bw 1 +#define MSK_TOP_REGS__TX_SYNC_CTRL__TX_SYNC_F2_reset 0x0 + +// Reg - msk_top_regs::tx_sync_cnt +#define MSK_TOP_REGS__TX_SYNC_CNT__TX_SYNC_CNT_bm 0xffffff +#define MSK_TOP_REGS__TX_SYNC_CNT__TX_SYNC_CNT_bp 0 +#define MSK_TOP_REGS__TX_SYNC_CNT__TX_SYNC_CNT_bw 24 +#define MSK_TOP_REGS__TX_SYNC_CNT__TX_SYNC_CNT_reset 0x0 + +// Reg - msk_top_regs::lowpass_ema_alpha +#define MSK_TOP_REGS__LOWPASS_EMA_ALPHA__ALPHA_bm 0x3ffff +#define MSK_TOP_REGS__LOWPASS_EMA_ALPHA__ALPHA_bp 0 +#define MSK_TOP_REGS__LOWPASS_EMA_ALPHA__ALPHA_bw 18 +#define MSK_TOP_REGS__LOWPASS_EMA_ALPHA__ALPHA_reset 0x0 + +// Reg - msk_top_regs::rx_power +#define MSK_TOP_REGS__RX_POWER__RX_POWER_bm 0x7fffff +#define MSK_TOP_REGS__RX_POWER__RX_POWER_bp 0 +#define MSK_TOP_REGS__RX_POWER__RX_POWER_bw 23 +#define MSK_TOP_REGS__RX_POWER__RX_POWER_reset 0x0 + +// Addrmap - msk_top_regs +typedef struct __attribute__ ((__packed__)) { + uint32_t Hash_ID_Low; + uint32_t Hash_ID_High; + uint32_t MSK_Init; + uint32_t MSK_Control; + uint32_t MSK_Status; + uint32_t Tx_Bit_Count; + uint32_t Tx_Enable_Count; + uint32_t Fb_FreqWord; + uint32_t TX_F1_FreqWord; + uint32_t TX_F2_FreqWord; + uint32_t RX_F1_FreqWord; + uint32_t RX_F2_FreqWord; + uint32_t LPF_Config_0; + uint32_t LPF_Config_1; + uint32_t Tx_Data_Width; + uint32_t Rx_Data_Width; + uint32_t PRBS_Control; + uint32_t PRBS_Initial_State; + uint32_t PRBS_Polynomial; + uint32_t PRBS_Error_Mask; + uint32_t PRBS_Bit_Count; + uint32_t PRBS_Error_Count; + uint32_t LPF_Accum_F1; + uint32_t LPF_Accum_F2; + uint32_t axis_xfer_count; + uint32_t Rx_Sample_Discard; + uint32_t LPF_Config_2; + uint32_t f1_nco_adjust; + uint32_t f2_nco_adjust; + uint32_t f1_error; + uint32_t f2_error; + uint32_t Tx_Sync_Ctrl; + uint32_t Tx_Sync_Cnt; + uint32_t lowpass_ema_alpha1; + uint32_t lowpass_ema_alpha2; + uint32_t rx_power; +} msk_top_regs_t; + + +static_assert(sizeof(msk_top_regs_t) == 0x90, "Packing error"); + +#ifdef __cplusplus +} +#endif + +#endif /* MSK_TOP_REGS_H */ diff --git a/rdl/msk_top_regs.md b/rdl/outputs/docs/msk_top_regs.md similarity index 87% rename from rdl/msk_top_regs.md rename to rdl/outputs/docs/msk_top_regs.md index 79009bc..82c2c8d 100644 --- a/rdl/msk_top_regs.md +++ b/rdl/outputs/docs/msk_top_regs.md @@ -1,24 +1,15 @@ -## Pluto_MSK_Modem address map +## msk_top_regs address map - Absolute Address: 0x0 - Base Offset: 0x0 -- Size: 0x43C00090 - -| Offset | Identifier | Name | -|----------|--------------|-------------------| -|0x43C00000|pluto_msk_regs|Pluto MSK Registers| - -## pluto_msk_regs address map - -- Absolute Address: 0x43C00000 -- Base Offset: 0x43C00000 - Size: 0x90

MSK Modem Configuration and Status Registers

@@ -27,8 +18,8 @@ Don't override. Generated from: Pluto_MSK_Modem |------|------------------|-------------------------------------------------------------| | 0x00 | Hash_ID_Low | Pluto MSK FPGA Hash ID - Lower 32-bits | | 0x04 | Hash_ID_High | Pluto MSK FPGA Hash ID - Upper 32-bits | -| 0x08 | MSK_Init | MSK Modem Control 0 | -| 0x0C | MSK_Control | MSK Modem Control 1 | +| 0x08 | MSK_Init | MSK Modem Initialization Control | +| 0x0C | MSK_Control | MSK Modem Control | | 0x10 | MSK_Status | MSK Modem Status 0 | | 0x14 | Tx_Bit_Count | MSK Modem Status 1 | | 0x18 | Tx_Enable_Count | MSK Modem Status 2 | @@ -64,7 +55,7 @@ Don't override. Generated from: Pluto_MSK_Modem ### Hash_ID_Low register -- Absolute Address: 0x43C00000 +- Absolute Address: 0x0 - Base Offset: 0x0 - Size: 0x4 @@ -78,7 +69,7 @@ Don't override. Generated from: Pluto_MSK_Modem ### Hash_ID_High register -- Absolute Address: 0x43C00004 +- Absolute Address: 0x4 - Base Offset: 0x4 - Size: 0x4 @@ -92,7 +83,7 @@ Don't override. Generated from: Pluto_MSK_Modem ### MSK_Init register -- Absolute Address: 0x43C00008 +- Absolute Address: 0x8 - Base Offset: 0x8 - Size: 0x4 @@ -121,7 +112,7 @@ Don't override. Generated from: Pluto_MSK_Modem ### MSK_Control register -- Absolute Address: 0x43C0000C +- Absolute Address: 0xC - Base Offset: 0xC - Size: 0x4 @@ -130,7 +121,7 @@ Don't override. Generated from: Pluto_MSK_Modem |Bits| Identifier |Access|Reset| Name | |----|---------------------|------|-----|-----------------------------------------------| | 0 | ptt | rw | 0x0 | Push-to-Talk Enable | -| 1 | loopback_ena | rw | 0x0 | Modem Loopback Enable | +| 1 | loopback_ena | rw | 0x0 | Modem Digital Tx -> Rx Loopback Enable | | 2 | rx_invert | rw | 0x0 | Rx Data Invert Enable | | 3 | clear_counts | rw | 0x0 | Clear Status Counters | | 4 |diff_encoder_loopback| rw | 0x0 |Differential Encoder -> Decoder Loopback Enable| @@ -161,7 +152,7 @@ Don't override. Generated from: Pluto_MSK_Modem ### MSK_Status register -- Absolute Address: 0x43C00010 +- Absolute Address: 0x10 - Base Offset: 0x10 - Size: 0x4 @@ -195,7 +186,7 @@ Don't override. Generated from: Pluto_MSK_Modem ### Tx_Bit_Count register -- Absolute Address: 0x43C00014 +- Absolute Address: 0x14 - Base Offset: 0x14 - Size: 0x4 @@ -203,7 +194,7 @@ Don't override. Generated from: Pluto_MSK_Modem |Bits| Identifier |Access|Reset| Name | |----|--------------|------|-----|------------| -|31:0|tx_bit_counter| r | 0x0 |Tx Bit Count| +|31:0|tx_bit_counter| r | — |Tx Bit Count| #### tx_bit_counter field @@ -211,7 +202,7 @@ Don't override. Generated from: Pluto_MSK_Modem ### Tx_Enable_Count register -- Absolute Address: 0x43C00018 +- Absolute Address: 0x18 - Base Offset: 0x18 - Size: 0x4 @@ -227,7 +218,7 @@ Don't override. Generated from: Pluto_MSK_Modem ### Fb_FreqWord register -- Absolute Address: 0x43C0001C +- Absolute Address: 0x1C - Base Offset: 0x1C - Size: 0x4 @@ -239,11 +230,12 @@ Don't override. Generated from: Pluto_MSK_Modem #### config_data field -

Sets the center frequency of the NCO as FW = Fn * 2^32/Fs, where Fn is the desired NCO frequency, and Fs is the NCO sample rate

+

Sets the center frequency of the NCO as FW = Fn * 2^32/Fs, +where Fn is the desired NCO frequency, and Fs is the NCO sample rate

### TX_F1_FreqWord register -- Absolute Address: 0x43C00020 +- Absolute Address: 0x20 - Base Offset: 0x20 - Size: 0x4 @@ -255,11 +247,12 @@ Don't override. Generated from: Pluto_MSK_Modem #### config_data field -

Sets the center frequency of the NCO as FW = Fn * 2^32/Fs, where Fn is the desired NCO frequency, and Fs is the NCO sample rate

+

Sets the center frequency of the NCO as FW = Fn * 2^32/Fs, +where Fn is the desired NCO frequency, and Fs is the NCO sample rate

### TX_F2_FreqWord register -- Absolute Address: 0x43C00024 +- Absolute Address: 0x24 - Base Offset: 0x24 - Size: 0x4 @@ -271,11 +264,12 @@ Don't override. Generated from: Pluto_MSK_Modem #### config_data field -

Sets the center frequency of the NCO as FW = Fn * 2^32/Fs, where Fn is the desired NCO frequency, and Fs is the NCO sample rate

+

Sets the center frequency of the NCO as FW = Fn * 2^32/Fs, +where Fn is the desired NCO frequency, and Fs is the NCO sample rate

### RX_F1_FreqWord register -- Absolute Address: 0x43C00028 +- Absolute Address: 0x28 - Base Offset: 0x28 - Size: 0x4 @@ -287,11 +281,12 @@ Don't override. Generated from: Pluto_MSK_Modem #### config_data field -

Sets the center frequency of the NCO as FW = Fn * 2^32/Fs, where Fn is the desired NCO frequency, and Fs is the NCO sample rate

+

Sets the center frequency of the NCO as FW = Fn * 2^32/Fs, +where Fn is the desired NCO frequency, and Fs is the NCO sample rate

### RX_F2_FreqWord register -- Absolute Address: 0x43C0002C +- Absolute Address: 0x2C - Base Offset: 0x2C - Size: 0x4 @@ -303,11 +298,12 @@ Don't override. Generated from: Pluto_MSK_Modem #### config_data field -

Sets the center frequency of the NCO as FW = Fn * 2^32/Fs, where Fn is the desired NCO frequency, and Fs is the NCO sample rate

+

Sets the center frequency of the NCO as FW = Fn * 2^32/Fs, +where Fn is the desired NCO frequency, and Fs is the NCO sample rate

### LPF_Config_0 register -- Absolute Address: 0x43C00030 +- Absolute Address: 0x30 - Base Offset: 0x30 - Size: 0x4 @@ -317,7 +313,7 @@ Don't override. Generated from: Pluto_MSK_Modem |----|-------------|------|-----|--------------------------------------| | 0 | lpf_freeze | rw | 0x0 |Freeze the accumulator's current value| | 1 | lpf_zero | rw | 0x0 | Hold the PI Accumulator at zero | -| 7:2|prbs_reserved| w | 0x0 | — | +| 7:2|prbs_reserved| rw | 0x0 | Reserved | |31:8| lpf_alpha | rw | 0x0 | Lowpass IIR filter alpha | #### lpf_freeze field @@ -336,7 +332,7 @@ Don't override. Generated from: Pluto_MSK_Modem ### LPF_Config_1 register -- Absolute Address: 0x43C00034 +- Absolute Address: 0x34 - Base Offset: 0x34 - Size: 0x4 @@ -357,7 +353,7 @@ Don't override. Generated from: Pluto_MSK_Modem ### Tx_Data_Width register -- Absolute Address: 0x43C00038 +- Absolute Address: 0x38 - Base Offset: 0x38 - Size: 0x4 @@ -373,7 +369,7 @@ Don't override. Generated from: Pluto_MSK_Modem ### Rx_Data_Width register -- Absolute Address: 0x43C0003C +- Absolute Address: 0x3C - Base Offset: 0x3C - Size: 0x4 @@ -389,7 +385,7 @@ Don't override. Generated from: Pluto_MSK_Modem ### PRBS_Control register -- Absolute Address: 0x43C00040 +- Absolute Address: 0x40 - Base Offset: 0x40 - Size: 0x4 @@ -401,8 +397,8 @@ Don't override. Generated from: Pluto_MSK_Modem | 1 | prbs_error_insert | w | 0x0 | PRBS Error Insert | | 2 | prbs_clear | w | 0x0 | PRBS Clear Counters | | 3 | prbs_manual_sync | w | 0x0 | PRBS Manual Sync | -| 15:4| prbs_reserved | w | 0x0 | — | -|31:16|prbs_sync_threshold| w | 0x0 |PRBS Auto Sync Threshold| +| 15:4| prbs_reserved | rw | 0x0 | Reserved | +|31:16|prbs_sync_threshold| rw | 0x0 |PRBS Auto Sync Threshold| #### prbs_sel field @@ -431,7 +427,7 @@ N > 0 : Auto sync after N errors

### PRBS_Initial_State register -- Absolute Address: 0x43C00044 +- Absolute Address: 0x44 - Base Offset: 0x44 - Size: 0x4 @@ -447,7 +443,7 @@ N > 0 : Auto sync after N errors

### PRBS_Polynomial register -- Absolute Address: 0x43C00048 +- Absolute Address: 0x48 - Base Offset: 0x48 - Size: 0x4 @@ -463,7 +459,7 @@ N > 0 : Auto sync after N errors

### PRBS_Error_Mask register -- Absolute Address: 0x43C0004C +- Absolute Address: 0x4C - Base Offset: 0x4C - Size: 0x4 @@ -479,7 +475,7 @@ N > 0 : Auto sync after N errors

### PRBS_Bit_Count register -- Absolute Address: 0x43C00050 +- Absolute Address: 0x50 - Base Offset: 0x50 - Size: 0x4 @@ -496,7 +492,7 @@ BER can be calculated as the ratio of received bits to errored-bits

### PRBS_Error_Count register -- Absolute Address: 0x43C00054 +- Absolute Address: 0x54 - Base Offset: 0x54 - Size: 0x4 @@ -513,7 +509,7 @@ BER can be calculated as the ratio of received bits to errored-bits

### LPF_Accum_F1 register -- Absolute Address: 0x43C00058 +- Absolute Address: 0x58 - Base Offset: 0x58 - Size: 0x4 @@ -529,7 +525,7 @@ BER can be calculated as the ratio of received bits to errored-bits

### LPF_Accum_F2 register -- Absolute Address: 0x43C0005C +- Absolute Address: 0x5C - Base Offset: 0x5C - Size: 0x4 @@ -545,7 +541,7 @@ BER can be calculated as the ratio of received bits to errored-bits

### axis_xfer_count register -- Absolute Address: 0x43C00060 +- Absolute Address: 0x60 - Base Offset: 0x60 - Size: 0x4 @@ -561,7 +557,7 @@ BER can be calculated as the ratio of received bits to errored-bits

### Rx_Sample_Discard register -- Absolute Address: 0x43C00064 +- Absolute Address: 0x64 - Base Offset: 0x64 - Size: 0x4 @@ -582,7 +578,7 @@ BER can be calculated as the ratio of received bits to errored-bits

### LPF_Config_2 register -- Absolute Address: 0x43C00068 +- Absolute Address: 0x68 - Base Offset: 0x68 - Size: 0x4 @@ -603,7 +599,7 @@ BER can be calculated as the ratio of received bits to errored-bits

### f1_nco_adjust register -- Absolute Address: 0x43C0006C +- Absolute Address: 0x6C - Base Offset: 0x6C - Size: 0x4 @@ -619,7 +615,7 @@ BER can be calculated as the ratio of received bits to errored-bits

### f2_nco_adjust register -- Absolute Address: 0x43C00070 +- Absolute Address: 0x70 - Base Offset: 0x70 - Size: 0x4 @@ -635,7 +631,7 @@ BER can be calculated as the ratio of received bits to errored-bits

### f1_error register -- Absolute Address: 0x43C00074 +- Absolute Address: 0x74 - Base Offset: 0x74 - Size: 0x4 @@ -651,7 +647,7 @@ BER can be calculated as the ratio of received bits to errored-bits

### f2_error register -- Absolute Address: 0x43C00078 +- Absolute Address: 0x78 - Base Offset: 0x78 - Size: 0x4 @@ -667,7 +663,7 @@ BER can be calculated as the ratio of received bits to errored-bits

### Tx_Sync_Ctrl register -- Absolute Address: 0x43C0007C +- Absolute Address: 0x7C - Base Offset: 0x7C - Size: 0x4 @@ -706,7 +702,7 @@ Both F1 and F2 can be enabled at the same time

### Tx_Sync_Cnt register -- Absolute Address: 0x43C00080 +- Absolute Address: 0x80 - Base Offset: 0x80 - Size: 0x4 @@ -718,11 +714,13 @@ Both F1 and F2 can be enabled at the same time

#### tx_sync_cnt field -

Value from 0x00_0000 to 0xFF_FFFF. This value represents the number bit-times the synchronization signal should be sent after PTT is asserted.

+

Value from 0x00_0000 to 0xFF_FFFF. +This value represents the number bit-times the synchronization +signal should be sent after PTT is asserted.

### lowpass_ema_alpha1 register -- Absolute Address: 0x43C00084 +- Absolute Address: 0x84 - Base Offset: 0x84 - Size: 0x4 @@ -738,7 +736,7 @@ Both F1 and F2 can be enabled at the same time

### lowpass_ema_alpha2 register -- Absolute Address: 0x43C00088 +- Absolute Address: 0x88 - Base Offset: 0x88 - Size: 0x4 @@ -754,7 +752,7 @@ Both F1 and F2 can be enabled at the same time

### rx_power register -- Absolute Address: 0x43C0008C +- Absolute Address: 0x8C - Base Offset: 0x8C - Size: 0x4 diff --git a/rdl/msk_top_regs.pdf b/rdl/outputs/docs/msk_top_regs.pdf similarity index 60% rename from rdl/msk_top_regs.pdf rename to rdl/outputs/docs/msk_top_regs.pdf index e4168d0f15b62638c9812e54a8f3d6db62257574..59a0dda50a5bcf17e93d29e926658db1bd86b449 100644 GIT binary patch delta 44201 zcmZs?Qw5=~~+qP9{+qP}n*?XUVbYJv2akcJaJZrv~F%tmU z_W%(`0?Nk0nP`Yg3Fy+$PEC|V^v%`pBk_>5+cD4ZaiX6qD{Lh1xaKOqEXbr7^(hdKIuIZoiaf?T`7=h&hgF&0O(bMXLqCI2`Va86otKZ zvydY*VVOtYQ1#(qk>fDm4C^SqjQQl$yokY?VLIhTl{x?2+L17xZi_^4A7zBdBx`iC z@x<&%RnlAY`od>P84O!{LwGg z_8U|GpruZ522|>cZxnm(URQ-h_|)ikhpS8J4QlH3x2NlScN6--@)W_hQ*agNa7RuJ zbs(&2_K%#vi~H{K=uZ^mggR(QgYnj8uMH7!2Ww3-!kDPnD#Syzvg`n%9V{nUM+*u% z8m#Ma=?-h7JrFCQ9>C%T^PP7`u-^ee?veCsrh-B$0#2ODl0ES6_hhg@C4qRc1Fw61 z(2oct2H{Fq_9mP~eO_q14e;G=2z6DiJ~ptb-1BoO+!S(8DU%Y879O<#I2S$Av0!|8 zv=Du=0262LTvXH1b66BM+?t)h0gsi~h=QW^*zuBpcUny!YmaP4Nv2y@D;GI`yvFI> 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msk_top_regs_cls +from .sim.msk_top_regs import msk_top_regs_simulator_cls + +if __name__ == '__main__': + + sim = msk_top_regs_simulator_cls(address=0) + + # create an instance of the class + reg_model = msk_top_regs_cls(callbacks=AsyncCallbackSet(read_callback=sim.read, + write_callback=sim.write)) \ No newline at end of file diff --git a/rdl/outputs/python/msk_top_regs/lib/__init__.py b/rdl/outputs/python/msk_top_regs/lib/__init__.py new file mode 100644 index 0000000..fc1b286 --- /dev/null +++ b/rdl/outputs/python/msk_top_regs/lib/__init__.py @@ -0,0 +1,114 @@ +""" +peakrdl-python is a tool to generate Python Register Access Layer (RAL) from SystemRDL +Copyright (C) 2021 - 2023 + +This program is free software: you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation, either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . + +This package is intended to distributed as part of automatically generated code by the PeakRDL +Python tool. It provides a set of classes used by the autogenerated code +""" + +from .callbacks import ReadCallback +from .callbacks import ReadBlockCallback +from .callbacks import WriteCallback +from .callbacks import WriteBlockCallback +from .callbacks import NormalCallbackSet, NormalCallbackSetLegacy +from .callbacks import AsyncCallbackSet, AsyncCallbackSetLegacy +from .callbacks import CallbackSet + +from .base import AddressMap +from .base import RegFile +from .base import AddressMapArray +from .base import RegFileArray + +from .base import AsyncAddressMap +from .base import AsyncRegFile +from .base import AsyncAddressMapArray +from .base import AsyncRegFileArray + +from .register_and_field import Reg +from .register_and_field import RegArray +from .register_and_field import RegisterWriteVerifyError + +from .register_and_field import RegReadOnly +from .register_and_field import RegWriteOnly +from .register_and_field import RegReadWrite +from .register_and_field import WritableRegister +from .register_and_field import ReadableRegister + +from .register_and_field import RegReadOnlyArray +from .register_and_field import RegWriteOnlyArray +from .register_and_field import RegReadWriteArray +from .register_and_field import ReadableRegisterArray +from .register_and_field import WriteableRegisterArray + +from .async_register_and_field import AsyncReg +from .async_register_and_field import AsyncRegArray +from .async_register_and_field import RegAsyncReadOnly +from .async_register_and_field import RegAsyncWriteOnly +from .async_register_and_field import RegAsyncReadWrite +from .async_register_and_field import ReadableAsyncRegister +from .async_register_and_field import WritableAsyncRegister +from .async_register_and_field import RegAsyncReadOnlyArray +from .async_register_and_field import RegAsyncWriteOnlyArray +from .async_register_and_field import RegAsyncReadWriteArray +from .async_register_and_field import ReadableAsyncRegisterArray +from .async_register_and_field import WriteableAsyncRegisterArray + +from .base_field import FieldSizeProps +from .base_field import FieldMiscProps +from .register_and_field import FieldReadOnly +from .register_and_field import FieldWriteOnly +from .register_and_field import FieldReadWrite +from .base_field import Field +from .register_and_field import FieldEnumReadOnly +from .register_and_field import FieldEnumWriteOnly +from .register_and_field import FieldEnumReadWrite +from .base_field import FieldEnum +from .field_encoding import SystemRDLEnum, SystemRDLEnumEntry +from .field_encoding import RegisterFieldJSONEncoder + +from .async_register_and_field import FieldAsyncReadOnly +from .async_register_and_field import FieldAsyncWriteOnly +from .async_register_and_field import FieldAsyncReadWrite +from .async_register_and_field import FieldEnumAsyncReadOnly +from .async_register_and_field import FieldEnumAsyncWriteOnly +from .async_register_and_field import FieldEnumAsyncReadWrite + +from .memory import MemoryReadOnly, MemoryReadOnlyLegacy +from .memory import MemoryWriteOnly, MemoryWriteOnlyLegacy +from .memory import MemoryReadWrite, MemoryReadWriteLegacy +from .memory import MemoryReadOnlyArray +from .memory import MemoryWriteOnlyArray +from .memory import MemoryReadWriteArray +from .async_memory import MemoryAsyncReadOnly, MemoryAsyncReadOnlyLegacy +from .async_memory import MemoryAsyncWriteOnly, MemoryAsyncWriteOnlyLegacy +from .async_memory import MemoryAsyncReadWrite, MemoryAsyncReadWriteLegacy +from .async_memory import MemoryAsyncReadOnlyArray +from .async_memory import MemoryAsyncWriteOnlyArray +from .async_memory import MemoryAsyncReadWriteArray +from .memory import ReadableMemory, ReadableMemoryLegacy +from .memory import WritableMemory, WritableMemoryLegacy +from .memory import Memory +from .async_memory import ReadableAsyncMemory, ReadableAsyncMemoryLegacy +from .async_memory import WritableAsyncMemory, WritableAsyncMemoryLegacy +from .async_memory import AsyncMemory +from .memory import MemoryArray +from .async_memory import AsyncMemoryArray + +from .utility_functions import get_array_typecode +from .utility_functions import UnsupportedWidthError +from .base import Node +from .base import Base +from .base import UDPStruct diff --git a/rdl/outputs/python/msk_top_regs/lib/async_memory.py b/rdl/outputs/python/msk_top_regs/lib/async_memory.py new file mode 100644 index 0000000..427a3cb --- /dev/null +++ b/rdl/outputs/python/msk_top_regs/lib/async_memory.py @@ -0,0 +1,626 @@ +""" +peakrdl-python is a tool to generate Python Register Access Layer (RAL) from SystemRDL +Copyright (C) 2021 - 2023 + +This program is free software: you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation, either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . + +This module is intended to distributed as part of automatically generated code by the +peakrdl-python tool. It provides a set of classes used by the autogenerated code to represent +memories +""" +from array import array as Array +from typing import Union, TYPE_CHECKING +from abc import ABC, abstractmethod +from collections.abc import Iterator +import sys + +from .base import AsyncAddressMap, NodeArray +from .memory import BaseMemory + +from .callbacks import AsyncCallbackSet, AsyncCallbackSetLegacy + +# same bit of code exists in base so flags as duplicate +# pylint: disable=duplicate-code +if sys.version_info >= (3, 10): + # type guarding was introduced in python 3.10 + from typing import TypeGuard +else: + from typing_extensions import TypeGuard +# pylint: enable=duplicate-code + + +if TYPE_CHECKING: + from .async_register_and_field import AsyncReg, AsyncRegArray + from .async_register_and_field import ReadableAsyncRegister, WritableAsyncRegister + from .async_register_and_field import ReadableAsyncRegisterArray, WriteableAsyncRegisterArray +# pylint: disable=duplicate-code + + +class AsyncMemory(BaseMemory, ABC): + """ + base class of non_async memory wrappers + + Note: + It is not expected that this class will be instantiated under normal + circumstances however, it is useful for type checking + """ + __slots__: list[str] = [] + + # pylint: disable=too-many-arguments + def __init__(self, *, + address: int, + width: int, + accesswidth: int, + entries: int, + logger_handle: str, + inst_name: str, + parent: Union[AsyncAddressMap, 'AsyncMemoryArray']): + """ + Initialise the class + + Args: + address: address of the register + width: width of the register in bits + logger_handle: name to be used logging messages associate with thisobject + """ + if not isinstance(parent, (AsyncAddressMap, + MemoryAsyncWriteOnlyArray, MemoryAsyncReadOnlyArray, + MemoryAsyncReadWriteArray)): + raise TypeError(f'parent should be either AddressMap or Memory Array got ' + f'{type(parent)}') + super().__init__(address=address, + logger_handle=logger_handle, + inst_name=inst_name, + width=width, + accesswidth=accesswidth, + entries=entries, + parent=parent) + + @abstractmethod + def get_registers(self, unroll: bool = False) -> \ + Iterator[Union['AsyncReg', 'AsyncRegArray']]: + """ + generator that produces all the readable_registers of this node + + Args: + unroll: Whether to unroll child array or not + """ + + +class _MemoryAsyncReadOnly(AsyncMemory, ABC): + """ + base class of memory wrappers + + Note: + It is not expected that this class will be instantiated under normal + circumstances however, it is useful for type checking + """ + + __slots__: list[str] = [] + + # pylint: disable=too-many-arguments + def __init__(self, *, + address: int, + width: int, + accesswidth: int, + entries: int, + logger_handle: str, + inst_name: str, + parent: Union[AsyncAddressMap, 'AsyncMemoryArray']): + + if not isinstance(parent, (AsyncAddressMap, MemoryAsyncWriteOnlyArray, + MemoryAsyncReadOnlyArray, MemoryAsyncReadWriteArray)): + raise TypeError('parent should be either AddressMap or Memory Array ' + f'got {type(parent)}') + + if not isinstance(parent._callbacks, (AsyncCallbackSet, AsyncCallbackSetLegacy)): + raise TypeError(f'callback set type is wrong, got {type(parent._callbacks)}') + + super().__init__(address=address, + width=width, + accesswidth=accesswidth, + entries=entries, + logger_handle=logger_handle, + inst_name=inst_name, + parent=parent) + + # pylint: enable=too-many-arguments + @property + def _callbacks(self) -> Union[AsyncCallbackSet, AsyncCallbackSetLegacy]: + # pylint: disable=protected-access + if self.parent is None: + raise RuntimeError('Parent must be set') + + if isinstance(self.parent._callbacks, (AsyncCallbackSet, AsyncCallbackSetLegacy)): + return self.parent._callbacks + + raise TypeError(f'unhandled parent callback type: {type(self.parent._callbacks)}') + + async def _read(self, start_entry: int, number_entries: int) -> list[int]: + """ + Read from the memory + + Args: + start_entry: index in the memory to start from, this is not the address + number_entries: number of entries to read + + Returns: data read from memory + + """ + + if not isinstance(start_entry, int): + raise TypeError(f'start_entry should be an int got {type(start_entry)}') + + if not isinstance(number_entries, int): + raise TypeError(f'number_entries should be an int got {type(number_entries)}') + + if start_entry not in range(0, self.entries): + raise ValueError(f'entry must be in range 0 to {self.entries - 1:d} ' + f'but got {start_entry:d}') + + if number_entries not in range(0, self.entries - start_entry + 1): + raise ValueError(f'number_entries must be in range 0 to' + f' {self.entries - start_entry:d} but got {number_entries:d}') + + read_block_callback = self._callbacks.read_block_callback + read_callback = self._callbacks.read_callback + + if read_block_callback is not None: + addr = self.address_lookup(entry=start_entry) + data_read = \ + await read_block_callback(addr=addr, + width=self.width, + accesswidth=self.width, + length=number_entries) + + if isinstance(self._callbacks, AsyncCallbackSet): + if not isinstance(data_read, list): + raise TypeError('The read block callback is expected to return an List') + return data_read + + if isinstance(self._callbacks, AsyncCallbackSetLegacy): + if not isinstance(data_read, Array): + raise TypeError('The read block callback is expected to return an array') + return data_read.tolist() + + raise RuntimeError(f'There is no usable callback block callback:{read_block_callback}') + + if read_callback is not None: + # there is not read_block_callback defined so we must used individual read + data_read = [0 for _ in range(number_entries)] + + for entry in range(number_entries): + entry_address = self.address_lookup(entry=start_entry+entry) + + data_entry = await read_callback(addr=entry_address, + width=self.width, + accesswidth=self.width) + + data_read[entry] = data_entry + + return data_read + + raise RuntimeError(f'There is no usable callback, ' + f'block callback:{read_block_callback}, ' + f'normal callback:{read_callback}') + + async def _read_legacy(self, start_entry: int, number_entries: int) -> Array: + """ + Read from the memory + + Args: + start_entry: index in the memory to start from, this is not the address + number_entries: number of entries to read + + Returns: data read from memory + + """ + + if not isinstance(start_entry, int): + raise TypeError(f'start_entry should be an int got {type(start_entry)}') + + if not isinstance(number_entries, int): + raise TypeError(f'number_entries should be an int got {type(number_entries)}') + + if start_entry not in range(0, self.entries): + raise ValueError(f'entry must be in range 0 to {self.entries - 1:d} ' + f'but got {start_entry:d}') + + if number_entries not in range(0, self.entries - start_entry + 1): + raise ValueError(f'number_entries must be in range 0 to' + f' {self.entries - start_entry:d} but got {number_entries:d}') + + read_block_callback = self._callbacks.read_block_callback + read_callback = self._callbacks.read_callback + + if read_block_callback is not None: + addr = self.address_lookup(entry=start_entry) + data_read = \ + await read_block_callback(addr=addr, + width=self.width, + accesswidth=self.width, + length=number_entries) + + if isinstance(self._callbacks, AsyncCallbackSet): + if not isinstance(data_read, list): + raise TypeError('The read block callback is expected to return an List') + return Array(self.array_typecode, data_read) + + if isinstance(self._callbacks, AsyncCallbackSetLegacy): + if not isinstance(data_read, Array): + raise TypeError('The read block callback is expected to return an array') + return data_read + + raise RuntimeError(f'There is no usable callback block callback:{read_block_callback}') + + if read_callback is not None: + # there is not read_block_callback defined so we must used individual read + data_read_block = Array(self.array_typecode, [0 for _ in range(number_entries)]) + + for entry in range(number_entries): + entry_address = self.address_lookup(entry=start_entry + entry) + data_entry = await read_callback(addr=entry_address, + width=self.width, + accesswidth=self.width) + + data_read_block[entry] = data_entry + + return data_read_block + + raise RuntimeError(f'There is no usable callback, ' + f'block callback:{read_block_callback}, ' + f'normal callback:{read_callback}') + + def get_readable_registers(self, unroll: bool = False) -> \ + Iterator[Union['ReadableAsyncRegister', 'ReadableAsyncRegisterArray']]: + """ + generator that produces all the readable_registers of this node + + Args: + unroll: Whether to unroll child array or not + """ + def is_readable(item: Union['AsyncReg', 'AsyncRegArray']) -> \ + TypeGuard[Union['ReadableAsyncRegister', 'ReadableAsyncRegisterArray']]: + # pylint: disable-next=protected-access + return item._is_readable + + return filter(is_readable, self.get_registers(unroll=unroll)) + + +class MemoryAsyncReadOnly(_MemoryAsyncReadOnly, ABC): + """ + base class of memory wrappers + + Note: + It is not expected that this class will be instantiated under normal + circumstances however, it is useful for type checking + """ + __slots__: list[str] = [] + + async def read(self, start_entry: int, number_entries: int) -> list[int]: + """ + Read from the memory + + Args: + start_entry: index in the memory to start from, this is not the address + number_entries: number of entries to read + + Returns: data read from memory + + """ + return await self._read(start_entry=start_entry, number_entries=number_entries) + + +class MemoryAsyncReadOnlyLegacy(_MemoryAsyncReadOnly, ABC): + """ + base class of memory wrappers + + Note: + It is not expected that this class will be instantiated under normal + circumstances however, it is useful for type checking + """ + __slots__: list[str] = [] + + async def read(self, start_entry: int, number_entries: int) -> Array: + """ + Read from the memory + + Args: + start_entry: index in the memory to start from, this is not the address + number_entries: number of entries to read + + Returns: data read from memory + + """ + return await self._read_legacy(start_entry=start_entry, number_entries=number_entries) + + +class _MemoryAsyncWriteOnly(AsyncMemory, ABC): + """ + base class of memory wrappers + + Note: + It is not expected that this class will be instantiated under normal + circumstances however, it is useful for type checking + """ + + __slots__: list[str] = [] + + # pylint: disable=too-many-arguments + def __init__(self, *, + address: int, + width: int, + accesswidth: int, + entries: int, + logger_handle: str, + inst_name: str, + parent: Union[AsyncAddressMap, 'AsyncMemoryArray']): + + if not isinstance(parent, (AsyncAddressMap, MemoryAsyncWriteOnlyArray, + MemoryAsyncReadOnlyArray, MemoryAsyncReadWriteArray)): + raise TypeError('parent should be either AddressMap or Memory Array ' + f'got {type(parent)}') + if not isinstance(parent._callbacks, (AsyncCallbackSet, AsyncCallbackSetLegacy)): + raise TypeError(f'callback set type is wrong, got {type(parent._callbacks)}') + + super().__init__(address=address, + width=width, + accesswidth=accesswidth, + entries=entries, + logger_handle=logger_handle, + inst_name=inst_name, + parent=parent) + + # pylint: enable=too-many-arguments + @property + def _callbacks(self) -> Union[AsyncCallbackSet, AsyncCallbackSetLegacy]: + # pylint: disable=protected-access + if self.parent is None: + raise RuntimeError('Parent must be set') + + if isinstance(self.parent._callbacks, (AsyncCallbackSet, AsyncCallbackSetLegacy)): + return self.parent._callbacks + + raise TypeError(f'unhandled parent callback type: {type(self.parent._callbacks)}') + + async def _write(self, start_entry: int, data: Union[Array, list[int]]) -> None: + """ + Asynchronously write data to memory + + Args: + start_entry: index in the memory to start from, this is not the address + data: data to write + + Returns: None + + """ + # pylint:disable=too-many-branches + if not isinstance(start_entry, int): + raise TypeError(f'start_entry should be an int got {type(start_entry)}') + + if start_entry not in range(0, self.entries): + raise ValueError(f'entry must be in range 0 to {self.entries - 1:d} ' + f'but got {start_entry:d}') + + if not isinstance(data, (list, Array)): + raise TypeError(f'data should be an array.array got {type(data)}') + + if len(data) not in range(0, self.entries - start_entry + 1): + raise ValueError(f'data length must be in range 0 to {self.entries - start_entry:d} ' + f'but got {len(data):d}') + + if self._callbacks.write_block_callback is not None: + + addr = self.address_lookup(entry=start_entry) + if isinstance(self._callbacks, AsyncCallbackSet): + if isinstance(data, Array): + await self._callbacks.write_block_callback(addr=addr, + width=self.width, + accesswidth=self.width, + data=data.tolist()) + else: + await self._callbacks.write_block_callback(addr=addr, + width=self.width, + accesswidth=self.width, + data=data) + if isinstance(self._callbacks, AsyncCallbackSetLegacy): + if isinstance(data, list): + # need to convert the data to an array before calling + await self._callbacks.write_block_callback( + addr=addr, + width=self.width, + accesswidth=self.width, + data=Array(self.array_typecode, data)) + else: + await self._callbacks.write_block_callback(addr=addr, + width=self.width, + accesswidth=self.width, + data=data) + + elif self._callbacks.write_callback is not None: + # there is not write_block_callback defined so we must used individual write + for entry_index, entry_data in enumerate(data): + entry_address = self.address_lookup(entry=start_entry+entry_index) + await self._callbacks.write_callback(addr=entry_address, + width=self.width, + accesswidth=self.width, + data=entry_data) + + else: + raise RuntimeError('No suitable callback') + + def get_writable_registers(self, unroll: bool = False) -> \ + Iterator[Union['WritableAsyncRegister', 'WriteableAsyncRegisterArray']]: + """ + generator that produces all the readable_registers of this node + + Args: + unroll: Whether to unroll child array or not + """ + def is_writable(item: Union['AsyncReg', 'AsyncRegArray']) -> \ + TypeGuard[Union['WritableAsyncRegister', 'WriteableAsyncRegisterArray']]: + # pylint: disable-next=protected-access + return item._is_writeable + + return filter(is_writable, self.get_registers(unroll=unroll)) + + +class MemoryAsyncWriteOnly(_MemoryAsyncWriteOnly, ABC): + """ + base class of memory wrappers + + Note: + It is not expected that this class will be instantiated under normal + circumstances however, it is useful for type checking + """ + __slots__: list[str] = [] + + async def write(self, start_entry: int, data: list[int]) -> None: + """ + Asynchronously write data to memory + + Args: + start_entry: index in the memory to start from, this is not the address + data: data to write + + Returns: None + + """ + if not isinstance(data, list): + raise TypeError(f'data should be an List got {type(data)}') + return await self._write(start_entry=start_entry, data=data) + + +class MemoryAsyncWriteOnlyLegacy(_MemoryAsyncWriteOnly, ABC): + """ + base class of memory wrappers + + Note: + It is not expected that this class will be instantiated under normal + circumstances however, it is useful for type checking + """ + __slots__: list[str] = [] + + async def write(self, start_entry: int, data: Array) -> None: + """ + Asynchronously write data to memory + + Args: + start_entry: index in the memory to start from, this is not the address + data: data to write + + Returns: None + + """ + if not isinstance(data, Array): + raise TypeError(f'data should be an Array {type(data)}') + return await self._write(start_entry=start_entry, data=data) + + +class MemoryAsyncReadWrite(MemoryAsyncReadOnly, MemoryAsyncWriteOnly, ABC): + """ + base class of memory wrappers + + Note: + It is not expected that this class will be instantiated under normal + circumstances however, it is useful for type checking + """ + + __slots__: list[str] = [] + + +class MemoryAsyncReadWriteLegacy(MemoryAsyncReadOnlyLegacy, MemoryAsyncWriteOnlyLegacy, ABC): + """ + base class of memory wrappers + + Note: + It is not expected that this class will be instantiated under normal + circumstances however, it is useful for type checking + """ + + __slots__: list[str] = [] + + +class MemoryAsyncReadOnlyArray(NodeArray, ABC): + """ + base class for a array of asynchronous read only memories + """ + __slots__: list[str] = [] + + # pylint: disable-next=too-many-arguments + def __init__(self, *, + logger_handle: str, inst_name: str, + parent: AsyncAddressMap, + address: int, + stride: int, + dimensions: tuple[int, ...]): + + if not isinstance(parent, AsyncAddressMap): + raise TypeError(f'parent should be either AsyncAddressMap got {type(parent)}') + + super().__init__(logger_handle=logger_handle, inst_name=inst_name, + parent=parent, address=address, + stride=stride, dimensions=dimensions) + + +class MemoryAsyncWriteOnlyArray(NodeArray, ABC): + """ + base class for a array of asynchronous write only memories + """ + __slots__: list[str] = [] + + # pylint: disable-next=too-many-arguments + def __init__(self, *, + logger_handle: str, inst_name: str, + parent: AsyncAddressMap, + address: int, + stride: int, + dimensions: tuple[int, ...]): + + if not isinstance(parent, AsyncAddressMap): + raise TypeError(f'parent should be either AsyncAddressMap got {type(parent)}') + + super().__init__(logger_handle=logger_handle, inst_name=inst_name, + parent=parent, address=address, + stride=stride, dimensions=dimensions) + + +class MemoryAsyncReadWriteArray(MemoryAsyncReadOnlyArray, MemoryAsyncWriteOnlyArray, ABC): + """ + base class for a array of asynchronous read and write memories + """ + __slots__: list[str] = [] + + # pylint: disable-next=too-many-arguments + def __init__(self, *, + logger_handle: str, inst_name: str, + parent: AsyncAddressMap, + address: int, + stride: int, + dimensions: tuple[int, ...]): + + if not isinstance(parent, AsyncAddressMap): + raise TypeError(f'parent should be either AsyncAddressMap got {type(parent)}') + + super().__init__(logger_handle=logger_handle, inst_name=inst_name, + parent=parent, address=address, + stride=stride, dimensions=dimensions) + + +ReadableAsyncMemory = Union[MemoryAsyncReadOnly, MemoryAsyncReadWrite] +WritableAsyncMemory = Union[MemoryAsyncWriteOnly, MemoryAsyncReadWrite] +ReadableAsyncMemoryLegacy = Union[MemoryAsyncReadOnlyLegacy, MemoryAsyncReadWriteLegacy] +WritableAsyncMemoryLegacy = Union[MemoryAsyncWriteOnlyLegacy, MemoryAsyncReadWriteLegacy] +AsyncMemoryArray = Union[MemoryAsyncReadOnlyArray, MemoryAsyncWriteOnlyArray, + MemoryAsyncReadWriteArray] diff --git a/rdl/outputs/python/msk_top_regs/lib/async_register_and_field.py b/rdl/outputs/python/msk_top_regs/lib/async_register_and_field.py new file mode 100644 index 0000000..cf5bed3 --- /dev/null +++ b/rdl/outputs/python/msk_top_regs/lib/async_register_and_field.py @@ -0,0 +1,1230 @@ +""" +peakrdl-python is a tool to generate Python Register Access Layer (RAL) from SystemRDL +Copyright (C) 2021 - 2023 + +This program is free software: you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation, either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . + +This module is intended to distributed as part of automatically generated code by the +peakrdl-python tool. It provides a set of classes used by the autogenerated code to represent +asynchronous registers and fields +""" +from enum import Enum +from typing import Union, Optional, TypeVar, cast +from collections.abc import AsyncGenerator, Iterator +from abc import ABC, abstractmethod +from contextlib import asynccontextmanager +from array import array as Array +import sys +from warnings import warn + +from .utility_functions import get_array_typecode +from .base import AsyncAddressMap, AsyncRegFile +from .async_memory import MemoryAsyncReadOnly, MemoryAsyncWriteOnly, MemoryAsyncReadWrite, \ + AsyncMemory, ReadableAsyncMemory, WritableAsyncMemory +from .async_memory import MemoryAsyncReadOnlyLegacy, MemoryAsyncWriteOnlyLegacy, \ + MemoryAsyncReadWriteLegacy +from .async_memory import ReadableAsyncMemoryLegacy, WritableAsyncMemoryLegacy +from .callbacks import AsyncCallbackSet, AsyncCallbackSetLegacy +from .base_register import BaseReg, BaseRegArray, RegisterWriteVerifyError +from .base_field import FieldEnum, FieldSizeProps, FieldMiscProps, \ + _FieldReadOnlyFramework, _FieldWriteOnlyFramework, FieldType + +# pylint: disable=duplicate-code +if sys.version_info >= (3, 11): + from typing import Self +else: + from typing_extensions import Self +# pylint: enable=duplicate-code + +# pylint: disable=duplicate-code +if sys.version_info >= (3, 10): + # type guarding was introduced in python 3.10 + from typing import TypeGuard +else: + from typing_extensions import TypeGuard +# pylint: enable=duplicate-code + +# pylint: disable=redefined-slots-in-subclass,too-many-lines + + +class AsyncReg(BaseReg, ABC): + """ + base class of async register wrappers + + Note: + It is not expected that this class will be instantiated under normal + circumstances however, it is useful for type checking + """ + + __slots__: list[str] = [] + + # pylint: disable=too-many-arguments,duplicate-code + def __init__(self, *, + address: int, + width: int, + accesswidth: int, + logger_handle: str, + inst_name: str, + parent: Union[AsyncAddressMap, AsyncRegFile, AsyncMemory, 'AsyncRegArray']): + + if not isinstance(parent, (AsyncAddressMap, AsyncRegFile, + MemoryAsyncReadOnly, MemoryAsyncWriteOnly, + MemoryAsyncReadWrite, AsyncRegArray, MemoryAsyncReadOnlyLegacy, + MemoryAsyncWriteOnlyLegacy, + MemoryAsyncReadWriteLegacy)): + raise TypeError(f'bad parent type got: {type(parent)}') + + if not isinstance(parent._callbacks, (AsyncCallbackSet, AsyncCallbackSetLegacy)): + raise TypeError(f'callback set type is wrong, got {type(parent._callbacks)}') + + super().__init__(address=address, width=width, accesswidth=accesswidth, + logger_handle=logger_handle, inst_name=inst_name, parent=parent) + + @property + def _callbacks(self) -> Union[AsyncCallbackSet, AsyncCallbackSetLegacy]: + # pylint: disable=protected-access + if self.parent is None: + raise RuntimeError('Parent must be set') + + if isinstance(self.parent._callbacks, (AsyncCallbackSet, AsyncCallbackSetLegacy)): + return self.parent._callbacks + + raise TypeError(f'unhandled parent callback type: {type(self.parent._callbacks)}') + + @property + @abstractmethod + def fields(self) -> \ + Iterator[Union['FieldAsyncReadOnly', 'FieldAsyncWriteOnly', 'FieldAsyncReadWrite']]: + """ + generator that produces has all the fields within the register + """ + + +class RegAsyncReadOnly(AsyncReg, ABC): + """ + class for an async read only register + + Args: + address: address of the register + width: width of the register in bits + accesswidth: minimum access width of the register in bits + logger_handle: name to be used logging messages associate with this + object + + """ + + __slots__: list[str] = ['__in_context_manager', '__register_state'] + + # pylint: disable=too-many-arguments, duplicate-code + def __init__(self, *, + address: int, + width: int, + accesswidth: int, + logger_handle: str, + inst_name: str, + parent: Union[AsyncAddressMap, AsyncRegFile, ReadableAsyncMemory, + ReadableAsyncMemoryLegacy]): + + super().__init__(address=address, + logger_handle=logger_handle, + inst_name=inst_name, + parent=parent, width=width, accesswidth=accesswidth) + + self.__in_context_manager: bool = False + self.__register_state: int = 0 + # pylint: enable=too-many-arguments, duplicate-code + + @asynccontextmanager + async def single_read(self) -> AsyncGenerator[Self]: + """ + Context manager to allow multiple field accesses to be performed with a single + read of the register + """ + self.__register_state = await self.read() + # pylint: disable=duplicate-code + self.__in_context_manager = True + # this try/finally is needed to make sure that in the event of an exception + # the state flags are not left incorrectly set + try: + yield self + finally: + self.__in_context_manager = False + + async def read(self) -> int: + """Asynchronously read value from the register + + Returns: + The value from register + + """ + # pylint: disable=duplicate-code + if self.__in_context_manager: + return self.__register_state + + read_block_callback = self._callbacks.read_block_callback + read_callback = self._callbacks.read_callback + # pylint: enable=duplicate-code + + if read_callback is not None: + + return await read_callback(addr=self.address, + width=self.width, + accesswidth=self.accesswidth) + + if read_block_callback is not None: + array_read_result = \ + await read_block_callback(addr=self.address, + width=self.width, + accesswidth=self.accesswidth, + length=1) + return array_read_result[0] + + raise RuntimeError('This function does not have a useable callback') + + @property + def readable_fields(self) -> Iterator[Union['FieldAsyncReadOnly', 'FieldAsyncReadWrite']]: + """ + generator that produces has all the readable fields within the register + """ + def is_readable(field: Union['FieldAsyncReadOnly', + 'FieldAsyncWriteOnly', + 'FieldAsyncReadWrite']) -> \ + TypeGuard[Union['FieldAsyncReadOnly', 'FieldAsyncReadWrite']]: + return isinstance(field, (FieldAsyncReadOnly, FieldAsyncReadWrite)) + + return filter(is_readable, self.fields) + + async def read_fields(self) -> dict['str', Union[bool, Enum, int]]: + """ + asynchronously read the register and return a dictionary of the field values + """ + return_dict: dict['str', Union[bool, Enum, int]] = {} + async with self.single_read() as reg: + for field in reg.readable_fields: + return_dict[field.inst_name] = await field.read() + + return return_dict + + @property + def _is_readable(self) -> bool: + return True + + @property + def _is_writeable(self) -> bool: + return False + + +class RegAsyncWriteOnly(AsyncReg, ABC): + """ + class for an asynchronous write only register + """ + + __slots__: list[str] = [] + + # pylint: disable=too-many-arguments, duplicate-code, useless-parent-delegation + def __init__(self, *, + address: int, + width: int, + accesswidth: int, + logger_handle: str, + inst_name: str, + parent: Union[AsyncAddressMap, AsyncRegFile, + WritableAsyncMemory, WritableAsyncMemoryLegacy]): + + super().__init__(address=address, + logger_handle=logger_handle, + inst_name=inst_name, + parent=parent, width=width, accesswidth=accesswidth) + # pylint: enable=too-many-arguments, duplicate-code + + async def write(self, data: int) -> None: + """Asynchronously writes a value to the register + + Args: + data: data to be written + + Raises: + ValueError: if the value provided is outside the range of the + permissible values for the register + TypeError: if the type of data is wrong + """ + + # this method check the types and range checks the data + self._validate_data(data=data) + + # pylint: disable=duplicate-code + self._logger.info('Writing data:%X to %X', data, self.address) + # pylint: enable=duplicate-code + + if self._callbacks.write_callback is not None: + + await self._callbacks.write_callback(addr=self.address, + width=self.width, + accesswidth=self.accesswidth, + data=data) + + elif self._callbacks.write_block_callback is not None: + + if isinstance(self._callbacks, AsyncCallbackSetLegacy): + data_as_array = Array(get_array_typecode(self.width), [data]) + await self._callbacks.write_block_callback(addr=self.address, + width=self.width, + accesswidth=self.accesswidth, + data=data_as_array) + + if isinstance(self._callbacks, AsyncCallbackSet): + await self._callbacks.write_block_callback(addr=self.address, + width=self.width, + accesswidth=self.accesswidth, + data=[data]) + + else: + # pylint: disable-next=duplicate-code + raise RuntimeError('This function does not have a useable callback') + + @property + def writable_fields(self) -> Iterator[Union['FieldAsyncWriteOnly', 'FieldAsyncReadWrite']]: + """ + generator that produces has all the writable fields within the register + """ + def is_writable(field: Union['FieldAsyncReadOnly', + 'FieldAsyncWriteOnly', + 'FieldAsyncReadWrite']) -> \ + TypeGuard[Union['FieldAsyncWriteOnly', 'FieldAsyncReadWrite']]: + return isinstance(field, (FieldAsyncWriteOnly, FieldAsyncReadWrite)) + + return filter(is_writable, self.fields) + + @abstractmethod + async def write_fields(self, **kwargs) -> None: # type: ignore[no-untyped-def] + """ + Do an async write to the register, updating any field included in + the arguments + """ + + @property + def _is_readable(self) -> bool: + return False + + @property + def _is_writeable(self) -> bool: + return True + + +class RegAsyncReadWrite(RegAsyncReadOnly, RegAsyncWriteOnly, ABC): + """ + class for an async read and write only register + + """ + __slots__: list[str] = ['__in_read_write_context_manager', '__in_read_context_manager', + '__register_state'] + + # pylint: disable=too-many-arguments, duplicate-code + def __init__(self, *, + address: int, + width: int, + accesswidth: int, + logger_handle: str, + inst_name: str, + parent: Union[AsyncAddressMap, AsyncRegFile, MemoryAsyncReadWrite, + MemoryAsyncReadWriteLegacy]): + + super().__init__(address=address, + logger_handle=logger_handle, + inst_name=inst_name, + parent=parent, width=width, accesswidth=accesswidth) + + self.__in_read_write_context_manager: bool = False + self.__in_read_context_manager: bool = False + self.__register_state: Optional[int] = None + + # pylint: enable=too-many-arguments, duplicate-code + + @asynccontextmanager + async def single_read_modify_write(self, verify: bool = False, skip_write: bool = False) -> \ + AsyncGenerator[Self]: + """ + Context manager to allow multiple field reads/write to be done with a single set of + field operations + + Args: + verify (bool): very the write with a read afterwards + skip_write (bool): skip the write back at the end + + """ + # pylint: disable=duplicate-code + if self.__in_read_context_manager: + raise RuntimeError('using the `single_read_modify_write` context manager within the ' + 'single_read` is not permitted') + + if skip_write is True: + warn('The `skip_write` argument will be removed in the future, use `single_read`' + ' instead', + DeprecationWarning, stacklevel=2) + # pylint: enable=duplicate-code + + self.__register_state = await self.read() + + # pylint: disable=duplicate-code + self.__in_read_write_context_manager = True + # this try/finally is needed to make sure that in the event of an exception + # the state flags are not left incorrectly set + try: + yield self + finally: + self.__in_read_write_context_manager = False + # pylint: enable=duplicate-code + if not skip_write: + await self.write(self.__register_state, verify) + + # clear the register states at the end of the context manager + self.__register_state = None + + @asynccontextmanager + async def single_read(self) -> \ + AsyncGenerator[Self]: + """ + Context manager to allow multiple field reads with a single register read + """ + # pylint: disable=duplicate-code + if self.__in_read_write_context_manager: + raise RuntimeError('using the `single_read` context manager within the ' + 'single_read_modify_write` is not permitted') + self.__in_read_context_manager = True + # pylint: enable=duplicate-code + try: + async with super().single_read() as reg: + yield reg + finally: + # pylint: disable=duplicate-code + self.__in_read_context_manager = False + + async def write(self, data: int, verify: bool = False) -> None: + """ + Writes a value to the register + + Args: + data: data to be written + verify: set to True to read back the register to verify the read has occurred correctly + + Raises: + ValueError: if the value provided is outside the range of the + permissible values for the register + TypeError: if the type of data is wrong + RegisterWriteVerifyError: the read back data after the write does not match the + expected value + """ + if self.__in_read_context_manager: + # pylint: disable=duplicate-code + raise RuntimeError('writes within the single read context manager are not permitted') + + if self.__in_read_write_context_manager: + # pylint: disable=duplicate-code + if self.__register_state is None: + raise RuntimeError('The internal register state should never be None in the ' + 'context manager') + self.__register_state = data + else: + await super().write(data) + if verify: + read_back = await self.read() + if read_back != data: + raise RegisterWriteVerifyError(f'Readback {read_back:X} ' + f'after writing {data:X}') + + async def read(self) -> int: + """ + Asynchronously read value from the register + """ + if self.__in_read_write_context_manager: + # pylint: disable=duplicate-code + if self.__register_state is None: + raise RuntimeError('The internal register state should never be None in the ' + 'context manager') + return self.__register_state + + # the single read context manager is handled in the base class so does need any + # handling here + + return await super().read() + + async def read_fields(self) -> dict['str', Union[bool, Enum, int]]: + """ + asynchronously read the register and return a dictionary of the field values + """ + return_dict: dict['str', Union[bool, Enum, int]] = {} + async with self.single_read() as reg: + for field in reg.readable_fields: + return_dict[field.inst_name] = await field.read() + + return return_dict + + async def write_fields(self, **kwargs) -> None: # type: ignore[no-untyped-def] + """ + asynchronously read-modify-write to the register, updating any field included in + the arguments + """ + if len(kwargs) == 0: + raise ValueError('no command args') + + async with self.single_read_modify_write() as reg: + for field_name, field_value in kwargs.items(): + if field_name not in reg.systemrdl_python_child_name_map.values(): + raise ValueError(f'{field_name} is not a member of the register') + + field = getattr(reg, field_name) + await field.write(field_value) + + @property + def _is_readable(self) -> bool: + return True + + @property + def _is_writeable(self) -> bool: + return True + + +ReadableAsyncRegister = Union[RegAsyncReadOnly, RegAsyncReadWrite] +WritableAsyncRegister = Union[RegAsyncWriteOnly, RegAsyncReadWrite] + + +# pylint: disable-next=invalid-name +AsyncRegArrayElementType= TypeVar('AsyncRegArrayElementType', bound=AsyncReg) + + +class AsyncRegArray(BaseRegArray, ABC): + """ + base class of register array wrappers + + Note: + It is not expected that this class will be instantiated under normal + circumstances however, it is useful for type checking + """ + # pylint: disable=too-many-arguments,duplicate-code + + __slots__: list[str] = ['__in_context_manager', '__register_cache', + '__register_address_array'] + + def __init__(self, *, + logger_handle: str, inst_name: str, + parent: Union[AsyncAddressMap, AsyncRegFile, AsyncMemory], + width: int, + accesswidth: int, + address: int, + stride: int, + dimensions: tuple[int, ...], + elements: Optional[dict[tuple[int, ...], AsyncRegArrayElementType]] = None): + + self.__in_context_manager: bool = False + self.__register_cache: Optional[Union[Array, list[int]]] = None + self.__register_address_array: Optional[list[int]] = None + + if not isinstance(parent._callbacks, (AsyncCallbackSet, AsyncCallbackSetLegacy)): + raise TypeError(f'callback set type is wrong, got {type(parent._callbacks)}') + + super().__init__(logger_handle=logger_handle, inst_name=inst_name, + parent=parent, address=address, width=width, accesswidth=accesswidth, + stride=stride, dimensions=dimensions, elements=elements) + + @property + def __empty_array_cache(self) -> Array: + return Array(get_array_typecode(self.width), self.__empty_list_cache) + + @property + def __empty_list_cache(self) -> list[int]: + return [0 for _ in range(self.__number_cache_entries)] + + async def __block_read_legacy(self) -> Array: + """ + Read all the contents of the array in the most optimal way, ideally with a block operation + """ + if not isinstance(self._callbacks, AsyncCallbackSetLegacy): + raise RuntimeError('This function should only be used with legacy callbacks') + + read_block_callback = self._callbacks.read_block_callback + read_callback = self._callbacks.read_callback + + if read_block_callback is not None: + + data_read = await read_block_callback(addr=self.address, + width=self.width, + accesswidth=self.accesswidth, + length=self.__number_cache_entries) + + if not isinstance(data_read, Array): + raise TypeError('The read block callback is expected to return an array') + + return data_read + + if read_callback is not None: + # there is not read_block_callback defined so we must used individual read + data_array = self.__empty_array_cache + + if self.__register_address_array is None: + raise RuntimeError('This address array has not be initialised') + + for entry, address in enumerate(self.__register_address_array): + data_entry = await read_callback(addr=address, + width=self.width, + accesswidth=self.accesswidth) + + data_array[entry] = data_entry + + return data_array + + raise RuntimeError('There is no usable callback') + + async def __block_write_legacy(self, data: Array, verify: bool) -> None: + """ + Write all the contents of the array in the most optimal way, ideally with a block operation + """ + if not isinstance(self._callbacks, AsyncCallbackSetLegacy): + raise RuntimeError('This function should only be used with legacy callbacks') + + write_block_callback = self._callbacks.write_block_callback + write_callback = self._callbacks.write_callback + + if write_block_callback is not None: + await write_block_callback(addr=self.address, + width=self.width, + accesswidth=self.width, + data=data) + + elif write_callback is not None: + # there is not write_block_callback defined so we must used individual write + + if self.__register_address_array is None: + raise RuntimeError('This address array has not be initialised') + + for entry_index, entry_data in enumerate(data): + entry_address = self.__register_address_array[entry_index] + await write_callback(addr=entry_address, + width=self.width, + accesswidth=self.accesswidth, + data=entry_data) + + else: + raise RuntimeError('No suitable callback') + + if verify: + read_back_verify_data = self.__block_read_legacy() + if read_back_verify_data != data: + raise RegisterWriteVerifyError('Read back block miss-match') + + async def __block_read(self) -> list[int]: + """ + Read all the contents of the array in the most optimal way, ideally with a block operation + """ + if not isinstance(self._callbacks, AsyncCallbackSet): + raise RuntimeError('This function should only be used with non-legacy callbacks') + + read_block_callback = self._callbacks.read_block_callback + read_callback = self._callbacks.read_callback + + if read_block_callback is not None: + data_read = \ + await read_block_callback(addr=self.address, + width=self.width, + accesswidth=self.accesswidth, + length=self.__number_cache_entries) + + + if not isinstance(data_read, list): + raise TypeError('The read block callback is expected to return an array') + + return data_read + + if read_callback is not None: + # there is not read_block_callback defined so we must used individual read + data_list = self.__empty_list_cache + + if self.__register_address_array is None: + raise RuntimeError('This address array has not be initialised') + + for entry, address in enumerate(self.__register_address_array): + data = await read_callback(addr=address, + width=self.width, + accesswidth=self.accesswidth) + + data_list[entry] = data + + return data_list + + raise RuntimeError('There is no usable callback') + + async def __block_write(self, data: list[int], verify: bool) -> None: + """ + Write all the contents of the array in the most optimal way, ideally with a block operation + """ + if not isinstance(self._callbacks, AsyncCallbackSet): + raise RuntimeError('This function should only be used with non-legacy callbacks') + + write_block_callback = self._callbacks.write_block_callback + write_callback = self._callbacks.write_callback + + if write_block_callback is not None: + await write_block_callback(addr=self.address, + width=self.width, + accesswidth=self.width, + data=data) + elif write_callback is not None: + # there is not write_block_callback defined so we must used individual write + + if self.__register_address_array is None: + raise RuntimeError('This address array has not be initialised') + + for entry_index, entry_data in enumerate(data): + entry_address = self.__register_address_array[entry_index] + await write_callback(addr=entry_address, + width=self.width, + accesswidth=self.accesswidth, + data=entry_data) + + else: + raise RuntimeError('No suitable callback') + + if verify: + read_back_verify_data = self.__block_read() + if read_back_verify_data != data: + raise RegisterWriteVerifyError('Read back block miss-match') + + def __cache_entry(self, addr: int, width: int, accesswidth: int) -> int: + """ + Validate the data provided and determine the cache entry + + Args: + addr: Address to write to + width: Width of the register in bits + accesswidth: Minimum access width of the register in bits + + Returns: + cache entry + + """ + if not isinstance(width, int): + raise TypeError(f'Width should be an int byt got {type(width)}') + if width != self.width: + raise ValueError('Requested Read width does not match the expected value') + if not isinstance(accesswidth, int): + raise TypeError(f'accesswidth should be an int byt got {type(accesswidth)}') + if accesswidth != self.accesswidth: + raise ValueError('Requested Read accesswidth does not match the expected value') + if not isinstance(addr, int): + raise TypeError(f'addr should be an int byt got {type(addr)}') + if not self.address <= addr < (self.address + self.size): + raise ValueError(f'Requested address 0x{addr:X} is out of range 0x{self.address:X} to ' + f'0x{self.address + self.size - (self.width >> 3):X}') + cache_entry = (addr - self.address) // (self.width >> 3) + if self.__register_address_array is None: + raise RuntimeError('The address table should always be populated here') + if self.__register_address_array[cache_entry] != addr: + raise RuntimeError(f'The calculated cache entry for address 0x{addr:X}') + return cache_entry + + async def __cache_read(self, addr: int, width: int, accesswidth: int) -> int: + """ + Used to replace the normal callbacks with those that access the cache + + Args: + addr: Address to write to + width: Width of the register in bits + accesswidth: Minimum access width of the register in bits + + Returns: + value inputted by the used + """ + if self.__register_cache is None: + raise RuntimeError('The cache array should be initialised') + return self.__register_cache[self.__cache_entry(addr=addr, + width=width, + accesswidth=accesswidth)] + + async def __cache_write(self, addr: int, width: int, accesswidth: int, data: int) -> None: + """ + Used to replace the normal callbacks with those that access the cache + + Args: + addr: Address to write to + width: Width of the register in bits + accesswidth: Minimum access width of the register in bits + data: value to be written to the register + + Returns: + None + """ + if not isinstance(data, int): + raise TypeError(f'Data should be an int byt got {type(data)}') + if self.__register_cache is None: + raise RuntimeError('The cache array should be initialised') + self.__register_cache[self.__cache_entry(addr=addr, + width=width, + accesswidth=accesswidth)] = data + + @property + def __cache_callbacks(self) -> AsyncCallbackSet: + return AsyncCallbackSet(read_callback=self.__cache_read, + write_callback=self.__cache_write) + + @property + def __number_cache_entries(self) -> int: + return self.size // (self.width >> 3) + + async def __initialise_cache(self, skip_initial_read: bool) -> Union[Array, list[int]]: + if isinstance(self._callbacks, AsyncCallbackSet): + if skip_initial_read: + return self.__empty_list_cache + return await self.__block_read() + + if isinstance(self._callbacks, AsyncCallbackSetLegacy): + if skip_initial_read: + return self.__empty_array_cache + return await self.__block_read_legacy() + + raise TypeError('Unhandled callback type') + + @asynccontextmanager + async def _cached_access(self, verify: bool = False, skip_write: bool = False, + skip_initial_read: bool = False) -> \ + AsyncGenerator[Self]: + """ + Context manager to allow multiple field reads/write to be done with a single set of + field operations + + Args: + verify (bool): very the write with a read afterwards + skip_write (bool): skip the write back at the end + + """ + self.__register_address_array = \ + [self.address + (i * (self.width >> 3)) for i in range(self.__number_cache_entries)] + self.__register_cache = await self.__initialise_cache(skip_initial_read=skip_initial_read) + self.__in_context_manager = True + # this try/finally is needed to make sure that in the event of an exception + # the state flags are not left incorrectly set + try: + yield self + finally: + self.__in_context_manager = False + if not skip_write: + if isinstance(self._callbacks, AsyncCallbackSet): + if not isinstance(self.__register_cache, list): + raise TypeError('Register cache should be a list in non-legacy mode') + await self.__block_write(self.__register_cache, verify) + if isinstance(self._callbacks, AsyncCallbackSetLegacy): + if not isinstance(self.__register_cache, Array): + raise TypeError('Register cache should be a Array in legacy mode') + await self.__block_write_legacy(self.__register_cache, verify) + + # clear the register states at the end of the context manager + self.__register_address_array = None + self.__register_cache = None + + @property + def _callbacks(self) -> Union[AsyncCallbackSet, AsyncCallbackSetLegacy]: + # pylint: disable=protected-access + if self.__in_context_manager: + return self.__cache_callbacks + + if self.parent is None: + raise RuntimeError('Parent must be set') + + if isinstance(self.parent._callbacks, (AsyncCallbackSet, AsyncCallbackSetLegacy)): + return self.parent._callbacks + + raise TypeError(f'unhandled parent callback type: {type(self.parent._callbacks)}') + + +class RegAsyncReadOnlyArray(AsyncRegArray, ABC): + """ + base class for a array of async read only registers + """ + __slots__: list[str] = [] + + # pylint: disable=too-many-arguments,duplicate-code + def __init__(self, *, + logger_handle: str, inst_name: str, + parent: Union[AsyncRegFile, AsyncAddressMap, ReadableAsyncMemory, + ReadableAsyncMemoryLegacy], + address: int, + width: int, + accesswidth: int, + stride: int, + dimensions: tuple[int, ...], + elements: Optional[dict[tuple[int, ...], RegAsyncReadOnly]] = None): + + if not isinstance(parent, (AsyncRegFile, AsyncAddressMap, + MemoryAsyncReadOnly, MemoryAsyncReadOnlyLegacy, + MemoryAsyncReadWrite, MemoryAsyncReadWriteLegacy)): + raise TypeError('parent should be either AsyncRegFile, AsyncAddressMap, ' + 'MemoryAsyncReadOnly, MemoryAsyncReadWrite ' + f'got {type(parent)}') + + super().__init__(logger_handle=logger_handle, inst_name=inst_name, + parent=parent, address=address, width=width, accesswidth=accesswidth, + stride=stride, dimensions=dimensions, elements=elements) + # pylint: enable=too-many-arguments,duplicate-code + + @asynccontextmanager + async def single_read(self) -> AsyncGenerator[Self]: + """ + Context manager to allow multiple field reads/write to be done with a single set of + field operations + + Args: + + + Returns: + + """ + async with self._cached_access(verify=False, skip_write=True, + skip_initial_read=False) as reg_array: + yield reg_array + + @property + def _is_readable(self) -> bool: + return True + + @property + def _is_writeable(self) -> bool: + return False + + +class RegAsyncWriteOnlyArray(AsyncRegArray, ABC): + """ + base class for a array of async write only registers + """ + __slots__: list[str] = [] + + # pylint: disable=too-many-arguments,duplicate-code + def __init__(self, *, + logger_handle: str, inst_name: str, + parent: Union[AsyncRegFile, AsyncAddressMap, + WritableAsyncMemory, WritableAsyncMemoryLegacy], + address: int, + width: int, + accesswidth: int, + stride: int, + dimensions: tuple[int, ...], + elements: Optional[dict[tuple[int, ...], RegAsyncWriteOnly]] = None): + + if not isinstance(parent, (AsyncRegFile, AsyncAddressMap, + MemoryAsyncWriteOnly, MemoryAsyncReadWrite, + MemoryAsyncWriteOnlyLegacy, MemoryAsyncReadWriteLegacy)): + raise TypeError('parent should be either AsyncRegFile, AsyncAddressMap, ' + 'MemoryAsyncWriteOnly, MemoryAsyncReadWrite ' + f'got {type(parent)}') + + super().__init__(logger_handle=logger_handle, inst_name=inst_name, + parent=parent, address=address, width=width, accesswidth=accesswidth, + stride=stride, dimensions=dimensions, elements=elements) + # pylint: enable=too-many-arguments,duplicate-code + + @asynccontextmanager + async def single_write(self) -> AsyncGenerator[Self]: + """ + Context manager to allow multiple field reads/write to be done with a single set of + field operations + + Args: + + + Returns: + + """ + async with self._cached_access(verify=False, skip_write=False, + skip_initial_read=True) as reg_array: + yield reg_array + + @property + def _is_readable(self) -> bool: + return False + + @property + def _is_writeable(self) -> bool: + return True + + +class RegAsyncReadWriteArray(AsyncRegArray, ABC): + """ + base class for a array of read and write registers + """ + __slots__: list[str] = [] + + # pylint: disable=too-many-arguments,duplicate-code + def __init__(self, *, + logger_handle: str, inst_name: str, + parent: Union[AsyncRegFile, AsyncAddressMap, + MemoryAsyncReadWrite, MemoryAsyncReadWriteLegacy], + address: int, + width: int, + accesswidth: int, + stride: int, + dimensions: tuple[int, ...], + elements: Optional[dict[tuple[int, ...], RegAsyncReadWrite]] = None): + + if not isinstance(parent, (AsyncRegFile, AsyncAddressMap, + MemoryAsyncReadWrite, MemoryAsyncReadWriteLegacy)): + raise TypeError('parent should be either AsyncRegFile, AsyncAddressMap, ' + 'MemoryAsyncReadWrite ' + f'got {type(parent)}') + + super().__init__(logger_handle=logger_handle, inst_name=inst_name, + parent=parent, address=address, width=width, accesswidth=accesswidth, + stride=stride, dimensions=dimensions, elements=elements) + # pylint: enable=too-many-arguments,duplicate-code + + @asynccontextmanager + async def single_read_modify_write(self, verify: bool = False, skip_write: bool = False) -> \ + AsyncGenerator[Self]: + """ + Context manager to allow multiple field reads/write to be done with a single set of + field operations + + Args: + verify (bool): very the write with a read afterwards + skip_write (bool): skip the write back at the end + + Returns: + + """ + if skip_write is True: + warn('The `skip_write` argument will be removed in the future, use `single_read`' + ' instead', + DeprecationWarning, stacklevel=2) + + async with self._cached_access(verify=verify, skip_write=skip_write, + skip_initial_read=False) as reg_array: + yield reg_array + + @property + def _is_readable(self) -> bool: + return True + + @property + def _is_writeable(self) -> bool: + return True + + +ReadableAsyncRegisterArray = Union[RegAsyncReadOnlyArray, RegAsyncReadWriteArray] +WriteableAsyncRegisterArray = Union[RegAsyncWriteOnlyArray, RegAsyncReadWriteArray] + + +class FieldAsyncReadOnly(_FieldReadOnlyFramework[FieldType], ABC): + """ + class for an asynchronous read only register field + + Args: + parent_register: register within which the field resides + size_props: object defining the msb, lsb, high bit, low bit and width + logger_handle: name to be used logging messages associate with this + object + + """ + __slots__: list[str] = [] + + # pylint: disable-next=too-many-arguments + def __init__(self, *, + parent_register: ReadableAsyncRegister, + size_props: FieldSizeProps, + misc_props: FieldMiscProps, + logger_handle: str, + inst_name: str, + field_type:type[FieldType]): + + if not isinstance(parent_register, (RegAsyncReadWrite, RegAsyncReadOnly)): + raise TypeError(f'size_props must be of {type(RegAsyncReadWrite)} or ' + f'{type(RegAsyncReadOnly)} but got {type(parent_register)}') + + # pylint: disable=duplicate-code + super().__init__(logger_handle=logger_handle, + size_props=size_props, + misc_props=misc_props, + parent_register=parent_register, + inst_name=inst_name, + field_type=field_type) + # pylint: enable=duplicate-code + + async def read(self) -> FieldType: # pylint: disable=invalid-overridden-method + """ + Asynchronously reads the register that this field is located in and retries the field + value applying the required masking and shifting + + Returns: + field value + + """ + return self._decode_read_value(await self.parent_register.read()) + + @property + def parent_register(self) -> ReadableAsyncRegister: + """ + parent register the field is placed in + """ + + # this cast is OK because an explict typing check was done in the __init__ + return cast(ReadableAsyncRegister, self.parent) + + +class FieldAsyncWriteOnly(_FieldWriteOnlyFramework[FieldType], ABC): + """ + class for an asynchronous write only register field + + Args: + parent_register: register within which the field resides + size_props: object defining the msb, lsb, high bit, low bit and width + logger_handle: name to be used logging messages associate with this + object + + """ + __slots__: list[str] = [] + + # pylint: disable-next=too-many-arguments + def __init__(self, *, + parent_register: WritableAsyncRegister, + size_props: FieldSizeProps, + misc_props: FieldMiscProps, + logger_handle: str, + inst_name: str, + field_type:type[FieldType]): + + if not isinstance(parent_register, (RegAsyncReadWrite, RegAsyncWriteOnly)): + raise TypeError(f'size_props must be of {type(RegAsyncReadWrite)} or ' + f'{type(RegAsyncWriteOnly)} but got {type(parent_register)}') + + # pylint: disable=duplicate-code + super().__init__(logger_handle=logger_handle, + size_props=size_props, + misc_props=misc_props, + parent_register=parent_register, + inst_name=inst_name, + field_type=field_type) + # pylint: enable=duplicate-code + + async def write(self, value: FieldType) -> None: # pylint: disable=invalid-overridden-method + """ + The behaviour of this method depends on whether the field is located in + a readable register or not: + + If the register is readable, the method will perform an async read-modify-write + on the register updating the field with the value provided + + If the register is not writable all other field values will be asynchronously written + with zero. + + Args: + value: field value to update to + + """ + encoded_value = self._encode_write_value(value) + + if (self.high == (self.register_data_width - 1)) and (self.low == 0): + # special case where the field occupies the whole register, + # there a straight write can be performed + new_reg_value = encoded_value + else: + # do a read, modify write + if isinstance(self.parent_register, RegAsyncReadWrite): + reg_value = await self.parent_register.read() + masked_reg_value = reg_value & self.inverse_bitmask + new_reg_value = masked_reg_value | encoded_value + elif isinstance(self.parent_register, RegAsyncWriteOnly): + new_reg_value = encoded_value + else: + raise TypeError('Unhandled parent type') + + await self.parent_register.write(new_reg_value) + + @property + def parent_register(self) -> WritableAsyncRegister: + """ + parent register the field is placed in + """ + + # this cast is OK because an explict typing check was done in the __init__ + return cast(WritableAsyncRegister, self.parent) + + +class FieldAsyncReadWrite(FieldAsyncReadOnly[FieldType], FieldAsyncWriteOnly[FieldType], ABC): + """ + class for an asynchronous read/write register field + + Args: + parent_register: register within which the field resides + size_props: object defining the msb, lsb, high bit, low bit and width + logger_handle: name to be used logging messages associate with this + object + + """ + __slots__: list[str] = [] + + # pylint: disable-next=too-many-arguments + def __init__(self, *, + parent_register: RegAsyncReadWrite, + size_props: FieldSizeProps, + misc_props: FieldMiscProps, + logger_handle: str, + inst_name: str, + field_type:type[FieldType]): + + if not isinstance(parent_register, RegAsyncReadWrite): + raise TypeError(f'size_props must be of {type(RegAsyncReadWrite)} ' + f'but got {type(parent_register)}') + + # pylint: disable=duplicate-code + super().__init__(logger_handle=logger_handle, + size_props=size_props, + misc_props=misc_props, + parent_register=parent_register, + inst_name=inst_name, + field_type=field_type) + # pylint: enable=duplicate-code + + @property + def parent_register(self) -> RegAsyncReadWrite: + """ + parent register the field is placed in + """ + + # this cast is OK because an explict typing check was done in the __init__ + return cast(RegAsyncReadWrite, self.parent) + + +class FieldEnumAsyncReadWrite(FieldAsyncReadWrite[FieldType], FieldEnum[FieldType], ABC): + """ + class for an async read/write register field with an enumerated value + """ + __slots__: list[str] = [] + + @property + def parent_register(self) -> RegAsyncReadWrite: + """ + parent register the field is placed in + """ + + # this cast is OK because an explict typing check was done in the __init__ + return cast(RegAsyncReadWrite, self.parent) + + +class FieldEnumAsyncReadOnly(FieldAsyncReadOnly[FieldType], FieldEnum[FieldType], ABC): + """ + class for an async read only register field with an enumerated value + """ + __slots__: list[str] = [] + + +class FieldEnumAsyncWriteOnly(FieldAsyncWriteOnly[FieldType], FieldEnum[FieldType], ABC): + """ + class for an async write only register field with an enumerated value + """ + __slots__: list[str] = [] diff --git a/rdl/outputs/python/msk_top_regs/lib/base.py b/rdl/outputs/python/msk_top_regs/lib/base.py new file mode 100644 index 0000000..c99cc7e --- /dev/null +++ b/rdl/outputs/python/msk_top_regs/lib/base.py @@ -0,0 +1,942 @@ +""" +peakrdl-python is a tool to generate Python Register Access Layer (RAL) from SystemRDL +Copyright (C) 2021 - 2023 + +This program is free software: you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation, either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . + +This module is intended to distributed as part of automatically generated code by the +peakrdl-python tool. It provides a set of base classes used by the autogenerated code +""" +from __future__ import annotations +import logging +import warnings +from typing import Optional, Union, TYPE_CHECKING, TypeVar, Any +from collections.abc import Iterator, Sequence +from abc import ABC, abstractmethod +from itertools import product, chain +from functools import reduce +from operator import mul +import sys +from enum import IntEnum + +from .callbacks import CallbackSet, CallbackSetLegacy +from .callbacks import NormalCallbackSet, AsyncCallbackSet +from .callbacks import NormalCallbackSetLegacy, AsyncCallbackSetLegacy + +if sys.version_info >= (3, 10): + # type guarding was introduced in python 3.10 + from typing import TypeGuard +else: + from typing_extensions import TypeGuard + +if TYPE_CHECKING: + from .memory import Memory, MemoryArray + from .async_memory import AsyncMemory, AsyncMemoryArray + from .register_and_field import Reg, RegArray + from .register_and_field import WritableRegister, ReadableRegister + from .async_register_and_field import AsyncReg, AsyncRegArray + from .async_register_and_field import ReadableAsyncRegister, WritableAsyncRegister + from .register_and_field import ReadableRegisterArray, WriteableRegisterArray + from .async_register_and_field import ReadableAsyncRegisterArray, WriteableAsyncRegisterArray + +UDPStruct = dict[str, 'UDPType'] +UDPType = Union[str, int, bool, IntEnum, UDPStruct] + +class Base(ABC): + """ + base class of for all types + """ + __slots__: list[str] = ['__logger', '__inst_name', '__parent'] + + def __init__(self, *, + logger_handle: str, inst_name: str, parent: Optional[Union['Node', 'NodeArray']]): + + if not isinstance(logger_handle, str): + raise TypeError(f'logger_handle should be str but got {type(logger_handle)}') + + self.__logger = logging.getLogger(logger_handle) + self._logger.debug('creating instance of %s', self.__class__) + + if not isinstance(inst_name, str): + raise TypeError(f'inst_name should be str but got {type(inst_name)}') + self.__inst_name = inst_name + + if parent is not None: + if not isinstance(parent, (Node, NodeArray)): + raise TypeError(f'parent should be Node or Node Array but got {type(parent)}') + self.__parent = parent + + @property + def _logger(self) -> logging.Logger: + return self.__logger + + @property + def inst_name(self) -> str: + """ + systemRDL name of the instance in the parent + """ + return self.__inst_name + + @property + def parent(self) -> Optional[Union['Node', 'NodeArray']]: + """ + parent of the node or field, or None if it has no parent + """ + return self.__parent + + @property + def full_inst_name(self) -> str: + """ + The full hierarchical systemRDL name of the instance + """ + if self.parent is not None: + if isinstance(self.parent, NodeArray): + if self.parent.parent is None: + raise RuntimeError('A node array must have a parent it can not be the ' + 'top level') + return self.parent.parent.full_inst_name + "." + self.inst_name + + return self.parent.full_inst_name + "." + self.inst_name + + return self.inst_name + + @property + def udp(self) -> UDPStruct: + """ + A dictionary of the user defined properties for the node + """ + return {} + + @property + def rdl_name(self) -> Optional[str]: + """ + The systemRDL name property for the item + """ + return None + + @property + def rdl_desc(self) -> Optional[str]: + """ + The systemRDL desc property for the item + """ + return None + + +class Node(Base, ABC): + """ + base class of for all types with an address i.e. not fields + + Note: + It is not expected that this class will be instantiated under normal + circumstances however, it is useful for type checking + """ + + __slots__ = ['__address'] + + def __init__(self, *, + address: int, + logger_handle: str, + inst_name: str, + parent: Optional[Union['Node', 'NodeArray']]): + super().__init__(logger_handle=logger_handle, inst_name=inst_name, parent=parent) + + if not isinstance(address, int): + raise TypeError(f'address should be int but got {type(address)}') + + self.__address = address + + @property + def address(self) -> int: + """ + address of the node + """ + return self.__address + + @property + @abstractmethod + def _callbacks(self) -> Union[CallbackSet, CallbackSetLegacy]: + ... + + @property + @abstractmethod + def systemrdl_python_child_name_map(self) -> dict[str, str]: + """ + In some cases systemRDL names need to be converted make them python safe, this dictionary + is used to map the original systemRDL names to the names of the python attributes of this + class + + Returns: dictionary whose key is the systemRDL names and value it the property name + """ + + def get_child_by_system_rdl_name(self, name: Any) -> Any: + """ + returns a child node by its systemRDL name + + Args: + name: name of the node in the systemRDL + + Returns: Node + + """ + if not isinstance(name, str): + raise TypeError(f'name must be a string got {type(name)}') + return getattr(self, self.systemrdl_python_child_name_map[name]) + + @property + @abstractmethod + def size(self) -> int: + """ + Total Number of bytes of address the node occupies + """ + + +# pylint: disable-next=invalid-name +NodeArrayElementType = TypeVar('NodeArrayElementType', bound=Node) + + +class NodeArray(Base, Sequence[NodeArrayElementType]): + """ + base class of for all array types + """ + + # pylint: disable=too-few-public-methods + __slots__: list[str] = ['__elements', '__address', + '__stride', '__dimensions'] + + # pylint: disable-next=too-many-arguments + def __init__(self, *, logger_handle: str, + inst_name: str, + parent: Node, + address: int, + stride: int, + dimensions: tuple[int, ...], + elements: Optional[dict[tuple[int, ...], NodeArrayElementType]] = None): + + super().__init__(logger_handle=logger_handle, inst_name=inst_name, parent=parent) + + if not isinstance(address, int): + raise TypeError(f'address should be a int but got {type(dimensions)}') + self.__address = address + if not isinstance(stride, int): + raise TypeError(f'stride should be a int but got {type(dimensions)}') + self.__stride = stride + + if not isinstance(dimensions, tuple): + raise TypeError(f'dimensions should be a tuple but got {type(dimensions)}') + for dimension in dimensions: + if not isinstance(dimension, int): + raise TypeError(f'dimension should be a int but got {type(dimension)}') + self.__dimensions = dimensions + + # There are two use cases for this class: + # 1. Initial creation - elements is None in which case the data is populated + # 2. Creating a recursive version of itself, this happens when it is sliced by the parent + # in which case a subset of the elements is presented and a new instance + + if elements is not None: + self.__check_init_element(elements) + self.__elements = elements + else: + new_elements: dict[tuple[int, ...], NodeArrayElementType] = {} + for indices in product(*[range(dim) for dim in self.dimensions]): + new_elements[indices] = self._build_element(indices=indices) + + self.__elements = new_elements + + def _build_element(self, indices: tuple[int, ...]) -> NodeArrayElementType: + + return self._element_datatype( + logger_handle=self._build_element_logger_handle(indices=indices), + address=self._address_calculator(indices), + inst_name=self._build_element_inst_name(indices=indices), + parent=self) + + def _build_element_logger_handle(self, indices: tuple[int, ...]) -> str: + """ + Build the logger handle for an element in the array + + Args: + indices: element index + + Returns: + """ + return self._logger.name + '[' + ','.join([str(item) for item in indices]) + ']' + + def _build_element_inst_name(self, indices: tuple[int, ...]) -> str: + """ + Build the logger handle for an element in the array + + Args: + indices: element index + + Returns: + """ + return self.inst_name + '[' + ']['.join([str(item) for item in indices]) + ']' + + def __check_init_element(self, elements: dict[tuple[int, ...], NodeArrayElementType]) -> None: + """ + Used in the __init__ to check that the elements passed in are valid + Args: + elements: proposed element of the array + + Returns: + + """ + if not isinstance(elements, dict): + raise TypeError(f'elements should be a dictionary but got {type(elements)}') + + for index, item in elements.items(): + if not isinstance(index, tuple): + raise TypeError(f'element index should be a tuple but got {type(index)}') + + if len(index) != len(self.dimensions): + raise ValueError(f'size of index does not match index length = {len(index)}') + + for index_pos, index_item in enumerate(index): + if not isinstance(index_item, int): + raise TypeError(f'element index_item should be a int ' + f'but got {type(index_item)}') + + if not 0 <= index_item < self.dimensions[index_pos]: + raise ValueError('index outside of range of dimensions') + + if not isinstance(item, self._element_datatype): + raise TypeError(f'elements should be a {self._element_datatype} ' + f'but got {type(item)}') + + def _address_calculator(self, indices: tuple[int, ...]) -> int: + def cal_addr(dimensions: tuple[int,...], indices: tuple[int, ...], base_address: int, + stride: int) -> int: + """ + Calculates the address of an register within an array + + :param dimensions: list of the array dimensions + :param indices: list of the array indices (length must match the dimensions) + :param base_address: base address of the array + :param stride: address stride of of the array + :return: address of the register + """ + if len(dimensions) == 1: + return (indices[0] * stride) + base_address + + outer_offset = reduce(mul, dimensions[1::], 1) * stride * indices[0] + return outer_offset + cal_addr(dimensions=dimensions[1::], + indices=indices[1::], + stride=self.stride, + base_address=self.address) + + return cal_addr(self.dimensions, base_address=self.address, + stride=self.stride, indices=indices) + + def _sub_instance(self, elements: dict[tuple[int, ...], NodeArrayElementType]) -> \ + NodeArray[NodeArrayElementType]: + if not isinstance(self.parent, Node): + raise RuntimeError('Parent of a Node Array must be Node') + return self.__class__(logger_handle=self._logger.name, + inst_name=self.inst_name, + parent=self.parent, + address=self.address, + stride=self.stride, + dimensions=self.dimensions, + elements=elements) + + def __getitem__(self, item): # type: ignore[no-untyped-def] + if len(self.dimensions) > 1: + return self.__getitem_nd(item) + + if isinstance(item, tuple): + raise IndexError('attempting a multidimensional array access on a single dimension' + ' array') + + if isinstance(item, slice): + + valid_items = [(i,) for i in range(*item.indices(self.dimensions[0]))] + def filter_1d_func(to_filter:tuple[tuple[int, ...], NodeArrayElementType]) -> bool: + index, _ = to_filter + if index in valid_items: + return True + return False + + return self._sub_instance(elements=dict(filter(filter_1d_func, self.items()))) + + if isinstance(item, int): + if (item, ) not in self.__elements: + raise IndexError(f'{item:d} in in the array') + return self.__elements[(item, )] + + raise TypeError(f'Array index must either being an int or a slice, got {type(item)}') + + def __getitem_nd(self, item): # type: ignore[no-untyped-def] + + if isinstance(item, tuple): + + if len(item) != len(self.dimensions): + raise ValueError('When using a multidimensional access, the size must match the' + ' dimensions of the array, array dimensions ' + f'are {len(self.dimensions)}') + + if all(isinstance(i, int) for i in item): + # single item access + if item not in self.__elements: + msg = 'index[' + ','.join([str(i) for i in item]) + '] not in array' + raise IndexError(msg) + return self.__elements[item] + + unpack_index_set = [] + for axis, sub_index in enumerate(item): + if isinstance(sub_index, int): + if not 0 <= sub_index < self.dimensions[axis]: + raise IndexError(f'{sub_index:d} out of range for dimension {axis}') + unpack_index_set.append((sub_index,)) + continue + + if isinstance(sub_index, slice): + unpack_index_set.append(range(*sub_index.indices(self.dimensions[axis]))) + continue + + raise TypeError(f'unhandle index of {type(sub_index)} in position {axis:d}') + + valid_items = tuple(product(*unpack_index_set)) + + def filter_nd_func(to_filter: tuple[tuple[int, ...], NodeArrayElementType]) -> bool: + index, _ = to_filter + if index in valid_items: + return True + return False + + return self._sub_instance(elements=dict(filter(filter_nd_func, self.items()))) + + raise IndexError('attempting a single dimensional array access on a multidimension' + ' array') + + def __len__(self) -> int: + return len(self.__elements) + + def __iter__(self) -> Iterator[NodeArrayElementType]: + yield from self.__elements.values() + + def items(self) -> Iterator[tuple[tuple[int, ...], NodeArrayElementType]]: + """ + iterate through all the items in an array but also return the index of the array + """ + yield from self.__elements.items() + + @property + def dimensions(self) -> Union[tuple[int, ...], tuple[int]]: + """ + Dimensions of the array + """ + return self.__dimensions + + @property + @abstractmethod + def _element_datatype(self) -> type[NodeArrayElementType]: + ... + + @property + def address(self) -> int: + """ + address of the node + """ + return self.__address + + @property + def stride(self) -> int: + """ + address stride of the array + """ + return self.__stride + + @property + def _callbacks(self) -> Union[CallbackSet, CallbackSetLegacy]: + if self.parent is None: + raise RuntimeError('Parent must be set') + # pylint: disable-next=protected-access + return self.parent._callbacks + + @property + def size(self) -> int: + """ + Total Number of bytes of address the array occupies + """ + return reduce(mul, self.dimensions, 1) * self.stride + + +class BaseSection(Node, ABC): + """ + base class of non-async and sync sections (AddressMaps and RegFile) + + Note: + It is not expected that this class will be instantiated under normal + circumstances however, it is useful for type checking + """ + __slots__: list[str] = [] + + @abstractmethod + def get_children(self, unroll: bool = False) -> Iterator[Union[Node, NodeArray]]: + """ + generator that produces all the readable_registers of this node + + Args: + unroll: Whether to unroll child array or not + """ + + +class Section(BaseSection, ABC): + """ + base class of non-async sections (AddressMaps and RegFile) + + Note: + It is not expected that this class will be instantiated under normal + circumstances however, it is useful for type checking + """ + __slots__: list[str] = [] + + def get_writable_registers(self, unroll:bool=False) -> \ + Iterator[Union[WritableRegister, WriteableRegisterArray]]: + """ + generator that produces all the readable_registers of this node + + Args: + unroll: Whether to unroll child array or not + """ + def is_writable(item: Union[Reg, RegArray]) -> \ + TypeGuard[Union[WritableRegister, WriteableRegisterArray]]: + # pylint: disable-next=protected-access + return item._is_writeable + + return filter(is_writable, self.get_registers(unroll=unroll)) + + def get_readable_registers(self, unroll: bool = False) -> \ + Iterator[Union[ReadableRegister, ReadableRegisterArray]]: + """ + generator that produces all the readable_registers of this node + + Args: + unroll: Whether to unroll child array or not + """ + def is_readable(item: Union[Reg, RegArray]) ->\ + TypeGuard[Union[ReadableRegister, ReadableRegisterArray]]: + # pylint: disable-next=protected-access + return item._is_readable + + return filter(is_readable, self.get_registers(unroll=unroll)) + + @abstractmethod + def get_registers(self, unroll: bool = False) -> \ + Iterator[Union[Reg, RegArray]]: + """ + generator that produces all the readable_registers of this node + + Args: + unroll: Whether to unroll child array or not + """ + + +class AddressMap(Section, ABC): + """ + base class of address map wrappers + + Note: + It is not expected that this class will be instantiated under normal + circumstances however, it is useful for type checking + """ + __slots__: list[str] = ['__callbacks'] + + def __init__(self, *, + callbacks: Optional[Union[NormalCallbackSet, NormalCallbackSetLegacy]], + address: int, + logger_handle: str, + inst_name: str, + parent: Optional['AddressMap']): + + # only the top-level address map should have callbacks assigned, everything else should + # use its parent callback + if parent is None: + if not isinstance(callbacks, (NormalCallbackSet, NormalCallbackSetLegacy)): + raise TypeError(f'callback type wrong, got {type(callbacks)}') + if isinstance(callbacks, NormalCallbackSetLegacy): + warnings.warn('Support for the legacy callback using the array types will be ' + 'withdrawn in the future, please consider changing to the list ' + 'versions', category=DeprecationWarning) + self.__callbacks = callbacks + else: + if not callbacks is None: + raise RuntimeError('Callbacks must be None when a parent is set') + if not isinstance(parent._callbacks, (NormalCallbackSet, NormalCallbackSetLegacy)): + raise TypeError(f'callback type wrong, got {type(callbacks)}') + + super().__init__(address=address, + logger_handle=logger_handle, + inst_name=inst_name, + parent=parent) + + @abstractmethod + def get_sections(self, unroll: bool = False) -> \ + Iterator[Union['AddressMap', RegFile, AddressMapArray, RegFileArray]]: + """ + generator that produces all the AddressMap and RegFile children of this node + + Args: + unroll: Whether to unroll child array or not + + Returns: + + """ + + @abstractmethod + def get_memories(self, unroll: bool = False) -> \ + Iterator[Union['Memory', 'MemoryArray']]: + """ + generator that produces all the Memory children of this node + + Args: + unroll: Whether to unroll child array or not + + Returns: + + """ + + def get_children(self, unroll: bool = False) -> Iterator[Union[Node, NodeArray]]: + return chain(self.get_registers(unroll=unroll), + self.get_sections(unroll=unroll), + self.get_memories(unroll=unroll)) + + @property + def _callbacks(self) -> Union[NormalCallbackSet, NormalCallbackSetLegacy]: + # pylint: disable=protected-access + if self.parent is None: + return self.__callbacks + + if isinstance(self.parent._callbacks, (NormalCallbackSet, NormalCallbackSetLegacy)): + return self.parent._callbacks + + raise TypeError(f'unhandled parent callback type: {type(self.parent._callbacks)}') + + +class AsyncSection(BaseSection, ABC): + """ + base class of async sections (AddressMaps and RegFile) + + Note: + It is not expected that this class will be instantiated under normal + circumstances however, it is useful for type checking + """ + __slots__: list[str] = [] + + def get_writable_registers(self, unroll: bool = False) -> \ + Iterator[Union[WritableAsyncRegister, WriteableAsyncRegisterArray]]: + """ + generator that produces all the readable_registers of this node + + Args: + unroll: Whether to unroll child array or not + """ + def is_writable(item: Union[AsyncReg, AsyncRegArray]) -> \ + TypeGuard[Union[WritableAsyncRegister, WriteableAsyncRegisterArray]]: + # pylint: disable-next=protected-access + return item._is_writeable + + return filter(is_writable, self.get_registers(unroll=unroll)) + + def get_readable_registers(self, unroll: bool = False) -> \ + Iterator[Union[ReadableAsyncRegister, ReadableAsyncRegisterArray]]: + """ + generator that produces all the readable_registers of this node + + Args: + unroll: Whether to unroll child array or not + """ + def is_readable(item: Union[AsyncReg, AsyncRegArray]) -> \ + TypeGuard[Union[ReadableAsyncRegister, ReadableAsyncRegisterArray]]: + # pylint: disable-next=protected-access + return item._is_readable + + return filter(is_readable, self.get_registers(unroll=unroll)) + + + @abstractmethod + def get_registers(self, unroll: bool = False) -> \ + Iterator[Union[AsyncReg, AsyncRegArray]]: + """ + generator that produces all the readable_registers of this node + + Args: + unroll: Whether to unroll child array or not + """ + + @property + @abstractmethod + def _callbacks(self) -> Union[AsyncCallbackSet, AsyncCallbackSetLegacy]: + ... + + +class AsyncAddressMap(AsyncSection, ABC): + """ + base class of address map wrappers + + Note: + It is not expected that this class will be instantiated under normal + circumstances however, it is useful for type checking + """ + + __slots__: list[str] = ['__callbacks'] + + def __init__(self, *, + callbacks: Optional[Union[AsyncCallbackSet, AsyncCallbackSetLegacy]], + address: int, + logger_handle: str, + inst_name: str, + parent: Optional['AsyncAddressMap']): + + # only the top-level address map should have callbacks assigned, everything else should + # use its parent callback + if parent is None: + if not isinstance(callbacks, (AsyncCallbackSet, AsyncCallbackSetLegacy)): + raise TypeError(f'callback type wrong, got {type(callbacks)}') + if isinstance(callbacks, AsyncCallbackSetLegacy): + warnings.warn('Support for the legacy callback using the array types will be ' + 'withdrawn in the future, please consider changing to the list ' + 'versions', category=DeprecationWarning) + self.__callbacks = callbacks + else: + if not callbacks is None: + raise RuntimeError('Callbacks must be None when a parent is set') + if not isinstance(parent._callbacks, (AsyncCallbackSet, AsyncCallbackSetLegacy)): + raise TypeError(f'callback type wrong, got {type(callbacks)}') + + super().__init__(address=address, + logger_handle=logger_handle, + inst_name=inst_name, + parent=parent) + + @abstractmethod + def get_sections(self, unroll: bool = False) -> \ + Iterator[Union['AsyncAddressMap', AsyncRegFile, + AsyncAddressMapArray, AsyncRegFileArray]]: + """ + generator that produces all the AddressMap and RegFile children of this node + + Args: + unroll: Whether to unroll child array or not + + Returns: + + """ + + @abstractmethod + def get_memories(self, unroll: bool = False) -> \ + Iterator[Union['AsyncMemory', 'AsyncMemoryArray']]: + """ + generator that produces all the Memory children of this node + + Args: + unroll: Whether to unroll child array or not + + Returns: + + """ + + @property + def _callbacks(self) -> Union[AsyncCallbackSet, AsyncCallbackSetLegacy]: + # pylint: disable=protected-access + if self.parent is None: + return self.__callbacks + + if isinstance(self.parent._callbacks, (AsyncCallbackSet, AsyncCallbackSetLegacy)): + return self.parent._callbacks + + raise TypeError(f'unhandled parent callback type: {type(self.parent._callbacks)}') + + def get_children(self, unroll: bool = False) -> Iterator[Union[Node, NodeArray]]: + return chain(self.get_registers(unroll=unroll), self.get_sections(unroll=unroll), + self.get_memories(unroll=unroll)) + + +class AddressMapArray(NodeArray, ABC): + """ + base class for a array of address maps + """ + __slots__: list[str] = [] + + # pylint: disable-next=too-many-arguments + def __init__(self, *, logger_handle: str, inst_name: str, + parent: AddressMap, + address: int, + stride: int, + dimensions: tuple[int, ...]): + + super().__init__(logger_handle=logger_handle, inst_name=inst_name, + parent=parent, address=address, stride=stride, dimensions=dimensions) + + +class AsyncAddressMapArray(NodeArray, ABC): + """ + base class for a array of address maps + """ + __slots__: list[str] = [] + + # pylint: disable-next=too-many-arguments + def __init__(self, *, logger_handle: str, inst_name: str, + parent: AsyncAddressMap, + address: int, + stride: int, + dimensions: tuple[int, ...]): + + super().__init__(logger_handle=logger_handle, inst_name=inst_name, + parent=parent, address=address, + stride=stride, dimensions=dimensions) + + +class RegFile(Section, ABC): + """ + base class of register file wrappers + + Note: + It is not expected that this class will be instantiated under normal + circumstances however, it is useful for type checking + """ + + __slots__: list[str] = [] + + def __init__(self, *, + address: int, + logger_handle: str, + inst_name: str, + parent: Union[AddressMap, 'RegFile']): + + if not isinstance(parent._callbacks, (NormalCallbackSet, NormalCallbackSetLegacy)): + raise TypeError(f'parent._callbacks type wrong, got {type(parent._callbacks)}') + + super().__init__(address=address, + logger_handle=logger_handle, + inst_name=inst_name, + parent=parent) + + @abstractmethod + def get_sections(self, unroll: bool = False) -> \ + Iterator[Union['RegFile','RegFileArray']]: + """ + generator that produces all the RegFile children of this node + + Args: + unroll: Whether to unroll child array or not + + Returns: + + """ + + @property + def _callbacks(self) -> Union[NormalCallbackSet, NormalCallbackSetLegacy]: + # pylint: disable=protected-access + if self.parent is None: + raise RuntimeError('Parent must be set') + + if isinstance(self.parent._callbacks, (NormalCallbackSet, NormalCallbackSetLegacy)): + return self.parent._callbacks + + raise TypeError(f'unhandled parent callback type: {type(self.parent._callbacks)}') + + def get_children(self, unroll: bool = False) -> Iterator[Union[Node, NodeArray]]: + return chain(self.get_registers(unroll=unroll), self.get_sections(unroll=unroll)) + + +class AsyncRegFile(AsyncSection, ABC): + """ + base class of register file wrappers + + Note: + It is not expected that this class will be instantiated under normal + circumstances however, it is useful for type checking + """ + + __slots__: list[str] = [] + + def __init__(self, *, + address: int, + logger_handle: str, + inst_name: str, + parent: Union[AsyncAddressMap, 'AsyncRegFile']): + super().__init__(address=address, + logger_handle=logger_handle, + inst_name=inst_name, + parent=parent) + + if not isinstance(parent._callbacks, (AsyncCallbackSet, AsyncCallbackSetLegacy)): + raise TypeError(f'parent._callbacks type wrong, got {type(parent._callbacks)}') + + @abstractmethod + def get_sections(self, unroll: bool = False) -> \ + Iterator[Union['AsyncRegFile','AsyncRegFileArray']]: + """ + generator that produces all the RegFile children of this node + + Args: + unroll: Whether to unroll child array or not + + Returns: + + """ + + def get_children(self, unroll: bool = False) -> Iterator[Union[Node, NodeArray]]: + return chain(self.get_registers(unroll=unroll), self.get_sections(unroll=unroll)) + + @property + def _callbacks(self) -> Union[AsyncCallbackSet, AsyncCallbackSetLegacy]: + # pylint: disable=protected-access + if self.parent is None: + raise RuntimeError('Parent must be set') + + if isinstance(self.parent._callbacks, (AsyncCallbackSet, AsyncCallbackSetLegacy)): + return self.parent._callbacks + + raise TypeError(f'unhandled parent callback type: {type(self.parent._callbacks)}') + + +class RegFileArray(NodeArray, ABC): + """ + base class for a array of register files + """ + __slots__: list[str] = [] + + # pylint: disable-next=too-many-arguments + def __init__(self, *, + logger_handle: str, inst_name: str, + parent: Union[AddressMap, RegFile], + address: int, + stride: int, + dimensions: tuple[int, ...]): + + super().__init__(logger_handle=logger_handle, inst_name=inst_name, + parent=parent, address=address, + stride=stride, dimensions=dimensions) + + +class AsyncRegFileArray(NodeArray, ABC): + """ + base class for a array of register files + """ + __slots__: list[str] = [] + + # pylint: disable-next=too-many-arguments + def __init__(self, *, + logger_handle: str, inst_name: str, + parent: Union[AsyncAddressMap, AsyncRegFile], + address: int, + stride: int, + dimensions: tuple[int, ...]): + + super().__init__(logger_handle=logger_handle, inst_name=inst_name, + parent=parent, address=address, + stride=stride, dimensions=dimensions) diff --git a/rdl/outputs/python/msk_top_regs/lib/base_field.py b/rdl/outputs/python/msk_top_regs/lib/base_field.py new file mode 100644 index 0000000..415747b --- /dev/null +++ b/rdl/outputs/python/msk_top_regs/lib/base_field.py @@ -0,0 +1,549 @@ +""" +peakrdl-python is a tool to generate Python Register Access Layer (RAL) from SystemRDL +Copyright (C) 2021 - 2023 + +This program is free software: you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation, either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . + +This module is intended to distributed as part of automatically generated code by the +peakrdl-python tool. It provides the base types for fields that are shared by non-async and async +fields +""" +from enum import IntEnum +from typing import cast, Optional, TypeVar, Generic +from abc import ABC +import warnings + +from .base import Base +from .utility_functions import swap_msb_lsb_ordering +from .base_register import BaseReg +from .field_encoding import SystemRDLEnum + + +class FieldSizeProps: + """ + class to hold the key attributes of a field + """ + __slots__ = ['__msb', '__lsb', '__width', '__high', '__low'] + + # pylint: disable-next=too-many-arguments + def __init__(self, *, width: int, msb: int, lsb: int, high: int, low: int): + self.__width = width + self.__msb = msb + self.__lsb = lsb + self.__high = high + self.__low = low + + if self.width < 1: + raise ValueError('width must be greater than 0') + + if self.high < self.low: + raise ValueError('field high bit position can not be less than the ' + 'low bit position') + + if self.lsb < 0: + raise ValueError('field low bit position cannot be less than zero') + + @property + def lsb(self) -> int: + """ + bit position of the least significant bit (lsb) of the field in the + parent register + + Note: + fields can be defined as msb in bit 0 or as lsb in bit 0 + """ + return self.__lsb + + @property + def msb(self) -> int: + """ + bit position of the most significant bit (msb) of the field in the + parent register + + Note: + fields can be defined as msb in bit 0 or as lsb in bit 0 + """ + return self.__msb + + @property + def width(self) -> int: + """ + The width of the field in bits + """ + return self.__width + + @property + def max_value(self) -> int: + """maximum unsigned integer value that can be stored in the field + + For example: + + * 8-bit field returns 0xFF (255) + * 16-bit field returns 0xFFFF (65535) + * 32-bit field returns 0xFFFF_FFFF (4294967295) + + """ + return (2 ** self.width) - 1 + + @property + def high(self) -> int: + """ + low index of the bit range of the field in the + parent register + + Note: + The first bit in the register is bit 0 + """ + return self.__high + + @property + def low(self) -> int: + """ + low index of the bit range of the field in the + parent register + + Note: + The first bit in the register is bit 0 + """ + return self.__low + + +class FieldMiscProps: + """ + Class to hold additional attributes of a field + """ + + __slots__ = ['__default', '__is_volatile'] + + def __init__(self, default:Optional[int], is_volatile:bool): + if not isinstance(default, int) and default is not None: + raise TypeError(f'default should be int or None, got {type(default)}') + self.__default = default + self.__is_volatile = is_volatile + + @property + def default(self) -> Optional[int]: + """ + The default (reset) value of the field + + None + - if the field is not reset. + - if the register resets to a signal value tht can not be determined + """ + return self.__default + + @property + def is_volatile(self) -> bool: + """ + Volatility of the field. True if the field is hardware-writable. + """ + return self.__is_volatile + + +# The following line should be: +# FieldType = TypeVar('FieldType', bound=int|IntEnum|SystemRDLEnum) +# However, python 3.9 does not support the combination so the binding was removed +# pylint: disable-next=invalid-name +FieldType = TypeVar('FieldType') +class Field(Generic[FieldType], Base, ABC): + """ + base class of register field wrappers + + Note: + It is not expected that this class will be instantiated under normal + circumstances however, it is useful for type checking + """ + + __slots__ = ['__size_props', '__misc_props', + '__bitmask', '__msb0', '__lsb0', '__field_type'] + + # pylint: disable-next=too-many-arguments + def __init__(self, *, + parent_register: BaseReg, size_props: FieldSizeProps, misc_props: FieldMiscProps, + logger_handle: str, inst_name: str, field_type:type[FieldType]): + + super().__init__(logger_handle=logger_handle, + inst_name=inst_name, parent=parent_register) + + if not isinstance(size_props, FieldSizeProps): + raise TypeError(f'size_props must be of {type(FieldSizeProps)} ' + f'but got {type(size_props)}') + self.__size_props = size_props + + if not isinstance(misc_props, FieldMiscProps): + raise TypeError(f'misc_props must be of {type(FieldMiscProps)} ' + f'but got {type(misc_props)}') + self.__misc_props = misc_props + + if not isinstance(parent_register, BaseReg): + raise TypeError(f'parent_register must be of {type(BaseReg)} ' + f'but got {type(parent_register)}') + + if self.width > self.register_data_width: + raise ValueError('width can not be greater than parent width') + + if self.high > self.register_data_width: + raise ValueError(f'field high bit position {self.high:d} must be less than the ' + f'parent register width ({self.register_data_width:d})') + + if self.low > self.register_data_width: + raise ValueError('field lsb must be less than the parent ' + 'register width') + + if self.high - self.low + 1 != self.width: + raise ValueError('field width defined by lsb and msb does not match' + ' specified width') + + if (self.msb == self.high) and (self.lsb == self.low): + self.__lsb0 = True + self.__msb0 = False + elif (self.msb == self.low) and (self.lsb == self.high): + self.__lsb0 = False + self.__msb0 = True + else: + raise ValueError('msb/lsb are inconsistent with low/high') + + self.__bitmask = 0 + for bit_position in range(self.low, self.high+1): + self.__bitmask |= (1 << bit_position) + + if not issubclass(field_type, (int, IntEnum, SystemRDLEnum)): + raise TypeError(f'Unsupported field type: {field_type}') + self.__field_type = field_type + + @property + def lsb(self) -> int: + """ + bit position of the least significant bit (lsb) of the field in the + parent register + + Note: + fields can be defined as msb in bit 0 or as lsb in bit 0 + """ + return self.__size_props.lsb + + @property + def msb(self) -> int: + """ + bit position of the most significant bit (msb) of the field in the + parent register + + Note: + fields can be defined as msb in bit 0 or as lsb in bit 0 + """ + return self.__size_props.msb + + @property + def width(self) -> int: + """ + The width of the field in bits + """ + return self.__size_props.width + + @property + def max_value(self) -> int: + """maximum unsigned integer value that can be stored in the field + + For example: + + * 8-bit field returns 0xFF (255) + * 16-bit field returns 0xFFFF (65535) + * 32-bit field returns 0xFFFF_FFFF (4294967295) + + """ + return (2 ** self.width) - 1 + + @property + def high(self) -> int: + """ + low index of the bit range of the field in the + parent register + + Note: + The first bit in the register is bit 0 + """ + return self.__size_props.high + + @property + def low(self) -> int: + """ + low index of the bit range of the field in the + parent register + + Note: + The first bit in the register is bit 0 + """ + return self.__size_props.low + + @property + def bitmask(self) -> int: + """ + The bit mask needed to extract the field from its register + + For example a register field occupying bits 7 to 4 in a 16-bit register + will have a bit mask of 0x00F0 + """ + return self.__bitmask + + @property + def register_data_width(self) -> int: + """ + The width of the register within which the field resides in bits + """ + return self.__parent_register.width + + @property + def inverse_bitmask(self) -> int: + """ + The bitwise inverse of the bitmask needed to extract the field from its + register + + For example a register field occupying bits 7 to 4 in a 16-bit register + will have a inverse bit mask of 0xFF0F + """ + return self.__parent_register.max_value ^ self.bitmask + + @property + def msb0(self) -> bool: + """ + The field can either be lsb0 or msb0 + + Returns: true if msb0 + + """ + return self.__msb0 + + @property + def lsb0(self) -> bool: + """ + The field can either be lsb0 or msb0 + + Returns: true if lsb0 + + """ + return self.__lsb0 + + @property + def default(self) -> Optional[FieldType]: + """ + The default value of the field + + This returns None: + - if the field is not reset. + - if the register resets to a signal value that can not be determined + """ + if issubclass(self._field_type, (SystemRDLEnum, IntEnum)): + int_default = self.__misc_props.default + + if int_default is not None: + if int_default not in [item.value for item in self._field_type]: + # this is a special case which can occur if the default value of the register + # does not cover the enum + msg = f'reset value {int_default:d} is not within the enumeration for the class' + self._logger.warning(msg) + warnings.warn(msg) + return None + + return_value = self._field_type(int_default) + return return_value # type: ignore[return-value] + + return None + + return self.__misc_props.default # type: ignore[return-value] + + @property + def is_volatile(self) -> bool: + """ + The HW volatility of the field + """ + return self.__misc_props.is_volatile + + @property + def __parent_register(self) -> BaseReg: + """ + parent register the field is placed in + """ + # this cast is OK because an explict typing check was done in the __init__ + return cast(BaseReg, self.parent) + + @property + def _field_type(self) -> type[FieldType]: + return self.__field_type # type: ignore[return-value] + + +class _FieldReadOnlyFramework(Field[FieldType], ABC): + """ + base class for a async or normal read only register field + """ + __slots__ : list[str] = [] + + def decode_read_value(self, value: int) -> FieldType: + """ + extracts the field value from a register value, by applying the bit + mask and shift needed + + Args: + value: value to decode, normally read from a register + + Returns: + field value + + Warning: + This method will be removed from a future version, if you have a compelling use + case for it please add a comment to the #184 ticket + + """ + # end users should not need access to the `decode_read_value` as the decoding is done + # for them, it felt like an anomaly that this was public, see #184 + warnings.warn('decode_read_value will be made private in a future version', + DeprecationWarning, stacklevel=2) + return self._decode_read_value(value=value) + + def _decode_read_value(self, value: int) -> FieldType: + """ + extracts the field value from a register value, by applying the bit + mask and shift needed + + Args: + value: value to decode, normally read from a register + + Returns: + field value + """ + if not isinstance(value, int): + raise TypeError(f'value must be an int but got {type(value)}') + + if value < 0: + raise ValueError('value to be decoded must be greater ' + 'than or equal to 0') + + if value > self.__parent_register.max_value: + raise ValueError(f'value to bede coded must be less than or equal ' + f'to {self.__parent_register.max_value:d}') + + if self.msb0 is False: + return_int_value = (value & self.bitmask) >> self.low + else: + return_int_value = swap_msb_lsb_ordering(value=(value & self.bitmask) >> self.low, + width=self.width) + + if issubclass(self._field_type, (SystemRDLEnum, IntEnum)): + return self._field_type(return_int_value) # type: ignore[return-value] + if issubclass(self._field_type, int): + return return_int_value # type: ignore[return-value] + + raise TypeError(f'unhandled field_type: {self._field_type}') + + + @property + def __parent_register(self) -> BaseReg: + """ + parent register the field is placed in + """ + # this cast is OK because an explict typing check was done in the __init__ + return cast(BaseReg, self.parent) + + +class _FieldWriteOnlyFramework(Field[FieldType], ABC): + """ + class for a write only register field + """ + __slots__ : list[str] = [] + + def _write_value_checks(self, value: int) -> None: + """ + Carries out the value for the encode_write_value and write methods + + Args: + value: proposed value to write + """ + if not isinstance(value, int): + raise TypeError(f'value must be an int but got {type(value)}') + + if value < 0: + raise ValueError('value to be written to register must be greater ' + 'than or equal to 0') + + if value > self.max_value: + raise ValueError(f'value to be written to register must be less ' + f'than or equal to {self.max_value:d}') + + + def encode_write_value(self, value: FieldType) -> int: + """ + Check that a value is legal for the field and then encode it in preparation to be written + to the register + + Args: + value: field value + + Returns: + value which can be applied to the register to update the field + + Warning: + This method will be removed from a future version, if you have a compelling use + case for it please add a comment to the #184 ticket + + """ + # end users should not need access to the `decode_read_value` as the decoding is done + # for them, it felt like an anomaly that this was public, see #184 + warnings.warn('encode_write_value will be made private in a future version', + DeprecationWarning, stacklevel=2) + return self._encode_write_value(value=value) + + def _encode_write_value(self, value: FieldType) -> int: + """ + Check that a value is legal for the field and then encode it in preparation to be written + to the register + + Args: + value: field value + + Returns: + value which can be applied to the register to update the field + + """ + if not isinstance(value, self._field_type): + raise TypeError(f'Field type is not as expected, got {type(value)},' + f' expected {self._field_type}') + + if isinstance(value, (SystemRDLEnum, IntEnum)): + int_value = value.value + elif isinstance(value, int): + int_value = value + else: + raise RuntimeError('Unhandled type configuration') + + self._write_value_checks(value=int_value) + + if self.msb0 is False: + return_value = int_value << self.low + else: + return_value = swap_msb_lsb_ordering(value=int_value, width=self.width) << self.low + + return return_value + + +class FieldEnum(Field[FieldType], ABC): + """ + class for a register field with an enumerated value + """ + __slots__: list[str] = [] + + @property + def enum_cls(self) -> type[FieldType]: + """ + The enumeration class for this field + """ + return self._field_type diff --git a/rdl/outputs/python/msk_top_regs/lib/base_register.py b/rdl/outputs/python/msk_top_regs/lib/base_register.py new file mode 100644 index 0000000..e854a86 --- /dev/null +++ b/rdl/outputs/python/msk_top_regs/lib/base_register.py @@ -0,0 +1,229 @@ +""" +peakrdl-python is a tool to generate Python Register Access Layer (RAL) from SystemRDL +Copyright (C) 2021 - 2023 + +This program is free software: you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation, either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . + +This module is intended to distributed as part of automatically generated code by the +peakrdl-python tool. It provides a set of classes used by the autogenerated code to represent +registers +""" +from typing import Union, Optional, TypeVar +from abc import ABC, abstractmethod + + +from .base import Node, AddressMap, RegFile, NodeArray +from .utility_functions import legal_register_width +from .base import AsyncAddressMap, AsyncRegFile +from .memory import BaseMemory + + +class RegisterWriteVerifyError(Exception): + """ + Exception that occurs when the read after a write does not match the expected value + """ + + +class BaseReg(Node, ABC): + """ + base class of register wrappers + + Note: + It is not expected that this class will be instantiated under normal + circumstances however, it is useful for type checking + """ + + __slots__: list[str] = ['__width', '__accesswidth'] + + # pylint: disable=too-many-arguments,duplicate-code + def __init__(self, *, + address: int, + width: int, + accesswidth: int, + logger_handle: str, + inst_name: str, + parent: Union[AddressMap, AsyncAddressMap, RegFile, AsyncRegFile, BaseMemory, + 'BaseRegArray']): + + super().__init__(address=address, + logger_handle=logger_handle, + inst_name=inst_name, + parent=parent) + if not isinstance(width, int): + raise TypeError(f'width should be int but got {(type(width))}') + if not legal_register_width(width_in_bits=width): + raise ValueError(f'Unsupported register width {width:d}') + self.__width = width + if not isinstance(accesswidth, int): + raise TypeError(f'accesswidth should be int but got {(type(accesswidth))}') + if not legal_register_width(width_in_bits=accesswidth): + raise ValueError(f'Unsupported access width {accesswidth:d}') + self.__accesswidth = accesswidth + # pylint: enable=too-many-arguments,duplicate-code + + @property + def max_value(self) -> int: + """ + maximum unsigned integer value that can be stored in the register + + For example: + + * 8-bit register returns 0xFF (255) + * 16-bit register returns 0xFFFF (65535) + * 32-bit register returns 0xFFFF_FFFF (4294967295) + + """ + return (2 ** self.width) - 1 + + def _validate_data(self, data: int) -> None: + """ + Check that the data parameter is of valid type and range + """ + if not isinstance(data, int): + raise TypeError(f'data should be an int got {type(data)}') + + if data > self.max_value: + raise ValueError('data out of range') + + if data < 0: + raise ValueError('data out of range') + + @property + def width(self) -> int: + """ + The width of the register in bits, this uses the `regwidth` systemRDL property + """ + return self.__width + + @property + def accesswidth(self) -> int: + """ + The access width of the register in bits, this uses the `accesswidth` systemRDL property + """ + return self.__accesswidth + + @property + def size(self) -> int: + """ + Total Number of bytes of address the node occupies + """ + return self.__width >> 3 + + @property + @abstractmethod + def _is_readable(self) -> bool: + ... + + @property + @abstractmethod + def _is_writeable(self) -> bool: + ... + +# pylint: disable-next=invalid-name +BaseRegArrayElementType= TypeVar('BaseRegArrayElementType', bound=BaseReg) + + +class BaseRegArray(NodeArray[BaseRegArrayElementType], ABC): + """ + base class of register array wrappers (async and non-async) + + Note: + It is not expected that this class will be instantiated under normal + circumstances however, it is useful for type checking + """ + # pylint: disable=too-many-arguments,duplicate-code + + __slots__: list[str] = ['__width', '__accesswidth'] + + def __init__(self, *, + logger_handle: str, inst_name: str, + parent: Union[AddressMap, AsyncAddressMap, RegFile, AsyncRegFile, BaseMemory], + width: int, + accesswidth: int, + address: int, + stride: int, + dimensions: tuple[int, ...], + elements: Optional[dict[tuple[int, ...], BaseRegArrayElementType]] = None): + + if not isinstance(width, int): + raise TypeError(f'width should be int but got {(type(width))}') + if not legal_register_width(width_in_bits=width): + raise ValueError(f'Unsupported register width {width:d}') + self.__width = width + if not isinstance(accesswidth, int): + raise TypeError(f'accesswidth should be int but got {(type(accesswidth))}') + if not legal_register_width(width_in_bits=accesswidth): + raise ValueError(f'Unsupported access width {accesswidth:d}') + self.__accesswidth = accesswidth + + if not issubclass(self._element_datatype, BaseReg): + raise TypeError(f'{self._element_datatype}') + + super().__init__(logger_handle=logger_handle, inst_name=inst_name, + parent=parent, address=address, + stride=stride, dimensions=dimensions, elements=elements) + + @property + def width(self) -> int: + """ + The width of the register in bits, this uses the `regwidth` systemRDL property + """ + return self.__width + + @property + def accesswidth(self) -> int: + """ + The access width of the register in bits, this uses the `accesswidth` systemRDL property + """ + return self.__accesswidth + + def _build_element(self, indices: tuple[int, ...]) -> BaseRegArrayElementType: + + return self._element_datatype( + logger_handle=self._build_element_logger_handle(indices=indices), + address=self._address_calculator(indices), + inst_name=self._build_element_inst_name(indices=indices), + width=self.width, + accesswidth=self.accesswidth, + parent=self) + + def _sub_instance(self, elements: dict[tuple[int, ...], BaseRegArrayElementType]) ->\ + NodeArray[BaseRegArrayElementType]: + if not isinstance(self.parent, (AddressMap, AsyncAddressMap, RegFile, + AsyncRegFile, BaseMemory)): + raise RuntimeError('Parent of a Node Array must be Node') + return self.__class__(logger_handle=self._logger.name, + inst_name=self.inst_name, + parent=self.parent, + address=self.address, + width=self.width, + accesswidth=self.accesswidth, + stride=self.stride, + dimensions=self.dimensions, + elements=elements) + + @property + @abstractmethod + def _element_datatype(self) -> type[BaseRegArrayElementType]: + ... + + @property + @abstractmethod + def _is_readable(self) -> bool: + ... + + @property + @abstractmethod + def _is_writeable(self) -> bool: + ... diff --git a/rdl/outputs/python/msk_top_regs/lib/callbacks.py b/rdl/outputs/python/msk_top_regs/lib/callbacks.py new file mode 100644 index 0000000..8c8b541 --- /dev/null +++ b/rdl/outputs/python/msk_top_regs/lib/callbacks.py @@ -0,0 +1,363 @@ +""" +peakrdl-python is a tool to generate Python Register Access Layer (RAL) from SystemRDL +Copyright (C) 2021 - 2023 + +This program is free software: you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation, either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . + +This module is intended to distributed as part of automatically generated code by the +peakrdl-python tool. It provides a set of types used by the autogenerated code to callbacks +""" +from array import array as Array + +from typing import Optional, Union +from typing import Protocol + + +class ReadCallback(Protocol): + """ + Callback definition for a single register read operation + """ + # pylint: disable=too-few-public-methods + def __call__(self, addr: int, width: int, accesswidth: int) -> int: + pass + + +class WriteCallback(Protocol): + """ + Callback definition for a single register write operation + """ + # pylint: disable=too-few-public-methods + def __call__(self, addr: int, width: int, accesswidth: int, data: int) -> None: + pass + + +class ReadBlockLegacyCallback(Protocol): + """ + Callback definition for a block read operation + """ + # pylint: disable=too-few-public-methods + def __call__(self, addr: int, width: int, accesswidth: int, length: int) -> Array: + pass + +class ReadBlockCallback(Protocol): + """ + Callback definition for a block read operation + """ + # pylint: disable=too-few-public-methods + def __call__(self, addr: int, width: int, accesswidth: int, length: int) -> list[int]: + pass + + +class WriteBlockCallback(Protocol): + """ + Callback definition for a block write operation + """ + # pylint: disable=too-few-public-methods + def __call__(self, addr: int, width: int, accesswidth: int, data: list[int]) -> None: + pass + + +class WriteBlockLegacyCallback(Protocol): + """ + Callback definition for a block write operation + """ + # pylint: disable=too-few-public-methods + def __call__(self, addr: int, width: int, accesswidth: int, data: Array) -> None: + pass + + +class AsyncReadCallback(Protocol): + """ + Callback definition for a single register async read operation + """ + # pylint: disable=too-few-public-methods,unexpected-special-method-signature + async def __call__(self, addr: int, width: int, accesswidth: int) -> int: + pass + + +class AsyncWriteCallback(Protocol): + """ + Callback definition for a single register async write operation + """ + # pylint: disable=too-few-public-methods,unexpected-special-method-signature + async def __call__(self, addr: int, width: int, accesswidth: int, data: int) -> None: + pass + + +class AsyncReadBlockCallback(Protocol): + """ + Callback definition for an async block read operation + """ + # pylint: disable=too-few-public-methods,unexpected-special-method-signature + async def __call__(self, addr: int, width: int, accesswidth: int, length: int) -> list[int]: + pass + +class AsyncReadBlockLegacyCallback(Protocol): + """ + Callback definition for an async block read operation + """ + # pylint: disable=too-few-public-methods,unexpected-special-method-signature + async def __call__(self, addr: int, width: int, accesswidth: int, length: int) -> Array: + pass + + +class AsyncWriteBlockCallback(Protocol): + """ + Callback definition for an async block write operation + """ + # pylint: disable=too-few-public-methods,unexpected-special-method-signature + async def __call__(self, addr: int, width: int, accesswidth: int, data: list[int]) -> None: + pass + +class AsyncWriteBlockLegacyCallback(Protocol): + """ + Callback definition for an async block write operation + """ + # pylint: disable=too-few-public-methods,unexpected-special-method-signature + async def __call__(self, addr: int, width: int, accesswidth: int, data: Array) -> None: + pass + + +class _NormalCallbackSetBase: + """ + Class to hold a set of callbacks, this reduces the number of callback that need to be passed + around + """ + + __slots__ = ['__write_callback', '__read_callback'] + + def __init__(self, + write_callback: Optional[WriteCallback] = None, + read_callback: Optional[ReadCallback] = None): + + self.__read_callback = read_callback + self.__write_callback = write_callback + + @property + def read_callback(self) -> Optional[ReadCallback]: + """ + single read callback function + + Returns: call back function + + """ + return self.__read_callback + + @property + def write_callback(self) -> Optional[WriteCallback]: + """ + single write callback function + + Returns: call back function + + """ + return self.__write_callback + + +class NormalCallbackSet(_NormalCallbackSetBase): + """ + Class to hold a set of callbacks, this reduces the number of callback that need to be passed + around + """ + + __slots__ = ['__write_block_callback', '__read_block_callback'] + + def __init__(self, + write_callback: Optional[WriteCallback] = None, + read_callback: Optional[ReadCallback] = None, + write_block_callback: Optional[WriteBlockCallback] = None, + read_block_callback: Optional[ReadBlockCallback] = None): + + super().__init__(read_callback=read_callback, write_callback=write_callback) + + self.__read_block_callback = read_block_callback + self.__write_block_callback = write_block_callback + + @property + def read_block_callback(self) -> Optional[ReadBlockCallback]: + """ + block read callback function + + Returns: call back function + + """ + return self.__read_block_callback + + @property + def write_block_callback(self) -> Optional[WriteBlockCallback]: + """ + block read callback function + + Returns: call back function + + """ + return self.__write_block_callback + + +class NormalCallbackSetLegacy(_NormalCallbackSetBase): + """ + Class to hold a set of callbacks, this reduces the number of callback that need to be passed + around + """ + + __slots__ = ['__write_block_callback', '__read_block_callback'] + + def __init__(self, + write_callback: Optional[WriteCallback] = None, + read_callback: Optional[ReadCallback] = None, + write_block_callback: Optional[WriteBlockLegacyCallback] = None, + read_block_callback: Optional[ReadBlockLegacyCallback] = None): + + super().__init__(read_callback=read_callback, write_callback=write_callback) + + self.__read_block_callback = read_block_callback + self.__write_block_callback = write_block_callback + + @property + def read_block_callback(self) -> Optional[ReadBlockLegacyCallback]: + """ + block read callback function + + Returns: call back function + + """ + return self.__read_block_callback + + @property + def write_block_callback(self) -> Optional[WriteBlockLegacyCallback]: + """ + block read callback function + + Returns: call back function + + """ + return self.__write_block_callback + +class _AsyncCallbackSetBase: + """ + Class to hold a set of callbacks, this reduces the number of callback that need to be passed + around + """ + + __slots__ = ['__write_callback', '__read_callback'] + + def __init__(self, + write_callback: Optional[AsyncWriteCallback] = None, + read_callback: Optional[AsyncReadCallback] = None): + + self.__read_callback = read_callback + self.__write_callback = write_callback + + @property + def read_callback(self) -> Optional[AsyncReadCallback]: + """ + single read callback function + + Returns: call back function + + """ + return self.__read_callback + + @property + def write_callback(self) -> Optional[AsyncWriteCallback]: + """ + single write callback function + + Returns: call back function + + """ + return self.__write_callback + + +class AsyncCallbackSet(_AsyncCallbackSetBase): + """ + Class to hold a set of callbacks, this reduces the number of callback that need to be passed + around + """ + + __slots__ = ['__write_block_callback', '__read_block_callback'] + + def __init__(self, + write_callback: Optional[AsyncWriteCallback] = None, + read_callback: Optional[AsyncReadCallback] = None, + write_block_callback: Optional[AsyncWriteBlockCallback] = None, + read_block_callback: Optional[AsyncReadBlockCallback] = None): + + super().__init__(read_callback=read_callback, write_callback=write_callback) + + self.__read_block_callback = read_block_callback + self.__write_block_callback = write_block_callback + + @property + def read_block_callback(self) -> Optional[AsyncReadBlockCallback]: + """ + block read callback function + + Returns: call back function + + """ + return self.__read_block_callback + + @property + def write_block_callback(self) -> Optional[AsyncWriteBlockCallback]: + """ + block read callback function + + Returns: call back function + + """ + return self.__write_block_callback + + +class AsyncCallbackSetLegacy(_AsyncCallbackSetBase): + """ + Class to hold a set of callbacks, this reduces the number of callback that need to be passed + around + """ + + __slots__ = ['__write_block_callback', '__read_block_callback'] + + def __init__(self, + write_callback: Optional[AsyncWriteCallback] = None, + read_callback: Optional[AsyncReadCallback] = None, + write_block_callback: Optional[AsyncWriteBlockLegacyCallback] = None, + read_block_callback: Optional[AsyncReadBlockLegacyCallback] = None): + super().__init__(read_callback=read_callback, write_callback=write_callback) + + self.__read_block_callback = read_block_callback + self.__write_block_callback = write_block_callback + + @property + def read_block_callback(self) -> Optional[AsyncReadBlockLegacyCallback]: + """ + block read callback function + + Returns: call back function + + """ + return self.__read_block_callback + + @property + def write_block_callback(self) -> Optional[AsyncWriteBlockLegacyCallback]: + """ + block read callback function + + Returns: call back function + + """ + return self.__write_block_callback + + +CallbackSet = Union[AsyncCallbackSet, NormalCallbackSet] +CallbackSetLegacy = Union[AsyncCallbackSetLegacy, NormalCallbackSetLegacy] diff --git a/rdl/outputs/python/msk_top_regs/lib/field_encoding.py b/rdl/outputs/python/msk_top_regs/lib/field_encoding.py new file mode 100644 index 0000000..44d4068 --- /dev/null +++ b/rdl/outputs/python/msk_top_regs/lib/field_encoding.py @@ -0,0 +1,80 @@ +""" +peakrdl-python is a tool to generate Python Register Access Layer (RAL) from SystemRDL +Copyright (C) 2021 - 2023 + +This program is free software: you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation, either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . + +This module is intended to distributed as part of automatically generated code by the +peakrdl-python tool. It provides the base types of field enumerations +""" +from enum import Enum +from typing import Optional +from collections import namedtuple +from json import JSONEncoder + +SystemRDLEnumEntry = namedtuple('SystemRDLEnumEntry', ['int_value', 'name', 'desc']) + +class SystemRDLEnum(Enum): + """ + A Enumeration that can also hold the system RDL properties, notably the `name` and `desc + """ + @property + def _full_value(self) -> SystemRDLEnumEntry: + """ The full field value (needed to some operation) """ + return super().value + + @property + # pylint:disable-next=invalid-overridden-method + def value(self) -> int: + """ The integer value used to encode the field value """ + return super().value.int_value + + @property + def rdl_name(self) -> Optional[str]: + """ + The systemRDL name property for the encoding entry + """ + return super().value.name + + @property + def rdl_desc(self) -> Optional[str]: + """ + The systemRDL name property for the encoding entry + """ + return super().value.desc + + @classmethod + def _missing_(cls, value): # type: ignore[no-untyped-def] + + if isinstance(value, int): + # pylint:disable-next=protected-access,no-member + int_mapping = {item.value: item._full_value for item in cls._member_map_.values()} + if value not in int_mapping: + raise ValueError(f'Enumeration has not integer value of {value}') + return cls(int_mapping[value]) + + return None + + def __str__(self) -> str: + return self.name + +class RegisterFieldJSONEncoder(JSONEncoder): + """ + JSON Encoder that supports SystemRDLEnum + """ + def default(self, o): # type: ignore[no-untyped-def] + if isinstance(o, SystemRDLEnum): + return o.name + # Let the base class default method raise the TypeError + return super().default(o) diff --git a/rdl/outputs/python/msk_top_regs/lib/memory.py b/rdl/outputs/python/msk_top_regs/lib/memory.py new file mode 100644 index 0000000..2ab3a7d --- /dev/null +++ b/rdl/outputs/python/msk_top_regs/lib/memory.py @@ -0,0 +1,752 @@ +""" +peakrdl-python is a tool to generate Python Register Access Layer (RAL) from SystemRDL +Copyright (C) 2021 - 2023 + +This program is free software: you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation, either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . + +This module is intended to distributed as part of automatically generated code by the +peakrdl-python tool. It provides a set of classes used by the autogenerated code to represent +memories +""" +from array import array as Array +from typing import Union, TYPE_CHECKING +from collections.abc import Iterator +from abc import ABC, abstractmethod +import sys + +from .base import Node, AddressMap, AsyncAddressMap, NodeArray +from .utility_functions import get_array_typecode + +from .callbacks import NormalCallbackSet, NormalCallbackSetLegacy + +# same bit of code exists in base so flags as duplicate +# pylint: disable=duplicate-code +if sys.version_info >= (3, 10): + # type guarding was introduced in python 3.10 + from typing import TypeGuard +else: + from typing_extensions import TypeGuard +# pylint: enable=duplicate-code + + +if TYPE_CHECKING: + from .register_and_field import Reg, RegArray + from .register_and_field import ReadableRegister, WritableRegister + from .register_and_field import ReadableRegisterArray, WriteableRegisterArray + from .async_memory import AsyncMemoryArray + +# pylint: disable=duplicate-code + + +class BaseMemory(Node, ABC): + """ + base class of memory wrappers + + Note: + It is not expected that this class will be instantiated under normal + circumstances however, it is useful for type checking + """ + + __slots__: list[str] = ['__memwidth', '__entries', '__accesswidth'] + + # pylint: disable=too-many-arguments + def __init__(self, *, + address: int, + width: int, + accesswidth: int, + entries: int, + logger_handle: str, + inst_name: str, + parent: Union[AddressMap, AsyncAddressMap, 'MemoryArray', 'AsyncMemoryArray']): + """ + Initialise the class + + Args: + address: address of the register + width: width of the register in bits + logger_handle: name to be used logging messages associate with this object + """ + super().__init__(address=address, + logger_handle=logger_handle, + inst_name=inst_name, + parent=parent) + + self.__memwidth = width + self.__entries = entries + self.__accesswidth = accesswidth + # pylint: enable=too-many-arguments + + @property + def width(self) -> int: + """ + The width of the memory in bits, this uses the `memwidth` systemRDL property + + Returns: memory width + + """ + return self.__memwidth + + @property + def width_in_bytes(self) -> int: + """ + The width of the memory bytes, i.e. the width in bits divided by 8 + + Returns: memory width (in bytes) + + """ + def roundup_pow2(x: int) -> int: + return 1 << (x - 1).bit_length() + + return roundup_pow2(self.width) // 8 + + @property + def entries(self) -> int: + """ + The number of entries in the memory, this uses the `mementries` systemRDL property + + Returns: memory entries + + """ + return self.__entries + + @property + def array_typecode(self) -> str: + """ + the python array.array type is initialised with a typecode. This property provides the + recommended typecode to use with this class instance (based on the memwidth) + + Returns: typecode + + """ + return get_array_typecode(self.width) + + @property + def size(self) -> int: + """ + Total Number of bytes of address the node occupies + """ + return self.entries * self.width_in_bytes + + def address_lookup(self, entry: int) -> int: + """ + provides the address for an entry in the memory. + + Examples + + Args: + entry: entry number to look up the address for + + Returns: Address + + """ + if not isinstance(entry, int): + raise TypeError(f'entry must be an int but got {type(entry)}') + + if entry not in range(0, self.entries): + raise ValueError(f'entry must be in range 0 to {self.entries-1:d} but got {entry:d}') + + return self.address + (entry * self.width_in_bytes) + + @property + def accesswidth(self) -> int: + """ + The access width of the register in bits, this uses the `accesswidth` systemRDL property + + Returns: register access width + """ + return self.__accesswidth + + +class Memory(BaseMemory, ABC): + """ + base class of non_async memory wrappers + + Note: + It is not expected that this class will be instantiated under normal + circumstances however, it is useful for type checking + """ + __slots__: list[str] = [] + + # pylint: disable=too-many-arguments + def __init__(self, *, + address: int, + width: int, + accesswidth: int, + entries: int, + logger_handle: str, + inst_name: str, + parent: Union[AddressMap, 'MemoryArray']): + """ + Initialise the class + + Args: + address: address of the register + width: width of the register in bits + logger_handle: name to be used logging messages associate with this object + """ + if not isinstance(parent, (AddressMap, + MemoryWriteOnlyArray, MemoryReadOnlyArray, + MemoryReadWriteArray)): + raise TypeError(f'parent should be either AddressMap or Memory Array got ' + f'{type(parent)}') + super().__init__(address=address, + logger_handle=logger_handle, + inst_name=inst_name, + width=width, + accesswidth=accesswidth, + entries=entries, + parent=parent) + + @abstractmethod + def get_registers(self, unroll: bool = False) -> \ + Iterator[Union['Reg', 'RegArray']]: + """ + generator that produces all the readable_registers of this node + + Args: + unroll: Whether to unroll child array or not + """ + + +class _MemoryReadOnly(Memory, ABC): + """ + base class of memory wrappers + + Note: + It is not expected that this class will be instantiated under normal + circumstances however, it is useful for type checking + """ + + __slots__: list[str] = [] + + # pylint: disable-next=too-many-arguments + def __init__(self, *, + address: int, + width: int, + accesswidth: int, + entries: int, + logger_handle: str, + inst_name: str, + parent: Union[AddressMap, 'MemoryArray']): + + if parent is None: + raise TypeError('parent should be either AddressMap or Memory Array ' + f'got {type(parent)}') + + if not isinstance(parent, (AddressMap, MemoryWriteOnlyArray, + MemoryReadOnlyArray, MemoryReadWriteArray)): + raise TypeError('parent should be either AddressMap or Memory Array ' + f'got {type(parent)}') + + if not isinstance(parent._callbacks, (NormalCallbackSet, NormalCallbackSetLegacy)): + raise TypeError(f'callback set type is wrong, got {type(parent._callbacks)}') + + super().__init__(address=address, + width=width, + accesswidth=accesswidth, + entries=entries, + logger_handle=logger_handle, + inst_name=inst_name, + parent=parent) + + # pylint: enable=too-many-arguments + @property + def _callbacks(self) -> Union[NormalCallbackSet, NormalCallbackSetLegacy]: + # pylint: disable=protected-access + if self.parent is None: + raise RuntimeError('Parent must be set') + + if isinstance(self.parent._callbacks, (NormalCallbackSet, NormalCallbackSetLegacy)): + return self.parent._callbacks + + raise TypeError(f'unhandled parent callback type: {type(self.parent._callbacks)}') + + def _read(self, start_entry: int, number_entries: int) -> list[int]: + """ + Read from the memory + + Args: + start_entry: index in the memory to start from, this is not the address + number_entries: number of entries to read + + Returns: data read from memory + + """ + + if not isinstance(start_entry, int): + raise TypeError(f'start_entry should be an int got {type(start_entry)}') + + if not isinstance(number_entries, int): + raise TypeError(f'number_entries should be an int got {type(number_entries)}') + + if start_entry not in range(0, self.entries): + raise ValueError(f'entry must be in range 0 to {self.entries - 1:d} ' + f'but got {start_entry:d}') + + if number_entries not in range(0, self.entries - start_entry + 1): + raise ValueError(f'number_entries must be in range 0 to' + f' {self.entries - start_entry:d} but got {number_entries:d}') + + read_block_callback = self._callbacks.read_block_callback + read_callback = self._callbacks.read_callback + + if read_block_callback is not None: + addr = self.address_lookup(entry=start_entry) + data_read = \ + read_block_callback(addr=addr, + width=self.width, + accesswidth=self.width, + length=number_entries) + + if isinstance(self._callbacks, NormalCallbackSet): + if not isinstance(data_read, list): + if isinstance(data_read, Array): + raise TypeError( + 'The read block callback is expected to return an list, this ' + 'is likely to happen if you are using legacy callbacks without ' + 'NormalCallbackSetLegacy') + raise TypeError('The read block callback is expected to return an List') + return data_read + + if isinstance(self._callbacks, NormalCallbackSetLegacy): + if not isinstance(data_read, Array): + raise TypeError('The read block callback is expected to return an array') + return data_read.tolist() + + raise RuntimeError(f'There is no usable callback block callback:{read_block_callback}') + + if read_callback is not None: + # there is not read_block_callback defined so we must used individual read + data_read = [0 for _ in range(number_entries)] + + for entry in range(number_entries): + entry_address = self.address_lookup(entry=start_entry+entry) + data_entry = read_callback(addr=entry_address, + width=self.width, + accesswidth=self.width) + + data_read[entry] = data_entry + + return data_read + + raise RuntimeError(f'There is no usable callback, ' + f'block callback:{read_block_callback}, ' + f'normal callback:{read_callback}') + + def _read_legacy(self, start_entry: int, number_entries: int) -> Array: + """ + Read from the memory + + Args: + start_entry: index in the memory to start from, this is not the address + number_entries: number of entries to read + + Returns: data read from memory + + """ + + if not isinstance(start_entry, int): + raise TypeError(f'start_entry should be an int got {type(start_entry)}') + + if not isinstance(number_entries, int): + raise TypeError(f'number_entries should be an int got {type(number_entries)}') + + if start_entry not in range(0, self.entries): + raise ValueError(f'entry must be in range 0 to {self.entries - 1:d} ' + f'but got {start_entry:d}') + + if number_entries not in range(0, self.entries - start_entry + 1): + raise ValueError(f'number_entries must be in range 0 to' + f' {self.entries - start_entry:d} but got {number_entries:d}') + + read_block_callback = self._callbacks.read_block_callback + read_callback = self._callbacks.read_callback + + if read_block_callback is not None: + addr = self.address_lookup(entry=start_entry) + data_read = \ + read_block_callback(addr=addr, + width=self.width, + accesswidth=self.width, + length=number_entries) + + if isinstance(self._callbacks, NormalCallbackSet): + if not isinstance(data_read, list): + if isinstance(data_read, Array): + raise TypeError( + 'The read block callback is expected to return an list, this ' + 'is likely to happen if you are using legacy callbacks without ' + 'NormalCallbackSetLegacy') + raise TypeError('The read block callback is expected to return an List') + return Array(self.array_typecode, data_read) + + if isinstance(self._callbacks, NormalCallbackSetLegacy): + if not isinstance(data_read, Array): + raise TypeError('The read block callback is expected to return an array') + return data_read + + raise RuntimeError(f'There is no usable callback block callback:{read_block_callback}') + + if read_callback is not None: + # there is not read_block_callback defined so we must used individual read + data_read = Array(self.array_typecode, [0 for _ in range(number_entries)]) + + for entry in range(number_entries): + entry_address = self.address_lookup(entry=start_entry+entry) + data_entry = read_callback(addr=entry_address, + width=self.width, + accesswidth=self.width) + + data_read[entry] = data_entry + + return data_read + + raise RuntimeError(f'There is no usable callback, ' + f'block callback:{read_block_callback}, ' + f'normal callback:{read_callback}') + + def get_readable_registers(self, unroll: bool = False) -> \ + Iterator[Union['ReadableRegister', 'ReadableRegisterArray']]: + """ + generator that produces all the readable_registers of this node + + Args: + unroll: Whether to unroll child array or not + """ + def is_readable(item: Union['Reg', 'RegArray']) ->\ + TypeGuard[Union['ReadableRegister', 'ReadableRegisterArray']]: + # pylint: disable-next=protected-access + return item._is_readable + + return filter(is_readable, self.get_registers(unroll=unroll)) + + +class MemoryReadOnly(_MemoryReadOnly, ABC): + """ + base class of memory wrappers + + Note: + It is not expected that this class will be instantiated under normal + circumstances however, it is useful for type checking + """ + + __slots__: list[str] = [] + + def read(self, start_entry: int, number_entries: int) -> list[int]: + """ + Read from the memory + + Args: + start_entry: index in the memory to start from, this is not the address + number_entries: number of entries to read + + Returns: data read from memory + + """ + return self._read(start_entry=start_entry, number_entries=number_entries) + + +class MemoryReadOnlyLegacy(_MemoryReadOnly, ABC): + """ + base class of memory wrappers + + Note: + It is not expected that this class will be instantiated under normal + circumstances however, it is useful for type checking + """ + __slots__: list[str] = [] + + def read(self, start_entry: int, number_entries: int) -> Array: + """ + Read from the memory + + Args: + start_entry: index in the memory to start from, this is not the address + number_entries: number of entries to read + + Returns: data read from memory + + """ + return self._read_legacy(start_entry=start_entry, number_entries=number_entries) + + +class _MemoryWriteOnly(Memory, ABC): + """ + base class of memory wrappers + + Note: + It is not expected that this class will be instantiated under normal + circumstances however, it is useful for type checking + """ + __slots__: list[str] = [] + + # pylint: disable-next=too-many-arguments + def __init__(self, *, + address: int, + width: int, + accesswidth: int, + entries: int, + logger_handle: str, + inst_name: str, + parent: Union[AddressMap, 'MemoryArray']): + + if not isinstance(parent, (AddressMap, MemoryWriteOnlyArray, + MemoryReadOnlyArray, MemoryReadWriteArray)): + raise TypeError('parent should be either AddressMap or Memory Array ' + f'got {type(parent)}') + + if not isinstance(parent._callbacks, (NormalCallbackSet, NormalCallbackSetLegacy)): + raise TypeError(f'callback set type is wrong, got {type(parent._callbacks)}') + + super().__init__(address=address, + width=width, + accesswidth=accesswidth, + entries=entries, + logger_handle=logger_handle, + inst_name=inst_name, + parent=parent) + + # pylint: enable=too-many-arguments + @property + def _callbacks(self) -> Union[NormalCallbackSet, NormalCallbackSetLegacy]: + # pylint: disable=protected-access + if self.parent is None: + raise RuntimeError('Parent must be set') + + if isinstance(self.parent._callbacks, (NormalCallbackSet, NormalCallbackSetLegacy)): + return self.parent._callbacks + + raise TypeError(f'unhandled parent callback type: {type(self.parent._callbacks)}') + + def _write(self, start_entry: int, data: Union[Array, list[int]]) -> None: + """ + Write data to memory + + Args: + start_entry: index in the memory to start from, this is not the address + data: data to write + + Returns: None + + """ + # pylint:disable=too-many-branches + if not isinstance(start_entry, int): + raise TypeError(f'start_entry should be an int got {type(start_entry)}') + + if start_entry not in range(0, self.entries): + raise ValueError(f'entry must be in range 0 to {self.entries - 1:d} ' + f'but got {start_entry:d}') + + if not isinstance(data, (Array, list)): + raise TypeError(f'data should be an List or array.array got {type(data)}') + + if len(data) not in range(0, self.entries - start_entry + 1): + raise ValueError(f'data length must be in range 0 to {self.entries - start_entry:d} ' + f'but got {len(data):d}') + + if self._callbacks.write_block_callback is not None: + addr = self.address_lookup(entry=start_entry) + if isinstance(self._callbacks, NormalCallbackSet): + if isinstance(data, Array): + self._callbacks.write_block_callback(addr=addr, + width=self.width, + accesswidth=self.width, + data=data.tolist()) + else: + self._callbacks.write_block_callback(addr=addr, + width=self.width, + accesswidth=self.width, + data=data) + if isinstance(self._callbacks, NormalCallbackSetLegacy): + if isinstance(data, list): + # need to convert the data to an array before calling + self._callbacks.write_block_callback(addr=addr, + width=self.width, + accesswidth=self.width, + data=Array(self.array_typecode, data)) + else: + self._callbacks.write_block_callback(addr=addr, + width=self.width, + accesswidth=self.width, + data=data) + + elif self._callbacks.write_callback is not None: + # there is not write_block_callback defined so we must used individual write + for entry_index, entry_data in enumerate(data): + entry_address = self.address_lookup(entry=start_entry+entry_index) + self._callbacks.write_callback(addr=entry_address, + width=self.width, + accesswidth=self.width, + data=entry_data) + + else: + raise RuntimeError('No suitable callback') + + def get_writable_registers(self, unroll: bool = False) -> \ + Iterator[Union['WritableRegister', 'WriteableRegisterArray']]: + """ + generator that produces all the readable_registers of this node + + Args: + unroll: Whether to unroll child array or not + """ + def is_writable(item: Union['Reg', 'RegArray']) -> \ + TypeGuard[Union['WritableRegister', 'WriteableRegisterArray']]: + # pylint: disable-next=protected-access + return item._is_writeable + + return filter(is_writable, self.get_registers(unroll=unroll)) + + +class MemoryWriteOnly(_MemoryWriteOnly, ABC): + """ + base class of memory wrappers + + Note: + It is not expected that this class will be instantiated under normal + circumstances however, it is useful for type checking + """ + __slots__: list[str] = [] + + def write(self, start_entry: int, data: list[int]) -> None: + """ + Write data to memory + + Args: + start_entry: index in the memory to start from, this is not the address + data: data to write + + Returns: None + + """ + if not isinstance(data, list): + raise TypeError(f'data should be an List got {type(data)}') + return self._write(start_entry=start_entry, data=data) + + +class MemoryWriteOnlyLegacy(_MemoryWriteOnly, ABC): + """ + base class of memory wrappers + + Note: + It is not expected that this class will be instantiated under normal + circumstances however, it is useful for type checking + """ + __slots__: list[str] = [] + + def write(self, start_entry: int, data: Array) -> None: + """ + Write data to memory + + Args: + start_entry: index in the memory to start from, this is not the address + data: data to write + + Returns: None + + """ + if not isinstance(data, Array): + raise TypeError(f'data should be an Array {type(data)}') + return self._write(start_entry=start_entry, data=data) + + +class MemoryReadWrite(MemoryReadOnly, MemoryWriteOnly, ABC): + """ + base class of memory wrappers + + Note: + It is not expected that this class will be instantiated under normal + circumstances however, it is useful for type checking + """ + + __slots__: list[str] = [] + + +class MemoryReadWriteLegacy(MemoryReadOnlyLegacy, MemoryWriteOnlyLegacy, ABC): + """ + base class of memory wrappers + + Note: + It is not expected that this class will be instantiated under normal + circumstances however, it is useful for type checking + """ + + __slots__: list[str] = [] + + +class MemoryReadOnlyArray(NodeArray, ABC): + """ + base class for a array of read only memories + """ + __slots__: list[str] = [] + + # pylint: disable-next=too-many-arguments + def __init__(self, *, + logger_handle: str, inst_name: str, + parent: AddressMap, + address: int, + stride: int, + dimensions: tuple[int, ...]): + + super().__init__(logger_handle=logger_handle, inst_name=inst_name, + parent=parent, address=address, + stride=stride, dimensions=dimensions) + + +class MemoryWriteOnlyArray(NodeArray, ABC): + """ + base class for a array of write only memories + """ + __slots__: list[str] = [] + + # pylint: disable-next=too-many-arguments + def __init__(self, *, + logger_handle: str, inst_name: str, + parent: AddressMap, + address: int, + stride: int, + dimensions: tuple[int, ...]): + + super().__init__(logger_handle=logger_handle, inst_name=inst_name, + parent=parent, address=address, + stride=stride, dimensions=dimensions) + + +class MemoryReadWriteArray(MemoryReadOnlyArray, MemoryWriteOnlyArray, ABC): + """ + base class for a array of read and write memories + """ + __slots__: list[str] = [] + + # pylint: disable-next=too-many-arguments + def __init__(self, *, + logger_handle: str, inst_name: str, + parent: AddressMap, + address: int, + stride: int, + dimensions: tuple[int, ...]): + + if not isinstance(parent, AddressMap): + raise TypeError(f'parent should be either AddressMap got {type(parent)}') + + super().__init__(logger_handle=logger_handle, inst_name=inst_name, + parent=parent, address=address, + stride=stride, dimensions=dimensions) + + +ReadableMemory = Union[MemoryReadOnly, MemoryReadWrite] +WritableMemory = Union[MemoryWriteOnly, MemoryReadWrite] +ReadableMemoryLegacy = Union[MemoryReadOnlyLegacy, MemoryReadWriteLegacy] +WritableMemoryLegacy = Union[MemoryWriteOnlyLegacy, MemoryReadWriteLegacy] +MemoryArray = Union[MemoryReadOnlyArray, MemoryWriteOnlyArray, MemoryReadWriteArray] diff --git a/rdl/outputs/python/msk_top_regs/lib/register_and_field.py b/rdl/outputs/python/msk_top_regs/lib/register_and_field.py new file mode 100644 index 0000000..62df291 --- /dev/null +++ b/rdl/outputs/python/msk_top_regs/lib/register_and_field.py @@ -0,0 +1,1189 @@ +""" +peakrdl-python is a tool to generate Python Register Access Layer (RAL) from SystemRDL +Copyright (C) 2021 - 2023 + +This program is free software: you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation, either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . + +This module is intended to distributed as part of automatically generated code by the +peakrdl-python tool. It provides a set of classes used by the autogenerated code to represent +registers and fields +""" +from enum import Enum +from typing import Union, cast, Optional, TypeVar +from collections.abc import Generator, Iterator +from abc import ABC, abstractmethod +from contextlib import contextmanager +from array import array as Array +import sys +from warnings import warn + +from .base import AddressMap, RegFile +from .utility_functions import get_array_typecode +from .memory import MemoryReadOnly, MemoryWriteOnly, MemoryReadWrite, Memory, \ + ReadableMemory, WritableMemory +from .memory import MemoryReadOnlyLegacy, MemoryWriteOnlyLegacy, MemoryReadWriteLegacy +from .memory import ReadableMemoryLegacy, WritableMemoryLegacy +from .callbacks import NormalCallbackSet, NormalCallbackSetLegacy +from .base_register import BaseReg, BaseRegArray, RegisterWriteVerifyError +from .base_field import FieldEnum, FieldSizeProps, FieldMiscProps, \ + _FieldReadOnlyFramework, _FieldWriteOnlyFramework, FieldType + +# pylint: disable=duplicate-code +if sys.version_info >= (3, 11): + from typing import Self +else: + from typing_extensions import Self +# pylint: enable=duplicate-code + +# pylint: disable=duplicate-code +if sys.version_info >= (3, 10): + # type guarding was introduced in python 3.10 + from typing import TypeGuard +else: + from typing_extensions import TypeGuard +# pylint: enable=duplicate-code + +# pylint: disable=redefined-slots-in-subclass,too-many-lines + + +class Reg(BaseReg, ABC): + """ + base class of non-async register wrappers + + Note: + It is not expected that this class will be instantiated under normal + circumstances however, it is useful for type checking + """ + + __slots__: list[str] = [] + + # pylint: disable=too-many-arguments,duplicate-code + def __init__(self, *, + address: int, + width: int, + accesswidth: int, + logger_handle: str, + inst_name: str, + parent: Union[AddressMap, RegFile, Memory, 'RegArray']): + + if not isinstance(parent, (AddressMap, RegFile, + MemoryReadOnly, MemoryWriteOnly, MemoryReadWrite, RegArray, + MemoryReadOnlyLegacy, MemoryWriteOnlyLegacy, + MemoryReadWriteLegacy)): + raise TypeError(f'bad parent type got: {type(parent)}') + + if not isinstance(parent._callbacks, (NormalCallbackSet, NormalCallbackSetLegacy)): + raise TypeError(f'callback set type is wrong, got {type(parent._callbacks)}') + + super().__init__(address=address, width=width, accesswidth=accesswidth, + logger_handle=logger_handle, inst_name=inst_name, parent=parent) + + @property + def _callbacks(self) -> Union[NormalCallbackSet, NormalCallbackSetLegacy]: + # pylint: disable=protected-access + if self.parent is None: + raise RuntimeError('Parent must be set') + + if isinstance(self.parent._callbacks, (NormalCallbackSet, NormalCallbackSetLegacy)): + return self.parent._callbacks + + raise TypeError(f'unhandled parent callback type: {type(self.parent._callbacks)}') + + @property + @abstractmethod + def fields(self) -> Iterator[Union['FieldReadOnly', 'FieldWriteOnly', 'FieldReadWrite']]: + """ + generator that produces has all the fields within the register + """ + + +# pylint: disable-next=invalid-name +RegArrayElementType= TypeVar('RegArrayElementType', bound=BaseReg) + + +class RegArray(BaseRegArray, ABC): + """ + base class of register array wrappers + + Note: + It is not expected that this class will be instantiated under normal + circumstances however, it is useful for type checking + """ + # pylint: disable=too-many-arguments,duplicate-code + + __slots__: list[str] = ['__in_context_manager', '__register_cache', + '__register_address_array'] + + def __init__(self, *, + logger_handle: str, inst_name: str, + parent: Union[AddressMap, RegFile, Memory], + width: int, + accesswidth: int, + address: int, + stride: int, + dimensions: tuple[int, ...], + elements: Optional[dict[tuple[int, ...], RegArrayElementType]] = None): + + self.__in_context_manager: bool = False + self.__register_cache: Optional[Union[Array, list[int]]] = None + self.__register_address_array: Optional[list[int]] = None + + if not isinstance(parent._callbacks, (NormalCallbackSet, NormalCallbackSetLegacy)): + raise TypeError(f'callback set type is wrong, got {type(parent._callbacks)}') + + super().__init__(logger_handle=logger_handle, inst_name=inst_name, + parent=parent, address=address, width=width, accesswidth=accesswidth, + stride=stride, dimensions=dimensions, elements=elements) + + @property + def __empty_array_cache(self) -> Array: + return Array(get_array_typecode(self.width), self.__empty_list_cache) + + @property + def __empty_list_cache(self) -> list[int]: + return [0 for _ in range(self.__number_cache_entries)] + + def __block_read_legacy(self) -> Array: + """ + Read all the contents of the array in the most optimal way, ideally with a block operation + """ + if not isinstance(self._callbacks, NormalCallbackSetLegacy): + raise RuntimeError('This function should only be used with legacy callbacks') + + read_block_callback = self._callbacks.read_block_callback + read_callback = self._callbacks.read_callback + + if read_block_callback is not None: + data_read = read_block_callback(addr=self.address, width=self.width, + accesswidth=self.accesswidth, + length=self.__number_cache_entries) + + if not isinstance(data_read, Array): + raise TypeError('The read block callback is expected to return an array') + + return data_read + + if read_callback is not None: + # there is not read_block_callback defined so we must used individual read + data_array = self.__empty_array_cache + + if self.__register_address_array is None: + raise RuntimeError('This address array has not be initialised') + + for entry, address in enumerate(self.__register_address_array): + data_entry = read_callback(addr=address, + width=self.width, + accesswidth=self.accesswidth) + + data_array[entry] = data_entry + + return data_array + + raise RuntimeError('There is no usable callback') + + def __block_write_legacy(self, data: Array, verify: bool) -> None: + """ + Write all the contents of the array in the most optimal way, ideally with a block operation + """ + if not isinstance(self._callbacks, NormalCallbackSetLegacy): + raise RuntimeError('This function should only be used with legacy callbacks') + + write_block_callback = self._callbacks.write_block_callback + write_callback = self._callbacks.write_callback + + if write_block_callback is not None: + write_block_callback(addr=self.address, + width=self.width, + accesswidth=self.width, + data=data) + + elif write_callback is not None: + # there is not write_block_callback defined so we must used individual write + + if self.__register_address_array is None: + raise RuntimeError('This address array has not be initialised') + + for entry_index, entry_data in enumerate(data): + entry_address = self.__register_address_array[entry_index] + write_callback(addr=entry_address, + width=self.width, + accesswidth=self.accesswidth, + data=entry_data) + + else: + raise RuntimeError('No suitable callback') + + if verify: + read_back_verify_data = self.__block_read_legacy() + if read_back_verify_data != data: + raise RegisterWriteVerifyError('Read back block miss-match') + + def __block_read(self) -> list[int]: + """ + Read all the contents of the array in the most optimal way, ideally with a block operation + """ + if not isinstance(self._callbacks, NormalCallbackSet): + raise RuntimeError('This function should only be used with non-legacy callbacks') + + read_block_callback = self._callbacks.read_block_callback + read_callback = self._callbacks.read_callback + + if read_block_callback is not None: + data_read = \ + read_block_callback(addr=self.address, + width=self.width, + accesswidth=self.accesswidth, + length=self.__number_cache_entries) + + if not isinstance(data_read, list): + if isinstance(data_read, Array): + raise TypeError('The read block callback is expected to return an list, this ' + 'is likely to happen if you are using legacy callbacks without ' + 'NormalCallbackSetLegacy') + raise TypeError('The read block callback is expected to return an list') + return data_read + + if read_callback is not None: + # there is not read_block_callback defined so we must used individual read + data_list = self.__empty_list_cache + + if self.__register_address_array is None: + raise RuntimeError('This address array has not be initialised') + + for entry, address in enumerate(self.__register_address_array): + data_entry = read_callback(addr=address, + width=self.width, + accesswidth=self.accesswidth) + + data_list[entry] = data_entry + + return data_list + + raise RuntimeError('There is no usable callback') + + def __block_write(self, data: list[int], verify: bool) -> None: + """ + Write all the contents of the array in the most optimal way, ideally with a block operation + """ + if not isinstance(self._callbacks, NormalCallbackSet): + raise RuntimeError('This function should only be used with non-legacy callbacks') + + write_block_callback = self._callbacks.write_block_callback + write_callback = self._callbacks.write_callback + + if write_block_callback is not None: + write_block_callback(addr=self.address, + width=self.width, + accesswidth=self.width, + data=data) + + elif write_callback is not None: + # there is not write_block_callback defined so we must used individual write + + if self.__register_address_array is None: + raise RuntimeError('This address array has not be initialised') + + for entry_index, entry_data in enumerate(data): + entry_address = self.__register_address_array[entry_index] + write_callback(addr=entry_address, + width=self.width, + accesswidth=self.accesswidth, + data=entry_data) + + else: + raise RuntimeError('No suitable callback') + + if verify: + read_back_verify_data = self.__block_read() + if read_back_verify_data != data: + raise RegisterWriteVerifyError('Read back block miss-match') + + def __cache_entry(self, addr: int, width: int, accesswidth: int) -> int: + """ + Validate the data provided and determine the cache entry + + Args: + addr: Address to write to + width: Width of the register in bits + accesswidth: Minimum access width of the register in bits + + Returns: + cache entry + + """ + if not isinstance(width, int): + raise TypeError(f'Width should be an int byt got {type(width)}') + if width != self.width: + raise ValueError('Requested Read width does not match the expected value') + if not isinstance(accesswidth, int): + raise TypeError(f'accesswidth should be an int byt got {type(accesswidth)}') + if accesswidth != self.accesswidth: + raise ValueError('Requested Read accesswidth does not match the expected value') + if not isinstance(addr, int): + raise TypeError(f'addr should be an int byt got {type(addr)}') + if not self.address <= addr < (self.address + self.size): + raise ValueError(f'Requested address 0x{addr:X} is out of range 0x{self.address:X} to ' + f'0x{self.address + self.size - (self.width >> 3):X}') + cache_entry = (addr - self.address) // (self.width >> 3) + if self.__register_address_array is None: + raise RuntimeError('The address table should always be populated here') + if self.__register_address_array[cache_entry] != addr: + raise RuntimeError(f'The calculated cache entry for address 0x{addr:X}') + return cache_entry + + def __cache_read(self, addr: int, width: int, accesswidth: int) -> int: + """ + Used to replace the normal callbacks with those that access the cache + + Args: + addr: Address to write to + width: Width of the register in bits + accesswidth: Minimum access width of the register in bits + + Returns: + value inputted by the used + """ + if self.__register_cache is None: + raise RuntimeError('The cache array should be initialised') + return self.__register_cache[self.__cache_entry(addr=addr, + width=width, + accesswidth=accesswidth)] + + def __cache_write(self, addr: int, width: int, accesswidth: int, data: int) -> None: + """ + Used to replace the normal callbacks with those that access the cache + + Args: + addr: Address to write to + width: Width of the register in bits + accesswidth: Minimum access width of the register in bits + data: value to be written to the register + + Returns: + None + """ + if not isinstance(data, int): + raise TypeError(f'Data should be an int byt got {type(data)}') + if self.__register_cache is None: + raise RuntimeError('The cache array should be initialised') + self.__register_cache[self.__cache_entry(addr=addr, + width=width, + accesswidth=accesswidth)] = data + + @property + def __cache_callbacks(self) -> NormalCallbackSet: + return NormalCallbackSet(read_callback=self.__cache_read, + write_callback=self.__cache_write) + + @property + def __number_cache_entries(self) -> int: + return self.size // (self.width >> 3) + + def __initialise_cache(self, skip_initial_read: bool) -> Union[Array, list[int]]: + if isinstance(self._callbacks, NormalCallbackSet): + if skip_initial_read: + return self.__empty_list_cache + return self.__block_read() + + if isinstance(self._callbacks, NormalCallbackSetLegacy): + if skip_initial_read: + return self.__empty_array_cache + return self.__block_read_legacy() + + raise TypeError('Unhandled callback type') + + @contextmanager + def _cached_access(self, verify: bool = False, skip_write: bool = False, + skip_initial_read: bool = False) -> \ + Generator[Self]: + """ + Context manager to allow multiple field reads/write to be done with a single set of + field operations + + Args: + verify (bool): very the write with a read afterwards + skip_write (bool): skip the write back at the end + """ + self.__register_address_array = \ + [self.address + (i * (self.width >> 3)) for i in range(self.__number_cache_entries)] + self.__register_cache = self.__initialise_cache(skip_initial_read=skip_initial_read) + self.__in_context_manager = True + # this try/finally is needed to make sure that in the event of an exception + # the state flags are not left incorrectly set + try: + yield self + finally: + self.__in_context_manager = False + if not skip_write: + if isinstance(self._callbacks, NormalCallbackSet): + if not isinstance(self.__register_cache, list): + raise TypeError('Register cache should be a list in non-legacy mode') + self.__block_write(self.__register_cache, verify) + if isinstance(self._callbacks, NormalCallbackSetLegacy): + if not isinstance(self.__register_cache, Array): + raise TypeError('Register cache should be a Array in legacy mode') + self.__block_write_legacy(self.__register_cache, verify) + + # clear the register states at the end of the context manager + self.__register_address_array = None + self.__register_cache = None + + @property + def _callbacks(self) -> NormalCallbackSet: + + if self.__in_context_manager: + return self.__cache_callbacks + + if self.parent is None: + raise RuntimeError('Parent must be set') + # This cast is OK because the type was checked in the __init__ + # pylint: disable-next=protected-access + return cast(NormalCallbackSet, self.parent._callbacks) + + +class RegReadOnly(Reg, ABC): + """ + class for a read only register + + Args: + address: address of the register + width: width of the register in bits + accesswidth: minimum access width of the register in bits + logger_handle: name to be used logging messages associate with this + object + + """ + + __slots__: list[str] = ['__in_context_manager', '__register_state'] + + # pylint: disable=too-many-arguments, duplicate-code + def __init__(self, *, + address: int, + width: int, + accesswidth: int, + logger_handle: str, + inst_name: str, + parent: Union[AddressMap, RegFile, ReadableMemory, ReadableMemoryLegacy ]): + + super().__init__(address=address, + logger_handle=logger_handle, + inst_name=inst_name, + parent=parent, width=width, accesswidth=accesswidth) + + self.__in_context_manager: bool = False + self.__register_state: int = 0 + + # pylint: enable=too-many-arguments, duplicate-code + + @contextmanager + def single_read(self) -> Generator[Self]: + """ + Context manager to allow multiple field accesses to be performed with a single + read of the register + """ + self.__register_state = self.read() + self.__in_context_manager = True + # this try/finally is needed to make sure that in the event of an exception + # the state flags are not left incorrectly set + try: + yield self + finally: + self.__in_context_manager = False + + def read(self) -> int: + """ + Read value from the register + """ + if self.__in_context_manager: + return self.__register_state + + read_block_callback = self._callbacks.read_block_callback + read_callback = self._callbacks.read_callback + + if read_callback is not None: + return read_callback(addr=self.address, + width=self.width, + accesswidth=self.accesswidth) + + if read_block_callback is not None: + return read_block_callback(addr=self.address, + width=self.width, + accesswidth=self.accesswidth, + length=1)[0] + + raise RuntimeError('This function does not have a useable callback') + + @property + def readable_fields(self) -> Iterator[Union['FieldReadOnly', 'FieldReadWrite']]: + """ + generator that produces has all the readable fields within the register + """ + def is_readable(field: Union['FieldReadOnly', 'FieldWriteOnly', 'FieldReadWrite']) -> \ + TypeGuard[Union['FieldReadOnly', 'FieldReadWrite']]: + return isinstance(field, (FieldReadOnly, FieldReadWrite)) + + return filter(is_readable, self.fields) + + def read_fields(self) -> dict['str', Union[bool, Enum, int]]: + """ + read the register and return a dictionary of the field values + """ + return_dict: dict['str', Union[bool, Enum, int]] = {} + with self.single_read() as reg: + for field in reg.readable_fields: + return_dict[field.inst_name] = field.read() + + return return_dict + + @property + def _is_readable(self) -> bool: + # pylint: disable=duplicate-code + return True + + @property + def _is_writeable(self) -> bool: + # pylint: disable=duplicate-code + return False + + +class RegWriteOnly(Reg, ABC): + """ + class for a write only register + """ + + __slots__: list[str] = [] + + # pylint: disable=too-many-arguments, duplicate-code, useless-parent-delegation + def __init__(self, *, + address: int, + width: int, + accesswidth: int, + logger_handle: str, + inst_name: str, + parent: Union[AddressMap, RegFile, WritableMemory, WritableMemoryLegacy]): + + super().__init__(address=address, + logger_handle=logger_handle, + inst_name=inst_name, + parent=parent, width=width, accesswidth=accesswidth) + # pylint: enable=too-many-arguments, duplicate-code + + def write(self, data: int) -> None: + """Writes a value to the register + + Args: + data: data to be written + + Raises: + ValueError: if the value provided is outside the range of the + permissible values for the register + TypeError: if the type of data is wrong + """ + # this method check the types and range checks the data + self._validate_data(data=data) + + self._logger.info('Writing data:%X to %X', data, self.address) + + if self._callbacks.write_callback is not None: + self._callbacks.write_callback(addr=self.address, + width=self.width, + accesswidth=self.accesswidth, + data=data) # + + elif self._callbacks.write_block_callback is not None: + if isinstance(self._callbacks, NormalCallbackSetLegacy): + data_as_array = Array(get_array_typecode(self.width), [data]) + self._callbacks.write_block_callback(addr=self.address, + width=self.width, + accesswidth=self.accesswidth, + data=data_as_array) + + if isinstance(self._callbacks, NormalCallbackSet): + self._callbacks.write_block_callback(addr=self.address, + width=self.width, + accesswidth=self.accesswidth, + data=[data]) + + else: + raise RuntimeError('This function does not have a useable callback') + + @property + def writable_fields(self) -> Iterator[Union['FieldWriteOnly', 'FieldReadWrite']]: + """ + generator that produces has all the readable fields within the register + """ + def is_writable(field: Union['FieldReadOnly', 'FieldWriteOnly', 'FieldReadWrite']) -> \ + TypeGuard[Union['FieldWriteOnly', 'FieldReadWrite']]: + return isinstance(field, (FieldWriteOnly, FieldReadWrite)) + + return filter(is_writable, self.fields) + + @abstractmethod + def write_fields(self, **kwargs) -> None: # type: ignore[no-untyped-def] + """ + Do a write to the register, updating any field included in + the arguments + """ + + @property + def _is_readable(self) -> bool: + # pylint: disable=duplicate-code + return False + + @property + def _is_writeable(self) -> bool: + # pylint: disable=duplicate-code + return True + + +class RegReadWrite(RegReadOnly, RegWriteOnly, ABC): + """ + class for a read and write only register + + """ + __slots__: list[str] = ['__in_read_write_context_manager', '__in_read_context_manager', + '__register_state'] + + # pylint: disable=too-many-arguments, duplicate-code + def __init__(self, *, + address: int, + width: int, + accesswidth: int, + logger_handle: str, + inst_name: str, + parent: Union[AddressMap, RegFile, MemoryReadWrite, MemoryReadWriteLegacy]): + + super().__init__(address=address, + logger_handle=logger_handle, + inst_name=inst_name, + parent=parent, width=width, accesswidth=accesswidth) + + self.__in_read_write_context_manager: bool = False + self.__in_read_context_manager: bool = False + self.__register_state: Optional[int] = None + + # pylint: enable=too-many-arguments, duplicate-code + + @contextmanager + def single_read_modify_write(self, verify: bool = False, skip_write: bool = False) -> \ + Generator[Self]: + """ + Context manager to allow multiple field reads/write to be done with a single set of + field operations + + Args: + verify (bool): very the write with a read afterwards + skip_write (bool): skip the write back at the end + + """ + if self.__in_read_context_manager: + raise RuntimeError('using the `single_read_modify_write` context manager within the ' + 'single_read` is not permitted') + + if skip_write is True: + warn('The `skip_write` argument will be removed in the future, use `single_read`' + ' instead', + DeprecationWarning, stacklevel=2) + + self.__register_state = self.read() + self.__in_read_write_context_manager = True + try: + yield self + finally: + # need to make sure the state flag is cleared even if an exception occurs within + # the context + self.__in_read_write_context_manager = False + + if not skip_write: + self.write(self.__register_state, verify) + + # clear the register states at the end of the context manager + self.__register_state = None + + @contextmanager + def single_read(self) -> \ + Generator[Self]: + """ + Context manager to allow multiple field reads with a single register read + """ + if self.__in_read_write_context_manager: + raise RuntimeError('using the `single_read` context manager within the ' + 'single_read_modify_write` is not permitted') + self.__in_read_context_manager = True + try: + with super().single_read() as reg: + yield reg + finally: + self.__in_read_context_manager = False + + def write(self, data: int, verify: bool = False) -> None: # pylint: disable=arguments-differ + """ + Writes a value to the register + + Args: + data: data to be written + verify: set to True to read back the register to verify the read has occurred correctly + + Raises: + ValueError: if the value provided is outside the range of the + permissible values for the register + TypeError: if the type of data is wrong + RegisterWriteVerifyError: the read back data after the write does not match the + expected value + """ + if self.__in_read_context_manager: + raise RuntimeError('writes within the single read context manager are not permitted') + + if self.__in_read_write_context_manager: + if self.__register_state is None: + raise RuntimeError('The internal register state should never be None in the ' + 'context manager') + self.__register_state = data + else: + super().write(data) + if verify: + read_back = self.read() + if read_back != data: + raise RegisterWriteVerifyError(f'Readback {read_back:X} ' + f'after writing {data:X}') + + def read(self) -> int: + """ + Read value from the register + """ + if self.__in_read_write_context_manager: + if self.__register_state is None: + raise RuntimeError('The internal register state should never be None in the ' + 'context manager') + return self.__register_state + + # the single read context manager is handled in the base class so does need any + # handling here + + return super().read() + + def write_fields(self, **kwargs) -> None: # type: ignore[no-untyped-def] + """ + Do a read-modify-write to the register, updating any field included in + the arguments + """ + if len(kwargs) == 0: + raise ValueError('no command args') + + with self.single_read_modify_write() as reg: + for field_name, field_value in kwargs.items(): + if field_name not in reg.systemrdl_python_child_name_map.values(): + raise ValueError(f'{field_name} is not a member of the register') + + field = getattr(reg, field_name) + field.write(field_value) + + def read_fields(self) -> dict['str', Union[bool, Enum, int]]: + """ + read the register and return a dictionary of the field values + """ + return_dict: dict['str', Union[bool, Enum, int]] = {} + with self.single_read() as reg: + for field in reg.readable_fields: + return_dict[field.inst_name] = field.read() + + return return_dict + + @property + def _is_readable(self) -> bool: + # pylint: disable=duplicate-code + return True + + @property + def _is_writeable(self) -> bool: + # pylint: disable=duplicate-code + return True + + +ReadableRegister = Union[RegReadOnly, RegReadWrite] +WritableRegister = Union[RegWriteOnly, RegReadWrite] + + +class RegReadOnlyArray(RegArray, ABC): + """ + base class for a array of read only registers + """ + __slots__: list[str] = [] + + # pylint: disable=too-many-arguments,duplicate-code + def __init__(self, *, + logger_handle: str, inst_name: str, + parent: Union[RegFile, AddressMap, ReadableMemory, ReadableMemoryLegacy], + address: int, + width: int, + accesswidth: int, + stride: int, + dimensions: tuple[int, ...], + elements: Optional[dict[tuple[int, ...], RegReadOnly]] = None): + + if not isinstance(parent, (RegFile, AddressMap, MemoryReadOnly, MemoryReadWrite, + MemoryReadOnlyLegacy, MemoryReadWriteLegacy)): + raise TypeError('parent should be either RegFile, AddressMap, ' + 'MemoryReadOnly, MemoryReadWrite ' + f'got {type(parent)}') + + if not isinstance(parent._callbacks, (NormalCallbackSet, NormalCallbackSetLegacy)): + raise TypeError(f'callback set type is wrong, got {type(parent._callbacks)}') + + super().__init__(logger_handle=logger_handle, inst_name=inst_name, + parent=parent, address=address, width=width, accesswidth=accesswidth, + stride=stride, dimensions=dimensions, elements=elements) + # pylint: enable=too-many-arguments,duplicate-code + + @contextmanager + def single_read(self) -> \ + Generator[Self]: + """ + Context manager to allow multiple field reads/write to be done with a single set of + field operations + """ + with self._cached_access(verify=False, skip_write=True, + skip_initial_read=False) as reg_array: + yield reg_array + + @property + def _is_readable(self) -> bool: + # pylint: disable=duplicate-code + return True + + @property + def _is_writeable(self) -> bool: + # pylint: disable=duplicate-code + return False + + +class RegWriteOnlyArray(RegArray, ABC): + """ + base class for a array of write only registers + """ + __slots__: list[str] = [] + + # pylint: disable=too-many-arguments,duplicate-code + def __init__(self, *, + logger_handle: str, inst_name: str, + parent: Union[RegFile, AddressMap, WritableMemory, WritableMemoryLegacy], + address: int, + width: int, + accesswidth: int, + stride: int, + dimensions: tuple[int, ...], + elements: Optional[dict[tuple[int, ...], RegWriteOnly]] = None): + + if not isinstance(parent, (RegFile, AddressMap, MemoryWriteOnly, MemoryReadWrite, + MemoryWriteOnlyLegacy, MemoryReadWriteLegacy)): + raise TypeError('parent should be either RegFile, AddressMap, MemoryWriteOnly, ' + 'MemoryReadWrite ' + f'got {type(parent)}') + + if not isinstance(parent._callbacks, (NormalCallbackSet, NormalCallbackSetLegacy)): + raise TypeError(f'callback set type is wrong, got {type(parent._callbacks)}') + + super().__init__(logger_handle=logger_handle, inst_name=inst_name, + parent=parent, address=address, width=width, accesswidth=accesswidth, + stride=stride, dimensions=dimensions, elements=elements) + # pylint: enable=too-many-arguments,duplicate-code + + @contextmanager + def single_write(self) -> \ + Generator[Self]: + """ + Context manager to allow multiple field reads/write to be done with a single set of + field operations + """ + with self._cached_access(verify=False, skip_write=False, + skip_initial_read=True) as reg_array: + yield reg_array + + @property + def _is_readable(self) -> bool: + # pylint: disable=duplicate-code + return False + + @property + def _is_writeable(self) -> bool: + # pylint: disable=duplicate-code + return True + + +class RegReadWriteArray(RegArray, ABC): + """ + base class for a array of read and write registers + """ + __slots__: list[str] = [] + + # pylint: disable=too-many-arguments,duplicate-code + def __init__(self, *, + logger_handle: str, inst_name: str, + parent: Union[RegFile, AddressMap, MemoryReadWrite, MemoryReadWriteLegacy], + address: int, + width: int, + accesswidth: int, + stride: int, + dimensions: tuple[int, ...], + elements: Optional[dict[tuple[int, ...], RegReadWrite]] = None): + + if not isinstance(parent, (RegFile, AddressMap, MemoryReadWrite, MemoryReadWriteLegacy)): + raise TypeError('parent should be either RegFile, AddressMap, MemoryReadWrite ' + f'got {type(parent)}') + + if not isinstance(parent._callbacks, (NormalCallbackSet, NormalCallbackSetLegacy)): + raise TypeError(f'callback set type is wrong, got {type(parent._callbacks)}') + + super().__init__(logger_handle=logger_handle, inst_name=inst_name, + parent=parent, address=address, width=width, accesswidth=accesswidth, + stride=stride, dimensions=dimensions, elements=elements) + + # pylint: enable=too-many-arguments,duplicate-code + + @contextmanager + def single_read_modify_write(self, verify: bool = False, skip_write: bool = False) -> \ + Generator[Self]: + """ + Context manager to allow multiple field reads/write to be done with a single set of + field operations + + Args: + verify (bool): very the write with a read afterwards + skip_write (bool): skip the write back at the end + """ + with self._cached_access(verify=verify, skip_write=skip_write, + skip_initial_read=False) as reg_array: + yield reg_array + + @property + def _is_readable(self) -> bool: + # pylint: disable=duplicate-code + return True + + @property + def _is_writeable(self) -> bool: + # pylint: disable=duplicate-code + return True + + +ReadableRegisterArray = Union[RegReadOnlyArray, RegReadWriteArray] +WriteableRegisterArray = Union[RegWriteOnlyArray, RegReadWriteArray] + + +class FieldReadOnly(_FieldReadOnlyFramework[FieldType], ABC): + """ + class for a read only register field + + Args: + parent_register: register within which the field resides + size_props: object defining the msb, lsb, high bit, low bit and width + logger_handle: name to be used logging messages associate with this + object + + """ + __slots__: list[str] = [] + + # pylint: disable-next=too-many-arguments + def __init__(self, *, + parent_register: ReadableRegister, + size_props: FieldSizeProps, + misc_props: FieldMiscProps, + logger_handle: str, + inst_name: str, + field_type:type[FieldType]): + + if not isinstance(parent_register, (RegReadWrite, RegReadOnly)): + raise TypeError(f'size_props must be of {type(RegReadWrite)} or {type(RegReadOnly)} ' + f'but got {type(parent_register)}') + + # pylint: disable=duplicate-code + super().__init__(logger_handle=logger_handle, + size_props=size_props, + misc_props=misc_props, + parent_register=parent_register, + inst_name=inst_name, + field_type=field_type) + # pylint: enable=duplicate-code + + def read(self) -> FieldType: + """ + Reads the register that this field is located in and retries the field + value applying the required masking and shifting + + Returns: + field value + + """ + return self._decode_read_value(self.parent_register.read()) + + @property + def parent_register(self) -> ReadableRegister: + """ + parent register the field is placed in + """ + + # this cast is OK because an explict typing check was done in the __init__ + return cast(ReadableRegister, self.parent) + + +class FieldWriteOnly(_FieldWriteOnlyFramework[FieldType], ABC): + """ + class for a write only register field + + Args: + parent_register: register within which the field resides + size_props: object defining the msb, lsb, high bit, low bit and width + logger_handle: name to be used logging messages associate with this + object + + """ + __slots__: list[str] = [] + + # pylint: disable-next=too-many-arguments + def __init__(self, *, + parent_register: WritableRegister, + size_props: FieldSizeProps, + misc_props: FieldMiscProps, + logger_handle: str, + inst_name: str, + field_type:type[FieldType]): + + if not isinstance(parent_register, (RegReadWrite, RegWriteOnly)): + raise TypeError(f'size_props must be of {type(RegReadWrite)} or {type(RegWriteOnly)} ' + f'but got {type(parent_register)}') + + # pylint: disable=duplicate-code + super().__init__(logger_handle=logger_handle, + size_props=size_props, + misc_props=misc_props, + parent_register=parent_register, + inst_name=inst_name, + field_type=field_type) + # pylint: enable=duplicate-code + + def write(self, value: FieldType) -> None: + """ + The behaviour of this method depends on whether the field is located in + a readable register or not: + + If the register is readable, the method will perform a read-modify-write + on the register updating the field with the value provided + + If the register is not writable all other field values will be written + with zero. + + Args: + value: field value to update to + + """ + encoded_value = self._encode_write_value(value) + + if (self.high == (self.register_data_width - 1)) and (self.low == 0): + # special case where the field occupies the whole register, + # there a straight write can be performed + new_reg_value = encoded_value + else: + # do a read, modify write + if isinstance(self.parent_register, RegReadWrite): + reg_value = self.parent_register.read() + masked_reg_value = reg_value & self.inverse_bitmask + new_reg_value = masked_reg_value | encoded_value + elif isinstance(self.parent_register, RegWriteOnly): + new_reg_value = encoded_value + else: + raise TypeError('Unhandled parent type') + + self.parent_register.write(new_reg_value) + + @property + def parent_register(self) -> WritableRegister: + """ + parent register the field is placed in + """ + + # this cast is OK because an explict typing check was done in the __init__ + return cast(WritableRegister, self.parent) + + +class FieldReadWrite(FieldReadOnly[FieldType], FieldWriteOnly[FieldType], ABC): + """ + class for a read/write register field + + Args: + parent_register: register within which the field resides + size_props: object defining the msb, lsb, high bit, low bit and width + logger_handle: name to be used logging messages associate with this + object + + """ + __slots__: list[str] = [] + + # pylint: disable-next=too-many-arguments + def __init__(self, *, + parent_register: RegReadWrite, + size_props: FieldSizeProps, + misc_props: FieldMiscProps, + logger_handle: str, + inst_name: str, + field_type:type[FieldType]): + + if not isinstance(parent_register, RegReadWrite): + raise TypeError(f'parent_register must be of {type(RegReadWrite)} ' + f'but got {type(parent_register)}') + + super().__init__(logger_handle=logger_handle, + size_props=size_props, + misc_props=misc_props, + parent_register=parent_register, + inst_name=inst_name, + field_type=field_type) + + @property + def parent_register(self) -> RegReadWrite: + """ + parent register the field is placed in + """ + + # this cast is OK because an explict typing check was done in the __init__ + return cast(RegReadWrite, self.parent) + + +class FieldEnumReadWrite(FieldReadWrite[FieldType], FieldEnum[FieldType], ABC): + """ + class for a read/write register field with an enumerated value + """ + __slots__: list[str] = [] + + @property + def parent_register(self) -> RegReadWrite: + """ + parent register the field is placed in + """ + + # this cast is OK because an explict typing check was done in the __init__ + return cast(RegReadWrite, self.parent) + + +class FieldEnumReadOnly(FieldReadOnly[FieldType], FieldEnum[FieldType], ABC): + """ + class for a read only register field with an enumerated value + """ + __slots__: list[str] = [] + + +class FieldEnumWriteOnly(FieldWriteOnly[FieldType], FieldEnum[FieldType], ABC): + """ + class for a write only register field with an enumerated value + """ + __slots__: list[str] = [] diff --git a/rdl/outputs/python/msk_top_regs/lib/utility_functions.py b/rdl/outputs/python/msk_top_regs/lib/utility_functions.py new file mode 100644 index 0000000..6c9113d --- /dev/null +++ b/rdl/outputs/python/msk_top_regs/lib/utility_functions.py @@ -0,0 +1,83 @@ +""" +peakrdl-python is a tool to generate Python Register Access Layer (RAL) from SystemRDL +Copyright (C) 2021 - 2023 + +This program is free software: you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation, either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . + +This module is intended to distributed as part of automatically generated code by the +peakrdl-python tool. It provides a set of base classes used by the autogenerated code +""" + + +def swap_msb_lsb_ordering(width: int, value: int) -> int: + """ + swaps the msb/lsb on a integer + + Returns: + swapped value + """ + value_to_return = 0 + for bit_positions in zip(range(0, width), range(width-1, -1, -1)): + bit_value = (value >> bit_positions[0]) & 0x1 + value_to_return |= bit_value << bit_positions[1] + + return value_to_return + + +class UnsupportedWidthError(Exception): + """ + Exception for width that can not be supported in the legacy array based API + """ + + +def get_array_typecode(width: int) -> str: + """ + python array typecode + + Args: + width: in bits + + Returns: + string to pass into the array generator + + """ + if width == 32: + return 'L' + + if width == 64: + return 'Q' + + if width == 16: + return 'I' + + if width == 8: + return 'B' + + raise UnsupportedWidthError(f'unhandled width {width:d}, consider using the new new list ' + f'based API and callbacks rather than the legacy Array versions') + + +def is_power_two(value: int) -> bool: + """ + efficient algorithm for checking if something is a power of two + """ + return (value != 0) and ((value & (value - 1)) == 0) + + +def legal_register_width(width_in_bits: int) -> bool: + """ + check if a register width is legal, see the system RDL specification 10.1 e) and f) + must be a power of 2 and greater than 8 + """ + return (width_in_bits >= 8) and is_power_two(width_in_bits) diff --git a/rdl/outputs/python/msk_top_regs/reg_model/__init__.py b/rdl/outputs/python/msk_top_regs/reg_model/__init__.py new file mode 100644 index 0000000..2ae2839 --- /dev/null +++ b/rdl/outputs/python/msk_top_regs/reg_model/__init__.py @@ -0,0 +1 @@ +pass diff --git a/rdl/outputs/python/msk_top_regs/reg_model/msk_top_regs.py b/rdl/outputs/python/msk_top_regs/reg_model/msk_top_regs.py new file mode 100644 index 0000000..8ea7fa8 --- /dev/null +++ b/rdl/outputs/python/msk_top_regs/reg_model/msk_top_regs.py @@ -0,0 +1,9451 @@ + + + +""" +Python Wrapper for the msk_top_regs register model + +This code was generated from the PeakRDL-python package version 1.4.0 + +""" + + +from enum import unique +from typing import Iterator +from typing import Optional +from typing import Union +from typing import Type +from typing import overload +from typing import Literal +from typing import Any +from typing import NoReturn +from typing import AsyncGenerator + +import warnings + + + +from contextlib import asynccontextmanager + +from ..lib import Node, Base +from ..lib import UDPStruct + +from ..lib import AddressMapArray, RegFileArray +from ..lib import AsyncMemory, AsyncMemoryArray +from ..lib import AsyncAddressMap +from ..lib import AsyncRegFile +from ..lib import AsyncAddressMapArray +from ..lib import AsyncRegFileArray +from ..lib import MemoryAsyncReadOnly, MemoryAsyncWriteOnly, MemoryAsyncReadWrite +from ..lib import MemoryAsyncReadOnlyArray, MemoryAsyncWriteOnlyArray, MemoryAsyncReadWriteArray +from ..lib import AsyncReg, AsyncRegArray +from ..lib import RegAsyncReadOnly, RegAsyncWriteOnly, RegAsyncReadWrite +from ..lib import RegAsyncReadOnlyArray, RegAsyncWriteOnlyArray, RegAsyncReadWriteArray +from ..lib import FieldAsyncReadOnly, FieldAsyncWriteOnly, FieldAsyncReadWrite, Field + +from ..lib import ReadableAsyncRegister, WritableAsyncRegister +from ..lib import ReadableAsyncMemory, WritableAsyncMemory +from ..lib import ReadableAsyncRegisterArray, WriteableAsyncRegisterArray +from ..lib import FieldSizeProps, FieldMiscProps + + +from ..lib import SystemRDLEnum, SystemRDLEnumEntry + + + +from ..lib import AsyncCallbackSet, AsyncCallbackSetLegacy + + + + + + + + + + + + + + + + + + + +# regfile, register and field definitions + + + +class msk_top_regs_rx_power_rx_power_cls(FieldAsyncReadOnly): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Receive Power | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Value that represent the RMS power of the incoming I;

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "Receive Power" + @property + def rdl_desc(self) -> str: + return "Value that represent the RMS power of the incoming I;" + + + + + + +class msk_top_regs_rx_power_cls(RegAsyncReadOnly): + """ + Class to represent a register in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Receive Power | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Receive power computed from I/Q ssamples

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = ['__rx_power'] + + def __init__(self, + address: int, + width: int, + accesswidth: int, + logger_handle: str, + inst_name: str, + parent: Union[AsyncAddressMap,AsyncRegFile,ReadableAsyncMemory]): + + super().__init__(address=address, + width=width, + accesswidth=accesswidth, + logger_handle=logger_handle, + inst_name=inst_name, + parent=parent) + + # build the field attributes + + self.__rx_power:msk_top_regs_rx_power_rx_power_cls = msk_top_regs_rx_power_rx_power_cls( + parent_register=self, + size_props=FieldSizeProps( + width=23, + lsb=0, + msb=22, + low=0, + high=22), + misc_props=FieldMiscProps( + default=0, + is_volatile=True), + logger_handle=logger_handle+'.rx_power', + inst_name='rx_power', + field_type=int) + + @property + def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,FieldAsyncReadWrite]]: + """ + generator that produces has all the fields within the register + """ + yield self.rx_power + + # Empty generator in case there are no children of this type + if False: yield + + + + + # build the properties for the fields + + @property + def rx_power(self) -> msk_top_regs_rx_power_rx_power_cls: + """ + Property to access rx_power field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Receive Power | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Value that represent the RMS power of the incoming I;

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__rx_power + + + @property + def systemrdl_python_child_name_map(self) -> dict[str, str]: + """ + In some cases systemRDL names need to be converted make them python safe, this dictionary + is used to map the original systemRDL names to the names of the python attributes of this + class + + Returns: dictionary whose key is the systemRDL names and value it the property name + """ + return {'rx_power':'rx_power', + } + + + + + + + + + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_rx_power_rx_power_cls: + return super().get_child_by_system_rdl_name(name) + + + + + + + + + + @property + def rdl_name(self) -> str: + return "Receive Power" + @property + def rdl_desc(self) -> str: + return "Receive power computed from I/Q ssamples" + + + + + + + +class msk_top_regs_lowpass_ema_alpha_alpha_cls(FieldAsyncReadWrite): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | EMA alpha | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Value from 0x0_0000 to 0x3_FFFF represent the EMA alpha

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "EMA alpha" + @property + def rdl_desc(self) -> str: + return "Value from 0x0_0000 to 0x3_FFFF represent the EMA alpha" + + + + + + +class msk_top_regs_lowpass_ema_alpha_cls(RegAsyncReadWrite): + """ + Class to represent a register in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Exponential Moving Average Alpha | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Sets the alpha for the EMA

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = ['__alpha'] + + def __init__(self, + address: int, + width: int, + accesswidth: int, + logger_handle: str, + inst_name: str, + parent: Union[AsyncAddressMap,AsyncRegFile,MemoryAsyncReadWrite]): + + super().__init__(address=address, + width=width, + accesswidth=accesswidth, + logger_handle=logger_handle, + inst_name=inst_name, + parent=parent) + + # build the field attributes + + self.__alpha:msk_top_regs_lowpass_ema_alpha_alpha_cls = msk_top_regs_lowpass_ema_alpha_alpha_cls( + parent_register=self, + size_props=FieldSizeProps( + width=18, + lsb=0, + msb=17, + low=0, + high=17), + misc_props=FieldMiscProps( + default=0, + is_volatile=False), + logger_handle=logger_handle+'.alpha', + inst_name='alpha', + field_type=int) + + @property + def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,FieldAsyncReadWrite]]: + """ + generator that produces has all the fields within the register + """ + yield self.alpha + + # Empty generator in case there are no children of this type + if False: yield + + + + + # build the properties for the fields + + @property + def alpha(self) -> msk_top_regs_lowpass_ema_alpha_alpha_cls: + """ + Property to access alpha field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | EMA alpha | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Value from 0x0_0000 to 0x3_FFFF represent the EMA alpha

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__alpha + + + @property + def systemrdl_python_child_name_map(self) -> dict[str, str]: + """ + In some cases systemRDL names need to be converted make them python safe, this dictionary + is used to map the original systemRDL names to the names of the python attributes of this + class + + Returns: dictionary whose key is the systemRDL names and value it the property name + """ + return {'alpha':'alpha', + } + + + + + + + + + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_lowpass_ema_alpha_alpha_cls: + return super().get_child_by_system_rdl_name(name) + + + + + + + + + + @property + def rdl_name(self) -> str: + return "Exponential Moving Average Alpha" + @property + def rdl_desc(self) -> str: + return "Sets the alpha for the EMA" + + + + + + + +class msk_top_regs_lowpass_ema_alpha_alpha_0x0x106a859a_cls(FieldAsyncReadWrite): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | EMA alpha | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Value from 0x0_0000 to 0x3_FFFF represent the EMA alpha

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "EMA alpha" + @property + def rdl_desc(self) -> str: + return "Value from 0x0_0000 to 0x3_FFFF represent the EMA alpha" + + + + + + +class msk_top_regs_lowpass_ema_alpha_0x0x106a8591_cls(RegAsyncReadWrite): + """ + Class to represent a register in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Exponential Moving Average Alpha | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Sets the alpha for the EMA

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = ['__alpha'] + + def __init__(self, + address: int, + width: int, + accesswidth: int, + logger_handle: str, + inst_name: str, + parent: Union[AsyncAddressMap,AsyncRegFile,MemoryAsyncReadWrite]): + + super().__init__(address=address, + width=width, + accesswidth=accesswidth, + logger_handle=logger_handle, + inst_name=inst_name, + parent=parent) + + # build the field attributes + + self.__alpha:msk_top_regs_lowpass_ema_alpha_alpha_0x0x106a859a_cls = msk_top_regs_lowpass_ema_alpha_alpha_0x0x106a859a_cls( + parent_register=self, + size_props=FieldSizeProps( + width=18, + lsb=0, + msb=17, + low=0, + high=17), + misc_props=FieldMiscProps( + default=0, + is_volatile=False), + logger_handle=logger_handle+'.alpha', + inst_name='alpha', + field_type=int) + + @property + def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,FieldAsyncReadWrite]]: + """ + generator that produces has all the fields within the register + """ + yield self.alpha + + # Empty generator in case there are no children of this type + if False: yield + + + + + # build the properties for the fields + + @property + def alpha(self) -> msk_top_regs_lowpass_ema_alpha_alpha_0x0x106a859a_cls: + """ + Property to access alpha field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | EMA alpha | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Value from 0x0_0000 to 0x3_FFFF represent the EMA alpha

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__alpha + + + @property + def systemrdl_python_child_name_map(self) -> dict[str, str]: + """ + In some cases systemRDL names need to be converted make them python safe, this dictionary + is used to map the original systemRDL names to the names of the python attributes of this + class + + Returns: dictionary whose key is the systemRDL names and value it the property name + """ + return {'alpha':'alpha', + } + + + + + + + + + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_lowpass_ema_alpha_alpha_0x0x106a859a_cls: + return super().get_child_by_system_rdl_name(name) + + + + + + + + + + @property + def rdl_name(self) -> str: + return "Exponential Moving Average Alpha" + @property + def rdl_desc(self) -> str: + return "Sets the alpha for the EMA" + + + + + + + +class msk_top_regs_tx_sync_cnt_tx_sync_cnt_cls(FieldAsyncReadWrite): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Tx sync duration | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Value from 0x00_0000 to 0xFF_FFFF. This value represents the | + | | number bit-times the synchronization signal should be sent after | + | | PTT is asserted.

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "Tx sync duration" + @property + def rdl_desc(self) -> str: + return "Value from 0x00_0000 to 0xFF_FFFF. \nThis value represents the number bit-times the synchronization \nsignal should be sent after PTT is asserted." + + + + + + +class msk_top_regs_tx_sync_cnt_cls(RegAsyncReadWrite): + """ + Class to represent a register in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Transmitter Sync Duration | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Sets the duration of the synchronization tones when enabled

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = ['__tx_sync_cnt'] + + def __init__(self, + address: int, + width: int, + accesswidth: int, + logger_handle: str, + inst_name: str, + parent: Union[AsyncAddressMap,AsyncRegFile,MemoryAsyncReadWrite]): + + super().__init__(address=address, + width=width, + accesswidth=accesswidth, + logger_handle=logger_handle, + inst_name=inst_name, + parent=parent) + + # build the field attributes + + self.__tx_sync_cnt:msk_top_regs_tx_sync_cnt_tx_sync_cnt_cls = msk_top_regs_tx_sync_cnt_tx_sync_cnt_cls( + parent_register=self, + size_props=FieldSizeProps( + width=24, + lsb=0, + msb=23, + low=0, + high=23), + misc_props=FieldMiscProps( + default=0, + is_volatile=False), + logger_handle=logger_handle+'.tx_sync_cnt', + inst_name='tx_sync_cnt', + field_type=int) + + @property + def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,FieldAsyncReadWrite]]: + """ + generator that produces has all the fields within the register + """ + yield self.tx_sync_cnt + + # Empty generator in case there are no children of this type + if False: yield + + + + + # build the properties for the fields + + @property + def tx_sync_cnt(self) -> msk_top_regs_tx_sync_cnt_tx_sync_cnt_cls: + """ + Property to access tx_sync_cnt field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Tx sync duration | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Value from 0x00_0000 to 0xFF_FFFF. This value represents the | + | | number bit-times the synchronization signal should be sent after | + | | PTT is asserted.

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__tx_sync_cnt + + + @property + def systemrdl_python_child_name_map(self) -> dict[str, str]: + """ + In some cases systemRDL names need to be converted make them python safe, this dictionary + is used to map the original systemRDL names to the names of the python attributes of this + class + + Returns: dictionary whose key is the systemRDL names and value it the property name + """ + return {'tx_sync_cnt':'tx_sync_cnt', + } + + + + + + + + + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_tx_sync_cnt_tx_sync_cnt_cls: + return super().get_child_by_system_rdl_name(name) + + + + + + + + + + @property + def rdl_name(self) -> str: + return "Transmitter Sync Duration" + @property + def rdl_desc(self) -> str: + return "Sets the duration of the synchronization tones when enabled" + + + + + + + +class msk_top_regs_tx_sync_ctrl_tx_sync_f2_cls(FieldAsyncReadWrite): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Tx F2 Sync Enable | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Enables/Disables transmission of F2 tone for receiver | + | | synchronization 0 : F2 tone transmission disabled 1 : F2 tone | + | | transmission enabled Both F1 and F2 can be enabled at the same | + | | time

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "Tx F2 Sync Enable" + @property + def rdl_desc(self) -> str: + return "Enables/Disables transmission of F2 tone for receiver synchronization\n0 : F2 tone transmission disabled\n1 : F2 tone transmission enabled\nBoth F1 and F2 can be enabled at the same time" + + + + + + + +class msk_top_regs_tx_sync_ctrl_tx_sync_f1_cls(FieldAsyncReadWrite): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Tx F1 Sync Enable | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Enables/Disables transmission of F1 tone for receiver | + | | synchronization 0 : F1 tone transmission disabled 1 : F1 tone | + | | transmission enabled Both F1 and F2 can be enabled at the same | + | | time

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "Tx F1 Sync Enable" + @property + def rdl_desc(self) -> str: + return "Enables/Disables transmission of F1 tone for receiver synchronization\n0 : F1 tone transmission disabled\n1 : F1 tone transmission enabled\nBoth F1 and F2 can be enabled at the same time" + + + + + + + +class msk_top_regs_tx_sync_ctrl_tx_sync_force_cls(FieldAsyncReadWrite): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Tx Sync Force | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

0 : Normal operation) 1 : Transmit synchronization pattern)

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "Tx Sync Force" + @property + def rdl_desc(self) -> str: + return "0 : Normal operation)\n1 : Transmit synchronization pattern)" + + + + + + + +class msk_top_regs_tx_sync_ctrl_tx_sync_ena_cls(FieldAsyncReadWrite): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Tx Sync Enable | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

0 -> Disable sync transmission 1 -> Enable sync | + | | transmission when PTT is asserted

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "Tx Sync Enable" + @property + def rdl_desc(self) -> str: + return "0 -\u003e Disable sync transmission\n1 -\u003e Enable sync transmission when PTT is asserted" + + + + + + +class msk_top_regs_tx_sync_ctrl_cls(RegAsyncReadWrite): + """ + Class to represent a register in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Transmitter Sync Control | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Provides control bits for generation of transmitter | + | | synchronization patterns

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = ['__tx_sync_ena', '__tx_sync_force', '__tx_sync_f1', '__tx_sync_f2'] + + def __init__(self, + address: int, + width: int, + accesswidth: int, + logger_handle: str, + inst_name: str, + parent: Union[AsyncAddressMap,AsyncRegFile,MemoryAsyncReadWrite]): + + super().__init__(address=address, + width=width, + accesswidth=accesswidth, + logger_handle=logger_handle, + inst_name=inst_name, + parent=parent) + + # build the field attributes + + self.__tx_sync_ena:msk_top_regs_tx_sync_ctrl_tx_sync_ena_cls = msk_top_regs_tx_sync_ctrl_tx_sync_ena_cls( + parent_register=self, + size_props=FieldSizeProps( + width=1, + lsb=0, + msb=0, + low=0, + high=0), + misc_props=FieldMiscProps( + default=0, + is_volatile=False), + logger_handle=logger_handle+'.tx_sync_ena', + inst_name='tx_sync_ena', + field_type=int) + self.__tx_sync_force:msk_top_regs_tx_sync_ctrl_tx_sync_force_cls = msk_top_regs_tx_sync_ctrl_tx_sync_force_cls( + parent_register=self, + size_props=FieldSizeProps( + width=1, + lsb=1, + msb=1, + low=1, + high=1), + misc_props=FieldMiscProps( + default=0, + is_volatile=False), + logger_handle=logger_handle+'.tx_sync_force', + inst_name='tx_sync_force', + field_type=int) + self.__tx_sync_f1:msk_top_regs_tx_sync_ctrl_tx_sync_f1_cls = msk_top_regs_tx_sync_ctrl_tx_sync_f1_cls( + parent_register=self, + size_props=FieldSizeProps( + width=1, + lsb=2, + msb=2, + low=2, + high=2), + misc_props=FieldMiscProps( + default=0, + is_volatile=False), + logger_handle=logger_handle+'.tx_sync_f1', + inst_name='tx_sync_f1', + field_type=int) + self.__tx_sync_f2:msk_top_regs_tx_sync_ctrl_tx_sync_f2_cls = msk_top_regs_tx_sync_ctrl_tx_sync_f2_cls( + parent_register=self, + size_props=FieldSizeProps( + width=1, + lsb=3, + msb=3, + low=3, + high=3), + misc_props=FieldMiscProps( + default=0, + is_volatile=False), + logger_handle=logger_handle+'.tx_sync_f2', + inst_name='tx_sync_f2', + field_type=int) + + @property + def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,FieldAsyncReadWrite]]: + """ + generator that produces has all the fields within the register + """ + yield self.tx_sync_ena + yield self.tx_sync_force + yield self.tx_sync_f1 + yield self.tx_sync_f2 + + # Empty generator in case there are no children of this type + if False: yield + + + + + # build the properties for the fields + + @property + def tx_sync_ena(self) -> msk_top_regs_tx_sync_ctrl_tx_sync_ena_cls: + """ + Property to access tx_sync_ena field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Tx Sync Enable | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

0 -> Disable sync transmission 1 -> Enable sync | + | | transmission when PTT is asserted

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__tx_sync_ena + @property + def tx_sync_force(self) -> msk_top_regs_tx_sync_ctrl_tx_sync_force_cls: + """ + Property to access tx_sync_force field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Tx Sync Force | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

0 : Normal operation) 1 : Transmit synchronization pattern)

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__tx_sync_force + @property + def tx_sync_f1(self) -> msk_top_regs_tx_sync_ctrl_tx_sync_f1_cls: + """ + Property to access tx_sync_f1 field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Tx F1 Sync Enable | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Enables/Disables transmission of F1 tone for receiver | + | | synchronization 0 : F1 tone transmission disabled 1 : F1 tone | + | | transmission enabled Both F1 and F2 can be enabled at the same | + | | time

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__tx_sync_f1 + @property + def tx_sync_f2(self) -> msk_top_regs_tx_sync_ctrl_tx_sync_f2_cls: + """ + Property to access tx_sync_f2 field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Tx F2 Sync Enable | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Enables/Disables transmission of F2 tone for receiver | + | | synchronization 0 : F2 tone transmission disabled 1 : F2 tone | + | | transmission enabled Both F1 and F2 can be enabled at the same | + | | time

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__tx_sync_f2 + + + @property + def systemrdl_python_child_name_map(self) -> dict[str, str]: + """ + In some cases systemRDL names need to be converted make them python safe, this dictionary + is used to map the original systemRDL names to the names of the python attributes of this + class + + Returns: dictionary whose key is the systemRDL names and value it the property name + """ + return {'tx_sync_ena':'tx_sync_ena','tx_sync_force':'tx_sync_force','tx_sync_f1':'tx_sync_f1','tx_sync_f2':'tx_sync_f2', + } + + + + + + + + # nodes:4 + + @overload + def get_child_by_system_rdl_name(self, name: Literal["tx_sync_ena"]) -> msk_top_regs_tx_sync_ctrl_tx_sync_ena_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["tx_sync_force"]) -> msk_top_regs_tx_sync_ctrl_tx_sync_force_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["tx_sync_f1"]) -> msk_top_regs_tx_sync_ctrl_tx_sync_f1_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["tx_sync_f2"]) -> msk_top_regs_tx_sync_ctrl_tx_sync_f2_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: str) -> Union[msk_top_regs_tx_sync_ctrl_tx_sync_ena_cls, msk_top_regs_tx_sync_ctrl_tx_sync_force_cls, msk_top_regs_tx_sync_ctrl_tx_sync_f1_cls, msk_top_regs_tx_sync_ctrl_tx_sync_f2_cls, ]: ... + + def get_child_by_system_rdl_name(self, name: Any) -> Any: + return super().get_child_by_system_rdl_name(name) + + + + + + + + + @property + def rdl_name(self) -> str: + return "Transmitter Sync Control" + @property + def rdl_desc(self) -> str: + return "Provides control bits for generation of transmitter synchronization patterns" + + + + + + + +class msk_top_regs_data32_desc_70869502_name_3de9a0d3_cls(FieldAsyncReadOnly): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | F2 Error Value | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Error value of the F2 Costas loop after each active bit | + | | period

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "F2 Error Value" + @property + def rdl_desc(self) -> str: + return "Error value of the F2 Costas loop after each active bit period" + + + + + + +class msk_top_regs_observation_data_data_272a00b6_desc_70869502_name_3de9a0d3_cls(RegAsyncReadOnly): + """ + Class to represent a register in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | F2 Error Value | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Error value of the F2 Costas loop after each active bit | + | | period

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = ['__data'] + + def __init__(self, + address: int, + width: int, + accesswidth: int, + logger_handle: str, + inst_name: str, + parent: Union[AsyncAddressMap,AsyncRegFile,ReadableAsyncMemory]): + + super().__init__(address=address, + width=width, + accesswidth=accesswidth, + logger_handle=logger_handle, + inst_name=inst_name, + parent=parent) + + # build the field attributes + + self.__data:msk_top_regs_data32_desc_70869502_name_3de9a0d3_cls = msk_top_regs_data32_desc_70869502_name_3de9a0d3_cls( + parent_register=self, + size_props=FieldSizeProps( + width=32, + lsb=0, + msb=31, + low=0, + high=31), + misc_props=FieldMiscProps( + default=0, + is_volatile=True), + logger_handle=logger_handle+'.data', + inst_name='data', + field_type=int) + + @property + def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,FieldAsyncReadWrite]]: + """ + generator that produces has all the fields within the register + """ + yield self.data + + # Empty generator in case there are no children of this type + if False: yield + + + + + # build the properties for the fields + + @property + def data(self) -> msk_top_regs_data32_desc_70869502_name_3de9a0d3_cls: + """ + Property to access data field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | F2 Error Value | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Error value of the F2 Costas loop after each active bit | + | | period

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__data + + + @property + def systemrdl_python_child_name_map(self) -> dict[str, str]: + """ + In some cases systemRDL names need to be converted make them python safe, this dictionary + is used to map the original systemRDL names to the names of the python attributes of this + class + + Returns: dictionary whose key is the systemRDL names and value it the property name + """ + return {'data':'data', + } + + + + + + + + + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_data32_desc_70869502_name_3de9a0d3_cls: + return super().get_child_by_system_rdl_name(name) + + + + + + + + + + @property + def rdl_name(self) -> str: + return "F2 Error Value" + @property + def rdl_desc(self) -> str: + return "Error value of the F2 Costas loop after each active bit period" + + + + + + + +class msk_top_regs_data32_desc_417e1c96_name_3b640507_cls(FieldAsyncReadOnly): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | F1 Error Value | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Error value of the F1 Costas loop after each active bit | + | | period

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "F1 Error Value" + @property + def rdl_desc(self) -> str: + return "Error value of the F1 Costas loop after each active bit period" + + + + + + +class msk_top_regs_observation_data_data_25a21249_desc_417e1c96_name_3b640507_cls(RegAsyncReadOnly): + """ + Class to represent a register in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | F1 Error Value | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Error value of the F1 Costas loop after each active bit | + | | period

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = ['__data'] + + def __init__(self, + address: int, + width: int, + accesswidth: int, + logger_handle: str, + inst_name: str, + parent: Union[AsyncAddressMap,AsyncRegFile,ReadableAsyncMemory]): + + super().__init__(address=address, + width=width, + accesswidth=accesswidth, + logger_handle=logger_handle, + inst_name=inst_name, + parent=parent) + + # build the field attributes + + self.__data:msk_top_regs_data32_desc_417e1c96_name_3b640507_cls = msk_top_regs_data32_desc_417e1c96_name_3b640507_cls( + parent_register=self, + size_props=FieldSizeProps( + width=32, + lsb=0, + msb=31, + low=0, + high=31), + misc_props=FieldMiscProps( + default=0, + is_volatile=True), + logger_handle=logger_handle+'.data', + inst_name='data', + field_type=int) + + @property + def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,FieldAsyncReadWrite]]: + """ + generator that produces has all the fields within the register + """ + yield self.data + + # Empty generator in case there are no children of this type + if False: yield + + + + + # build the properties for the fields + + @property + def data(self) -> msk_top_regs_data32_desc_417e1c96_name_3b640507_cls: + """ + Property to access data field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | F1 Error Value | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Error value of the F1 Costas loop after each active bit | + | | period

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__data + + + @property + def systemrdl_python_child_name_map(self) -> dict[str, str]: + """ + In some cases systemRDL names need to be converted make them python safe, this dictionary + is used to map the original systemRDL names to the names of the python attributes of this + class + + Returns: dictionary whose key is the systemRDL names and value it the property name + """ + return {'data':'data', + } + + + + + + + + + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_data32_desc_417e1c96_name_3b640507_cls: + return super().get_child_by_system_rdl_name(name) + + + + + + + + + + @property + def rdl_name(self) -> str: + return "F1 Error Value" + @property + def rdl_desc(self) -> str: + return "Error value of the F1 Costas loop after each active bit period" + + + + + + + +class msk_top_regs_data32_desc_ebde6d39_name_2c154788_cls(FieldAsyncReadOnly): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | F2 NCO Frequency Adjust | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Frequency offet applied to the F2 NCO

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "F2 NCO Frequency Adjust" + @property + def rdl_desc(self) -> str: + return "Frequency offet applied to the F2 NCO" + + + + + + +class msk_top_regs_observation_data_data_0515efaa_desc_ebde6d39_name_2c154788_cls(RegAsyncReadOnly): + """ + Class to represent a register in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | F2 NCO Frequency Adjust | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Frequency offet applied to the F2 NCO

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = ['__data'] + + def __init__(self, + address: int, + width: int, + accesswidth: int, + logger_handle: str, + inst_name: str, + parent: Union[AsyncAddressMap,AsyncRegFile,ReadableAsyncMemory]): + + super().__init__(address=address, + width=width, + accesswidth=accesswidth, + logger_handle=logger_handle, + inst_name=inst_name, + parent=parent) + + # build the field attributes + + self.__data:msk_top_regs_data32_desc_ebde6d39_name_2c154788_cls = msk_top_regs_data32_desc_ebde6d39_name_2c154788_cls( + parent_register=self, + size_props=FieldSizeProps( + width=32, + lsb=0, + msb=31, + low=0, + high=31), + misc_props=FieldMiscProps( + default=0, + is_volatile=True), + logger_handle=logger_handle+'.data', + inst_name='data', + field_type=int) + + @property + def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,FieldAsyncReadWrite]]: + """ + generator that produces has all the fields within the register + """ + yield self.data + + # Empty generator in case there are no children of this type + if False: yield + + + + + # build the properties for the fields + + @property + def data(self) -> msk_top_regs_data32_desc_ebde6d39_name_2c154788_cls: + """ + Property to access data field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | F2 NCO Frequency Adjust | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Frequency offet applied to the F2 NCO

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__data + + + @property + def systemrdl_python_child_name_map(self) -> dict[str, str]: + """ + In some cases systemRDL names need to be converted make them python safe, this dictionary + is used to map the original systemRDL names to the names of the python attributes of this + class + + Returns: dictionary whose key is the systemRDL names and value it the property name + """ + return {'data':'data', + } + + + + + + + + + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_data32_desc_ebde6d39_name_2c154788_cls: + return super().get_child_by_system_rdl_name(name) + + + + + + + + + + @property + def rdl_name(self) -> str: + return "F2 NCO Frequency Adjust" + @property + def rdl_desc(self) -> str: + return "Frequency offet applied to the F2 NCO" + + + + + + + +class msk_top_regs_data32_desc_64ff3689_name_d8ad3b25_cls(FieldAsyncReadOnly): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | F1 NCO Frequency Adjust | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Frequency offet applied to the F1 NCO

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "F1 NCO Frequency Adjust" + @property + def rdl_desc(self) -> str: + return "Frequency offet applied to the F1 NCO" + + + + + + +class msk_top_regs_observation_data_data_0c017ef4_desc_64ff3689_name_d8ad3b25_cls(RegAsyncReadOnly): + """ + Class to represent a register in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | F1 NCO Frequency Adjust | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Frequency offet applied to the F1 NCO

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = ['__data'] + + def __init__(self, + address: int, + width: int, + accesswidth: int, + logger_handle: str, + inst_name: str, + parent: Union[AsyncAddressMap,AsyncRegFile,ReadableAsyncMemory]): + + super().__init__(address=address, + width=width, + accesswidth=accesswidth, + logger_handle=logger_handle, + inst_name=inst_name, + parent=parent) + + # build the field attributes + + self.__data:msk_top_regs_data32_desc_64ff3689_name_d8ad3b25_cls = msk_top_regs_data32_desc_64ff3689_name_d8ad3b25_cls( + parent_register=self, + size_props=FieldSizeProps( + width=32, + lsb=0, + msb=31, + low=0, + high=31), + misc_props=FieldMiscProps( + default=0, + is_volatile=True), + logger_handle=logger_handle+'.data', + inst_name='data', + field_type=int) + + @property + def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,FieldAsyncReadWrite]]: + """ + generator that produces has all the fields within the register + """ + yield self.data + + # Empty generator in case there are no children of this type + if False: yield + + + + + # build the properties for the fields + + @property + def data(self) -> msk_top_regs_data32_desc_64ff3689_name_d8ad3b25_cls: + """ + Property to access data field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | F1 NCO Frequency Adjust | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Frequency offet applied to the F1 NCO

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__data + + + @property + def systemrdl_python_child_name_map(self) -> dict[str, str]: + """ + In some cases systemRDL names need to be converted make them python safe, this dictionary + is used to map the original systemRDL names to the names of the python attributes of this + class + + Returns: dictionary whose key is the systemRDL names and value it the property name + """ + return {'data':'data', + } + + + + + + + + + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_data32_desc_64ff3689_name_d8ad3b25_cls: + return super().get_child_by_system_rdl_name(name) + + + + + + + + + + @property + def rdl_name(self) -> str: + return "F1 NCO Frequency Adjust" + @property + def rdl_desc(self) -> str: + return "Frequency offet applied to the F1 NCO" + + + + + + + +class msk_top_regs_lpf_config_2_p_shift_cls(FieldAsyncReadWrite): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Proportional Gain Bit Shift | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Value n of 0-32 sets the proportional divisor as 2^-n

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "Proportional Gain Bit Shift" + @property + def rdl_desc(self) -> str: + return "Value n of 0-32 sets the proportional divisor as 2^-n" + + + + + + + +class msk_top_regs_lpf_config_2_p_gain_cls(FieldAsyncReadWrite): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Proportional Gain Value | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Value m of 0-16,777,215 sets the proportional multiplier

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "Proportional Gain Value" + @property + def rdl_desc(self) -> str: + return "Value m of 0-16,777,215 sets the proportional multiplier" + + + + + + +class msk_top_regs_lpf_config_2_cls(RegAsyncReadWrite): + """ + Class to represent a register in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | PI Controller Configuration Configuration Register 2 | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Configures PI Controller I-gain and divisor

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = ['__p_gain', '__p_shift'] + + def __init__(self, + address: int, + width: int, + accesswidth: int, + logger_handle: str, + inst_name: str, + parent: Union[AsyncAddressMap,AsyncRegFile,MemoryAsyncReadWrite]): + + super().__init__(address=address, + width=width, + accesswidth=accesswidth, + logger_handle=logger_handle, + inst_name=inst_name, + parent=parent) + + # build the field attributes + + self.__p_gain:msk_top_regs_lpf_config_2_p_gain_cls = msk_top_regs_lpf_config_2_p_gain_cls( + parent_register=self, + size_props=FieldSizeProps( + width=24, + lsb=0, + msb=23, + low=0, + high=23), + misc_props=FieldMiscProps( + default=0, + is_volatile=False), + logger_handle=logger_handle+'.p_gain', + inst_name='p_gain', + field_type=int) + self.__p_shift:msk_top_regs_lpf_config_2_p_shift_cls = msk_top_regs_lpf_config_2_p_shift_cls( + parent_register=self, + size_props=FieldSizeProps( + width=8, + lsb=24, + msb=31, + low=24, + high=31), + misc_props=FieldMiscProps( + default=0, + is_volatile=False), + logger_handle=logger_handle+'.p_shift', + inst_name='p_shift', + field_type=int) + + @property + def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,FieldAsyncReadWrite]]: + """ + generator that produces has all the fields within the register + """ + yield self.p_gain + yield self.p_shift + + # Empty generator in case there are no children of this type + if False: yield + + + + + # build the properties for the fields + + @property + def p_gain(self) -> msk_top_regs_lpf_config_2_p_gain_cls: + """ + Property to access p_gain field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Proportional Gain Value | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Value m of 0-16,777,215 sets the proportional multiplier

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__p_gain + @property + def p_shift(self) -> msk_top_regs_lpf_config_2_p_shift_cls: + """ + Property to access p_shift field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Proportional Gain Bit Shift | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Value n of 0-32 sets the proportional divisor as 2^-n

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__p_shift + + + @property + def systemrdl_python_child_name_map(self) -> dict[str, str]: + """ + In some cases systemRDL names need to be converted make them python safe, this dictionary + is used to map the original systemRDL names to the names of the python attributes of this + class + + Returns: dictionary whose key is the systemRDL names and value it the property name + """ + return {'p_gain':'p_gain','p_shift':'p_shift', + } + + + + + + + + # nodes:2 + + @overload + def get_child_by_system_rdl_name(self, name: Literal["p_gain"]) -> msk_top_regs_lpf_config_2_p_gain_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["p_shift"]) -> msk_top_regs_lpf_config_2_p_shift_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: str) -> Union[msk_top_regs_lpf_config_2_p_gain_cls, msk_top_regs_lpf_config_2_p_shift_cls, ]: ... + + def get_child_by_system_rdl_name(self, name: Any) -> Any: + return super().get_child_by_system_rdl_name(name) + + + + + + + + + @property + def rdl_name(self) -> str: + return "PI Controller Configuration Configuration Register 2" + @property + def rdl_desc(self) -> str: + return "Configures PI Controller I-gain and divisor" + + + + + + + +class msk_top_regs_rx_sample_discard_rx_nco_discard_cls(FieldAsyncReadWrite): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Rx NCO Sample Discard Value | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Number of NCO samples to discard

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "Rx NCO Sample Discard Value" + @property + def rdl_desc(self) -> str: + return "Number of NCO samples to discard" + + + + + + + +class msk_top_regs_rx_sample_discard_rx_sample_discard_cls(FieldAsyncReadWrite): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Rx Sample Discard Value | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Number of Rx samples to discard

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "Rx Sample Discard Value" + @property + def rdl_desc(self) -> str: + return "Number of Rx samples to discard" + + + + + + +class msk_top_regs_rx_sample_discard_cls(RegAsyncReadWrite): + """ + Class to represent a register in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Rx Sample Discard | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Configure samples discard operation for demodulator

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = ['__rx_sample_discard', '__rx_nco_discard'] + + def __init__(self, + address: int, + width: int, + accesswidth: int, + logger_handle: str, + inst_name: str, + parent: Union[AsyncAddressMap,AsyncRegFile,MemoryAsyncReadWrite]): + + super().__init__(address=address, + width=width, + accesswidth=accesswidth, + logger_handle=logger_handle, + inst_name=inst_name, + parent=parent) + + # build the field attributes + + self.__rx_sample_discard:msk_top_regs_rx_sample_discard_rx_sample_discard_cls = msk_top_regs_rx_sample_discard_rx_sample_discard_cls( + parent_register=self, + size_props=FieldSizeProps( + width=8, + lsb=0, + msb=7, + low=0, + high=7), + misc_props=FieldMiscProps( + default=0, + is_volatile=False), + logger_handle=logger_handle+'.rx_sample_discard', + inst_name='rx_sample_discard', + field_type=int) + self.__rx_nco_discard:msk_top_regs_rx_sample_discard_rx_nco_discard_cls = msk_top_regs_rx_sample_discard_rx_nco_discard_cls( + parent_register=self, + size_props=FieldSizeProps( + width=8, + lsb=8, + msb=15, + low=8, + high=15), + misc_props=FieldMiscProps( + default=0, + is_volatile=False), + logger_handle=logger_handle+'.rx_nco_discard', + inst_name='rx_nco_discard', + field_type=int) + + @property + def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,FieldAsyncReadWrite]]: + """ + generator that produces has all the fields within the register + """ + yield self.rx_sample_discard + yield self.rx_nco_discard + + # Empty generator in case there are no children of this type + if False: yield + + + + + # build the properties for the fields + + @property + def rx_sample_discard(self) -> msk_top_regs_rx_sample_discard_rx_sample_discard_cls: + """ + Property to access rx_sample_discard field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Rx Sample Discard Value | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Number of Rx samples to discard

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__rx_sample_discard + @property + def rx_nco_discard(self) -> msk_top_regs_rx_sample_discard_rx_nco_discard_cls: + """ + Property to access rx_nco_discard field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Rx NCO Sample Discard Value | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Number of NCO samples to discard

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__rx_nco_discard + + + @property + def systemrdl_python_child_name_map(self) -> dict[str, str]: + """ + In some cases systemRDL names need to be converted make them python safe, this dictionary + is used to map the original systemRDL names to the names of the python attributes of this + class + + Returns: dictionary whose key is the systemRDL names and value it the property name + """ + return {'rx_sample_discard':'rx_sample_discard','rx_nco_discard':'rx_nco_discard', + } + + + + + + + + # nodes:2 + + @overload + def get_child_by_system_rdl_name(self, name: Literal["rx_sample_discard"]) -> msk_top_regs_rx_sample_discard_rx_sample_discard_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["rx_nco_discard"]) -> msk_top_regs_rx_sample_discard_rx_nco_discard_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: str) -> Union[msk_top_regs_rx_sample_discard_rx_sample_discard_cls, msk_top_regs_rx_sample_discard_rx_nco_discard_cls, ]: ... + + def get_child_by_system_rdl_name(self, name: Any) -> Any: + return super().get_child_by_system_rdl_name(name) + + + + + + + + + @property + def rdl_name(self) -> str: + return "Rx Sample Discard" + @property + def rdl_desc(self) -> str: + return "Configure samples discard operation for demodulator" + + + + + + + +class msk_top_regs_msk_stat_3_xfer_count_cls(FieldAsyncReadOnly): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | S_AXIS Transfers | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Number completed S_AXIS transfers

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "S_AXIS Transfers" + @property + def rdl_desc(self) -> str: + return "Number completed S_AXIS transfers" + + + + + + +class msk_top_regs_msk_stat_3_cls(RegAsyncReadOnly): + """ + Class to represent a register in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | MSK Modem Status 3 | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Modem status data

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = ['__xfer_count'] + + def __init__(self, + address: int, + width: int, + accesswidth: int, + logger_handle: str, + inst_name: str, + parent: Union[AsyncAddressMap,AsyncRegFile,ReadableAsyncMemory]): + + super().__init__(address=address, + width=width, + accesswidth=accesswidth, + logger_handle=logger_handle, + inst_name=inst_name, + parent=parent) + + # build the field attributes + + self.__xfer_count:msk_top_regs_msk_stat_3_xfer_count_cls = msk_top_regs_msk_stat_3_xfer_count_cls( + parent_register=self, + size_props=FieldSizeProps( + width=32, + lsb=0, + msb=31, + low=0, + high=31), + misc_props=FieldMiscProps( + default=0, + is_volatile=True), + logger_handle=logger_handle+'.xfer_count', + inst_name='xfer_count', + field_type=int) + + @property + def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,FieldAsyncReadWrite]]: + """ + generator that produces has all the fields within the register + """ + yield self.xfer_count + + # Empty generator in case there are no children of this type + if False: yield + + + + + # build the properties for the fields + + @property + def xfer_count(self) -> msk_top_regs_msk_stat_3_xfer_count_cls: + """ + Property to access xfer_count field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | S_AXIS Transfers | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Number completed S_AXIS transfers

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__xfer_count + + + @property + def systemrdl_python_child_name_map(self) -> dict[str, str]: + """ + In some cases systemRDL names need to be converted make them python safe, this dictionary + is used to map the original systemRDL names to the names of the python attributes of this + class + + Returns: dictionary whose key is the systemRDL names and value it the property name + """ + return {'xfer_count':'xfer_count', + } + + + + + + + + + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_msk_stat_3_xfer_count_cls: + return super().get_child_by_system_rdl_name(name) + + + + + + + + + + @property + def rdl_name(self) -> str: + return "MSK Modem Status 3" + @property + def rdl_desc(self) -> str: + return "Modem status data" + + + + + + + +class msk_top_regs_stat_32_lpf_acc_status_data_cls(FieldAsyncReadOnly): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | PI Controller Accumulator Value | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

PI Controller Accumulator Value

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "PI Controller Accumulator Value" + @property + def rdl_desc(self) -> str: + return "PI Controller Accumulator Value" + + + + + + +class msk_top_regs_stat_32_lpf_acc_desc_dea6bd99_name_758fd0ce_cls(RegAsyncReadOnly): + """ + Class to represent a register in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | F2 PI Controller Accumulator | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Value of the F2 PI Controller Accumulator

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = ['__status_data'] + + def __init__(self, + address: int, + width: int, + accesswidth: int, + logger_handle: str, + inst_name: str, + parent: Union[AsyncAddressMap,AsyncRegFile,ReadableAsyncMemory]): + + super().__init__(address=address, + width=width, + accesswidth=accesswidth, + logger_handle=logger_handle, + inst_name=inst_name, + parent=parent) + + # build the field attributes + + self.__status_data:msk_top_regs_stat_32_lpf_acc_status_data_cls = msk_top_regs_stat_32_lpf_acc_status_data_cls( + parent_register=self, + size_props=FieldSizeProps( + width=32, + lsb=0, + msb=31, + low=0, + high=31), + misc_props=FieldMiscProps( + default=0, + is_volatile=True), + logger_handle=logger_handle+'.status_data', + inst_name='status_data', + field_type=int) + + @property + def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,FieldAsyncReadWrite]]: + """ + generator that produces has all the fields within the register + """ + yield self.status_data + + # Empty generator in case there are no children of this type + if False: yield + + + + + # build the properties for the fields + + @property + def status_data(self) -> msk_top_regs_stat_32_lpf_acc_status_data_cls: + """ + Property to access status_data field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | PI Controller Accumulator Value | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

PI Controller Accumulator Value

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__status_data + + + @property + def systemrdl_python_child_name_map(self) -> dict[str, str]: + """ + In some cases systemRDL names need to be converted make them python safe, this dictionary + is used to map the original systemRDL names to the names of the python attributes of this + class + + Returns: dictionary whose key is the systemRDL names and value it the property name + """ + return {'status_data':'status_data', + } + + + + + + + + + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_stat_32_lpf_acc_status_data_cls: + return super().get_child_by_system_rdl_name(name) + + + + + + + + + + @property + def rdl_name(self) -> str: + return "F2 PI Controller Accumulator" + @property + def rdl_desc(self) -> str: + return "Value of the F2 PI Controller Accumulator" + + + + + + + +class msk_top_regs_stat_32_lpf_acc_status_data_0x0x106b05c7_cls(FieldAsyncReadOnly): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | PI Controller Accumulator Value | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

PI Controller Accumulator Value

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "PI Controller Accumulator Value" + @property + def rdl_desc(self) -> str: + return "PI Controller Accumulator Value" + + + + + + +class msk_top_regs_stat_32_lpf_acc_desc_8cebc7dc_name_f20c6670_cls(RegAsyncReadOnly): + """ + Class to represent a register in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | F1 PI Controller Accumulator | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Value of the F1 PI Controller Accumulator

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = ['__status_data'] + + def __init__(self, + address: int, + width: int, + accesswidth: int, + logger_handle: str, + inst_name: str, + parent: Union[AsyncAddressMap,AsyncRegFile,ReadableAsyncMemory]): + + super().__init__(address=address, + width=width, + accesswidth=accesswidth, + logger_handle=logger_handle, + inst_name=inst_name, + parent=parent) + + # build the field attributes + + self.__status_data:msk_top_regs_stat_32_lpf_acc_status_data_0x0x106b05c7_cls = msk_top_regs_stat_32_lpf_acc_status_data_0x0x106b05c7_cls( + parent_register=self, + size_props=FieldSizeProps( + width=32, + lsb=0, + msb=31, + low=0, + high=31), + misc_props=FieldMiscProps( + default=0, + is_volatile=True), + logger_handle=logger_handle+'.status_data', + inst_name='status_data', + field_type=int) + + @property + def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,FieldAsyncReadWrite]]: + """ + generator that produces has all the fields within the register + """ + yield self.status_data + + # Empty generator in case there are no children of this type + if False: yield + + + + + # build the properties for the fields + + @property + def status_data(self) -> msk_top_regs_stat_32_lpf_acc_status_data_0x0x106b05c7_cls: + """ + Property to access status_data field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | PI Controller Accumulator Value | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

PI Controller Accumulator Value

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__status_data + + + @property + def systemrdl_python_child_name_map(self) -> dict[str, str]: + """ + In some cases systemRDL names need to be converted make them python safe, this dictionary + is used to map the original systemRDL names to the names of the python attributes of this + class + + Returns: dictionary whose key is the systemRDL names and value it the property name + """ + return {'status_data':'status_data', + } + + + + + + + + + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_stat_32_lpf_acc_status_data_0x0x106b05c7_cls: + return super().get_child_by_system_rdl_name(name) + + + + + + + + + + @property + def rdl_name(self) -> str: + return "F1 PI Controller Accumulator" + @property + def rdl_desc(self) -> str: + return "Value of the F1 PI Controller Accumulator" + + + + + + + +class msk_top_regs_stat_32_errs_status_data_cls(FieldAsyncReadOnly): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | PRBS Bit Errors | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Number of errored-bits received by the PRBS monitor since last | + | | sync BER can be calculated as the ratio of received bits to | + | | errored-bits

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "PRBS Bit Errors" + @property + def rdl_desc(self) -> str: + return "Number of errored-bits received by the PRBS monitor since last sync\nBER can be calculated as the ratio of received bits to errored-bits" + + + + + + +class msk_top_regs_stat_32_errs_cls(RegAsyncReadOnly): + """ + Class to represent a register in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | PRBS Status 1 | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

PRBS Bit Errors

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = ['__status_data'] + + def __init__(self, + address: int, + width: int, + accesswidth: int, + logger_handle: str, + inst_name: str, + parent: Union[AsyncAddressMap,AsyncRegFile,ReadableAsyncMemory]): + + super().__init__(address=address, + width=width, + accesswidth=accesswidth, + logger_handle=logger_handle, + inst_name=inst_name, + parent=parent) + + # build the field attributes + + self.__status_data:msk_top_regs_stat_32_errs_status_data_cls = msk_top_regs_stat_32_errs_status_data_cls( + parent_register=self, + size_props=FieldSizeProps( + width=32, + lsb=0, + msb=31, + low=0, + high=31), + misc_props=FieldMiscProps( + default=0, + is_volatile=True), + logger_handle=logger_handle+'.status_data', + inst_name='status_data', + field_type=int) + + @property + def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,FieldAsyncReadWrite]]: + """ + generator that produces has all the fields within the register + """ + yield self.status_data + + # Empty generator in case there are no children of this type + if False: yield + + + + + # build the properties for the fields + + @property + def status_data(self) -> msk_top_regs_stat_32_errs_status_data_cls: + """ + Property to access status_data field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | PRBS Bit Errors | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Number of errored-bits received by the PRBS monitor since last | + | | sync BER can be calculated as the ratio of received bits to | + | | errored-bits

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__status_data + + + @property + def systemrdl_python_child_name_map(self) -> dict[str, str]: + """ + In some cases systemRDL names need to be converted make them python safe, this dictionary + is used to map the original systemRDL names to the names of the python attributes of this + class + + Returns: dictionary whose key is the systemRDL names and value it the property name + """ + return {'status_data':'status_data', + } + + + + + + + + + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_stat_32_errs_status_data_cls: + return super().get_child_by_system_rdl_name(name) + + + + + + + + + + @property + def rdl_name(self) -> str: + return "PRBS Status 1" + @property + def rdl_desc(self) -> str: + return "PRBS Bit Errors" + + + + + + + +class msk_top_regs_stat_32_bits_status_data_cls(FieldAsyncReadOnly): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | PRBS Bits Received | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Number of bits received by the PRBS monitor since last BER can | + | | be calculated as the ratio of received bits to errored-bits

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "PRBS Bits Received" + @property + def rdl_desc(self) -> str: + return "Number of bits received by the PRBS monitor since last\nBER can be calculated as the ratio of received bits to errored-bits" + + + + + + +class msk_top_regs_stat_32_bits_cls(RegAsyncReadOnly): + """ + Class to represent a register in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | PRBS Status 0 | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

PRBS Bits Received

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = ['__status_data'] + + def __init__(self, + address: int, + width: int, + accesswidth: int, + logger_handle: str, + inst_name: str, + parent: Union[AsyncAddressMap,AsyncRegFile,ReadableAsyncMemory]): + + super().__init__(address=address, + width=width, + accesswidth=accesswidth, + logger_handle=logger_handle, + inst_name=inst_name, + parent=parent) + + # build the field attributes + + self.__status_data:msk_top_regs_stat_32_bits_status_data_cls = msk_top_regs_stat_32_bits_status_data_cls( + parent_register=self, + size_props=FieldSizeProps( + width=32, + lsb=0, + msb=31, + low=0, + high=31), + misc_props=FieldMiscProps( + default=0, + is_volatile=True), + logger_handle=logger_handle+'.status_data', + inst_name='status_data', + field_type=int) + + @property + def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,FieldAsyncReadWrite]]: + """ + generator that produces has all the fields within the register + """ + yield self.status_data + + # Empty generator in case there are no children of this type + if False: yield + + + + + # build the properties for the fields + + @property + def status_data(self) -> msk_top_regs_stat_32_bits_status_data_cls: + """ + Property to access status_data field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | PRBS Bits Received | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Number of bits received by the PRBS monitor since last BER can | + | | be calculated as the ratio of received bits to errored-bits

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__status_data + + + @property + def systemrdl_python_child_name_map(self) -> dict[str, str]: + """ + In some cases systemRDL names need to be converted make them python safe, this dictionary + is used to map the original systemRDL names to the names of the python attributes of this + class + + Returns: dictionary whose key is the systemRDL names and value it the property name + """ + return {'status_data':'status_data', + } + + + + + + + + + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_stat_32_bits_status_data_cls: + return super().get_child_by_system_rdl_name(name) + + + + + + + + + + @property + def rdl_name(self) -> str: + return "PRBS Status 0" + @property + def rdl_desc(self) -> str: + return "PRBS Bits Received" + + + + + + + +class msk_top_regs_config_prbs_errmask_config_data_cls(FieldAsyncReadWrite): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | PRBS Error Mask | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Bit positions set to '1' indicate bits that are inverted when a | + | | bit error is inserted

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "PRBS Error Mask" + @property + def rdl_desc(self) -> str: + return "Bit positions set to \u00271\u0027 indicate bits that are inverted when a bit error is inserted" + + + + + + +class msk_top_regs_config_prbs_errmask_cls(RegAsyncReadWrite): + """ + Class to represent a register in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | PRBS Control 3 | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

PRBS Error Mask

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = ['__config_data'] + + def __init__(self, + address: int, + width: int, + accesswidth: int, + logger_handle: str, + inst_name: str, + parent: Union[AsyncAddressMap,AsyncRegFile,MemoryAsyncReadWrite]): + + super().__init__(address=address, + width=width, + accesswidth=accesswidth, + logger_handle=logger_handle, + inst_name=inst_name, + parent=parent) + + # build the field attributes + + self.__config_data:msk_top_regs_config_prbs_errmask_config_data_cls = msk_top_regs_config_prbs_errmask_config_data_cls( + parent_register=self, + size_props=FieldSizeProps( + width=32, + lsb=0, + msb=31, + low=0, + high=31), + misc_props=FieldMiscProps( + default=0, + is_volatile=False), + logger_handle=logger_handle+'.config_data', + inst_name='config_data', + field_type=int) + + @property + def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,FieldAsyncReadWrite]]: + """ + generator that produces has all the fields within the register + """ + yield self.config_data + + # Empty generator in case there are no children of this type + if False: yield + + + + + # build the properties for the fields + + @property + def config_data(self) -> msk_top_regs_config_prbs_errmask_config_data_cls: + """ + Property to access config_data field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | PRBS Error Mask | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Bit positions set to '1' indicate bits that are inverted when a | + | | bit error is inserted

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__config_data + + + @property + def systemrdl_python_child_name_map(self) -> dict[str, str]: + """ + In some cases systemRDL names need to be converted make them python safe, this dictionary + is used to map the original systemRDL names to the names of the python attributes of this + class + + Returns: dictionary whose key is the systemRDL names and value it the property name + """ + return {'config_data':'config_data', + } + + + + + + + + + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_config_prbs_errmask_config_data_cls: + return super().get_child_by_system_rdl_name(name) + + + + + + + + + + @property + def rdl_name(self) -> str: + return "PRBS Control 3" + @property + def rdl_desc(self) -> str: + return "PRBS Error Mask" + + + + + + + +class msk_top_regs_config_prbs_poly_config_data_cls(FieldAsyncReadWrite): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | PRBS Polynomial | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Bit positions set to '1' indicate polynomial feedback | + | | positions

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "PRBS Polynomial" + @property + def rdl_desc(self) -> str: + return "Bit positions set to \u00271\u0027 indicate polynomial feedback positions" + + + + + + +class msk_top_regs_config_prbs_poly_cls(RegAsyncReadWrite): + """ + Class to represent a register in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | PRBS Control 2 | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

PRBS Polynomial

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = ['__config_data'] + + def __init__(self, + address: int, + width: int, + accesswidth: int, + logger_handle: str, + inst_name: str, + parent: Union[AsyncAddressMap,AsyncRegFile,MemoryAsyncReadWrite]): + + super().__init__(address=address, + width=width, + accesswidth=accesswidth, + logger_handle=logger_handle, + inst_name=inst_name, + parent=parent) + + # build the field attributes + + self.__config_data:msk_top_regs_config_prbs_poly_config_data_cls = msk_top_regs_config_prbs_poly_config_data_cls( + parent_register=self, + size_props=FieldSizeProps( + width=32, + lsb=0, + msb=31, + low=0, + high=31), + misc_props=FieldMiscProps( + default=0, + is_volatile=False), + logger_handle=logger_handle+'.config_data', + inst_name='config_data', + field_type=int) + + @property + def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,FieldAsyncReadWrite]]: + """ + generator that produces has all the fields within the register + """ + yield self.config_data + + # Empty generator in case there are no children of this type + if False: yield + + + + + # build the properties for the fields + + @property + def config_data(self) -> msk_top_regs_config_prbs_poly_config_data_cls: + """ + Property to access config_data field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | PRBS Polynomial | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Bit positions set to '1' indicate polynomial feedback | + | | positions

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__config_data + + + @property + def systemrdl_python_child_name_map(self) -> dict[str, str]: + """ + In some cases systemRDL names need to be converted make them python safe, this dictionary + is used to map the original systemRDL names to the names of the python attributes of this + class + + Returns: dictionary whose key is the systemRDL names and value it the property name + """ + return {'config_data':'config_data', + } + + + + + + + + + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_config_prbs_poly_config_data_cls: + return super().get_child_by_system_rdl_name(name) + + + + + + + + + + @property + def rdl_name(self) -> str: + return "PRBS Control 2" + @property + def rdl_desc(self) -> str: + return "PRBS Polynomial" + + + + + + + +class msk_top_regs_config_prbs_seed_config_data_cls(FieldAsyncReadWrite): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | PRBS Seed | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Sets the starting value of the PRBS generator

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "PRBS Seed" + @property + def rdl_desc(self) -> str: + return "Sets the starting value of the PRBS generator" + + + + + + +class msk_top_regs_config_prbs_seed_cls(RegAsyncReadWrite): + """ + Class to represent a register in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | PRBS Control 1 | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

PRBS Initial State

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = ['__config_data'] + + def __init__(self, + address: int, + width: int, + accesswidth: int, + logger_handle: str, + inst_name: str, + parent: Union[AsyncAddressMap,AsyncRegFile,MemoryAsyncReadWrite]): + + super().__init__(address=address, + width=width, + accesswidth=accesswidth, + logger_handle=logger_handle, + inst_name=inst_name, + parent=parent) + + # build the field attributes + + self.__config_data:msk_top_regs_config_prbs_seed_config_data_cls = msk_top_regs_config_prbs_seed_config_data_cls( + parent_register=self, + size_props=FieldSizeProps( + width=32, + lsb=0, + msb=31, + low=0, + high=31), + misc_props=FieldMiscProps( + default=0, + is_volatile=False), + logger_handle=logger_handle+'.config_data', + inst_name='config_data', + field_type=int) + + @property + def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,FieldAsyncReadWrite]]: + """ + generator that produces has all the fields within the register + """ + yield self.config_data + + # Empty generator in case there are no children of this type + if False: yield + + + + + # build the properties for the fields + + @property + def config_data(self) -> msk_top_regs_config_prbs_seed_config_data_cls: + """ + Property to access config_data field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | PRBS Seed | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Sets the starting value of the PRBS generator

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__config_data + + + @property + def systemrdl_python_child_name_map(self) -> dict[str, str]: + """ + In some cases systemRDL names need to be converted make them python safe, this dictionary + is used to map the original systemRDL names to the names of the python attributes of this + class + + Returns: dictionary whose key is the systemRDL names and value it the property name + """ + return {'config_data':'config_data', + } + + + + + + + + + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_config_prbs_seed_config_data_cls: + return super().get_child_by_system_rdl_name(name) + + + + + + + + + + @property + def rdl_name(self) -> str: + return "PRBS Control 1" + @property + def rdl_desc(self) -> str: + return "PRBS Initial State" + + + + + + + +class msk_top_regs_prbs_ctrl_prbs_sync_threshold_cls(FieldAsyncReadWrite): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | PRBS Auto Sync Threshold | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

0 : Auto Sync Disabled N > 0 : Auto sync after N errors

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "PRBS Auto Sync Threshold" + @property + def rdl_desc(self) -> str: + return "0 : Auto Sync Disabled\nN \u003e 0 : Auto sync after N errors" + + + + + + + +class msk_top_regs_prbs_ctrl_prbs_reserved_cls(FieldAsyncReadWrite): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Reserved | + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "Reserved" + + + + + + + +class msk_top_regs_prbs_ctrl_prbs_manual_sync_cls(FieldAsyncWriteOnly): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | PRBS Manual Sync | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

0 -> 1 : Synchronize PRBS monitor 1 -> 0 : Synchronize | + | | PRBS monitor

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "PRBS Manual Sync" + @property + def rdl_desc(self) -> str: + return "0 -\u003e 1 : Synchronize PRBS monitor\n1 -\u003e 0 : Synchronize PRBS monitor" + + + + + + + +class msk_top_regs_prbs_ctrl_prbs_clear_cls(FieldAsyncWriteOnly): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | PRBS Clear Counters | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

0 -> 1 : Clear PRBS Counters 1 -> 0 : Clear PRBS | + | | Counters

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "PRBS Clear Counters" + @property + def rdl_desc(self) -> str: + return "0 -\u003e 1 : Clear PRBS Counters\n1 -\u003e 0 : Clear PRBS Counters" + + + + + + + +class msk_top_regs_prbs_ctrl_prbs_error_insert_cls(FieldAsyncWriteOnly): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | PRBS Error Insert | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

0 -> 1 : Insert bit error in Tx data (both Normal and PRBS) | + | | 1 -> 0 : Insert bit error in Tx data (both Normal and PRBS)

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "PRBS Error Insert" + @property + def rdl_desc(self) -> str: + return "0 -\u003e 1 : Insert bit error in Tx data (both Normal and PRBS)\n1 -\u003e 0 : Insert bit error in Tx data (both Normal and PRBS)" + + + + + + + +class msk_top_regs_prbs_ctrl_prbs_sel_cls(FieldAsyncReadWrite): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | PRBS Data Select | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

0 -> Select Normal Tx Data 1 -> Select PRBS Tx Data

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "PRBS Data Select" + @property + def rdl_desc(self) -> str: + return "0 -\u003e Select Normal Tx Data\n1 -\u003e Select PRBS Tx Data" + + + + + + +class msk_top_regs_prbs_ctrl_cls(RegAsyncReadWrite): + """ + Class to represent a register in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | PRBS Control 0 | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Configures operation of the PRBS Generator and Monitor

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = ['__prbs_sel', '__prbs_error_insert', '__prbs_clear', '__prbs_manual_sync', '__prbs_reserved', '__prbs_sync_threshold'] + + def __init__(self, + address: int, + width: int, + accesswidth: int, + logger_handle: str, + inst_name: str, + parent: Union[AsyncAddressMap,AsyncRegFile,MemoryAsyncReadWrite]): + + super().__init__(address=address, + width=width, + accesswidth=accesswidth, + logger_handle=logger_handle, + inst_name=inst_name, + parent=parent) + + # build the field attributes + + self.__prbs_sel:msk_top_regs_prbs_ctrl_prbs_sel_cls = msk_top_regs_prbs_ctrl_prbs_sel_cls( + parent_register=self, + size_props=FieldSizeProps( + width=1, + lsb=0, + msb=0, + low=0, + high=0), + misc_props=FieldMiscProps( + default=0, + is_volatile=False), + logger_handle=logger_handle+'.prbs_sel', + inst_name='prbs_sel', + field_type=int) + self.__prbs_error_insert:msk_top_regs_prbs_ctrl_prbs_error_insert_cls = msk_top_regs_prbs_ctrl_prbs_error_insert_cls( + parent_register=self, + size_props=FieldSizeProps( + width=1, + lsb=1, + msb=1, + low=1, + high=1), + misc_props=FieldMiscProps( + default=0, + is_volatile=False), + logger_handle=logger_handle+'.prbs_error_insert', + inst_name='prbs_error_insert', + field_type=int) + self.__prbs_clear:msk_top_regs_prbs_ctrl_prbs_clear_cls = msk_top_regs_prbs_ctrl_prbs_clear_cls( + parent_register=self, + size_props=FieldSizeProps( + width=1, + lsb=2, + msb=2, + low=2, + high=2), + misc_props=FieldMiscProps( + default=0, + is_volatile=False), + logger_handle=logger_handle+'.prbs_clear', + inst_name='prbs_clear', + field_type=int) + self.__prbs_manual_sync:msk_top_regs_prbs_ctrl_prbs_manual_sync_cls = msk_top_regs_prbs_ctrl_prbs_manual_sync_cls( + parent_register=self, + size_props=FieldSizeProps( + width=1, + lsb=3, + msb=3, + low=3, + high=3), + misc_props=FieldMiscProps( + default=0, + is_volatile=False), + logger_handle=logger_handle+'.prbs_manual_sync', + inst_name='prbs_manual_sync', + field_type=int) + self.__prbs_reserved:msk_top_regs_prbs_ctrl_prbs_reserved_cls = msk_top_regs_prbs_ctrl_prbs_reserved_cls( + parent_register=self, + size_props=FieldSizeProps( + width=12, + lsb=4, + msb=15, + low=4, + high=15), + misc_props=FieldMiscProps( + default=0, + is_volatile=False), + logger_handle=logger_handle+'.prbs_reserved', + inst_name='prbs_reserved', + field_type=int) + self.__prbs_sync_threshold:msk_top_regs_prbs_ctrl_prbs_sync_threshold_cls = msk_top_regs_prbs_ctrl_prbs_sync_threshold_cls( + parent_register=self, + size_props=FieldSizeProps( + width=16, + lsb=16, + msb=31, + low=16, + high=31), + misc_props=FieldMiscProps( + default=0, + is_volatile=False), + logger_handle=logger_handle+'.prbs_sync_threshold', + inst_name='prbs_sync_threshold', + field_type=int) + + @property + def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,FieldAsyncReadWrite]]: + """ + generator that produces has all the fields within the register + """ + yield self.prbs_sel + yield self.prbs_error_insert + yield self.prbs_clear + yield self.prbs_manual_sync + yield self.prbs_reserved + yield self.prbs_sync_threshold + + # Empty generator in case there are no children of this type + if False: yield + + + + + # build the properties for the fields + + @property + def prbs_sel(self) -> msk_top_regs_prbs_ctrl_prbs_sel_cls: + """ + Property to access prbs_sel field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | PRBS Data Select | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

0 -> Select Normal Tx Data 1 -> Select PRBS Tx Data

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__prbs_sel + @property + def prbs_error_insert(self) -> msk_top_regs_prbs_ctrl_prbs_error_insert_cls: + """ + Property to access prbs_error_insert field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | PRBS Error Insert | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

0 -> 1 : Insert bit error in Tx data (both Normal and PRBS) | + | | 1 -> 0 : Insert bit error in Tx data (both Normal and PRBS)

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__prbs_error_insert + @property + def prbs_clear(self) -> msk_top_regs_prbs_ctrl_prbs_clear_cls: + """ + Property to access prbs_clear field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | PRBS Clear Counters | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

0 -> 1 : Clear PRBS Counters 1 -> 0 : Clear PRBS | + | | Counters

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__prbs_clear + @property + def prbs_manual_sync(self) -> msk_top_regs_prbs_ctrl_prbs_manual_sync_cls: + """ + Property to access prbs_manual_sync field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | PRBS Manual Sync | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

0 -> 1 : Synchronize PRBS monitor 1 -> 0 : Synchronize | + | | PRBS monitor

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__prbs_manual_sync + @property + def prbs_reserved(self) -> msk_top_regs_prbs_ctrl_prbs_reserved_cls: + """ + Property to access prbs_reserved field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Reserved | + +--------------+-------------------------------------------------------------------------+ + """ + return self.__prbs_reserved + @property + def prbs_sync_threshold(self) -> msk_top_regs_prbs_ctrl_prbs_sync_threshold_cls: + """ + Property to access prbs_sync_threshold field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | PRBS Auto Sync Threshold | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

0 : Auto Sync Disabled N > 0 : Auto sync after N errors

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__prbs_sync_threshold + + + @property + def systemrdl_python_child_name_map(self) -> dict[str, str]: + """ + In some cases systemRDL names need to be converted make them python safe, this dictionary + is used to map the original systemRDL names to the names of the python attributes of this + class + + Returns: dictionary whose key is the systemRDL names and value it the property name + """ + return {'prbs_sel':'prbs_sel','prbs_error_insert':'prbs_error_insert','prbs_clear':'prbs_clear','prbs_manual_sync':'prbs_manual_sync','prbs_reserved':'prbs_reserved','prbs_sync_threshold':'prbs_sync_threshold', + } + + + + + + + + # nodes:6 + + @overload + def get_child_by_system_rdl_name(self, name: Literal["prbs_sel"]) -> msk_top_regs_prbs_ctrl_prbs_sel_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["prbs_error_insert"]) -> msk_top_regs_prbs_ctrl_prbs_error_insert_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["prbs_clear"]) -> msk_top_regs_prbs_ctrl_prbs_clear_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["prbs_manual_sync"]) -> msk_top_regs_prbs_ctrl_prbs_manual_sync_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["prbs_reserved"]) -> msk_top_regs_prbs_ctrl_prbs_reserved_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["prbs_sync_threshold"]) -> msk_top_regs_prbs_ctrl_prbs_sync_threshold_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: str) -> Union[msk_top_regs_prbs_ctrl_prbs_sel_cls, msk_top_regs_prbs_ctrl_prbs_error_insert_cls, msk_top_regs_prbs_ctrl_prbs_clear_cls, msk_top_regs_prbs_ctrl_prbs_manual_sync_cls, msk_top_regs_prbs_ctrl_prbs_reserved_cls, msk_top_regs_prbs_ctrl_prbs_sync_threshold_cls, ]: ... + + def get_child_by_system_rdl_name(self, name: Any) -> Any: + return super().get_child_by_system_rdl_name(name) + + + + + + + + + @property + def rdl_name(self) -> str: + return "PRBS Control 0" + @property + def rdl_desc(self) -> str: + return "Configures operation of the PRBS Generator and Monitor" + + + + + + + +class msk_top_regs_data_width_data_width_cls(FieldAsyncReadWrite): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Modem input/output data width | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Set the data width of the modem input/output

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "Modem input/output data width" + @property + def rdl_desc(self) -> str: + return "Set the data width of the modem input/output" + + + + + + +class msk_top_regs_data_width_desc_6097df38_name_4609588b_cls(RegAsyncReadWrite): + """ + Class to represent a register in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Modem Rx Output Data Width | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Set the parallel data width of the serial-to-parallel | + | | converter

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = ['__data_width'] + + def __init__(self, + address: int, + width: int, + accesswidth: int, + logger_handle: str, + inst_name: str, + parent: Union[AsyncAddressMap,AsyncRegFile,MemoryAsyncReadWrite]): + + super().__init__(address=address, + width=width, + accesswidth=accesswidth, + logger_handle=logger_handle, + inst_name=inst_name, + parent=parent) + + # build the field attributes + + self.__data_width:msk_top_regs_data_width_data_width_cls = msk_top_regs_data_width_data_width_cls( + parent_register=self, + size_props=FieldSizeProps( + width=8, + lsb=0, + msb=7, + low=0, + high=7), + misc_props=FieldMiscProps( + default=8, + is_volatile=False), + logger_handle=logger_handle+'.data_width', + inst_name='data_width', + field_type=int) + + @property + def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,FieldAsyncReadWrite]]: + """ + generator that produces has all the fields within the register + """ + yield self.data_width + + # Empty generator in case there are no children of this type + if False: yield + + + + + # build the properties for the fields + + @property + def data_width(self) -> msk_top_regs_data_width_data_width_cls: + """ + Property to access data_width field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Modem input/output data width | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Set the data width of the modem input/output

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__data_width + + + @property + def systemrdl_python_child_name_map(self) -> dict[str, str]: + """ + In some cases systemRDL names need to be converted make them python safe, this dictionary + is used to map the original systemRDL names to the names of the python attributes of this + class + + Returns: dictionary whose key is the systemRDL names and value it the property name + """ + return {'data_width':'data_width', + } + + + + + + + + + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_data_width_data_width_cls: + return super().get_child_by_system_rdl_name(name) + + + + + + + + + + @property + def rdl_name(self) -> str: + return "Modem Rx Output Data Width" + @property + def rdl_desc(self) -> str: + return "Set the parallel data width of the serial-to-parallel converter" + + + + + + + +class msk_top_regs_data_width_data_width_0x0x106a65e2_cls(FieldAsyncReadWrite): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Modem input/output data width | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Set the data width of the modem input/output

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "Modem input/output data width" + @property + def rdl_desc(self) -> str: + return "Set the data width of the modem input/output" + + + + + + +class msk_top_regs_data_width_desc_58c848dd_name_2fbd8eba_cls(RegAsyncReadWrite): + """ + Class to represent a register in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Modem Tx Input Data Width | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Set the parallel data width of the parallel-to-serial | + | | converter

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = ['__data_width'] + + def __init__(self, + address: int, + width: int, + accesswidth: int, + logger_handle: str, + inst_name: str, + parent: Union[AsyncAddressMap,AsyncRegFile,MemoryAsyncReadWrite]): + + super().__init__(address=address, + width=width, + accesswidth=accesswidth, + logger_handle=logger_handle, + inst_name=inst_name, + parent=parent) + + # build the field attributes + + self.__data_width:msk_top_regs_data_width_data_width_0x0x106a65e2_cls = msk_top_regs_data_width_data_width_0x0x106a65e2_cls( + parent_register=self, + size_props=FieldSizeProps( + width=8, + lsb=0, + msb=7, + low=0, + high=7), + misc_props=FieldMiscProps( + default=8, + is_volatile=False), + logger_handle=logger_handle+'.data_width', + inst_name='data_width', + field_type=int) + + @property + def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,FieldAsyncReadWrite]]: + """ + generator that produces has all the fields within the register + """ + yield self.data_width + + # Empty generator in case there are no children of this type + if False: yield + + + + + # build the properties for the fields + + @property + def data_width(self) -> msk_top_regs_data_width_data_width_0x0x106a65e2_cls: + """ + Property to access data_width field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Modem input/output data width | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Set the data width of the modem input/output

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__data_width + + + @property + def systemrdl_python_child_name_map(self) -> dict[str, str]: + """ + In some cases systemRDL names need to be converted make them python safe, this dictionary + is used to map the original systemRDL names to the names of the python attributes of this + class + + Returns: dictionary whose key is the systemRDL names and value it the property name + """ + return {'data_width':'data_width', + } + + + + + + + + + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_data_width_data_width_0x0x106a65e2_cls: + return super().get_child_by_system_rdl_name(name) + + + + + + + + + + @property + def rdl_name(self) -> str: + return "Modem Tx Input Data Width" + @property + def rdl_desc(self) -> str: + return "Set the parallel data width of the parallel-to-serial converter" + + + + + + + +class msk_top_regs_lpf_config_1_i_shift_cls(FieldAsyncReadWrite): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Integral Gain Bit Shift | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Value n of 0-32 sets the integral divisor as 2^-n

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "Integral Gain Bit Shift" + @property + def rdl_desc(self) -> str: + return "Value n of 0-32 sets the integral divisor as 2^-n" + + + + + + + +class msk_top_regs_lpf_config_1_i_gain_cls(FieldAsyncReadWrite): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Integral Gain Value | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Value m of 0-16,777,215 sets the integral multiplier

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "Integral Gain Value" + @property + def rdl_desc(self) -> str: + return "Value m of 0-16,777,215 sets the integral multiplier" + + + + + + +class msk_top_regs_lpf_config_1_cls(RegAsyncReadWrite): + """ + Class to represent a register in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | PI Controller Configuration Configuration Register 1 | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Configures PI Controller I-gain and divisor

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = ['__i_gain', '__i_shift'] + + def __init__(self, + address: int, + width: int, + accesswidth: int, + logger_handle: str, + inst_name: str, + parent: Union[AsyncAddressMap,AsyncRegFile,MemoryAsyncReadWrite]): + + super().__init__(address=address, + width=width, + accesswidth=accesswidth, + logger_handle=logger_handle, + inst_name=inst_name, + parent=parent) + + # build the field attributes + + self.__i_gain:msk_top_regs_lpf_config_1_i_gain_cls = msk_top_regs_lpf_config_1_i_gain_cls( + parent_register=self, + size_props=FieldSizeProps( + width=24, + lsb=0, + msb=23, + low=0, + high=23), + misc_props=FieldMiscProps( + default=0, + is_volatile=False), + logger_handle=logger_handle+'.i_gain', + inst_name='i_gain', + field_type=int) + self.__i_shift:msk_top_regs_lpf_config_1_i_shift_cls = msk_top_regs_lpf_config_1_i_shift_cls( + parent_register=self, + size_props=FieldSizeProps( + width=8, + lsb=24, + msb=31, + low=24, + high=31), + misc_props=FieldMiscProps( + default=0, + is_volatile=False), + logger_handle=logger_handle+'.i_shift', + inst_name='i_shift', + field_type=int) + + @property + def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,FieldAsyncReadWrite]]: + """ + generator that produces has all the fields within the register + """ + yield self.i_gain + yield self.i_shift + + # Empty generator in case there are no children of this type + if False: yield + + + + + # build the properties for the fields + + @property + def i_gain(self) -> msk_top_regs_lpf_config_1_i_gain_cls: + """ + Property to access i_gain field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Integral Gain Value | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Value m of 0-16,777,215 sets the integral multiplier

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__i_gain + @property + def i_shift(self) -> msk_top_regs_lpf_config_1_i_shift_cls: + """ + Property to access i_shift field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Integral Gain Bit Shift | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Value n of 0-32 sets the integral divisor as 2^-n

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__i_shift + + + @property + def systemrdl_python_child_name_map(self) -> dict[str, str]: + """ + In some cases systemRDL names need to be converted make them python safe, this dictionary + is used to map the original systemRDL names to the names of the python attributes of this + class + + Returns: dictionary whose key is the systemRDL names and value it the property name + """ + return {'i_gain':'i_gain','i_shift':'i_shift', + } + + + + + + + + # nodes:2 + + @overload + def get_child_by_system_rdl_name(self, name: Literal["i_gain"]) -> msk_top_regs_lpf_config_1_i_gain_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["i_shift"]) -> msk_top_regs_lpf_config_1_i_shift_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: str) -> Union[msk_top_regs_lpf_config_1_i_gain_cls, msk_top_regs_lpf_config_1_i_shift_cls, ]: ... + + def get_child_by_system_rdl_name(self, name: Any) -> Any: + return super().get_child_by_system_rdl_name(name) + + + + + + + + + @property + def rdl_name(self) -> str: + return "PI Controller Configuration Configuration Register 1" + @property + def rdl_desc(self) -> str: + return "Configures PI Controller I-gain and divisor" + + + + + + + +class msk_top_regs_lpf_config_0_lpf_alpha_cls(FieldAsyncReadWrite): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Lowpass IIR filter alpha | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Value controls the filter rolloff

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "Lowpass IIR filter alpha" + @property + def rdl_desc(self) -> str: + return "Value controls the filter rolloff" + + + + + + + +class msk_top_regs_lpf_config_0_prbs_reserved_cls(FieldAsyncReadWrite): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Reserved | + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "Reserved" + + + + + + + +class msk_top_regs_lpf_config_0_lpf_zero_cls(FieldAsyncReadWrite): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Hold the PI Accumulator at zero | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

0 -> Normal operation 1 -> Zero and hold accumulator

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "Hold the PI Accumulator at zero" + @property + def rdl_desc(self) -> str: + return "0 -\u003e Normal operation\n1 -\u003e Zero and hold accumulator" + + + + + + + +class msk_top_regs_lpf_config_0_lpf_freeze_cls(FieldAsyncReadWrite): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Freeze the accumulator's current value | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

0 -> Normal operation 1 -> Freeze current value

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "Freeze the accumulator\u0027s current value" + @property + def rdl_desc(self) -> str: + return "0 -\u003e Normal operation\n1 -\u003e Freeze current value" + + + + + + +class msk_top_regs_lpf_config_0_cls(RegAsyncReadWrite): + """ + Class to represent a register in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | PI Controller Configuration and Low-pass Filter Configuration | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Configure PI controller and low-pass filter

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = ['__lpf_freeze', '__lpf_zero', '__prbs_reserved', '__lpf_alpha'] + + def __init__(self, + address: int, + width: int, + accesswidth: int, + logger_handle: str, + inst_name: str, + parent: Union[AsyncAddressMap,AsyncRegFile,MemoryAsyncReadWrite]): + + super().__init__(address=address, + width=width, + accesswidth=accesswidth, + logger_handle=logger_handle, + inst_name=inst_name, + parent=parent) + + # build the field attributes + + self.__lpf_freeze:msk_top_regs_lpf_config_0_lpf_freeze_cls = msk_top_regs_lpf_config_0_lpf_freeze_cls( + parent_register=self, + size_props=FieldSizeProps( + width=1, + lsb=0, + msb=0, + low=0, + high=0), + misc_props=FieldMiscProps( + default=0, + is_volatile=False), + logger_handle=logger_handle+'.lpf_freeze', + inst_name='lpf_freeze', + field_type=int) + self.__lpf_zero:msk_top_regs_lpf_config_0_lpf_zero_cls = msk_top_regs_lpf_config_0_lpf_zero_cls( + parent_register=self, + size_props=FieldSizeProps( + width=1, + lsb=1, + msb=1, + low=1, + high=1), + misc_props=FieldMiscProps( + default=0, + is_volatile=False), + logger_handle=logger_handle+'.lpf_zero', + inst_name='lpf_zero', + field_type=int) + self.__prbs_reserved:msk_top_regs_lpf_config_0_prbs_reserved_cls = msk_top_regs_lpf_config_0_prbs_reserved_cls( + parent_register=self, + size_props=FieldSizeProps( + width=6, + lsb=2, + msb=7, + low=2, + high=7), + misc_props=FieldMiscProps( + default=0, + is_volatile=False), + logger_handle=logger_handle+'.prbs_reserved', + inst_name='prbs_reserved', + field_type=int) + self.__lpf_alpha:msk_top_regs_lpf_config_0_lpf_alpha_cls = msk_top_regs_lpf_config_0_lpf_alpha_cls( + parent_register=self, + size_props=FieldSizeProps( + width=24, + lsb=8, + msb=31, + low=8, + high=31), + misc_props=FieldMiscProps( + default=0, + is_volatile=False), + logger_handle=logger_handle+'.lpf_alpha', + inst_name='lpf_alpha', + field_type=int) + + @property + def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,FieldAsyncReadWrite]]: + """ + generator that produces has all the fields within the register + """ + yield self.lpf_freeze + yield self.lpf_zero + yield self.prbs_reserved + yield self.lpf_alpha + + # Empty generator in case there are no children of this type + if False: yield + + + + + # build the properties for the fields + + @property + def lpf_freeze(self) -> msk_top_regs_lpf_config_0_lpf_freeze_cls: + """ + Property to access lpf_freeze field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Freeze the accumulator's current value | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

0 -> Normal operation 1 -> Freeze current value

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__lpf_freeze + @property + def lpf_zero(self) -> msk_top_regs_lpf_config_0_lpf_zero_cls: + """ + Property to access lpf_zero field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Hold the PI Accumulator at zero | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

0 -> Normal operation 1 -> Zero and hold accumulator

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__lpf_zero + @property + def prbs_reserved(self) -> msk_top_regs_lpf_config_0_prbs_reserved_cls: + """ + Property to access prbs_reserved field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Reserved | + +--------------+-------------------------------------------------------------------------+ + """ + return self.__prbs_reserved + @property + def lpf_alpha(self) -> msk_top_regs_lpf_config_0_lpf_alpha_cls: + """ + Property to access lpf_alpha field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Lowpass IIR filter alpha | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Value controls the filter rolloff

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__lpf_alpha + + + @property + def systemrdl_python_child_name_map(self) -> dict[str, str]: + """ + In some cases systemRDL names need to be converted make them python safe, this dictionary + is used to map the original systemRDL names to the names of the python attributes of this + class + + Returns: dictionary whose key is the systemRDL names and value it the property name + """ + return {'lpf_freeze':'lpf_freeze','lpf_zero':'lpf_zero','prbs_reserved':'prbs_reserved','lpf_alpha':'lpf_alpha', + } + + + + + + + + # nodes:4 + + @overload + def get_child_by_system_rdl_name(self, name: Literal["lpf_freeze"]) -> msk_top_regs_lpf_config_0_lpf_freeze_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["lpf_zero"]) -> msk_top_regs_lpf_config_0_lpf_zero_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["prbs_reserved"]) -> msk_top_regs_lpf_config_0_prbs_reserved_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["lpf_alpha"]) -> msk_top_regs_lpf_config_0_lpf_alpha_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: str) -> Union[msk_top_regs_lpf_config_0_lpf_freeze_cls, msk_top_regs_lpf_config_0_lpf_zero_cls, msk_top_regs_lpf_config_0_prbs_reserved_cls, msk_top_regs_lpf_config_0_lpf_alpha_cls, ]: ... + + def get_child_by_system_rdl_name(self, name: Any) -> Any: + return super().get_child_by_system_rdl_name(name) + + + + + + + + + @property + def rdl_name(self) -> str: + return "PI Controller Configuration and Low-pass Filter Configuration" + @property + def rdl_desc(self) -> str: + return "Configure PI controller and low-pass filter" + + + + + + + +class msk_top_regs_config_nco_fw_config_data_cls(FieldAsyncReadWrite): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Frequency Control Word | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Sets the center frequency of the NCO as FW = Fn * 2^32/Fs, | + | | where Fn is the desired NCO frequency, and Fs is the NCO sample | + | | rate

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "Frequency Control Word" + @property + def rdl_desc(self) -> str: + return "Sets the center frequency of the NCO as FW = Fn * 2^32/Fs, \nwhere Fn is the desired NCO frequency, and Fs is the NCO sample rate" + + + + + + +class msk_top_regs_config_nco_fw_desc_43c0828f_name_bdc60ecf_cls(RegAsyncReadWrite): + """ + Class to represent a register in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Rx F2 NCO Frequency Control Word | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Set Demodulator F2 Frequency

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = ['__config_data'] + + def __init__(self, + address: int, + width: int, + accesswidth: int, + logger_handle: str, + inst_name: str, + parent: Union[AsyncAddressMap,AsyncRegFile,MemoryAsyncReadWrite]): + + super().__init__(address=address, + width=width, + accesswidth=accesswidth, + logger_handle=logger_handle, + inst_name=inst_name, + parent=parent) + + # build the field attributes + + self.__config_data:msk_top_regs_config_nco_fw_config_data_cls = msk_top_regs_config_nco_fw_config_data_cls( + parent_register=self, + size_props=FieldSizeProps( + width=32, + lsb=0, + msb=31, + low=0, + high=31), + misc_props=FieldMiscProps( + default=0, + is_volatile=False), + logger_handle=logger_handle+'.config_data', + inst_name='config_data', + field_type=int) + + @property + def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,FieldAsyncReadWrite]]: + """ + generator that produces has all the fields within the register + """ + yield self.config_data + + # Empty generator in case there are no children of this type + if False: yield + + + + + # build the properties for the fields + + @property + def config_data(self) -> msk_top_regs_config_nco_fw_config_data_cls: + """ + Property to access config_data field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Frequency Control Word | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Sets the center frequency of the NCO as FW = Fn * 2^32/Fs, | + | | where Fn is the desired NCO frequency, and Fs is the NCO sample | + | | rate

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__config_data + + + @property + def systemrdl_python_child_name_map(self) -> dict[str, str]: + """ + In some cases systemRDL names need to be converted make them python safe, this dictionary + is used to map the original systemRDL names to the names of the python attributes of this + class + + Returns: dictionary whose key is the systemRDL names and value it the property name + """ + return {'config_data':'config_data', + } + + + + + + + + + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_config_nco_fw_config_data_cls: + return super().get_child_by_system_rdl_name(name) + + + + + + + + + + @property + def rdl_name(self) -> str: + return "Rx F2 NCO Frequency Control Word" + @property + def rdl_desc(self) -> str: + return "Set Demodulator F2 Frequency" + + + + + + + +class msk_top_regs_config_nco_fw_config_data_0x0x106a67e3_cls(FieldAsyncReadWrite): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Frequency Control Word | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Sets the center frequency of the NCO as FW = Fn * 2^32/Fs, | + | | where Fn is the desired NCO frequency, and Fs is the NCO sample | + | | rate

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "Frequency Control Word" + @property + def rdl_desc(self) -> str: + return "Sets the center frequency of the NCO as FW = Fn * 2^32/Fs, \nwhere Fn is the desired NCO frequency, and Fs is the NCO sample rate" + + + + + + +class msk_top_regs_config_nco_fw_desc_16fb48c8_name_8d01a20d_cls(RegAsyncReadWrite): + """ + Class to represent a register in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Rx F1 NCO Frequency Control Word | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Set Demodulator F1 Frequency

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = ['__config_data'] + + def __init__(self, + address: int, + width: int, + accesswidth: int, + logger_handle: str, + inst_name: str, + parent: Union[AsyncAddressMap,AsyncRegFile,MemoryAsyncReadWrite]): + + super().__init__(address=address, + width=width, + accesswidth=accesswidth, + logger_handle=logger_handle, + inst_name=inst_name, + parent=parent) + + # build the field attributes + + self.__config_data:msk_top_regs_config_nco_fw_config_data_0x0x106a67e3_cls = msk_top_regs_config_nco_fw_config_data_0x0x106a67e3_cls( + parent_register=self, + size_props=FieldSizeProps( + width=32, + lsb=0, + msb=31, + low=0, + high=31), + misc_props=FieldMiscProps( + default=0, + is_volatile=False), + logger_handle=logger_handle+'.config_data', + inst_name='config_data', + field_type=int) + + @property + def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,FieldAsyncReadWrite]]: + """ + generator that produces has all the fields within the register + """ + yield self.config_data + + # Empty generator in case there are no children of this type + if False: yield + + + + + # build the properties for the fields + + @property + def config_data(self) -> msk_top_regs_config_nco_fw_config_data_0x0x106a67e3_cls: + """ + Property to access config_data field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Frequency Control Word | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Sets the center frequency of the NCO as FW = Fn * 2^32/Fs, | + | | where Fn is the desired NCO frequency, and Fs is the NCO sample | + | | rate

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__config_data + + + @property + def systemrdl_python_child_name_map(self) -> dict[str, str]: + """ + In some cases systemRDL names need to be converted make them python safe, this dictionary + is used to map the original systemRDL names to the names of the python attributes of this + class + + Returns: dictionary whose key is the systemRDL names and value it the property name + """ + return {'config_data':'config_data', + } + + + + + + + + + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_config_nco_fw_config_data_0x0x106a67e3_cls: + return super().get_child_by_system_rdl_name(name) + + + + + + + + + + @property + def rdl_name(self) -> str: + return "Rx F1 NCO Frequency Control Word" + @property + def rdl_desc(self) -> str: + return "Set Demodulator F1 Frequency" + + + + + + + +class msk_top_regs_config_nco_fw_config_data_0x0x106a672f_cls(FieldAsyncReadWrite): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Frequency Control Word | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Sets the center frequency of the NCO as FW = Fn * 2^32/Fs, | + | | where Fn is the desired NCO frequency, and Fs is the NCO sample | + | | rate

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "Frequency Control Word" + @property + def rdl_desc(self) -> str: + return "Sets the center frequency of the NCO as FW = Fn * 2^32/Fs, \nwhere Fn is the desired NCO frequency, and Fs is the NCO sample rate" + + + + + + +class msk_top_regs_config_nco_fw_desc_42134a4f_name_d97dbd51_cls(RegAsyncReadWrite): + """ + Class to represent a register in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Tx F2 NCO Frequency Control Word | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Set Modulator F2 Frequency

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = ['__config_data'] + + def __init__(self, + address: int, + width: int, + accesswidth: int, + logger_handle: str, + inst_name: str, + parent: Union[AsyncAddressMap,AsyncRegFile,MemoryAsyncReadWrite]): + + super().__init__(address=address, + width=width, + accesswidth=accesswidth, + logger_handle=logger_handle, + inst_name=inst_name, + parent=parent) + + # build the field attributes + + self.__config_data:msk_top_regs_config_nco_fw_config_data_0x0x106a672f_cls = msk_top_regs_config_nco_fw_config_data_0x0x106a672f_cls( + parent_register=self, + size_props=FieldSizeProps( + width=32, + lsb=0, + msb=31, + low=0, + high=31), + misc_props=FieldMiscProps( + default=0, + is_volatile=False), + logger_handle=logger_handle+'.config_data', + inst_name='config_data', + field_type=int) + + @property + def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,FieldAsyncReadWrite]]: + """ + generator that produces has all the fields within the register + """ + yield self.config_data + + # Empty generator in case there are no children of this type + if False: yield + + + + + # build the properties for the fields + + @property + def config_data(self) -> msk_top_regs_config_nco_fw_config_data_0x0x106a672f_cls: + """ + Property to access config_data field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Frequency Control Word | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Sets the center frequency of the NCO as FW = Fn * 2^32/Fs, | + | | where Fn is the desired NCO frequency, and Fs is the NCO sample | + | | rate

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__config_data + + + @property + def systemrdl_python_child_name_map(self) -> dict[str, str]: + """ + In some cases systemRDL names need to be converted make them python safe, this dictionary + is used to map the original systemRDL names to the names of the python attributes of this + class + + Returns: dictionary whose key is the systemRDL names and value it the property name + """ + return {'config_data':'config_data', + } + + + + + + + + + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_config_nco_fw_config_data_0x0x106a672f_cls: + return super().get_child_by_system_rdl_name(name) + + + + + + + + + + @property + def rdl_name(self) -> str: + return "Tx F2 NCO Frequency Control Word" + @property + def rdl_desc(self) -> str: + return "Set Modulator F2 Frequency" + + + + + + + +class msk_top_regs_config_nco_fw_config_data_0x0x1067ecad_cls(FieldAsyncReadWrite): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Frequency Control Word | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Sets the center frequency of the NCO as FW = Fn * 2^32/Fs, | + | | where Fn is the desired NCO frequency, and Fs is the NCO sample | + | | rate

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "Frequency Control Word" + @property + def rdl_desc(self) -> str: + return "Sets the center frequency of the NCO as FW = Fn * 2^32/Fs, \nwhere Fn is the desired NCO frequency, and Fs is the NCO sample rate" + + + + + + +class msk_top_regs_config_nco_fw_desc_94d7aaf5_name_84dd0c1c_cls(RegAsyncReadWrite): + """ + Class to represent a register in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Tx F1 NCO Frequency Control Word | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Set Modulator F1 Frequency

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = ['__config_data'] + + def __init__(self, + address: int, + width: int, + accesswidth: int, + logger_handle: str, + inst_name: str, + parent: Union[AsyncAddressMap,AsyncRegFile,MemoryAsyncReadWrite]): + + super().__init__(address=address, + width=width, + accesswidth=accesswidth, + logger_handle=logger_handle, + inst_name=inst_name, + parent=parent) + + # build the field attributes + + self.__config_data:msk_top_regs_config_nco_fw_config_data_0x0x1067ecad_cls = msk_top_regs_config_nco_fw_config_data_0x0x1067ecad_cls( + parent_register=self, + size_props=FieldSizeProps( + width=32, + lsb=0, + msb=31, + low=0, + high=31), + misc_props=FieldMiscProps( + default=0, + is_volatile=False), + logger_handle=logger_handle+'.config_data', + inst_name='config_data', + field_type=int) + + @property + def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,FieldAsyncReadWrite]]: + """ + generator that produces has all the fields within the register + """ + yield self.config_data + + # Empty generator in case there are no children of this type + if False: yield + + + + + # build the properties for the fields + + @property + def config_data(self) -> msk_top_regs_config_nco_fw_config_data_0x0x1067ecad_cls: + """ + Property to access config_data field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Frequency Control Word | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Sets the center frequency of the NCO as FW = Fn * 2^32/Fs, | + | | where Fn is the desired NCO frequency, and Fs is the NCO sample | + | | rate

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__config_data + + + @property + def systemrdl_python_child_name_map(self) -> dict[str, str]: + """ + In some cases systemRDL names need to be converted make them python safe, this dictionary + is used to map the original systemRDL names to the names of the python attributes of this + class + + Returns: dictionary whose key is the systemRDL names and value it the property name + """ + return {'config_data':'config_data', + } + + + + + + + + + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_config_nco_fw_config_data_0x0x1067ecad_cls: + return super().get_child_by_system_rdl_name(name) + + + + + + + + + + @property + def rdl_name(self) -> str: + return "Tx F1 NCO Frequency Control Word" + @property + def rdl_desc(self) -> str: + return "Set Modulator F1 Frequency" + + + + + + + +class msk_top_regs_config_nco_fw_config_data_0x0x1069f40b_cls(FieldAsyncReadWrite): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Frequency Control Word | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Sets the center frequency of the NCO as FW = Fn * 2^32/Fs, | + | | where Fn is the desired NCO frequency, and Fs is the NCO sample | + | | rate

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "Frequency Control Word" + @property + def rdl_desc(self) -> str: + return "Sets the center frequency of the NCO as FW = Fn * 2^32/Fs, \nwhere Fn is the desired NCO frequency, and Fs is the NCO sample rate" + + + + + + +class msk_top_regs_config_nco_fw_desc_c4924cc6_name_0c494469_cls(RegAsyncReadWrite): + """ + Class to represent a register in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Bitrate NCO Frequency Control Word | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Set Modem Data Rate

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = ['__config_data'] + + def __init__(self, + address: int, + width: int, + accesswidth: int, + logger_handle: str, + inst_name: str, + parent: Union[AsyncAddressMap,AsyncRegFile,MemoryAsyncReadWrite]): + + super().__init__(address=address, + width=width, + accesswidth=accesswidth, + logger_handle=logger_handle, + inst_name=inst_name, + parent=parent) + + # build the field attributes + + self.__config_data:msk_top_regs_config_nco_fw_config_data_0x0x1069f40b_cls = msk_top_regs_config_nco_fw_config_data_0x0x1069f40b_cls( + parent_register=self, + size_props=FieldSizeProps( + width=32, + lsb=0, + msb=31, + low=0, + high=31), + misc_props=FieldMiscProps( + default=0, + is_volatile=False), + logger_handle=logger_handle+'.config_data', + inst_name='config_data', + field_type=int) + + @property + def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,FieldAsyncReadWrite]]: + """ + generator that produces has all the fields within the register + """ + yield self.config_data + + # Empty generator in case there are no children of this type + if False: yield + + + + + # build the properties for the fields + + @property + def config_data(self) -> msk_top_regs_config_nco_fw_config_data_0x0x1069f40b_cls: + """ + Property to access config_data field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Frequency Control Word | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Sets the center frequency of the NCO as FW = Fn * 2^32/Fs, | + | | where Fn is the desired NCO frequency, and Fs is the NCO sample | + | | rate

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__config_data + + + @property + def systemrdl_python_child_name_map(self) -> dict[str, str]: + """ + In some cases systemRDL names need to be converted make them python safe, this dictionary + is used to map the original systemRDL names to the names of the python attributes of this + class + + Returns: dictionary whose key is the systemRDL names and value it the property name + """ + return {'config_data':'config_data', + } + + + + + + + + + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_config_nco_fw_config_data_0x0x1069f40b_cls: + return super().get_child_by_system_rdl_name(name) + + + + + + + + + + @property + def rdl_name(self) -> str: + return "Bitrate NCO Frequency Control Word" + @property + def rdl_desc(self) -> str: + return "Set Modem Data Rate" + + + + + + + +class msk_top_regs_msk_stat_2_tx_ena_counter_cls(FieldAsyncReadOnly): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Tx Enable Count | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Number of clocks on which Tx Enable is active

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "Tx Enable Count" + @property + def rdl_desc(self) -> str: + return "Number of clocks on which Tx Enable is active" + + + + + + +class msk_top_regs_msk_stat_2_cls(RegAsyncReadOnly): + """ + Class to represent a register in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | MSK Modem Status 2 | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Modem status data

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = ['__tx_ena_counter'] + + def __init__(self, + address: int, + width: int, + accesswidth: int, + logger_handle: str, + inst_name: str, + parent: Union[AsyncAddressMap,AsyncRegFile,ReadableAsyncMemory]): + + super().__init__(address=address, + width=width, + accesswidth=accesswidth, + logger_handle=logger_handle, + inst_name=inst_name, + parent=parent) + + # build the field attributes + + self.__tx_ena_counter:msk_top_regs_msk_stat_2_tx_ena_counter_cls = msk_top_regs_msk_stat_2_tx_ena_counter_cls( + parent_register=self, + size_props=FieldSizeProps( + width=32, + lsb=0, + msb=31, + low=0, + high=31), + misc_props=FieldMiscProps( + default=0, + is_volatile=True), + logger_handle=logger_handle+'.tx_ena_counter', + inst_name='tx_ena_counter', + field_type=int) + + @property + def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,FieldAsyncReadWrite]]: + """ + generator that produces has all the fields within the register + """ + yield self.tx_ena_counter + + # Empty generator in case there are no children of this type + if False: yield + + + + + # build the properties for the fields + + @property + def tx_ena_counter(self) -> msk_top_regs_msk_stat_2_tx_ena_counter_cls: + """ + Property to access tx_ena_counter field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Tx Enable Count | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Number of clocks on which Tx Enable is active

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__tx_ena_counter + + + @property + def systemrdl_python_child_name_map(self) -> dict[str, str]: + """ + In some cases systemRDL names need to be converted make them python safe, this dictionary + is used to map the original systemRDL names to the names of the python attributes of this + class + + Returns: dictionary whose key is the systemRDL names and value it the property name + """ + return {'tx_ena_counter':'tx_ena_counter', + } + + + + + + + + + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_msk_stat_2_tx_ena_counter_cls: + return super().get_child_by_system_rdl_name(name) + + + + + + + + + + @property + def rdl_name(self) -> str: + return "MSK Modem Status 2" + @property + def rdl_desc(self) -> str: + return "Modem status data" + + + + + + + +class msk_top_regs_msk_stat_1_tx_bit_counter_cls(FieldAsyncReadOnly): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Tx Bit Count | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Count of data requests made by modem

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "Tx Bit Count" + @property + def rdl_desc(self) -> str: + return "Count of data requests made by modem" + + + + + + +class msk_top_regs_msk_stat_1_cls(RegAsyncReadOnly): + """ + Class to represent a register in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | MSK Modem Status 1 | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Modem status data

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = ['__tx_bit_counter'] + + def __init__(self, + address: int, + width: int, + accesswidth: int, + logger_handle: str, + inst_name: str, + parent: Union[AsyncAddressMap,AsyncRegFile,ReadableAsyncMemory]): + + super().__init__(address=address, + width=width, + accesswidth=accesswidth, + logger_handle=logger_handle, + inst_name=inst_name, + parent=parent) + + # build the field attributes + + self.__tx_bit_counter:msk_top_regs_msk_stat_1_tx_bit_counter_cls = msk_top_regs_msk_stat_1_tx_bit_counter_cls( + parent_register=self, + size_props=FieldSizeProps( + width=32, + lsb=0, + msb=31, + low=0, + high=31), + misc_props=FieldMiscProps( + default=None, + is_volatile=True), + logger_handle=logger_handle+'.tx_bit_counter', + inst_name='tx_bit_counter', + field_type=int) + + @property + def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,FieldAsyncReadWrite]]: + """ + generator that produces has all the fields within the register + """ + yield self.tx_bit_counter + + # Empty generator in case there are no children of this type + if False: yield + + + + + # build the properties for the fields + + @property + def tx_bit_counter(self) -> msk_top_regs_msk_stat_1_tx_bit_counter_cls: + """ + Property to access tx_bit_counter field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Tx Bit Count | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Count of data requests made by modem

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__tx_bit_counter + + + @property + def systemrdl_python_child_name_map(self) -> dict[str, str]: + """ + In some cases systemRDL names need to be converted make them python safe, this dictionary + is used to map the original systemRDL names to the names of the python attributes of this + class + + Returns: dictionary whose key is the systemRDL names and value it the property name + """ + return {'tx_bit_counter':'tx_bit_counter', + } + + + + + + + + + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_msk_stat_1_tx_bit_counter_cls: + return super().get_child_by_system_rdl_name(name) + + + + + + + + + + @property + def rdl_name(self) -> str: + return "MSK Modem Status 1" + @property + def rdl_desc(self) -> str: + return "Modem status data" + + + + + + + +class msk_top_regs_msk_stat_0_tx_axis_valid_cls(FieldAsyncReadOnly): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Tx S_AXIS_VALID | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

1 -> S_AXIS_VALID Enabled 0 -> S_AXIS_VALID Disabled

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "Tx S_AXIS_VALID" + @property + def rdl_desc(self) -> str: + return "1 -\u003e S_AXIS_VALID Enabled\n0 -\u003e S_AXIS_VALID Disabled" + + + + + + + +class msk_top_regs_msk_stat_0_rx_enable_cls(FieldAsyncReadOnly): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | AD9363 ADC Interface Rx Enable Input Active | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

1 -> Data from ADC Enabled 0 -> Data from ADC | + | | Disabled

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "AD9363 ADC Interface Rx Enable Input Active" + @property + def rdl_desc(self) -> str: + return "1 -\u003e Data from ADC Enabled\n0 -\u003e Data from ADC Disabled" + + + + + + + +class msk_top_regs_msk_stat_0_tx_enable_cls(FieldAsyncReadOnly): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | AD9363 DAC Interface Tx Enable Input Active | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

1 -> Data to DAC Enabled 0 -> Data to DAC Disabled

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "AD9363 DAC Interface Tx Enable Input Active" + @property + def rdl_desc(self) -> str: + return "1 -\u003e Data to DAC Enabled\n0 -\u003e Data to DAC Disabled" + + + + + + + +class msk_top_regs_msk_stat_0_demod_sync_lock_cls(FieldAsyncReadOnly): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Demodulator Sync Status | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Demodulator Sync Status - not currently implemented

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "Demodulator Sync Status" + @property + def rdl_desc(self) -> str: + return "Demodulator Sync Status - not currently implemented" + + + + + + +class msk_top_regs_msk_stat_0_cls(RegAsyncReadOnly): + """ + Class to represent a register in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | MSK Modem Status 0 | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Modem status bits

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = ['__demod_sync_lock', '__tx_enable', '__rx_enable', '__tx_axis_valid'] + + def __init__(self, + address: int, + width: int, + accesswidth: int, + logger_handle: str, + inst_name: str, + parent: Union[AsyncAddressMap,AsyncRegFile,ReadableAsyncMemory]): + + super().__init__(address=address, + width=width, + accesswidth=accesswidth, + logger_handle=logger_handle, + inst_name=inst_name, + parent=parent) + + # build the field attributes + + self.__demod_sync_lock:msk_top_regs_msk_stat_0_demod_sync_lock_cls = msk_top_regs_msk_stat_0_demod_sync_lock_cls( + parent_register=self, + size_props=FieldSizeProps( + width=1, + lsb=0, + msb=0, + low=0, + high=0), + misc_props=FieldMiscProps( + default=0, + is_volatile=True), + logger_handle=logger_handle+'.demod_sync_lock', + inst_name='demod_sync_lock', + field_type=int) + self.__tx_enable:msk_top_regs_msk_stat_0_tx_enable_cls = msk_top_regs_msk_stat_0_tx_enable_cls( + parent_register=self, + size_props=FieldSizeProps( + width=1, + lsb=1, + msb=1, + low=1, + high=1), + misc_props=FieldMiscProps( + default=0, + is_volatile=True), + logger_handle=logger_handle+'.tx_enable', + inst_name='tx_enable', + field_type=int) + self.__rx_enable:msk_top_regs_msk_stat_0_rx_enable_cls = msk_top_regs_msk_stat_0_rx_enable_cls( + parent_register=self, + size_props=FieldSizeProps( + width=1, + lsb=2, + msb=2, + low=2, + high=2), + misc_props=FieldMiscProps( + default=0, + is_volatile=True), + logger_handle=logger_handle+'.rx_enable', + inst_name='rx_enable', + field_type=int) + self.__tx_axis_valid:msk_top_regs_msk_stat_0_tx_axis_valid_cls = msk_top_regs_msk_stat_0_tx_axis_valid_cls( + parent_register=self, + size_props=FieldSizeProps( + width=1, + lsb=3, + msb=3, + low=3, + high=3), + misc_props=FieldMiscProps( + default=0, + is_volatile=True), + logger_handle=logger_handle+'.tx_axis_valid', + inst_name='tx_axis_valid', + field_type=int) + + @property + def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,FieldAsyncReadWrite]]: + """ + generator that produces has all the fields within the register + """ + yield self.demod_sync_lock + yield self.tx_enable + yield self.rx_enable + yield self.tx_axis_valid + + # Empty generator in case there are no children of this type + if False: yield + + + + + # build the properties for the fields + + @property + def demod_sync_lock(self) -> msk_top_regs_msk_stat_0_demod_sync_lock_cls: + """ + Property to access demod_sync_lock field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Demodulator Sync Status | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Demodulator Sync Status - not currently implemented

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__demod_sync_lock + @property + def tx_enable(self) -> msk_top_regs_msk_stat_0_tx_enable_cls: + """ + Property to access tx_enable field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | AD9363 DAC Interface Tx Enable Input Active | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

1 -> Data to DAC Enabled 0 -> Data to DAC Disabled

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__tx_enable + @property + def rx_enable(self) -> msk_top_regs_msk_stat_0_rx_enable_cls: + """ + Property to access rx_enable field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | AD9363 ADC Interface Rx Enable Input Active | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

1 -> Data from ADC Enabled 0 -> Data from ADC | + | | Disabled

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__rx_enable + @property + def tx_axis_valid(self) -> msk_top_regs_msk_stat_0_tx_axis_valid_cls: + """ + Property to access tx_axis_valid field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Tx S_AXIS_VALID | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

1 -> S_AXIS_VALID Enabled 0 -> S_AXIS_VALID Disabled

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__tx_axis_valid + + + @property + def systemrdl_python_child_name_map(self) -> dict[str, str]: + """ + In some cases systemRDL names need to be converted make them python safe, this dictionary + is used to map the original systemRDL names to the names of the python attributes of this + class + + Returns: dictionary whose key is the systemRDL names and value it the property name + """ + return {'demod_sync_lock':'demod_sync_lock','tx_enable':'tx_enable','rx_enable':'rx_enable','tx_axis_valid':'tx_axis_valid', + } + + + + + + + + # nodes:4 + + @overload + def get_child_by_system_rdl_name(self, name: Literal["demod_sync_lock"]) -> msk_top_regs_msk_stat_0_demod_sync_lock_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["tx_enable"]) -> msk_top_regs_msk_stat_0_tx_enable_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["rx_enable"]) -> msk_top_regs_msk_stat_0_rx_enable_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["tx_axis_valid"]) -> msk_top_regs_msk_stat_0_tx_axis_valid_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: str) -> Union[msk_top_regs_msk_stat_0_demod_sync_lock_cls, msk_top_regs_msk_stat_0_tx_enable_cls, msk_top_regs_msk_stat_0_rx_enable_cls, msk_top_regs_msk_stat_0_tx_axis_valid_cls, ]: ... + + def get_child_by_system_rdl_name(self, name: Any) -> Any: + return super().get_child_by_system_rdl_name(name) + + + + + + + + + @property + def rdl_name(self) -> str: + return "MSK Modem Status 0" + @property + def rdl_desc(self) -> str: + return "Modem status bits" + + + + + + + +class msk_top_regs_msk_ctrl_diff_encoder_loopback_cls(FieldAsyncReadWrite): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Differential Encoder -> Decoder Loopback Enable | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

0 -> Differential Encoder -> Decoder loopback disabled 1 | + | | -> Differential Encoder -> Decoder loopback enabled

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "Differential Encoder -\u003e Decoder Loopback Enable" + @property + def rdl_desc(self) -> str: + return "0 -\u003e Differential Encoder -\u003e Decoder loopback disabled\n1 -\u003e Differential Encoder -\u003e Decoder loopback enabled" + + + + + + + +class msk_top_regs_msk_ctrl_clear_counts_cls(FieldAsyncReadWrite): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Clear Status Counters | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Clear Tx Bit Counter and Tx Enable Counter

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "Clear Status Counters" + @property + def rdl_desc(self) -> str: + return "Clear Tx Bit Counter and Tx Enable Counter" + + + + + + + +class msk_top_regs_msk_ctrl_rx_invert_cls(FieldAsyncReadWrite): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Rx Data Invert Enable | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

0 -> Rx data normal 1 -> Rx data inverted

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "Rx Data Invert Enable" + @property + def rdl_desc(self) -> str: + return "0 -\u003e Rx data normal\n1 -\u003e Rx data inverted" + + + + + + + +class msk_top_regs_msk_ctrl_loopback_ena_cls(FieldAsyncReadWrite): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Modem Digital Tx -> Rx Loopback Enable | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

0 -> Modem loopback disabled 1 -> Modem loopback | + | | enabled

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "Modem Digital Tx -\u003e Rx Loopback Enable" + @property + def rdl_desc(self) -> str: + return "0 -\u003e Modem loopback disabled\n1 -\u003e Modem loopback enabled" + + + + + + + +class msk_top_regs_msk_ctrl_ptt_cls(FieldAsyncReadWrite): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Push-to-Talk Enable | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

0 -> PTT Disabled 1 -> PTT Enabled

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "Push-to-Talk Enable" + @property + def rdl_desc(self) -> str: + return "0 -\u003e PTT Disabled\n1 -\u003e PTT Enabled" + + + + + + +class msk_top_regs_msk_ctrl_cls(RegAsyncReadWrite): + """ + Class to represent a register in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | MSK Modem Control | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

MSK Modem Configuration and Control

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = ['__ptt', '__loopback_ena', '__rx_invert', '__clear_counts', '__diff_encoder_loopback'] + + def __init__(self, + address: int, + width: int, + accesswidth: int, + logger_handle: str, + inst_name: str, + parent: Union[AsyncAddressMap,AsyncRegFile,MemoryAsyncReadWrite]): + + super().__init__(address=address, + width=width, + accesswidth=accesswidth, + logger_handle=logger_handle, + inst_name=inst_name, + parent=parent) + + # build the field attributes + + self.__ptt:msk_top_regs_msk_ctrl_ptt_cls = msk_top_regs_msk_ctrl_ptt_cls( + parent_register=self, + size_props=FieldSizeProps( + width=1, + lsb=0, + msb=0, + low=0, + high=0), + misc_props=FieldMiscProps( + default=0, + is_volatile=False), + logger_handle=logger_handle+'.ptt', + inst_name='ptt', + field_type=int) + self.__loopback_ena:msk_top_regs_msk_ctrl_loopback_ena_cls = msk_top_regs_msk_ctrl_loopback_ena_cls( + parent_register=self, + size_props=FieldSizeProps( + width=1, + lsb=1, + msb=1, + low=1, + high=1), + misc_props=FieldMiscProps( + default=0, + is_volatile=False), + logger_handle=logger_handle+'.loopback_ena', + inst_name='loopback_ena', + field_type=int) + self.__rx_invert:msk_top_regs_msk_ctrl_rx_invert_cls = msk_top_regs_msk_ctrl_rx_invert_cls( + parent_register=self, + size_props=FieldSizeProps( + width=1, + lsb=2, + msb=2, + low=2, + high=2), + misc_props=FieldMiscProps( + default=0, + is_volatile=False), + logger_handle=logger_handle+'.rx_invert', + inst_name='rx_invert', + field_type=int) + self.__clear_counts:msk_top_regs_msk_ctrl_clear_counts_cls = msk_top_regs_msk_ctrl_clear_counts_cls( + parent_register=self, + size_props=FieldSizeProps( + width=1, + lsb=3, + msb=3, + low=3, + high=3), + misc_props=FieldMiscProps( + default=0, + is_volatile=False), + logger_handle=logger_handle+'.clear_counts', + inst_name='clear_counts', + field_type=int) + self.__diff_encoder_loopback:msk_top_regs_msk_ctrl_diff_encoder_loopback_cls = msk_top_regs_msk_ctrl_diff_encoder_loopback_cls( + parent_register=self, + size_props=FieldSizeProps( + width=1, + lsb=4, + msb=4, + low=4, + high=4), + misc_props=FieldMiscProps( + default=0, + is_volatile=False), + logger_handle=logger_handle+'.diff_encoder_loopback', + inst_name='diff_encoder_loopback', + field_type=int) + + @property + def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,FieldAsyncReadWrite]]: + """ + generator that produces has all the fields within the register + """ + yield self.ptt + yield self.loopback_ena + yield self.rx_invert + yield self.clear_counts + yield self.diff_encoder_loopback + + # Empty generator in case there are no children of this type + if False: yield + + + + + # build the properties for the fields + + @property + def ptt(self) -> msk_top_regs_msk_ctrl_ptt_cls: + """ + Property to access ptt field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Push-to-Talk Enable | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

0 -> PTT Disabled 1 -> PTT Enabled

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__ptt + @property + def loopback_ena(self) -> msk_top_regs_msk_ctrl_loopback_ena_cls: + """ + Property to access loopback_ena field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Modem Digital Tx -> Rx Loopback Enable | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

0 -> Modem loopback disabled 1 -> Modem loopback | + | | enabled

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__loopback_ena + @property + def rx_invert(self) -> msk_top_regs_msk_ctrl_rx_invert_cls: + """ + Property to access rx_invert field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Rx Data Invert Enable | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

0 -> Rx data normal 1 -> Rx data inverted

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__rx_invert + @property + def clear_counts(self) -> msk_top_regs_msk_ctrl_clear_counts_cls: + """ + Property to access clear_counts field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Clear Status Counters | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Clear Tx Bit Counter and Tx Enable Counter

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__clear_counts + @property + def diff_encoder_loopback(self) -> msk_top_regs_msk_ctrl_diff_encoder_loopback_cls: + """ + Property to access diff_encoder_loopback field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Differential Encoder -> Decoder Loopback Enable | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

0 -> Differential Encoder -> Decoder loopback disabled 1 | + | | -> Differential Encoder -> Decoder loopback enabled

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__diff_encoder_loopback + + + @property + def systemrdl_python_child_name_map(self) -> dict[str, str]: + """ + In some cases systemRDL names need to be converted make them python safe, this dictionary + is used to map the original systemRDL names to the names of the python attributes of this + class + + Returns: dictionary whose key is the systemRDL names and value it the property name + """ + return {'ptt':'ptt','loopback_ena':'loopback_ena','rx_invert':'rx_invert','clear_counts':'clear_counts','diff_encoder_loopback':'diff_encoder_loopback', + } + + + + + + + + # nodes:5 + + @overload + def get_child_by_system_rdl_name(self, name: Literal["ptt"]) -> msk_top_regs_msk_ctrl_ptt_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["loopback_ena"]) -> msk_top_regs_msk_ctrl_loopback_ena_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["rx_invert"]) -> msk_top_regs_msk_ctrl_rx_invert_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["clear_counts"]) -> msk_top_regs_msk_ctrl_clear_counts_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["diff_encoder_loopback"]) -> msk_top_regs_msk_ctrl_diff_encoder_loopback_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: str) -> Union[msk_top_regs_msk_ctrl_ptt_cls, msk_top_regs_msk_ctrl_loopback_ena_cls, msk_top_regs_msk_ctrl_rx_invert_cls, msk_top_regs_msk_ctrl_clear_counts_cls, msk_top_regs_msk_ctrl_diff_encoder_loopback_cls, ]: ... + + def get_child_by_system_rdl_name(self, name: Any) -> Any: + return super().get_child_by_system_rdl_name(name) + + + + + + + + + @property + def rdl_name(self) -> str: + return "MSK Modem Control" + @property + def rdl_desc(self) -> str: + return "MSK Modem Configuration and Control" + + + + + + + +class msk_top_regs_msk_init_rxinit_cls(FieldAsyncReadWrite): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Rx Init Enable | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

0 -> Normal Rx operation 1 -> Initialize Rx

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "Rx Init Enable" + @property + def rdl_desc(self) -> str: + return "0 -\u003e Normal Rx operation \n1 -\u003e Initialize Rx" + + + + + + + +class msk_top_regs_msk_init_txinit_cls(FieldAsyncReadWrite): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Tx Init Enable | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

0 -> Normal Tx operation 1 -> Initialize Tx

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "Tx Init Enable" + @property + def rdl_desc(self) -> str: + return "0 -\u003e Normal Tx operation \n1 -\u003e Initialize Tx" + + + + + + + +class msk_top_regs_msk_init_txrxinit_cls(FieldAsyncReadWrite): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Tx/Rx Init Enable | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

0 -> Normal modem operation 1 -> Initialize Tx and | + | | Rx

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "Tx/Rx Init Enable" + @property + def rdl_desc(self) -> str: + return "0 -\u003e Normal modem operation \n1 -\u003e Initialize Tx and Rx" + + + + + + +class msk_top_regs_msk_init_cls(RegAsyncReadWrite): + """ + Class to represent a register in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | MSK Modem Initialization Control | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Synchronous initialization of MSK Modem functions, does not | + | | affect configuration registers.

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = ['__txrxinit', '__txinit', '__rxinit'] + + def __init__(self, + address: int, + width: int, + accesswidth: int, + logger_handle: str, + inst_name: str, + parent: Union[AsyncAddressMap,AsyncRegFile,MemoryAsyncReadWrite]): + + super().__init__(address=address, + width=width, + accesswidth=accesswidth, + logger_handle=logger_handle, + inst_name=inst_name, + parent=parent) + + # build the field attributes + + self.__txrxinit:msk_top_regs_msk_init_txrxinit_cls = msk_top_regs_msk_init_txrxinit_cls( + parent_register=self, + size_props=FieldSizeProps( + width=1, + lsb=0, + msb=0, + low=0, + high=0), + misc_props=FieldMiscProps( + default=1, + is_volatile=False), + logger_handle=logger_handle+'.txrxinit', + inst_name='txrxinit', + field_type=int) + self.__txinit:msk_top_regs_msk_init_txinit_cls = msk_top_regs_msk_init_txinit_cls( + parent_register=self, + size_props=FieldSizeProps( + width=1, + lsb=1, + msb=1, + low=1, + high=1), + misc_props=FieldMiscProps( + default=1, + is_volatile=False), + logger_handle=logger_handle+'.txinit', + inst_name='txinit', + field_type=int) + self.__rxinit:msk_top_regs_msk_init_rxinit_cls = msk_top_regs_msk_init_rxinit_cls( + parent_register=self, + size_props=FieldSizeProps( + width=1, + lsb=2, + msb=2, + low=2, + high=2), + misc_props=FieldMiscProps( + default=1, + is_volatile=False), + logger_handle=logger_handle+'.rxinit', + inst_name='rxinit', + field_type=int) + + @property + def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,FieldAsyncReadWrite]]: + """ + generator that produces has all the fields within the register + """ + yield self.txrxinit + yield self.txinit + yield self.rxinit + + # Empty generator in case there are no children of this type + if False: yield + + + + + # build the properties for the fields + + @property + def txrxinit(self) -> msk_top_regs_msk_init_txrxinit_cls: + """ + Property to access txrxinit field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Tx/Rx Init Enable | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

0 -> Normal modem operation 1 -> Initialize Tx and | + | | Rx

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__txrxinit + @property + def txinit(self) -> msk_top_regs_msk_init_txinit_cls: + """ + Property to access txinit field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Tx Init Enable | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

0 -> Normal Tx operation 1 -> Initialize Tx

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__txinit + @property + def rxinit(self) -> msk_top_regs_msk_init_rxinit_cls: + """ + Property to access rxinit field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Rx Init Enable | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

0 -> Normal Rx operation 1 -> Initialize Rx

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__rxinit + + + @property + def systemrdl_python_child_name_map(self) -> dict[str, str]: + """ + In some cases systemRDL names need to be converted make them python safe, this dictionary + is used to map the original systemRDL names to the names of the python attributes of this + class + + Returns: dictionary whose key is the systemRDL names and value it the property name + """ + return {'txrxinit':'txrxinit','txinit':'txinit','rxinit':'rxinit', + } + + + + + + + + # nodes:3 + + @overload + def get_child_by_system_rdl_name(self, name: Literal["txrxinit"]) -> msk_top_regs_msk_init_txrxinit_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["txinit"]) -> msk_top_regs_msk_init_txinit_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["rxinit"]) -> msk_top_regs_msk_init_rxinit_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: str) -> Union[msk_top_regs_msk_init_txrxinit_cls, msk_top_regs_msk_init_txinit_cls, msk_top_regs_msk_init_rxinit_cls, ]: ... + + def get_child_by_system_rdl_name(self, name: Any) -> Any: + return super().get_child_by_system_rdl_name(name) + + + + + + + + + @property + def rdl_name(self) -> str: + return "MSK Modem Initialization Control" + @property + def rdl_desc(self) -> str: + return "Synchronous initialization of MSK Modem functions, does not affect configuration registers." + + + + + + + +class msk_top_regs_msk_hash_hi_hash_id_hi_cls(FieldAsyncReadOnly): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Hash ID Upper 32-bits | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Upper 32-bits of Pluto MSK FPGA Hash ID

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "Hash ID Upper 32-bits" + @property + def rdl_desc(self) -> str: + return "Upper 32-bits of Pluto MSK FPGA Hash ID" + + + + + + +class msk_top_regs_msk_hash_hi_cls(RegAsyncReadOnly): + """ + Class to represent a register in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Pluto MSK FPGA Hash ID - Upper 32-bits | + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = ['__hash_id_hi'] + + def __init__(self, + address: int, + width: int, + accesswidth: int, + logger_handle: str, + inst_name: str, + parent: Union[AsyncAddressMap,AsyncRegFile,ReadableAsyncMemory]): + + super().__init__(address=address, + width=width, + accesswidth=accesswidth, + logger_handle=logger_handle, + inst_name=inst_name, + parent=parent) + + # build the field attributes + + self.__hash_id_hi:msk_top_regs_msk_hash_hi_hash_id_hi_cls = msk_top_regs_msk_hash_hi_hash_id_hi_cls( + parent_register=self, + size_props=FieldSizeProps( + width=32, + lsb=0, + msb=31, + low=0, + high=31), + misc_props=FieldMiscProps( + default=1431677610, + is_volatile=False), + logger_handle=logger_handle+'.hash_id_hi', + inst_name='hash_id_hi', + field_type=int) + + @property + def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,FieldAsyncReadWrite]]: + """ + generator that produces has all the fields within the register + """ + yield self.hash_id_hi + + # Empty generator in case there are no children of this type + if False: yield + + + + + # build the properties for the fields + + @property + def hash_id_hi(self) -> msk_top_regs_msk_hash_hi_hash_id_hi_cls: + """ + Property to access hash_id_hi field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Hash ID Upper 32-bits | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Upper 32-bits of Pluto MSK FPGA Hash ID

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__hash_id_hi + + + @property + def systemrdl_python_child_name_map(self) -> dict[str, str]: + """ + In some cases systemRDL names need to be converted make them python safe, this dictionary + is used to map the original systemRDL names to the names of the python attributes of this + class + + Returns: dictionary whose key is the systemRDL names and value it the property name + """ + return {'hash_id_hi':'hash_id_hi', + } + + + + + + + + + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_msk_hash_hi_hash_id_hi_cls: + return super().get_child_by_system_rdl_name(name) + + + + + + + + + + @property + def rdl_name(self) -> str: + return "Pluto MSK FPGA Hash ID - Upper 32-bits" + + + + + + + +class msk_top_regs_msk_hash_lo_hash_id_lo_cls(FieldAsyncReadOnly): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Hash ID Lower 32-bits | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Lower 32-bits of Pluto MSK FPGA Hash ID

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "Hash ID Lower 32-bits" + @property + def rdl_desc(self) -> str: + return "Lower 32-bits of Pluto MSK FPGA Hash ID" + + + + + + +class msk_top_regs_msk_hash_lo_cls(RegAsyncReadOnly): + """ + Class to represent a register in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Pluto MSK FPGA Hash ID - Lower 32-bits | + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = ['__hash_id_lo'] + + def __init__(self, + address: int, + width: int, + accesswidth: int, + logger_handle: str, + inst_name: str, + parent: Union[AsyncAddressMap,AsyncRegFile,ReadableAsyncMemory]): + + super().__init__(address=address, + width=width, + accesswidth=accesswidth, + logger_handle=logger_handle, + inst_name=inst_name, + parent=parent) + + # build the field attributes + + self.__hash_id_lo:msk_top_regs_msk_hash_lo_hash_id_lo_cls = msk_top_regs_msk_hash_lo_hash_id_lo_cls( + parent_register=self, + size_props=FieldSizeProps( + width=32, + lsb=0, + msb=31, + low=0, + high=31), + misc_props=FieldMiscProps( + default=2863289685, + is_volatile=False), + logger_handle=logger_handle+'.hash_id_lo', + inst_name='hash_id_lo', + field_type=int) + + @property + def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,FieldAsyncReadWrite]]: + """ + generator that produces has all the fields within the register + """ + yield self.hash_id_lo + + # Empty generator in case there are no children of this type + if False: yield + + + + + # build the properties for the fields + + @property + def hash_id_lo(self) -> msk_top_regs_msk_hash_lo_hash_id_lo_cls: + """ + Property to access hash_id_lo field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Hash ID Lower 32-bits | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Lower 32-bits of Pluto MSK FPGA Hash ID

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__hash_id_lo + + + @property + def systemrdl_python_child_name_map(self) -> dict[str, str]: + """ + In some cases systemRDL names need to be converted make them python safe, this dictionary + is used to map the original systemRDL names to the names of the python attributes of this + class + + Returns: dictionary whose key is the systemRDL names and value it the property name + """ + return {'hash_id_lo':'hash_id_lo', + } + + + + + + + + + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_msk_hash_lo_hash_id_lo_cls: + return super().get_child_by_system_rdl_name(name) + + + + + + + + + + @property + def rdl_name(self) -> str: + return "Pluto MSK FPGA Hash ID - Lower 32-bits" + + + + + + +class msk_top_regs_cls(AsyncAddressMap): + """ + Class to represent a address map in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Pluto MSK Registers | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

MSK Modem Configuration and Status Registers

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = ['__Hash_ID_Low', '__Hash_ID_High', '__MSK_Init', '__MSK_Control', '__MSK_Status', '__Tx_Bit_Count', '__Tx_Enable_Count', '__Fb_FreqWord', '__TX_F1_FreqWord', '__TX_F2_FreqWord', '__RX_F1_FreqWord', '__RX_F2_FreqWord', '__LPF_Config_0', '__LPF_Config_1', '__Tx_Data_Width', '__Rx_Data_Width', '__PRBS_Control', '__PRBS_Initial_State', '__PRBS_Polynomial', '__PRBS_Error_Mask', '__PRBS_Bit_Count', '__PRBS_Error_Count', '__LPF_Accum_F1', '__LPF_Accum_F2', '__axis_xfer_count', '__Rx_Sample_Discard', '__LPF_Config_2', '__f1_nco_adjust', '__f2_nco_adjust', '__f1_error', '__f2_error', '__Tx_Sync_Ctrl', '__Tx_Sync_Cnt', '__lowpass_ema_alpha1', '__lowpass_ema_alpha2', '__rx_power'] + + def __init__(self, *, + address:int=0, + logger_handle:str='reg_model.msk_top_regs', + inst_name:str='msk_top_regs', + callbacks: Optional[Union[AsyncCallbackSet, AsyncCallbackSetLegacy]]=None, + parent:Optional[AsyncAddressMap]=None): + + if callbacks is not None: + if not isinstance(callbacks, (AsyncCallbackSet, AsyncCallbackSetLegacy)): + raise TypeError(f'callbacks should be AsyncCallbackSet, AsyncCallbackSetLegacy got {type(callbacks)}') + + super().__init__(callbacks=callbacks, + address=address, + logger_handle=logger_handle, + inst_name=inst_name, + parent=parent) + + + + self.__Hash_ID_Low:msk_top_regs_msk_hash_lo_cls = msk_top_regs_msk_hash_lo_cls( + address=self.address+0, + accesswidth=32, + width=32, + logger_handle=logger_handle+'.Hash_ID_Low', + inst_name='Hash_ID_Low', parent=self) + + + self.__Hash_ID_High:msk_top_regs_msk_hash_hi_cls = msk_top_regs_msk_hash_hi_cls( + address=self.address+4, + accesswidth=32, + width=32, + logger_handle=logger_handle+'.Hash_ID_High', + inst_name='Hash_ID_High', parent=self) + + + self.__MSK_Init:msk_top_regs_msk_init_cls = msk_top_regs_msk_init_cls( + address=self.address+8, + accesswidth=32, + width=32, + logger_handle=logger_handle+'.MSK_Init', + inst_name='MSK_Init', parent=self) + + + self.__MSK_Control:msk_top_regs_msk_ctrl_cls = msk_top_regs_msk_ctrl_cls( + address=self.address+12, + accesswidth=32, + width=32, + logger_handle=logger_handle+'.MSK_Control', + inst_name='MSK_Control', parent=self) + + + self.__MSK_Status:msk_top_regs_msk_stat_0_cls = msk_top_regs_msk_stat_0_cls( + address=self.address+16, + accesswidth=32, + width=32, + logger_handle=logger_handle+'.MSK_Status', + inst_name='MSK_Status', parent=self) + + + self.__Tx_Bit_Count:msk_top_regs_msk_stat_1_cls = msk_top_regs_msk_stat_1_cls( + address=self.address+20, + accesswidth=32, + width=32, + logger_handle=logger_handle+'.Tx_Bit_Count', + inst_name='Tx_Bit_Count', parent=self) + + + self.__Tx_Enable_Count:msk_top_regs_msk_stat_2_cls = msk_top_regs_msk_stat_2_cls( + address=self.address+24, + accesswidth=32, + width=32, + logger_handle=logger_handle+'.Tx_Enable_Count', + inst_name='Tx_Enable_Count', parent=self) + + + self.__Fb_FreqWord:msk_top_regs_config_nco_fw_desc_c4924cc6_name_0c494469_cls = msk_top_regs_config_nco_fw_desc_c4924cc6_name_0c494469_cls( + address=self.address+28, + accesswidth=32, + width=32, + logger_handle=logger_handle+'.Fb_FreqWord', + inst_name='Fb_FreqWord', parent=self) + + + self.__TX_F1_FreqWord:msk_top_regs_config_nco_fw_desc_94d7aaf5_name_84dd0c1c_cls = msk_top_regs_config_nco_fw_desc_94d7aaf5_name_84dd0c1c_cls( + address=self.address+32, + accesswidth=32, + width=32, + logger_handle=logger_handle+'.TX_F1_FreqWord', + inst_name='TX_F1_FreqWord', parent=self) + + + self.__TX_F2_FreqWord:msk_top_regs_config_nco_fw_desc_42134a4f_name_d97dbd51_cls = msk_top_regs_config_nco_fw_desc_42134a4f_name_d97dbd51_cls( + address=self.address+36, + accesswidth=32, + width=32, + logger_handle=logger_handle+'.TX_F2_FreqWord', + inst_name='TX_F2_FreqWord', parent=self) + + + self.__RX_F1_FreqWord:msk_top_regs_config_nco_fw_desc_16fb48c8_name_8d01a20d_cls = msk_top_regs_config_nco_fw_desc_16fb48c8_name_8d01a20d_cls( + address=self.address+40, + accesswidth=32, + width=32, + logger_handle=logger_handle+'.RX_F1_FreqWord', + inst_name='RX_F1_FreqWord', parent=self) + + + self.__RX_F2_FreqWord:msk_top_regs_config_nco_fw_desc_43c0828f_name_bdc60ecf_cls = msk_top_regs_config_nco_fw_desc_43c0828f_name_bdc60ecf_cls( + address=self.address+44, + accesswidth=32, + width=32, + logger_handle=logger_handle+'.RX_F2_FreqWord', + inst_name='RX_F2_FreqWord', parent=self) + + + self.__LPF_Config_0:msk_top_regs_lpf_config_0_cls = msk_top_regs_lpf_config_0_cls( + address=self.address+48, + accesswidth=32, + width=32, + logger_handle=logger_handle+'.LPF_Config_0', + inst_name='LPF_Config_0', parent=self) + + + self.__LPF_Config_1:msk_top_regs_lpf_config_1_cls = msk_top_regs_lpf_config_1_cls( + address=self.address+52, + accesswidth=32, + width=32, + logger_handle=logger_handle+'.LPF_Config_1', + inst_name='LPF_Config_1', parent=self) + + + self.__Tx_Data_Width:msk_top_regs_data_width_desc_58c848dd_name_2fbd8eba_cls = msk_top_regs_data_width_desc_58c848dd_name_2fbd8eba_cls( + address=self.address+56, + accesswidth=32, + width=32, + logger_handle=logger_handle+'.Tx_Data_Width', + inst_name='Tx_Data_Width', parent=self) + + + self.__Rx_Data_Width:msk_top_regs_data_width_desc_6097df38_name_4609588b_cls = msk_top_regs_data_width_desc_6097df38_name_4609588b_cls( + address=self.address+60, + accesswidth=32, + width=32, + logger_handle=logger_handle+'.Rx_Data_Width', + inst_name='Rx_Data_Width', parent=self) + + + self.__PRBS_Control:msk_top_regs_prbs_ctrl_cls = msk_top_regs_prbs_ctrl_cls( + address=self.address+64, + accesswidth=32, + width=32, + logger_handle=logger_handle+'.PRBS_Control', + inst_name='PRBS_Control', parent=self) + + + self.__PRBS_Initial_State:msk_top_regs_config_prbs_seed_cls = msk_top_regs_config_prbs_seed_cls( + address=self.address+68, + accesswidth=32, + width=32, + logger_handle=logger_handle+'.PRBS_Initial_State', + inst_name='PRBS_Initial_State', parent=self) + + + self.__PRBS_Polynomial:msk_top_regs_config_prbs_poly_cls = msk_top_regs_config_prbs_poly_cls( + address=self.address+72, + accesswidth=32, + width=32, + logger_handle=logger_handle+'.PRBS_Polynomial', + inst_name='PRBS_Polynomial', parent=self) + + + self.__PRBS_Error_Mask:msk_top_regs_config_prbs_errmask_cls = msk_top_regs_config_prbs_errmask_cls( + address=self.address+76, + accesswidth=32, + width=32, + logger_handle=logger_handle+'.PRBS_Error_Mask', + inst_name='PRBS_Error_Mask', parent=self) + + + self.__PRBS_Bit_Count:msk_top_regs_stat_32_bits_cls = msk_top_regs_stat_32_bits_cls( + address=self.address+80, + accesswidth=32, + width=32, + logger_handle=logger_handle+'.PRBS_Bit_Count', + inst_name='PRBS_Bit_Count', parent=self) + + + self.__PRBS_Error_Count:msk_top_regs_stat_32_errs_cls = msk_top_regs_stat_32_errs_cls( + address=self.address+84, + accesswidth=32, + width=32, + logger_handle=logger_handle+'.PRBS_Error_Count', + inst_name='PRBS_Error_Count', parent=self) + + + self.__LPF_Accum_F1:msk_top_regs_stat_32_lpf_acc_desc_8cebc7dc_name_f20c6670_cls = msk_top_regs_stat_32_lpf_acc_desc_8cebc7dc_name_f20c6670_cls( + address=self.address+88, + accesswidth=32, + width=32, + logger_handle=logger_handle+'.LPF_Accum_F1', + inst_name='LPF_Accum_F1', parent=self) + + + self.__LPF_Accum_F2:msk_top_regs_stat_32_lpf_acc_desc_dea6bd99_name_758fd0ce_cls = msk_top_regs_stat_32_lpf_acc_desc_dea6bd99_name_758fd0ce_cls( + address=self.address+92, + accesswidth=32, + width=32, + logger_handle=logger_handle+'.LPF_Accum_F2', + inst_name='LPF_Accum_F2', parent=self) + + + self.__axis_xfer_count:msk_top_regs_msk_stat_3_cls = msk_top_regs_msk_stat_3_cls( + address=self.address+96, + accesswidth=32, + width=32, + logger_handle=logger_handle+'.axis_xfer_count', + inst_name='axis_xfer_count', parent=self) + + + self.__Rx_Sample_Discard:msk_top_regs_rx_sample_discard_cls = msk_top_regs_rx_sample_discard_cls( + address=self.address+100, + accesswidth=32, + width=32, + logger_handle=logger_handle+'.Rx_Sample_Discard', + inst_name='Rx_Sample_Discard', parent=self) + + + self.__LPF_Config_2:msk_top_regs_lpf_config_2_cls = msk_top_regs_lpf_config_2_cls( + address=self.address+104, + accesswidth=32, + width=32, + logger_handle=logger_handle+'.LPF_Config_2', + inst_name='LPF_Config_2', parent=self) + + + self.__f1_nco_adjust:msk_top_regs_observation_data_data_0c017ef4_desc_64ff3689_name_d8ad3b25_cls = msk_top_regs_observation_data_data_0c017ef4_desc_64ff3689_name_d8ad3b25_cls( + address=self.address+108, + accesswidth=32, + width=32, + logger_handle=logger_handle+'.f1_nco_adjust', + inst_name='f1_nco_adjust', parent=self) + + + self.__f2_nco_adjust:msk_top_regs_observation_data_data_0515efaa_desc_ebde6d39_name_2c154788_cls = msk_top_regs_observation_data_data_0515efaa_desc_ebde6d39_name_2c154788_cls( + address=self.address+112, + accesswidth=32, + width=32, + logger_handle=logger_handle+'.f2_nco_adjust', + inst_name='f2_nco_adjust', parent=self) + + + self.__f1_error:msk_top_regs_observation_data_data_25a21249_desc_417e1c96_name_3b640507_cls = msk_top_regs_observation_data_data_25a21249_desc_417e1c96_name_3b640507_cls( + address=self.address+116, + accesswidth=32, + width=32, + logger_handle=logger_handle+'.f1_error', + inst_name='f1_error', parent=self) + + + self.__f2_error:msk_top_regs_observation_data_data_272a00b6_desc_70869502_name_3de9a0d3_cls = msk_top_regs_observation_data_data_272a00b6_desc_70869502_name_3de9a0d3_cls( + address=self.address+120, + accesswidth=32, + width=32, + logger_handle=logger_handle+'.f2_error', + inst_name='f2_error', parent=self) + + + self.__Tx_Sync_Ctrl:msk_top_regs_tx_sync_ctrl_cls = msk_top_regs_tx_sync_ctrl_cls( + address=self.address+124, + accesswidth=32, + width=32, + logger_handle=logger_handle+'.Tx_Sync_Ctrl', + inst_name='Tx_Sync_Ctrl', parent=self) + + + self.__Tx_Sync_Cnt:msk_top_regs_tx_sync_cnt_cls = msk_top_regs_tx_sync_cnt_cls( + address=self.address+128, + accesswidth=32, + width=32, + logger_handle=logger_handle+'.Tx_Sync_Cnt', + inst_name='Tx_Sync_Cnt', parent=self) + + + self.__lowpass_ema_alpha1:msk_top_regs_lowpass_ema_alpha_0x0x106a8591_cls = msk_top_regs_lowpass_ema_alpha_0x0x106a8591_cls( + address=self.address+132, + accesswidth=32, + width=32, + logger_handle=logger_handle+'.lowpass_ema_alpha1', + inst_name='lowpass_ema_alpha1', parent=self) + + + self.__lowpass_ema_alpha2:msk_top_regs_lowpass_ema_alpha_cls = msk_top_regs_lowpass_ema_alpha_cls( + address=self.address+136, + accesswidth=32, + width=32, + logger_handle=logger_handle+'.lowpass_ema_alpha2', + inst_name='lowpass_ema_alpha2', parent=self) + + + self.__rx_power:msk_top_regs_rx_power_cls = msk_top_regs_rx_power_cls( + address=self.address+140, + accesswidth=32, + width=32, + logger_handle=logger_handle+'.rx_power', + inst_name='rx_power', parent=self) + + + @property + def size(self) -> int: + return 144 + @property + def Hash_ID_Low(self) -> msk_top_regs_msk_hash_lo_cls: + """ + Property to access Hash_ID_Low + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Pluto MSK FPGA Hash ID - Lower 32-bits | + +--------------+-------------------------------------------------------------------------+ + """ + return self.__Hash_ID_Low + + @property + def Hash_ID_High(self) -> msk_top_regs_msk_hash_hi_cls: + """ + Property to access Hash_ID_High + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Pluto MSK FPGA Hash ID - Upper 32-bits | + +--------------+-------------------------------------------------------------------------+ + """ + return self.__Hash_ID_High + + @property + def MSK_Init(self) -> msk_top_regs_msk_init_cls: + """ + Property to access MSK_Init + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | MSK Modem Initialization Control | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Synchronous initialization of MSK Modem functions, does not | + | | affect configuration registers.

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__MSK_Init + + @property + def MSK_Control(self) -> msk_top_regs_msk_ctrl_cls: + """ + Property to access MSK_Control + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | MSK Modem Control | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

MSK Modem Configuration and Control

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__MSK_Control + + @property + def MSK_Status(self) -> msk_top_regs_msk_stat_0_cls: + """ + Property to access MSK_Status + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | MSK Modem Status 0 | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Modem status bits

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__MSK_Status + + @property + def Tx_Bit_Count(self) -> msk_top_regs_msk_stat_1_cls: + """ + Property to access Tx_Bit_Count + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | MSK Modem Status 1 | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Modem status data

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__Tx_Bit_Count + + @property + def Tx_Enable_Count(self) -> msk_top_regs_msk_stat_2_cls: + """ + Property to access Tx_Enable_Count + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | MSK Modem Status 2 | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Modem status data

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__Tx_Enable_Count + + @property + def Fb_FreqWord(self) -> msk_top_regs_config_nco_fw_desc_c4924cc6_name_0c494469_cls: + """ + Property to access Fb_FreqWord + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Bitrate NCO Frequency Control Word | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Set Modem Data Rate

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__Fb_FreqWord + + @property + def TX_F1_FreqWord(self) -> msk_top_regs_config_nco_fw_desc_94d7aaf5_name_84dd0c1c_cls: + """ + Property to access TX_F1_FreqWord + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Tx F1 NCO Frequency Control Word | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Set Modulator F1 Frequency

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__TX_F1_FreqWord + + @property + def TX_F2_FreqWord(self) -> msk_top_regs_config_nco_fw_desc_42134a4f_name_d97dbd51_cls: + """ + Property to access TX_F2_FreqWord + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Tx F2 NCO Frequency Control Word | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Set Modulator F2 Frequency

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__TX_F2_FreqWord + + @property + def RX_F1_FreqWord(self) -> msk_top_regs_config_nco_fw_desc_16fb48c8_name_8d01a20d_cls: + """ + Property to access RX_F1_FreqWord + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Rx F1 NCO Frequency Control Word | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Set Demodulator F1 Frequency

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__RX_F1_FreqWord + + @property + def RX_F2_FreqWord(self) -> msk_top_regs_config_nco_fw_desc_43c0828f_name_bdc60ecf_cls: + """ + Property to access RX_F2_FreqWord + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Rx F2 NCO Frequency Control Word | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Set Demodulator F2 Frequency

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__RX_F2_FreqWord + + @property + def LPF_Config_0(self) -> msk_top_regs_lpf_config_0_cls: + """ + Property to access LPF_Config_0 + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | PI Controller Configuration and Low-pass Filter Configuration | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Configure PI controller and low-pass filter

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__LPF_Config_0 + + @property + def LPF_Config_1(self) -> msk_top_regs_lpf_config_1_cls: + """ + Property to access LPF_Config_1 + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | PI Controller Configuration Configuration Register 1 | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Configures PI Controller I-gain and divisor

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__LPF_Config_1 + + @property + def Tx_Data_Width(self) -> msk_top_regs_data_width_desc_58c848dd_name_2fbd8eba_cls: + """ + Property to access Tx_Data_Width + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Modem Tx Input Data Width | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Set the parallel data width of the parallel-to-serial | + | | converter

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__Tx_Data_Width + + @property + def Rx_Data_Width(self) -> msk_top_regs_data_width_desc_6097df38_name_4609588b_cls: + """ + Property to access Rx_Data_Width + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Modem Rx Output Data Width | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Set the parallel data width of the serial-to-parallel | + | | converter

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__Rx_Data_Width + + @property + def PRBS_Control(self) -> msk_top_regs_prbs_ctrl_cls: + """ + Property to access PRBS_Control + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | PRBS Control 0 | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Configures operation of the PRBS Generator and Monitor

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__PRBS_Control + + @property + def PRBS_Initial_State(self) -> msk_top_regs_config_prbs_seed_cls: + """ + Property to access PRBS_Initial_State + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | PRBS Control 1 | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

PRBS Initial State

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__PRBS_Initial_State + + @property + def PRBS_Polynomial(self) -> msk_top_regs_config_prbs_poly_cls: + """ + Property to access PRBS_Polynomial + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | PRBS Control 2 | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

PRBS Polynomial

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__PRBS_Polynomial + + @property + def PRBS_Error_Mask(self) -> msk_top_regs_config_prbs_errmask_cls: + """ + Property to access PRBS_Error_Mask + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | PRBS Control 3 | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

PRBS Error Mask

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__PRBS_Error_Mask + + @property + def PRBS_Bit_Count(self) -> msk_top_regs_stat_32_bits_cls: + """ + Property to access PRBS_Bit_Count + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | PRBS Status 0 | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

PRBS Bits Received

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__PRBS_Bit_Count + + @property + def PRBS_Error_Count(self) -> msk_top_regs_stat_32_errs_cls: + """ + Property to access PRBS_Error_Count + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | PRBS Status 1 | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

PRBS Bit Errors

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__PRBS_Error_Count + + @property + def LPF_Accum_F1(self) -> msk_top_regs_stat_32_lpf_acc_desc_8cebc7dc_name_f20c6670_cls: + """ + Property to access LPF_Accum_F1 + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | F1 PI Controller Accumulator | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Value of the F1 PI Controller Accumulator

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__LPF_Accum_F1 + + @property + def LPF_Accum_F2(self) -> msk_top_regs_stat_32_lpf_acc_desc_dea6bd99_name_758fd0ce_cls: + """ + Property to access LPF_Accum_F2 + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | F2 PI Controller Accumulator | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Value of the F2 PI Controller Accumulator

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__LPF_Accum_F2 + + @property + def axis_xfer_count(self) -> msk_top_regs_msk_stat_3_cls: + """ + Property to access axis_xfer_count + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | MSK Modem Status 3 | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Modem status data

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__axis_xfer_count + + @property + def Rx_Sample_Discard(self) -> msk_top_regs_rx_sample_discard_cls: + """ + Property to access Rx_Sample_Discard + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Rx Sample Discard | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Configure samples discard operation for demodulator

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__Rx_Sample_Discard + + @property + def LPF_Config_2(self) -> msk_top_regs_lpf_config_2_cls: + """ + Property to access LPF_Config_2 + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | PI Controller Configuration Configuration Register 2 | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Configures PI Controller I-gain and divisor

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__LPF_Config_2 + + @property + def f1_nco_adjust(self) -> msk_top_regs_observation_data_data_0c017ef4_desc_64ff3689_name_d8ad3b25_cls: + """ + Property to access f1_nco_adjust + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | F1 NCO Frequency Adjust | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Frequency offet applied to the F1 NCO

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__f1_nco_adjust + + @property + def f2_nco_adjust(self) -> msk_top_regs_observation_data_data_0515efaa_desc_ebde6d39_name_2c154788_cls: + """ + Property to access f2_nco_adjust + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | F2 NCO Frequency Adjust | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Frequency offet applied to the F2 NCO

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__f2_nco_adjust + + @property + def f1_error(self) -> msk_top_regs_observation_data_data_25a21249_desc_417e1c96_name_3b640507_cls: + """ + Property to access f1_error + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | F1 Error Value | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Error value of the F1 Costas loop after each active bit | + | | period

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__f1_error + + @property + def f2_error(self) -> msk_top_regs_observation_data_data_272a00b6_desc_70869502_name_3de9a0d3_cls: + """ + Property to access f2_error + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | F2 Error Value | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Error value of the F2 Costas loop after each active bit | + | | period

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__f2_error + + @property + def Tx_Sync_Ctrl(self) -> msk_top_regs_tx_sync_ctrl_cls: + """ + Property to access Tx_Sync_Ctrl + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Transmitter Sync Control | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Provides control bits for generation of transmitter | + | | synchronization patterns

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__Tx_Sync_Ctrl + + @property + def Tx_Sync_Cnt(self) -> msk_top_regs_tx_sync_cnt_cls: + """ + Property to access Tx_Sync_Cnt + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Transmitter Sync Duration | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Sets the duration of the synchronization tones when enabled

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__Tx_Sync_Cnt + + @property + def lowpass_ema_alpha1(self) -> msk_top_regs_lowpass_ema_alpha_0x0x106a8591_cls: + """ + Property to access lowpass_ema_alpha1 + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Exponential Moving Average Alpha | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Sets the alpha for the EMA

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__lowpass_ema_alpha1 + + @property + def lowpass_ema_alpha2(self) -> msk_top_regs_lowpass_ema_alpha_cls: + """ + Property to access lowpass_ema_alpha2 + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Exponential Moving Average Alpha | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Sets the alpha for the EMA

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__lowpass_ema_alpha2 + + @property + def rx_power(self) -> msk_top_regs_rx_power_cls: + """ + Property to access rx_power + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Receive Power | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Receive power computed from I/Q ssamples

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__rx_power + + + + @property + def systemrdl_python_child_name_map(self) -> dict[str, str]: + """ + In some cases systemRDL names need to be converted make them python safe, this dictionary + is used to map the original systemRDL names to the names of the python attributes of this + class + + Returns: dictionary whose key is the systemRDL names and value it the property name + """ + return {'Hash_ID_Low':'Hash_ID_Low','Hash_ID_High':'Hash_ID_High','MSK_Init':'MSK_Init','MSK_Control':'MSK_Control','MSK_Status':'MSK_Status','Tx_Bit_Count':'Tx_Bit_Count','Tx_Enable_Count':'Tx_Enable_Count','Fb_FreqWord':'Fb_FreqWord','TX_F1_FreqWord':'TX_F1_FreqWord','TX_F2_FreqWord':'TX_F2_FreqWord','RX_F1_FreqWord':'RX_F1_FreqWord','RX_F2_FreqWord':'RX_F2_FreqWord','LPF_Config_0':'LPF_Config_0','LPF_Config_1':'LPF_Config_1','Tx_Data_Width':'Tx_Data_Width','Rx_Data_Width':'Rx_Data_Width','PRBS_Control':'PRBS_Control','PRBS_Initial_State':'PRBS_Initial_State','PRBS_Polynomial':'PRBS_Polynomial','PRBS_Error_Mask':'PRBS_Error_Mask','PRBS_Bit_Count':'PRBS_Bit_Count','PRBS_Error_Count':'PRBS_Error_Count','LPF_Accum_F1':'LPF_Accum_F1','LPF_Accum_F2':'LPF_Accum_F2','axis_xfer_count':'axis_xfer_count','Rx_Sample_Discard':'Rx_Sample_Discard','LPF_Config_2':'LPF_Config_2','f1_nco_adjust':'f1_nco_adjust','f2_nco_adjust':'f2_nco_adjust','f1_error':'f1_error','f2_error':'f2_error','Tx_Sync_Ctrl':'Tx_Sync_Ctrl','Tx_Sync_Cnt':'Tx_Sync_Cnt','lowpass_ema_alpha1':'lowpass_ema_alpha1','lowpass_ema_alpha2':'lowpass_ema_alpha2','rx_power':'rx_power', + } + + + + + + + + # nodes:36 + + @overload + def get_child_by_system_rdl_name(self, name: Literal["Hash_ID_Low"]) -> msk_top_regs_msk_hash_lo_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["Hash_ID_High"]) -> msk_top_regs_msk_hash_hi_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["MSK_Init"]) -> msk_top_regs_msk_init_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["MSK_Control"]) -> msk_top_regs_msk_ctrl_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["MSK_Status"]) -> msk_top_regs_msk_stat_0_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["Tx_Bit_Count"]) -> msk_top_regs_msk_stat_1_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["Tx_Enable_Count"]) -> msk_top_regs_msk_stat_2_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["Fb_FreqWord"]) -> msk_top_regs_config_nco_fw_desc_c4924cc6_name_0c494469_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["TX_F1_FreqWord"]) -> msk_top_regs_config_nco_fw_desc_94d7aaf5_name_84dd0c1c_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["TX_F2_FreqWord"]) -> msk_top_regs_config_nco_fw_desc_42134a4f_name_d97dbd51_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["RX_F1_FreqWord"]) -> msk_top_regs_config_nco_fw_desc_16fb48c8_name_8d01a20d_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["RX_F2_FreqWord"]) -> msk_top_regs_config_nco_fw_desc_43c0828f_name_bdc60ecf_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["LPF_Config_0"]) -> msk_top_regs_lpf_config_0_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["LPF_Config_1"]) -> msk_top_regs_lpf_config_1_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["Tx_Data_Width"]) -> msk_top_regs_data_width_desc_58c848dd_name_2fbd8eba_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["Rx_Data_Width"]) -> msk_top_regs_data_width_desc_6097df38_name_4609588b_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["PRBS_Control"]) -> msk_top_regs_prbs_ctrl_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["PRBS_Initial_State"]) -> msk_top_regs_config_prbs_seed_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["PRBS_Polynomial"]) -> msk_top_regs_config_prbs_poly_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["PRBS_Error_Mask"]) -> msk_top_regs_config_prbs_errmask_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["PRBS_Bit_Count"]) -> msk_top_regs_stat_32_bits_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["PRBS_Error_Count"]) -> msk_top_regs_stat_32_errs_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["LPF_Accum_F1"]) -> msk_top_regs_stat_32_lpf_acc_desc_8cebc7dc_name_f20c6670_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["LPF_Accum_F2"]) -> msk_top_regs_stat_32_lpf_acc_desc_dea6bd99_name_758fd0ce_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["axis_xfer_count"]) -> msk_top_regs_msk_stat_3_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["Rx_Sample_Discard"]) -> msk_top_regs_rx_sample_discard_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["LPF_Config_2"]) -> msk_top_regs_lpf_config_2_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["f1_nco_adjust"]) -> msk_top_regs_observation_data_data_0c017ef4_desc_64ff3689_name_d8ad3b25_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["f2_nco_adjust"]) -> msk_top_regs_observation_data_data_0515efaa_desc_ebde6d39_name_2c154788_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["f1_error"]) -> msk_top_regs_observation_data_data_25a21249_desc_417e1c96_name_3b640507_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["f2_error"]) -> msk_top_regs_observation_data_data_272a00b6_desc_70869502_name_3de9a0d3_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["Tx_Sync_Ctrl"]) -> msk_top_regs_tx_sync_ctrl_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["Tx_Sync_Cnt"]) -> msk_top_regs_tx_sync_cnt_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["lowpass_ema_alpha1"]) -> msk_top_regs_lowpass_ema_alpha_0x0x106a8591_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["lowpass_ema_alpha2"]) -> msk_top_regs_lowpass_ema_alpha_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["rx_power"]) -> msk_top_regs_rx_power_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: str) -> Union[msk_top_regs_msk_hash_lo_cls, msk_top_regs_msk_hash_hi_cls, msk_top_regs_msk_init_cls, msk_top_regs_msk_ctrl_cls, msk_top_regs_msk_stat_0_cls, msk_top_regs_msk_stat_1_cls, msk_top_regs_msk_stat_2_cls, msk_top_regs_config_nco_fw_desc_c4924cc6_name_0c494469_cls, msk_top_regs_config_nco_fw_desc_94d7aaf5_name_84dd0c1c_cls, msk_top_regs_config_nco_fw_desc_42134a4f_name_d97dbd51_cls, msk_top_regs_config_nco_fw_desc_16fb48c8_name_8d01a20d_cls, msk_top_regs_config_nco_fw_desc_43c0828f_name_bdc60ecf_cls, msk_top_regs_lpf_config_0_cls, msk_top_regs_lpf_config_1_cls, msk_top_regs_data_width_desc_58c848dd_name_2fbd8eba_cls, msk_top_regs_data_width_desc_6097df38_name_4609588b_cls, msk_top_regs_prbs_ctrl_cls, msk_top_regs_config_prbs_seed_cls, msk_top_regs_config_prbs_poly_cls, msk_top_regs_config_prbs_errmask_cls, msk_top_regs_stat_32_bits_cls, msk_top_regs_stat_32_errs_cls, msk_top_regs_stat_32_lpf_acc_desc_8cebc7dc_name_f20c6670_cls, msk_top_regs_stat_32_lpf_acc_desc_dea6bd99_name_758fd0ce_cls, msk_top_regs_msk_stat_3_cls, msk_top_regs_rx_sample_discard_cls, msk_top_regs_lpf_config_2_cls, msk_top_regs_observation_data_data_0c017ef4_desc_64ff3689_name_d8ad3b25_cls, msk_top_regs_observation_data_data_0515efaa_desc_ebde6d39_name_2c154788_cls, msk_top_regs_observation_data_data_25a21249_desc_417e1c96_name_3b640507_cls, msk_top_regs_observation_data_data_272a00b6_desc_70869502_name_3de9a0d3_cls, msk_top_regs_tx_sync_ctrl_cls, msk_top_regs_tx_sync_cnt_cls, msk_top_regs_lowpass_ema_alpha_0x0x106a8591_cls, msk_top_regs_lowpass_ema_alpha_cls, msk_top_regs_rx_power_cls, ]: ... + + def get_child_by_system_rdl_name(self, name: Any) -> Any: + return super().get_child_by_system_rdl_name(name) + + + + + + + + + @property + def rdl_name(self) -> str: + return "Pluto MSK Registers" + @property + def rdl_desc(self) -> str: + return "MSK Modem Configuration and Status Registers" + + + + + def get_registers(self, unroll:bool=False) -> Iterator[Union[AsyncReg, AsyncRegArray]]: + """ + generator that produces all the registers of this node + """ + + + yield self.Hash_ID_Low + + + yield self.Hash_ID_High + + + yield self.MSK_Init + + + yield self.MSK_Control + + + yield self.MSK_Status + + + yield self.Tx_Bit_Count + + + yield self.Tx_Enable_Count + + + yield self.Fb_FreqWord + + + yield self.TX_F1_FreqWord + + + yield self.TX_F2_FreqWord + + + yield self.RX_F1_FreqWord + + + yield self.RX_F2_FreqWord + + + yield self.LPF_Config_0 + + + yield self.LPF_Config_1 + + + yield self.Tx_Data_Width + + + yield self.Rx_Data_Width + + + yield self.PRBS_Control + + + yield self.PRBS_Initial_State + + + yield self.PRBS_Polynomial + + + yield self.PRBS_Error_Mask + + + yield self.PRBS_Bit_Count + + + yield self.PRBS_Error_Count + + + yield self.LPF_Accum_F1 + + + yield self.LPF_Accum_F2 + + + yield self.axis_xfer_count + + + yield self.Rx_Sample_Discard + + + yield self.LPF_Config_2 + + + yield self.f1_nco_adjust + + + yield self.f2_nco_adjust + + + yield self.f1_error + + + yield self.f2_error + + + yield self.Tx_Sync_Ctrl + + + yield self.Tx_Sync_Cnt + + + yield self.lowpass_ema_alpha1 + + + yield self.lowpass_ema_alpha2 + + + yield self.rx_power + + + # Empty generator in case there are no children of this type + if False: yield + + + def get_sections(self, unroll:bool=False) -> Iterator[Union[AsyncAddressMap, AsyncRegFile, AsyncAddressMapArray, AsyncRegFileArray]]: + """ + generator that produces all the AsyncAddressMap, AsyncRegFile, AsyncAddressMapArray, AsyncRegFileArray children of this node + """ + + + # Empty generator in case there are no children of this type + if False: yield + + def get_memories(self, unroll:bool=False) -> Iterator[Union[AsyncMemory, AsyncMemoryArray]]: + """ + generator that produces all the AsyncMemory, AsyncMemoryArray children of this node + """ + + + # Empty generator in case there are no children of this type + if False: yield + + + + + +if __name__ == '__main__': + # dummy functions to demonstrate the class + async def read_addr_space(addr: int, width: int, accesswidth: int) -> int: + """ + Callback to simulate the operation of the package, everytime the read is called, it will + request the user input the value to be read back. + + Args: + addr: Address to write to + width: Width of the register in bits + accesswidth: Minimum access width of the register in bits + + Returns: + value inputted by the used + """ + assert isinstance(addr, int) + assert isinstance(width, int) + assert isinstance(accesswidth, int) + return int(input('value to read from address:0x%X'%addr)) + + async def write_addr_space(addr: int, width: int, accesswidth: int, data: int) -> None: + """ + Callback to simulate the operation of the package, everytime the read is called, it will + request the user input the value to be read back. + + Args: + addr: Address to write to + width: Width of the register in bits + accesswidth: Minimum access width of the register in bits + data: value to be written to the register + + Returns: + None + """ + assert isinstance(addr, int) + assert isinstance(width, int) + assert isinstance(accesswidth, int) + assert isinstance(data, int) + print('write data:0x%X to address:0x%X'%(data, addr)) + + # create an instance of the class + msk_top_regs = msk_top_regs_cls(callbacks = AsyncCallbackSet(read_callback=read_addr_space, + write_callback=write_addr_space)) \ No newline at end of file diff --git a/rdl/outputs/python/msk_top_regs/sim/__init__.py b/rdl/outputs/python/msk_top_regs/sim/__init__.py new file mode 100644 index 0000000..2ae2839 --- /dev/null +++ b/rdl/outputs/python/msk_top_regs/sim/__init__.py @@ -0,0 +1 @@ +pass diff --git a/rdl/outputs/python/msk_top_regs/sim/msk_top_regs.py b/rdl/outputs/python/msk_top_regs/sim/msk_top_regs.py new file mode 100644 index 0000000..95e0aa1 --- /dev/null +++ b/rdl/outputs/python/msk_top_regs/sim/msk_top_regs.py @@ -0,0 +1,175 @@ + + + +""" +Python Wrapper for the msk_top_regs register model + +This code was generated from the PeakRDL-python package version 1.4.0 + +""" + +from typing import Union + +from ..sim_lib.register import Register, MemoryRegister +from ..sim_lib.memory import Memory +from ..sim_lib.simulator import MemoryEntry +from ..sim_lib.field import FieldDefinition +from ..sim_lib.simulator import AsyncSimulator as Simulator + + +class msk_top_regs_simulator_cls(Simulator): + + def _build_registers(self) -> dict[int, Union[list[Union[MemoryRegister, Register]], Union[MemoryRegister, Register]]]: + return { + 0 : + Register(width=32, full_inst_name='msk_top_regs.Hash_ID_Low', readable=True, writable=False, + fields=[FieldDefinition(high=31, low=0, msb=31, lsb=0, inst_name='hash_id_lo'), + ]), + 4 : + Register(width=32, full_inst_name='msk_top_regs.Hash_ID_High', readable=True, writable=False, + fields=[FieldDefinition(high=31, low=0, msb=31, lsb=0, inst_name='hash_id_hi'), + ]), + 8 : + Register(width=32, full_inst_name='msk_top_regs.MSK_Init', readable=True, writable=True, + fields=[FieldDefinition(high=0, low=0, msb=0, lsb=0, inst_name='txrxinit'),FieldDefinition(high=1, low=1, msb=1, lsb=1, inst_name='txinit'),FieldDefinition(high=2, low=2, msb=2, lsb=2, inst_name='rxinit'), + ]), + 12 : + Register(width=32, full_inst_name='msk_top_regs.MSK_Control', readable=True, writable=True, + fields=[FieldDefinition(high=0, low=0, msb=0, lsb=0, inst_name='ptt'),FieldDefinition(high=1, low=1, msb=1, lsb=1, inst_name='loopback_ena'),FieldDefinition(high=2, low=2, msb=2, lsb=2, inst_name='rx_invert'),FieldDefinition(high=3, low=3, msb=3, lsb=3, inst_name='clear_counts'),FieldDefinition(high=4, low=4, msb=4, lsb=4, inst_name='diff_encoder_loopback'), + ]), + 16 : + Register(width=32, full_inst_name='msk_top_regs.MSK_Status', readable=True, writable=False, + fields=[FieldDefinition(high=0, low=0, msb=0, lsb=0, inst_name='demod_sync_lock'),FieldDefinition(high=1, low=1, msb=1, lsb=1, inst_name='tx_enable'),FieldDefinition(high=2, low=2, msb=2, lsb=2, inst_name='rx_enable'),FieldDefinition(high=3, low=3, msb=3, lsb=3, inst_name='tx_axis_valid'), + ]), + 20 : + Register(width=32, full_inst_name='msk_top_regs.Tx_Bit_Count', readable=True, writable=False, + fields=[FieldDefinition(high=31, low=0, msb=31, lsb=0, inst_name='tx_bit_counter'), + ]), + 24 : + Register(width=32, full_inst_name='msk_top_regs.Tx_Enable_Count', readable=True, writable=False, + fields=[FieldDefinition(high=31, low=0, msb=31, lsb=0, inst_name='tx_ena_counter'), + ]), + 28 : + Register(width=32, full_inst_name='msk_top_regs.Fb_FreqWord', readable=True, writable=True, + fields=[FieldDefinition(high=31, low=0, msb=31, lsb=0, inst_name='config_data'), + ]), + 32 : + Register(width=32, full_inst_name='msk_top_regs.TX_F1_FreqWord', readable=True, writable=True, + fields=[FieldDefinition(high=31, low=0, msb=31, lsb=0, inst_name='config_data'), + ]), + 36 : + Register(width=32, full_inst_name='msk_top_regs.TX_F2_FreqWord', readable=True, writable=True, + fields=[FieldDefinition(high=31, low=0, msb=31, lsb=0, inst_name='config_data'), + ]), + 40 : + Register(width=32, full_inst_name='msk_top_regs.RX_F1_FreqWord', readable=True, writable=True, + fields=[FieldDefinition(high=31, low=0, msb=31, lsb=0, inst_name='config_data'), + ]), + 44 : + Register(width=32, full_inst_name='msk_top_regs.RX_F2_FreqWord', readable=True, writable=True, + fields=[FieldDefinition(high=31, low=0, msb=31, lsb=0, inst_name='config_data'), + ]), + 48 : + Register(width=32, full_inst_name='msk_top_regs.LPF_Config_0', readable=True, writable=True, + fields=[FieldDefinition(high=0, low=0, msb=0, lsb=0, inst_name='lpf_freeze'),FieldDefinition(high=1, low=1, msb=1, lsb=1, inst_name='lpf_zero'),FieldDefinition(high=7, low=2, msb=7, lsb=2, inst_name='prbs_reserved'),FieldDefinition(high=31, low=8, msb=31, lsb=8, inst_name='lpf_alpha'), + ]), + 52 : + Register(width=32, full_inst_name='msk_top_regs.LPF_Config_1', readable=True, writable=True, + fields=[FieldDefinition(high=23, low=0, msb=23, lsb=0, inst_name='i_gain'),FieldDefinition(high=31, low=24, msb=31, lsb=24, inst_name='i_shift'), + ]), + 56 : + Register(width=32, full_inst_name='msk_top_regs.Tx_Data_Width', readable=True, writable=True, + fields=[FieldDefinition(high=7, low=0, msb=7, lsb=0, inst_name='data_width'), + ]), + 60 : + Register(width=32, full_inst_name='msk_top_regs.Rx_Data_Width', readable=True, writable=True, + fields=[FieldDefinition(high=7, low=0, msb=7, lsb=0, inst_name='data_width'), + ]), + 64 : + Register(width=32, full_inst_name='msk_top_regs.PRBS_Control', readable=True, writable=True, + fields=[FieldDefinition(high=0, low=0, msb=0, lsb=0, inst_name='prbs_sel'),FieldDefinition(high=1, low=1, msb=1, lsb=1, inst_name='prbs_error_insert'),FieldDefinition(high=2, low=2, msb=2, lsb=2, inst_name='prbs_clear'),FieldDefinition(high=3, low=3, msb=3, lsb=3, inst_name='prbs_manual_sync'),FieldDefinition(high=15, low=4, msb=15, lsb=4, inst_name='prbs_reserved'),FieldDefinition(high=31, low=16, msb=31, lsb=16, inst_name='prbs_sync_threshold'), + ]), + 68 : + Register(width=32, full_inst_name='msk_top_regs.PRBS_Initial_State', readable=True, writable=True, + fields=[FieldDefinition(high=31, low=0, msb=31, lsb=0, inst_name='config_data'), + ]), + 72 : + Register(width=32, full_inst_name='msk_top_regs.PRBS_Polynomial', readable=True, writable=True, + fields=[FieldDefinition(high=31, low=0, msb=31, lsb=0, inst_name='config_data'), + ]), + 76 : + Register(width=32, full_inst_name='msk_top_regs.PRBS_Error_Mask', readable=True, writable=True, + fields=[FieldDefinition(high=31, low=0, msb=31, lsb=0, inst_name='config_data'), + ]), + 80 : + Register(width=32, full_inst_name='msk_top_regs.PRBS_Bit_Count', readable=True, writable=False, + fields=[FieldDefinition(high=31, low=0, msb=31, lsb=0, inst_name='status_data'), + ]), + 84 : + Register(width=32, full_inst_name='msk_top_regs.PRBS_Error_Count', readable=True, writable=False, + fields=[FieldDefinition(high=31, low=0, msb=31, lsb=0, inst_name='status_data'), + ]), + 88 : + Register(width=32, full_inst_name='msk_top_regs.LPF_Accum_F1', readable=True, writable=False, + fields=[FieldDefinition(high=31, low=0, msb=31, lsb=0, inst_name='status_data'), + ]), + 92 : + Register(width=32, full_inst_name='msk_top_regs.LPF_Accum_F2', readable=True, writable=False, + fields=[FieldDefinition(high=31, low=0, msb=31, lsb=0, inst_name='status_data'), + ]), + 96 : + Register(width=32, full_inst_name='msk_top_regs.axis_xfer_count', readable=True, writable=False, + fields=[FieldDefinition(high=31, low=0, msb=31, lsb=0, inst_name='xfer_count'), + ]), + 100 : + Register(width=32, full_inst_name='msk_top_regs.Rx_Sample_Discard', readable=True, writable=True, + fields=[FieldDefinition(high=7, low=0, msb=7, lsb=0, inst_name='rx_sample_discard'),FieldDefinition(high=15, low=8, msb=15, lsb=8, inst_name='rx_nco_discard'), + ]), + 104 : + Register(width=32, full_inst_name='msk_top_regs.LPF_Config_2', readable=True, writable=True, + fields=[FieldDefinition(high=23, low=0, msb=23, lsb=0, inst_name='p_gain'),FieldDefinition(high=31, low=24, msb=31, lsb=24, inst_name='p_shift'), + ]), + 108 : + Register(width=32, full_inst_name='msk_top_regs.f1_nco_adjust', readable=True, writable=False, + fields=[FieldDefinition(high=31, low=0, msb=31, lsb=0, inst_name='data'), + ]), + 112 : + Register(width=32, full_inst_name='msk_top_regs.f2_nco_adjust', readable=True, writable=False, + fields=[FieldDefinition(high=31, low=0, msb=31, lsb=0, inst_name='data'), + ]), + 116 : + Register(width=32, full_inst_name='msk_top_regs.f1_error', readable=True, writable=False, + fields=[FieldDefinition(high=31, low=0, msb=31, lsb=0, inst_name='data'), + ]), + 120 : + Register(width=32, full_inst_name='msk_top_regs.f2_error', readable=True, writable=False, + fields=[FieldDefinition(high=31, low=0, msb=31, lsb=0, inst_name='data'), + ]), + 124 : + Register(width=32, full_inst_name='msk_top_regs.Tx_Sync_Ctrl', readable=True, writable=True, + fields=[FieldDefinition(high=0, low=0, msb=0, lsb=0, inst_name='tx_sync_ena'),FieldDefinition(high=1, low=1, msb=1, lsb=1, inst_name='tx_sync_force'),FieldDefinition(high=2, low=2, msb=2, lsb=2, inst_name='tx_sync_f1'),FieldDefinition(high=3, low=3, msb=3, lsb=3, inst_name='tx_sync_f2'), + ]), + 128 : + Register(width=32, full_inst_name='msk_top_regs.Tx_Sync_Cnt', readable=True, writable=True, + fields=[FieldDefinition(high=23, low=0, msb=23, lsb=0, inst_name='tx_sync_cnt'), + ]), + 132 : + Register(width=32, full_inst_name='msk_top_regs.lowpass_ema_alpha1', readable=True, writable=True, + fields=[FieldDefinition(high=17, low=0, msb=17, lsb=0, inst_name='alpha'), + ]), + 136 : + Register(width=32, full_inst_name='msk_top_regs.lowpass_ema_alpha2', readable=True, writable=True, + fields=[FieldDefinition(high=17, low=0, msb=17, lsb=0, inst_name='alpha'), + ]), + 140 : + Register(width=32, full_inst_name='msk_top_regs.rx_power', readable=True, writable=False, + fields=[FieldDefinition(high=22, low=0, msb=22, lsb=0, inst_name='rx_power'), + ]), + } + + def _build_memories(self) -> list[MemoryEntry]: + return [ + ] + +if __name__ == '__main__': + pass diff --git a/rdl/cocotb/desyrdl/__init__.py b/rdl/outputs/python/msk_top_regs/sim_lib/__init__.py similarity index 100% rename from rdl/cocotb/desyrdl/__init__.py rename to rdl/outputs/python/msk_top_regs/sim_lib/__init__.py diff --git a/rdl/outputs/python/msk_top_regs/sim_lib/_callbacks.py b/rdl/outputs/python/msk_top_regs/sim_lib/_callbacks.py new file mode 100644 index 0000000..e294617 --- /dev/null +++ b/rdl/outputs/python/msk_top_regs/sim_lib/_callbacks.py @@ -0,0 +1,79 @@ +""" +peakrdl-python is a tool to generate Python Register Access Layer (RAL) from SystemRDL +Copyright (C) 2021 - 2023 + +This program is free software: you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation, either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . + +This module is intended to distributed as part of automatically generated code by the +peakrdl-python tool. It provides a set of types used by the autogenerated code to callbacks +""" +from typing import Protocol + + +class RegisterReadCallback(Protocol): + """ + Callback definition software read to a field, register or memory + """ + + # pylint: disable=too-few-public-methods + def __call__(self, value: int) -> None: + pass + + +class RegisterWriteCallback(Protocol): + """ + Callback definition software write to a field, register or memory + """ + + # pylint: disable=too-few-public-methods + def __call__(self, value: int) -> None: + pass + +class FieldReadCallback(Protocol): + """ + Callback definition software read to a field, register or memory + """ + + # pylint: disable=too-few-public-methods + def __call__(self, value: int) -> None: + pass + + +class FieldWriteCallback(Protocol): + """ + Callback definition software write to a field, register or memory + """ + + # pylint: disable=too-few-public-methods + def __call__(self, value: int) -> None: + pass + +class MemoryReadCallback(Protocol): + """ + Callback definition software read to a field, register or memory + """ + + # pylint: disable=too-few-public-methods + def __call__(self, offset: int, value: int) -> None: + pass + + +class MemoryWriteCallback(Protocol): + """ + Callback definition software write to a field, register or memory + """ + + # pylint: disable=too-few-public-methods + def __call__(self, offset: int, value: int) -> None: + pass diff --git a/rdl/outputs/python/msk_top_regs/sim_lib/base.py b/rdl/outputs/python/msk_top_regs/sim_lib/base.py new file mode 100644 index 0000000..22077ad --- /dev/null +++ b/rdl/outputs/python/msk_top_regs/sim_lib/base.py @@ -0,0 +1,34 @@ +""" +peakrdl-python is a tool to generate Python Register Access Layer (RAL) from SystemRDL +Copyright (C) 2021 - 2023 + +This program is free software: you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation, either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . + +This module is intended to distributed as part of automatically generated code by the +peakrdl-python tool. It provides a set of base classes used by the autogenerated code +""" +from abc import ABC + + +# pylint: disable=too-few-public-methods +class Base(ABC): + """ + base class for the simulator nodes + """ + + __slots__ = ['full_inst_name'] + + def __init__(self, *, + full_inst_name: str): + self.full_inst_name = full_inst_name diff --git a/rdl/outputs/python/msk_top_regs/sim_lib/dummy_callbacks.py b/rdl/outputs/python/msk_top_regs/sim_lib/dummy_callbacks.py new file mode 100644 index 0000000..07215a8 --- /dev/null +++ b/rdl/outputs/python/msk_top_regs/sim_lib/dummy_callbacks.py @@ -0,0 +1,256 @@ +""" +peakrdl-python is a tool to generate Python Register Access Layer (RAL) from SystemRDL +Copyright (C) 2021 - 2023 + +This program is free software: you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation, either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . + +This module provides a set of "dummy" callbacks that provide the most basic of operations +""" +from array import array as Array +import asyncio + +from ..lib.utility_functions import get_array_typecode + +# many of the functions in this file do not use all the arguments, this is because they are stub +# functions +# pylint: disable=unused-argument + + +def dummy_read(addr: int, width: int, accesswidth: int) -> int: + """ + Callback to simulate the operation of the package, everytime the read is called, it return + an integer value of 0 + + Args: + addr: Address to write to + width: Width of the register in bits + accesswidth: Minimum access width of the register in bits + + Returns: + value inputted by the used + """ + return int(0) + + +def dummy_write(addr: int, width: int, accesswidth: int, data: int) -> None: + """ + Callback to simulate the operation of the package, everytime the write is called, it will + print the content + + Args: + addr: Address to write to + width: Width of the register in bits + accesswidth: Minimum access width of the register in bits + data: value to be written to the register + + Returns: + None + """ + # pylint: disable-next=bad-builtin + print(f'0x{data:X} written to 0x{addr:X}') + + +def dummy_read_block(addr: int, width: int, accesswidth: int, length:int) -> list[int]: + """ + Callback to simulate the operation of the package, everytime the read_block is called, it + return an integer value of array of o's + + Args: + addr: Address to write to + width: Width of the register in bits + accesswidth: Minimum access width of the register in bits + length: number of array entries + + Returns: + an array with the correct type (based on width) populated with 0's + + """ + return [0 for x in range(length)] + + +def dummy_read_block_legacy(addr: int, width: int, accesswidth: int, length:int) -> Array: + """ + Callback to simulate the operation of the package, everytime the read_block is called, it + return an integer value of array of o's + + Args: + addr: Address to write to + width: Width of the register in bits + accesswidth: Minimum access width of the register in bits + length: number of array entries + + Returns: + an list with the correct type (based on width) populated with 0's + + """ + return Array(get_array_typecode(width=width), [0 for x in range(length)]) + + +def dummy_write_block(addr: int, width: int, accesswidth: int, data: list[int]) -> None: + """ + Callback to simulate the operation of the package, everytime the read_block is called, it + return an integer value of array of o's + + Args: + addr: Address to write to + width: Width of the register in bits + accesswidth: Minimum access width of the register in bits + data: number of array entries + + Returns: + None + + """ + # pylint: disable=unnecessary-pass + pass + + +def dummy_write_block_legacy(addr: int, width: int, accesswidth: int, data: Array) -> None: + """ + Callback to simulate the operation of the package, everytime the read_block is called, it + return an integer value of array of o's + + Args: + addr: Address to write to + width: Width of the register in bits + accesswidth: Minimum access width of the register in bits + data: number of array entries + + Returns: + None + + """ + # pylint: disable=unnecessary-pass + pass + + +async def async_dummy_read(addr: int, width: int, accesswidth: int) -> int: + """ + async Callback to simulate the operation of the package, everytime the read is called, it + return an integer value of 0 + + Args: + addr: Address to write to + width: Width of the register in bits + accesswidth: Minimum access width of the register in bits + + Returns: + value inputted by the used + """ + await asyncio.sleep(0) + return dummy_read(addr, width, accesswidth) + + +async def async_dummy_write(addr: int, width: int, accesswidth: int, data: int) -> None: + """ + Callback to simulate the operation of the package, everytime the write is called, it will + print the content + + Args: + addr: Address to write to + width: Width of the register in bits + accesswidth: Minimum access width of the register in bits + data: value to be written to the register + + Returns: + None + """ + await asyncio.sleep(0) + return dummy_write(addr, width, accesswidth, data) + + +async def async_dummy_read_block(addr: int, + width: int, + accesswidth: int, + length: int) -> list[int]: + """ + Callback to simulate the operation of the package, everytime the read_block is called, it + return an integer value of array of o's + + Args: + addr: Address to write to + width: Width of the register in bits + accesswidth: Minimum access width of the register in bits + length: number of array entries + + Returns: + an array with the correct type (based on width) populated with 0's + + """ + await asyncio.sleep(0) + return dummy_read_block(addr, width, accesswidth, length) + + +async def async_dummy_read_block_legacy(addr: int, + width: int, + accesswidth: int, + length: int) -> Array: + """ + Callback to simulate the operation of the package, everytime the read_block is called, it + return an integer value of array of o's + + Args: + addr: Address to write to + width: Width of the register in bits + accesswidth: Minimum access width of the register in bits + length: number of array entries + + Returns: + an List with the correct type (based on width) populated with 0's + + """ + await asyncio.sleep(0) + return dummy_read_block_legacy(addr, width, accesswidth, length) + + +async def async_dummy_write_block(addr: int, + width: int, + accesswidth: int, data: list[int]) -> None: + """ + Callback to simulate the operation of the package, everytime the read_block is called, it + return an integer value of array of o's + + Args: + addr: Address to write to + width: Width of the register in bits + accesswidth: Minimum access width of the register in bits + data: number of array entries + + Returns: + None + + """ + await asyncio.sleep(0) + return dummy_write_block(addr, width, accesswidth, data) + + +async def async_dummy_write_block_legacy(addr: int, + width: int, + accesswidth: int, data: Array) -> None: + """ + Callback to simulate the operation of the package, everytime the read_block is called, it + return an integer value of array of o's + + Args: + addr: Address to write to + width: Width of the register in bits + accesswidth: Minimum access width of the register in bits + data: number of array entries + + Returns: + None + + """ + await asyncio.sleep(0) + return dummy_write_block_legacy(addr, width, accesswidth, data) diff --git a/rdl/outputs/python/msk_top_regs/sim_lib/field.py b/rdl/outputs/python/msk_top_regs/sim_lib/field.py new file mode 100644 index 0000000..2516905 --- /dev/null +++ b/rdl/outputs/python/msk_top_regs/sim_lib/field.py @@ -0,0 +1,154 @@ +""" +peakrdl-python is a tool to generate Python Register Access Layer (RAL) from SystemRDL +Copyright (C) 2021 - 2023 + +This program is free software: you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation, either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . + +This module is intended to distributed as part of automatically generated code by the +peakrdl-python tool. It provides a set of base classes used by the autogenerated code +""" +from dataclasses import dataclass +from typing import TYPE_CHECKING +from typing import Optional + +from ..lib.utility_functions import swap_msb_lsb_ordering + +from ._callbacks import FieldReadCallback, FieldWriteCallback + +from .base import Base + +if TYPE_CHECKING: + from .register import BaseRegister + +# pylint: disable=too-many-instance-attributes,too-many-arguments + + +@dataclass +class FieldDefinition: + """ + Class for an entry in the list of memories in the simulator + """ + high: int + low: int + msb: int + lsb: int + inst_name: str + +class Field(Base): + """ + class for all fields + + Note: + It is not expected that this class will be instantiated under normal + circumstances however, it is useful for type checking + """ + + __slots__ = ['__high', '__low', '__msb', '__lsb', + '__bitmask', '__inverse_bitmask', + '__msb0', '__lsb0', + '__parent_register','__parent_width', + '__read_callback', '__write_callback'] + + def __init__(self, *, low: int, high: int, msb: int, lsb: int, + parent_register: 'BaseRegister', parent_width: int, inst_name: str): + + super().__init__(full_inst_name=parent_register.full_inst_name + '.' + inst_name) + + self.__low = low + self.__high = high + + # there are a couple of properties that have been included because they may be needed in + # the future but are currently unused + # pylint: disable=unused-private-member + self.__lsb = lsb + self.__msb = msb + + if (msb == high) and (lsb == low): + self.__lsb0 = True + self.__msb0 = False + elif (msb == low) and (lsb == high): + self.__lsb0 = False + self.__msb0 = True + else: + raise ValueError('msb/lsb are inconsistent with low/high') + # pylint: enable=unused-private-member + + self.__parent_register = parent_register + self.__parent_width = parent_width + + self.__bitmask = 0 + for bit_position in range(low, high+1): + self.__bitmask |= (1 << bit_position) + + parent_max_value = (2 ** parent_width) - 1 + self.__inverse_bitmask = parent_max_value ^ self.__bitmask + + self.__read_callback: Optional[FieldReadCallback] = None + self.__write_callback: Optional[FieldWriteCallback] = None + + @property + def read_callback(self) -> Optional[FieldReadCallback]: + """ + Callback made during each read operation + """ + return self.__read_callback + + @read_callback.setter + def read_callback(self, callback: Optional[FieldReadCallback]) -> None: + self.__read_callback = callback + + @property + def write_callback(self) -> Optional[FieldWriteCallback]: + """ + Callback made during each write operation + """ + return self.__write_callback + + @write_callback.setter + def write_callback(self, callback: Optional[FieldWriteCallback]) -> None: + self.__write_callback = callback + + @property + def __width(self) -> int: + return self.__high - self.__low + 1 + + @property + def value(self) -> int: + """ + Access the register value without triggering the callbacks + """ + + reg_value = self.__parent_register.value + + if self.__msb0: + return swap_msb_lsb_ordering(value=(reg_value & self.__bitmask) >> self.__low, + width=self.__width) + + return (reg_value & self.__bitmask) >> self.__low + + @value.setter + def value(self, value: int) -> None: + + if self.__msb0: + value = swap_msb_lsb_ordering(value=value, width=self.__width) + + if (self.__high == (self.__parent_width - 1)) and (self.__low == 0): + # special case where the field occupies the whole register, + # there a straight write can be performed + self.__parent_register.value = value + else: + # do a read, modify write + reg_value = self.__parent_register.read() + self.__parent_register.value = (reg_value & self.__inverse_bitmask) | \ + (value << self.__low) diff --git a/rdl/outputs/python/msk_top_regs/sim_lib/memory.py b/rdl/outputs/python/msk_top_regs/sim_lib/memory.py new file mode 100644 index 0000000..209f0ca --- /dev/null +++ b/rdl/outputs/python/msk_top_regs/sim_lib/memory.py @@ -0,0 +1,159 @@ +""" +peakrdl-python is a tool to generate Python Register Access Layer (RAL) from SystemRDL +Copyright (C) 2021 - 2023 + +This program is free software: you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation, either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . + +This module is intended to distributed as part of automatically generated code by the +peakrdl-python tool. It provides a set of base classes used by the autogenerated code +""" +from typing import Optional + +from .base import Base +from ._callbacks import MemoryReadCallback, MemoryWriteCallback + + +class _MemoryContent: + + __slots__ = ['__value', '__default_value', '__length'] + + def __init__(self, *, + default_value: int): + self.__value:dict[int, int] = {} + self.__default_value = default_value + + def __getitem__(self, item: int) -> int: + if item in self.__value: + return self.__value[item] + + return self.__default_value + + def __setitem__(self, key: int, value: int) -> None: + self.__value[key] = value + + +class Memory(Base): + """ + Simulation of a memory, this is implemented using a sparse approach to avoid the simulator + storing every possible entry in a register map, which could be very big. + """ + __slots__ = ['__value', '__width', '__length', + '__read_callback', '__write_callback'] + + def __init__(self, *, + width: int, + length: int, + default_value: int, + full_inst_name: str): + + super().__init__(full_inst_name=full_inst_name) + + self.__value = _MemoryContent(default_value=default_value) + self.__width = width + self.__length = length + self.__read_callback: Optional[MemoryReadCallback] = None + self.__write_callback: Optional[MemoryWriteCallback] = None + + @property + def read_callback(self) -> Optional[MemoryReadCallback]: + """ + Callback made during each read operation + """ + return self.__read_callback + + @read_callback.setter + def read_callback(self, callback: Optional[MemoryReadCallback]) -> None: + self.__read_callback = callback + + @property + def write_callback(self) -> Optional[MemoryWriteCallback]: + """ + Callback made during each write operation + """ + return self.__write_callback + + @write_callback.setter + def write_callback(self, callback: Optional[MemoryWriteCallback]) -> None: + self.__write_callback = callback + + def read(self, offset: int) -> int: + """ + Read a memory word + + Args: + offset (int): Word offset in the memory + + Returns: + memory word content + + """ + self.__offset_range_check(offset) + value = self.value[offset] + if self.read_callback is not None: + # pylint does not recognise that the property is returning a callback therefore it + # is legal to call it. + # pylint: disable-next=not-callable + self.read_callback(offset=offset, value=value) + return value + + def write(self, offset: int, data: int) -> None: + """ + Write a memory word + + Args: + offset: (int): Word offset in the memory + data: data word + + Returns: + None + + """ + self.__offset_range_check(offset) + if self.write_callback is not None: + # pylint does not recognise that the property is returning a callback therefore it + # is legal to call it. + # pylint: disable-next=not-callable + self.write_callback(offset=offset, value=data) + self.value[offset] = data + + @property + def _width_in_bytes(self) -> int: + def roundup_pow2(x: int) -> int: + return 1 << (x - 1).bit_length() + + return roundup_pow2(self.__width) // 8 + + def byte_offset_to_word_offset(self, byte_offset: int) -> int: + """ + Determine a memory word offset + + Args: + byte_offset (int): byte offset from memory start + + Returns: + word offset + + """ + return byte_offset // self._width_in_bytes + + @property + def value(self) -> _MemoryContent: + """ + Access to the memory content, bypassing the callbacks + """ + return self.__value + + def __offset_range_check(self, offset: int) -> None: + if not 0 <= offset < self.__length: + raise IndexError(f'offset must in in range 0 to {self.__length-1}, got {offset:d}') diff --git a/rdl/outputs/python/msk_top_regs/sim_lib/register.py b/rdl/outputs/python/msk_top_regs/sim_lib/register.py new file mode 100644 index 0000000..9f5b72a --- /dev/null +++ b/rdl/outputs/python/msk_top_regs/sim_lib/register.py @@ -0,0 +1,211 @@ +""" +peakrdl-python is a tool to generate Python Register Access Layer (RAL) from SystemRDL +Copyright (C) 2021 - 2023 + +This program is free software: you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation, either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . + +This module is intended to distributed as part of automatically generated code by the +peakrdl-python tool. It provides a set of base classes used by the autogenerated code +""" +from abc import ABC, abstractmethod +from typing import Optional + +from .memory import Memory +from .base import Base +from .field import FieldDefinition, Field +from ._callbacks import RegisterReadCallback,RegisterWriteCallback + +# pylint: disable=too-many-arguments + +class BaseRegister(Base, ABC): + """ + Base class for registers + """ + + __slots__ = ['_width', '_readable', '_writable', 'fields', + '__read_callback', '__write_callback'] + + def __init__(self, *, + width: int, + full_inst_name: str, + readable: bool, + writable: bool, + fields: list[FieldDefinition]): + super().__init__(full_inst_name=full_inst_name) + self._width = width + self._readable = readable + self._writable = writable + self.fields = [Field(low=field_def.low, + high=field_def.high, + msb=field_def.msb, + lsb=field_def.lsb, + inst_name=field_def.inst_name, + parent_register=self, + parent_width=width) for field_def in fields] + self.__read_callback: Optional[RegisterReadCallback] = None + self.__write_callback: Optional[RegisterWriteCallback] = None + + @property + def read_callback(self) -> Optional[RegisterReadCallback]: + """ + Callback made during each read operation + """ + return self.__read_callback + + @read_callback.setter + def read_callback(self, callback: Optional[RegisterReadCallback]) -> None: + self.__read_callback = callback + + @property + def write_callback(self) -> Optional[RegisterWriteCallback]: + """ + Callback made during each write operation + """ + return self.__write_callback + + @write_callback.setter + def write_callback(self, callback: Optional[RegisterWriteCallback]) -> None: + self.__write_callback = callback + + def _action_read_callback(self) -> None: + if self.read_callback is not None: + # pylint does not recognise that the property is returning a callback therefore it + # is legal to call it. + # pylint: disable-next=not-callable + self.read_callback(value=self.value) + + for field in self.fields: + if field.read_callback is not None: + field.read_callback(value=field.value) + + def _action_write_callback(self) -> None: + if self.write_callback is not None: + # pylint does not recognise that the property is returning a callback therefore it + # is legal to call it. + # pylint: disable-next=not-callable + self.write_callback(value=self.value) + + for field in self.fields: + if field.write_callback is not None: + field.write_callback(value=field.value) + + @abstractmethod + def read(self) -> int: + """ + Read the register + + Returns: + register content + + """ + + @abstractmethod + def write(self, data: int) -> None: + """ + Write the register + + Args: + data (int): new register content + + Returns: + None + + """ + + @property + @abstractmethod + def value(self) -> int: + """ + Access the register value without triggering the callbacks + """ + + @value.setter + @abstractmethod + def value(self, value:int) -> None: + ... + + +class Register(BaseRegister): + """ + Class for Register that is created in normal logic + """ + + __slots__ = ['__value'] + + def __init__(self, *, + width: int, + full_inst_name: str, + readable: bool, + writable: bool, + fields: list[FieldDefinition]): + super().__init__(width=width, full_inst_name=full_inst_name, + readable=readable, writable=writable, fields=fields) + self.__value = 0 + + def read(self) -> int: + + self._action_read_callback() + return self.__value + + def write(self, data: int) -> None: + + self.__value = data + self._action_write_callback() + + @property + def value(self) -> int: + return self.__value + + @value.setter + def value(self, value: int) -> None: + self.__value = value + + +class MemoryRegister(BaseRegister): + """ + Class for Register that maps onto a memory + """ + + __slots__ = ['__memory', '__offset'] + + def __init__(self, *, + width: int, + full_inst_name: str, + readable: bool, + writable: bool, + memory: Memory, + memory_address_offset: int, + fields: list[FieldDefinition]): + super().__init__(width=width, full_inst_name=full_inst_name, + readable=readable, writable=writable, fields=fields) + if not isinstance(memory, Memory): + raise TypeError(f'memory type is wrong, got {type(memory)}') + self.__memory = memory + self.__offset = memory.byte_offset_to_word_offset(memory_address_offset) + + def read(self) -> int: + self._action_read_callback() + return self.__memory.read(self.__offset) + + def write(self, data: int) -> None: + self.__memory.write(self.__offset, data) + self._action_write_callback() + + @property + def value(self) -> int: + return self.__memory.value[self.__offset] + + @value.setter + def value(self, value: int) -> None: + self.__memory.value[self.__offset] = value diff --git a/rdl/outputs/python/msk_top_regs/sim_lib/simulator.py b/rdl/outputs/python/msk_top_regs/sim_lib/simulator.py new file mode 100644 index 0000000..e7cef5b --- /dev/null +++ b/rdl/outputs/python/msk_top_regs/sim_lib/simulator.py @@ -0,0 +1,500 @@ +""" +peakrdl-python is a tool to generate Python Register Access Layer (RAL) from SystemRDL +Copyright (C) 2021 - 2023 + +This program is free software: you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation, either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . + +This module is intended to distributed as part of automatically generated code by the +peakrdl-python tool. It provides a set of base classes used by the autogenerated code +""" +from abc import ABC, abstractmethod +from dataclasses import dataclass +from typing import Optional, Union +from array import array as Array +import asyncio + +from .register import Register, MemoryRegister +from .memory import Memory +from .field import Field + +from ..lib.utility_functions import get_array_typecode + +@dataclass +class MemoryEntry: + """ + Class for an entry in the list of memories in the simulator + """ + start_address: int + end_address: int + memory: Memory + + def memory_offset(self, address: int) -> int: + """ + Convert an absolute address to word offset within a memory + + Args: + address: byte address + + Returns: memory word offset + + """ + return self.memory.byte_offset_to_word_offset(address - self.start_address) + + + def address_in_memory(self, address: int) -> bool: + """ + Determine if an address is within a memory or not + + Args: + address: byte address + + Returns: + if address is within the range of the memory + + """ + return self.start_address <= address <= self.end_address + + +class BaseSimulator(ABC): + """ + Base class of a simple simulate that can be used to test and debug peakrdl-python generated + register access layer (RAL) + """ + # pylint: disable=too-few-public-methods + + def __init__(self, address: int): + + # it is important to build the memories first as some registers may be within memories + self._memories = self._build_memories() + self._registers = self._build_registers() + self.address = address + + @abstractmethod + def _build_registers(self) -> dict[int, Union[list[Union[MemoryRegister, Register]], + Union[MemoryRegister, Register]]]: + """ + populate the register structure, this method is intended to implemented by the generated + code based on then design + """ + + @abstractmethod + def _build_memories(self) -> list[MemoryEntry]: + """ + populate the memory structure, this method is intended to written by the generated code + based on then design + """ + + def memory_for_address(self, address: int) -> Optional[MemoryEntry]: + """ + Find a memory entry for a given address + + Args: + address: byte address + + Returns: + None or matching memory entry + + """ + + memory_subset = list(filter(lambda x : x.address_in_memory(address=address), + self._memories)) + + if len(memory_subset) > 1: + raise RuntimeError(f'multiple memory matches on address 0x{address:X}({address:d})') + + if len(memory_subset) == 1: + return memory_subset[0] + + return None + + def memory_for_address_with_exception(self, address: int) -> MemoryEntry: + """ + Find a memory entry for a given address + + Args: + address: byte address + + Returns: + matching memory entry + + """ + + memory_entry = self.memory_for_address(address=address) + if memory_entry is None: + raise RuntimeError(f'Memory not found at address 0x{address:X}') + + return memory_entry + + def _read(self, addr: int, + width: int, # pylint: disable=unused-argument + accesswidth: int) -> int: # pylint: disable=unused-argument + """ + function to simulate a device read, this needs to match the protocol for the callbacks + """ + + # see if the address is a register first this ensures that registers in memories are + # accessed directly + if addr in self._registers: + addr_entry = self._registers[addr] + if isinstance(addr_entry, list): + # search the list for a readable register + for inner_reg in addr_entry: + # pylint: disable-next=protected-access + if inner_reg._readable: + return inner_reg.read() + else: + return addr_entry.read() + + potential_memory = self.memory_for_address(address=addr) + if potential_memory is not None: + return potential_memory.memory.read(offset=potential_memory.memory_offset(addr)) + + # catch all for other addresses + return 0 + + def _write(self, addr: int, + width: int, # pylint: disable=unused-argument + accesswidth: int, # pylint: disable=unused-argument + data: int) -> None: + """ + function to simulate a device write, this needs to match the protocol for the callbacks + """ + # see if the address is a register first this ensures that registers in memories are + # accessed directly + if addr in self._registers: + addr_entry = self._registers[addr] + if isinstance(addr_entry, list): + for inner_reg in addr_entry: + # pylint: disable-next=protected-access + if inner_reg._writable: + inner_reg.write(data) + else: + addr_entry.write(data) + else: + potential_memory = self.memory_for_address(address=addr) + if potential_memory is not None: + potential_memory.memory.write(offset=potential_memory.memory_offset(addr), + data=data) + + def _read_block_legacy(self, addr: int, width: int, accesswidth: int, length: int) -> Array: + """ + function to simulate a device block read, this needs to match the protocol for the + callbacks + + This currently uses a simplified implementation of converting all the block operations + to discrete operations, a future enhancement could be to access slices of memories + """ + return Array(get_array_typecode(width),self._read_block(addr=addr, + width=width, + accesswidth=accesswidth, + length=length)) + + def _read_block(self, addr: int, width: int, accesswidth: int, length: int) -> list[int]: + """ + function to simulate a device block read, this needs to match the protocol for the + callbacks + + This currently uses a simplified implementation of converting all the block operations + to discrete operations, a future enhancement could be to access slices of memories + """ + addresses = self._block_access_addresses(start_address=addr, width=width, length=length) + return [self._read(element_addr, + width=width, + accesswidth=accesswidth) for element_addr in addresses] + + def _write_block(self, addr: int, width: int, accesswidth: int, + data: Union[list, Array]) -> None: + """ + function to simulate a device block write, this needs to match the protocol for the + callbacks + + This currently uses a simplified implementation of converting all the block operations + to discrete operations, a future enhancement could be to access slices of memories + """ + addresses = self._block_access_addresses(start_address=addr, + width=width, + length=len(data)) + for (element_address, element_data) in zip(addresses, data): + self._write(addr=element_address, + data=element_data, + width=width, + accesswidth=accesswidth) + + @staticmethod + def _block_access_addresses(start_address: int, width: int, length: int) -> range: + """ + + Args: + start_address: start byte address + width: word width + length: number of word in the block + + Returns: range iterator for the addresses in the block + """ + def roundup_pow2(x: int) -> int: + return 1 << (x - 1).bit_length() + + address_increment = roundup_pow2(width) // 8 + end_address = start_address + (length * address_increment) + return range(start_address, end_address, address_increment) + + def register_by_full_name(self, name: str) -> Union[MemoryRegister, Register]: + """ + Find a register in the simulator by its fully qualified name + + Args: + name: fully qualified register name + + Returns: Register + + """ + for reg in self._registers.values(): + if isinstance(reg, list): + for reg_list_entry in reg: + if reg_list_entry.full_inst_name == name: + return reg_list_entry + else: + if reg.full_inst_name == name: + return reg + + raise ValueError(f'register name not matched: {name}') + + def field_by_full_name(self, name: str) -> Field: + """ + Find a register field in the simulator by its fully qualified name + + Args: + name: fully qualified field name + + Returns: Field + + """ + for reg in self._registers.values(): + if isinstance(reg, list): + for reg_list_entry in reg: + for field in reg_list_entry.fields: + if field.full_inst_name == name: + return field + else: + for field in reg.fields: + if field.full_inst_name == name: + return field + + raise ValueError(f'field name not matched: {name}') + + def node_by_full_name(self, name: str) -> Union[Memory, MemoryRegister, Register, Field]: + """ + Find a node in the simulator by its fully qualified name + + Args: + name: fully qualified node name + + Returns: Node + + """ + + for mem in self._memories: + if mem.memory.full_inst_name == name: + return mem.memory + + for reg in self._registers.values(): + if isinstance(reg, list): + for reg_list_entry in reg: + if reg_list_entry.full_inst_name == name: + return reg_list_entry + + for field in reg_list_entry.fields: + if field.full_inst_name == name: + return field + else: + if reg.full_inst_name == name: + return reg + + for field in reg.fields: + if field.full_inst_name == name: + return field + + raise ValueError(f'node name not matched: {name}') + + +class Simulator(BaseSimulator, ABC): + """ + Base class of a simple simulator that uses non-async callbacks that can be used to test and + debug peakrdl-python generated register access layer (RAL) + """ + + def read(self, addr: int, + width: int, # pylint: disable=unused-argument + accesswidth: int) -> int: # pylint: disable=unused-argument + """ + function to simulate a device read, this needs to match the protocol for the callbacks + """ + return self._read(addr, width, accesswidth) + + def write(self, addr: int, width: int, accesswidth: int, data: int) -> None: + """ + function to simulate a device write, this needs to match the protocol for the callbacks + """ + return self._write(addr, width, accesswidth, data) + + def read_block(self, addr: int, width: int, accesswidth: int, length: int) -> list[int]: + """ + function to simulate a device block read, this needs to match the protocol for the + callbacks + + This currently uses a simplified implementation of converting all the block operations + to discrete operations, a future enhancement could be to access slices of memories + """ + return self._read_block(addr, width, accesswidth, length) + + def write_block(self, addr: int, width: int, accesswidth: int, data: list[int]) -> None: + """ + function to simulate a device block write, this needs to match the protocol for the + callbacks + + This currently uses a simplified implementation of converting all the block operations + to discrete operations, a future enhancement could be to access slices of memories + """ + return self._write_block(addr, width, accesswidth, data) + + +class SimulatorLegacy(BaseSimulator, ABC): + """ + Base class of a simple simulator that uses non-async callbacks that can be used to test and + debug peakrdl-python generated register access layer (RAL) + """ + + def read(self, addr: int, + width: int, # pylint: disable=unused-argument + accesswidth: int) -> int: # pylint: disable=unused-argument + """ + function to simulate a device read, this needs to match the protocol for the callbacks + """ + return self._read(addr, width, accesswidth) + + def write(self, addr: int, width: int, accesswidth: int, data: int) -> None: + """ + function to simulate a device write, this needs to match the protocol for the callbacks + """ + return self._write(addr, width, accesswidth, data) + + def read_block(self, addr: int, width: int, accesswidth: int, length: int) -> Array: + """ + function to simulate a device block read, this needs to match the protocol for the + callbacks + + This currently uses a simplified implementation of converting all the block operations + to discrete operations, a future enhancement could be to access slices of memories + """ + return self._read_block_legacy(addr, width, accesswidth, length) + + def write_block(self, addr: int, width: int, accesswidth: int, data: Array) -> None: + """ + function to simulate a device block write, this needs to match the protocol for the + callbacks + + This currently uses a simplified implementation of converting all the block operations + to discrete operations, a future enhancement could be to access slices of memories + """ + return self._write_block(addr, width, accesswidth, data) + + +class AsyncSimulator(BaseSimulator, ABC): + """ + Base class of a simple simulator that uses async callbacks that can be used to test and + debug peakrdl-python generated register access layer (RAL) + """ + + async def read(self, addr: int, + width: int, # pylint: disable=unused-argument + accesswidth: int) -> int: # pylint: disable=unused-argument + """ + function to simulate a device read, this needs to match the protocol for the callbacks + """ + await asyncio.sleep(0) + return self._read(addr, width, accesswidth) + + async def write(self, addr: int, width: int, accesswidth: int, data: int) -> None: + """ + function to simulate a device write, this needs to match the protocol for the callbacks + """ + await asyncio.sleep(0) + return self._write(addr, width, accesswidth, data) + + async def read_block(self, addr: int, width: int, accesswidth: int, length: int) -> list[int]: + """ + function to simulate a device block read, this needs to match the protocol for the + callbacks + + This currently uses a simplified implementation of converting all the block operations + to discrete operations, a future enhancement could be to access slices of memories + """ + await asyncio.sleep(0) + return self._read_block(addr, width, accesswidth, length) + + async def write_block(self, addr: int, width: int, accesswidth: int, data: list[int]) -> None: + """ + function to simulate a device block write, this needs to match the protocol for the + callbacks + + This currently uses a simplified implementation of converting all the block operations + to discrete operations, a future enhancement could be to access slices of memories + """ + await asyncio.sleep(0) + return self._write_block(addr, width, accesswidth, data) + + +class AsyncSimulatorLegacy(BaseSimulator, ABC): + """ + Base class of a simple simulator that uses async callbacks that can be used to test and + debug peakrdl-python generated register access layer (RAL) + """ + + async def read(self, addr: int, + width: int, # pylint: disable=unused-argument + accesswidth: int) -> int: # pylint: disable=unused-argument + """ + function to simulate a device read, this needs to match the protocol for the callbacks + """ + await asyncio.sleep(0) + return self._read(addr, width, accesswidth) + + async def write(self, addr: int, width: int, accesswidth: int, data: int) -> None: + """ + function to simulate a device write, this needs to match the protocol for the callbacks + """ + await asyncio.sleep(0) + return self._write(addr, width, accesswidth, data) + + async def read_block(self, addr: int, width: int, accesswidth: int, length: int) -> Array: + """ + function to simulate a device block read, this needs to match the protocol for the + callbacks + + This currently uses a simplified implementation of converting all the block operations + to discrete operations, a future enhancement could be to access slices of memories + """ + await asyncio.sleep(0) + return self._read_block_legacy(addr, width, accesswidth, length) + + async def write_block(self, addr: int, width: int, accesswidth: int, data: Array) -> None: + """ + function to simulate a device block write, this needs to match the protocol for the + callbacks + + This currently uses a simplified implementation of converting all the block operations + to discrete operations, a future enhancement could be to access slices of memories + """ + await asyncio.sleep(0) + return self._write_block(addr, width, accesswidth, data) diff --git a/rdl/outputs/python/msk_top_regs/tests/__init__.py b/rdl/outputs/python/msk_top_regs/tests/__init__.py new file mode 100644 index 0000000..2ae2839 --- /dev/null +++ b/rdl/outputs/python/msk_top_regs/tests/__init__.py @@ -0,0 +1 @@ +pass diff --git a/rdl/outputs/python/msk_top_regs/tests/_msk_top_regs_sim_test_base.py b/rdl/outputs/python/msk_top_regs/tests/_msk_top_regs_sim_test_base.py new file mode 100644 index 0000000..65350f8 --- /dev/null +++ b/rdl/outputs/python/msk_top_regs/tests/_msk_top_regs_sim_test_base.py @@ -0,0 +1,50 @@ + + + +""" +Unit Tests for the msk_top_regs register model Python Wrapper + +This code was generated from the PeakRDL-python package version 1.4.0 +""" + + +import sys +import asyncio +if sys.version_info < (3, 8): + import asynctest # type: ignore[import] +else: + import unittest + + + +from ..lib import RegisterWriteVerifyError + +from ..lib import AsyncCallbackSet + + +from ._msk_top_regs_test_base import msk_top_regs_TestCase, msk_top_regs_TestCase_BlockAccess + +from ..reg_model.msk_top_regs import msk_top_regs_cls +from ..sim.msk_top_regs import msk_top_regs_simulator_cls + +class msk_top_regs_SimTestCase(msk_top_regs_TestCase): # type: ignore[valid-type,misc] + + def setUp(self) -> None: + self.sim = msk_top_regs_simulator_cls(address=0) + self.dut = msk_top_regs_cls(callbacks=AsyncCallbackSet(read_callback=self.sim.read, + write_callback=self.sim.write)) + +class msk_top_regs_SimTestCase_BlockAccess(msk_top_regs_TestCase_BlockAccess): # type: ignore[valid-type,misc] + + def setUp(self) -> None: + self.sim = msk_top_regs_simulator_cls(address=0) + self.dut = msk_top_regs_cls(callbacks=AsyncCallbackSet(read_callback=self.sim.read, + write_callback=self.sim.write, + read_block_callback=self.sim.read_block, + write_block_callback=self.sim.write_block)) + + + + +if __name__ == '__main__': + pass \ No newline at end of file diff --git a/rdl/outputs/python/msk_top_regs/tests/_msk_top_regs_test_base.py b/rdl/outputs/python/msk_top_regs/tests/_msk_top_regs_test_base.py new file mode 100644 index 0000000..eebf57f --- /dev/null +++ b/rdl/outputs/python/msk_top_regs/tests/_msk_top_regs_test_base.py @@ -0,0 +1,121 @@ + + + +""" +Unit Tests for the msk_top_regs register model Python Wrapper + +This code was generated from the PeakRDL-python package version 1.4.0 +""" +from array import array as Array + +import sys +import asyncio +if sys.version_info < (3, 8): + import asynctest # type: ignore[import] +else: + import unittest + +import random + + + +from ..lib import RegisterWriteVerifyError + +from ..lib import AsyncCallbackSet, AsyncCallbackSetLegacy + + + +from ..reg_model.msk_top_regs import msk_top_regs_cls + +from ..sim_lib.dummy_callbacks import async_dummy_read as read_addr_space +from ..sim_lib.dummy_callbacks import async_dummy_write as write_addr_space +from ..sim_lib.dummy_callbacks import async_dummy_read_block as read_block_addr_space +from ..sim_lib.dummy_callbacks import async_dummy_write_block as write_block_addr_space +from ..sim_lib.dummy_callbacks import async_dummy_read_block_legacy as read_block_addr_space_alt +from ..sim_lib.dummy_callbacks import async_dummy_write_block_legacy as write_block_addr_space_alt + + + +from ..lib import SystemRDLEnum, SystemRDLEnumEntry + + +async def read_callback(addr: int, width: int, accesswidth: int) -> int: + return await read_addr_space(addr=addr, width=width, accesswidth=accesswidth) + +async def read_block_callback(addr: int, width: int, accesswidth: int, length: int) -> list[int]: + return await read_block_addr_space(addr=addr, width=width, accesswidth=accesswidth, length=length) + +async def read_block_callback_alt(addr: int, width: int, accesswidth: int, length: int) -> Array: + return await read_block_addr_space_alt(addr=addr, width=width, accesswidth=accesswidth, length=length) + +async def write_callback(addr: int, width: int, accesswidth: int, data: int) -> None: + await write_addr_space(addr=addr, width=width, accesswidth=accesswidth, data=data) + +async def write_block_callback(addr: int, width: int, accesswidth: int, data: list[int]) -> None: + await write_block_addr_space(addr=addr, width=width, accesswidth=accesswidth, data=data) + +async def write_block_callback_alt(addr: int, width: int, accesswidth: int, data: Array) -> None: + await write_block_addr_space_alt(addr=addr, width=width, accesswidth=accesswidth, data=data) + +def random_enum_reg_value(enum_class: type[SystemRDLEnum]) -> SystemRDLEnum: + return random.choice(list(enum_class)) + + +if sys.version_info < (3, 8): + TestCaseBase = asynctest.TestCase +else: + TestCaseBase = unittest.IsolatedAsyncioTestCase + + +class msk_top_regs_TestCase(TestCaseBase): # type: ignore[valid-type,misc] + + def setUp(self) -> None: + self.dut = msk_top_regs_cls(callbacks=AsyncCallbackSet(read_callback=read_callback, + write_callback=write_callback)) + + @staticmethod + def _reverse_bits(value: int, number_bits: int) -> int: + """ + + Args: + value: value to reverse + number_bits: number of bits used in the value + + Returns: + reversed valued + """ + result = 0 + for i in range(number_bits): + if (value >> i) & 1: + result |= 1 << (number_bits - 1 - i) + return result + +class msk_top_regs_TestCase_BlockAccess(TestCaseBase): # type: ignore[valid-type,misc] + + def setUp(self) -> None: + self.dut = msk_top_regs_cls(callbacks=AsyncCallbackSet(read_callback=read_callback, + write_callback=write_callback, + read_block_callback=read_block_callback, + write_block_callback=write_block_callback)) + +class msk_top_regs_TestCase_AltBlockAccess(TestCaseBase): # type: ignore[valid-type,misc] + """ + Based test to use with the alternative call backs, this allow the legacy output API to be tested + with the new callbacks and visa versa. + """ + + def setUp(self) -> None: + self.dut = msk_top_regs_cls(callbacks=AsyncCallbackSetLegacy( + read_callback=read_callback, + write_callback=write_callback, + read_block_callback=read_block_callback_alt, + write_block_callback=write_block_callback_alt)) + + + + +if __name__ == '__main__': + pass + + + diff --git a/rdl/outputs/python/msk_top_regs/tests/test_msk_top_regs.py b/rdl/outputs/python/msk_top_regs/tests/test_msk_top_regs.py new file mode 100644 index 0000000..9241d51 --- /dev/null +++ b/rdl/outputs/python/msk_top_regs/tests/test_msk_top_regs.py @@ -0,0 +1,16576 @@ + + + +""" +Unit Tests for the msk_top_regs register model Python Wrapper + +This code was generated from the PeakRDL-python package version 1.4.0 +""" +from typing import Union,Iterable +from array import array as Array + +import sys +import asyncio +import unittest +from unittest.mock import patch, call + +import random +from itertools import combinations, chain +import math + + +from ..lib import RegisterWriteVerifyError, UnsupportedWidthError + +from ..reg_model.msk_top_regs import msk_top_regs_cls + + + + +from ..lib import FieldAsyncReadOnly, FieldAsyncWriteOnly, FieldAsyncReadWrite +from ..lib import WritableAsyncRegister, ReadableAsyncRegister +from ..lib import RegAsyncReadWrite, RegAsyncReadOnly, RegAsyncWriteOnly +from ..lib import RegAsyncReadWriteArray, RegAsyncReadOnlyArray, RegAsyncWriteOnlyArray +from ..lib import MemoryAsyncReadOnly, MemoryAsyncWriteOnly, MemoryAsyncReadWrite +from ..lib import MemoryAsyncReadOnlyArray, MemoryAsyncWriteOnlyArray, MemoryAsyncReadWriteArray +from ..lib import AsyncAddressMap, AsyncRegFile +from ..lib import AsyncAddressMapArray, AsyncRegFileArray +from ..lib import AsyncMemory + + + +from ..lib import Field +from ..lib import Reg + +from ..lib import SystemRDLEnum, SystemRDLEnumEntry + + +from ._msk_top_regs_test_base import msk_top_regs_TestCase, msk_top_regs_TestCase_BlockAccess, msk_top_regs_TestCase_AltBlockAccess +from ._msk_top_regs_test_base import __name__ as base_name +from ._msk_top_regs_test_base import random_enum_reg_value + + + +class msk_top_regs_single_access(msk_top_regs_TestCase): # type: ignore[valid-type,misc] + + def test_inst_name(self) -> None: + """ + Walk the address map and check the inst name has been correctly populated + """ + with self.subTest(msg='node: msk_top_regs.Hash_ID_Low'): + self.assertEqual(self.dut.Hash_ID_Low.inst_name, 'Hash_ID_Low') # type: ignore[union-attr] + self.assertEqual(self.dut.Hash_ID_Low.full_inst_name, 'msk_top_regs.Hash_ID_Low') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.Hash_ID_High'): + self.assertEqual(self.dut.Hash_ID_High.inst_name, 'Hash_ID_High') # type: ignore[union-attr] + self.assertEqual(self.dut.Hash_ID_High.full_inst_name, 'msk_top_regs.Hash_ID_High') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.MSK_Init'): + self.assertEqual(self.dut.MSK_Init.inst_name, 'MSK_Init') # type: ignore[union-attr] + self.assertEqual(self.dut.MSK_Init.full_inst_name, 'msk_top_regs.MSK_Init') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.MSK_Control'): + self.assertEqual(self.dut.MSK_Control.inst_name, 'MSK_Control') # type: ignore[union-attr] + self.assertEqual(self.dut.MSK_Control.full_inst_name, 'msk_top_regs.MSK_Control') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.MSK_Status'): + self.assertEqual(self.dut.MSK_Status.inst_name, 'MSK_Status') # type: ignore[union-attr] + self.assertEqual(self.dut.MSK_Status.full_inst_name, 'msk_top_regs.MSK_Status') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.Tx_Bit_Count'): + self.assertEqual(self.dut.Tx_Bit_Count.inst_name, 'Tx_Bit_Count') # type: ignore[union-attr] + self.assertEqual(self.dut.Tx_Bit_Count.full_inst_name, 'msk_top_regs.Tx_Bit_Count') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.Tx_Enable_Count'): + self.assertEqual(self.dut.Tx_Enable_Count.inst_name, 'Tx_Enable_Count') # type: ignore[union-attr] + self.assertEqual(self.dut.Tx_Enable_Count.full_inst_name, 'msk_top_regs.Tx_Enable_Count') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.Fb_FreqWord'): + self.assertEqual(self.dut.Fb_FreqWord.inst_name, 'Fb_FreqWord') # type: ignore[union-attr] + self.assertEqual(self.dut.Fb_FreqWord.full_inst_name, 'msk_top_regs.Fb_FreqWord') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.TX_F1_FreqWord'): + self.assertEqual(self.dut.TX_F1_FreqWord.inst_name, 'TX_F1_FreqWord') # type: ignore[union-attr] + self.assertEqual(self.dut.TX_F1_FreqWord.full_inst_name, 'msk_top_regs.TX_F1_FreqWord') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.TX_F2_FreqWord'): + self.assertEqual(self.dut.TX_F2_FreqWord.inst_name, 'TX_F2_FreqWord') # type: ignore[union-attr] + self.assertEqual(self.dut.TX_F2_FreqWord.full_inst_name, 'msk_top_regs.TX_F2_FreqWord') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.RX_F1_FreqWord'): + self.assertEqual(self.dut.RX_F1_FreqWord.inst_name, 'RX_F1_FreqWord') # type: ignore[union-attr] + self.assertEqual(self.dut.RX_F1_FreqWord.full_inst_name, 'msk_top_regs.RX_F1_FreqWord') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.RX_F2_FreqWord'): + self.assertEqual(self.dut.RX_F2_FreqWord.inst_name, 'RX_F2_FreqWord') # type: ignore[union-attr] + self.assertEqual(self.dut.RX_F2_FreqWord.full_inst_name, 'msk_top_regs.RX_F2_FreqWord') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.LPF_Config_0'): + self.assertEqual(self.dut.LPF_Config_0.inst_name, 'LPF_Config_0') # type: ignore[union-attr] + self.assertEqual(self.dut.LPF_Config_0.full_inst_name, 'msk_top_regs.LPF_Config_0') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.LPF_Config_1'): + self.assertEqual(self.dut.LPF_Config_1.inst_name, 'LPF_Config_1') # type: ignore[union-attr] + self.assertEqual(self.dut.LPF_Config_1.full_inst_name, 'msk_top_regs.LPF_Config_1') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.Tx_Data_Width'): + self.assertEqual(self.dut.Tx_Data_Width.inst_name, 'Tx_Data_Width') # type: ignore[union-attr] + self.assertEqual(self.dut.Tx_Data_Width.full_inst_name, 'msk_top_regs.Tx_Data_Width') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.Rx_Data_Width'): + self.assertEqual(self.dut.Rx_Data_Width.inst_name, 'Rx_Data_Width') # type: ignore[union-attr] + self.assertEqual(self.dut.Rx_Data_Width.full_inst_name, 'msk_top_regs.Rx_Data_Width') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.PRBS_Control'): + self.assertEqual(self.dut.PRBS_Control.inst_name, 'PRBS_Control') # type: ignore[union-attr] + self.assertEqual(self.dut.PRBS_Control.full_inst_name, 'msk_top_regs.PRBS_Control') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.PRBS_Initial_State'): + self.assertEqual(self.dut.PRBS_Initial_State.inst_name, 'PRBS_Initial_State') # type: ignore[union-attr] + self.assertEqual(self.dut.PRBS_Initial_State.full_inst_name, 'msk_top_regs.PRBS_Initial_State') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.PRBS_Polynomial'): + self.assertEqual(self.dut.PRBS_Polynomial.inst_name, 'PRBS_Polynomial') # type: ignore[union-attr] + self.assertEqual(self.dut.PRBS_Polynomial.full_inst_name, 'msk_top_regs.PRBS_Polynomial') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.PRBS_Error_Mask'): + self.assertEqual(self.dut.PRBS_Error_Mask.inst_name, 'PRBS_Error_Mask') # type: ignore[union-attr] + self.assertEqual(self.dut.PRBS_Error_Mask.full_inst_name, 'msk_top_regs.PRBS_Error_Mask') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.PRBS_Bit_Count'): + self.assertEqual(self.dut.PRBS_Bit_Count.inst_name, 'PRBS_Bit_Count') # type: ignore[union-attr] + self.assertEqual(self.dut.PRBS_Bit_Count.full_inst_name, 'msk_top_regs.PRBS_Bit_Count') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.PRBS_Error_Count'): + self.assertEqual(self.dut.PRBS_Error_Count.inst_name, 'PRBS_Error_Count') # type: ignore[union-attr] + self.assertEqual(self.dut.PRBS_Error_Count.full_inst_name, 'msk_top_regs.PRBS_Error_Count') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.LPF_Accum_F1'): + self.assertEqual(self.dut.LPF_Accum_F1.inst_name, 'LPF_Accum_F1') # type: ignore[union-attr] + self.assertEqual(self.dut.LPF_Accum_F1.full_inst_name, 'msk_top_regs.LPF_Accum_F1') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.LPF_Accum_F2'): + self.assertEqual(self.dut.LPF_Accum_F2.inst_name, 'LPF_Accum_F2') # type: ignore[union-attr] + self.assertEqual(self.dut.LPF_Accum_F2.full_inst_name, 'msk_top_regs.LPF_Accum_F2') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.axis_xfer_count'): + self.assertEqual(self.dut.axis_xfer_count.inst_name, 'axis_xfer_count') # type: ignore[union-attr] + self.assertEqual(self.dut.axis_xfer_count.full_inst_name, 'msk_top_regs.axis_xfer_count') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.Rx_Sample_Discard'): + self.assertEqual(self.dut.Rx_Sample_Discard.inst_name, 'Rx_Sample_Discard') # type: ignore[union-attr] + self.assertEqual(self.dut.Rx_Sample_Discard.full_inst_name, 'msk_top_regs.Rx_Sample_Discard') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.LPF_Config_2'): + self.assertEqual(self.dut.LPF_Config_2.inst_name, 'LPF_Config_2') # type: ignore[union-attr] + self.assertEqual(self.dut.LPF_Config_2.full_inst_name, 'msk_top_regs.LPF_Config_2') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.f1_nco_adjust'): + self.assertEqual(self.dut.f1_nco_adjust.inst_name, 'f1_nco_adjust') # type: ignore[union-attr] + self.assertEqual(self.dut.f1_nco_adjust.full_inst_name, 'msk_top_regs.f1_nco_adjust') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.f2_nco_adjust'): + self.assertEqual(self.dut.f2_nco_adjust.inst_name, 'f2_nco_adjust') # type: ignore[union-attr] + self.assertEqual(self.dut.f2_nco_adjust.full_inst_name, 'msk_top_regs.f2_nco_adjust') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.f1_error'): + self.assertEqual(self.dut.f1_error.inst_name, 'f1_error') # type: ignore[union-attr] + self.assertEqual(self.dut.f1_error.full_inst_name, 'msk_top_regs.f1_error') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.f2_error'): + self.assertEqual(self.dut.f2_error.inst_name, 'f2_error') # type: ignore[union-attr] + self.assertEqual(self.dut.f2_error.full_inst_name, 'msk_top_regs.f2_error') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.Tx_Sync_Ctrl'): + self.assertEqual(self.dut.Tx_Sync_Ctrl.inst_name, 'Tx_Sync_Ctrl') # type: ignore[union-attr] + self.assertEqual(self.dut.Tx_Sync_Ctrl.full_inst_name, 'msk_top_regs.Tx_Sync_Ctrl') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.Tx_Sync_Cnt'): + self.assertEqual(self.dut.Tx_Sync_Cnt.inst_name, 'Tx_Sync_Cnt') # type: ignore[union-attr] + self.assertEqual(self.dut.Tx_Sync_Cnt.full_inst_name, 'msk_top_regs.Tx_Sync_Cnt') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.lowpass_ema_alpha1'): + self.assertEqual(self.dut.lowpass_ema_alpha1.inst_name, 'lowpass_ema_alpha1') # type: ignore[union-attr] + self.assertEqual(self.dut.lowpass_ema_alpha1.full_inst_name, 'msk_top_regs.lowpass_ema_alpha1') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.lowpass_ema_alpha2'): + self.assertEqual(self.dut.lowpass_ema_alpha2.inst_name, 'lowpass_ema_alpha2') # type: ignore[union-attr] + self.assertEqual(self.dut.lowpass_ema_alpha2.full_inst_name, 'msk_top_regs.lowpass_ema_alpha2') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.rx_power'): + self.assertEqual(self.dut.rx_power.inst_name, 'rx_power') # type: ignore[union-attr] + self.assertEqual(self.dut.rx_power.full_inst_name, 'msk_top_regs.rx_power') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.Hash_ID_Low.hash_id_lo'): + self.assertEqual(self.dut.Hash_ID_Low.hash_id_lo.inst_name, 'hash_id_lo') # type: ignore[union-attr] + self.assertEqual(self.dut.Hash_ID_Low.hash_id_lo.full_inst_name, 'msk_top_regs.Hash_ID_Low.hash_id_lo') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.Hash_ID_High.hash_id_hi'): + self.assertEqual(self.dut.Hash_ID_High.hash_id_hi.inst_name, 'hash_id_hi') # type: ignore[union-attr] + self.assertEqual(self.dut.Hash_ID_High.hash_id_hi.full_inst_name, 'msk_top_regs.Hash_ID_High.hash_id_hi') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.MSK_Init.txrxinit'): + self.assertEqual(self.dut.MSK_Init.txrxinit.inst_name, 'txrxinit') # type: ignore[union-attr] + self.assertEqual(self.dut.MSK_Init.txrxinit.full_inst_name, 'msk_top_regs.MSK_Init.txrxinit') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.MSK_Init.txinit'): + self.assertEqual(self.dut.MSK_Init.txinit.inst_name, 'txinit') # type: ignore[union-attr] + self.assertEqual(self.dut.MSK_Init.txinit.full_inst_name, 'msk_top_regs.MSK_Init.txinit') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.MSK_Init.rxinit'): + self.assertEqual(self.dut.MSK_Init.rxinit.inst_name, 'rxinit') # type: ignore[union-attr] + self.assertEqual(self.dut.MSK_Init.rxinit.full_inst_name, 'msk_top_regs.MSK_Init.rxinit') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.MSK_Control.ptt'): + self.assertEqual(self.dut.MSK_Control.ptt.inst_name, 'ptt') # type: ignore[union-attr] + self.assertEqual(self.dut.MSK_Control.ptt.full_inst_name, 'msk_top_regs.MSK_Control.ptt') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.MSK_Control.loopback_ena'): + self.assertEqual(self.dut.MSK_Control.loopback_ena.inst_name, 'loopback_ena') # type: ignore[union-attr] + self.assertEqual(self.dut.MSK_Control.loopback_ena.full_inst_name, 'msk_top_regs.MSK_Control.loopback_ena') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.MSK_Control.rx_invert'): + self.assertEqual(self.dut.MSK_Control.rx_invert.inst_name, 'rx_invert') # type: ignore[union-attr] + self.assertEqual(self.dut.MSK_Control.rx_invert.full_inst_name, 'msk_top_regs.MSK_Control.rx_invert') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.MSK_Control.clear_counts'): + self.assertEqual(self.dut.MSK_Control.clear_counts.inst_name, 'clear_counts') # type: ignore[union-attr] + self.assertEqual(self.dut.MSK_Control.clear_counts.full_inst_name, 'msk_top_regs.MSK_Control.clear_counts') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.MSK_Control.diff_encoder_loopback'): + self.assertEqual(self.dut.MSK_Control.diff_encoder_loopback.inst_name, 'diff_encoder_loopback') # type: ignore[union-attr] + self.assertEqual(self.dut.MSK_Control.diff_encoder_loopback.full_inst_name, 'msk_top_regs.MSK_Control.diff_encoder_loopback') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.MSK_Status.demod_sync_lock'): + self.assertEqual(self.dut.MSK_Status.demod_sync_lock.inst_name, 'demod_sync_lock') # type: ignore[union-attr] + self.assertEqual(self.dut.MSK_Status.demod_sync_lock.full_inst_name, 'msk_top_regs.MSK_Status.demod_sync_lock') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.MSK_Status.tx_enable'): + self.assertEqual(self.dut.MSK_Status.tx_enable.inst_name, 'tx_enable') # type: ignore[union-attr] + self.assertEqual(self.dut.MSK_Status.tx_enable.full_inst_name, 'msk_top_regs.MSK_Status.tx_enable') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.MSK_Status.rx_enable'): + self.assertEqual(self.dut.MSK_Status.rx_enable.inst_name, 'rx_enable') # type: ignore[union-attr] + self.assertEqual(self.dut.MSK_Status.rx_enable.full_inst_name, 'msk_top_regs.MSK_Status.rx_enable') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.MSK_Status.tx_axis_valid'): + self.assertEqual(self.dut.MSK_Status.tx_axis_valid.inst_name, 'tx_axis_valid') # type: ignore[union-attr] + self.assertEqual(self.dut.MSK_Status.tx_axis_valid.full_inst_name, 'msk_top_regs.MSK_Status.tx_axis_valid') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.Tx_Bit_Count.tx_bit_counter'): + self.assertEqual(self.dut.Tx_Bit_Count.tx_bit_counter.inst_name, 'tx_bit_counter') # type: ignore[union-attr] + self.assertEqual(self.dut.Tx_Bit_Count.tx_bit_counter.full_inst_name, 'msk_top_regs.Tx_Bit_Count.tx_bit_counter') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.Tx_Enable_Count.tx_ena_counter'): + self.assertEqual(self.dut.Tx_Enable_Count.tx_ena_counter.inst_name, 'tx_ena_counter') # type: ignore[union-attr] + self.assertEqual(self.dut.Tx_Enable_Count.tx_ena_counter.full_inst_name, 'msk_top_regs.Tx_Enable_Count.tx_ena_counter') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.Fb_FreqWord.config_data'): + self.assertEqual(self.dut.Fb_FreqWord.config_data.inst_name, 'config_data') # type: ignore[union-attr] + self.assertEqual(self.dut.Fb_FreqWord.config_data.full_inst_name, 'msk_top_regs.Fb_FreqWord.config_data') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.TX_F1_FreqWord.config_data'): + self.assertEqual(self.dut.TX_F1_FreqWord.config_data.inst_name, 'config_data') # type: ignore[union-attr] + self.assertEqual(self.dut.TX_F1_FreqWord.config_data.full_inst_name, 'msk_top_regs.TX_F1_FreqWord.config_data') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.TX_F2_FreqWord.config_data'): + self.assertEqual(self.dut.TX_F2_FreqWord.config_data.inst_name, 'config_data') # type: ignore[union-attr] + self.assertEqual(self.dut.TX_F2_FreqWord.config_data.full_inst_name, 'msk_top_regs.TX_F2_FreqWord.config_data') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.RX_F1_FreqWord.config_data'): + self.assertEqual(self.dut.RX_F1_FreqWord.config_data.inst_name, 'config_data') # type: ignore[union-attr] + self.assertEqual(self.dut.RX_F1_FreqWord.config_data.full_inst_name, 'msk_top_regs.RX_F1_FreqWord.config_data') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.RX_F2_FreqWord.config_data'): + self.assertEqual(self.dut.RX_F2_FreqWord.config_data.inst_name, 'config_data') # type: ignore[union-attr] + self.assertEqual(self.dut.RX_F2_FreqWord.config_data.full_inst_name, 'msk_top_regs.RX_F2_FreqWord.config_data') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.LPF_Config_0.lpf_freeze'): + self.assertEqual(self.dut.LPF_Config_0.lpf_freeze.inst_name, 'lpf_freeze') # type: ignore[union-attr] + self.assertEqual(self.dut.LPF_Config_0.lpf_freeze.full_inst_name, 'msk_top_regs.LPF_Config_0.lpf_freeze') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.LPF_Config_0.lpf_zero'): + self.assertEqual(self.dut.LPF_Config_0.lpf_zero.inst_name, 'lpf_zero') # type: ignore[union-attr] + self.assertEqual(self.dut.LPF_Config_0.lpf_zero.full_inst_name, 'msk_top_regs.LPF_Config_0.lpf_zero') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.LPF_Config_0.prbs_reserved'): + self.assertEqual(self.dut.LPF_Config_0.prbs_reserved.inst_name, 'prbs_reserved') # type: ignore[union-attr] + self.assertEqual(self.dut.LPF_Config_0.prbs_reserved.full_inst_name, 'msk_top_regs.LPF_Config_0.prbs_reserved') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.LPF_Config_0.lpf_alpha'): + self.assertEqual(self.dut.LPF_Config_0.lpf_alpha.inst_name, 'lpf_alpha') # type: ignore[union-attr] + self.assertEqual(self.dut.LPF_Config_0.lpf_alpha.full_inst_name, 'msk_top_regs.LPF_Config_0.lpf_alpha') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.LPF_Config_1.i_gain'): + self.assertEqual(self.dut.LPF_Config_1.i_gain.inst_name, 'i_gain') # type: ignore[union-attr] + self.assertEqual(self.dut.LPF_Config_1.i_gain.full_inst_name, 'msk_top_regs.LPF_Config_1.i_gain') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.LPF_Config_1.i_shift'): + self.assertEqual(self.dut.LPF_Config_1.i_shift.inst_name, 'i_shift') # type: ignore[union-attr] + self.assertEqual(self.dut.LPF_Config_1.i_shift.full_inst_name, 'msk_top_regs.LPF_Config_1.i_shift') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.Tx_Data_Width.data_width'): + self.assertEqual(self.dut.Tx_Data_Width.data_width.inst_name, 'data_width') # type: ignore[union-attr] + self.assertEqual(self.dut.Tx_Data_Width.data_width.full_inst_name, 'msk_top_regs.Tx_Data_Width.data_width') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.Rx_Data_Width.data_width'): + self.assertEqual(self.dut.Rx_Data_Width.data_width.inst_name, 'data_width') # type: ignore[union-attr] + self.assertEqual(self.dut.Rx_Data_Width.data_width.full_inst_name, 'msk_top_regs.Rx_Data_Width.data_width') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.PRBS_Control.prbs_sel'): + self.assertEqual(self.dut.PRBS_Control.prbs_sel.inst_name, 'prbs_sel') # type: ignore[union-attr] + self.assertEqual(self.dut.PRBS_Control.prbs_sel.full_inst_name, 'msk_top_regs.PRBS_Control.prbs_sel') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.PRBS_Control.prbs_error_insert'): + self.assertEqual(self.dut.PRBS_Control.prbs_error_insert.inst_name, 'prbs_error_insert') # type: ignore[union-attr] + self.assertEqual(self.dut.PRBS_Control.prbs_error_insert.full_inst_name, 'msk_top_regs.PRBS_Control.prbs_error_insert') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.PRBS_Control.prbs_clear'): + self.assertEqual(self.dut.PRBS_Control.prbs_clear.inst_name, 'prbs_clear') # type: ignore[union-attr] + self.assertEqual(self.dut.PRBS_Control.prbs_clear.full_inst_name, 'msk_top_regs.PRBS_Control.prbs_clear') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.PRBS_Control.prbs_manual_sync'): + self.assertEqual(self.dut.PRBS_Control.prbs_manual_sync.inst_name, 'prbs_manual_sync') # type: ignore[union-attr] + self.assertEqual(self.dut.PRBS_Control.prbs_manual_sync.full_inst_name, 'msk_top_regs.PRBS_Control.prbs_manual_sync') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.PRBS_Control.prbs_reserved'): + self.assertEqual(self.dut.PRBS_Control.prbs_reserved.inst_name, 'prbs_reserved') # type: ignore[union-attr] + self.assertEqual(self.dut.PRBS_Control.prbs_reserved.full_inst_name, 'msk_top_regs.PRBS_Control.prbs_reserved') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.PRBS_Control.prbs_sync_threshold'): + self.assertEqual(self.dut.PRBS_Control.prbs_sync_threshold.inst_name, 'prbs_sync_threshold') # type: ignore[union-attr] + self.assertEqual(self.dut.PRBS_Control.prbs_sync_threshold.full_inst_name, 'msk_top_regs.PRBS_Control.prbs_sync_threshold') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.PRBS_Initial_State.config_data'): + self.assertEqual(self.dut.PRBS_Initial_State.config_data.inst_name, 'config_data') # type: ignore[union-attr] + self.assertEqual(self.dut.PRBS_Initial_State.config_data.full_inst_name, 'msk_top_regs.PRBS_Initial_State.config_data') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.PRBS_Polynomial.config_data'): + self.assertEqual(self.dut.PRBS_Polynomial.config_data.inst_name, 'config_data') # type: ignore[union-attr] + self.assertEqual(self.dut.PRBS_Polynomial.config_data.full_inst_name, 'msk_top_regs.PRBS_Polynomial.config_data') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.PRBS_Error_Mask.config_data'): + self.assertEqual(self.dut.PRBS_Error_Mask.config_data.inst_name, 'config_data') # type: ignore[union-attr] + self.assertEqual(self.dut.PRBS_Error_Mask.config_data.full_inst_name, 'msk_top_regs.PRBS_Error_Mask.config_data') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.PRBS_Bit_Count.status_data'): + self.assertEqual(self.dut.PRBS_Bit_Count.status_data.inst_name, 'status_data') # type: ignore[union-attr] + self.assertEqual(self.dut.PRBS_Bit_Count.status_data.full_inst_name, 'msk_top_regs.PRBS_Bit_Count.status_data') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.PRBS_Error_Count.status_data'): + self.assertEqual(self.dut.PRBS_Error_Count.status_data.inst_name, 'status_data') # type: ignore[union-attr] + self.assertEqual(self.dut.PRBS_Error_Count.status_data.full_inst_name, 'msk_top_regs.PRBS_Error_Count.status_data') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.LPF_Accum_F1.status_data'): + self.assertEqual(self.dut.LPF_Accum_F1.status_data.inst_name, 'status_data') # type: ignore[union-attr] + self.assertEqual(self.dut.LPF_Accum_F1.status_data.full_inst_name, 'msk_top_regs.LPF_Accum_F1.status_data') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.LPF_Accum_F2.status_data'): + self.assertEqual(self.dut.LPF_Accum_F2.status_data.inst_name, 'status_data') # type: ignore[union-attr] + self.assertEqual(self.dut.LPF_Accum_F2.status_data.full_inst_name, 'msk_top_regs.LPF_Accum_F2.status_data') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.axis_xfer_count.xfer_count'): + self.assertEqual(self.dut.axis_xfer_count.xfer_count.inst_name, 'xfer_count') # type: ignore[union-attr] + self.assertEqual(self.dut.axis_xfer_count.xfer_count.full_inst_name, 'msk_top_regs.axis_xfer_count.xfer_count') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.Rx_Sample_Discard.rx_sample_discard'): + self.assertEqual(self.dut.Rx_Sample_Discard.rx_sample_discard.inst_name, 'rx_sample_discard') # type: ignore[union-attr] + self.assertEqual(self.dut.Rx_Sample_Discard.rx_sample_discard.full_inst_name, 'msk_top_regs.Rx_Sample_Discard.rx_sample_discard') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.Rx_Sample_Discard.rx_nco_discard'): + self.assertEqual(self.dut.Rx_Sample_Discard.rx_nco_discard.inst_name, 'rx_nco_discard') # type: ignore[union-attr] + self.assertEqual(self.dut.Rx_Sample_Discard.rx_nco_discard.full_inst_name, 'msk_top_regs.Rx_Sample_Discard.rx_nco_discard') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.LPF_Config_2.p_gain'): + self.assertEqual(self.dut.LPF_Config_2.p_gain.inst_name, 'p_gain') # type: ignore[union-attr] + self.assertEqual(self.dut.LPF_Config_2.p_gain.full_inst_name, 'msk_top_regs.LPF_Config_2.p_gain') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.LPF_Config_2.p_shift'): + self.assertEqual(self.dut.LPF_Config_2.p_shift.inst_name, 'p_shift') # type: ignore[union-attr] + self.assertEqual(self.dut.LPF_Config_2.p_shift.full_inst_name, 'msk_top_regs.LPF_Config_2.p_shift') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.f1_nco_adjust.data'): + self.assertEqual(self.dut.f1_nco_adjust.data.inst_name, 'data') # type: ignore[union-attr] + self.assertEqual(self.dut.f1_nco_adjust.data.full_inst_name, 'msk_top_regs.f1_nco_adjust.data') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.f2_nco_adjust.data'): + self.assertEqual(self.dut.f2_nco_adjust.data.inst_name, 'data') # type: ignore[union-attr] + self.assertEqual(self.dut.f2_nco_adjust.data.full_inst_name, 'msk_top_regs.f2_nco_adjust.data') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.f1_error.data'): + self.assertEqual(self.dut.f1_error.data.inst_name, 'data') # type: ignore[union-attr] + self.assertEqual(self.dut.f1_error.data.full_inst_name, 'msk_top_regs.f1_error.data') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.f2_error.data'): + self.assertEqual(self.dut.f2_error.data.inst_name, 'data') # type: ignore[union-attr] + self.assertEqual(self.dut.f2_error.data.full_inst_name, 'msk_top_regs.f2_error.data') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.Tx_Sync_Ctrl.tx_sync_ena'): + self.assertEqual(self.dut.Tx_Sync_Ctrl.tx_sync_ena.inst_name, 'tx_sync_ena') # type: ignore[union-attr] + self.assertEqual(self.dut.Tx_Sync_Ctrl.tx_sync_ena.full_inst_name, 'msk_top_regs.Tx_Sync_Ctrl.tx_sync_ena') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.Tx_Sync_Ctrl.tx_sync_force'): + self.assertEqual(self.dut.Tx_Sync_Ctrl.tx_sync_force.inst_name, 'tx_sync_force') # type: ignore[union-attr] + self.assertEqual(self.dut.Tx_Sync_Ctrl.tx_sync_force.full_inst_name, 'msk_top_regs.Tx_Sync_Ctrl.tx_sync_force') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.Tx_Sync_Ctrl.tx_sync_f1'): + self.assertEqual(self.dut.Tx_Sync_Ctrl.tx_sync_f1.inst_name, 'tx_sync_f1') # type: ignore[union-attr] + self.assertEqual(self.dut.Tx_Sync_Ctrl.tx_sync_f1.full_inst_name, 'msk_top_regs.Tx_Sync_Ctrl.tx_sync_f1') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.Tx_Sync_Ctrl.tx_sync_f2'): + self.assertEqual(self.dut.Tx_Sync_Ctrl.tx_sync_f2.inst_name, 'tx_sync_f2') # type: ignore[union-attr] + self.assertEqual(self.dut.Tx_Sync_Ctrl.tx_sync_f2.full_inst_name, 'msk_top_regs.Tx_Sync_Ctrl.tx_sync_f2') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.Tx_Sync_Cnt.tx_sync_cnt'): + self.assertEqual(self.dut.Tx_Sync_Cnt.tx_sync_cnt.inst_name, 'tx_sync_cnt') # type: ignore[union-attr] + self.assertEqual(self.dut.Tx_Sync_Cnt.tx_sync_cnt.full_inst_name, 'msk_top_regs.Tx_Sync_Cnt.tx_sync_cnt') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.lowpass_ema_alpha1.alpha'): + self.assertEqual(self.dut.lowpass_ema_alpha1.alpha.inst_name, 'alpha') # type: ignore[union-attr] + self.assertEqual(self.dut.lowpass_ema_alpha1.alpha.full_inst_name, 'msk_top_regs.lowpass_ema_alpha1.alpha') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.lowpass_ema_alpha2.alpha'): + self.assertEqual(self.dut.lowpass_ema_alpha2.alpha.inst_name, 'alpha') # type: ignore[union-attr] + self.assertEqual(self.dut.lowpass_ema_alpha2.alpha.full_inst_name, 'msk_top_regs.lowpass_ema_alpha2.alpha') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.rx_power.rx_power'): + self.assertEqual(self.dut.rx_power.rx_power.inst_name, 'rx_power') # type: ignore[union-attr] + self.assertEqual(self.dut.rx_power.rx_power.full_inst_name, 'msk_top_regs.rx_power.rx_power') # type: ignore[union-attr] + + + def test_name_property(self) -> None: + """ + Walk the address map and check the name property has been correctly populated + """ + with self.subTest(msg='node: msk_top_regs.Hash_ID_Low'): + + + self.assertEqual(self.dut.Hash_ID_Low.rdl_name, "Pluto MSK FPGA Hash ID - Lower 32-bits") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.Hash_ID_High'): + + + self.assertEqual(self.dut.Hash_ID_High.rdl_name, "Pluto MSK FPGA Hash ID - Upper 32-bits") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.MSK_Init'): + + + self.assertEqual(self.dut.MSK_Init.rdl_name, "MSK Modem Initialization Control") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.MSK_Control'): + + + self.assertEqual(self.dut.MSK_Control.rdl_name, "MSK Modem Control") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.MSK_Status'): + + + self.assertEqual(self.dut.MSK_Status.rdl_name, "MSK Modem Status 0") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.Tx_Bit_Count'): + + + self.assertEqual(self.dut.Tx_Bit_Count.rdl_name, "MSK Modem Status 1") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.Tx_Enable_Count'): + + + self.assertEqual(self.dut.Tx_Enable_Count.rdl_name, "MSK Modem Status 2") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.Fb_FreqWord'): + + + self.assertEqual(self.dut.Fb_FreqWord.rdl_name, "Bitrate NCO Frequency Control Word") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.TX_F1_FreqWord'): + + + self.assertEqual(self.dut.TX_F1_FreqWord.rdl_name, "Tx F1 NCO Frequency Control Word") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.TX_F2_FreqWord'): + + + self.assertEqual(self.dut.TX_F2_FreqWord.rdl_name, "Tx F2 NCO Frequency Control Word") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.RX_F1_FreqWord'): + + + self.assertEqual(self.dut.RX_F1_FreqWord.rdl_name, "Rx F1 NCO Frequency Control Word") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.RX_F2_FreqWord'): + + + self.assertEqual(self.dut.RX_F2_FreqWord.rdl_name, "Rx F2 NCO Frequency Control Word") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.LPF_Config_0'): + + + self.assertEqual(self.dut.LPF_Config_0.rdl_name, "PI Controller Configuration and Low-pass Filter Configuration") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.LPF_Config_1'): + + + self.assertEqual(self.dut.LPF_Config_1.rdl_name, "PI Controller Configuration Configuration Register 1") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.Tx_Data_Width'): + + + self.assertEqual(self.dut.Tx_Data_Width.rdl_name, "Modem Tx Input Data Width") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.Rx_Data_Width'): + + + self.assertEqual(self.dut.Rx_Data_Width.rdl_name, "Modem Rx Output Data Width") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.PRBS_Control'): + + + self.assertEqual(self.dut.PRBS_Control.rdl_name, "PRBS Control 0") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.PRBS_Initial_State'): + + + self.assertEqual(self.dut.PRBS_Initial_State.rdl_name, "PRBS Control 1") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.PRBS_Polynomial'): + + + self.assertEqual(self.dut.PRBS_Polynomial.rdl_name, "PRBS Control 2") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.PRBS_Error_Mask'): + + + self.assertEqual(self.dut.PRBS_Error_Mask.rdl_name, "PRBS Control 3") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.PRBS_Bit_Count'): + + + self.assertEqual(self.dut.PRBS_Bit_Count.rdl_name, "PRBS Status 0") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.PRBS_Error_Count'): + + + self.assertEqual(self.dut.PRBS_Error_Count.rdl_name, "PRBS Status 1") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.LPF_Accum_F1'): + + + self.assertEqual(self.dut.LPF_Accum_F1.rdl_name, "F1 PI Controller Accumulator") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.LPF_Accum_F2'): + + + self.assertEqual(self.dut.LPF_Accum_F2.rdl_name, "F2 PI Controller Accumulator") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.axis_xfer_count'): + + + self.assertEqual(self.dut.axis_xfer_count.rdl_name, "MSK Modem Status 3") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.Rx_Sample_Discard'): + + + self.assertEqual(self.dut.Rx_Sample_Discard.rdl_name, "Rx Sample Discard") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.LPF_Config_2'): + + + self.assertEqual(self.dut.LPF_Config_2.rdl_name, "PI Controller Configuration Configuration Register 2") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.f1_nco_adjust'): + + + self.assertEqual(self.dut.f1_nco_adjust.rdl_name, "F1 NCO Frequency Adjust") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.f2_nco_adjust'): + + + self.assertEqual(self.dut.f2_nco_adjust.rdl_name, "F2 NCO Frequency Adjust") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.f1_error'): + + + self.assertEqual(self.dut.f1_error.rdl_name, "F1 Error Value") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.f2_error'): + + + self.assertEqual(self.dut.f2_error.rdl_name, "F2 Error Value") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.Tx_Sync_Ctrl'): + + + self.assertEqual(self.dut.Tx_Sync_Ctrl.rdl_name, "Transmitter Sync Control") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.Tx_Sync_Cnt'): + + + self.assertEqual(self.dut.Tx_Sync_Cnt.rdl_name, "Transmitter Sync Duration") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.lowpass_ema_alpha1'): + + + self.assertEqual(self.dut.lowpass_ema_alpha1.rdl_name, "Exponential Moving Average Alpha") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.lowpass_ema_alpha2'): + + + self.assertEqual(self.dut.lowpass_ema_alpha2.rdl_name, "Exponential Moving Average Alpha") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.rx_power'): + + + self.assertEqual(self.dut.rx_power.rdl_name, "Receive Power") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.Hash_ID_Low.hash_id_lo'): + + + self.assertEqual(self.dut.Hash_ID_Low.hash_id_lo.rdl_name, "Hash ID Lower 32-bits") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.Hash_ID_High.hash_id_hi'): + + + self.assertEqual(self.dut.Hash_ID_High.hash_id_hi.rdl_name, "Hash ID Upper 32-bits") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.MSK_Init.txrxinit'): + + + self.assertEqual(self.dut.MSK_Init.txrxinit.rdl_name, "Tx/Rx Init Enable") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.MSK_Init.txinit'): + + + self.assertEqual(self.dut.MSK_Init.txinit.rdl_name, "Tx Init Enable") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.MSK_Init.rxinit'): + + + self.assertEqual(self.dut.MSK_Init.rxinit.rdl_name, "Rx Init Enable") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.MSK_Control.ptt'): + + + self.assertEqual(self.dut.MSK_Control.ptt.rdl_name, "Push-to-Talk Enable") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.MSK_Control.loopback_ena'): + + + self.assertEqual(self.dut.MSK_Control.loopback_ena.rdl_name, "Modem Digital Tx -\u003e Rx Loopback Enable") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.MSK_Control.rx_invert'): + + + self.assertEqual(self.dut.MSK_Control.rx_invert.rdl_name, "Rx Data Invert Enable") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.MSK_Control.clear_counts'): + + + self.assertEqual(self.dut.MSK_Control.clear_counts.rdl_name, "Clear Status Counters") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.MSK_Control.diff_encoder_loopback'): + + + self.assertEqual(self.dut.MSK_Control.diff_encoder_loopback.rdl_name, "Differential Encoder -\u003e Decoder Loopback Enable") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.MSK_Status.demod_sync_lock'): + + + self.assertEqual(self.dut.MSK_Status.demod_sync_lock.rdl_name, "Demodulator Sync Status") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.MSK_Status.tx_enable'): + + + self.assertEqual(self.dut.MSK_Status.tx_enable.rdl_name, "AD9363 DAC Interface Tx Enable Input Active") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.MSK_Status.rx_enable'): + + + self.assertEqual(self.dut.MSK_Status.rx_enable.rdl_name, "AD9363 ADC Interface Rx Enable Input Active") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.MSK_Status.tx_axis_valid'): + + + self.assertEqual(self.dut.MSK_Status.tx_axis_valid.rdl_name, "Tx S_AXIS_VALID") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.Tx_Bit_Count.tx_bit_counter'): + + + self.assertEqual(self.dut.Tx_Bit_Count.tx_bit_counter.rdl_name, "Tx Bit Count") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.Tx_Enable_Count.tx_ena_counter'): + + + self.assertEqual(self.dut.Tx_Enable_Count.tx_ena_counter.rdl_name, "Tx Enable Count") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.Fb_FreqWord.config_data'): + + + self.assertEqual(self.dut.Fb_FreqWord.config_data.rdl_name, "Frequency Control Word") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.TX_F1_FreqWord.config_data'): + + + self.assertEqual(self.dut.TX_F1_FreqWord.config_data.rdl_name, "Frequency Control Word") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.TX_F2_FreqWord.config_data'): + + + self.assertEqual(self.dut.TX_F2_FreqWord.config_data.rdl_name, "Frequency Control Word") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.RX_F1_FreqWord.config_data'): + + + self.assertEqual(self.dut.RX_F1_FreqWord.config_data.rdl_name, "Frequency Control Word") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.RX_F2_FreqWord.config_data'): + + + self.assertEqual(self.dut.RX_F2_FreqWord.config_data.rdl_name, "Frequency Control Word") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.LPF_Config_0.lpf_freeze'): + + + self.assertEqual(self.dut.LPF_Config_0.lpf_freeze.rdl_name, "Freeze the accumulator\u0027s current value") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.LPF_Config_0.lpf_zero'): + + + self.assertEqual(self.dut.LPF_Config_0.lpf_zero.rdl_name, "Hold the PI Accumulator at zero") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.LPF_Config_0.prbs_reserved'): + + + self.assertEqual(self.dut.LPF_Config_0.prbs_reserved.rdl_name, "Reserved") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.LPF_Config_0.lpf_alpha'): + + + self.assertEqual(self.dut.LPF_Config_0.lpf_alpha.rdl_name, "Lowpass IIR filter alpha") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.LPF_Config_1.i_gain'): + + + self.assertEqual(self.dut.LPF_Config_1.i_gain.rdl_name, "Integral Gain Value") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.LPF_Config_1.i_shift'): + + + self.assertEqual(self.dut.LPF_Config_1.i_shift.rdl_name, "Integral Gain Bit Shift") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.Tx_Data_Width.data_width'): + + + self.assertEqual(self.dut.Tx_Data_Width.data_width.rdl_name, "Modem input/output data width") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.Rx_Data_Width.data_width'): + + + self.assertEqual(self.dut.Rx_Data_Width.data_width.rdl_name, "Modem input/output data width") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.PRBS_Control.prbs_sel'): + + + self.assertEqual(self.dut.PRBS_Control.prbs_sel.rdl_name, "PRBS Data Select") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.PRBS_Control.prbs_error_insert'): + + + self.assertEqual(self.dut.PRBS_Control.prbs_error_insert.rdl_name, "PRBS Error Insert") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.PRBS_Control.prbs_clear'): + + + self.assertEqual(self.dut.PRBS_Control.prbs_clear.rdl_name, "PRBS Clear Counters") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.PRBS_Control.prbs_manual_sync'): + + + self.assertEqual(self.dut.PRBS_Control.prbs_manual_sync.rdl_name, "PRBS Manual Sync") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.PRBS_Control.prbs_reserved'): + + + self.assertEqual(self.dut.PRBS_Control.prbs_reserved.rdl_name, "Reserved") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.PRBS_Control.prbs_sync_threshold'): + + + self.assertEqual(self.dut.PRBS_Control.prbs_sync_threshold.rdl_name, "PRBS Auto Sync Threshold") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.PRBS_Initial_State.config_data'): + + + self.assertEqual(self.dut.PRBS_Initial_State.config_data.rdl_name, "PRBS Seed") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.PRBS_Polynomial.config_data'): + + + self.assertEqual(self.dut.PRBS_Polynomial.config_data.rdl_name, "PRBS Polynomial") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.PRBS_Error_Mask.config_data'): + + + self.assertEqual(self.dut.PRBS_Error_Mask.config_data.rdl_name, "PRBS Error Mask") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.PRBS_Bit_Count.status_data'): + + + self.assertEqual(self.dut.PRBS_Bit_Count.status_data.rdl_name, "PRBS Bits Received") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.PRBS_Error_Count.status_data'): + + + self.assertEqual(self.dut.PRBS_Error_Count.status_data.rdl_name, "PRBS Bit Errors") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.LPF_Accum_F1.status_data'): + + + self.assertEqual(self.dut.LPF_Accum_F1.status_data.rdl_name, "PI Controller Accumulator Value") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.LPF_Accum_F2.status_data'): + + + self.assertEqual(self.dut.LPF_Accum_F2.status_data.rdl_name, "PI Controller Accumulator Value") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.axis_xfer_count.xfer_count'): + + + self.assertEqual(self.dut.axis_xfer_count.xfer_count.rdl_name, "S_AXIS Transfers") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.Rx_Sample_Discard.rx_sample_discard'): + + + self.assertEqual(self.dut.Rx_Sample_Discard.rx_sample_discard.rdl_name, "Rx Sample Discard Value") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.Rx_Sample_Discard.rx_nco_discard'): + + + self.assertEqual(self.dut.Rx_Sample_Discard.rx_nco_discard.rdl_name, "Rx NCO Sample Discard Value") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.LPF_Config_2.p_gain'): + + + self.assertEqual(self.dut.LPF_Config_2.p_gain.rdl_name, "Proportional Gain Value") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.LPF_Config_2.p_shift'): + + + self.assertEqual(self.dut.LPF_Config_2.p_shift.rdl_name, "Proportional Gain Bit Shift") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.f1_nco_adjust.data'): + + + self.assertEqual(self.dut.f1_nco_adjust.data.rdl_name, "F1 NCO Frequency Adjust") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.f2_nco_adjust.data'): + + + self.assertEqual(self.dut.f2_nco_adjust.data.rdl_name, "F2 NCO Frequency Adjust") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.f1_error.data'): + + + self.assertEqual(self.dut.f1_error.data.rdl_name, "F1 Error Value") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.f2_error.data'): + + + self.assertEqual(self.dut.f2_error.data.rdl_name, "F2 Error Value") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.Tx_Sync_Ctrl.tx_sync_ena'): + + + self.assertEqual(self.dut.Tx_Sync_Ctrl.tx_sync_ena.rdl_name, "Tx Sync Enable") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.Tx_Sync_Ctrl.tx_sync_force'): + + + self.assertEqual(self.dut.Tx_Sync_Ctrl.tx_sync_force.rdl_name, "Tx Sync Force") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.Tx_Sync_Ctrl.tx_sync_f1'): + + + self.assertEqual(self.dut.Tx_Sync_Ctrl.tx_sync_f1.rdl_name, "Tx F1 Sync Enable") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.Tx_Sync_Ctrl.tx_sync_f2'): + + + self.assertEqual(self.dut.Tx_Sync_Ctrl.tx_sync_f2.rdl_name, "Tx F2 Sync Enable") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.Tx_Sync_Cnt.tx_sync_cnt'): + + + self.assertEqual(self.dut.Tx_Sync_Cnt.tx_sync_cnt.rdl_name, "Tx sync duration") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.lowpass_ema_alpha1.alpha'): + + + self.assertEqual(self.dut.lowpass_ema_alpha1.alpha.rdl_name, "EMA alpha") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.lowpass_ema_alpha2.alpha'): + + + self.assertEqual(self.dut.lowpass_ema_alpha2.alpha.rdl_name, "EMA alpha") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.rx_power.rx_power'): + + + self.assertEqual(self.dut.rx_power.rx_power.rdl_name, "Receive Power") # type: ignore[union-attr] + + + + + + def test_desc(self) -> None: + """ + Walk the address map and check the desc property has been correctly populated + """ + with self.subTest(msg='node: msk_top_regs.Hash_ID_Low'): + + + self.assertIsNone(self.dut.Hash_ID_Low.rdl_desc) # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.Hash_ID_High'): + + + self.assertIsNone(self.dut.Hash_ID_High.rdl_desc) # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.MSK_Init'): + + + self.assertEqual(self.dut.MSK_Init.rdl_desc, "Synchronous initialization of MSK Modem functions, does not affect configuration registers.") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.MSK_Control'): + + + self.assertEqual(self.dut.MSK_Control.rdl_desc, "MSK Modem Configuration and Control") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.MSK_Status'): + + + self.assertEqual(self.dut.MSK_Status.rdl_desc, "Modem status bits") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.Tx_Bit_Count'): + + + self.assertEqual(self.dut.Tx_Bit_Count.rdl_desc, "Modem status data") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.Tx_Enable_Count'): + + + self.assertEqual(self.dut.Tx_Enable_Count.rdl_desc, "Modem status data") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.Fb_FreqWord'): + + + self.assertEqual(self.dut.Fb_FreqWord.rdl_desc, "Set Modem Data Rate") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.TX_F1_FreqWord'): + + + self.assertEqual(self.dut.TX_F1_FreqWord.rdl_desc, "Set Modulator F1 Frequency") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.TX_F2_FreqWord'): + + + self.assertEqual(self.dut.TX_F2_FreqWord.rdl_desc, "Set Modulator F2 Frequency") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.RX_F1_FreqWord'): + + + self.assertEqual(self.dut.RX_F1_FreqWord.rdl_desc, "Set Demodulator F1 Frequency") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.RX_F2_FreqWord'): + + + self.assertEqual(self.dut.RX_F2_FreqWord.rdl_desc, "Set Demodulator F2 Frequency") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.LPF_Config_0'): + + + self.assertEqual(self.dut.LPF_Config_0.rdl_desc, "Configure PI controller and low-pass filter") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.LPF_Config_1'): + + + self.assertEqual(self.dut.LPF_Config_1.rdl_desc, "Configures PI Controller I-gain and divisor") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.Tx_Data_Width'): + + + self.assertEqual(self.dut.Tx_Data_Width.rdl_desc, "Set the parallel data width of the parallel-to-serial converter") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.Rx_Data_Width'): + + + self.assertEqual(self.dut.Rx_Data_Width.rdl_desc, "Set the parallel data width of the serial-to-parallel converter") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.PRBS_Control'): + + + self.assertEqual(self.dut.PRBS_Control.rdl_desc, "Configures operation of the PRBS Generator and Monitor") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.PRBS_Initial_State'): + + + self.assertEqual(self.dut.PRBS_Initial_State.rdl_desc, "PRBS Initial State") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.PRBS_Polynomial'): + + + self.assertEqual(self.dut.PRBS_Polynomial.rdl_desc, "PRBS Polynomial") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.PRBS_Error_Mask'): + + + self.assertEqual(self.dut.PRBS_Error_Mask.rdl_desc, "PRBS Error Mask") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.PRBS_Bit_Count'): + + + self.assertEqual(self.dut.PRBS_Bit_Count.rdl_desc, "PRBS Bits Received") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.PRBS_Error_Count'): + + + self.assertEqual(self.dut.PRBS_Error_Count.rdl_desc, "PRBS Bit Errors") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.LPF_Accum_F1'): + + + self.assertEqual(self.dut.LPF_Accum_F1.rdl_desc, "Value of the F1 PI Controller Accumulator") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.LPF_Accum_F2'): + + + self.assertEqual(self.dut.LPF_Accum_F2.rdl_desc, "Value of the F2 PI Controller Accumulator") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.axis_xfer_count'): + + + self.assertEqual(self.dut.axis_xfer_count.rdl_desc, "Modem status data") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.Rx_Sample_Discard'): + + + self.assertEqual(self.dut.Rx_Sample_Discard.rdl_desc, "Configure samples discard operation for demodulator") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.LPF_Config_2'): + + + self.assertEqual(self.dut.LPF_Config_2.rdl_desc, "Configures PI Controller I-gain and divisor") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.f1_nco_adjust'): + + + self.assertEqual(self.dut.f1_nco_adjust.rdl_desc, "Frequency offet applied to the F1 NCO") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.f2_nco_adjust'): + + + self.assertEqual(self.dut.f2_nco_adjust.rdl_desc, "Frequency offet applied to the F2 NCO") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.f1_error'): + + + self.assertEqual(self.dut.f1_error.rdl_desc, "Error value of the F1 Costas loop after each active bit period") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.f2_error'): + + + self.assertEqual(self.dut.f2_error.rdl_desc, "Error value of the F2 Costas loop after each active bit period") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.Tx_Sync_Ctrl'): + + + self.assertEqual(self.dut.Tx_Sync_Ctrl.rdl_desc, "Provides control bits for generation of transmitter synchronization patterns") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.Tx_Sync_Cnt'): + + + self.assertEqual(self.dut.Tx_Sync_Cnt.rdl_desc, "Sets the duration of the synchronization tones when enabled") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.lowpass_ema_alpha1'): + + + self.assertEqual(self.dut.lowpass_ema_alpha1.rdl_desc, "Sets the alpha for the EMA") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.lowpass_ema_alpha2'): + + + self.assertEqual(self.dut.lowpass_ema_alpha2.rdl_desc, "Sets the alpha for the EMA") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.rx_power'): + + + self.assertEqual(self.dut.rx_power.rdl_desc, "Receive power computed from I/Q ssamples") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.Hash_ID_Low.hash_id_lo'): + + + self.assertEqual(self.dut.Hash_ID_Low.hash_id_lo.rdl_desc, "Lower 32-bits of Pluto MSK FPGA Hash ID") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.Hash_ID_High.hash_id_hi'): + + + self.assertEqual(self.dut.Hash_ID_High.hash_id_hi.rdl_desc, "Upper 32-bits of Pluto MSK FPGA Hash ID") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.MSK_Init.txrxinit'): + + + self.assertEqual(self.dut.MSK_Init.txrxinit.rdl_desc, "0 -\u003e Normal modem operation \n1 -\u003e Initialize Tx and Rx") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.MSK_Init.txinit'): + + + self.assertEqual(self.dut.MSK_Init.txinit.rdl_desc, "0 -\u003e Normal Tx operation \n1 -\u003e Initialize Tx") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.MSK_Init.rxinit'): + + + self.assertEqual(self.dut.MSK_Init.rxinit.rdl_desc, "0 -\u003e Normal Rx operation \n1 -\u003e Initialize Rx") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.MSK_Control.ptt'): + + + self.assertEqual(self.dut.MSK_Control.ptt.rdl_desc, "0 -\u003e PTT Disabled\n1 -\u003e PTT Enabled") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.MSK_Control.loopback_ena'): + + + self.assertEqual(self.dut.MSK_Control.loopback_ena.rdl_desc, "0 -\u003e Modem loopback disabled\n1 -\u003e Modem loopback enabled") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.MSK_Control.rx_invert'): + + + self.assertEqual(self.dut.MSK_Control.rx_invert.rdl_desc, "0 -\u003e Rx data normal\n1 -\u003e Rx data inverted") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.MSK_Control.clear_counts'): + + + self.assertEqual(self.dut.MSK_Control.clear_counts.rdl_desc, "Clear Tx Bit Counter and Tx Enable Counter") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.MSK_Control.diff_encoder_loopback'): + + + self.assertEqual(self.dut.MSK_Control.diff_encoder_loopback.rdl_desc, "0 -\u003e Differential Encoder -\u003e Decoder loopback disabled\n1 -\u003e Differential Encoder -\u003e Decoder loopback enabled") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.MSK_Status.demod_sync_lock'): + + + self.assertEqual(self.dut.MSK_Status.demod_sync_lock.rdl_desc, "Demodulator Sync Status - not currently implemented") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.MSK_Status.tx_enable'): + + + self.assertEqual(self.dut.MSK_Status.tx_enable.rdl_desc, "1 -\u003e Data to DAC Enabled\n0 -\u003e Data to DAC Disabled") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.MSK_Status.rx_enable'): + + + self.assertEqual(self.dut.MSK_Status.rx_enable.rdl_desc, "1 -\u003e Data from ADC Enabled\n0 -\u003e Data from ADC Disabled") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.MSK_Status.tx_axis_valid'): + + + self.assertEqual(self.dut.MSK_Status.tx_axis_valid.rdl_desc, "1 -\u003e S_AXIS_VALID Enabled\n0 -\u003e S_AXIS_VALID Disabled") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.Tx_Bit_Count.tx_bit_counter'): + + + self.assertEqual(self.dut.Tx_Bit_Count.tx_bit_counter.rdl_desc, "Count of data requests made by modem") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.Tx_Enable_Count.tx_ena_counter'): + + + self.assertEqual(self.dut.Tx_Enable_Count.tx_ena_counter.rdl_desc, "Number of clocks on which Tx Enable is active") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.Fb_FreqWord.config_data'): + + + self.assertEqual(self.dut.Fb_FreqWord.config_data.rdl_desc, "Sets the center frequency of the NCO as FW = Fn * 2^32/Fs, \nwhere Fn is the desired NCO frequency, and Fs is the NCO sample rate") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.TX_F1_FreqWord.config_data'): + + + self.assertEqual(self.dut.TX_F1_FreqWord.config_data.rdl_desc, "Sets the center frequency of the NCO as FW = Fn * 2^32/Fs, \nwhere Fn is the desired NCO frequency, and Fs is the NCO sample rate") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.TX_F2_FreqWord.config_data'): + + + self.assertEqual(self.dut.TX_F2_FreqWord.config_data.rdl_desc, "Sets the center frequency of the NCO as FW = Fn * 2^32/Fs, \nwhere Fn is the desired NCO frequency, and Fs is the NCO sample rate") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.RX_F1_FreqWord.config_data'): + + + self.assertEqual(self.dut.RX_F1_FreqWord.config_data.rdl_desc, "Sets the center frequency of the NCO as FW = Fn * 2^32/Fs, \nwhere Fn is the desired NCO frequency, and Fs is the NCO sample rate") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.RX_F2_FreqWord.config_data'): + + + self.assertEqual(self.dut.RX_F2_FreqWord.config_data.rdl_desc, "Sets the center frequency of the NCO as FW = Fn * 2^32/Fs, \nwhere Fn is the desired NCO frequency, and Fs is the NCO sample rate") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.LPF_Config_0.lpf_freeze'): + + + self.assertEqual(self.dut.LPF_Config_0.lpf_freeze.rdl_desc, "0 -\u003e Normal operation\n1 -\u003e Freeze current value") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.LPF_Config_0.lpf_zero'): + + + self.assertEqual(self.dut.LPF_Config_0.lpf_zero.rdl_desc, "0 -\u003e Normal operation\n1 -\u003e Zero and hold accumulator") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.LPF_Config_0.prbs_reserved'): + + + self.assertIsNone(self.dut.LPF_Config_0.prbs_reserved.rdl_desc) # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.LPF_Config_0.lpf_alpha'): + + + self.assertEqual(self.dut.LPF_Config_0.lpf_alpha.rdl_desc, "Value controls the filter rolloff") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.LPF_Config_1.i_gain'): + + + self.assertEqual(self.dut.LPF_Config_1.i_gain.rdl_desc, "Value m of 0-16,777,215 sets the integral multiplier") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.LPF_Config_1.i_shift'): + + + self.assertEqual(self.dut.LPF_Config_1.i_shift.rdl_desc, "Value n of 0-32 sets the integral divisor as 2^-n") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.Tx_Data_Width.data_width'): + + + self.assertEqual(self.dut.Tx_Data_Width.data_width.rdl_desc, "Set the data width of the modem input/output") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.Rx_Data_Width.data_width'): + + + self.assertEqual(self.dut.Rx_Data_Width.data_width.rdl_desc, "Set the data width of the modem input/output") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.PRBS_Control.prbs_sel'): + + + self.assertEqual(self.dut.PRBS_Control.prbs_sel.rdl_desc, "0 -\u003e Select Normal Tx Data\n1 -\u003e Select PRBS Tx Data") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.PRBS_Control.prbs_error_insert'): + + + self.assertEqual(self.dut.PRBS_Control.prbs_error_insert.rdl_desc, "0 -\u003e 1 : Insert bit error in Tx data (both Normal and PRBS)\n1 -\u003e 0 : Insert bit error in Tx data (both Normal and PRBS)") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.PRBS_Control.prbs_clear'): + + + self.assertEqual(self.dut.PRBS_Control.prbs_clear.rdl_desc, "0 -\u003e 1 : Clear PRBS Counters\n1 -\u003e 0 : Clear PRBS Counters") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.PRBS_Control.prbs_manual_sync'): + + + self.assertEqual(self.dut.PRBS_Control.prbs_manual_sync.rdl_desc, "0 -\u003e 1 : Synchronize PRBS monitor\n1 -\u003e 0 : Synchronize PRBS monitor") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.PRBS_Control.prbs_reserved'): + + + self.assertIsNone(self.dut.PRBS_Control.prbs_reserved.rdl_desc) # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.PRBS_Control.prbs_sync_threshold'): + + + self.assertEqual(self.dut.PRBS_Control.prbs_sync_threshold.rdl_desc, "0 : Auto Sync Disabled\nN \u003e 0 : Auto sync after N errors") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.PRBS_Initial_State.config_data'): + + + self.assertEqual(self.dut.PRBS_Initial_State.config_data.rdl_desc, "Sets the starting value of the PRBS generator") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.PRBS_Polynomial.config_data'): + + + self.assertEqual(self.dut.PRBS_Polynomial.config_data.rdl_desc, "Bit positions set to \u00271\u0027 indicate polynomial feedback positions") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.PRBS_Error_Mask.config_data'): + + + self.assertEqual(self.dut.PRBS_Error_Mask.config_data.rdl_desc, "Bit positions set to \u00271\u0027 indicate bits that are inverted when a bit error is inserted") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.PRBS_Bit_Count.status_data'): + + + self.assertEqual(self.dut.PRBS_Bit_Count.status_data.rdl_desc, "Number of bits received by the PRBS monitor since last\nBER can be calculated as the ratio of received bits to errored-bits") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.PRBS_Error_Count.status_data'): + + + self.assertEqual(self.dut.PRBS_Error_Count.status_data.rdl_desc, "Number of errored-bits received by the PRBS monitor since last sync\nBER can be calculated as the ratio of received bits to errored-bits") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.LPF_Accum_F1.status_data'): + + + self.assertEqual(self.dut.LPF_Accum_F1.status_data.rdl_desc, "PI Controller Accumulator Value") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.LPF_Accum_F2.status_data'): + + + self.assertEqual(self.dut.LPF_Accum_F2.status_data.rdl_desc, "PI Controller Accumulator Value") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.axis_xfer_count.xfer_count'): + + + self.assertEqual(self.dut.axis_xfer_count.xfer_count.rdl_desc, "Number completed S_AXIS transfers") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.Rx_Sample_Discard.rx_sample_discard'): + + + self.assertEqual(self.dut.Rx_Sample_Discard.rx_sample_discard.rdl_desc, "Number of Rx samples to discard") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.Rx_Sample_Discard.rx_nco_discard'): + + + self.assertEqual(self.dut.Rx_Sample_Discard.rx_nco_discard.rdl_desc, "Number of NCO samples to discard") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.LPF_Config_2.p_gain'): + + + self.assertEqual(self.dut.LPF_Config_2.p_gain.rdl_desc, "Value m of 0-16,777,215 sets the proportional multiplier") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.LPF_Config_2.p_shift'): + + + self.assertEqual(self.dut.LPF_Config_2.p_shift.rdl_desc, "Value n of 0-32 sets the proportional divisor as 2^-n") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.f1_nco_adjust.data'): + + + self.assertEqual(self.dut.f1_nco_adjust.data.rdl_desc, "Frequency offet applied to the F1 NCO") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.f2_nco_adjust.data'): + + + self.assertEqual(self.dut.f2_nco_adjust.data.rdl_desc, "Frequency offet applied to the F2 NCO") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.f1_error.data'): + + + self.assertEqual(self.dut.f1_error.data.rdl_desc, "Error value of the F1 Costas loop after each active bit period") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.f2_error.data'): + + + self.assertEqual(self.dut.f2_error.data.rdl_desc, "Error value of the F2 Costas loop after each active bit period") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.Tx_Sync_Ctrl.tx_sync_ena'): + + + self.assertEqual(self.dut.Tx_Sync_Ctrl.tx_sync_ena.rdl_desc, "0 -\u003e Disable sync transmission\n1 -\u003e Enable sync transmission when PTT is asserted") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.Tx_Sync_Ctrl.tx_sync_force'): + + + self.assertEqual(self.dut.Tx_Sync_Ctrl.tx_sync_force.rdl_desc, "0 : Normal operation)\n1 : Transmit synchronization pattern)") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.Tx_Sync_Ctrl.tx_sync_f1'): + + + self.assertEqual(self.dut.Tx_Sync_Ctrl.tx_sync_f1.rdl_desc, "Enables/Disables transmission of F1 tone for receiver synchronization\n0 : F1 tone transmission disabled\n1 : F1 tone transmission enabled\nBoth F1 and F2 can be enabled at the same time") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.Tx_Sync_Ctrl.tx_sync_f2'): + + + self.assertEqual(self.dut.Tx_Sync_Ctrl.tx_sync_f2.rdl_desc, "Enables/Disables transmission of F2 tone for receiver synchronization\n0 : F2 tone transmission disabled\n1 : F2 tone transmission enabled\nBoth F1 and F2 can be enabled at the same time") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.Tx_Sync_Cnt.tx_sync_cnt'): + + + self.assertEqual(self.dut.Tx_Sync_Cnt.tx_sync_cnt.rdl_desc, "Value from 0x00_0000 to 0xFF_FFFF. \nThis value represents the number bit-times the synchronization \nsignal should be sent after PTT is asserted.") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.lowpass_ema_alpha1.alpha'): + + + self.assertEqual(self.dut.lowpass_ema_alpha1.alpha.rdl_desc, "Value from 0x0_0000 to 0x3_FFFF represent the EMA alpha") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.lowpass_ema_alpha2.alpha'): + + + self.assertEqual(self.dut.lowpass_ema_alpha2.alpha.rdl_desc, "Value from 0x0_0000 to 0x3_FFFF represent the EMA alpha") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.rx_power.rx_power'): + + + self.assertEqual(self.dut.rx_power.rx_power.rdl_desc, "Value that represent the RMS power of the incoming I;") # type: ignore[union-attr] + + + + + + def test_sizes(self) -> None: + """ + Check that the sizes all match + """ + with self.subTest(msg='node: msk_top_regs.Hash_ID_Low'): + self.assertEqual(self.dut.Hash_ID_Low.size, 4) # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.Hash_ID_High'): + self.assertEqual(self.dut.Hash_ID_High.size, 4) # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.MSK_Init'): + self.assertEqual(self.dut.MSK_Init.size, 4) # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.MSK_Control'): + self.assertEqual(self.dut.MSK_Control.size, 4) # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.MSK_Status'): + self.assertEqual(self.dut.MSK_Status.size, 4) # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.Tx_Bit_Count'): + self.assertEqual(self.dut.Tx_Bit_Count.size, 4) # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.Tx_Enable_Count'): + self.assertEqual(self.dut.Tx_Enable_Count.size, 4) # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.Fb_FreqWord'): + self.assertEqual(self.dut.Fb_FreqWord.size, 4) # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.TX_F1_FreqWord'): + self.assertEqual(self.dut.TX_F1_FreqWord.size, 4) # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.TX_F2_FreqWord'): + self.assertEqual(self.dut.TX_F2_FreqWord.size, 4) # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.RX_F1_FreqWord'): + self.assertEqual(self.dut.RX_F1_FreqWord.size, 4) # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.RX_F2_FreqWord'): + self.assertEqual(self.dut.RX_F2_FreqWord.size, 4) # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.LPF_Config_0'): + self.assertEqual(self.dut.LPF_Config_0.size, 4) # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.LPF_Config_1'): + self.assertEqual(self.dut.LPF_Config_1.size, 4) # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.Tx_Data_Width'): + self.assertEqual(self.dut.Tx_Data_Width.size, 4) # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.Rx_Data_Width'): + self.assertEqual(self.dut.Rx_Data_Width.size, 4) # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.PRBS_Control'): + self.assertEqual(self.dut.PRBS_Control.size, 4) # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.PRBS_Initial_State'): + self.assertEqual(self.dut.PRBS_Initial_State.size, 4) # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.PRBS_Polynomial'): + self.assertEqual(self.dut.PRBS_Polynomial.size, 4) # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.PRBS_Error_Mask'): + self.assertEqual(self.dut.PRBS_Error_Mask.size, 4) # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.PRBS_Bit_Count'): + self.assertEqual(self.dut.PRBS_Bit_Count.size, 4) # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.PRBS_Error_Count'): + self.assertEqual(self.dut.PRBS_Error_Count.size, 4) # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.LPF_Accum_F1'): + self.assertEqual(self.dut.LPF_Accum_F1.size, 4) # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.LPF_Accum_F2'): + self.assertEqual(self.dut.LPF_Accum_F2.size, 4) # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.axis_xfer_count'): + self.assertEqual(self.dut.axis_xfer_count.size, 4) # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.Rx_Sample_Discard'): + self.assertEqual(self.dut.Rx_Sample_Discard.size, 4) # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.LPF_Config_2'): + self.assertEqual(self.dut.LPF_Config_2.size, 4) # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.f1_nco_adjust'): + self.assertEqual(self.dut.f1_nco_adjust.size, 4) # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.f2_nco_adjust'): + self.assertEqual(self.dut.f2_nco_adjust.size, 4) # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.f1_error'): + self.assertEqual(self.dut.f1_error.size, 4) # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.f2_error'): + self.assertEqual(self.dut.f2_error.size, 4) # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.Tx_Sync_Ctrl'): + self.assertEqual(self.dut.Tx_Sync_Ctrl.size, 4) # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.Tx_Sync_Cnt'): + self.assertEqual(self.dut.Tx_Sync_Cnt.size, 4) # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.lowpass_ema_alpha1'): + self.assertEqual(self.dut.lowpass_ema_alpha1.size, 4) # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.lowpass_ema_alpha2'): + self.assertEqual(self.dut.lowpass_ema_alpha2.size, 4) # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.rx_power'): + self.assertEqual(self.dut.rx_power.size, 4) # type: ignore[union-attr] + + + # check the size of the address map itself + + with self.subTest(msg='node: msk_top_regs'): + self.assertEqual(self.dut.size, 144) # type: ignore[union-attr] + + + + def test_register_properties(self) -> None: + """ + Walk the address map and check the address, size and accesswidth of every register is + correct + """ + with self.subTest(msg='register: msk_top_regs.Hash_ID_Low'): + self.assertEqual(self.dut.Hash_ID_Low.address, 0) # type: ignore[union-attr] + self.assertEqual(self.dut.Hash_ID_Low.width, 32) # type: ignore[union-attr] + self.assertEqual(self.dut.Hash_ID_Low.size, 4) # type: ignore[union-attr] + self.assertEqual(self.dut.Hash_ID_Low.accesswidth, 32) # type: ignore[union-attr] + with self.subTest(msg='register: msk_top_regs.Hash_ID_High'): + self.assertEqual(self.dut.Hash_ID_High.address, 4) # type: ignore[union-attr] + self.assertEqual(self.dut.Hash_ID_High.width, 32) # type: ignore[union-attr] + self.assertEqual(self.dut.Hash_ID_High.size, 4) # type: ignore[union-attr] + self.assertEqual(self.dut.Hash_ID_High.accesswidth, 32) # type: ignore[union-attr] + with self.subTest(msg='register: msk_top_regs.MSK_Init'): + self.assertEqual(self.dut.MSK_Init.address, 8) # type: ignore[union-attr] + self.assertEqual(self.dut.MSK_Init.width, 32) # type: ignore[union-attr] + self.assertEqual(self.dut.MSK_Init.size, 4) # type: ignore[union-attr] + self.assertEqual(self.dut.MSK_Init.accesswidth, 32) # type: ignore[union-attr] + with self.subTest(msg='register: msk_top_regs.MSK_Control'): + self.assertEqual(self.dut.MSK_Control.address, 12) # type: ignore[union-attr] + self.assertEqual(self.dut.MSK_Control.width, 32) # type: ignore[union-attr] + self.assertEqual(self.dut.MSK_Control.size, 4) # type: ignore[union-attr] + self.assertEqual(self.dut.MSK_Control.accesswidth, 32) # type: ignore[union-attr] + with self.subTest(msg='register: msk_top_regs.MSK_Status'): + self.assertEqual(self.dut.MSK_Status.address, 16) # type: ignore[union-attr] + self.assertEqual(self.dut.MSK_Status.width, 32) # type: ignore[union-attr] + self.assertEqual(self.dut.MSK_Status.size, 4) # type: ignore[union-attr] + self.assertEqual(self.dut.MSK_Status.accesswidth, 32) # type: ignore[union-attr] + with self.subTest(msg='register: msk_top_regs.Tx_Bit_Count'): + self.assertEqual(self.dut.Tx_Bit_Count.address, 20) # type: ignore[union-attr] + self.assertEqual(self.dut.Tx_Bit_Count.width, 32) # type: ignore[union-attr] + self.assertEqual(self.dut.Tx_Bit_Count.size, 4) # type: ignore[union-attr] + self.assertEqual(self.dut.Tx_Bit_Count.accesswidth, 32) # type: ignore[union-attr] + with self.subTest(msg='register: msk_top_regs.Tx_Enable_Count'): + self.assertEqual(self.dut.Tx_Enable_Count.address, 24) # type: ignore[union-attr] + self.assertEqual(self.dut.Tx_Enable_Count.width, 32) # type: ignore[union-attr] + self.assertEqual(self.dut.Tx_Enable_Count.size, 4) # type: ignore[union-attr] + self.assertEqual(self.dut.Tx_Enable_Count.accesswidth, 32) # type: ignore[union-attr] + with self.subTest(msg='register: msk_top_regs.Fb_FreqWord'): + self.assertEqual(self.dut.Fb_FreqWord.address, 28) # type: ignore[union-attr] + self.assertEqual(self.dut.Fb_FreqWord.width, 32) # type: ignore[union-attr] + self.assertEqual(self.dut.Fb_FreqWord.size, 4) # type: ignore[union-attr] + self.assertEqual(self.dut.Fb_FreqWord.accesswidth, 32) # type: ignore[union-attr] + with self.subTest(msg='register: msk_top_regs.TX_F1_FreqWord'): + self.assertEqual(self.dut.TX_F1_FreqWord.address, 32) # type: ignore[union-attr] + self.assertEqual(self.dut.TX_F1_FreqWord.width, 32) # type: ignore[union-attr] + self.assertEqual(self.dut.TX_F1_FreqWord.size, 4) # type: ignore[union-attr] + self.assertEqual(self.dut.TX_F1_FreqWord.accesswidth, 32) # type: ignore[union-attr] + with self.subTest(msg='register: msk_top_regs.TX_F2_FreqWord'): + self.assertEqual(self.dut.TX_F2_FreqWord.address, 36) # type: ignore[union-attr] + self.assertEqual(self.dut.TX_F2_FreqWord.width, 32) # type: ignore[union-attr] + self.assertEqual(self.dut.TX_F2_FreqWord.size, 4) # type: ignore[union-attr] + self.assertEqual(self.dut.TX_F2_FreqWord.accesswidth, 32) # type: ignore[union-attr] + with self.subTest(msg='register: msk_top_regs.RX_F1_FreqWord'): + self.assertEqual(self.dut.RX_F1_FreqWord.address, 40) # type: ignore[union-attr] + self.assertEqual(self.dut.RX_F1_FreqWord.width, 32) # type: ignore[union-attr] + self.assertEqual(self.dut.RX_F1_FreqWord.size, 4) # type: ignore[union-attr] + self.assertEqual(self.dut.RX_F1_FreqWord.accesswidth, 32) # type: ignore[union-attr] + with self.subTest(msg='register: msk_top_regs.RX_F2_FreqWord'): + self.assertEqual(self.dut.RX_F2_FreqWord.address, 44) # type: ignore[union-attr] + self.assertEqual(self.dut.RX_F2_FreqWord.width, 32) # type: ignore[union-attr] + self.assertEqual(self.dut.RX_F2_FreqWord.size, 4) # type: ignore[union-attr] + self.assertEqual(self.dut.RX_F2_FreqWord.accesswidth, 32) # type: ignore[union-attr] + with self.subTest(msg='register: msk_top_regs.LPF_Config_0'): + self.assertEqual(self.dut.LPF_Config_0.address, 48) # type: ignore[union-attr] + self.assertEqual(self.dut.LPF_Config_0.width, 32) # type: ignore[union-attr] + self.assertEqual(self.dut.LPF_Config_0.size, 4) # type: ignore[union-attr] + self.assertEqual(self.dut.LPF_Config_0.accesswidth, 32) # type: ignore[union-attr] + with self.subTest(msg='register: msk_top_regs.LPF_Config_1'): + self.assertEqual(self.dut.LPF_Config_1.address, 52) # type: ignore[union-attr] + self.assertEqual(self.dut.LPF_Config_1.width, 32) # type: ignore[union-attr] + self.assertEqual(self.dut.LPF_Config_1.size, 4) # type: ignore[union-attr] + self.assertEqual(self.dut.LPF_Config_1.accesswidth, 32) # type: ignore[union-attr] + with self.subTest(msg='register: msk_top_regs.Tx_Data_Width'): + self.assertEqual(self.dut.Tx_Data_Width.address, 56) # type: ignore[union-attr] + self.assertEqual(self.dut.Tx_Data_Width.width, 32) # type: ignore[union-attr] + self.assertEqual(self.dut.Tx_Data_Width.size, 4) # type: ignore[union-attr] + self.assertEqual(self.dut.Tx_Data_Width.accesswidth, 32) # type: ignore[union-attr] + with self.subTest(msg='register: msk_top_regs.Rx_Data_Width'): + self.assertEqual(self.dut.Rx_Data_Width.address, 60) # type: ignore[union-attr] + self.assertEqual(self.dut.Rx_Data_Width.width, 32) # type: ignore[union-attr] + self.assertEqual(self.dut.Rx_Data_Width.size, 4) # type: ignore[union-attr] + self.assertEqual(self.dut.Rx_Data_Width.accesswidth, 32) # type: ignore[union-attr] + with self.subTest(msg='register: msk_top_regs.PRBS_Control'): + self.assertEqual(self.dut.PRBS_Control.address, 64) # type: ignore[union-attr] + self.assertEqual(self.dut.PRBS_Control.width, 32) # type: ignore[union-attr] + self.assertEqual(self.dut.PRBS_Control.size, 4) # type: ignore[union-attr] + self.assertEqual(self.dut.PRBS_Control.accesswidth, 32) # type: ignore[union-attr] + with self.subTest(msg='register: msk_top_regs.PRBS_Initial_State'): + self.assertEqual(self.dut.PRBS_Initial_State.address, 68) # type: ignore[union-attr] + self.assertEqual(self.dut.PRBS_Initial_State.width, 32) # type: ignore[union-attr] + self.assertEqual(self.dut.PRBS_Initial_State.size, 4) # type: ignore[union-attr] + self.assertEqual(self.dut.PRBS_Initial_State.accesswidth, 32) # type: ignore[union-attr] + with self.subTest(msg='register: msk_top_regs.PRBS_Polynomial'): + self.assertEqual(self.dut.PRBS_Polynomial.address, 72) # type: ignore[union-attr] + self.assertEqual(self.dut.PRBS_Polynomial.width, 32) # type: ignore[union-attr] + self.assertEqual(self.dut.PRBS_Polynomial.size, 4) # type: ignore[union-attr] + self.assertEqual(self.dut.PRBS_Polynomial.accesswidth, 32) # type: ignore[union-attr] + with self.subTest(msg='register: msk_top_regs.PRBS_Error_Mask'): + self.assertEqual(self.dut.PRBS_Error_Mask.address, 76) # type: ignore[union-attr] + self.assertEqual(self.dut.PRBS_Error_Mask.width, 32) # type: ignore[union-attr] + self.assertEqual(self.dut.PRBS_Error_Mask.size, 4) # type: ignore[union-attr] + self.assertEqual(self.dut.PRBS_Error_Mask.accesswidth, 32) # type: ignore[union-attr] + with self.subTest(msg='register: msk_top_regs.PRBS_Bit_Count'): + self.assertEqual(self.dut.PRBS_Bit_Count.address, 80) # type: ignore[union-attr] + self.assertEqual(self.dut.PRBS_Bit_Count.width, 32) # type: ignore[union-attr] + self.assertEqual(self.dut.PRBS_Bit_Count.size, 4) # type: ignore[union-attr] + self.assertEqual(self.dut.PRBS_Bit_Count.accesswidth, 32) # type: ignore[union-attr] + with self.subTest(msg='register: msk_top_regs.PRBS_Error_Count'): + self.assertEqual(self.dut.PRBS_Error_Count.address, 84) # type: ignore[union-attr] + self.assertEqual(self.dut.PRBS_Error_Count.width, 32) # type: ignore[union-attr] + self.assertEqual(self.dut.PRBS_Error_Count.size, 4) # type: ignore[union-attr] + self.assertEqual(self.dut.PRBS_Error_Count.accesswidth, 32) # type: ignore[union-attr] + with self.subTest(msg='register: msk_top_regs.LPF_Accum_F1'): + self.assertEqual(self.dut.LPF_Accum_F1.address, 88) # type: ignore[union-attr] + self.assertEqual(self.dut.LPF_Accum_F1.width, 32) # type: ignore[union-attr] + self.assertEqual(self.dut.LPF_Accum_F1.size, 4) # type: ignore[union-attr] + self.assertEqual(self.dut.LPF_Accum_F1.accesswidth, 32) # type: ignore[union-attr] + with self.subTest(msg='register: msk_top_regs.LPF_Accum_F2'): + self.assertEqual(self.dut.LPF_Accum_F2.address, 92) # type: ignore[union-attr] + self.assertEqual(self.dut.LPF_Accum_F2.width, 32) # type: ignore[union-attr] + self.assertEqual(self.dut.LPF_Accum_F2.size, 4) # type: ignore[union-attr] + self.assertEqual(self.dut.LPF_Accum_F2.accesswidth, 32) # type: ignore[union-attr] + with self.subTest(msg='register: msk_top_regs.axis_xfer_count'): + self.assertEqual(self.dut.axis_xfer_count.address, 96) # type: ignore[union-attr] + self.assertEqual(self.dut.axis_xfer_count.width, 32) # type: ignore[union-attr] + self.assertEqual(self.dut.axis_xfer_count.size, 4) # type: ignore[union-attr] + self.assertEqual(self.dut.axis_xfer_count.accesswidth, 32) # type: ignore[union-attr] + with self.subTest(msg='register: msk_top_regs.Rx_Sample_Discard'): + self.assertEqual(self.dut.Rx_Sample_Discard.address, 100) # type: ignore[union-attr] + self.assertEqual(self.dut.Rx_Sample_Discard.width, 32) # type: ignore[union-attr] + self.assertEqual(self.dut.Rx_Sample_Discard.size, 4) # type: ignore[union-attr] + self.assertEqual(self.dut.Rx_Sample_Discard.accesswidth, 32) # type: ignore[union-attr] + with self.subTest(msg='register: msk_top_regs.LPF_Config_2'): + self.assertEqual(self.dut.LPF_Config_2.address, 104) # type: ignore[union-attr] + self.assertEqual(self.dut.LPF_Config_2.width, 32) # type: ignore[union-attr] + self.assertEqual(self.dut.LPF_Config_2.size, 4) # type: ignore[union-attr] + self.assertEqual(self.dut.LPF_Config_2.accesswidth, 32) # type: ignore[union-attr] + with self.subTest(msg='register: msk_top_regs.f1_nco_adjust'): + self.assertEqual(self.dut.f1_nco_adjust.address, 108) # type: ignore[union-attr] + self.assertEqual(self.dut.f1_nco_adjust.width, 32) # type: ignore[union-attr] + self.assertEqual(self.dut.f1_nco_adjust.size, 4) # type: ignore[union-attr] + self.assertEqual(self.dut.f1_nco_adjust.accesswidth, 32) # type: ignore[union-attr] + with self.subTest(msg='register: msk_top_regs.f2_nco_adjust'): + self.assertEqual(self.dut.f2_nco_adjust.address, 112) # type: ignore[union-attr] + self.assertEqual(self.dut.f2_nco_adjust.width, 32) # type: ignore[union-attr] + self.assertEqual(self.dut.f2_nco_adjust.size, 4) # type: ignore[union-attr] + self.assertEqual(self.dut.f2_nco_adjust.accesswidth, 32) # type: ignore[union-attr] + with self.subTest(msg='register: msk_top_regs.f1_error'): + self.assertEqual(self.dut.f1_error.address, 116) # type: ignore[union-attr] + self.assertEqual(self.dut.f1_error.width, 32) # type: ignore[union-attr] + self.assertEqual(self.dut.f1_error.size, 4) # type: ignore[union-attr] + self.assertEqual(self.dut.f1_error.accesswidth, 32) # type: ignore[union-attr] + with self.subTest(msg='register: msk_top_regs.f2_error'): + self.assertEqual(self.dut.f2_error.address, 120) # type: ignore[union-attr] + self.assertEqual(self.dut.f2_error.width, 32) # type: ignore[union-attr] + self.assertEqual(self.dut.f2_error.size, 4) # type: ignore[union-attr] + self.assertEqual(self.dut.f2_error.accesswidth, 32) # type: ignore[union-attr] + with self.subTest(msg='register: msk_top_regs.Tx_Sync_Ctrl'): + self.assertEqual(self.dut.Tx_Sync_Ctrl.address, 124) # type: ignore[union-attr] + self.assertEqual(self.dut.Tx_Sync_Ctrl.width, 32) # type: ignore[union-attr] + self.assertEqual(self.dut.Tx_Sync_Ctrl.size, 4) # type: ignore[union-attr] + self.assertEqual(self.dut.Tx_Sync_Ctrl.accesswidth, 32) # type: ignore[union-attr] + with self.subTest(msg='register: msk_top_regs.Tx_Sync_Cnt'): + self.assertEqual(self.dut.Tx_Sync_Cnt.address, 128) # type: ignore[union-attr] + self.assertEqual(self.dut.Tx_Sync_Cnt.width, 32) # type: ignore[union-attr] + self.assertEqual(self.dut.Tx_Sync_Cnt.size, 4) # type: ignore[union-attr] + self.assertEqual(self.dut.Tx_Sync_Cnt.accesswidth, 32) # type: ignore[union-attr] + with self.subTest(msg='register: msk_top_regs.lowpass_ema_alpha1'): + self.assertEqual(self.dut.lowpass_ema_alpha1.address, 132) # type: ignore[union-attr] + self.assertEqual(self.dut.lowpass_ema_alpha1.width, 32) # type: ignore[union-attr] + self.assertEqual(self.dut.lowpass_ema_alpha1.size, 4) # type: ignore[union-attr] + self.assertEqual(self.dut.lowpass_ema_alpha1.accesswidth, 32) # type: ignore[union-attr] + with self.subTest(msg='register: msk_top_regs.lowpass_ema_alpha2'): + self.assertEqual(self.dut.lowpass_ema_alpha2.address, 136) # type: ignore[union-attr] + self.assertEqual(self.dut.lowpass_ema_alpha2.width, 32) # type: ignore[union-attr] + self.assertEqual(self.dut.lowpass_ema_alpha2.size, 4) # type: ignore[union-attr] + self.assertEqual(self.dut.lowpass_ema_alpha2.accesswidth, 32) # type: ignore[union-attr] + with self.subTest(msg='register: msk_top_regs.rx_power'): + self.assertEqual(self.dut.rx_power.address, 140) # type: ignore[union-attr] + self.assertEqual(self.dut.rx_power.width, 32) # type: ignore[union-attr] + self.assertEqual(self.dut.rx_power.size, 4) # type: ignore[union-attr] + self.assertEqual(self.dut.rx_power.accesswidth, 32) # type: ignore[union-attr] + + + def test_memory_properties(self) -> None: + """ + Walk the address map and check the address, size and accesswidth of every memory is + correct + """ + mut: AsyncMemory + + + def test_field_properties(self) -> None: + """ + walk the address map and check: + - that the lsb and msb of every field is correct + - that where default values are provided they are applied correctly + """ + fut:Field + with self.subTest(msg='field: msk_top_regs.Hash_ID_Low.hash_id_lo'): + # test properties of field: msk_top_regs.Hash_ID_Low.hash_id_lo + fut = self.dut.Hash_ID_Low.hash_id_lo # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,0) + self.assertEqual(fut.msb,31) + self.assertEqual(fut.low,0) + self.assertEqual(fut.high,31) + self.assertEqual(fut.bitmask,0xFFFFFFFF) + self.assertEqual(fut.inverse_bitmask,0x0) + self.assertEqual(fut.max_value,0xFFFFFFFF) + + self.assertEqual(fut.default,2863289685) + + self.assertEqual(fut.is_volatile,False) + with self.subTest(msg='field: msk_top_regs.Hash_ID_High.hash_id_hi'): + # test properties of field: msk_top_regs.Hash_ID_High.hash_id_hi + fut = self.dut.Hash_ID_High.hash_id_hi # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,0) + self.assertEqual(fut.msb,31) + self.assertEqual(fut.low,0) + self.assertEqual(fut.high,31) + self.assertEqual(fut.bitmask,0xFFFFFFFF) + self.assertEqual(fut.inverse_bitmask,0x0) + self.assertEqual(fut.max_value,0xFFFFFFFF) + + self.assertEqual(fut.default,1431677610) + + self.assertEqual(fut.is_volatile,False) + with self.subTest(msg='field: msk_top_regs.MSK_Init.txrxinit'): + # test properties of field: msk_top_regs.MSK_Init.txrxinit + fut = self.dut.MSK_Init.txrxinit # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,0) + self.assertEqual(fut.msb,0) + self.assertEqual(fut.low,0) + self.assertEqual(fut.high,0) + self.assertEqual(fut.bitmask,0x1) + self.assertEqual(fut.inverse_bitmask,0xFFFFFFFE) + self.assertEqual(fut.max_value,0x1) + + self.assertEqual(fut.default,1) + + self.assertEqual(fut.is_volatile,False) + with self.subTest(msg='field: msk_top_regs.MSK_Init.txinit'): + # test properties of field: msk_top_regs.MSK_Init.txinit + fut = self.dut.MSK_Init.txinit # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,1) + self.assertEqual(fut.msb,1) + self.assertEqual(fut.low,1) + self.assertEqual(fut.high,1) + self.assertEqual(fut.bitmask,0x2) + self.assertEqual(fut.inverse_bitmask,0xFFFFFFFD) + self.assertEqual(fut.max_value,0x1) + + self.assertEqual(fut.default,1) + + self.assertEqual(fut.is_volatile,False) + with self.subTest(msg='field: msk_top_regs.MSK_Init.rxinit'): + # test properties of field: msk_top_regs.MSK_Init.rxinit + fut = self.dut.MSK_Init.rxinit # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,2) + self.assertEqual(fut.msb,2) + self.assertEqual(fut.low,2) + self.assertEqual(fut.high,2) + self.assertEqual(fut.bitmask,0x4) + self.assertEqual(fut.inverse_bitmask,0xFFFFFFFB) + self.assertEqual(fut.max_value,0x1) + + self.assertEqual(fut.default,1) + + self.assertEqual(fut.is_volatile,False) + with self.subTest(msg='field: msk_top_regs.MSK_Control.ptt'): + # test properties of field: msk_top_regs.MSK_Control.ptt + fut = self.dut.MSK_Control.ptt # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,0) + self.assertEqual(fut.msb,0) + self.assertEqual(fut.low,0) + self.assertEqual(fut.high,0) + self.assertEqual(fut.bitmask,0x1) + self.assertEqual(fut.inverse_bitmask,0xFFFFFFFE) + self.assertEqual(fut.max_value,0x1) + + self.assertEqual(fut.default,0) + + self.assertEqual(fut.is_volatile,False) + with self.subTest(msg='field: msk_top_regs.MSK_Control.loopback_ena'): + # test properties of field: msk_top_regs.MSK_Control.loopback_ena + fut = self.dut.MSK_Control.loopback_ena # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,1) + self.assertEqual(fut.msb,1) + self.assertEqual(fut.low,1) + self.assertEqual(fut.high,1) + self.assertEqual(fut.bitmask,0x2) + self.assertEqual(fut.inverse_bitmask,0xFFFFFFFD) + self.assertEqual(fut.max_value,0x1) + + self.assertEqual(fut.default,0) + + self.assertEqual(fut.is_volatile,False) + with self.subTest(msg='field: msk_top_regs.MSK_Control.rx_invert'): + # test properties of field: msk_top_regs.MSK_Control.rx_invert + fut = self.dut.MSK_Control.rx_invert # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,2) + self.assertEqual(fut.msb,2) + self.assertEqual(fut.low,2) + self.assertEqual(fut.high,2) + self.assertEqual(fut.bitmask,0x4) + self.assertEqual(fut.inverse_bitmask,0xFFFFFFFB) + self.assertEqual(fut.max_value,0x1) + + self.assertEqual(fut.default,0) + + self.assertEqual(fut.is_volatile,False) + with self.subTest(msg='field: msk_top_regs.MSK_Control.clear_counts'): + # test properties of field: msk_top_regs.MSK_Control.clear_counts + fut = self.dut.MSK_Control.clear_counts # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,3) + self.assertEqual(fut.msb,3) + self.assertEqual(fut.low,3) + self.assertEqual(fut.high,3) + self.assertEqual(fut.bitmask,0x8) + self.assertEqual(fut.inverse_bitmask,0xFFFFFFF7) + self.assertEqual(fut.max_value,0x1) + + self.assertEqual(fut.default,0) + + self.assertEqual(fut.is_volatile,False) + with self.subTest(msg='field: msk_top_regs.MSK_Control.diff_encoder_loopback'): + # test properties of field: msk_top_regs.MSK_Control.diff_encoder_loopback + fut = self.dut.MSK_Control.diff_encoder_loopback # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,4) + self.assertEqual(fut.msb,4) + self.assertEqual(fut.low,4) + self.assertEqual(fut.high,4) + self.assertEqual(fut.bitmask,0x10) + self.assertEqual(fut.inverse_bitmask,0xFFFFFFEF) + self.assertEqual(fut.max_value,0x1) + + self.assertEqual(fut.default,0) + + self.assertEqual(fut.is_volatile,False) + with self.subTest(msg='field: msk_top_regs.MSK_Status.demod_sync_lock'): + # test properties of field: msk_top_regs.MSK_Status.demod_sync_lock + fut = self.dut.MSK_Status.demod_sync_lock # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,0) + self.assertEqual(fut.msb,0) + self.assertEqual(fut.low,0) + self.assertEqual(fut.high,0) + self.assertEqual(fut.bitmask,0x1) + self.assertEqual(fut.inverse_bitmask,0xFFFFFFFE) + self.assertEqual(fut.max_value,0x1) + + self.assertEqual(fut.default,0) + + self.assertEqual(fut.is_volatile,True) + with self.subTest(msg='field: msk_top_regs.MSK_Status.tx_enable'): + # test properties of field: msk_top_regs.MSK_Status.tx_enable + fut = self.dut.MSK_Status.tx_enable # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,1) + self.assertEqual(fut.msb,1) + self.assertEqual(fut.low,1) + self.assertEqual(fut.high,1) + self.assertEqual(fut.bitmask,0x2) + self.assertEqual(fut.inverse_bitmask,0xFFFFFFFD) + self.assertEqual(fut.max_value,0x1) + + self.assertEqual(fut.default,0) + + self.assertEqual(fut.is_volatile,True) + with self.subTest(msg='field: msk_top_regs.MSK_Status.rx_enable'): + # test properties of field: msk_top_regs.MSK_Status.rx_enable + fut = self.dut.MSK_Status.rx_enable # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,2) + self.assertEqual(fut.msb,2) + self.assertEqual(fut.low,2) + self.assertEqual(fut.high,2) + self.assertEqual(fut.bitmask,0x4) + self.assertEqual(fut.inverse_bitmask,0xFFFFFFFB) + self.assertEqual(fut.max_value,0x1) + + self.assertEqual(fut.default,0) + + self.assertEqual(fut.is_volatile,True) + with self.subTest(msg='field: msk_top_regs.MSK_Status.tx_axis_valid'): + # test properties of field: msk_top_regs.MSK_Status.tx_axis_valid + fut = self.dut.MSK_Status.tx_axis_valid # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,3) + self.assertEqual(fut.msb,3) + self.assertEqual(fut.low,3) + self.assertEqual(fut.high,3) + self.assertEqual(fut.bitmask,0x8) + self.assertEqual(fut.inverse_bitmask,0xFFFFFFF7) + self.assertEqual(fut.max_value,0x1) + + self.assertEqual(fut.default,0) + + self.assertEqual(fut.is_volatile,True) + with self.subTest(msg='field: msk_top_regs.Tx_Bit_Count.tx_bit_counter'): + # test properties of field: msk_top_regs.Tx_Bit_Count.tx_bit_counter + fut = self.dut.Tx_Bit_Count.tx_bit_counter # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,0) + self.assertEqual(fut.msb,31) + self.assertEqual(fut.low,0) + self.assertEqual(fut.high,31) + self.assertEqual(fut.bitmask,0xFFFFFFFF) + self.assertEqual(fut.inverse_bitmask,0x0) + self.assertEqual(fut.max_value,0xFFFFFFFF) + + self.assertEqual(fut.default,None) + + self.assertEqual(fut.is_volatile,True) + with self.subTest(msg='field: msk_top_regs.Tx_Enable_Count.tx_ena_counter'): + # test properties of field: msk_top_regs.Tx_Enable_Count.tx_ena_counter + fut = self.dut.Tx_Enable_Count.tx_ena_counter # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,0) + self.assertEqual(fut.msb,31) + self.assertEqual(fut.low,0) + self.assertEqual(fut.high,31) + self.assertEqual(fut.bitmask,0xFFFFFFFF) + self.assertEqual(fut.inverse_bitmask,0x0) + self.assertEqual(fut.max_value,0xFFFFFFFF) + + self.assertEqual(fut.default,0) + + self.assertEqual(fut.is_volatile,True) + with self.subTest(msg='field: msk_top_regs.Fb_FreqWord.config_data'): + # test properties of field: msk_top_regs.Fb_FreqWord.config_data + fut = self.dut.Fb_FreqWord.config_data # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,0) + self.assertEqual(fut.msb,31) + self.assertEqual(fut.low,0) + self.assertEqual(fut.high,31) + self.assertEqual(fut.bitmask,0xFFFFFFFF) + self.assertEqual(fut.inverse_bitmask,0x0) + self.assertEqual(fut.max_value,0xFFFFFFFF) + + self.assertEqual(fut.default,0) + + self.assertEqual(fut.is_volatile,False) + with self.subTest(msg='field: msk_top_regs.TX_F1_FreqWord.config_data'): + # test properties of field: msk_top_regs.TX_F1_FreqWord.config_data + fut = self.dut.TX_F1_FreqWord.config_data # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,0) + self.assertEqual(fut.msb,31) + self.assertEqual(fut.low,0) + self.assertEqual(fut.high,31) + self.assertEqual(fut.bitmask,0xFFFFFFFF) + self.assertEqual(fut.inverse_bitmask,0x0) + self.assertEqual(fut.max_value,0xFFFFFFFF) + + self.assertEqual(fut.default,0) + + self.assertEqual(fut.is_volatile,False) + with self.subTest(msg='field: msk_top_regs.TX_F2_FreqWord.config_data'): + # test properties of field: msk_top_regs.TX_F2_FreqWord.config_data + fut = self.dut.TX_F2_FreqWord.config_data # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,0) + self.assertEqual(fut.msb,31) + self.assertEqual(fut.low,0) + self.assertEqual(fut.high,31) + self.assertEqual(fut.bitmask,0xFFFFFFFF) + self.assertEqual(fut.inverse_bitmask,0x0) + self.assertEqual(fut.max_value,0xFFFFFFFF) + + self.assertEqual(fut.default,0) + + self.assertEqual(fut.is_volatile,False) + with self.subTest(msg='field: msk_top_regs.RX_F1_FreqWord.config_data'): + # test properties of field: msk_top_regs.RX_F1_FreqWord.config_data + fut = self.dut.RX_F1_FreqWord.config_data # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,0) + self.assertEqual(fut.msb,31) + self.assertEqual(fut.low,0) + self.assertEqual(fut.high,31) + self.assertEqual(fut.bitmask,0xFFFFFFFF) + self.assertEqual(fut.inverse_bitmask,0x0) + self.assertEqual(fut.max_value,0xFFFFFFFF) + + self.assertEqual(fut.default,0) + + self.assertEqual(fut.is_volatile,False) + with self.subTest(msg='field: msk_top_regs.RX_F2_FreqWord.config_data'): + # test properties of field: msk_top_regs.RX_F2_FreqWord.config_data + fut = self.dut.RX_F2_FreqWord.config_data # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,0) + self.assertEqual(fut.msb,31) + self.assertEqual(fut.low,0) + self.assertEqual(fut.high,31) + self.assertEqual(fut.bitmask,0xFFFFFFFF) + self.assertEqual(fut.inverse_bitmask,0x0) + self.assertEqual(fut.max_value,0xFFFFFFFF) + + self.assertEqual(fut.default,0) + + self.assertEqual(fut.is_volatile,False) + with self.subTest(msg='field: msk_top_regs.LPF_Config_0.lpf_freeze'): + # test properties of field: msk_top_regs.LPF_Config_0.lpf_freeze + fut = self.dut.LPF_Config_0.lpf_freeze # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,0) + self.assertEqual(fut.msb,0) + self.assertEqual(fut.low,0) + self.assertEqual(fut.high,0) + self.assertEqual(fut.bitmask,0x1) + self.assertEqual(fut.inverse_bitmask,0xFFFFFFFE) + self.assertEqual(fut.max_value,0x1) + + self.assertEqual(fut.default,0) + + self.assertEqual(fut.is_volatile,False) + with self.subTest(msg='field: msk_top_regs.LPF_Config_0.lpf_zero'): + # test properties of field: msk_top_regs.LPF_Config_0.lpf_zero + fut = self.dut.LPF_Config_0.lpf_zero # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,1) + self.assertEqual(fut.msb,1) + self.assertEqual(fut.low,1) + self.assertEqual(fut.high,1) + self.assertEqual(fut.bitmask,0x2) + self.assertEqual(fut.inverse_bitmask,0xFFFFFFFD) + self.assertEqual(fut.max_value,0x1) + + self.assertEqual(fut.default,0) + + self.assertEqual(fut.is_volatile,False) + with self.subTest(msg='field: msk_top_regs.LPF_Config_0.prbs_reserved'): + # test properties of field: msk_top_regs.LPF_Config_0.prbs_reserved + fut = self.dut.LPF_Config_0.prbs_reserved # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,2) + self.assertEqual(fut.msb,7) + self.assertEqual(fut.low,2) + self.assertEqual(fut.high,7) + self.assertEqual(fut.bitmask,0xFC) + self.assertEqual(fut.inverse_bitmask,0xFFFFFF03) + self.assertEqual(fut.max_value,0x3F) + + self.assertEqual(fut.default,0) + + self.assertEqual(fut.is_volatile,False) + with self.subTest(msg='field: msk_top_regs.LPF_Config_0.lpf_alpha'): + # test properties of field: msk_top_regs.LPF_Config_0.lpf_alpha + fut = self.dut.LPF_Config_0.lpf_alpha # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,8) + self.assertEqual(fut.msb,31) + self.assertEqual(fut.low,8) + self.assertEqual(fut.high,31) + self.assertEqual(fut.bitmask,0xFFFFFF00) + self.assertEqual(fut.inverse_bitmask,0xFF) + self.assertEqual(fut.max_value,0xFFFFFF) + + self.assertEqual(fut.default,0) + + self.assertEqual(fut.is_volatile,False) + with self.subTest(msg='field: msk_top_regs.LPF_Config_1.i_gain'): + # test properties of field: msk_top_regs.LPF_Config_1.i_gain + fut = self.dut.LPF_Config_1.i_gain # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,0) + self.assertEqual(fut.msb,23) + self.assertEqual(fut.low,0) + self.assertEqual(fut.high,23) + self.assertEqual(fut.bitmask,0xFFFFFF) + self.assertEqual(fut.inverse_bitmask,0xFF000000) + self.assertEqual(fut.max_value,0xFFFFFF) + + self.assertEqual(fut.default,0) + + self.assertEqual(fut.is_volatile,False) + with self.subTest(msg='field: msk_top_regs.LPF_Config_1.i_shift'): + # test properties of field: msk_top_regs.LPF_Config_1.i_shift + fut = self.dut.LPF_Config_1.i_shift # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,24) + self.assertEqual(fut.msb,31) + self.assertEqual(fut.low,24) + self.assertEqual(fut.high,31) + self.assertEqual(fut.bitmask,0xFF000000) + self.assertEqual(fut.inverse_bitmask,0xFFFFFF) + self.assertEqual(fut.max_value,0xFF) + + self.assertEqual(fut.default,0) + + self.assertEqual(fut.is_volatile,False) + with self.subTest(msg='field: msk_top_regs.Tx_Data_Width.data_width'): + # test properties of field: msk_top_regs.Tx_Data_Width.data_width + fut = self.dut.Tx_Data_Width.data_width # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,0) + self.assertEqual(fut.msb,7) + self.assertEqual(fut.low,0) + self.assertEqual(fut.high,7) + self.assertEqual(fut.bitmask,0xFF) + self.assertEqual(fut.inverse_bitmask,0xFFFFFF00) + self.assertEqual(fut.max_value,0xFF) + + self.assertEqual(fut.default,8) + + self.assertEqual(fut.is_volatile,False) + with self.subTest(msg='field: msk_top_regs.Rx_Data_Width.data_width'): + # test properties of field: msk_top_regs.Rx_Data_Width.data_width + fut = self.dut.Rx_Data_Width.data_width # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,0) + self.assertEqual(fut.msb,7) + self.assertEqual(fut.low,0) + self.assertEqual(fut.high,7) + self.assertEqual(fut.bitmask,0xFF) + self.assertEqual(fut.inverse_bitmask,0xFFFFFF00) + self.assertEqual(fut.max_value,0xFF) + + self.assertEqual(fut.default,8) + + self.assertEqual(fut.is_volatile,False) + with self.subTest(msg='field: msk_top_regs.PRBS_Control.prbs_sel'): + # test properties of field: msk_top_regs.PRBS_Control.prbs_sel + fut = self.dut.PRBS_Control.prbs_sel # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,0) + self.assertEqual(fut.msb,0) + self.assertEqual(fut.low,0) + self.assertEqual(fut.high,0) + self.assertEqual(fut.bitmask,0x1) + self.assertEqual(fut.inverse_bitmask,0xFFFFFFFE) + self.assertEqual(fut.max_value,0x1) + + self.assertEqual(fut.default,0) + + self.assertEqual(fut.is_volatile,False) + with self.subTest(msg='field: msk_top_regs.PRBS_Control.prbs_error_insert'): + # test properties of field: msk_top_regs.PRBS_Control.prbs_error_insert + fut = self.dut.PRBS_Control.prbs_error_insert # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,1) + self.assertEqual(fut.msb,1) + self.assertEqual(fut.low,1) + self.assertEqual(fut.high,1) + self.assertEqual(fut.bitmask,0x2) + self.assertEqual(fut.inverse_bitmask,0xFFFFFFFD) + self.assertEqual(fut.max_value,0x1) + + self.assertEqual(fut.default,0) + + self.assertEqual(fut.is_volatile,False) + with self.subTest(msg='field: msk_top_regs.PRBS_Control.prbs_clear'): + # test properties of field: msk_top_regs.PRBS_Control.prbs_clear + fut = self.dut.PRBS_Control.prbs_clear # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,2) + self.assertEqual(fut.msb,2) + self.assertEqual(fut.low,2) + self.assertEqual(fut.high,2) + self.assertEqual(fut.bitmask,0x4) + self.assertEqual(fut.inverse_bitmask,0xFFFFFFFB) + self.assertEqual(fut.max_value,0x1) + + self.assertEqual(fut.default,0) + + self.assertEqual(fut.is_volatile,False) + with self.subTest(msg='field: msk_top_regs.PRBS_Control.prbs_manual_sync'): + # test properties of field: msk_top_regs.PRBS_Control.prbs_manual_sync + fut = self.dut.PRBS_Control.prbs_manual_sync # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,3) + self.assertEqual(fut.msb,3) + self.assertEqual(fut.low,3) + self.assertEqual(fut.high,3) + self.assertEqual(fut.bitmask,0x8) + self.assertEqual(fut.inverse_bitmask,0xFFFFFFF7) + self.assertEqual(fut.max_value,0x1) + + self.assertEqual(fut.default,0) + + self.assertEqual(fut.is_volatile,False) + with self.subTest(msg='field: msk_top_regs.PRBS_Control.prbs_reserved'): + # test properties of field: msk_top_regs.PRBS_Control.prbs_reserved + fut = self.dut.PRBS_Control.prbs_reserved # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,4) + self.assertEqual(fut.msb,15) + self.assertEqual(fut.low,4) + self.assertEqual(fut.high,15) + self.assertEqual(fut.bitmask,0xFFF0) + self.assertEqual(fut.inverse_bitmask,0xFFFF000F) + self.assertEqual(fut.max_value,0xFFF) + + self.assertEqual(fut.default,0) + + self.assertEqual(fut.is_volatile,False) + with self.subTest(msg='field: msk_top_regs.PRBS_Control.prbs_sync_threshold'): + # test properties of field: msk_top_regs.PRBS_Control.prbs_sync_threshold + fut = self.dut.PRBS_Control.prbs_sync_threshold # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,16) + self.assertEqual(fut.msb,31) + self.assertEqual(fut.low,16) + self.assertEqual(fut.high,31) + self.assertEqual(fut.bitmask,0xFFFF0000) + self.assertEqual(fut.inverse_bitmask,0xFFFF) + self.assertEqual(fut.max_value,0xFFFF) + + self.assertEqual(fut.default,0) + + self.assertEqual(fut.is_volatile,False) + with self.subTest(msg='field: msk_top_regs.PRBS_Initial_State.config_data'): + # test properties of field: msk_top_regs.PRBS_Initial_State.config_data + fut = self.dut.PRBS_Initial_State.config_data # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,0) + self.assertEqual(fut.msb,31) + self.assertEqual(fut.low,0) + self.assertEqual(fut.high,31) + self.assertEqual(fut.bitmask,0xFFFFFFFF) + self.assertEqual(fut.inverse_bitmask,0x0) + self.assertEqual(fut.max_value,0xFFFFFFFF) + + self.assertEqual(fut.default,0) + + self.assertEqual(fut.is_volatile,False) + with self.subTest(msg='field: msk_top_regs.PRBS_Polynomial.config_data'): + # test properties of field: msk_top_regs.PRBS_Polynomial.config_data + fut = self.dut.PRBS_Polynomial.config_data # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,0) + self.assertEqual(fut.msb,31) + self.assertEqual(fut.low,0) + self.assertEqual(fut.high,31) + self.assertEqual(fut.bitmask,0xFFFFFFFF) + self.assertEqual(fut.inverse_bitmask,0x0) + self.assertEqual(fut.max_value,0xFFFFFFFF) + + self.assertEqual(fut.default,0) + + self.assertEqual(fut.is_volatile,False) + with self.subTest(msg='field: msk_top_regs.PRBS_Error_Mask.config_data'): + # test properties of field: msk_top_regs.PRBS_Error_Mask.config_data + fut = self.dut.PRBS_Error_Mask.config_data # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,0) + self.assertEqual(fut.msb,31) + self.assertEqual(fut.low,0) + self.assertEqual(fut.high,31) + self.assertEqual(fut.bitmask,0xFFFFFFFF) + self.assertEqual(fut.inverse_bitmask,0x0) + self.assertEqual(fut.max_value,0xFFFFFFFF) + + self.assertEqual(fut.default,0) + + self.assertEqual(fut.is_volatile,False) + with self.subTest(msg='field: msk_top_regs.PRBS_Bit_Count.status_data'): + # test properties of field: msk_top_regs.PRBS_Bit_Count.status_data + fut = self.dut.PRBS_Bit_Count.status_data # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,0) + self.assertEqual(fut.msb,31) + self.assertEqual(fut.low,0) + self.assertEqual(fut.high,31) + self.assertEqual(fut.bitmask,0xFFFFFFFF) + self.assertEqual(fut.inverse_bitmask,0x0) + self.assertEqual(fut.max_value,0xFFFFFFFF) + + self.assertEqual(fut.default,0) + + self.assertEqual(fut.is_volatile,True) + with self.subTest(msg='field: msk_top_regs.PRBS_Error_Count.status_data'): + # test properties of field: msk_top_regs.PRBS_Error_Count.status_data + fut = self.dut.PRBS_Error_Count.status_data # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,0) + self.assertEqual(fut.msb,31) + self.assertEqual(fut.low,0) + self.assertEqual(fut.high,31) + self.assertEqual(fut.bitmask,0xFFFFFFFF) + self.assertEqual(fut.inverse_bitmask,0x0) + self.assertEqual(fut.max_value,0xFFFFFFFF) + + self.assertEqual(fut.default,0) + + self.assertEqual(fut.is_volatile,True) + with self.subTest(msg='field: msk_top_regs.LPF_Accum_F1.status_data'): + # test properties of field: msk_top_regs.LPF_Accum_F1.status_data + fut = self.dut.LPF_Accum_F1.status_data # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,0) + self.assertEqual(fut.msb,31) + self.assertEqual(fut.low,0) + self.assertEqual(fut.high,31) + self.assertEqual(fut.bitmask,0xFFFFFFFF) + self.assertEqual(fut.inverse_bitmask,0x0) + self.assertEqual(fut.max_value,0xFFFFFFFF) + + self.assertEqual(fut.default,0) + + self.assertEqual(fut.is_volatile,True) + with self.subTest(msg='field: msk_top_regs.LPF_Accum_F2.status_data'): + # test properties of field: msk_top_regs.LPF_Accum_F2.status_data + fut = self.dut.LPF_Accum_F2.status_data # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,0) + self.assertEqual(fut.msb,31) + self.assertEqual(fut.low,0) + self.assertEqual(fut.high,31) + self.assertEqual(fut.bitmask,0xFFFFFFFF) + self.assertEqual(fut.inverse_bitmask,0x0) + self.assertEqual(fut.max_value,0xFFFFFFFF) + + self.assertEqual(fut.default,0) + + self.assertEqual(fut.is_volatile,True) + with self.subTest(msg='field: msk_top_regs.axis_xfer_count.xfer_count'): + # test properties of field: msk_top_regs.axis_xfer_count.xfer_count + fut = self.dut.axis_xfer_count.xfer_count # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,0) + self.assertEqual(fut.msb,31) + self.assertEqual(fut.low,0) + self.assertEqual(fut.high,31) + self.assertEqual(fut.bitmask,0xFFFFFFFF) + self.assertEqual(fut.inverse_bitmask,0x0) + self.assertEqual(fut.max_value,0xFFFFFFFF) + + self.assertEqual(fut.default,0) + + self.assertEqual(fut.is_volatile,True) + with self.subTest(msg='field: msk_top_regs.Rx_Sample_Discard.rx_sample_discard'): + # test properties of field: msk_top_regs.Rx_Sample_Discard.rx_sample_discard + fut = self.dut.Rx_Sample_Discard.rx_sample_discard # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,0) + self.assertEqual(fut.msb,7) + self.assertEqual(fut.low,0) + self.assertEqual(fut.high,7) + self.assertEqual(fut.bitmask,0xFF) + self.assertEqual(fut.inverse_bitmask,0xFFFFFF00) + self.assertEqual(fut.max_value,0xFF) + + self.assertEqual(fut.default,0) + + self.assertEqual(fut.is_volatile,False) + with self.subTest(msg='field: msk_top_regs.Rx_Sample_Discard.rx_nco_discard'): + # test properties of field: msk_top_regs.Rx_Sample_Discard.rx_nco_discard + fut = self.dut.Rx_Sample_Discard.rx_nco_discard # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,8) + self.assertEqual(fut.msb,15) + self.assertEqual(fut.low,8) + self.assertEqual(fut.high,15) + self.assertEqual(fut.bitmask,0xFF00) + self.assertEqual(fut.inverse_bitmask,0xFFFF00FF) + self.assertEqual(fut.max_value,0xFF) + + self.assertEqual(fut.default,0) + + self.assertEqual(fut.is_volatile,False) + with self.subTest(msg='field: msk_top_regs.LPF_Config_2.p_gain'): + # test properties of field: msk_top_regs.LPF_Config_2.p_gain + fut = self.dut.LPF_Config_2.p_gain # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,0) + self.assertEqual(fut.msb,23) + self.assertEqual(fut.low,0) + self.assertEqual(fut.high,23) + self.assertEqual(fut.bitmask,0xFFFFFF) + self.assertEqual(fut.inverse_bitmask,0xFF000000) + self.assertEqual(fut.max_value,0xFFFFFF) + + self.assertEqual(fut.default,0) + + self.assertEqual(fut.is_volatile,False) + with self.subTest(msg='field: msk_top_regs.LPF_Config_2.p_shift'): + # test properties of field: msk_top_regs.LPF_Config_2.p_shift + fut = self.dut.LPF_Config_2.p_shift # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,24) + self.assertEqual(fut.msb,31) + self.assertEqual(fut.low,24) + self.assertEqual(fut.high,31) + self.assertEqual(fut.bitmask,0xFF000000) + self.assertEqual(fut.inverse_bitmask,0xFFFFFF) + self.assertEqual(fut.max_value,0xFF) + + self.assertEqual(fut.default,0) + + self.assertEqual(fut.is_volatile,False) + with self.subTest(msg='field: msk_top_regs.f1_nco_adjust.data'): + # test properties of field: msk_top_regs.f1_nco_adjust.data + fut = self.dut.f1_nco_adjust.data # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,0) + self.assertEqual(fut.msb,31) + self.assertEqual(fut.low,0) + self.assertEqual(fut.high,31) + self.assertEqual(fut.bitmask,0xFFFFFFFF) + self.assertEqual(fut.inverse_bitmask,0x0) + self.assertEqual(fut.max_value,0xFFFFFFFF) + + self.assertEqual(fut.default,0) + + self.assertEqual(fut.is_volatile,True) + with self.subTest(msg='field: msk_top_regs.f2_nco_adjust.data'): + # test properties of field: msk_top_regs.f2_nco_adjust.data + fut = self.dut.f2_nco_adjust.data # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,0) + self.assertEqual(fut.msb,31) + self.assertEqual(fut.low,0) + self.assertEqual(fut.high,31) + self.assertEqual(fut.bitmask,0xFFFFFFFF) + self.assertEqual(fut.inverse_bitmask,0x0) + self.assertEqual(fut.max_value,0xFFFFFFFF) + + self.assertEqual(fut.default,0) + + self.assertEqual(fut.is_volatile,True) + with self.subTest(msg='field: msk_top_regs.f1_error.data'): + # test properties of field: msk_top_regs.f1_error.data + fut = self.dut.f1_error.data # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,0) + self.assertEqual(fut.msb,31) + self.assertEqual(fut.low,0) + self.assertEqual(fut.high,31) + self.assertEqual(fut.bitmask,0xFFFFFFFF) + self.assertEqual(fut.inverse_bitmask,0x0) + self.assertEqual(fut.max_value,0xFFFFFFFF) + + self.assertEqual(fut.default,0) + + self.assertEqual(fut.is_volatile,True) + with self.subTest(msg='field: msk_top_regs.f2_error.data'): + # test properties of field: msk_top_regs.f2_error.data + fut = self.dut.f2_error.data # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,0) + self.assertEqual(fut.msb,31) + self.assertEqual(fut.low,0) + self.assertEqual(fut.high,31) + self.assertEqual(fut.bitmask,0xFFFFFFFF) + self.assertEqual(fut.inverse_bitmask,0x0) + self.assertEqual(fut.max_value,0xFFFFFFFF) + + self.assertEqual(fut.default,0) + + self.assertEqual(fut.is_volatile,True) + with self.subTest(msg='field: msk_top_regs.Tx_Sync_Ctrl.tx_sync_ena'): + # test properties of field: msk_top_regs.Tx_Sync_Ctrl.tx_sync_ena + fut = self.dut.Tx_Sync_Ctrl.tx_sync_ena # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,0) + self.assertEqual(fut.msb,0) + self.assertEqual(fut.low,0) + self.assertEqual(fut.high,0) + self.assertEqual(fut.bitmask,0x1) + self.assertEqual(fut.inverse_bitmask,0xFFFFFFFE) + self.assertEqual(fut.max_value,0x1) + + self.assertEqual(fut.default,0) + + self.assertEqual(fut.is_volatile,False) + with self.subTest(msg='field: msk_top_regs.Tx_Sync_Ctrl.tx_sync_force'): + # test properties of field: msk_top_regs.Tx_Sync_Ctrl.tx_sync_force + fut = self.dut.Tx_Sync_Ctrl.tx_sync_force # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,1) + self.assertEqual(fut.msb,1) + self.assertEqual(fut.low,1) + self.assertEqual(fut.high,1) + self.assertEqual(fut.bitmask,0x2) + self.assertEqual(fut.inverse_bitmask,0xFFFFFFFD) + self.assertEqual(fut.max_value,0x1) + + self.assertEqual(fut.default,0) + + self.assertEqual(fut.is_volatile,False) + with self.subTest(msg='field: msk_top_regs.Tx_Sync_Ctrl.tx_sync_f1'): + # test properties of field: msk_top_regs.Tx_Sync_Ctrl.tx_sync_f1 + fut = self.dut.Tx_Sync_Ctrl.tx_sync_f1 # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,2) + self.assertEqual(fut.msb,2) + self.assertEqual(fut.low,2) + self.assertEqual(fut.high,2) + self.assertEqual(fut.bitmask,0x4) + self.assertEqual(fut.inverse_bitmask,0xFFFFFFFB) + self.assertEqual(fut.max_value,0x1) + + self.assertEqual(fut.default,0) + + self.assertEqual(fut.is_volatile,False) + with self.subTest(msg='field: msk_top_regs.Tx_Sync_Ctrl.tx_sync_f2'): + # test properties of field: msk_top_regs.Tx_Sync_Ctrl.tx_sync_f2 + fut = self.dut.Tx_Sync_Ctrl.tx_sync_f2 # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,3) + self.assertEqual(fut.msb,3) + self.assertEqual(fut.low,3) + self.assertEqual(fut.high,3) + self.assertEqual(fut.bitmask,0x8) + self.assertEqual(fut.inverse_bitmask,0xFFFFFFF7) + self.assertEqual(fut.max_value,0x1) + + self.assertEqual(fut.default,0) + + self.assertEqual(fut.is_volatile,False) + with self.subTest(msg='field: msk_top_regs.Tx_Sync_Cnt.tx_sync_cnt'): + # test properties of field: msk_top_regs.Tx_Sync_Cnt.tx_sync_cnt + fut = self.dut.Tx_Sync_Cnt.tx_sync_cnt # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,0) + self.assertEqual(fut.msb,23) + self.assertEqual(fut.low,0) + self.assertEqual(fut.high,23) + self.assertEqual(fut.bitmask,0xFFFFFF) + self.assertEqual(fut.inverse_bitmask,0xFF000000) + self.assertEqual(fut.max_value,0xFFFFFF) + + self.assertEqual(fut.default,0) + + self.assertEqual(fut.is_volatile,False) + with self.subTest(msg='field: msk_top_regs.lowpass_ema_alpha1.alpha'): + # test properties of field: msk_top_regs.lowpass_ema_alpha1.alpha + fut = self.dut.lowpass_ema_alpha1.alpha # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,0) + self.assertEqual(fut.msb,17) + self.assertEqual(fut.low,0) + self.assertEqual(fut.high,17) + self.assertEqual(fut.bitmask,0x3FFFF) + self.assertEqual(fut.inverse_bitmask,0xFFFC0000) + self.assertEqual(fut.max_value,0x3FFFF) + + self.assertEqual(fut.default,0) + + self.assertEqual(fut.is_volatile,False) + with self.subTest(msg='field: msk_top_regs.lowpass_ema_alpha2.alpha'): + # test properties of field: msk_top_regs.lowpass_ema_alpha2.alpha + fut = self.dut.lowpass_ema_alpha2.alpha # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,0) + self.assertEqual(fut.msb,17) + self.assertEqual(fut.low,0) + self.assertEqual(fut.high,17) + self.assertEqual(fut.bitmask,0x3FFFF) + self.assertEqual(fut.inverse_bitmask,0xFFFC0000) + self.assertEqual(fut.max_value,0x3FFFF) + + self.assertEqual(fut.default,0) + + self.assertEqual(fut.is_volatile,False) + with self.subTest(msg='field: msk_top_regs.rx_power.rx_power'): + # test properties of field: msk_top_regs.rx_power.rx_power + fut = self.dut.rx_power.rx_power # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,0) + self.assertEqual(fut.msb,22) + self.assertEqual(fut.low,0) + self.assertEqual(fut.high,22) + self.assertEqual(fut.bitmask,0x7FFFFF) + self.assertEqual(fut.inverse_bitmask,0xFF800000) + self.assertEqual(fut.max_value,0x7FFFFF) + + self.assertEqual(fut.default,0) + + self.assertEqual(fut.is_volatile,True) + + + def test_field_encoding_properties(self) -> None: + """ + Check that enumeration has the name and desc meta data from the systemRDL + """ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + def test_user_defined_properties(self) -> None: + """ + Walk the address map and check user defined properties are correctly pulled up + """ + with self.subTest(msg='register: msk_top_regs.Hash_ID_Low'): + + self.assertDictEqual(self.dut.Hash_ID_Low.udp,{}) + + with self.subTest(msg='register: msk_top_regs.Hash_ID_High'): + + self.assertDictEqual(self.dut.Hash_ID_High.udp,{}) + + with self.subTest(msg='register: msk_top_regs.MSK_Init'): + + self.assertDictEqual(self.dut.MSK_Init.udp,{}) + + with self.subTest(msg='register: msk_top_regs.MSK_Control'): + + self.assertDictEqual(self.dut.MSK_Control.udp,{}) + + with self.subTest(msg='register: msk_top_regs.MSK_Status'): + + self.assertDictEqual(self.dut.MSK_Status.udp,{}) + + with self.subTest(msg='register: msk_top_regs.Tx_Bit_Count'): + + self.assertDictEqual(self.dut.Tx_Bit_Count.udp,{}) + + with self.subTest(msg='register: msk_top_regs.Tx_Enable_Count'): + + self.assertDictEqual(self.dut.Tx_Enable_Count.udp,{}) + + with self.subTest(msg='register: msk_top_regs.Fb_FreqWord'): + + self.assertDictEqual(self.dut.Fb_FreqWord.udp,{}) + + with self.subTest(msg='register: msk_top_regs.TX_F1_FreqWord'): + + self.assertDictEqual(self.dut.TX_F1_FreqWord.udp,{}) + + with self.subTest(msg='register: msk_top_regs.TX_F2_FreqWord'): + + self.assertDictEqual(self.dut.TX_F2_FreqWord.udp,{}) + + with self.subTest(msg='register: msk_top_regs.RX_F1_FreqWord'): + + self.assertDictEqual(self.dut.RX_F1_FreqWord.udp,{}) + + with self.subTest(msg='register: msk_top_regs.RX_F2_FreqWord'): + + self.assertDictEqual(self.dut.RX_F2_FreqWord.udp,{}) + + with self.subTest(msg='register: msk_top_regs.LPF_Config_0'): + + self.assertDictEqual(self.dut.LPF_Config_0.udp,{}) + + with self.subTest(msg='register: msk_top_regs.LPF_Config_1'): + + self.assertDictEqual(self.dut.LPF_Config_1.udp,{}) + + with self.subTest(msg='register: msk_top_regs.Tx_Data_Width'): + + self.assertDictEqual(self.dut.Tx_Data_Width.udp,{}) + + with self.subTest(msg='register: msk_top_regs.Rx_Data_Width'): + + self.assertDictEqual(self.dut.Rx_Data_Width.udp,{}) + + with self.subTest(msg='register: msk_top_regs.PRBS_Control'): + + self.assertDictEqual(self.dut.PRBS_Control.udp,{}) + + with self.subTest(msg='register: msk_top_regs.PRBS_Initial_State'): + + self.assertDictEqual(self.dut.PRBS_Initial_State.udp,{}) + + with self.subTest(msg='register: msk_top_regs.PRBS_Polynomial'): + + self.assertDictEqual(self.dut.PRBS_Polynomial.udp,{}) + + with self.subTest(msg='register: msk_top_regs.PRBS_Error_Mask'): + + self.assertDictEqual(self.dut.PRBS_Error_Mask.udp,{}) + + with self.subTest(msg='register: msk_top_regs.PRBS_Bit_Count'): + + self.assertDictEqual(self.dut.PRBS_Bit_Count.udp,{}) + + with self.subTest(msg='register: msk_top_regs.PRBS_Error_Count'): + + self.assertDictEqual(self.dut.PRBS_Error_Count.udp,{}) + + with self.subTest(msg='register: msk_top_regs.LPF_Accum_F1'): + + self.assertDictEqual(self.dut.LPF_Accum_F1.udp,{}) + + with self.subTest(msg='register: msk_top_regs.LPF_Accum_F2'): + + self.assertDictEqual(self.dut.LPF_Accum_F2.udp,{}) + + with self.subTest(msg='register: msk_top_regs.axis_xfer_count'): + + self.assertDictEqual(self.dut.axis_xfer_count.udp,{}) + + with self.subTest(msg='register: msk_top_regs.Rx_Sample_Discard'): + + self.assertDictEqual(self.dut.Rx_Sample_Discard.udp,{}) + + with self.subTest(msg='register: msk_top_regs.LPF_Config_2'): + + self.assertDictEqual(self.dut.LPF_Config_2.udp,{}) + + with self.subTest(msg='register: msk_top_regs.f1_nco_adjust'): + + self.assertDictEqual(self.dut.f1_nco_adjust.udp,{}) + + with self.subTest(msg='register: msk_top_regs.f2_nco_adjust'): + + self.assertDictEqual(self.dut.f2_nco_adjust.udp,{}) + + with self.subTest(msg='register: msk_top_regs.f1_error'): + + self.assertDictEqual(self.dut.f1_error.udp,{}) + + with self.subTest(msg='register: msk_top_regs.f2_error'): + + self.assertDictEqual(self.dut.f2_error.udp,{}) + + with self.subTest(msg='register: msk_top_regs.Tx_Sync_Ctrl'): + + self.assertDictEqual(self.dut.Tx_Sync_Ctrl.udp,{}) + + with self.subTest(msg='register: msk_top_regs.Tx_Sync_Cnt'): + + self.assertDictEqual(self.dut.Tx_Sync_Cnt.udp,{}) + + with self.subTest(msg='register: msk_top_regs.lowpass_ema_alpha1'): + + self.assertDictEqual(self.dut.lowpass_ema_alpha1.udp,{}) + + with self.subTest(msg='register: msk_top_regs.lowpass_ema_alpha2'): + + self.assertDictEqual(self.dut.lowpass_ema_alpha2.udp,{}) + + with self.subTest(msg='register: msk_top_regs.rx_power'): + + self.assertDictEqual(self.dut.rx_power.udp,{}) + + with self.subTest(msg='register: msk_top_regs.Hash_ID_Low.hash_id_lo'): + + self.assertDictEqual(self.dut.Hash_ID_Low.hash_id_lo.udp,{}) + + with self.subTest(msg='register: msk_top_regs.Hash_ID_High.hash_id_hi'): + + self.assertDictEqual(self.dut.Hash_ID_High.hash_id_hi.udp,{}) + + with self.subTest(msg='register: msk_top_regs.MSK_Init.txrxinit'): + + self.assertDictEqual(self.dut.MSK_Init.txrxinit.udp,{}) + + with self.subTest(msg='register: msk_top_regs.MSK_Init.txinit'): + + self.assertDictEqual(self.dut.MSK_Init.txinit.udp,{}) + + with self.subTest(msg='register: msk_top_regs.MSK_Init.rxinit'): + + self.assertDictEqual(self.dut.MSK_Init.rxinit.udp,{}) + + with self.subTest(msg='register: msk_top_regs.MSK_Control.ptt'): + + self.assertDictEqual(self.dut.MSK_Control.ptt.udp,{}) + + with self.subTest(msg='register: msk_top_regs.MSK_Control.loopback_ena'): + + self.assertDictEqual(self.dut.MSK_Control.loopback_ena.udp,{}) + + with self.subTest(msg='register: msk_top_regs.MSK_Control.rx_invert'): + + self.assertDictEqual(self.dut.MSK_Control.rx_invert.udp,{}) + + with self.subTest(msg='register: msk_top_regs.MSK_Control.clear_counts'): + + self.assertDictEqual(self.dut.MSK_Control.clear_counts.udp,{}) + + with self.subTest(msg='register: msk_top_regs.MSK_Control.diff_encoder_loopback'): + + self.assertDictEqual(self.dut.MSK_Control.diff_encoder_loopback.udp,{}) + + with self.subTest(msg='register: msk_top_regs.MSK_Status.demod_sync_lock'): + + self.assertDictEqual(self.dut.MSK_Status.demod_sync_lock.udp,{}) + + with self.subTest(msg='register: msk_top_regs.MSK_Status.tx_enable'): + + self.assertDictEqual(self.dut.MSK_Status.tx_enable.udp,{}) + + with self.subTest(msg='register: msk_top_regs.MSK_Status.rx_enable'): + + self.assertDictEqual(self.dut.MSK_Status.rx_enable.udp,{}) + + with self.subTest(msg='register: msk_top_regs.MSK_Status.tx_axis_valid'): + + self.assertDictEqual(self.dut.MSK_Status.tx_axis_valid.udp,{}) + + with self.subTest(msg='register: msk_top_regs.Tx_Bit_Count.tx_bit_counter'): + + self.assertDictEqual(self.dut.Tx_Bit_Count.tx_bit_counter.udp,{}) + + with self.subTest(msg='register: msk_top_regs.Tx_Enable_Count.tx_ena_counter'): + + self.assertDictEqual(self.dut.Tx_Enable_Count.tx_ena_counter.udp,{}) + + with self.subTest(msg='register: msk_top_regs.Fb_FreqWord.config_data'): + + self.assertDictEqual(self.dut.Fb_FreqWord.config_data.udp,{}) + + with self.subTest(msg='register: msk_top_regs.TX_F1_FreqWord.config_data'): + + self.assertDictEqual(self.dut.TX_F1_FreqWord.config_data.udp,{}) + + with self.subTest(msg='register: msk_top_regs.TX_F2_FreqWord.config_data'): + + self.assertDictEqual(self.dut.TX_F2_FreqWord.config_data.udp,{}) + + with self.subTest(msg='register: msk_top_regs.RX_F1_FreqWord.config_data'): + + self.assertDictEqual(self.dut.RX_F1_FreqWord.config_data.udp,{}) + + with self.subTest(msg='register: msk_top_regs.RX_F2_FreqWord.config_data'): + + self.assertDictEqual(self.dut.RX_F2_FreqWord.config_data.udp,{}) + + with self.subTest(msg='register: msk_top_regs.LPF_Config_0.lpf_freeze'): + + self.assertDictEqual(self.dut.LPF_Config_0.lpf_freeze.udp,{}) + + with self.subTest(msg='register: msk_top_regs.LPF_Config_0.lpf_zero'): + + self.assertDictEqual(self.dut.LPF_Config_0.lpf_zero.udp,{}) + + with self.subTest(msg='register: msk_top_regs.LPF_Config_0.prbs_reserved'): + + self.assertDictEqual(self.dut.LPF_Config_0.prbs_reserved.udp,{}) + + with self.subTest(msg='register: msk_top_regs.LPF_Config_0.lpf_alpha'): + + self.assertDictEqual(self.dut.LPF_Config_0.lpf_alpha.udp,{}) + + with self.subTest(msg='register: msk_top_regs.LPF_Config_1.i_gain'): + + self.assertDictEqual(self.dut.LPF_Config_1.i_gain.udp,{}) + + with self.subTest(msg='register: msk_top_regs.LPF_Config_1.i_shift'): + + self.assertDictEqual(self.dut.LPF_Config_1.i_shift.udp,{}) + + with self.subTest(msg='register: msk_top_regs.Tx_Data_Width.data_width'): + + self.assertDictEqual(self.dut.Tx_Data_Width.data_width.udp,{}) + + with self.subTest(msg='register: msk_top_regs.Rx_Data_Width.data_width'): + + self.assertDictEqual(self.dut.Rx_Data_Width.data_width.udp,{}) + + with self.subTest(msg='register: msk_top_regs.PRBS_Control.prbs_sel'): + + self.assertDictEqual(self.dut.PRBS_Control.prbs_sel.udp,{}) + + with self.subTest(msg='register: msk_top_regs.PRBS_Control.prbs_error_insert'): + + self.assertDictEqual(self.dut.PRBS_Control.prbs_error_insert.udp,{}) + + with self.subTest(msg='register: msk_top_regs.PRBS_Control.prbs_clear'): + + self.assertDictEqual(self.dut.PRBS_Control.prbs_clear.udp,{}) + + with self.subTest(msg='register: msk_top_regs.PRBS_Control.prbs_manual_sync'): + + self.assertDictEqual(self.dut.PRBS_Control.prbs_manual_sync.udp,{}) + + with self.subTest(msg='register: msk_top_regs.PRBS_Control.prbs_reserved'): + + self.assertDictEqual(self.dut.PRBS_Control.prbs_reserved.udp,{}) + + with self.subTest(msg='register: msk_top_regs.PRBS_Control.prbs_sync_threshold'): + + self.assertDictEqual(self.dut.PRBS_Control.prbs_sync_threshold.udp,{}) + + with self.subTest(msg='register: msk_top_regs.PRBS_Initial_State.config_data'): + + self.assertDictEqual(self.dut.PRBS_Initial_State.config_data.udp,{}) + + with self.subTest(msg='register: msk_top_regs.PRBS_Polynomial.config_data'): + + self.assertDictEqual(self.dut.PRBS_Polynomial.config_data.udp,{}) + + with self.subTest(msg='register: msk_top_regs.PRBS_Error_Mask.config_data'): + + self.assertDictEqual(self.dut.PRBS_Error_Mask.config_data.udp,{}) + + with self.subTest(msg='register: msk_top_regs.PRBS_Bit_Count.status_data'): + + self.assertDictEqual(self.dut.PRBS_Bit_Count.status_data.udp,{}) + + with self.subTest(msg='register: msk_top_regs.PRBS_Error_Count.status_data'): + + self.assertDictEqual(self.dut.PRBS_Error_Count.status_data.udp,{}) + + with self.subTest(msg='register: msk_top_regs.LPF_Accum_F1.status_data'): + + self.assertDictEqual(self.dut.LPF_Accum_F1.status_data.udp,{}) + + with self.subTest(msg='register: msk_top_regs.LPF_Accum_F2.status_data'): + + self.assertDictEqual(self.dut.LPF_Accum_F2.status_data.udp,{}) + + with self.subTest(msg='register: msk_top_regs.axis_xfer_count.xfer_count'): + + self.assertDictEqual(self.dut.axis_xfer_count.xfer_count.udp,{}) + + with self.subTest(msg='register: msk_top_regs.Rx_Sample_Discard.rx_sample_discard'): + + self.assertDictEqual(self.dut.Rx_Sample_Discard.rx_sample_discard.udp,{}) + + with self.subTest(msg='register: msk_top_regs.Rx_Sample_Discard.rx_nco_discard'): + + self.assertDictEqual(self.dut.Rx_Sample_Discard.rx_nco_discard.udp,{}) + + with self.subTest(msg='register: msk_top_regs.LPF_Config_2.p_gain'): + + self.assertDictEqual(self.dut.LPF_Config_2.p_gain.udp,{}) + + with self.subTest(msg='register: msk_top_regs.LPF_Config_2.p_shift'): + + self.assertDictEqual(self.dut.LPF_Config_2.p_shift.udp,{}) + + with self.subTest(msg='register: msk_top_regs.f1_nco_adjust.data'): + + self.assertDictEqual(self.dut.f1_nco_adjust.data.udp,{}) + + with self.subTest(msg='register: msk_top_regs.f2_nco_adjust.data'): + + self.assertDictEqual(self.dut.f2_nco_adjust.data.udp,{}) + + with self.subTest(msg='register: msk_top_regs.f1_error.data'): + + self.assertDictEqual(self.dut.f1_error.data.udp,{}) + + with self.subTest(msg='register: msk_top_regs.f2_error.data'): + + self.assertDictEqual(self.dut.f2_error.data.udp,{}) + + with self.subTest(msg='register: msk_top_regs.Tx_Sync_Ctrl.tx_sync_ena'): + + self.assertDictEqual(self.dut.Tx_Sync_Ctrl.tx_sync_ena.udp,{}) + + with self.subTest(msg='register: msk_top_regs.Tx_Sync_Ctrl.tx_sync_force'): + + self.assertDictEqual(self.dut.Tx_Sync_Ctrl.tx_sync_force.udp,{}) + + with self.subTest(msg='register: msk_top_regs.Tx_Sync_Ctrl.tx_sync_f1'): + + self.assertDictEqual(self.dut.Tx_Sync_Ctrl.tx_sync_f1.udp,{}) + + with self.subTest(msg='register: msk_top_regs.Tx_Sync_Ctrl.tx_sync_f2'): + + self.assertDictEqual(self.dut.Tx_Sync_Ctrl.tx_sync_f2.udp,{}) + + with self.subTest(msg='register: msk_top_regs.Tx_Sync_Cnt.tx_sync_cnt'): + + self.assertDictEqual(self.dut.Tx_Sync_Cnt.tx_sync_cnt.udp,{}) + + with self.subTest(msg='register: msk_top_regs.lowpass_ema_alpha1.alpha'): + + self.assertDictEqual(self.dut.lowpass_ema_alpha1.alpha.udp,{}) + + with self.subTest(msg='register: msk_top_regs.lowpass_ema_alpha2.alpha'): + + self.assertDictEqual(self.dut.lowpass_ema_alpha2.alpha.udp,{}) + + with self.subTest(msg='register: msk_top_regs.rx_power.rx_power'): + + self.assertDictEqual(self.dut.rx_power.rx_power.udp,{}) + + + + async def test_register_read_and_write(self) -> None: + """ + Walk the register map and check every register can be read and written to correctly + """ + rut: Reg + # test access operations (read and/or write) to register: + # msk_top_regs.Hash_ID_Low + with self.subTest(msg='register: msk_top_regs.Hash_ID_Low'): + rut=self.dut.Hash_ID_Low # type: ignore[union-attr,assignment] + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=1) as read_callback_mock: + + + if not isinstance(rut, (RegAsyncReadOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Readable Async Type') + + # test reading back 1 (the unpatched version returns 0 so this confirms the patch works) + self.assertEqual(await rut.read(), 1) + read_callback_mock.assert_called_once_with( + addr=0, + width=32, + accesswidth=rut.accesswidth) + + # test the read check with high value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await rut.read(), 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=0, + width=32, + accesswidth=rut.accesswidth) + + # test the read of the low value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0 + self.assertEqual(await rut.read(), 0x0) + read_callback_mock.assert_called_once_with( + addr=0, + width=32, + accesswidth=rut.accesswidth) + + # test the read of a random value + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.reset_mock() + read_callback_mock.return_value = random_value + self.assertEqual(await rut.read(), random_value) + read_callback_mock.assert_called_once_with( + addr=0, + width=32, + accesswidth=rut.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + + + # test that a non-writable register has no write method and attempting one generates and error + with self.assertRaises(AttributeError): + await rut.write(0) # type: ignore[attr-defined] + + # check the read has not been called in the write test + read_callback_mock.assert_not_called() + # test access operations (read and/or write) to register: + # msk_top_regs.Hash_ID_High + with self.subTest(msg='register: msk_top_regs.Hash_ID_High'): + rut=self.dut.Hash_ID_High # type: ignore[union-attr,assignment] + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=1) as read_callback_mock: + + + if not isinstance(rut, (RegAsyncReadOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Readable Async Type') + + # test reading back 1 (the unpatched version returns 0 so this confirms the patch works) + self.assertEqual(await rut.read(), 1) + read_callback_mock.assert_called_once_with( + addr=4, + width=32, + accesswidth=rut.accesswidth) + + # test the read check with high value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await rut.read(), 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=4, + width=32, + accesswidth=rut.accesswidth) + + # test the read of the low value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0 + self.assertEqual(await rut.read(), 0x0) + read_callback_mock.assert_called_once_with( + addr=4, + width=32, + accesswidth=rut.accesswidth) + + # test the read of a random value + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.reset_mock() + read_callback_mock.return_value = random_value + self.assertEqual(await rut.read(), random_value) + read_callback_mock.assert_called_once_with( + addr=4, + width=32, + accesswidth=rut.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + + + # test that a non-writable register has no write method and attempting one generates and error + with self.assertRaises(AttributeError): + await rut.write(0) # type: ignore[attr-defined] + + # check the read has not been called in the write test + read_callback_mock.assert_not_called() + # test access operations (read and/or write) to register: + # msk_top_regs.MSK_Init + with self.subTest(msg='register: msk_top_regs.MSK_Init'): + rut=self.dut.MSK_Init # type: ignore[union-attr,assignment] + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=1) as read_callback_mock: + + + if not isinstance(rut, (RegAsyncReadOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Readable Async Type') + + # test reading back 1 (the unpatched version returns 0 so this confirms the patch works) + self.assertEqual(await rut.read(), 1) + read_callback_mock.assert_called_once_with( + addr=8, + width=32, + accesswidth=rut.accesswidth) + + # test the read check with high value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await rut.read(), 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=8, + width=32, + accesswidth=rut.accesswidth) + + # test the read of the low value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0 + self.assertEqual(await rut.read(), 0x0) + read_callback_mock.assert_called_once_with( + addr=8, + width=32, + accesswidth=rut.accesswidth) + + # test the read of a random value + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.reset_mock() + read_callback_mock.return_value = random_value + self.assertEqual(await rut.read(), random_value) + read_callback_mock.assert_called_once_with( + addr=8, + width=32, + accesswidth=rut.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + + + if not isinstance(rut, (RegAsyncWriteOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Writeable Async Type') + + # test the write with high value + await rut.write(0xFFFFFFFF) + write_callback_mock.assert_called_once_with( + addr=8, + width=32, + accesswidth=rut.accesswidth, + data=0xFFFFFFFF) + write_callback_mock.reset_mock() + + # test the write of a low value + await rut.write(0) + write_callback_mock.assert_called_once_with( + addr=8, + width=32, + accesswidth=rut.accesswidth, + data=0) + write_callback_mock.reset_mock() + + # test the write of a random + random_value = random.randrange(0, 0xFFFFFFFF+1) + await rut.write(random_value) # type: ignore[union-attr] + write_callback_mock.assert_called_once_with( + addr=8, + width=32, + accesswidth=rut.accesswidth, + data=random_value) + write_callback_mock.reset_mock() + + # test writing a value beyond the register range is blocked with an exception being raised + with self.assertRaises(ValueError): + await rut.write(-1) + + with self.assertRaises(ValueError): + await rut.write(0xFFFFFFFF+1) + + # check the read has not been called in the write test + read_callback_mock.assert_not_called() + # test access operations (read and/or write) to register: + # msk_top_regs.MSK_Control + with self.subTest(msg='register: msk_top_regs.MSK_Control'): + rut=self.dut.MSK_Control # type: ignore[union-attr,assignment] + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=1) as read_callback_mock: + + + if not isinstance(rut, (RegAsyncReadOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Readable Async Type') + + # test reading back 1 (the unpatched version returns 0 so this confirms the patch works) + self.assertEqual(await rut.read(), 1) + read_callback_mock.assert_called_once_with( + addr=12, + width=32, + accesswidth=rut.accesswidth) + + # test the read check with high value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await rut.read(), 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=12, + width=32, + accesswidth=rut.accesswidth) + + # test the read of the low value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0 + self.assertEqual(await rut.read(), 0x0) + read_callback_mock.assert_called_once_with( + addr=12, + width=32, + accesswidth=rut.accesswidth) + + # test the read of a random value + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.reset_mock() + read_callback_mock.return_value = random_value + self.assertEqual(await rut.read(), random_value) + read_callback_mock.assert_called_once_with( + addr=12, + width=32, + accesswidth=rut.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + + + if not isinstance(rut, (RegAsyncWriteOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Writeable Async Type') + + # test the write with high value + await rut.write(0xFFFFFFFF) + write_callback_mock.assert_called_once_with( + addr=12, + width=32, + accesswidth=rut.accesswidth, + data=0xFFFFFFFF) + write_callback_mock.reset_mock() + + # test the write of a low value + await rut.write(0) + write_callback_mock.assert_called_once_with( + addr=12, + width=32, + accesswidth=rut.accesswidth, + data=0) + write_callback_mock.reset_mock() + + # test the write of a random + random_value = random.randrange(0, 0xFFFFFFFF+1) + await rut.write(random_value) # type: ignore[union-attr] + write_callback_mock.assert_called_once_with( + addr=12, + width=32, + accesswidth=rut.accesswidth, + data=random_value) + write_callback_mock.reset_mock() + + # test writing a value beyond the register range is blocked with an exception being raised + with self.assertRaises(ValueError): + await rut.write(-1) + + with self.assertRaises(ValueError): + await rut.write(0xFFFFFFFF+1) + + # check the read has not been called in the write test + read_callback_mock.assert_not_called() + # test access operations (read and/or write) to register: + # msk_top_regs.MSK_Status + with self.subTest(msg='register: msk_top_regs.MSK_Status'): + rut=self.dut.MSK_Status # type: ignore[union-attr,assignment] + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=1) as read_callback_mock: + + + if not isinstance(rut, (RegAsyncReadOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Readable Async Type') + + # test reading back 1 (the unpatched version returns 0 so this confirms the patch works) + self.assertEqual(await rut.read(), 1) + read_callback_mock.assert_called_once_with( + addr=16, + width=32, + accesswidth=rut.accesswidth) + + # test the read check with high value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await rut.read(), 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=16, + width=32, + accesswidth=rut.accesswidth) + + # test the read of the low value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0 + self.assertEqual(await rut.read(), 0x0) + read_callback_mock.assert_called_once_with( + addr=16, + width=32, + accesswidth=rut.accesswidth) + + # test the read of a random value + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.reset_mock() + read_callback_mock.return_value = random_value + self.assertEqual(await rut.read(), random_value) + read_callback_mock.assert_called_once_with( + addr=16, + width=32, + accesswidth=rut.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + + + # test that a non-writable register has no write method and attempting one generates and error + with self.assertRaises(AttributeError): + await rut.write(0) # type: ignore[attr-defined] + + # check the read has not been called in the write test + read_callback_mock.assert_not_called() + # test access operations (read and/or write) to register: + # msk_top_regs.Tx_Bit_Count + with self.subTest(msg='register: msk_top_regs.Tx_Bit_Count'): + rut=self.dut.Tx_Bit_Count # type: ignore[union-attr,assignment] + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=1) as read_callback_mock: + + + if not isinstance(rut, (RegAsyncReadOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Readable Async Type') + + # test reading back 1 (the unpatched version returns 0 so this confirms the patch works) + self.assertEqual(await rut.read(), 1) + read_callback_mock.assert_called_once_with( + addr=20, + width=32, + accesswidth=rut.accesswidth) + + # test the read check with high value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await rut.read(), 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=20, + width=32, + accesswidth=rut.accesswidth) + + # test the read of the low value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0 + self.assertEqual(await rut.read(), 0x0) + read_callback_mock.assert_called_once_with( + addr=20, + width=32, + accesswidth=rut.accesswidth) + + # test the read of a random value + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.reset_mock() + read_callback_mock.return_value = random_value + self.assertEqual(await rut.read(), random_value) + read_callback_mock.assert_called_once_with( + addr=20, + width=32, + accesswidth=rut.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + + + # test that a non-writable register has no write method and attempting one generates and error + with self.assertRaises(AttributeError): + await rut.write(0) # type: ignore[attr-defined] + + # check the read has not been called in the write test + read_callback_mock.assert_not_called() + # test access operations (read and/or write) to register: + # msk_top_regs.Tx_Enable_Count + with self.subTest(msg='register: msk_top_regs.Tx_Enable_Count'): + rut=self.dut.Tx_Enable_Count # type: ignore[union-attr,assignment] + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=1) as read_callback_mock: + + + if not isinstance(rut, (RegAsyncReadOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Readable Async Type') + + # test reading back 1 (the unpatched version returns 0 so this confirms the patch works) + self.assertEqual(await rut.read(), 1) + read_callback_mock.assert_called_once_with( + addr=24, + width=32, + accesswidth=rut.accesswidth) + + # test the read check with high value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await rut.read(), 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=24, + width=32, + accesswidth=rut.accesswidth) + + # test the read of the low value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0 + self.assertEqual(await rut.read(), 0x0) + read_callback_mock.assert_called_once_with( + addr=24, + width=32, + accesswidth=rut.accesswidth) + + # test the read of a random value + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.reset_mock() + read_callback_mock.return_value = random_value + self.assertEqual(await rut.read(), random_value) + read_callback_mock.assert_called_once_with( + addr=24, + width=32, + accesswidth=rut.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + + + # test that a non-writable register has no write method and attempting one generates and error + with self.assertRaises(AttributeError): + await rut.write(0) # type: ignore[attr-defined] + + # check the read has not been called in the write test + read_callback_mock.assert_not_called() + # test access operations (read and/or write) to register: + # msk_top_regs.Fb_FreqWord + with self.subTest(msg='register: msk_top_regs.Fb_FreqWord'): + rut=self.dut.Fb_FreqWord # type: ignore[union-attr,assignment] + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=1) as read_callback_mock: + + + if not isinstance(rut, (RegAsyncReadOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Readable Async Type') + + # test reading back 1 (the unpatched version returns 0 so this confirms the patch works) + self.assertEqual(await rut.read(), 1) + read_callback_mock.assert_called_once_with( + addr=28, + width=32, + accesswidth=rut.accesswidth) + + # test the read check with high value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await rut.read(), 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=28, + width=32, + accesswidth=rut.accesswidth) + + # test the read of the low value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0 + self.assertEqual(await rut.read(), 0x0) + read_callback_mock.assert_called_once_with( + addr=28, + width=32, + accesswidth=rut.accesswidth) + + # test the read of a random value + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.reset_mock() + read_callback_mock.return_value = random_value + self.assertEqual(await rut.read(), random_value) + read_callback_mock.assert_called_once_with( + addr=28, + width=32, + accesswidth=rut.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + + + if not isinstance(rut, (RegAsyncWriteOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Writeable Async Type') + + # test the write with high value + await rut.write(0xFFFFFFFF) + write_callback_mock.assert_called_once_with( + addr=28, + width=32, + accesswidth=rut.accesswidth, + data=0xFFFFFFFF) + write_callback_mock.reset_mock() + + # test the write of a low value + await rut.write(0) + write_callback_mock.assert_called_once_with( + addr=28, + width=32, + accesswidth=rut.accesswidth, + data=0) + write_callback_mock.reset_mock() + + # test the write of a random + random_value = random.randrange(0, 0xFFFFFFFF+1) + await rut.write(random_value) # type: ignore[union-attr] + write_callback_mock.assert_called_once_with( + addr=28, + width=32, + accesswidth=rut.accesswidth, + data=random_value) + write_callback_mock.reset_mock() + + # test writing a value beyond the register range is blocked with an exception being raised + with self.assertRaises(ValueError): + await rut.write(-1) + + with self.assertRaises(ValueError): + await rut.write(0xFFFFFFFF+1) + + # check the read has not been called in the write test + read_callback_mock.assert_not_called() + # test access operations (read and/or write) to register: + # msk_top_regs.TX_F1_FreqWord + with self.subTest(msg='register: msk_top_regs.TX_F1_FreqWord'): + rut=self.dut.TX_F1_FreqWord # type: ignore[union-attr,assignment] + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=1) as read_callback_mock: + + + if not isinstance(rut, (RegAsyncReadOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Readable Async Type') + + # test reading back 1 (the unpatched version returns 0 so this confirms the patch works) + self.assertEqual(await rut.read(), 1) + read_callback_mock.assert_called_once_with( + addr=32, + width=32, + accesswidth=rut.accesswidth) + + # test the read check with high value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await rut.read(), 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=32, + width=32, + accesswidth=rut.accesswidth) + + # test the read of the low value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0 + self.assertEqual(await rut.read(), 0x0) + read_callback_mock.assert_called_once_with( + addr=32, + width=32, + accesswidth=rut.accesswidth) + + # test the read of a random value + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.reset_mock() + read_callback_mock.return_value = random_value + self.assertEqual(await rut.read(), random_value) + read_callback_mock.assert_called_once_with( + addr=32, + width=32, + accesswidth=rut.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + + + if not isinstance(rut, (RegAsyncWriteOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Writeable Async Type') + + # test the write with high value + await rut.write(0xFFFFFFFF) + write_callback_mock.assert_called_once_with( + addr=32, + width=32, + accesswidth=rut.accesswidth, + data=0xFFFFFFFF) + write_callback_mock.reset_mock() + + # test the write of a low value + await rut.write(0) + write_callback_mock.assert_called_once_with( + addr=32, + width=32, + accesswidth=rut.accesswidth, + data=0) + write_callback_mock.reset_mock() + + # test the write of a random + random_value = random.randrange(0, 0xFFFFFFFF+1) + await rut.write(random_value) # type: ignore[union-attr] + write_callback_mock.assert_called_once_with( + addr=32, + width=32, + accesswidth=rut.accesswidth, + data=random_value) + write_callback_mock.reset_mock() + + # test writing a value beyond the register range is blocked with an exception being raised + with self.assertRaises(ValueError): + await rut.write(-1) + + with self.assertRaises(ValueError): + await rut.write(0xFFFFFFFF+1) + + # check the read has not been called in the write test + read_callback_mock.assert_not_called() + # test access operations (read and/or write) to register: + # msk_top_regs.TX_F2_FreqWord + with self.subTest(msg='register: msk_top_regs.TX_F2_FreqWord'): + rut=self.dut.TX_F2_FreqWord # type: ignore[union-attr,assignment] + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=1) as read_callback_mock: + + + if not isinstance(rut, (RegAsyncReadOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Readable Async Type') + + # test reading back 1 (the unpatched version returns 0 so this confirms the patch works) + self.assertEqual(await rut.read(), 1) + read_callback_mock.assert_called_once_with( + addr=36, + width=32, + accesswidth=rut.accesswidth) + + # test the read check with high value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await rut.read(), 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=36, + width=32, + accesswidth=rut.accesswidth) + + # test the read of the low value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0 + self.assertEqual(await rut.read(), 0x0) + read_callback_mock.assert_called_once_with( + addr=36, + width=32, + accesswidth=rut.accesswidth) + + # test the read of a random value + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.reset_mock() + read_callback_mock.return_value = random_value + self.assertEqual(await rut.read(), random_value) + read_callback_mock.assert_called_once_with( + addr=36, + width=32, + accesswidth=rut.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + + + if not isinstance(rut, (RegAsyncWriteOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Writeable Async Type') + + # test the write with high value + await rut.write(0xFFFFFFFF) + write_callback_mock.assert_called_once_with( + addr=36, + width=32, + accesswidth=rut.accesswidth, + data=0xFFFFFFFF) + write_callback_mock.reset_mock() + + # test the write of a low value + await rut.write(0) + write_callback_mock.assert_called_once_with( + addr=36, + width=32, + accesswidth=rut.accesswidth, + data=0) + write_callback_mock.reset_mock() + + # test the write of a random + random_value = random.randrange(0, 0xFFFFFFFF+1) + await rut.write(random_value) # type: ignore[union-attr] + write_callback_mock.assert_called_once_with( + addr=36, + width=32, + accesswidth=rut.accesswidth, + data=random_value) + write_callback_mock.reset_mock() + + # test writing a value beyond the register range is blocked with an exception being raised + with self.assertRaises(ValueError): + await rut.write(-1) + + with self.assertRaises(ValueError): + await rut.write(0xFFFFFFFF+1) + + # check the read has not been called in the write test + read_callback_mock.assert_not_called() + # test access operations (read and/or write) to register: + # msk_top_regs.RX_F1_FreqWord + with self.subTest(msg='register: msk_top_regs.RX_F1_FreqWord'): + rut=self.dut.RX_F1_FreqWord # type: ignore[union-attr,assignment] + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=1) as read_callback_mock: + + + if not isinstance(rut, (RegAsyncReadOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Readable Async Type') + + # test reading back 1 (the unpatched version returns 0 so this confirms the patch works) + self.assertEqual(await rut.read(), 1) + read_callback_mock.assert_called_once_with( + addr=40, + width=32, + accesswidth=rut.accesswidth) + + # test the read check with high value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await rut.read(), 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=40, + width=32, + accesswidth=rut.accesswidth) + + # test the read of the low value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0 + self.assertEqual(await rut.read(), 0x0) + read_callback_mock.assert_called_once_with( + addr=40, + width=32, + accesswidth=rut.accesswidth) + + # test the read of a random value + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.reset_mock() + read_callback_mock.return_value = random_value + self.assertEqual(await rut.read(), random_value) + read_callback_mock.assert_called_once_with( + addr=40, + width=32, + accesswidth=rut.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + + + if not isinstance(rut, (RegAsyncWriteOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Writeable Async Type') + + # test the write with high value + await rut.write(0xFFFFFFFF) + write_callback_mock.assert_called_once_with( + addr=40, + width=32, + accesswidth=rut.accesswidth, + data=0xFFFFFFFF) + write_callback_mock.reset_mock() + + # test the write of a low value + await rut.write(0) + write_callback_mock.assert_called_once_with( + addr=40, + width=32, + accesswidth=rut.accesswidth, + data=0) + write_callback_mock.reset_mock() + + # test the write of a random + random_value = random.randrange(0, 0xFFFFFFFF+1) + await rut.write(random_value) # type: ignore[union-attr] + write_callback_mock.assert_called_once_with( + addr=40, + width=32, + accesswidth=rut.accesswidth, + data=random_value) + write_callback_mock.reset_mock() + + # test writing a value beyond the register range is blocked with an exception being raised + with self.assertRaises(ValueError): + await rut.write(-1) + + with self.assertRaises(ValueError): + await rut.write(0xFFFFFFFF+1) + + # check the read has not been called in the write test + read_callback_mock.assert_not_called() + # test access operations (read and/or write) to register: + # msk_top_regs.RX_F2_FreqWord + with self.subTest(msg='register: msk_top_regs.RX_F2_FreqWord'): + rut=self.dut.RX_F2_FreqWord # type: ignore[union-attr,assignment] + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=1) as read_callback_mock: + + + if not isinstance(rut, (RegAsyncReadOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Readable Async Type') + + # test reading back 1 (the unpatched version returns 0 so this confirms the patch works) + self.assertEqual(await rut.read(), 1) + read_callback_mock.assert_called_once_with( + addr=44, + width=32, + accesswidth=rut.accesswidth) + + # test the read check with high value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await rut.read(), 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=44, + width=32, + accesswidth=rut.accesswidth) + + # test the read of the low value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0 + self.assertEqual(await rut.read(), 0x0) + read_callback_mock.assert_called_once_with( + addr=44, + width=32, + accesswidth=rut.accesswidth) + + # test the read of a random value + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.reset_mock() + read_callback_mock.return_value = random_value + self.assertEqual(await rut.read(), random_value) + read_callback_mock.assert_called_once_with( + addr=44, + width=32, + accesswidth=rut.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + + + if not isinstance(rut, (RegAsyncWriteOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Writeable Async Type') + + # test the write with high value + await rut.write(0xFFFFFFFF) + write_callback_mock.assert_called_once_with( + addr=44, + width=32, + accesswidth=rut.accesswidth, + data=0xFFFFFFFF) + write_callback_mock.reset_mock() + + # test the write of a low value + await rut.write(0) + write_callback_mock.assert_called_once_with( + addr=44, + width=32, + accesswidth=rut.accesswidth, + data=0) + write_callback_mock.reset_mock() + + # test the write of a random + random_value = random.randrange(0, 0xFFFFFFFF+1) + await rut.write(random_value) # type: ignore[union-attr] + write_callback_mock.assert_called_once_with( + addr=44, + width=32, + accesswidth=rut.accesswidth, + data=random_value) + write_callback_mock.reset_mock() + + # test writing a value beyond the register range is blocked with an exception being raised + with self.assertRaises(ValueError): + await rut.write(-1) + + with self.assertRaises(ValueError): + await rut.write(0xFFFFFFFF+1) + + # check the read has not been called in the write test + read_callback_mock.assert_not_called() + # test access operations (read and/or write) to register: + # msk_top_regs.LPF_Config_0 + with self.subTest(msg='register: msk_top_regs.LPF_Config_0'): + rut=self.dut.LPF_Config_0 # type: ignore[union-attr,assignment] + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=1) as read_callback_mock: + + + if not isinstance(rut, (RegAsyncReadOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Readable Async Type') + + # test reading back 1 (the unpatched version returns 0 so this confirms the patch works) + self.assertEqual(await rut.read(), 1) + read_callback_mock.assert_called_once_with( + addr=48, + width=32, + accesswidth=rut.accesswidth) + + # test the read check with high value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await rut.read(), 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=48, + width=32, + accesswidth=rut.accesswidth) + + # test the read of the low value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0 + self.assertEqual(await rut.read(), 0x0) + read_callback_mock.assert_called_once_with( + addr=48, + width=32, + accesswidth=rut.accesswidth) + + # test the read of a random value + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.reset_mock() + read_callback_mock.return_value = random_value + self.assertEqual(await rut.read(), random_value) + read_callback_mock.assert_called_once_with( + addr=48, + width=32, + accesswidth=rut.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + + + if not isinstance(rut, (RegAsyncWriteOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Writeable Async Type') + + # test the write with high value + await rut.write(0xFFFFFFFF) + write_callback_mock.assert_called_once_with( + addr=48, + width=32, + accesswidth=rut.accesswidth, + data=0xFFFFFFFF) + write_callback_mock.reset_mock() + + # test the write of a low value + await rut.write(0) + write_callback_mock.assert_called_once_with( + addr=48, + width=32, + accesswidth=rut.accesswidth, + data=0) + write_callback_mock.reset_mock() + + # test the write of a random + random_value = random.randrange(0, 0xFFFFFFFF+1) + await rut.write(random_value) # type: ignore[union-attr] + write_callback_mock.assert_called_once_with( + addr=48, + width=32, + accesswidth=rut.accesswidth, + data=random_value) + write_callback_mock.reset_mock() + + # test writing a value beyond the register range is blocked with an exception being raised + with self.assertRaises(ValueError): + await rut.write(-1) + + with self.assertRaises(ValueError): + await rut.write(0xFFFFFFFF+1) + + # check the read has not been called in the write test + read_callback_mock.assert_not_called() + # test access operations (read and/or write) to register: + # msk_top_regs.LPF_Config_1 + with self.subTest(msg='register: msk_top_regs.LPF_Config_1'): + rut=self.dut.LPF_Config_1 # type: ignore[union-attr,assignment] + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=1) as read_callback_mock: + + + if not isinstance(rut, (RegAsyncReadOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Readable Async Type') + + # test reading back 1 (the unpatched version returns 0 so this confirms the patch works) + self.assertEqual(await rut.read(), 1) + read_callback_mock.assert_called_once_with( + addr=52, + width=32, + accesswidth=rut.accesswidth) + + # test the read check with high value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await rut.read(), 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=52, + width=32, + accesswidth=rut.accesswidth) + + # test the read of the low value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0 + self.assertEqual(await rut.read(), 0x0) + read_callback_mock.assert_called_once_with( + addr=52, + width=32, + accesswidth=rut.accesswidth) + + # test the read of a random value + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.reset_mock() + read_callback_mock.return_value = random_value + self.assertEqual(await rut.read(), random_value) + read_callback_mock.assert_called_once_with( + addr=52, + width=32, + accesswidth=rut.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + + + if not isinstance(rut, (RegAsyncWriteOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Writeable Async Type') + + # test the write with high value + await rut.write(0xFFFFFFFF) + write_callback_mock.assert_called_once_with( + addr=52, + width=32, + accesswidth=rut.accesswidth, + data=0xFFFFFFFF) + write_callback_mock.reset_mock() + + # test the write of a low value + await rut.write(0) + write_callback_mock.assert_called_once_with( + addr=52, + width=32, + accesswidth=rut.accesswidth, + data=0) + write_callback_mock.reset_mock() + + # test the write of a random + random_value = random.randrange(0, 0xFFFFFFFF+1) + await rut.write(random_value) # type: ignore[union-attr] + write_callback_mock.assert_called_once_with( + addr=52, + width=32, + accesswidth=rut.accesswidth, + data=random_value) + write_callback_mock.reset_mock() + + # test writing a value beyond the register range is blocked with an exception being raised + with self.assertRaises(ValueError): + await rut.write(-1) + + with self.assertRaises(ValueError): + await rut.write(0xFFFFFFFF+1) + + # check the read has not been called in the write test + read_callback_mock.assert_not_called() + # test access operations (read and/or write) to register: + # msk_top_regs.Tx_Data_Width + with self.subTest(msg='register: msk_top_regs.Tx_Data_Width'): + rut=self.dut.Tx_Data_Width # type: ignore[union-attr,assignment] + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=1) as read_callback_mock: + + + if not isinstance(rut, (RegAsyncReadOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Readable Async Type') + + # test reading back 1 (the unpatched version returns 0 so this confirms the patch works) + self.assertEqual(await rut.read(), 1) + read_callback_mock.assert_called_once_with( + addr=56, + width=32, + accesswidth=rut.accesswidth) + + # test the read check with high value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await rut.read(), 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=56, + width=32, + accesswidth=rut.accesswidth) + + # test the read of the low value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0 + self.assertEqual(await rut.read(), 0x0) + read_callback_mock.assert_called_once_with( + addr=56, + width=32, + accesswidth=rut.accesswidth) + + # test the read of a random value + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.reset_mock() + read_callback_mock.return_value = random_value + self.assertEqual(await rut.read(), random_value) + read_callback_mock.assert_called_once_with( + addr=56, + width=32, + accesswidth=rut.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + + + if not isinstance(rut, (RegAsyncWriteOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Writeable Async Type') + + # test the write with high value + await rut.write(0xFFFFFFFF) + write_callback_mock.assert_called_once_with( + addr=56, + width=32, + accesswidth=rut.accesswidth, + data=0xFFFFFFFF) + write_callback_mock.reset_mock() + + # test the write of a low value + await rut.write(0) + write_callback_mock.assert_called_once_with( + addr=56, + width=32, + accesswidth=rut.accesswidth, + data=0) + write_callback_mock.reset_mock() + + # test the write of a random + random_value = random.randrange(0, 0xFFFFFFFF+1) + await rut.write(random_value) # type: ignore[union-attr] + write_callback_mock.assert_called_once_with( + addr=56, + width=32, + accesswidth=rut.accesswidth, + data=random_value) + write_callback_mock.reset_mock() + + # test writing a value beyond the register range is blocked with an exception being raised + with self.assertRaises(ValueError): + await rut.write(-1) + + with self.assertRaises(ValueError): + await rut.write(0xFFFFFFFF+1) + + # check the read has not been called in the write test + read_callback_mock.assert_not_called() + # test access operations (read and/or write) to register: + # msk_top_regs.Rx_Data_Width + with self.subTest(msg='register: msk_top_regs.Rx_Data_Width'): + rut=self.dut.Rx_Data_Width # type: ignore[union-attr,assignment] + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=1) as read_callback_mock: + + + if not isinstance(rut, (RegAsyncReadOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Readable Async Type') + + # test reading back 1 (the unpatched version returns 0 so this confirms the patch works) + self.assertEqual(await rut.read(), 1) + read_callback_mock.assert_called_once_with( + addr=60, + width=32, + accesswidth=rut.accesswidth) + + # test the read check with high value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await rut.read(), 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=60, + width=32, + accesswidth=rut.accesswidth) + + # test the read of the low value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0 + self.assertEqual(await rut.read(), 0x0) + read_callback_mock.assert_called_once_with( + addr=60, + width=32, + accesswidth=rut.accesswidth) + + # test the read of a random value + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.reset_mock() + read_callback_mock.return_value = random_value + self.assertEqual(await rut.read(), random_value) + read_callback_mock.assert_called_once_with( + addr=60, + width=32, + accesswidth=rut.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + + + if not isinstance(rut, (RegAsyncWriteOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Writeable Async Type') + + # test the write with high value + await rut.write(0xFFFFFFFF) + write_callback_mock.assert_called_once_with( + addr=60, + width=32, + accesswidth=rut.accesswidth, + data=0xFFFFFFFF) + write_callback_mock.reset_mock() + + # test the write of a low value + await rut.write(0) + write_callback_mock.assert_called_once_with( + addr=60, + width=32, + accesswidth=rut.accesswidth, + data=0) + write_callback_mock.reset_mock() + + # test the write of a random + random_value = random.randrange(0, 0xFFFFFFFF+1) + await rut.write(random_value) # type: ignore[union-attr] + write_callback_mock.assert_called_once_with( + addr=60, + width=32, + accesswidth=rut.accesswidth, + data=random_value) + write_callback_mock.reset_mock() + + # test writing a value beyond the register range is blocked with an exception being raised + with self.assertRaises(ValueError): + await rut.write(-1) + + with self.assertRaises(ValueError): + await rut.write(0xFFFFFFFF+1) + + # check the read has not been called in the write test + read_callback_mock.assert_not_called() + # test access operations (read and/or write) to register: + # msk_top_regs.PRBS_Control + with self.subTest(msg='register: msk_top_regs.PRBS_Control'): + rut=self.dut.PRBS_Control # type: ignore[union-attr,assignment] + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=1) as read_callback_mock: + + + if not isinstance(rut, (RegAsyncReadOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Readable Async Type') + + # test reading back 1 (the unpatched version returns 0 so this confirms the patch works) + self.assertEqual(await rut.read(), 1) + read_callback_mock.assert_called_once_with( + addr=64, + width=32, + accesswidth=rut.accesswidth) + + # test the read check with high value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await rut.read(), 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=64, + width=32, + accesswidth=rut.accesswidth) + + # test the read of the low value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0 + self.assertEqual(await rut.read(), 0x0) + read_callback_mock.assert_called_once_with( + addr=64, + width=32, + accesswidth=rut.accesswidth) + + # test the read of a random value + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.reset_mock() + read_callback_mock.return_value = random_value + self.assertEqual(await rut.read(), random_value) + read_callback_mock.assert_called_once_with( + addr=64, + width=32, + accesswidth=rut.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + + + if not isinstance(rut, (RegAsyncWriteOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Writeable Async Type') + + # test the write with high value + await rut.write(0xFFFFFFFF) + write_callback_mock.assert_called_once_with( + addr=64, + width=32, + accesswidth=rut.accesswidth, + data=0xFFFFFFFF) + write_callback_mock.reset_mock() + + # test the write of a low value + await rut.write(0) + write_callback_mock.assert_called_once_with( + addr=64, + width=32, + accesswidth=rut.accesswidth, + data=0) + write_callback_mock.reset_mock() + + # test the write of a random + random_value = random.randrange(0, 0xFFFFFFFF+1) + await rut.write(random_value) # type: ignore[union-attr] + write_callback_mock.assert_called_once_with( + addr=64, + width=32, + accesswidth=rut.accesswidth, + data=random_value) + write_callback_mock.reset_mock() + + # test writing a value beyond the register range is blocked with an exception being raised + with self.assertRaises(ValueError): + await rut.write(-1) + + with self.assertRaises(ValueError): + await rut.write(0xFFFFFFFF+1) + + # check the read has not been called in the write test + read_callback_mock.assert_not_called() + # test access operations (read and/or write) to register: + # msk_top_regs.PRBS_Initial_State + with self.subTest(msg='register: msk_top_regs.PRBS_Initial_State'): + rut=self.dut.PRBS_Initial_State # type: ignore[union-attr,assignment] + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=1) as read_callback_mock: + + + if not isinstance(rut, (RegAsyncReadOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Readable Async Type') + + # test reading back 1 (the unpatched version returns 0 so this confirms the patch works) + self.assertEqual(await rut.read(), 1) + read_callback_mock.assert_called_once_with( + addr=68, + width=32, + accesswidth=rut.accesswidth) + + # test the read check with high value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await rut.read(), 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=68, + width=32, + accesswidth=rut.accesswidth) + + # test the read of the low value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0 + self.assertEqual(await rut.read(), 0x0) + read_callback_mock.assert_called_once_with( + addr=68, + width=32, + accesswidth=rut.accesswidth) + + # test the read of a random value + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.reset_mock() + read_callback_mock.return_value = random_value + self.assertEqual(await rut.read(), random_value) + read_callback_mock.assert_called_once_with( + addr=68, + width=32, + accesswidth=rut.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + + + if not isinstance(rut, (RegAsyncWriteOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Writeable Async Type') + + # test the write with high value + await rut.write(0xFFFFFFFF) + write_callback_mock.assert_called_once_with( + addr=68, + width=32, + accesswidth=rut.accesswidth, + data=0xFFFFFFFF) + write_callback_mock.reset_mock() + + # test the write of a low value + await rut.write(0) + write_callback_mock.assert_called_once_with( + addr=68, + width=32, + accesswidth=rut.accesswidth, + data=0) + write_callback_mock.reset_mock() + + # test the write of a random + random_value = random.randrange(0, 0xFFFFFFFF+1) + await rut.write(random_value) # type: ignore[union-attr] + write_callback_mock.assert_called_once_with( + addr=68, + width=32, + accesswidth=rut.accesswidth, + data=random_value) + write_callback_mock.reset_mock() + + # test writing a value beyond the register range is blocked with an exception being raised + with self.assertRaises(ValueError): + await rut.write(-1) + + with self.assertRaises(ValueError): + await rut.write(0xFFFFFFFF+1) + + # check the read has not been called in the write test + read_callback_mock.assert_not_called() + # test access operations (read and/or write) to register: + # msk_top_regs.PRBS_Polynomial + with self.subTest(msg='register: msk_top_regs.PRBS_Polynomial'): + rut=self.dut.PRBS_Polynomial # type: ignore[union-attr,assignment] + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=1) as read_callback_mock: + + + if not isinstance(rut, (RegAsyncReadOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Readable Async Type') + + # test reading back 1 (the unpatched version returns 0 so this confirms the patch works) + self.assertEqual(await rut.read(), 1) + read_callback_mock.assert_called_once_with( + addr=72, + width=32, + accesswidth=rut.accesswidth) + + # test the read check with high value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await rut.read(), 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=72, + width=32, + accesswidth=rut.accesswidth) + + # test the read of the low value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0 + self.assertEqual(await rut.read(), 0x0) + read_callback_mock.assert_called_once_with( + addr=72, + width=32, + accesswidth=rut.accesswidth) + + # test the read of a random value + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.reset_mock() + read_callback_mock.return_value = random_value + self.assertEqual(await rut.read(), random_value) + read_callback_mock.assert_called_once_with( + addr=72, + width=32, + accesswidth=rut.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + + + if not isinstance(rut, (RegAsyncWriteOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Writeable Async Type') + + # test the write with high value + await rut.write(0xFFFFFFFF) + write_callback_mock.assert_called_once_with( + addr=72, + width=32, + accesswidth=rut.accesswidth, + data=0xFFFFFFFF) + write_callback_mock.reset_mock() + + # test the write of a low value + await rut.write(0) + write_callback_mock.assert_called_once_with( + addr=72, + width=32, + accesswidth=rut.accesswidth, + data=0) + write_callback_mock.reset_mock() + + # test the write of a random + random_value = random.randrange(0, 0xFFFFFFFF+1) + await rut.write(random_value) # type: ignore[union-attr] + write_callback_mock.assert_called_once_with( + addr=72, + width=32, + accesswidth=rut.accesswidth, + data=random_value) + write_callback_mock.reset_mock() + + # test writing a value beyond the register range is blocked with an exception being raised + with self.assertRaises(ValueError): + await rut.write(-1) + + with self.assertRaises(ValueError): + await rut.write(0xFFFFFFFF+1) + + # check the read has not been called in the write test + read_callback_mock.assert_not_called() + # test access operations (read and/or write) to register: + # msk_top_regs.PRBS_Error_Mask + with self.subTest(msg='register: msk_top_regs.PRBS_Error_Mask'): + rut=self.dut.PRBS_Error_Mask # type: ignore[union-attr,assignment] + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=1) as read_callback_mock: + + + if not isinstance(rut, (RegAsyncReadOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Readable Async Type') + + # test reading back 1 (the unpatched version returns 0 so this confirms the patch works) + self.assertEqual(await rut.read(), 1) + read_callback_mock.assert_called_once_with( + addr=76, + width=32, + accesswidth=rut.accesswidth) + + # test the read check with high value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await rut.read(), 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=76, + width=32, + accesswidth=rut.accesswidth) + + # test the read of the low value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0 + self.assertEqual(await rut.read(), 0x0) + read_callback_mock.assert_called_once_with( + addr=76, + width=32, + accesswidth=rut.accesswidth) + + # test the read of a random value + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.reset_mock() + read_callback_mock.return_value = random_value + self.assertEqual(await rut.read(), random_value) + read_callback_mock.assert_called_once_with( + addr=76, + width=32, + accesswidth=rut.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + + + if not isinstance(rut, (RegAsyncWriteOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Writeable Async Type') + + # test the write with high value + await rut.write(0xFFFFFFFF) + write_callback_mock.assert_called_once_with( + addr=76, + width=32, + accesswidth=rut.accesswidth, + data=0xFFFFFFFF) + write_callback_mock.reset_mock() + + # test the write of a low value + await rut.write(0) + write_callback_mock.assert_called_once_with( + addr=76, + width=32, + accesswidth=rut.accesswidth, + data=0) + write_callback_mock.reset_mock() + + # test the write of a random + random_value = random.randrange(0, 0xFFFFFFFF+1) + await rut.write(random_value) # type: ignore[union-attr] + write_callback_mock.assert_called_once_with( + addr=76, + width=32, + accesswidth=rut.accesswidth, + data=random_value) + write_callback_mock.reset_mock() + + # test writing a value beyond the register range is blocked with an exception being raised + with self.assertRaises(ValueError): + await rut.write(-1) + + with self.assertRaises(ValueError): + await rut.write(0xFFFFFFFF+1) + + # check the read has not been called in the write test + read_callback_mock.assert_not_called() + # test access operations (read and/or write) to register: + # msk_top_regs.PRBS_Bit_Count + with self.subTest(msg='register: msk_top_regs.PRBS_Bit_Count'): + rut=self.dut.PRBS_Bit_Count # type: ignore[union-attr,assignment] + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=1) as read_callback_mock: + + + if not isinstance(rut, (RegAsyncReadOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Readable Async Type') + + # test reading back 1 (the unpatched version returns 0 so this confirms the patch works) + self.assertEqual(await rut.read(), 1) + read_callback_mock.assert_called_once_with( + addr=80, + width=32, + accesswidth=rut.accesswidth) + + # test the read check with high value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await rut.read(), 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=80, + width=32, + accesswidth=rut.accesswidth) + + # test the read of the low value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0 + self.assertEqual(await rut.read(), 0x0) + read_callback_mock.assert_called_once_with( + addr=80, + width=32, + accesswidth=rut.accesswidth) + + # test the read of a random value + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.reset_mock() + read_callback_mock.return_value = random_value + self.assertEqual(await rut.read(), random_value) + read_callback_mock.assert_called_once_with( + addr=80, + width=32, + accesswidth=rut.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + + + # test that a non-writable register has no write method and attempting one generates and error + with self.assertRaises(AttributeError): + await rut.write(0) # type: ignore[attr-defined] + + # check the read has not been called in the write test + read_callback_mock.assert_not_called() + # test access operations (read and/or write) to register: + # msk_top_regs.PRBS_Error_Count + with self.subTest(msg='register: msk_top_regs.PRBS_Error_Count'): + rut=self.dut.PRBS_Error_Count # type: ignore[union-attr,assignment] + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=1) as read_callback_mock: + + + if not isinstance(rut, (RegAsyncReadOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Readable Async Type') + + # test reading back 1 (the unpatched version returns 0 so this confirms the patch works) + self.assertEqual(await rut.read(), 1) + read_callback_mock.assert_called_once_with( + addr=84, + width=32, + accesswidth=rut.accesswidth) + + # test the read check with high value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await rut.read(), 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=84, + width=32, + accesswidth=rut.accesswidth) + + # test the read of the low value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0 + self.assertEqual(await rut.read(), 0x0) + read_callback_mock.assert_called_once_with( + addr=84, + width=32, + accesswidth=rut.accesswidth) + + # test the read of a random value + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.reset_mock() + read_callback_mock.return_value = random_value + self.assertEqual(await rut.read(), random_value) + read_callback_mock.assert_called_once_with( + addr=84, + width=32, + accesswidth=rut.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + + + # test that a non-writable register has no write method and attempting one generates and error + with self.assertRaises(AttributeError): + await rut.write(0) # type: ignore[attr-defined] + + # check the read has not been called in the write test + read_callback_mock.assert_not_called() + # test access operations (read and/or write) to register: + # msk_top_regs.LPF_Accum_F1 + with self.subTest(msg='register: msk_top_regs.LPF_Accum_F1'): + rut=self.dut.LPF_Accum_F1 # type: ignore[union-attr,assignment] + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=1) as read_callback_mock: + + + if not isinstance(rut, (RegAsyncReadOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Readable Async Type') + + # test reading back 1 (the unpatched version returns 0 so this confirms the patch works) + self.assertEqual(await rut.read(), 1) + read_callback_mock.assert_called_once_with( + addr=88, + width=32, + accesswidth=rut.accesswidth) + + # test the read check with high value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await rut.read(), 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=88, + width=32, + accesswidth=rut.accesswidth) + + # test the read of the low value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0 + self.assertEqual(await rut.read(), 0x0) + read_callback_mock.assert_called_once_with( + addr=88, + width=32, + accesswidth=rut.accesswidth) + + # test the read of a random value + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.reset_mock() + read_callback_mock.return_value = random_value + self.assertEqual(await rut.read(), random_value) + read_callback_mock.assert_called_once_with( + addr=88, + width=32, + accesswidth=rut.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + + + # test that a non-writable register has no write method and attempting one generates and error + with self.assertRaises(AttributeError): + await rut.write(0) # type: ignore[attr-defined] + + # check the read has not been called in the write test + read_callback_mock.assert_not_called() + # test access operations (read and/or write) to register: + # msk_top_regs.LPF_Accum_F2 + with self.subTest(msg='register: msk_top_regs.LPF_Accum_F2'): + rut=self.dut.LPF_Accum_F2 # type: ignore[union-attr,assignment] + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=1) as read_callback_mock: + + + if not isinstance(rut, (RegAsyncReadOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Readable Async Type') + + # test reading back 1 (the unpatched version returns 0 so this confirms the patch works) + self.assertEqual(await rut.read(), 1) + read_callback_mock.assert_called_once_with( + addr=92, + width=32, + accesswidth=rut.accesswidth) + + # test the read check with high value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await rut.read(), 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=92, + width=32, + accesswidth=rut.accesswidth) + + # test the read of the low value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0 + self.assertEqual(await rut.read(), 0x0) + read_callback_mock.assert_called_once_with( + addr=92, + width=32, + accesswidth=rut.accesswidth) + + # test the read of a random value + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.reset_mock() + read_callback_mock.return_value = random_value + self.assertEqual(await rut.read(), random_value) + read_callback_mock.assert_called_once_with( + addr=92, + width=32, + accesswidth=rut.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + + + # test that a non-writable register has no write method and attempting one generates and error + with self.assertRaises(AttributeError): + await rut.write(0) # type: ignore[attr-defined] + + # check the read has not been called in the write test + read_callback_mock.assert_not_called() + # test access operations (read and/or write) to register: + # msk_top_regs.axis_xfer_count + with self.subTest(msg='register: msk_top_regs.axis_xfer_count'): + rut=self.dut.axis_xfer_count # type: ignore[union-attr,assignment] + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=1) as read_callback_mock: + + + if not isinstance(rut, (RegAsyncReadOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Readable Async Type') + + # test reading back 1 (the unpatched version returns 0 so this confirms the patch works) + self.assertEqual(await rut.read(), 1) + read_callback_mock.assert_called_once_with( + addr=96, + width=32, + accesswidth=rut.accesswidth) + + # test the read check with high value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await rut.read(), 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=96, + width=32, + accesswidth=rut.accesswidth) + + # test the read of the low value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0 + self.assertEqual(await rut.read(), 0x0) + read_callback_mock.assert_called_once_with( + addr=96, + width=32, + accesswidth=rut.accesswidth) + + # test the read of a random value + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.reset_mock() + read_callback_mock.return_value = random_value + self.assertEqual(await rut.read(), random_value) + read_callback_mock.assert_called_once_with( + addr=96, + width=32, + accesswidth=rut.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + + + # test that a non-writable register has no write method and attempting one generates and error + with self.assertRaises(AttributeError): + await rut.write(0) # type: ignore[attr-defined] + + # check the read has not been called in the write test + read_callback_mock.assert_not_called() + # test access operations (read and/or write) to register: + # msk_top_regs.Rx_Sample_Discard + with self.subTest(msg='register: msk_top_regs.Rx_Sample_Discard'): + rut=self.dut.Rx_Sample_Discard # type: ignore[union-attr,assignment] + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=1) as read_callback_mock: + + + if not isinstance(rut, (RegAsyncReadOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Readable Async Type') + + # test reading back 1 (the unpatched version returns 0 so this confirms the patch works) + self.assertEqual(await rut.read(), 1) + read_callback_mock.assert_called_once_with( + addr=100, + width=32, + accesswidth=rut.accesswidth) + + # test the read check with high value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await rut.read(), 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=100, + width=32, + accesswidth=rut.accesswidth) + + # test the read of the low value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0 + self.assertEqual(await rut.read(), 0x0) + read_callback_mock.assert_called_once_with( + addr=100, + width=32, + accesswidth=rut.accesswidth) + + # test the read of a random value + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.reset_mock() + read_callback_mock.return_value = random_value + self.assertEqual(await rut.read(), random_value) + read_callback_mock.assert_called_once_with( + addr=100, + width=32, + accesswidth=rut.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + + + if not isinstance(rut, (RegAsyncWriteOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Writeable Async Type') + + # test the write with high value + await rut.write(0xFFFFFFFF) + write_callback_mock.assert_called_once_with( + addr=100, + width=32, + accesswidth=rut.accesswidth, + data=0xFFFFFFFF) + write_callback_mock.reset_mock() + + # test the write of a low value + await rut.write(0) + write_callback_mock.assert_called_once_with( + addr=100, + width=32, + accesswidth=rut.accesswidth, + data=0) + write_callback_mock.reset_mock() + + # test the write of a random + random_value = random.randrange(0, 0xFFFFFFFF+1) + await rut.write(random_value) # type: ignore[union-attr] + write_callback_mock.assert_called_once_with( + addr=100, + width=32, + accesswidth=rut.accesswidth, + data=random_value) + write_callback_mock.reset_mock() + + # test writing a value beyond the register range is blocked with an exception being raised + with self.assertRaises(ValueError): + await rut.write(-1) + + with self.assertRaises(ValueError): + await rut.write(0xFFFFFFFF+1) + + # check the read has not been called in the write test + read_callback_mock.assert_not_called() + # test access operations (read and/or write) to register: + # msk_top_regs.LPF_Config_2 + with self.subTest(msg='register: msk_top_regs.LPF_Config_2'): + rut=self.dut.LPF_Config_2 # type: ignore[union-attr,assignment] + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=1) as read_callback_mock: + + + if not isinstance(rut, (RegAsyncReadOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Readable Async Type') + + # test reading back 1 (the unpatched version returns 0 so this confirms the patch works) + self.assertEqual(await rut.read(), 1) + read_callback_mock.assert_called_once_with( + addr=104, + width=32, + accesswidth=rut.accesswidth) + + # test the read check with high value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await rut.read(), 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=104, + width=32, + accesswidth=rut.accesswidth) + + # test the read of the low value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0 + self.assertEqual(await rut.read(), 0x0) + read_callback_mock.assert_called_once_with( + addr=104, + width=32, + accesswidth=rut.accesswidth) + + # test the read of a random value + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.reset_mock() + read_callback_mock.return_value = random_value + self.assertEqual(await rut.read(), random_value) + read_callback_mock.assert_called_once_with( + addr=104, + width=32, + accesswidth=rut.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + + + if not isinstance(rut, (RegAsyncWriteOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Writeable Async Type') + + # test the write with high value + await rut.write(0xFFFFFFFF) + write_callback_mock.assert_called_once_with( + addr=104, + width=32, + accesswidth=rut.accesswidth, + data=0xFFFFFFFF) + write_callback_mock.reset_mock() + + # test the write of a low value + await rut.write(0) + write_callback_mock.assert_called_once_with( + addr=104, + width=32, + accesswidth=rut.accesswidth, + data=0) + write_callback_mock.reset_mock() + + # test the write of a random + random_value = random.randrange(0, 0xFFFFFFFF+1) + await rut.write(random_value) # type: ignore[union-attr] + write_callback_mock.assert_called_once_with( + addr=104, + width=32, + accesswidth=rut.accesswidth, + data=random_value) + write_callback_mock.reset_mock() + + # test writing a value beyond the register range is blocked with an exception being raised + with self.assertRaises(ValueError): + await rut.write(-1) + + with self.assertRaises(ValueError): + await rut.write(0xFFFFFFFF+1) + + # check the read has not been called in the write test + read_callback_mock.assert_not_called() + # test access operations (read and/or write) to register: + # msk_top_regs.f1_nco_adjust + with self.subTest(msg='register: msk_top_regs.f1_nco_adjust'): + rut=self.dut.f1_nco_adjust # type: ignore[union-attr,assignment] + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=1) as read_callback_mock: + + + if not isinstance(rut, (RegAsyncReadOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Readable Async Type') + + # test reading back 1 (the unpatched version returns 0 so this confirms the patch works) + self.assertEqual(await rut.read(), 1) + read_callback_mock.assert_called_once_with( + addr=108, + width=32, + accesswidth=rut.accesswidth) + + # test the read check with high value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await rut.read(), 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=108, + width=32, + accesswidth=rut.accesswidth) + + # test the read of the low value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0 + self.assertEqual(await rut.read(), 0x0) + read_callback_mock.assert_called_once_with( + addr=108, + width=32, + accesswidth=rut.accesswidth) + + # test the read of a random value + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.reset_mock() + read_callback_mock.return_value = random_value + self.assertEqual(await rut.read(), random_value) + read_callback_mock.assert_called_once_with( + addr=108, + width=32, + accesswidth=rut.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + + + # test that a non-writable register has no write method and attempting one generates and error + with self.assertRaises(AttributeError): + await rut.write(0) # type: ignore[attr-defined] + + # check the read has not been called in the write test + read_callback_mock.assert_not_called() + # test access operations (read and/or write) to register: + # msk_top_regs.f2_nco_adjust + with self.subTest(msg='register: msk_top_regs.f2_nco_adjust'): + rut=self.dut.f2_nco_adjust # type: ignore[union-attr,assignment] + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=1) as read_callback_mock: + + + if not isinstance(rut, (RegAsyncReadOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Readable Async Type') + + # test reading back 1 (the unpatched version returns 0 so this confirms the patch works) + self.assertEqual(await rut.read(), 1) + read_callback_mock.assert_called_once_with( + addr=112, + width=32, + accesswidth=rut.accesswidth) + + # test the read check with high value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await rut.read(), 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=112, + width=32, + accesswidth=rut.accesswidth) + + # test the read of the low value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0 + self.assertEqual(await rut.read(), 0x0) + read_callback_mock.assert_called_once_with( + addr=112, + width=32, + accesswidth=rut.accesswidth) + + # test the read of a random value + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.reset_mock() + read_callback_mock.return_value = random_value + self.assertEqual(await rut.read(), random_value) + read_callback_mock.assert_called_once_with( + addr=112, + width=32, + accesswidth=rut.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + + + # test that a non-writable register has no write method and attempting one generates and error + with self.assertRaises(AttributeError): + await rut.write(0) # type: ignore[attr-defined] + + # check the read has not been called in the write test + read_callback_mock.assert_not_called() + # test access operations (read and/or write) to register: + # msk_top_regs.f1_error + with self.subTest(msg='register: msk_top_regs.f1_error'): + rut=self.dut.f1_error # type: ignore[union-attr,assignment] + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=1) as read_callback_mock: + + + if not isinstance(rut, (RegAsyncReadOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Readable Async Type') + + # test reading back 1 (the unpatched version returns 0 so this confirms the patch works) + self.assertEqual(await rut.read(), 1) + read_callback_mock.assert_called_once_with( + addr=116, + width=32, + accesswidth=rut.accesswidth) + + # test the read check with high value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await rut.read(), 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=116, + width=32, + accesswidth=rut.accesswidth) + + # test the read of the low value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0 + self.assertEqual(await rut.read(), 0x0) + read_callback_mock.assert_called_once_with( + addr=116, + width=32, + accesswidth=rut.accesswidth) + + # test the read of a random value + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.reset_mock() + read_callback_mock.return_value = random_value + self.assertEqual(await rut.read(), random_value) + read_callback_mock.assert_called_once_with( + addr=116, + width=32, + accesswidth=rut.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + + + # test that a non-writable register has no write method and attempting one generates and error + with self.assertRaises(AttributeError): + await rut.write(0) # type: ignore[attr-defined] + + # check the read has not been called in the write test + read_callback_mock.assert_not_called() + # test access operations (read and/or write) to register: + # msk_top_regs.f2_error + with self.subTest(msg='register: msk_top_regs.f2_error'): + rut=self.dut.f2_error # type: ignore[union-attr,assignment] + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=1) as read_callback_mock: + + + if not isinstance(rut, (RegAsyncReadOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Readable Async Type') + + # test reading back 1 (the unpatched version returns 0 so this confirms the patch works) + self.assertEqual(await rut.read(), 1) + read_callback_mock.assert_called_once_with( + addr=120, + width=32, + accesswidth=rut.accesswidth) + + # test the read check with high value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await rut.read(), 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=120, + width=32, + accesswidth=rut.accesswidth) + + # test the read of the low value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0 + self.assertEqual(await rut.read(), 0x0) + read_callback_mock.assert_called_once_with( + addr=120, + width=32, + accesswidth=rut.accesswidth) + + # test the read of a random value + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.reset_mock() + read_callback_mock.return_value = random_value + self.assertEqual(await rut.read(), random_value) + read_callback_mock.assert_called_once_with( + addr=120, + width=32, + accesswidth=rut.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + + + # test that a non-writable register has no write method and attempting one generates and error + with self.assertRaises(AttributeError): + await rut.write(0) # type: ignore[attr-defined] + + # check the read has not been called in the write test + read_callback_mock.assert_not_called() + # test access operations (read and/or write) to register: + # msk_top_regs.Tx_Sync_Ctrl + with self.subTest(msg='register: msk_top_regs.Tx_Sync_Ctrl'): + rut=self.dut.Tx_Sync_Ctrl # type: ignore[union-attr,assignment] + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=1) as read_callback_mock: + + + if not isinstance(rut, (RegAsyncReadOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Readable Async Type') + + # test reading back 1 (the unpatched version returns 0 so this confirms the patch works) + self.assertEqual(await rut.read(), 1) + read_callback_mock.assert_called_once_with( + addr=124, + width=32, + accesswidth=rut.accesswidth) + + # test the read check with high value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await rut.read(), 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=124, + width=32, + accesswidth=rut.accesswidth) + + # test the read of the low value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0 + self.assertEqual(await rut.read(), 0x0) + read_callback_mock.assert_called_once_with( + addr=124, + width=32, + accesswidth=rut.accesswidth) + + # test the read of a random value + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.reset_mock() + read_callback_mock.return_value = random_value + self.assertEqual(await rut.read(), random_value) + read_callback_mock.assert_called_once_with( + addr=124, + width=32, + accesswidth=rut.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + + + if not isinstance(rut, (RegAsyncWriteOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Writeable Async Type') + + # test the write with high value + await rut.write(0xFFFFFFFF) + write_callback_mock.assert_called_once_with( + addr=124, + width=32, + accesswidth=rut.accesswidth, + data=0xFFFFFFFF) + write_callback_mock.reset_mock() + + # test the write of a low value + await rut.write(0) + write_callback_mock.assert_called_once_with( + addr=124, + width=32, + accesswidth=rut.accesswidth, + data=0) + write_callback_mock.reset_mock() + + # test the write of a random + random_value = random.randrange(0, 0xFFFFFFFF+1) + await rut.write(random_value) # type: ignore[union-attr] + write_callback_mock.assert_called_once_with( + addr=124, + width=32, + accesswidth=rut.accesswidth, + data=random_value) + write_callback_mock.reset_mock() + + # test writing a value beyond the register range is blocked with an exception being raised + with self.assertRaises(ValueError): + await rut.write(-1) + + with self.assertRaises(ValueError): + await rut.write(0xFFFFFFFF+1) + + # check the read has not been called in the write test + read_callback_mock.assert_not_called() + # test access operations (read and/or write) to register: + # msk_top_regs.Tx_Sync_Cnt + with self.subTest(msg='register: msk_top_regs.Tx_Sync_Cnt'): + rut=self.dut.Tx_Sync_Cnt # type: ignore[union-attr,assignment] + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=1) as read_callback_mock: + + + if not isinstance(rut, (RegAsyncReadOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Readable Async Type') + + # test reading back 1 (the unpatched version returns 0 so this confirms the patch works) + self.assertEqual(await rut.read(), 1) + read_callback_mock.assert_called_once_with( + addr=128, + width=32, + accesswidth=rut.accesswidth) + + # test the read check with high value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await rut.read(), 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=128, + width=32, + accesswidth=rut.accesswidth) + + # test the read of the low value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0 + self.assertEqual(await rut.read(), 0x0) + read_callback_mock.assert_called_once_with( + addr=128, + width=32, + accesswidth=rut.accesswidth) + + # test the read of a random value + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.reset_mock() + read_callback_mock.return_value = random_value + self.assertEqual(await rut.read(), random_value) + read_callback_mock.assert_called_once_with( + addr=128, + width=32, + accesswidth=rut.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + + + if not isinstance(rut, (RegAsyncWriteOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Writeable Async Type') + + # test the write with high value + await rut.write(0xFFFFFFFF) + write_callback_mock.assert_called_once_with( + addr=128, + width=32, + accesswidth=rut.accesswidth, + data=0xFFFFFFFF) + write_callback_mock.reset_mock() + + # test the write of a low value + await rut.write(0) + write_callback_mock.assert_called_once_with( + addr=128, + width=32, + accesswidth=rut.accesswidth, + data=0) + write_callback_mock.reset_mock() + + # test the write of a random + random_value = random.randrange(0, 0xFFFFFFFF+1) + await rut.write(random_value) # type: ignore[union-attr] + write_callback_mock.assert_called_once_with( + addr=128, + width=32, + accesswidth=rut.accesswidth, + data=random_value) + write_callback_mock.reset_mock() + + # test writing a value beyond the register range is blocked with an exception being raised + with self.assertRaises(ValueError): + await rut.write(-1) + + with self.assertRaises(ValueError): + await rut.write(0xFFFFFFFF+1) + + # check the read has not been called in the write test + read_callback_mock.assert_not_called() + # test access operations (read and/or write) to register: + # msk_top_regs.lowpass_ema_alpha1 + with self.subTest(msg='register: msk_top_regs.lowpass_ema_alpha1'): + rut=self.dut.lowpass_ema_alpha1 # type: ignore[union-attr,assignment] + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=1) as read_callback_mock: + + + if not isinstance(rut, (RegAsyncReadOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Readable Async Type') + + # test reading back 1 (the unpatched version returns 0 so this confirms the patch works) + self.assertEqual(await rut.read(), 1) + read_callback_mock.assert_called_once_with( + addr=132, + width=32, + accesswidth=rut.accesswidth) + + # test the read check with high value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await rut.read(), 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=132, + width=32, + accesswidth=rut.accesswidth) + + # test the read of the low value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0 + self.assertEqual(await rut.read(), 0x0) + read_callback_mock.assert_called_once_with( + addr=132, + width=32, + accesswidth=rut.accesswidth) + + # test the read of a random value + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.reset_mock() + read_callback_mock.return_value = random_value + self.assertEqual(await rut.read(), random_value) + read_callback_mock.assert_called_once_with( + addr=132, + width=32, + accesswidth=rut.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + + + if not isinstance(rut, (RegAsyncWriteOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Writeable Async Type') + + # test the write with high value + await rut.write(0xFFFFFFFF) + write_callback_mock.assert_called_once_with( + addr=132, + width=32, + accesswidth=rut.accesswidth, + data=0xFFFFFFFF) + write_callback_mock.reset_mock() + + # test the write of a low value + await rut.write(0) + write_callback_mock.assert_called_once_with( + addr=132, + width=32, + accesswidth=rut.accesswidth, + data=0) + write_callback_mock.reset_mock() + + # test the write of a random + random_value = random.randrange(0, 0xFFFFFFFF+1) + await rut.write(random_value) # type: ignore[union-attr] + write_callback_mock.assert_called_once_with( + addr=132, + width=32, + accesswidth=rut.accesswidth, + data=random_value) + write_callback_mock.reset_mock() + + # test writing a value beyond the register range is blocked with an exception being raised + with self.assertRaises(ValueError): + await rut.write(-1) + + with self.assertRaises(ValueError): + await rut.write(0xFFFFFFFF+1) + + # check the read has not been called in the write test + read_callback_mock.assert_not_called() + # test access operations (read and/or write) to register: + # msk_top_regs.lowpass_ema_alpha2 + with self.subTest(msg='register: msk_top_regs.lowpass_ema_alpha2'): + rut=self.dut.lowpass_ema_alpha2 # type: ignore[union-attr,assignment] + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=1) as read_callback_mock: + + + if not isinstance(rut, (RegAsyncReadOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Readable Async Type') + + # test reading back 1 (the unpatched version returns 0 so this confirms the patch works) + self.assertEqual(await rut.read(), 1) + read_callback_mock.assert_called_once_with( + addr=136, + width=32, + accesswidth=rut.accesswidth) + + # test the read check with high value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await rut.read(), 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=136, + width=32, + accesswidth=rut.accesswidth) + + # test the read of the low value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0 + self.assertEqual(await rut.read(), 0x0) + read_callback_mock.assert_called_once_with( + addr=136, + width=32, + accesswidth=rut.accesswidth) + + # test the read of a random value + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.reset_mock() + read_callback_mock.return_value = random_value + self.assertEqual(await rut.read(), random_value) + read_callback_mock.assert_called_once_with( + addr=136, + width=32, + accesswidth=rut.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + + + if not isinstance(rut, (RegAsyncWriteOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Writeable Async Type') + + # test the write with high value + await rut.write(0xFFFFFFFF) + write_callback_mock.assert_called_once_with( + addr=136, + width=32, + accesswidth=rut.accesswidth, + data=0xFFFFFFFF) + write_callback_mock.reset_mock() + + # test the write of a low value + await rut.write(0) + write_callback_mock.assert_called_once_with( + addr=136, + width=32, + accesswidth=rut.accesswidth, + data=0) + write_callback_mock.reset_mock() + + # test the write of a random + random_value = random.randrange(0, 0xFFFFFFFF+1) + await rut.write(random_value) # type: ignore[union-attr] + write_callback_mock.assert_called_once_with( + addr=136, + width=32, + accesswidth=rut.accesswidth, + data=random_value) + write_callback_mock.reset_mock() + + # test writing a value beyond the register range is blocked with an exception being raised + with self.assertRaises(ValueError): + await rut.write(-1) + + with self.assertRaises(ValueError): + await rut.write(0xFFFFFFFF+1) + + # check the read has not been called in the write test + read_callback_mock.assert_not_called() + # test access operations (read and/or write) to register: + # msk_top_regs.rx_power + with self.subTest(msg='register: msk_top_regs.rx_power'): + rut=self.dut.rx_power # type: ignore[union-attr,assignment] + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=1) as read_callback_mock: + + + if not isinstance(rut, (RegAsyncReadOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Readable Async Type') + + # test reading back 1 (the unpatched version returns 0 so this confirms the patch works) + self.assertEqual(await rut.read(), 1) + read_callback_mock.assert_called_once_with( + addr=140, + width=32, + accesswidth=rut.accesswidth) + + # test the read check with high value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await rut.read(), 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=140, + width=32, + accesswidth=rut.accesswidth) + + # test the read of the low value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0 + self.assertEqual(await rut.read(), 0x0) + read_callback_mock.assert_called_once_with( + addr=140, + width=32, + accesswidth=rut.accesswidth) + + # test the read of a random value + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.reset_mock() + read_callback_mock.return_value = random_value + self.assertEqual(await rut.read(), random_value) + read_callback_mock.assert_called_once_with( + addr=140, + width=32, + accesswidth=rut.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + + + # test that a non-writable register has no write method and attempting one generates and error + with self.assertRaises(AttributeError): + await rut.write(0) # type: ignore[attr-defined] + + # check the read has not been called in the write test + read_callback_mock.assert_not_called() + + + async def test_int_field_read_and_write(self) -> None: + """ + Check the ability to read and write to integer (non-eumn) fields + """ + fut:Field + + + # test access operations (read and/or write) to field: + # msk_top_regs.Hash_ID_Low.hash_id_lo + with self.subTest(msg='field: msk_top_regs.Hash_ID_Low.hash_id_lo'): + fut = self.dut.Hash_ID_Low.hash_id_lo # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0x0 + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=0, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await fut.read(), + 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=0, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=0, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + # test access operations (read and/or write) to field: + # msk_top_regs.Hash_ID_High.hash_id_hi + with self.subTest(msg='field: msk_top_regs.Hash_ID_High.hash_id_hi'): + fut = self.dut.Hash_ID_High.hash_id_hi # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0x0 + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=4, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await fut.read(), + 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=4, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=4, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + # test access operations (read and/or write) to field: + # msk_top_regs.MSK_Init.txrxinit + with self.subTest(msg='field: msk_top_regs.MSK_Init.txrxinit'): + fut = self.dut.MSK_Init.txrxinit # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0xFFFFFFFE + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=8, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0x1 + self.assertEqual(await fut.read(), + 0x1) + read_callback_mock.assert_called_once_with( + addr=8, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0x1) >> 0 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=8, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0x1 + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0x1, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.MSK_Init.txrxinit.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_called_once_with( + addr=8, + width=32, + accesswidth=fut.parent_register.accesswidth) + + write_callback_mock.assert_called_once_with( + addr=8, + width=32, + accesswidth=self.dut.MSK_Init.txrxinit.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0xFFFFFFFE) | \ + (0x1 & (field_value << 0))) + + + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0x1 + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) + + # test access operations (read and/or write) to field: + # msk_top_regs.MSK_Init.txinit + with self.subTest(msg='field: msk_top_regs.MSK_Init.txinit'): + fut = self.dut.MSK_Init.txinit # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0xFFFFFFFD + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=8, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0x2 + self.assertEqual(await fut.read(), + 0x1) + read_callback_mock.assert_called_once_with( + addr=8, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0x2) >> 1 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=8, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0x1 + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0x1, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.MSK_Init.txinit.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_called_once_with( + addr=8, + width=32, + accesswidth=fut.parent_register.accesswidth) + + write_callback_mock.assert_called_once_with( + addr=8, + width=32, + accesswidth=self.dut.MSK_Init.txinit.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0xFFFFFFFD) | \ + (0x2 & (field_value << 1))) + + + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0x1 + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) + + # test access operations (read and/or write) to field: + # msk_top_regs.MSK_Init.rxinit + with self.subTest(msg='field: msk_top_regs.MSK_Init.rxinit'): + fut = self.dut.MSK_Init.rxinit # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0xFFFFFFFB + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=8, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0x4 + self.assertEqual(await fut.read(), + 0x1) + read_callback_mock.assert_called_once_with( + addr=8, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0x4) >> 2 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=8, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0x1 + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0x1, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.MSK_Init.rxinit.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_called_once_with( + addr=8, + width=32, + accesswidth=fut.parent_register.accesswidth) + + write_callback_mock.assert_called_once_with( + addr=8, + width=32, + accesswidth=self.dut.MSK_Init.rxinit.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0xFFFFFFFB) | \ + (0x4 & (field_value << 2))) + + + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0x1 + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) + + # test access operations (read and/or write) to field: + # msk_top_regs.MSK_Control.ptt + with self.subTest(msg='field: msk_top_regs.MSK_Control.ptt'): + fut = self.dut.MSK_Control.ptt # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0xFFFFFFFE + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=12, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0x1 + self.assertEqual(await fut.read(), + 0x1) + read_callback_mock.assert_called_once_with( + addr=12, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0x1) >> 0 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=12, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0x1 + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0x1, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.MSK_Control.ptt.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_called_once_with( + addr=12, + width=32, + accesswidth=fut.parent_register.accesswidth) + + write_callback_mock.assert_called_once_with( + addr=12, + width=32, + accesswidth=self.dut.MSK_Control.ptt.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0xFFFFFFFE) | \ + (0x1 & (field_value << 0))) + + + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0x1 + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) + + # test access operations (read and/or write) to field: + # msk_top_regs.MSK_Control.loopback_ena + with self.subTest(msg='field: msk_top_regs.MSK_Control.loopback_ena'): + fut = self.dut.MSK_Control.loopback_ena # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0xFFFFFFFD + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=12, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0x2 + self.assertEqual(await fut.read(), + 0x1) + read_callback_mock.assert_called_once_with( + addr=12, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0x2) >> 1 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=12, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0x1 + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0x1, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.MSK_Control.loopback_ena.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_called_once_with( + addr=12, + width=32, + accesswidth=fut.parent_register.accesswidth) + + write_callback_mock.assert_called_once_with( + addr=12, + width=32, + accesswidth=self.dut.MSK_Control.loopback_ena.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0xFFFFFFFD) | \ + (0x2 & (field_value << 1))) + + + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0x1 + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) + + # test access operations (read and/or write) to field: + # msk_top_regs.MSK_Control.rx_invert + with self.subTest(msg='field: msk_top_regs.MSK_Control.rx_invert'): + fut = self.dut.MSK_Control.rx_invert # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0xFFFFFFFB + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=12, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0x4 + self.assertEqual(await fut.read(), + 0x1) + read_callback_mock.assert_called_once_with( + addr=12, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0x4) >> 2 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=12, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0x1 + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0x1, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.MSK_Control.rx_invert.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_called_once_with( + addr=12, + width=32, + accesswidth=fut.parent_register.accesswidth) + + write_callback_mock.assert_called_once_with( + addr=12, + width=32, + accesswidth=self.dut.MSK_Control.rx_invert.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0xFFFFFFFB) | \ + (0x4 & (field_value << 2))) + + + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0x1 + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) + + # test access operations (read and/or write) to field: + # msk_top_regs.MSK_Control.clear_counts + with self.subTest(msg='field: msk_top_regs.MSK_Control.clear_counts'): + fut = self.dut.MSK_Control.clear_counts # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0xFFFFFFF7 + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=12, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0x8 + self.assertEqual(await fut.read(), + 0x1) + read_callback_mock.assert_called_once_with( + addr=12, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0x8) >> 3 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=12, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0x1 + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0x1, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.MSK_Control.clear_counts.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_called_once_with( + addr=12, + width=32, + accesswidth=fut.parent_register.accesswidth) + + write_callback_mock.assert_called_once_with( + addr=12, + width=32, + accesswidth=self.dut.MSK_Control.clear_counts.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0xFFFFFFF7) | \ + (0x8 & (field_value << 3))) + + + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0x1 + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) + + # test access operations (read and/or write) to field: + # msk_top_regs.MSK_Control.diff_encoder_loopback + with self.subTest(msg='field: msk_top_regs.MSK_Control.diff_encoder_loopback'): + fut = self.dut.MSK_Control.diff_encoder_loopback # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0xFFFFFFEF + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=12, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0x10 + self.assertEqual(await fut.read(), + 0x1) + read_callback_mock.assert_called_once_with( + addr=12, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0x10) >> 4 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=12, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0x1 + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0x1, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.MSK_Control.diff_encoder_loopback.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_called_once_with( + addr=12, + width=32, + accesswidth=fut.parent_register.accesswidth) + + write_callback_mock.assert_called_once_with( + addr=12, + width=32, + accesswidth=self.dut.MSK_Control.diff_encoder_loopback.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0xFFFFFFEF) | \ + (0x10 & (field_value << 4))) + + + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0x1 + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) + + # test access operations (read and/or write) to field: + # msk_top_regs.MSK_Status.demod_sync_lock + with self.subTest(msg='field: msk_top_regs.MSK_Status.demod_sync_lock'): + fut = self.dut.MSK_Status.demod_sync_lock # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0xFFFFFFFE + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=16, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0x1 + self.assertEqual(await fut.read(), + 0x1) + read_callback_mock.assert_called_once_with( + addr=16, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0x1) >> 0 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=16, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + # test access operations (read and/or write) to field: + # msk_top_regs.MSK_Status.tx_enable + with self.subTest(msg='field: msk_top_regs.MSK_Status.tx_enable'): + fut = self.dut.MSK_Status.tx_enable # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0xFFFFFFFD + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=16, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0x2 + self.assertEqual(await fut.read(), + 0x1) + read_callback_mock.assert_called_once_with( + addr=16, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0x2) >> 1 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=16, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + # test access operations (read and/or write) to field: + # msk_top_regs.MSK_Status.rx_enable + with self.subTest(msg='field: msk_top_regs.MSK_Status.rx_enable'): + fut = self.dut.MSK_Status.rx_enable # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0xFFFFFFFB + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=16, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0x4 + self.assertEqual(await fut.read(), + 0x1) + read_callback_mock.assert_called_once_with( + addr=16, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0x4) >> 2 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=16, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + # test access operations (read and/or write) to field: + # msk_top_regs.MSK_Status.tx_axis_valid + with self.subTest(msg='field: msk_top_regs.MSK_Status.tx_axis_valid'): + fut = self.dut.MSK_Status.tx_axis_valid # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0xFFFFFFF7 + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=16, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0x8 + self.assertEqual(await fut.read(), + 0x1) + read_callback_mock.assert_called_once_with( + addr=16, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0x8) >> 3 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=16, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + # test access operations (read and/or write) to field: + # msk_top_regs.Tx_Bit_Count.tx_bit_counter + with self.subTest(msg='field: msk_top_regs.Tx_Bit_Count.tx_bit_counter'): + fut = self.dut.Tx_Bit_Count.tx_bit_counter # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0x0 + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=20, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await fut.read(), + 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=20, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=20, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + # test access operations (read and/or write) to field: + # msk_top_regs.Tx_Enable_Count.tx_ena_counter + with self.subTest(msg='field: msk_top_regs.Tx_Enable_Count.tx_ena_counter'): + fut = self.dut.Tx_Enable_Count.tx_ena_counter # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0x0 + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=24, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await fut.read(), + 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=24, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=24, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + # test access operations (read and/or write) to field: + # msk_top_regs.Fb_FreqWord.config_data + with self.subTest(msg='field: msk_top_regs.Fb_FreqWord.config_data'): + fut = self.dut.Fb_FreqWord.config_data # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0x0 + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=28, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await fut.read(), + 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=28, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=28, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0xFFFFFFFF + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0xFFFFFFFF, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.Fb_FreqWord.config_data.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_not_called() + write_callback_mock.assert_called_once_with( + addr=28, + width=32, + accesswidth=self.dut.Fb_FreqWord.config_data.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0x0) | \ + (0xFFFFFFFF & (field_value << 0))) + + + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0xFFFFFFFF + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) + + # test access operations (read and/or write) to field: + # msk_top_regs.TX_F1_FreqWord.config_data + with self.subTest(msg='field: msk_top_regs.TX_F1_FreqWord.config_data'): + fut = self.dut.TX_F1_FreqWord.config_data # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0x0 + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=32, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await fut.read(), + 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=32, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=32, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0xFFFFFFFF + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0xFFFFFFFF, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.TX_F1_FreqWord.config_data.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_not_called() + write_callback_mock.assert_called_once_with( + addr=32, + width=32, + accesswidth=self.dut.TX_F1_FreqWord.config_data.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0x0) | \ + (0xFFFFFFFF & (field_value << 0))) + + + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0xFFFFFFFF + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) + + # test access operations (read and/or write) to field: + # msk_top_regs.TX_F2_FreqWord.config_data + with self.subTest(msg='field: msk_top_regs.TX_F2_FreqWord.config_data'): + fut = self.dut.TX_F2_FreqWord.config_data # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0x0 + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=36, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await fut.read(), + 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=36, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=36, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0xFFFFFFFF + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0xFFFFFFFF, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.TX_F2_FreqWord.config_data.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_not_called() + write_callback_mock.assert_called_once_with( + addr=36, + width=32, + accesswidth=self.dut.TX_F2_FreqWord.config_data.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0x0) | \ + (0xFFFFFFFF & (field_value << 0))) + + + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0xFFFFFFFF + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) + + # test access operations (read and/or write) to field: + # msk_top_regs.RX_F1_FreqWord.config_data + with self.subTest(msg='field: msk_top_regs.RX_F1_FreqWord.config_data'): + fut = self.dut.RX_F1_FreqWord.config_data # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0x0 + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=40, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await fut.read(), + 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=40, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=40, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0xFFFFFFFF + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0xFFFFFFFF, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.RX_F1_FreqWord.config_data.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_not_called() + write_callback_mock.assert_called_once_with( + addr=40, + width=32, + accesswidth=self.dut.RX_F1_FreqWord.config_data.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0x0) | \ + (0xFFFFFFFF & (field_value << 0))) + + + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0xFFFFFFFF + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) + + # test access operations (read and/or write) to field: + # msk_top_regs.RX_F2_FreqWord.config_data + with self.subTest(msg='field: msk_top_regs.RX_F2_FreqWord.config_data'): + fut = self.dut.RX_F2_FreqWord.config_data # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0x0 + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=44, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await fut.read(), + 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=44, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=44, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0xFFFFFFFF + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0xFFFFFFFF, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.RX_F2_FreqWord.config_data.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_not_called() + write_callback_mock.assert_called_once_with( + addr=44, + width=32, + accesswidth=self.dut.RX_F2_FreqWord.config_data.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0x0) | \ + (0xFFFFFFFF & (field_value << 0))) + + + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0xFFFFFFFF + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) + + # test access operations (read and/or write) to field: + # msk_top_regs.LPF_Config_0.lpf_freeze + with self.subTest(msg='field: msk_top_regs.LPF_Config_0.lpf_freeze'): + fut = self.dut.LPF_Config_0.lpf_freeze # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0xFFFFFFFE + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=48, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0x1 + self.assertEqual(await fut.read(), + 0x1) + read_callback_mock.assert_called_once_with( + addr=48, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0x1) >> 0 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=48, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0x1 + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0x1, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.LPF_Config_0.lpf_freeze.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_called_once_with( + addr=48, + width=32, + accesswidth=fut.parent_register.accesswidth) + + write_callback_mock.assert_called_once_with( + addr=48, + width=32, + accesswidth=self.dut.LPF_Config_0.lpf_freeze.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0xFFFFFFFE) | \ + (0x1 & (field_value << 0))) + + + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0x1 + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) + + # test access operations (read and/or write) to field: + # msk_top_regs.LPF_Config_0.lpf_zero + with self.subTest(msg='field: msk_top_regs.LPF_Config_0.lpf_zero'): + fut = self.dut.LPF_Config_0.lpf_zero # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0xFFFFFFFD + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=48, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0x2 + self.assertEqual(await fut.read(), + 0x1) + read_callback_mock.assert_called_once_with( + addr=48, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0x2) >> 1 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=48, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0x1 + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0x1, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.LPF_Config_0.lpf_zero.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_called_once_with( + addr=48, + width=32, + accesswidth=fut.parent_register.accesswidth) + + write_callback_mock.assert_called_once_with( + addr=48, + width=32, + accesswidth=self.dut.LPF_Config_0.lpf_zero.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0xFFFFFFFD) | \ + (0x2 & (field_value << 1))) + + + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0x1 + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) + + # test access operations (read and/or write) to field: + # msk_top_regs.LPF_Config_0.prbs_reserved + with self.subTest(msg='field: msk_top_regs.LPF_Config_0.prbs_reserved'): + fut = self.dut.LPF_Config_0.prbs_reserved # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0xFFFFFF03 + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=48, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFC + self.assertEqual(await fut.read(), + 0x3F) + read_callback_mock.assert_called_once_with( + addr=48, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0xFC) >> 2 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=48, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0x3F + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0x3F, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.LPF_Config_0.prbs_reserved.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_called_once_with( + addr=48, + width=32, + accesswidth=fut.parent_register.accesswidth) + + write_callback_mock.assert_called_once_with( + addr=48, + width=32, + accesswidth=self.dut.LPF_Config_0.prbs_reserved.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0xFFFFFF03) | \ + (0xFC & (field_value << 2))) + + + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0x3F + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) + + # test access operations (read and/or write) to field: + # msk_top_regs.LPF_Config_0.lpf_alpha + with self.subTest(msg='field: msk_top_regs.LPF_Config_0.lpf_alpha'): + fut = self.dut.LPF_Config_0.lpf_alpha # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0xFF + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=48, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFF00 + self.assertEqual(await fut.read(), + 0xFFFFFF) + read_callback_mock.assert_called_once_with( + addr=48, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0xFFFFFF00) >> 8 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=48, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0xFFFFFF + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0xFFFFFF, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.LPF_Config_0.lpf_alpha.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_called_once_with( + addr=48, + width=32, + accesswidth=fut.parent_register.accesswidth) + + write_callback_mock.assert_called_once_with( + addr=48, + width=32, + accesswidth=self.dut.LPF_Config_0.lpf_alpha.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0xFF) | \ + (0xFFFFFF00 & (field_value << 8))) + + + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0xFFFFFF + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) + + # test access operations (read and/or write) to field: + # msk_top_regs.LPF_Config_1.i_gain + with self.subTest(msg='field: msk_top_regs.LPF_Config_1.i_gain'): + fut = self.dut.LPF_Config_1.i_gain # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0xFF000000 + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=52, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFF + self.assertEqual(await fut.read(), + 0xFFFFFF) + read_callback_mock.assert_called_once_with( + addr=52, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0xFFFFFF) >> 0 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=52, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0xFFFFFF + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0xFFFFFF, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.LPF_Config_1.i_gain.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_called_once_with( + addr=52, + width=32, + accesswidth=fut.parent_register.accesswidth) + + write_callback_mock.assert_called_once_with( + addr=52, + width=32, + accesswidth=self.dut.LPF_Config_1.i_gain.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0xFF000000) | \ + (0xFFFFFF & (field_value << 0))) + + + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0xFFFFFF + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) + + # test access operations (read and/or write) to field: + # msk_top_regs.LPF_Config_1.i_shift + with self.subTest(msg='field: msk_top_regs.LPF_Config_1.i_shift'): + fut = self.dut.LPF_Config_1.i_shift # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0xFFFFFF + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=52, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFF000000 + self.assertEqual(await fut.read(), + 0xFF) + read_callback_mock.assert_called_once_with( + addr=52, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0xFF000000) >> 24 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=52, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0xFF + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0xFF, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.LPF_Config_1.i_shift.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_called_once_with( + addr=52, + width=32, + accesswidth=fut.parent_register.accesswidth) + + write_callback_mock.assert_called_once_with( + addr=52, + width=32, + accesswidth=self.dut.LPF_Config_1.i_shift.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0xFFFFFF) | \ + (0xFF000000 & (field_value << 24))) + + + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0xFF + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) + + # test access operations (read and/or write) to field: + # msk_top_regs.Tx_Data_Width.data_width + with self.subTest(msg='field: msk_top_regs.Tx_Data_Width.data_width'): + fut = self.dut.Tx_Data_Width.data_width # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0xFFFFFF00 + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=56, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFF + self.assertEqual(await fut.read(), + 0xFF) + read_callback_mock.assert_called_once_with( + addr=56, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0xFF) >> 0 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=56, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0xFF + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0xFF, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.Tx_Data_Width.data_width.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_called_once_with( + addr=56, + width=32, + accesswidth=fut.parent_register.accesswidth) + + write_callback_mock.assert_called_once_with( + addr=56, + width=32, + accesswidth=self.dut.Tx_Data_Width.data_width.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0xFFFFFF00) | \ + (0xFF & (field_value << 0))) + + + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0xFF + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) + + # test access operations (read and/or write) to field: + # msk_top_regs.Rx_Data_Width.data_width + with self.subTest(msg='field: msk_top_regs.Rx_Data_Width.data_width'): + fut = self.dut.Rx_Data_Width.data_width # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0xFFFFFF00 + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=60, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFF + self.assertEqual(await fut.read(), + 0xFF) + read_callback_mock.assert_called_once_with( + addr=60, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0xFF) >> 0 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=60, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0xFF + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0xFF, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.Rx_Data_Width.data_width.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_called_once_with( + addr=60, + width=32, + accesswidth=fut.parent_register.accesswidth) + + write_callback_mock.assert_called_once_with( + addr=60, + width=32, + accesswidth=self.dut.Rx_Data_Width.data_width.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0xFFFFFF00) | \ + (0xFF & (field_value << 0))) + + + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0xFF + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) + + # test access operations (read and/or write) to field: + # msk_top_regs.PRBS_Control.prbs_sel + with self.subTest(msg='field: msk_top_regs.PRBS_Control.prbs_sel'): + fut = self.dut.PRBS_Control.prbs_sel # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0xFFFFFFFE + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=64, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0x1 + self.assertEqual(await fut.read(), + 0x1) + read_callback_mock.assert_called_once_with( + addr=64, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0x1) >> 0 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=64, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0x1 + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0x1, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.PRBS_Control.prbs_sel.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_called_once_with( + addr=64, + width=32, + accesswidth=fut.parent_register.accesswidth) + + write_callback_mock.assert_called_once_with( + addr=64, + width=32, + accesswidth=self.dut.PRBS_Control.prbs_sel.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0xFFFFFFFE) | \ + (0x1 & (field_value << 0))) + + + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0x1 + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) + + # test access operations (read and/or write) to field: + # msk_top_regs.PRBS_Control.prbs_error_insert + with self.subTest(msg='field: msk_top_regs.PRBS_Control.prbs_error_insert'): + fut = self.dut.PRBS_Control.prbs_error_insert # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0x1 + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0x1, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.PRBS_Control.prbs_error_insert.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_called_once_with( + addr=64, + width=32, + accesswidth=fut.parent_register.accesswidth) + + write_callback_mock.assert_called_once_with( + addr=64, + width=32, + accesswidth=self.dut.PRBS_Control.prbs_error_insert.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0xFFFFFFFD) | \ + (0x2 & (field_value << 1))) + + + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0x1 + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) + + # test access operations (read and/or write) to field: + # msk_top_regs.PRBS_Control.prbs_clear + with self.subTest(msg='field: msk_top_regs.PRBS_Control.prbs_clear'): + fut = self.dut.PRBS_Control.prbs_clear # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0x1 + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0x1, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.PRBS_Control.prbs_clear.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_called_once_with( + addr=64, + width=32, + accesswidth=fut.parent_register.accesswidth) + + write_callback_mock.assert_called_once_with( + addr=64, + width=32, + accesswidth=self.dut.PRBS_Control.prbs_clear.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0xFFFFFFFB) | \ + (0x4 & (field_value << 2))) + + + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0x1 + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) + + # test access operations (read and/or write) to field: + # msk_top_regs.PRBS_Control.prbs_manual_sync + with self.subTest(msg='field: msk_top_regs.PRBS_Control.prbs_manual_sync'): + fut = self.dut.PRBS_Control.prbs_manual_sync # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0x1 + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0x1, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.PRBS_Control.prbs_manual_sync.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_called_once_with( + addr=64, + width=32, + accesswidth=fut.parent_register.accesswidth) + + write_callback_mock.assert_called_once_with( + addr=64, + width=32, + accesswidth=self.dut.PRBS_Control.prbs_manual_sync.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0xFFFFFFF7) | \ + (0x8 & (field_value << 3))) + + + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0x1 + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) + + # test access operations (read and/or write) to field: + # msk_top_regs.PRBS_Control.prbs_reserved + with self.subTest(msg='field: msk_top_regs.PRBS_Control.prbs_reserved'): + fut = self.dut.PRBS_Control.prbs_reserved # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0xFFFF000F + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=64, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFF0 + self.assertEqual(await fut.read(), + 0xFFF) + read_callback_mock.assert_called_once_with( + addr=64, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0xFFF0) >> 4 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=64, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0xFFF + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0xFFF, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.PRBS_Control.prbs_reserved.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_called_once_with( + addr=64, + width=32, + accesswidth=fut.parent_register.accesswidth) + + write_callback_mock.assert_called_once_with( + addr=64, + width=32, + accesswidth=self.dut.PRBS_Control.prbs_reserved.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0xFFFF000F) | \ + (0xFFF0 & (field_value << 4))) + + + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0xFFF + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) + + # test access operations (read and/or write) to field: + # msk_top_regs.PRBS_Control.prbs_sync_threshold + with self.subTest(msg='field: msk_top_regs.PRBS_Control.prbs_sync_threshold'): + fut = self.dut.PRBS_Control.prbs_sync_threshold # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0xFFFF + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=64, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFF0000 + self.assertEqual(await fut.read(), + 0xFFFF) + read_callback_mock.assert_called_once_with( + addr=64, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0xFFFF0000) >> 16 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=64, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0xFFFF + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0xFFFF, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.PRBS_Control.prbs_sync_threshold.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_called_once_with( + addr=64, + width=32, + accesswidth=fut.parent_register.accesswidth) + + write_callback_mock.assert_called_once_with( + addr=64, + width=32, + accesswidth=self.dut.PRBS_Control.prbs_sync_threshold.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0xFFFF) | \ + (0xFFFF0000 & (field_value << 16))) + + + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0xFFFF + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) + + # test access operations (read and/or write) to field: + # msk_top_regs.PRBS_Initial_State.config_data + with self.subTest(msg='field: msk_top_regs.PRBS_Initial_State.config_data'): + fut = self.dut.PRBS_Initial_State.config_data # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0x0 + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=68, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await fut.read(), + 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=68, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=68, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0xFFFFFFFF + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0xFFFFFFFF, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.PRBS_Initial_State.config_data.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_not_called() + write_callback_mock.assert_called_once_with( + addr=68, + width=32, + accesswidth=self.dut.PRBS_Initial_State.config_data.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0x0) | \ + (0xFFFFFFFF & (field_value << 0))) + + + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0xFFFFFFFF + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) + + # test access operations (read and/or write) to field: + # msk_top_regs.PRBS_Polynomial.config_data + with self.subTest(msg='field: msk_top_regs.PRBS_Polynomial.config_data'): + fut = self.dut.PRBS_Polynomial.config_data # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0x0 + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=72, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await fut.read(), + 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=72, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=72, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0xFFFFFFFF + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0xFFFFFFFF, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.PRBS_Polynomial.config_data.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_not_called() + write_callback_mock.assert_called_once_with( + addr=72, + width=32, + accesswidth=self.dut.PRBS_Polynomial.config_data.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0x0) | \ + (0xFFFFFFFF & (field_value << 0))) + + + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0xFFFFFFFF + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) + + # test access operations (read and/or write) to field: + # msk_top_regs.PRBS_Error_Mask.config_data + with self.subTest(msg='field: msk_top_regs.PRBS_Error_Mask.config_data'): + fut = self.dut.PRBS_Error_Mask.config_data # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0x0 + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=76, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await fut.read(), + 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=76, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=76, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0xFFFFFFFF + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0xFFFFFFFF, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.PRBS_Error_Mask.config_data.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_not_called() + write_callback_mock.assert_called_once_with( + addr=76, + width=32, + accesswidth=self.dut.PRBS_Error_Mask.config_data.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0x0) | \ + (0xFFFFFFFF & (field_value << 0))) + + + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0xFFFFFFFF + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) + + # test access operations (read and/or write) to field: + # msk_top_regs.PRBS_Bit_Count.status_data + with self.subTest(msg='field: msk_top_regs.PRBS_Bit_Count.status_data'): + fut = self.dut.PRBS_Bit_Count.status_data # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0x0 + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=80, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await fut.read(), + 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=80, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=80, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + # test access operations (read and/or write) to field: + # msk_top_regs.PRBS_Error_Count.status_data + with self.subTest(msg='field: msk_top_regs.PRBS_Error_Count.status_data'): + fut = self.dut.PRBS_Error_Count.status_data # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0x0 + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=84, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await fut.read(), + 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=84, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=84, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + # test access operations (read and/or write) to field: + # msk_top_regs.LPF_Accum_F1.status_data + with self.subTest(msg='field: msk_top_regs.LPF_Accum_F1.status_data'): + fut = self.dut.LPF_Accum_F1.status_data # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0x0 + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=88, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await fut.read(), + 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=88, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=88, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + # test access operations (read and/or write) to field: + # msk_top_regs.LPF_Accum_F2.status_data + with self.subTest(msg='field: msk_top_regs.LPF_Accum_F2.status_data'): + fut = self.dut.LPF_Accum_F2.status_data # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0x0 + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=92, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await fut.read(), + 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=92, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=92, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + # test access operations (read and/or write) to field: + # msk_top_regs.axis_xfer_count.xfer_count + with self.subTest(msg='field: msk_top_regs.axis_xfer_count.xfer_count'): + fut = self.dut.axis_xfer_count.xfer_count # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0x0 + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=96, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await fut.read(), + 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=96, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=96, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + # test access operations (read and/or write) to field: + # msk_top_regs.Rx_Sample_Discard.rx_sample_discard + with self.subTest(msg='field: msk_top_regs.Rx_Sample_Discard.rx_sample_discard'): + fut = self.dut.Rx_Sample_Discard.rx_sample_discard # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0xFFFFFF00 + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=100, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFF + self.assertEqual(await fut.read(), + 0xFF) + read_callback_mock.assert_called_once_with( + addr=100, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0xFF) >> 0 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=100, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0xFF + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0xFF, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.Rx_Sample_Discard.rx_sample_discard.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_called_once_with( + addr=100, + width=32, + accesswidth=fut.parent_register.accesswidth) + + write_callback_mock.assert_called_once_with( + addr=100, + width=32, + accesswidth=self.dut.Rx_Sample_Discard.rx_sample_discard.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0xFFFFFF00) | \ + (0xFF & (field_value << 0))) + + + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0xFF + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) + + # test access operations (read and/or write) to field: + # msk_top_regs.Rx_Sample_Discard.rx_nco_discard + with self.subTest(msg='field: msk_top_regs.Rx_Sample_Discard.rx_nco_discard'): + fut = self.dut.Rx_Sample_Discard.rx_nco_discard # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0xFFFF00FF + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=100, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFF00 + self.assertEqual(await fut.read(), + 0xFF) + read_callback_mock.assert_called_once_with( + addr=100, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0xFF00) >> 8 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=100, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0xFF + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0xFF, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.Rx_Sample_Discard.rx_nco_discard.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_called_once_with( + addr=100, + width=32, + accesswidth=fut.parent_register.accesswidth) + + write_callback_mock.assert_called_once_with( + addr=100, + width=32, + accesswidth=self.dut.Rx_Sample_Discard.rx_nco_discard.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0xFFFF00FF) | \ + (0xFF00 & (field_value << 8))) + + + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0xFF + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) + + # test access operations (read and/or write) to field: + # msk_top_regs.LPF_Config_2.p_gain + with self.subTest(msg='field: msk_top_regs.LPF_Config_2.p_gain'): + fut = self.dut.LPF_Config_2.p_gain # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0xFF000000 + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=104, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFF + self.assertEqual(await fut.read(), + 0xFFFFFF) + read_callback_mock.assert_called_once_with( + addr=104, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0xFFFFFF) >> 0 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=104, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0xFFFFFF + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0xFFFFFF, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.LPF_Config_2.p_gain.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_called_once_with( + addr=104, + width=32, + accesswidth=fut.parent_register.accesswidth) + + write_callback_mock.assert_called_once_with( + addr=104, + width=32, + accesswidth=self.dut.LPF_Config_2.p_gain.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0xFF000000) | \ + (0xFFFFFF & (field_value << 0))) + + + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0xFFFFFF + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) + + # test access operations (read and/or write) to field: + # msk_top_regs.LPF_Config_2.p_shift + with self.subTest(msg='field: msk_top_regs.LPF_Config_2.p_shift'): + fut = self.dut.LPF_Config_2.p_shift # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0xFFFFFF + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=104, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFF000000 + self.assertEqual(await fut.read(), + 0xFF) + read_callback_mock.assert_called_once_with( + addr=104, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0xFF000000) >> 24 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=104, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0xFF + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0xFF, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.LPF_Config_2.p_shift.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_called_once_with( + addr=104, + width=32, + accesswidth=fut.parent_register.accesswidth) + + write_callback_mock.assert_called_once_with( + addr=104, + width=32, + accesswidth=self.dut.LPF_Config_2.p_shift.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0xFFFFFF) | \ + (0xFF000000 & (field_value << 24))) + + + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0xFF + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) + + # test access operations (read and/or write) to field: + # msk_top_regs.f1_nco_adjust.data + with self.subTest(msg='field: msk_top_regs.f1_nco_adjust.data'): + fut = self.dut.f1_nco_adjust.data # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0x0 + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=108, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await fut.read(), + 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=108, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=108, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + # test access operations (read and/or write) to field: + # msk_top_regs.f2_nco_adjust.data + with self.subTest(msg='field: msk_top_regs.f2_nco_adjust.data'): + fut = self.dut.f2_nco_adjust.data # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0x0 + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=112, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await fut.read(), + 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=112, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=112, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + # test access operations (read and/or write) to field: + # msk_top_regs.f1_error.data + with self.subTest(msg='field: msk_top_regs.f1_error.data'): + fut = self.dut.f1_error.data # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0x0 + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=116, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await fut.read(), + 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=116, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=116, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + # test access operations (read and/or write) to field: + # msk_top_regs.f2_error.data + with self.subTest(msg='field: msk_top_regs.f2_error.data'): + fut = self.dut.f2_error.data # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0x0 + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=120, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await fut.read(), + 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=120, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=120, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + # test access operations (read and/or write) to field: + # msk_top_regs.Tx_Sync_Ctrl.tx_sync_ena + with self.subTest(msg='field: msk_top_regs.Tx_Sync_Ctrl.tx_sync_ena'): + fut = self.dut.Tx_Sync_Ctrl.tx_sync_ena # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0xFFFFFFFE + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=124, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0x1 + self.assertEqual(await fut.read(), + 0x1) + read_callback_mock.assert_called_once_with( + addr=124, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0x1) >> 0 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=124, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0x1 + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0x1, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.Tx_Sync_Ctrl.tx_sync_ena.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_called_once_with( + addr=124, + width=32, + accesswidth=fut.parent_register.accesswidth) + + write_callback_mock.assert_called_once_with( + addr=124, + width=32, + accesswidth=self.dut.Tx_Sync_Ctrl.tx_sync_ena.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0xFFFFFFFE) | \ + (0x1 & (field_value << 0))) + + + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0x1 + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) + + # test access operations (read and/or write) to field: + # msk_top_regs.Tx_Sync_Ctrl.tx_sync_force + with self.subTest(msg='field: msk_top_regs.Tx_Sync_Ctrl.tx_sync_force'): + fut = self.dut.Tx_Sync_Ctrl.tx_sync_force # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0xFFFFFFFD + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=124, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0x2 + self.assertEqual(await fut.read(), + 0x1) + read_callback_mock.assert_called_once_with( + addr=124, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0x2) >> 1 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=124, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0x1 + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0x1, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.Tx_Sync_Ctrl.tx_sync_force.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_called_once_with( + addr=124, + width=32, + accesswidth=fut.parent_register.accesswidth) + + write_callback_mock.assert_called_once_with( + addr=124, + width=32, + accesswidth=self.dut.Tx_Sync_Ctrl.tx_sync_force.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0xFFFFFFFD) | \ + (0x2 & (field_value << 1))) + + + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0x1 + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) + + # test access operations (read and/or write) to field: + # msk_top_regs.Tx_Sync_Ctrl.tx_sync_f1 + with self.subTest(msg='field: msk_top_regs.Tx_Sync_Ctrl.tx_sync_f1'): + fut = self.dut.Tx_Sync_Ctrl.tx_sync_f1 # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0xFFFFFFFB + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=124, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0x4 + self.assertEqual(await fut.read(), + 0x1) + read_callback_mock.assert_called_once_with( + addr=124, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0x4) >> 2 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=124, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0x1 + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0x1, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.Tx_Sync_Ctrl.tx_sync_f1.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_called_once_with( + addr=124, + width=32, + accesswidth=fut.parent_register.accesswidth) + + write_callback_mock.assert_called_once_with( + addr=124, + width=32, + accesswidth=self.dut.Tx_Sync_Ctrl.tx_sync_f1.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0xFFFFFFFB) | \ + (0x4 & (field_value << 2))) + + + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0x1 + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) + + # test access operations (read and/or write) to field: + # msk_top_regs.Tx_Sync_Ctrl.tx_sync_f2 + with self.subTest(msg='field: msk_top_regs.Tx_Sync_Ctrl.tx_sync_f2'): + fut = self.dut.Tx_Sync_Ctrl.tx_sync_f2 # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0xFFFFFFF7 + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=124, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0x8 + self.assertEqual(await fut.read(), + 0x1) + read_callback_mock.assert_called_once_with( + addr=124, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0x8) >> 3 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=124, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0x1 + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0x1, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.Tx_Sync_Ctrl.tx_sync_f2.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_called_once_with( + addr=124, + width=32, + accesswidth=fut.parent_register.accesswidth) + + write_callback_mock.assert_called_once_with( + addr=124, + width=32, + accesswidth=self.dut.Tx_Sync_Ctrl.tx_sync_f2.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0xFFFFFFF7) | \ + (0x8 & (field_value << 3))) + + + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0x1 + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) + + # test access operations (read and/or write) to field: + # msk_top_regs.Tx_Sync_Cnt.tx_sync_cnt + with self.subTest(msg='field: msk_top_regs.Tx_Sync_Cnt.tx_sync_cnt'): + fut = self.dut.Tx_Sync_Cnt.tx_sync_cnt # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0xFF000000 + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=128, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFF + self.assertEqual(await fut.read(), + 0xFFFFFF) + read_callback_mock.assert_called_once_with( + addr=128, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0xFFFFFF) >> 0 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=128, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0xFFFFFF + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0xFFFFFF, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.Tx_Sync_Cnt.tx_sync_cnt.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_called_once_with( + addr=128, + width=32, + accesswidth=fut.parent_register.accesswidth) + + write_callback_mock.assert_called_once_with( + addr=128, + width=32, + accesswidth=self.dut.Tx_Sync_Cnt.tx_sync_cnt.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0xFF000000) | \ + (0xFFFFFF & (field_value << 0))) + + + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0xFFFFFF + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) + + # test access operations (read and/or write) to field: + # msk_top_regs.lowpass_ema_alpha1.alpha + with self.subTest(msg='field: msk_top_regs.lowpass_ema_alpha1.alpha'): + fut = self.dut.lowpass_ema_alpha1.alpha # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0xFFFC0000 + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=132, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0x3FFFF + self.assertEqual(await fut.read(), + 0x3FFFF) + read_callback_mock.assert_called_once_with( + addr=132, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0x3FFFF) >> 0 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=132, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0x3FFFF + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0x3FFFF, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.lowpass_ema_alpha1.alpha.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_called_once_with( + addr=132, + width=32, + accesswidth=fut.parent_register.accesswidth) + + write_callback_mock.assert_called_once_with( + addr=132, + width=32, + accesswidth=self.dut.lowpass_ema_alpha1.alpha.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0xFFFC0000) | \ + (0x3FFFF & (field_value << 0))) + + + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0x3FFFF + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) + + # test access operations (read and/or write) to field: + # msk_top_regs.lowpass_ema_alpha2.alpha + with self.subTest(msg='field: msk_top_regs.lowpass_ema_alpha2.alpha'): + fut = self.dut.lowpass_ema_alpha2.alpha # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0xFFFC0000 + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=136, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0x3FFFF + self.assertEqual(await fut.read(), + 0x3FFFF) + read_callback_mock.assert_called_once_with( + addr=136, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0x3FFFF) >> 0 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=136, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0x3FFFF + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0x3FFFF, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.lowpass_ema_alpha2.alpha.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_called_once_with( + addr=136, + width=32, + accesswidth=fut.parent_register.accesswidth) + + write_callback_mock.assert_called_once_with( + addr=136, + width=32, + accesswidth=self.dut.lowpass_ema_alpha2.alpha.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0xFFFC0000) | \ + (0x3FFFF & (field_value << 0))) + + + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0x3FFFF + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) + + # test access operations (read and/or write) to field: + # msk_top_regs.rx_power.rx_power + with self.subTest(msg='field: msk_top_regs.rx_power.rx_power'): + fut = self.dut.rx_power.rx_power # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0xFF800000 + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=140, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0x7FFFFF + self.assertEqual(await fut.read(), + 0x7FFFFF) + read_callback_mock.assert_called_once_with( + addr=140, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0x7FFFFF) >> 0 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=140, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + + + async def test_register_read_fields(self) -> None: + """ + Walk the register map and check every register read_fields method + """ + reference_read_fields: dict[str, Union[bool, SystemRDLEnum, int]] + + with self.subTest(msg='register: msk_top_regs.Hash_ID_Low'): + # test read_fields to register: + # msk_top_regs.Hash_ID_Low + # build up the register value with a random base value, overlaid with + # a random value for each field + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFFFFFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0x0) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + # the read_fields method gets a dictionary back + # from the object with all the read back field + # values + reference_read_fields = { + 'hash_id_lo' : await self.dut.Hash_ID_Low.hash_id_lo.read() + } + + read_callback_mock.reset_mock() + + self.assertDictEqual(await self.dut.Hash_ID_Low.read_fields(), + reference_read_fields) + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + with self.subTest(msg='register: msk_top_regs.Hash_ID_High'): + # test read_fields to register: + # msk_top_regs.Hash_ID_High + # build up the register value with a random base value, overlaid with + # a random value for each field + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFFFFFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0x0) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + # the read_fields method gets a dictionary back + # from the object with all the read back field + # values + reference_read_fields = { + 'hash_id_hi' : await self.dut.Hash_ID_High.hash_id_hi.read() + } + + read_callback_mock.reset_mock() + + self.assertDictEqual(await self.dut.Hash_ID_High.read_fields(), + reference_read_fields) + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + with self.subTest(msg='register: msk_top_regs.MSK_Init'): + # test read_fields to register: + # msk_top_regs.MSK_Init + # build up the register value with a random base value, overlaid with + # a random value for each field + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0x1 + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFFFFFE) | (rand_field_value << 0) + + + + + + + + rand_field_value = random.randrange(0, 0x1 + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFFFFFD) | (rand_field_value << 1) + + + + + + + + rand_field_value = random.randrange(0, 0x1 + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFFFFFB) | (rand_field_value << 2) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + # the read_fields method gets a dictionary back + # from the object with all the read back field + # values + reference_read_fields = { + 'txrxinit' : await self.dut.MSK_Init.txrxinit.read(), + 'txinit' : await self.dut.MSK_Init.txinit.read(), + 'rxinit' : await self.dut.MSK_Init.rxinit.read() + } + + read_callback_mock.reset_mock() + + self.assertDictEqual(await self.dut.MSK_Init.read_fields(), + reference_read_fields) + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + with self.subTest(msg='register: msk_top_regs.MSK_Control'): + # test read_fields to register: + # msk_top_regs.MSK_Control + # build up the register value with a random base value, overlaid with + # a random value for each field + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0x1 + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFFFFFE) | (rand_field_value << 0) + + + + + + + + rand_field_value = random.randrange(0, 0x1 + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFFFFFD) | (rand_field_value << 1) + + + + + + + + rand_field_value = random.randrange(0, 0x1 + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFFFFFB) | (rand_field_value << 2) + + + + + + + + rand_field_value = random.randrange(0, 0x1 + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFFFFF7) | (rand_field_value << 3) + + + + + + + + rand_field_value = random.randrange(0, 0x1 + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFFFFEF) | (rand_field_value << 4) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + # the read_fields method gets a dictionary back + # from the object with all the read back field + # values + reference_read_fields = { + 'ptt' : await self.dut.MSK_Control.ptt.read(), + 'loopback_ena' : await self.dut.MSK_Control.loopback_ena.read(), + 'rx_invert' : await self.dut.MSK_Control.rx_invert.read(), + 'clear_counts' : await self.dut.MSK_Control.clear_counts.read(), + 'diff_encoder_loopback' : await self.dut.MSK_Control.diff_encoder_loopback.read() + } + + read_callback_mock.reset_mock() + + self.assertDictEqual(await self.dut.MSK_Control.read_fields(), + reference_read_fields) + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + with self.subTest(msg='register: msk_top_regs.MSK_Status'): + # test read_fields to register: + # msk_top_regs.MSK_Status + # build up the register value with a random base value, overlaid with + # a random value for each field + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0x1 + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFFFFFE) | (rand_field_value << 0) + + + + + + + + rand_field_value = random.randrange(0, 0x1 + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFFFFFD) | (rand_field_value << 1) + + + + + + + + rand_field_value = random.randrange(0, 0x1 + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFFFFFB) | (rand_field_value << 2) + + + + + + + + rand_field_value = random.randrange(0, 0x1 + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFFFFF7) | (rand_field_value << 3) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + # the read_fields method gets a dictionary back + # from the object with all the read back field + # values + reference_read_fields = { + 'demod_sync_lock' : await self.dut.MSK_Status.demod_sync_lock.read(), + 'tx_enable' : await self.dut.MSK_Status.tx_enable.read(), + 'rx_enable' : await self.dut.MSK_Status.rx_enable.read(), + 'tx_axis_valid' : await self.dut.MSK_Status.tx_axis_valid.read() + } + + read_callback_mock.reset_mock() + + self.assertDictEqual(await self.dut.MSK_Status.read_fields(), + reference_read_fields) + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + with self.subTest(msg='register: msk_top_regs.Tx_Bit_Count'): + # test read_fields to register: + # msk_top_regs.Tx_Bit_Count + # build up the register value with a random base value, overlaid with + # a random value for each field + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFFFFFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0x0) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + # the read_fields method gets a dictionary back + # from the object with all the read back field + # values + reference_read_fields = { + 'tx_bit_counter' : await self.dut.Tx_Bit_Count.tx_bit_counter.read() + } + + read_callback_mock.reset_mock() + + self.assertDictEqual(await self.dut.Tx_Bit_Count.read_fields(), + reference_read_fields) + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + with self.subTest(msg='register: msk_top_regs.Tx_Enable_Count'): + # test read_fields to register: + # msk_top_regs.Tx_Enable_Count + # build up the register value with a random base value, overlaid with + # a random value for each field + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFFFFFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0x0) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + # the read_fields method gets a dictionary back + # from the object with all the read back field + # values + reference_read_fields = { + 'tx_ena_counter' : await self.dut.Tx_Enable_Count.tx_ena_counter.read() + } + + read_callback_mock.reset_mock() + + self.assertDictEqual(await self.dut.Tx_Enable_Count.read_fields(), + reference_read_fields) + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + with self.subTest(msg='register: msk_top_regs.Fb_FreqWord'): + # test read_fields to register: + # msk_top_regs.Fb_FreqWord + # build up the register value with a random base value, overlaid with + # a random value for each field + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFFFFFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0x0) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + # the read_fields method gets a dictionary back + # from the object with all the read back field + # values + reference_read_fields = { + 'config_data' : await self.dut.Fb_FreqWord.config_data.read() + } + + read_callback_mock.reset_mock() + + self.assertDictEqual(await self.dut.Fb_FreqWord.read_fields(), + reference_read_fields) + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + with self.subTest(msg='register: msk_top_regs.TX_F1_FreqWord'): + # test read_fields to register: + # msk_top_regs.TX_F1_FreqWord + # build up the register value with a random base value, overlaid with + # a random value for each field + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFFFFFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0x0) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + # the read_fields method gets a dictionary back + # from the object with all the read back field + # values + reference_read_fields = { + 'config_data' : await self.dut.TX_F1_FreqWord.config_data.read() + } + + read_callback_mock.reset_mock() + + self.assertDictEqual(await self.dut.TX_F1_FreqWord.read_fields(), + reference_read_fields) + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + with self.subTest(msg='register: msk_top_regs.TX_F2_FreqWord'): + # test read_fields to register: + # msk_top_regs.TX_F2_FreqWord + # build up the register value with a random base value, overlaid with + # a random value for each field + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFFFFFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0x0) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + # the read_fields method gets a dictionary back + # from the object with all the read back field + # values + reference_read_fields = { + 'config_data' : await self.dut.TX_F2_FreqWord.config_data.read() + } + + read_callback_mock.reset_mock() + + self.assertDictEqual(await self.dut.TX_F2_FreqWord.read_fields(), + reference_read_fields) + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + with self.subTest(msg='register: msk_top_regs.RX_F1_FreqWord'): + # test read_fields to register: + # msk_top_regs.RX_F1_FreqWord + # build up the register value with a random base value, overlaid with + # a random value for each field + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFFFFFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0x0) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + # the read_fields method gets a dictionary back + # from the object with all the read back field + # values + reference_read_fields = { + 'config_data' : await self.dut.RX_F1_FreqWord.config_data.read() + } + + read_callback_mock.reset_mock() + + self.assertDictEqual(await self.dut.RX_F1_FreqWord.read_fields(), + reference_read_fields) + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + with self.subTest(msg='register: msk_top_regs.RX_F2_FreqWord'): + # test read_fields to register: + # msk_top_regs.RX_F2_FreqWord + # build up the register value with a random base value, overlaid with + # a random value for each field + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFFFFFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0x0) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + # the read_fields method gets a dictionary back + # from the object with all the read back field + # values + reference_read_fields = { + 'config_data' : await self.dut.RX_F2_FreqWord.config_data.read() + } + + read_callback_mock.reset_mock() + + self.assertDictEqual(await self.dut.RX_F2_FreqWord.read_fields(), + reference_read_fields) + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + with self.subTest(msg='register: msk_top_regs.LPF_Config_0'): + # test read_fields to register: + # msk_top_regs.LPF_Config_0 + # build up the register value with a random base value, overlaid with + # a random value for each field + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0x1 + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFFFFFE) | (rand_field_value << 0) + + + + + + + + rand_field_value = random.randrange(0, 0x1 + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFFFFFD) | (rand_field_value << 1) + + + + + + + + rand_field_value = random.randrange(0, 0x3F + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFFFF03) | (rand_field_value << 2) + + + + + + + + rand_field_value = random.randrange(0, 0xFFFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0xFF) | (rand_field_value << 8) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + # the read_fields method gets a dictionary back + # from the object with all the read back field + # values + reference_read_fields = { + 'lpf_freeze' : await self.dut.LPF_Config_0.lpf_freeze.read(), + 'lpf_zero' : await self.dut.LPF_Config_0.lpf_zero.read(), + 'prbs_reserved' : await self.dut.LPF_Config_0.prbs_reserved.read(), + 'lpf_alpha' : await self.dut.LPF_Config_0.lpf_alpha.read() + } + + read_callback_mock.reset_mock() + + self.assertDictEqual(await self.dut.LPF_Config_0.read_fields(), + reference_read_fields) + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + with self.subTest(msg='register: msk_top_regs.LPF_Config_1'): + # test read_fields to register: + # msk_top_regs.LPF_Config_1 + # build up the register value with a random base value, overlaid with + # a random value for each field + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFFFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0xFF000000) | (rand_field_value << 0) + + + + + + + + rand_field_value = random.randrange(0, 0xFF + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFFFF) | (rand_field_value << 24) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + # the read_fields method gets a dictionary back + # from the object with all the read back field + # values + reference_read_fields = { + 'i_gain' : await self.dut.LPF_Config_1.i_gain.read(), + 'i_shift' : await self.dut.LPF_Config_1.i_shift.read() + } + + read_callback_mock.reset_mock() + + self.assertDictEqual(await self.dut.LPF_Config_1.read_fields(), + reference_read_fields) + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + with self.subTest(msg='register: msk_top_regs.Tx_Data_Width'): + # test read_fields to register: + # msk_top_regs.Tx_Data_Width + # build up the register value with a random base value, overlaid with + # a random value for each field + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFF + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFFFF00) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + # the read_fields method gets a dictionary back + # from the object with all the read back field + # values + reference_read_fields = { + 'data_width' : await self.dut.Tx_Data_Width.data_width.read() + } + + read_callback_mock.reset_mock() + + self.assertDictEqual(await self.dut.Tx_Data_Width.read_fields(), + reference_read_fields) + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + with self.subTest(msg='register: msk_top_regs.Rx_Data_Width'): + # test read_fields to register: + # msk_top_regs.Rx_Data_Width + # build up the register value with a random base value, overlaid with + # a random value for each field + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFF + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFFFF00) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + # the read_fields method gets a dictionary back + # from the object with all the read back field + # values + reference_read_fields = { + 'data_width' : await self.dut.Rx_Data_Width.data_width.read() + } + + read_callback_mock.reset_mock() + + self.assertDictEqual(await self.dut.Rx_Data_Width.read_fields(), + reference_read_fields) + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + with self.subTest(msg='register: msk_top_regs.PRBS_Control'): + # test read_fields to register: + # msk_top_regs.PRBS_Control + # build up the register value with a random base value, overlaid with + # a random value for each field + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0x1 + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFFFFFE) | (rand_field_value << 0) + + + + + + + + + + + + + + + + + + + + rand_field_value = random.randrange(0, 0xFFF + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFF000F) | (rand_field_value << 4) + + + + + + + + rand_field_value = random.randrange(0, 0xFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFF) | (rand_field_value << 16) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + # the read_fields method gets a dictionary back + # from the object with all the read back field + # values + reference_read_fields = { + 'prbs_sel' : await self.dut.PRBS_Control.prbs_sel.read(), + 'prbs_reserved' : await self.dut.PRBS_Control.prbs_reserved.read(), + 'prbs_sync_threshold' : await self.dut.PRBS_Control.prbs_sync_threshold.read() + } + + read_callback_mock.reset_mock() + + self.assertDictEqual(await self.dut.PRBS_Control.read_fields(), + reference_read_fields) + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + with self.subTest(msg='register: msk_top_regs.PRBS_Initial_State'): + # test read_fields to register: + # msk_top_regs.PRBS_Initial_State + # build up the register value with a random base value, overlaid with + # a random value for each field + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFFFFFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0x0) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + # the read_fields method gets a dictionary back + # from the object with all the read back field + # values + reference_read_fields = { + 'config_data' : await self.dut.PRBS_Initial_State.config_data.read() + } + + read_callback_mock.reset_mock() + + self.assertDictEqual(await self.dut.PRBS_Initial_State.read_fields(), + reference_read_fields) + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + with self.subTest(msg='register: msk_top_regs.PRBS_Polynomial'): + # test read_fields to register: + # msk_top_regs.PRBS_Polynomial + # build up the register value with a random base value, overlaid with + # a random value for each field + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFFFFFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0x0) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + # the read_fields method gets a dictionary back + # from the object with all the read back field + # values + reference_read_fields = { + 'config_data' : await self.dut.PRBS_Polynomial.config_data.read() + } + + read_callback_mock.reset_mock() + + self.assertDictEqual(await self.dut.PRBS_Polynomial.read_fields(), + reference_read_fields) + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + with self.subTest(msg='register: msk_top_regs.PRBS_Error_Mask'): + # test read_fields to register: + # msk_top_regs.PRBS_Error_Mask + # build up the register value with a random base value, overlaid with + # a random value for each field + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFFFFFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0x0) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + # the read_fields method gets a dictionary back + # from the object with all the read back field + # values + reference_read_fields = { + 'config_data' : await self.dut.PRBS_Error_Mask.config_data.read() + } + + read_callback_mock.reset_mock() + + self.assertDictEqual(await self.dut.PRBS_Error_Mask.read_fields(), + reference_read_fields) + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + with self.subTest(msg='register: msk_top_regs.PRBS_Bit_Count'): + # test read_fields to register: + # msk_top_regs.PRBS_Bit_Count + # build up the register value with a random base value, overlaid with + # a random value for each field + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFFFFFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0x0) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + # the read_fields method gets a dictionary back + # from the object with all the read back field + # values + reference_read_fields = { + 'status_data' : await self.dut.PRBS_Bit_Count.status_data.read() + } + + read_callback_mock.reset_mock() + + self.assertDictEqual(await self.dut.PRBS_Bit_Count.read_fields(), + reference_read_fields) + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + with self.subTest(msg='register: msk_top_regs.PRBS_Error_Count'): + # test read_fields to register: + # msk_top_regs.PRBS_Error_Count + # build up the register value with a random base value, overlaid with + # a random value for each field + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFFFFFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0x0) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + # the read_fields method gets a dictionary back + # from the object with all the read back field + # values + reference_read_fields = { + 'status_data' : await self.dut.PRBS_Error_Count.status_data.read() + } + + read_callback_mock.reset_mock() + + self.assertDictEqual(await self.dut.PRBS_Error_Count.read_fields(), + reference_read_fields) + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + with self.subTest(msg='register: msk_top_regs.LPF_Accum_F1'): + # test read_fields to register: + # msk_top_regs.LPF_Accum_F1 + # build up the register value with a random base value, overlaid with + # a random value for each field + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFFFFFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0x0) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + # the read_fields method gets a dictionary back + # from the object with all the read back field + # values + reference_read_fields = { + 'status_data' : await self.dut.LPF_Accum_F1.status_data.read() + } + + read_callback_mock.reset_mock() + + self.assertDictEqual(await self.dut.LPF_Accum_F1.read_fields(), + reference_read_fields) + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + with self.subTest(msg='register: msk_top_regs.LPF_Accum_F2'): + # test read_fields to register: + # msk_top_regs.LPF_Accum_F2 + # build up the register value with a random base value, overlaid with + # a random value for each field + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFFFFFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0x0) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + # the read_fields method gets a dictionary back + # from the object with all the read back field + # values + reference_read_fields = { + 'status_data' : await self.dut.LPF_Accum_F2.status_data.read() + } + + read_callback_mock.reset_mock() + + self.assertDictEqual(await self.dut.LPF_Accum_F2.read_fields(), + reference_read_fields) + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + with self.subTest(msg='register: msk_top_regs.axis_xfer_count'): + # test read_fields to register: + # msk_top_regs.axis_xfer_count + # build up the register value with a random base value, overlaid with + # a random value for each field + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFFFFFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0x0) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + # the read_fields method gets a dictionary back + # from the object with all the read back field + # values + reference_read_fields = { + 'xfer_count' : await self.dut.axis_xfer_count.xfer_count.read() + } + + read_callback_mock.reset_mock() + + self.assertDictEqual(await self.dut.axis_xfer_count.read_fields(), + reference_read_fields) + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + with self.subTest(msg='register: msk_top_regs.Rx_Sample_Discard'): + # test read_fields to register: + # msk_top_regs.Rx_Sample_Discard + # build up the register value with a random base value, overlaid with + # a random value for each field + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFF + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFFFF00) | (rand_field_value << 0) + + + + + + + + rand_field_value = random.randrange(0, 0xFF + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFF00FF) | (rand_field_value << 8) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + # the read_fields method gets a dictionary back + # from the object with all the read back field + # values + reference_read_fields = { + 'rx_sample_discard' : await self.dut.Rx_Sample_Discard.rx_sample_discard.read(), + 'rx_nco_discard' : await self.dut.Rx_Sample_Discard.rx_nco_discard.read() + } + + read_callback_mock.reset_mock() + + self.assertDictEqual(await self.dut.Rx_Sample_Discard.read_fields(), + reference_read_fields) + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + with self.subTest(msg='register: msk_top_regs.LPF_Config_2'): + # test read_fields to register: + # msk_top_regs.LPF_Config_2 + # build up the register value with a random base value, overlaid with + # a random value for each field + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFFFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0xFF000000) | (rand_field_value << 0) + + + + + + + + rand_field_value = random.randrange(0, 0xFF + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFFFF) | (rand_field_value << 24) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + # the read_fields method gets a dictionary back + # from the object with all the read back field + # values + reference_read_fields = { + 'p_gain' : await self.dut.LPF_Config_2.p_gain.read(), + 'p_shift' : await self.dut.LPF_Config_2.p_shift.read() + } + + read_callback_mock.reset_mock() + + self.assertDictEqual(await self.dut.LPF_Config_2.read_fields(), + reference_read_fields) + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + with self.subTest(msg='register: msk_top_regs.f1_nco_adjust'): + # test read_fields to register: + # msk_top_regs.f1_nco_adjust + # build up the register value with a random base value, overlaid with + # a random value for each field + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFFFFFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0x0) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + # the read_fields method gets a dictionary back + # from the object with all the read back field + # values + reference_read_fields = { + 'data' : await self.dut.f1_nco_adjust.data.read() + } + + read_callback_mock.reset_mock() + + self.assertDictEqual(await self.dut.f1_nco_adjust.read_fields(), + reference_read_fields) + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + with self.subTest(msg='register: msk_top_regs.f2_nco_adjust'): + # test read_fields to register: + # msk_top_regs.f2_nco_adjust + # build up the register value with a random base value, overlaid with + # a random value for each field + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFFFFFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0x0) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + # the read_fields method gets a dictionary back + # from the object with all the read back field + # values + reference_read_fields = { + 'data' : await self.dut.f2_nco_adjust.data.read() + } + + read_callback_mock.reset_mock() + + self.assertDictEqual(await self.dut.f2_nco_adjust.read_fields(), + reference_read_fields) + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + with self.subTest(msg='register: msk_top_regs.f1_error'): + # test read_fields to register: + # msk_top_regs.f1_error + # build up the register value with a random base value, overlaid with + # a random value for each field + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFFFFFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0x0) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + # the read_fields method gets a dictionary back + # from the object with all the read back field + # values + reference_read_fields = { + 'data' : await self.dut.f1_error.data.read() + } + + read_callback_mock.reset_mock() + + self.assertDictEqual(await self.dut.f1_error.read_fields(), + reference_read_fields) + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + with self.subTest(msg='register: msk_top_regs.f2_error'): + # test read_fields to register: + # msk_top_regs.f2_error + # build up the register value with a random base value, overlaid with + # a random value for each field + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFFFFFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0x0) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + # the read_fields method gets a dictionary back + # from the object with all the read back field + # values + reference_read_fields = { + 'data' : await self.dut.f2_error.data.read() + } + + read_callback_mock.reset_mock() + + self.assertDictEqual(await self.dut.f2_error.read_fields(), + reference_read_fields) + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + with self.subTest(msg='register: msk_top_regs.Tx_Sync_Ctrl'): + # test read_fields to register: + # msk_top_regs.Tx_Sync_Ctrl + # build up the register value with a random base value, overlaid with + # a random value for each field + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0x1 + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFFFFFE) | (rand_field_value << 0) + + + + + + + + rand_field_value = random.randrange(0, 0x1 + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFFFFFD) | (rand_field_value << 1) + + + + + + + + rand_field_value = random.randrange(0, 0x1 + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFFFFFB) | (rand_field_value << 2) + + + + + + + + rand_field_value = random.randrange(0, 0x1 + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFFFFF7) | (rand_field_value << 3) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + # the read_fields method gets a dictionary back + # from the object with all the read back field + # values + reference_read_fields = { + 'tx_sync_ena' : await self.dut.Tx_Sync_Ctrl.tx_sync_ena.read(), + 'tx_sync_force' : await self.dut.Tx_Sync_Ctrl.tx_sync_force.read(), + 'tx_sync_f1' : await self.dut.Tx_Sync_Ctrl.tx_sync_f1.read(), + 'tx_sync_f2' : await self.dut.Tx_Sync_Ctrl.tx_sync_f2.read() + } + + read_callback_mock.reset_mock() + + self.assertDictEqual(await self.dut.Tx_Sync_Ctrl.read_fields(), + reference_read_fields) + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + with self.subTest(msg='register: msk_top_regs.Tx_Sync_Cnt'): + # test read_fields to register: + # msk_top_regs.Tx_Sync_Cnt + # build up the register value with a random base value, overlaid with + # a random value for each field + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFFFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0xFF000000) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + # the read_fields method gets a dictionary back + # from the object with all the read back field + # values + reference_read_fields = { + 'tx_sync_cnt' : await self.dut.Tx_Sync_Cnt.tx_sync_cnt.read() + } + + read_callback_mock.reset_mock() + + self.assertDictEqual(await self.dut.Tx_Sync_Cnt.read_fields(), + reference_read_fields) + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + with self.subTest(msg='register: msk_top_regs.lowpass_ema_alpha1'): + # test read_fields to register: + # msk_top_regs.lowpass_ema_alpha1 + # build up the register value with a random base value, overlaid with + # a random value for each field + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0x3FFFF + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFC0000) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + # the read_fields method gets a dictionary back + # from the object with all the read back field + # values + reference_read_fields = { + 'alpha' : await self.dut.lowpass_ema_alpha1.alpha.read() + } + + read_callback_mock.reset_mock() + + self.assertDictEqual(await self.dut.lowpass_ema_alpha1.read_fields(), + reference_read_fields) + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + with self.subTest(msg='register: msk_top_regs.lowpass_ema_alpha2'): + # test read_fields to register: + # msk_top_regs.lowpass_ema_alpha2 + # build up the register value with a random base value, overlaid with + # a random value for each field + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0x3FFFF + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFC0000) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + # the read_fields method gets a dictionary back + # from the object with all the read back field + # values + reference_read_fields = { + 'alpha' : await self.dut.lowpass_ema_alpha2.alpha.read() + } + + read_callback_mock.reset_mock() + + self.assertDictEqual(await self.dut.lowpass_ema_alpha2.read_fields(), + reference_read_fields) + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + with self.subTest(msg='register: msk_top_regs.rx_power'): + # test read_fields to register: + # msk_top_regs.rx_power + # build up the register value with a random base value, overlaid with + # a random value for each field + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0x7FFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0xFF800000) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + # the read_fields method gets a dictionary back + # from the object with all the read back field + # values + reference_read_fields = { + 'rx_power' : await self.dut.rx_power.rx_power.read() + } + + read_callback_mock.reset_mock() + + self.assertDictEqual(await self.dut.rx_power.read_fields(), + reference_read_fields) + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + + async def test_register_read_context_manager(self) -> None: + """ + Walk the register map and check every register read_fields method + """ + reference_read_fields: dict[str, Union[bool, SystemRDLEnum, int]] + + # test context manager to register: + # msk_top_regs.Hash_ID_Low + # build up the register value with a random base value, overlaid with + # a random value for each field + with self.subTest(msg='register: msk_top_regs.Hash_ID_Low'): + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFFFFFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0x0) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + + # first read the fields using the "normal" method, then compare the result to reading + # via the context manager + reference_read_fields = { + 'hash_id_lo' : await self.dut.Hash_ID_Low.hash_id_lo.read() # type: ignore[union-attr] + } + read_callback_mock.reset_mock() + + + async with self.dut.Hash_ID_Low.single_read() as reg_context: # type: ignore[union-attr] + self.assertEqual(reference_read_fields['hash_id_lo'], + await reg_context.get_child_by_system_rdl_name('hash_id_lo').read() + ) + pass + + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + # test context manager to register: + # msk_top_regs.Hash_ID_High + # build up the register value with a random base value, overlaid with + # a random value for each field + with self.subTest(msg='register: msk_top_regs.Hash_ID_High'): + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFFFFFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0x0) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + + # first read the fields using the "normal" method, then compare the result to reading + # via the context manager + reference_read_fields = { + 'hash_id_hi' : await self.dut.Hash_ID_High.hash_id_hi.read() # type: ignore[union-attr] + } + read_callback_mock.reset_mock() + + + async with self.dut.Hash_ID_High.single_read() as reg_context: # type: ignore[union-attr] + self.assertEqual(reference_read_fields['hash_id_hi'], + await reg_context.get_child_by_system_rdl_name('hash_id_hi').read() + ) + pass + + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + # test context manager to register: + # msk_top_regs.MSK_Init + # build up the register value with a random base value, overlaid with + # a random value for each field + with self.subTest(msg='register: msk_top_regs.MSK_Init'): + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0x1 + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFFFFFE) | (rand_field_value << 0) + + + + + + + + rand_field_value = random.randrange(0, 0x1 + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFFFFFD) | (rand_field_value << 1) + + + + + + + + rand_field_value = random.randrange(0, 0x1 + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFFFFFB) | (rand_field_value << 2) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + + # first read the fields using the "normal" method, then compare the result to reading + # via the context manager + reference_read_fields = { + 'txrxinit' : await self.dut.MSK_Init.txrxinit.read(), # type: ignore[union-attr] + 'txinit' : await self.dut.MSK_Init.txinit.read(), # type: ignore[union-attr] + 'rxinit' : await self.dut.MSK_Init.rxinit.read() # type: ignore[union-attr] + } + read_callback_mock.reset_mock() + + + async with self.dut.MSK_Init.single_read_modify_write(skip_write=True) as reg_context: # type: ignore[union-attr] + + self.assertEqual(reference_read_fields['txrxinit'], + await reg_context.get_child_by_system_rdl_name('txrxinit').read() + ) + self.assertEqual(reference_read_fields['txinit'], + await reg_context.get_child_by_system_rdl_name('txinit').read() + ) + self.assertEqual(reference_read_fields['rxinit'], + await reg_context.get_child_by_system_rdl_name('rxinit').read() + ) + pass + + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + # test context manager to register: + # msk_top_regs.MSK_Control + # build up the register value with a random base value, overlaid with + # a random value for each field + with self.subTest(msg='register: msk_top_regs.MSK_Control'): + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0x1 + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFFFFFE) | (rand_field_value << 0) + + + + + + + + rand_field_value = random.randrange(0, 0x1 + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFFFFFD) | (rand_field_value << 1) + + + + + + + + rand_field_value = random.randrange(0, 0x1 + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFFFFFB) | (rand_field_value << 2) + + + + + + + + rand_field_value = random.randrange(0, 0x1 + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFFFFF7) | (rand_field_value << 3) + + + + + + + + rand_field_value = random.randrange(0, 0x1 + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFFFFEF) | (rand_field_value << 4) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + + # first read the fields using the "normal" method, then compare the result to reading + # via the context manager + reference_read_fields = { + 'ptt' : await self.dut.MSK_Control.ptt.read(), # type: ignore[union-attr] + 'loopback_ena' : await self.dut.MSK_Control.loopback_ena.read(), # type: ignore[union-attr] + 'rx_invert' : await self.dut.MSK_Control.rx_invert.read(), # type: ignore[union-attr] + 'clear_counts' : await self.dut.MSK_Control.clear_counts.read(), # type: ignore[union-attr] + 'diff_encoder_loopback' : await self.dut.MSK_Control.diff_encoder_loopback.read() # type: ignore[union-attr] + } + read_callback_mock.reset_mock() + + + async with self.dut.MSK_Control.single_read_modify_write(skip_write=True) as reg_context: # type: ignore[union-attr] + + self.assertEqual(reference_read_fields['ptt'], + await reg_context.get_child_by_system_rdl_name('ptt').read() + ) + self.assertEqual(reference_read_fields['loopback_ena'], + await reg_context.get_child_by_system_rdl_name('loopback_ena').read() + ) + self.assertEqual(reference_read_fields['rx_invert'], + await reg_context.get_child_by_system_rdl_name('rx_invert').read() + ) + self.assertEqual(reference_read_fields['clear_counts'], + await reg_context.get_child_by_system_rdl_name('clear_counts').read() + ) + self.assertEqual(reference_read_fields['diff_encoder_loopback'], + await reg_context.get_child_by_system_rdl_name('diff_encoder_loopback').read() + ) + pass + + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + # test context manager to register: + # msk_top_regs.MSK_Status + # build up the register value with a random base value, overlaid with + # a random value for each field + with self.subTest(msg='register: msk_top_regs.MSK_Status'): + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0x1 + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFFFFFE) | (rand_field_value << 0) + + + + + + + + rand_field_value = random.randrange(0, 0x1 + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFFFFFD) | (rand_field_value << 1) + + + + + + + + rand_field_value = random.randrange(0, 0x1 + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFFFFFB) | (rand_field_value << 2) + + + + + + + + rand_field_value = random.randrange(0, 0x1 + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFFFFF7) | (rand_field_value << 3) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + + # first read the fields using the "normal" method, then compare the result to reading + # via the context manager + reference_read_fields = { + 'demod_sync_lock' : await self.dut.MSK_Status.demod_sync_lock.read(), # type: ignore[union-attr] + 'tx_enable' : await self.dut.MSK_Status.tx_enable.read(), # type: ignore[union-attr] + 'rx_enable' : await self.dut.MSK_Status.rx_enable.read(), # type: ignore[union-attr] + 'tx_axis_valid' : await self.dut.MSK_Status.tx_axis_valid.read() # type: ignore[union-attr] + } + read_callback_mock.reset_mock() + + + async with self.dut.MSK_Status.single_read() as reg_context: # type: ignore[union-attr] + self.assertEqual(reference_read_fields['demod_sync_lock'], + await reg_context.get_child_by_system_rdl_name('demod_sync_lock').read() + ) + self.assertEqual(reference_read_fields['tx_enable'], + await reg_context.get_child_by_system_rdl_name('tx_enable').read() + ) + self.assertEqual(reference_read_fields['rx_enable'], + await reg_context.get_child_by_system_rdl_name('rx_enable').read() + ) + self.assertEqual(reference_read_fields['tx_axis_valid'], + await reg_context.get_child_by_system_rdl_name('tx_axis_valid').read() + ) + pass + + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + # test context manager to register: + # msk_top_regs.Tx_Bit_Count + # build up the register value with a random base value, overlaid with + # a random value for each field + with self.subTest(msg='register: msk_top_regs.Tx_Bit_Count'): + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFFFFFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0x0) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + + # first read the fields using the "normal" method, then compare the result to reading + # via the context manager + reference_read_fields = { + 'tx_bit_counter' : await self.dut.Tx_Bit_Count.tx_bit_counter.read() # type: ignore[union-attr] + } + read_callback_mock.reset_mock() + + + async with self.dut.Tx_Bit_Count.single_read() as reg_context: # type: ignore[union-attr] + self.assertEqual(reference_read_fields['tx_bit_counter'], + await reg_context.get_child_by_system_rdl_name('tx_bit_counter').read() + ) + pass + + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + # test context manager to register: + # msk_top_regs.Tx_Enable_Count + # build up the register value with a random base value, overlaid with + # a random value for each field + with self.subTest(msg='register: msk_top_regs.Tx_Enable_Count'): + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFFFFFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0x0) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + + # first read the fields using the "normal" method, then compare the result to reading + # via the context manager + reference_read_fields = { + 'tx_ena_counter' : await self.dut.Tx_Enable_Count.tx_ena_counter.read() # type: ignore[union-attr] + } + read_callback_mock.reset_mock() + + + async with self.dut.Tx_Enable_Count.single_read() as reg_context: # type: ignore[union-attr] + self.assertEqual(reference_read_fields['tx_ena_counter'], + await reg_context.get_child_by_system_rdl_name('tx_ena_counter').read() + ) + pass + + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + # test context manager to register: + # msk_top_regs.Fb_FreqWord + # build up the register value with a random base value, overlaid with + # a random value for each field + with self.subTest(msg='register: msk_top_regs.Fb_FreqWord'): + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFFFFFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0x0) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + + # first read the fields using the "normal" method, then compare the result to reading + # via the context manager + reference_read_fields = { + 'config_data' : await self.dut.Fb_FreqWord.config_data.read() # type: ignore[union-attr] + } + read_callback_mock.reset_mock() + + + async with self.dut.Fb_FreqWord.single_read_modify_write(skip_write=True) as reg_context: # type: ignore[union-attr] + + self.assertEqual(reference_read_fields['config_data'], + await reg_context.get_child_by_system_rdl_name('config_data').read() + ) + pass + + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + # test context manager to register: + # msk_top_regs.TX_F1_FreqWord + # build up the register value with a random base value, overlaid with + # a random value for each field + with self.subTest(msg='register: msk_top_regs.TX_F1_FreqWord'): + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFFFFFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0x0) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + + # first read the fields using the "normal" method, then compare the result to reading + # via the context manager + reference_read_fields = { + 'config_data' : await self.dut.TX_F1_FreqWord.config_data.read() # type: ignore[union-attr] + } + read_callback_mock.reset_mock() + + + async with self.dut.TX_F1_FreqWord.single_read_modify_write(skip_write=True) as reg_context: # type: ignore[union-attr] + + self.assertEqual(reference_read_fields['config_data'], + await reg_context.get_child_by_system_rdl_name('config_data').read() + ) + pass + + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + # test context manager to register: + # msk_top_regs.TX_F2_FreqWord + # build up the register value with a random base value, overlaid with + # a random value for each field + with self.subTest(msg='register: msk_top_regs.TX_F2_FreqWord'): + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFFFFFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0x0) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + + # first read the fields using the "normal" method, then compare the result to reading + # via the context manager + reference_read_fields = { + 'config_data' : await self.dut.TX_F2_FreqWord.config_data.read() # type: ignore[union-attr] + } + read_callback_mock.reset_mock() + + + async with self.dut.TX_F2_FreqWord.single_read_modify_write(skip_write=True) as reg_context: # type: ignore[union-attr] + + self.assertEqual(reference_read_fields['config_data'], + await reg_context.get_child_by_system_rdl_name('config_data').read() + ) + pass + + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + # test context manager to register: + # msk_top_regs.RX_F1_FreqWord + # build up the register value with a random base value, overlaid with + # a random value for each field + with self.subTest(msg='register: msk_top_regs.RX_F1_FreqWord'): + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFFFFFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0x0) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + + # first read the fields using the "normal" method, then compare the result to reading + # via the context manager + reference_read_fields = { + 'config_data' : await self.dut.RX_F1_FreqWord.config_data.read() # type: ignore[union-attr] + } + read_callback_mock.reset_mock() + + + async with self.dut.RX_F1_FreqWord.single_read_modify_write(skip_write=True) as reg_context: # type: ignore[union-attr] + + self.assertEqual(reference_read_fields['config_data'], + await reg_context.get_child_by_system_rdl_name('config_data').read() + ) + pass + + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + # test context manager to register: + # msk_top_regs.RX_F2_FreqWord + # build up the register value with a random base value, overlaid with + # a random value for each field + with self.subTest(msg='register: msk_top_regs.RX_F2_FreqWord'): + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFFFFFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0x0) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + + # first read the fields using the "normal" method, then compare the result to reading + # via the context manager + reference_read_fields = { + 'config_data' : await self.dut.RX_F2_FreqWord.config_data.read() # type: ignore[union-attr] + } + read_callback_mock.reset_mock() + + + async with self.dut.RX_F2_FreqWord.single_read_modify_write(skip_write=True) as reg_context: # type: ignore[union-attr] + + self.assertEqual(reference_read_fields['config_data'], + await reg_context.get_child_by_system_rdl_name('config_data').read() + ) + pass + + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + # test context manager to register: + # msk_top_regs.LPF_Config_0 + # build up the register value with a random base value, overlaid with + # a random value for each field + with self.subTest(msg='register: msk_top_regs.LPF_Config_0'): + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0x1 + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFFFFFE) | (rand_field_value << 0) + + + + + + + + rand_field_value = random.randrange(0, 0x1 + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFFFFFD) | (rand_field_value << 1) + + + + + + + + rand_field_value = random.randrange(0, 0x3F + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFFFF03) | (rand_field_value << 2) + + + + + + + + rand_field_value = random.randrange(0, 0xFFFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0xFF) | (rand_field_value << 8) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + + # first read the fields using the "normal" method, then compare the result to reading + # via the context manager + reference_read_fields = { + 'lpf_freeze' : await self.dut.LPF_Config_0.lpf_freeze.read(), # type: ignore[union-attr] + 'lpf_zero' : await self.dut.LPF_Config_0.lpf_zero.read(), # type: ignore[union-attr] + 'prbs_reserved' : await self.dut.LPF_Config_0.prbs_reserved.read(), # type: ignore[union-attr] + 'lpf_alpha' : await self.dut.LPF_Config_0.lpf_alpha.read() # type: ignore[union-attr] + } + read_callback_mock.reset_mock() + + + async with self.dut.LPF_Config_0.single_read_modify_write(skip_write=True) as reg_context: # type: ignore[union-attr] + + self.assertEqual(reference_read_fields['lpf_freeze'], + await reg_context.get_child_by_system_rdl_name('lpf_freeze').read() + ) + self.assertEqual(reference_read_fields['lpf_zero'], + await reg_context.get_child_by_system_rdl_name('lpf_zero').read() + ) + self.assertEqual(reference_read_fields['prbs_reserved'], + await reg_context.get_child_by_system_rdl_name('prbs_reserved').read() + ) + self.assertEqual(reference_read_fields['lpf_alpha'], + await reg_context.get_child_by_system_rdl_name('lpf_alpha').read() + ) + pass + + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + # test context manager to register: + # msk_top_regs.LPF_Config_1 + # build up the register value with a random base value, overlaid with + # a random value for each field + with self.subTest(msg='register: msk_top_regs.LPF_Config_1'): + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFFFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0xFF000000) | (rand_field_value << 0) + + + + + + + + rand_field_value = random.randrange(0, 0xFF + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFFFF) | (rand_field_value << 24) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + + # first read the fields using the "normal" method, then compare the result to reading + # via the context manager + reference_read_fields = { + 'i_gain' : await self.dut.LPF_Config_1.i_gain.read(), # type: ignore[union-attr] + 'i_shift' : await self.dut.LPF_Config_1.i_shift.read() # type: ignore[union-attr] + } + read_callback_mock.reset_mock() + + + async with self.dut.LPF_Config_1.single_read_modify_write(skip_write=True) as reg_context: # type: ignore[union-attr] + + self.assertEqual(reference_read_fields['i_gain'], + await reg_context.get_child_by_system_rdl_name('i_gain').read() + ) + self.assertEqual(reference_read_fields['i_shift'], + await reg_context.get_child_by_system_rdl_name('i_shift').read() + ) + pass + + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + # test context manager to register: + # msk_top_regs.Tx_Data_Width + # build up the register value with a random base value, overlaid with + # a random value for each field + with self.subTest(msg='register: msk_top_regs.Tx_Data_Width'): + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFF + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFFFF00) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + + # first read the fields using the "normal" method, then compare the result to reading + # via the context manager + reference_read_fields = { + 'data_width' : await self.dut.Tx_Data_Width.data_width.read() # type: ignore[union-attr] + } + read_callback_mock.reset_mock() + + + async with self.dut.Tx_Data_Width.single_read_modify_write(skip_write=True) as reg_context: # type: ignore[union-attr] + + self.assertEqual(reference_read_fields['data_width'], + await reg_context.get_child_by_system_rdl_name('data_width').read() + ) + pass + + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + # test context manager to register: + # msk_top_regs.Rx_Data_Width + # build up the register value with a random base value, overlaid with + # a random value for each field + with self.subTest(msg='register: msk_top_regs.Rx_Data_Width'): + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFF + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFFFF00) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + + # first read the fields using the "normal" method, then compare the result to reading + # via the context manager + reference_read_fields = { + 'data_width' : await self.dut.Rx_Data_Width.data_width.read() # type: ignore[union-attr] + } + read_callback_mock.reset_mock() + + + async with self.dut.Rx_Data_Width.single_read_modify_write(skip_write=True) as reg_context: # type: ignore[union-attr] + + self.assertEqual(reference_read_fields['data_width'], + await reg_context.get_child_by_system_rdl_name('data_width').read() + ) + pass + + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + # test context manager to register: + # msk_top_regs.PRBS_Control + # build up the register value with a random base value, overlaid with + # a random value for each field + with self.subTest(msg='register: msk_top_regs.PRBS_Control'): + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0x1 + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFFFFFE) | (rand_field_value << 0) + + + + + + + + + + + + + + + + + + + + rand_field_value = random.randrange(0, 0xFFF + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFF000F) | (rand_field_value << 4) + + + + + + + + rand_field_value = random.randrange(0, 0xFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFF) | (rand_field_value << 16) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + + # first read the fields using the "normal" method, then compare the result to reading + # via the context manager + reference_read_fields = { + 'prbs_sel' : await self.dut.PRBS_Control.prbs_sel.read(), # type: ignore[union-attr] + 'prbs_reserved' : await self.dut.PRBS_Control.prbs_reserved.read(), # type: ignore[union-attr] + 'prbs_sync_threshold' : await self.dut.PRBS_Control.prbs_sync_threshold.read() # type: ignore[union-attr] + } + read_callback_mock.reset_mock() + + + async with self.dut.PRBS_Control.single_read_modify_write(skip_write=True) as reg_context: # type: ignore[union-attr] + + self.assertEqual(reference_read_fields['prbs_sel'], + await reg_context.get_child_by_system_rdl_name('prbs_sel').read() + ) + self.assertEqual(reference_read_fields['prbs_reserved'], + await reg_context.get_child_by_system_rdl_name('prbs_reserved').read() + ) + self.assertEqual(reference_read_fields['prbs_sync_threshold'], + await reg_context.get_child_by_system_rdl_name('prbs_sync_threshold').read() + ) + pass + + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + # test context manager to register: + # msk_top_regs.PRBS_Initial_State + # build up the register value with a random base value, overlaid with + # a random value for each field + with self.subTest(msg='register: msk_top_regs.PRBS_Initial_State'): + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFFFFFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0x0) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + + # first read the fields using the "normal" method, then compare the result to reading + # via the context manager + reference_read_fields = { + 'config_data' : await self.dut.PRBS_Initial_State.config_data.read() # type: ignore[union-attr] + } + read_callback_mock.reset_mock() + + + async with self.dut.PRBS_Initial_State.single_read_modify_write(skip_write=True) as reg_context: # type: ignore[union-attr] + + self.assertEqual(reference_read_fields['config_data'], + await reg_context.get_child_by_system_rdl_name('config_data').read() + ) + pass + + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + # test context manager to register: + # msk_top_regs.PRBS_Polynomial + # build up the register value with a random base value, overlaid with + # a random value for each field + with self.subTest(msg='register: msk_top_regs.PRBS_Polynomial'): + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFFFFFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0x0) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + + # first read the fields using the "normal" method, then compare the result to reading + # via the context manager + reference_read_fields = { + 'config_data' : await self.dut.PRBS_Polynomial.config_data.read() # type: ignore[union-attr] + } + read_callback_mock.reset_mock() + + + async with self.dut.PRBS_Polynomial.single_read_modify_write(skip_write=True) as reg_context: # type: ignore[union-attr] + + self.assertEqual(reference_read_fields['config_data'], + await reg_context.get_child_by_system_rdl_name('config_data').read() + ) + pass + + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + # test context manager to register: + # msk_top_regs.PRBS_Error_Mask + # build up the register value with a random base value, overlaid with + # a random value for each field + with self.subTest(msg='register: msk_top_regs.PRBS_Error_Mask'): + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFFFFFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0x0) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + + # first read the fields using the "normal" method, then compare the result to reading + # via the context manager + reference_read_fields = { + 'config_data' : await self.dut.PRBS_Error_Mask.config_data.read() # type: ignore[union-attr] + } + read_callback_mock.reset_mock() + + + async with self.dut.PRBS_Error_Mask.single_read_modify_write(skip_write=True) as reg_context: # type: ignore[union-attr] + + self.assertEqual(reference_read_fields['config_data'], + await reg_context.get_child_by_system_rdl_name('config_data').read() + ) + pass + + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + # test context manager to register: + # msk_top_regs.PRBS_Bit_Count + # build up the register value with a random base value, overlaid with + # a random value for each field + with self.subTest(msg='register: msk_top_regs.PRBS_Bit_Count'): + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFFFFFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0x0) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + + # first read the fields using the "normal" method, then compare the result to reading + # via the context manager + reference_read_fields = { + 'status_data' : await self.dut.PRBS_Bit_Count.status_data.read() # type: ignore[union-attr] + } + read_callback_mock.reset_mock() + + + async with self.dut.PRBS_Bit_Count.single_read() as reg_context: # type: ignore[union-attr] + self.assertEqual(reference_read_fields['status_data'], + await reg_context.get_child_by_system_rdl_name('status_data').read() + ) + pass + + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + # test context manager to register: + # msk_top_regs.PRBS_Error_Count + # build up the register value with a random base value, overlaid with + # a random value for each field + with self.subTest(msg='register: msk_top_regs.PRBS_Error_Count'): + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFFFFFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0x0) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + + # first read the fields using the "normal" method, then compare the result to reading + # via the context manager + reference_read_fields = { + 'status_data' : await self.dut.PRBS_Error_Count.status_data.read() # type: ignore[union-attr] + } + read_callback_mock.reset_mock() + + + async with self.dut.PRBS_Error_Count.single_read() as reg_context: # type: ignore[union-attr] + self.assertEqual(reference_read_fields['status_data'], + await reg_context.get_child_by_system_rdl_name('status_data').read() + ) + pass + + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + # test context manager to register: + # msk_top_regs.LPF_Accum_F1 + # build up the register value with a random base value, overlaid with + # a random value for each field + with self.subTest(msg='register: msk_top_regs.LPF_Accum_F1'): + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFFFFFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0x0) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + + # first read the fields using the "normal" method, then compare the result to reading + # via the context manager + reference_read_fields = { + 'status_data' : await self.dut.LPF_Accum_F1.status_data.read() # type: ignore[union-attr] + } + read_callback_mock.reset_mock() + + + async with self.dut.LPF_Accum_F1.single_read() as reg_context: # type: ignore[union-attr] + self.assertEqual(reference_read_fields['status_data'], + await reg_context.get_child_by_system_rdl_name('status_data').read() + ) + pass + + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + # test context manager to register: + # msk_top_regs.LPF_Accum_F2 + # build up the register value with a random base value, overlaid with + # a random value for each field + with self.subTest(msg='register: msk_top_regs.LPF_Accum_F2'): + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFFFFFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0x0) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + + # first read the fields using the "normal" method, then compare the result to reading + # via the context manager + reference_read_fields = { + 'status_data' : await self.dut.LPF_Accum_F2.status_data.read() # type: ignore[union-attr] + } + read_callback_mock.reset_mock() + + + async with self.dut.LPF_Accum_F2.single_read() as reg_context: # type: ignore[union-attr] + self.assertEqual(reference_read_fields['status_data'], + await reg_context.get_child_by_system_rdl_name('status_data').read() + ) + pass + + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + # test context manager to register: + # msk_top_regs.axis_xfer_count + # build up the register value with a random base value, overlaid with + # a random value for each field + with self.subTest(msg='register: msk_top_regs.axis_xfer_count'): + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFFFFFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0x0) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + + # first read the fields using the "normal" method, then compare the result to reading + # via the context manager + reference_read_fields = { + 'xfer_count' : await self.dut.axis_xfer_count.xfer_count.read() # type: ignore[union-attr] + } + read_callback_mock.reset_mock() + + + async with self.dut.axis_xfer_count.single_read() as reg_context: # type: ignore[union-attr] + self.assertEqual(reference_read_fields['xfer_count'], + await reg_context.get_child_by_system_rdl_name('xfer_count').read() + ) + pass + + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + # test context manager to register: + # msk_top_regs.Rx_Sample_Discard + # build up the register value with a random base value, overlaid with + # a random value for each field + with self.subTest(msg='register: msk_top_regs.Rx_Sample_Discard'): + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFF + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFFFF00) | (rand_field_value << 0) + + + + + + + + rand_field_value = random.randrange(0, 0xFF + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFF00FF) | (rand_field_value << 8) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + + # first read the fields using the "normal" method, then compare the result to reading + # via the context manager + reference_read_fields = { + 'rx_sample_discard' : await self.dut.Rx_Sample_Discard.rx_sample_discard.read(), # type: ignore[union-attr] + 'rx_nco_discard' : await self.dut.Rx_Sample_Discard.rx_nco_discard.read() # type: ignore[union-attr] + } + read_callback_mock.reset_mock() + + + async with self.dut.Rx_Sample_Discard.single_read_modify_write(skip_write=True) as reg_context: # type: ignore[union-attr] + + self.assertEqual(reference_read_fields['rx_sample_discard'], + await reg_context.get_child_by_system_rdl_name('rx_sample_discard').read() + ) + self.assertEqual(reference_read_fields['rx_nco_discard'], + await reg_context.get_child_by_system_rdl_name('rx_nco_discard').read() + ) + pass + + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + # test context manager to register: + # msk_top_regs.LPF_Config_2 + # build up the register value with a random base value, overlaid with + # a random value for each field + with self.subTest(msg='register: msk_top_regs.LPF_Config_2'): + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFFFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0xFF000000) | (rand_field_value << 0) + + + + + + + + rand_field_value = random.randrange(0, 0xFF + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFFFF) | (rand_field_value << 24) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + + # first read the fields using the "normal" method, then compare the result to reading + # via the context manager + reference_read_fields = { + 'p_gain' : await self.dut.LPF_Config_2.p_gain.read(), # type: ignore[union-attr] + 'p_shift' : await self.dut.LPF_Config_2.p_shift.read() # type: ignore[union-attr] + } + read_callback_mock.reset_mock() + + + async with self.dut.LPF_Config_2.single_read_modify_write(skip_write=True) as reg_context: # type: ignore[union-attr] + + self.assertEqual(reference_read_fields['p_gain'], + await reg_context.get_child_by_system_rdl_name('p_gain').read() + ) + self.assertEqual(reference_read_fields['p_shift'], + await reg_context.get_child_by_system_rdl_name('p_shift').read() + ) + pass + + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + # test context manager to register: + # msk_top_regs.f1_nco_adjust + # build up the register value with a random base value, overlaid with + # a random value for each field + with self.subTest(msg='register: msk_top_regs.f1_nco_adjust'): + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFFFFFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0x0) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + + # first read the fields using the "normal" method, then compare the result to reading + # via the context manager + reference_read_fields = { + 'data' : await self.dut.f1_nco_adjust.data.read() # type: ignore[union-attr] + } + read_callback_mock.reset_mock() + + + async with self.dut.f1_nco_adjust.single_read() as reg_context: # type: ignore[union-attr] + self.assertEqual(reference_read_fields['data'], + await reg_context.get_child_by_system_rdl_name('data').read() + ) + pass + + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + # test context manager to register: + # msk_top_regs.f2_nco_adjust + # build up the register value with a random base value, overlaid with + # a random value for each field + with self.subTest(msg='register: msk_top_regs.f2_nco_adjust'): + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFFFFFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0x0) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + + # first read the fields using the "normal" method, then compare the result to reading + # via the context manager + reference_read_fields = { + 'data' : await self.dut.f2_nco_adjust.data.read() # type: ignore[union-attr] + } + read_callback_mock.reset_mock() + + + async with self.dut.f2_nco_adjust.single_read() as reg_context: # type: ignore[union-attr] + self.assertEqual(reference_read_fields['data'], + await reg_context.get_child_by_system_rdl_name('data').read() + ) + pass + + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + # test context manager to register: + # msk_top_regs.f1_error + # build up the register value with a random base value, overlaid with + # a random value for each field + with self.subTest(msg='register: msk_top_regs.f1_error'): + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFFFFFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0x0) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + + # first read the fields using the "normal" method, then compare the result to reading + # via the context manager + reference_read_fields = { + 'data' : await self.dut.f1_error.data.read() # type: ignore[union-attr] + } + read_callback_mock.reset_mock() + + + async with self.dut.f1_error.single_read() as reg_context: # type: ignore[union-attr] + self.assertEqual(reference_read_fields['data'], + await reg_context.get_child_by_system_rdl_name('data').read() + ) + pass + + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + # test context manager to register: + # msk_top_regs.f2_error + # build up the register value with a random base value, overlaid with + # a random value for each field + with self.subTest(msg='register: msk_top_regs.f2_error'): + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFFFFFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0x0) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + + # first read the fields using the "normal" method, then compare the result to reading + # via the context manager + reference_read_fields = { + 'data' : await self.dut.f2_error.data.read() # type: ignore[union-attr] + } + read_callback_mock.reset_mock() + + + async with self.dut.f2_error.single_read() as reg_context: # type: ignore[union-attr] + self.assertEqual(reference_read_fields['data'], + await reg_context.get_child_by_system_rdl_name('data').read() + ) + pass + + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + # test context manager to register: + # msk_top_regs.Tx_Sync_Ctrl + # build up the register value with a random base value, overlaid with + # a random value for each field + with self.subTest(msg='register: msk_top_regs.Tx_Sync_Ctrl'): + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0x1 + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFFFFFE) | (rand_field_value << 0) + + + + + + + + rand_field_value = random.randrange(0, 0x1 + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFFFFFD) | (rand_field_value << 1) + + + + + + + + rand_field_value = random.randrange(0, 0x1 + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFFFFFB) | (rand_field_value << 2) + + + + + + + + rand_field_value = random.randrange(0, 0x1 + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFFFFF7) | (rand_field_value << 3) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + + # first read the fields using the "normal" method, then compare the result to reading + # via the context manager + reference_read_fields = { + 'tx_sync_ena' : await self.dut.Tx_Sync_Ctrl.tx_sync_ena.read(), # type: ignore[union-attr] + 'tx_sync_force' : await self.dut.Tx_Sync_Ctrl.tx_sync_force.read(), # type: ignore[union-attr] + 'tx_sync_f1' : await self.dut.Tx_Sync_Ctrl.tx_sync_f1.read(), # type: ignore[union-attr] + 'tx_sync_f2' : await self.dut.Tx_Sync_Ctrl.tx_sync_f2.read() # type: ignore[union-attr] + } + read_callback_mock.reset_mock() + + + async with self.dut.Tx_Sync_Ctrl.single_read_modify_write(skip_write=True) as reg_context: # type: ignore[union-attr] + + self.assertEqual(reference_read_fields['tx_sync_ena'], + await reg_context.get_child_by_system_rdl_name('tx_sync_ena').read() + ) + self.assertEqual(reference_read_fields['tx_sync_force'], + await reg_context.get_child_by_system_rdl_name('tx_sync_force').read() + ) + self.assertEqual(reference_read_fields['tx_sync_f1'], + await reg_context.get_child_by_system_rdl_name('tx_sync_f1').read() + ) + self.assertEqual(reference_read_fields['tx_sync_f2'], + await reg_context.get_child_by_system_rdl_name('tx_sync_f2').read() + ) + pass + + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + # test context manager to register: + # msk_top_regs.Tx_Sync_Cnt + # build up the register value with a random base value, overlaid with + # a random value for each field + with self.subTest(msg='register: msk_top_regs.Tx_Sync_Cnt'): + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFFFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0xFF000000) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + + # first read the fields using the "normal" method, then compare the result to reading + # via the context manager + reference_read_fields = { + 'tx_sync_cnt' : await self.dut.Tx_Sync_Cnt.tx_sync_cnt.read() # type: ignore[union-attr] + } + read_callback_mock.reset_mock() + + + async with self.dut.Tx_Sync_Cnt.single_read_modify_write(skip_write=True) as reg_context: # type: ignore[union-attr] + + self.assertEqual(reference_read_fields['tx_sync_cnt'], + await reg_context.get_child_by_system_rdl_name('tx_sync_cnt').read() + ) + pass + + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + # test context manager to register: + # msk_top_regs.lowpass_ema_alpha1 + # build up the register value with a random base value, overlaid with + # a random value for each field + with self.subTest(msg='register: msk_top_regs.lowpass_ema_alpha1'): + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0x3FFFF + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFC0000) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + + # first read the fields using the "normal" method, then compare the result to reading + # via the context manager + reference_read_fields = { + 'alpha' : await self.dut.lowpass_ema_alpha1.alpha.read() # type: ignore[union-attr] + } + read_callback_mock.reset_mock() + + + async with self.dut.lowpass_ema_alpha1.single_read_modify_write(skip_write=True) as reg_context: # type: ignore[union-attr] + + self.assertEqual(reference_read_fields['alpha'], + await reg_context.get_child_by_system_rdl_name('alpha').read() + ) + pass + + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + # test context manager to register: + # msk_top_regs.lowpass_ema_alpha2 + # build up the register value with a random base value, overlaid with + # a random value for each field + with self.subTest(msg='register: msk_top_regs.lowpass_ema_alpha2'): + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0x3FFFF + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFC0000) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + + # first read the fields using the "normal" method, then compare the result to reading + # via the context manager + reference_read_fields = { + 'alpha' : await self.dut.lowpass_ema_alpha2.alpha.read() # type: ignore[union-attr] + } + read_callback_mock.reset_mock() + + + async with self.dut.lowpass_ema_alpha2.single_read_modify_write(skip_write=True) as reg_context: # type: ignore[union-attr] + + self.assertEqual(reference_read_fields['alpha'], + await reg_context.get_child_by_system_rdl_name('alpha').read() + ) + pass + + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + # test context manager to register: + # msk_top_regs.rx_power + # build up the register value with a random base value, overlaid with + # a random value for each field + with self.subTest(msg='register: msk_top_regs.rx_power'): + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0x7FFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0xFF800000) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + + # first read the fields using the "normal" method, then compare the result to reading + # via the context manager + reference_read_fields = { + 'rx_power' : await self.dut.rx_power.rx_power.read() # type: ignore[union-attr] + } + read_callback_mock.reset_mock() + + + async with self.dut.rx_power.single_read() as reg_context: # type: ignore[union-attr] + self.assertEqual(reference_read_fields['rx_power'], + await reg_context.get_child_by_system_rdl_name('rx_power').read() + ) + pass + + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + + async def test_register_write_context_manager(self) -> None: + """ + Test the read modify write context manager + """ + async def write_field_combinations(reg: RegAsyncReadWrite, writable_fields:list[str]) -> None: + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + # fix for #196 (excessive test time) if the number of fields is greater than 4 + # the combinations are reduced to only tests combinations of three plus the full + # set + if len(writable_fields) > 4: + perms_iterator: Iterable[int] = chain(range(1,4), [len(writable_fields)]) + else: + perms_iterator = range(1, len(writable_fields) + 1) + for fields_to_write in chain.from_iterable((combinations(writable_fields, perms) for perms in perms_iterator)): + field_values: dict[str, Union[bool, SystemRDLEnum, int]] = {} + expected_value = 0 + for field_str in fields_to_write: + field = getattr(reg, field_str) + if hasattr(field, 'enum_cls'): + rand_enum_value = random_enum_reg_value(field.enum_cls) + rand_field_value = rand_enum_value.value + field_values[field_str] = rand_enum_value + else: + rand_field_value = random.randrange(0, field.max_value + 1) + field_values[field_str] = rand_field_value + + if field.msb == field.high: + expected_value = ( expected_value & field.inverse_bitmask ) | (rand_field_value << field.low) + elif field.msb == field.low: + expected_value = ( expected_value & field.inverse_bitmask ) | (self._reverse_bits(value=rand_field_value, number_bits=field.width) << field.low) + else: + raise RuntimeError('invalid msb/lsb high/low combination') + + # read/write without verify + read_callback_mock.return_value = 0 + async with reg.single_read_modify_write(verify=False) as reg_session: + for field_name, field_value in field_values.items(): + field = getattr(reg_session, field_name) + await field.write(field_value) + + write_callback_mock.assert_called_once_with( + addr=reg.address, + width=reg.width, + accesswidth=reg.accesswidth, + data=expected_value) + read_callback_mock.assert_called_once() + write_callback_mock.reset_mock() + read_callback_mock.reset_mock() + + # read/write/verify pass + async with reg.single_read_modify_write(verify=True) as reg_session: + for field_name, field_value in field_values.items(): + field = getattr(reg_session, field_name) + await field.write(field_value) + read_callback_mock.return_value = expected_value + + write_callback_mock.assert_called_once_with( + addr=reg.address, + width=reg.width, + accesswidth=reg.accesswidth, + data=expected_value) + self.assertEqual(read_callback_mock.call_count, 2) + write_callback_mock.reset_mock() + read_callback_mock.reset_mock() + + # read/write/verify pass + with self.assertRaises(RegisterWriteVerifyError) as context: + async with reg.single_read_modify_write(verify=True) as reg_session: + for field_name, field_value in field_values.items(): + field = getattr(reg_session, field_name) + await field.write(field_value) + read_callback_mock.return_value = expected_value ^ reg_session.max_value + + write_callback_mock.reset_mock() + read_callback_mock.reset_mock() + + + with self.subTest(msg='register: msk_top_regs.MSK_Init'): + await write_field_combinations(reg=self.dut.MSK_Init, + writable_fields = [ 'txrxinit', + 'txinit', + 'rxinit' + ]) + with self.subTest(msg='register: msk_top_regs.MSK_Control'): + await write_field_combinations(reg=self.dut.MSK_Control, + writable_fields = [ 'ptt', + 'loopback_ena', + 'rx_invert', + 'clear_counts', + 'diff_encoder_loopback' + ]) + with self.subTest(msg='register: msk_top_regs.Fb_FreqWord'): + await write_field_combinations(reg=self.dut.Fb_FreqWord, + writable_fields = [ 'config_data' + ]) + with self.subTest(msg='register: msk_top_regs.TX_F1_FreqWord'): + await write_field_combinations(reg=self.dut.TX_F1_FreqWord, + writable_fields = [ 'config_data' + ]) + with self.subTest(msg='register: msk_top_regs.TX_F2_FreqWord'): + await write_field_combinations(reg=self.dut.TX_F2_FreqWord, + writable_fields = [ 'config_data' + ]) + with self.subTest(msg='register: msk_top_regs.RX_F1_FreqWord'): + await write_field_combinations(reg=self.dut.RX_F1_FreqWord, + writable_fields = [ 'config_data' + ]) + with self.subTest(msg='register: msk_top_regs.RX_F2_FreqWord'): + await write_field_combinations(reg=self.dut.RX_F2_FreqWord, + writable_fields = [ 'config_data' + ]) + with self.subTest(msg='register: msk_top_regs.LPF_Config_0'): + await write_field_combinations(reg=self.dut.LPF_Config_0, + writable_fields = [ 'lpf_freeze', + 'lpf_zero', + 'prbs_reserved', + 'lpf_alpha' + ]) + with self.subTest(msg='register: msk_top_regs.LPF_Config_1'): + await write_field_combinations(reg=self.dut.LPF_Config_1, + writable_fields = [ 'i_gain', + 'i_shift' + ]) + with self.subTest(msg='register: msk_top_regs.Tx_Data_Width'): + await write_field_combinations(reg=self.dut.Tx_Data_Width, + writable_fields = [ 'data_width' + ]) + with self.subTest(msg='register: msk_top_regs.Rx_Data_Width'): + await write_field_combinations(reg=self.dut.Rx_Data_Width, + writable_fields = [ 'data_width' + ]) + with self.subTest(msg='register: msk_top_regs.PRBS_Control'): + await write_field_combinations(reg=self.dut.PRBS_Control, + writable_fields = [ 'prbs_sel', + 'prbs_error_insert', + 'prbs_clear', + 'prbs_manual_sync', + 'prbs_reserved', + 'prbs_sync_threshold' + ]) + with self.subTest(msg='register: msk_top_regs.PRBS_Initial_State'): + await write_field_combinations(reg=self.dut.PRBS_Initial_State, + writable_fields = [ 'config_data' + ]) + with self.subTest(msg='register: msk_top_regs.PRBS_Polynomial'): + await write_field_combinations(reg=self.dut.PRBS_Polynomial, + writable_fields = [ 'config_data' + ]) + with self.subTest(msg='register: msk_top_regs.PRBS_Error_Mask'): + await write_field_combinations(reg=self.dut.PRBS_Error_Mask, + writable_fields = [ 'config_data' + ]) + with self.subTest(msg='register: msk_top_regs.Rx_Sample_Discard'): + await write_field_combinations(reg=self.dut.Rx_Sample_Discard, + writable_fields = [ 'rx_sample_discard', + 'rx_nco_discard' + ]) + with self.subTest(msg='register: msk_top_regs.LPF_Config_2'): + await write_field_combinations(reg=self.dut.LPF_Config_2, + writable_fields = [ 'p_gain', + 'p_shift' + ]) + with self.subTest(msg='register: msk_top_regs.Tx_Sync_Ctrl'): + await write_field_combinations(reg=self.dut.Tx_Sync_Ctrl, + writable_fields = [ 'tx_sync_ena', + 'tx_sync_force', + 'tx_sync_f1', + 'tx_sync_f2' + ]) + with self.subTest(msg='register: msk_top_regs.Tx_Sync_Cnt'): + await write_field_combinations(reg=self.dut.Tx_Sync_Cnt, + writable_fields = [ 'tx_sync_cnt' + ]) + with self.subTest(msg='register: msk_top_regs.lowpass_ema_alpha1'): + await write_field_combinations(reg=self.dut.lowpass_ema_alpha1, + writable_fields = [ 'alpha' + ]) + with self.subTest(msg='register: msk_top_regs.lowpass_ema_alpha2'): + await write_field_combinations(reg=self.dut.lowpass_ema_alpha2, + writable_fields = [ 'alpha' + ]) + + async def test_register_write_fields(self) -> None: + """ + Walk the register map and check every register write_fields method + """ + rand_enum_value:SystemRDLEnum + async def write_field_combinations(reg: RegAsyncReadWrite, writable_fields:list[str]) -> None: + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + # fix for #196 (excessive test time) if the number of fields is greater than 4 + # the combinations are reduced to only tests combinations of three plus the full + # set + if len(writable_fields) > 4: + perms_iterator: Iterable[int] = chain(range(1,4), [len(writable_fields)]) + else: + perms_iterator = range(1, len(writable_fields) + 1) + for fields_to_write in chain.from_iterable((combinations(writable_fields, perms) for perms in perms_iterator)): + kwargs: dict[str, Union[bool, SystemRDLEnum, int]] = {} + expected_value = 0 + for field_str in fields_to_write: + field = getattr(reg, field_str) + if hasattr(field, 'enum_cls'): + rand_enum_value = random_enum_reg_value(field.enum_cls) + rand_field_value = rand_enum_value.value + kwargs[field_str] = rand_enum_value + else: + rand_field_value = random.randrange(0, field.max_value + 1) + kwargs[field_str] = rand_field_value + + if field.msb == field.high: + expected_value = ( expected_value & field.inverse_bitmask ) | (rand_field_value << field.low) + elif field.msb == field.low: + expected_value = ( expected_value & field.inverse_bitmask ) | (self._reverse_bits(value=rand_field_value, number_bits=field.width) << field.low) + else: + raise RuntimeError('invalid msb/lsb high/low combination') + + await reg.write_fields(**kwargs) + write_callback_mock.assert_called_once_with( + addr=reg.address, + width=reg.width, + accesswidth=reg.accesswidth, + data=expected_value) + read_callback_mock.assert_called_once() + write_callback_mock.reset_mock() + read_callback_mock.reset_mock() + + kwargs : dict[str, Union[bool, SystemRDLEnum, int]] + + + with self.subTest(msg='register: msk_top_regs.MSK_Init'): + # test read_fields to register: + # msk_top_regs.MSK_Init + await write_field_combinations(reg=self.dut.MSK_Init, + writable_fields = [ 'txrxinit', + 'txinit', + 'rxinit' + ]) + + with self.subTest(msg='register: msk_top_regs.MSK_Control'): + # test read_fields to register: + # msk_top_regs.MSK_Control + await write_field_combinations(reg=self.dut.MSK_Control, + writable_fields = [ 'ptt', + 'loopback_ena', + 'rx_invert', + 'clear_counts', + 'diff_encoder_loopback' + ]) + + with self.subTest(msg='register: msk_top_regs.Fb_FreqWord'): + # test read_fields to register: + # msk_top_regs.Fb_FreqWord + await write_field_combinations(reg=self.dut.Fb_FreqWord, + writable_fields = [ 'config_data' + ]) + + with self.subTest(msg='register: msk_top_regs.TX_F1_FreqWord'): + # test read_fields to register: + # msk_top_regs.TX_F1_FreqWord + await write_field_combinations(reg=self.dut.TX_F1_FreqWord, + writable_fields = [ 'config_data' + ]) + + with self.subTest(msg='register: msk_top_regs.TX_F2_FreqWord'): + # test read_fields to register: + # msk_top_regs.TX_F2_FreqWord + await write_field_combinations(reg=self.dut.TX_F2_FreqWord, + writable_fields = [ 'config_data' + ]) + + with self.subTest(msg='register: msk_top_regs.RX_F1_FreqWord'): + # test read_fields to register: + # msk_top_regs.RX_F1_FreqWord + await write_field_combinations(reg=self.dut.RX_F1_FreqWord, + writable_fields = [ 'config_data' + ]) + + with self.subTest(msg='register: msk_top_regs.RX_F2_FreqWord'): + # test read_fields to register: + # msk_top_regs.RX_F2_FreqWord + await write_field_combinations(reg=self.dut.RX_F2_FreqWord, + writable_fields = [ 'config_data' + ]) + + with self.subTest(msg='register: msk_top_regs.LPF_Config_0'): + # test read_fields to register: + # msk_top_regs.LPF_Config_0 + await write_field_combinations(reg=self.dut.LPF_Config_0, + writable_fields = [ 'lpf_freeze', + 'lpf_zero', + 'prbs_reserved', + 'lpf_alpha' + ]) + + with self.subTest(msg='register: msk_top_regs.LPF_Config_1'): + # test read_fields to register: + # msk_top_regs.LPF_Config_1 + await write_field_combinations(reg=self.dut.LPF_Config_1, + writable_fields = [ 'i_gain', + 'i_shift' + ]) + + with self.subTest(msg='register: msk_top_regs.Tx_Data_Width'): + # test read_fields to register: + # msk_top_regs.Tx_Data_Width + await write_field_combinations(reg=self.dut.Tx_Data_Width, + writable_fields = [ 'data_width' + ]) + + with self.subTest(msg='register: msk_top_regs.Rx_Data_Width'): + # test read_fields to register: + # msk_top_regs.Rx_Data_Width + await write_field_combinations(reg=self.dut.Rx_Data_Width, + writable_fields = [ 'data_width' + ]) + + with self.subTest(msg='register: msk_top_regs.PRBS_Control'): + # test read_fields to register: + # msk_top_regs.PRBS_Control + await write_field_combinations(reg=self.dut.PRBS_Control, + writable_fields = [ 'prbs_sel', + 'prbs_error_insert', + 'prbs_clear', + 'prbs_manual_sync', + 'prbs_reserved', + 'prbs_sync_threshold' + ]) + + with self.subTest(msg='register: msk_top_regs.PRBS_Initial_State'): + # test read_fields to register: + # msk_top_regs.PRBS_Initial_State + await write_field_combinations(reg=self.dut.PRBS_Initial_State, + writable_fields = [ 'config_data' + ]) + + with self.subTest(msg='register: msk_top_regs.PRBS_Polynomial'): + # test read_fields to register: + # msk_top_regs.PRBS_Polynomial + await write_field_combinations(reg=self.dut.PRBS_Polynomial, + writable_fields = [ 'config_data' + ]) + + with self.subTest(msg='register: msk_top_regs.PRBS_Error_Mask'): + # test read_fields to register: + # msk_top_regs.PRBS_Error_Mask + await write_field_combinations(reg=self.dut.PRBS_Error_Mask, + writable_fields = [ 'config_data' + ]) + + with self.subTest(msg='register: msk_top_regs.Rx_Sample_Discard'): + # test read_fields to register: + # msk_top_regs.Rx_Sample_Discard + await write_field_combinations(reg=self.dut.Rx_Sample_Discard, + writable_fields = [ 'rx_sample_discard', + 'rx_nco_discard' + ]) + + with self.subTest(msg='register: msk_top_regs.LPF_Config_2'): + # test read_fields to register: + # msk_top_regs.LPF_Config_2 + await write_field_combinations(reg=self.dut.LPF_Config_2, + writable_fields = [ 'p_gain', + 'p_shift' + ]) + + with self.subTest(msg='register: msk_top_regs.Tx_Sync_Ctrl'): + # test read_fields to register: + # msk_top_regs.Tx_Sync_Ctrl + await write_field_combinations(reg=self.dut.Tx_Sync_Ctrl, + writable_fields = [ 'tx_sync_ena', + 'tx_sync_force', + 'tx_sync_f1', + 'tx_sync_f2' + ]) + + with self.subTest(msg='register: msk_top_regs.Tx_Sync_Cnt'): + # test read_fields to register: + # msk_top_regs.Tx_Sync_Cnt + await write_field_combinations(reg=self.dut.Tx_Sync_Cnt, + writable_fields = [ 'tx_sync_cnt' + ]) + + with self.subTest(msg='register: msk_top_regs.lowpass_ema_alpha1'): + # test read_fields to register: + # msk_top_regs.lowpass_ema_alpha1 + await write_field_combinations(reg=self.dut.lowpass_ema_alpha1, + writable_fields = [ 'alpha' + ]) + + with self.subTest(msg='register: msk_top_regs.lowpass_ema_alpha2'): + # test read_fields to register: + # msk_top_regs.lowpass_ema_alpha2 + await write_field_combinations(reg=self.dut.lowpass_ema_alpha2, + writable_fields = [ 'alpha' + ]) + + + + + def test_adding_attributes(self) -> None: + """ + Walk the address map and attempt to set a new value on each node + + The attribute name: cppkbrgmgeloagvfgjjeiiushygirh was randomly generated to be unlikely to + every be a attribute name + + """ + with self.subTest(msg='node: msk_top_regs.Hash_ID_Low'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.Hash_ID_Low.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.Hash_ID_High'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.Hash_ID_High.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.MSK_Init'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.MSK_Init.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.MSK_Control'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.MSK_Control.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.MSK_Status'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.MSK_Status.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.Tx_Bit_Count'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.Tx_Bit_Count.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.Tx_Enable_Count'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.Tx_Enable_Count.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.Fb_FreqWord'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.Fb_FreqWord.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.TX_F1_FreqWord'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.TX_F1_FreqWord.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.TX_F2_FreqWord'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.TX_F2_FreqWord.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.RX_F1_FreqWord'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.RX_F1_FreqWord.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.RX_F2_FreqWord'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.RX_F2_FreqWord.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.LPF_Config_0'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.LPF_Config_0.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.LPF_Config_1'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.LPF_Config_1.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.Tx_Data_Width'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.Tx_Data_Width.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.Rx_Data_Width'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.Rx_Data_Width.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.PRBS_Control'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.PRBS_Control.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.PRBS_Initial_State'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.PRBS_Initial_State.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.PRBS_Polynomial'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.PRBS_Polynomial.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.PRBS_Error_Mask'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.PRBS_Error_Mask.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.PRBS_Bit_Count'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.PRBS_Bit_Count.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.PRBS_Error_Count'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.PRBS_Error_Count.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.LPF_Accum_F1'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.LPF_Accum_F1.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.LPF_Accum_F2'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.LPF_Accum_F2.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.axis_xfer_count'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.axis_xfer_count.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.Rx_Sample_Discard'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.Rx_Sample_Discard.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.LPF_Config_2'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.LPF_Config_2.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.f1_nco_adjust'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.f1_nco_adjust.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.f2_nco_adjust'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.f2_nco_adjust.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.f1_error'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.f1_error.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.f2_error'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.f2_error.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.Tx_Sync_Ctrl'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.Tx_Sync_Ctrl.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.Tx_Sync_Cnt'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.Tx_Sync_Cnt.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.lowpass_ema_alpha1'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.lowpass_ema_alpha1.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.lowpass_ema_alpha2'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.lowpass_ema_alpha2.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.rx_power'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.rx_power.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.Hash_ID_Low.hash_id_lo'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.Hash_ID_Low.hash_id_lo.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.Hash_ID_High.hash_id_hi'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.Hash_ID_High.hash_id_hi.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.MSK_Init.txrxinit'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.MSK_Init.txrxinit.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.MSK_Init.txinit'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.MSK_Init.txinit.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.MSK_Init.rxinit'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.MSK_Init.rxinit.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.MSK_Control.ptt'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.MSK_Control.ptt.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.MSK_Control.loopback_ena'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.MSK_Control.loopback_ena.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.MSK_Control.rx_invert'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.MSK_Control.rx_invert.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.MSK_Control.clear_counts'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.MSK_Control.clear_counts.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.MSK_Control.diff_encoder_loopback'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.MSK_Control.diff_encoder_loopback.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.MSK_Status.demod_sync_lock'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.MSK_Status.demod_sync_lock.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.MSK_Status.tx_enable'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.MSK_Status.tx_enable.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.MSK_Status.rx_enable'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.MSK_Status.rx_enable.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.MSK_Status.tx_axis_valid'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.MSK_Status.tx_axis_valid.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.Tx_Bit_Count.tx_bit_counter'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.Tx_Bit_Count.tx_bit_counter.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.Tx_Enable_Count.tx_ena_counter'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.Tx_Enable_Count.tx_ena_counter.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.Fb_FreqWord.config_data'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.Fb_FreqWord.config_data.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.TX_F1_FreqWord.config_data'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.TX_F1_FreqWord.config_data.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.TX_F2_FreqWord.config_data'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.TX_F2_FreqWord.config_data.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.RX_F1_FreqWord.config_data'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.RX_F1_FreqWord.config_data.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.RX_F2_FreqWord.config_data'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.RX_F2_FreqWord.config_data.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.LPF_Config_0.lpf_freeze'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.LPF_Config_0.lpf_freeze.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.LPF_Config_0.lpf_zero'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.LPF_Config_0.lpf_zero.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.LPF_Config_0.prbs_reserved'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.LPF_Config_0.prbs_reserved.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.LPF_Config_0.lpf_alpha'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.LPF_Config_0.lpf_alpha.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.LPF_Config_1.i_gain'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.LPF_Config_1.i_gain.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.LPF_Config_1.i_shift'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.LPF_Config_1.i_shift.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.Tx_Data_Width.data_width'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.Tx_Data_Width.data_width.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.Rx_Data_Width.data_width'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.Rx_Data_Width.data_width.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.PRBS_Control.prbs_sel'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.PRBS_Control.prbs_sel.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.PRBS_Control.prbs_error_insert'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.PRBS_Control.prbs_error_insert.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.PRBS_Control.prbs_clear'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.PRBS_Control.prbs_clear.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.PRBS_Control.prbs_manual_sync'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.PRBS_Control.prbs_manual_sync.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.PRBS_Control.prbs_reserved'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.PRBS_Control.prbs_reserved.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.PRBS_Control.prbs_sync_threshold'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.PRBS_Control.prbs_sync_threshold.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.PRBS_Initial_State.config_data'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.PRBS_Initial_State.config_data.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.PRBS_Polynomial.config_data'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.PRBS_Polynomial.config_data.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.PRBS_Error_Mask.config_data'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.PRBS_Error_Mask.config_data.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.PRBS_Bit_Count.status_data'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.PRBS_Bit_Count.status_data.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.PRBS_Error_Count.status_data'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.PRBS_Error_Count.status_data.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.LPF_Accum_F1.status_data'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.LPF_Accum_F1.status_data.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.LPF_Accum_F2.status_data'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.LPF_Accum_F2.status_data.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.axis_xfer_count.xfer_count'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.axis_xfer_count.xfer_count.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.Rx_Sample_Discard.rx_sample_discard'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.Rx_Sample_Discard.rx_sample_discard.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.Rx_Sample_Discard.rx_nco_discard'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.Rx_Sample_Discard.rx_nco_discard.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.LPF_Config_2.p_gain'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.LPF_Config_2.p_gain.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.LPF_Config_2.p_shift'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.LPF_Config_2.p_shift.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.f1_nco_adjust.data'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.f1_nco_adjust.data.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.f2_nco_adjust.data'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.f2_nco_adjust.data.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.f1_error.data'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.f1_error.data.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.f2_error.data'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.f2_error.data.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.Tx_Sync_Ctrl.tx_sync_ena'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.Tx_Sync_Ctrl.tx_sync_ena.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.Tx_Sync_Ctrl.tx_sync_force'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.Tx_Sync_Ctrl.tx_sync_force.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.Tx_Sync_Ctrl.tx_sync_f1'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.Tx_Sync_Ctrl.tx_sync_f1.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.Tx_Sync_Ctrl.tx_sync_f2'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.Tx_Sync_Ctrl.tx_sync_f2.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.Tx_Sync_Cnt.tx_sync_cnt'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.Tx_Sync_Cnt.tx_sync_cnt.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.lowpass_ema_alpha1.alpha'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.lowpass_ema_alpha1.alpha.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.lowpass_ema_alpha2.alpha'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.lowpass_ema_alpha2.alpha.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.rx_power.rx_power'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.rx_power.rx_power.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + + + + def test_top_traversal_iterators(self) -> None: + + expected_writable_regs: list[WritableAsyncRegister] + expected_readable_regs: list[ReadableAsyncRegister] + expected_memories:list[Union[MemoryAsyncReadOnly, MemoryAsyncWriteOnly, MemoryAsyncReadWrite]] + + + expected_sections : list[Union[AsyncAddressMap, AsyncRegFile]] + + # check the readable registers + expected_readable_regs = [self.dut.Hash_ID_Low, # type: ignore[union-attr,list-item] + + self.dut.Hash_ID_High, # type: ignore[union-attr,list-item] + + self.dut.MSK_Init, # type: ignore[union-attr,list-item] + + self.dut.MSK_Control, # type: ignore[union-attr,list-item] + + self.dut.MSK_Status, # type: ignore[union-attr,list-item] + + self.dut.Tx_Bit_Count, # type: ignore[union-attr,list-item] + + self.dut.Tx_Enable_Count, # type: ignore[union-attr,list-item] + + self.dut.Fb_FreqWord, # type: ignore[union-attr,list-item] + + self.dut.TX_F1_FreqWord, # type: ignore[union-attr,list-item] + + self.dut.TX_F2_FreqWord, # type: ignore[union-attr,list-item] + + self.dut.RX_F1_FreqWord, # type: ignore[union-attr,list-item] + + self.dut.RX_F2_FreqWord, # type: ignore[union-attr,list-item] + + self.dut.LPF_Config_0, # type: ignore[union-attr,list-item] + + self.dut.LPF_Config_1, # type: ignore[union-attr,list-item] + + self.dut.Tx_Data_Width, # type: ignore[union-attr,list-item] + + self.dut.Rx_Data_Width, # type: ignore[union-attr,list-item] + + self.dut.PRBS_Control, # type: ignore[union-attr,list-item] + + self.dut.PRBS_Initial_State, # type: ignore[union-attr,list-item] + + self.dut.PRBS_Polynomial, # type: ignore[union-attr,list-item] + + self.dut.PRBS_Error_Mask, # type: ignore[union-attr,list-item] + + self.dut.PRBS_Bit_Count, # type: ignore[union-attr,list-item] + + self.dut.PRBS_Error_Count, # type: ignore[union-attr,list-item] + + self.dut.LPF_Accum_F1, # type: ignore[union-attr,list-item] + + self.dut.LPF_Accum_F2, # type: ignore[union-attr,list-item] + + self.dut.axis_xfer_count, # type: ignore[union-attr,list-item] + + self.dut.Rx_Sample_Discard, # type: ignore[union-attr,list-item] + + self.dut.LPF_Config_2, # type: ignore[union-attr,list-item] + + self.dut.f1_nco_adjust, # type: ignore[union-attr,list-item] + + self.dut.f2_nco_adjust, # type: ignore[union-attr,list-item] + + self.dut.f1_error, # type: ignore[union-attr,list-item] + + self.dut.f2_error, # type: ignore[union-attr,list-item] + + self.dut.Tx_Sync_Ctrl, # type: ignore[union-attr,list-item] + + self.dut.Tx_Sync_Cnt, # type: ignore[union-attr,list-item] + + self.dut.lowpass_ema_alpha1, # type: ignore[union-attr,list-item] + + self.dut.lowpass_ema_alpha2, # type: ignore[union-attr,list-item] + + self.dut.rx_power, # type: ignore[union-attr,list-item] + + ] + readable_regs = [] + for readable_reg in self.dut.get_readable_registers(unroll=True): # type: ignore[union-attr] + self.assertIsInstance(readable_reg, (RegAsyncReadWrite, RegAsyncReadOnly)) + readable_regs.append(readable_reg) + self.assertCountEqual(expected_readable_regs, readable_regs) + + expected_readable_regs = [self.dut.Hash_ID_Low, # type: ignore[union-attr,list-item] + + self.dut.Hash_ID_High, # type: ignore[union-attr,list-item] + + self.dut.MSK_Init, # type: ignore[union-attr,list-item] + + self.dut.MSK_Control, # type: ignore[union-attr,list-item] + + self.dut.MSK_Status, # type: ignore[union-attr,list-item] + + self.dut.Tx_Bit_Count, # type: ignore[union-attr,list-item] + + self.dut.Tx_Enable_Count, # type: ignore[union-attr,list-item] + + self.dut.Fb_FreqWord, # type: ignore[union-attr,list-item] + + self.dut.TX_F1_FreqWord, # type: ignore[union-attr,list-item] + + self.dut.TX_F2_FreqWord, # type: ignore[union-attr,list-item] + + self.dut.RX_F1_FreqWord, # type: ignore[union-attr,list-item] + + self.dut.RX_F2_FreqWord, # type: ignore[union-attr,list-item] + + self.dut.LPF_Config_0, # type: ignore[union-attr,list-item] + + self.dut.LPF_Config_1, # type: ignore[union-attr,list-item] + + self.dut.Tx_Data_Width, # type: ignore[union-attr,list-item] + + self.dut.Rx_Data_Width, # type: ignore[union-attr,list-item] + + self.dut.PRBS_Control, # type: ignore[union-attr,list-item] + + self.dut.PRBS_Initial_State, # type: ignore[union-attr,list-item] + + self.dut.PRBS_Polynomial, # type: ignore[union-attr,list-item] + + self.dut.PRBS_Error_Mask, # type: ignore[union-attr,list-item] + + self.dut.PRBS_Bit_Count, # type: ignore[union-attr,list-item] + + self.dut.PRBS_Error_Count, # type: ignore[union-attr,list-item] + + self.dut.LPF_Accum_F1, # type: ignore[union-attr,list-item] + + self.dut.LPF_Accum_F2, # type: ignore[union-attr,list-item] + + self.dut.axis_xfer_count, # type: ignore[union-attr,list-item] + + self.dut.Rx_Sample_Discard, # type: ignore[union-attr,list-item] + + self.dut.LPF_Config_2, # type: ignore[union-attr,list-item] + + self.dut.f1_nco_adjust, # type: ignore[union-attr,list-item] + + self.dut.f2_nco_adjust, # type: ignore[union-attr,list-item] + + self.dut.f1_error, # type: ignore[union-attr,list-item] + + self.dut.f2_error, # type: ignore[union-attr,list-item] + + self.dut.Tx_Sync_Ctrl, # type: ignore[union-attr,list-item] + + self.dut.Tx_Sync_Cnt, # type: ignore[union-attr,list-item] + + self.dut.lowpass_ema_alpha1, # type: ignore[union-attr,list-item] + + self.dut.lowpass_ema_alpha2, # type: ignore[union-attr,list-item] + + self.dut.rx_power, # type: ignore[union-attr,list-item] + + ] + readable_regs = [] + for readable_reg in self.dut.get_readable_registers(unroll=False): # type: ignore[union-attr] + readable_regs.append(readable_reg) + self.assertCountEqual(expected_readable_regs, readable_regs) + + # check the writable registers + expected_writable_regs = [ + + + + self.dut.MSK_Init, # type: ignore[union-attr,list-item] + + self.dut.MSK_Control, # type: ignore[union-attr,list-item] + + + + + + + + self.dut.Fb_FreqWord, # type: ignore[union-attr,list-item] + + self.dut.TX_F1_FreqWord, # type: ignore[union-attr,list-item] + + self.dut.TX_F2_FreqWord, # type: ignore[union-attr,list-item] + + self.dut.RX_F1_FreqWord, # type: ignore[union-attr,list-item] + + self.dut.RX_F2_FreqWord, # type: ignore[union-attr,list-item] + + self.dut.LPF_Config_0, # type: ignore[union-attr,list-item] + + self.dut.LPF_Config_1, # type: ignore[union-attr,list-item] + + self.dut.Tx_Data_Width, # type: ignore[union-attr,list-item] + + self.dut.Rx_Data_Width, # type: ignore[union-attr,list-item] + + self.dut.PRBS_Control, # type: ignore[union-attr,list-item] + + self.dut.PRBS_Initial_State, # type: ignore[union-attr,list-item] + + self.dut.PRBS_Polynomial, # type: ignore[union-attr,list-item] + + self.dut.PRBS_Error_Mask, # type: ignore[union-attr,list-item] + + + + + + + + + + + + self.dut.Rx_Sample_Discard, # type: ignore[union-attr,list-item] + + self.dut.LPF_Config_2, # type: ignore[union-attr,list-item] + + + + + + + + + + self.dut.Tx_Sync_Ctrl, # type: ignore[union-attr,list-item] + + self.dut.Tx_Sync_Cnt, # type: ignore[union-attr,list-item] + + self.dut.lowpass_ema_alpha1, # type: ignore[union-attr,list-item] + + self.dut.lowpass_ema_alpha2, # type: ignore[union-attr,list-item] + + + + ] + writable_regs = [] + for writable_reg in self.dut.get_writable_registers(unroll=True): # type: ignore[union-attr] + self.assertIsInstance(writable_reg, (RegAsyncReadWrite, RegAsyncWriteOnly)) + writable_regs.append(writable_reg) + self.assertCountEqual(expected_writable_regs, writable_regs) + + expected_writable_regs = [ + + + + self.dut.MSK_Init, # type: ignore[union-attr,list-item] + + self.dut.MSK_Control, # type: ignore[union-attr,list-item] + + + + + + + + self.dut.Fb_FreqWord, # type: ignore[union-attr,list-item] + + self.dut.TX_F1_FreqWord, # type: ignore[union-attr,list-item] + + self.dut.TX_F2_FreqWord, # type: ignore[union-attr,list-item] + + self.dut.RX_F1_FreqWord, # type: ignore[union-attr,list-item] + + self.dut.RX_F2_FreqWord, # type: ignore[union-attr,list-item] + + self.dut.LPF_Config_0, # type: ignore[union-attr,list-item] + + self.dut.LPF_Config_1, # type: ignore[union-attr,list-item] + + self.dut.Tx_Data_Width, # type: ignore[union-attr,list-item] + + self.dut.Rx_Data_Width, # type: ignore[union-attr,list-item] + + self.dut.PRBS_Control, # type: ignore[union-attr,list-item] + + self.dut.PRBS_Initial_State, # type: ignore[union-attr,list-item] + + self.dut.PRBS_Polynomial, # type: ignore[union-attr,list-item] + + self.dut.PRBS_Error_Mask, # type: ignore[union-attr,list-item] + + + + + + + + + + + + self.dut.Rx_Sample_Discard, # type: ignore[union-attr,list-item] + + self.dut.LPF_Config_2, # type: ignore[union-attr,list-item] + + + + + + + + + + self.dut.Tx_Sync_Ctrl, # type: ignore[union-attr,list-item] + + self.dut.Tx_Sync_Cnt, # type: ignore[union-attr,list-item] + + self.dut.lowpass_ema_alpha1, # type: ignore[union-attr,list-item] + + self.dut.lowpass_ema_alpha2, # type: ignore[union-attr,list-item] + + + + ] + writable_regs = [] + for writable_reg in self.dut.get_writable_registers(unroll=False): # type: ignore[union-attr] + writable_regs.append(writable_reg) + self.assertCountEqual(expected_writable_regs, writable_regs) + + # check the sections + expected_sections = [ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ] + sections = [] + for section in self.dut.get_sections(unroll=True): # type: ignore[union-attr] + self.assertIsInstance(section, (AsyncAddressMap, AsyncRegFile)) + sections.append(section) + self.assertCountEqual(expected_sections, sections) + + expected_sections = [ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ] + sections = [] + for section in self.dut.get_sections(unroll=False): # type: ignore[union-attr] + sections.append(section) + self.assertCountEqual(expected_sections, sections) + + # check the memories + expected_memories = [ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ] + memories = [] + for memory in self.dut.get_memories(unroll=True): # type: ignore[union-attr] + self.assertIsInstance(memory, (MemoryAsyncReadOnly, MemoryAsyncWriteOnly, MemoryAsyncReadWrite)) + memories.append(memory) + self.assertCountEqual(expected_memories, memories) + + expected_memories = [ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ] + memories = [] + for memory in self.dut.get_memories(unroll=False): # type: ignore[union-attr] + self.assertIsInstance(memory, (MemoryAsyncReadOnly, MemoryAsyncWriteOnly, MemoryAsyncReadWrite, MemoryAsyncReadOnlyArray, MemoryAsyncWriteOnlyArray, MemoryAsyncReadWriteArray)) + memories.append(memory) + self.assertCountEqual(expected_memories, memories) + + + + + + + + + + + + def test_traversal_iterators(self) -> None: + """ + Walk the address map and check that the iterators for each node as as expected + """ + + expected_writable_fields: list[Union[FieldAsyncWriteOnly, FieldAsyncReadWrite]] + expected_readable_fields: list[Union[FieldAsyncReadOnly, FieldAsyncReadWrite]] + expected_fields: list[Union[FieldAsyncWriteOnly, FieldAsyncReadOnly, FieldAsyncReadWrite]] + expected_writable_regs: list[WritableAsyncRegister] + expected_readable_regs: list[ReadableAsyncRegister] + expected_memories:list[Union[MemoryAsyncReadOnly, MemoryAsyncWriteOnly, MemoryAsyncReadWrite]] + + + expected_sections : list[Union[AsyncAddressMap, AsyncRegFile]] + + # test all the registers + with self.subTest(msg='register: msk_top_regs.Hash_ID_Low'): + + expected_fields = [self.dut.Hash_ID_Low.hash_id_lo, # type: ignore[union-attr,list-item] + + + + ] + fields = [] + for field in self.dut.Hash_ID_Low.fields: # type: ignore[union-attr] + fields.append(field) + self.assertCountEqual(expected_fields, fields) + + # register should not have writable_fields attribute + self.assertFalse(hasattr(self.dut.Hash_ID_Low, 'writable_fields')) # type: ignore[union-attr] + + + expected_readable_fields = [self.dut.Hash_ID_Low.hash_id_lo, # type: ignore[union-attr,list-item] + + + ] + readable_fields = [] + for readable_field in self.dut.Hash_ID_Low.readable_fields: # type: ignore[union-attr] + readable_fields.append(readable_field) + self.assertCountEqual(expected_readable_fields, readable_fields) + + with self.subTest(msg='register: msk_top_regs.Hash_ID_High'): + + expected_fields = [self.dut.Hash_ID_High.hash_id_hi, # type: ignore[union-attr,list-item] + + + + ] + fields = [] + for field in self.dut.Hash_ID_High.fields: # type: ignore[union-attr] + fields.append(field) + self.assertCountEqual(expected_fields, fields) + + # register should not have writable_fields attribute + self.assertFalse(hasattr(self.dut.Hash_ID_High, 'writable_fields')) # type: ignore[union-attr] + + + expected_readable_fields = [self.dut.Hash_ID_High.hash_id_hi, # type: ignore[union-attr,list-item] + + + ] + readable_fields = [] + for readable_field in self.dut.Hash_ID_High.readable_fields: # type: ignore[union-attr] + readable_fields.append(readable_field) + self.assertCountEqual(expected_readable_fields, readable_fields) + + with self.subTest(msg='register: msk_top_regs.MSK_Init'): + + expected_fields = [self.dut.MSK_Init.txrxinit, # type: ignore[union-attr,list-item] + + + self.dut.MSK_Init.txinit, # type: ignore[union-attr,list-item] + + + self.dut.MSK_Init.rxinit, # type: ignore[union-attr,list-item] + + + + ] + fields = [] + for field in self.dut.MSK_Init.fields: # type: ignore[union-attr] + fields.append(field) + self.assertCountEqual(expected_fields, fields) + + expected_writable_fields = [self.dut.MSK_Init.txrxinit, # type: ignore[union-attr,list-item] + + self.dut.MSK_Init.txinit, # type: ignore[union-attr,list-item] + + self.dut.MSK_Init.rxinit, # type: ignore[union-attr,list-item] + + + ] + writable_fields = [] + for writable_field in self.dut.MSK_Init.writable_fields: # type: ignore[union-attr] + writable_fields.append(writable_field) + self.assertCountEqual(expected_writable_fields, writable_fields) + + + expected_readable_fields = [self.dut.MSK_Init.txrxinit, # type: ignore[union-attr,list-item] + + self.dut.MSK_Init.txinit, # type: ignore[union-attr,list-item] + + self.dut.MSK_Init.rxinit, # type: ignore[union-attr,list-item] + + + ] + readable_fields = [] + for readable_field in self.dut.MSK_Init.readable_fields: # type: ignore[union-attr] + readable_fields.append(readable_field) + self.assertCountEqual(expected_readable_fields, readable_fields) + + with self.subTest(msg='register: msk_top_regs.MSK_Control'): + + expected_fields = [self.dut.MSK_Control.ptt, # type: ignore[union-attr,list-item] + + + self.dut.MSK_Control.loopback_ena, # type: ignore[union-attr,list-item] + + + self.dut.MSK_Control.rx_invert, # type: ignore[union-attr,list-item] + + + self.dut.MSK_Control.clear_counts, # type: ignore[union-attr,list-item] + + + self.dut.MSK_Control.diff_encoder_loopback, # type: ignore[union-attr,list-item] + + + + ] + fields = [] + for field in self.dut.MSK_Control.fields: # type: ignore[union-attr] + fields.append(field) + self.assertCountEqual(expected_fields, fields) + + expected_writable_fields = [self.dut.MSK_Control.ptt, # type: ignore[union-attr,list-item] + + self.dut.MSK_Control.loopback_ena, # type: ignore[union-attr,list-item] + + self.dut.MSK_Control.rx_invert, # type: ignore[union-attr,list-item] + + self.dut.MSK_Control.clear_counts, # type: ignore[union-attr,list-item] + + self.dut.MSK_Control.diff_encoder_loopback, # type: ignore[union-attr,list-item] + + + ] + writable_fields = [] + for writable_field in self.dut.MSK_Control.writable_fields: # type: ignore[union-attr] + writable_fields.append(writable_field) + self.assertCountEqual(expected_writable_fields, writable_fields) + + + expected_readable_fields = [self.dut.MSK_Control.ptt, # type: ignore[union-attr,list-item] + + self.dut.MSK_Control.loopback_ena, # type: ignore[union-attr,list-item] + + self.dut.MSK_Control.rx_invert, # type: ignore[union-attr,list-item] + + self.dut.MSK_Control.clear_counts, # type: ignore[union-attr,list-item] + + self.dut.MSK_Control.diff_encoder_loopback, # type: ignore[union-attr,list-item] + + + ] + readable_fields = [] + for readable_field in self.dut.MSK_Control.readable_fields: # type: ignore[union-attr] + readable_fields.append(readable_field) + self.assertCountEqual(expected_readable_fields, readable_fields) + + with self.subTest(msg='register: msk_top_regs.MSK_Status'): + + expected_fields = [self.dut.MSK_Status.demod_sync_lock, # type: ignore[union-attr,list-item] + + + self.dut.MSK_Status.tx_enable, # type: ignore[union-attr,list-item] + + + self.dut.MSK_Status.rx_enable, # type: ignore[union-attr,list-item] + + + self.dut.MSK_Status.tx_axis_valid, # type: ignore[union-attr,list-item] + + + + ] + fields = [] + for field in self.dut.MSK_Status.fields: # type: ignore[union-attr] + fields.append(field) + self.assertCountEqual(expected_fields, fields) + + # register should not have writable_fields attribute + self.assertFalse(hasattr(self.dut.MSK_Status, 'writable_fields')) # type: ignore[union-attr] + + + expected_readable_fields = [self.dut.MSK_Status.demod_sync_lock, # type: ignore[union-attr,list-item] + + self.dut.MSK_Status.tx_enable, # type: ignore[union-attr,list-item] + + self.dut.MSK_Status.rx_enable, # type: ignore[union-attr,list-item] + + self.dut.MSK_Status.tx_axis_valid, # type: ignore[union-attr,list-item] + + + ] + readable_fields = [] + for readable_field in self.dut.MSK_Status.readable_fields: # type: ignore[union-attr] + readable_fields.append(readable_field) + self.assertCountEqual(expected_readable_fields, readable_fields) + + with self.subTest(msg='register: msk_top_regs.Tx_Bit_Count'): + + expected_fields = [self.dut.Tx_Bit_Count.tx_bit_counter, # type: ignore[union-attr,list-item] + + + + ] + fields = [] + for field in self.dut.Tx_Bit_Count.fields: # type: ignore[union-attr] + fields.append(field) + self.assertCountEqual(expected_fields, fields) + + # register should not have writable_fields attribute + self.assertFalse(hasattr(self.dut.Tx_Bit_Count, 'writable_fields')) # type: ignore[union-attr] + + + expected_readable_fields = [self.dut.Tx_Bit_Count.tx_bit_counter, # type: ignore[union-attr,list-item] + + + ] + readable_fields = [] + for readable_field in self.dut.Tx_Bit_Count.readable_fields: # type: ignore[union-attr] + readable_fields.append(readable_field) + self.assertCountEqual(expected_readable_fields, readable_fields) + + with self.subTest(msg='register: msk_top_regs.Tx_Enable_Count'): + + expected_fields = [self.dut.Tx_Enable_Count.tx_ena_counter, # type: ignore[union-attr,list-item] + + + + ] + fields = [] + for field in self.dut.Tx_Enable_Count.fields: # type: ignore[union-attr] + fields.append(field) + self.assertCountEqual(expected_fields, fields) + + # register should not have writable_fields attribute + self.assertFalse(hasattr(self.dut.Tx_Enable_Count, 'writable_fields')) # type: ignore[union-attr] + + + expected_readable_fields = [self.dut.Tx_Enable_Count.tx_ena_counter, # type: ignore[union-attr,list-item] + + + ] + readable_fields = [] + for readable_field in self.dut.Tx_Enable_Count.readable_fields: # type: ignore[union-attr] + readable_fields.append(readable_field) + self.assertCountEqual(expected_readable_fields, readable_fields) + + with self.subTest(msg='register: msk_top_regs.Fb_FreqWord'): + + expected_fields = [self.dut.Fb_FreqWord.config_data, # type: ignore[union-attr,list-item] + + + + ] + fields = [] + for field in self.dut.Fb_FreqWord.fields: # type: ignore[union-attr] + fields.append(field) + self.assertCountEqual(expected_fields, fields) + + expected_writable_fields = [self.dut.Fb_FreqWord.config_data, # type: ignore[union-attr,list-item] + + + ] + writable_fields = [] + for writable_field in self.dut.Fb_FreqWord.writable_fields: # type: ignore[union-attr] + writable_fields.append(writable_field) + self.assertCountEqual(expected_writable_fields, writable_fields) + + + expected_readable_fields = [self.dut.Fb_FreqWord.config_data, # type: ignore[union-attr,list-item] + + + ] + readable_fields = [] + for readable_field in self.dut.Fb_FreqWord.readable_fields: # type: ignore[union-attr] + readable_fields.append(readable_field) + self.assertCountEqual(expected_readable_fields, readable_fields) + + with self.subTest(msg='register: msk_top_regs.TX_F1_FreqWord'): + + expected_fields = [self.dut.TX_F1_FreqWord.config_data, # type: ignore[union-attr,list-item] + + + + ] + fields = [] + for field in self.dut.TX_F1_FreqWord.fields: # type: ignore[union-attr] + fields.append(field) + self.assertCountEqual(expected_fields, fields) + + expected_writable_fields = [self.dut.TX_F1_FreqWord.config_data, # type: ignore[union-attr,list-item] + + + ] + writable_fields = [] + for writable_field in self.dut.TX_F1_FreqWord.writable_fields: # type: ignore[union-attr] + writable_fields.append(writable_field) + self.assertCountEqual(expected_writable_fields, writable_fields) + + + expected_readable_fields = [self.dut.TX_F1_FreqWord.config_data, # type: ignore[union-attr,list-item] + + + ] + readable_fields = [] + for readable_field in self.dut.TX_F1_FreqWord.readable_fields: # type: ignore[union-attr] + readable_fields.append(readable_field) + self.assertCountEqual(expected_readable_fields, readable_fields) + + with self.subTest(msg='register: msk_top_regs.TX_F2_FreqWord'): + + expected_fields = [self.dut.TX_F2_FreqWord.config_data, # type: ignore[union-attr,list-item] + + + + ] + fields = [] + for field in self.dut.TX_F2_FreqWord.fields: # type: ignore[union-attr] + fields.append(field) + self.assertCountEqual(expected_fields, fields) + + expected_writable_fields = [self.dut.TX_F2_FreqWord.config_data, # type: ignore[union-attr,list-item] + + + ] + writable_fields = [] + for writable_field in self.dut.TX_F2_FreqWord.writable_fields: # type: ignore[union-attr] + writable_fields.append(writable_field) + self.assertCountEqual(expected_writable_fields, writable_fields) + + + expected_readable_fields = [self.dut.TX_F2_FreqWord.config_data, # type: ignore[union-attr,list-item] + + + ] + readable_fields = [] + for readable_field in self.dut.TX_F2_FreqWord.readable_fields: # type: ignore[union-attr] + readable_fields.append(readable_field) + self.assertCountEqual(expected_readable_fields, readable_fields) + + with self.subTest(msg='register: msk_top_regs.RX_F1_FreqWord'): + + expected_fields = [self.dut.RX_F1_FreqWord.config_data, # type: ignore[union-attr,list-item] + + + + ] + fields = [] + for field in self.dut.RX_F1_FreqWord.fields: # type: ignore[union-attr] + fields.append(field) + self.assertCountEqual(expected_fields, fields) + + expected_writable_fields = [self.dut.RX_F1_FreqWord.config_data, # type: ignore[union-attr,list-item] + + + ] + writable_fields = [] + for writable_field in self.dut.RX_F1_FreqWord.writable_fields: # type: ignore[union-attr] + writable_fields.append(writable_field) + self.assertCountEqual(expected_writable_fields, writable_fields) + + + expected_readable_fields = [self.dut.RX_F1_FreqWord.config_data, # type: ignore[union-attr,list-item] + + + ] + readable_fields = [] + for readable_field in self.dut.RX_F1_FreqWord.readable_fields: # type: ignore[union-attr] + readable_fields.append(readable_field) + self.assertCountEqual(expected_readable_fields, readable_fields) + + with self.subTest(msg='register: msk_top_regs.RX_F2_FreqWord'): + + expected_fields = [self.dut.RX_F2_FreqWord.config_data, # type: ignore[union-attr,list-item] + + + + ] + fields = [] + for field in self.dut.RX_F2_FreqWord.fields: # type: ignore[union-attr] + fields.append(field) + self.assertCountEqual(expected_fields, fields) + + expected_writable_fields = [self.dut.RX_F2_FreqWord.config_data, # type: ignore[union-attr,list-item] + + + ] + writable_fields = [] + for writable_field in self.dut.RX_F2_FreqWord.writable_fields: # type: ignore[union-attr] + writable_fields.append(writable_field) + self.assertCountEqual(expected_writable_fields, writable_fields) + + + expected_readable_fields = [self.dut.RX_F2_FreqWord.config_data, # type: ignore[union-attr,list-item] + + + ] + readable_fields = [] + for readable_field in self.dut.RX_F2_FreqWord.readable_fields: # type: ignore[union-attr] + readable_fields.append(readable_field) + self.assertCountEqual(expected_readable_fields, readable_fields) + + with self.subTest(msg='register: msk_top_regs.LPF_Config_0'): + + expected_fields = [self.dut.LPF_Config_0.lpf_freeze, # type: ignore[union-attr,list-item] + + + self.dut.LPF_Config_0.lpf_zero, # type: ignore[union-attr,list-item] + + + self.dut.LPF_Config_0.prbs_reserved, # type: ignore[union-attr,list-item] + + + self.dut.LPF_Config_0.lpf_alpha, # type: ignore[union-attr,list-item] + + + + ] + fields = [] + for field in self.dut.LPF_Config_0.fields: # type: ignore[union-attr] + fields.append(field) + self.assertCountEqual(expected_fields, fields) + + expected_writable_fields = [self.dut.LPF_Config_0.lpf_freeze, # type: ignore[union-attr,list-item] + + self.dut.LPF_Config_0.lpf_zero, # type: ignore[union-attr,list-item] + + self.dut.LPF_Config_0.prbs_reserved, # type: ignore[union-attr,list-item] + + self.dut.LPF_Config_0.lpf_alpha, # type: ignore[union-attr,list-item] + + + ] + writable_fields = [] + for writable_field in self.dut.LPF_Config_0.writable_fields: # type: ignore[union-attr] + writable_fields.append(writable_field) + self.assertCountEqual(expected_writable_fields, writable_fields) + + + expected_readable_fields = [self.dut.LPF_Config_0.lpf_freeze, # type: ignore[union-attr,list-item] + + self.dut.LPF_Config_0.lpf_zero, # type: ignore[union-attr,list-item] + + self.dut.LPF_Config_0.prbs_reserved, # type: ignore[union-attr,list-item] + + self.dut.LPF_Config_0.lpf_alpha, # type: ignore[union-attr,list-item] + + + ] + readable_fields = [] + for readable_field in self.dut.LPF_Config_0.readable_fields: # type: ignore[union-attr] + readable_fields.append(readable_field) + self.assertCountEqual(expected_readable_fields, readable_fields) + + with self.subTest(msg='register: msk_top_regs.LPF_Config_1'): + + expected_fields = [self.dut.LPF_Config_1.i_gain, # type: ignore[union-attr,list-item] + + + self.dut.LPF_Config_1.i_shift, # type: ignore[union-attr,list-item] + + + + ] + fields = [] + for field in self.dut.LPF_Config_1.fields: # type: ignore[union-attr] + fields.append(field) + self.assertCountEqual(expected_fields, fields) + + expected_writable_fields = [self.dut.LPF_Config_1.i_gain, # type: ignore[union-attr,list-item] + + self.dut.LPF_Config_1.i_shift, # type: ignore[union-attr,list-item] + + + ] + writable_fields = [] + for writable_field in self.dut.LPF_Config_1.writable_fields: # type: ignore[union-attr] + writable_fields.append(writable_field) + self.assertCountEqual(expected_writable_fields, writable_fields) + + + expected_readable_fields = [self.dut.LPF_Config_1.i_gain, # type: ignore[union-attr,list-item] + + self.dut.LPF_Config_1.i_shift, # type: ignore[union-attr,list-item] + + + ] + readable_fields = [] + for readable_field in self.dut.LPF_Config_1.readable_fields: # type: ignore[union-attr] + readable_fields.append(readable_field) + self.assertCountEqual(expected_readable_fields, readable_fields) + + with self.subTest(msg='register: msk_top_regs.Tx_Data_Width'): + + expected_fields = [self.dut.Tx_Data_Width.data_width, # type: ignore[union-attr,list-item] + + + + ] + fields = [] + for field in self.dut.Tx_Data_Width.fields: # type: ignore[union-attr] + fields.append(field) + self.assertCountEqual(expected_fields, fields) + + expected_writable_fields = [self.dut.Tx_Data_Width.data_width, # type: ignore[union-attr,list-item] + + + ] + writable_fields = [] + for writable_field in self.dut.Tx_Data_Width.writable_fields: # type: ignore[union-attr] + writable_fields.append(writable_field) + self.assertCountEqual(expected_writable_fields, writable_fields) + + + expected_readable_fields = [self.dut.Tx_Data_Width.data_width, # type: ignore[union-attr,list-item] + + + ] + readable_fields = [] + for readable_field in self.dut.Tx_Data_Width.readable_fields: # type: ignore[union-attr] + readable_fields.append(readable_field) + self.assertCountEqual(expected_readable_fields, readable_fields) + + with self.subTest(msg='register: msk_top_regs.Rx_Data_Width'): + + expected_fields = [self.dut.Rx_Data_Width.data_width, # type: ignore[union-attr,list-item] + + + + ] + fields = [] + for field in self.dut.Rx_Data_Width.fields: # type: ignore[union-attr] + fields.append(field) + self.assertCountEqual(expected_fields, fields) + + expected_writable_fields = [self.dut.Rx_Data_Width.data_width, # type: ignore[union-attr,list-item] + + + ] + writable_fields = [] + for writable_field in self.dut.Rx_Data_Width.writable_fields: # type: ignore[union-attr] + writable_fields.append(writable_field) + self.assertCountEqual(expected_writable_fields, writable_fields) + + + expected_readable_fields = [self.dut.Rx_Data_Width.data_width, # type: ignore[union-attr,list-item] + + + ] + readable_fields = [] + for readable_field in self.dut.Rx_Data_Width.readable_fields: # type: ignore[union-attr] + readable_fields.append(readable_field) + self.assertCountEqual(expected_readable_fields, readable_fields) + + with self.subTest(msg='register: msk_top_regs.PRBS_Control'): + + expected_fields = [self.dut.PRBS_Control.prbs_sel, # type: ignore[union-attr,list-item] + + + self.dut.PRBS_Control.prbs_error_insert, # type: ignore[union-attr,list-item] + + + self.dut.PRBS_Control.prbs_clear, # type: ignore[union-attr,list-item] + + + self.dut.PRBS_Control.prbs_manual_sync, # type: ignore[union-attr,list-item] + + + self.dut.PRBS_Control.prbs_reserved, # type: ignore[union-attr,list-item] + + + self.dut.PRBS_Control.prbs_sync_threshold, # type: ignore[union-attr,list-item] + + + + ] + fields = [] + for field in self.dut.PRBS_Control.fields: # type: ignore[union-attr] + fields.append(field) + self.assertCountEqual(expected_fields, fields) + + expected_writable_fields = [self.dut.PRBS_Control.prbs_sel, # type: ignore[union-attr,list-item] + + self.dut.PRBS_Control.prbs_error_insert, # type: ignore[union-attr,list-item] + + self.dut.PRBS_Control.prbs_clear, # type: ignore[union-attr,list-item] + + self.dut.PRBS_Control.prbs_manual_sync, # type: ignore[union-attr,list-item] + + self.dut.PRBS_Control.prbs_reserved, # type: ignore[union-attr,list-item] + + self.dut.PRBS_Control.prbs_sync_threshold, # type: ignore[union-attr,list-item] + + + ] + writable_fields = [] + for writable_field in self.dut.PRBS_Control.writable_fields: # type: ignore[union-attr] + writable_fields.append(writable_field) + self.assertCountEqual(expected_writable_fields, writable_fields) + + + expected_readable_fields = [self.dut.PRBS_Control.prbs_sel, # type: ignore[union-attr,list-item] + + + + + + + + self.dut.PRBS_Control.prbs_reserved, # type: ignore[union-attr,list-item] + + self.dut.PRBS_Control.prbs_sync_threshold, # type: ignore[union-attr,list-item] + + + ] + readable_fields = [] + for readable_field in self.dut.PRBS_Control.readable_fields: # type: ignore[union-attr] + readable_fields.append(readable_field) + self.assertCountEqual(expected_readable_fields, readable_fields) + + with self.subTest(msg='register: msk_top_regs.PRBS_Initial_State'): + + expected_fields = [self.dut.PRBS_Initial_State.config_data, # type: ignore[union-attr,list-item] + + + + ] + fields = [] + for field in self.dut.PRBS_Initial_State.fields: # type: ignore[union-attr] + fields.append(field) + self.assertCountEqual(expected_fields, fields) + + expected_writable_fields = [self.dut.PRBS_Initial_State.config_data, # type: ignore[union-attr,list-item] + + + ] + writable_fields = [] + for writable_field in self.dut.PRBS_Initial_State.writable_fields: # type: ignore[union-attr] + writable_fields.append(writable_field) + self.assertCountEqual(expected_writable_fields, writable_fields) + + + expected_readable_fields = [self.dut.PRBS_Initial_State.config_data, # type: ignore[union-attr,list-item] + + + ] + readable_fields = [] + for readable_field in self.dut.PRBS_Initial_State.readable_fields: # type: ignore[union-attr] + readable_fields.append(readable_field) + self.assertCountEqual(expected_readable_fields, readable_fields) + + with self.subTest(msg='register: msk_top_regs.PRBS_Polynomial'): + + expected_fields = [self.dut.PRBS_Polynomial.config_data, # type: ignore[union-attr,list-item] + + + + ] + fields = [] + for field in self.dut.PRBS_Polynomial.fields: # type: ignore[union-attr] + fields.append(field) + self.assertCountEqual(expected_fields, fields) + + expected_writable_fields = [self.dut.PRBS_Polynomial.config_data, # type: ignore[union-attr,list-item] + + + ] + writable_fields = [] + for writable_field in self.dut.PRBS_Polynomial.writable_fields: # type: ignore[union-attr] + writable_fields.append(writable_field) + self.assertCountEqual(expected_writable_fields, writable_fields) + + + expected_readable_fields = [self.dut.PRBS_Polynomial.config_data, # type: ignore[union-attr,list-item] + + + ] + readable_fields = [] + for readable_field in self.dut.PRBS_Polynomial.readable_fields: # type: ignore[union-attr] + readable_fields.append(readable_field) + self.assertCountEqual(expected_readable_fields, readable_fields) + + with self.subTest(msg='register: msk_top_regs.PRBS_Error_Mask'): + + expected_fields = [self.dut.PRBS_Error_Mask.config_data, # type: ignore[union-attr,list-item] + + + + ] + fields = [] + for field in self.dut.PRBS_Error_Mask.fields: # type: ignore[union-attr] + fields.append(field) + self.assertCountEqual(expected_fields, fields) + + expected_writable_fields = [self.dut.PRBS_Error_Mask.config_data, # type: ignore[union-attr,list-item] + + + ] + writable_fields = [] + for writable_field in self.dut.PRBS_Error_Mask.writable_fields: # type: ignore[union-attr] + writable_fields.append(writable_field) + self.assertCountEqual(expected_writable_fields, writable_fields) + + + expected_readable_fields = [self.dut.PRBS_Error_Mask.config_data, # type: ignore[union-attr,list-item] + + + ] + readable_fields = [] + for readable_field in self.dut.PRBS_Error_Mask.readable_fields: # type: ignore[union-attr] + readable_fields.append(readable_field) + self.assertCountEqual(expected_readable_fields, readable_fields) + + with self.subTest(msg='register: msk_top_regs.PRBS_Bit_Count'): + + expected_fields = [self.dut.PRBS_Bit_Count.status_data, # type: ignore[union-attr,list-item] + + + + ] + fields = [] + for field in self.dut.PRBS_Bit_Count.fields: # type: ignore[union-attr] + fields.append(field) + self.assertCountEqual(expected_fields, fields) + + # register should not have writable_fields attribute + self.assertFalse(hasattr(self.dut.PRBS_Bit_Count, 'writable_fields')) # type: ignore[union-attr] + + + expected_readable_fields = [self.dut.PRBS_Bit_Count.status_data, # type: ignore[union-attr,list-item] + + + ] + readable_fields = [] + for readable_field in self.dut.PRBS_Bit_Count.readable_fields: # type: ignore[union-attr] + readable_fields.append(readable_field) + self.assertCountEqual(expected_readable_fields, readable_fields) + + with self.subTest(msg='register: msk_top_regs.PRBS_Error_Count'): + + expected_fields = [self.dut.PRBS_Error_Count.status_data, # type: ignore[union-attr,list-item] + + + + ] + fields = [] + for field in self.dut.PRBS_Error_Count.fields: # type: ignore[union-attr] + fields.append(field) + self.assertCountEqual(expected_fields, fields) + + # register should not have writable_fields attribute + self.assertFalse(hasattr(self.dut.PRBS_Error_Count, 'writable_fields')) # type: ignore[union-attr] + + + expected_readable_fields = [self.dut.PRBS_Error_Count.status_data, # type: ignore[union-attr,list-item] + + + ] + readable_fields = [] + for readable_field in self.dut.PRBS_Error_Count.readable_fields: # type: ignore[union-attr] + readable_fields.append(readable_field) + self.assertCountEqual(expected_readable_fields, readable_fields) + + with self.subTest(msg='register: msk_top_regs.LPF_Accum_F1'): + + expected_fields = [self.dut.LPF_Accum_F1.status_data, # type: ignore[union-attr,list-item] + + + + ] + fields = [] + for field in self.dut.LPF_Accum_F1.fields: # type: ignore[union-attr] + fields.append(field) + self.assertCountEqual(expected_fields, fields) + + # register should not have writable_fields attribute + self.assertFalse(hasattr(self.dut.LPF_Accum_F1, 'writable_fields')) # type: ignore[union-attr] + + + expected_readable_fields = [self.dut.LPF_Accum_F1.status_data, # type: ignore[union-attr,list-item] + + + ] + readable_fields = [] + for readable_field in self.dut.LPF_Accum_F1.readable_fields: # type: ignore[union-attr] + readable_fields.append(readable_field) + self.assertCountEqual(expected_readable_fields, readable_fields) + + with self.subTest(msg='register: msk_top_regs.LPF_Accum_F2'): + + expected_fields = [self.dut.LPF_Accum_F2.status_data, # type: ignore[union-attr,list-item] + + + + ] + fields = [] + for field in self.dut.LPF_Accum_F2.fields: # type: ignore[union-attr] + fields.append(field) + self.assertCountEqual(expected_fields, fields) + + # register should not have writable_fields attribute + self.assertFalse(hasattr(self.dut.LPF_Accum_F2, 'writable_fields')) # type: ignore[union-attr] + + + expected_readable_fields = [self.dut.LPF_Accum_F2.status_data, # type: ignore[union-attr,list-item] + + + ] + readable_fields = [] + for readable_field in self.dut.LPF_Accum_F2.readable_fields: # type: ignore[union-attr] + readable_fields.append(readable_field) + self.assertCountEqual(expected_readable_fields, readable_fields) + + with self.subTest(msg='register: msk_top_regs.axis_xfer_count'): + + expected_fields = [self.dut.axis_xfer_count.xfer_count, # type: ignore[union-attr,list-item] + + + + ] + fields = [] + for field in self.dut.axis_xfer_count.fields: # type: ignore[union-attr] + fields.append(field) + self.assertCountEqual(expected_fields, fields) + + # register should not have writable_fields attribute + self.assertFalse(hasattr(self.dut.axis_xfer_count, 'writable_fields')) # type: ignore[union-attr] + + + expected_readable_fields = [self.dut.axis_xfer_count.xfer_count, # type: ignore[union-attr,list-item] + + + ] + readable_fields = [] + for readable_field in self.dut.axis_xfer_count.readable_fields: # type: ignore[union-attr] + readable_fields.append(readable_field) + self.assertCountEqual(expected_readable_fields, readable_fields) + + with self.subTest(msg='register: msk_top_regs.Rx_Sample_Discard'): + + expected_fields = [self.dut.Rx_Sample_Discard.rx_sample_discard, # type: ignore[union-attr,list-item] + + + self.dut.Rx_Sample_Discard.rx_nco_discard, # type: ignore[union-attr,list-item] + + + + ] + fields = [] + for field in self.dut.Rx_Sample_Discard.fields: # type: ignore[union-attr] + fields.append(field) + self.assertCountEqual(expected_fields, fields) + + expected_writable_fields = [self.dut.Rx_Sample_Discard.rx_sample_discard, # type: ignore[union-attr,list-item] + + self.dut.Rx_Sample_Discard.rx_nco_discard, # type: ignore[union-attr,list-item] + + + ] + writable_fields = [] + for writable_field in self.dut.Rx_Sample_Discard.writable_fields: # type: ignore[union-attr] + writable_fields.append(writable_field) + self.assertCountEqual(expected_writable_fields, writable_fields) + + + expected_readable_fields = [self.dut.Rx_Sample_Discard.rx_sample_discard, # type: ignore[union-attr,list-item] + + self.dut.Rx_Sample_Discard.rx_nco_discard, # type: ignore[union-attr,list-item] + + + ] + readable_fields = [] + for readable_field in self.dut.Rx_Sample_Discard.readable_fields: # type: ignore[union-attr] + readable_fields.append(readable_field) + self.assertCountEqual(expected_readable_fields, readable_fields) + + with self.subTest(msg='register: msk_top_regs.LPF_Config_2'): + + expected_fields = [self.dut.LPF_Config_2.p_gain, # type: ignore[union-attr,list-item] + + + self.dut.LPF_Config_2.p_shift, # type: ignore[union-attr,list-item] + + + + ] + fields = [] + for field in self.dut.LPF_Config_2.fields: # type: ignore[union-attr] + fields.append(field) + self.assertCountEqual(expected_fields, fields) + + expected_writable_fields = [self.dut.LPF_Config_2.p_gain, # type: ignore[union-attr,list-item] + + self.dut.LPF_Config_2.p_shift, # type: ignore[union-attr,list-item] + + + ] + writable_fields = [] + for writable_field in self.dut.LPF_Config_2.writable_fields: # type: ignore[union-attr] + writable_fields.append(writable_field) + self.assertCountEqual(expected_writable_fields, writable_fields) + + + expected_readable_fields = [self.dut.LPF_Config_2.p_gain, # type: ignore[union-attr,list-item] + + self.dut.LPF_Config_2.p_shift, # type: ignore[union-attr,list-item] + + + ] + readable_fields = [] + for readable_field in self.dut.LPF_Config_2.readable_fields: # type: ignore[union-attr] + readable_fields.append(readable_field) + self.assertCountEqual(expected_readable_fields, readable_fields) + + with self.subTest(msg='register: msk_top_regs.f1_nco_adjust'): + + expected_fields = [self.dut.f1_nco_adjust.data, # type: ignore[union-attr,list-item] + + + + ] + fields = [] + for field in self.dut.f1_nco_adjust.fields: # type: ignore[union-attr] + fields.append(field) + self.assertCountEqual(expected_fields, fields) + + # register should not have writable_fields attribute + self.assertFalse(hasattr(self.dut.f1_nco_adjust, 'writable_fields')) # type: ignore[union-attr] + + + expected_readable_fields = [self.dut.f1_nco_adjust.data, # type: ignore[union-attr,list-item] + + + ] + readable_fields = [] + for readable_field in self.dut.f1_nco_adjust.readable_fields: # type: ignore[union-attr] + readable_fields.append(readable_field) + self.assertCountEqual(expected_readable_fields, readable_fields) + + with self.subTest(msg='register: msk_top_regs.f2_nco_adjust'): + + expected_fields = [self.dut.f2_nco_adjust.data, # type: ignore[union-attr,list-item] + + + + ] + fields = [] + for field in self.dut.f2_nco_adjust.fields: # type: ignore[union-attr] + fields.append(field) + self.assertCountEqual(expected_fields, fields) + + # register should not have writable_fields attribute + self.assertFalse(hasattr(self.dut.f2_nco_adjust, 'writable_fields')) # type: ignore[union-attr] + + + expected_readable_fields = [self.dut.f2_nco_adjust.data, # type: ignore[union-attr,list-item] + + + ] + readable_fields = [] + for readable_field in self.dut.f2_nco_adjust.readable_fields: # type: ignore[union-attr] + readable_fields.append(readable_field) + self.assertCountEqual(expected_readable_fields, readable_fields) + + with self.subTest(msg='register: msk_top_regs.f1_error'): + + expected_fields = [self.dut.f1_error.data, # type: ignore[union-attr,list-item] + + + + ] + fields = [] + for field in self.dut.f1_error.fields: # type: ignore[union-attr] + fields.append(field) + self.assertCountEqual(expected_fields, fields) + + # register should not have writable_fields attribute + self.assertFalse(hasattr(self.dut.f1_error, 'writable_fields')) # type: ignore[union-attr] + + + expected_readable_fields = [self.dut.f1_error.data, # type: ignore[union-attr,list-item] + + + ] + readable_fields = [] + for readable_field in self.dut.f1_error.readable_fields: # type: ignore[union-attr] + readable_fields.append(readable_field) + self.assertCountEqual(expected_readable_fields, readable_fields) + + with self.subTest(msg='register: msk_top_regs.f2_error'): + + expected_fields = [self.dut.f2_error.data, # type: ignore[union-attr,list-item] + + + + ] + fields = [] + for field in self.dut.f2_error.fields: # type: ignore[union-attr] + fields.append(field) + self.assertCountEqual(expected_fields, fields) + + # register should not have writable_fields attribute + self.assertFalse(hasattr(self.dut.f2_error, 'writable_fields')) # type: ignore[union-attr] + + + expected_readable_fields = [self.dut.f2_error.data, # type: ignore[union-attr,list-item] + + + ] + readable_fields = [] + for readable_field in self.dut.f2_error.readable_fields: # type: ignore[union-attr] + readable_fields.append(readable_field) + self.assertCountEqual(expected_readable_fields, readable_fields) + + with self.subTest(msg='register: msk_top_regs.Tx_Sync_Ctrl'): + + expected_fields = [self.dut.Tx_Sync_Ctrl.tx_sync_ena, # type: ignore[union-attr,list-item] + + + self.dut.Tx_Sync_Ctrl.tx_sync_force, # type: ignore[union-attr,list-item] + + + self.dut.Tx_Sync_Ctrl.tx_sync_f1, # type: ignore[union-attr,list-item] + + + self.dut.Tx_Sync_Ctrl.tx_sync_f2, # type: ignore[union-attr,list-item] + + + + ] + fields = [] + for field in self.dut.Tx_Sync_Ctrl.fields: # type: ignore[union-attr] + fields.append(field) + self.assertCountEqual(expected_fields, fields) + + expected_writable_fields = [self.dut.Tx_Sync_Ctrl.tx_sync_ena, # type: ignore[union-attr,list-item] + + self.dut.Tx_Sync_Ctrl.tx_sync_force, # type: ignore[union-attr,list-item] + + self.dut.Tx_Sync_Ctrl.tx_sync_f1, # type: ignore[union-attr,list-item] + + self.dut.Tx_Sync_Ctrl.tx_sync_f2, # type: ignore[union-attr,list-item] + + + ] + writable_fields = [] + for writable_field in self.dut.Tx_Sync_Ctrl.writable_fields: # type: ignore[union-attr] + writable_fields.append(writable_field) + self.assertCountEqual(expected_writable_fields, writable_fields) + + + expected_readable_fields = [self.dut.Tx_Sync_Ctrl.tx_sync_ena, # type: ignore[union-attr,list-item] + + self.dut.Tx_Sync_Ctrl.tx_sync_force, # type: ignore[union-attr,list-item] + + self.dut.Tx_Sync_Ctrl.tx_sync_f1, # type: ignore[union-attr,list-item] + + self.dut.Tx_Sync_Ctrl.tx_sync_f2, # type: ignore[union-attr,list-item] + + + ] + readable_fields = [] + for readable_field in self.dut.Tx_Sync_Ctrl.readable_fields: # type: ignore[union-attr] + readable_fields.append(readable_field) + self.assertCountEqual(expected_readable_fields, readable_fields) + + with self.subTest(msg='register: msk_top_regs.Tx_Sync_Cnt'): + + expected_fields = [self.dut.Tx_Sync_Cnt.tx_sync_cnt, # type: ignore[union-attr,list-item] + + + + ] + fields = [] + for field in self.dut.Tx_Sync_Cnt.fields: # type: ignore[union-attr] + fields.append(field) + self.assertCountEqual(expected_fields, fields) + + expected_writable_fields = [self.dut.Tx_Sync_Cnt.tx_sync_cnt, # type: ignore[union-attr,list-item] + + + ] + writable_fields = [] + for writable_field in self.dut.Tx_Sync_Cnt.writable_fields: # type: ignore[union-attr] + writable_fields.append(writable_field) + self.assertCountEqual(expected_writable_fields, writable_fields) + + + expected_readable_fields = [self.dut.Tx_Sync_Cnt.tx_sync_cnt, # type: ignore[union-attr,list-item] + + + ] + readable_fields = [] + for readable_field in self.dut.Tx_Sync_Cnt.readable_fields: # type: ignore[union-attr] + readable_fields.append(readable_field) + self.assertCountEqual(expected_readable_fields, readable_fields) + + with self.subTest(msg='register: msk_top_regs.lowpass_ema_alpha1'): + + expected_fields = [self.dut.lowpass_ema_alpha1.alpha, # type: ignore[union-attr,list-item] + + + + ] + fields = [] + for field in self.dut.lowpass_ema_alpha1.fields: # type: ignore[union-attr] + fields.append(field) + self.assertCountEqual(expected_fields, fields) + + expected_writable_fields = [self.dut.lowpass_ema_alpha1.alpha, # type: ignore[union-attr,list-item] + + + ] + writable_fields = [] + for writable_field in self.dut.lowpass_ema_alpha1.writable_fields: # type: ignore[union-attr] + writable_fields.append(writable_field) + self.assertCountEqual(expected_writable_fields, writable_fields) + + + expected_readable_fields = [self.dut.lowpass_ema_alpha1.alpha, # type: ignore[union-attr,list-item] + + + ] + readable_fields = [] + for readable_field in self.dut.lowpass_ema_alpha1.readable_fields: # type: ignore[union-attr] + readable_fields.append(readable_field) + self.assertCountEqual(expected_readable_fields, readable_fields) + + with self.subTest(msg='register: msk_top_regs.lowpass_ema_alpha2'): + + expected_fields = [self.dut.lowpass_ema_alpha2.alpha, # type: ignore[union-attr,list-item] + + + + ] + fields = [] + for field in self.dut.lowpass_ema_alpha2.fields: # type: ignore[union-attr] + fields.append(field) + self.assertCountEqual(expected_fields, fields) + + expected_writable_fields = [self.dut.lowpass_ema_alpha2.alpha, # type: ignore[union-attr,list-item] + + + ] + writable_fields = [] + for writable_field in self.dut.lowpass_ema_alpha2.writable_fields: # type: ignore[union-attr] + writable_fields.append(writable_field) + self.assertCountEqual(expected_writable_fields, writable_fields) + + + expected_readable_fields = [self.dut.lowpass_ema_alpha2.alpha, # type: ignore[union-attr,list-item] + + + ] + readable_fields = [] + for readable_field in self.dut.lowpass_ema_alpha2.readable_fields: # type: ignore[union-attr] + readable_fields.append(readable_field) + self.assertCountEqual(expected_readable_fields, readable_fields) + + with self.subTest(msg='register: msk_top_regs.rx_power'): + + expected_fields = [self.dut.rx_power.rx_power, # type: ignore[union-attr,list-item] + + + + ] + fields = [] + for field in self.dut.rx_power.fields: # type: ignore[union-attr] + fields.append(field) + self.assertCountEqual(expected_fields, fields) + + # register should not have writable_fields attribute + self.assertFalse(hasattr(self.dut.rx_power, 'writable_fields')) # type: ignore[union-attr] + + + expected_readable_fields = [self.dut.rx_power.rx_power, # type: ignore[union-attr,list-item] + + + ] + readable_fields = [] + for readable_field in self.dut.rx_power.readable_fields: # type: ignore[union-attr] + readable_fields.append(readable_field) + self.assertCountEqual(expected_readable_fields, readable_fields) + + + # test all the memories + + # test all the address maps + + # test all the register files + + + def test_name_map(self) -> None: + """ + Check that the function for getting a node by its original systemRDL name works + """ + + + self.assertEqual(self.dut.Hash_ID_Low.get_child_by_system_rdl_name('hash_id_lo').inst_name, 'hash_id_lo') + + + + + + self.assertEqual(self.dut.Hash_ID_High.get_child_by_system_rdl_name('hash_id_hi').inst_name, 'hash_id_hi') + + + + + + self.assertEqual(self.dut.MSK_Init.get_child_by_system_rdl_name('txrxinit').inst_name, 'txrxinit') + + + + + self.assertEqual(self.dut.MSK_Init.get_child_by_system_rdl_name('txinit').inst_name, 'txinit') + + + + + self.assertEqual(self.dut.MSK_Init.get_child_by_system_rdl_name('rxinit').inst_name, 'rxinit') + + + + + + self.assertEqual(self.dut.MSK_Control.get_child_by_system_rdl_name('ptt').inst_name, 'ptt') + + + + + self.assertEqual(self.dut.MSK_Control.get_child_by_system_rdl_name('loopback_ena').inst_name, 'loopback_ena') + + + + + self.assertEqual(self.dut.MSK_Control.get_child_by_system_rdl_name('rx_invert').inst_name, 'rx_invert') + + + + + self.assertEqual(self.dut.MSK_Control.get_child_by_system_rdl_name('clear_counts').inst_name, 'clear_counts') + + + + + self.assertEqual(self.dut.MSK_Control.get_child_by_system_rdl_name('diff_encoder_loopback').inst_name, 'diff_encoder_loopback') + + + + + + self.assertEqual(self.dut.MSK_Status.get_child_by_system_rdl_name('demod_sync_lock').inst_name, 'demod_sync_lock') + + + + + self.assertEqual(self.dut.MSK_Status.get_child_by_system_rdl_name('tx_enable').inst_name, 'tx_enable') + + + + + self.assertEqual(self.dut.MSK_Status.get_child_by_system_rdl_name('rx_enable').inst_name, 'rx_enable') + + + + + self.assertEqual(self.dut.MSK_Status.get_child_by_system_rdl_name('tx_axis_valid').inst_name, 'tx_axis_valid') + + + + + + self.assertEqual(self.dut.Tx_Bit_Count.get_child_by_system_rdl_name('tx_bit_counter').inst_name, 'tx_bit_counter') + + + + + + self.assertEqual(self.dut.Tx_Enable_Count.get_child_by_system_rdl_name('tx_ena_counter').inst_name, 'tx_ena_counter') + + + + + + self.assertEqual(self.dut.Fb_FreqWord.get_child_by_system_rdl_name('config_data').inst_name, 'config_data') + + + + + + self.assertEqual(self.dut.TX_F1_FreqWord.get_child_by_system_rdl_name('config_data').inst_name, 'config_data') + + + + + + self.assertEqual(self.dut.TX_F2_FreqWord.get_child_by_system_rdl_name('config_data').inst_name, 'config_data') + + + + + + self.assertEqual(self.dut.RX_F1_FreqWord.get_child_by_system_rdl_name('config_data').inst_name, 'config_data') + + + + + + self.assertEqual(self.dut.RX_F2_FreqWord.get_child_by_system_rdl_name('config_data').inst_name, 'config_data') + + + + + + self.assertEqual(self.dut.LPF_Config_0.get_child_by_system_rdl_name('lpf_freeze').inst_name, 'lpf_freeze') + + + + + self.assertEqual(self.dut.LPF_Config_0.get_child_by_system_rdl_name('lpf_zero').inst_name, 'lpf_zero') + + + + + self.assertEqual(self.dut.LPF_Config_0.get_child_by_system_rdl_name('prbs_reserved').inst_name, 'prbs_reserved') + + + + + self.assertEqual(self.dut.LPF_Config_0.get_child_by_system_rdl_name('lpf_alpha').inst_name, 'lpf_alpha') + + + + + + self.assertEqual(self.dut.LPF_Config_1.get_child_by_system_rdl_name('i_gain').inst_name, 'i_gain') + + + + + self.assertEqual(self.dut.LPF_Config_1.get_child_by_system_rdl_name('i_shift').inst_name, 'i_shift') + + + + + + self.assertEqual(self.dut.Tx_Data_Width.get_child_by_system_rdl_name('data_width').inst_name, 'data_width') + + + + + + self.assertEqual(self.dut.Rx_Data_Width.get_child_by_system_rdl_name('data_width').inst_name, 'data_width') + + + + + + self.assertEqual(self.dut.PRBS_Control.get_child_by_system_rdl_name('prbs_sel').inst_name, 'prbs_sel') + + + + + self.assertEqual(self.dut.PRBS_Control.get_child_by_system_rdl_name('prbs_error_insert').inst_name, 'prbs_error_insert') + + + + + self.assertEqual(self.dut.PRBS_Control.get_child_by_system_rdl_name('prbs_clear').inst_name, 'prbs_clear') + + + + + self.assertEqual(self.dut.PRBS_Control.get_child_by_system_rdl_name('prbs_manual_sync').inst_name, 'prbs_manual_sync') + + + + + self.assertEqual(self.dut.PRBS_Control.get_child_by_system_rdl_name('prbs_reserved').inst_name, 'prbs_reserved') + + + + + self.assertEqual(self.dut.PRBS_Control.get_child_by_system_rdl_name('prbs_sync_threshold').inst_name, 'prbs_sync_threshold') + + + + + + self.assertEqual(self.dut.PRBS_Initial_State.get_child_by_system_rdl_name('config_data').inst_name, 'config_data') + + + + + + self.assertEqual(self.dut.PRBS_Polynomial.get_child_by_system_rdl_name('config_data').inst_name, 'config_data') + + + + + + self.assertEqual(self.dut.PRBS_Error_Mask.get_child_by_system_rdl_name('config_data').inst_name, 'config_data') + + + + + + self.assertEqual(self.dut.PRBS_Bit_Count.get_child_by_system_rdl_name('status_data').inst_name, 'status_data') + + + + + + self.assertEqual(self.dut.PRBS_Error_Count.get_child_by_system_rdl_name('status_data').inst_name, 'status_data') + + + + + + self.assertEqual(self.dut.LPF_Accum_F1.get_child_by_system_rdl_name('status_data').inst_name, 'status_data') + + + + + + self.assertEqual(self.dut.LPF_Accum_F2.get_child_by_system_rdl_name('status_data').inst_name, 'status_data') + + + + + + self.assertEqual(self.dut.axis_xfer_count.get_child_by_system_rdl_name('xfer_count').inst_name, 'xfer_count') + + + + + + self.assertEqual(self.dut.Rx_Sample_Discard.get_child_by_system_rdl_name('rx_sample_discard').inst_name, 'rx_sample_discard') + + + + + self.assertEqual(self.dut.Rx_Sample_Discard.get_child_by_system_rdl_name('rx_nco_discard').inst_name, 'rx_nco_discard') + + + + + + self.assertEqual(self.dut.LPF_Config_2.get_child_by_system_rdl_name('p_gain').inst_name, 'p_gain') + + + + + self.assertEqual(self.dut.LPF_Config_2.get_child_by_system_rdl_name('p_shift').inst_name, 'p_shift') + + + + + + self.assertEqual(self.dut.f1_nco_adjust.get_child_by_system_rdl_name('data').inst_name, 'data') + + + + + + self.assertEqual(self.dut.f2_nco_adjust.get_child_by_system_rdl_name('data').inst_name, 'data') + + + + + + self.assertEqual(self.dut.f1_error.get_child_by_system_rdl_name('data').inst_name, 'data') + + + + + + self.assertEqual(self.dut.f2_error.get_child_by_system_rdl_name('data').inst_name, 'data') + + + + + + self.assertEqual(self.dut.Tx_Sync_Ctrl.get_child_by_system_rdl_name('tx_sync_ena').inst_name, 'tx_sync_ena') + + + + + self.assertEqual(self.dut.Tx_Sync_Ctrl.get_child_by_system_rdl_name('tx_sync_force').inst_name, 'tx_sync_force') + + + + + self.assertEqual(self.dut.Tx_Sync_Ctrl.get_child_by_system_rdl_name('tx_sync_f1').inst_name, 'tx_sync_f1') + + + + + self.assertEqual(self.dut.Tx_Sync_Ctrl.get_child_by_system_rdl_name('tx_sync_f2').inst_name, 'tx_sync_f2') + + + + + + self.assertEqual(self.dut.Tx_Sync_Cnt.get_child_by_system_rdl_name('tx_sync_cnt').inst_name, 'tx_sync_cnt') + + + + + + self.assertEqual(self.dut.lowpass_ema_alpha1.get_child_by_system_rdl_name('alpha').inst_name, 'alpha') + + + + + + self.assertEqual(self.dut.lowpass_ema_alpha2.get_child_by_system_rdl_name('alpha').inst_name, 'alpha') + + + + + + self.assertEqual(self.dut.rx_power.get_child_by_system_rdl_name('rx_power').inst_name, 'rx_power') + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +class msk_top_regs_block_access(msk_top_regs_TestCase_BlockAccess): # type: ignore[valid-type,misc] + """ + tests for all the block access methods + """ + + + + async def test_register_array_context_manager(self) -> None: + """ + Walk the register map and check that register map context managers work correctly + """ + + +class msk_top_regs_alt_block_access(msk_top_regs_TestCase_AltBlockAccess): # type: ignore[valid-type,misc] + """ + tests for all the block access methods with the alternative callbacks, this is a simpler + version of the tests above + """ + + + async def test_register_array_context_manager(self) -> None: + """ + Walk the register map and check that register map context managers work correctly + """ + + + +if __name__ == '__main__': + + if sys.version_info < (3, 8): + asynctest.main() + else: + unittest.main() + + + + diff --git a/rdl/outputs/python/msk_top_regs/tests/test_sim_msk_top_regs.py b/rdl/outputs/python/msk_top_regs/tests/test_sim_msk_top_regs.py new file mode 100644 index 0000000..d649ad0 --- /dev/null +++ b/rdl/outputs/python/msk_top_regs/tests/test_sim_msk_top_regs.py @@ -0,0 +1,7518 @@ + + + +""" +Unit Tests for the msk_top_regs register model Python Wrapper + +This code was generated from the PeakRDL-python package version 1.4.0 +""" + + +from typing import Union, cast + +import sys +import asyncio +import unittest +from unittest.mock import Mock + +import random + + +from ..sim_lib.register import Register,MemoryRegister +from ..sim_lib.field import Field + +from ._msk_top_regs_sim_test_base import msk_top_regs_SimTestCase, msk_top_regs_SimTestCase_BlockAccess +from ._msk_top_regs_sim_test_base import __name__ as base_name +from ._msk_top_regs_test_base import random_enum_reg_value + + +from ..lib import SystemRDLEnum + + +class msk_top_regs_single_access(msk_top_regs_SimTestCase): # type: ignore[valid-type,misc] + + async def test_register_read_and_write(self) -> None: + """ + Walk the register map and check every register can be read and written to correctly + """ + # test access operations (read and/or write) to register: + # msk_top_regs.Hash_ID_Low + with self.subTest(msg='register: msk_top_regs.Hash_ID_Low'): + sim_register = self.sim.register_by_full_name('msk_top_regs.Hash_ID_Low') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + register_read_callback = Mock() + register_write_callback = Mock() + + # register read checks + # update the value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.Hash_ID_Low.read(), random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.Hash_ID_Low.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.value = random_value + sim_register.read_callback = None + sim_register.write_callback = None + self.assertEqual(await self.dut.Hash_ID_Low.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + + + + + + # test access operations (read and/or write) to register: + # msk_top_regs.Hash_ID_High + with self.subTest(msg='register: msk_top_regs.Hash_ID_High'): + sim_register = self.sim.register_by_full_name('msk_top_regs.Hash_ID_High') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + register_read_callback = Mock() + register_write_callback = Mock() + + # register read checks + # update the value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.Hash_ID_High.read(), random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.Hash_ID_High.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.value = random_value + sim_register.read_callback = None + sim_register.write_callback = None + self.assertEqual(await self.dut.Hash_ID_High.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + + + + + + # test access operations (read and/or write) to register: + # msk_top_regs.MSK_Init + with self.subTest(msg='register: msk_top_regs.MSK_Init'): + sim_register = self.sim.register_by_full_name('msk_top_regs.MSK_Init') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + register_read_callback = Mock() + register_write_callback = Mock() + + # register read checks + # update the value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.MSK_Init.read(), random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.MSK_Init.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.value = random_value + sim_register.read_callback = None + sim_register.write_callback = None + self.assertEqual(await self.dut.MSK_Init.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + + + + # register write checks + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.MSK_Init.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.MSK_Init.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + register_write_callback.assert_called_once_with(value=random_value) + register_read_callback.assert_not_called() + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.MSK_Init.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + self.assertEqual(await self.dut.MSK_Init.read(), random_value) + + + + # test access operations (read and/or write) to register: + # msk_top_regs.MSK_Control + with self.subTest(msg='register: msk_top_regs.MSK_Control'): + sim_register = self.sim.register_by_full_name('msk_top_regs.MSK_Control') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + register_read_callback = Mock() + register_write_callback = Mock() + + # register read checks + # update the value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.MSK_Control.read(), random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.MSK_Control.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.value = random_value + sim_register.read_callback = None + sim_register.write_callback = None + self.assertEqual(await self.dut.MSK_Control.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + + + + # register write checks + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.MSK_Control.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.MSK_Control.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + register_write_callback.assert_called_once_with(value=random_value) + register_read_callback.assert_not_called() + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.MSK_Control.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + self.assertEqual(await self.dut.MSK_Control.read(), random_value) + + + + # test access operations (read and/or write) to register: + # msk_top_regs.MSK_Status + with self.subTest(msg='register: msk_top_regs.MSK_Status'): + sim_register = self.sim.register_by_full_name('msk_top_regs.MSK_Status') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + register_read_callback = Mock() + register_write_callback = Mock() + + # register read checks + # update the value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.MSK_Status.read(), random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.MSK_Status.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.value = random_value + sim_register.read_callback = None + sim_register.write_callback = None + self.assertEqual(await self.dut.MSK_Status.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + + + + + + # test access operations (read and/or write) to register: + # msk_top_regs.Tx_Bit_Count + with self.subTest(msg='register: msk_top_regs.Tx_Bit_Count'): + sim_register = self.sim.register_by_full_name('msk_top_regs.Tx_Bit_Count') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + register_read_callback = Mock() + register_write_callback = Mock() + + # register read checks + # update the value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.Tx_Bit_Count.read(), random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.Tx_Bit_Count.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.value = random_value + sim_register.read_callback = None + sim_register.write_callback = None + self.assertEqual(await self.dut.Tx_Bit_Count.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + + + + + + # test access operations (read and/or write) to register: + # msk_top_regs.Tx_Enable_Count + with self.subTest(msg='register: msk_top_regs.Tx_Enable_Count'): + sim_register = self.sim.register_by_full_name('msk_top_regs.Tx_Enable_Count') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + register_read_callback = Mock() + register_write_callback = Mock() + + # register read checks + # update the value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.Tx_Enable_Count.read(), random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.Tx_Enable_Count.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.value = random_value + sim_register.read_callback = None + sim_register.write_callback = None + self.assertEqual(await self.dut.Tx_Enable_Count.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + + + + + + # test access operations (read and/or write) to register: + # msk_top_regs.Fb_FreqWord + with self.subTest(msg='register: msk_top_regs.Fb_FreqWord'): + sim_register = self.sim.register_by_full_name('msk_top_regs.Fb_FreqWord') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + register_read_callback = Mock() + register_write_callback = Mock() + + # register read checks + # update the value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.Fb_FreqWord.read(), random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.Fb_FreqWord.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.value = random_value + sim_register.read_callback = None + sim_register.write_callback = None + self.assertEqual(await self.dut.Fb_FreqWord.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + + + + # register write checks + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.Fb_FreqWord.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.Fb_FreqWord.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + register_write_callback.assert_called_once_with(value=random_value) + register_read_callback.assert_not_called() + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.Fb_FreqWord.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + self.assertEqual(await self.dut.Fb_FreqWord.read(), random_value) + + + + # test access operations (read and/or write) to register: + # msk_top_regs.TX_F1_FreqWord + with self.subTest(msg='register: msk_top_regs.TX_F1_FreqWord'): + sim_register = self.sim.register_by_full_name('msk_top_regs.TX_F1_FreqWord') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + register_read_callback = Mock() + register_write_callback = Mock() + + # register read checks + # update the value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.TX_F1_FreqWord.read(), random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.TX_F1_FreqWord.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.value = random_value + sim_register.read_callback = None + sim_register.write_callback = None + self.assertEqual(await self.dut.TX_F1_FreqWord.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + + + + # register write checks + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.TX_F1_FreqWord.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.TX_F1_FreqWord.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + register_write_callback.assert_called_once_with(value=random_value) + register_read_callback.assert_not_called() + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.TX_F1_FreqWord.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + self.assertEqual(await self.dut.TX_F1_FreqWord.read(), random_value) + + + + # test access operations (read and/or write) to register: + # msk_top_regs.TX_F2_FreqWord + with self.subTest(msg='register: msk_top_regs.TX_F2_FreqWord'): + sim_register = self.sim.register_by_full_name('msk_top_regs.TX_F2_FreqWord') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + register_read_callback = Mock() + register_write_callback = Mock() + + # register read checks + # update the value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.TX_F2_FreqWord.read(), random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.TX_F2_FreqWord.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.value = random_value + sim_register.read_callback = None + sim_register.write_callback = None + self.assertEqual(await self.dut.TX_F2_FreqWord.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + + + + # register write checks + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.TX_F2_FreqWord.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.TX_F2_FreqWord.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + register_write_callback.assert_called_once_with(value=random_value) + register_read_callback.assert_not_called() + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.TX_F2_FreqWord.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + self.assertEqual(await self.dut.TX_F2_FreqWord.read(), random_value) + + + + # test access operations (read and/or write) to register: + # msk_top_regs.RX_F1_FreqWord + with self.subTest(msg='register: msk_top_regs.RX_F1_FreqWord'): + sim_register = self.sim.register_by_full_name('msk_top_regs.RX_F1_FreqWord') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + register_read_callback = Mock() + register_write_callback = Mock() + + # register read checks + # update the value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.RX_F1_FreqWord.read(), random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.RX_F1_FreqWord.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.value = random_value + sim_register.read_callback = None + sim_register.write_callback = None + self.assertEqual(await self.dut.RX_F1_FreqWord.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + + + + # register write checks + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.RX_F1_FreqWord.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.RX_F1_FreqWord.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + register_write_callback.assert_called_once_with(value=random_value) + register_read_callback.assert_not_called() + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.RX_F1_FreqWord.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + self.assertEqual(await self.dut.RX_F1_FreqWord.read(), random_value) + + + + # test access operations (read and/or write) to register: + # msk_top_regs.RX_F2_FreqWord + with self.subTest(msg='register: msk_top_regs.RX_F2_FreqWord'): + sim_register = self.sim.register_by_full_name('msk_top_regs.RX_F2_FreqWord') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + register_read_callback = Mock() + register_write_callback = Mock() + + # register read checks + # update the value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.RX_F2_FreqWord.read(), random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.RX_F2_FreqWord.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.value = random_value + sim_register.read_callback = None + sim_register.write_callback = None + self.assertEqual(await self.dut.RX_F2_FreqWord.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + + + + # register write checks + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.RX_F2_FreqWord.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.RX_F2_FreqWord.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + register_write_callback.assert_called_once_with(value=random_value) + register_read_callback.assert_not_called() + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.RX_F2_FreqWord.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + self.assertEqual(await self.dut.RX_F2_FreqWord.read(), random_value) + + + + # test access operations (read and/or write) to register: + # msk_top_regs.LPF_Config_0 + with self.subTest(msg='register: msk_top_regs.LPF_Config_0'): + sim_register = self.sim.register_by_full_name('msk_top_regs.LPF_Config_0') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + register_read_callback = Mock() + register_write_callback = Mock() + + # register read checks + # update the value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.LPF_Config_0.read(), random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.LPF_Config_0.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.value = random_value + sim_register.read_callback = None + sim_register.write_callback = None + self.assertEqual(await self.dut.LPF_Config_0.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + + + + # register write checks + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.LPF_Config_0.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.LPF_Config_0.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + register_write_callback.assert_called_once_with(value=random_value) + register_read_callback.assert_not_called() + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.LPF_Config_0.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + self.assertEqual(await self.dut.LPF_Config_0.read(), random_value) + + + + # test access operations (read and/or write) to register: + # msk_top_regs.LPF_Config_1 + with self.subTest(msg='register: msk_top_regs.LPF_Config_1'): + sim_register = self.sim.register_by_full_name('msk_top_regs.LPF_Config_1') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + register_read_callback = Mock() + register_write_callback = Mock() + + # register read checks + # update the value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.LPF_Config_1.read(), random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.LPF_Config_1.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.value = random_value + sim_register.read_callback = None + sim_register.write_callback = None + self.assertEqual(await self.dut.LPF_Config_1.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + + + + # register write checks + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.LPF_Config_1.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.LPF_Config_1.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + register_write_callback.assert_called_once_with(value=random_value) + register_read_callback.assert_not_called() + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.LPF_Config_1.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + self.assertEqual(await self.dut.LPF_Config_1.read(), random_value) + + + + # test access operations (read and/or write) to register: + # msk_top_regs.Tx_Data_Width + with self.subTest(msg='register: msk_top_regs.Tx_Data_Width'): + sim_register = self.sim.register_by_full_name('msk_top_regs.Tx_Data_Width') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + register_read_callback = Mock() + register_write_callback = Mock() + + # register read checks + # update the value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.Tx_Data_Width.read(), random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.Tx_Data_Width.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.value = random_value + sim_register.read_callback = None + sim_register.write_callback = None + self.assertEqual(await self.dut.Tx_Data_Width.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + + + + # register write checks + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.Tx_Data_Width.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.Tx_Data_Width.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + register_write_callback.assert_called_once_with(value=random_value) + register_read_callback.assert_not_called() + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.Tx_Data_Width.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + self.assertEqual(await self.dut.Tx_Data_Width.read(), random_value) + + + + # test access operations (read and/or write) to register: + # msk_top_regs.Rx_Data_Width + with self.subTest(msg='register: msk_top_regs.Rx_Data_Width'): + sim_register = self.sim.register_by_full_name('msk_top_regs.Rx_Data_Width') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + register_read_callback = Mock() + register_write_callback = Mock() + + # register read checks + # update the value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.Rx_Data_Width.read(), random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.Rx_Data_Width.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.value = random_value + sim_register.read_callback = None + sim_register.write_callback = None + self.assertEqual(await self.dut.Rx_Data_Width.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + + + + # register write checks + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.Rx_Data_Width.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.Rx_Data_Width.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + register_write_callback.assert_called_once_with(value=random_value) + register_read_callback.assert_not_called() + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.Rx_Data_Width.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + self.assertEqual(await self.dut.Rx_Data_Width.read(), random_value) + + + + # test access operations (read and/or write) to register: + # msk_top_regs.PRBS_Control + with self.subTest(msg='register: msk_top_regs.PRBS_Control'): + sim_register = self.sim.register_by_full_name('msk_top_regs.PRBS_Control') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + register_read_callback = Mock() + register_write_callback = Mock() + + # register read checks + # update the value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.PRBS_Control.read(), random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.PRBS_Control.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.value = random_value + sim_register.read_callback = None + sim_register.write_callback = None + self.assertEqual(await self.dut.PRBS_Control.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + + + + # register write checks + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.PRBS_Control.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.PRBS_Control.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + register_write_callback.assert_called_once_with(value=random_value) + register_read_callback.assert_not_called() + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.PRBS_Control.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + self.assertEqual(await self.dut.PRBS_Control.read(), random_value) + + + + # test access operations (read and/or write) to register: + # msk_top_regs.PRBS_Initial_State + with self.subTest(msg='register: msk_top_regs.PRBS_Initial_State'): + sim_register = self.sim.register_by_full_name('msk_top_regs.PRBS_Initial_State') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + register_read_callback = Mock() + register_write_callback = Mock() + + # register read checks + # update the value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.PRBS_Initial_State.read(), random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.PRBS_Initial_State.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.value = random_value + sim_register.read_callback = None + sim_register.write_callback = None + self.assertEqual(await self.dut.PRBS_Initial_State.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + + + + # register write checks + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.PRBS_Initial_State.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.PRBS_Initial_State.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + register_write_callback.assert_called_once_with(value=random_value) + register_read_callback.assert_not_called() + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.PRBS_Initial_State.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + self.assertEqual(await self.dut.PRBS_Initial_State.read(), random_value) + + + + # test access operations (read and/or write) to register: + # msk_top_regs.PRBS_Polynomial + with self.subTest(msg='register: msk_top_regs.PRBS_Polynomial'): + sim_register = self.sim.register_by_full_name('msk_top_regs.PRBS_Polynomial') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + register_read_callback = Mock() + register_write_callback = Mock() + + # register read checks + # update the value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.PRBS_Polynomial.read(), random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.PRBS_Polynomial.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.value = random_value + sim_register.read_callback = None + sim_register.write_callback = None + self.assertEqual(await self.dut.PRBS_Polynomial.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + + + + # register write checks + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.PRBS_Polynomial.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.PRBS_Polynomial.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + register_write_callback.assert_called_once_with(value=random_value) + register_read_callback.assert_not_called() + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.PRBS_Polynomial.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + self.assertEqual(await self.dut.PRBS_Polynomial.read(), random_value) + + + + # test access operations (read and/or write) to register: + # msk_top_regs.PRBS_Error_Mask + with self.subTest(msg='register: msk_top_regs.PRBS_Error_Mask'): + sim_register = self.sim.register_by_full_name('msk_top_regs.PRBS_Error_Mask') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + register_read_callback = Mock() + register_write_callback = Mock() + + # register read checks + # update the value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.PRBS_Error_Mask.read(), random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.PRBS_Error_Mask.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.value = random_value + sim_register.read_callback = None + sim_register.write_callback = None + self.assertEqual(await self.dut.PRBS_Error_Mask.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + + + + # register write checks + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.PRBS_Error_Mask.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.PRBS_Error_Mask.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + register_write_callback.assert_called_once_with(value=random_value) + register_read_callback.assert_not_called() + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.PRBS_Error_Mask.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + self.assertEqual(await self.dut.PRBS_Error_Mask.read(), random_value) + + + + # test access operations (read and/or write) to register: + # msk_top_regs.PRBS_Bit_Count + with self.subTest(msg='register: msk_top_regs.PRBS_Bit_Count'): + sim_register = self.sim.register_by_full_name('msk_top_regs.PRBS_Bit_Count') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + register_read_callback = Mock() + register_write_callback = Mock() + + # register read checks + # update the value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.PRBS_Bit_Count.read(), random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.PRBS_Bit_Count.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.value = random_value + sim_register.read_callback = None + sim_register.write_callback = None + self.assertEqual(await self.dut.PRBS_Bit_Count.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + + + + + + # test access operations (read and/or write) to register: + # msk_top_regs.PRBS_Error_Count + with self.subTest(msg='register: msk_top_regs.PRBS_Error_Count'): + sim_register = self.sim.register_by_full_name('msk_top_regs.PRBS_Error_Count') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + register_read_callback = Mock() + register_write_callback = Mock() + + # register read checks + # update the value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.PRBS_Error_Count.read(), random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.PRBS_Error_Count.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.value = random_value + sim_register.read_callback = None + sim_register.write_callback = None + self.assertEqual(await self.dut.PRBS_Error_Count.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + + + + + + # test access operations (read and/or write) to register: + # msk_top_regs.LPF_Accum_F1 + with self.subTest(msg='register: msk_top_regs.LPF_Accum_F1'): + sim_register = self.sim.register_by_full_name('msk_top_regs.LPF_Accum_F1') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + register_read_callback = Mock() + register_write_callback = Mock() + + # register read checks + # update the value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.LPF_Accum_F1.read(), random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.LPF_Accum_F1.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.value = random_value + sim_register.read_callback = None + sim_register.write_callback = None + self.assertEqual(await self.dut.LPF_Accum_F1.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + + + + + + # test access operations (read and/or write) to register: + # msk_top_regs.LPF_Accum_F2 + with self.subTest(msg='register: msk_top_regs.LPF_Accum_F2'): + sim_register = self.sim.register_by_full_name('msk_top_regs.LPF_Accum_F2') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + register_read_callback = Mock() + register_write_callback = Mock() + + # register read checks + # update the value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.LPF_Accum_F2.read(), random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.LPF_Accum_F2.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.value = random_value + sim_register.read_callback = None + sim_register.write_callback = None + self.assertEqual(await self.dut.LPF_Accum_F2.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + + + + + + # test access operations (read and/or write) to register: + # msk_top_regs.axis_xfer_count + with self.subTest(msg='register: msk_top_regs.axis_xfer_count'): + sim_register = self.sim.register_by_full_name('msk_top_regs.axis_xfer_count') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + register_read_callback = Mock() + register_write_callback = Mock() + + # register read checks + # update the value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.axis_xfer_count.read(), random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.axis_xfer_count.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.value = random_value + sim_register.read_callback = None + sim_register.write_callback = None + self.assertEqual(await self.dut.axis_xfer_count.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + + + + + + # test access operations (read and/or write) to register: + # msk_top_regs.Rx_Sample_Discard + with self.subTest(msg='register: msk_top_regs.Rx_Sample_Discard'): + sim_register = self.sim.register_by_full_name('msk_top_regs.Rx_Sample_Discard') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + register_read_callback = Mock() + register_write_callback = Mock() + + # register read checks + # update the value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.Rx_Sample_Discard.read(), random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.Rx_Sample_Discard.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.value = random_value + sim_register.read_callback = None + sim_register.write_callback = None + self.assertEqual(await self.dut.Rx_Sample_Discard.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + + + + # register write checks + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.Rx_Sample_Discard.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.Rx_Sample_Discard.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + register_write_callback.assert_called_once_with(value=random_value) + register_read_callback.assert_not_called() + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.Rx_Sample_Discard.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + self.assertEqual(await self.dut.Rx_Sample_Discard.read(), random_value) + + + + # test access operations (read and/or write) to register: + # msk_top_regs.LPF_Config_2 + with self.subTest(msg='register: msk_top_regs.LPF_Config_2'): + sim_register = self.sim.register_by_full_name('msk_top_regs.LPF_Config_2') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + register_read_callback = Mock() + register_write_callback = Mock() + + # register read checks + # update the value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.LPF_Config_2.read(), random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.LPF_Config_2.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.value = random_value + sim_register.read_callback = None + sim_register.write_callback = None + self.assertEqual(await self.dut.LPF_Config_2.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + + + + # register write checks + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.LPF_Config_2.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.LPF_Config_2.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + register_write_callback.assert_called_once_with(value=random_value) + register_read_callback.assert_not_called() + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.LPF_Config_2.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + self.assertEqual(await self.dut.LPF_Config_2.read(), random_value) + + + + # test access operations (read and/or write) to register: + # msk_top_regs.f1_nco_adjust + with self.subTest(msg='register: msk_top_regs.f1_nco_adjust'): + sim_register = self.sim.register_by_full_name('msk_top_regs.f1_nco_adjust') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + register_read_callback = Mock() + register_write_callback = Mock() + + # register read checks + # update the value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.f1_nco_adjust.read(), random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.f1_nco_adjust.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.value = random_value + sim_register.read_callback = None + sim_register.write_callback = None + self.assertEqual(await self.dut.f1_nco_adjust.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + + + + + + # test access operations (read and/or write) to register: + # msk_top_regs.f2_nco_adjust + with self.subTest(msg='register: msk_top_regs.f2_nco_adjust'): + sim_register = self.sim.register_by_full_name('msk_top_regs.f2_nco_adjust') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + register_read_callback = Mock() + register_write_callback = Mock() + + # register read checks + # update the value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.f2_nco_adjust.read(), random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.f2_nco_adjust.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.value = random_value + sim_register.read_callback = None + sim_register.write_callback = None + self.assertEqual(await self.dut.f2_nco_adjust.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + + + + + + # test access operations (read and/or write) to register: + # msk_top_regs.f1_error + with self.subTest(msg='register: msk_top_regs.f1_error'): + sim_register = self.sim.register_by_full_name('msk_top_regs.f1_error') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + register_read_callback = Mock() + register_write_callback = Mock() + + # register read checks + # update the value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.f1_error.read(), random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.f1_error.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.value = random_value + sim_register.read_callback = None + sim_register.write_callback = None + self.assertEqual(await self.dut.f1_error.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + + + + + + # test access operations (read and/or write) to register: + # msk_top_regs.f2_error + with self.subTest(msg='register: msk_top_regs.f2_error'): + sim_register = self.sim.register_by_full_name('msk_top_regs.f2_error') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + register_read_callback = Mock() + register_write_callback = Mock() + + # register read checks + # update the value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.f2_error.read(), random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.f2_error.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.value = random_value + sim_register.read_callback = None + sim_register.write_callback = None + self.assertEqual(await self.dut.f2_error.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + + + + + + # test access operations (read and/or write) to register: + # msk_top_regs.Tx_Sync_Ctrl + with self.subTest(msg='register: msk_top_regs.Tx_Sync_Ctrl'): + sim_register = self.sim.register_by_full_name('msk_top_regs.Tx_Sync_Ctrl') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + register_read_callback = Mock() + register_write_callback = Mock() + + # register read checks + # update the value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.Tx_Sync_Ctrl.read(), random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.Tx_Sync_Ctrl.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.value = random_value + sim_register.read_callback = None + sim_register.write_callback = None + self.assertEqual(await self.dut.Tx_Sync_Ctrl.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + + + + # register write checks + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.Tx_Sync_Ctrl.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.Tx_Sync_Ctrl.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + register_write_callback.assert_called_once_with(value=random_value) + register_read_callback.assert_not_called() + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.Tx_Sync_Ctrl.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + self.assertEqual(await self.dut.Tx_Sync_Ctrl.read(), random_value) + + + + # test access operations (read and/or write) to register: + # msk_top_regs.Tx_Sync_Cnt + with self.subTest(msg='register: msk_top_regs.Tx_Sync_Cnt'): + sim_register = self.sim.register_by_full_name('msk_top_regs.Tx_Sync_Cnt') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + register_read_callback = Mock() + register_write_callback = Mock() + + # register read checks + # update the value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.Tx_Sync_Cnt.read(), random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.Tx_Sync_Cnt.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.value = random_value + sim_register.read_callback = None + sim_register.write_callback = None + self.assertEqual(await self.dut.Tx_Sync_Cnt.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + + + + # register write checks + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.Tx_Sync_Cnt.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.Tx_Sync_Cnt.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + register_write_callback.assert_called_once_with(value=random_value) + register_read_callback.assert_not_called() + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.Tx_Sync_Cnt.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + self.assertEqual(await self.dut.Tx_Sync_Cnt.read(), random_value) + + + + # test access operations (read and/or write) to register: + # msk_top_regs.lowpass_ema_alpha1 + with self.subTest(msg='register: msk_top_regs.lowpass_ema_alpha1'): + sim_register = self.sim.register_by_full_name('msk_top_regs.lowpass_ema_alpha1') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + register_read_callback = Mock() + register_write_callback = Mock() + + # register read checks + # update the value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.lowpass_ema_alpha1.read(), random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.lowpass_ema_alpha1.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.value = random_value + sim_register.read_callback = None + sim_register.write_callback = None + self.assertEqual(await self.dut.lowpass_ema_alpha1.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + + + + # register write checks + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.lowpass_ema_alpha1.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.lowpass_ema_alpha1.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + register_write_callback.assert_called_once_with(value=random_value) + register_read_callback.assert_not_called() + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.lowpass_ema_alpha1.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + self.assertEqual(await self.dut.lowpass_ema_alpha1.read(), random_value) + + + + # test access operations (read and/or write) to register: + # msk_top_regs.lowpass_ema_alpha2 + with self.subTest(msg='register: msk_top_regs.lowpass_ema_alpha2'): + sim_register = self.sim.register_by_full_name('msk_top_regs.lowpass_ema_alpha2') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + register_read_callback = Mock() + register_write_callback = Mock() + + # register read checks + # update the value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.lowpass_ema_alpha2.read(), random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.lowpass_ema_alpha2.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.value = random_value + sim_register.read_callback = None + sim_register.write_callback = None + self.assertEqual(await self.dut.lowpass_ema_alpha2.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + + + + # register write checks + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.lowpass_ema_alpha2.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.lowpass_ema_alpha2.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + register_write_callback.assert_called_once_with(value=random_value) + register_read_callback.assert_not_called() + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.lowpass_ema_alpha2.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + self.assertEqual(await self.dut.lowpass_ema_alpha2.read(), random_value) + + + + # test access operations (read and/or write) to register: + # msk_top_regs.rx_power + with self.subTest(msg='register: msk_top_regs.rx_power'): + sim_register = self.sim.register_by_full_name('msk_top_regs.rx_power') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + register_read_callback = Mock() + register_write_callback = Mock() + + # register read checks + # update the value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.rx_power.read(), random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.rx_power.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.value = random_value + sim_register.read_callback = None + sim_register.write_callback = None + self.assertEqual(await self.dut.rx_power.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + + + + + + + + async def test_field_read_and_write(self) -> None: + """ + Walk the register map and check every field can be read and written to correctly + """ + random_field_value: Union[int, SystemRDLEnum] + # test access operations (read and/or write) to register: + # msk_top_regs.Hash_ID_Low.hash_id_lo + with self.subTest(msg='field: msk_top_regs.Hash_ID_Low.hash_id_lo'): + sim_register = self.sim.register_by_full_name('msk_top_regs.Hash_ID_Low') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.Hash_ID_Low.hash_id_lo') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.Hash_ID_Low.hash_id_lo.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0x0) | (random_field_value << 0)) + + self.assertEqual(await self.dut.Hash_ID_Low.hash_id_lo.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.Hash_ID_Low.hash_id_lo.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.Hash_ID_Low.hash_id_lo.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + + + # test access operations (read and/or write) to register: + # msk_top_regs.Hash_ID_High.hash_id_hi + with self.subTest(msg='field: msk_top_regs.Hash_ID_High.hash_id_hi'): + sim_register = self.sim.register_by_full_name('msk_top_regs.Hash_ID_High') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.Hash_ID_High.hash_id_hi') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.Hash_ID_High.hash_id_hi.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0x0) | (random_field_value << 0)) + + self.assertEqual(await self.dut.Hash_ID_High.hash_id_hi.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.Hash_ID_High.hash_id_hi.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.Hash_ID_High.hash_id_hi.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + + + # test access operations (read and/or write) to register: + # msk_top_regs.MSK_Init.txrxinit + with self.subTest(msg='field: msk_top_regs.MSK_Init.txrxinit'): + sim_register = self.sim.register_by_full_name('msk_top_regs.MSK_Init') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.MSK_Init.txrxinit') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x1) >> 0 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + self.assertEqual(await self.dut.MSK_Init.txrxinit.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0x1+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0xFFFFFFFE) | (random_field_value << 0)) + + self.assertEqual(await self.dut.MSK_Init.txrxinit.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x1) >> 0 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.MSK_Init.txrxinit.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x1) >> 0 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + self.assertEqual(await self.dut.MSK_Init.txrxinit.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value + + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.MSK_Init.txrxinit.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFFE) | (0x1 & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.MSK_Init.txrxinit.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFFE) | (0x1 & (random_field_value << 0))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0xFFFFFFFE) | (0x1 & (random_field_value << 0))) + field_write_callback.assert_called_once_with(value=random_field_value) + + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.write_callback = None + sim_field.write_callback = None + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.MSK_Init.txrxinit.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFFE) | (0x1 & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # test access operations (read and/or write) to register: + # msk_top_regs.MSK_Init.txinit + with self.subTest(msg='field: msk_top_regs.MSK_Init.txinit'): + sim_register = self.sim.register_by_full_name('msk_top_regs.MSK_Init') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.MSK_Init.txinit') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x2) >> 1 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + self.assertEqual(await self.dut.MSK_Init.txinit.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0x1+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0xFFFFFFFD) | (random_field_value << 1)) + + self.assertEqual(await self.dut.MSK_Init.txinit.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x2) >> 1 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.MSK_Init.txinit.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x2) >> 1 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + self.assertEqual(await self.dut.MSK_Init.txinit.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value + + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.MSK_Init.txinit.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFFD) | (0x2 & (random_field_value << 1))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.MSK_Init.txinit.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFFD) | (0x2 & (random_field_value << 1))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0xFFFFFFFD) | (0x2 & (random_field_value << 1))) + field_write_callback.assert_called_once_with(value=random_field_value) + + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.write_callback = None + sim_field.write_callback = None + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.MSK_Init.txinit.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFFD) | (0x2 & (random_field_value << 1))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # test access operations (read and/or write) to register: + # msk_top_regs.MSK_Init.rxinit + with self.subTest(msg='field: msk_top_regs.MSK_Init.rxinit'): + sim_register = self.sim.register_by_full_name('msk_top_regs.MSK_Init') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.MSK_Init.rxinit') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x4) >> 2 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + self.assertEqual(await self.dut.MSK_Init.rxinit.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0x1+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0xFFFFFFFB) | (random_field_value << 2)) + + self.assertEqual(await self.dut.MSK_Init.rxinit.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x4) >> 2 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.MSK_Init.rxinit.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x4) >> 2 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + self.assertEqual(await self.dut.MSK_Init.rxinit.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value + + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.MSK_Init.rxinit.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFFB) | (0x4 & (random_field_value << 2))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.MSK_Init.rxinit.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFFB) | (0x4 & (random_field_value << 2))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0xFFFFFFFB) | (0x4 & (random_field_value << 2))) + field_write_callback.assert_called_once_with(value=random_field_value) + + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.write_callback = None + sim_field.write_callback = None + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.MSK_Init.rxinit.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFFB) | (0x4 & (random_field_value << 2))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # test access operations (read and/or write) to register: + # msk_top_regs.MSK_Control.ptt + with self.subTest(msg='field: msk_top_regs.MSK_Control.ptt'): + sim_register = self.sim.register_by_full_name('msk_top_regs.MSK_Control') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.MSK_Control.ptt') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x1) >> 0 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + self.assertEqual(await self.dut.MSK_Control.ptt.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0x1+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0xFFFFFFFE) | (random_field_value << 0)) + + self.assertEqual(await self.dut.MSK_Control.ptt.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x1) >> 0 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.MSK_Control.ptt.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x1) >> 0 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + self.assertEqual(await self.dut.MSK_Control.ptt.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value + + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.MSK_Control.ptt.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFFE) | (0x1 & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.MSK_Control.ptt.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFFE) | (0x1 & (random_field_value << 0))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0xFFFFFFFE) | (0x1 & (random_field_value << 0))) + field_write_callback.assert_called_once_with(value=random_field_value) + + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.write_callback = None + sim_field.write_callback = None + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.MSK_Control.ptt.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFFE) | (0x1 & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # test access operations (read and/or write) to register: + # msk_top_regs.MSK_Control.loopback_ena + with self.subTest(msg='field: msk_top_regs.MSK_Control.loopback_ena'): + sim_register = self.sim.register_by_full_name('msk_top_regs.MSK_Control') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.MSK_Control.loopback_ena') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x2) >> 1 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + self.assertEqual(await self.dut.MSK_Control.loopback_ena.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0x1+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0xFFFFFFFD) | (random_field_value << 1)) + + self.assertEqual(await self.dut.MSK_Control.loopback_ena.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x2) >> 1 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.MSK_Control.loopback_ena.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x2) >> 1 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + self.assertEqual(await self.dut.MSK_Control.loopback_ena.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value + + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.MSK_Control.loopback_ena.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFFD) | (0x2 & (random_field_value << 1))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.MSK_Control.loopback_ena.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFFD) | (0x2 & (random_field_value << 1))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0xFFFFFFFD) | (0x2 & (random_field_value << 1))) + field_write_callback.assert_called_once_with(value=random_field_value) + + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.write_callback = None + sim_field.write_callback = None + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.MSK_Control.loopback_ena.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFFD) | (0x2 & (random_field_value << 1))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # test access operations (read and/or write) to register: + # msk_top_regs.MSK_Control.rx_invert + with self.subTest(msg='field: msk_top_regs.MSK_Control.rx_invert'): + sim_register = self.sim.register_by_full_name('msk_top_regs.MSK_Control') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.MSK_Control.rx_invert') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x4) >> 2 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + self.assertEqual(await self.dut.MSK_Control.rx_invert.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0x1+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0xFFFFFFFB) | (random_field_value << 2)) + + self.assertEqual(await self.dut.MSK_Control.rx_invert.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x4) >> 2 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.MSK_Control.rx_invert.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x4) >> 2 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + self.assertEqual(await self.dut.MSK_Control.rx_invert.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value + + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.MSK_Control.rx_invert.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFFB) | (0x4 & (random_field_value << 2))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.MSK_Control.rx_invert.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFFB) | (0x4 & (random_field_value << 2))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0xFFFFFFFB) | (0x4 & (random_field_value << 2))) + field_write_callback.assert_called_once_with(value=random_field_value) + + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.write_callback = None + sim_field.write_callback = None + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.MSK_Control.rx_invert.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFFB) | (0x4 & (random_field_value << 2))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # test access operations (read and/or write) to register: + # msk_top_regs.MSK_Control.clear_counts + with self.subTest(msg='field: msk_top_regs.MSK_Control.clear_counts'): + sim_register = self.sim.register_by_full_name('msk_top_regs.MSK_Control') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.MSK_Control.clear_counts') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x8) >> 3 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + self.assertEqual(await self.dut.MSK_Control.clear_counts.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0x1+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0xFFFFFFF7) | (random_field_value << 3)) + + self.assertEqual(await self.dut.MSK_Control.clear_counts.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x8) >> 3 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.MSK_Control.clear_counts.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x8) >> 3 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + self.assertEqual(await self.dut.MSK_Control.clear_counts.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value + + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.MSK_Control.clear_counts.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFF7) | (0x8 & (random_field_value << 3))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.MSK_Control.clear_counts.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFF7) | (0x8 & (random_field_value << 3))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0xFFFFFFF7) | (0x8 & (random_field_value << 3))) + field_write_callback.assert_called_once_with(value=random_field_value) + + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.write_callback = None + sim_field.write_callback = None + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.MSK_Control.clear_counts.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFF7) | (0x8 & (random_field_value << 3))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # test access operations (read and/or write) to register: + # msk_top_regs.MSK_Control.diff_encoder_loopback + with self.subTest(msg='field: msk_top_regs.MSK_Control.diff_encoder_loopback'): + sim_register = self.sim.register_by_full_name('msk_top_regs.MSK_Control') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.MSK_Control.diff_encoder_loopback') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x10) >> 4 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + self.assertEqual(await self.dut.MSK_Control.diff_encoder_loopback.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0x1+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0xFFFFFFEF) | (random_field_value << 4)) + + self.assertEqual(await self.dut.MSK_Control.diff_encoder_loopback.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x10) >> 4 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.MSK_Control.diff_encoder_loopback.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x10) >> 4 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + self.assertEqual(await self.dut.MSK_Control.diff_encoder_loopback.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value + + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.MSK_Control.diff_encoder_loopback.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFEF) | (0x10 & (random_field_value << 4))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.MSK_Control.diff_encoder_loopback.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFEF) | (0x10 & (random_field_value << 4))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0xFFFFFFEF) | (0x10 & (random_field_value << 4))) + field_write_callback.assert_called_once_with(value=random_field_value) + + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.write_callback = None + sim_field.write_callback = None + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.MSK_Control.diff_encoder_loopback.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFEF) | (0x10 & (random_field_value << 4))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # test access operations (read and/or write) to register: + # msk_top_regs.MSK_Status.demod_sync_lock + with self.subTest(msg='field: msk_top_regs.MSK_Status.demod_sync_lock'): + sim_register = self.sim.register_by_full_name('msk_top_regs.MSK_Status') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.MSK_Status.demod_sync_lock') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x1) >> 0 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + self.assertEqual(await self.dut.MSK_Status.demod_sync_lock.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0x1+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0xFFFFFFFE) | (random_field_value << 0)) + + self.assertEqual(await self.dut.MSK_Status.demod_sync_lock.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x1) >> 0 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.MSK_Status.demod_sync_lock.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x1) >> 0 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + self.assertEqual(await self.dut.MSK_Status.demod_sync_lock.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + + + # test access operations (read and/or write) to register: + # msk_top_regs.MSK_Status.tx_enable + with self.subTest(msg='field: msk_top_regs.MSK_Status.tx_enable'): + sim_register = self.sim.register_by_full_name('msk_top_regs.MSK_Status') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.MSK_Status.tx_enable') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x2) >> 1 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + self.assertEqual(await self.dut.MSK_Status.tx_enable.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0x1+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0xFFFFFFFD) | (random_field_value << 1)) + + self.assertEqual(await self.dut.MSK_Status.tx_enable.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x2) >> 1 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.MSK_Status.tx_enable.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x2) >> 1 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + self.assertEqual(await self.dut.MSK_Status.tx_enable.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + + + # test access operations (read and/or write) to register: + # msk_top_regs.MSK_Status.rx_enable + with self.subTest(msg='field: msk_top_regs.MSK_Status.rx_enable'): + sim_register = self.sim.register_by_full_name('msk_top_regs.MSK_Status') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.MSK_Status.rx_enable') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x4) >> 2 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + self.assertEqual(await self.dut.MSK_Status.rx_enable.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0x1+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0xFFFFFFFB) | (random_field_value << 2)) + + self.assertEqual(await self.dut.MSK_Status.rx_enable.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x4) >> 2 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.MSK_Status.rx_enable.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x4) >> 2 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + self.assertEqual(await self.dut.MSK_Status.rx_enable.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + + + # test access operations (read and/or write) to register: + # msk_top_regs.MSK_Status.tx_axis_valid + with self.subTest(msg='field: msk_top_regs.MSK_Status.tx_axis_valid'): + sim_register = self.sim.register_by_full_name('msk_top_regs.MSK_Status') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.MSK_Status.tx_axis_valid') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x8) >> 3 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + self.assertEqual(await self.dut.MSK_Status.tx_axis_valid.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0x1+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0xFFFFFFF7) | (random_field_value << 3)) + + self.assertEqual(await self.dut.MSK_Status.tx_axis_valid.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x8) >> 3 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.MSK_Status.tx_axis_valid.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x8) >> 3 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + self.assertEqual(await self.dut.MSK_Status.tx_axis_valid.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + + + # test access operations (read and/or write) to register: + # msk_top_regs.Tx_Bit_Count.tx_bit_counter + with self.subTest(msg='field: msk_top_regs.Tx_Bit_Count.tx_bit_counter'): + sim_register = self.sim.register_by_full_name('msk_top_regs.Tx_Bit_Count') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.Tx_Bit_Count.tx_bit_counter') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.Tx_Bit_Count.tx_bit_counter.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0x0) | (random_field_value << 0)) + + self.assertEqual(await self.dut.Tx_Bit_Count.tx_bit_counter.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.Tx_Bit_Count.tx_bit_counter.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.Tx_Bit_Count.tx_bit_counter.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + + + # test access operations (read and/or write) to register: + # msk_top_regs.Tx_Enable_Count.tx_ena_counter + with self.subTest(msg='field: msk_top_regs.Tx_Enable_Count.tx_ena_counter'): + sim_register = self.sim.register_by_full_name('msk_top_regs.Tx_Enable_Count') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.Tx_Enable_Count.tx_ena_counter') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.Tx_Enable_Count.tx_ena_counter.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0x0) | (random_field_value << 0)) + + self.assertEqual(await self.dut.Tx_Enable_Count.tx_ena_counter.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.Tx_Enable_Count.tx_ena_counter.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.Tx_Enable_Count.tx_ena_counter.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + + + # test access operations (read and/or write) to register: + # msk_top_regs.Fb_FreqWord.config_data + with self.subTest(msg='field: msk_top_regs.Fb_FreqWord.config_data'): + sim_register = self.sim.register_by_full_name('msk_top_regs.Fb_FreqWord') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.Fb_FreqWord.config_data') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.Fb_FreqWord.config_data.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0x0) | (random_field_value << 0)) + + self.assertEqual(await self.dut.Fb_FreqWord.config_data.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.Fb_FreqWord.config_data.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.Fb_FreqWord.config_data.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value + + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.Fb_FreqWord.config_data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.Fb_FreqWord.config_data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + field_write_callback.assert_called_once_with(value=random_field_value) + + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.write_callback = None + sim_field.write_callback = None + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.Fb_FreqWord.config_data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # test access operations (read and/or write) to register: + # msk_top_regs.TX_F1_FreqWord.config_data + with self.subTest(msg='field: msk_top_regs.TX_F1_FreqWord.config_data'): + sim_register = self.sim.register_by_full_name('msk_top_regs.TX_F1_FreqWord') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.TX_F1_FreqWord.config_data') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.TX_F1_FreqWord.config_data.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0x0) | (random_field_value << 0)) + + self.assertEqual(await self.dut.TX_F1_FreqWord.config_data.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.TX_F1_FreqWord.config_data.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.TX_F1_FreqWord.config_data.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value + + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.TX_F1_FreqWord.config_data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.TX_F1_FreqWord.config_data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + field_write_callback.assert_called_once_with(value=random_field_value) + + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.write_callback = None + sim_field.write_callback = None + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.TX_F1_FreqWord.config_data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # test access operations (read and/or write) to register: + # msk_top_regs.TX_F2_FreqWord.config_data + with self.subTest(msg='field: msk_top_regs.TX_F2_FreqWord.config_data'): + sim_register = self.sim.register_by_full_name('msk_top_regs.TX_F2_FreqWord') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.TX_F2_FreqWord.config_data') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.TX_F2_FreqWord.config_data.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0x0) | (random_field_value << 0)) + + self.assertEqual(await self.dut.TX_F2_FreqWord.config_data.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.TX_F2_FreqWord.config_data.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.TX_F2_FreqWord.config_data.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value + + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.TX_F2_FreqWord.config_data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.TX_F2_FreqWord.config_data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + field_write_callback.assert_called_once_with(value=random_field_value) + + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.write_callback = None + sim_field.write_callback = None + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.TX_F2_FreqWord.config_data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # test access operations (read and/or write) to register: + # msk_top_regs.RX_F1_FreqWord.config_data + with self.subTest(msg='field: msk_top_regs.RX_F1_FreqWord.config_data'): + sim_register = self.sim.register_by_full_name('msk_top_regs.RX_F1_FreqWord') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.RX_F1_FreqWord.config_data') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.RX_F1_FreqWord.config_data.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0x0) | (random_field_value << 0)) + + self.assertEqual(await self.dut.RX_F1_FreqWord.config_data.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.RX_F1_FreqWord.config_data.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.RX_F1_FreqWord.config_data.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value + + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.RX_F1_FreqWord.config_data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.RX_F1_FreqWord.config_data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + field_write_callback.assert_called_once_with(value=random_field_value) + + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.write_callback = None + sim_field.write_callback = None + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.RX_F1_FreqWord.config_data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # test access operations (read and/or write) to register: + # msk_top_regs.RX_F2_FreqWord.config_data + with self.subTest(msg='field: msk_top_regs.RX_F2_FreqWord.config_data'): + sim_register = self.sim.register_by_full_name('msk_top_regs.RX_F2_FreqWord') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.RX_F2_FreqWord.config_data') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.RX_F2_FreqWord.config_data.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0x0) | (random_field_value << 0)) + + self.assertEqual(await self.dut.RX_F2_FreqWord.config_data.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.RX_F2_FreqWord.config_data.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.RX_F2_FreqWord.config_data.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value + + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.RX_F2_FreqWord.config_data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.RX_F2_FreqWord.config_data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + field_write_callback.assert_called_once_with(value=random_field_value) + + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.write_callback = None + sim_field.write_callback = None + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.RX_F2_FreqWord.config_data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # test access operations (read and/or write) to register: + # msk_top_regs.LPF_Config_0.lpf_freeze + with self.subTest(msg='field: msk_top_regs.LPF_Config_0.lpf_freeze'): + sim_register = self.sim.register_by_full_name('msk_top_regs.LPF_Config_0') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.LPF_Config_0.lpf_freeze') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x1) >> 0 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + self.assertEqual(await self.dut.LPF_Config_0.lpf_freeze.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0x1+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0xFFFFFFFE) | (random_field_value << 0)) + + self.assertEqual(await self.dut.LPF_Config_0.lpf_freeze.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x1) >> 0 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.LPF_Config_0.lpf_freeze.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x1) >> 0 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + self.assertEqual(await self.dut.LPF_Config_0.lpf_freeze.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value + + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.LPF_Config_0.lpf_freeze.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFFE) | (0x1 & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.LPF_Config_0.lpf_freeze.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFFE) | (0x1 & (random_field_value << 0))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0xFFFFFFFE) | (0x1 & (random_field_value << 0))) + field_write_callback.assert_called_once_with(value=random_field_value) + + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.write_callback = None + sim_field.write_callback = None + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.LPF_Config_0.lpf_freeze.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFFE) | (0x1 & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # test access operations (read and/or write) to register: + # msk_top_regs.LPF_Config_0.lpf_zero + with self.subTest(msg='field: msk_top_regs.LPF_Config_0.lpf_zero'): + sim_register = self.sim.register_by_full_name('msk_top_regs.LPF_Config_0') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.LPF_Config_0.lpf_zero') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x2) >> 1 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + self.assertEqual(await self.dut.LPF_Config_0.lpf_zero.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0x1+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0xFFFFFFFD) | (random_field_value << 1)) + + self.assertEqual(await self.dut.LPF_Config_0.lpf_zero.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x2) >> 1 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.LPF_Config_0.lpf_zero.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x2) >> 1 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + self.assertEqual(await self.dut.LPF_Config_0.lpf_zero.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value + + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.LPF_Config_0.lpf_zero.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFFD) | (0x2 & (random_field_value << 1))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.LPF_Config_0.lpf_zero.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFFD) | (0x2 & (random_field_value << 1))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0xFFFFFFFD) | (0x2 & (random_field_value << 1))) + field_write_callback.assert_called_once_with(value=random_field_value) + + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.write_callback = None + sim_field.write_callback = None + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.LPF_Config_0.lpf_zero.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFFD) | (0x2 & (random_field_value << 1))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # test access operations (read and/or write) to register: + # msk_top_regs.LPF_Config_0.prbs_reserved + with self.subTest(msg='field: msk_top_regs.LPF_Config_0.prbs_reserved'): + sim_register = self.sim.register_by_full_name('msk_top_regs.LPF_Config_0') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.LPF_Config_0.prbs_reserved') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFC) >> 2 + + + sim_register.value = random_value + self.assertEqual(await self.dut.LPF_Config_0.prbs_reserved.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0x3F+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0xFFFFFF03) | (random_field_value << 2)) + + self.assertEqual(await self.dut.LPF_Config_0.prbs_reserved.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFC) >> 2 + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.LPF_Config_0.prbs_reserved.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFC) >> 2 + + + sim_register.value = random_value + self.assertEqual(await self.dut.LPF_Config_0.prbs_reserved.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value + + random_field_value = random.randrange(0, 0x3F+1) + + await self.dut.LPF_Config_0.prbs_reserved.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFF03) | (0xFC & (random_field_value << 2))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0x3F+1) + + await self.dut.LPF_Config_0.prbs_reserved.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFF03) | (0xFC & (random_field_value << 2))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0xFFFFFF03) | (0xFC & (random_field_value << 2))) + field_write_callback.assert_called_once_with(value=random_field_value) + + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.write_callback = None + sim_field.write_callback = None + random_field_value = random.randrange(0, 0x3F+1) + + await self.dut.LPF_Config_0.prbs_reserved.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFF03) | (0xFC & (random_field_value << 2))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # test access operations (read and/or write) to register: + # msk_top_regs.LPF_Config_0.lpf_alpha + with self.subTest(msg='field: msk_top_regs.LPF_Config_0.lpf_alpha'): + sim_register = self.sim.register_by_full_name('msk_top_regs.LPF_Config_0') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.LPF_Config_0.lpf_alpha') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFF00) >> 8 + + + sim_register.value = random_value + self.assertEqual(await self.dut.LPF_Config_0.lpf_alpha.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0xFFFFFF+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0xFF) | (random_field_value << 8)) + + self.assertEqual(await self.dut.LPF_Config_0.lpf_alpha.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFF00) >> 8 + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.LPF_Config_0.lpf_alpha.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFF00) >> 8 + + + sim_register.value = random_value + self.assertEqual(await self.dut.LPF_Config_0.lpf_alpha.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value + + random_field_value = random.randrange(0, 0xFFFFFF+1) + + await self.dut.LPF_Config_0.lpf_alpha.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFF) | (0xFFFFFF00 & (random_field_value << 8))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0xFFFFFF+1) + + await self.dut.LPF_Config_0.lpf_alpha.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFF) | (0xFFFFFF00 & (random_field_value << 8))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0xFF) | (0xFFFFFF00 & (random_field_value << 8))) + field_write_callback.assert_called_once_with(value=random_field_value) + + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.write_callback = None + sim_field.write_callback = None + random_field_value = random.randrange(0, 0xFFFFFF+1) + + await self.dut.LPF_Config_0.lpf_alpha.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFF) | (0xFFFFFF00 & (random_field_value << 8))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # test access operations (read and/or write) to register: + # msk_top_regs.LPF_Config_1.i_gain + with self.subTest(msg='field: msk_top_regs.LPF_Config_1.i_gain'): + sim_register = self.sim.register_by_full_name('msk_top_regs.LPF_Config_1') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.LPF_Config_1.i_gain') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.LPF_Config_1.i_gain.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0xFFFFFF+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0xFF000000) | (random_field_value << 0)) + + self.assertEqual(await self.dut.LPF_Config_1.i_gain.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFF) >> 0 + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.LPF_Config_1.i_gain.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.LPF_Config_1.i_gain.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value + + random_field_value = random.randrange(0, 0xFFFFFF+1) + + await self.dut.LPF_Config_1.i_gain.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFF000000) | (0xFFFFFF & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0xFFFFFF+1) + + await self.dut.LPF_Config_1.i_gain.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFF000000) | (0xFFFFFF & (random_field_value << 0))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0xFF000000) | (0xFFFFFF & (random_field_value << 0))) + field_write_callback.assert_called_once_with(value=random_field_value) + + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.write_callback = None + sim_field.write_callback = None + random_field_value = random.randrange(0, 0xFFFFFF+1) + + await self.dut.LPF_Config_1.i_gain.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFF000000) | (0xFFFFFF & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # test access operations (read and/or write) to register: + # msk_top_regs.LPF_Config_1.i_shift + with self.subTest(msg='field: msk_top_regs.LPF_Config_1.i_shift'): + sim_register = self.sim.register_by_full_name('msk_top_regs.LPF_Config_1') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.LPF_Config_1.i_shift') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFF000000) >> 24 + + + sim_register.value = random_value + self.assertEqual(await self.dut.LPF_Config_1.i_shift.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0xFF+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0xFFFFFF) | (random_field_value << 24)) + + self.assertEqual(await self.dut.LPF_Config_1.i_shift.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFF000000) >> 24 + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.LPF_Config_1.i_shift.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFF000000) >> 24 + + + sim_register.value = random_value + self.assertEqual(await self.dut.LPF_Config_1.i_shift.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value + + random_field_value = random.randrange(0, 0xFF+1) + + await self.dut.LPF_Config_1.i_shift.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFF) | (0xFF000000 & (random_field_value << 24))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0xFF+1) + + await self.dut.LPF_Config_1.i_shift.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFF) | (0xFF000000 & (random_field_value << 24))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0xFFFFFF) | (0xFF000000 & (random_field_value << 24))) + field_write_callback.assert_called_once_with(value=random_field_value) + + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.write_callback = None + sim_field.write_callback = None + random_field_value = random.randrange(0, 0xFF+1) + + await self.dut.LPF_Config_1.i_shift.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFF) | (0xFF000000 & (random_field_value << 24))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # test access operations (read and/or write) to register: + # msk_top_regs.Tx_Data_Width.data_width + with self.subTest(msg='field: msk_top_regs.Tx_Data_Width.data_width'): + sim_register = self.sim.register_by_full_name('msk_top_regs.Tx_Data_Width') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.Tx_Data_Width.data_width') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.Tx_Data_Width.data_width.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0xFF+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0xFFFFFF00) | (random_field_value << 0)) + + self.assertEqual(await self.dut.Tx_Data_Width.data_width.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFF) >> 0 + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.Tx_Data_Width.data_width.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.Tx_Data_Width.data_width.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value + + random_field_value = random.randrange(0, 0xFF+1) + + await self.dut.Tx_Data_Width.data_width.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFF00) | (0xFF & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0xFF+1) + + await self.dut.Tx_Data_Width.data_width.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFF00) | (0xFF & (random_field_value << 0))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0xFFFFFF00) | (0xFF & (random_field_value << 0))) + field_write_callback.assert_called_once_with(value=random_field_value) + + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.write_callback = None + sim_field.write_callback = None + random_field_value = random.randrange(0, 0xFF+1) + + await self.dut.Tx_Data_Width.data_width.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFF00) | (0xFF & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # test access operations (read and/or write) to register: + # msk_top_regs.Rx_Data_Width.data_width + with self.subTest(msg='field: msk_top_regs.Rx_Data_Width.data_width'): + sim_register = self.sim.register_by_full_name('msk_top_regs.Rx_Data_Width') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.Rx_Data_Width.data_width') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.Rx_Data_Width.data_width.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0xFF+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0xFFFFFF00) | (random_field_value << 0)) + + self.assertEqual(await self.dut.Rx_Data_Width.data_width.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFF) >> 0 + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.Rx_Data_Width.data_width.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.Rx_Data_Width.data_width.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value + + random_field_value = random.randrange(0, 0xFF+1) + + await self.dut.Rx_Data_Width.data_width.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFF00) | (0xFF & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0xFF+1) + + await self.dut.Rx_Data_Width.data_width.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFF00) | (0xFF & (random_field_value << 0))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0xFFFFFF00) | (0xFF & (random_field_value << 0))) + field_write_callback.assert_called_once_with(value=random_field_value) + + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.write_callback = None + sim_field.write_callback = None + random_field_value = random.randrange(0, 0xFF+1) + + await self.dut.Rx_Data_Width.data_width.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFF00) | (0xFF & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # test access operations (read and/or write) to register: + # msk_top_regs.PRBS_Control.prbs_sel + with self.subTest(msg='field: msk_top_regs.PRBS_Control.prbs_sel'): + sim_register = self.sim.register_by_full_name('msk_top_regs.PRBS_Control') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.PRBS_Control.prbs_sel') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x1) >> 0 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + self.assertEqual(await self.dut.PRBS_Control.prbs_sel.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0x1+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0xFFFFFFFE) | (random_field_value << 0)) + + self.assertEqual(await self.dut.PRBS_Control.prbs_sel.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x1) >> 0 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.PRBS_Control.prbs_sel.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x1) >> 0 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + self.assertEqual(await self.dut.PRBS_Control.prbs_sel.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value + + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.PRBS_Control.prbs_sel.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFFE) | (0x1 & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.PRBS_Control.prbs_sel.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFFE) | (0x1 & (random_field_value << 0))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0xFFFFFFFE) | (0x1 & (random_field_value << 0))) + field_write_callback.assert_called_once_with(value=random_field_value) + + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.write_callback = None + sim_field.write_callback = None + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.PRBS_Control.prbs_sel.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFFE) | (0x1 & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # test access operations (read and/or write) to register: + # msk_top_regs.PRBS_Control.prbs_error_insert + with self.subTest(msg='field: msk_top_regs.PRBS_Control.prbs_error_insert'): + sim_register = self.sim.register_by_full_name('msk_top_regs.PRBS_Control') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.PRBS_Control.prbs_error_insert') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + + + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value + + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.PRBS_Control.prbs_error_insert.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFFD) | (0x2 & (random_field_value << 1))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.PRBS_Control.prbs_error_insert.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFFD) | (0x2 & (random_field_value << 1))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0xFFFFFFFD) | (0x2 & (random_field_value << 1))) + field_write_callback.assert_called_once_with(value=random_field_value) + + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.write_callback = None + sim_field.write_callback = None + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.PRBS_Control.prbs_error_insert.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFFD) | (0x2 & (random_field_value << 1))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # test access operations (read and/or write) to register: + # msk_top_regs.PRBS_Control.prbs_clear + with self.subTest(msg='field: msk_top_regs.PRBS_Control.prbs_clear'): + sim_register = self.sim.register_by_full_name('msk_top_regs.PRBS_Control') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.PRBS_Control.prbs_clear') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + + + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value + + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.PRBS_Control.prbs_clear.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFFB) | (0x4 & (random_field_value << 2))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.PRBS_Control.prbs_clear.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFFB) | (0x4 & (random_field_value << 2))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0xFFFFFFFB) | (0x4 & (random_field_value << 2))) + field_write_callback.assert_called_once_with(value=random_field_value) + + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.write_callback = None + sim_field.write_callback = None + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.PRBS_Control.prbs_clear.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFFB) | (0x4 & (random_field_value << 2))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # test access operations (read and/or write) to register: + # msk_top_regs.PRBS_Control.prbs_manual_sync + with self.subTest(msg='field: msk_top_regs.PRBS_Control.prbs_manual_sync'): + sim_register = self.sim.register_by_full_name('msk_top_regs.PRBS_Control') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.PRBS_Control.prbs_manual_sync') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + + + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value + + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.PRBS_Control.prbs_manual_sync.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFF7) | (0x8 & (random_field_value << 3))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.PRBS_Control.prbs_manual_sync.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFF7) | (0x8 & (random_field_value << 3))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0xFFFFFFF7) | (0x8 & (random_field_value << 3))) + field_write_callback.assert_called_once_with(value=random_field_value) + + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.write_callback = None + sim_field.write_callback = None + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.PRBS_Control.prbs_manual_sync.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFF7) | (0x8 & (random_field_value << 3))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # test access operations (read and/or write) to register: + # msk_top_regs.PRBS_Control.prbs_reserved + with self.subTest(msg='field: msk_top_regs.PRBS_Control.prbs_reserved'): + sim_register = self.sim.register_by_full_name('msk_top_regs.PRBS_Control') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.PRBS_Control.prbs_reserved') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFF0) >> 4 + + + sim_register.value = random_value + self.assertEqual(await self.dut.PRBS_Control.prbs_reserved.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0xFFF+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0xFFFF000F) | (random_field_value << 4)) + + self.assertEqual(await self.dut.PRBS_Control.prbs_reserved.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFF0) >> 4 + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.PRBS_Control.prbs_reserved.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFF0) >> 4 + + + sim_register.value = random_value + self.assertEqual(await self.dut.PRBS_Control.prbs_reserved.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value + + random_field_value = random.randrange(0, 0xFFF+1) + + await self.dut.PRBS_Control.prbs_reserved.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFF000F) | (0xFFF0 & (random_field_value << 4))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0xFFF+1) + + await self.dut.PRBS_Control.prbs_reserved.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFF000F) | (0xFFF0 & (random_field_value << 4))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0xFFFF000F) | (0xFFF0 & (random_field_value << 4))) + field_write_callback.assert_called_once_with(value=random_field_value) + + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.write_callback = None + sim_field.write_callback = None + random_field_value = random.randrange(0, 0xFFF+1) + + await self.dut.PRBS_Control.prbs_reserved.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFF000F) | (0xFFF0 & (random_field_value << 4))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # test access operations (read and/or write) to register: + # msk_top_regs.PRBS_Control.prbs_sync_threshold + with self.subTest(msg='field: msk_top_regs.PRBS_Control.prbs_sync_threshold'): + sim_register = self.sim.register_by_full_name('msk_top_regs.PRBS_Control') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.PRBS_Control.prbs_sync_threshold') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFF0000) >> 16 + + + sim_register.value = random_value + self.assertEqual(await self.dut.PRBS_Control.prbs_sync_threshold.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0xFFFF+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0xFFFF) | (random_field_value << 16)) + + self.assertEqual(await self.dut.PRBS_Control.prbs_sync_threshold.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFF0000) >> 16 + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.PRBS_Control.prbs_sync_threshold.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFF0000) >> 16 + + + sim_register.value = random_value + self.assertEqual(await self.dut.PRBS_Control.prbs_sync_threshold.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value + + random_field_value = random.randrange(0, 0xFFFF+1) + + await self.dut.PRBS_Control.prbs_sync_threshold.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFF) | (0xFFFF0000 & (random_field_value << 16))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0xFFFF+1) + + await self.dut.PRBS_Control.prbs_sync_threshold.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFF) | (0xFFFF0000 & (random_field_value << 16))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0xFFFF) | (0xFFFF0000 & (random_field_value << 16))) + field_write_callback.assert_called_once_with(value=random_field_value) + + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.write_callback = None + sim_field.write_callback = None + random_field_value = random.randrange(0, 0xFFFF+1) + + await self.dut.PRBS_Control.prbs_sync_threshold.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFF) | (0xFFFF0000 & (random_field_value << 16))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # test access operations (read and/or write) to register: + # msk_top_regs.PRBS_Initial_State.config_data + with self.subTest(msg='field: msk_top_regs.PRBS_Initial_State.config_data'): + sim_register = self.sim.register_by_full_name('msk_top_regs.PRBS_Initial_State') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.PRBS_Initial_State.config_data') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.PRBS_Initial_State.config_data.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0x0) | (random_field_value << 0)) + + self.assertEqual(await self.dut.PRBS_Initial_State.config_data.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.PRBS_Initial_State.config_data.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.PRBS_Initial_State.config_data.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value + + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.PRBS_Initial_State.config_data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.PRBS_Initial_State.config_data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + field_write_callback.assert_called_once_with(value=random_field_value) + + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.write_callback = None + sim_field.write_callback = None + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.PRBS_Initial_State.config_data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # test access operations (read and/or write) to register: + # msk_top_regs.PRBS_Polynomial.config_data + with self.subTest(msg='field: msk_top_regs.PRBS_Polynomial.config_data'): + sim_register = self.sim.register_by_full_name('msk_top_regs.PRBS_Polynomial') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.PRBS_Polynomial.config_data') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.PRBS_Polynomial.config_data.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0x0) | (random_field_value << 0)) + + self.assertEqual(await self.dut.PRBS_Polynomial.config_data.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.PRBS_Polynomial.config_data.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.PRBS_Polynomial.config_data.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value + + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.PRBS_Polynomial.config_data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.PRBS_Polynomial.config_data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + field_write_callback.assert_called_once_with(value=random_field_value) + + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.write_callback = None + sim_field.write_callback = None + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.PRBS_Polynomial.config_data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # test access operations (read and/or write) to register: + # msk_top_regs.PRBS_Error_Mask.config_data + with self.subTest(msg='field: msk_top_regs.PRBS_Error_Mask.config_data'): + sim_register = self.sim.register_by_full_name('msk_top_regs.PRBS_Error_Mask') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.PRBS_Error_Mask.config_data') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.PRBS_Error_Mask.config_data.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0x0) | (random_field_value << 0)) + + self.assertEqual(await self.dut.PRBS_Error_Mask.config_data.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.PRBS_Error_Mask.config_data.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.PRBS_Error_Mask.config_data.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value + + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.PRBS_Error_Mask.config_data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.PRBS_Error_Mask.config_data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + field_write_callback.assert_called_once_with(value=random_field_value) + + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.write_callback = None + sim_field.write_callback = None + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.PRBS_Error_Mask.config_data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # test access operations (read and/or write) to register: + # msk_top_regs.PRBS_Bit_Count.status_data + with self.subTest(msg='field: msk_top_regs.PRBS_Bit_Count.status_data'): + sim_register = self.sim.register_by_full_name('msk_top_regs.PRBS_Bit_Count') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.PRBS_Bit_Count.status_data') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.PRBS_Bit_Count.status_data.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0x0) | (random_field_value << 0)) + + self.assertEqual(await self.dut.PRBS_Bit_Count.status_data.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.PRBS_Bit_Count.status_data.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.PRBS_Bit_Count.status_data.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + + + # test access operations (read and/or write) to register: + # msk_top_regs.PRBS_Error_Count.status_data + with self.subTest(msg='field: msk_top_regs.PRBS_Error_Count.status_data'): + sim_register = self.sim.register_by_full_name('msk_top_regs.PRBS_Error_Count') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.PRBS_Error_Count.status_data') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.PRBS_Error_Count.status_data.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0x0) | (random_field_value << 0)) + + self.assertEqual(await self.dut.PRBS_Error_Count.status_data.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.PRBS_Error_Count.status_data.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.PRBS_Error_Count.status_data.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + + + # test access operations (read and/or write) to register: + # msk_top_regs.LPF_Accum_F1.status_data + with self.subTest(msg='field: msk_top_regs.LPF_Accum_F1.status_data'): + sim_register = self.sim.register_by_full_name('msk_top_regs.LPF_Accum_F1') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.LPF_Accum_F1.status_data') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.LPF_Accum_F1.status_data.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0x0) | (random_field_value << 0)) + + self.assertEqual(await self.dut.LPF_Accum_F1.status_data.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.LPF_Accum_F1.status_data.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.LPF_Accum_F1.status_data.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + + + # test access operations (read and/or write) to register: + # msk_top_regs.LPF_Accum_F2.status_data + with self.subTest(msg='field: msk_top_regs.LPF_Accum_F2.status_data'): + sim_register = self.sim.register_by_full_name('msk_top_regs.LPF_Accum_F2') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.LPF_Accum_F2.status_data') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.LPF_Accum_F2.status_data.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0x0) | (random_field_value << 0)) + + self.assertEqual(await self.dut.LPF_Accum_F2.status_data.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.LPF_Accum_F2.status_data.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.LPF_Accum_F2.status_data.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + + + # test access operations (read and/or write) to register: + # msk_top_regs.axis_xfer_count.xfer_count + with self.subTest(msg='field: msk_top_regs.axis_xfer_count.xfer_count'): + sim_register = self.sim.register_by_full_name('msk_top_regs.axis_xfer_count') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.axis_xfer_count.xfer_count') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.axis_xfer_count.xfer_count.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0x0) | (random_field_value << 0)) + + self.assertEqual(await self.dut.axis_xfer_count.xfer_count.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.axis_xfer_count.xfer_count.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.axis_xfer_count.xfer_count.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + + + # test access operations (read and/or write) to register: + # msk_top_regs.Rx_Sample_Discard.rx_sample_discard + with self.subTest(msg='field: msk_top_regs.Rx_Sample_Discard.rx_sample_discard'): + sim_register = self.sim.register_by_full_name('msk_top_regs.Rx_Sample_Discard') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.Rx_Sample_Discard.rx_sample_discard') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.Rx_Sample_Discard.rx_sample_discard.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0xFF+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0xFFFFFF00) | (random_field_value << 0)) + + self.assertEqual(await self.dut.Rx_Sample_Discard.rx_sample_discard.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFF) >> 0 + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.Rx_Sample_Discard.rx_sample_discard.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.Rx_Sample_Discard.rx_sample_discard.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value + + random_field_value = random.randrange(0, 0xFF+1) + + await self.dut.Rx_Sample_Discard.rx_sample_discard.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFF00) | (0xFF & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0xFF+1) + + await self.dut.Rx_Sample_Discard.rx_sample_discard.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFF00) | (0xFF & (random_field_value << 0))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0xFFFFFF00) | (0xFF & (random_field_value << 0))) + field_write_callback.assert_called_once_with(value=random_field_value) + + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.write_callback = None + sim_field.write_callback = None + random_field_value = random.randrange(0, 0xFF+1) + + await self.dut.Rx_Sample_Discard.rx_sample_discard.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFF00) | (0xFF & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # test access operations (read and/or write) to register: + # msk_top_regs.Rx_Sample_Discard.rx_nco_discard + with self.subTest(msg='field: msk_top_regs.Rx_Sample_Discard.rx_nco_discard'): + sim_register = self.sim.register_by_full_name('msk_top_regs.Rx_Sample_Discard') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.Rx_Sample_Discard.rx_nco_discard') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFF00) >> 8 + + + sim_register.value = random_value + self.assertEqual(await self.dut.Rx_Sample_Discard.rx_nco_discard.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0xFF+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0xFFFF00FF) | (random_field_value << 8)) + + self.assertEqual(await self.dut.Rx_Sample_Discard.rx_nco_discard.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFF00) >> 8 + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.Rx_Sample_Discard.rx_nco_discard.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFF00) >> 8 + + + sim_register.value = random_value + self.assertEqual(await self.dut.Rx_Sample_Discard.rx_nco_discard.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value + + random_field_value = random.randrange(0, 0xFF+1) + + await self.dut.Rx_Sample_Discard.rx_nco_discard.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFF00FF) | (0xFF00 & (random_field_value << 8))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0xFF+1) + + await self.dut.Rx_Sample_Discard.rx_nco_discard.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFF00FF) | (0xFF00 & (random_field_value << 8))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0xFFFF00FF) | (0xFF00 & (random_field_value << 8))) + field_write_callback.assert_called_once_with(value=random_field_value) + + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.write_callback = None + sim_field.write_callback = None + random_field_value = random.randrange(0, 0xFF+1) + + await self.dut.Rx_Sample_Discard.rx_nco_discard.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFF00FF) | (0xFF00 & (random_field_value << 8))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # test access operations (read and/or write) to register: + # msk_top_regs.LPF_Config_2.p_gain + with self.subTest(msg='field: msk_top_regs.LPF_Config_2.p_gain'): + sim_register = self.sim.register_by_full_name('msk_top_regs.LPF_Config_2') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.LPF_Config_2.p_gain') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.LPF_Config_2.p_gain.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0xFFFFFF+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0xFF000000) | (random_field_value << 0)) + + self.assertEqual(await self.dut.LPF_Config_2.p_gain.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFF) >> 0 + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.LPF_Config_2.p_gain.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.LPF_Config_2.p_gain.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value + + random_field_value = random.randrange(0, 0xFFFFFF+1) + + await self.dut.LPF_Config_2.p_gain.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFF000000) | (0xFFFFFF & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0xFFFFFF+1) + + await self.dut.LPF_Config_2.p_gain.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFF000000) | (0xFFFFFF & (random_field_value << 0))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0xFF000000) | (0xFFFFFF & (random_field_value << 0))) + field_write_callback.assert_called_once_with(value=random_field_value) + + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.write_callback = None + sim_field.write_callback = None + random_field_value = random.randrange(0, 0xFFFFFF+1) + + await self.dut.LPF_Config_2.p_gain.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFF000000) | (0xFFFFFF & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # test access operations (read and/or write) to register: + # msk_top_regs.LPF_Config_2.p_shift + with self.subTest(msg='field: msk_top_regs.LPF_Config_2.p_shift'): + sim_register = self.sim.register_by_full_name('msk_top_regs.LPF_Config_2') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.LPF_Config_2.p_shift') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFF000000) >> 24 + + + sim_register.value = random_value + self.assertEqual(await self.dut.LPF_Config_2.p_shift.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0xFF+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0xFFFFFF) | (random_field_value << 24)) + + self.assertEqual(await self.dut.LPF_Config_2.p_shift.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFF000000) >> 24 + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.LPF_Config_2.p_shift.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFF000000) >> 24 + + + sim_register.value = random_value + self.assertEqual(await self.dut.LPF_Config_2.p_shift.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value + + random_field_value = random.randrange(0, 0xFF+1) + + await self.dut.LPF_Config_2.p_shift.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFF) | (0xFF000000 & (random_field_value << 24))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0xFF+1) + + await self.dut.LPF_Config_2.p_shift.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFF) | (0xFF000000 & (random_field_value << 24))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0xFFFFFF) | (0xFF000000 & (random_field_value << 24))) + field_write_callback.assert_called_once_with(value=random_field_value) + + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.write_callback = None + sim_field.write_callback = None + random_field_value = random.randrange(0, 0xFF+1) + + await self.dut.LPF_Config_2.p_shift.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFF) | (0xFF000000 & (random_field_value << 24))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # test access operations (read and/or write) to register: + # msk_top_regs.f1_nco_adjust.data + with self.subTest(msg='field: msk_top_regs.f1_nco_adjust.data'): + sim_register = self.sim.register_by_full_name('msk_top_regs.f1_nco_adjust') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.f1_nco_adjust.data') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.f1_nco_adjust.data.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0x0) | (random_field_value << 0)) + + self.assertEqual(await self.dut.f1_nco_adjust.data.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.f1_nco_adjust.data.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.f1_nco_adjust.data.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + + + # test access operations (read and/or write) to register: + # msk_top_regs.f2_nco_adjust.data + with self.subTest(msg='field: msk_top_regs.f2_nco_adjust.data'): + sim_register = self.sim.register_by_full_name('msk_top_regs.f2_nco_adjust') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.f2_nco_adjust.data') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.f2_nco_adjust.data.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0x0) | (random_field_value << 0)) + + self.assertEqual(await self.dut.f2_nco_adjust.data.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.f2_nco_adjust.data.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.f2_nco_adjust.data.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + + + # test access operations (read and/or write) to register: + # msk_top_regs.f1_error.data + with self.subTest(msg='field: msk_top_regs.f1_error.data'): + sim_register = self.sim.register_by_full_name('msk_top_regs.f1_error') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.f1_error.data') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.f1_error.data.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0x0) | (random_field_value << 0)) + + self.assertEqual(await self.dut.f1_error.data.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.f1_error.data.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.f1_error.data.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + + + # test access operations (read and/or write) to register: + # msk_top_regs.f2_error.data + with self.subTest(msg='field: msk_top_regs.f2_error.data'): + sim_register = self.sim.register_by_full_name('msk_top_regs.f2_error') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.f2_error.data') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.f2_error.data.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0x0) | (random_field_value << 0)) + + self.assertEqual(await self.dut.f2_error.data.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.f2_error.data.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.f2_error.data.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + + + # test access operations (read and/or write) to register: + # msk_top_regs.Tx_Sync_Ctrl.tx_sync_ena + with self.subTest(msg='field: msk_top_regs.Tx_Sync_Ctrl.tx_sync_ena'): + sim_register = self.sim.register_by_full_name('msk_top_regs.Tx_Sync_Ctrl') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.Tx_Sync_Ctrl.tx_sync_ena') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x1) >> 0 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + self.assertEqual(await self.dut.Tx_Sync_Ctrl.tx_sync_ena.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0x1+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0xFFFFFFFE) | (random_field_value << 0)) + + self.assertEqual(await self.dut.Tx_Sync_Ctrl.tx_sync_ena.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x1) >> 0 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.Tx_Sync_Ctrl.tx_sync_ena.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x1) >> 0 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + self.assertEqual(await self.dut.Tx_Sync_Ctrl.tx_sync_ena.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value + + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.Tx_Sync_Ctrl.tx_sync_ena.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFFE) | (0x1 & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.Tx_Sync_Ctrl.tx_sync_ena.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFFE) | (0x1 & (random_field_value << 0))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0xFFFFFFFE) | (0x1 & (random_field_value << 0))) + field_write_callback.assert_called_once_with(value=random_field_value) + + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.write_callback = None + sim_field.write_callback = None + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.Tx_Sync_Ctrl.tx_sync_ena.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFFE) | (0x1 & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # test access operations (read and/or write) to register: + # msk_top_regs.Tx_Sync_Ctrl.tx_sync_force + with self.subTest(msg='field: msk_top_regs.Tx_Sync_Ctrl.tx_sync_force'): + sim_register = self.sim.register_by_full_name('msk_top_regs.Tx_Sync_Ctrl') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.Tx_Sync_Ctrl.tx_sync_force') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x2) >> 1 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + self.assertEqual(await self.dut.Tx_Sync_Ctrl.tx_sync_force.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0x1+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0xFFFFFFFD) | (random_field_value << 1)) + + self.assertEqual(await self.dut.Tx_Sync_Ctrl.tx_sync_force.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x2) >> 1 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.Tx_Sync_Ctrl.tx_sync_force.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x2) >> 1 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + self.assertEqual(await self.dut.Tx_Sync_Ctrl.tx_sync_force.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value + + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.Tx_Sync_Ctrl.tx_sync_force.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFFD) | (0x2 & (random_field_value << 1))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.Tx_Sync_Ctrl.tx_sync_force.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFFD) | (0x2 & (random_field_value << 1))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0xFFFFFFFD) | (0x2 & (random_field_value << 1))) + field_write_callback.assert_called_once_with(value=random_field_value) + + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.write_callback = None + sim_field.write_callback = None + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.Tx_Sync_Ctrl.tx_sync_force.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFFD) | (0x2 & (random_field_value << 1))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # test access operations (read and/or write) to register: + # msk_top_regs.Tx_Sync_Ctrl.tx_sync_f1 + with self.subTest(msg='field: msk_top_regs.Tx_Sync_Ctrl.tx_sync_f1'): + sim_register = self.sim.register_by_full_name('msk_top_regs.Tx_Sync_Ctrl') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.Tx_Sync_Ctrl.tx_sync_f1') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x4) >> 2 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + self.assertEqual(await self.dut.Tx_Sync_Ctrl.tx_sync_f1.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0x1+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0xFFFFFFFB) | (random_field_value << 2)) + + self.assertEqual(await self.dut.Tx_Sync_Ctrl.tx_sync_f1.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x4) >> 2 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.Tx_Sync_Ctrl.tx_sync_f1.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x4) >> 2 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + self.assertEqual(await self.dut.Tx_Sync_Ctrl.tx_sync_f1.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value + + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.Tx_Sync_Ctrl.tx_sync_f1.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFFB) | (0x4 & (random_field_value << 2))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.Tx_Sync_Ctrl.tx_sync_f1.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFFB) | (0x4 & (random_field_value << 2))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0xFFFFFFFB) | (0x4 & (random_field_value << 2))) + field_write_callback.assert_called_once_with(value=random_field_value) + + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.write_callback = None + sim_field.write_callback = None + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.Tx_Sync_Ctrl.tx_sync_f1.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFFB) | (0x4 & (random_field_value << 2))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # test access operations (read and/or write) to register: + # msk_top_regs.Tx_Sync_Ctrl.tx_sync_f2 + with self.subTest(msg='field: msk_top_regs.Tx_Sync_Ctrl.tx_sync_f2'): + sim_register = self.sim.register_by_full_name('msk_top_regs.Tx_Sync_Ctrl') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.Tx_Sync_Ctrl.tx_sync_f2') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x8) >> 3 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + self.assertEqual(await self.dut.Tx_Sync_Ctrl.tx_sync_f2.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0x1+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0xFFFFFFF7) | (random_field_value << 3)) + + self.assertEqual(await self.dut.Tx_Sync_Ctrl.tx_sync_f2.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x8) >> 3 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.Tx_Sync_Ctrl.tx_sync_f2.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x8) >> 3 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + self.assertEqual(await self.dut.Tx_Sync_Ctrl.tx_sync_f2.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value + + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.Tx_Sync_Ctrl.tx_sync_f2.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFF7) | (0x8 & (random_field_value << 3))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.Tx_Sync_Ctrl.tx_sync_f2.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFF7) | (0x8 & (random_field_value << 3))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0xFFFFFFF7) | (0x8 & (random_field_value << 3))) + field_write_callback.assert_called_once_with(value=random_field_value) + + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.write_callback = None + sim_field.write_callback = None + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.Tx_Sync_Ctrl.tx_sync_f2.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFF7) | (0x8 & (random_field_value << 3))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # test access operations (read and/or write) to register: + # msk_top_regs.Tx_Sync_Cnt.tx_sync_cnt + with self.subTest(msg='field: msk_top_regs.Tx_Sync_Cnt.tx_sync_cnt'): + sim_register = self.sim.register_by_full_name('msk_top_regs.Tx_Sync_Cnt') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.Tx_Sync_Cnt.tx_sync_cnt') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.Tx_Sync_Cnt.tx_sync_cnt.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0xFFFFFF+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0xFF000000) | (random_field_value << 0)) + + self.assertEqual(await self.dut.Tx_Sync_Cnt.tx_sync_cnt.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFF) >> 0 + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.Tx_Sync_Cnt.tx_sync_cnt.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.Tx_Sync_Cnt.tx_sync_cnt.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value + + random_field_value = random.randrange(0, 0xFFFFFF+1) + + await self.dut.Tx_Sync_Cnt.tx_sync_cnt.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFF000000) | (0xFFFFFF & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0xFFFFFF+1) + + await self.dut.Tx_Sync_Cnt.tx_sync_cnt.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFF000000) | (0xFFFFFF & (random_field_value << 0))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0xFF000000) | (0xFFFFFF & (random_field_value << 0))) + field_write_callback.assert_called_once_with(value=random_field_value) + + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.write_callback = None + sim_field.write_callback = None + random_field_value = random.randrange(0, 0xFFFFFF+1) + + await self.dut.Tx_Sync_Cnt.tx_sync_cnt.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFF000000) | (0xFFFFFF & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # test access operations (read and/or write) to register: + # msk_top_regs.lowpass_ema_alpha1.alpha + with self.subTest(msg='field: msk_top_regs.lowpass_ema_alpha1.alpha'): + sim_register = self.sim.register_by_full_name('msk_top_regs.lowpass_ema_alpha1') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.lowpass_ema_alpha1.alpha') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x3FFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.lowpass_ema_alpha1.alpha.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0x3FFFF+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0xFFFC0000) | (random_field_value << 0)) + + self.assertEqual(await self.dut.lowpass_ema_alpha1.alpha.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x3FFFF) >> 0 + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.lowpass_ema_alpha1.alpha.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x3FFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.lowpass_ema_alpha1.alpha.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value + + random_field_value = random.randrange(0, 0x3FFFF+1) + + await self.dut.lowpass_ema_alpha1.alpha.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFC0000) | (0x3FFFF & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0x3FFFF+1) + + await self.dut.lowpass_ema_alpha1.alpha.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFC0000) | (0x3FFFF & (random_field_value << 0))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0xFFFC0000) | (0x3FFFF & (random_field_value << 0))) + field_write_callback.assert_called_once_with(value=random_field_value) + + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.write_callback = None + sim_field.write_callback = None + random_field_value = random.randrange(0, 0x3FFFF+1) + + await self.dut.lowpass_ema_alpha1.alpha.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFC0000) | (0x3FFFF & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # test access operations (read and/or write) to register: + # msk_top_regs.lowpass_ema_alpha2.alpha + with self.subTest(msg='field: msk_top_regs.lowpass_ema_alpha2.alpha'): + sim_register = self.sim.register_by_full_name('msk_top_regs.lowpass_ema_alpha2') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.lowpass_ema_alpha2.alpha') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x3FFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.lowpass_ema_alpha2.alpha.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0x3FFFF+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0xFFFC0000) | (random_field_value << 0)) + + self.assertEqual(await self.dut.lowpass_ema_alpha2.alpha.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x3FFFF) >> 0 + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.lowpass_ema_alpha2.alpha.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x3FFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.lowpass_ema_alpha2.alpha.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value + + random_field_value = random.randrange(0, 0x3FFFF+1) + + await self.dut.lowpass_ema_alpha2.alpha.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFC0000) | (0x3FFFF & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0x3FFFF+1) + + await self.dut.lowpass_ema_alpha2.alpha.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFC0000) | (0x3FFFF & (random_field_value << 0))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0xFFFC0000) | (0x3FFFF & (random_field_value << 0))) + field_write_callback.assert_called_once_with(value=random_field_value) + + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.write_callback = None + sim_field.write_callback = None + random_field_value = random.randrange(0, 0x3FFFF+1) + + await self.dut.lowpass_ema_alpha2.alpha.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFC0000) | (0x3FFFF & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # test access operations (read and/or write) to register: + # msk_top_regs.rx_power.rx_power + with self.subTest(msg='field: msk_top_regs.rx_power.rx_power'): + sim_register = self.sim.register_by_full_name('msk_top_regs.rx_power') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.rx_power.rx_power') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x7FFFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.rx_power.rx_power.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0x7FFFFF+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0xFF800000) | (random_field_value << 0)) + + self.assertEqual(await self.dut.rx_power.rx_power.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x7FFFFF) >> 0 + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.rx_power.rx_power.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x7FFFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.rx_power.rx_power.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + + + + + + + + + +class msk_top_regs_block_access(msk_top_regs_SimTestCase_BlockAccess): # type: ignore[valid-type,misc] + """ + tests for all the block access methods + """ + + + +if __name__ == '__main__': + + if sys.version_info < (3, 8): + asynctest.main() + else: + unittest.main() + + + + diff --git a/rdl/outputs/rtl/msk_top_regs.vhd b/rdl/outputs/rtl/msk_top_regs.vhd new file mode 100644 index 0000000..9606951 --- /dev/null +++ b/rdl/outputs/rtl/msk_top_regs.vhd @@ -0,0 +1,2321 @@ +-- Generated by PeakRDL-regblock-vhdl - A free and open-source VHDL generator +-- https://github.com/SystemRDL/PeakRDL-regblock-vhdl +library ieee; +context ieee.ieee_std_context; +use ieee.fixed_pkg.all; + +use work.msk_top_regs_pkg.all; +use work.axi4lite_intf_pkg.all; +use work.reg_utils.all; + +entity msk_top_regs is + port ( + clk : in std_logic; + rst : in std_logic; + + s_axil_i : in axi4lite_slave_in_intf( + AWADDR(7 downto 0), + WDATA(31 downto 0), + WSTRB(3 downto 0), + ARADDR(7 downto 0) + ); + s_axil_o : out axi4lite_slave_out_intf( + RDATA(31 downto 0) + ); + + hwif_in : in msk_top_regs_in_t; + hwif_out : out msk_top_regs_out_t + ); +end entity msk_top_regs; + +architecture rtl of msk_top_regs is + ---------------------------------------------------------------------------- + -- CPU Bus interface signals + ---------------------------------------------------------------------------- + signal cpuif_req : std_logic; + signal cpuif_req_is_wr : std_logic; + signal cpuif_addr : std_logic_vector(7 downto 0); + signal cpuif_wr_data : std_logic_vector(31 downto 0); + signal cpuif_wr_biten : std_logic_vector(31 downto 0); + signal cpuif_req_stall_wr : std_logic; + signal cpuif_req_stall_rd : std_logic; + + signal cpuif_rd_ack : std_logic; + signal cpuif_rd_err : std_logic; + signal cpuif_rd_data : std_logic_vector(31 downto 0); + + signal cpuif_wr_ack : std_logic; + signal cpuif_wr_err : std_logic; + + signal cpuif_req_masked : std_logic; + + signal axil_n_in_flight : unsigned(1 downto 0); + signal axil_prev_was_rd : std_logic; + signal axil_arvalid : std_logic; + signal axil_araddr : std_logic_vector(7 downto 0); + signal axil_ar_accept : std_logic; + signal axil_awvalid : std_logic; + signal axil_awaddr : std_logic_vector(7 downto 0); + signal axil_wvalid : std_logic; + signal axil_wdata : std_logic_vector(31 downto 0); + signal axil_wstrb : std_logic_vector(3 downto 0); + signal axil_aw_accept : std_logic; + signal axil_resp_acked : std_logic; + type axil_resp_buffer_t is record + is_wr : std_logic; + err : std_logic; + rdata : std_logic_vector(31 downto 0); + end record axil_resp_buffer_t; + type axil_resp_buffer_array_t is array (integer range <>) of axil_resp_buffer_t; + signal axil_resp_buffer : axil_resp_buffer_array_t(1 downto 0); + signal axil_resp_wptr : unsigned(1 downto 0); + signal axil_resp_rptr : unsigned(1 downto 0); + + ---------------------------------------------------------------------------- + -- Address Decode Signals + ---------------------------------------------------------------------------- + type decoded_reg_strb_t is record + Hash_ID_Low : std_logic; + Hash_ID_High : std_logic; + MSK_Init : std_logic; + MSK_Control : std_logic; + MSK_Status : std_logic; + Tx_Bit_Count : std_logic; + Tx_Enable_Count : std_logic; + Fb_FreqWord : std_logic; + TX_F1_FreqWord : std_logic; + TX_F2_FreqWord : std_logic; + RX_F1_FreqWord : std_logic; + RX_F2_FreqWord : std_logic; + LPF_Config_0 : std_logic; + LPF_Config_1 : std_logic; + Tx_Data_Width : std_logic; + Rx_Data_Width : std_logic; + PRBS_Control : std_logic; + PRBS_Initial_State : std_logic; + PRBS_Polynomial : std_logic; + PRBS_Error_Mask : std_logic; + PRBS_Bit_Count : std_logic; + PRBS_Error_Count : std_logic; + LPF_Accum_F1 : std_logic; + LPF_Accum_F2 : std_logic; + axis_xfer_count : std_logic; + Rx_Sample_Discard : std_logic; + LPF_Config_2 : std_logic; + f1_nco_adjust : std_logic; + f2_nco_adjust : std_logic; + f1_error : std_logic; + f2_error : std_logic; + Tx_Sync_Ctrl : std_logic; + Tx_Sync_Cnt : std_logic; + lowpass_ema_alpha1 : std_logic; + lowpass_ema_alpha2 : std_logic; + rx_power : std_logic; + end record; + signal decoded_reg_strb : decoded_reg_strb_t; + signal decoded_req : std_logic; + signal decoded_req_is_wr : std_logic; + signal decoded_wr_data : std_logic_vector(31 downto 0); + signal decoded_wr_biten : std_logic_vector(31 downto 0); + + ---------------------------------------------------------------------------- + -- Field Logic Signals + ---------------------------------------------------------------------------- + -- Field Combinational Signals + type \msk_top_regs.MSK_Init.txrxinit_combo_t\ is record + next_q : std_logic; + load_next : std_logic; + end record; + + type \msk_top_regs.MSK_Init.txinit_combo_t\ is record + next_q : std_logic; + load_next : std_logic; + end record; + + type \msk_top_regs.MSK_Init.rxinit_combo_t\ is record + next_q : std_logic; + load_next : std_logic; + end record; + + type \msk_top_regs.MSK_Init_combo_t\ is record + txrxinit : \msk_top_regs.MSK_Init.txrxinit_combo_t\; + txinit : \msk_top_regs.MSK_Init.txinit_combo_t\; + rxinit : \msk_top_regs.MSK_Init.rxinit_combo_t\; + end record; + + type \msk_top_regs.MSK_Control.ptt_combo_t\ is record + next_q : std_logic; + load_next : std_logic; + end record; + + type \msk_top_regs.MSK_Control.loopback_ena_combo_t\ is record + next_q : std_logic; + load_next : std_logic; + end record; + + type \msk_top_regs.MSK_Control.rx_invert_combo_t\ is record + next_q : std_logic; + load_next : std_logic; + end record; + + type \msk_top_regs.MSK_Control.clear_counts_combo_t\ is record + next_q : std_logic; + load_next : std_logic; + end record; + + type \msk_top_regs.MSK_Control.diff_encoder_loopback_combo_t\ is record + next_q : std_logic; + load_next : std_logic; + end record; + + type \msk_top_regs.MSK_Control_combo_t\ is record + ptt : \msk_top_regs.MSK_Control.ptt_combo_t\; + loopback_ena : \msk_top_regs.MSK_Control.loopback_ena_combo_t\; + rx_invert : \msk_top_regs.MSK_Control.rx_invert_combo_t\; + clear_counts : \msk_top_regs.MSK_Control.clear_counts_combo_t\; + diff_encoder_loopback : \msk_top_regs.MSK_Control.diff_encoder_loopback_combo_t\; + end record; + + type \msk_top_regs.Fb_FreqWord.config_data_combo_t\ is record + next_q : std_logic_vector(31 downto 0); + load_next : std_logic; + end record; + + type \msk_top_regs.Fb_FreqWord_combo_t\ is record + config_data : \msk_top_regs.Fb_FreqWord.config_data_combo_t\; + end record; + + type \msk_top_regs.TX_F1_FreqWord.config_data_combo_t\ is record + next_q : std_logic_vector(31 downto 0); + load_next : std_logic; + end record; + + type \msk_top_regs.TX_F1_FreqWord_combo_t\ is record + config_data : \msk_top_regs.TX_F1_FreqWord.config_data_combo_t\; + end record; + + type \msk_top_regs.TX_F2_FreqWord.config_data_combo_t\ is record + next_q : std_logic_vector(31 downto 0); + load_next : std_logic; + end record; + + type \msk_top_regs.TX_F2_FreqWord_combo_t\ is record + config_data : \msk_top_regs.TX_F2_FreqWord.config_data_combo_t\; + end record; + + type \msk_top_regs.RX_F1_FreqWord.config_data_combo_t\ is record + next_q : std_logic_vector(31 downto 0); + load_next : std_logic; + end record; + + type \msk_top_regs.RX_F1_FreqWord_combo_t\ is record + config_data : \msk_top_regs.RX_F1_FreqWord.config_data_combo_t\; + end record; + + type \msk_top_regs.RX_F2_FreqWord.config_data_combo_t\ is record + next_q : std_logic_vector(31 downto 0); + load_next : std_logic; + end record; + + type \msk_top_regs.RX_F2_FreqWord_combo_t\ is record + config_data : \msk_top_regs.RX_F2_FreqWord.config_data_combo_t\; + end record; + + type \msk_top_regs.LPF_Config_0.lpf_freeze_combo_t\ is record + next_q : std_logic; + load_next : std_logic; + end record; + + type \msk_top_regs.LPF_Config_0.lpf_zero_combo_t\ is record + next_q : std_logic; + load_next : std_logic; + end record; + + type \msk_top_regs.LPF_Config_0.prbs_reserved_combo_t\ is record + next_q : std_logic_vector(5 downto 0); + load_next : std_logic; + end record; + + type \msk_top_regs.LPF_Config_0.lpf_alpha_combo_t\ is record + next_q : std_logic_vector(23 downto 0); + load_next : std_logic; + end record; + + type \msk_top_regs.LPF_Config_0_combo_t\ is record + lpf_freeze : \msk_top_regs.LPF_Config_0.lpf_freeze_combo_t\; + lpf_zero : \msk_top_regs.LPF_Config_0.lpf_zero_combo_t\; + prbs_reserved : \msk_top_regs.LPF_Config_0.prbs_reserved_combo_t\; + lpf_alpha : \msk_top_regs.LPF_Config_0.lpf_alpha_combo_t\; + end record; + + type \msk_top_regs.LPF_Config_1.i_gain_combo_t\ is record + next_q : std_logic_vector(23 downto 0); + load_next : std_logic; + end record; + + type \msk_top_regs.LPF_Config_1.i_shift_combo_t\ is record + next_q : std_logic_vector(7 downto 0); + load_next : std_logic; + end record; + + type \msk_top_regs.LPF_Config_1_combo_t\ is record + i_gain : \msk_top_regs.LPF_Config_1.i_gain_combo_t\; + i_shift : \msk_top_regs.LPF_Config_1.i_shift_combo_t\; + end record; + + type \msk_top_regs.Tx_Data_Width.data_width_combo_t\ is record + next_q : std_logic_vector(7 downto 0); + load_next : std_logic; + end record; + + type \msk_top_regs.Tx_Data_Width_combo_t\ is record + data_width : \msk_top_regs.Tx_Data_Width.data_width_combo_t\; + end record; + + type \msk_top_regs.Rx_Data_Width.data_width_combo_t\ is record + next_q : std_logic_vector(7 downto 0); + load_next : std_logic; + end record; + + type \msk_top_regs.Rx_Data_Width_combo_t\ is record + data_width : \msk_top_regs.Rx_Data_Width.data_width_combo_t\; + end record; + + type \msk_top_regs.PRBS_Control.prbs_sel_combo_t\ is record + next_q : std_logic; + load_next : std_logic; + end record; + + type \msk_top_regs.PRBS_Control.prbs_error_insert_combo_t\ is record + next_q : std_logic; + load_next : std_logic; + end record; + + type \msk_top_regs.PRBS_Control.prbs_clear_combo_t\ is record + next_q : std_logic; + load_next : std_logic; + end record; + + type \msk_top_regs.PRBS_Control.prbs_manual_sync_combo_t\ is record + next_q : std_logic; + load_next : std_logic; + end record; + + type \msk_top_regs.PRBS_Control.prbs_reserved_combo_t\ is record + next_q : std_logic_vector(11 downto 0); + load_next : std_logic; + end record; + + type \msk_top_regs.PRBS_Control.prbs_sync_threshold_combo_t\ is record + next_q : std_logic_vector(15 downto 0); + load_next : std_logic; + end record; + + type \msk_top_regs.PRBS_Control_combo_t\ is record + prbs_sel : \msk_top_regs.PRBS_Control.prbs_sel_combo_t\; + prbs_error_insert : \msk_top_regs.PRBS_Control.prbs_error_insert_combo_t\; + prbs_clear : \msk_top_regs.PRBS_Control.prbs_clear_combo_t\; + prbs_manual_sync : \msk_top_regs.PRBS_Control.prbs_manual_sync_combo_t\; + prbs_reserved : \msk_top_regs.PRBS_Control.prbs_reserved_combo_t\; + prbs_sync_threshold : \msk_top_regs.PRBS_Control.prbs_sync_threshold_combo_t\; + end record; + + type \msk_top_regs.PRBS_Initial_State.config_data_combo_t\ is record + next_q : std_logic_vector(31 downto 0); + load_next : std_logic; + end record; + + type \msk_top_regs.PRBS_Initial_State_combo_t\ is record + config_data : \msk_top_regs.PRBS_Initial_State.config_data_combo_t\; + end record; + + type \msk_top_regs.PRBS_Polynomial.config_data_combo_t\ is record + next_q : std_logic_vector(31 downto 0); + load_next : std_logic; + end record; + + type \msk_top_regs.PRBS_Polynomial_combo_t\ is record + config_data : \msk_top_regs.PRBS_Polynomial.config_data_combo_t\; + end record; + + type \msk_top_regs.PRBS_Error_Mask.config_data_combo_t\ is record + next_q : std_logic_vector(31 downto 0); + load_next : std_logic; + end record; + + type \msk_top_regs.PRBS_Error_Mask_combo_t\ is record + config_data : \msk_top_regs.PRBS_Error_Mask.config_data_combo_t\; + end record; + + type \msk_top_regs.Rx_Sample_Discard.rx_sample_discard_combo_t\ is record + next_q : std_logic_vector(7 downto 0); + load_next : std_logic; + end record; + + type \msk_top_regs.Rx_Sample_Discard.rx_nco_discard_combo_t\ is record + next_q : std_logic_vector(7 downto 0); + load_next : std_logic; + end record; + + type \msk_top_regs.Rx_Sample_Discard_combo_t\ is record + rx_sample_discard : \msk_top_regs.Rx_Sample_Discard.rx_sample_discard_combo_t\; + rx_nco_discard : \msk_top_regs.Rx_Sample_Discard.rx_nco_discard_combo_t\; + end record; + + type \msk_top_regs.LPF_Config_2.p_gain_combo_t\ is record + next_q : std_logic_vector(23 downto 0); + load_next : std_logic; + end record; + + type \msk_top_regs.LPF_Config_2.p_shift_combo_t\ is record + next_q : std_logic_vector(7 downto 0); + load_next : std_logic; + end record; + + type \msk_top_regs.LPF_Config_2_combo_t\ is record + p_gain : \msk_top_regs.LPF_Config_2.p_gain_combo_t\; + p_shift : \msk_top_regs.LPF_Config_2.p_shift_combo_t\; + end record; + + type \msk_top_regs.Tx_Sync_Ctrl.tx_sync_ena_combo_t\ is record + next_q : std_logic; + load_next : std_logic; + end record; + + type \msk_top_regs.Tx_Sync_Ctrl.tx_sync_force_combo_t\ is record + next_q : std_logic; + load_next : std_logic; + end record; + + type \msk_top_regs.Tx_Sync_Ctrl.tx_sync_f1_combo_t\ is record + next_q : std_logic; + load_next : std_logic; + end record; + + type \msk_top_regs.Tx_Sync_Ctrl.tx_sync_f2_combo_t\ is record + next_q : std_logic; + load_next : std_logic; + end record; + + type \msk_top_regs.Tx_Sync_Ctrl_combo_t\ is record + tx_sync_ena : \msk_top_regs.Tx_Sync_Ctrl.tx_sync_ena_combo_t\; + tx_sync_force : \msk_top_regs.Tx_Sync_Ctrl.tx_sync_force_combo_t\; + tx_sync_f1 : \msk_top_regs.Tx_Sync_Ctrl.tx_sync_f1_combo_t\; + tx_sync_f2 : \msk_top_regs.Tx_Sync_Ctrl.tx_sync_f2_combo_t\; + end record; + + type \msk_top_regs.Tx_Sync_Cnt.tx_sync_cnt_combo_t\ is record + next_q : std_logic_vector(23 downto 0); + load_next : std_logic; + end record; + + type \msk_top_regs.Tx_Sync_Cnt_combo_t\ is record + tx_sync_cnt : \msk_top_regs.Tx_Sync_Cnt.tx_sync_cnt_combo_t\; + end record; + + type \msk_top_regs.lowpass_ema_alpha1.alpha_combo_t\ is record + next_q : std_logic_vector(17 downto 0); + load_next : std_logic; + end record; + + type \msk_top_regs.lowpass_ema_alpha1_combo_t\ is record + alpha : \msk_top_regs.lowpass_ema_alpha1.alpha_combo_t\; + end record; + + type \msk_top_regs.lowpass_ema_alpha2.alpha_combo_t\ is record + next_q : std_logic_vector(17 downto 0); + load_next : std_logic; + end record; + + type \msk_top_regs.lowpass_ema_alpha2_combo_t\ is record + alpha : \msk_top_regs.lowpass_ema_alpha2.alpha_combo_t\; + end record; + + type field_combo_t is record + MSK_Init : \msk_top_regs.MSK_Init_combo_t\; + MSK_Control : \msk_top_regs.MSK_Control_combo_t\; + Fb_FreqWord : \msk_top_regs.Fb_FreqWord_combo_t\; + TX_F1_FreqWord : \msk_top_regs.TX_F1_FreqWord_combo_t\; + TX_F2_FreqWord : \msk_top_regs.TX_F2_FreqWord_combo_t\; + RX_F1_FreqWord : \msk_top_regs.RX_F1_FreqWord_combo_t\; + RX_F2_FreqWord : \msk_top_regs.RX_F2_FreqWord_combo_t\; + LPF_Config_0 : \msk_top_regs.LPF_Config_0_combo_t\; + LPF_Config_1 : \msk_top_regs.LPF_Config_1_combo_t\; + Tx_Data_Width : \msk_top_regs.Tx_Data_Width_combo_t\; + Rx_Data_Width : \msk_top_regs.Rx_Data_Width_combo_t\; + PRBS_Control : \msk_top_regs.PRBS_Control_combo_t\; + PRBS_Initial_State : \msk_top_regs.PRBS_Initial_State_combo_t\; + PRBS_Polynomial : \msk_top_regs.PRBS_Polynomial_combo_t\; + PRBS_Error_Mask : \msk_top_regs.PRBS_Error_Mask_combo_t\; + Rx_Sample_Discard : \msk_top_regs.Rx_Sample_Discard_combo_t\; + LPF_Config_2 : \msk_top_regs.LPF_Config_2_combo_t\; + Tx_Sync_Ctrl : \msk_top_regs.Tx_Sync_Ctrl_combo_t\; + Tx_Sync_Cnt : \msk_top_regs.Tx_Sync_Cnt_combo_t\; + lowpass_ema_alpha1 : \msk_top_regs.lowpass_ema_alpha1_combo_t\; + lowpass_ema_alpha2 : \msk_top_regs.lowpass_ema_alpha2_combo_t\; + end record; + signal field_combo : field_combo_t; + + -- Field Storage Signals + type \msk_top_regs.MSK_Init.txrxinit_storage_t\ is record + value : std_logic; + end record; + + type \msk_top_regs.MSK_Init.txinit_storage_t\ is record + value : std_logic; + end record; + + type \msk_top_regs.MSK_Init.rxinit_storage_t\ is record + value : std_logic; + end record; + + type \msk_top_regs.MSK_Init_storage_t\ is record + txrxinit : \msk_top_regs.MSK_Init.txrxinit_storage_t\; + txinit : \msk_top_regs.MSK_Init.txinit_storage_t\; + rxinit : \msk_top_regs.MSK_Init.rxinit_storage_t\; + end record; + + type \msk_top_regs.MSK_Control.ptt_storage_t\ is record + value : std_logic; + end record; + + type \msk_top_regs.MSK_Control.loopback_ena_storage_t\ is record + value : std_logic; + end record; + + type \msk_top_regs.MSK_Control.rx_invert_storage_t\ is record + value : std_logic; + end record; + + type \msk_top_regs.MSK_Control.clear_counts_storage_t\ is record + value : std_logic; + end record; + + type \msk_top_regs.MSK_Control.diff_encoder_loopback_storage_t\ is record + value : std_logic; + end record; + + type \msk_top_regs.MSK_Control_storage_t\ is record + ptt : \msk_top_regs.MSK_Control.ptt_storage_t\; + loopback_ena : \msk_top_regs.MSK_Control.loopback_ena_storage_t\; + rx_invert : \msk_top_regs.MSK_Control.rx_invert_storage_t\; + clear_counts : \msk_top_regs.MSK_Control.clear_counts_storage_t\; + diff_encoder_loopback : \msk_top_regs.MSK_Control.diff_encoder_loopback_storage_t\; + end record; + + type \msk_top_regs.Fb_FreqWord.config_data_storage_t\ is record + value : std_logic_vector(31 downto 0); + end record; + + type \msk_top_regs.Fb_FreqWord_storage_t\ is record + config_data : \msk_top_regs.Fb_FreqWord.config_data_storage_t\; + end record; + + type \msk_top_regs.TX_F1_FreqWord.config_data_storage_t\ is record + value : std_logic_vector(31 downto 0); + end record; + + type \msk_top_regs.TX_F1_FreqWord_storage_t\ is record + config_data : \msk_top_regs.TX_F1_FreqWord.config_data_storage_t\; + end record; + + type \msk_top_regs.TX_F2_FreqWord.config_data_storage_t\ is record + value : std_logic_vector(31 downto 0); + end record; + + type \msk_top_regs.TX_F2_FreqWord_storage_t\ is record + config_data : \msk_top_regs.TX_F2_FreqWord.config_data_storage_t\; + end record; + + type \msk_top_regs.RX_F1_FreqWord.config_data_storage_t\ is record + value : std_logic_vector(31 downto 0); + end record; + + type \msk_top_regs.RX_F1_FreqWord_storage_t\ is record + config_data : \msk_top_regs.RX_F1_FreqWord.config_data_storage_t\; + end record; + + type \msk_top_regs.RX_F2_FreqWord.config_data_storage_t\ is record + value : std_logic_vector(31 downto 0); + end record; + + type \msk_top_regs.RX_F2_FreqWord_storage_t\ is record + config_data : \msk_top_regs.RX_F2_FreqWord.config_data_storage_t\; + end record; + + type \msk_top_regs.LPF_Config_0.lpf_freeze_storage_t\ is record + value : std_logic; + end record; + + type \msk_top_regs.LPF_Config_0.lpf_zero_storage_t\ is record + value : std_logic; + end record; + + type \msk_top_regs.LPF_Config_0.prbs_reserved_storage_t\ is record + value : std_logic_vector(5 downto 0); + end record; + + type \msk_top_regs.LPF_Config_0.lpf_alpha_storage_t\ is record + value : std_logic_vector(23 downto 0); + end record; + + type \msk_top_regs.LPF_Config_0_storage_t\ is record + lpf_freeze : \msk_top_regs.LPF_Config_0.lpf_freeze_storage_t\; + lpf_zero : \msk_top_regs.LPF_Config_0.lpf_zero_storage_t\; + prbs_reserved : \msk_top_regs.LPF_Config_0.prbs_reserved_storage_t\; + lpf_alpha : \msk_top_regs.LPF_Config_0.lpf_alpha_storage_t\; + end record; + + type \msk_top_regs.LPF_Config_1.i_gain_storage_t\ is record + value : std_logic_vector(23 downto 0); + end record; + + type \msk_top_regs.LPF_Config_1.i_shift_storage_t\ is record + value : std_logic_vector(7 downto 0); + end record; + + type \msk_top_regs.LPF_Config_1_storage_t\ is record + i_gain : \msk_top_regs.LPF_Config_1.i_gain_storage_t\; + i_shift : \msk_top_regs.LPF_Config_1.i_shift_storage_t\; + end record; + + type \msk_top_regs.Tx_Data_Width.data_width_storage_t\ is record + value : std_logic_vector(7 downto 0); + end record; + + type \msk_top_regs.Tx_Data_Width_storage_t\ is record + data_width : \msk_top_regs.Tx_Data_Width.data_width_storage_t\; + end record; + + type \msk_top_regs.Rx_Data_Width.data_width_storage_t\ is record + value : std_logic_vector(7 downto 0); + end record; + + type \msk_top_regs.Rx_Data_Width_storage_t\ is record + data_width : \msk_top_regs.Rx_Data_Width.data_width_storage_t\; + end record; + + type \msk_top_regs.PRBS_Control.prbs_sel_storage_t\ is record + value : std_logic; + end record; + + type \msk_top_regs.PRBS_Control.prbs_error_insert_storage_t\ is record + value : std_logic; + end record; + + type \msk_top_regs.PRBS_Control.prbs_clear_storage_t\ is record + value : std_logic; + end record; + + type \msk_top_regs.PRBS_Control.prbs_manual_sync_storage_t\ is record + value : std_logic; + end record; + + type \msk_top_regs.PRBS_Control.prbs_reserved_storage_t\ is record + value : std_logic_vector(11 downto 0); + end record; + + type \msk_top_regs.PRBS_Control.prbs_sync_threshold_storage_t\ is record + value : std_logic_vector(15 downto 0); + end record; + + type \msk_top_regs.PRBS_Control_storage_t\ is record + prbs_sel : \msk_top_regs.PRBS_Control.prbs_sel_storage_t\; + prbs_error_insert : \msk_top_regs.PRBS_Control.prbs_error_insert_storage_t\; + prbs_clear : \msk_top_regs.PRBS_Control.prbs_clear_storage_t\; + prbs_manual_sync : \msk_top_regs.PRBS_Control.prbs_manual_sync_storage_t\; + prbs_reserved : \msk_top_regs.PRBS_Control.prbs_reserved_storage_t\; + prbs_sync_threshold : \msk_top_regs.PRBS_Control.prbs_sync_threshold_storage_t\; + end record; + + type \msk_top_regs.PRBS_Initial_State.config_data_storage_t\ is record + value : std_logic_vector(31 downto 0); + end record; + + type \msk_top_regs.PRBS_Initial_State_storage_t\ is record + config_data : \msk_top_regs.PRBS_Initial_State.config_data_storage_t\; + end record; + + type \msk_top_regs.PRBS_Polynomial.config_data_storage_t\ is record + value : std_logic_vector(31 downto 0); + end record; + + type \msk_top_regs.PRBS_Polynomial_storage_t\ is record + config_data : \msk_top_regs.PRBS_Polynomial.config_data_storage_t\; + end record; + + type \msk_top_regs.PRBS_Error_Mask.config_data_storage_t\ is record + value : std_logic_vector(31 downto 0); + end record; + + type \msk_top_regs.PRBS_Error_Mask_storage_t\ is record + config_data : \msk_top_regs.PRBS_Error_Mask.config_data_storage_t\; + end record; + + type \msk_top_regs.Rx_Sample_Discard.rx_sample_discard_storage_t\ is record + value : std_logic_vector(7 downto 0); + end record; + + type \msk_top_regs.Rx_Sample_Discard.rx_nco_discard_storage_t\ is record + value : std_logic_vector(7 downto 0); + end record; + + type \msk_top_regs.Rx_Sample_Discard_storage_t\ is record + rx_sample_discard : \msk_top_regs.Rx_Sample_Discard.rx_sample_discard_storage_t\; + rx_nco_discard : \msk_top_regs.Rx_Sample_Discard.rx_nco_discard_storage_t\; + end record; + + type \msk_top_regs.LPF_Config_2.p_gain_storage_t\ is record + value : std_logic_vector(23 downto 0); + end record; + + type \msk_top_regs.LPF_Config_2.p_shift_storage_t\ is record + value : std_logic_vector(7 downto 0); + end record; + + type \msk_top_regs.LPF_Config_2_storage_t\ is record + p_gain : \msk_top_regs.LPF_Config_2.p_gain_storage_t\; + p_shift : \msk_top_regs.LPF_Config_2.p_shift_storage_t\; + end record; + + type \msk_top_regs.Tx_Sync_Ctrl.tx_sync_ena_storage_t\ is record + value : std_logic; + end record; + + type \msk_top_regs.Tx_Sync_Ctrl.tx_sync_force_storage_t\ is record + value : std_logic; + end record; + + type \msk_top_regs.Tx_Sync_Ctrl.tx_sync_f1_storage_t\ is record + value : std_logic; + end record; + + type \msk_top_regs.Tx_Sync_Ctrl.tx_sync_f2_storage_t\ is record + value : std_logic; + end record; + + type \msk_top_regs.Tx_Sync_Ctrl_storage_t\ is record + tx_sync_ena : \msk_top_regs.Tx_Sync_Ctrl.tx_sync_ena_storage_t\; + tx_sync_force : \msk_top_regs.Tx_Sync_Ctrl.tx_sync_force_storage_t\; + tx_sync_f1 : \msk_top_regs.Tx_Sync_Ctrl.tx_sync_f1_storage_t\; + tx_sync_f2 : \msk_top_regs.Tx_Sync_Ctrl.tx_sync_f2_storage_t\; + end record; + + type \msk_top_regs.Tx_Sync_Cnt.tx_sync_cnt_storage_t\ is record + value : std_logic_vector(23 downto 0); + end record; + + type \msk_top_regs.Tx_Sync_Cnt_storage_t\ is record + tx_sync_cnt : \msk_top_regs.Tx_Sync_Cnt.tx_sync_cnt_storage_t\; + end record; + + type \msk_top_regs.lowpass_ema_alpha1.alpha_storage_t\ is record + value : std_logic_vector(17 downto 0); + end record; + + type \msk_top_regs.lowpass_ema_alpha1_storage_t\ is record + alpha : \msk_top_regs.lowpass_ema_alpha1.alpha_storage_t\; + end record; + + type \msk_top_regs.lowpass_ema_alpha2.alpha_storage_t\ is record + value : std_logic_vector(17 downto 0); + end record; + + type \msk_top_regs.lowpass_ema_alpha2_storage_t\ is record + alpha : \msk_top_regs.lowpass_ema_alpha2.alpha_storage_t\; + end record; + + type field_storage_t is record + MSK_Init : \msk_top_regs.MSK_Init_storage_t\; + MSK_Control : \msk_top_regs.MSK_Control_storage_t\; + Fb_FreqWord : \msk_top_regs.Fb_FreqWord_storage_t\; + TX_F1_FreqWord : \msk_top_regs.TX_F1_FreqWord_storage_t\; + TX_F2_FreqWord : \msk_top_regs.TX_F2_FreqWord_storage_t\; + RX_F1_FreqWord : \msk_top_regs.RX_F1_FreqWord_storage_t\; + RX_F2_FreqWord : \msk_top_regs.RX_F2_FreqWord_storage_t\; + LPF_Config_0 : \msk_top_regs.LPF_Config_0_storage_t\; + LPF_Config_1 : \msk_top_regs.LPF_Config_1_storage_t\; + Tx_Data_Width : \msk_top_regs.Tx_Data_Width_storage_t\; + Rx_Data_Width : \msk_top_regs.Rx_Data_Width_storage_t\; + PRBS_Control : \msk_top_regs.PRBS_Control_storage_t\; + PRBS_Initial_State : \msk_top_regs.PRBS_Initial_State_storage_t\; + PRBS_Polynomial : \msk_top_regs.PRBS_Polynomial_storage_t\; + PRBS_Error_Mask : \msk_top_regs.PRBS_Error_Mask_storage_t\; + Rx_Sample_Discard : \msk_top_regs.Rx_Sample_Discard_storage_t\; + LPF_Config_2 : \msk_top_regs.LPF_Config_2_storage_t\; + Tx_Sync_Ctrl : \msk_top_regs.Tx_Sync_Ctrl_storage_t\; + Tx_Sync_Cnt : \msk_top_regs.Tx_Sync_Cnt_storage_t\; + lowpass_ema_alpha1 : \msk_top_regs.lowpass_ema_alpha1_storage_t\; + lowpass_ema_alpha2 : \msk_top_regs.lowpass_ema_alpha2_storage_t\; + end record; + signal field_storage : field_storage_t; + + ---------------------------------------------------------------------------- + -- Readback Signals + ---------------------------------------------------------------------------- + signal readback_err : std_logic; + signal readback_done : std_logic; + signal readback_data : std_logic_vector(31 downto 0); + signal readback_array : std_logic_vector_array1(0 to 35)(31 downto 0); + +begin + + ---------------------------------------------------------------------------- + -- CPU Bus interface + ---------------------------------------------------------------------------- + -- pragma translate_off + cpuif_generics: process begin + assert_bad_addr_width: assert s_axil_i.ARADDR'length >= MSK_TOP_REGS_MIN_ADDR_WIDTH + report "Interface address width of " & integer'image(s_axil_i.ARADDR'length) & " is too small. Shall be at least " & integer'image(MSK_TOP_REGS_MIN_ADDR_WIDTH) & " bits" + severity failure; + assert_bad_data_width: assert s_axil_i.WDATA'length = MSK_TOP_REGS_DATA_WIDTH + report "Interface data width of " & integer'image(s_axil_i.WDATA'length) & " is incorrect. Shall be " & integer'image(MSK_TOP_REGS_DATA_WIDTH) & " bits" + severity failure; + wait; + end process; + -- pragma translate_on + + + -- Max Outstanding Transactions: 2 + -- Transaction request acceptance + process(clk) begin + if false then -- async reset + axil_prev_was_rd <= '0'; + axil_arvalid <= '0'; + axil_araddr <= (others => '0'); + axil_awvalid <= '0'; + axil_awaddr <= (others => '0'); + axil_wvalid <= '0'; + axil_wdata <= (others => '0'); + axil_wstrb <= (others => '0'); + axil_n_in_flight <= (others => '0'); + elsif rising_edge(clk) then + if rst then -- sync reset + axil_prev_was_rd <= '0'; + axil_arvalid <= '0'; + axil_araddr <= (others => '0'); + axil_awvalid <= '0'; + axil_awaddr <= (others => '0'); + axil_wvalid <= '0'; + axil_wdata <= (others => '0'); + axil_wstrb <= (others => '0'); + axil_n_in_flight <= (others => '0'); + else + -- AR* acceptance register + if axil_ar_accept then + axil_prev_was_rd <= '1'; + axil_arvalid <= '0'; + end if; + if s_axil_i.ARVALID and s_axil_o.ARREADY then + axil_arvalid <= '1'; + axil_araddr <= s_axil_i.ARADDR; + end if; + + -- AW* & W* acceptance registers + if axil_aw_accept then + axil_prev_was_rd <= '0'; + axil_awvalid <= '0'; + axil_wvalid <= '0'; + end if; + if s_axil_i.AWVALID and s_axil_o.AWREADY then + axil_awvalid <= '1'; + axil_awaddr <= s_axil_i.AWADDR; + end if; + if s_axil_i.WVALID and s_axil_o.WREADY then + axil_wvalid <= '1'; + axil_wdata <= s_axil_i.WDATA; + axil_wstrb <= s_axil_i.WSTRB; + end if; + + -- Keep track of in-flight transactions + if (axil_ar_accept or axil_aw_accept) and not axil_resp_acked then + axil_n_in_flight <= axil_n_in_flight + 1; + elsif not (axil_ar_accept or axil_aw_accept) and axil_resp_acked then + axil_n_in_flight <= axil_n_in_flight - 1; + end if; + end if; + end if; + end process; + + process(all) begin + s_axil_o.ARREADY <= not axil_arvalid or axil_ar_accept; + s_axil_o.AWREADY <= not axil_awvalid or axil_aw_accept; + s_axil_o.WREADY <= not axil_wvalid or axil_aw_accept; + end process; + + -- Request dispatch + process(all) begin + cpuif_wr_data <= axil_wdata; + for i in axil_wstrb'RANGE loop + cpuif_wr_biten(i*8 + 7 downto i*8) <= (others => axil_wstrb(i)); + end loop; + cpuif_req <= '0'; + cpuif_req_is_wr <= '0'; + cpuif_addr <= (others => '0'); + axil_ar_accept <= '0'; + axil_aw_accept <= '0'; + + if axil_n_in_flight < to_unsigned(2, 2) then + -- Can safely issue more transactions without overwhelming response buffer + if axil_arvalid and not axil_prev_was_rd then + cpuif_req <= '1'; + cpuif_req_is_wr <= '0'; + cpuif_addr <= (7 downto 2 => axil_araddr(7 downto 2), others => '0'); + if not cpuif_req_stall_rd then + axil_ar_accept <= '1'; + end if; + elsif axil_awvalid and axil_wvalid then + cpuif_req <= '1'; + cpuif_req_is_wr <= '1'; + cpuif_addr <= (7 downto 2 => axil_awaddr(7 downto 2), others => '0'); + if not cpuif_req_stall_wr then + axil_aw_accept <= '1'; + end if; + elsif axil_arvalid then + cpuif_req <= '1'; + cpuif_req_is_wr <= '0'; + cpuif_addr <= (7 downto 2 => axil_araddr(7 downto 2), others => '0'); + if not cpuif_req_stall_rd then + axil_ar_accept <= '1'; + end if; + end if; + end if; + end process; + -- AXI4-Lite Response Logic + process(clk) begin + if false then -- async reset + for i in axil_resp_buffer'RANGE loop + axil_resp_buffer(i).is_wr <= '0'; + axil_resp_buffer(i).err <= '0'; + axil_resp_buffer(i).rdata <= (others => '0'); + end loop; + axil_resp_wptr <= (others => '0'); + axil_resp_rptr <= (others => '0'); + elsif rising_edge(clk) then + if rst then -- sync reset + for i in axil_resp_buffer'RANGE loop + axil_resp_buffer(i).is_wr <= '0'; + axil_resp_buffer(i).err <= '0'; + axil_resp_buffer(i).rdata <= (others => '0'); + end loop; + axil_resp_wptr <= (others => '0'); + axil_resp_rptr <= (others => '0'); + else + -- Store responses in buffer until AXI response channel accepts them + if cpuif_rd_ack or cpuif_wr_ack then + if cpuif_rd_ack then + axil_resp_buffer(to_integer(axil_resp_wptr(0 downto 0))).is_wr <= '0'; + axil_resp_buffer(to_integer(axil_resp_wptr(0 downto 0))).err <= cpuif_rd_err; + axil_resp_buffer(to_integer(axil_resp_wptr(0 downto 0))).rdata <= cpuif_rd_data; + + elsif cpuif_wr_ack then + axil_resp_buffer(to_integer(axil_resp_wptr(0 downto 0))).is_wr <= '1'; + axil_resp_buffer(to_integer(axil_resp_wptr(0 downto 0))).err <= cpuif_wr_err; + end if; + axil_resp_wptr <= axil_resp_wptr + 1; + end if; + + -- Advance read pointer when acknowledged + if axil_resp_acked then + axil_resp_rptr <= axil_resp_rptr + 1; + end if; + end if; + end if; + end process; + + process(all) begin + axil_resp_acked <= '0'; + s_axil_o.BVALID <= '0'; + s_axil_o.RVALID <= '0'; + if axil_resp_rptr /= axil_resp_wptr then + if axil_resp_buffer(to_integer(axil_resp_rptr(0 downto 0))).is_wr then + s_axil_o.BVALID <= '1'; + if s_axil_i.BREADY then + axil_resp_acked <= '1'; + end if; + else + s_axil_o.RVALID <= '1'; + if s_axil_i.RREADY then + axil_resp_acked <= '1'; + end if; + end if; + end if; + + s_axil_o.RDATA <= axil_resp_buffer(to_integer(axil_resp_rptr(0 downto 0))).rdata; + if axil_resp_buffer(to_integer(axil_resp_rptr(0 downto 0))).err then + s_axil_o.BRESP <= "10"; + s_axil_o.RRESP <= "10"; + else + s_axil_o.BRESP <= "00"; + s_axil_o.RRESP <= "00"; + end if; + end process; + + -- Read & write latencies are balanced. Stalls not required + cpuif_req_stall_rd <= '0'; + cpuif_req_stall_wr <= '0'; + cpuif_req_masked <= cpuif_req + and not (not cpuif_req_is_wr and cpuif_req_stall_rd) + and not (cpuif_req_is_wr and cpuif_req_stall_wr); + + ---------------------------------------------------------------------------- + -- Address Decode + ---------------------------------------------------------------------------- + process(all) + -- overload "=" in this scope to avoid lots of type casts + function "="(L: std_logic_vector; R: integer) return std_logic is + variable result : std_logic; + begin + result := '1' when unsigned(L) = R else '0'; + return result; + end; + begin + decoded_reg_strb.Hash_ID_Low <= cpuif_req_masked and (cpuif_addr = 16#0#); + decoded_reg_strb.Hash_ID_High <= cpuif_req_masked and (cpuif_addr = 16#4#); + decoded_reg_strb.MSK_Init <= cpuif_req_masked and (cpuif_addr = 16#8#); + decoded_reg_strb.MSK_Control <= cpuif_req_masked and (cpuif_addr = 16#C#); + decoded_reg_strb.MSK_Status <= cpuif_req_masked and (cpuif_addr = 16#10#); + decoded_reg_strb.Tx_Bit_Count <= cpuif_req_masked and (cpuif_addr = 16#14#); + decoded_reg_strb.Tx_Enable_Count <= cpuif_req_masked and (cpuif_addr = 16#18#); + decoded_reg_strb.Fb_FreqWord <= cpuif_req_masked and (cpuif_addr = 16#1C#); + decoded_reg_strb.TX_F1_FreqWord <= cpuif_req_masked and (cpuif_addr = 16#20#); + decoded_reg_strb.TX_F2_FreqWord <= cpuif_req_masked and (cpuif_addr = 16#24#); + decoded_reg_strb.RX_F1_FreqWord <= cpuif_req_masked and (cpuif_addr = 16#28#); + decoded_reg_strb.RX_F2_FreqWord <= cpuif_req_masked and (cpuif_addr = 16#2C#); + decoded_reg_strb.LPF_Config_0 <= cpuif_req_masked and (cpuif_addr = 16#30#); + decoded_reg_strb.LPF_Config_1 <= cpuif_req_masked and (cpuif_addr = 16#34#); + decoded_reg_strb.Tx_Data_Width <= cpuif_req_masked and (cpuif_addr = 16#38#); + decoded_reg_strb.Rx_Data_Width <= cpuif_req_masked and (cpuif_addr = 16#3C#); + decoded_reg_strb.PRBS_Control <= cpuif_req_masked and (cpuif_addr = 16#40#); + decoded_reg_strb.PRBS_Initial_State <= cpuif_req_masked and (cpuif_addr = 16#44#); + decoded_reg_strb.PRBS_Polynomial <= cpuif_req_masked and (cpuif_addr = 16#48#); + decoded_reg_strb.PRBS_Error_Mask <= cpuif_req_masked and (cpuif_addr = 16#4C#); + decoded_reg_strb.PRBS_Bit_Count <= cpuif_req_masked and (cpuif_addr = 16#50#); + decoded_reg_strb.PRBS_Error_Count <= cpuif_req_masked and (cpuif_addr = 16#54#); + decoded_reg_strb.LPF_Accum_F1 <= cpuif_req_masked and (cpuif_addr = 16#58#); + decoded_reg_strb.LPF_Accum_F2 <= cpuif_req_masked and (cpuif_addr = 16#5C#); + decoded_reg_strb.axis_xfer_count <= cpuif_req_masked and (cpuif_addr = 16#60#); + decoded_reg_strb.Rx_Sample_Discard <= cpuif_req_masked and (cpuif_addr = 16#64#); + decoded_reg_strb.LPF_Config_2 <= cpuif_req_masked and (cpuif_addr = 16#68#); + decoded_reg_strb.f1_nco_adjust <= cpuif_req_masked and (cpuif_addr = 16#6C#); + decoded_reg_strb.f2_nco_adjust <= cpuif_req_masked and (cpuif_addr = 16#70#); + decoded_reg_strb.f1_error <= cpuif_req_masked and (cpuif_addr = 16#74#); + decoded_reg_strb.f2_error <= cpuif_req_masked and (cpuif_addr = 16#78#); + decoded_reg_strb.Tx_Sync_Ctrl <= cpuif_req_masked and (cpuif_addr = 16#7C#); + decoded_reg_strb.Tx_Sync_Cnt <= cpuif_req_masked and (cpuif_addr = 16#80#); + decoded_reg_strb.lowpass_ema_alpha1 <= cpuif_req_masked and (cpuif_addr = 16#84#); + decoded_reg_strb.lowpass_ema_alpha2 <= cpuif_req_masked and (cpuif_addr = 16#88#); + decoded_reg_strb.rx_power <= cpuif_req_masked and (cpuif_addr = 16#8C#); + end process; + + -- Pass down signals to next stage + process(all) begin + decoded_req <= cpuif_req_masked; + decoded_req_is_wr <= cpuif_req_is_wr; + decoded_wr_data <= cpuif_wr_data; + decoded_wr_biten <= cpuif_wr_biten; + end process; + + ---------------------------------------------------------------------------- + -- Field logic + ---------------------------------------------------------------------------- + + -- Field: msk_top_regs.MSK_Init.txrxinit + process(all) + variable next_c: std_logic; + variable load_next_c: std_logic; + begin + next_c := field_storage.MSK_Init.txrxinit.value; + load_next_c := '0'; + if decoded_reg_strb.MSK_Init and decoded_req_is_wr then -- SW write + next_c := (field_storage.MSK_Init.txrxinit.value and not decoded_wr_biten(0)) or (decoded_wr_data(0) and decoded_wr_biten(0)); + load_next_c := '1'; + end if; + field_combo.MSK_Init.txrxinit.next_q <= next_c; + field_combo.MSK_Init.txrxinit.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.MSK_Init.txrxinit.value <= '1'; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.MSK_Init.txrxinit.value <= '1'; + else + if field_combo.MSK_Init.txrxinit.load_next then + field_storage.MSK_Init.txrxinit.value <= field_combo.MSK_Init.txrxinit.next_q; + end if; + end if; + end if; + end process; + hwif_out.MSK_Init.txrxinit.value <= field_storage.MSK_Init.txrxinit.value; + + -- Field: msk_top_regs.MSK_Init.txinit + process(all) + variable next_c: std_logic; + variable load_next_c: std_logic; + begin + next_c := field_storage.MSK_Init.txinit.value; + load_next_c := '0'; + if decoded_reg_strb.MSK_Init and decoded_req_is_wr then -- SW write + next_c := (field_storage.MSK_Init.txinit.value and not decoded_wr_biten(1)) or (decoded_wr_data(1) and decoded_wr_biten(1)); + load_next_c := '1'; + end if; + field_combo.MSK_Init.txinit.next_q <= next_c; + field_combo.MSK_Init.txinit.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.MSK_Init.txinit.value <= '1'; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.MSK_Init.txinit.value <= '1'; + else + if field_combo.MSK_Init.txinit.load_next then + field_storage.MSK_Init.txinit.value <= field_combo.MSK_Init.txinit.next_q; + end if; + end if; + end if; + end process; + hwif_out.MSK_Init.txinit.value <= field_storage.MSK_Init.txinit.value; + + -- Field: msk_top_regs.MSK_Init.rxinit + process(all) + variable next_c: std_logic; + variable load_next_c: std_logic; + begin + next_c := field_storage.MSK_Init.rxinit.value; + load_next_c := '0'; + if decoded_reg_strb.MSK_Init and decoded_req_is_wr then -- SW write + next_c := (field_storage.MSK_Init.rxinit.value and not decoded_wr_biten(2)) or (decoded_wr_data(2) and decoded_wr_biten(2)); + load_next_c := '1'; + end if; + field_combo.MSK_Init.rxinit.next_q <= next_c; + field_combo.MSK_Init.rxinit.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.MSK_Init.rxinit.value <= '1'; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.MSK_Init.rxinit.value <= '1'; + else + if field_combo.MSK_Init.rxinit.load_next then + field_storage.MSK_Init.rxinit.value <= field_combo.MSK_Init.rxinit.next_q; + end if; + end if; + end if; + end process; + hwif_out.MSK_Init.rxinit.value <= field_storage.MSK_Init.rxinit.value; + + -- Field: msk_top_regs.MSK_Control.ptt + process(all) + variable next_c: std_logic; + variable load_next_c: std_logic; + begin + next_c := field_storage.MSK_Control.ptt.value; + load_next_c := '0'; + if decoded_reg_strb.MSK_Control and decoded_req_is_wr then -- SW write + next_c := (field_storage.MSK_Control.ptt.value and not decoded_wr_biten(0)) or (decoded_wr_data(0) and decoded_wr_biten(0)); + load_next_c := '1'; + end if; + field_combo.MSK_Control.ptt.next_q <= next_c; + field_combo.MSK_Control.ptt.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.MSK_Control.ptt.value <= '0'; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.MSK_Control.ptt.value <= '0'; + else + if field_combo.MSK_Control.ptt.load_next then + field_storage.MSK_Control.ptt.value <= field_combo.MSK_Control.ptt.next_q; + end if; + end if; + end if; + end process; + hwif_out.MSK_Control.ptt.value <= field_storage.MSK_Control.ptt.value; + + -- Field: msk_top_regs.MSK_Control.loopback_ena + process(all) + variable next_c: std_logic; + variable load_next_c: std_logic; + begin + next_c := field_storage.MSK_Control.loopback_ena.value; + load_next_c := '0'; + if decoded_reg_strb.MSK_Control and decoded_req_is_wr then -- SW write + next_c := (field_storage.MSK_Control.loopback_ena.value and not decoded_wr_biten(1)) or (decoded_wr_data(1) and decoded_wr_biten(1)); + load_next_c := '1'; + end if; + field_combo.MSK_Control.loopback_ena.next_q <= next_c; + field_combo.MSK_Control.loopback_ena.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.MSK_Control.loopback_ena.value <= '0'; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.MSK_Control.loopback_ena.value <= '0'; + else + if field_combo.MSK_Control.loopback_ena.load_next then + field_storage.MSK_Control.loopback_ena.value <= field_combo.MSK_Control.loopback_ena.next_q; + end if; + end if; + end if; + end process; + hwif_out.MSK_Control.loopback_ena.value <= field_storage.MSK_Control.loopback_ena.value; + + -- Field: msk_top_regs.MSK_Control.rx_invert + process(all) + variable next_c: std_logic; + variable load_next_c: std_logic; + begin + next_c := field_storage.MSK_Control.rx_invert.value; + load_next_c := '0'; + if decoded_reg_strb.MSK_Control and decoded_req_is_wr then -- SW write + next_c := (field_storage.MSK_Control.rx_invert.value and not decoded_wr_biten(2)) or (decoded_wr_data(2) and decoded_wr_biten(2)); + load_next_c := '1'; + end if; + field_combo.MSK_Control.rx_invert.next_q <= next_c; + field_combo.MSK_Control.rx_invert.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.MSK_Control.rx_invert.value <= '0'; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.MSK_Control.rx_invert.value <= '0'; + else + if field_combo.MSK_Control.rx_invert.load_next then + field_storage.MSK_Control.rx_invert.value <= field_combo.MSK_Control.rx_invert.next_q; + end if; + end if; + end if; + end process; + hwif_out.MSK_Control.rx_invert.value <= field_storage.MSK_Control.rx_invert.value; + + -- Field: msk_top_regs.MSK_Control.clear_counts + process(all) + variable next_c: std_logic; + variable load_next_c: std_logic; + begin + next_c := field_storage.MSK_Control.clear_counts.value; + load_next_c := '0'; + if decoded_reg_strb.MSK_Control and decoded_req_is_wr then -- SW write + next_c := (field_storage.MSK_Control.clear_counts.value and not decoded_wr_biten(3)) or (decoded_wr_data(3) and decoded_wr_biten(3)); + load_next_c := '1'; + else -- singlepulse clears back to 0 + next_c := '0'; + load_next_c := '1'; + end if; + field_combo.MSK_Control.clear_counts.next_q <= next_c; + field_combo.MSK_Control.clear_counts.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.MSK_Control.clear_counts.value <= '0'; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.MSK_Control.clear_counts.value <= '0'; + else + if field_combo.MSK_Control.clear_counts.load_next then + field_storage.MSK_Control.clear_counts.value <= field_combo.MSK_Control.clear_counts.next_q; + end if; + end if; + end if; + end process; + hwif_out.MSK_Control.clear_counts.value <= field_storage.MSK_Control.clear_counts.value; + + -- Field: msk_top_regs.MSK_Control.diff_encoder_loopback + process(all) + variable next_c: std_logic; + variable load_next_c: std_logic; + begin + next_c := field_storage.MSK_Control.diff_encoder_loopback.value; + load_next_c := '0'; + if decoded_reg_strb.MSK_Control and decoded_req_is_wr then -- SW write + next_c := (field_storage.MSK_Control.diff_encoder_loopback.value and not decoded_wr_biten(4)) or (decoded_wr_data(4) and decoded_wr_biten(4)); + load_next_c := '1'; + end if; + field_combo.MSK_Control.diff_encoder_loopback.next_q <= next_c; + field_combo.MSK_Control.diff_encoder_loopback.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.MSK_Control.diff_encoder_loopback.value <= '0'; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.MSK_Control.diff_encoder_loopback.value <= '0'; + else + if field_combo.MSK_Control.diff_encoder_loopback.load_next then + field_storage.MSK_Control.diff_encoder_loopback.value <= field_combo.MSK_Control.diff_encoder_loopback.next_q; + end if; + end if; + end if; + end process; + hwif_out.MSK_Control.diff_encoder_loopback.value <= field_storage.MSK_Control.diff_encoder_loopback.value; + + -- Field: msk_top_regs.Fb_FreqWord.config_data + process(all) + variable next_c: std_logic_vector(31 downto 0); + variable load_next_c: std_logic; + begin + next_c := field_storage.Fb_FreqWord.config_data.value; + load_next_c := '0'; + if decoded_reg_strb.Fb_FreqWord and decoded_req_is_wr then -- SW write + next_c := (field_storage.Fb_FreqWord.config_data.value and not decoded_wr_biten(31 downto 0)) or (decoded_wr_data(31 downto 0) and decoded_wr_biten(31 downto 0)); + load_next_c := '1'; + end if; + field_combo.Fb_FreqWord.config_data.next_q <= next_c; + field_combo.Fb_FreqWord.config_data.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.Fb_FreqWord.config_data.value <= 32x"0"; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.Fb_FreqWord.config_data.value <= 32x"0"; + else + if field_combo.Fb_FreqWord.config_data.load_next then + field_storage.Fb_FreqWord.config_data.value <= field_combo.Fb_FreqWord.config_data.next_q; + end if; + end if; + end if; + end process; + hwif_out.Fb_FreqWord.config_data.value <= field_storage.Fb_FreqWord.config_data.value; + + -- Field: msk_top_regs.TX_F1_FreqWord.config_data + process(all) + variable next_c: std_logic_vector(31 downto 0); + variable load_next_c: std_logic; + begin + next_c := field_storage.TX_F1_FreqWord.config_data.value; + load_next_c := '0'; + if decoded_reg_strb.TX_F1_FreqWord and decoded_req_is_wr then -- SW write + next_c := (field_storage.TX_F1_FreqWord.config_data.value and not decoded_wr_biten(31 downto 0)) or (decoded_wr_data(31 downto 0) and decoded_wr_biten(31 downto 0)); + load_next_c := '1'; + end if; + field_combo.TX_F1_FreqWord.config_data.next_q <= next_c; + field_combo.TX_F1_FreqWord.config_data.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.TX_F1_FreqWord.config_data.value <= 32x"0"; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.TX_F1_FreqWord.config_data.value <= 32x"0"; + else + if field_combo.TX_F1_FreqWord.config_data.load_next then + field_storage.TX_F1_FreqWord.config_data.value <= field_combo.TX_F1_FreqWord.config_data.next_q; + end if; + end if; + end if; + end process; + hwif_out.TX_F1_FreqWord.config_data.value <= field_storage.TX_F1_FreqWord.config_data.value; + + -- Field: msk_top_regs.TX_F2_FreqWord.config_data + process(all) + variable next_c: std_logic_vector(31 downto 0); + variable load_next_c: std_logic; + begin + next_c := field_storage.TX_F2_FreqWord.config_data.value; + load_next_c := '0'; + if decoded_reg_strb.TX_F2_FreqWord and decoded_req_is_wr then -- SW write + next_c := (field_storage.TX_F2_FreqWord.config_data.value and not decoded_wr_biten(31 downto 0)) or (decoded_wr_data(31 downto 0) and decoded_wr_biten(31 downto 0)); + load_next_c := '1'; + end if; + field_combo.TX_F2_FreqWord.config_data.next_q <= next_c; + field_combo.TX_F2_FreqWord.config_data.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.TX_F2_FreqWord.config_data.value <= 32x"0"; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.TX_F2_FreqWord.config_data.value <= 32x"0"; + else + if field_combo.TX_F2_FreqWord.config_data.load_next then + field_storage.TX_F2_FreqWord.config_data.value <= field_combo.TX_F2_FreqWord.config_data.next_q; + end if; + end if; + end if; + end process; + hwif_out.TX_F2_FreqWord.config_data.value <= field_storage.TX_F2_FreqWord.config_data.value; + + -- Field: msk_top_regs.RX_F1_FreqWord.config_data + process(all) + variable next_c: std_logic_vector(31 downto 0); + variable load_next_c: std_logic; + begin + next_c := field_storage.RX_F1_FreqWord.config_data.value; + load_next_c := '0'; + if decoded_reg_strb.RX_F1_FreqWord and decoded_req_is_wr then -- SW write + next_c := (field_storage.RX_F1_FreqWord.config_data.value and not decoded_wr_biten(31 downto 0)) or (decoded_wr_data(31 downto 0) and decoded_wr_biten(31 downto 0)); + load_next_c := '1'; + end if; + field_combo.RX_F1_FreqWord.config_data.next_q <= next_c; + field_combo.RX_F1_FreqWord.config_data.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.RX_F1_FreqWord.config_data.value <= 32x"0"; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.RX_F1_FreqWord.config_data.value <= 32x"0"; + else + if field_combo.RX_F1_FreqWord.config_data.load_next then + field_storage.RX_F1_FreqWord.config_data.value <= field_combo.RX_F1_FreqWord.config_data.next_q; + end if; + end if; + end if; + end process; + hwif_out.RX_F1_FreqWord.config_data.value <= field_storage.RX_F1_FreqWord.config_data.value; + + -- Field: msk_top_regs.RX_F2_FreqWord.config_data + process(all) + variable next_c: std_logic_vector(31 downto 0); + variable load_next_c: std_logic; + begin + next_c := field_storage.RX_F2_FreqWord.config_data.value; + load_next_c := '0'; + if decoded_reg_strb.RX_F2_FreqWord and decoded_req_is_wr then -- SW write + next_c := (field_storage.RX_F2_FreqWord.config_data.value and not decoded_wr_biten(31 downto 0)) or (decoded_wr_data(31 downto 0) and decoded_wr_biten(31 downto 0)); + load_next_c := '1'; + end if; + field_combo.RX_F2_FreqWord.config_data.next_q <= next_c; + field_combo.RX_F2_FreqWord.config_data.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.RX_F2_FreqWord.config_data.value <= 32x"0"; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.RX_F2_FreqWord.config_data.value <= 32x"0"; + else + if field_combo.RX_F2_FreqWord.config_data.load_next then + field_storage.RX_F2_FreqWord.config_data.value <= field_combo.RX_F2_FreqWord.config_data.next_q; + end if; + end if; + end if; + end process; + hwif_out.RX_F2_FreqWord.config_data.value <= field_storage.RX_F2_FreqWord.config_data.value; + + -- Field: msk_top_regs.LPF_Config_0.lpf_freeze + process(all) + variable next_c: std_logic; + variable load_next_c: std_logic; + begin + next_c := field_storage.LPF_Config_0.lpf_freeze.value; + load_next_c := '0'; + if decoded_reg_strb.LPF_Config_0 and decoded_req_is_wr then -- SW write + next_c := (field_storage.LPF_Config_0.lpf_freeze.value and not decoded_wr_biten(0)) or (decoded_wr_data(0) and decoded_wr_biten(0)); + load_next_c := '1'; + end if; + field_combo.LPF_Config_0.lpf_freeze.next_q <= next_c; + field_combo.LPF_Config_0.lpf_freeze.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.LPF_Config_0.lpf_freeze.value <= '0'; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.LPF_Config_0.lpf_freeze.value <= '0'; + else + if field_combo.LPF_Config_0.lpf_freeze.load_next then + field_storage.LPF_Config_0.lpf_freeze.value <= field_combo.LPF_Config_0.lpf_freeze.next_q; + end if; + end if; + end if; + end process; + hwif_out.LPF_Config_0.lpf_freeze.value <= field_storage.LPF_Config_0.lpf_freeze.value; + + -- Field: msk_top_regs.LPF_Config_0.lpf_zero + process(all) + variable next_c: std_logic; + variable load_next_c: std_logic; + begin + next_c := field_storage.LPF_Config_0.lpf_zero.value; + load_next_c := '0'; + if decoded_reg_strb.LPF_Config_0 and decoded_req_is_wr then -- SW write + next_c := (field_storage.LPF_Config_0.lpf_zero.value and not decoded_wr_biten(1)) or (decoded_wr_data(1) and decoded_wr_biten(1)); + load_next_c := '1'; + end if; + field_combo.LPF_Config_0.lpf_zero.next_q <= next_c; + field_combo.LPF_Config_0.lpf_zero.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.LPF_Config_0.lpf_zero.value <= '0'; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.LPF_Config_0.lpf_zero.value <= '0'; + else + if field_combo.LPF_Config_0.lpf_zero.load_next then + field_storage.LPF_Config_0.lpf_zero.value <= field_combo.LPF_Config_0.lpf_zero.next_q; + end if; + end if; + end if; + end process; + hwif_out.LPF_Config_0.lpf_zero.value <= field_storage.LPF_Config_0.lpf_zero.value; + + -- Field: msk_top_regs.LPF_Config_0.prbs_reserved + process(all) + variable next_c: std_logic_vector(5 downto 0); + variable load_next_c: std_logic; + begin + next_c := field_storage.LPF_Config_0.prbs_reserved.value; + load_next_c := '0'; + if decoded_reg_strb.LPF_Config_0 and decoded_req_is_wr then -- SW write + next_c := (field_storage.LPF_Config_0.prbs_reserved.value and not decoded_wr_biten(7 downto 2)) or (decoded_wr_data(7 downto 2) and decoded_wr_biten(7 downto 2)); + load_next_c := '1'; + end if; + field_combo.LPF_Config_0.prbs_reserved.next_q <= next_c; + field_combo.LPF_Config_0.prbs_reserved.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.LPF_Config_0.prbs_reserved.value <= 6x"0"; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.LPF_Config_0.prbs_reserved.value <= 6x"0"; + else + if field_combo.LPF_Config_0.prbs_reserved.load_next then + field_storage.LPF_Config_0.prbs_reserved.value <= field_combo.LPF_Config_0.prbs_reserved.next_q; + end if; + end if; + end if; + end process; + hwif_out.LPF_Config_0.prbs_reserved.value <= field_storage.LPF_Config_0.prbs_reserved.value; + + -- Field: msk_top_regs.LPF_Config_0.lpf_alpha + process(all) + variable next_c: std_logic_vector(23 downto 0); + variable load_next_c: std_logic; + begin + next_c := field_storage.LPF_Config_0.lpf_alpha.value; + load_next_c := '0'; + if decoded_reg_strb.LPF_Config_0 and decoded_req_is_wr then -- SW write + next_c := (field_storage.LPF_Config_0.lpf_alpha.value and not decoded_wr_biten(31 downto 8)) or (decoded_wr_data(31 downto 8) and decoded_wr_biten(31 downto 8)); + load_next_c := '1'; + end if; + field_combo.LPF_Config_0.lpf_alpha.next_q <= next_c; + field_combo.LPF_Config_0.lpf_alpha.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.LPF_Config_0.lpf_alpha.value <= 24x"0"; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.LPF_Config_0.lpf_alpha.value <= 24x"0"; + else + if field_combo.LPF_Config_0.lpf_alpha.load_next then + field_storage.LPF_Config_0.lpf_alpha.value <= field_combo.LPF_Config_0.lpf_alpha.next_q; + end if; + end if; + end if; + end process; + hwif_out.LPF_Config_0.lpf_alpha.value <= field_storage.LPF_Config_0.lpf_alpha.value; + + -- Field: msk_top_regs.LPF_Config_1.i_gain + process(all) + variable next_c: std_logic_vector(23 downto 0); + variable load_next_c: std_logic; + begin + next_c := field_storage.LPF_Config_1.i_gain.value; + load_next_c := '0'; + if decoded_reg_strb.LPF_Config_1 and decoded_req_is_wr then -- SW write + next_c := (field_storage.LPF_Config_1.i_gain.value and not decoded_wr_biten(23 downto 0)) or (decoded_wr_data(23 downto 0) and decoded_wr_biten(23 downto 0)); + load_next_c := '1'; + end if; + field_combo.LPF_Config_1.i_gain.next_q <= next_c; + field_combo.LPF_Config_1.i_gain.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.LPF_Config_1.i_gain.value <= 24x"0"; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.LPF_Config_1.i_gain.value <= 24x"0"; + else + if field_combo.LPF_Config_1.i_gain.load_next then + field_storage.LPF_Config_1.i_gain.value <= field_combo.LPF_Config_1.i_gain.next_q; + end if; + end if; + end if; + end process; + hwif_out.LPF_Config_1.i_gain.value <= field_storage.LPF_Config_1.i_gain.value; + + -- Field: msk_top_regs.LPF_Config_1.i_shift + process(all) + variable next_c: std_logic_vector(7 downto 0); + variable load_next_c: std_logic; + begin + next_c := field_storage.LPF_Config_1.i_shift.value; + load_next_c := '0'; + if decoded_reg_strb.LPF_Config_1 and decoded_req_is_wr then -- SW write + next_c := (field_storage.LPF_Config_1.i_shift.value and not decoded_wr_biten(31 downto 24)) or (decoded_wr_data(31 downto 24) and decoded_wr_biten(31 downto 24)); + load_next_c := '1'; + end if; + field_combo.LPF_Config_1.i_shift.next_q <= next_c; + field_combo.LPF_Config_1.i_shift.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.LPF_Config_1.i_shift.value <= 8x"0"; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.LPF_Config_1.i_shift.value <= 8x"0"; + else + if field_combo.LPF_Config_1.i_shift.load_next then + field_storage.LPF_Config_1.i_shift.value <= field_combo.LPF_Config_1.i_shift.next_q; + end if; + end if; + end if; + end process; + hwif_out.LPF_Config_1.i_shift.value <= field_storage.LPF_Config_1.i_shift.value; + + -- Field: msk_top_regs.Tx_Data_Width.data_width + process(all) + variable next_c: std_logic_vector(7 downto 0); + variable load_next_c: std_logic; + begin + next_c := field_storage.Tx_Data_Width.data_width.value; + load_next_c := '0'; + if decoded_reg_strb.Tx_Data_Width and decoded_req_is_wr then -- SW write + next_c := (field_storage.Tx_Data_Width.data_width.value and not decoded_wr_biten(7 downto 0)) or (decoded_wr_data(7 downto 0) and decoded_wr_biten(7 downto 0)); + load_next_c := '1'; + end if; + field_combo.Tx_Data_Width.data_width.next_q <= next_c; + field_combo.Tx_Data_Width.data_width.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.Tx_Data_Width.data_width.value <= 8x"8"; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.Tx_Data_Width.data_width.value <= 8x"8"; + else + if field_combo.Tx_Data_Width.data_width.load_next then + field_storage.Tx_Data_Width.data_width.value <= field_combo.Tx_Data_Width.data_width.next_q; + end if; + end if; + end if; + end process; + hwif_out.Tx_Data_Width.data_width.value <= field_storage.Tx_Data_Width.data_width.value; + + -- Field: msk_top_regs.Rx_Data_Width.data_width + process(all) + variable next_c: std_logic_vector(7 downto 0); + variable load_next_c: std_logic; + begin + next_c := field_storage.Rx_Data_Width.data_width.value; + load_next_c := '0'; + if decoded_reg_strb.Rx_Data_Width and decoded_req_is_wr then -- SW write + next_c := (field_storage.Rx_Data_Width.data_width.value and not decoded_wr_biten(7 downto 0)) or (decoded_wr_data(7 downto 0) and decoded_wr_biten(7 downto 0)); + load_next_c := '1'; + end if; + field_combo.Rx_Data_Width.data_width.next_q <= next_c; + field_combo.Rx_Data_Width.data_width.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.Rx_Data_Width.data_width.value <= 8x"8"; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.Rx_Data_Width.data_width.value <= 8x"8"; + else + if field_combo.Rx_Data_Width.data_width.load_next then + field_storage.Rx_Data_Width.data_width.value <= field_combo.Rx_Data_Width.data_width.next_q; + end if; + end if; + end if; + end process; + hwif_out.Rx_Data_Width.data_width.value <= field_storage.Rx_Data_Width.data_width.value; + + -- Field: msk_top_regs.PRBS_Control.prbs_sel + process(all) + variable next_c: std_logic; + variable load_next_c: std_logic; + begin + next_c := field_storage.PRBS_Control.prbs_sel.value; + load_next_c := '0'; + if decoded_reg_strb.PRBS_Control and decoded_req_is_wr then -- SW write + next_c := (field_storage.PRBS_Control.prbs_sel.value and not decoded_wr_biten(0)) or (decoded_wr_data(0) and decoded_wr_biten(0)); + load_next_c := '1'; + end if; + field_combo.PRBS_Control.prbs_sel.next_q <= next_c; + field_combo.PRBS_Control.prbs_sel.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.PRBS_Control.prbs_sel.value <= '0'; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.PRBS_Control.prbs_sel.value <= '0'; + else + if field_combo.PRBS_Control.prbs_sel.load_next then + field_storage.PRBS_Control.prbs_sel.value <= field_combo.PRBS_Control.prbs_sel.next_q; + end if; + end if; + end if; + end process; + hwif_out.PRBS_Control.prbs_sel.value <= field_storage.PRBS_Control.prbs_sel.value; + + -- Field: msk_top_regs.PRBS_Control.prbs_error_insert + process(all) + variable next_c: std_logic; + variable load_next_c: std_logic; + begin + next_c := field_storage.PRBS_Control.prbs_error_insert.value; + load_next_c := '0'; + if decoded_reg_strb.PRBS_Control and decoded_req_is_wr then -- SW write + next_c := (field_storage.PRBS_Control.prbs_error_insert.value and not decoded_wr_biten(1)) or (decoded_wr_data(1) and decoded_wr_biten(1)); + load_next_c := '1'; + else -- singlepulse clears back to 0 + next_c := '0'; + load_next_c := '1'; + end if; + field_combo.PRBS_Control.prbs_error_insert.next_q <= next_c; + field_combo.PRBS_Control.prbs_error_insert.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.PRBS_Control.prbs_error_insert.value <= '0'; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.PRBS_Control.prbs_error_insert.value <= '0'; + else + if field_combo.PRBS_Control.prbs_error_insert.load_next then + field_storage.PRBS_Control.prbs_error_insert.value <= field_combo.PRBS_Control.prbs_error_insert.next_q; + end if; + end if; + end if; + end process; + hwif_out.PRBS_Control.prbs_error_insert.value <= field_storage.PRBS_Control.prbs_error_insert.value; + + -- Field: msk_top_regs.PRBS_Control.prbs_clear + process(all) + variable next_c: std_logic; + variable load_next_c: std_logic; + begin + next_c := field_storage.PRBS_Control.prbs_clear.value; + load_next_c := '0'; + if decoded_reg_strb.PRBS_Control and decoded_req_is_wr then -- SW write + next_c := (field_storage.PRBS_Control.prbs_clear.value and not decoded_wr_biten(2)) or (decoded_wr_data(2) and decoded_wr_biten(2)); + load_next_c := '1'; + else -- singlepulse clears back to 0 + next_c := '0'; + load_next_c := '1'; + end if; + field_combo.PRBS_Control.prbs_clear.next_q <= next_c; + field_combo.PRBS_Control.prbs_clear.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.PRBS_Control.prbs_clear.value <= '0'; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.PRBS_Control.prbs_clear.value <= '0'; + else + if field_combo.PRBS_Control.prbs_clear.load_next then + field_storage.PRBS_Control.prbs_clear.value <= field_combo.PRBS_Control.prbs_clear.next_q; + end if; + end if; + end if; + end process; + hwif_out.PRBS_Control.prbs_clear.value <= field_storage.PRBS_Control.prbs_clear.value; + + -- Field: msk_top_regs.PRBS_Control.prbs_manual_sync + process(all) + variable next_c: std_logic; + variable load_next_c: std_logic; + begin + next_c := field_storage.PRBS_Control.prbs_manual_sync.value; + load_next_c := '0'; + if decoded_reg_strb.PRBS_Control and decoded_req_is_wr then -- SW write + next_c := (field_storage.PRBS_Control.prbs_manual_sync.value and not decoded_wr_biten(3)) or (decoded_wr_data(3) and decoded_wr_biten(3)); + load_next_c := '1'; + else -- singlepulse clears back to 0 + next_c := '0'; + load_next_c := '1'; + end if; + field_combo.PRBS_Control.prbs_manual_sync.next_q <= next_c; + field_combo.PRBS_Control.prbs_manual_sync.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.PRBS_Control.prbs_manual_sync.value <= '0'; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.PRBS_Control.prbs_manual_sync.value <= '0'; + else + if field_combo.PRBS_Control.prbs_manual_sync.load_next then + field_storage.PRBS_Control.prbs_manual_sync.value <= field_combo.PRBS_Control.prbs_manual_sync.next_q; + end if; + end if; + end if; + end process; + hwif_out.PRBS_Control.prbs_manual_sync.value <= field_storage.PRBS_Control.prbs_manual_sync.value; + + -- Field: msk_top_regs.PRBS_Control.prbs_reserved + process(all) + variable next_c: std_logic_vector(11 downto 0); + variable load_next_c: std_logic; + begin + next_c := field_storage.PRBS_Control.prbs_reserved.value; + load_next_c := '0'; + if decoded_reg_strb.PRBS_Control and decoded_req_is_wr then -- SW write + next_c := (field_storage.PRBS_Control.prbs_reserved.value and not decoded_wr_biten(15 downto 4)) or (decoded_wr_data(15 downto 4) and decoded_wr_biten(15 downto 4)); + load_next_c := '1'; + end if; + field_combo.PRBS_Control.prbs_reserved.next_q <= next_c; + field_combo.PRBS_Control.prbs_reserved.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.PRBS_Control.prbs_reserved.value <= 12x"0"; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.PRBS_Control.prbs_reserved.value <= 12x"0"; + else + if field_combo.PRBS_Control.prbs_reserved.load_next then + field_storage.PRBS_Control.prbs_reserved.value <= field_combo.PRBS_Control.prbs_reserved.next_q; + end if; + end if; + end if; + end process; + hwif_out.PRBS_Control.prbs_reserved.value <= field_storage.PRBS_Control.prbs_reserved.value; + + -- Field: msk_top_regs.PRBS_Control.prbs_sync_threshold + process(all) + variable next_c: std_logic_vector(15 downto 0); + variable load_next_c: std_logic; + begin + next_c := field_storage.PRBS_Control.prbs_sync_threshold.value; + load_next_c := '0'; + if decoded_reg_strb.PRBS_Control and decoded_req_is_wr then -- SW write + next_c := (field_storage.PRBS_Control.prbs_sync_threshold.value and not decoded_wr_biten(31 downto 16)) or (decoded_wr_data(31 downto 16) and decoded_wr_biten(31 downto 16)); + load_next_c := '1'; + end if; + field_combo.PRBS_Control.prbs_sync_threshold.next_q <= next_c; + field_combo.PRBS_Control.prbs_sync_threshold.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.PRBS_Control.prbs_sync_threshold.value <= 16x"0"; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.PRBS_Control.prbs_sync_threshold.value <= 16x"0"; + else + if field_combo.PRBS_Control.prbs_sync_threshold.load_next then + field_storage.PRBS_Control.prbs_sync_threshold.value <= field_combo.PRBS_Control.prbs_sync_threshold.next_q; + end if; + end if; + end if; + end process; + hwif_out.PRBS_Control.prbs_sync_threshold.value <= field_storage.PRBS_Control.prbs_sync_threshold.value; + + -- Field: msk_top_regs.PRBS_Initial_State.config_data + process(all) + variable next_c: std_logic_vector(31 downto 0); + variable load_next_c: std_logic; + begin + next_c := field_storage.PRBS_Initial_State.config_data.value; + load_next_c := '0'; + if decoded_reg_strb.PRBS_Initial_State and decoded_req_is_wr then -- SW write + next_c := (field_storage.PRBS_Initial_State.config_data.value and not decoded_wr_biten(31 downto 0)) or (decoded_wr_data(31 downto 0) and decoded_wr_biten(31 downto 0)); + load_next_c := '1'; + end if; + field_combo.PRBS_Initial_State.config_data.next_q <= next_c; + field_combo.PRBS_Initial_State.config_data.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.PRBS_Initial_State.config_data.value <= 32x"0"; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.PRBS_Initial_State.config_data.value <= 32x"0"; + else + if field_combo.PRBS_Initial_State.config_data.load_next then + field_storage.PRBS_Initial_State.config_data.value <= field_combo.PRBS_Initial_State.config_data.next_q; + end if; + end if; + end if; + end process; + hwif_out.PRBS_Initial_State.config_data.value <= field_storage.PRBS_Initial_State.config_data.value; + + -- Field: msk_top_regs.PRBS_Polynomial.config_data + process(all) + variable next_c: std_logic_vector(31 downto 0); + variable load_next_c: std_logic; + begin + next_c := field_storage.PRBS_Polynomial.config_data.value; + load_next_c := '0'; + if decoded_reg_strb.PRBS_Polynomial and decoded_req_is_wr then -- SW write + next_c := (field_storage.PRBS_Polynomial.config_data.value and not decoded_wr_biten(31 downto 0)) or (decoded_wr_data(31 downto 0) and decoded_wr_biten(31 downto 0)); + load_next_c := '1'; + end if; + field_combo.PRBS_Polynomial.config_data.next_q <= next_c; + field_combo.PRBS_Polynomial.config_data.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.PRBS_Polynomial.config_data.value <= 32x"0"; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.PRBS_Polynomial.config_data.value <= 32x"0"; + else + if field_combo.PRBS_Polynomial.config_data.load_next then + field_storage.PRBS_Polynomial.config_data.value <= field_combo.PRBS_Polynomial.config_data.next_q; + end if; + end if; + end if; + end process; + hwif_out.PRBS_Polynomial.config_data.value <= field_storage.PRBS_Polynomial.config_data.value; + + -- Field: msk_top_regs.PRBS_Error_Mask.config_data + process(all) + variable next_c: std_logic_vector(31 downto 0); + variable load_next_c: std_logic; + begin + next_c := field_storage.PRBS_Error_Mask.config_data.value; + load_next_c := '0'; + if decoded_reg_strb.PRBS_Error_Mask and decoded_req_is_wr then -- SW write + next_c := (field_storage.PRBS_Error_Mask.config_data.value and not decoded_wr_biten(31 downto 0)) or (decoded_wr_data(31 downto 0) and decoded_wr_biten(31 downto 0)); + load_next_c := '1'; + end if; + field_combo.PRBS_Error_Mask.config_data.next_q <= next_c; + field_combo.PRBS_Error_Mask.config_data.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.PRBS_Error_Mask.config_data.value <= 32x"0"; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.PRBS_Error_Mask.config_data.value <= 32x"0"; + else + if field_combo.PRBS_Error_Mask.config_data.load_next then + field_storage.PRBS_Error_Mask.config_data.value <= field_combo.PRBS_Error_Mask.config_data.next_q; + end if; + end if; + end if; + end process; + hwif_out.PRBS_Error_Mask.config_data.value <= field_storage.PRBS_Error_Mask.config_data.value; + + -- Field: msk_top_regs.Rx_Sample_Discard.rx_sample_discard + process(all) + variable next_c: std_logic_vector(7 downto 0); + variable load_next_c: std_logic; + begin + next_c := field_storage.Rx_Sample_Discard.rx_sample_discard.value; + load_next_c := '0'; + if decoded_reg_strb.Rx_Sample_Discard and decoded_req_is_wr then -- SW write + next_c := (field_storage.Rx_Sample_Discard.rx_sample_discard.value and not decoded_wr_biten(7 downto 0)) or (decoded_wr_data(7 downto 0) and decoded_wr_biten(7 downto 0)); + load_next_c := '1'; + end if; + field_combo.Rx_Sample_Discard.rx_sample_discard.next_q <= next_c; + field_combo.Rx_Sample_Discard.rx_sample_discard.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.Rx_Sample_Discard.rx_sample_discard.value <= 8x"0"; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.Rx_Sample_Discard.rx_sample_discard.value <= 8x"0"; + else + if field_combo.Rx_Sample_Discard.rx_sample_discard.load_next then + field_storage.Rx_Sample_Discard.rx_sample_discard.value <= field_combo.Rx_Sample_Discard.rx_sample_discard.next_q; + end if; + end if; + end if; + end process; + hwif_out.Rx_Sample_Discard.rx_sample_discard.value <= field_storage.Rx_Sample_Discard.rx_sample_discard.value; + + -- Field: msk_top_regs.Rx_Sample_Discard.rx_nco_discard + process(all) + variable next_c: std_logic_vector(7 downto 0); + variable load_next_c: std_logic; + begin + next_c := field_storage.Rx_Sample_Discard.rx_nco_discard.value; + load_next_c := '0'; + if decoded_reg_strb.Rx_Sample_Discard and decoded_req_is_wr then -- SW write + next_c := (field_storage.Rx_Sample_Discard.rx_nco_discard.value and not decoded_wr_biten(15 downto 8)) or (decoded_wr_data(15 downto 8) and decoded_wr_biten(15 downto 8)); + load_next_c := '1'; + end if; + field_combo.Rx_Sample_Discard.rx_nco_discard.next_q <= next_c; + field_combo.Rx_Sample_Discard.rx_nco_discard.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.Rx_Sample_Discard.rx_nco_discard.value <= 8x"0"; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.Rx_Sample_Discard.rx_nco_discard.value <= 8x"0"; + else + if field_combo.Rx_Sample_Discard.rx_nco_discard.load_next then + field_storage.Rx_Sample_Discard.rx_nco_discard.value <= field_combo.Rx_Sample_Discard.rx_nco_discard.next_q; + end if; + end if; + end if; + end process; + hwif_out.Rx_Sample_Discard.rx_nco_discard.value <= field_storage.Rx_Sample_Discard.rx_nco_discard.value; + + -- Field: msk_top_regs.LPF_Config_2.p_gain + process(all) + variable next_c: std_logic_vector(23 downto 0); + variable load_next_c: std_logic; + begin + next_c := field_storage.LPF_Config_2.p_gain.value; + load_next_c := '0'; + if decoded_reg_strb.LPF_Config_2 and decoded_req_is_wr then -- SW write + next_c := (field_storage.LPF_Config_2.p_gain.value and not decoded_wr_biten(23 downto 0)) or (decoded_wr_data(23 downto 0) and decoded_wr_biten(23 downto 0)); + load_next_c := '1'; + end if; + field_combo.LPF_Config_2.p_gain.next_q <= next_c; + field_combo.LPF_Config_2.p_gain.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.LPF_Config_2.p_gain.value <= 24x"0"; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.LPF_Config_2.p_gain.value <= 24x"0"; + else + if field_combo.LPF_Config_2.p_gain.load_next then + field_storage.LPF_Config_2.p_gain.value <= field_combo.LPF_Config_2.p_gain.next_q; + end if; + end if; + end if; + end process; + hwif_out.LPF_Config_2.p_gain.value <= field_storage.LPF_Config_2.p_gain.value; + + -- Field: msk_top_regs.LPF_Config_2.p_shift + process(all) + variable next_c: std_logic_vector(7 downto 0); + variable load_next_c: std_logic; + begin + next_c := field_storage.LPF_Config_2.p_shift.value; + load_next_c := '0'; + if decoded_reg_strb.LPF_Config_2 and decoded_req_is_wr then -- SW write + next_c := (field_storage.LPF_Config_2.p_shift.value and not decoded_wr_biten(31 downto 24)) or (decoded_wr_data(31 downto 24) and decoded_wr_biten(31 downto 24)); + load_next_c := '1'; + end if; + field_combo.LPF_Config_2.p_shift.next_q <= next_c; + field_combo.LPF_Config_2.p_shift.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.LPF_Config_2.p_shift.value <= 8x"0"; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.LPF_Config_2.p_shift.value <= 8x"0"; + else + if field_combo.LPF_Config_2.p_shift.load_next then + field_storage.LPF_Config_2.p_shift.value <= field_combo.LPF_Config_2.p_shift.next_q; + end if; + end if; + end if; + end process; + hwif_out.LPF_Config_2.p_shift.value <= field_storage.LPF_Config_2.p_shift.value; + + -- Field: msk_top_regs.Tx_Sync_Ctrl.tx_sync_ena + process(all) + variable next_c: std_logic; + variable load_next_c: std_logic; + begin + next_c := field_storage.Tx_Sync_Ctrl.tx_sync_ena.value; + load_next_c := '0'; + if decoded_reg_strb.Tx_Sync_Ctrl and decoded_req_is_wr then -- SW write + next_c := (field_storage.Tx_Sync_Ctrl.tx_sync_ena.value and not decoded_wr_biten(0)) or (decoded_wr_data(0) and decoded_wr_biten(0)); + load_next_c := '1'; + end if; + field_combo.Tx_Sync_Ctrl.tx_sync_ena.next_q <= next_c; + field_combo.Tx_Sync_Ctrl.tx_sync_ena.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.Tx_Sync_Ctrl.tx_sync_ena.value <= '0'; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.Tx_Sync_Ctrl.tx_sync_ena.value <= '0'; + else + if field_combo.Tx_Sync_Ctrl.tx_sync_ena.load_next then + field_storage.Tx_Sync_Ctrl.tx_sync_ena.value <= field_combo.Tx_Sync_Ctrl.tx_sync_ena.next_q; + end if; + end if; + end if; + end process; + hwif_out.Tx_Sync_Ctrl.tx_sync_ena.value <= field_storage.Tx_Sync_Ctrl.tx_sync_ena.value; + + -- Field: msk_top_regs.Tx_Sync_Ctrl.tx_sync_force + process(all) + variable next_c: std_logic; + variable load_next_c: std_logic; + begin + next_c := field_storage.Tx_Sync_Ctrl.tx_sync_force.value; + load_next_c := '0'; + if decoded_reg_strb.Tx_Sync_Ctrl and decoded_req_is_wr then -- SW write + next_c := (field_storage.Tx_Sync_Ctrl.tx_sync_force.value and not decoded_wr_biten(1)) or (decoded_wr_data(1) and decoded_wr_biten(1)); + load_next_c := '1'; + end if; + field_combo.Tx_Sync_Ctrl.tx_sync_force.next_q <= next_c; + field_combo.Tx_Sync_Ctrl.tx_sync_force.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.Tx_Sync_Ctrl.tx_sync_force.value <= '0'; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.Tx_Sync_Ctrl.tx_sync_force.value <= '0'; + else + if field_combo.Tx_Sync_Ctrl.tx_sync_force.load_next then + field_storage.Tx_Sync_Ctrl.tx_sync_force.value <= field_combo.Tx_Sync_Ctrl.tx_sync_force.next_q; + end if; + end if; + end if; + end process; + hwif_out.Tx_Sync_Ctrl.tx_sync_force.value <= field_storage.Tx_Sync_Ctrl.tx_sync_force.value; + + -- Field: msk_top_regs.Tx_Sync_Ctrl.tx_sync_f1 + process(all) + variable next_c: std_logic; + variable load_next_c: std_logic; + begin + next_c := field_storage.Tx_Sync_Ctrl.tx_sync_f1.value; + load_next_c := '0'; + if decoded_reg_strb.Tx_Sync_Ctrl and decoded_req_is_wr then -- SW write + next_c := (field_storage.Tx_Sync_Ctrl.tx_sync_f1.value and not decoded_wr_biten(2)) or (decoded_wr_data(2) and decoded_wr_biten(2)); + load_next_c := '1'; + end if; + field_combo.Tx_Sync_Ctrl.tx_sync_f1.next_q <= next_c; + field_combo.Tx_Sync_Ctrl.tx_sync_f1.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.Tx_Sync_Ctrl.tx_sync_f1.value <= '0'; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.Tx_Sync_Ctrl.tx_sync_f1.value <= '0'; + else + if field_combo.Tx_Sync_Ctrl.tx_sync_f1.load_next then + field_storage.Tx_Sync_Ctrl.tx_sync_f1.value <= field_combo.Tx_Sync_Ctrl.tx_sync_f1.next_q; + end if; + end if; + end if; + end process; + hwif_out.Tx_Sync_Ctrl.tx_sync_f1.value <= field_storage.Tx_Sync_Ctrl.tx_sync_f1.value; + + -- Field: msk_top_regs.Tx_Sync_Ctrl.tx_sync_f2 + process(all) + variable next_c: std_logic; + variable load_next_c: std_logic; + begin + next_c := field_storage.Tx_Sync_Ctrl.tx_sync_f2.value; + load_next_c := '0'; + if decoded_reg_strb.Tx_Sync_Ctrl and decoded_req_is_wr then -- SW write + next_c := (field_storage.Tx_Sync_Ctrl.tx_sync_f2.value and not decoded_wr_biten(3)) or (decoded_wr_data(3) and decoded_wr_biten(3)); + load_next_c := '1'; + end if; + field_combo.Tx_Sync_Ctrl.tx_sync_f2.next_q <= next_c; + field_combo.Tx_Sync_Ctrl.tx_sync_f2.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.Tx_Sync_Ctrl.tx_sync_f2.value <= '0'; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.Tx_Sync_Ctrl.tx_sync_f2.value <= '0'; + else + if field_combo.Tx_Sync_Ctrl.tx_sync_f2.load_next then + field_storage.Tx_Sync_Ctrl.tx_sync_f2.value <= field_combo.Tx_Sync_Ctrl.tx_sync_f2.next_q; + end if; + end if; + end if; + end process; + hwif_out.Tx_Sync_Ctrl.tx_sync_f2.value <= field_storage.Tx_Sync_Ctrl.tx_sync_f2.value; + + -- Field: msk_top_regs.Tx_Sync_Cnt.tx_sync_cnt + process(all) + variable next_c: std_logic_vector(23 downto 0); + variable load_next_c: std_logic; + begin + next_c := field_storage.Tx_Sync_Cnt.tx_sync_cnt.value; + load_next_c := '0'; + if decoded_reg_strb.Tx_Sync_Cnt and decoded_req_is_wr then -- SW write + next_c := (field_storage.Tx_Sync_Cnt.tx_sync_cnt.value and not decoded_wr_biten(23 downto 0)) or (decoded_wr_data(23 downto 0) and decoded_wr_biten(23 downto 0)); + load_next_c := '1'; + end if; + field_combo.Tx_Sync_Cnt.tx_sync_cnt.next_q <= next_c; + field_combo.Tx_Sync_Cnt.tx_sync_cnt.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.Tx_Sync_Cnt.tx_sync_cnt.value <= 24x"0"; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.Tx_Sync_Cnt.tx_sync_cnt.value <= 24x"0"; + else + if field_combo.Tx_Sync_Cnt.tx_sync_cnt.load_next then + field_storage.Tx_Sync_Cnt.tx_sync_cnt.value <= field_combo.Tx_Sync_Cnt.tx_sync_cnt.next_q; + end if; + end if; + end if; + end process; + hwif_out.Tx_Sync_Cnt.tx_sync_cnt.value <= field_storage.Tx_Sync_Cnt.tx_sync_cnt.value; + + -- Field: msk_top_regs.lowpass_ema_alpha1.alpha + process(all) + variable next_c: std_logic_vector(17 downto 0); + variable load_next_c: std_logic; + begin + next_c := field_storage.lowpass_ema_alpha1.alpha.value; + load_next_c := '0'; + if decoded_reg_strb.lowpass_ema_alpha1 and decoded_req_is_wr then -- SW write + next_c := (field_storage.lowpass_ema_alpha1.alpha.value and not decoded_wr_biten(17 downto 0)) or (decoded_wr_data(17 downto 0) and decoded_wr_biten(17 downto 0)); + load_next_c := '1'; + end if; + field_combo.lowpass_ema_alpha1.alpha.next_q <= next_c; + field_combo.lowpass_ema_alpha1.alpha.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.lowpass_ema_alpha1.alpha.value <= 18x"0"; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.lowpass_ema_alpha1.alpha.value <= 18x"0"; + else + if field_combo.lowpass_ema_alpha1.alpha.load_next then + field_storage.lowpass_ema_alpha1.alpha.value <= field_combo.lowpass_ema_alpha1.alpha.next_q; + end if; + end if; + end if; + end process; + hwif_out.lowpass_ema_alpha1.alpha.value <= field_storage.lowpass_ema_alpha1.alpha.value; + + -- Field: msk_top_regs.lowpass_ema_alpha2.alpha + process(all) + variable next_c: std_logic_vector(17 downto 0); + variable load_next_c: std_logic; + begin + next_c := field_storage.lowpass_ema_alpha2.alpha.value; + load_next_c := '0'; + if decoded_reg_strb.lowpass_ema_alpha2 and decoded_req_is_wr then -- SW write + next_c := (field_storage.lowpass_ema_alpha2.alpha.value and not decoded_wr_biten(17 downto 0)) or (decoded_wr_data(17 downto 0) and decoded_wr_biten(17 downto 0)); + load_next_c := '1'; + end if; + field_combo.lowpass_ema_alpha2.alpha.next_q <= next_c; + field_combo.lowpass_ema_alpha2.alpha.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.lowpass_ema_alpha2.alpha.value <= 18x"0"; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.lowpass_ema_alpha2.alpha.value <= 18x"0"; + else + if field_combo.lowpass_ema_alpha2.alpha.load_next then + field_storage.lowpass_ema_alpha2.alpha.value <= field_combo.lowpass_ema_alpha2.alpha.next_q; + end if; + end if; + end if; + end process; + hwif_out.lowpass_ema_alpha2.alpha.value <= field_storage.lowpass_ema_alpha2.alpha.value; + + ---------------------------------------------------------------------------- + -- Write response + ---------------------------------------------------------------------------- + cpuif_wr_ack <= decoded_req and decoded_req_is_wr; + -- Writes are always granted with no error response + cpuif_wr_err <= '0'; + + ---------------------------------------------------------------------------- + -- Readback + ---------------------------------------------------------------------------- + + -- Assign readback values to a flattened array + readback_array(0)(31 downto 0) <= 32x"AAAA5555" when (decoded_reg_strb.Hash_ID_Low and not decoded_req_is_wr) else (others => '0'); + readback_array(1)(31 downto 0) <= 32x"5555AAAA" when (decoded_reg_strb.Hash_ID_High and not decoded_req_is_wr) else (others => '0'); + readback_array(2)(0 downto 0) <= to_std_logic_vector(field_storage.MSK_Init.txrxinit.value) when (decoded_reg_strb.MSK_Init and not decoded_req_is_wr) else (others => '0'); + readback_array(2)(1 downto 1) <= to_std_logic_vector(field_storage.MSK_Init.txinit.value) when (decoded_reg_strb.MSK_Init and not decoded_req_is_wr) else (others => '0'); + readback_array(2)(2 downto 2) <= to_std_logic_vector(field_storage.MSK_Init.rxinit.value) when (decoded_reg_strb.MSK_Init and not decoded_req_is_wr) else (others => '0'); + readback_array(2)(31 downto 3) <= (others => '0'); + readback_array(3)(0 downto 0) <= to_std_logic_vector(field_storage.MSK_Control.ptt.value) when (decoded_reg_strb.MSK_Control and not decoded_req_is_wr) else (others => '0'); + readback_array(3)(1 downto 1) <= to_std_logic_vector(field_storage.MSK_Control.loopback_ena.value) when (decoded_reg_strb.MSK_Control and not decoded_req_is_wr) else (others => '0'); + readback_array(3)(2 downto 2) <= to_std_logic_vector(field_storage.MSK_Control.rx_invert.value) when (decoded_reg_strb.MSK_Control and not decoded_req_is_wr) else (others => '0'); + readback_array(3)(3 downto 3) <= to_std_logic_vector(field_storage.MSK_Control.clear_counts.value) when (decoded_reg_strb.MSK_Control and not decoded_req_is_wr) else (others => '0'); + readback_array(3)(4 downto 4) <= to_std_logic_vector(field_storage.MSK_Control.diff_encoder_loopback.value) when (decoded_reg_strb.MSK_Control and not decoded_req_is_wr) else (others => '0'); + readback_array(3)(31 downto 5) <= (others => '0'); + readback_array(4)(0 downto 0) <= to_std_logic_vector(hwif_in.MSK_Status.demod_sync_lock.next_q) when (decoded_reg_strb.MSK_Status and not decoded_req_is_wr) else (others => '0'); + readback_array(4)(1 downto 1) <= to_std_logic_vector(hwif_in.MSK_Status.tx_enable.next_q) when (decoded_reg_strb.MSK_Status and not decoded_req_is_wr) else (others => '0'); + readback_array(4)(2 downto 2) <= to_std_logic_vector(hwif_in.MSK_Status.rx_enable.next_q) when (decoded_reg_strb.MSK_Status and not decoded_req_is_wr) else (others => '0'); + readback_array(4)(3 downto 3) <= to_std_logic_vector(hwif_in.MSK_Status.tx_axis_valid.next_q) when (decoded_reg_strb.MSK_Status and not decoded_req_is_wr) else (others => '0'); + readback_array(4)(31 downto 4) <= (others => '0'); + readback_array(5)(31 downto 0) <= hwif_in.Tx_Bit_Count.tx_bit_counter.next_q when (decoded_reg_strb.Tx_Bit_Count and not decoded_req_is_wr) else (others => '0'); + readback_array(6)(31 downto 0) <= hwif_in.Tx_Enable_Count.tx_ena_counter.next_q when (decoded_reg_strb.Tx_Enable_Count and not decoded_req_is_wr) else (others => '0'); + readback_array(7)(31 downto 0) <= field_storage.Fb_FreqWord.config_data.value when (decoded_reg_strb.Fb_FreqWord and not decoded_req_is_wr) else (others => '0'); + readback_array(8)(31 downto 0) <= field_storage.TX_F1_FreqWord.config_data.value when (decoded_reg_strb.TX_F1_FreqWord and not decoded_req_is_wr) else (others => '0'); + readback_array(9)(31 downto 0) <= field_storage.TX_F2_FreqWord.config_data.value when (decoded_reg_strb.TX_F2_FreqWord and not decoded_req_is_wr) else (others => '0'); + readback_array(10)(31 downto 0) <= field_storage.RX_F1_FreqWord.config_data.value when (decoded_reg_strb.RX_F1_FreqWord and not decoded_req_is_wr) else (others => '0'); + readback_array(11)(31 downto 0) <= field_storage.RX_F2_FreqWord.config_data.value when (decoded_reg_strb.RX_F2_FreqWord and not decoded_req_is_wr) else (others => '0'); + readback_array(12)(0 downto 0) <= to_std_logic_vector(field_storage.LPF_Config_0.lpf_freeze.value) when (decoded_reg_strb.LPF_Config_0 and not decoded_req_is_wr) else (others => '0'); + readback_array(12)(1 downto 1) <= to_std_logic_vector(field_storage.LPF_Config_0.lpf_zero.value) when (decoded_reg_strb.LPF_Config_0 and not decoded_req_is_wr) else (others => '0'); + readback_array(12)(7 downto 2) <= field_storage.LPF_Config_0.prbs_reserved.value when (decoded_reg_strb.LPF_Config_0 and not decoded_req_is_wr) else (others => '0'); + readback_array(12)(31 downto 8) <= field_storage.LPF_Config_0.lpf_alpha.value when (decoded_reg_strb.LPF_Config_0 and not decoded_req_is_wr) else (others => '0'); + readback_array(13)(23 downto 0) <= field_storage.LPF_Config_1.i_gain.value when (decoded_reg_strb.LPF_Config_1 and not decoded_req_is_wr) else (others => '0'); + readback_array(13)(31 downto 24) <= field_storage.LPF_Config_1.i_shift.value when (decoded_reg_strb.LPF_Config_1 and not decoded_req_is_wr) else (others => '0'); + readback_array(14)(7 downto 0) <= field_storage.Tx_Data_Width.data_width.value when (decoded_reg_strb.Tx_Data_Width and not decoded_req_is_wr) else (others => '0'); + readback_array(14)(31 downto 8) <= (others => '0'); + readback_array(15)(7 downto 0) <= field_storage.Rx_Data_Width.data_width.value when (decoded_reg_strb.Rx_Data_Width and not decoded_req_is_wr) else (others => '0'); + readback_array(15)(31 downto 8) <= (others => '0'); + readback_array(16)(0 downto 0) <= to_std_logic_vector(field_storage.PRBS_Control.prbs_sel.value) when (decoded_reg_strb.PRBS_Control and not decoded_req_is_wr) else (others => '0'); + readback_array(16)(3 downto 1) <= (others => '0'); + readback_array(16)(15 downto 4) <= field_storage.PRBS_Control.prbs_reserved.value when (decoded_reg_strb.PRBS_Control and not decoded_req_is_wr) else (others => '0'); + readback_array(16)(31 downto 16) <= field_storage.PRBS_Control.prbs_sync_threshold.value when (decoded_reg_strb.PRBS_Control and not decoded_req_is_wr) else (others => '0'); + readback_array(17)(31 downto 0) <= field_storage.PRBS_Initial_State.config_data.value when (decoded_reg_strb.PRBS_Initial_State and not decoded_req_is_wr) else (others => '0'); + readback_array(18)(31 downto 0) <= field_storage.PRBS_Polynomial.config_data.value when (decoded_reg_strb.PRBS_Polynomial and not decoded_req_is_wr) else (others => '0'); + readback_array(19)(31 downto 0) <= field_storage.PRBS_Error_Mask.config_data.value when (decoded_reg_strb.PRBS_Error_Mask and not decoded_req_is_wr) else (others => '0'); + readback_array(20)(31 downto 0) <= hwif_in.PRBS_Bit_Count.status_data.next_q when (decoded_reg_strb.PRBS_Bit_Count and not decoded_req_is_wr) else (others => '0'); + readback_array(21)(31 downto 0) <= hwif_in.PRBS_Error_Count.status_data.next_q when (decoded_reg_strb.PRBS_Error_Count and not decoded_req_is_wr) else (others => '0'); + readback_array(22)(31 downto 0) <= hwif_in.LPF_Accum_F1.status_data.next_q when (decoded_reg_strb.LPF_Accum_F1 and not decoded_req_is_wr) else (others => '0'); + readback_array(23)(31 downto 0) <= hwif_in.LPF_Accum_F2.status_data.next_q when (decoded_reg_strb.LPF_Accum_F2 and not decoded_req_is_wr) else (others => '0'); + readback_array(24)(31 downto 0) <= hwif_in.axis_xfer_count.xfer_count.next_q when (decoded_reg_strb.axis_xfer_count and not decoded_req_is_wr) else (others => '0'); + readback_array(25)(7 downto 0) <= field_storage.Rx_Sample_Discard.rx_sample_discard.value when (decoded_reg_strb.Rx_Sample_Discard and not decoded_req_is_wr) else (others => '0'); + readback_array(25)(15 downto 8) <= field_storage.Rx_Sample_Discard.rx_nco_discard.value when (decoded_reg_strb.Rx_Sample_Discard and not decoded_req_is_wr) else (others => '0'); + readback_array(25)(31 downto 16) <= (others => '0'); + readback_array(26)(23 downto 0) <= field_storage.LPF_Config_2.p_gain.value when (decoded_reg_strb.LPF_Config_2 and not decoded_req_is_wr) else (others => '0'); + readback_array(26)(31 downto 24) <= field_storage.LPF_Config_2.p_shift.value when (decoded_reg_strb.LPF_Config_2 and not decoded_req_is_wr) else (others => '0'); + readback_array(27)(31 downto 0) <= hwif_in.f1_nco_adjust.data.next_q when (decoded_reg_strb.f1_nco_adjust and not decoded_req_is_wr) else (others => '0'); + readback_array(28)(31 downto 0) <= hwif_in.f2_nco_adjust.data.next_q when (decoded_reg_strb.f2_nco_adjust and not decoded_req_is_wr) else (others => '0'); + readback_array(29)(31 downto 0) <= hwif_in.f1_error.data.next_q when (decoded_reg_strb.f1_error and not decoded_req_is_wr) else (others => '0'); + readback_array(30)(31 downto 0) <= hwif_in.f2_error.data.next_q when (decoded_reg_strb.f2_error and not decoded_req_is_wr) else (others => '0'); + readback_array(31)(0 downto 0) <= to_std_logic_vector(field_storage.Tx_Sync_Ctrl.tx_sync_ena.value) when (decoded_reg_strb.Tx_Sync_Ctrl and not decoded_req_is_wr) else (others => '0'); + readback_array(31)(1 downto 1) <= to_std_logic_vector(field_storage.Tx_Sync_Ctrl.tx_sync_force.value) when (decoded_reg_strb.Tx_Sync_Ctrl and not decoded_req_is_wr) else (others => '0'); + readback_array(31)(2 downto 2) <= to_std_logic_vector(field_storage.Tx_Sync_Ctrl.tx_sync_f1.value) when (decoded_reg_strb.Tx_Sync_Ctrl and not decoded_req_is_wr) else (others => '0'); + readback_array(31)(3 downto 3) <= to_std_logic_vector(field_storage.Tx_Sync_Ctrl.tx_sync_f2.value) when (decoded_reg_strb.Tx_Sync_Ctrl and not decoded_req_is_wr) else (others => '0'); + readback_array(31)(31 downto 4) <= (others => '0'); + readback_array(32)(23 downto 0) <= field_storage.Tx_Sync_Cnt.tx_sync_cnt.value when (decoded_reg_strb.Tx_Sync_Cnt and not decoded_req_is_wr) else (others => '0'); + readback_array(32)(31 downto 24) <= (others => '0'); + readback_array(33)(17 downto 0) <= field_storage.lowpass_ema_alpha1.alpha.value when (decoded_reg_strb.lowpass_ema_alpha1 and not decoded_req_is_wr) else (others => '0'); + readback_array(33)(31 downto 18) <= (others => '0'); + readback_array(34)(17 downto 0) <= field_storage.lowpass_ema_alpha2.alpha.value when (decoded_reg_strb.lowpass_ema_alpha2 and not decoded_req_is_wr) else (others => '0'); + readback_array(34)(31 downto 18) <= (others => '0'); + readback_array(35)(22 downto 0) <= hwif_in.rx_power.rx_power.next_q when (decoded_reg_strb.rx_power and not decoded_req_is_wr) else (others => '0'); + readback_array(35)(31 downto 23) <= (others => '0'); + + -- Reduce the array + process(all) + variable readback_data_var : std_logic_vector(31 downto 0) := (others => '0'); + begin + readback_done <= decoded_req and not decoded_req_is_wr; + readback_err <= '0'; + readback_data_var := (others => '0'); + for i in readback_array'RANGE loop + readback_data_var := readback_data_var or readback_array(i); + end loop; + readback_data <= readback_data_var; + end process; + + cpuif_rd_ack <= readback_done; + cpuif_rd_data <= readback_data; + cpuif_rd_err <= readback_err; +end architecture rtl; diff --git a/rdl/outputs/rtl/msk_top_regs_pkg.vhd b/rdl/outputs/rtl/msk_top_regs_pkg.vhd new file mode 100644 index 0000000..a362018 --- /dev/null +++ b/rdl/outputs/rtl/msk_top_regs_pkg.vhd @@ -0,0 +1,432 @@ +-- Generated by PeakRDL-regblock-vhdl - A free and open-source VHDL generator +-- https://github.com/SystemRDL/PeakRDL-regblock-vhdl +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.fixed_pkg.all; + +package msk_top_regs_pkg is + + constant MSK_TOP_REGS_DATA_WIDTH : positive := 32; + constant MSK_TOP_REGS_MIN_ADDR_WIDTH : positive := 8; + constant MSK_TOP_REGS_SIZE : positive := 144; + + type \msk_top_regs.msk_stat_0.demod_sync_lock_in_t\ is record + next_q : std_logic; + end record; + + type \msk_top_regs.msk_stat_0.tx_enable_in_t\ is record + next_q : std_logic; + end record; + + type \msk_top_regs.msk_stat_0.rx_enable_in_t\ is record + next_q : std_logic; + end record; + + type \msk_top_regs.msk_stat_0.tx_axis_valid_in_t\ is record + next_q : std_logic; + end record; + + type \msk_top_regs.msk_stat_0_in_t\ is record + demod_sync_lock : \msk_top_regs.msk_stat_0.demod_sync_lock_in_t\; + tx_enable : \msk_top_regs.msk_stat_0.tx_enable_in_t\; + rx_enable : \msk_top_regs.msk_stat_0.rx_enable_in_t\; + tx_axis_valid : \msk_top_regs.msk_stat_0.tx_axis_valid_in_t\; + end record; + + type \msk_top_regs.msk_stat_1.tx_bit_counter_in_t\ is record + next_q : std_logic_vector(31 downto 0); + end record; + + type \msk_top_regs.msk_stat_1_in_t\ is record + tx_bit_counter : \msk_top_regs.msk_stat_1.tx_bit_counter_in_t\; + end record; + + type \msk_top_regs.msk_stat_2.tx_ena_counter_in_t\ is record + next_q : std_logic_vector(31 downto 0); + end record; + + type \msk_top_regs.msk_stat_2_in_t\ is record + tx_ena_counter : \msk_top_regs.msk_stat_2.tx_ena_counter_in_t\; + end record; + + type \msk_top_regs.stat_32_bits.status_data_in_t\ is record + next_q : std_logic_vector(31 downto 0); + end record; + + type \msk_top_regs.stat_32_bits_in_t\ is record + status_data : \msk_top_regs.stat_32_bits.status_data_in_t\; + end record; + + type \msk_top_regs.stat_32_errs.status_data_in_t\ is record + next_q : std_logic_vector(31 downto 0); + end record; + + type \msk_top_regs.stat_32_errs_in_t\ is record + status_data : \msk_top_regs.stat_32_errs.status_data_in_t\; + end record; + + type \msk_top_regs.stat_32_lpf_acc_desc_8cebc7dc_name_f20c6670.status_data_in_t\ is record + next_q : std_logic_vector(31 downto 0); + end record; + + type \msk_top_regs.stat_32_lpf_acc_desc_8cebc7dc_name_f20c6670_in_t\ is record + status_data : \msk_top_regs.stat_32_lpf_acc_desc_8cebc7dc_name_f20c6670.status_data_in_t\; + end record; + + type \msk_top_regs.stat_32_lpf_acc_desc_dea6bd99_name_758fd0ce.status_data_in_t\ is record + next_q : std_logic_vector(31 downto 0); + end record; + + type \msk_top_regs.stat_32_lpf_acc_desc_dea6bd99_name_758fd0ce_in_t\ is record + status_data : \msk_top_regs.stat_32_lpf_acc_desc_dea6bd99_name_758fd0ce.status_data_in_t\; + end record; + + type \msk_top_regs.msk_stat_3.xfer_count_in_t\ is record + next_q : std_logic_vector(31 downto 0); + end record; + + type \msk_top_regs.msk_stat_3_in_t\ is record + xfer_count : \msk_top_regs.msk_stat_3.xfer_count_in_t\; + end record; + + type \msk_top_regs.data32_desc_64ff3689_name_d8ad3b25_in_t\ is record + next_q : std_logic_vector(31 downto 0); + end record; + + type \msk_top_regs.observation_data_data_0c017ef4_desc_64ff3689_name_d8ad3b25_in_t\ is record + data : \msk_top_regs.data32_desc_64ff3689_name_d8ad3b25_in_t\; + end record; + + type \msk_top_regs.data32_desc_ebde6d39_name_2c154788_in_t\ is record + next_q : std_logic_vector(31 downto 0); + end record; + + type \msk_top_regs.observation_data_data_0515efaa_desc_ebde6d39_name_2c154788_in_t\ is record + data : \msk_top_regs.data32_desc_ebde6d39_name_2c154788_in_t\; + end record; + + type \msk_top_regs.data32_desc_417e1c96_name_3b640507_in_t\ is record + next_q : std_logic_vector(31 downto 0); + end record; + + type \msk_top_regs.observation_data_data_25a21249_desc_417e1c96_name_3b640507_in_t\ is record + data : \msk_top_regs.data32_desc_417e1c96_name_3b640507_in_t\; + end record; + + type \msk_top_regs.data32_desc_70869502_name_3de9a0d3_in_t\ is record + next_q : std_logic_vector(31 downto 0); + end record; + + type \msk_top_regs.observation_data_data_272a00b6_desc_70869502_name_3de9a0d3_in_t\ is record + data : \msk_top_regs.data32_desc_70869502_name_3de9a0d3_in_t\; + end record; + + type \msk_top_regs.rx_power.rx_power_in_t\ is record + next_q : std_logic_vector(22 downto 0); + end record; + + type \msk_top_regs.rx_power_in_t\ is record + rx_power : \msk_top_regs.rx_power.rx_power_in_t\; + end record; + + type msk_top_regs_in_t is record + MSK_Status : \msk_top_regs.msk_stat_0_in_t\; + Tx_Bit_Count : \msk_top_regs.msk_stat_1_in_t\; + Tx_Enable_Count : \msk_top_regs.msk_stat_2_in_t\; + PRBS_Bit_Count : \msk_top_regs.stat_32_bits_in_t\; + PRBS_Error_Count : \msk_top_regs.stat_32_errs_in_t\; + LPF_Accum_F1 : \msk_top_regs.stat_32_lpf_acc_desc_8cebc7dc_name_f20c6670_in_t\; + LPF_Accum_F2 : \msk_top_regs.stat_32_lpf_acc_desc_dea6bd99_name_758fd0ce_in_t\; + axis_xfer_count : \msk_top_regs.msk_stat_3_in_t\; + f1_nco_adjust : \msk_top_regs.observation_data_data_0c017ef4_desc_64ff3689_name_d8ad3b25_in_t\; + f2_nco_adjust : \msk_top_regs.observation_data_data_0515efaa_desc_ebde6d39_name_2c154788_in_t\; + f1_error : \msk_top_regs.observation_data_data_25a21249_desc_417e1c96_name_3b640507_in_t\; + f2_error : \msk_top_regs.observation_data_data_272a00b6_desc_70869502_name_3de9a0d3_in_t\; + rx_power : \msk_top_regs.rx_power_in_t\; + end record; + + type \msk_top_regs.msk_init.txrxinit_out_t\ is record + value : std_logic; + end record; + + type \msk_top_regs.msk_init.txinit_out_t\ is record + value : std_logic; + end record; + + type \msk_top_regs.msk_init.rxinit_out_t\ is record + value : std_logic; + end record; + + type \msk_top_regs.msk_init_out_t\ is record + txrxinit : \msk_top_regs.msk_init.txrxinit_out_t\; + txinit : \msk_top_regs.msk_init.txinit_out_t\; + rxinit : \msk_top_regs.msk_init.rxinit_out_t\; + end record; + + type \msk_top_regs.msk_ctrl.ptt_out_t\ is record + value : std_logic; + end record; + + type \msk_top_regs.msk_ctrl.loopback_ena_out_t\ is record + value : std_logic; + end record; + + type \msk_top_regs.msk_ctrl.rx_invert_out_t\ is record + value : std_logic; + end record; + + type \msk_top_regs.msk_ctrl.clear_counts_out_t\ is record + value : std_logic; + end record; + + type \msk_top_regs.msk_ctrl.diff_encoder_loopback_out_t\ is record + value : std_logic; + end record; + + type \msk_top_regs.msk_ctrl_out_t\ is record + ptt : \msk_top_regs.msk_ctrl.ptt_out_t\; + loopback_ena : \msk_top_regs.msk_ctrl.loopback_ena_out_t\; + rx_invert : \msk_top_regs.msk_ctrl.rx_invert_out_t\; + clear_counts : \msk_top_regs.msk_ctrl.clear_counts_out_t\; + diff_encoder_loopback : \msk_top_regs.msk_ctrl.diff_encoder_loopback_out_t\; + end record; + + type \msk_top_regs.config_nco_fw_desc_c4924cc6_name_0c494469.config_data_out_t\ is record + value : std_logic_vector(31 downto 0); + end record; + + type \msk_top_regs.config_nco_fw_desc_c4924cc6_name_0c494469_out_t\ is record + config_data : \msk_top_regs.config_nco_fw_desc_c4924cc6_name_0c494469.config_data_out_t\; + end record; + + type \msk_top_regs.config_nco_fw_desc_94d7aaf5_name_84dd0c1c.config_data_out_t\ is record + value : std_logic_vector(31 downto 0); + end record; + + type \msk_top_regs.config_nco_fw_desc_94d7aaf5_name_84dd0c1c_out_t\ is record + config_data : \msk_top_regs.config_nco_fw_desc_94d7aaf5_name_84dd0c1c.config_data_out_t\; + end record; + + type \msk_top_regs.config_nco_fw_desc_42134a4f_name_d97dbd51.config_data_out_t\ is record + value : std_logic_vector(31 downto 0); + end record; + + type \msk_top_regs.config_nco_fw_desc_42134a4f_name_d97dbd51_out_t\ is record + config_data : \msk_top_regs.config_nco_fw_desc_42134a4f_name_d97dbd51.config_data_out_t\; + end record; + + type \msk_top_regs.config_nco_fw_desc_16fb48c8_name_8d01a20d.config_data_out_t\ is record + value : std_logic_vector(31 downto 0); + end record; + + type \msk_top_regs.config_nco_fw_desc_16fb48c8_name_8d01a20d_out_t\ is record + config_data : \msk_top_regs.config_nco_fw_desc_16fb48c8_name_8d01a20d.config_data_out_t\; + end record; + + type \msk_top_regs.config_nco_fw_desc_43c0828f_name_bdc60ecf.config_data_out_t\ is record + value : std_logic_vector(31 downto 0); + end record; + + type \msk_top_regs.config_nco_fw_desc_43c0828f_name_bdc60ecf_out_t\ is record + config_data : \msk_top_regs.config_nco_fw_desc_43c0828f_name_bdc60ecf.config_data_out_t\; + end record; + + type \msk_top_regs.lpf_config_0.lpf_freeze_out_t\ is record + value : std_logic; + end record; + + type \msk_top_regs.lpf_config_0.lpf_zero_out_t\ is record + value : std_logic; + end record; + + type \msk_top_regs.lpf_config_0.prbs_reserved_out_t\ is record + value : std_logic_vector(5 downto 0); + end record; + + type \msk_top_regs.lpf_config_0.lpf_alpha_out_t\ is record + value : std_logic_vector(23 downto 0); + end record; + + type \msk_top_regs.lpf_config_0_out_t\ is record + lpf_freeze : \msk_top_regs.lpf_config_0.lpf_freeze_out_t\; + lpf_zero : \msk_top_regs.lpf_config_0.lpf_zero_out_t\; + prbs_reserved : \msk_top_regs.lpf_config_0.prbs_reserved_out_t\; + lpf_alpha : \msk_top_regs.lpf_config_0.lpf_alpha_out_t\; + end record; + + type \msk_top_regs.lpf_config_1.i_gain_out_t\ is record + value : std_logic_vector(23 downto 0); + end record; + + type \msk_top_regs.lpf_config_1.i_shift_out_t\ is record + value : std_logic_vector(7 downto 0); + end record; + + type \msk_top_regs.lpf_config_1_out_t\ is record + i_gain : \msk_top_regs.lpf_config_1.i_gain_out_t\; + i_shift : \msk_top_regs.lpf_config_1.i_shift_out_t\; + end record; + + type \msk_top_regs.data_width_desc_58c848dd_name_2fbd8eba.data_width_out_t\ is record + value : std_logic_vector(7 downto 0); + end record; + + type \msk_top_regs.data_width_desc_58c848dd_name_2fbd8eba_out_t\ is record + data_width : \msk_top_regs.data_width_desc_58c848dd_name_2fbd8eba.data_width_out_t\; + end record; + + type \msk_top_regs.data_width_desc_6097df38_name_4609588b.data_width_out_t\ is record + value : std_logic_vector(7 downto 0); + end record; + + type \msk_top_regs.data_width_desc_6097df38_name_4609588b_out_t\ is record + data_width : \msk_top_regs.data_width_desc_6097df38_name_4609588b.data_width_out_t\; + end record; + + type \msk_top_regs.prbs_ctrl.prbs_sel_out_t\ is record + value : std_logic; + end record; + + type \msk_top_regs.prbs_ctrl.prbs_error_insert_out_t\ is record + value : std_logic; + end record; + + type \msk_top_regs.prbs_ctrl.prbs_clear_out_t\ is record + value : std_logic; + end record; + + type \msk_top_regs.prbs_ctrl.prbs_manual_sync_out_t\ is record + value : std_logic; + end record; + + type \msk_top_regs.prbs_ctrl.prbs_reserved_out_t\ is record + value : std_logic_vector(11 downto 0); + end record; + + type \msk_top_regs.prbs_ctrl.prbs_sync_threshold_out_t\ is record + value : std_logic_vector(15 downto 0); + end record; + + type \msk_top_regs.prbs_ctrl_out_t\ is record + prbs_sel : \msk_top_regs.prbs_ctrl.prbs_sel_out_t\; + prbs_error_insert : \msk_top_regs.prbs_ctrl.prbs_error_insert_out_t\; + prbs_clear : \msk_top_regs.prbs_ctrl.prbs_clear_out_t\; + prbs_manual_sync : \msk_top_regs.prbs_ctrl.prbs_manual_sync_out_t\; + prbs_reserved : \msk_top_regs.prbs_ctrl.prbs_reserved_out_t\; + prbs_sync_threshold : \msk_top_regs.prbs_ctrl.prbs_sync_threshold_out_t\; + end record; + + type \msk_top_regs.config_prbs_seed.config_data_out_t\ is record + value : std_logic_vector(31 downto 0); + end record; + + type \msk_top_regs.config_prbs_seed_out_t\ is record + config_data : \msk_top_regs.config_prbs_seed.config_data_out_t\; + end record; + + type \msk_top_regs.config_prbs_poly.config_data_out_t\ is record + value : std_logic_vector(31 downto 0); + end record; + + type \msk_top_regs.config_prbs_poly_out_t\ is record + config_data : \msk_top_regs.config_prbs_poly.config_data_out_t\; + end record; + + type \msk_top_regs.config_prbs_errmask.config_data_out_t\ is record + value : std_logic_vector(31 downto 0); + end record; + + type \msk_top_regs.config_prbs_errmask_out_t\ is record + config_data : \msk_top_regs.config_prbs_errmask.config_data_out_t\; + end record; + + type \msk_top_regs.rx_sample_discard.rx_sample_discard_out_t\ is record + value : std_logic_vector(7 downto 0); + end record; + + type \msk_top_regs.rx_sample_discard.rx_nco_discard_out_t\ is record + value : std_logic_vector(7 downto 0); + end record; + + type \msk_top_regs.rx_sample_discard_out_t\ is record + rx_sample_discard : \msk_top_regs.rx_sample_discard.rx_sample_discard_out_t\; + rx_nco_discard : \msk_top_regs.rx_sample_discard.rx_nco_discard_out_t\; + end record; + + type \msk_top_regs.lpf_config_2.p_gain_out_t\ is record + value : std_logic_vector(23 downto 0); + end record; + + type \msk_top_regs.lpf_config_2.p_shift_out_t\ is record + value : std_logic_vector(7 downto 0); + end record; + + type \msk_top_regs.lpf_config_2_out_t\ is record + p_gain : \msk_top_regs.lpf_config_2.p_gain_out_t\; + p_shift : \msk_top_regs.lpf_config_2.p_shift_out_t\; + end record; + + type \msk_top_regs.tx_sync_ctrl.tx_sync_ena_out_t\ is record + value : std_logic; + end record; + + type \msk_top_regs.tx_sync_ctrl.tx_sync_force_out_t\ is record + value : std_logic; + end record; + + type \msk_top_regs.tx_sync_ctrl.tx_sync_f1_out_t\ is record + value : std_logic; + end record; + + type \msk_top_regs.tx_sync_ctrl.tx_sync_f2_out_t\ is record + value : std_logic; + end record; + + type \msk_top_regs.tx_sync_ctrl_out_t\ is record + tx_sync_ena : \msk_top_regs.tx_sync_ctrl.tx_sync_ena_out_t\; + tx_sync_force : \msk_top_regs.tx_sync_ctrl.tx_sync_force_out_t\; + tx_sync_f1 : \msk_top_regs.tx_sync_ctrl.tx_sync_f1_out_t\; + tx_sync_f2 : \msk_top_regs.tx_sync_ctrl.tx_sync_f2_out_t\; + end record; + + type \msk_top_regs.tx_sync_cnt.tx_sync_cnt_out_t\ is record + value : std_logic_vector(23 downto 0); + end record; + + type \msk_top_regs.tx_sync_cnt_out_t\ is record + tx_sync_cnt : \msk_top_regs.tx_sync_cnt.tx_sync_cnt_out_t\; + end record; + + type \msk_top_regs.lowpass_ema_alpha.alpha_out_t\ is record + value : std_logic_vector(17 downto 0); + end record; + + type \msk_top_regs.lowpass_ema_alpha_out_t\ is record + alpha : \msk_top_regs.lowpass_ema_alpha.alpha_out_t\; + end record; + + type msk_top_regs_out_t is record + MSK_Init : \msk_top_regs.msk_init_out_t\; + MSK_Control : \msk_top_regs.msk_ctrl_out_t\; + Fb_FreqWord : \msk_top_regs.config_nco_fw_desc_c4924cc6_name_0c494469_out_t\; + TX_F1_FreqWord : \msk_top_regs.config_nco_fw_desc_94d7aaf5_name_84dd0c1c_out_t\; + TX_F2_FreqWord : \msk_top_regs.config_nco_fw_desc_42134a4f_name_d97dbd51_out_t\; + RX_F1_FreqWord : \msk_top_regs.config_nco_fw_desc_16fb48c8_name_8d01a20d_out_t\; + RX_F2_FreqWord : \msk_top_regs.config_nco_fw_desc_43c0828f_name_bdc60ecf_out_t\; + LPF_Config_0 : \msk_top_regs.lpf_config_0_out_t\; + LPF_Config_1 : \msk_top_regs.lpf_config_1_out_t\; + Tx_Data_Width : \msk_top_regs.data_width_desc_58c848dd_name_2fbd8eba_out_t\; + Rx_Data_Width : \msk_top_regs.data_width_desc_6097df38_name_4609588b_out_t\; + PRBS_Control : \msk_top_regs.prbs_ctrl_out_t\; + PRBS_Initial_State : \msk_top_regs.config_prbs_seed_out_t\; + PRBS_Polynomial : \msk_top_regs.config_prbs_poly_out_t\; + PRBS_Error_Mask : \msk_top_regs.config_prbs_errmask_out_t\; + Rx_Sample_Discard : \msk_top_regs.rx_sample_discard_out_t\; + LPF_Config_2 : \msk_top_regs.lpf_config_2_out_t\; + Tx_Sync_Ctrl : \msk_top_regs.tx_sync_ctrl_out_t\; + Tx_Sync_Cnt : \msk_top_regs.tx_sync_cnt_out_t\; + lowpass_ema_alpha1 : \msk_top_regs.lowpass_ema_alpha_out_t\; + lowpass_ema_alpha2 : \msk_top_regs.lowpass_ema_alpha_out_t\; + end record; +end package; diff --git a/rdl/src/axi4lite_intf_pkg.vhd b/rdl/src/axi4lite_intf_pkg.vhd new file mode 100644 index 0000000..3cd73fc --- /dev/null +++ b/rdl/src/axi4lite_intf_pkg.vhd @@ -0,0 +1,42 @@ +library ieee; +context ieee.ieee_std_context; + +package axi4lite_intf_pkg is + + type axi4lite_slave_in_intf is record + AWVALID : std_logic; + AWADDR : std_logic_vector; + AWPROT : std_logic_vector(2 downto 0); + + WVALID : std_logic; + WDATA : std_logic_vector; + WSTRB : std_logic_vector; + + BREADY : std_logic; + + ARVALID : std_logic; + ARADDR : std_logic_vector; + ARPROT : std_logic_vector(2 downto 0); + + RREADY : std_logic; + end record axi4lite_slave_in_intf; + + type axi4lite_slave_out_intf is record + AWREADY : std_logic; + + WREADY : std_logic; + + BVALID : std_logic; + BRESP : std_logic_vector(1 downto 0); + + ARREADY : std_logic; + + RVALID : std_logic; + RDATA : std_logic_vector; + RRESP : std_logic_vector(1 downto 0); + end record axi4lite_slave_out_intf; + +end package axi4lite_intf_pkg; + +-- package body axi4lite_intf_pkg is +-- end package body axi4lite_intf_pkg; \ No newline at end of file diff --git a/rdl/src/msk_top_regs.rdl b/rdl/src/msk_top_regs.rdl new file mode 100644 index 0000000..207c848 --- /dev/null +++ b/rdl/src/msk_top_regs.rdl @@ -0,0 +1,552 @@ +//---------------------------------------------------------------------------------------------------- +//---------------------------------------------------------------------------------------------------- +// _______ ________ ______ +// __ __ \________ _____ _______ ___ __ \_____ _____________ ______ ___________________ /_ +// _ / / /___ __ \_ _ \__ __ \ __ /_/ /_ _ \__ ___/_ _ \_ __ `/__ ___/_ ___/__ __ \ +// / /_/ / __ /_/ // __/_ / / / _ _, _/ / __/_(__ ) / __// /_/ / _ / / /__ _ / / / +// \____/ _ .___/ \___/ /_/ /_/ /_/ |_| \___/ /____/ \___/ \__,_/ /_/ \___/ /_/ /_/ +// /_/ +// ________ _____ _____ _____ _____ +// ____ _/_______ __________ /____(_)__ /_____ ____ /______ +// __ / __ __ \__ ___/_ __/__ / _ __/_ / / /_ __/_ _ \ +// __/ / _ / / /_(__ ) / /_ _ / / /_ / /_/ / / /_ / __/ +// /___/ /_/ /_/ /____/ \__/ /_/ \__/ \__,_/ \__/ \___/ +// +//---------------------------------------------------------------------------------------------------- +//---------------------------------------------------------------------------------------------------- +// +// Copyright 2024, 2025 by M. Wishek +// +//---------------------------------------------------------------------------------------------------- +// License +//---------------------------------------------------------------------------------------------------- +// +// This source describes Open Hardware and is licensed under the CERN-OHL-W v2. +// +// You may redistribute and modify this source and make products using it under +// the terms of the CERN-OHL-W v2 (https://ohwr.org/cern_ohl_w_v2.txt). +// +// This source is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING +// OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR A PARTICULAR PURPOSE. +// Please see the CERN-OHL-W v2 for applicable conditions. +// +// Source location: TBD +// +// As per CERN-OHL-W v2 section 4.1, should You produce hardware based on this +// source, You must maintain the Source Location visible on the external case of +// the products you make using this source. +// +//---------------------------------------------------------------------------------------------------- +// Block name and description +//---------------------------------------------------------------------------------------------------- +// +// SystemRDL register definitions for Pluto MSK modem +// +// Documentation location: TBD +// +//---------------------------------------------------------------------------------------------------- +//---------------------------------------------------------------------------------------------------- + + +addrmap msk_top_regs { + + name="Pluto MSK Registers"; + desc="MSK Modem Configuration and Status Registers"; + lsb0; + default accesswidth = 32; + default regwidth = 32; + default sw = rw; + default hw = r; + + reg msk_hash_lo { + + name = "Pluto MSK FPGA Hash ID - Lower 32-bits"; + + default sw = r; + default hw = na; + + field { + name = "Hash ID Lower 32-bits"; + desc = "Lower 32-bits of Pluto MSK FPGA Hash ID"; + } hash_id_lo[31:0] = 0xAAAA5555; + }; + + reg msk_hash_hi { + + name = "Pluto MSK FPGA Hash ID - Upper 32-bits"; + + default sw = r; + default hw = na; + + field { + name = "Hash ID Upper 32-bits"; + desc = "Upper 32-bits of Pluto MSK FPGA Hash ID"; + } hash_id_hi[31:0] = 0x5555AAAA; + }; + + reg msk_init { + + name = "MSK Modem Initialization Control"; + desc = "Synchronous initialization of MSK Modem functions, does not affect configuration registers."; + + field { + name = "Tx/Rx Init Enable"; + desc = "0 -> Normal modem operation + 1 -> Initialize Tx and Rx"; + } txrxinit = 1; + + field { + name = "Tx Init Enable"; + desc = "0 -> Normal Tx operation + 1 -> Initialize Tx"; + } txinit = 1; + + field { + name = "Rx Init Enable"; + desc = "0 -> Normal Rx operation + 1 -> Initialize Rx"; + } rxinit = 1; + }; + + reg msk_ctrl { + + name = "MSK Modem Control"; + desc = "MSK Modem Configuration and Control"; + + field { + name = "Push-to-Talk Enable"; + desc = "0 -> PTT Disabled + 1 -> PTT Enabled"; + } ptt = 0; + field { + name = "Modem Digital Tx -> Rx Loopback Enable"; + desc = "0 -> Modem loopback disabled + 1 -> Modem loopback enabled"; + } loopback_ena = 0; + field { + name = "Rx Data Invert Enable"; + desc = "0 -> Rx data normal + 1 -> Rx data inverted"; + } rx_invert = 0; + field { + desc = "Clear Tx Bit Counter and Tx Enable Counter"; + name = "Clear Status Counters"; + singlepulse = true; + } clear_counts = 0; + field { + name = "Differential Encoder -> Decoder Loopback Enable"; + desc = "0 -> Differential Encoder -> Decoder loopback disabled + 1 -> Differential Encoder -> Decoder loopback enabled"; + } diff_encoder_loopback = 0; + }; + + reg msk_stat_0 { + name = "MSK Modem Status 0"; + desc = "Modem status bits"; + regwidth = 32; + field { + name = "Demodulator Sync Status"; + desc = "Demodulator Sync Status - not currently implemented"; + sw = r; + hw = w; + } demod_sync_lock = 0; + field { + name = "AD9363 DAC Interface Tx Enable Input Active"; + desc = "1 -> Data to DAC Enabled + 0 -> Data to DAC Disabled"; + sw = r; + hw = w; + } tx_enable=0; + field { + name = "AD9363 ADC Interface Rx Enable Input Active"; + desc = "1 -> Data from ADC Enabled + 0 -> Data from ADC Disabled"; + sw = r; + hw = w; + } rx_enable = 0; + field { + name = "Tx S_AXIS_VALID"; + desc = "1 -> S_AXIS_VALID Enabled + 0 -> S_AXIS_VALID Disabled"; + sw = r; + hw = w; + } tx_axis_valid = 0; + }; + + reg msk_stat_1 { + name = "MSK Modem Status 1"; + desc = "Modem status data"; + regwidth = 32; + field { + name = "Tx Bit Count"; + desc = "Count of data requests made by modem"; + sw = r; + hw = w; + } tx_bit_counter[31:0]; + }; + + reg msk_stat_2 { + name = "MSK Modem Status 2"; + desc = "Modem status data"; + regwidth = 32; + field { + desc = "Number of clocks on which Tx Enable is active"; + name = "Tx Enable Count"; + sw = r; + hw = w; + } tx_ena_counter[31:0] = 0; + }; + + reg config_nco_fw { + regwidth = 32; + field { + name = "Frequency Control Word"; + desc = "Sets the center frequency of the NCO as FW = Fn * 2^32/Fs, + where Fn is the desired NCO frequency, and Fs is the NCO sample rate"; + } config_data[31:0] = 0; + }; + + reg rx_sample_discard { + name = "Rx Sample Discard"; + desc = "Configure samples discard operation for demodulator"; + regwidth = 32; + field { + desc = "Number of Rx samples to discard"; + name = "Rx Sample Discard Value"; + } rx_sample_discard[7:0] = 0; + field { + desc = "Number of NCO samples to discard"; + name = "Rx NCO Sample Discard Value"; + } rx_nco_discard[15:8] = 0; + }; + + reg lpf_config_0 { + name = "PI Controller Configuration and Low-pass Filter Configuration"; + desc = "Configure PI controller and low-pass filter"; + regwidth = 32; + field { + name = "Freeze the accumulator's current value"; + desc = "0 -> Normal operation + 1 -> Freeze current value"; + } lpf_freeze = 0; + field { + name = "Hold the PI Accumulator at zero"; + desc = "0 -> Normal operation + 1 -> Zero and hold accumulator"; + } lpf_zero = 0; + field { + name = "Reserved"; + } prbs_reserved[7:2] = 0; + field { + name = "Lowpass IIR filter alpha"; + desc = "Value controls the filter rolloff"; + } lpf_alpha[31:8] = 0; + }; + + reg lpf_config_1 { + name = "PI Controller Configuration Configuration Register 1"; + desc = "Configures PI Controller I-gain and divisor"; + regwidth = 32; + field { + name = "Integral Gain Value"; + desc = "Value m of 0-16,777,215 sets the integral multiplier"; + } i_gain[23:0] = 0; + field { + name = "Integral Gain Bit Shift"; + desc = "Value n of 0-32 sets the integral divisor as 2^-n"; + } i_shift[31:24] = 0; + }; + + reg lpf_config_2 { + name = "PI Controller Configuration Configuration Register 2"; + desc = "Configures PI Controller I-gain and divisor"; + regwidth = 32; + field { + name = "Proportional Gain Value"; + desc = "Value m of 0-16,777,215 sets the proportional multiplier"; + } p_gain[23:0] = 0; + field { + name = "Proportional Gain Bit Shift"; + desc = "Value n of 0-32 sets the proportional divisor as 2^-n"; + } p_shift[31:24] = 0; + }; + + reg data_width { + regwidth = 32; + field { + name = "Modem input/output data width"; + desc = "Set the data width of the modem input/output"; + } data_width[7:0] = 8; + }; + + reg prbs_ctrl { + name = "PRBS Control 0"; + desc = "Configures operation of the PRBS Generator and Monitor"; + regwidth = 32; + field { + name = "PRBS Data Select"; + desc = "0 -> Select Normal Tx Data + 1 -> Select PRBS Tx Data"; + } prbs_sel = 0; + field { + name = "PRBS Error Insert"; + desc = "0 -> 1 : Insert bit error in Tx data (both Normal and PRBS) + 1 -> 0 : Insert bit error in Tx data (both Normal and PRBS)"; + sw = w; + hw = r; + singlepulse = true; + } prbs_error_insert = 0; + field { + name = "PRBS Clear Counters"; + desc = "0 -> 1 : Clear PRBS Counters + 1 -> 0 : Clear PRBS Counters"; + sw = w; + hw = r; + singlepulse = true; + } prbs_clear = 0; + field { + name = "PRBS Manual Sync"; + desc = "0 -> 1 : Synchronize PRBS monitor + 1 -> 0 : Synchronize PRBS monitor"; + sw = w; + hw = r; + singlepulse = true; + } prbs_manual_sync = 0; + field { + name = "Reserved"; + } prbs_reserved[15:4] = 0; + field { + name = "PRBS Auto Sync Threshold"; + desc = "0 : Auto Sync Disabled + N > 0 : Auto sync after N errors"; + } prbs_sync_threshold[31:16] = 0; + }; + + reg config_prbs_seed { + name = "PRBS Control 1"; + desc = "PRBS Initial State"; + regwidth = 32; + field { + name = "PRBS Seed"; + desc = "Sets the starting value of the PRBS generator"; + } config_data[31:0] = 0; + }; + + reg config_prbs_poly { + name = "PRBS Control 2"; + desc = "PRBS Polynomial"; + regwidth = 32; + field { + name = "PRBS Polynomial"; + desc = "Bit positions set to '1' indicate polynomial feedback positions"; + } config_data[31:0] = 0; + }; + + reg config_prbs_errmask { + name = "PRBS Control 3"; + desc = "PRBS Error Mask"; + regwidth = 32; + field { + name = "PRBS Error Mask"; + desc = "Bit positions set to '1' indicate bits that are inverted when a bit error is inserted"; + } config_data[31:0] = 0; + }; + + reg stat_32_bits { + name = "PRBS Status 0"; + desc = "PRBS Bits Received"; + regwidth = 32; + field { + name = "PRBS Bits Received"; + desc = "Number of bits received by the PRBS monitor since last + BER can be calculated as the ratio of received bits to errored-bits"; + sw = r; + hw = w; + } status_data[31:0] = 0; + }; + + reg stat_32_errs { + name = "PRBS Status 1"; + desc = "PRBS Bit Errors"; + regwidth = 32; + field { + name = "PRBS Bit Errors"; + desc = "Number of errored-bits received by the PRBS monitor since last sync + BER can be calculated as the ratio of received bits to errored-bits"; + sw = r; + hw = w; + } status_data[31:0] = 0; + }; + + reg stat_32_lpf_acc { + regwidth = 32; + field { + name = "PI Controller Accumulator Value"; + desc = "PI Controller Accumulator Value"; + sw = r; + hw = w; + } status_data[31:0] = 0; + }; + + reg msk_stat_3 { + name = "MSK Modem Status 3"; + desc = "Modem status data"; + regwidth = 32; + field { + desc = "Number completed S_AXIS transfers"; + name = "S_AXIS Transfers"; + sw = r; + hw = w; + } xfer_count[31:0] = 0; + }; + + reg tx_sync_ctrl { + name = "Transmitter Sync Control"; + desc = "Provides control bits for generation of transmitter synchronization patterns"; + regwidth = 32; + field { + name = "Tx Sync Enable"; + desc = "0 -> Disable sync transmission + 1 -> Enable sync transmission when PTT is asserted"; + } tx_sync_ena = 0; + field { + name = "Tx Sync Force"; + desc = "0 : Normal operation) + 1 : Transmit synchronization pattern)"; + } tx_sync_force = 0; + field { + name = "Tx F1 Sync Enable"; + desc = "Enables/Disables transmission of F1 tone for receiver synchronization + 0 : F1 tone transmission disabled + 1 : F1 tone transmission enabled + Both F1 and F2 can be enabled at the same time"; + } tx_sync_f1 = 0; + field { + name = "Tx F2 Sync Enable"; + desc = "Enables/Disables transmission of F2 tone for receiver synchronization + 0 : F2 tone transmission disabled + 1 : F2 tone transmission enabled + Both F1 and F2 can be enabled at the same time"; + } tx_sync_f2 = 0; + }; + + reg tx_sync_cnt { + name = "Transmitter Sync Duration"; + desc = "Sets the duration of the synchronization tones when enabled"; + regwidth = 32; + field { + name = "Tx sync duration"; + desc = "Value from 0x00_0000 to 0xFF_FFFF. + This value represents the number bit-times the synchronization + signal should be sent after PTT is asserted."; + sw = rw; + hw = r; + } tx_sync_cnt[23:0] = 0; + }; + + reg lowpass_ema_alpha { + name = "Exponential Moving Average Alpha"; + desc = "Sets the alpha for the EMA"; + regwidth = 32; + field { + name = "EMA alpha"; + desc = "Value from 0x0_0000 to 0x3_FFFF represent the EMA alpha"; + } alpha[17:0] = 0; + }; + + reg rx_power { + name = "Receive Power"; + desc = "Receive power computed from I/Q ssamples"; + regwidth = 32; + field { + name = "Receive Power"; + desc = "Value that represent the RMS power of the incoming I;"; + sw = r; + hw = w; + } rx_power[22:0] = 0; + }; + + field data32 { + fieldwidth = 32; + sw = r; + hw = w; + }; + + reg observation_data { + regwidth = 32; + data32 data[31:0] = 0; + }; + + + msk_hash_lo Hash_ID_Low; + msk_hash_hi Hash_ID_High; + msk_init MSK_Init; + msk_ctrl MSK_Control; + msk_stat_0 MSK_Status; + msk_stat_1 Tx_Bit_Count; + msk_stat_2 Tx_Enable_Count; + config_nco_fw Fb_FreqWord; + Fb_FreqWord->desc = "Set Modem Data Rate"; + Fb_FreqWord->name = "Bitrate NCO Frequency Control Word"; + config_nco_fw TX_F1_FreqWord; + TX_F1_FreqWord->desc = "Set Modulator F1 Frequency"; + TX_F1_FreqWord->name = "Tx F1 NCO Frequency Control Word"; + config_nco_fw TX_F2_FreqWord; + TX_F2_FreqWord->desc = "Set Modulator F2 Frequency"; + TX_F2_FreqWord->name = "Tx F2 NCO Frequency Control Word"; + config_nco_fw RX_F1_FreqWord; + RX_F1_FreqWord->desc = "Set Demodulator F1 Frequency"; + RX_F1_FreqWord->name = "Rx F1 NCO Frequency Control Word"; + config_nco_fw RX_F2_FreqWord; + RX_F2_FreqWord->desc = "Set Demodulator F2 Frequency"; + RX_F2_FreqWord->name = "Rx F2 NCO Frequency Control Word"; + lpf_config_0 LPF_Config_0; + lpf_config_1 LPF_Config_1; + data_width Tx_Data_Width; + Tx_Data_Width->desc = "Set the parallel data width of the parallel-to-serial converter"; + Tx_Data_Width->name = "Modem Tx Input Data Width"; + data_width Rx_Data_Width; + Rx_Data_Width->desc = "Set the parallel data width of the serial-to-parallel converter"; + Rx_Data_Width->name = "Modem Rx Output Data Width"; + prbs_ctrl PRBS_Control; + config_prbs_seed PRBS_Initial_State; + config_prbs_poly PRBS_Polynomial; + config_prbs_errmask PRBS_Error_Mask; + stat_32_bits PRBS_Bit_Count; + stat_32_errs PRBS_Error_Count; + stat_32_lpf_acc LPF_Accum_F1; + LPF_Accum_F1->name = "F1 PI Controller Accumulator"; + LPF_Accum_F1->desc = "Value of the F1 PI Controller Accumulator"; + stat_32_lpf_acc LPF_Accum_F2; + LPF_Accum_F2->name = "F2 PI Controller Accumulator"; + LPF_Accum_F2->desc = "Value of the F2 PI Controller Accumulator"; + msk_stat_3 axis_xfer_count; + rx_sample_discard Rx_Sample_Discard; + lpf_config_2 LPF_Config_2; + observation_data f1_nco_adjust; + f1_nco_adjust->name = "F1 NCO Frequency Adjust"; + f1_nco_adjust->desc = "Frequency offet applied to the F1 NCO"; + f1_nco_adjust.data->name = "F1 NCO Frequency Adjust"; + f1_nco_adjust.data->desc = "Frequency offet applied to the F1 NCO"; + observation_data f2_nco_adjust; + f2_nco_adjust->name = "F2 NCO Frequency Adjust"; + f2_nco_adjust->desc = "Frequency offet applied to the F2 NCO"; + f2_nco_adjust.data->name = "F2 NCO Frequency Adjust"; + f2_nco_adjust.data->desc = "Frequency offet applied to the F2 NCO"; + observation_data f1_error; + f1_error->name = "F1 Error Value"; + f1_error->desc = "Error value of the F1 Costas loop after each active bit period"; + f1_error.data->name = "F1 Error Value"; + f1_error.data->desc = "Error value of the F1 Costas loop after each active bit period"; + observation_data f2_error; + f2_error->name = "F2 Error Value"; + f2_error->desc = "Error value of the F2 Costas loop after each active bit period"; + f2_error.data->name = "F2 Error Value"; + f2_error.data->desc = "Error value of the F2 Costas loop after each active bit period"; + tx_sync_ctrl Tx_Sync_Ctrl; + tx_sync_cnt Tx_Sync_Cnt; + lowpass_ema_alpha lowpass_ema_alpha1; + lowpass_ema_alpha lowpass_ema_alpha2; + rx_power rx_power; + +}; diff --git a/rdl/src/reg_utils.vhd b/rdl/src/reg_utils.vhd new file mode 100644 index 0000000..d1c1748 --- /dev/null +++ b/rdl/src/reg_utils.vhd @@ -0,0 +1,232 @@ +library ieee; +context ieee.ieee_std_context; +use ieee.fixed_pkg.all; + +-- Convenience types and utility functions used by the autogenerated regblock code +package reg_utils is + + type std_logic_array1 is array(natural range<>) of std_logic; + type std_logic_array2 is array(natural range<>, natural range<>) of std_logic; + type std_logic_array3 is array(natural range<>, natural range<>, natural range<>) of std_logic; + type std_logic_array4 is array(natural range<>, natural range<>, natural range<>, natural range<>) of std_logic; + type std_logic_array5 is array(natural range<>, natural range<>, natural range<>, natural range<>, natural range<>) of std_logic; + + type std_logic_vector_array1 is array(natural range<>) of std_logic_vector; + type std_logic_vector_array2 is array(natural range<>, natural range<>) of std_logic_vector; + type std_logic_vector_array3 is array(natural range<>, natural range<>, natural range<>) of std_logic_vector; + type std_logic_vector_array4 is array(natural range<>, natural range<>, natural range<>, natural range<>) of std_logic_vector; + type std_logic_vector_array5 is array(natural range<>, natural range<>, natural range<>, natural range<>, natural range<>) of std_logic_vector; + + -- reverse bits of the input vector + function bitswap(vec: in std_logic_vector) return std_logic_vector; + function bitswap(logic: in std_logic) return std_logic; + + -- Autogenerating VHDL when dealing with programmatically defined field widths + -- can be challenging, especially when doing arithmetic. These conversion functions + -- are overloaded with various input types, allow them to work regardless + -- of the input type or width. + function to_unsigned(vec: in std_logic_vector) return unsigned; + function to_unsigned(logic: in std_logic) return unsigned; + + function to_signed(vec: in std_logic_vector) return signed; + function to_signed(logic: in std_logic) return signed; + + function to_std_logic_vector(uns: in unsigned) return std_logic_vector; + function to_std_logic_vector(sgnd: in signed) return std_logic_vector; + function to_std_logic_vector(logic: in std_logic) return std_logic_vector; + -- std_logic_vector variant provided by ieee.std_logic_1164 + -- ufixed and sfixed variants are provided by ieee.fixed_pkg + + function from_std_logic_vector(vec: in std_logic_vector; slv: in std_logic_vector) return std_logic_vector; + function from_std_logic_vector(vec: in std_logic_vector; uns: in unsigned) return unsigned; + function from_std_logic_vector(vec: in std_logic_vector; sgnd: in signed) return signed; + function from_std_logic_vector(vec: in std_logic_vector; ufx: in ufixed) return ufixed; + function from_std_logic_vector(vec: in std_logic_vector; sfx: in sfixed) return sfixed; + + function to_std_logic(bool: in boolean) return std_logic; + function to_std_logic(logic: in std_logic) return std_logic; + function to_std_logic(vec: in std_logic_vector(0 downto 0)) return std_logic; + function to_std_logic(uns: in unsigned(0 downto 0)) return std_logic; + function to_std_logic(sgnd: in signed(0 downto 0)) return std_logic; + function to_std_logic(ufx: in ufixed(0 downto 0)) return std_logic; + function to_std_logic(sfx: in sfixed(0 downto 0)) return std_logic; + + function from_std_logic(logic: in std_logic; lg: in std_logic) return std_logic; + function from_std_logic(logic: in std_logic; uns: in unsigned) return unsigned; + function from_std_logic(logic: in std_logic; sgnd: in signed) return signed; + function from_std_logic(logic: in std_logic; ufx: in ufixed) return ufixed; + function from_std_logic(logic: in std_logic; sfx: in sfixed) return sfixed; + + -- reduction OR for tools with poor VHDL 2008 support + function or_reduce(vec: in std_logic_vector) return std_logic; + function or_reduce(logic: in std_logic) return std_logic; + +end package reg_utils; + +package body reg_utils is + + function bitswap(vec: in std_logic_vector) return std_logic_vector is + variable result: std_logic_vector(vec'RANGE); + alias swapped: std_logic_vector(vec'REVERSE_RANGE) is vec; + begin + for i in swapped'RANGE loop + result(i) := swapped(i); + end loop; + return result; + end function; + + function bitswap(logic: in std_logic) return std_logic is + begin + return logic; + end function; + + function to_unsigned(vec: in std_logic_vector) return unsigned is + begin + return unsigned(vec); + end function; + + function to_unsigned(logic: in std_logic) return unsigned is + variable result: unsigned(0 downto 0); + begin + result(0) := logic; + return result; + end function; + + function to_signed(vec: in std_logic_vector) return signed is + begin + return signed(vec); + end function; + + function to_signed(logic: in std_logic) return signed is + variable result: signed(0 downto 0); + begin + result(0) := logic; + return result; + end function; + + function to_std_logic_vector(uns: in unsigned) return std_logic_vector is + begin + return std_logic_vector(uns); + end function; + + function to_std_logic_vector(sgnd: in signed) return std_logic_vector is + begin + return std_logic_vector(sgnd); + end function; + + function to_std_logic_vector(logic: in std_logic) return std_logic_vector is + variable result: std_logic_vector(0 downto 0); + begin + result(0) := logic; + return result; + end function; + + + function from_std_logic_vector(vec: in std_logic_vector; slv: in std_logic_vector) return std_logic_vector is + begin + return vec; + end function; + + function from_std_logic_vector(vec: in std_logic_vector; uns: in unsigned) return unsigned is + begin + return unsigned(vec); + end function; + + function from_std_logic_vector(vec: in std_logic_vector; sgnd: in signed) return signed is + begin + return signed(vec); + end function; + + function from_std_logic_vector(vec: in std_logic_vector; ufx: in ufixed) return ufixed is + begin + return ufixed(vec); + end function; + + function from_std_logic_vector(vec: in std_logic_vector; sfx: in sfixed) return sfixed is + begin + return sfixed(vec); + end function; + + + function to_std_logic(bool: in boolean) return std_logic is + begin + if bool = TRUE then + return '1'; + else + return '0'; + end if; + end function; + + function to_std_logic(logic: in std_logic) return std_logic is + begin + return logic; + end function; + + function to_std_logic(vec: in std_logic_vector(0 downto 0)) return std_logic is + begin + return vec(0); + end function; + + function to_std_logic(uns: in unsigned(0 downto 0)) return std_logic is + begin + return uns(0); + end function; + + function to_std_logic(sgnd: in signed(0 downto 0)) return std_logic is + begin + return sgnd(0); + end function; + + function to_std_logic(ufx: in ufixed(0 downto 0)) return std_logic is + begin + return ufx(0); + end function; + + function to_std_logic(sfx: in sfixed(0 downto 0)) return std_logic is + begin + return sfx(0); + end function; + + + function from_std_logic(logic: in std_logic; lg: in std_logic) return std_logic is + begin + return logic; + end function; + + function from_std_logic(logic: in std_logic; uns: in unsigned) return unsigned is + begin + return to_unsigned(logic); + end function; + + function from_std_logic(logic: in std_logic; sgnd: in signed) return signed is + begin + return to_signed(logic); + end function; + + function from_std_logic(logic: in std_logic; ufx: in ufixed) return ufixed is + begin + return ufixed(to_unsigned(logic)); + end function; + + function from_std_logic(logic: in std_logic; sfx: in sfixed) return sfixed is + begin + return sfixed(to_signed(logic)); + end function; + + + function or_reduce(vec: in std_logic_vector) return std_logic is + variable result: std_logic; + begin + result := '0'; + for i in vec'RANGE loop + result := result or vec(i); + end loop; + return result; + end function; + + function or_reduce(logic: in std_logic) return std_logic is + begin + return logic; + end function; + +end package body; \ No newline at end of file diff --git a/rdl/src/regblock_udps.rdl b/rdl/src/regblock_udps.rdl new file mode 100644 index 0000000..eafdc5a --- /dev/null +++ b/rdl/src/regblock_udps.rdl @@ -0,0 +1,54 @@ +/* + * This file defines several property extensions that are understood by the + * PeakRDL-Regblock-vhdl code generator. + * + * Compile this file prior to your other SystemRDL sources. + * + * For more details, see: https://peakrdl-regblock-vhdl.readthedocs.io/en/latest/udps/intro.html + */ + +property buffer_reads { + component = reg; + type = boolean; +}; + +property rbuffer_trigger { + component = reg; + type = ref; +}; + +property buffer_writes { + component = reg; + type = boolean; +}; + +property wbuffer_trigger { + component = reg; + type = ref; +}; + +property rd_swacc { + component = field; + type = boolean; +}; + +property wr_swacc { + component = field; + type = boolean; +}; + +property is_signed { + type = boolean; + component = field; + default = true; +}; + +property intwidth { + type = longint unsigned; + component = field; +}; + +property fracwidth { + type = longint unsigned; + component = field; +}; diff --git a/sim/Makefile b/sim/Makefile index ea1aa80..d983c1c 100644 --- a/sim/Makefile +++ b/sim/Makefile @@ -17,16 +17,17 @@ ifeq ($(SIM),nvc) endif SRC = ../src -RDL = ../rdl/vhdl/msk_top_regs - -VHDL_SOURCES_desyrdl = ../rdl/vhdl/desyrdl/pkg_desyrdl_common.vhd - -VHDL_LIB_ORDER = desyrdl +RDL = ../rdl/ # use VHDL_SOURCES for VHDL files -VHDL_SOURCES += $(RDL)/msk_top_regs_decoder_axi4l.vhd \ - $(RDL)/pkg_msk_top_regs.vhd \ - $(RDL)/msk_top_regs.vhd \ +VHDL_SOURCES += $(RDL)/src/axi4lite_intf_pkg.vhd \ + $(RDL)/src/reg_utils.vhd \ + $(RDL)/outputs/rtl/msk_top_regs_pkg.vhd \ + $(RDL)/outputs/rtl/msk_top_regs.vhd \ + $(SRC)/cdc_resync.vhd \ + $(SRC)/axis_async_fifo.vhd \ + $(SRC)/axis_dma_adapter.vhd \ + $(SRC)/byte_to_bit_deserializer.vhd \ $(SRC)/msk_top_csr.vhd \ ../lowpass_ema/src/lowpass_ema.vhd \ ../power_detector/src/power_detector.vhd \ diff --git a/sim/desyrdl b/sim/desyrdl deleted file mode 120000 index 3ef65d1..0000000 --- a/sim/desyrdl +++ /dev/null @@ -1 +0,0 @@ -../rdl/cocotb/desyrdl \ No newline at end of file diff --git a/sim/msk_test.py b/sim/msk_test.py index d3d02e5..04a6aa2 100755 --- a/sim/msk_test.py +++ b/sim/msk_test.py @@ -65,7 +65,8 @@ import sys import inspect -from desyrdl import addrmap_ch0 +from msk_top_regs.reg_model.msk_top_regs import msk_top_regs_cls +from msk_top_regs.lib import AsyncCallbackSet, AsyncCallbackSetLegacy #------------------------------------------------------------------------------------------------------ # __ __ ___ __ __ ___ __ __ @@ -259,7 +260,7 @@ async def write_dwords(self,addr, data): await self.write(addr, data[0]) - async def read(self, addr): + async def read(self, addr, width, accesswidth): await RisingEdge(self.aclk) @@ -287,8 +288,10 @@ async def read(self, addr): return self.rdata.value.integer - async def write(self, addr, data): + async def write(self, addr, width, accesswidth, data): + self.dut.s_axi_awvalid.value = 1 + self.dut.s_axi_wvalid.value = 1 self.awaddr.value = addr self.wdata.value = data self.wstrb.value = 15 @@ -296,9 +299,6 @@ async def write(self, addr, data): await RisingEdge(self.aclk) - self.dut.s_axi_awvalid.value = 1 - self.dut.s_axi_wvalid.value = 1 - while self.awready.value == 0 and self.wready.value == 0: await RisingEdge(self.aclk) @@ -497,7 +497,7 @@ async def generate_data(self): while self.sim_run: data = await self.gen() - print("Data: ", data) + self.dut._log.info("Data: %s", hex(data)) await self.saxis.send(data) self.dut._log.info("...prbs generator - done") @@ -670,7 +670,7 @@ async def msk_test_1(dut): print("Instantiate registers") axi = axi_bus(dut) - regs = addrmap_ch0.Addrmap(axi) + regs = msk_top_regs_cls(callbacks=AsyncCallbackSet(read_callback=axi.read, write_callback=axi.write)) tx_samples = [] tx_time = [] @@ -679,8 +679,8 @@ async def msk_test_1(dut): rx_sample_rate = tx_sample_rate / tx_rx_sample_ratio - tx_data_width = 32 - rx_data_width = 32 + tx_data_width = 8 + rx_data_width = 8 await cocotb.start(Clock(dut.clk, tx_sample_per, units="fs").start()) @@ -718,105 +718,45 @@ async def msk_test_1(dut): dut.rx_samples_I.value = 0 dut.rx_samples_Q.value = 0 - hash_id = await regs.read("msk_top_regs", "Hash_ID_Low") - - dut.s_axi_wvalid.value = 1 - dut.s_axi_awvalid.value = 1 - await regs.write("msk_top_regs", "Fb_FreqWord", br_fcw) - # await axi.write(20, int(f1 / sample_rate * 2.0**32)) # F1 frequency word - dut.s_axi_wvalid.value = 1 - dut.s_axi_awvalid.value = 1 - await regs.write("msk_top_regs", "TX_F1_FreqWord", f1_fcw_tx) - dut.s_axi_wvalid.value = 1 - dut.s_axi_awvalid.value = 1 - await regs.write("msk_top_regs", "TX_F2_FreqWord", f2_fcw_tx) - dut.s_axi_wvalid.value = 1 - dut.s_axi_awvalid.value = 1 - await regs.write("msk_top_regs", "RX_F1_FreqWord", f1_fcw_rx) - dut.s_axi_wvalid.value = 1 - dut.s_axi_awvalid.value = 1 - await regs.write("msk_top_regs", "RX_F2_FreqWord", f2_fcw_rx) - dut.s_axi_wvalid.value = 1 - dut.s_axi_awvalid.value = 1 - await regs.write("msk_top_regs", "Rx_Sample_Discard", (tx_rx_sample_ratio-1 << 8) + tx_rx_sample_ratio-1) - # await axi.write(28, (50 << 16) + 20) # p-gain / i-gain - dut.s_axi_wvalid.value = 1 - dut.s_axi_awvalid.value = 1 - await regs.write("msk_top_regs", "LPF_Config_0", (lpf_alpha << 8)) - # await axi.write(32, (2 << 16)) # low-pass filter alpha - dut.s_axi_wvalid.value = 1 - dut.s_axi_awvalid.value = 1 - await regs.write("msk_top_regs", "LPF_Config_1", (i_shift << 24) + i_gain) - # await axi.write(36, 8) - dut.s_axi_wvalid.value = 1 - dut.s_axi_awvalid.value = 1 - await regs.write("msk_top_regs", "LPF_Config_2", (p_shift << 24) + p_gain) - # await axi.write(36, 8) - dut.s_axi_wvalid.value = 1 - dut.s_axi_awvalid.value = 1 - await regs.write("msk_top_regs", "Tx_Data_Width", tx_data_width) - # await axi.write(40, 8) - dut.s_axi_wvalid.value = 1 - dut.s_axi_awvalid.value = 1 - await regs.write("msk_top_regs", "Rx_Data_Width", rx_data_width) - # await axi.write(44, 1) # Select PRBS data path - dut.s_axi_wvalid.value = 1 - dut.s_axi_awvalid.value = 1 - await regs.write("msk_top_regs", "PRBS_Control", (autosync_threshold << 16) + 1) - # await axi.write(48, (1 << 31) + (1 << 28)) # Polynomial - dut.s_axi_wvalid.value = 1 - dut.s_axi_awvalid.value = 1 - await regs.write("msk_top_regs", "PRBS_Polynomial", (1 << 30) + (1 << 27)) - # await axi.write(52, 65535) # initial state - dut.s_axi_wvalid.value = 1 - dut.s_axi_awvalid.value = 1 - await regs.write("msk_top_regs", "PRBS_Initial_State", 0x8E7589FD) - # await axi.write(56, 1) # Error Mask - dut.s_axi_wvalid.value = 1 - dut.s_axi_awvalid.value = 1 - await regs.write("msk_top_regs", "PRBS_Error_Mask", 1) - # await axi.write(60, 0) - dut.s_axi_wvalid.value = 1 - dut.s_axi_awvalid.value = 1 - await regs.write("msk_top_regs", "lowpass_ema_alpha1", 64) - # await axi.write(60, 0) - dut.s_axi_wvalid.value = 1 - dut.s_axi_awvalid.value = 1 - await regs.write("msk_top_regs", "lowpass_ema_alpha2", 64) - # await axi.write(60, 0) - dut.s_axi_wvalid.value = 1 - dut.s_axi_awvalid.value = 1 - await regs.write("msk_top_regs", "Tx_Sync_Ctrl", 0b0001) - # await axi.write(60, 0) - dut.s_axi_wvalid.value = 1 - dut.s_axi_awvalid.value = 1 - await regs.write("msk_top_regs", "Tx_Sync_Cnt", 192) - # await axi.write(60, 0) - - - hash_id = await regs.read("msk_top_regs", "Hash_ID_Low") - #print("Hash ID: ", hex(hash_id)) - hash_id = await regs.read("msk_top_regs", "Hash_ID_Low") - #print("Hash ID: ", hex(hash_id)) - hash_id = await regs.read("msk_top_regs", "Hash_ID_Low") - #print("Hash ID: ", hex(hash_id)) - hash_id = await regs.read("msk_top_regs", "Hash_ID_Low") - #print("Hash ID: ", hex(hash_id)) - hash_id = await regs.read("msk_top_regs", "Hash_ID_Low") + hash_low = await regs.Hash_ID_Low.read() + hash_high = await regs.Hash_ID_High.read() + + await regs.Fb_FreqWord.write(br_fcw) + await regs.TX_F1_FreqWord.write(f1_fcw_tx) + await regs.TX_F2_FreqWord.write(f2_fcw_tx) + await regs.RX_F1_FreqWord.write(f1_fcw_rx) + await regs.RX_F2_FreqWord.write(f2_fcw_rx) + await regs.Rx_Sample_Discard.write((tx_rx_sample_ratio-1 << 8) + tx_rx_sample_ratio-1) + await regs.LPF_Config_0.write((lpf_alpha << 8)) + await regs.LPF_Config_1.write((i_shift << 24) + i_gain) + await regs.LPF_Config_2.write((p_shift << 24) + p_gain) + await regs.Tx_Data_Width.write(tx_data_width) + await regs.Rx_Data_Width.write(rx_data_width) + await regs.PRBS_Control.write((autosync_threshold << 16) + 1) + await regs.PRBS_Polynomial.write((1 << 30) + (1 << 27)) + await regs.PRBS_Initial_State.write(0x8E7589FD) + await regs.PRBS_Error_Mask.write(1) + await regs.lowpass_ema_alpha1.write(64) + await regs.lowpass_ema_alpha2.write(64) + await regs.Tx_Sync_Ctrl.write(0b0001) + await regs.Tx_Sync_Cnt.write(192) + + + hash_id = await regs.Hash_ID_Low.read() + hash_id = await regs.Hash_ID_Low.read() + hash_id = await regs.Hash_ID_Low.read() + hash_id = await regs.Hash_ID_Low.read() + hash_id = await regs.Hash_ID_Low.read() print("Hash ID Low: ", hex(hash_id)) - hash_id = await regs.read("msk_top_regs", "Hash_ID_High") + hash_id = await regs.Hash_ID_High.read() print("Hash ID High: ", hex(hash_id)) await Timer(100, units="ns") await RisingEdge(dut.clk) - dut.s_axi_wvalid.value = 1 - dut.s_axi_awvalid.value = 1 - await regs.write("msk_top_regs", "MSK_Init", 0) - dut.s_axi_wvalid.value = 1 - dut.s_axi_awvalid.value = 1 - await regs.write("msk_top_regs", "MSK_Control", (diff_enc_loopback << 4) + (rx_invert <<2) + ptt) + await regs.MSK_Init.write(0) + await regs.MSK_Control.write((diff_enc_loopback << 4) + (rx_invert <<2) + ptt) await RisingEdge(dut.clk) @@ -830,8 +770,8 @@ async def msk_test_1(dut): await cocotb.start(msksim.rx_sample_capture()) await cocotb.start(ducsim.upconvert()) await cocotb.start(ddcsim.downconvert()) - #await cocotb.start(pn.generate_data()) - #await cocotb.start(pn.check_data()) + await cocotb.start(pn.generate_data()) + await cocotb.start(pn.check_data()) sim_time = get_sim_time("us") sim_start = sim_time @@ -861,11 +801,11 @@ async def msk_test_1(dut): # await regs.write("msk_top_regs", "PRBS_Control", data) if sim_time_d <= sim_start + 20000 and sim_time >= sim_start + 20000: - data = await regs.read("msk_top_regs", "PRBS_Control") + data = await regs.PRBS_Control.read() data = data | 0x2 dut.s_axi_wvalid.value = 1 dut.s_axi_awvalid.value = 1 - await regs.write("msk_top_regs", "PRBS_Control", data) + await regs.PRBS_Control.write(data) # if sim_time_d <= sim_start + 3000 and sim_time >= sim_start + 3000: # await pn.resync() @@ -885,13 +825,13 @@ async def msk_test_1(dut): sim_time_d = sim_time sim_time = get_sim_time("us") - data = await regs.read("msk_top_regs", "f1_nco_adjust") + data = await regs.f1_nco_adjust.read() print("F1 NCO Adjust: ", hex(data)) - data = await regs.read("msk_top_regs", "f2_nco_adjust") + data = await regs.f2_nco_adjust.read() print("F2 NCO Adjust: ", hex(data)) - data = await regs.read("msk_top_regs", "f1_error") + data = await regs.f1_error.read() print("F1 Error: ", hex(data)) - data = await regs.read("msk_top_regs", "f2_error") + data = await regs.f2_error.read() print("F2 Error: ", hex(data)) #data = await regs.read("msk_top_regs", "LPF_Accum_F1") # print("F1 Acc: ", hex(data)) @@ -929,9 +869,9 @@ async def msk_test_1(dut): # print("Ones: ", pn.ones_count) # print("Zeros: ", pn.zeros_count) - errs = await regs.read("msk_top_regs", "PRBS_Error_Count") + errs = await regs.PRBS_Error_Count.read() print("Bit errors: ", errs) - bits = await regs.read("msk_top_regs", "PRBS_Bit_Count") + bits = await regs.PRBS_Bit_Count.read() print("Bit count: ", bits) print("BER: ", (1.0*errs)/bits) diff --git a/sim/msk_top_nvc.gtkw b/sim/msk_top_nvc.gtkw index b0ef9ee..4c86d96 100644 --- a/sim/msk_top_nvc.gtkw +++ b/sim/msk_top_nvc.gtkw @@ -1,15 +1,15 @@ [*] [*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI -[*] Fri Oct 10 05:31:31 2025 +[*] Sun Oct 26 04:27:27 2025 [*] [dumpfile] "/Users/nonlinear/dev/pluto_msk/sim/msk_top.ghw" -[dumpfile_mtime] "Fri Oct 10 05:30:38 2025" -[dumpfile_size] 217869621 +[dumpfile_mtime] "Sun Oct 26 04:27:24 2025" +[dumpfile_size] 1112248 [savefile] "/Users/nonlinear/dev/pluto_msk/sim/msk_top_nvc.gtkw" [timestart] 0 [size] 1504 828 [pos] -1 -1 -*-42.987041 3950520428800 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +*-33.240414 190000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 [markername] AA [markername] BB [markername] CC @@ -42,6 +42,8 @@ [treeopen] msk_top.u_dem.u_f2. [treeopen] msk_top.u_mod. [treeopen] msk_top.u_msk_top_csr. +[treeopen] msk_top.u_msk_top_csr.u_msk_regs. +[treeopen] msk_top.u_msk_top_csr.u_msk_regs.field_storage.fb_freqword. [sst_width] 298 [signals_width] 383 [sst_expanded] 1 @@ -69,6 +71,9 @@ msk_top.u_mod.tx_sync_force @22 msk_top.u_mod.sync_counter[23:0] msk_top.u_mod.sync_counter_next[23:0] +msk_top.u_mod.freq_word_f1[31:0] +msk_top.u_mod.freq_word_f2[31:0] +msk_top.u_mod.freq_word_tclk[31:0] @200 - @22 @@ -366,7 +371,7 @@ msk_top.u_dem.rx_data -Differential Coder Loopback @c00200 -PRBS Generator -@29 +@28 msk_top.u_prbs_gen.clk msk_top.u_prbs_gen.data_in[0] msk_top.u_prbs_gen.data_out[0] @@ -375,11 +380,11 @@ msk_top.u_prbs_gen.error_arm msk_top.u_prbs_gen.error_insert msk_top.u_prbs_gen.error_insert_d msk_top.u_prbs_gen.init -@23 +@22 msk_top.u_prbs_gen.initial_state[30:0] msk_top.u_prbs_gen.lfsr[30:0] msk_top.u_prbs_gen.polynomial[30:0] -@29 +@28 msk_top.u_prbs_gen.prbs_sel @1401200 -PRBS Generator @@ -416,5 +421,605 @@ msk_top.u_prbs_mon.sync_now msk_top.u_prbs_mon.sync_threshold[15:0] @1000200 -PRBS Monitor +@28 +msk_top.u_msk_top_csr.clear_counts +msk_top.u_msk_top_csr.clk +msk_top.u_msk_top_csr.demod_sync_lock +msk_top.u_msk_top_csr.diff_encdec_lbk_ena +@22 +msk_top.u_msk_top_csr.discard_rxnco[7:0] +msk_top.u_msk_top_csr.discard_rxsamples[7:0] +msk_top.u_msk_top_csr.f1_error[31:0] +msk_top.u_msk_top_csr.f1_nco_adjust[31:0] +msk_top.u_msk_top_csr.f2_error[31:0] +msk_top.u_msk_top_csr.f2_nco_adjust[31:0] +msk_top.u_msk_top_csr.freq_word_ft[31:0] +msk_top.u_msk_top_csr.freq_word_rx_f1[31:0] +msk_top.u_msk_top_csr.freq_word_rx_f2[31:0] +msk_top.u_msk_top_csr.freq_word_tx_f1[31:0] +msk_top.u_msk_top_csr.freq_word_tx_f2[31:0] +msk_top.u_msk_top_csr.hwif_in.axis_xfer_count.xfer_count.next_q[31:0] +msk_top.u_msk_top_csr.hwif_in.f1_error.data.next_q[31:0] +msk_top.u_msk_top_csr.hwif_in.f1_nco_adjust.data.next_q[31:0] +msk_top.u_msk_top_csr.hwif_in.f2_error.data.next_q[31:0] +msk_top.u_msk_top_csr.hwif_in.f2_nco_adjust.data.next_q[31:0] +msk_top.u_msk_top_csr.hwif_in.lpf_accum_f1.status_data.next_q[31:0] +msk_top.u_msk_top_csr.hwif_in.lpf_accum_f2.status_data.next_q[31:0] +@28 +msk_top.u_msk_top_csr.hwif_in.msk_status.demod_sync_lock.next_q +msk_top.u_msk_top_csr.hwif_in.msk_status.rx_enable.next_q +msk_top.u_msk_top_csr.hwif_in.msk_status.tx_axis_valid.next_q +msk_top.u_msk_top_csr.hwif_in.msk_status.tx_enable.next_q +@22 +msk_top.u_msk_top_csr.hwif_in.prbs_bit_count.status_data.next_q[31:0] +msk_top.u_msk_top_csr.hwif_in.prbs_error_count.status_data.next_q[31:0] +msk_top.u_msk_top_csr.hwif_in.rx_power.rx_power.next_q[22:0] +msk_top.u_msk_top_csr.hwif_in.tx_enable_count.tx_ena_counter.next_q[31:0] +msk_top.u_msk_top_csr.hwif_out.fb_freqword.config_data.value[31:0] +msk_top.u_msk_top_csr.hwif_out.lowpass_ema_alpha1.alpha.value[17:0] +msk_top.u_msk_top_csr.hwif_out.lowpass_ema_alpha2.alpha.value[17:0] +msk_top.u_msk_top_csr.hwif_out.lpf_config_0.lpf_alpha.value[23:0] +@28 +msk_top.u_msk_top_csr.hwif_out.lpf_config_0.lpf_freeze.value +msk_top.u_msk_top_csr.hwif_out.lpf_config_0.lpf_zero.value +@22 +msk_top.u_msk_top_csr.hwif_out.lpf_config_0.prbs_reserved.value[5:0] +msk_top.u_msk_top_csr.hwif_out.lpf_config_1.i_gain.value[23:0] +msk_top.u_msk_top_csr.hwif_out.lpf_config_1.i_shift.value[7:0] +msk_top.u_msk_top_csr.hwif_out.lpf_config_2.p_gain.value[23:0] +msk_top.u_msk_top_csr.hwif_out.lpf_config_2.p_shift.value[7:0] +@28 +msk_top.u_msk_top_csr.hwif_out.msk_control.clear_counts.value +msk_top.u_msk_top_csr.hwif_out.msk_control.diff_encoder_loopback.value +msk_top.u_msk_top_csr.hwif_out.msk_control.loopback_ena.value +msk_top.u_msk_top_csr.hwif_out.msk_control.ptt.value +msk_top.u_msk_top_csr.hwif_out.msk_control.rx_invert.value +msk_top.u_msk_top_csr.hwif_out.msk_init.rxinit.value +msk_top.u_msk_top_csr.hwif_out.msk_init.txinit.value +msk_top.u_msk_top_csr.hwif_out.msk_init.txrxinit.value +msk_top.u_msk_top_csr.hwif_out.prbs_control.prbs_clear.value +msk_top.u_msk_top_csr.hwif_out.prbs_control.prbs_error_insert.value +msk_top.u_msk_top_csr.hwif_out.prbs_control.prbs_manual_sync.value +@22 +msk_top.u_msk_top_csr.hwif_out.prbs_control.prbs_reserved.value[11:0] +@28 +msk_top.u_msk_top_csr.hwif_out.prbs_control.prbs_sel.value +@22 +msk_top.u_msk_top_csr.hwif_out.prbs_control.prbs_sync_threshold.value[15:0] +msk_top.u_msk_top_csr.hwif_out.prbs_error_mask.config_data.value[31:0] +msk_top.u_msk_top_csr.hwif_out.prbs_initial_state.config_data.value[31:0] +msk_top.u_msk_top_csr.hwif_out.prbs_polynomial.config_data.value[31:0] +msk_top.u_msk_top_csr.hwif_out.rx_data_width.data_width.value[7:0] +msk_top.u_msk_top_csr.hwif_out.rx_f1_freqword.config_data.value[31:0] +msk_top.u_msk_top_csr.hwif_out.rx_f2_freqword.config_data.value[31:0] +msk_top.u_msk_top_csr.hwif_out.rx_sample_discard.rx_nco_discard.value[7:0] +msk_top.u_msk_top_csr.hwif_out.rx_sample_discard.rx_sample_discard.value[7:0] +msk_top.u_msk_top_csr.hwif_out.tx_data_width.data_width.value[7:0] +msk_top.u_msk_top_csr.hwif_out.tx_f1_freqword.config_data.value[31:0] +msk_top.u_msk_top_csr.hwif_out.tx_f2_freqword.config_data.value[31:0] +msk_top.u_msk_top_csr.hwif_out.tx_sync_cnt.tx_sync_cnt.value[23:0] +@28 +msk_top.u_msk_top_csr.hwif_out.tx_sync_ctrl.tx_sync_ena.value +msk_top.u_msk_top_csr.hwif_out.tx_sync_ctrl.tx_sync_f1.value +msk_top.u_msk_top_csr.hwif_out.tx_sync_ctrl.tx_sync_f2.value +msk_top.u_msk_top_csr.hwif_out.tx_sync_ctrl.tx_sync_force.value +msk_top.u_msk_top_csr.loopback_ena +@22 +msk_top.u_msk_top_csr.lpf_accum_f1[31:0] +msk_top.u_msk_top_csr.lpf_accum_f2[31:0] +msk_top.u_msk_top_csr.lpf_alpha[23:0] +@28 +msk_top.u_msk_top_csr.lpf_freeze +@22 +msk_top.u_msk_top_csr.lpf_i_gain[23:0] +msk_top.u_msk_top_csr.lpf_i_shift[7:0] +msk_top.u_msk_top_csr.lpf_p_gain[23:0] +msk_top.u_msk_top_csr.lpf_p_shift[7:0] +@28 +msk_top.u_msk_top_csr.lpf_zero +@22 +msk_top.u_msk_top_csr.pd_alpha1[17:0] +msk_top.u_msk_top_csr.pd_alpha2[17:0] +msk_top.u_msk_top_csr.pd_power[22:0] +msk_top.u_msk_top_csr.prbs_bits[31:0] +@28 +msk_top.u_msk_top_csr.prbs_clear +msk_top.u_msk_top_csr.prbs_err_insert +@22 +msk_top.u_msk_top_csr.prbs_err_mask[31:0] +msk_top.u_msk_top_csr.prbs_errs[31:0] +msk_top.u_msk_top_csr.prbs_initial[31:0] +@28 +msk_top.u_msk_top_csr.prbs_manual_sync +@22 +msk_top.u_msk_top_csr.prbs_poly[31:0] +@28 +msk_top.u_msk_top_csr.prbs_sel +@22 +msk_top.u_msk_top_csr.prbs_sync_threshold[15:0] +@28 +msk_top.u_msk_top_csr.ptt +@22 +msk_top.u_msk_top_csr.rx_data_w[7:0] +@28 +msk_top.u_msk_top_csr.rx_enable +msk_top.u_msk_top_csr.rx_invert +msk_top.u_msk_top_csr.rxinit +msk_top.u_msk_top_csr.s_axi_aclk +@22 +msk_top.u_msk_top_csr.s_axi_araddr[31:0] +@28 +msk_top.u_msk_top_csr.s_axi_aresetn +msk_top.u_msk_top_csr.s_axi_arprot[2:0] +msk_top.u_msk_top_csr.s_axi_arready +msk_top.u_msk_top_csr.s_axi_arvalid +@22 +msk_top.u_msk_top_csr.s_axi_awaddr[31:0] +@28 +msk_top.u_msk_top_csr.s_axi_awprot[2:0] +msk_top.u_msk_top_csr.s_axi_awready +msk_top.u_msk_top_csr.s_axi_awvalid +msk_top.u_msk_top_csr.s_axi_bready +msk_top.u_msk_top_csr.s_axi_bresp[1:0] +msk_top.u_msk_top_csr.s_axi_bvalid +@22 +msk_top.u_msk_top_csr.s_axi_rdata[31:0] +@28 +msk_top.u_msk_top_csr.s_axi_rready +msk_top.u_msk_top_csr.s_axi_rresp[1:0] +msk_top.u_msk_top_csr.s_axi_rvalid +@22 +msk_top.u_msk_top_csr.s_axi_wdata[31:0] +@28 +msk_top.u_msk_top_csr.s_axi_wready +@22 +msk_top.u_msk_top_csr.s_axi_wstrb[3:0] +@28 +msk_top.u_msk_top_csr.s_axi_wvalid +@c00023 +msk_top.u_msk_top_csr.s_axil_i.araddr[7:0] +@28 +(0)msk_top.u_msk_top_csr.s_axil_i.araddr[7:0] +(1)msk_top.u_msk_top_csr.s_axil_i.araddr[7:0] +(2)msk_top.u_msk_top_csr.s_axil_i.araddr[7:0] +(3)msk_top.u_msk_top_csr.s_axil_i.araddr[7:0] +(4)msk_top.u_msk_top_csr.s_axil_i.araddr[7:0] +(5)msk_top.u_msk_top_csr.s_axil_i.araddr[7:0] +(6)msk_top.u_msk_top_csr.s_axil_i.araddr[7:0] +(7)msk_top.u_msk_top_csr.s_axil_i.araddr[7:0] +@1401201 +-group_end +@28 +msk_top.u_msk_top_csr.s_axil_i.arprot[2:0] +msk_top.u_msk_top_csr.s_axil_i.arvalid +@22 +msk_top.u_msk_top_csr.s_axil_i.awaddr[7:0] +@28 +msk_top.u_msk_top_csr.s_axil_i.awprot[2:0] +msk_top.u_msk_top_csr.s_axil_i.awvalid +msk_top.u_msk_top_csr.s_axil_i.bready +msk_top.u_msk_top_csr.s_axil_i.rready +@22 +msk_top.u_msk_top_csr.s_axil_i.wdata[31:0] +msk_top.u_msk_top_csr.s_axil_i.wstrb[3:0] +@28 +msk_top.u_msk_top_csr.s_axil_i.wvalid +msk_top.u_msk_top_csr.s_axil_o.arready +msk_top.u_msk_top_csr.u_msk_regs.decoded_reg_strb.tx_f1_freqword +msk_top.u_msk_top_csr.s_axil_o.awready +msk_top.u_msk_top_csr.s_axil_o.bresp[1:0] +msk_top.u_msk_top_csr.s_axil_o.bvalid +@22 +msk_top.u_msk_top_csr.s_axil_o.rdata[31:0] +@28 +msk_top.u_msk_top_csr.s_axil_o.rresp[1:0] +msk_top.u_msk_top_csr.s_axil_o.rvalid +msk_top.u_msk_top_csr.s_axil_o.wready +msk_top.u_msk_top_csr.tx_axis_valid +@22 +msk_top.u_msk_top_csr.tx_bit_counter[31:0] +msk_top.u_msk_top_csr.tx_data_w[7:0] +msk_top.u_msk_top_csr.tx_ena_counter[31:0] +@28 +msk_top.u_msk_top_csr.tx_enable +msk_top.u_msk_top_csr.tx_req +@22 +msk_top.u_msk_top_csr.tx_sync_cnt[23:0] +@28 +msk_top.u_msk_top_csr.tx_sync_ena +msk_top.u_msk_top_csr.tx_sync_f1 +msk_top.u_msk_top_csr.tx_sync_f2 +msk_top.u_msk_top_csr.tx_sync_force +msk_top.u_msk_top_csr.txinit +msk_top.u_msk_top_csr.txrxinit +msk_top.u_msk_top_csr.u01s.clk +msk_top.u_msk_top_csr.u01s.di +msk_top.u_msk_top_csr.u01s.di_s[0:1] +msk_top.u_msk_top_csr.u01s.do +msk_top.u_msk_top_csr.u02s.clk +msk_top.u_msk_top_csr.u02s.di_s[0:1] +msk_top.u_msk_top_csr.u02s.do +msk_top.u_msk_top_csr.u03s.clk +msk_top.u_msk_top_csr.u03s.di_s[0:1] +msk_top.u_msk_top_csr.u03s.do +msk_top.u_msk_top_csr.u04s.clk +msk_top.u_msk_top_csr.u04s.di +msk_top.u_msk_top_csr.u04s.di_s[0:1] +msk_top.u_msk_top_csr.u04s.do +msk_top.u_msk_top_csr.u05s.clk +msk_top.u_msk_top_csr.u05s.di +msk_top.u_msk_top_csr.u05s.di_s[0:1] +msk_top.u_msk_top_csr.u05s.do +msk_top.u_msk_top_csr.u06s.clk +msk_top.u_msk_top_csr.u06s.di +msk_top.u_msk_top_csr.u06s.di_s[0:1] +msk_top.u_msk_top_csr.u06s.do +msk_top.u_msk_top_csr.u07s.clk +msk_top.u_msk_top_csr.u07s.di +msk_top.u_msk_top_csr.u07s.di_s[0:1] +msk_top.u_msk_top_csr.u07s.do +msk_top.u_msk_top_csr.u08s.clk +msk_top.u_msk_top_csr.u08s.di +msk_top.u_msk_top_csr.u08s.di_s[0:1] +msk_top.u_msk_top_csr.u08s.do +msk_top.u_msk_top_csr.u09s.clk +msk_top.u_msk_top_csr.u09s.di +msk_top.u_msk_top_csr.u09s.di_s[0:1] +msk_top.u_msk_top_csr.u09s.do +msk_top.u_msk_top_csr.u10s.clk +msk_top.u_msk_top_csr.u10s.di +msk_top.u_msk_top_csr.u10s.di_s[0:1] +msk_top.u_msk_top_csr.u10s.do +msk_top.u_msk_top_csr.u11s.clk +msk_top.u_msk_top_csr.u11s.di +msk_top.u_msk_top_csr.u11s.di_s[0:1] +msk_top.u_msk_top_csr.u11s.do +msk_top.u_msk_top_csr.u12s.clk +msk_top.u_msk_top_csr.u12s.di +msk_top.u_msk_top_csr.u12s.di_s[0:1] +msk_top.u_msk_top_csr.u12s.do +msk_top.u_msk_top_csr.u13s.clk +msk_top.u_msk_top_csr.u13s.di +msk_top.u_msk_top_csr.u13s.di_s[0:1] +msk_top.u_msk_top_csr.u13s.do +msk_top.u_msk_top_csr.u14s.clk +msk_top.u_msk_top_csr.u14s.di +msk_top.u_msk_top_csr.u14s.di_s[0:1] +msk_top.u_msk_top_csr.u14s.do +msk_top.u_msk_top_csr.u15s.clk +msk_top.u_msk_top_csr.u15s.di +msk_top.u_msk_top_csr.u15s.di_s[0:1] +msk_top.u_msk_top_csr.u15s.do +msk_top.u_msk_top_csr.u16s.clk +msk_top.u_msk_top_csr.u16s.di +msk_top.u_msk_top_csr.u16s.di_s[0:1] +msk_top.u_msk_top_csr.u16s.do +msk_top.u_msk_top_csr.u_msk_regs.axil_ar_accept +@22 +msk_top.u_msk_top_csr.u_msk_regs.axil_araddr[7:0] +msk_top.u_msk_top_csr.s_axil_i.araddr[7:0] +@28 +msk_top.u_msk_top_csr.u_msk_regs.axil_arvalid +msk_top.u_msk_top_csr.u_msk_regs.axil_aw_accept +@22 +msk_top.u_msk_top_csr.u_msk_regs.axil_awaddr[7:0] +@28 +msk_top.u_msk_top_csr.u_msk_regs.axil_awvalid +msk_top.u_msk_top_csr.u_msk_regs.axil_n_in_flight[1:0] +msk_top.u_msk_top_csr.u_msk_regs.axil_prev_was_rd +msk_top.u_msk_top_csr.u_msk_regs.axil_resp_acked +msk_top.u_msk_top_csr.u_msk_regs.axil_resp_rptr[1:0] +msk_top.u_msk_top_csr.u_msk_regs.axil_resp_wptr[1:0] +@22 +msk_top.u_msk_top_csr.u_msk_regs.axil_wdata[31:0] +msk_top.u_msk_top_csr.u_msk_regs.axil_wstrb[3:0] +@28 +msk_top.u_msk_top_csr.u_msk_regs.axil_wvalid +msk_top.u_msk_top_csr.u_msk_regs.clk +@22 +msk_top.u_msk_top_csr.u_msk_regs.cpuif_addr[7:0] +@28 +msk_top.u_msk_top_csr.u_msk_regs.cpuif_rd_ack +@22 +msk_top.u_msk_top_csr.u_msk_regs.cpuif_rd_data[31:0] +@28 +msk_top.u_msk_top_csr.u_msk_regs.cpuif_rd_err +msk_top.u_msk_top_csr.u_msk_regs.cpuif_req +msk_top.u_msk_top_csr.u_msk_regs.cpuif_req_is_wr +msk_top.u_msk_top_csr.u_msk_regs.cpuif_req_masked +msk_top.u_msk_top_csr.u_msk_regs.cpuif_req_stall_rd +msk_top.u_msk_top_csr.u_msk_regs.cpuif_req_stall_wr +msk_top.u_msk_top_csr.u_msk_regs.cpuif_wr_ack +@22 +msk_top.u_msk_top_csr.u_msk_regs.cpuif_wr_biten[31:0] +msk_top.u_msk_top_csr.u_msk_regs.cpuif_wr_data[31:0] +@28 +msk_top.u_msk_top_csr.u_msk_regs.cpuif_wr_err +msk_top.u_msk_top_csr.u_msk_regs.decoded_reg_strb.axis_xfer_count +msk_top.u_msk_top_csr.u_msk_regs.decoded_reg_strb.f1_error +msk_top.u_msk_top_csr.u_msk_regs.decoded_reg_strb.f1_nco_adjust +msk_top.u_msk_top_csr.u_msk_regs.decoded_reg_strb.f2_error +msk_top.u_msk_top_csr.u_msk_regs.decoded_reg_strb.f2_nco_adjust +msk_top.u_msk_top_csr.u_msk_regs.decoded_reg_strb.fb_freqword +msk_top.u_msk_top_csr.u_msk_regs.decoded_reg_strb.hash_id_high +msk_top.u_msk_top_csr.u_msk_regs.decoded_reg_strb.hash_id_low +msk_top.u_msk_top_csr.u_msk_regs.decoded_reg_strb.lowpass_ema_alpha1 +msk_top.u_msk_top_csr.u_msk_regs.decoded_reg_strb.lowpass_ema_alpha2 +msk_top.u_msk_top_csr.u_msk_regs.decoded_reg_strb.lpf_accum_f1 +msk_top.u_msk_top_csr.u_msk_regs.decoded_reg_strb.lpf_accum_f2 +msk_top.u_msk_top_csr.u_msk_regs.decoded_reg_strb.lpf_config_0 +msk_top.u_msk_top_csr.u_msk_regs.decoded_reg_strb.lpf_config_1 +msk_top.u_msk_top_csr.u_msk_regs.decoded_reg_strb.lpf_config_2 +msk_top.u_msk_top_csr.u_msk_regs.decoded_reg_strb.msk_control +msk_top.u_msk_top_csr.u_msk_regs.decoded_reg_strb.msk_init +msk_top.u_msk_top_csr.u_msk_regs.decoded_reg_strb.msk_status +msk_top.u_msk_top_csr.u_msk_regs.decoded_reg_strb.prbs_bit_count +msk_top.u_msk_top_csr.u_msk_regs.decoded_reg_strb.prbs_control +msk_top.u_msk_top_csr.u_msk_regs.decoded_reg_strb.prbs_error_count +msk_top.u_msk_top_csr.u_msk_regs.decoded_reg_strb.prbs_error_mask +msk_top.u_msk_top_csr.u_msk_regs.decoded_reg_strb.prbs_initial_state +msk_top.u_msk_top_csr.u_msk_regs.decoded_reg_strb.prbs_polynomial +msk_top.u_msk_top_csr.u_msk_regs.decoded_reg_strb.rx_data_width +msk_top.u_msk_top_csr.u_msk_regs.decoded_reg_strb.rx_f1_freqword +msk_top.u_msk_top_csr.u_msk_regs.decoded_reg_strb.rx_f2_freqword +msk_top.u_msk_top_csr.u_msk_regs.decoded_reg_strb.rx_power +msk_top.u_msk_top_csr.u_msk_regs.decoded_reg_strb.rx_sample_discard +msk_top.u_msk_top_csr.u_msk_regs.decoded_reg_strb.tx_bit_count +msk_top.u_msk_top_csr.u_msk_regs.decoded_reg_strb.tx_data_width +msk_top.u_msk_top_csr.u_msk_regs.decoded_reg_strb.tx_enable_count +msk_top.u_msk_top_csr.u_msk_regs.decoded_reg_strb.tx_f1_freqword +msk_top.u_msk_top_csr.u_msk_regs.decoded_reg_strb.tx_f2_freqword +msk_top.u_msk_top_csr.u_msk_regs.decoded_reg_strb.tx_sync_cnt +msk_top.u_msk_top_csr.u_msk_regs.decoded_reg_strb.tx_sync_ctrl +msk_top.u_msk_top_csr.u_msk_regs.decoded_req +msk_top.u_msk_top_csr.u_msk_regs.decoded_req_is_wr +@22 +msk_top.u_msk_top_csr.u_msk_regs.decoded_wr_biten[31:0] +msk_top.u_msk_top_csr.u_msk_regs.decoded_wr_data[31:0] +@28 +msk_top.u_msk_top_csr.u_msk_regs.field_combo.fb_freqword.config_data.load_next +@22 +msk_top.u_msk_top_csr.u_msk_regs.field_combo.fb_freqword.config_data.next_q[31:0] +@28 +msk_top.u_msk_top_csr.u_msk_regs.field_combo.lowpass_ema_alpha1.alpha.load_next +@22 +msk_top.u_msk_top_csr.u_msk_regs.field_combo.lowpass_ema_alpha1.alpha.next_q[17:0] +@28 +msk_top.u_msk_top_csr.u_msk_regs.field_combo.lowpass_ema_alpha2.alpha.load_next +@22 +msk_top.u_msk_top_csr.u_msk_regs.field_combo.lowpass_ema_alpha2.alpha.next_q[17:0] +@28 +msk_top.u_msk_top_csr.u_msk_regs.field_combo.lpf_config_0.lpf_alpha.load_next +@22 +msk_top.u_msk_top_csr.u_msk_regs.field_combo.lpf_config_0.lpf_alpha.next_q[23:0] +@28 +msk_top.u_msk_top_csr.u_msk_regs.field_combo.lpf_config_0.lpf_freeze.load_next +msk_top.u_msk_top_csr.u_msk_regs.field_combo.lpf_config_0.lpf_freeze.next_q +msk_top.u_msk_top_csr.u_msk_regs.field_combo.lpf_config_0.lpf_zero.load_next +msk_top.u_msk_top_csr.u_msk_regs.field_combo.lpf_config_0.lpf_zero.next_q +msk_top.u_msk_top_csr.u_msk_regs.field_combo.lpf_config_0.prbs_reserved.load_next +@22 +msk_top.u_msk_top_csr.u_msk_regs.field_combo.lpf_config_0.prbs_reserved.next_q[5:0] +@28 +msk_top.u_msk_top_csr.u_msk_regs.field_combo.lpf_config_1.i_gain.load_next +@22 +msk_top.u_msk_top_csr.u_msk_regs.field_combo.lpf_config_1.i_gain.next_q[23:0] +@28 +msk_top.u_msk_top_csr.u_msk_regs.field_combo.lpf_config_1.i_shift.load_next +@22 +msk_top.u_msk_top_csr.u_msk_regs.field_combo.lpf_config_1.i_shift.next_q[7:0] +@28 +msk_top.u_msk_top_csr.u_msk_regs.field_combo.lpf_config_2.p_gain.load_next +@22 +msk_top.u_msk_top_csr.u_msk_regs.field_combo.lpf_config_2.p_gain.next_q[23:0] +@28 +msk_top.u_msk_top_csr.u_msk_regs.field_combo.lpf_config_2.p_shift.load_next +@22 +msk_top.u_msk_top_csr.u_msk_regs.field_combo.lpf_config_2.p_shift.next_q[7:0] +@28 +msk_top.u_msk_top_csr.u_msk_regs.field_combo.msk_control.clear_counts.load_next +msk_top.u_msk_top_csr.u_msk_regs.field_combo.msk_control.clear_counts.next_q +msk_top.u_msk_top_csr.u_msk_regs.field_combo.msk_control.diff_encoder_loopback.load_next +msk_top.u_msk_top_csr.u_msk_regs.field_combo.msk_control.diff_encoder_loopback.next_q +msk_top.u_msk_top_csr.u_msk_regs.field_combo.msk_control.loopback_ena.load_next +msk_top.u_msk_top_csr.u_msk_regs.field_combo.msk_control.loopback_ena.next_q +msk_top.u_msk_top_csr.u_msk_regs.field_combo.msk_control.ptt.load_next +msk_top.u_msk_top_csr.u_msk_regs.field_combo.msk_control.ptt.next_q +msk_top.u_msk_top_csr.u_msk_regs.field_combo.msk_control.rx_invert.load_next +msk_top.u_msk_top_csr.u_msk_regs.field_combo.msk_control.rx_invert.next_q +msk_top.u_msk_top_csr.u_msk_regs.field_combo.msk_init.rxinit.load_next +msk_top.u_msk_top_csr.u_msk_regs.field_combo.msk_init.rxinit.next_q +msk_top.u_msk_top_csr.u_msk_regs.field_combo.msk_init.txinit.load_next +msk_top.u_msk_top_csr.u_msk_regs.field_combo.msk_init.txinit.next_q +msk_top.u_msk_top_csr.u_msk_regs.field_combo.msk_init.txrxinit.load_next +msk_top.u_msk_top_csr.u_msk_regs.field_combo.msk_init.txrxinit.next_q +msk_top.u_msk_top_csr.u_msk_regs.field_combo.prbs_control.prbs_clear.load_next +msk_top.u_msk_top_csr.u_msk_regs.field_combo.prbs_control.prbs_clear.next_q +msk_top.u_msk_top_csr.u_msk_regs.field_combo.prbs_control.prbs_error_insert.load_next +msk_top.u_msk_top_csr.u_msk_regs.field_combo.prbs_control.prbs_error_insert.next_q +msk_top.u_msk_top_csr.u_msk_regs.field_combo.prbs_control.prbs_manual_sync.load_next +msk_top.u_msk_top_csr.u_msk_regs.field_combo.prbs_control.prbs_manual_sync.next_q +msk_top.u_msk_top_csr.u_msk_regs.field_combo.prbs_control.prbs_reserved.load_next +@22 +msk_top.u_msk_top_csr.u_msk_regs.field_combo.prbs_control.prbs_reserved.next_q[11:0] +@28 +msk_top.u_msk_top_csr.u_msk_regs.field_combo.prbs_control.prbs_sel.load_next +msk_top.u_msk_top_csr.u_msk_regs.field_combo.prbs_control.prbs_sel.next_q +msk_top.u_msk_top_csr.u_msk_regs.field_combo.prbs_control.prbs_sync_threshold.load_next +@22 +msk_top.u_msk_top_csr.u_msk_regs.field_combo.prbs_control.prbs_sync_threshold.next_q[15:0] +@28 +msk_top.u_msk_top_csr.u_msk_regs.field_combo.prbs_error_mask.config_data.load_next +@22 +msk_top.u_msk_top_csr.u_msk_regs.field_combo.prbs_error_mask.config_data.next_q[31:0] +@28 +msk_top.u_msk_top_csr.u_msk_regs.field_combo.prbs_initial_state.config_data.load_next +@22 +msk_top.u_msk_top_csr.u_msk_regs.field_combo.prbs_initial_state.config_data.next_q[31:0] +@28 +msk_top.u_msk_top_csr.u_msk_regs.field_combo.prbs_polynomial.config_data.load_next +@22 +msk_top.u_msk_top_csr.u_msk_regs.field_combo.prbs_polynomial.config_data.next_q[31:0] +@28 +msk_top.u_msk_top_csr.u_msk_regs.field_combo.rx_data_width.data_width.load_next +@22 +msk_top.u_msk_top_csr.u_msk_regs.field_combo.rx_data_width.data_width.next_q[7:0] +@28 +msk_top.u_msk_top_csr.u_msk_regs.field_combo.rx_f1_freqword.config_data.load_next +@22 +msk_top.u_msk_top_csr.u_msk_regs.field_combo.rx_f1_freqword.config_data.next_q[31:0] +@28 +msk_top.u_msk_top_csr.u_msk_regs.field_combo.rx_f2_freqword.config_data.load_next +@22 +msk_top.u_msk_top_csr.u_msk_regs.field_combo.rx_f2_freqword.config_data.next_q[31:0] +@28 +msk_top.u_msk_top_csr.u_msk_regs.field_combo.rx_sample_discard.rx_nco_discard.load_next +@22 +msk_top.u_msk_top_csr.u_msk_regs.field_combo.rx_sample_discard.rx_nco_discard.next_q[7:0] +@28 +msk_top.u_msk_top_csr.u_msk_regs.field_combo.rx_sample_discard.rx_sample_discard.load_next +@22 +msk_top.u_msk_top_csr.u_msk_regs.field_combo.rx_sample_discard.rx_sample_discard.next_q[7:0] +@28 +msk_top.u_msk_top_csr.u_msk_regs.field_combo.tx_data_width.data_width.load_next +@22 +msk_top.u_msk_top_csr.u_msk_regs.field_combo.tx_data_width.data_width.next_q[7:0] +@28 +msk_top.u_msk_top_csr.u_msk_regs.field_combo.tx_f1_freqword.config_data.load_next +@22 +msk_top.u_msk_top_csr.u_msk_regs.field_combo.tx_f1_freqword.config_data.next_q[31:0] +@28 +msk_top.u_msk_top_csr.u_msk_regs.field_combo.tx_f2_freqword.config_data.load_next +@22 +msk_top.u_msk_top_csr.u_msk_regs.field_combo.tx_f2_freqword.config_data.next_q[31:0] +@28 +msk_top.u_msk_top_csr.u_msk_regs.field_combo.tx_sync_cnt.tx_sync_cnt.load_next +@22 +msk_top.u_msk_top_csr.u_msk_regs.field_combo.tx_sync_cnt.tx_sync_cnt.next_q[23:0] +@28 +msk_top.u_msk_top_csr.u_msk_regs.field_combo.tx_sync_ctrl.tx_sync_ena.load_next +msk_top.u_msk_top_csr.u_msk_regs.field_combo.tx_sync_ctrl.tx_sync_ena.next_q +msk_top.u_msk_top_csr.u_msk_regs.field_combo.tx_sync_ctrl.tx_sync_f1.load_next +msk_top.u_msk_top_csr.u_msk_regs.field_combo.tx_sync_ctrl.tx_sync_f1.next_q +msk_top.u_msk_top_csr.u_msk_regs.field_combo.tx_sync_ctrl.tx_sync_f2.load_next +msk_top.u_msk_top_csr.u_msk_regs.field_combo.tx_sync_ctrl.tx_sync_f2.next_q +msk_top.u_msk_top_csr.u_msk_regs.field_combo.tx_sync_ctrl.tx_sync_force.load_next +msk_top.u_msk_top_csr.u_msk_regs.field_combo.tx_sync_ctrl.tx_sync_force.next_q +@22 +msk_top.u_msk_top_csr.u_msk_regs.field_storage.fb_freqword.config_data.value[31:0] +msk_top.u_msk_top_csr.u_msk_regs.field_storage.lowpass_ema_alpha1.alpha.value[17:0] +msk_top.u_msk_top_csr.u_msk_regs.field_storage.lowpass_ema_alpha2.alpha.value[17:0] +msk_top.u_msk_top_csr.u_msk_regs.field_storage.lpf_config_0.lpf_alpha.value[23:0] +@28 +msk_top.u_msk_top_csr.u_msk_regs.field_storage.lpf_config_0.lpf_freeze.value +msk_top.u_msk_top_csr.u_msk_regs.field_storage.lpf_config_0.lpf_zero.value +@22 +msk_top.u_msk_top_csr.u_msk_regs.field_storage.lpf_config_0.prbs_reserved.value[5:0] +msk_top.u_msk_top_csr.u_msk_regs.field_storage.lpf_config_1.i_gain.value[23:0] +msk_top.u_msk_top_csr.u_msk_regs.field_storage.lpf_config_1.i_shift.value[7:0] +msk_top.u_msk_top_csr.u_msk_regs.field_storage.lpf_config_2.p_gain.value[23:0] +msk_top.u_msk_top_csr.u_msk_regs.field_storage.lpf_config_2.p_shift.value[7:0] +@28 +msk_top.u_msk_top_csr.u_msk_regs.field_storage.msk_control.clear_counts.value +msk_top.u_msk_top_csr.u_msk_regs.field_storage.msk_control.diff_encoder_loopback.value +msk_top.u_msk_top_csr.u_msk_regs.field_storage.msk_control.loopback_ena.value +msk_top.u_msk_top_csr.u_msk_regs.field_storage.msk_control.ptt.value +msk_top.u_msk_top_csr.u_msk_regs.field_storage.msk_control.rx_invert.value +msk_top.u_msk_top_csr.u_msk_regs.field_storage.msk_init.rxinit.value +msk_top.u_msk_top_csr.u_msk_regs.field_storage.msk_init.txinit.value +msk_top.u_msk_top_csr.u_msk_regs.field_storage.msk_init.txrxinit.value +msk_top.u_msk_top_csr.u_msk_regs.field_storage.prbs_control.prbs_clear.value +msk_top.u_msk_top_csr.u_msk_regs.field_storage.prbs_control.prbs_error_insert.value +msk_top.u_msk_top_csr.u_msk_regs.field_storage.prbs_control.prbs_manual_sync.value +@22 +msk_top.u_msk_top_csr.u_msk_regs.field_storage.prbs_control.prbs_reserved.value[11:0] +@28 +msk_top.u_msk_top_csr.u_msk_regs.field_storage.prbs_control.prbs_sel.value +@22 +msk_top.u_msk_top_csr.u_msk_regs.field_storage.prbs_control.prbs_sync_threshold.value[15:0] +msk_top.u_msk_top_csr.u_msk_regs.field_storage.prbs_error_mask.config_data.value[31:0] +msk_top.u_msk_top_csr.u_msk_regs.field_storage.prbs_initial_state.config_data.value[31:0] +msk_top.u_msk_top_csr.u_msk_regs.field_storage.prbs_polynomial.config_data.value[31:0] +msk_top.u_msk_top_csr.u_msk_regs.field_storage.rx_data_width.data_width.value[7:0] +msk_top.u_msk_top_csr.u_msk_regs.field_storage.rx_f1_freqword.config_data.value[31:0] +msk_top.u_msk_top_csr.u_msk_regs.field_storage.rx_f2_freqword.config_data.value[31:0] +msk_top.u_msk_top_csr.u_msk_regs.field_storage.rx_sample_discard.rx_nco_discard.value[7:0] +msk_top.u_msk_top_csr.u_msk_regs.field_storage.rx_sample_discard.rx_sample_discard.value[7:0] +msk_top.u_msk_top_csr.u_msk_regs.field_storage.tx_data_width.data_width.value[7:0] +msk_top.u_msk_top_csr.u_msk_regs.field_storage.tx_f1_freqword.config_data.value[31:0] +msk_top.u_msk_top_csr.u_msk_regs.field_storage.tx_f2_freqword.config_data.value[31:0] +msk_top.u_msk_top_csr.u_msk_regs.field_storage.tx_sync_cnt.tx_sync_cnt.value[23:0] +@28 +msk_top.u_msk_top_csr.u_msk_regs.field_storage.tx_sync_ctrl.tx_sync_ena.value +msk_top.u_msk_top_csr.u_msk_regs.field_storage.tx_sync_ctrl.tx_sync_f1.value +msk_top.u_msk_top_csr.u_msk_regs.field_storage.tx_sync_ctrl.tx_sync_f2.value +msk_top.u_msk_top_csr.u_msk_regs.field_storage.tx_sync_ctrl.tx_sync_force.value +@22 +msk_top.u_msk_top_csr.u_msk_regs.hwif_out.fb_freqword.config_data.value[31:0] +msk_top.u_msk_top_csr.u_msk_regs.hwif_out.lowpass_ema_alpha1.alpha.value[17:0] +msk_top.u_msk_top_csr.u_msk_regs.hwif_out.lowpass_ema_alpha2.alpha.value[17:0] +msk_top.u_msk_top_csr.u_msk_regs.hwif_out.lpf_config_0.lpf_alpha.value[23:0] +@28 +msk_top.u_msk_top_csr.u_msk_regs.hwif_out.lpf_config_0.lpf_freeze.value +msk_top.u_msk_top_csr.u_msk_regs.hwif_out.lpf_config_0.lpf_zero.value +@22 +msk_top.u_msk_top_csr.u_msk_regs.hwif_out.lpf_config_0.prbs_reserved.value[5:0] +msk_top.u_msk_top_csr.u_msk_regs.hwif_out.lpf_config_1.i_gain.value[23:0] +msk_top.u_msk_top_csr.u_msk_regs.hwif_out.lpf_config_1.i_shift.value[7:0] +msk_top.u_msk_top_csr.u_msk_regs.hwif_out.lpf_config_2.p_gain.value[23:0] +msk_top.u_msk_top_csr.u_msk_regs.hwif_out.lpf_config_2.p_shift.value[7:0] +@28 +msk_top.u_msk_top_csr.u_msk_regs.hwif_out.msk_control.clear_counts.value +msk_top.u_msk_top_csr.u_msk_regs.hwif_out.msk_control.diff_encoder_loopback.value +msk_top.u_msk_top_csr.u_msk_regs.hwif_out.msk_control.loopback_ena.value +msk_top.u_msk_top_csr.u_msk_regs.hwif_out.msk_control.ptt.value +msk_top.u_msk_top_csr.u_msk_regs.hwif_out.msk_control.rx_invert.value +msk_top.u_msk_top_csr.u_msk_regs.hwif_out.msk_init.rxinit.value +msk_top.u_msk_top_csr.u_msk_regs.hwif_out.msk_init.txinit.value +msk_top.u_msk_top_csr.u_msk_regs.hwif_out.msk_init.txrxinit.value +msk_top.u_msk_top_csr.u_msk_regs.hwif_out.prbs_control.prbs_clear.value +msk_top.u_msk_top_csr.u_msk_regs.hwif_out.prbs_control.prbs_error_insert.value +msk_top.u_msk_top_csr.u_msk_regs.hwif_out.prbs_control.prbs_manual_sync.value +@22 +msk_top.u_msk_top_csr.u_msk_regs.hwif_out.prbs_control.prbs_reserved.value[11:0] +@28 +msk_top.u_msk_top_csr.u_msk_regs.hwif_out.prbs_control.prbs_sel.value +@22 +msk_top.u_msk_top_csr.u_msk_regs.hwif_out.prbs_control.prbs_sync_threshold.value[15:0] +msk_top.u_msk_top_csr.u_msk_regs.hwif_out.prbs_error_mask.config_data.value[31:0] +msk_top.u_msk_top_csr.u_msk_regs.hwif_out.prbs_initial_state.config_data.value[31:0] +msk_top.u_msk_top_csr.u_msk_regs.hwif_out.prbs_polynomial.config_data.value[31:0] +msk_top.u_msk_top_csr.u_msk_regs.hwif_out.rx_data_width.data_width.value[7:0] +msk_top.u_msk_top_csr.u_msk_regs.hwif_out.rx_f1_freqword.config_data.value[31:0] +msk_top.u_msk_top_csr.u_msk_regs.hwif_out.rx_f2_freqword.config_data.value[31:0] +msk_top.u_msk_top_csr.u_msk_regs.hwif_out.rx_sample_discard.rx_nco_discard.value[7:0] +msk_top.u_msk_top_csr.u_msk_regs.hwif_out.rx_sample_discard.rx_sample_discard.value[7:0] +msk_top.u_msk_top_csr.u_msk_regs.hwif_out.tx_data_width.data_width.value[7:0] +msk_top.u_msk_top_csr.u_msk_regs.hwif_out.tx_f1_freqword.config_data.value[31:0] +msk_top.u_msk_top_csr.u_msk_regs.hwif_out.tx_f2_freqword.config_data.value[31:0] +msk_top.u_msk_top_csr.u_msk_regs.hwif_out.tx_sync_cnt.tx_sync_cnt.value[23:0] +@28 +msk_top.u_msk_top_csr.u_msk_regs.hwif_out.tx_sync_ctrl.tx_sync_ena.value +msk_top.u_msk_top_csr.u_msk_regs.hwif_out.tx_sync_ctrl.tx_sync_f1.value +msk_top.u_msk_top_csr.u_msk_regs.hwif_out.tx_sync_ctrl.tx_sync_f2.value +msk_top.u_msk_top_csr.u_msk_regs.hwif_out.tx_sync_ctrl.tx_sync_force.value +@22 +msk_top.u_msk_top_csr.u_msk_regs.readback_data[31:0] +@28 +msk_top.u_msk_top_csr.u_msk_regs.readback_done +msk_top.u_msk_top_csr.u_msk_regs.readback_err +msk_top.u_msk_top_csr.u_msk_regs.rst +msk_top.u_msk_top_csr.u_msk_regs.s_axil_o.arready +msk_top.u_msk_top_csr.u_msk_regs.s_axil_o.awready +msk_top.u_msk_top_csr.u_msk_regs.s_axil_o.bresp[1:0] +msk_top.u_msk_top_csr.u_msk_regs.s_axil_o.bvalid +@22 +msk_top.u_msk_top_csr.u_msk_regs.s_axil_o.rdata[31:0] +@28 +msk_top.u_msk_top_csr.u_msk_regs.s_axil_o.rresp[1:0] +msk_top.u_msk_top_csr.u_msk_regs.s_axil_o.rvalid +msk_top.u_msk_top_csr.u_msk_regs.s_axil_o.wready +@22 +msk_top.u_msk_top_csr.xfer_count[31:0] [pattern_trace] 1 [pattern_trace] 0 diff --git a/sim/msk_top_regs b/sim/msk_top_regs new file mode 120000 index 0000000..43bc91d --- /dev/null +++ b/sim/msk_top_regs @@ -0,0 +1 @@ +../rdl/outputs/python/msk_top_regs \ No newline at end of file diff --git a/src/cdc_resync.vhd b/src/cdc_resync.vhd new file mode 100644 index 0000000..027ac44 --- /dev/null +++ b/src/cdc_resync.vhd @@ -0,0 +1,103 @@ +------------------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------------------ +-- _______ ________ ______ +-- __ __ \________ _____ _______ ___ __ \_____ _____________ ______ ___________________ /_ +-- _ / / /___ __ \_ _ \__ __ \ __ /_/ /_ _ \__ ___/_ _ \_ __ `/__ ___/_ ___/__ __ \ +-- / /_/ / __ /_/ // __/_ / / / _ _, _/ / __/_(__ ) / __// /_/ / _ / / /__ _ / / / +-- \____/ _ .___/ \___/ /_/ /_/ /_/ |_| \___/ /____/ \___/ \__,_/ /_/ \___/ /_/ /_/ +-- /_/ +-- ________ _____ _____ _____ _____ +-- ____ _/_______ __________ /____(_)__ /_____ ____ /______ +-- __ / __ __ \__ ___/_ __/__ / _ __/_ / / /_ __/_ _ \ +-- __/ / _ / / /_(__ ) / /_ _ / / /_ / /_/ / / /_ / __/ +-- /___/ /_/ /_/ /____/ \__/ /_/ \__/ \__,_/ \__/ \___/ +-- +------------------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------------------ +-- Copyright +------------------------------------------------------------------------------------------------------ +-- +-- Copyright 2025 by M. Wishek +-- +------------------------------------------------------------------------------------------------------ +-- License +------------------------------------------------------------------------------------------------------ +-- +-- This source describes Open Hardware and is licensed under the CERN-OHL-W v2. +-- +-- You may redistribute and modify this source and make products using it under +-- the terms of the CERN-OHL-W v2 (https://ohwr.org/cern_ohl_w_v2.txt). +-- +-- This source is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING +-- OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR A PARTICULAR PURPOSE. +-- Please see the CERN-OHL-W v2 for applicable conditions. +-- +-- Source location: TBD +-- +-- As per CERN-OHL-W v2 section 4.1, should You produce hardware based on this +-- source, You must maintain the Source Location visible on the external case of +-- the products you make using this source. +-- +------------------------------------------------------------------------------------------------------ +-- Block name and description +------------------------------------------------------------------------------------------------------ +-- +-- This is a wrapper block for the register module generated by DesyRDL. +-- +-- Documentation location: TBD +-- +------------------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------------------ + + +------------------------------------------------------------------------------------------------------ +-- ╦ ┬┌┐ ┬─┐┌─┐┬─┐┬┌─┐┌─┐ +-- ║ │├┴┐├┬┘├─┤├┬┘│├┤ └─┐ +-- ╩═╝┴└─┘┴└─┴ ┴┴└─┴└─┘└─┘ +------------------------------------------------------------------------------------------------------ +-- Libraries + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +------------------------------------------------------------------------------------------------------ +-- ╔═╗┌┐┌┌┬┐┬┌┬┐┬ ┬ +-- ║╣ │││ │ │ │ └┬┘ +-- ╚═╝┘└┘ ┴ ┴ ┴ ┴ +------------------------------------------------------------------------------------------------------ +-- Entity + +ENTITY cdc_resync IS + GENERIC ( + STAGES : NATURAL := 2 + ); + PORT ( + clk : IN std_logic; + resetn : IN std_logic; + + di : IN std_logic; + do : OUT std_logic + ); +END ENTITY cdc_resync; + +ARCHITECTURE rtl OF cdc_resync IS + + SIGNAL di_s : std_logic_vector(0 TO STAGES-1); + +BEGIN + + do <= di_s(STAGES -1); + + resync : PROCESS (clk, resetn) + BEGIN + IF resetn = '0' THEN + di_s <= (OTHERS => '0'); + ELSIF clk'EVENT AND clk = '1' THEN + di_s <= di & di_s(0 TO STAGES-2); + END IF; + END PROCESS resync; + +END ARCHITECTURE rtl; + + diff --git a/src/msk_top.vhd b/src/msk_top.vhd index 41a4f65..1e5d3e7 100644 --- a/src/msk_top.vhd +++ b/src/msk_top.vhd @@ -64,8 +64,6 @@ LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; -USE work.pkg_msk_top_regs.ALL; - ENTITY msk_top IS GENERIC ( HASH_ID_LO : std_logic_vector := X"AAAA5555"; diff --git a/src/msk_top_csr.vhd b/src/msk_top_csr.vhd index b19e22e..b8b1780 100644 --- a/src/msk_top_csr.vhd +++ b/src/msk_top_csr.vhd @@ -61,7 +61,8 @@ LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; -USE work.pkg_msk_top_regs.ALL; +USE work.axi4lite_intf_pkg.ALL; +USE work.msk_top_regs_pkg.ALL; ------------------------------------------------------------------------------------------------------ -- ╔═╗┌┐┌┌┬┐┬┌┬┐┬ ┬ @@ -171,120 +172,132 @@ END ENTITY msk_top_csr; ARCHITECTURE rtl OF msk_top_csr IS - SIGNAL pi_s_top : t_msk_top_regs_m2s; - SIGNAL po_s_top : t_msk_top_regs_s2m; + SIGNAL s_axil_i : axi4lite_slave_in_intf( + AWADDR(7 downto 0), + WDATA(31 downto 0), + WSTRB(3 downto 0), + ARADDR(7 downto 0) + ); + SIGNAL s_axil_o : axi4lite_slave_out_intf( + RDATA(31 downto 0) + ); - SIGNAL pi_addrmap : t_addrmap_msk_top_regs_in; - SIGNAL po_addrmap : t_addrmap_msk_top_regs_out; + SIGNAL hwif_in : msk_top_regs_in_t; + SIGNAL hwif_out : msk_top_regs_out_t; SIGNAL txrxinit : std_logic; + COMPONENT cdc_resync IS + GENERIC ( + STAGES : NATURAL := 2 + ); + PORT ( + clk : IN std_logic; + resetn : IN std_logic; + + di : IN std_logic; + do : OUT std_logic + ); + END COMPONENT cdc_resync; + BEGIN - u_msk_regs : ENTITY work.msk_top_regs(arch) + s_axil_i.AWVALID <= s_axi_awvalid; + s_axil_i.AWADDR <= s_axi_awaddr(7 DOWNTO 0); + s_axil_i.AWPROT <= s_axi_awprot; + s_axil_i.WVALID <= s_axi_wvalid; + s_axil_i.WDATA <= s_axi_wdata; + s_axil_i.WSTRB <= s_axi_wstrb; + s_axil_i.BREADY <= s_axi_bready; + s_axil_i.ARVALID <= s_axi_arvalid; + s_axil_i.ARADDR <= s_axi_araddr(7 DOWNTO 0); + s_axil_i.ARPROT <= s_axi_arprot; + s_axil_i.RREADY <= s_axi_rready; + + s_axi_awready <= s_axil_o.AWREADY; + s_axi_wready <= s_axil_o.WREADY; + s_axi_bvalid <= s_axil_o.BVALID; + s_axi_bresp <= s_axil_o.BRESP; + s_axi_arready <= s_axil_o.ARREADY; + s_axi_rvalid <= s_axil_o.RVALID; + s_axi_rdata <= s_axil_o.RDATA; + s_axi_rresp <= s_axil_o.RRESP; + + u_msk_regs : ENTITY work.msk_top_regs(rtl) PORT MAP ( - pi_clock => s_axi_aclk, - pi_reset => NOT s_axi_aresetn, - -- TOP subordinate memory mapped interface - pi_s_reset => NOT s_axi_aresetn, - pi_s_top => pi_s_top, - po_s_top => po_s_top, + clk => s_axi_aclk, + rst => NOT s_axi_aresetn, + s_axil_i => s_axil_i, + s_axil_o => s_axil_o, -- to logic interface - pi_addrmap => pi_addrmap, - po_addrmap => po_addrmap + hwif_in => hwif_in, + hwif_out => hwif_out ); - -- write address channel signals--------------------------------------------- - pi_s_top.awaddr <= s_axi_awaddr; - pi_s_top.awprot <= s_axi_awprot; - pi_s_top.awvalid <= s_axi_awvalid; - -- write data channel signals--------------------------------------------- - pi_s_top.wdata <= s_axi_wdata; - pi_s_top.wstrb <= s_axi_wstrb; - pi_s_top.wvalid <= s_axi_wvalid; - -- write response channel signals - pi_s_top.bready <= s_axi_bready; - -- read address channel signals --------------------------------------------- - pi_s_top.araddr <= s_axi_araddr; - pi_s_top.arprot <= s_axi_arprot; - pi_s_top.arvalid <= s_axi_arvalid; - -- read data channel signals--------------------------------------------- - pi_s_top.rready <= s_axi_rready; - - -- write address channel signals--------------------------------------------- - s_axi_awready <= po_s_top.awready; - -- write data channel signals--------------------------------------------- - s_axi_wready <= po_s_top.wready; - -- write response channel signals --------------------------------------------- - s_axi_bresp <= po_s_top.bresp; - s_axi_bvalid <= po_s_top.bvalid; - -- read address channel signals--------------------------------------------- - s_axi_arready <= po_s_top.arready; - -- read data channel signals--------------------------------------------- - s_axi_rdata <= po_s_top.rdata; - s_axi_rresp <= po_s_top.rresp; - s_axi_rvalid <= po_s_top.rvalid; + -- Status signals crossing from local clock domain to the AXI clock domain + hwif_in.MSK_Status.demod_sync_lock.next_q <= '0'; + hwif_in.MSK_Status.tx_enable.next_q <= tx_enable; + hwif_in.MSK_Status.rx_enable.next_q <= rx_enable; + hwif_in.MSK_Status.tx_axis_valid.next_q <= tx_axis_valid; + hwif_in.Tx_Bit_Count.tx_bit_counter.next_q <= tx_bit_counter; + hwif_in.Tx_Enable_Count.tx_ena_counter.next_q <= tx_ena_counter; + hwif_in.axis_xfer_count.xfer_count.next_q <= xfer_count; + hwif_in.PRBS_Bit_Count.status_data.next_q <= prbs_bits; + hwif_in.PRBS_Error_Count.status_data.next_q <= prbs_errs; + hwif_in.LPF_Accum_F1.status_data.next_q <= lpf_accum_f1; + hwif_in.LPF_Accum_F2.status_data.next_q <= lpf_accum_f2; + hwif_in.f1_nco_adjust.data.next_q <= f1_nco_adjust; + hwif_in.f2_nco_adjust.data.next_q <= f2_nco_adjust; + hwif_in.f1_error.data.next_q <= f1_error; + hwif_in.f2_error.data.next_q <= f2_error; + hwif_in.rx_power.rx_power.next_q <= pd_power; - pi_addrmap.MSK_Status.demod_sync_lock.data(0) <= '0'; - pi_addrmap.MSK_Status.tx_enable.data(0) <= tx_enable; - pi_addrmap.MSK_Status.rx_enable.data(0) <= rx_enable; - pi_addrmap.MSK_Status.tx_axis_valid.data(0) <= tx_axis_valid; - pi_addrmap.Tx_Bit_Count.tx_bit_counter.data <= tx_bit_counter; - pi_addrmap.Tx_Enable_Count.tx_ena_counter.data <= tx_ena_counter; - pi_addrmap.axis_xfer_count.xfer_count.data <= xfer_count; - pi_addrmap.PRBS_Bit_Count.status_data.data <= prbs_bits; - pi_addrmap.PRBS_Error_Count.status_data.data <= prbs_errs; - pi_addrmap.LPF_Accum_F1.status_data.data <= lpf_accum_f1; - pi_addrmap.LPF_Accum_F2.status_data.data <= lpf_accum_f2; - pi_addrmap.f1_nco_adjust.data.data <= f1_nco_adjust; - pi_addrmap.f2_nco_adjust.data.data <= f2_nco_adjust; - pi_addrmap.f1_error.data.data <= f1_error; - pi_addrmap.f2_error.data.data <= f2_error; - pi_addrmap.rx_power.rx_power.data <= pd_power; + -- Control signals requiring re-sync from AXI clock domain to local clock domain + u01s: cdc_resync PORT MAP (clk, '1', hwif_out.MSK_Init.txrxinit.value, txrxinit ); + u02s: cdc_resync PORT MAP (clk, '1', hwif_out.MSK_Init.txinit.value OR txrxinit, txinit ); + u03s: cdc_resync PORT MAP (clk, '1', hwif_out.MSK_Init.rxinit.value OR txrxinit, rxinit ); + u04s: cdc_resync PORT MAP (clk, '1', hwif_out.MSK_Control.ptt.value, ptt ); + u05s: cdc_resync PORT MAP (clk, '1', hwif_out.MSK_Control.loopback_ena.value, loopback_ena ); + u06s: cdc_resync PORT MAP (clk, '1', hwif_out.MSK_Control.diff_encoder_loopback.value, diff_encdec_lbk_ena ); + u07s: cdc_resync PORT MAP (clk, '1', hwif_out.MSK_Control.rx_invert.value, rx_invert ); + u08s: cdc_resync PORT MAP (clk, '1', hwif_out.MSK_Control.clear_counts.value, clear_counts ); + u09s: cdc_resync PORT MAP (clk, '1', hwif_out.LPF_Config_0.lpf_freeze.value, lpf_freeze ); + u10s: cdc_resync PORT MAP (clk, '1', hwif_out.LPF_Config_0.lpf_zero.value, lpf_zero ); + u11s: cdc_resync PORT MAP (clk, '1', hwif_out.PRBS_Control.prbs_sel.value, prbs_sel ); + u12s: cdc_resync PORT MAP (clk, '1', hwif_out.PRBS_Control.prbs_clear.value, prbs_clear ); + u13s: cdc_resync PORT MAP (clk, '1', hwif_out.PRBS_Control.prbs_error_insert.value, prbs_err_insert ); + u14s: cdc_resync PORT MAP (clk, '1', hwif_out.PRBS_Control.prbs_manual_sync.value, prbs_manual_sync ); + u15s: cdc_resync PORT MAP (clk, '1', hwif_out.Tx_Sync_Ctrl.tx_sync_ena.value, tx_sync_ena ); + u16s: cdc_resync PORT MAP (clk, '1', hwif_out.Tx_Sync_Ctrl.tx_sync_force.value, tx_sync_force ); + -- The remaining control signals also cross from the AXI to the local clock domain. These are static signals + -- that are configured while the txrxinit is active. The active txrxinit hold the destination FFs to an + -- initial state preventing meta-stable conditions. + freq_word_ft <= hwif_out.Fb_FreqWord.config_data.value; + freq_word_tx_f1 <= hwif_out.TX_F1_FreqWord.config_data.value; + freq_word_tx_f2 <= hwif_out.TX_F2_FreqWord.config_data.value; + freq_word_rx_f1 <= hwif_out.RX_F1_FreqWord.config_data.value; + freq_word_rx_f2 <= hwif_out.RX_F2_FreqWord.config_data.value; + lpf_alpha <= hwif_out.LPF_Config_0.lpf_alpha.value; + lpf_i_gain <= hwif_out.LPF_Config_1.i_gain.value; + lpf_i_shift <= hwif_out.LPF_Config_1.i_shift.value; + lpf_p_gain <= hwif_out.LPF_Config_2.p_gain.value; + lpf_p_shift <= hwif_out.LPF_Config_2.p_shift.value; - txrxinit <= po_addrmap.MSK_Init.txrxinit.data(0); - txinit <= po_addrmap.MSK_Init.txinit.data(0) OR txrxinit; - rxinit <= po_addrmap.MSK_Init.rxinit.data(0) OR txrxinit; - ptt <= po_addrmap.MSK_Control.ptt.data(0); - loopback_ena <= po_addrmap.MSK_Control.loopback_ena.data(0); - diff_encdec_lbk_ena <= po_addrmap.MSK_Control.diff_encoder_loopback.data(0); - rx_invert <= po_addrmap.MSK_Control.rx_invert.data(0); - clear_counts <= po_addrmap.MSK_Control.clear_counts.data(0); - freq_word_ft <= po_addrmap.Fb_FreqWord.config_data.data; - freq_word_tx_f1 <= po_addrmap.TX_F1_FreqWord.config_data.data; - freq_word_tx_f2 <= po_addrmap.TX_F2_FreqWord.config_data.data; - freq_word_rx_f1 <= po_addrmap.RX_F1_FreqWord.config_data.data; - freq_word_rx_f2 <= po_addrmap.RX_F2_FreqWord.config_data.data; - lpf_freeze <= po_addrmap.LPF_Config_0.lpf_freeze.data(0); - lpf_zero <= po_addrmap.LPF_Config_0.lpf_zero.data(0); - lpf_alpha <= po_addrmap.LPF_Config_0.lpf_alpha.data; - lpf_i_gain <= po_addrmap.LPF_Config_1.i_gain.data; - lpf_i_shift <= po_addrmap.LPF_Config_1.i_shift.data; - lpf_p_gain <= po_addrmap.LPF_Config_2.p_gain.data; - lpf_p_shift <= po_addrmap.LPF_Config_2.p_shift.data; - tx_data_w <= po_addrmap.Tx_Data_Width.data_width.data; - rx_data_w <= po_addrmap.Rx_Data_Width.data_width.data; - discard_rxsamples <= po_addrmap.Rx_Sample_Discard.rx_sample_discard.data; - discard_rxnco <= po_addrmap.Rx_Sample_Discard.rx_nco_discard.data; + tx_data_w <= hwif_out.Tx_Data_Width.data_width.value; + rx_data_w <= hwif_out.Rx_Data_Width.data_width.value; + discard_rxsamples <= hwif_out.Rx_Sample_Discard.rx_sample_discard.value; + discard_rxnco <= hwif_out.Rx_Sample_Discard.rx_nco_discard.value; - prbs_initial <= po_addrmap.PRBS_Initial_State.config_data.data; - prbs_poly <= po_addrmap.PRBS_Polynomial.config_data.data; - prbs_err_mask <= po_addrmap.PRBS_Error_Mask.config_data.data; - prbs_err_insert <= po_addrmap.PRBS_Control.prbs_error_insert.data(0); - prbs_sel <= po_addrmap.PRBS_Control.prbs_sel.data(0); - prbs_clear <= po_addrmap.PRBS_Control.prbs_clear.data(0); - prbs_manual_sync <= po_addrmap.PRBS_Control.prbs_manual_sync.data(0); - prbs_sync_threshold <= po_addrmap.PRBS_Control.prbs_sync_threshold.data; + prbs_initial <= hwif_out.PRBS_Initial_State.config_data.value; + prbs_poly <= hwif_out.PRBS_Polynomial.config_data.value; + prbs_err_mask <= hwif_out.PRBS_Error_Mask.config_data.value; + prbs_sync_threshold <= hwif_out.PRBS_Control.prbs_sync_threshold.value; - tx_sync_ena <= po_addrmap.Tx_Sync_Ctrl.tx_sync_ena.data(0); - tx_sync_cnt <= po_addrmap.Tx_Sync_Cnt.tx_sync_cnt.data; - tx_sync_force <= po_addrmap.Tx_Sync_Ctrl.tx_sync_force.data(0); - tx_sync_f1 <= po_addrmap.Tx_Sync_Ctrl.tx_sync_f1.data(0); - tx_sync_f2 <= po_addrmap.Tx_Sync_Ctrl.tx_sync_f2.data(0); + tx_sync_cnt <= hwif_out.Tx_Sync_Cnt.tx_sync_cnt.value; - pd_alpha1 <= po_addrmap.lowpass_ema_alpha1.alpha.data; - pd_alpha2 <= po_addrmap.lowpass_ema_alpha2.alpha.data; + pd_alpha1 <= hwif_out.lowpass_ema_alpha1.alpha.value; + pd_alpha2 <= hwif_out.lowpass_ema_alpha2.alpha.value; END ARCHITECTURE rtl; From 860deaee9faf1b2305287935ccc71e219eb97715 Mon Sep 17 00:00:00 2001 From: Matthew Wishek Date: Sun, 26 Oct 2025 20:46:59 -0600 Subject: [PATCH 02/60] CDC updates for CSRs and PeakRDL transition complete --- rdl/outputs/docs/msk_top_regs.md | 36 ++-- rdl/outputs/docs/msk_top_regs.pdf | Bin 113089 -> 113116 bytes .../msk_top_regs/reg_model/msk_top_regs.py | 66 +++--- rdl/outputs/rtl/msk_top_regs.vhd | 145 +++++++++++-- rdl/outputs/rtl/msk_top_regs_pkg.vhd | 204 ++++++++++-------- rdl/src/msk_top_regs.rdl | 27 +-- sim/Makefile | 2 + sim/msk_test.py | 12 +- src/cdc_resync.vhd | 21 +- src/data_capture.vhd | 102 +++++++++ src/msk_top_csr.vhd | 161 ++++++++++---- src/pulse_detect.vhd | 109 ++++++++++ 12 files changed, 663 insertions(+), 222 deletions(-) create mode 100644 src/data_capture.vhd create mode 100644 src/pulse_detect.vhd diff --git a/rdl/outputs/docs/msk_top_regs.md b/rdl/outputs/docs/msk_top_regs.md index 82c2c8d..db06b21 100644 --- a/rdl/outputs/docs/msk_top_regs.md +++ b/rdl/outputs/docs/msk_top_regs.md @@ -192,9 +192,9 @@ Don't override. Generated from: msk_top_regs

Modem status data

-|Bits| Identifier |Access|Reset| Name | -|----|--------------|------|-----|------------| -|31:0|tx_bit_counter| r | — |Tx Bit Count| +|Bits| Identifier | Access |Reset| Name | +|----|--------------|--------|-----|------------| +|31:0|tx_bit_counter|r, ruser| — |Tx Bit Count| #### tx_bit_counter field @@ -208,9 +208,9 @@ Don't override. Generated from: msk_top_regs

Modem status data

-|Bits| Identifier |Access|Reset| Name | -|----|--------------|------|-----|---------------| -|31:0|tx_ena_counter| r | 0x0 |Tx Enable Count| +|Bits| Identifier | Access |Reset| Name | +|----|--------------|--------|-----|---------------| +|31:0|tx_ena_counter|r, ruser| 0x0 |Tx Enable Count| #### tx_ena_counter field @@ -605,9 +605,9 @@ BER can be calculated as the ratio of received bits to errored-bits

Frequency offet applied to the F1 NCO

-|Bits|Identifier|Access|Reset| Name | -|----|----------|------|-----|-----------------------| -|31:0| data | r | 0x0 |F1 NCO Frequency Adjust| +|Bits|Identifier| Access |Reset| Name | +|----|----------|--------|-----|-----------------------| +|31:0| data |r, ruser| 0x0 |F1 NCO Frequency Adjust| #### data field @@ -621,9 +621,9 @@ BER can be calculated as the ratio of received bits to errored-bits

Frequency offet applied to the F2 NCO

-|Bits|Identifier|Access|Reset| Name | -|----|----------|------|-----|-----------------------| -|31:0| data | r | 0x0 |F2 NCO Frequency Adjust| +|Bits|Identifier| Access |Reset| Name | +|----|----------|--------|-----|-----------------------| +|31:0| data |r, ruser| 0x0 |F2 NCO Frequency Adjust| #### data field @@ -637,9 +637,9 @@ BER can be calculated as the ratio of received bits to errored-bits

Error value of the F1 Costas loop after each active bit period

-|Bits|Identifier|Access|Reset| Name | -|----|----------|------|-----|--------------| -|31:0| data | r | 0x0 |F1 Error Value| +|Bits|Identifier| Access |Reset| Name | +|----|----------|--------|-----|--------------| +|31:0| data |r, ruser| 0x0 |F1 Error Value| #### data field @@ -653,9 +653,9 @@ BER can be calculated as the ratio of received bits to errored-bits

Error value of the F2 Costas loop after each active bit period

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z)qcK8K!)<(iBesWX`$JRrdgq~mLxsR=1A>v`bDWmHQwW2XQ#z|YV@4cT=R599nmMc zn&xYuB2r<-Ruz_S|9LquDu`jL%<9j7DT#l`#&W27oG?XR7&R;Ttr@1^Q{VH`$i6z6s`78%2Yl7Tv zkeGiMV$}+tF~`c&KlH7<2Ot9SI{i=ZOVA+Ez4eD(wU+jmXKYu1ZIQLy|I-W{J?Q-d b(0&0={ajq><>Vl8bYMAp5J=ZVkN&>^W>z%U diff --git a/rdl/outputs/python/msk_top_regs/reg_model/msk_top_regs.py b/rdl/outputs/python/msk_top_regs/reg_model/msk_top_regs.py index 8ea7fa8..8ac24d9 100644 --- a/rdl/outputs/python/msk_top_regs/reg_model/msk_top_regs.py +++ b/rdl/outputs/python/msk_top_regs/reg_model/msk_top_regs.py @@ -414,7 +414,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_lowpass_ema_alpha_alpha_0x0x106a859a_cls(FieldAsyncReadWrite): +class msk_top_regs_lowpass_ema_alpha_alpha_0x0x1065fc05_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -452,7 +452,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_lowpass_ema_alpha_0x0x106a8591_cls(RegAsyncReadWrite): +class msk_top_regs_lowpass_ema_alpha_0x0x1065fc20_cls(RegAsyncReadWrite): """ Class to represent a register in the register model @@ -489,7 +489,7 @@ def __init__(self, # build the field attributes - self.__alpha:msk_top_regs_lowpass_ema_alpha_alpha_0x0x106a859a_cls = msk_top_regs_lowpass_ema_alpha_alpha_0x0x106a859a_cls( + self.__alpha:msk_top_regs_lowpass_ema_alpha_alpha_0x0x1065fc05_cls = msk_top_regs_lowpass_ema_alpha_alpha_0x0x1065fc05_cls( parent_register=self, size_props=FieldSizeProps( width=18, @@ -520,7 +520,7 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field # build the properties for the fields @property - def alpha(self) -> msk_top_regs_lowpass_ema_alpha_alpha_0x0x106a859a_cls: + def alpha(self) -> msk_top_regs_lowpass_ema_alpha_alpha_0x0x1065fc05_cls: """ Property to access alpha field of the register @@ -559,7 +559,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_lowpass_ema_alpha_alpha_0x0x106a859a_cls: + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_lowpass_ema_alpha_alpha_0x0x1065fc05_cls: return super().get_child_by_system_rdl_name(name) @@ -2704,7 +2704,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_stat_32_lpf_acc_status_data_0x0x106b05c7_cls(FieldAsyncReadOnly): +class msk_top_regs_stat_32_lpf_acc_status_data_0x0x10647158_cls(FieldAsyncReadOnly): """ Class to represent a register field in the register model @@ -2779,7 +2779,7 @@ def __init__(self, # build the field attributes - self.__status_data:msk_top_regs_stat_32_lpf_acc_status_data_0x0x106b05c7_cls = msk_top_regs_stat_32_lpf_acc_status_data_0x0x106b05c7_cls( + self.__status_data:msk_top_regs_stat_32_lpf_acc_status_data_0x0x10647158_cls = msk_top_regs_stat_32_lpf_acc_status_data_0x0x10647158_cls( parent_register=self, size_props=FieldSizeProps( width=32, @@ -2810,7 +2810,7 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field # build the properties for the fields @property - def status_data(self) -> msk_top_regs_stat_32_lpf_acc_status_data_0x0x106b05c7_cls: + def status_data(self) -> msk_top_regs_stat_32_lpf_acc_status_data_0x0x10647158_cls: """ Property to access status_data field of the register @@ -2849,7 +2849,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_stat_32_lpf_acc_status_data_0x0x106b05c7_cls: + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_stat_32_lpf_acc_status_data_0x0x10647158_cls: return super().get_child_by_system_rdl_name(name) @@ -4454,7 +4454,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_data_width_data_width_0x0x106a65e2_cls(FieldAsyncReadWrite): +class msk_top_regs_data_width_data_width_0x0x10645fbf_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -4530,7 +4530,7 @@ def __init__(self, # build the field attributes - self.__data_width:msk_top_regs_data_width_data_width_0x0x106a65e2_cls = msk_top_regs_data_width_data_width_0x0x106a65e2_cls( + self.__data_width:msk_top_regs_data_width_data_width_0x0x10645fbf_cls = msk_top_regs_data_width_data_width_0x0x10645fbf_cls( parent_register=self, size_props=FieldSizeProps( width=8, @@ -4561,7 +4561,7 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field # build the properties for the fields @property - def data_width(self) -> msk_top_regs_data_width_data_width_0x0x106a65e2_cls: + def data_width(self) -> msk_top_regs_data_width_data_width_0x0x10645fbf_cls: """ Property to access data_width field of the register @@ -4600,7 +4600,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_data_width_data_width_0x0x106a65e2_cls: + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_data_width_data_width_0x0x10645fbf_cls: return super().get_child_by_system_rdl_name(name) @@ -5446,7 +5446,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_config_nco_fw_config_data_0x0x106a67e3_cls(FieldAsyncReadWrite): +class msk_top_regs_config_nco_fw_config_data_0x0x1065dd1f_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -5523,7 +5523,7 @@ def __init__(self, # build the field attributes - self.__config_data:msk_top_regs_config_nco_fw_config_data_0x0x106a67e3_cls = msk_top_regs_config_nco_fw_config_data_0x0x106a67e3_cls( + self.__config_data:msk_top_regs_config_nco_fw_config_data_0x0x1065dd1f_cls = msk_top_regs_config_nco_fw_config_data_0x0x1065dd1f_cls( parent_register=self, size_props=FieldSizeProps( width=32, @@ -5554,7 +5554,7 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field # build the properties for the fields @property - def config_data(self) -> msk_top_regs_config_nco_fw_config_data_0x0x106a67e3_cls: + def config_data(self) -> msk_top_regs_config_nco_fw_config_data_0x0x1065dd1f_cls: """ Property to access config_data field of the register @@ -5595,7 +5595,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_config_nco_fw_config_data_0x0x106a67e3_cls: + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_config_nco_fw_config_data_0x0x1065dd1f_cls: return super().get_child_by_system_rdl_name(name) @@ -5619,7 +5619,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_config_nco_fw_config_data_0x0x106a672f_cls(FieldAsyncReadWrite): +class msk_top_regs_config_nco_fw_config_data_0x0x1065de03_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -5696,7 +5696,7 @@ def __init__(self, # build the field attributes - self.__config_data:msk_top_regs_config_nco_fw_config_data_0x0x106a672f_cls = msk_top_regs_config_nco_fw_config_data_0x0x106a672f_cls( + self.__config_data:msk_top_regs_config_nco_fw_config_data_0x0x1065de03_cls = msk_top_regs_config_nco_fw_config_data_0x0x1065de03_cls( parent_register=self, size_props=FieldSizeProps( width=32, @@ -5727,7 +5727,7 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field # build the properties for the fields @property - def config_data(self) -> msk_top_regs_config_nco_fw_config_data_0x0x106a672f_cls: + def config_data(self) -> msk_top_regs_config_nco_fw_config_data_0x0x1065de03_cls: """ Property to access config_data field of the register @@ -5768,7 +5768,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_config_nco_fw_config_data_0x0x106a672f_cls: + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_config_nco_fw_config_data_0x0x1065de03_cls: return super().get_child_by_system_rdl_name(name) @@ -5792,7 +5792,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_config_nco_fw_config_data_0x0x1067ecad_cls(FieldAsyncReadWrite): +class msk_top_regs_config_nco_fw_config_data_0x0x1065df17_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -5869,7 +5869,7 @@ def __init__(self, # build the field attributes - self.__config_data:msk_top_regs_config_nco_fw_config_data_0x0x1067ecad_cls = msk_top_regs_config_nco_fw_config_data_0x0x1067ecad_cls( + self.__config_data:msk_top_regs_config_nco_fw_config_data_0x0x1065df17_cls = msk_top_regs_config_nco_fw_config_data_0x0x1065df17_cls( parent_register=self, size_props=FieldSizeProps( width=32, @@ -5900,7 +5900,7 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field # build the properties for the fields @property - def config_data(self) -> msk_top_regs_config_nco_fw_config_data_0x0x1067ecad_cls: + def config_data(self) -> msk_top_regs_config_nco_fw_config_data_0x0x1065df17_cls: """ Property to access config_data field of the register @@ -5941,7 +5941,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_config_nco_fw_config_data_0x0x1067ecad_cls: + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_config_nco_fw_config_data_0x0x1065df17_cls: return super().get_child_by_system_rdl_name(name) @@ -5965,7 +5965,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_config_nco_fw_config_data_0x0x1069f40b_cls(FieldAsyncReadWrite): +class msk_top_regs_config_nco_fw_config_data_0x0x1065e8ef_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -6042,7 +6042,7 @@ def __init__(self, # build the field attributes - self.__config_data:msk_top_regs_config_nco_fw_config_data_0x0x1069f40b_cls = msk_top_regs_config_nco_fw_config_data_0x0x1069f40b_cls( + self.__config_data:msk_top_regs_config_nco_fw_config_data_0x0x1065e8ef_cls = msk_top_regs_config_nco_fw_config_data_0x0x1065e8ef_cls( parent_register=self, size_props=FieldSizeProps( width=32, @@ -6073,7 +6073,7 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field # build the properties for the fields @property - def config_data(self) -> msk_top_regs_config_nco_fw_config_data_0x0x1069f40b_cls: + def config_data(self) -> msk_top_regs_config_nco_fw_config_data_0x0x1065e8ef_cls: """ Property to access config_data field of the register @@ -6114,7 +6114,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_config_nco_fw_config_data_0x0x1069f40b_cls: + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_config_nco_fw_config_data_0x0x1065e8ef_cls: return super().get_child_by_system_rdl_name(name) @@ -8332,7 +8332,7 @@ def __init__(self, *, inst_name='Tx_Sync_Cnt', parent=self) - self.__lowpass_ema_alpha1:msk_top_regs_lowpass_ema_alpha_0x0x106a8591_cls = msk_top_regs_lowpass_ema_alpha_0x0x106a8591_cls( + self.__lowpass_ema_alpha1:msk_top_regs_lowpass_ema_alpha_0x0x1065fc20_cls = msk_top_regs_lowpass_ema_alpha_0x0x1065fc20_cls( address=self.address+132, accesswidth=32, width=32, @@ -9018,7 +9018,7 @@ def Tx_Sync_Cnt(self) -> msk_top_regs_tx_sync_cnt_cls: return self.__Tx_Sync_Cnt @property - def lowpass_ema_alpha1(self) -> msk_top_regs_lowpass_ema_alpha_0x0x106a8591_cls: + def lowpass_ema_alpha1(self) -> msk_top_regs_lowpass_ema_alpha_0x0x1065fc20_cls: """ Property to access lowpass_ema_alpha1 @@ -9232,7 +9232,7 @@ def get_child_by_system_rdl_name(self, name: Literal["Tx_Sync_Cnt"]) -> msk_top_ @overload - def get_child_by_system_rdl_name(self, name: Literal["lowpass_ema_alpha1"]) -> msk_top_regs_lowpass_ema_alpha_0x0x106a8591_cls: ... + def get_child_by_system_rdl_name(self, name: Literal["lowpass_ema_alpha1"]) -> msk_top_regs_lowpass_ema_alpha_0x0x1065fc20_cls: ... @overload @@ -9244,7 +9244,7 @@ def get_child_by_system_rdl_name(self, name: Literal["rx_power"]) -> msk_top_reg @overload - def get_child_by_system_rdl_name(self, name: str) -> Union[msk_top_regs_msk_hash_lo_cls, msk_top_regs_msk_hash_hi_cls, msk_top_regs_msk_init_cls, msk_top_regs_msk_ctrl_cls, msk_top_regs_msk_stat_0_cls, msk_top_regs_msk_stat_1_cls, msk_top_regs_msk_stat_2_cls, msk_top_regs_config_nco_fw_desc_c4924cc6_name_0c494469_cls, msk_top_regs_config_nco_fw_desc_94d7aaf5_name_84dd0c1c_cls, msk_top_regs_config_nco_fw_desc_42134a4f_name_d97dbd51_cls, msk_top_regs_config_nco_fw_desc_16fb48c8_name_8d01a20d_cls, msk_top_regs_config_nco_fw_desc_43c0828f_name_bdc60ecf_cls, msk_top_regs_lpf_config_0_cls, msk_top_regs_lpf_config_1_cls, msk_top_regs_data_width_desc_58c848dd_name_2fbd8eba_cls, msk_top_regs_data_width_desc_6097df38_name_4609588b_cls, msk_top_regs_prbs_ctrl_cls, msk_top_regs_config_prbs_seed_cls, msk_top_regs_config_prbs_poly_cls, msk_top_regs_config_prbs_errmask_cls, msk_top_regs_stat_32_bits_cls, msk_top_regs_stat_32_errs_cls, msk_top_regs_stat_32_lpf_acc_desc_8cebc7dc_name_f20c6670_cls, msk_top_regs_stat_32_lpf_acc_desc_dea6bd99_name_758fd0ce_cls, msk_top_regs_msk_stat_3_cls, msk_top_regs_rx_sample_discard_cls, msk_top_regs_lpf_config_2_cls, msk_top_regs_observation_data_data_0c017ef4_desc_64ff3689_name_d8ad3b25_cls, msk_top_regs_observation_data_data_0515efaa_desc_ebde6d39_name_2c154788_cls, msk_top_regs_observation_data_data_25a21249_desc_417e1c96_name_3b640507_cls, msk_top_regs_observation_data_data_272a00b6_desc_70869502_name_3de9a0d3_cls, msk_top_regs_tx_sync_ctrl_cls, msk_top_regs_tx_sync_cnt_cls, msk_top_regs_lowpass_ema_alpha_0x0x106a8591_cls, msk_top_regs_lowpass_ema_alpha_cls, msk_top_regs_rx_power_cls, ]: ... + def get_child_by_system_rdl_name(self, name: str) -> Union[msk_top_regs_msk_hash_lo_cls, msk_top_regs_msk_hash_hi_cls, msk_top_regs_msk_init_cls, msk_top_regs_msk_ctrl_cls, msk_top_regs_msk_stat_0_cls, msk_top_regs_msk_stat_1_cls, msk_top_regs_msk_stat_2_cls, msk_top_regs_config_nco_fw_desc_c4924cc6_name_0c494469_cls, msk_top_regs_config_nco_fw_desc_94d7aaf5_name_84dd0c1c_cls, msk_top_regs_config_nco_fw_desc_42134a4f_name_d97dbd51_cls, msk_top_regs_config_nco_fw_desc_16fb48c8_name_8d01a20d_cls, msk_top_regs_config_nco_fw_desc_43c0828f_name_bdc60ecf_cls, msk_top_regs_lpf_config_0_cls, msk_top_regs_lpf_config_1_cls, msk_top_regs_data_width_desc_58c848dd_name_2fbd8eba_cls, msk_top_regs_data_width_desc_6097df38_name_4609588b_cls, msk_top_regs_prbs_ctrl_cls, msk_top_regs_config_prbs_seed_cls, msk_top_regs_config_prbs_poly_cls, msk_top_regs_config_prbs_errmask_cls, msk_top_regs_stat_32_bits_cls, msk_top_regs_stat_32_errs_cls, msk_top_regs_stat_32_lpf_acc_desc_8cebc7dc_name_f20c6670_cls, msk_top_regs_stat_32_lpf_acc_desc_dea6bd99_name_758fd0ce_cls, msk_top_regs_msk_stat_3_cls, msk_top_regs_rx_sample_discard_cls, msk_top_regs_lpf_config_2_cls, msk_top_regs_observation_data_data_0c017ef4_desc_64ff3689_name_d8ad3b25_cls, msk_top_regs_observation_data_data_0515efaa_desc_ebde6d39_name_2c154788_cls, msk_top_regs_observation_data_data_25a21249_desc_417e1c96_name_3b640507_cls, msk_top_regs_observation_data_data_272a00b6_desc_70869502_name_3de9a0d3_cls, msk_top_regs_tx_sync_ctrl_cls, msk_top_regs_tx_sync_cnt_cls, msk_top_regs_lowpass_ema_alpha_0x0x1065fc20_cls, msk_top_regs_lowpass_ema_alpha_cls, msk_top_regs_rx_power_cls, ]: ... def get_child_by_system_rdl_name(self, name: Any) -> Any: return super().get_child_by_system_rdl_name(name) diff --git a/rdl/outputs/rtl/msk_top_regs.vhd b/rdl/outputs/rtl/msk_top_regs.vhd index 9606951..25efa10 100644 --- a/rdl/outputs/rtl/msk_top_regs.vhd +++ b/rdl/outputs/rtl/msk_top_regs.vhd @@ -70,6 +70,10 @@ architecture rtl of msk_top_regs is signal axil_resp_buffer : axil_resp_buffer_array_t(1 downto 0); signal axil_resp_wptr : unsigned(1 downto 0); signal axil_resp_rptr : unsigned(1 downto 0); + signal external_req : std_logic; + signal external_pending : std_logic; + signal external_wr_ack : std_logic; + signal external_rd_ack : std_logic; ---------------------------------------------------------------------------- -- Address Decode Signals @@ -113,6 +117,8 @@ architecture rtl of msk_top_regs is rx_power : std_logic; end record; signal decoded_reg_strb : decoded_reg_strb_t; + signal decoded_strb_is_external : std_logic; + signal decoded_req : std_logic; signal decoded_req_is_wr : std_logic; signal decoded_wr_data : std_logic_vector(31 downto 0); @@ -753,6 +759,8 @@ architecture rtl of msk_top_regs is ---------------------------------------------------------------------------- -- Readback Signals ---------------------------------------------------------------------------- + signal readback_external_rd_ack_c : std_logic; + signal readback_external_rd_ack : std_logic; signal readback_err : std_logic; signal readback_done : std_logic; signal readback_data : std_logic_vector(31 downto 0); @@ -950,10 +958,32 @@ begin s_axil_o.RRESP <= "00"; end if; end process; + process(clk) begin + if false then -- async reset + external_pending <= '0'; + elsif rising_edge(clk) then + if rst then -- sync reset + external_pending <= '0'; + else + if external_req and not external_wr_ack and not external_rd_ack then + external_pending <= '1'; + elsif external_wr_ack or external_rd_ack then + external_pending <= '0'; + end if; + --pragma translate_off + assert_bad_ext_wr_ack: assert not external_wr_ack or (external_pending or external_req) + report "An external wr_ack strobe was asserted when no external request was active"; + assert_bad_ext_rd_ack: assert not external_rd_ack or (external_pending or external_req) + report "An external rd_ack strobe was asserted when no external request was active"; + --pragma translate_on + end if; + end if; + end process; -- Read & write latencies are balanced. Stalls not required - cpuif_req_stall_rd <= '0'; - cpuif_req_stall_wr <= '0'; + -- except if external + cpuif_req_stall_rd <= external_pending; + cpuif_req_stall_wr <= external_pending; cpuif_req_masked <= cpuif_req and not (not cpuif_req_is_wr and cpuif_req_stall_rd) and not (cpuif_req_is_wr and cpuif_req_stall_wr); @@ -969,14 +999,18 @@ begin result := '1' when unsigned(L) = R else '0'; return result; end; + variable is_external: std_logic; begin + is_external := '0'; decoded_reg_strb.Hash_ID_Low <= cpuif_req_masked and (cpuif_addr = 16#0#); decoded_reg_strb.Hash_ID_High <= cpuif_req_masked and (cpuif_addr = 16#4#); decoded_reg_strb.MSK_Init <= cpuif_req_masked and (cpuif_addr = 16#8#); decoded_reg_strb.MSK_Control <= cpuif_req_masked and (cpuif_addr = 16#C#); decoded_reg_strb.MSK_Status <= cpuif_req_masked and (cpuif_addr = 16#10#); decoded_reg_strb.Tx_Bit_Count <= cpuif_req_masked and (cpuif_addr = 16#14#); + is_external := is_external or ((cpuif_req_masked and (cpuif_addr = 16#14#)) and not cpuif_req_is_wr); decoded_reg_strb.Tx_Enable_Count <= cpuif_req_masked and (cpuif_addr = 16#18#); + is_external := is_external or ((cpuif_req_masked and (cpuif_addr = 16#18#)) and not cpuif_req_is_wr); decoded_reg_strb.Fb_FreqWord <= cpuif_req_masked and (cpuif_addr = 16#1C#); decoded_reg_strb.TX_F1_FreqWord <= cpuif_req_masked and (cpuif_addr = 16#20#); decoded_reg_strb.TX_F2_FreqWord <= cpuif_req_masked and (cpuif_addr = 16#24#); @@ -991,21 +1025,33 @@ begin decoded_reg_strb.PRBS_Polynomial <= cpuif_req_masked and (cpuif_addr = 16#48#); decoded_reg_strb.PRBS_Error_Mask <= cpuif_req_masked and (cpuif_addr = 16#4C#); decoded_reg_strb.PRBS_Bit_Count <= cpuif_req_masked and (cpuif_addr = 16#50#); + is_external := is_external or ((cpuif_req_masked and (cpuif_addr = 16#50#)) and not cpuif_req_is_wr); decoded_reg_strb.PRBS_Error_Count <= cpuif_req_masked and (cpuif_addr = 16#54#); + is_external := is_external or ((cpuif_req_masked and (cpuif_addr = 16#54#)) and not cpuif_req_is_wr); decoded_reg_strb.LPF_Accum_F1 <= cpuif_req_masked and (cpuif_addr = 16#58#); + is_external := is_external or ((cpuif_req_masked and (cpuif_addr = 16#58#)) and not cpuif_req_is_wr); decoded_reg_strb.LPF_Accum_F2 <= cpuif_req_masked and (cpuif_addr = 16#5C#); + is_external := is_external or ((cpuif_req_masked and (cpuif_addr = 16#5C#)) and not cpuif_req_is_wr); decoded_reg_strb.axis_xfer_count <= cpuif_req_masked and (cpuif_addr = 16#60#); + is_external := is_external or ((cpuif_req_masked and (cpuif_addr = 16#60#)) and not cpuif_req_is_wr); decoded_reg_strb.Rx_Sample_Discard <= cpuif_req_masked and (cpuif_addr = 16#64#); decoded_reg_strb.LPF_Config_2 <= cpuif_req_masked and (cpuif_addr = 16#68#); decoded_reg_strb.f1_nco_adjust <= cpuif_req_masked and (cpuif_addr = 16#6C#); + is_external := is_external or ((cpuif_req_masked and (cpuif_addr = 16#6C#)) and not cpuif_req_is_wr); decoded_reg_strb.f2_nco_adjust <= cpuif_req_masked and (cpuif_addr = 16#70#); + is_external := is_external or ((cpuif_req_masked and (cpuif_addr = 16#70#)) and not cpuif_req_is_wr); decoded_reg_strb.f1_error <= cpuif_req_masked and (cpuif_addr = 16#74#); + is_external := is_external or ((cpuif_req_masked and (cpuif_addr = 16#74#)) and not cpuif_req_is_wr); decoded_reg_strb.f2_error <= cpuif_req_masked and (cpuif_addr = 16#78#); + is_external := is_external or ((cpuif_req_masked and (cpuif_addr = 16#78#)) and not cpuif_req_is_wr); decoded_reg_strb.Tx_Sync_Ctrl <= cpuif_req_masked and (cpuif_addr = 16#7C#); decoded_reg_strb.Tx_Sync_Cnt <= cpuif_req_masked and (cpuif_addr = 16#80#); decoded_reg_strb.lowpass_ema_alpha1 <= cpuif_req_masked and (cpuif_addr = 16#84#); decoded_reg_strb.lowpass_ema_alpha2 <= cpuif_req_masked and (cpuif_addr = 16#88#); decoded_reg_strb.rx_power <= cpuif_req_masked and (cpuif_addr = 16#8C#); + is_external := is_external or ((cpuif_req_masked and (cpuif_addr = 16#8C#)) and not cpuif_req_is_wr); + decoded_strb_is_external <= is_external; + external_req <= is_external; end process; -- Pass down signals to next stage @@ -1255,6 +1301,12 @@ begin end process; hwif_out.MSK_Control.diff_encoder_loopback.value <= field_storage.MSK_Control.diff_encoder_loopback.value; + hwif_out.Tx_Bit_Count.req <= decoded_reg_strb.Tx_Bit_Count when not decoded_req_is_wr else '0'; + hwif_out.Tx_Bit_Count.req_is_wr <= decoded_req_is_wr; + + hwif_out.Tx_Enable_Count.req <= decoded_reg_strb.Tx_Enable_Count when not decoded_req_is_wr else '0'; + hwif_out.Tx_Enable_Count.req_is_wr <= decoded_req_is_wr; + -- Field: msk_top_regs.Fb_FreqWord.config_data process(all) variable next_c: std_logic_vector(31 downto 0); @@ -1902,6 +1954,21 @@ begin end process; hwif_out.PRBS_Error_Mask.config_data.value <= field_storage.PRBS_Error_Mask.config_data.value; + hwif_out.PRBS_Bit_Count.req <= decoded_reg_strb.PRBS_Bit_Count when not decoded_req_is_wr else '0'; + hwif_out.PRBS_Bit_Count.req_is_wr <= decoded_req_is_wr; + + hwif_out.PRBS_Error_Count.req <= decoded_reg_strb.PRBS_Error_Count when not decoded_req_is_wr else '0'; + hwif_out.PRBS_Error_Count.req_is_wr <= decoded_req_is_wr; + + hwif_out.LPF_Accum_F1.req <= decoded_reg_strb.LPF_Accum_F1 when not decoded_req_is_wr else '0'; + hwif_out.LPF_Accum_F1.req_is_wr <= decoded_req_is_wr; + + hwif_out.LPF_Accum_F2.req <= decoded_reg_strb.LPF_Accum_F2 when not decoded_req_is_wr else '0'; + hwif_out.LPF_Accum_F2.req_is_wr <= decoded_req_is_wr; + + hwif_out.axis_xfer_count.req <= decoded_reg_strb.axis_xfer_count when not decoded_req_is_wr else '0'; + hwif_out.axis_xfer_count.req_is_wr <= decoded_req_is_wr; + -- Field: msk_top_regs.Rx_Sample_Discard.rx_sample_discard process(all) variable next_c: std_logic_vector(7 downto 0); @@ -2018,6 +2085,18 @@ begin end process; hwif_out.LPF_Config_2.p_shift.value <= field_storage.LPF_Config_2.p_shift.value; + hwif_out.f1_nco_adjust.req <= decoded_reg_strb.f1_nco_adjust when not decoded_req_is_wr else '0'; + hwif_out.f1_nco_adjust.req_is_wr <= decoded_req_is_wr; + + hwif_out.f2_nco_adjust.req <= decoded_reg_strb.f2_nco_adjust when not decoded_req_is_wr else '0'; + hwif_out.f2_nco_adjust.req_is_wr <= decoded_req_is_wr; + + hwif_out.f1_error.req <= decoded_reg_strb.f1_error when not decoded_req_is_wr else '0'; + hwif_out.f1_error.req_is_wr <= decoded_req_is_wr; + + hwif_out.f2_error.req <= decoded_reg_strb.f2_error when not decoded_req_is_wr else '0'; + hwif_out.f2_error.req_is_wr <= decoded_req_is_wr; + -- Field: msk_top_regs.Tx_Sync_Ctrl.tx_sync_ena process(all) variable next_c: std_logic; @@ -2221,16 +2300,46 @@ begin end process; hwif_out.lowpass_ema_alpha2.alpha.value <= field_storage.lowpass_ema_alpha2.alpha.value; + hwif_out.rx_power.req <= decoded_reg_strb.rx_power when not decoded_req_is_wr else '0'; + hwif_out.rx_power.req_is_wr <= decoded_req_is_wr; + ---------------------------------------------------------------------------- -- Write response ---------------------------------------------------------------------------- - cpuif_wr_ack <= decoded_req and decoded_req_is_wr; + process(all) + variable wr_ack: std_logic; + begin + wr_ack := '0'; + + external_wr_ack <= wr_ack; + end process; + cpuif_wr_ack <= external_wr_ack or (decoded_req and decoded_req_is_wr and not decoded_strb_is_external); -- Writes are always granted with no error response cpuif_wr_err <= '0'; ---------------------------------------------------------------------------- -- Readback ---------------------------------------------------------------------------- + process(all) + variable rd_ack: std_logic; + begin + rd_ack := '0'; + rd_ack := rd_ack or hwif_in.Tx_Bit_Count.rd_ack; + rd_ack := rd_ack or hwif_in.Tx_Enable_Count.rd_ack; + rd_ack := rd_ack or hwif_in.PRBS_Bit_Count.rd_ack; + rd_ack := rd_ack or hwif_in.PRBS_Error_Count.rd_ack; + rd_ack := rd_ack or hwif_in.LPF_Accum_F1.rd_ack; + rd_ack := rd_ack or hwif_in.LPF_Accum_F2.rd_ack; + rd_ack := rd_ack or hwif_in.axis_xfer_count.rd_ack; + rd_ack := rd_ack or hwif_in.f1_nco_adjust.rd_ack; + rd_ack := rd_ack or hwif_in.f2_nco_adjust.rd_ack; + rd_ack := rd_ack or hwif_in.f1_error.rd_ack; + rd_ack := rd_ack or hwif_in.f2_error.rd_ack; + rd_ack := rd_ack or hwif_in.rx_power.rd_ack; + readback_external_rd_ack_c <= rd_ack; + end process; + + readback_external_rd_ack <= readback_external_rd_ack_c; -- Assign readback values to a flattened array readback_array(0)(31 downto 0) <= 32x"AAAA5555" when (decoded_reg_strb.Hash_ID_Low and not decoded_req_is_wr) else (others => '0'); @@ -2250,8 +2359,8 @@ begin readback_array(4)(2 downto 2) <= to_std_logic_vector(hwif_in.MSK_Status.rx_enable.next_q) when (decoded_reg_strb.MSK_Status and not decoded_req_is_wr) else (others => '0'); readback_array(4)(3 downto 3) <= to_std_logic_vector(hwif_in.MSK_Status.tx_axis_valid.next_q) when (decoded_reg_strb.MSK_Status and not decoded_req_is_wr) else (others => '0'); readback_array(4)(31 downto 4) <= (others => '0'); - readback_array(5)(31 downto 0) <= hwif_in.Tx_Bit_Count.tx_bit_counter.next_q when (decoded_reg_strb.Tx_Bit_Count and not decoded_req_is_wr) else (others => '0'); - readback_array(6)(31 downto 0) <= hwif_in.Tx_Enable_Count.tx_ena_counter.next_q when (decoded_reg_strb.Tx_Enable_Count and not decoded_req_is_wr) else (others => '0'); + readback_array(5) <= hwif_in.Tx_Bit_Count.rd_data when hwif_in.Tx_Bit_Count.rd_ack else (others => '0'); + readback_array(6) <= hwif_in.Tx_Enable_Count.rd_data when hwif_in.Tx_Enable_Count.rd_ack else (others => '0'); readback_array(7)(31 downto 0) <= field_storage.Fb_FreqWord.config_data.value when (decoded_reg_strb.Fb_FreqWord and not decoded_req_is_wr) else (others => '0'); readback_array(8)(31 downto 0) <= field_storage.TX_F1_FreqWord.config_data.value when (decoded_reg_strb.TX_F1_FreqWord and not decoded_req_is_wr) else (others => '0'); readback_array(9)(31 downto 0) <= field_storage.TX_F2_FreqWord.config_data.value when (decoded_reg_strb.TX_F2_FreqWord and not decoded_req_is_wr) else (others => '0'); @@ -2274,20 +2383,20 @@ begin readback_array(17)(31 downto 0) <= field_storage.PRBS_Initial_State.config_data.value when (decoded_reg_strb.PRBS_Initial_State and not decoded_req_is_wr) else (others => '0'); readback_array(18)(31 downto 0) <= field_storage.PRBS_Polynomial.config_data.value when (decoded_reg_strb.PRBS_Polynomial and not decoded_req_is_wr) else (others => '0'); readback_array(19)(31 downto 0) <= field_storage.PRBS_Error_Mask.config_data.value when (decoded_reg_strb.PRBS_Error_Mask and not decoded_req_is_wr) else (others => '0'); - readback_array(20)(31 downto 0) <= hwif_in.PRBS_Bit_Count.status_data.next_q when (decoded_reg_strb.PRBS_Bit_Count and not decoded_req_is_wr) else (others => '0'); - readback_array(21)(31 downto 0) <= hwif_in.PRBS_Error_Count.status_data.next_q when (decoded_reg_strb.PRBS_Error_Count and not decoded_req_is_wr) else (others => '0'); - readback_array(22)(31 downto 0) <= hwif_in.LPF_Accum_F1.status_data.next_q when (decoded_reg_strb.LPF_Accum_F1 and not decoded_req_is_wr) else (others => '0'); - readback_array(23)(31 downto 0) <= hwif_in.LPF_Accum_F2.status_data.next_q when (decoded_reg_strb.LPF_Accum_F2 and not decoded_req_is_wr) else (others => '0'); - readback_array(24)(31 downto 0) <= hwif_in.axis_xfer_count.xfer_count.next_q when (decoded_reg_strb.axis_xfer_count and not decoded_req_is_wr) else (others => '0'); + readback_array(20) <= hwif_in.PRBS_Bit_Count.rd_data when hwif_in.PRBS_Bit_Count.rd_ack else (others => '0'); + readback_array(21) <= hwif_in.PRBS_Error_Count.rd_data when hwif_in.PRBS_Error_Count.rd_ack else (others => '0'); + readback_array(22) <= hwif_in.LPF_Accum_F1.rd_data when hwif_in.LPF_Accum_F1.rd_ack else (others => '0'); + readback_array(23) <= hwif_in.LPF_Accum_F2.rd_data when hwif_in.LPF_Accum_F2.rd_ack else (others => '0'); + readback_array(24) <= hwif_in.axis_xfer_count.rd_data when hwif_in.axis_xfer_count.rd_ack else (others => '0'); readback_array(25)(7 downto 0) <= field_storage.Rx_Sample_Discard.rx_sample_discard.value when (decoded_reg_strb.Rx_Sample_Discard and not decoded_req_is_wr) else (others => '0'); readback_array(25)(15 downto 8) <= field_storage.Rx_Sample_Discard.rx_nco_discard.value when (decoded_reg_strb.Rx_Sample_Discard and not decoded_req_is_wr) else (others => '0'); readback_array(25)(31 downto 16) <= (others => '0'); readback_array(26)(23 downto 0) <= field_storage.LPF_Config_2.p_gain.value when (decoded_reg_strb.LPF_Config_2 and not decoded_req_is_wr) else (others => '0'); readback_array(26)(31 downto 24) <= field_storage.LPF_Config_2.p_shift.value when (decoded_reg_strb.LPF_Config_2 and not decoded_req_is_wr) else (others => '0'); - readback_array(27)(31 downto 0) <= hwif_in.f1_nco_adjust.data.next_q when (decoded_reg_strb.f1_nco_adjust and not decoded_req_is_wr) else (others => '0'); - readback_array(28)(31 downto 0) <= hwif_in.f2_nco_adjust.data.next_q when (decoded_reg_strb.f2_nco_adjust and not decoded_req_is_wr) else (others => '0'); - readback_array(29)(31 downto 0) <= hwif_in.f1_error.data.next_q when (decoded_reg_strb.f1_error and not decoded_req_is_wr) else (others => '0'); - readback_array(30)(31 downto 0) <= hwif_in.f2_error.data.next_q when (decoded_reg_strb.f2_error and not decoded_req_is_wr) else (others => '0'); + readback_array(27) <= hwif_in.f1_nco_adjust.rd_data when hwif_in.f1_nco_adjust.rd_ack else (others => '0'); + readback_array(28) <= hwif_in.f2_nco_adjust.rd_data when hwif_in.f2_nco_adjust.rd_ack else (others => '0'); + readback_array(29) <= hwif_in.f1_error.rd_data when hwif_in.f1_error.rd_ack else (others => '0'); + readback_array(30) <= hwif_in.f2_error.rd_data when hwif_in.f2_error.rd_ack else (others => '0'); readback_array(31)(0 downto 0) <= to_std_logic_vector(field_storage.Tx_Sync_Ctrl.tx_sync_ena.value) when (decoded_reg_strb.Tx_Sync_Ctrl and not decoded_req_is_wr) else (others => '0'); readback_array(31)(1 downto 1) <= to_std_logic_vector(field_storage.Tx_Sync_Ctrl.tx_sync_force.value) when (decoded_reg_strb.Tx_Sync_Ctrl and not decoded_req_is_wr) else (others => '0'); readback_array(31)(2 downto 2) <= to_std_logic_vector(field_storage.Tx_Sync_Ctrl.tx_sync_f1.value) when (decoded_reg_strb.Tx_Sync_Ctrl and not decoded_req_is_wr) else (others => '0'); @@ -2299,14 +2408,13 @@ begin readback_array(33)(31 downto 18) <= (others => '0'); readback_array(34)(17 downto 0) <= field_storage.lowpass_ema_alpha2.alpha.value when (decoded_reg_strb.lowpass_ema_alpha2 and not decoded_req_is_wr) else (others => '0'); readback_array(34)(31 downto 18) <= (others => '0'); - readback_array(35)(22 downto 0) <= hwif_in.rx_power.rx_power.next_q when (decoded_reg_strb.rx_power and not decoded_req_is_wr) else (others => '0'); - readback_array(35)(31 downto 23) <= (others => '0'); + readback_array(35) <= hwif_in.rx_power.rd_data when hwif_in.rx_power.rd_ack else (others => '0'); -- Reduce the array process(all) variable readback_data_var : std_logic_vector(31 downto 0) := (others => '0'); begin - readback_done <= decoded_req and not decoded_req_is_wr; + readback_done <= decoded_req and not decoded_req_is_wr and not decoded_strb_is_external; readback_err <= '0'; readback_data_var := (others => '0'); for i in readback_array'RANGE loop @@ -2315,7 +2423,8 @@ begin readback_data <= readback_data_var; end process; - cpuif_rd_ack <= readback_done; + external_rd_ack <= readback_external_rd_ack; + cpuif_rd_ack <= readback_done or readback_external_rd_ack; cpuif_rd_data <= readback_data; cpuif_rd_err <= readback_err; end architecture rtl; diff --git a/rdl/outputs/rtl/msk_top_regs_pkg.vhd b/rdl/outputs/rtl/msk_top_regs_pkg.vhd index a362018..c00bed8 100644 --- a/rdl/outputs/rtl/msk_top_regs_pkg.vhd +++ b/rdl/outputs/rtl/msk_top_regs_pkg.vhd @@ -34,116 +34,80 @@ package msk_top_regs_pkg is tx_axis_valid : \msk_top_regs.msk_stat_0.tx_axis_valid_in_t\; end record; - type \msk_top_regs.msk_stat_1.tx_bit_counter_in_t\ is record - next_q : std_logic_vector(31 downto 0); + type \msk_top_regs.msk_stat_1__external_in_t\ is record + rd_ack : std_logic; + rd_data : std_logic_vector(31 downto 0); end record; - type \msk_top_regs.msk_stat_1_in_t\ is record - tx_bit_counter : \msk_top_regs.msk_stat_1.tx_bit_counter_in_t\; + type \msk_top_regs.msk_stat_2__external_in_t\ is record + rd_ack : std_logic; + rd_data : std_logic_vector(31 downto 0); end record; - type \msk_top_regs.msk_stat_2.tx_ena_counter_in_t\ is record - next_q : std_logic_vector(31 downto 0); + type \msk_top_regs.stat_32_bits__external_in_t\ is record + rd_ack : std_logic; + rd_data : std_logic_vector(31 downto 0); end record; - type \msk_top_regs.msk_stat_2_in_t\ is record - tx_ena_counter : \msk_top_regs.msk_stat_2.tx_ena_counter_in_t\; + type \msk_top_regs.stat_32_errs__external_in_t\ is record + rd_ack : std_logic; + rd_data : std_logic_vector(31 downto 0); end record; - type \msk_top_regs.stat_32_bits.status_data_in_t\ is record - next_q : std_logic_vector(31 downto 0); + type \msk_top_regs.stat_32_lpf_acc_desc_8cebc7dc_name_f20c6670__external_in_t\ is record + rd_ack : std_logic; + rd_data : std_logic_vector(31 downto 0); end record; - type \msk_top_regs.stat_32_bits_in_t\ is record - status_data : \msk_top_regs.stat_32_bits.status_data_in_t\; + type \msk_top_regs.stat_32_lpf_acc_desc_dea6bd99_name_758fd0ce__external_in_t\ is record + rd_ack : std_logic; + rd_data : std_logic_vector(31 downto 0); end record; - type \msk_top_regs.stat_32_errs.status_data_in_t\ is record - next_q : std_logic_vector(31 downto 0); + type \msk_top_regs.msk_stat_3__external_in_t\ is record + rd_ack : std_logic; + rd_data : std_logic_vector(31 downto 0); end record; - type \msk_top_regs.stat_32_errs_in_t\ is record - status_data : \msk_top_regs.stat_32_errs.status_data_in_t\; + type \msk_top_regs.observation_data_data_0c017ef4_desc_64ff3689_name_d8ad3b25__external_in_t\ is record + rd_ack : std_logic; + rd_data : std_logic_vector(31 downto 0); end record; - type \msk_top_regs.stat_32_lpf_acc_desc_8cebc7dc_name_f20c6670.status_data_in_t\ is record - next_q : std_logic_vector(31 downto 0); + type \msk_top_regs.observation_data_data_0515efaa_desc_ebde6d39_name_2c154788__external_in_t\ is record + rd_ack : std_logic; + rd_data : std_logic_vector(31 downto 0); end record; - type \msk_top_regs.stat_32_lpf_acc_desc_8cebc7dc_name_f20c6670_in_t\ is record - status_data : \msk_top_regs.stat_32_lpf_acc_desc_8cebc7dc_name_f20c6670.status_data_in_t\; + type \msk_top_regs.observation_data_data_25a21249_desc_417e1c96_name_3b640507__external_in_t\ is record + rd_ack : std_logic; + rd_data : std_logic_vector(31 downto 0); end record; - type \msk_top_regs.stat_32_lpf_acc_desc_dea6bd99_name_758fd0ce.status_data_in_t\ is record - next_q : std_logic_vector(31 downto 0); + type \msk_top_regs.observation_data_data_272a00b6_desc_70869502_name_3de9a0d3__external_in_t\ is record + rd_ack : std_logic; + rd_data : std_logic_vector(31 downto 0); end record; - type \msk_top_regs.stat_32_lpf_acc_desc_dea6bd99_name_758fd0ce_in_t\ is record - status_data : \msk_top_regs.stat_32_lpf_acc_desc_dea6bd99_name_758fd0ce.status_data_in_t\; - end record; - - type \msk_top_regs.msk_stat_3.xfer_count_in_t\ is record - next_q : std_logic_vector(31 downto 0); - end record; - - type \msk_top_regs.msk_stat_3_in_t\ is record - xfer_count : \msk_top_regs.msk_stat_3.xfer_count_in_t\; - end record; - - type \msk_top_regs.data32_desc_64ff3689_name_d8ad3b25_in_t\ is record - next_q : std_logic_vector(31 downto 0); - end record; - - type \msk_top_regs.observation_data_data_0c017ef4_desc_64ff3689_name_d8ad3b25_in_t\ is record - data : \msk_top_regs.data32_desc_64ff3689_name_d8ad3b25_in_t\; - end record; - - type \msk_top_regs.data32_desc_ebde6d39_name_2c154788_in_t\ is record - next_q : std_logic_vector(31 downto 0); - end record; - - type \msk_top_regs.observation_data_data_0515efaa_desc_ebde6d39_name_2c154788_in_t\ is record - data : \msk_top_regs.data32_desc_ebde6d39_name_2c154788_in_t\; - end record; - - type \msk_top_regs.data32_desc_417e1c96_name_3b640507_in_t\ is record - next_q : std_logic_vector(31 downto 0); - end record; - - type \msk_top_regs.observation_data_data_25a21249_desc_417e1c96_name_3b640507_in_t\ is record - data : \msk_top_regs.data32_desc_417e1c96_name_3b640507_in_t\; - end record; - - type \msk_top_regs.data32_desc_70869502_name_3de9a0d3_in_t\ is record - next_q : std_logic_vector(31 downto 0); - end record; - - type \msk_top_regs.observation_data_data_272a00b6_desc_70869502_name_3de9a0d3_in_t\ is record - data : \msk_top_regs.data32_desc_70869502_name_3de9a0d3_in_t\; - end record; - - type \msk_top_regs.rx_power.rx_power_in_t\ is record - next_q : std_logic_vector(22 downto 0); - end record; - - type \msk_top_regs.rx_power_in_t\ is record - rx_power : \msk_top_regs.rx_power.rx_power_in_t\; + type \msk_top_regs.rx_power__external_in_t\ is record + rd_ack : std_logic; + rd_data : std_logic_vector(31 downto 0); end record; type msk_top_regs_in_t is record MSK_Status : \msk_top_regs.msk_stat_0_in_t\; - Tx_Bit_Count : \msk_top_regs.msk_stat_1_in_t\; - Tx_Enable_Count : \msk_top_regs.msk_stat_2_in_t\; - PRBS_Bit_Count : \msk_top_regs.stat_32_bits_in_t\; - PRBS_Error_Count : \msk_top_regs.stat_32_errs_in_t\; - LPF_Accum_F1 : \msk_top_regs.stat_32_lpf_acc_desc_8cebc7dc_name_f20c6670_in_t\; - LPF_Accum_F2 : \msk_top_regs.stat_32_lpf_acc_desc_dea6bd99_name_758fd0ce_in_t\; - axis_xfer_count : \msk_top_regs.msk_stat_3_in_t\; - f1_nco_adjust : \msk_top_regs.observation_data_data_0c017ef4_desc_64ff3689_name_d8ad3b25_in_t\; - f2_nco_adjust : \msk_top_regs.observation_data_data_0515efaa_desc_ebde6d39_name_2c154788_in_t\; - f1_error : \msk_top_regs.observation_data_data_25a21249_desc_417e1c96_name_3b640507_in_t\; - f2_error : \msk_top_regs.observation_data_data_272a00b6_desc_70869502_name_3de9a0d3_in_t\; - rx_power : \msk_top_regs.rx_power_in_t\; + Tx_Bit_Count : \msk_top_regs.msk_stat_1__external_in_t\; + Tx_Enable_Count : \msk_top_regs.msk_stat_2__external_in_t\; + PRBS_Bit_Count : \msk_top_regs.stat_32_bits__external_in_t\; + PRBS_Error_Count : \msk_top_regs.stat_32_errs__external_in_t\; + LPF_Accum_F1 : \msk_top_regs.stat_32_lpf_acc_desc_8cebc7dc_name_f20c6670__external_in_t\; + LPF_Accum_F2 : \msk_top_regs.stat_32_lpf_acc_desc_dea6bd99_name_758fd0ce__external_in_t\; + axis_xfer_count : \msk_top_regs.msk_stat_3__external_in_t\; + f1_nco_adjust : \msk_top_regs.observation_data_data_0c017ef4_desc_64ff3689_name_d8ad3b25__external_in_t\; + f2_nco_adjust : \msk_top_regs.observation_data_data_0515efaa_desc_ebde6d39_name_2c154788__external_in_t\; + f1_error : \msk_top_regs.observation_data_data_25a21249_desc_417e1c96_name_3b640507__external_in_t\; + f2_error : \msk_top_regs.observation_data_data_272a00b6_desc_70869502_name_3de9a0d3__external_in_t\; + rx_power : \msk_top_regs.rx_power__external_in_t\; end record; type \msk_top_regs.msk_init.txrxinit_out_t\ is record @@ -192,6 +156,16 @@ package msk_top_regs_pkg is diff_encoder_loopback : \msk_top_regs.msk_ctrl.diff_encoder_loopback_out_t\; end record; + type \msk_top_regs.msk_stat_1__external_out_t\ is record + req : std_logic; + req_is_wr : std_logic; + end record; + + type \msk_top_regs.msk_stat_2__external_out_t\ is record + req : std_logic; + req_is_wr : std_logic; + end record; + type \msk_top_regs.config_nco_fw_desc_c4924cc6_name_0c494469.config_data_out_t\ is record value : std_logic_vector(31 downto 0); end record; @@ -341,6 +315,31 @@ package msk_top_regs_pkg is config_data : \msk_top_regs.config_prbs_errmask.config_data_out_t\; end record; + type \msk_top_regs.stat_32_bits__external_out_t\ is record + req : std_logic; + req_is_wr : std_logic; + end record; + + type \msk_top_regs.stat_32_errs__external_out_t\ is record + req : std_logic; + req_is_wr : std_logic; + end record; + + type \msk_top_regs.stat_32_lpf_acc_desc_8cebc7dc_name_f20c6670__external_out_t\ is record + req : std_logic; + req_is_wr : std_logic; + end record; + + type \msk_top_regs.stat_32_lpf_acc_desc_dea6bd99_name_758fd0ce__external_out_t\ is record + req : std_logic; + req_is_wr : std_logic; + end record; + + type \msk_top_regs.msk_stat_3__external_out_t\ is record + req : std_logic; + req_is_wr : std_logic; + end record; + type \msk_top_regs.rx_sample_discard.rx_sample_discard_out_t\ is record value : std_logic_vector(7 downto 0); end record; @@ -367,6 +366,26 @@ package msk_top_regs_pkg is p_shift : \msk_top_regs.lpf_config_2.p_shift_out_t\; end record; + type \msk_top_regs.observation_data_data_0c017ef4_desc_64ff3689_name_d8ad3b25__external_out_t\ is record + req : std_logic; + req_is_wr : std_logic; + end record; + + type \msk_top_regs.observation_data_data_0515efaa_desc_ebde6d39_name_2c154788__external_out_t\ is record + req : std_logic; + req_is_wr : std_logic; + end record; + + type \msk_top_regs.observation_data_data_25a21249_desc_417e1c96_name_3b640507__external_out_t\ is record + req : std_logic; + req_is_wr : std_logic; + end record; + + type \msk_top_regs.observation_data_data_272a00b6_desc_70869502_name_3de9a0d3__external_out_t\ is record + req : std_logic; + req_is_wr : std_logic; + end record; + type \msk_top_regs.tx_sync_ctrl.tx_sync_ena_out_t\ is record value : std_logic; end record; @@ -406,9 +425,16 @@ package msk_top_regs_pkg is alpha : \msk_top_regs.lowpass_ema_alpha.alpha_out_t\; end record; + type \msk_top_regs.rx_power__external_out_t\ is record + req : std_logic; + req_is_wr : std_logic; + end record; + type msk_top_regs_out_t is record MSK_Init : \msk_top_regs.msk_init_out_t\; MSK_Control : \msk_top_regs.msk_ctrl_out_t\; + Tx_Bit_Count : \msk_top_regs.msk_stat_1__external_out_t\; + Tx_Enable_Count : \msk_top_regs.msk_stat_2__external_out_t\; Fb_FreqWord : \msk_top_regs.config_nco_fw_desc_c4924cc6_name_0c494469_out_t\; TX_F1_FreqWord : \msk_top_regs.config_nco_fw_desc_94d7aaf5_name_84dd0c1c_out_t\; TX_F2_FreqWord : \msk_top_regs.config_nco_fw_desc_42134a4f_name_d97dbd51_out_t\; @@ -422,11 +448,21 @@ package msk_top_regs_pkg is PRBS_Initial_State : \msk_top_regs.config_prbs_seed_out_t\; PRBS_Polynomial : \msk_top_regs.config_prbs_poly_out_t\; PRBS_Error_Mask : \msk_top_regs.config_prbs_errmask_out_t\; + PRBS_Bit_Count : \msk_top_regs.stat_32_bits__external_out_t\; + PRBS_Error_Count : \msk_top_regs.stat_32_errs__external_out_t\; + LPF_Accum_F1 : \msk_top_regs.stat_32_lpf_acc_desc_8cebc7dc_name_f20c6670__external_out_t\; + LPF_Accum_F2 : \msk_top_regs.stat_32_lpf_acc_desc_dea6bd99_name_758fd0ce__external_out_t\; + axis_xfer_count : \msk_top_regs.msk_stat_3__external_out_t\; Rx_Sample_Discard : \msk_top_regs.rx_sample_discard_out_t\; LPF_Config_2 : \msk_top_regs.lpf_config_2_out_t\; + f1_nco_adjust : \msk_top_regs.observation_data_data_0c017ef4_desc_64ff3689_name_d8ad3b25__external_out_t\; + f2_nco_adjust : \msk_top_regs.observation_data_data_0515efaa_desc_ebde6d39_name_2c154788__external_out_t\; + f1_error : \msk_top_regs.observation_data_data_25a21249_desc_417e1c96_name_3b640507__external_out_t\; + f2_error : \msk_top_regs.observation_data_data_272a00b6_desc_70869502_name_3de9a0d3__external_out_t\; Tx_Sync_Ctrl : \msk_top_regs.tx_sync_ctrl_out_t\; Tx_Sync_Cnt : \msk_top_regs.tx_sync_cnt_out_t\; lowpass_ema_alpha1 : \msk_top_regs.lowpass_ema_alpha_out_t\; lowpass_ema_alpha2 : \msk_top_regs.lowpass_ema_alpha_out_t\; + rx_power : \msk_top_regs.rx_power__external_out_t\; end record; end package; diff --git a/rdl/src/msk_top_regs.rdl b/rdl/src/msk_top_regs.rdl index 207c848..c293d19 100644 --- a/rdl/src/msk_top_regs.rdl +++ b/rdl/src/msk_top_regs.rdl @@ -182,6 +182,7 @@ addrmap msk_top_regs { desc = "Count of data requests made by modem"; sw = r; hw = w; + onread = ruser; } tx_bit_counter[31:0]; }; @@ -194,6 +195,7 @@ addrmap msk_top_regs { name = "Tx Enable Count"; sw = r; hw = w; + onread = ruser; } tx_ena_counter[31:0] = 0; }; @@ -470,6 +472,7 @@ addrmap msk_top_regs { fieldwidth = 32; sw = r; hw = w; + onread = ruser; }; reg observation_data { @@ -483,8 +486,8 @@ addrmap msk_top_regs { msk_init MSK_Init; msk_ctrl MSK_Control; msk_stat_0 MSK_Status; - msk_stat_1 Tx_Bit_Count; - msk_stat_2 Tx_Enable_Count; + external msk_stat_1 Tx_Bit_Count; + external msk_stat_2 Tx_Enable_Count; config_nco_fw Fb_FreqWord; Fb_FreqWord->desc = "Set Modem Data Rate"; Fb_FreqWord->name = "Bitrate NCO Frequency Control Word"; @@ -512,33 +515,33 @@ addrmap msk_top_regs { config_prbs_seed PRBS_Initial_State; config_prbs_poly PRBS_Polynomial; config_prbs_errmask PRBS_Error_Mask; - stat_32_bits PRBS_Bit_Count; - stat_32_errs PRBS_Error_Count; - stat_32_lpf_acc LPF_Accum_F1; + external stat_32_bits PRBS_Bit_Count; + external stat_32_errs PRBS_Error_Count; + external stat_32_lpf_acc LPF_Accum_F1; LPF_Accum_F1->name = "F1 PI Controller Accumulator"; LPF_Accum_F1->desc = "Value of the F1 PI Controller Accumulator"; - stat_32_lpf_acc LPF_Accum_F2; + external stat_32_lpf_acc LPF_Accum_F2; LPF_Accum_F2->name = "F2 PI Controller Accumulator"; LPF_Accum_F2->desc = "Value of the F2 PI Controller Accumulator"; - msk_stat_3 axis_xfer_count; + external msk_stat_3 axis_xfer_count; rx_sample_discard Rx_Sample_Discard; lpf_config_2 LPF_Config_2; - observation_data f1_nco_adjust; + external observation_data f1_nco_adjust; f1_nco_adjust->name = "F1 NCO Frequency Adjust"; f1_nco_adjust->desc = "Frequency offet applied to the F1 NCO"; f1_nco_adjust.data->name = "F1 NCO Frequency Adjust"; f1_nco_adjust.data->desc = "Frequency offet applied to the F1 NCO"; - observation_data f2_nco_adjust; + external observation_data f2_nco_adjust; f2_nco_adjust->name = "F2 NCO Frequency Adjust"; f2_nco_adjust->desc = "Frequency offet applied to the F2 NCO"; f2_nco_adjust.data->name = "F2 NCO Frequency Adjust"; f2_nco_adjust.data->desc = "Frequency offet applied to the F2 NCO"; - observation_data f1_error; + external observation_data f1_error; f1_error->name = "F1 Error Value"; f1_error->desc = "Error value of the F1 Costas loop after each active bit period"; f1_error.data->name = "F1 Error Value"; f1_error.data->desc = "Error value of the F1 Costas loop after each active bit period"; - observation_data f2_error; + external observation_data f2_error; f2_error->name = "F2 Error Value"; f2_error->desc = "Error value of the F2 Costas loop after each active bit period"; f2_error.data->name = "F2 Error Value"; @@ -547,6 +550,6 @@ addrmap msk_top_regs { tx_sync_cnt Tx_Sync_Cnt; lowpass_ema_alpha lowpass_ema_alpha1; lowpass_ema_alpha lowpass_ema_alpha2; - rx_power rx_power; + external rx_power rx_power; }; diff --git a/sim/Makefile b/sim/Makefile index d983c1c..b41afca 100644 --- a/sim/Makefile +++ b/sim/Makefile @@ -24,6 +24,8 @@ VHDL_SOURCES += $(RDL)/src/axi4lite_intf_pkg.vhd \ $(RDL)/src/reg_utils.vhd \ $(RDL)/outputs/rtl/msk_top_regs_pkg.vhd \ $(RDL)/outputs/rtl/msk_top_regs.vhd \ + $(SRC)/pulse_detect.vhd \ + $(SRC)/data_capture.vhd \ $(SRC)/cdc_resync.vhd \ $(SRC)/axis_async_fifo.vhd \ $(SRC)/axis_dma_adapter.vhd \ diff --git a/sim/msk_test.py b/sim/msk_test.py index 04a6aa2..f595209 100755 --- a/sim/msk_test.py +++ b/sim/msk_test.py @@ -281,11 +281,11 @@ async def read(self, addr, width, accesswidth): self.rready.value = 0 - await RisingEdge(self.aclk) - await RisingEdge(self.aclk) + read_data = self.rdata.value.integer + await RisingEdge(self.aclk) - return self.rdata.value.integer + return read_data async def write(self, addr, width, accesswidth, data): @@ -748,7 +748,7 @@ async def msk_test_1(dut): hash_id = await regs.Hash_ID_Low.read() hash_id = await regs.Hash_ID_Low.read() print("Hash ID Low: ", hex(hash_id)) - hash_id = await regs.Hash_ID_High.read() + hash_id = await regs.Hash_ID_High.read() print("Hash ID High: ", hex(hash_id)) await Timer(100, units="ns") @@ -770,8 +770,8 @@ async def msk_test_1(dut): await cocotb.start(msksim.rx_sample_capture()) await cocotb.start(ducsim.upconvert()) await cocotb.start(ddcsim.downconvert()) - await cocotb.start(pn.generate_data()) - await cocotb.start(pn.check_data()) + # await cocotb.start(pn.generate_data()) + # await cocotb.start(pn.check_data()) sim_time = get_sim_time("us") sim_start = sim_time diff --git a/src/cdc_resync.vhd b/src/cdc_resync.vhd index 027ac44..d5f7128 100644 --- a/src/cdc_resync.vhd +++ b/src/cdc_resync.vhd @@ -69,12 +69,9 @@ USE ieee.numeric_std.ALL; -- Entity ENTITY cdc_resync IS - GENERIC ( - STAGES : NATURAL := 2 - ); PORT ( clk : IN std_logic; - resetn : IN std_logic; + sync_reset : IN std_logic; di : IN std_logic; do : OUT std_logic @@ -83,18 +80,20 @@ END ENTITY cdc_resync; ARCHITECTURE rtl OF cdc_resync IS - SIGNAL di_s : std_logic_vector(0 TO STAGES-1); + SIGNAL di_s : std_logic_vector(0 TO 1); BEGIN - do <= di_s(STAGES -1); + do <= di_s(1); - resync : PROCESS (clk, resetn) + resync : PROCESS (clk) BEGIN - IF resetn = '0' THEN - di_s <= (OTHERS => '0'); - ELSIF clk'EVENT AND clk = '1' THEN - di_s <= di & di_s(0 TO STAGES-2); + IF clk'EVENT AND clk = '1' THEN + IF sync_reset = '1' THEN + di_s <= (OTHERS => '0'); + ELSE + di_s <= di & di_s(0 TO 0); + END IF; END IF; END PROCESS resync; diff --git a/src/data_capture.vhd b/src/data_capture.vhd new file mode 100644 index 0000000..71a3bc8 --- /dev/null +++ b/src/data_capture.vhd @@ -0,0 +1,102 @@ +------------------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------------------ +-- _______ ________ ______ +-- __ __ \________ _____ _______ ___ __ \_____ _____________ ______ ___________________ /_ +-- _ / / /___ __ \_ _ \__ __ \ __ /_/ /_ _ \__ ___/_ _ \_ __ `/__ ___/_ ___/__ __ \ +-- / /_/ / __ /_/ // __/_ / / / _ _, _/ / __/_(__ ) / __// /_/ / _ / / /__ _ / / / +-- \____/ _ .___/ \___/ /_/ /_/ /_/ |_| \___/ /____/ \___/ \__,_/ /_/ \___/ /_/ /_/ +-- /_/ +-- ________ _____ _____ _____ _____ +-- ____ _/_______ __________ /____(_)__ /_____ ____ /______ +-- __ / __ __ \__ ___/_ __/__ / _ __/_ / / /_ __/_ _ \ +-- __/ / _ / / /_(__ ) / /_ _ / / /_ / /_/ / / /_ / __/ +-- /___/ /_/ /_/ /____/ \__/ /_/ \__/ \__,_/ \__/ \___/ +-- +------------------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------------------ +-- Copyright +------------------------------------------------------------------------------------------------------ +-- +-- Copyright 2025 by M. Wishek +-- +------------------------------------------------------------------------------------------------------ +-- License +------------------------------------------------------------------------------------------------------ +-- +-- This source describes Open Hardware and is licensed under the CERN-OHL-W v2. +-- +-- You may redistribute and modify this source and make products using it under +-- the terms of the CERN-OHL-W v2 (https://ohwr.org/cern_ohl_w_v2.txt). +-- +-- This source is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING +-- OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR A PARTICULAR PURPOSE. +-- Please see the CERN-OHL-W v2 for applicable conditions. +-- +-- Source location: TBD +-- +-- As per CERN-OHL-W v2 section 4.1, should You produce hardware based on this +-- source, You must maintain the Source Location visible on the external case of +-- the products you make using this source. +-- +------------------------------------------------------------------------------------------------------ +-- Block name and description +------------------------------------------------------------------------------------------------------ +-- +-- This is a wrapper block for the register module generated by DesyRDL. +-- +-- Documentation location: TBD +-- +------------------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------------------ + + +------------------------------------------------------------------------------------------------------ +-- ╦ ┬┌┐ ┬─┐┌─┐┬─┐┬┌─┐┌─┐ +-- ║ │├┴┐├┬┘├─┤├┬┘│├┤ └─┐ +-- ╩═╝┴└─┘┴└─┴ ┴┴└─┴└─┘└─┘ +------------------------------------------------------------------------------------------------------ +-- Libraries + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +------------------------------------------------------------------------------------------------------ +-- ╔═╗┌┐┌┌┬┐┬┌┬┐┬ ┬ +-- ║╣ │││ │ │ │ └┬┘ +-- ╚═╝┘└┘ ┴ ┴ ┴ ┴ +------------------------------------------------------------------------------------------------------ +-- Entity + +ENTITY data_capture IS + GENERIC ( + data_width : natural := 32 + ); + PORT ( + clk : IN std_logic; + sync_reset : IN std_logic; + + capture : IN std_logic; + + di : IN std_logic_vector(data_width -1 DOWNTO 0); + do : OUT std_logic_vector(data_width -1 DOWNTO 0) + ); +END ENTITY data_capture; + +ARCHITECTURE rtl OF data_capture IS +BEGIN + + capture_proc : PROCESS (clk) + BEGIN + IF clk'EVENT AND clk = '1' THEN + IF sync_reset = '1' THEN + do <= (OTHERS => '0'); + ELSIF capture = '1' THEN + do <= di; + END IF; + END IF; + END PROCESS capture_proc; + +END ARCHITECTURE rtl; + + diff --git a/src/msk_top_csr.vhd b/src/msk_top_csr.vhd index b8b1780..9fa83bd 100644 --- a/src/msk_top_csr.vhd +++ b/src/msk_top_csr.vhd @@ -188,18 +188,57 @@ ARCHITECTURE rtl OF msk_top_csr IS SIGNAL txrxinit : std_logic; COMPONENT cdc_resync IS - GENERIC ( - STAGES : NATURAL := 2 - ); PORT ( clk : IN std_logic; - resetn : IN std_logic; + sync_reset : IN std_logic; di : IN std_logic; do : OUT std_logic ); END COMPONENT cdc_resync; + COMPONENT pulse_detect IS + PORT ( + clk : IN std_logic; + sync_reset : IN std_logic; + + di : IN std_logic; + do : OUT std_logic + ); + END COMPONENT pulse_detect; + + COMPONENT data_capture IS + GENERIC ( + data_width : natural := 32 + ); + PORT ( + clk : IN std_logic; + sync_reset : IN std_logic; + + capture : IN std_logic; + + di : IN std_logic_vector(data_width -1 DOWNTO 0); + do : OUT std_logic_vector(data_width -1 DOWNTO 0) + ); + END COMPONENT data_capture; + + SIGNAL csr_meta : std_logic; + SIGNAL csr_init : std_logic; + + SIGNAL tx_bit_counter_req : std_logic; + SIGNAL tx_ena_counter_req : std_logic; + SIGNAL f1_error_req : std_logic; + SIGNAL f2_error_req : std_logic; + SIGNAL f1_nco_adjust_req : std_logic; + SIGNAL f2_nco_adjust_req : std_logic; + + SIGNAL prbs_bits_req : std_logic; + SIGNAL prbs_errs_req : std_logic; + SIGNAL lpf_accum_f1_req : std_logic; + SIGNAL lpf_accum_f2_req : std_logic; + SIGNAL pd_power_req : std_logic; + SIGNAL axis_xfer_count_req : std_logic; + BEGIN s_axil_i.AWVALID <= s_axi_awvalid; @@ -225,7 +264,7 @@ BEGIN u_msk_regs : ENTITY work.msk_top_regs(rtl) PORT MAP ( - clk => s_axi_aclk, + clk => s_axi_aclk, rst => NOT s_axi_aresetn, s_axil_i => s_axil_i, s_axil_o => s_axil_o, @@ -234,41 +273,83 @@ BEGIN hwif_out => hwif_out ); - -- Status signals crossing from local clock domain to the AXI clock domain - hwif_in.MSK_Status.demod_sync_lock.next_q <= '0'; - hwif_in.MSK_Status.tx_enable.next_q <= tx_enable; - hwif_in.MSK_Status.rx_enable.next_q <= rx_enable; - hwif_in.MSK_Status.tx_axis_valid.next_q <= tx_axis_valid; - hwif_in.Tx_Bit_Count.tx_bit_counter.next_q <= tx_bit_counter; - hwif_in.Tx_Enable_Count.tx_ena_counter.next_q <= tx_ena_counter; - hwif_in.axis_xfer_count.xfer_count.next_q <= xfer_count; - hwif_in.PRBS_Bit_Count.status_data.next_q <= prbs_bits; - hwif_in.PRBS_Error_Count.status_data.next_q <= prbs_errs; - hwif_in.LPF_Accum_F1.status_data.next_q <= lpf_accum_f1; - hwif_in.LPF_Accum_F2.status_data.next_q <= lpf_accum_f2; - hwif_in.f1_nco_adjust.data.next_q <= f1_nco_adjust; - hwif_in.f2_nco_adjust.data.next_q <= f2_nco_adjust; - hwif_in.f1_error.data.next_q <= f1_error; - hwif_in.f2_error.data.next_q <= f2_error; - hwif_in.rx_power.rx_power.next_q <= pd_power; - - -- Control signals requiring re-sync from AXI clock domain to local clock domain - u01s: cdc_resync PORT MAP (clk, '1', hwif_out.MSK_Init.txrxinit.value, txrxinit ); - u02s: cdc_resync PORT MAP (clk, '1', hwif_out.MSK_Init.txinit.value OR txrxinit, txinit ); - u03s: cdc_resync PORT MAP (clk, '1', hwif_out.MSK_Init.rxinit.value OR txrxinit, rxinit ); - u04s: cdc_resync PORT MAP (clk, '1', hwif_out.MSK_Control.ptt.value, ptt ); - u05s: cdc_resync PORT MAP (clk, '1', hwif_out.MSK_Control.loopback_ena.value, loopback_ena ); - u06s: cdc_resync PORT MAP (clk, '1', hwif_out.MSK_Control.diff_encoder_loopback.value, diff_encdec_lbk_ena ); - u07s: cdc_resync PORT MAP (clk, '1', hwif_out.MSK_Control.rx_invert.value, rx_invert ); - u08s: cdc_resync PORT MAP (clk, '1', hwif_out.MSK_Control.clear_counts.value, clear_counts ); - u09s: cdc_resync PORT MAP (clk, '1', hwif_out.LPF_Config_0.lpf_freeze.value, lpf_freeze ); - u10s: cdc_resync PORT MAP (clk, '1', hwif_out.LPF_Config_0.lpf_zero.value, lpf_zero ); - u11s: cdc_resync PORT MAP (clk, '1', hwif_out.PRBS_Control.prbs_sel.value, prbs_sel ); - u12s: cdc_resync PORT MAP (clk, '1', hwif_out.PRBS_Control.prbs_clear.value, prbs_clear ); - u13s: cdc_resync PORT MAP (clk, '1', hwif_out.PRBS_Control.prbs_error_insert.value, prbs_err_insert ); - u14s: cdc_resync PORT MAP (clk, '1', hwif_out.PRBS_Control.prbs_manual_sync.value, prbs_manual_sync ); - u15s: cdc_resync PORT MAP (clk, '1', hwif_out.Tx_Sync_Ctrl.tx_sync_ena.value, tx_sync_ena ); - u16s: cdc_resync PORT MAP (clk, '1', hwif_out.Tx_Sync_Ctrl.tx_sync_force.value, tx_sync_force ); + csr_init_proc : PROCESS (clk, s_axi_aresetn) + BEGIN + IF s_axi_aresetn = '0' THEN + csr_meta <= '1'; + csr_init <= '1'; + ELSIF clk'EVENT AND clk = '1' THEN + csr_meta <= '0'; + csr_init <= csr_meta; + END IF; + END PROCESS csr_init_proc; + + ulck_s: cdc_resync PORT MAP (s_axi_aclk, NOT s_axi_aresetn, '0', hwif_in.MSK_Status.demod_sync_lock.next_q); + utxe_s: cdc_resync PORT MAP (s_axi_aclk, NOT s_axi_aresetn, tx_enable, hwif_in.MSK_Status.tx_enable.next_q); + urxe_s: cdc_resync PORT MAP (s_axi_aclk, NOT s_axi_aresetn, rx_enable, hwif_in.MSK_Status.rx_enable.next_q); + + hwif_in.MSK_Status.tx_axis_valid.next_q <= tx_axis_valid; + + -- Status Request from AXI to MDM + utbc_r: pulse_detect PORT MAP (clk, csr_init, hwif_out.Tx_Bit_Count.req, tx_bit_counter_req ); + utbe_r: pulse_detect PORT MAP (clk, csr_init, hwif_out.Tx_Enable_Count.req, tx_ena_counter_req ); + utatc_r: pulse_detect PORT MAP (clk, csr_init, hwif_out.axis_xfer_count.req, axis_xfer_count_req ); + utf1e_r: pulse_detect PORT MAP (clk, csr_init, hwif_out.f1_error.req, f1_error_req ); + utf2e_r: pulse_detect PORT MAP (clk, csr_init, hwif_out.f2_error.req, f2_error_req ); + utf1a_r: pulse_detect PORT MAP (clk, csr_init, hwif_out.f1_nco_adjust.req, f1_nco_adjust_req ); + utf2a_r: pulse_detect PORT MAP (clk, csr_init, hwif_out.f2_nco_adjust.req, f2_nco_adjust_req ); + utprb_r: pulse_detect PORT MAP (clk, csr_init, hwif_out.PRBS_Bit_Count.req, prbs_bits_req ); + utpre_r: pulse_detect PORT MAP (clk, csr_init, hwif_out.PRBS_Error_Count.req, prbs_errs_req ); + utlp1_r: pulse_detect PORT MAP (clk, csr_init, hwif_out.LPF_Accum_F1.req, lpf_accum_f1_req ); + utlp2_r: pulse_detect PORT MAP (clk, csr_init, hwif_out.LPF_Accum_F2.req, lpf_accum_f2_req ); + utpwr_r: pulse_detect PORT MAP (clk, csr_init, hwif_out.rx_power.req, pd_power_req ); + + -- Status acknowledge from MDM to AXI + utbc_a : pulse_detect PORT MAP (s_axi_aclk, NOT s_axi_aresetn, tx_bit_counter_req, hwif_in.Tx_Bit_Count.rd_ack ); + utbe_a : pulse_detect PORT MAP (s_axi_aclk, NOT s_axi_aresetn, tx_ena_counter_req, hwif_in.Tx_Enable_Count.rd_ack ); + utatc_a: pulse_detect PORT MAP (s_axi_aclk, NOT s_axi_aresetn, axis_xfer_count_req, hwif_in.axis_xfer_count.rd_ack ); + utf1e_a: pulse_detect PORT MAP (s_axi_aclk, NOT s_axi_aresetn, f1_error_req, hwif_in.f1_error.rd_ack ); + utf2e_a: pulse_detect PORT MAP (s_axi_aclk, NOT s_axi_aresetn, f2_error_req, hwif_in.f2_error.rd_ack ); + utf1a_a: pulse_detect PORT MAP (s_axi_aclk, NOT s_axi_aresetn, f1_nco_adjust_req, hwif_in.f1_nco_adjust.rd_ack ); + utf2a_a: pulse_detect PORT MAP (s_axi_aclk, NOT s_axi_aresetn, f2_nco_adjust_req, hwif_in.f2_nco_adjust.rd_ack ); + utprb_a: pulse_detect PORT MAP (s_axi_aclk, NOT s_axi_aresetn, prbs_bits_req, hwif_in.PRBS_Bit_Count.rd_ack ); + utpre_a: pulse_detect PORT MAP (s_axi_aclk, NOT s_axi_aresetn, prbs_errs_req, hwif_in.PRBS_Error_Count.rd_ack ); + utlp1_a: pulse_detect PORT MAP (s_axi_aclk, NOT s_axi_aresetn, lpf_accum_f1_req, hwif_in.LPF_Accum_F1.rd_ack ); + utlp2_a: pulse_detect PORT MAP (s_axi_aclk, NOT s_axi_aresetn, lpf_accum_f2_req, hwif_in.LPF_Accum_F2.rd_ack ); + utpwr_a: pulse_detect PORT MAP (s_axi_aclk, NOT s_axi_aresetn, pd_power_req, hwif_in.rx_power.rd_ack ); + + -- Status capture from MDM to AXI + utbc_c : data_capture PORT MAP (clk, csr_init, tx_bit_counter_req, tx_bit_counter, hwif_in.Tx_Bit_Count.rd_data ); + utbe_c : data_capture PORT MAP (clk, csr_init, tx_ena_counter_req, tx_ena_counter, hwif_in.Tx_Enable_Count.rd_data ); + utatc_c: data_capture PORT MAP (clk, csr_init, axis_xfer_count_req, xfer_count, hwif_in.axis_xfer_count.rd_data ); + utf1e_c: data_capture PORT MAP (clk, csr_init, f1_error_req, f1_error, hwif_in.f1_error.rd_data ); + utf2e_c: data_capture PORT MAP (clk, csr_init, f2_error_req, f2_error, hwif_in.f2_error.rd_data ); + utf1a_c: data_capture PORT MAP (clk, csr_init, f1_nco_adjust_req, f1_nco_adjust, hwif_in.f1_nco_adjust.rd_data ); + utf2a_c: data_capture PORT MAP (clk, csr_init, f2_nco_adjust_req, f2_nco_adjust, hwif_in.f2_nco_adjust.rd_data ); + utprb_c: data_capture PORT MAP (clk, csr_init, prbs_bits_req, prbs_bits, hwif_in.PRBS_Bit_Count.rd_data ); + utpre_c: data_capture PORT MAP (clk, csr_init, prbs_errs_req, prbs_errs, hwif_in.PRBS_Error_Count.rd_data); + utlp1_c: data_capture PORT MAP (clk, csr_init, lpf_accum_f1_req, lpf_accum_f1, hwif_in.LPF_Accum_F1.rd_data ); + utlp2_c: data_capture PORT MAP (clk, csr_init, lpf_accum_f2_req, lpf_accum_f2, hwif_in.LPF_Accum_F2.rd_data ); + utpwr_c: data_capture PORT MAP (clk, csr_init, pd_power_req, std_logic_vector(resize(unsigned(pd_power),32)), + hwif_in.rx_power.rd_data); + + -- Control from AXI to MDM + u01s: cdc_resync PORT MAP (clk, csr_init, hwif_out.MSK_Init.txrxinit.value, txrxinit ); + u02s: cdc_resync PORT MAP (clk, csr_init, hwif_out.MSK_Init.txinit.value OR txrxinit, txinit ); + u03s: cdc_resync PORT MAP (clk, csr_init, hwif_out.MSK_Init.rxinit.value OR txrxinit, rxinit ); + u04s: cdc_resync PORT MAP (clk, csr_init, hwif_out.MSK_Control.ptt.value, ptt ); + u05s: cdc_resync PORT MAP (clk, csr_init, hwif_out.MSK_Control.loopback_ena.value, loopback_ena ); + u06s: cdc_resync PORT MAP (clk, csr_init, hwif_out.MSK_Control.diff_encoder_loopback.value, diff_encdec_lbk_ena ); + u07s: cdc_resync PORT MAP (clk, csr_init, hwif_out.MSK_Control.rx_invert.value, rx_invert ); + u08s: cdc_resync PORT MAP (clk, csr_init, hwif_out.MSK_Control.clear_counts.value, clear_counts ); + u09s: cdc_resync PORT MAP (clk, csr_init, hwif_out.LPF_Config_0.lpf_freeze.value, lpf_freeze ); + u10s: cdc_resync PORT MAP (clk, csr_init, hwif_out.LPF_Config_0.lpf_zero.value, lpf_zero ); + u11s: cdc_resync PORT MAP (clk, csr_init, hwif_out.PRBS_Control.prbs_sel.value, prbs_sel ); + u12s: cdc_resync PORT MAP (clk, csr_init, hwif_out.PRBS_Control.prbs_clear.value, prbs_clear ); + u13s: cdc_resync PORT MAP (clk, csr_init, hwif_out.PRBS_Control.prbs_error_insert.value, prbs_err_insert ); + u14s: cdc_resync PORT MAP (clk, csr_init, hwif_out.PRBS_Control.prbs_manual_sync.value, prbs_manual_sync ); + u15s: cdc_resync PORT MAP (clk, csr_init, hwif_out.Tx_Sync_Ctrl.tx_sync_ena.value, tx_sync_ena ); + u16s: cdc_resync PORT MAP (clk, csr_init, hwif_out.Tx_Sync_Ctrl.tx_sync_force.value, tx_sync_force ); -- The remaining control signals also cross from the AXI to the local clock domain. These are static signals -- that are configured while the txrxinit is active. The active txrxinit hold the destination FFs to an diff --git a/src/pulse_detect.vhd b/src/pulse_detect.vhd new file mode 100644 index 0000000..a1060f3 --- /dev/null +++ b/src/pulse_detect.vhd @@ -0,0 +1,109 @@ +------------------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------------------ +-- _______ ________ ______ +-- __ __ \________ _____ _______ ___ __ \_____ _____________ ______ ___________________ /_ +-- _ / / /___ __ \_ _ \__ __ \ __ /_/ /_ _ \__ ___/_ _ \_ __ `/__ ___/_ ___/__ __ \ +-- / /_/ / __ /_/ // __/_ / / / _ _, _/ / __/_(__ ) / __// /_/ / _ / / /__ _ / / / +-- \____/ _ .___/ \___/ /_/ /_/ /_/ |_| \___/ /____/ \___/ \__,_/ /_/ \___/ /_/ /_/ +-- /_/ +-- ________ _____ _____ _____ _____ +-- ____ _/_______ __________ /____(_)__ /_____ ____ /______ +-- __ / __ __ \__ ___/_ __/__ / _ __/_ / / /_ __/_ _ \ +-- __/ / _ / / /_(__ ) / /_ _ / / /_ / /_/ / / /_ / __/ +-- /___/ /_/ /_/ /____/ \__/ /_/ \__/ \__,_/ \__/ \___/ +-- +------------------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------------------ +-- Copyright +------------------------------------------------------------------------------------------------------ +-- +-- Copyright 2025 by M. Wishek +-- +------------------------------------------------------------------------------------------------------ +-- License +------------------------------------------------------------------------------------------------------ +-- +-- This source describes Open Hardware and is licensed under the CERN-OHL-W v2. +-- +-- You may redistribute and modify this source and make products using it under +-- the terms of the CERN-OHL-W v2 (https://ohwr.org/cern_ohl_w_v2.txt). +-- +-- This source is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING +-- OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR A PARTICULAR PURPOSE. +-- Please see the CERN-OHL-W v2 for applicable conditions. +-- +-- Source location: TBD +-- +-- As per CERN-OHL-W v2 section 4.1, should You produce hardware based on this +-- source, You must maintain the Source Location visible on the external case of +-- the products you make using this source. +-- +------------------------------------------------------------------------------------------------------ +-- Block name and description +------------------------------------------------------------------------------------------------------ +-- +-- This is a wrapper block for the register module generated by DesyRDL. +-- +-- Documentation location: TBD +-- +------------------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------------------ + + +------------------------------------------------------------------------------------------------------ +-- ╦ ┬┌┐ ┬─┐┌─┐┬─┐┬┌─┐┌─┐ +-- ║ │├┴┐├┬┘├─┤├┬┘│├┤ └─┐ +-- ╩═╝┴└─┘┴└─┴ ┴┴└─┴└─┘└─┘ +------------------------------------------------------------------------------------------------------ +-- Libraries + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +------------------------------------------------------------------------------------------------------ +-- ╔═╗┌┐┌┌┬┐┬┌┬┐┬ ┬ +-- ║╣ │││ │ │ │ └┬┘ +-- ╚═╝┘└┘ ┴ ┴ ┴ ┴ +------------------------------------------------------------------------------------------------------ +-- Entity + +ENTITY pulse_detect IS + PORT ( + clk : IN std_logic; + sync_reset : IN std_logic; + + di : IN std_logic; + do : OUT std_logic + ); +END ENTITY pulse_detect; + +ARCHITECTURE rtl OF pulse_detect IS + + SIGNAL detect_q : std_logic; + SIGNAL detect_q1 : std_logic; + SIGNAL detect_q2 : std_logic; + +BEGIN + + do <= detect_q1 AND NOT detect_q2; + + detect : PROCESS (clk, di) + BEGIN + IF di = '1' THEN + detect_q <= '1'; + ELSIF clk'EVENT AND clk = '1' THEN + IF sync_reset = '1' OR detect_q2 = '1' THEN + detect_q <= '0'; + detect_q1 <= '0'; + detect_q2 <= '0'; + ELSE + detect_q1 <= detect_q; + detect_q2 <= detect_q1; + END IF; + END IF; + END PROCESS detect; + +END ARCHITECTURE rtl; + + From 3cf82bb354d565cb1dbc504db4752f2a942a2823 Mon Sep 17 00:00:00 2001 From: Matthew Wishek Date: Sun, 26 Oct 2025 21:46:34 -0600 Subject: [PATCH 03/60] Resolve merge/rebase conflicts --- docs/msk_math.md | 18 ++++++-- prbs | 2 +- src/axis_async_fifo.vhd | 93 ++++++++++++++++++++++++++++++++++++++++- src/msk_top.vhd | 60 ++++++++++++++++++-------- 4 files changed, 150 insertions(+), 23 deletions(-) diff --git a/docs/msk_math.md b/docs/msk_math.md index fd03d93..186dfea 100644 --- a/docs/msk_math.md +++ b/docs/msk_math.md @@ -115,10 +115,12 @@ The four resulting values for the f1 mix are cos(2𝝿f1t)*cos(2𝝿f1t) = 1/2 [ cos(2𝝿f1t - 2𝝿f1t) + cos(2𝝿f1t + 2𝝿f1t) ] = 1/2 [ cos(0) + cos(4𝝿f1t) ] = 1/2 [ 1 + cos(4𝝿f1t)] + = 1/2 + 1/2cos(2𝝿2f1t) -cos(2𝝿f1t)*cos(2𝝿f1t) = -1/2 [ cos(2𝝿f1t - 2𝝿f1t) + cos(2𝝿f1t + 2𝝿f1t) ] = -1/2 [ cos(0) + cos(4𝝿f1t) ] = -1/2 [ 1 + cos(4𝝿f1t)] + = -1/2 - 1/2cos(2𝝿2f1t) (both the previous results are a DC value and a sinusoid at 2*f1) @@ -149,16 +151,16 @@ cos(2𝝿f1t)*sin(2𝝿f1t) = 1/2 [ sin(2𝝿f1t + 2𝝿f1t + theta) - sin(2𝝿 = 1/2 sin(4𝝿f1t + theta) --cos(2𝝿f1t)*sin(2𝝿f1t) = -1/2 [ sin(2𝝿f1t + 2𝝿f1t) - sin(2𝝿f1t - 2𝝿f1t) ] - = -1/2 [ sin(4𝝿f1t) - sin(0) ] - = -1/2 sin(4𝝿f1t) +-cos(2𝝿f1t)*sin(2𝝿f1t) = -1/2 [ sin(2𝝿f1t + 2𝝿f1t + theta) - sin(2𝝿f1t - 2𝝿f1t + theta) ] + = -1/2 [ sin(2𝝿2f1t + theta) - sin(theta) ] + = -1/2 sin(2𝝿2f1t + theta) again we only care about the DC component, which when the phases are aligned is 0. If the phases are not aligned the sin(0) term becomes sin(Δφ) a constant. cos(2𝝿f1t)*sin(2𝝿f1t) = 1/2 [ sin(2𝝿f2t + 2𝝿f1t) - sin(2𝝿f2t - 2𝝿f1t) ] - = 1/2 [ sin(2𝝿(f2+f1)t) - sin(2𝝿(f2-f1)t) ] + = 1/2 [ sin(2𝝿(f2+f1)t) - sin(2𝝿(f2-f1)t) ] cos(2𝝿f1t)*sin(2𝝿f1t) = -1/2 [ sin(2𝝿f2t + 2𝝿f1t) - sin(2𝝿f2t - 2𝝿f1t) ] @@ -166,3 +168,11 @@ cos(2𝝿f1t)*sin(2𝝿f1t) = -1/2 [ sin(2𝝿f2t + 2𝝿f1t) - sin(2𝝿f2t - 2 + +error_instant = 1/2 sin(2𝝿2f1t + theta) * sign( 1/2 + 1/2cos(2𝝿2f1t)) + = -1/2 sin(2𝝿2f1t + theta) * sign(-1/2 - 1/2cos(2𝝿2f1t)) + = 1/2 sin(2𝝿2f1t + theta) + +error = SUM_T(1/2 sin(2𝝿2f1t + theta)) = -cos(2𝝿2f1t + theta) + C + + diff --git a/prbs b/prbs index 8e42b3e..48d9d49 160000 --- a/prbs +++ b/prbs @@ -1 +1 @@ -Subproject commit 8e42b3ea00644cea5ae34b4ebba2e062bdc58be3 +Subproject commit 48d9d49b0380a4eb18c13c230182dede94462a28 diff --git a/src/axis_async_fifo.vhd b/src/axis_async_fifo.vhd index 7db0066..ec47e82 100644 --- a/src/axis_async_fifo.vhd +++ b/src/axis_async_fifo.vhd @@ -35,9 +35,20 @@ ENTITY axis_async_fifo IS m_axis_tready : IN std_logic; m_axis_tlast : OUT std_logic; + -- Control signals + --prog_packet_size: IN std_logic_vector... + -- Status signals prog_full : OUT std_logic; - prog_empty : OUT std_logic + prog_empty : OUT std_logic; + status_aclk : IN std_logic; + status_aresetn : IN std_logic; + status_req : IN std_logic; + status_ack : OUT std_logic; + fifo_overflow : OUT std_logic; + fifo_underflow : OUT std_logic; + fifo_wr_ptr : OUT std_logic_vector(ADDR_WIDTH DOWNTO 0); + fifo_rd_ptr : OUT srd_logic_vector(ADDR_WIDTH DOWNTO 0) ); END ENTITY axis_async_fifo; @@ -216,4 +227,84 @@ BEGIN END IF; END PROCESS read_proc; + ------------------------------------------------------------------------------ + -- Status Clock Domain + ------------------------------------------------------------------------------ + status_proc : PROCESS (prog_aclk) + BEGIN + IF rising_edge(prog_aclk) BEGIN + IF prog_aresetn = '0' THEN + --prog_empty <= '0'; + --prog_full <= '0'; + fifo_overflow <= '0'; + fifo_underflow <= '0'; + fifo_wr_ptr <= (OTHERS => '0'); + fifo_rd_ptr <= (OTHERS => '0'); + fifo_status_ack <= '0'; + ELSE + + wr_status_ack_sync1 <= wr_status_ack; + wr_status_ack_sync2 <= wr_status_ack_sync1; + wr_status_ack_sync3 <= wr_status_ack_sync2; + + IF (wr_status_req_sync2 XOR wr_status_ack_sync3) = '1' THEN + prog_wr_status_ack <= '1'; + END IF; + + rd_status_ack_sync1 <= rd_status_ack; + rd_status_ack_sync2 <= rd_status_ack_sync1; + rd_status_ack_sync3 <= rd_status_ack_sync2; + + IF (rd_status_req_sync2 XOR rd_status_ack_sync3) = '1' THEN + prog_rd_status_ack <= '1'; + END IF; + + IF prog_wr_status_ack = '1' AND prod_rd_status_ack = '1' THEN + prog_status_ack <= '1'; + ELSE + prog_status_ack <= '0'; + END IF; + + END IF; + END IF; + END PROCESS status_proc; + + status_wrclk : PROCESS (wr_aclk) + BEGIN + IF rising_edge(wr_aclk) THEN + IF wr_aresetn = '0' THEN + wr_status_req_sync1 <= '0'; + wr_status_req_sync2 <= '0'; + wr_status_ack <= '0'; + ELSE + wr_status_req_sync1 <= prog_status_req; + wr_status_req_sync2 <= wr_status_req_sync1; + + IF wr_status_req_sync2 THEN + fifo_wr_ptr <= wr_ptr_bin; + wr_status_ack <= NOT wr_status_ack; + END IF; + END IF; + END IF; + END PROCESS status_wrclk; + + status_rdclk : PROCESS (rd_aclk) + BEGIN + IF rising_edge(rd_aclk) THEN + IF rd_aresetn = '0' THEN + rd_status_req_sync1 <= '0'; + rd_status_req_sync2 <= '0'; + rd_status_ack <= '0'; + ELSE + rd_status_req_sync1 <= prog_status_req; + rd_status_req_sync2 <= rd_status_req_sync1; + + IF rd_status_req_sync2 THEN + fifo_rd_ptr <= rd_ptr_bin; + rd_status_ack <= NOT rd_status_ack; + END IF; + END IF; + END IF; + END PROCESS status_wrclk; + END ARCHITECTURE rtl; diff --git a/src/msk_top.vhd b/src/msk_top.vhd index 1e5d3e7..069bd1e 100644 --- a/src/msk_top.vhd +++ b/src/msk_top.vhd @@ -168,8 +168,24 @@ ARCHITECTURE struct OF msk_top IS SIGNAL fifo_tlast : std_logic; SIGNAL frame_complete : std_logic; - SIGNAL fifo_prog_full : std_logic; - SIGNAL fifo_prog_empty : std_logic; + + SIGNAL tx_async_fifo_prog_full : std_logic; + SIGNAL tx_async_fifo_prog_empty : std_logic; + SIGNAL tx_async_fifo_overflow : std_logic; + SIGNAL tx_async_fifo_underflow : std_logic; + SIGNAL tx_async_fifo_wr_ptr : std_logic(FIFO_ADDR_WIDTH DOWNTO 0); + SIGNAL tx_async_fifo_rd_ptr : std_logic(FIFO_ADDR_WIDTH DOWNTO 0); + SIGNAL tx_async_fifo_status_req : std_logic; + SIGNAL tx_async_fifo_status_ack : std_logic; + + SIGNAL rx_async_fifo_prog_full : std_logic; + SIGNAL rx_async_fifo_prog_empty : std_logic; + SIGNAL rx_async_fifo_overflow : std_logic; + SIGNAL rx_async_fifo_underflow : std_logic; + SIGNAL rx_async_fifo_wr_ptr : std_logic(FIFO_ADDR_WIDTH DOWNTO 0); + SIGNAL rx_async_fifo_rd_ptr : std_logic(FIFO_ADDR_WIDTH DOWNTO 0); + SIGNAL rx_async_fifo_status_req : std_logic; + SIGNAL rx_async_fifo_status_ack : std_logic; -- RX chain signals SIGNAL rx_byte : std_logic_vector(7 DOWNTO 0); @@ -322,8 +338,17 @@ BEGIN m_axis_tready => fifo_tready, m_axis_tlast => fifo_tlast, - prog_full => fifo_prog_full, - prog_empty => fifo_prog_empty + -- status signals synchronized to AXI control/status bus + prog_aclk => s_axi_aclk, + prog_aresetn => s_axi_aresetn, + prog_status_req => tx_async_fifo_status_req, + prog_status_ack => tx_async_fifo_status_ack, + prog_full => tx_async_fifo_prog_full, + prog_empty => tx_async_fifo_prog_empty, + prog_overflow => tx_async_fifo_overflow, + prog_underflow => tx_async_fifo_underflow, + prog_wr_ptr => tx_async_fifo_wr_ptr, + prog_rd_ptr => tx_async_fifo_rd_ptr ); -- Stage 3: Byte-to-Bit De-serializer (MSB-FIRST VERSION) @@ -439,13 +464,6 @@ BEGIN tx_samples_I => tx_samples_I_int, tx_samples_Q => tx_samples_Q_int ); - - - - - - - ------------------------------------------------------------------------------ -- RX Stage 2: Frame Sync Detector (MSB-FIRST VERSION) @@ -470,9 +488,9 @@ BEGIN m_axis_tvalid => sync_det_tvalid, m_axis_tready => sync_det_tready, m_axis_tlast => sync_det_tlast, - frame_sync_locked => rx_frame_sync_locked, - frames_received => rx_frames_count, - frame_sync_errors => rx_frame_sync_errors, + frame_sync_locked => rx_frame_sync_locked, + frames_received => rx_frames_count, + frame_sync_errors => rx_frame_sync_errors, buffer_overflow => rx_fifo_overflow ); @@ -504,8 +522,17 @@ BEGIN m_axis_tready => m_axis_tready, m_axis_tlast => m_axis_tlast, - prog_full => OPEN, - prog_empty => OPEN + -- status signals synchronized to AXI control/status bus + prog_aclk => s_axi_aclk, + prog_aresetn => s_axi_aresetn, + prog_status_req => rx_async_fifo_status_req, + prog_status_ack => rx_async_fifo_status_ack, + prog_full => rx_async_fifo_prog_full, + prog_empty => rx_async_fifo_prog_empty, + prog_overflow => rx_async_fifo_overflow, + prog_underflow => rx_async_fifo_underflow, + prog_wr_ptr => rx_async_fifo_wr_ptr, + prog_rd_ptr => rx_async_fifo_rd_ptr ); -- Zero-pad upper bits of m_axis_tdata if wider than 8 bits @@ -538,7 +565,6 @@ BEGIN rx_bit_corr <= rx_bit WHEN rx_invert = '0' ELSE NOT rx_bit; - ------------------------------------------------------------------------------------------------------ -- MSK DEMODULATOR ------------------------------------------------------------------------------------------------------ From ca022b93eb3ec156fc22b4ba72e34a99b794adee Mon Sep 17 00:00:00 2001 From: Matthew Wishek Date: Sun, 26 Oct 2025 23:35:31 -0600 Subject: [PATCH 04/60] Add read back of async FIFO read/write pointers --- prbs | 2 +- rdl/outputs/c-header/msk_top_regs.h | 16 +- rdl/outputs/docs/msk_top_regs.md | 110 ++-- rdl/outputs/docs/msk_top_regs.pdf | Bin 113116 -> 114122 bytes .../msk_top_regs/reg_model/msk_top_regs.py | 442 +++++++++++-- .../python/msk_top_regs/sim/msk_top_regs.py | 8 + .../msk_top_regs/tests/test_msk_top_regs.py | 598 +++++++++++++++++- .../tests/test_sim_msk_top_regs.py | 200 ++++++ rdl/outputs/rtl/msk_top_regs.vhd | 18 +- rdl/outputs/rtl/msk_top_regs_pkg.vhd | 26 +- rdl/src/msk_top_regs.rdl | 9 +- sim/Makefile | 1 + sim/msk_test.py | 23 +- src/axis_async_fifo.vhd | 80 ++- src/msk_top.vhd | 52 +- src/msk_top_csr.vhd | 23 +- 16 files changed, 1468 insertions(+), 140 deletions(-) diff --git a/prbs b/prbs index 48d9d49..935c25a 160000 --- a/prbs +++ b/prbs @@ -1 +1 @@ -Subproject commit 48d9d49b0380a4eb18c13c230182dede94462a28 +Subproject commit 935c25ab545be9102a9b5ba55b14de7f7c3bfc7c diff --git a/rdl/outputs/c-header/msk_top_regs.h b/rdl/outputs/c-header/msk_top_regs.h index 1d89a4a..accc8fb 100644 --- a/rdl/outputs/c-header/msk_top_regs.h +++ b/rdl/outputs/c-header/msk_top_regs.h @@ -312,6 +312,18 @@ extern "C" { #define MSK_TOP_REGS__RX_POWER__RX_POWER_bw 23 #define MSK_TOP_REGS__RX_POWER__RX_POWER_reset 0x0 +// Reg - msk_top_regs::observation_data_data_cf6acbd7_name_aa4ec676 +#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_CF6ACBD7_NAME_AA4EC676__DATA_bm 0xffffffff +#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_CF6ACBD7_NAME_AA4EC676__DATA_bp 0 +#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_CF6ACBD7_NAME_AA4EC676__DATA_bw 32 +#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_CF6ACBD7_NAME_AA4EC676__DATA_reset 0x0 + +// Reg - msk_top_regs::observation_data_data_cf6acbd7_name_8a90eed1 +#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_CF6ACBD7_NAME_8A90EED1__DATA_bm 0xffffffff +#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_CF6ACBD7_NAME_8A90EED1__DATA_bp 0 +#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_CF6ACBD7_NAME_8A90EED1__DATA_bw 32 +#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_CF6ACBD7_NAME_8A90EED1__DATA_reset 0x0 + // Addrmap - msk_top_regs typedef struct __attribute__ ((__packed__)) { uint32_t Hash_ID_Low; @@ -350,10 +362,12 @@ typedef struct __attribute__ ((__packed__)) { uint32_t lowpass_ema_alpha1; uint32_t lowpass_ema_alpha2; uint32_t rx_power; + uint32_t tx_async_fifo_rd_wr_ptr; + uint32_t rx_async_fifo_rd_wr_ptr; } msk_top_regs_t; -static_assert(sizeof(msk_top_regs_t) == 0x90, "Packing error"); +static_assert(sizeof(msk_top_regs_t) == 0x98, "Packing error"); #ifdef __cplusplus } diff --git a/rdl/outputs/docs/msk_top_regs.md b/rdl/outputs/docs/msk_top_regs.md index db06b21..e724aaf 100644 --- a/rdl/outputs/docs/msk_top_regs.md +++ b/rdl/outputs/docs/msk_top_regs.md @@ -10,48 +10,50 @@ Don't override. Generated from: msk_top_regs - Absolute Address: 0x0 - Base Offset: 0x0 -- Size: 0x90 +- Size: 0x98

MSK Modem Configuration and Status Registers

-|Offset| Identifier | Name | -|------|------------------|-------------------------------------------------------------| -| 0x00 | Hash_ID_Low | Pluto MSK FPGA Hash ID - Lower 32-bits | -| 0x04 | Hash_ID_High | Pluto MSK FPGA Hash ID - Upper 32-bits | -| 0x08 | MSK_Init | MSK Modem Initialization Control | -| 0x0C | MSK_Control | MSK Modem Control | -| 0x10 | MSK_Status | MSK Modem Status 0 | -| 0x14 | Tx_Bit_Count | MSK Modem Status 1 | -| 0x18 | Tx_Enable_Count | MSK Modem Status 2 | -| 0x1C | Fb_FreqWord | Bitrate NCO Frequency Control Word | -| 0x20 | TX_F1_FreqWord | Tx F1 NCO Frequency Control Word | -| 0x24 | TX_F2_FreqWord | Tx F2 NCO Frequency Control Word | -| 0x28 | RX_F1_FreqWord | Rx F1 NCO Frequency Control Word | -| 0x2C | RX_F2_FreqWord | Rx F2 NCO Frequency Control Word | -| 0x30 | LPF_Config_0 |PI Controller Configuration and Low-pass Filter Configuration| -| 0x34 | LPF_Config_1 | PI Controller Configuration Configuration Register 1 | -| 0x38 | Tx_Data_Width | Modem Tx Input Data Width | -| 0x3C | Rx_Data_Width | Modem Rx Output Data Width | -| 0x40 | PRBS_Control | PRBS Control 0 | -| 0x44 |PRBS_Initial_State| PRBS Control 1 | -| 0x48 | PRBS_Polynomial | PRBS Control 2 | -| 0x4C | PRBS_Error_Mask | PRBS Control 3 | -| 0x50 | PRBS_Bit_Count | PRBS Status 0 | -| 0x54 | PRBS_Error_Count | PRBS Status 1 | -| 0x58 | LPF_Accum_F1 | F1 PI Controller Accumulator | -| 0x5C | LPF_Accum_F2 | F2 PI Controller Accumulator | -| 0x60 | axis_xfer_count | MSK Modem Status 3 | -| 0x64 | Rx_Sample_Discard| Rx Sample Discard | -| 0x68 | LPF_Config_2 | PI Controller Configuration Configuration Register 2 | -| 0x6C | f1_nco_adjust | F1 NCO Frequency Adjust | -| 0x70 | f2_nco_adjust | F2 NCO Frequency Adjust | -| 0x74 | f1_error | F1 Error Value | -| 0x78 | f2_error | F2 Error Value | -| 0x7C | Tx_Sync_Ctrl | Transmitter Sync Control | -| 0x80 | Tx_Sync_Cnt | Transmitter Sync Duration | -| 0x84 |lowpass_ema_alpha1| Exponential Moving Average Alpha | -| 0x88 |lowpass_ema_alpha2| Exponential Moving Average Alpha | -| 0x8C | rx_power | Receive Power | +|Offset| Identifier | Name | +|------|-----------------------|-------------------------------------------------------------| +| 0x00 | Hash_ID_Low | Pluto MSK FPGA Hash ID - Lower 32-bits | +| 0x04 | Hash_ID_High | Pluto MSK FPGA Hash ID - Upper 32-bits | +| 0x08 | MSK_Init | MSK Modem Initialization Control | +| 0x0C | MSK_Control | MSK Modem Control | +| 0x10 | MSK_Status | MSK Modem Status 0 | +| 0x14 | Tx_Bit_Count | MSK Modem Status 1 | +| 0x18 | Tx_Enable_Count | MSK Modem Status 2 | +| 0x1C | Fb_FreqWord | Bitrate NCO Frequency Control Word | +| 0x20 | TX_F1_FreqWord | Tx F1 NCO Frequency Control Word | +| 0x24 | TX_F2_FreqWord | Tx F2 NCO Frequency Control Word | +| 0x28 | RX_F1_FreqWord | Rx F1 NCO Frequency Control Word | +| 0x2C | RX_F2_FreqWord | Rx F2 NCO Frequency Control Word | +| 0x30 | LPF_Config_0 |PI Controller Configuration and Low-pass Filter Configuration| +| 0x34 | LPF_Config_1 | PI Controller Configuration Configuration Register 1 | +| 0x38 | Tx_Data_Width | Modem Tx Input Data Width | +| 0x3C | Rx_Data_Width | Modem Rx Output Data Width | +| 0x40 | PRBS_Control | PRBS Control 0 | +| 0x44 | PRBS_Initial_State | PRBS Control 1 | +| 0x48 | PRBS_Polynomial | PRBS Control 2 | +| 0x4C | PRBS_Error_Mask | PRBS Control 3 | +| 0x50 | PRBS_Bit_Count | PRBS Status 0 | +| 0x54 | PRBS_Error_Count | PRBS Status 1 | +| 0x58 | LPF_Accum_F1 | F1 PI Controller Accumulator | +| 0x5C | LPF_Accum_F2 | F2 PI Controller Accumulator | +| 0x60 | axis_xfer_count | MSK Modem Status 3 | +| 0x64 | Rx_Sample_Discard | Rx Sample Discard | +| 0x68 | LPF_Config_2 | PI Controller Configuration Configuration Register 2 | +| 0x6C | f1_nco_adjust | F1 NCO Frequency Adjust | +| 0x70 | f2_nco_adjust | F2 NCO Frequency Adjust | +| 0x74 | f1_error | F1 Error Value | +| 0x78 | f2_error | F2 Error Value | +| 0x7C | Tx_Sync_Ctrl | Transmitter Sync Control | +| 0x80 | Tx_Sync_Cnt | Transmitter Sync Duration | +| 0x84 | lowpass_ema_alpha1 | Exponential Moving Average Alpha | +| 0x88 | lowpass_ema_alpha2 | Exponential Moving Average Alpha | +| 0x8C | rx_power | Receive Power | +| 0x90 |tx_async_fifo_rd_wr_ptr| Tx async FIFO read and write pointers | +| 0x94 |rx_async_fifo_rd_wr_ptr| Rx async FIFO read and write pointers | ### Hash_ID_Low register @@ -765,3 +767,33 @@ signal should be sent after PTT is asserted.

#### rx_power field

Value that represent the RMS power of the incoming I;

+ +### tx_async_fifo_rd_wr_ptr register + +- Absolute Address: 0x90 +- Base Offset: 0x90 +- Size: 0x4 + +|Bits|Identifier| Access |Reset|Name| +|----|----------|--------|-----|----| +|31:0| data |r, ruser| 0x0 | — | + +#### data field + +

Bits 31:16 -> write pointer (12-bits) +Bits 15:00 -> read pointer (12-bits)

+ +### rx_async_fifo_rd_wr_ptr register + +- Absolute Address: 0x94 +- Base Offset: 0x94 +- Size: 0x4 + +|Bits|Identifier| Access |Reset|Name| +|----|----------|--------|-----|----| +|31:0| data |r, ruser| 0x0 | — | + +#### data field + +

Bits 31:16 -> write pointer (12-bits) +Bits 15:00 -> read pointer (12-bits)

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z&qJ-ddy?f%L_(tp1{=Ko{zQ0;?h8a4BjLxp0_pPgiCrehf;tO)0rlyK;E&KE-f`{x$ zKQogDiyw24JKZf=(t1UZ3lIuj-(ha`+tK=gE4?&DVPS4>uUlqU4E}fA1c7P?&`^Md OMTE(@xs`QQ$o~s<=R0Qr diff --git a/rdl/outputs/python/msk_top_regs/reg_model/msk_top_regs.py b/rdl/outputs/python/msk_top_regs/reg_model/msk_top_regs.py index 8ac24d9..e9597a8 100644 --- a/rdl/outputs/python/msk_top_regs/reg_model/msk_top_regs.py +++ b/rdl/outputs/python/msk_top_regs/reg_model/msk_top_regs.py @@ -76,6 +76,312 @@ +class msk_top_regs_data32_desc_7b98a70e_cls(FieldAsyncReadOnly): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Description | .. raw:: html | + | | | + | |

Bits 31:16 -> write pointer (12-bits) Bits 15:00 -> read | + | | pointer (12-bits)

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_desc(self) -> str: + return "Bits 31:16 -\u003e write pointer (12-bits)\nBits 15:00 -\u003e read pointer (12-bits)" + + + + + + +class msk_top_regs_observation_data_data_cf6acbd7_name_8a90eed1_cls(RegAsyncReadOnly): + """ + Class to represent a register in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Rx async FIFO read and write pointers | + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = ['__data'] + + def __init__(self, + address: int, + width: int, + accesswidth: int, + logger_handle: str, + inst_name: str, + parent: Union[AsyncAddressMap,AsyncRegFile,ReadableAsyncMemory]): + + super().__init__(address=address, + width=width, + accesswidth=accesswidth, + logger_handle=logger_handle, + inst_name=inst_name, + parent=parent) + + # build the field attributes + + self.__data:msk_top_regs_data32_desc_7b98a70e_cls = msk_top_regs_data32_desc_7b98a70e_cls( + parent_register=self, + size_props=FieldSizeProps( + width=32, + lsb=0, + msb=31, + low=0, + high=31), + misc_props=FieldMiscProps( + default=0, + is_volatile=True), + logger_handle=logger_handle+'.data', + inst_name='data', + field_type=int) + + @property + def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,FieldAsyncReadWrite]]: + """ + generator that produces has all the fields within the register + """ + yield self.data + + # Empty generator in case there are no children of this type + if False: yield + + + + + # build the properties for the fields + + @property + def data(self) -> msk_top_regs_data32_desc_7b98a70e_cls: + """ + Property to access data field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Description | .. raw:: html | + | | | + | |

Bits 31:16 -> write pointer (12-bits) Bits 15:00 -> read | + | | pointer (12-bits)

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__data + + + @property + def systemrdl_python_child_name_map(self) -> dict[str, str]: + """ + In some cases systemRDL names need to be converted make them python safe, this dictionary + is used to map the original systemRDL names to the names of the python attributes of this + class + + Returns: dictionary whose key is the systemRDL names and value it the property name + """ + return {'data':'data', + } + + + + + + + + + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_data32_desc_7b98a70e_cls: + return super().get_child_by_system_rdl_name(name) + + + + + + + + + + @property + def rdl_name(self) -> str: + return "Rx async FIFO read and write pointers" + + + + + + + +class msk_top_regs_data32_desc_7b98a70e_0x0x1075e913_cls(FieldAsyncReadOnly): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Description | .. raw:: html | + | | | + | |

Bits 31:16 -> write pointer (12-bits) Bits 15:00 -> read | + | | pointer (12-bits)

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_desc(self) -> str: + return "Bits 31:16 -\u003e write pointer (12-bits)\nBits 15:00 -\u003e read pointer (12-bits)" + + + + + + +class msk_top_regs_observation_data_data_cf6acbd7_name_aa4ec676_cls(RegAsyncReadOnly): + """ + Class to represent a register in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Tx async FIFO read and write pointers | + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = ['__data'] + + def __init__(self, + address: int, + width: int, + accesswidth: int, + logger_handle: str, + inst_name: str, + parent: Union[AsyncAddressMap,AsyncRegFile,ReadableAsyncMemory]): + + super().__init__(address=address, + width=width, + accesswidth=accesswidth, + logger_handle=logger_handle, + inst_name=inst_name, + parent=parent) + + # build the field attributes + + self.__data:msk_top_regs_data32_desc_7b98a70e_0x0x1075e913_cls = msk_top_regs_data32_desc_7b98a70e_0x0x1075e913_cls( + parent_register=self, + size_props=FieldSizeProps( + width=32, + lsb=0, + msb=31, + low=0, + high=31), + misc_props=FieldMiscProps( + default=0, + is_volatile=True), + logger_handle=logger_handle+'.data', + inst_name='data', + field_type=int) + + @property + def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,FieldAsyncReadWrite]]: + """ + generator that produces has all the fields within the register + """ + yield self.data + + # Empty generator in case there are no children of this type + if False: yield + + + + + # build the properties for the fields + + @property + def data(self) -> msk_top_regs_data32_desc_7b98a70e_0x0x1075e913_cls: + """ + Property to access data field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Description | .. raw:: html | + | | | + | |

Bits 31:16 -> write pointer (12-bits) Bits 15:00 -> read | + | | pointer (12-bits)

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__data + + + @property + def systemrdl_python_child_name_map(self) -> dict[str, str]: + """ + In some cases systemRDL names need to be converted make them python safe, this dictionary + is used to map the original systemRDL names to the names of the python attributes of this + class + + Returns: dictionary whose key is the systemRDL names and value it the property name + """ + return {'data':'data', + } + + + + + + + + + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_data32_desc_7b98a70e_0x0x1075e913_cls: + return super().get_child_by_system_rdl_name(name) + + + + + + + + + + @property + def rdl_name(self) -> str: + return "Tx async FIFO read and write pointers" + + + + + + + class msk_top_regs_rx_power_rx_power_cls(FieldAsyncReadOnly): """ @@ -414,7 +720,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_lowpass_ema_alpha_alpha_0x0x1065fc05_cls(FieldAsyncReadWrite): +class msk_top_regs_lowpass_ema_alpha_alpha_0x0x1075e9a9_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -452,7 +758,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_lowpass_ema_alpha_0x0x1065fc20_cls(RegAsyncReadWrite): +class msk_top_regs_lowpass_ema_alpha_0x0x1075e9f4_cls(RegAsyncReadWrite): """ Class to represent a register in the register model @@ -489,7 +795,7 @@ def __init__(self, # build the field attributes - self.__alpha:msk_top_regs_lowpass_ema_alpha_alpha_0x0x1065fc05_cls = msk_top_regs_lowpass_ema_alpha_alpha_0x0x1065fc05_cls( + self.__alpha:msk_top_regs_lowpass_ema_alpha_alpha_0x0x1075e9a9_cls = msk_top_regs_lowpass_ema_alpha_alpha_0x0x1075e9a9_cls( parent_register=self, size_props=FieldSizeProps( width=18, @@ -520,7 +826,7 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field # build the properties for the fields @property - def alpha(self) -> msk_top_regs_lowpass_ema_alpha_alpha_0x0x1065fc05_cls: + def alpha(self) -> msk_top_regs_lowpass_ema_alpha_alpha_0x0x1075e9a9_cls: """ Property to access alpha field of the register @@ -559,7 +865,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_lowpass_ema_alpha_alpha_0x0x1065fc05_cls: + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_lowpass_ema_alpha_alpha_0x0x1075e9a9_cls: return super().get_child_by_system_rdl_name(name) @@ -2704,7 +3010,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_stat_32_lpf_acc_status_data_0x0x10647158_cls(FieldAsyncReadOnly): +class msk_top_regs_stat_32_lpf_acc_status_data_0x0x1073cd31_cls(FieldAsyncReadOnly): """ Class to represent a register field in the register model @@ -2779,7 +3085,7 @@ def __init__(self, # build the field attributes - self.__status_data:msk_top_regs_stat_32_lpf_acc_status_data_0x0x10647158_cls = msk_top_regs_stat_32_lpf_acc_status_data_0x0x10647158_cls( + self.__status_data:msk_top_regs_stat_32_lpf_acc_status_data_0x0x1073cd31_cls = msk_top_regs_stat_32_lpf_acc_status_data_0x0x1073cd31_cls( parent_register=self, size_props=FieldSizeProps( width=32, @@ -2810,7 +3116,7 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field # build the properties for the fields @property - def status_data(self) -> msk_top_regs_stat_32_lpf_acc_status_data_0x0x10647158_cls: + def status_data(self) -> msk_top_regs_stat_32_lpf_acc_status_data_0x0x1073cd31_cls: """ Property to access status_data field of the register @@ -2849,7 +3155,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_stat_32_lpf_acc_status_data_0x0x10647158_cls: + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_stat_32_lpf_acc_status_data_0x0x1073cd31_cls: return super().get_child_by_system_rdl_name(name) @@ -4454,7 +4760,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_data_width_data_width_0x0x10645fbf_cls(FieldAsyncReadWrite): +class msk_top_regs_data_width_data_width_0x0x107468c8_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -4530,7 +4836,7 @@ def __init__(self, # build the field attributes - self.__data_width:msk_top_regs_data_width_data_width_0x0x10645fbf_cls = msk_top_regs_data_width_data_width_0x0x10645fbf_cls( + self.__data_width:msk_top_regs_data_width_data_width_0x0x107468c8_cls = msk_top_regs_data_width_data_width_0x0x107468c8_cls( parent_register=self, size_props=FieldSizeProps( width=8, @@ -4561,7 +4867,7 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field # build the properties for the fields @property - def data_width(self) -> msk_top_regs_data_width_data_width_0x0x10645fbf_cls: + def data_width(self) -> msk_top_regs_data_width_data_width_0x0x107468c8_cls: """ Property to access data_width field of the register @@ -4600,7 +4906,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_data_width_data_width_0x0x10645fbf_cls: + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_data_width_data_width_0x0x107468c8_cls: return super().get_child_by_system_rdl_name(name) @@ -5446,7 +5752,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_config_nco_fw_config_data_0x0x1065dd1f_cls(FieldAsyncReadWrite): +class msk_top_regs_config_nco_fw_config_data_0x0x1074bb14_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -5523,7 +5829,7 @@ def __init__(self, # build the field attributes - self.__config_data:msk_top_regs_config_nco_fw_config_data_0x0x1065dd1f_cls = msk_top_regs_config_nco_fw_config_data_0x0x1065dd1f_cls( + self.__config_data:msk_top_regs_config_nco_fw_config_data_0x0x1074bb14_cls = msk_top_regs_config_nco_fw_config_data_0x0x1074bb14_cls( parent_register=self, size_props=FieldSizeProps( width=32, @@ -5554,7 +5860,7 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field # build the properties for the fields @property - def config_data(self) -> msk_top_regs_config_nco_fw_config_data_0x0x1065dd1f_cls: + def config_data(self) -> msk_top_regs_config_nco_fw_config_data_0x0x1074bb14_cls: """ Property to access config_data field of the register @@ -5595,7 +5901,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_config_nco_fw_config_data_0x0x1065dd1f_cls: + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_config_nco_fw_config_data_0x0x1074bb14_cls: return super().get_child_by_system_rdl_name(name) @@ -5619,7 +5925,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_config_nco_fw_config_data_0x0x1065de03_cls(FieldAsyncReadWrite): +class msk_top_regs_config_nco_fw_config_data_0x0x107566c9_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -5696,7 +6002,7 @@ def __init__(self, # build the field attributes - self.__config_data:msk_top_regs_config_nco_fw_config_data_0x0x1065de03_cls = msk_top_regs_config_nco_fw_config_data_0x0x1065de03_cls( + self.__config_data:msk_top_regs_config_nco_fw_config_data_0x0x107566c9_cls = msk_top_regs_config_nco_fw_config_data_0x0x107566c9_cls( parent_register=self, size_props=FieldSizeProps( width=32, @@ -5727,7 +6033,7 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field # build the properties for the fields @property - def config_data(self) -> msk_top_regs_config_nco_fw_config_data_0x0x1065de03_cls: + def config_data(self) -> msk_top_regs_config_nco_fw_config_data_0x0x107566c9_cls: """ Property to access config_data field of the register @@ -5768,7 +6074,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_config_nco_fw_config_data_0x0x1065de03_cls: + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_config_nco_fw_config_data_0x0x107566c9_cls: return super().get_child_by_system_rdl_name(name) @@ -5792,7 +6098,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_config_nco_fw_config_data_0x0x1065df17_cls(FieldAsyncReadWrite): +class msk_top_regs_config_nco_fw_config_data_0x0x10756468_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -5869,7 +6175,7 @@ def __init__(self, # build the field attributes - self.__config_data:msk_top_regs_config_nco_fw_config_data_0x0x1065df17_cls = msk_top_regs_config_nco_fw_config_data_0x0x1065df17_cls( + self.__config_data:msk_top_regs_config_nco_fw_config_data_0x0x10756468_cls = msk_top_regs_config_nco_fw_config_data_0x0x10756468_cls( parent_register=self, size_props=FieldSizeProps( width=32, @@ -5900,7 +6206,7 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field # build the properties for the fields @property - def config_data(self) -> msk_top_regs_config_nco_fw_config_data_0x0x1065df17_cls: + def config_data(self) -> msk_top_regs_config_nco_fw_config_data_0x0x10756468_cls: """ Property to access config_data field of the register @@ -5941,7 +6247,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_config_nco_fw_config_data_0x0x1065df17_cls: + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_config_nco_fw_config_data_0x0x10756468_cls: return super().get_child_by_system_rdl_name(name) @@ -5965,7 +6271,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_config_nco_fw_config_data_0x0x1065e8ef_cls(FieldAsyncReadWrite): +class msk_top_regs_config_nco_fw_config_data_0x0x1075c880_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -6042,7 +6348,7 @@ def __init__(self, # build the field attributes - self.__config_data:msk_top_regs_config_nco_fw_config_data_0x0x1065e8ef_cls = msk_top_regs_config_nco_fw_config_data_0x0x1065e8ef_cls( + self.__config_data:msk_top_regs_config_nco_fw_config_data_0x0x1075c880_cls = msk_top_regs_config_nco_fw_config_data_0x0x1075c880_cls( parent_register=self, size_props=FieldSizeProps( width=32, @@ -6073,7 +6379,7 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field # build the properties for the fields @property - def config_data(self) -> msk_top_regs_config_nco_fw_config_data_0x0x1065e8ef_cls: + def config_data(self) -> msk_top_regs_config_nco_fw_config_data_0x0x1075c880_cls: """ Property to access config_data field of the register @@ -6114,7 +6420,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_config_nco_fw_config_data_0x0x1065e8ef_cls: + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_config_nco_fw_config_data_0x0x1075c880_cls: return super().get_child_by_system_rdl_name(name) @@ -8047,7 +8353,7 @@ class msk_top_regs_cls(AsyncAddressMap): +--------------+-------------------------------------------------------------------------+ """ - __slots__ : list[str] = ['__Hash_ID_Low', '__Hash_ID_High', '__MSK_Init', '__MSK_Control', '__MSK_Status', '__Tx_Bit_Count', '__Tx_Enable_Count', '__Fb_FreqWord', '__TX_F1_FreqWord', '__TX_F2_FreqWord', '__RX_F1_FreqWord', '__RX_F2_FreqWord', '__LPF_Config_0', '__LPF_Config_1', '__Tx_Data_Width', '__Rx_Data_Width', '__PRBS_Control', '__PRBS_Initial_State', '__PRBS_Polynomial', '__PRBS_Error_Mask', '__PRBS_Bit_Count', '__PRBS_Error_Count', '__LPF_Accum_F1', '__LPF_Accum_F2', '__axis_xfer_count', '__Rx_Sample_Discard', '__LPF_Config_2', '__f1_nco_adjust', '__f2_nco_adjust', '__f1_error', '__f2_error', '__Tx_Sync_Ctrl', '__Tx_Sync_Cnt', '__lowpass_ema_alpha1', '__lowpass_ema_alpha2', '__rx_power'] + __slots__ : list[str] = ['__Hash_ID_Low', '__Hash_ID_High', '__MSK_Init', '__MSK_Control', '__MSK_Status', '__Tx_Bit_Count', '__Tx_Enable_Count', '__Fb_FreqWord', '__TX_F1_FreqWord', '__TX_F2_FreqWord', '__RX_F1_FreqWord', '__RX_F2_FreqWord', '__LPF_Config_0', '__LPF_Config_1', '__Tx_Data_Width', '__Rx_Data_Width', '__PRBS_Control', '__PRBS_Initial_State', '__PRBS_Polynomial', '__PRBS_Error_Mask', '__PRBS_Bit_Count', '__PRBS_Error_Count', '__LPF_Accum_F1', '__LPF_Accum_F2', '__axis_xfer_count', '__Rx_Sample_Discard', '__LPF_Config_2', '__f1_nco_adjust', '__f2_nco_adjust', '__f1_error', '__f2_error', '__Tx_Sync_Ctrl', '__Tx_Sync_Cnt', '__lowpass_ema_alpha1', '__lowpass_ema_alpha2', '__rx_power', '__tx_async_fifo_rd_wr_ptr', '__rx_async_fifo_rd_wr_ptr'] def __init__(self, *, address:int=0, @@ -8332,7 +8638,7 @@ def __init__(self, *, inst_name='Tx_Sync_Cnt', parent=self) - self.__lowpass_ema_alpha1:msk_top_regs_lowpass_ema_alpha_0x0x1065fc20_cls = msk_top_regs_lowpass_ema_alpha_0x0x1065fc20_cls( + self.__lowpass_ema_alpha1:msk_top_regs_lowpass_ema_alpha_0x0x1075e9f4_cls = msk_top_regs_lowpass_ema_alpha_0x0x1075e9f4_cls( address=self.address+132, accesswidth=32, width=32, @@ -8355,10 +8661,26 @@ def __init__(self, *, logger_handle=logger_handle+'.rx_power', inst_name='rx_power', parent=self) + + self.__tx_async_fifo_rd_wr_ptr:msk_top_regs_observation_data_data_cf6acbd7_name_aa4ec676_cls = msk_top_regs_observation_data_data_cf6acbd7_name_aa4ec676_cls( + address=self.address+144, + accesswidth=32, + width=32, + logger_handle=logger_handle+'.tx_async_fifo_rd_wr_ptr', + inst_name='tx_async_fifo_rd_wr_ptr', parent=self) + + + self.__rx_async_fifo_rd_wr_ptr:msk_top_regs_observation_data_data_cf6acbd7_name_8a90eed1_cls = msk_top_regs_observation_data_data_cf6acbd7_name_8a90eed1_cls( + address=self.address+148, + accesswidth=32, + width=32, + logger_handle=logger_handle+'.rx_async_fifo_rd_wr_ptr', + inst_name='rx_async_fifo_rd_wr_ptr', parent=self) + @property def size(self) -> int: - return 144 + return 152 @property def Hash_ID_Low(self) -> msk_top_regs_msk_hash_lo_cls: """ @@ -9018,7 +9340,7 @@ def Tx_Sync_Cnt(self) -> msk_top_regs_tx_sync_cnt_cls: return self.__Tx_Sync_Cnt @property - def lowpass_ema_alpha1(self) -> msk_top_regs_lowpass_ema_alpha_0x0x1065fc20_cls: + def lowpass_ema_alpha1(self) -> msk_top_regs_lowpass_ema_alpha_0x0x1075e9f4_cls: """ Property to access lowpass_ema_alpha1 @@ -9077,6 +9399,38 @@ def rx_power(self) -> msk_top_regs_rx_power_cls: """ return self.__rx_power + @property + def tx_async_fifo_rd_wr_ptr(self) -> msk_top_regs_observation_data_data_cf6acbd7_name_aa4ec676_cls: + """ + Property to access tx_async_fifo_rd_wr_ptr + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Tx async FIFO read and write pointers | + +--------------+-------------------------------------------------------------------------+ + """ + return self.__tx_async_fifo_rd_wr_ptr + + @property + def rx_async_fifo_rd_wr_ptr(self) -> msk_top_regs_observation_data_data_cf6acbd7_name_8a90eed1_cls: + """ + Property to access rx_async_fifo_rd_wr_ptr + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Rx async FIFO read and write pointers | + +--------------+-------------------------------------------------------------------------+ + """ + return self.__rx_async_fifo_rd_wr_ptr + @property @@ -9088,7 +9442,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: Returns: dictionary whose key is the systemRDL names and value it the property name """ - return {'Hash_ID_Low':'Hash_ID_Low','Hash_ID_High':'Hash_ID_High','MSK_Init':'MSK_Init','MSK_Control':'MSK_Control','MSK_Status':'MSK_Status','Tx_Bit_Count':'Tx_Bit_Count','Tx_Enable_Count':'Tx_Enable_Count','Fb_FreqWord':'Fb_FreqWord','TX_F1_FreqWord':'TX_F1_FreqWord','TX_F2_FreqWord':'TX_F2_FreqWord','RX_F1_FreqWord':'RX_F1_FreqWord','RX_F2_FreqWord':'RX_F2_FreqWord','LPF_Config_0':'LPF_Config_0','LPF_Config_1':'LPF_Config_1','Tx_Data_Width':'Tx_Data_Width','Rx_Data_Width':'Rx_Data_Width','PRBS_Control':'PRBS_Control','PRBS_Initial_State':'PRBS_Initial_State','PRBS_Polynomial':'PRBS_Polynomial','PRBS_Error_Mask':'PRBS_Error_Mask','PRBS_Bit_Count':'PRBS_Bit_Count','PRBS_Error_Count':'PRBS_Error_Count','LPF_Accum_F1':'LPF_Accum_F1','LPF_Accum_F2':'LPF_Accum_F2','axis_xfer_count':'axis_xfer_count','Rx_Sample_Discard':'Rx_Sample_Discard','LPF_Config_2':'LPF_Config_2','f1_nco_adjust':'f1_nco_adjust','f2_nco_adjust':'f2_nco_adjust','f1_error':'f1_error','f2_error':'f2_error','Tx_Sync_Ctrl':'Tx_Sync_Ctrl','Tx_Sync_Cnt':'Tx_Sync_Cnt','lowpass_ema_alpha1':'lowpass_ema_alpha1','lowpass_ema_alpha2':'lowpass_ema_alpha2','rx_power':'rx_power', + return {'Hash_ID_Low':'Hash_ID_Low','Hash_ID_High':'Hash_ID_High','MSK_Init':'MSK_Init','MSK_Control':'MSK_Control','MSK_Status':'MSK_Status','Tx_Bit_Count':'Tx_Bit_Count','Tx_Enable_Count':'Tx_Enable_Count','Fb_FreqWord':'Fb_FreqWord','TX_F1_FreqWord':'TX_F1_FreqWord','TX_F2_FreqWord':'TX_F2_FreqWord','RX_F1_FreqWord':'RX_F1_FreqWord','RX_F2_FreqWord':'RX_F2_FreqWord','LPF_Config_0':'LPF_Config_0','LPF_Config_1':'LPF_Config_1','Tx_Data_Width':'Tx_Data_Width','Rx_Data_Width':'Rx_Data_Width','PRBS_Control':'PRBS_Control','PRBS_Initial_State':'PRBS_Initial_State','PRBS_Polynomial':'PRBS_Polynomial','PRBS_Error_Mask':'PRBS_Error_Mask','PRBS_Bit_Count':'PRBS_Bit_Count','PRBS_Error_Count':'PRBS_Error_Count','LPF_Accum_F1':'LPF_Accum_F1','LPF_Accum_F2':'LPF_Accum_F2','axis_xfer_count':'axis_xfer_count','Rx_Sample_Discard':'Rx_Sample_Discard','LPF_Config_2':'LPF_Config_2','f1_nco_adjust':'f1_nco_adjust','f2_nco_adjust':'f2_nco_adjust','f1_error':'f1_error','f2_error':'f2_error','Tx_Sync_Ctrl':'Tx_Sync_Ctrl','Tx_Sync_Cnt':'Tx_Sync_Cnt','lowpass_ema_alpha1':'lowpass_ema_alpha1','lowpass_ema_alpha2':'lowpass_ema_alpha2','rx_power':'rx_power','tx_async_fifo_rd_wr_ptr':'tx_async_fifo_rd_wr_ptr','rx_async_fifo_rd_wr_ptr':'rx_async_fifo_rd_wr_ptr', } @@ -9097,7 +9451,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - # nodes:36 + # nodes:38 @overload def get_child_by_system_rdl_name(self, name: Literal["Hash_ID_Low"]) -> msk_top_regs_msk_hash_lo_cls: ... @@ -9232,7 +9586,7 @@ def get_child_by_system_rdl_name(self, name: Literal["Tx_Sync_Cnt"]) -> msk_top_ @overload - def get_child_by_system_rdl_name(self, name: Literal["lowpass_ema_alpha1"]) -> msk_top_regs_lowpass_ema_alpha_0x0x1065fc20_cls: ... + def get_child_by_system_rdl_name(self, name: Literal["lowpass_ema_alpha1"]) -> msk_top_regs_lowpass_ema_alpha_0x0x1075e9f4_cls: ... @overload @@ -9242,9 +9596,17 @@ def get_child_by_system_rdl_name(self, name: Literal["lowpass_ema_alpha2"]) -> m @overload def get_child_by_system_rdl_name(self, name: Literal["rx_power"]) -> msk_top_regs_rx_power_cls: ... + + @overload + def get_child_by_system_rdl_name(self, name: Literal["tx_async_fifo_rd_wr_ptr"]) -> msk_top_regs_observation_data_data_cf6acbd7_name_aa4ec676_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["rx_async_fifo_rd_wr_ptr"]) -> msk_top_regs_observation_data_data_cf6acbd7_name_8a90eed1_cls: ... + @overload - def get_child_by_system_rdl_name(self, name: str) -> Union[msk_top_regs_msk_hash_lo_cls, msk_top_regs_msk_hash_hi_cls, msk_top_regs_msk_init_cls, msk_top_regs_msk_ctrl_cls, msk_top_regs_msk_stat_0_cls, msk_top_regs_msk_stat_1_cls, msk_top_regs_msk_stat_2_cls, msk_top_regs_config_nco_fw_desc_c4924cc6_name_0c494469_cls, msk_top_regs_config_nco_fw_desc_94d7aaf5_name_84dd0c1c_cls, msk_top_regs_config_nco_fw_desc_42134a4f_name_d97dbd51_cls, msk_top_regs_config_nco_fw_desc_16fb48c8_name_8d01a20d_cls, msk_top_regs_config_nco_fw_desc_43c0828f_name_bdc60ecf_cls, msk_top_regs_lpf_config_0_cls, msk_top_regs_lpf_config_1_cls, msk_top_regs_data_width_desc_58c848dd_name_2fbd8eba_cls, msk_top_regs_data_width_desc_6097df38_name_4609588b_cls, msk_top_regs_prbs_ctrl_cls, msk_top_regs_config_prbs_seed_cls, msk_top_regs_config_prbs_poly_cls, msk_top_regs_config_prbs_errmask_cls, msk_top_regs_stat_32_bits_cls, msk_top_regs_stat_32_errs_cls, msk_top_regs_stat_32_lpf_acc_desc_8cebc7dc_name_f20c6670_cls, msk_top_regs_stat_32_lpf_acc_desc_dea6bd99_name_758fd0ce_cls, msk_top_regs_msk_stat_3_cls, msk_top_regs_rx_sample_discard_cls, msk_top_regs_lpf_config_2_cls, msk_top_regs_observation_data_data_0c017ef4_desc_64ff3689_name_d8ad3b25_cls, msk_top_regs_observation_data_data_0515efaa_desc_ebde6d39_name_2c154788_cls, msk_top_regs_observation_data_data_25a21249_desc_417e1c96_name_3b640507_cls, msk_top_regs_observation_data_data_272a00b6_desc_70869502_name_3de9a0d3_cls, msk_top_regs_tx_sync_ctrl_cls, msk_top_regs_tx_sync_cnt_cls, msk_top_regs_lowpass_ema_alpha_0x0x1065fc20_cls, msk_top_regs_lowpass_ema_alpha_cls, msk_top_regs_rx_power_cls, ]: ... + def get_child_by_system_rdl_name(self, name: str) -> Union[msk_top_regs_msk_hash_lo_cls, msk_top_regs_msk_hash_hi_cls, msk_top_regs_msk_init_cls, msk_top_regs_msk_ctrl_cls, msk_top_regs_msk_stat_0_cls, msk_top_regs_msk_stat_1_cls, msk_top_regs_msk_stat_2_cls, msk_top_regs_config_nco_fw_desc_c4924cc6_name_0c494469_cls, msk_top_regs_config_nco_fw_desc_94d7aaf5_name_84dd0c1c_cls, msk_top_regs_config_nco_fw_desc_42134a4f_name_d97dbd51_cls, msk_top_regs_config_nco_fw_desc_16fb48c8_name_8d01a20d_cls, msk_top_regs_config_nco_fw_desc_43c0828f_name_bdc60ecf_cls, msk_top_regs_lpf_config_0_cls, msk_top_regs_lpf_config_1_cls, msk_top_regs_data_width_desc_58c848dd_name_2fbd8eba_cls, msk_top_regs_data_width_desc_6097df38_name_4609588b_cls, msk_top_regs_prbs_ctrl_cls, msk_top_regs_config_prbs_seed_cls, msk_top_regs_config_prbs_poly_cls, msk_top_regs_config_prbs_errmask_cls, msk_top_regs_stat_32_bits_cls, msk_top_regs_stat_32_errs_cls, msk_top_regs_stat_32_lpf_acc_desc_8cebc7dc_name_f20c6670_cls, msk_top_regs_stat_32_lpf_acc_desc_dea6bd99_name_758fd0ce_cls, msk_top_regs_msk_stat_3_cls, msk_top_regs_rx_sample_discard_cls, msk_top_regs_lpf_config_2_cls, msk_top_regs_observation_data_data_0c017ef4_desc_64ff3689_name_d8ad3b25_cls, msk_top_regs_observation_data_data_0515efaa_desc_ebde6d39_name_2c154788_cls, msk_top_regs_observation_data_data_25a21249_desc_417e1c96_name_3b640507_cls, msk_top_regs_observation_data_data_272a00b6_desc_70869502_name_3de9a0d3_cls, msk_top_regs_tx_sync_ctrl_cls, msk_top_regs_tx_sync_cnt_cls, msk_top_regs_lowpass_ema_alpha_0x0x1075e9f4_cls, msk_top_regs_lowpass_ema_alpha_cls, msk_top_regs_rx_power_cls, msk_top_regs_observation_data_data_cf6acbd7_name_aa4ec676_cls, msk_top_regs_observation_data_data_cf6acbd7_name_8a90eed1_cls, ]: ... def get_child_by_system_rdl_name(self, name: Any) -> Any: return super().get_child_by_system_rdl_name(name) @@ -9379,6 +9741,12 @@ def get_registers(self, unroll:bool=False) -> Iterator[Union[AsyncReg, AsyncRegA yield self.rx_power + + yield self.tx_async_fifo_rd_wr_ptr + + + yield self.rx_async_fifo_rd_wr_ptr + # Empty generator in case there are no children of this type if False: yield diff --git a/rdl/outputs/python/msk_top_regs/sim/msk_top_regs.py b/rdl/outputs/python/msk_top_regs/sim/msk_top_regs.py index 95e0aa1..0b442a7 100644 --- a/rdl/outputs/python/msk_top_regs/sim/msk_top_regs.py +++ b/rdl/outputs/python/msk_top_regs/sim/msk_top_regs.py @@ -165,6 +165,14 @@ def _build_registers(self) -> dict[int, Union[list[Union[MemoryRegister, Registe Register(width=32, full_inst_name='msk_top_regs.rx_power', readable=True, writable=False, fields=[FieldDefinition(high=22, low=0, msb=22, lsb=0, inst_name='rx_power'), ]), + 144 : + Register(width=32, full_inst_name='msk_top_regs.tx_async_fifo_rd_wr_ptr', readable=True, writable=False, + fields=[FieldDefinition(high=31, low=0, msb=31, lsb=0, inst_name='data'), + ]), + 148 : + Register(width=32, full_inst_name='msk_top_regs.rx_async_fifo_rd_wr_ptr', readable=True, writable=False, + fields=[FieldDefinition(high=31, low=0, msb=31, lsb=0, inst_name='data'), + ]), } def _build_memories(self) -> list[MemoryEntry]: diff --git a/rdl/outputs/python/msk_top_regs/tests/test_msk_top_regs.py b/rdl/outputs/python/msk_top_regs/tests/test_msk_top_regs.py index 9241d51..2b9468e 100644 --- a/rdl/outputs/python/msk_top_regs/tests/test_msk_top_regs.py +++ b/rdl/outputs/python/msk_top_regs/tests/test_msk_top_regs.py @@ -164,6 +164,12 @@ def test_inst_name(self) -> None: with self.subTest(msg='node: msk_top_regs.rx_power'): self.assertEqual(self.dut.rx_power.inst_name, 'rx_power') # type: ignore[union-attr] self.assertEqual(self.dut.rx_power.full_inst_name, 'msk_top_regs.rx_power') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.tx_async_fifo_rd_wr_ptr'): + self.assertEqual(self.dut.tx_async_fifo_rd_wr_ptr.inst_name, 'tx_async_fifo_rd_wr_ptr') # type: ignore[union-attr] + self.assertEqual(self.dut.tx_async_fifo_rd_wr_ptr.full_inst_name, 'msk_top_regs.tx_async_fifo_rd_wr_ptr') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.rx_async_fifo_rd_wr_ptr'): + self.assertEqual(self.dut.rx_async_fifo_rd_wr_ptr.inst_name, 'rx_async_fifo_rd_wr_ptr') # type: ignore[union-attr] + self.assertEqual(self.dut.rx_async_fifo_rd_wr_ptr.full_inst_name, 'msk_top_regs.rx_async_fifo_rd_wr_ptr') # type: ignore[union-attr] with self.subTest(msg='node: msk_top_regs.Hash_ID_Low.hash_id_lo'): self.assertEqual(self.dut.Hash_ID_Low.hash_id_lo.inst_name, 'hash_id_lo') # type: ignore[union-attr] self.assertEqual(self.dut.Hash_ID_Low.hash_id_lo.full_inst_name, 'msk_top_regs.Hash_ID_Low.hash_id_lo') # type: ignore[union-attr] @@ -341,6 +347,12 @@ def test_inst_name(self) -> None: with self.subTest(msg='node: msk_top_regs.rx_power.rx_power'): self.assertEqual(self.dut.rx_power.rx_power.inst_name, 'rx_power') # type: ignore[union-attr] self.assertEqual(self.dut.rx_power.rx_power.full_inst_name, 'msk_top_regs.rx_power.rx_power') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.tx_async_fifo_rd_wr_ptr.data'): + self.assertEqual(self.dut.tx_async_fifo_rd_wr_ptr.data.inst_name, 'data') # type: ignore[union-attr] + self.assertEqual(self.dut.tx_async_fifo_rd_wr_ptr.data.full_inst_name, 'msk_top_regs.tx_async_fifo_rd_wr_ptr.data') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.rx_async_fifo_rd_wr_ptr.data'): + self.assertEqual(self.dut.rx_async_fifo_rd_wr_ptr.data.inst_name, 'data') # type: ignore[union-attr] + self.assertEqual(self.dut.rx_async_fifo_rd_wr_ptr.data.full_inst_name, 'msk_top_regs.rx_async_fifo_rd_wr_ptr.data') # type: ignore[union-attr] def test_name_property(self) -> None: @@ -599,6 +611,20 @@ def test_name_property(self) -> None: + with self.subTest(msg='node: msk_top_regs.tx_async_fifo_rd_wr_ptr'): + + + self.assertEqual(self.dut.tx_async_fifo_rd_wr_ptr.rdl_name, "Tx async FIFO read and write pointers") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.rx_async_fifo_rd_wr_ptr'): + + + self.assertEqual(self.dut.rx_async_fifo_rd_wr_ptr.rdl_name, "Rx async FIFO read and write pointers") # type: ignore[union-attr] + + + with self.subTest(msg='node: msk_top_regs.Hash_ID_Low.hash_id_lo'): @@ -1012,6 +1038,20 @@ def test_name_property(self) -> None: + with self.subTest(msg='node: msk_top_regs.tx_async_fifo_rd_wr_ptr.data'): + + + self.assertIsNone(self.dut.tx_async_fifo_rd_wr_ptr.data.rdl_name) # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.rx_async_fifo_rd_wr_ptr.data'): + + + self.assertIsNone(self.dut.rx_async_fifo_rd_wr_ptr.data.rdl_name) # type: ignore[union-attr] + + + def test_desc(self) -> None: @@ -1270,6 +1310,20 @@ def test_desc(self) -> None: + with self.subTest(msg='node: msk_top_regs.tx_async_fifo_rd_wr_ptr'): + + + self.assertIsNone(self.dut.tx_async_fifo_rd_wr_ptr.rdl_desc) # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.rx_async_fifo_rd_wr_ptr'): + + + self.assertIsNone(self.dut.rx_async_fifo_rd_wr_ptr.rdl_desc) # type: ignore[union-attr] + + + with self.subTest(msg='node: msk_top_regs.Hash_ID_Low.hash_id_lo'): @@ -1683,6 +1737,20 @@ def test_desc(self) -> None: + with self.subTest(msg='node: msk_top_regs.tx_async_fifo_rd_wr_ptr.data'): + + + self.assertEqual(self.dut.tx_async_fifo_rd_wr_ptr.data.rdl_desc, "Bits 31:16 -\u003e write pointer (12-bits)\nBits 15:00 -\u003e read pointer (12-bits)") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.rx_async_fifo_rd_wr_ptr.data'): + + + self.assertEqual(self.dut.rx_async_fifo_rd_wr_ptr.data.rdl_desc, "Bits 31:16 -\u003e write pointer (12-bits)\nBits 15:00 -\u003e read pointer (12-bits)") # type: ignore[union-attr] + + + def test_sizes(self) -> None: @@ -1761,12 +1829,16 @@ def test_sizes(self) -> None: self.assertEqual(self.dut.lowpass_ema_alpha2.size, 4) # type: ignore[union-attr] with self.subTest(msg='node: msk_top_regs.rx_power'): self.assertEqual(self.dut.rx_power.size, 4) # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.tx_async_fifo_rd_wr_ptr'): + self.assertEqual(self.dut.tx_async_fifo_rd_wr_ptr.size, 4) # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.rx_async_fifo_rd_wr_ptr'): + self.assertEqual(self.dut.rx_async_fifo_rd_wr_ptr.size, 4) # type: ignore[union-attr] # check the size of the address map itself with self.subTest(msg='node: msk_top_regs'): - self.assertEqual(self.dut.size, 144) # type: ignore[union-attr] + self.assertEqual(self.dut.size, 152) # type: ignore[union-attr] @@ -1955,6 +2027,16 @@ def test_register_properties(self) -> None: self.assertEqual(self.dut.rx_power.width, 32) # type: ignore[union-attr] self.assertEqual(self.dut.rx_power.size, 4) # type: ignore[union-attr] self.assertEqual(self.dut.rx_power.accesswidth, 32) # type: ignore[union-attr] + with self.subTest(msg='register: msk_top_regs.tx_async_fifo_rd_wr_ptr'): + self.assertEqual(self.dut.tx_async_fifo_rd_wr_ptr.address, 144) # type: ignore[union-attr] + self.assertEqual(self.dut.tx_async_fifo_rd_wr_ptr.width, 32) # type: ignore[union-attr] + self.assertEqual(self.dut.tx_async_fifo_rd_wr_ptr.size, 4) # type: ignore[union-attr] + self.assertEqual(self.dut.tx_async_fifo_rd_wr_ptr.accesswidth, 32) # type: ignore[union-attr] + with self.subTest(msg='register: msk_top_regs.rx_async_fifo_rd_wr_ptr'): + self.assertEqual(self.dut.rx_async_fifo_rd_wr_ptr.address, 148) # type: ignore[union-attr] + self.assertEqual(self.dut.rx_async_fifo_rd_wr_ptr.width, 32) # type: ignore[union-attr] + self.assertEqual(self.dut.rx_async_fifo_rd_wr_ptr.size, 4) # type: ignore[union-attr] + self.assertEqual(self.dut.rx_async_fifo_rd_wr_ptr.accesswidth, 32) # type: ignore[union-attr] def test_memory_properties(self) -> None: @@ -2916,6 +2998,38 @@ def test_field_properties(self) -> None: self.assertEqual(fut.default,0) self.assertEqual(fut.is_volatile,True) + with self.subTest(msg='field: msk_top_regs.tx_async_fifo_rd_wr_ptr.data'): + # test properties of field: msk_top_regs.tx_async_fifo_rd_wr_ptr.data + fut = self.dut.tx_async_fifo_rd_wr_ptr.data # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,0) + self.assertEqual(fut.msb,31) + self.assertEqual(fut.low,0) + self.assertEqual(fut.high,31) + self.assertEqual(fut.bitmask,0xFFFFFFFF) + self.assertEqual(fut.inverse_bitmask,0x0) + self.assertEqual(fut.max_value,0xFFFFFFFF) + + self.assertEqual(fut.default,0) + + self.assertEqual(fut.is_volatile,True) + with self.subTest(msg='field: msk_top_regs.rx_async_fifo_rd_wr_ptr.data'): + # test properties of field: msk_top_regs.rx_async_fifo_rd_wr_ptr.data + fut = self.dut.rx_async_fifo_rd_wr_ptr.data # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,0) + self.assertEqual(fut.msb,31) + self.assertEqual(fut.low,0) + self.assertEqual(fut.high,31) + self.assertEqual(fut.bitmask,0xFFFFFFFF) + self.assertEqual(fut.inverse_bitmask,0x0) + self.assertEqual(fut.max_value,0xFFFFFFFF) + + self.assertEqual(fut.default,0) + + self.assertEqual(fut.is_volatile,True) def test_field_encoding_properties(self) -> None: @@ -2979,6 +3093,8 @@ def test_field_encoding_properties(self) -> None: + + @@ -3131,6 +3247,14 @@ def test_user_defined_properties(self) -> None: self.assertDictEqual(self.dut.rx_power.udp,{}) + with self.subTest(msg='register: msk_top_regs.tx_async_fifo_rd_wr_ptr'): + + self.assertDictEqual(self.dut.tx_async_fifo_rd_wr_ptr.udp,{}) + + with self.subTest(msg='register: msk_top_regs.rx_async_fifo_rd_wr_ptr'): + + self.assertDictEqual(self.dut.rx_async_fifo_rd_wr_ptr.udp,{}) + with self.subTest(msg='register: msk_top_regs.Hash_ID_Low.hash_id_lo'): self.assertDictEqual(self.dut.Hash_ID_Low.hash_id_lo.udp,{}) @@ -3367,6 +3491,14 @@ def test_user_defined_properties(self) -> None: self.assertDictEqual(self.dut.rx_power.rx_power.udp,{}) + with self.subTest(msg='register: msk_top_regs.tx_async_fifo_rd_wr_ptr.data'): + + self.assertDictEqual(self.dut.tx_async_fifo_rd_wr_ptr.data.udp,{}) + + with self.subTest(msg='register: msk_top_regs.rx_async_fifo_rd_wr_ptr.data'): + + self.assertDictEqual(self.dut.rx_async_fifo_rd_wr_ptr.data.udp,{}) + async def test_register_read_and_write(self) -> None: @@ -6170,6 +6302,122 @@ async def test_register_read_and_write(self) -> None: + # test that a non-writable register has no write method and attempting one generates and error + with self.assertRaises(AttributeError): + await rut.write(0) # type: ignore[attr-defined] + + # check the read has not been called in the write test + read_callback_mock.assert_not_called() + # test access operations (read and/or write) to register: + # msk_top_regs.tx_async_fifo_rd_wr_ptr + with self.subTest(msg='register: msk_top_regs.tx_async_fifo_rd_wr_ptr'): + rut=self.dut.tx_async_fifo_rd_wr_ptr # type: ignore[union-attr,assignment] + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=1) as read_callback_mock: + + + if not isinstance(rut, (RegAsyncReadOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Readable Async Type') + + # test reading back 1 (the unpatched version returns 0 so this confirms the patch works) + self.assertEqual(await rut.read(), 1) + read_callback_mock.assert_called_once_with( + addr=144, + width=32, + accesswidth=rut.accesswidth) + + # test the read check with high value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await rut.read(), 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=144, + width=32, + accesswidth=rut.accesswidth) + + # test the read of the low value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0 + self.assertEqual(await rut.read(), 0x0) + read_callback_mock.assert_called_once_with( + addr=144, + width=32, + accesswidth=rut.accesswidth) + + # test the read of a random value + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.reset_mock() + read_callback_mock.return_value = random_value + self.assertEqual(await rut.read(), random_value) + read_callback_mock.assert_called_once_with( + addr=144, + width=32, + accesswidth=rut.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + + + # test that a non-writable register has no write method and attempting one generates and error + with self.assertRaises(AttributeError): + await rut.write(0) # type: ignore[attr-defined] + + # check the read has not been called in the write test + read_callback_mock.assert_not_called() + # test access operations (read and/or write) to register: + # msk_top_regs.rx_async_fifo_rd_wr_ptr + with self.subTest(msg='register: msk_top_regs.rx_async_fifo_rd_wr_ptr'): + rut=self.dut.rx_async_fifo_rd_wr_ptr # type: ignore[union-attr,assignment] + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=1) as read_callback_mock: + + + if not isinstance(rut, (RegAsyncReadOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Readable Async Type') + + # test reading back 1 (the unpatched version returns 0 so this confirms the patch works) + self.assertEqual(await rut.read(), 1) + read_callback_mock.assert_called_once_with( + addr=148, + width=32, + accesswidth=rut.accesswidth) + + # test the read check with high value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await rut.read(), 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=148, + width=32, + accesswidth=rut.accesswidth) + + # test the read of the low value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0 + self.assertEqual(await rut.read(), 0x0) + read_callback_mock.assert_called_once_with( + addr=148, + width=32, + accesswidth=rut.accesswidth) + + # test the read of a random value + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.reset_mock() + read_callback_mock.return_value = random_value + self.assertEqual(await rut.read(), random_value) + read_callback_mock.assert_called_once_with( + addr=148, + width=32, + accesswidth=rut.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + + # test that a non-writable register has no write method and attempting one generates and error with self.assertRaises(AttributeError): await rut.write(0) # type: ignore[attr-defined] @@ -10344,6 +10592,102 @@ async def test_int_field_read_and_write(self) -> None: read_callback_mock.reset_mock() write_callback_mock.assert_not_called() + # test access operations (read and/or write) to field: + # msk_top_regs.tx_async_fifo_rd_wr_ptr.data + with self.subTest(msg='field: msk_top_regs.tx_async_fifo_rd_wr_ptr.data'): + fut = self.dut.tx_async_fifo_rd_wr_ptr.data # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0x0 + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=144, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await fut.read(), + 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=144, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=144, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + # test access operations (read and/or write) to field: + # msk_top_regs.rx_async_fifo_rd_wr_ptr.data + with self.subTest(msg='field: msk_top_regs.rx_async_fifo_rd_wr_ptr.data'): + fut = self.dut.rx_async_fifo_rd_wr_ptr.data # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0x0 + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=148, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await fut.read(), + 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=148, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=148, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + async def test_register_read_fields(self) -> None: @@ -11756,6 +12100,70 @@ async def test_register_read_fields(self) -> None: reference_read_fields) read_callback_mock.assert_called_once() write_callback_mock.assert_not_called() + with self.subTest(msg='register: msk_top_regs.tx_async_fifo_rd_wr_ptr'): + # test read_fields to register: + # msk_top_regs.tx_async_fifo_rd_wr_ptr + # build up the register value with a random base value, overlaid with + # a random value for each field + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFFFFFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0x0) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + # the read_fields method gets a dictionary back + # from the object with all the read back field + # values + reference_read_fields = { + 'data' : await self.dut.tx_async_fifo_rd_wr_ptr.data.read() + } + + read_callback_mock.reset_mock() + + self.assertDictEqual(await self.dut.tx_async_fifo_rd_wr_ptr.read_fields(), + reference_read_fields) + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + with self.subTest(msg='register: msk_top_regs.rx_async_fifo_rd_wr_ptr'): + # test read_fields to register: + # msk_top_regs.rx_async_fifo_rd_wr_ptr + # build up the register value with a random base value, overlaid with + # a random value for each field + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFFFFFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0x0) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + # the read_fields method gets a dictionary back + # from the object with all the read back field + # values + reference_read_fields = { + 'data' : await self.dut.rx_async_fifo_rd_wr_ptr.data.read() + } + + read_callback_mock.reset_mock() + + self.assertDictEqual(await self.dut.rx_async_fifo_rd_wr_ptr.read_fields(), + reference_read_fields) + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() async def test_register_read_context_manager(self) -> None: """ @@ -13392,6 +13800,78 @@ async def test_register_read_context_manager(self) -> None: read_callback_mock.assert_called_once() write_callback_mock.assert_not_called() + # test context manager to register: + # msk_top_regs.tx_async_fifo_rd_wr_ptr + # build up the register value with a random base value, overlaid with + # a random value for each field + with self.subTest(msg='register: msk_top_regs.tx_async_fifo_rd_wr_ptr'): + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFFFFFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0x0) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + + # first read the fields using the "normal" method, then compare the result to reading + # via the context manager + reference_read_fields = { + 'data' : await self.dut.tx_async_fifo_rd_wr_ptr.data.read() # type: ignore[union-attr] + } + read_callback_mock.reset_mock() + + + async with self.dut.tx_async_fifo_rd_wr_ptr.single_read() as reg_context: # type: ignore[union-attr] + self.assertEqual(reference_read_fields['data'], + await reg_context.get_child_by_system_rdl_name('data').read() + ) + pass + + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + # test context manager to register: + # msk_top_regs.rx_async_fifo_rd_wr_ptr + # build up the register value with a random base value, overlaid with + # a random value for each field + with self.subTest(msg='register: msk_top_regs.rx_async_fifo_rd_wr_ptr'): + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFFFFFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0x0) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + + # first read the fields using the "normal" method, then compare the result to reading + # via the context manager + reference_read_fields = { + 'data' : await self.dut.rx_async_fifo_rd_wr_ptr.data.read() # type: ignore[union-attr] + } + read_callback_mock.reset_mock() + + + async with self.dut.rx_async_fifo_rd_wr_ptr.single_read() as reg_context: # type: ignore[union-attr] + self.assertEqual(reference_read_fields['data'], + await reg_context.get_child_by_system_rdl_name('data').read() + ) + pass + + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() async def test_register_write_context_manager(self) -> None: """ @@ -13982,6 +14462,16 @@ def test_adding_attributes(self) -> None: # this line is trying to set an illegal value so by definition should fail the type # checks self.dut.rx_power.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.tx_async_fifo_rd_wr_ptr'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.tx_async_fifo_rd_wr_ptr.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.rx_async_fifo_rd_wr_ptr'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.rx_async_fifo_rd_wr_ptr.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] with self.subTest(msg='node: msk_top_regs.Hash_ID_Low.hash_id_lo'): with self.assertRaises(AttributeError): # this line is trying to set an illegal value so by definition should fail the type @@ -14277,6 +14767,16 @@ def test_adding_attributes(self) -> None: # this line is trying to set an illegal value so by definition should fail the type # checks self.dut.rx_power.rx_power.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.tx_async_fifo_rd_wr_ptr.data'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.tx_async_fifo_rd_wr_ptr.data.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.rx_async_fifo_rd_wr_ptr.data'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.rx_async_fifo_rd_wr_ptr.data.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] @@ -14362,6 +14862,10 @@ def test_top_traversal_iterators(self) -> None: self.dut.rx_power, # type: ignore[union-attr,list-item] + self.dut.tx_async_fifo_rd_wr_ptr, # type: ignore[union-attr,list-item] + + self.dut.rx_async_fifo_rd_wr_ptr, # type: ignore[union-attr,list-item] + ] readable_regs = [] for readable_reg in self.dut.get_readable_registers(unroll=True): # type: ignore[union-attr] @@ -14441,6 +14945,10 @@ def test_top_traversal_iterators(self) -> None: self.dut.rx_power, # type: ignore[union-attr,list-item] + self.dut.tx_async_fifo_rd_wr_ptr, # type: ignore[union-attr,list-item] + + self.dut.rx_async_fifo_rd_wr_ptr, # type: ignore[union-attr,list-item] + ] readable_regs = [] for readable_reg in self.dut.get_readable_registers(unroll=False): # type: ignore[union-attr] @@ -14520,6 +15028,10 @@ def test_top_traversal_iterators(self) -> None: + + + + ] writable_regs = [] for writable_reg in self.dut.get_writable_registers(unroll=True): # type: ignore[union-attr] @@ -14599,6 +15111,10 @@ def test_top_traversal_iterators(self) -> None: + + + + ] writable_regs = [] for writable_reg in self.dut.get_writable_registers(unroll=False): # type: ignore[union-attr] @@ -14673,6 +15189,10 @@ def test_top_traversal_iterators(self) -> None: + + + + @@ -14752,6 +15272,10 @@ def test_top_traversal_iterators(self) -> None: + + + + @@ -14831,6 +15355,10 @@ def test_top_traversal_iterators(self) -> None: + + + + @@ -14910,6 +15438,10 @@ def test_top_traversal_iterators(self) -> None: + + + + @@ -16129,6 +16661,56 @@ def test_traversal_iterators(self) -> None: readable_fields.append(readable_field) self.assertCountEqual(expected_readable_fields, readable_fields) + with self.subTest(msg='register: msk_top_regs.tx_async_fifo_rd_wr_ptr'): + + expected_fields = [self.dut.tx_async_fifo_rd_wr_ptr.data, # type: ignore[union-attr,list-item] + + + + ] + fields = [] + for field in self.dut.tx_async_fifo_rd_wr_ptr.fields: # type: ignore[union-attr] + fields.append(field) + self.assertCountEqual(expected_fields, fields) + + # register should not have writable_fields attribute + self.assertFalse(hasattr(self.dut.tx_async_fifo_rd_wr_ptr, 'writable_fields')) # type: ignore[union-attr] + + + expected_readable_fields = [self.dut.tx_async_fifo_rd_wr_ptr.data, # type: ignore[union-attr,list-item] + + + ] + readable_fields = [] + for readable_field in self.dut.tx_async_fifo_rd_wr_ptr.readable_fields: # type: ignore[union-attr] + readable_fields.append(readable_field) + self.assertCountEqual(expected_readable_fields, readable_fields) + + with self.subTest(msg='register: msk_top_regs.rx_async_fifo_rd_wr_ptr'): + + expected_fields = [self.dut.rx_async_fifo_rd_wr_ptr.data, # type: ignore[union-attr,list-item] + + + + ] + fields = [] + for field in self.dut.rx_async_fifo_rd_wr_ptr.fields: # type: ignore[union-attr] + fields.append(field) + self.assertCountEqual(expected_fields, fields) + + # register should not have writable_fields attribute + self.assertFalse(hasattr(self.dut.rx_async_fifo_rd_wr_ptr, 'writable_fields')) # type: ignore[union-attr] + + + expected_readable_fields = [self.dut.rx_async_fifo_rd_wr_ptr.data, # type: ignore[union-attr,list-item] + + + ] + readable_fields = [] + for readable_field in self.dut.rx_async_fifo_rd_wr_ptr.readable_fields: # type: ignore[union-attr] + readable_fields.append(readable_field) + self.assertCountEqual(expected_readable_fields, readable_fields) + # test all the memories @@ -16474,6 +17056,20 @@ def test_name_map(self) -> None: + self.assertEqual(self.dut.tx_async_fifo_rd_wr_ptr.get_child_by_system_rdl_name('data').inst_name, 'data') + + + + + + self.assertEqual(self.dut.rx_async_fifo_rd_wr_ptr.get_child_by_system_rdl_name('data').inst_name, 'data') + + + + + + + diff --git a/rdl/outputs/python/msk_top_regs/tests/test_sim_msk_top_regs.py b/rdl/outputs/python/msk_top_regs/tests/test_sim_msk_top_regs.py index d649ad0..f4578fd 100644 --- a/rdl/outputs/python/msk_top_regs/tests/test_sim_msk_top_regs.py +++ b/rdl/outputs/python/msk_top_regs/tests/test_sim_msk_top_regs.py @@ -1700,6 +1700,74 @@ async def test_register_read_and_write(self) -> None: + # test access operations (read and/or write) to register: + # msk_top_regs.tx_async_fifo_rd_wr_ptr + with self.subTest(msg='register: msk_top_regs.tx_async_fifo_rd_wr_ptr'): + sim_register = self.sim.register_by_full_name('msk_top_regs.tx_async_fifo_rd_wr_ptr') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + register_read_callback = Mock() + register_write_callback = Mock() + + # register read checks + # update the value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.tx_async_fifo_rd_wr_ptr.read(), random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.tx_async_fifo_rd_wr_ptr.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.value = random_value + sim_register.read_callback = None + sim_register.write_callback = None + self.assertEqual(await self.dut.tx_async_fifo_rd_wr_ptr.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + + + + + + # test access operations (read and/or write) to register: + # msk_top_regs.rx_async_fifo_rd_wr_ptr + with self.subTest(msg='register: msk_top_regs.rx_async_fifo_rd_wr_ptr'): + sim_register = self.sim.register_by_full_name('msk_top_regs.rx_async_fifo_rd_wr_ptr') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + register_read_callback = Mock() + register_write_callback = Mock() + + # register read checks + # update the value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.rx_async_fifo_rd_wr_ptr.read(), random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.rx_async_fifo_rd_wr_ptr.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.value = random_value + sim_register.read_callback = None + sim_register.write_callback = None + self.assertEqual(await self.dut.rx_async_fifo_rd_wr_ptr.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + + + + + async def test_field_read_and_write(self) -> None: @@ -7492,6 +7560,138 @@ async def test_field_read_and_write(self) -> None: + # test access operations (read and/or write) to register: + # msk_top_regs.tx_async_fifo_rd_wr_ptr.data + with self.subTest(msg='field: msk_top_regs.tx_async_fifo_rd_wr_ptr.data'): + sim_register = self.sim.register_by_full_name('msk_top_regs.tx_async_fifo_rd_wr_ptr') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.tx_async_fifo_rd_wr_ptr.data') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.tx_async_fifo_rd_wr_ptr.data.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0x0) | (random_field_value << 0)) + + self.assertEqual(await self.dut.tx_async_fifo_rd_wr_ptr.data.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.tx_async_fifo_rd_wr_ptr.data.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.tx_async_fifo_rd_wr_ptr.data.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + + + # test access operations (read and/or write) to register: + # msk_top_regs.rx_async_fifo_rd_wr_ptr.data + with self.subTest(msg='field: msk_top_regs.rx_async_fifo_rd_wr_ptr.data'): + sim_register = self.sim.register_by_full_name('msk_top_regs.rx_async_fifo_rd_wr_ptr') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.rx_async_fifo_rd_wr_ptr.data') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.rx_async_fifo_rd_wr_ptr.data.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0x0) | (random_field_value << 0)) + + self.assertEqual(await self.dut.rx_async_fifo_rd_wr_ptr.data.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.rx_async_fifo_rd_wr_ptr.data.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.rx_async_fifo_rd_wr_ptr.data.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + + diff --git a/rdl/outputs/rtl/msk_top_regs.vhd b/rdl/outputs/rtl/msk_top_regs.vhd index 25efa10..dc0d5cb 100644 --- a/rdl/outputs/rtl/msk_top_regs.vhd +++ b/rdl/outputs/rtl/msk_top_regs.vhd @@ -115,6 +115,8 @@ architecture rtl of msk_top_regs is lowpass_ema_alpha1 : std_logic; lowpass_ema_alpha2 : std_logic; rx_power : std_logic; + tx_async_fifo_rd_wr_ptr : std_logic; + rx_async_fifo_rd_wr_ptr : std_logic; end record; signal decoded_reg_strb : decoded_reg_strb_t; signal decoded_strb_is_external : std_logic; @@ -764,7 +766,7 @@ architecture rtl of msk_top_regs is signal readback_err : std_logic; signal readback_done : std_logic; signal readback_data : std_logic_vector(31 downto 0); - signal readback_array : std_logic_vector_array1(0 to 35)(31 downto 0); + signal readback_array : std_logic_vector_array1(0 to 37)(31 downto 0); begin @@ -1050,6 +1052,10 @@ begin decoded_reg_strb.lowpass_ema_alpha2 <= cpuif_req_masked and (cpuif_addr = 16#88#); decoded_reg_strb.rx_power <= cpuif_req_masked and (cpuif_addr = 16#8C#); is_external := is_external or ((cpuif_req_masked and (cpuif_addr = 16#8C#)) and not cpuif_req_is_wr); + decoded_reg_strb.tx_async_fifo_rd_wr_ptr <= cpuif_req_masked and (cpuif_addr = 16#90#); + is_external := is_external or ((cpuif_req_masked and (cpuif_addr = 16#90#)) and not cpuif_req_is_wr); + decoded_reg_strb.rx_async_fifo_rd_wr_ptr <= cpuif_req_masked and (cpuif_addr = 16#94#); + is_external := is_external or ((cpuif_req_masked and (cpuif_addr = 16#94#)) and not cpuif_req_is_wr); decoded_strb_is_external <= is_external; external_req <= is_external; end process; @@ -2303,6 +2309,12 @@ begin hwif_out.rx_power.req <= decoded_reg_strb.rx_power when not decoded_req_is_wr else '0'; hwif_out.rx_power.req_is_wr <= decoded_req_is_wr; + hwif_out.tx_async_fifo_rd_wr_ptr.req <= decoded_reg_strb.tx_async_fifo_rd_wr_ptr when not decoded_req_is_wr else '0'; + hwif_out.tx_async_fifo_rd_wr_ptr.req_is_wr <= decoded_req_is_wr; + + hwif_out.rx_async_fifo_rd_wr_ptr.req <= decoded_reg_strb.rx_async_fifo_rd_wr_ptr when not decoded_req_is_wr else '0'; + hwif_out.rx_async_fifo_rd_wr_ptr.req_is_wr <= decoded_req_is_wr; + ---------------------------------------------------------------------------- -- Write response ---------------------------------------------------------------------------- @@ -2336,6 +2348,8 @@ begin rd_ack := rd_ack or hwif_in.f1_error.rd_ack; rd_ack := rd_ack or hwif_in.f2_error.rd_ack; rd_ack := rd_ack or hwif_in.rx_power.rd_ack; + rd_ack := rd_ack or hwif_in.tx_async_fifo_rd_wr_ptr.rd_ack; + rd_ack := rd_ack or hwif_in.rx_async_fifo_rd_wr_ptr.rd_ack; readback_external_rd_ack_c <= rd_ack; end process; @@ -2409,6 +2423,8 @@ begin readback_array(34)(17 downto 0) <= field_storage.lowpass_ema_alpha2.alpha.value when (decoded_reg_strb.lowpass_ema_alpha2 and not decoded_req_is_wr) else (others => '0'); readback_array(34)(31 downto 18) <= (others => '0'); readback_array(35) <= hwif_in.rx_power.rd_data when hwif_in.rx_power.rd_ack else (others => '0'); + readback_array(36) <= hwif_in.tx_async_fifo_rd_wr_ptr.rd_data when hwif_in.tx_async_fifo_rd_wr_ptr.rd_ack else (others => '0'); + readback_array(37) <= hwif_in.rx_async_fifo_rd_wr_ptr.rd_data when hwif_in.rx_async_fifo_rd_wr_ptr.rd_ack else (others => '0'); -- Reduce the array process(all) diff --git a/rdl/outputs/rtl/msk_top_regs_pkg.vhd b/rdl/outputs/rtl/msk_top_regs_pkg.vhd index c00bed8..394906e 100644 --- a/rdl/outputs/rtl/msk_top_regs_pkg.vhd +++ b/rdl/outputs/rtl/msk_top_regs_pkg.vhd @@ -9,7 +9,7 @@ package msk_top_regs_pkg is constant MSK_TOP_REGS_DATA_WIDTH : positive := 32; constant MSK_TOP_REGS_MIN_ADDR_WIDTH : positive := 8; - constant MSK_TOP_REGS_SIZE : positive := 144; + constant MSK_TOP_REGS_SIZE : positive := 152; type \msk_top_regs.msk_stat_0.demod_sync_lock_in_t\ is record next_q : std_logic; @@ -94,6 +94,16 @@ package msk_top_regs_pkg is rd_data : std_logic_vector(31 downto 0); end record; + type \msk_top_regs.observation_data_data_cf6acbd7_name_aa4ec676__external_in_t\ is record + rd_ack : std_logic; + rd_data : std_logic_vector(31 downto 0); + end record; + + type \msk_top_regs.observation_data_data_cf6acbd7_name_8a90eed1__external_in_t\ is record + rd_ack : std_logic; + rd_data : std_logic_vector(31 downto 0); + end record; + type msk_top_regs_in_t is record MSK_Status : \msk_top_regs.msk_stat_0_in_t\; Tx_Bit_Count : \msk_top_regs.msk_stat_1__external_in_t\; @@ -108,6 +118,8 @@ package msk_top_regs_pkg is f1_error : \msk_top_regs.observation_data_data_25a21249_desc_417e1c96_name_3b640507__external_in_t\; f2_error : \msk_top_regs.observation_data_data_272a00b6_desc_70869502_name_3de9a0d3__external_in_t\; rx_power : \msk_top_regs.rx_power__external_in_t\; + tx_async_fifo_rd_wr_ptr : \msk_top_regs.observation_data_data_cf6acbd7_name_aa4ec676__external_in_t\; + rx_async_fifo_rd_wr_ptr : \msk_top_regs.observation_data_data_cf6acbd7_name_8a90eed1__external_in_t\; end record; type \msk_top_regs.msk_init.txrxinit_out_t\ is record @@ -430,6 +442,16 @@ package msk_top_regs_pkg is req_is_wr : std_logic; end record; + type \msk_top_regs.observation_data_data_cf6acbd7_name_aa4ec676__external_out_t\ is record + req : std_logic; + req_is_wr : std_logic; + end record; + + type \msk_top_regs.observation_data_data_cf6acbd7_name_8a90eed1__external_out_t\ is record + req : std_logic; + req_is_wr : std_logic; + end record; + type msk_top_regs_out_t is record MSK_Init : \msk_top_regs.msk_init_out_t\; MSK_Control : \msk_top_regs.msk_ctrl_out_t\; @@ -464,5 +486,7 @@ package msk_top_regs_pkg is lowpass_ema_alpha1 : \msk_top_regs.lowpass_ema_alpha_out_t\; lowpass_ema_alpha2 : \msk_top_regs.lowpass_ema_alpha_out_t\; rx_power : \msk_top_regs.rx_power__external_out_t\; + tx_async_fifo_rd_wr_ptr : \msk_top_regs.observation_data_data_cf6acbd7_name_aa4ec676__external_out_t\; + rx_async_fifo_rd_wr_ptr : \msk_top_regs.observation_data_data_cf6acbd7_name_8a90eed1__external_out_t\; end record; end package; diff --git a/rdl/src/msk_top_regs.rdl b/rdl/src/msk_top_regs.rdl index c293d19..852fc5f 100644 --- a/rdl/src/msk_top_regs.rdl +++ b/rdl/src/msk_top_regs.rdl @@ -551,5 +551,12 @@ addrmap msk_top_regs { lowpass_ema_alpha lowpass_ema_alpha1; lowpass_ema_alpha lowpass_ema_alpha2; external rx_power rx_power; - + external observation_data tx_async_fifo_rd_wr_ptr; + tx_async_fifo_rd_wr_ptr->name = "Tx async FIFO read and write pointers"; + tx_async_fifo_rd_wr_ptr.data->desc = "Bits 31:16 -> write pointer (12-bits) + Bits 15:00 -> read pointer (12-bits)"; + external observation_data rx_async_fifo_rd_wr_ptr; + rx_async_fifo_rd_wr_ptr->name = "Rx async FIFO read and write pointers"; + rx_async_fifo_rd_wr_ptr.data->desc = "Bits 31:16 -> write pointer (12-bits) + Bits 15:00 -> read pointer (12-bits)"; }; diff --git a/sim/Makefile b/sim/Makefile index b41afca..672cb30 100644 --- a/sim/Makefile +++ b/sim/Makefile @@ -27,6 +27,7 @@ VHDL_SOURCES += $(RDL)/src/axi4lite_intf_pkg.vhd \ $(SRC)/pulse_detect.vhd \ $(SRC)/data_capture.vhd \ $(SRC)/cdc_resync.vhd \ + $(SRC)/frame_sync_detector.vhd \ $(SRC)/axis_async_fifo.vhd \ $(SRC)/axis_dma_adapter.vhd \ $(SRC)/byte_to_bit_deserializer.vhd \ diff --git a/sim/msk_test.py b/sim/msk_test.py index f595209..788ff60 100755 --- a/sim/msk_test.py +++ b/sim/msk_test.py @@ -130,9 +130,11 @@ def __init__(self, dut): self.aclk = dut.s_axis_aclk self.aresetn = dut.s_axis_aresetn - self.tvalid = dut.s_axis_valid - self.tready = dut.s_axis_ready - self.tdata = dut.s_axis_data + self.tvalid = dut.s_axis_tvalid + self.tready = dut.s_axis_tready + self.tdata = dut.s_axis_tdata + self.tlast = dut.s_axis_tlast + self.tkeep = dut.s_axis_tkeep self.aresetn.value = 1 self.tvalid.value = 0 @@ -793,12 +795,11 @@ async def msk_test_1(dut): # dut.s_axi_awvalid.value = 1 # await regs.write("msk_top_regs", "PRBS_Control", data) - # if sim_time_d <= sim_start + 20000 and sim_time >= sim_start + 20000: - # data = await regs.read("msk_top_regs", "PRBS_Control") - # data = data ^ 0x8 - # dut.s_axi_wvalid.value = 1 - # dut.s_axi_awvalid.value = 1 - # await regs.write("msk_top_regs", "PRBS_Control", data) + # if sim_time_d <= sim_start + 30000 and sim_time >= sim_start + 30000: + # data = await regs.tx_async_fifo_rd_wr_ptr.read() + # print("Tx FIFO Pointers", hex(data)) + # data = await regs.rx_async_fifo_rd_wr_ptr.read() + # print("Rx FIFO Pointers", hex(data)) if sim_time_d <= sim_start + 20000 and sim_time >= sim_start + 20000: data = await regs.PRBS_Control.read() @@ -833,6 +834,10 @@ async def msk_test_1(dut): print("F1 Error: ", hex(data)) data = await regs.f2_error.read() print("F2 Error: ", hex(data)) + data = await regs.tx_async_fifo_rd_wr_ptr.read() + print("Tx FIFO Pointers", hex(data)) + data = await regs.rx_async_fifo_rd_wr_ptr.read() + print("Rx FIFO Pointers", hex(data)) #data = await regs.read("msk_top_regs", "LPF_Accum_F1") # print("F1 Acc: ", hex(data)) # data = await regs.read("msk_top_regs", "LPF_Accum_F2") diff --git a/src/axis_async_fifo.vhd b/src/axis_async_fifo.vhd index ec47e82..1ab08b4 100644 --- a/src/axis_async_fifo.vhd +++ b/src/axis_async_fifo.vhd @@ -48,7 +48,7 @@ ENTITY axis_async_fifo IS fifo_overflow : OUT std_logic; fifo_underflow : OUT std_logic; fifo_wr_ptr : OUT std_logic_vector(ADDR_WIDTH DOWNTO 0); - fifo_rd_ptr : OUT srd_logic_vector(ADDR_WIDTH DOWNTO 0) + fifo_rd_ptr : OUT std_logic_vector(ADDR_WIDTH DOWNTO 0) ); END ENTITY axis_async_fifo; @@ -87,6 +87,23 @@ ARCHITECTURE rtl OF axis_async_fifo IS SIGNAL prog_full_int : std_logic := '0'; SIGNAL prog_empty_int : std_logic := '0'; + -- Status resync to AXI + SIGNAL wr_status_ack : std_logic; + SIGNAL wr_status_ack_sync1 : std_logic; + SIGNAL wr_status_ack_sync2 : std_logic; + SIGNAL wr_status_req_sync1 : std_logic; + SIGNAL wr_status_req_sync2 : std_logic; + SIGNAL rd_status_ack : std_logic; + SIGNAL rd_status_ack_sync1 : std_logic; + SIGNAL rd_status_ack_sync2 : std_logic; + SIGNAL rd_status_req_sync1 : std_logic; + SIGNAL rd_status_req_sync2 : std_logic; + + SIGNAL srequest : std_logic; + + TYPE state_type IS (IDLE, WAIT_FOR_WR_ACK, WAIT_FOR_RD_ACK); + SIGNAL status_state : state_type; + -- Binary to Gray conversion FUNCTION bin_to_gray(bin : std_logic_vector) RETURN std_logic_vector IS VARIABLE gray : std_logic_vector(bin'RANGE); @@ -230,40 +247,51 @@ BEGIN ------------------------------------------------------------------------------ -- Status Clock Domain ------------------------------------------------------------------------------ - status_proc : PROCESS (prog_aclk) + + status_proc : PROCESS (status_aclk) BEGIN - IF rising_edge(prog_aclk) BEGIN - IF prog_aresetn = '0' THEN + IF rising_edge(status_aclk) THEN + IF status_aresetn = '0' THEN --prog_empty <= '0'; --prog_full <= '0'; fifo_overflow <= '0'; fifo_underflow <= '0'; fifo_wr_ptr <= (OTHERS => '0'); fifo_rd_ptr <= (OTHERS => '0'); - fifo_status_ack <= '0'; + status_ack <= '0'; ELSE + CASE status_state IS + WHEN IDLE => + srequest <= '0'; + status_ack <= '0'; + IF status_req = '1' THEN + srequest <= '1'; + status_state <= WAIT_FOR_WR_ACK; + END IF; + + WHEN WAIT_FOR_WR_ACK => + IF wr_status_ack_sync2 = '1' THEN + status_state <= WAIT_FOR_RD_ACK; + END IF; + + WHEN WAIT_FOR_RD_ACK => + IF rd_status_ack_sync2 = '1' THEN + status_ack <= '1'; + srequest <= '0'; + status_state <= IDLE; + END IF; + + WHEN OTHERS => + status_state <= IDLE; + + END CASE; + wr_status_ack_sync1 <= wr_status_ack; wr_status_ack_sync2 <= wr_status_ack_sync1; - wr_status_ack_sync3 <= wr_status_ack_sync2; - - IF (wr_status_req_sync2 XOR wr_status_ack_sync3) = '1' THEN - prog_wr_status_ack <= '1'; - END IF; rd_status_ack_sync1 <= rd_status_ack; rd_status_ack_sync2 <= rd_status_ack_sync1; - rd_status_ack_sync3 <= rd_status_ack_sync2; - - IF (rd_status_req_sync2 XOR rd_status_ack_sync3) = '1' THEN - prog_rd_status_ack <= '1'; - END IF; - - IF prog_wr_status_ack = '1' AND prod_rd_status_ack = '1' THEN - prog_status_ack <= '1'; - ELSE - prog_status_ack <= '0'; - END IF; END IF; END IF; @@ -277,12 +305,12 @@ BEGIN wr_status_req_sync2 <= '0'; wr_status_ack <= '0'; ELSE - wr_status_req_sync1 <= prog_status_req; + wr_status_req_sync1 <= srequest; wr_status_req_sync2 <= wr_status_req_sync1; + wr_status_ack <= wr_status_req_sync2; IF wr_status_req_sync2 THEN fifo_wr_ptr <= wr_ptr_bin; - wr_status_ack <= NOT wr_status_ack; END IF; END IF; END IF; @@ -296,15 +324,15 @@ BEGIN rd_status_req_sync2 <= '0'; rd_status_ack <= '0'; ELSE - rd_status_req_sync1 <= prog_status_req; + rd_status_req_sync1 <= srequest; rd_status_req_sync2 <= rd_status_req_sync1; + rd_status_ack <= rd_status_req_sync2; IF rd_status_req_sync2 THEN fifo_rd_ptr <= rd_ptr_bin; - rd_status_ack <= NOT rd_status_ack; END IF; END IF; END IF; - END PROCESS status_wrclk; + END PROCESS status_rdclk; END ARCHITECTURE rtl; diff --git a/src/msk_top.vhd b/src/msk_top.vhd index 069bd1e..61ca0bc 100644 --- a/src/msk_top.vhd +++ b/src/msk_top.vhd @@ -173,8 +173,8 @@ ARCHITECTURE struct OF msk_top IS SIGNAL tx_async_fifo_prog_empty : std_logic; SIGNAL tx_async_fifo_overflow : std_logic; SIGNAL tx_async_fifo_underflow : std_logic; - SIGNAL tx_async_fifo_wr_ptr : std_logic(FIFO_ADDR_WIDTH DOWNTO 0); - SIGNAL tx_async_fifo_rd_ptr : std_logic(FIFO_ADDR_WIDTH DOWNTO 0); + SIGNAL tx_async_fifo_wr_ptr : std_logic_vector(FIFO_ADDR_WIDTH DOWNTO 0); + SIGNAL tx_async_fifo_rd_ptr : std_logic_vector(FIFO_ADDR_WIDTH DOWNTO 0); SIGNAL tx_async_fifo_status_req : std_logic; SIGNAL tx_async_fifo_status_ack : std_logic; @@ -182,8 +182,8 @@ ARCHITECTURE struct OF msk_top IS SIGNAL rx_async_fifo_prog_empty : std_logic; SIGNAL rx_async_fifo_overflow : std_logic; SIGNAL rx_async_fifo_underflow : std_logic; - SIGNAL rx_async_fifo_wr_ptr : std_logic(FIFO_ADDR_WIDTH DOWNTO 0); - SIGNAL rx_async_fifo_rd_ptr : std_logic(FIFO_ADDR_WIDTH DOWNTO 0); + SIGNAL rx_async_fifo_wr_ptr : std_logic_vector(FIFO_ADDR_WIDTH DOWNTO 0); + SIGNAL rx_async_fifo_rd_ptr : std_logic_vector(FIFO_ADDR_WIDTH DOWNTO 0); SIGNAL rx_async_fifo_status_req : std_logic; SIGNAL rx_async_fifo_status_ack : std_logic; @@ -339,16 +339,16 @@ BEGIN m_axis_tlast => fifo_tlast, -- status signals synchronized to AXI control/status bus - prog_aclk => s_axi_aclk, - prog_aresetn => s_axi_aresetn, - prog_status_req => tx_async_fifo_status_req, - prog_status_ack => tx_async_fifo_status_ack, + status_aclk => s_axi_aclk, + status_aresetn => s_axi_aresetn, + status_req => tx_async_fifo_status_req, + status_ack => tx_async_fifo_status_ack, prog_full => tx_async_fifo_prog_full, prog_empty => tx_async_fifo_prog_empty, - prog_overflow => tx_async_fifo_overflow, - prog_underflow => tx_async_fifo_underflow, - prog_wr_ptr => tx_async_fifo_wr_ptr, - prog_rd_ptr => tx_async_fifo_rd_ptr + fifo_overflow => tx_async_fifo_overflow, + fifo_underflow => tx_async_fifo_underflow, + fifo_wr_ptr => tx_async_fifo_wr_ptr, + fifo_rd_ptr => tx_async_fifo_rd_ptr ); -- Stage 3: Byte-to-Bit De-serializer (MSB-FIRST VERSION) @@ -523,16 +523,16 @@ BEGIN m_axis_tlast => m_axis_tlast, -- status signals synchronized to AXI control/status bus - prog_aclk => s_axi_aclk, - prog_aresetn => s_axi_aresetn, - prog_status_req => rx_async_fifo_status_req, - prog_status_ack => rx_async_fifo_status_ack, - prog_full => rx_async_fifo_prog_full, - prog_empty => rx_async_fifo_prog_empty, - prog_overflow => rx_async_fifo_overflow, - prog_underflow => rx_async_fifo_underflow, - prog_wr_ptr => rx_async_fifo_wr_ptr, - prog_rd_ptr => rx_async_fifo_rd_ptr + status_aclk => s_axi_aclk, + status_aresetn => s_axi_aresetn, + status_req => rx_async_fifo_status_req, + status_ack => rx_async_fifo_status_ack, + prog_full => rx_async_fifo_prog_full, + prog_empty => rx_async_fifo_prog_empty, + fifo_overflow => rx_async_fifo_overflow, + fifo_underflow => rx_async_fifo_underflow, + fifo_wr_ptr => rx_async_fifo_wr_ptr, + fifo_rd_ptr => rx_async_fifo_rd_ptr ); -- Zero-pad upper bits of m_axis_tdata if wider than 8 bits @@ -767,6 +767,14 @@ BEGIN f2_nco_adjust => f2_nco_adjust, f1_error => f1_error, f2_error => f2_error, + tx_async_fifo_wr_ptr => tx_async_fifo_wr_ptr, + tx_async_fifo_rd_ptr => tx_async_fifo_rd_ptr, + tx_async_fifo_status_req => tx_async_fifo_status_req, + tx_async_fifo_status_ack => tx_async_fifo_status_ack, + rx_async_fifo_wr_ptr => rx_async_fifo_wr_ptr, + rx_async_fifo_rd_ptr => rx_async_fifo_rd_ptr, + rx_async_fifo_status_req => rx_async_fifo_status_req, + rx_async_fifo_status_ack => rx_async_fifo_status_ack, txinit => txinit, rxinit => rxinit, ptt => ptt, diff --git a/src/msk_top_csr.vhd b/src/msk_top_csr.vhd index 9fa83bd..ee86e51 100644 --- a/src/msk_top_csr.vhd +++ b/src/msk_top_csr.vhd @@ -84,7 +84,8 @@ ENTITY msk_top_csr IS SYNC_W : NATURAL := 16; C_S_AXI_DATA_WIDTH : NATURAL := 32; C_S_AXI_ADDR_WIDTH : NATURAL := 32; - SYNC_CNT_W : NATURAL := 24 + SYNC_CNT_W : NATURAL := 24; + FIFO_ADDR_WIDTH : NATURAL := 11 ); PORT ( clk : IN std_logic; @@ -128,6 +129,15 @@ ENTITY msk_top_csr IS f1_error : IN std_logic_vector(31 DOWNTO 0); f2_error : IN std_logic_vector(31 DOWNTO 0); + tx_async_fifo_wr_ptr : IN std_logic_vector(FIFO_ADDR_WIDTH DOWNTO 0); + tx_async_fifo_rd_ptr : IN std_logic_vector(FIFO_ADDR_WIDTH DOWNTO 0); + tx_async_fifo_status_req : OUT std_logic; + tx_async_fifo_status_ack : IN std_logic; + rx_async_fifo_wr_ptr : IN std_logic_vector(FIFO_ADDR_WIDTH DOWNTO 0); + rx_async_fifo_rd_ptr : IN std_logic_vector(FIFO_ADDR_WIDTH DOWNTO 0); + rx_async_fifo_status_req : OUT std_logic; + rx_async_fifo_status_ack : IN std_logic; + txinit : out std_logic; rxinit : out std_logic; ptt : out std_logic; @@ -333,6 +343,17 @@ BEGIN utpwr_c: data_capture PORT MAP (clk, csr_init, pd_power_req, std_logic_vector(resize(unsigned(pd_power),32)), hwif_in.rx_power.rd_data); + -- FIFO status reads + rx_async_fifo_status_req <= hwif_out.rx_async_fifo_rd_wr_ptr.req; + hwif_in.rx_async_fifo_rd_wr_ptr.rd_ack <= rx_async_fifo_status_ack; + hwif_in.rx_async_fifo_rd_wr_ptr.rd_data <= std_logic_vector(resize(unsigned(rx_async_fifo_wr_ptr), 16) & + resize(unsigned(rx_async_fifo_rd_ptr), 16)); + + tx_async_fifo_status_req <= hwif_out.tx_async_fifo_rd_wr_ptr.req; + hwif_in.tx_async_fifo_rd_wr_ptr.rd_ack <= tx_async_fifo_status_ack; + hwif_in.tx_async_fifo_rd_wr_ptr.rd_data <= std_logic_vector(resize(unsigned(tx_async_fifo_wr_ptr), 16) & + resize(unsigned(tx_async_fifo_rd_ptr), 16)); + -- Control from AXI to MDM u01s: cdc_resync PORT MAP (clk, csr_init, hwif_out.MSK_Init.txrxinit.value, txrxinit ); u02s: cdc_resync PORT MAP (clk, csr_init, hwif_out.MSK_Init.txinit.value OR txrxinit, txinit ); From 4923b1f4f408e1f177aa0084735fc4843081dc32 Mon Sep 17 00:00:00 2001 From: Matthew Wishek Date: Sun, 26 Oct 2025 23:55:56 -0600 Subject: [PATCH 05/60] Fix fifo pointer read --- sim/msk_test.py | 10 +++++----- src/axis_async_fifo.vhd | 4 ++-- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/sim/msk_test.py b/sim/msk_test.py index 788ff60..d063eba 100755 --- a/sim/msk_test.py +++ b/sim/msk_test.py @@ -763,7 +763,7 @@ async def msk_test_1(dut): await RisingEdge(dut.clk) msksim = msk(dut, dut.clk, dut.tx_samples_I, dut.tx_samples_Q, dut.rx_sample_clk, dut.rx_samples_dec) - #pn = prbs(dut, dut.clk, axis, tx_data_width, rx_data_width, dut.rx_data, dut.rx_dvalid) + pn = prbs(dut, dut.clk, axis, tx_data_width, rx_data_width, dut.m_axis_tdata, dut.m_axis_tvalid) ducsim = duc(dut, msksim, local_osc, tx_sample_period) ddcsim = ddc(dut, msksim, ducsim, local_osc, tx_sample_period) @@ -772,8 +772,8 @@ async def msk_test_1(dut): await cocotb.start(msksim.rx_sample_capture()) await cocotb.start(ducsim.upconvert()) await cocotb.start(ddcsim.downconvert()) - # await cocotb.start(pn.generate_data()) - # await cocotb.start(pn.check_data()) + await cocotb.start(pn.generate_data()) + await cocotb.start(pn.check_data()) sim_time = get_sim_time("us") sim_start = sim_time @@ -783,8 +783,8 @@ async def msk_test_1(dut): msksim.sim_run = True - #pn.sim_run = True - #pn.sync = 100 + pn.sim_run = True + pn.sync = 100 while sim_time < run_time: #sim_start + run_time: diff --git a/src/axis_async_fifo.vhd b/src/axis_async_fifo.vhd index 1ab08b4..497109a 100644 --- a/src/axis_async_fifo.vhd +++ b/src/axis_async_fifo.vhd @@ -256,8 +256,6 @@ BEGIN --prog_full <= '0'; fifo_overflow <= '0'; fifo_underflow <= '0'; - fifo_wr_ptr <= (OTHERS => '0'); - fifo_rd_ptr <= (OTHERS => '0'); status_ack <= '0'; ELSE @@ -304,6 +302,7 @@ BEGIN wr_status_req_sync1 <= '0'; wr_status_req_sync2 <= '0'; wr_status_ack <= '0'; + fifo_wr_ptr <= (OTHERS => '0'); ELSE wr_status_req_sync1 <= srequest; wr_status_req_sync2 <= wr_status_req_sync1; @@ -323,6 +322,7 @@ BEGIN rd_status_req_sync1 <= '0'; rd_status_req_sync2 <= '0'; rd_status_ack <= '0'; + fifo_rd_ptr <= (OTHERS => '0'); ELSE rd_status_req_sync1 <= srequest; rd_status_req_sync2 <= rd_status_req_sync1; From ccd7b742d111d38665d6aabaac4a37273c0b8548 Mon Sep 17 00:00:00 2001 From: Abraxas3d Date: Mon, 27 Oct 2025 16:14:29 -0700 Subject: [PATCH 06/60] added the = '1' so implicit type casting from std_logic to boolean won't derail the firmware build --- src/axis_async_fifo.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/axis_async_fifo.vhd b/src/axis_async_fifo.vhd index 497109a..b6406eb 100644 --- a/src/axis_async_fifo.vhd +++ b/src/axis_async_fifo.vhd @@ -308,7 +308,7 @@ BEGIN wr_status_req_sync2 <= wr_status_req_sync1; wr_status_ack <= wr_status_req_sync2; - IF wr_status_req_sync2 THEN + IF wr_status_req_sync2 = '1' THEN fifo_wr_ptr <= wr_ptr_bin; END IF; END IF; From 5da15ebc1d218984694266c77feca84ea39bd4c2 Mon Sep 17 00:00:00 2001 From: Abraxas3d Date: Mon, 27 Oct 2025 16:22:24 -0700 Subject: [PATCH 07/60] added = '1' to rd_status_req_sync2 test in order to gresolve implicit type cast from std_logic to boolean. Now make will work. --- src/axis_async_fifo.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/axis_async_fifo.vhd b/src/axis_async_fifo.vhd index b6406eb..eed9962 100644 --- a/src/axis_async_fifo.vhd +++ b/src/axis_async_fifo.vhd @@ -328,7 +328,7 @@ BEGIN rd_status_req_sync2 <= rd_status_req_sync1; rd_status_ack <= rd_status_req_sync2; - IF rd_status_req_sync2 THEN + IF rd_status_req_sync2 = '1' THEN fifo_rd_ptr <= rd_ptr_bin; END IF; END IF; From a0e1f6f89c7f4ae7cbcb4c2d9963211ca13f9439 Mon Sep 17 00:00:00 2001 From: Abraxas3d Date: Mon, 27 Oct 2025 16:34:44 -0700 Subject: [PATCH 08/60] added /rdl/src/axi4lite_intf_pkg.vhd to the IP list in /pluto_msk/library/msk_top_ip.tcl --- library/msk_top_ip.tcl | 1 + 1 file changed, 1 insertion(+) diff --git a/library/msk_top_ip.tcl b/library/msk_top_ip.tcl index 36151aa..2a2733d 100644 --- a/library/msk_top_ip.tcl +++ b/library/msk_top_ip.tcl @@ -10,6 +10,7 @@ read_vhdl -library "desyrdl" "../rdl/vhdl/desyrdl/pkg_desyrdl_common.vhd" #set_property FILE_TYPE {VHDL 2008} [get_files $ad_hdl_dir/library/msk_top/src/*.vhd] adi_ip_files msk_top [list \ + "../rdl/src/axi4lite_intf_pkg.vhd" \ "../rdl/vhdl/msk_top_regs/msk_top_regs_decoder_axi4l.vhd" \ "../rdl/vhdl/msk_top_regs/pkg_msk_top_regs.vhd" \ "../rdl/vhdl/msk_top_regs/msk_top_regs.vhd" \ From b23e0f8524de940f77828c3f4caf48a8209ed84f Mon Sep 17 00:00:00 2001 From: Abraxas3d Date: Mon, 27 Oct 2025 17:05:08 -0700 Subject: [PATCH 09/60] putting read_vhdl pkg_msk_top_regs.vhd up above, and making sure 2008 is called out for /axi4lite_intf_pkg.vhd --- library/msk_top_ip.tcl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/library/msk_top_ip.tcl b/library/msk_top_ip.tcl index 2a2733d..3b4c90f 100644 --- a/library/msk_top_ip.tcl +++ b/library/msk_top_ip.tcl @@ -7,12 +7,12 @@ source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl adi_ip_create msk_top read_vhdl -library "desyrdl" "../rdl/vhdl/desyrdl/pkg_desyrdl_common.vhd" +read_vhdl -vhdl2008 "../rdl/src/axi4lite_intf_pkg.vhd" +read_vhdl "../rdl/vhdl/msk_top_regs/pkg_msk_top_regs.vhd" #set_property FILE_TYPE {VHDL 2008} [get_files $ad_hdl_dir/library/msk_top/src/*.vhd] adi_ip_files msk_top [list \ - "../rdl/src/axi4lite_intf_pkg.vhd" \ "../rdl/vhdl/msk_top_regs/msk_top_regs_decoder_axi4l.vhd" \ - "../rdl/vhdl/msk_top_regs/pkg_msk_top_regs.vhd" \ "../rdl/vhdl/msk_top_regs/msk_top_regs.vhd" \ "../msk_demodulator/src/costas_loop.vhd" \ "../pi_controller/src/pi_controller.vhd" \ From 3558ba21b602d181cd3defaf95f24de20892f10c Mon Sep 17 00:00:00 2001 From: Abraxas3d Date: Mon, 27 Oct 2025 17:16:21 -0700 Subject: [PATCH 10/60] there was a name mismatch so I changed it to match like this: USE work.axi4lite_intf_pkg.ALL; --USE work.msk_top_regs_pkg.ALL; USE work.pkg_msk_top_regs.ALL; --- src/msk_top_csr.vhd | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/msk_top_csr.vhd b/src/msk_top_csr.vhd index ee86e51..ba71d22 100644 --- a/src/msk_top_csr.vhd +++ b/src/msk_top_csr.vhd @@ -62,7 +62,8 @@ USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; USE work.axi4lite_intf_pkg.ALL; -USE work.msk_top_regs_pkg.ALL; +--USE work.msk_top_regs_pkg.ALL; +USE work.pkg_msk_top_regs.ALL; ------------------------------------------------------------------------------------------------------ -- ╔═╗┌┐┌┌┬┐┬┌┬┐┬ ┬ From bdac6a3909269ac621bc813281b25d4bb39b2117 Mon Sep 17 00:00:00 2001 From: Matthew Wishek Date: Mon, 27 Oct 2025 18:57:00 -0600 Subject: [PATCH 11/60] Remove rdl/vhdl folder and contents, revert USE library to work.msk_top_regs_pkg in msk_top_csr.vhd --- rdl/vhdl/desyrdl/pkg_desyrdl_common.vhd | 266 -- rdl/vhdl/msk_top_regs/msk_top_regs.vhd | 792 ---- .../msk_top_regs_decoder_axi4l.vhd | 536 --- rdl/vhdl/msk_top_regs/pkg_msk_top_regs.vhd | 3394 ----------------- src/msk_top_csr.vhd | 3 +- 5 files changed, 1 insertion(+), 4990 deletions(-) delete mode 100644 rdl/vhdl/desyrdl/pkg_desyrdl_common.vhd delete mode 100644 rdl/vhdl/msk_top_regs/msk_top_regs.vhd delete mode 100644 rdl/vhdl/msk_top_regs/msk_top_regs_decoder_axi4l.vhd delete mode 100644 rdl/vhdl/msk_top_regs/pkg_msk_top_regs.vhd diff --git a/rdl/vhdl/desyrdl/pkg_desyrdl_common.vhd b/rdl/vhdl/desyrdl/pkg_desyrdl_common.vhd deleted file mode 100644 index b630a3b..0000000 --- a/rdl/vhdl/desyrdl/pkg_desyrdl_common.vhd +++ /dev/null @@ -1,266 +0,0 @@ -------------------------------------------------------------------------------- --- ____ _____________ __ -- --- / __ \/ ____/ ___/\ \/ / _ _ _ -- --- / / / / __/ \__ \ \ / / \ / \ / \ -- --- / /_/ / /___ ___/ / / / = ( M | S | K )= -- --- /_____/_____//____/ /_/ \_/ \_/ \_/ -- --- -- -------------------------------------------------------------------------------- ---! @copyright Copyright 2021-2022 DESY ---! SPDX-License-Identifier: Apache-2.0 -------------------------------------------------------------------------------- ---! @date 2021-08-04 ---! @author Michael Büchler ---! @author Lukasz Butkowski -------------------------------------------------------------------------------- ---! @brief Package with common DesyRDL components -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - --- library desy; --- use desy.common_types.all; --- use desy.common_axi.all; - -package common is - - constant C_AXI4L_ADDR_WIDTH : natural := 32; - constant C_AXI4L_DATA_WIDTH : natural := 32; - - --------------------------------------------------------------------------- - -- common type definitions - -- type t_4b_slv_array is array (integer range<>) of std_logic_vector( 3 downto 0) ; - -- type t_32b_slv_array is array (integer range<>) of std_logic_vector(31 downto 0) ; - -- type t_integer_array is array (integer range<>) of integer ; - - --============================================================================ - -- AXI4-Lite - --============================================================================ - type t_axi4l_m2s is record - -- write address channel signals--------------------------------------------- - awaddr : std_logic_vector(C_AXI4L_ADDR_WIDTH-1 downto 0); - awprot : std_logic_vector(2 downto 0); - awvalid : std_logic; - -- write data channel signals--------------------------------------------- - wdata : std_logic_vector(C_AXI4L_DATA_WIDTH-1 downto 0); - wstrb : std_logic_vector(C_AXI4L_DATA_WIDTH/8-1 downto 0); - wvalid : std_logic; - -- write response channel signals - bready : std_logic; - -- read address channel signals --------------------------------------------- - araddr : std_logic_vector(C_AXI4L_ADDR_WIDTH-1 downto 0); - arprot : std_logic_vector(2 downto 0); - arvalid : std_logic; - -- read data channel signals--------------------------------------------- - rready : std_logic; - end record t_axi4l_m2s; - - type t_axi4l_s2m is record - -- write address channel signals--------------------------------------------- - awready : std_logic; - -- write data channel signals--------------------------------------------- - wready : std_logic; - -- write response channel signals --------------------------------------------- - bresp : std_logic_vector(1 downto 0); - bvalid : std_logic; - -- read address channel signals--------------------------------------------- - arready : std_logic; - -- read data channel signals--------------------------------------------- - rdata : std_logic_vector(C_AXI4L_DATA_WIDTH-1 downto 0); - rresp : std_logic_vector(1 downto 0); - rvalid : std_logic; - end record t_axi4l_s2m; - - type t_axi4l_m2s_vector is array (integer range <>) of t_axi4l_m2s; - type t_axi4l_s2m_vector is array (integer range <>) of t_axi4l_s2m; - - constant C_AXI4L_S2M_DEFAULT : t_axi4l_s2m := ( - awready => '0', - wready => '0', - bresp => (others => '0'), - bvalid => '0', - arready => '0' , - rdata => (others => '0'), - rresp => (others => '0'), - rvalid => '0' - ); - constant C_AXI4L_M2S_DEFAULT : t_axi4l_m2s := ( - awaddr => (others => '0'), - awprot => (others => '0'), - awvalid => '0', - wdata => (others => '0'), - wstrb => (others => '0'), - wvalid => '0', - bready => '0', - araddr => (others => '0'), - arprot => (others => '0'), - arvalid => '0', - rready => '0' - ); - - --------------------------------------------------------------------------- - -- Interface definitions for IBUS - -- Internal BUS (IBUS) is the internal bus used in the applications of MSK Firmware - -- repository. - - -- Output signals of IBUS. Through this record the application send data/commands to the bus - type t_ibus_m2s is record - addr : std_logic_vector(31 downto 0); - data : std_logic_vector(31 downto 0); - rena : std_logic; - wena : std_logic; - end record t_ibus_m2s; - - -- Output signals of IBUS. Through this record the application send data/commands to the bus - type t_ibus_s2m is record - data : std_logic_vector(31 downto 0); - rack : std_logic; - wack : std_logic; - end record t_ibus_s2m; - - -- Array of IBUS outputs - type t_ibus_m2s_vector is array (integer range<>) of t_ibus_m2s; - - -- Array of IBUS inputs - type t_ibus_s2m_vector is array (integer range<>) of t_ibus_s2m; - - -- Default IBUS connections for the output (All entries equals 0) - constant C_IBUS_M2S_DEFAULT : t_ibus_m2s := ( - addr => (others => '0'), - data => (others => '0'), - rena => '0', - wena => '0' - ); - -- Default IBUS connections for the input (All entries equals 0) - constant C_IBUS_S2M_DEFAULT : t_ibus_s2m := ( - data => (others => '0'), - rack => '0', - wack => '0' - ); - - - --------------------------------------------------------------------------- - -- SystemRDL-specific definitions - --type t_field_access is (R, W, RW, NA); - subtype t_access_type is integer; - constant C_NA : integer := 1; - constant C_RW : integer := 2; - constant C_R : integer := 3; - constant C_W : integer := 4; - constant C_RW1 : integer := 5; - constant C_W1 : integer := 6; - - type t_field_type is (STORAGE, WIRE, COUNTER, INTERRUPT); - - type t_field_info is record - ftype : t_field_type; - len : integer; - upper : integer; - lower : integer; - sw : t_access_type; - hw : t_access_type; - we : integer; - incrwidth : integer; - decrwidth : integer; - defval : integer; - end record; - - type t_field_info_vector is array (integer range <>) of t_field_info; - - constant C_FIELD_NONE : t_field_info := (WIRE, 0, 0, 0, C_NA, C_NA, 0, 0, 0, 0); - - type t_reg_info is record - -- index : integer; - address : unsigned(C_AXI4L_ADDR_WIDTH-1 downto 0); - elements : integer; - index : integer; - fields : t_field_info_vector(31 downto 0); - --dim : natural; - dim_n : positive; - dim_m : positive; - end record; - - type t_reg_info_vector is array (integer range <>) of t_reg_info; - - constant C_REG_NONE : t_reg_info := (x"0000_0000", 0, 0,(others => C_FIELD_NONE),1,1); - - type t_mem_info is record - -- index : integer; - address : unsigned(C_AXI4L_ADDR_WIDTH-1 downto 0); - addrwidth : integer; - datawidth : integer; - entries : integer; - sw : t_access_type; - end record; - - type t_mem_info_vector is array (integer range <>) of t_mem_info; - - constant C_MEM_NONE : t_mem_info := (x"0000_0000", 0, 0, 0, C_NA); - - type t_ext_info is record - -- index : integer; - address : unsigned(C_AXI4L_ADDR_WIDTH-1 downto 0); - addrwidth : integer; - size : integer; - end record; - - type t_ext_info_vector is array (integer range <>) of t_ext_info; - - constant C_EXT_NONE : t_ext_info := (x"0000_0000", 0, 0); - - -- interface types - type t_if_type Is (DPM, AXI4, AXI4L, IBUS, WISHBONE, AVALON, NONE); - type t_if_type_vector is array (integer range <>) of t_if_type; - - ----------------------------------------------------------------------------- - -- bus converter components - component axi4l_to_axi4l is - port ( - pi_reset : in std_logic; - pi_clock : in std_logic; - pi_s_decoder : in t_axi4l_m2s; - po_s_decoder : out t_axi4l_s2m; - po_m_ext : out t_axi4l_m2s; - pi_m_ext : in t_axi4l_s2m); - end component axi4l_to_axi4l; - - component axi4l_to_ibus is - port ( - pi_reset : in std_logic; - pi_clock : in std_logic; - pi_s_decoder : in t_axi4l_m2s; - po_s_decoder : out t_axi4l_s2m; - po_m_ext : out t_ibus_m2s; - pi_m_ext : in t_ibus_s2m); - end component axi4l_to_ibus; - - component ibus_to_axi4l is - port ( - pi_reset : in std_logic; - pi_clock : in std_logic; - pi_s_decoder : in t_ibus_m2s; - po_s_decoder : out t_ibus_s2m; - po_m_ext : out t_axi4l_m2s; - pi_m_ext : in t_axi4l_s2m); - end component ibus_to_axi4l; - - --common functions - -- intr_or_reduce - or recuce for interrupt register - function intr_or_reduce (arg: std_logic_vector) return std_logic; - -end package common; - ---============================================================================== -package body common is - function intr_or_reduce (arg : std_logic_vector) return std_logic is - constant C_ZEROES : std_logic_vector(arg'length - 1 downto 0) := (others => '0'); - begin -- function intr_or_reduce - if (arg = C_ZEROES) then - return '0'; - else - return '1'; - end if; - end function intr_or_reduce; -end package body; \ No newline at end of file diff --git a/rdl/vhdl/msk_top_regs/msk_top_regs.vhd b/rdl/vhdl/msk_top_regs/msk_top_regs.vhd deleted file mode 100644 index a0ba184..0000000 --- a/rdl/vhdl/msk_top_regs/msk_top_regs.vhd +++ /dev/null @@ -1,792 +0,0 @@ ------------------------------------------------------------------------------- --- ____ _____________ __ -- --- / __ \/ ____/ ___/\ \/ / _ _ _ -- --- / / / / __/ \__ \ \ / / \ / \ / \ -- --- / /_/ / /___ ___/ / / / = ( M | S | K )= -- --- /_____/_____//____/ /_/ \_/ \_/ \_/ -- --- -- ------------------------------------------------------------------------------- ---! @copyright Copyright 2021-2022 DESY ---! SPDX-License-Identifier: Apache-2.0 ------------------------------------------------------------------------------- ---! @date 2021-04-07 ---! @author Michael Büchler ---! @author Lukasz Butkowski ------------------------------------------------------------------------------- ---! @brief ---! Top component of DesyRDL address space decoder for msk_top_regs ------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library desyrdl; -use desyrdl.common.all; - -use work.pkg_msk_top_regs.all; - -entity msk_top_regs is - port ( - pi_clock : in std_logic; - pi_reset : in std_logic; - -- TOP subordinate memory mapped interface - pi_s_reset : in std_logic := '0'; - pi_s_top : in t_msk_top_regs_m2s; - po_s_top : out t_msk_top_regs_s2m; - -- to logic interface - pi_addrmap : in t_addrmap_msk_top_regs_in; - po_addrmap : out t_addrmap_msk_top_regs_out - ); -end entity msk_top_regs; - -architecture arch of msk_top_regs is - - type t_data_out is array (natural range<>) of std_logic_vector(C_DATA_WIDTH-1 downto 0) ; - - -- - signal reg_data_out_vect : t_data_out(36-1 downto 0); - signal reg_rd_stb : std_logic_vector(36-1 downto 0); - signal reg_wr_stb : std_logic_vector(36-1 downto 0); - signal reg_data_in : std_logic_vector(C_DATA_WIDTH-1 downto 0); - signal reg_data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0'); - -- - -begin - - ins_decoder_axi4l : entity work.msk_top_regs_decoder_axi4l - generic map ( - g_addr_width => C_ADDR_WIDTH, - g_data_width => C_DATA_WIDTH - ) - port map ( - pi_clock => pi_clock, - pi_reset => pi_reset, - - -- - po_reg_rd_stb => reg_rd_stb, - po_reg_wr_stb => reg_wr_stb, - po_reg_data => reg_data_in, - pi_reg_data => reg_data_out, - -- - -- - -- - -- - pi_s_reset => pi_s_reset, - pi_s_top => pi_s_top, - po_s_top => po_s_top - ); - -- - prs_reg_rd_mux: process(pi_clock) - begin - if rising_edge(pi_clock) then - for idx in 0 to 36-1 loop - if reg_rd_stb(idx) = '1' then - reg_data_out <= reg_data_out_vect(idx); - end if; - end loop; - end if; - end process prs_reg_rd_mux; - -- - -- - -- - - -- =========================================================================== - -- generated registers instances - -- --------------------------------------------------------------------------- - -- reg name: Hash_ID_Low reg type: msk_hash_lo - -- --------------------------------------------------------------------------- - blk_Hash_ID_Low : block - begin -- - inst_Hash_ID_Low: entity work.msk_top_regs_msk_hash_lo - port map( - pi_clock => pi_clock, - pi_reset => pi_reset, - -- to/from adapter - pi_decoder_rd_stb => reg_rd_stb(0), - pi_decoder_wr_stb => reg_wr_stb(0), - pi_decoder_data => reg_data_in, - po_decoder_data => reg_data_out_vect(0), - - pi_reg => pi_addrmap.Hash_ID_Low, - po_reg => po_addrmap.Hash_ID_Low - ); -- - end block; -- - -- --------------------------------------------------------------------------- - -- reg name: Hash_ID_High reg type: msk_hash_hi - -- --------------------------------------------------------------------------- - blk_Hash_ID_High : block - begin -- - inst_Hash_ID_High: entity work.msk_top_regs_msk_hash_hi - port map( - pi_clock => pi_clock, - pi_reset => pi_reset, - -- to/from adapter - pi_decoder_rd_stb => reg_rd_stb(1), - pi_decoder_wr_stb => reg_wr_stb(1), - pi_decoder_data => reg_data_in, - po_decoder_data => reg_data_out_vect(1), - - pi_reg => pi_addrmap.Hash_ID_High, - po_reg => po_addrmap.Hash_ID_High - ); -- - end block; -- - -- --------------------------------------------------------------------------- - -- reg name: MSK_Init reg type: msk_init - -- --------------------------------------------------------------------------- - blk_MSK_Init : block - begin -- - inst_MSK_Init: entity work.msk_top_regs_msk_init - port map( - pi_clock => pi_clock, - pi_reset => pi_reset, - -- to/from adapter - pi_decoder_rd_stb => reg_rd_stb(2), - pi_decoder_wr_stb => reg_wr_stb(2), - pi_decoder_data => reg_data_in, - po_decoder_data => reg_data_out_vect(2), - - pi_reg => pi_addrmap.MSK_Init, - po_reg => po_addrmap.MSK_Init - ); -- - end block; -- - -- --------------------------------------------------------------------------- - -- reg name: MSK_Control reg type: msk_ctrl - -- --------------------------------------------------------------------------- - blk_MSK_Control : block - begin -- - inst_MSK_Control: entity work.msk_top_regs_msk_ctrl - port map( - pi_clock => pi_clock, - pi_reset => pi_reset, - -- to/from adapter - pi_decoder_rd_stb => reg_rd_stb(3), - pi_decoder_wr_stb => reg_wr_stb(3), - pi_decoder_data => reg_data_in, - po_decoder_data => reg_data_out_vect(3), - - pi_reg => pi_addrmap.MSK_Control, - po_reg => po_addrmap.MSK_Control - ); -- - end block; -- - -- --------------------------------------------------------------------------- - -- reg name: MSK_Status reg type: msk_stat_0 - -- --------------------------------------------------------------------------- - blk_MSK_Status : block - begin -- - inst_MSK_Status: entity work.msk_top_regs_msk_stat_0 - port map( - pi_clock => pi_clock, - pi_reset => pi_reset, - -- to/from adapter - pi_decoder_rd_stb => reg_rd_stb(4), - pi_decoder_wr_stb => reg_wr_stb(4), - pi_decoder_data => reg_data_in, - po_decoder_data => reg_data_out_vect(4), - - pi_reg => pi_addrmap.MSK_Status, - po_reg => po_addrmap.MSK_Status - ); -- - end block; -- - -- --------------------------------------------------------------------------- - -- reg name: Tx_Bit_Count reg type: msk_stat_1 - -- --------------------------------------------------------------------------- - blk_Tx_Bit_Count : block - begin -- - inst_Tx_Bit_Count: entity work.msk_top_regs_msk_stat_1 - port map( - pi_clock => pi_clock, - pi_reset => pi_reset, - -- to/from adapter - pi_decoder_rd_stb => reg_rd_stb(5), - pi_decoder_wr_stb => reg_wr_stb(5), - pi_decoder_data => reg_data_in, - po_decoder_data => reg_data_out_vect(5), - - pi_reg => pi_addrmap.Tx_Bit_Count, - po_reg => po_addrmap.Tx_Bit_Count - ); -- - end block; -- - -- --------------------------------------------------------------------------- - -- reg name: Tx_Enable_Count reg type: msk_stat_2 - -- --------------------------------------------------------------------------- - blk_Tx_Enable_Count : block - begin -- - inst_Tx_Enable_Count: entity work.msk_top_regs_msk_stat_2 - port map( - pi_clock => pi_clock, - pi_reset => pi_reset, - -- to/from adapter - pi_decoder_rd_stb => reg_rd_stb(6), - pi_decoder_wr_stb => reg_wr_stb(6), - pi_decoder_data => reg_data_in, - po_decoder_data => reg_data_out_vect(6), - - pi_reg => pi_addrmap.Tx_Enable_Count, - po_reg => po_addrmap.Tx_Enable_Count - ); -- - end block; -- - -- --------------------------------------------------------------------------- - -- reg name: Fb_FreqWord reg type: config_nco_fw - -- --------------------------------------------------------------------------- - blk_Fb_FreqWord : block - begin -- - inst_Fb_FreqWord: entity work.msk_top_regs_config_nco_fw - port map( - pi_clock => pi_clock, - pi_reset => pi_reset, - -- to/from adapter - pi_decoder_rd_stb => reg_rd_stb(7), - pi_decoder_wr_stb => reg_wr_stb(7), - pi_decoder_data => reg_data_in, - po_decoder_data => reg_data_out_vect(7), - - pi_reg => pi_addrmap.Fb_FreqWord, - po_reg => po_addrmap.Fb_FreqWord - ); -- - end block; -- - -- --------------------------------------------------------------------------- - -- reg name: TX_F1_FreqWord reg type: config_nco_fw - -- --------------------------------------------------------------------------- - blk_TX_F1_FreqWord : block - begin -- - inst_TX_F1_FreqWord: entity work.msk_top_regs_config_nco_fw - port map( - pi_clock => pi_clock, - pi_reset => pi_reset, - -- to/from adapter - pi_decoder_rd_stb => reg_rd_stb(8), - pi_decoder_wr_stb => reg_wr_stb(8), - pi_decoder_data => reg_data_in, - po_decoder_data => reg_data_out_vect(8), - - pi_reg => pi_addrmap.TX_F1_FreqWord, - po_reg => po_addrmap.TX_F1_FreqWord - ); -- - end block; -- - -- --------------------------------------------------------------------------- - -- reg name: TX_F2_FreqWord reg type: config_nco_fw - -- --------------------------------------------------------------------------- - blk_TX_F2_FreqWord : block - begin -- - inst_TX_F2_FreqWord: entity work.msk_top_regs_config_nco_fw - port map( - pi_clock => pi_clock, - pi_reset => pi_reset, - -- to/from adapter - pi_decoder_rd_stb => reg_rd_stb(9), - pi_decoder_wr_stb => reg_wr_stb(9), - pi_decoder_data => reg_data_in, - po_decoder_data => reg_data_out_vect(9), - - pi_reg => pi_addrmap.TX_F2_FreqWord, - po_reg => po_addrmap.TX_F2_FreqWord - ); -- - end block; -- - -- --------------------------------------------------------------------------- - -- reg name: RX_F1_FreqWord reg type: config_nco_fw - -- --------------------------------------------------------------------------- - blk_RX_F1_FreqWord : block - begin -- - inst_RX_F1_FreqWord: entity work.msk_top_regs_config_nco_fw - port map( - pi_clock => pi_clock, - pi_reset => pi_reset, - -- to/from adapter - pi_decoder_rd_stb => reg_rd_stb(10), - pi_decoder_wr_stb => reg_wr_stb(10), - pi_decoder_data => reg_data_in, - po_decoder_data => reg_data_out_vect(10), - - pi_reg => pi_addrmap.RX_F1_FreqWord, - po_reg => po_addrmap.RX_F1_FreqWord - ); -- - end block; -- - -- --------------------------------------------------------------------------- - -- reg name: RX_F2_FreqWord reg type: config_nco_fw - -- --------------------------------------------------------------------------- - blk_RX_F2_FreqWord : block - begin -- - inst_RX_F2_FreqWord: entity work.msk_top_regs_config_nco_fw - port map( - pi_clock => pi_clock, - pi_reset => pi_reset, - -- to/from adapter - pi_decoder_rd_stb => reg_rd_stb(11), - pi_decoder_wr_stb => reg_wr_stb(11), - pi_decoder_data => reg_data_in, - po_decoder_data => reg_data_out_vect(11), - - pi_reg => pi_addrmap.RX_F2_FreqWord, - po_reg => po_addrmap.RX_F2_FreqWord - ); -- - end block; -- - -- --------------------------------------------------------------------------- - -- reg name: LPF_Config_0 reg type: lpf_config_0 - -- --------------------------------------------------------------------------- - blk_LPF_Config_0 : block - begin -- - inst_LPF_Config_0: entity work.msk_top_regs_lpf_config_0 - port map( - pi_clock => pi_clock, - pi_reset => pi_reset, - -- to/from adapter - pi_decoder_rd_stb => reg_rd_stb(12), - pi_decoder_wr_stb => reg_wr_stb(12), - pi_decoder_data => reg_data_in, - po_decoder_data => reg_data_out_vect(12), - - pi_reg => pi_addrmap.LPF_Config_0, - po_reg => po_addrmap.LPF_Config_0 - ); -- - end block; -- - -- --------------------------------------------------------------------------- - -- reg name: LPF_Config_1 reg type: lpf_config_1 - -- --------------------------------------------------------------------------- - blk_LPF_Config_1 : block - begin -- - inst_LPF_Config_1: entity work.msk_top_regs_lpf_config_1 - port map( - pi_clock => pi_clock, - pi_reset => pi_reset, - -- to/from adapter - pi_decoder_rd_stb => reg_rd_stb(13), - pi_decoder_wr_stb => reg_wr_stb(13), - pi_decoder_data => reg_data_in, - po_decoder_data => reg_data_out_vect(13), - - pi_reg => pi_addrmap.LPF_Config_1, - po_reg => po_addrmap.LPF_Config_1 - ); -- - end block; -- - -- --------------------------------------------------------------------------- - -- reg name: Tx_Data_Width reg type: data_width - -- --------------------------------------------------------------------------- - blk_Tx_Data_Width : block - begin -- - inst_Tx_Data_Width: entity work.msk_top_regs_data_width - port map( - pi_clock => pi_clock, - pi_reset => pi_reset, - -- to/from adapter - pi_decoder_rd_stb => reg_rd_stb(14), - pi_decoder_wr_stb => reg_wr_stb(14), - pi_decoder_data => reg_data_in, - po_decoder_data => reg_data_out_vect(14), - - pi_reg => pi_addrmap.Tx_Data_Width, - po_reg => po_addrmap.Tx_Data_Width - ); -- - end block; -- - -- --------------------------------------------------------------------------- - -- reg name: Rx_Data_Width reg type: data_width - -- --------------------------------------------------------------------------- - blk_Rx_Data_Width : block - begin -- - inst_Rx_Data_Width: entity work.msk_top_regs_data_width - port map( - pi_clock => pi_clock, - pi_reset => pi_reset, - -- to/from adapter - pi_decoder_rd_stb => reg_rd_stb(15), - pi_decoder_wr_stb => reg_wr_stb(15), - pi_decoder_data => reg_data_in, - po_decoder_data => reg_data_out_vect(15), - - pi_reg => pi_addrmap.Rx_Data_Width, - po_reg => po_addrmap.Rx_Data_Width - ); -- - end block; -- - -- --------------------------------------------------------------------------- - -- reg name: PRBS_Control reg type: prbs_ctrl - -- --------------------------------------------------------------------------- - blk_PRBS_Control : block - begin -- - inst_PRBS_Control: entity work.msk_top_regs_prbs_ctrl - port map( - pi_clock => pi_clock, - pi_reset => pi_reset, - -- to/from adapter - pi_decoder_rd_stb => reg_rd_stb(16), - pi_decoder_wr_stb => reg_wr_stb(16), - pi_decoder_data => reg_data_in, - po_decoder_data => reg_data_out_vect(16), - - pi_reg => pi_addrmap.PRBS_Control, - po_reg => po_addrmap.PRBS_Control - ); -- - end block; -- - -- --------------------------------------------------------------------------- - -- reg name: PRBS_Initial_State reg type: config_prbs_seed - -- --------------------------------------------------------------------------- - blk_PRBS_Initial_State : block - begin -- - inst_PRBS_Initial_State: entity work.msk_top_regs_config_prbs_seed - port map( - pi_clock => pi_clock, - pi_reset => pi_reset, - -- to/from adapter - pi_decoder_rd_stb => reg_rd_stb(17), - pi_decoder_wr_stb => reg_wr_stb(17), - pi_decoder_data => reg_data_in, - po_decoder_data => reg_data_out_vect(17), - - pi_reg => pi_addrmap.PRBS_Initial_State, - po_reg => po_addrmap.PRBS_Initial_State - ); -- - end block; -- - -- --------------------------------------------------------------------------- - -- reg name: PRBS_Polynomial reg type: config_prbs_poly - -- --------------------------------------------------------------------------- - blk_PRBS_Polynomial : block - begin -- - inst_PRBS_Polynomial: entity work.msk_top_regs_config_prbs_poly - port map( - pi_clock => pi_clock, - pi_reset => pi_reset, - -- to/from adapter - pi_decoder_rd_stb => reg_rd_stb(18), - pi_decoder_wr_stb => reg_wr_stb(18), - pi_decoder_data => reg_data_in, - po_decoder_data => reg_data_out_vect(18), - - pi_reg => pi_addrmap.PRBS_Polynomial, - po_reg => po_addrmap.PRBS_Polynomial - ); -- - end block; -- - -- --------------------------------------------------------------------------- - -- reg name: PRBS_Error_Mask reg type: config_prbs_errmask - -- --------------------------------------------------------------------------- - blk_PRBS_Error_Mask : block - begin -- - inst_PRBS_Error_Mask: entity work.msk_top_regs_config_prbs_errmask - port map( - pi_clock => pi_clock, - pi_reset => pi_reset, - -- to/from adapter - pi_decoder_rd_stb => reg_rd_stb(19), - pi_decoder_wr_stb => reg_wr_stb(19), - pi_decoder_data => reg_data_in, - po_decoder_data => reg_data_out_vect(19), - - pi_reg => pi_addrmap.PRBS_Error_Mask, - po_reg => po_addrmap.PRBS_Error_Mask - ); -- - end block; -- - -- --------------------------------------------------------------------------- - -- reg name: PRBS_Bit_Count reg type: stat_32_bits - -- --------------------------------------------------------------------------- - blk_PRBS_Bit_Count : block - begin -- - inst_PRBS_Bit_Count: entity work.msk_top_regs_stat_32_bits - port map( - pi_clock => pi_clock, - pi_reset => pi_reset, - -- to/from adapter - pi_decoder_rd_stb => reg_rd_stb(20), - pi_decoder_wr_stb => reg_wr_stb(20), - pi_decoder_data => reg_data_in, - po_decoder_data => reg_data_out_vect(20), - - pi_reg => pi_addrmap.PRBS_Bit_Count, - po_reg => po_addrmap.PRBS_Bit_Count - ); -- - end block; -- - -- --------------------------------------------------------------------------- - -- reg name: PRBS_Error_Count reg type: stat_32_errs - -- --------------------------------------------------------------------------- - blk_PRBS_Error_Count : block - begin -- - inst_PRBS_Error_Count: entity work.msk_top_regs_stat_32_errs - port map( - pi_clock => pi_clock, - pi_reset => pi_reset, - -- to/from adapter - pi_decoder_rd_stb => reg_rd_stb(21), - pi_decoder_wr_stb => reg_wr_stb(21), - pi_decoder_data => reg_data_in, - po_decoder_data => reg_data_out_vect(21), - - pi_reg => pi_addrmap.PRBS_Error_Count, - po_reg => po_addrmap.PRBS_Error_Count - ); -- - end block; -- - -- --------------------------------------------------------------------------- - -- reg name: LPF_Accum_F1 reg type: stat_32_lpf_acc - -- --------------------------------------------------------------------------- - blk_LPF_Accum_F1 : block - begin -- - inst_LPF_Accum_F1: entity work.msk_top_regs_stat_32_lpf_acc - port map( - pi_clock => pi_clock, - pi_reset => pi_reset, - -- to/from adapter - pi_decoder_rd_stb => reg_rd_stb(22), - pi_decoder_wr_stb => reg_wr_stb(22), - pi_decoder_data => reg_data_in, - po_decoder_data => reg_data_out_vect(22), - - pi_reg => pi_addrmap.LPF_Accum_F1, - po_reg => po_addrmap.LPF_Accum_F1 - ); -- - end block; -- - -- --------------------------------------------------------------------------- - -- reg name: LPF_Accum_F2 reg type: stat_32_lpf_acc - -- --------------------------------------------------------------------------- - blk_LPF_Accum_F2 : block - begin -- - inst_LPF_Accum_F2: entity work.msk_top_regs_stat_32_lpf_acc - port map( - pi_clock => pi_clock, - pi_reset => pi_reset, - -- to/from adapter - pi_decoder_rd_stb => reg_rd_stb(23), - pi_decoder_wr_stb => reg_wr_stb(23), - pi_decoder_data => reg_data_in, - po_decoder_data => reg_data_out_vect(23), - - pi_reg => pi_addrmap.LPF_Accum_F2, - po_reg => po_addrmap.LPF_Accum_F2 - ); -- - end block; -- - -- --------------------------------------------------------------------------- - -- reg name: axis_xfer_count reg type: msk_stat_3 - -- --------------------------------------------------------------------------- - blk_axis_xfer_count : block - begin -- - inst_axis_xfer_count: entity work.msk_top_regs_msk_stat_3 - port map( - pi_clock => pi_clock, - pi_reset => pi_reset, - -- to/from adapter - pi_decoder_rd_stb => reg_rd_stb(24), - pi_decoder_wr_stb => reg_wr_stb(24), - pi_decoder_data => reg_data_in, - po_decoder_data => reg_data_out_vect(24), - - pi_reg => pi_addrmap.axis_xfer_count, - po_reg => po_addrmap.axis_xfer_count - ); -- - end block; -- - -- --------------------------------------------------------------------------- - -- reg name: Rx_Sample_Discard reg type: rx_sample_discard - -- --------------------------------------------------------------------------- - blk_Rx_Sample_Discard : block - begin -- - inst_Rx_Sample_Discard: entity work.msk_top_regs_rx_sample_discard - port map( - pi_clock => pi_clock, - pi_reset => pi_reset, - -- to/from adapter - pi_decoder_rd_stb => reg_rd_stb(25), - pi_decoder_wr_stb => reg_wr_stb(25), - pi_decoder_data => reg_data_in, - po_decoder_data => reg_data_out_vect(25), - - pi_reg => pi_addrmap.Rx_Sample_Discard, - po_reg => po_addrmap.Rx_Sample_Discard - ); -- - end block; -- - -- --------------------------------------------------------------------------- - -- reg name: LPF_Config_2 reg type: lpf_config_2 - -- --------------------------------------------------------------------------- - blk_LPF_Config_2 : block - begin -- - inst_LPF_Config_2: entity work.msk_top_regs_lpf_config_2 - port map( - pi_clock => pi_clock, - pi_reset => pi_reset, - -- to/from adapter - pi_decoder_rd_stb => reg_rd_stb(26), - pi_decoder_wr_stb => reg_wr_stb(26), - pi_decoder_data => reg_data_in, - po_decoder_data => reg_data_out_vect(26), - - pi_reg => pi_addrmap.LPF_Config_2, - po_reg => po_addrmap.LPF_Config_2 - ); -- - end block; -- - -- --------------------------------------------------------------------------- - -- reg name: f1_nco_adjust reg type: observation_data - -- --------------------------------------------------------------------------- - blk_f1_nco_adjust : block - begin -- - inst_f1_nco_adjust: entity work.msk_top_regs_observation_data - port map( - pi_clock => pi_clock, - pi_reset => pi_reset, - -- to/from adapter - pi_decoder_rd_stb => reg_rd_stb(27), - pi_decoder_wr_stb => reg_wr_stb(27), - pi_decoder_data => reg_data_in, - po_decoder_data => reg_data_out_vect(27), - - pi_reg => pi_addrmap.f1_nco_adjust, - po_reg => po_addrmap.f1_nco_adjust - ); -- - end block; -- - -- --------------------------------------------------------------------------- - -- reg name: f2_nco_adjust reg type: observation_data - -- --------------------------------------------------------------------------- - blk_f2_nco_adjust : block - begin -- - inst_f2_nco_adjust: entity work.msk_top_regs_observation_data - port map( - pi_clock => pi_clock, - pi_reset => pi_reset, - -- to/from adapter - pi_decoder_rd_stb => reg_rd_stb(28), - pi_decoder_wr_stb => reg_wr_stb(28), - pi_decoder_data => reg_data_in, - po_decoder_data => reg_data_out_vect(28), - - pi_reg => pi_addrmap.f2_nco_adjust, - po_reg => po_addrmap.f2_nco_adjust - ); -- - end block; -- - -- --------------------------------------------------------------------------- - -- reg name: f1_error reg type: observation_data - -- --------------------------------------------------------------------------- - blk_f1_error : block - begin -- - inst_f1_error: entity work.msk_top_regs_observation_data - port map( - pi_clock => pi_clock, - pi_reset => pi_reset, - -- to/from adapter - pi_decoder_rd_stb => reg_rd_stb(29), - pi_decoder_wr_stb => reg_wr_stb(29), - pi_decoder_data => reg_data_in, - po_decoder_data => reg_data_out_vect(29), - - pi_reg => pi_addrmap.f1_error, - po_reg => po_addrmap.f1_error - ); -- - end block; -- - -- --------------------------------------------------------------------------- - -- reg name: f2_error reg type: observation_data - -- --------------------------------------------------------------------------- - blk_f2_error : block - begin -- - inst_f2_error: entity work.msk_top_regs_observation_data - port map( - pi_clock => pi_clock, - pi_reset => pi_reset, - -- to/from adapter - pi_decoder_rd_stb => reg_rd_stb(30), - pi_decoder_wr_stb => reg_wr_stb(30), - pi_decoder_data => reg_data_in, - po_decoder_data => reg_data_out_vect(30), - - pi_reg => pi_addrmap.f2_error, - po_reg => po_addrmap.f2_error - ); -- - end block; -- - -- --------------------------------------------------------------------------- - -- reg name: Tx_Sync_Ctrl reg type: tx_sync_ctrl - -- --------------------------------------------------------------------------- - blk_Tx_Sync_Ctrl : block - begin -- - inst_Tx_Sync_Ctrl: entity work.msk_top_regs_tx_sync_ctrl - port map( - pi_clock => pi_clock, - pi_reset => pi_reset, - -- to/from adapter - pi_decoder_rd_stb => reg_rd_stb(31), - pi_decoder_wr_stb => reg_wr_stb(31), - pi_decoder_data => reg_data_in, - po_decoder_data => reg_data_out_vect(31), - - pi_reg => pi_addrmap.Tx_Sync_Ctrl, - po_reg => po_addrmap.Tx_Sync_Ctrl - ); -- - end block; -- - -- --------------------------------------------------------------------------- - -- reg name: Tx_Sync_Cnt reg type: tx_sync_cnt - -- --------------------------------------------------------------------------- - blk_Tx_Sync_Cnt : block - begin -- - inst_Tx_Sync_Cnt: entity work.msk_top_regs_tx_sync_cnt - port map( - pi_clock => pi_clock, - pi_reset => pi_reset, - -- to/from adapter - pi_decoder_rd_stb => reg_rd_stb(32), - pi_decoder_wr_stb => reg_wr_stb(32), - pi_decoder_data => reg_data_in, - po_decoder_data => reg_data_out_vect(32), - - pi_reg => pi_addrmap.Tx_Sync_Cnt, - po_reg => po_addrmap.Tx_Sync_Cnt - ); -- - end block; -- - -- --------------------------------------------------------------------------- - -- reg name: lowpass_ema_alpha1 reg type: lowpass_ema_alpha - -- --------------------------------------------------------------------------- - blk_lowpass_ema_alpha1 : block - begin -- - inst_lowpass_ema_alpha1: entity work.msk_top_regs_lowpass_ema_alpha - port map( - pi_clock => pi_clock, - pi_reset => pi_reset, - -- to/from adapter - pi_decoder_rd_stb => reg_rd_stb(33), - pi_decoder_wr_stb => reg_wr_stb(33), - pi_decoder_data => reg_data_in, - po_decoder_data => reg_data_out_vect(33), - - pi_reg => pi_addrmap.lowpass_ema_alpha1, - po_reg => po_addrmap.lowpass_ema_alpha1 - ); -- - end block; -- - -- --------------------------------------------------------------------------- - -- reg name: lowpass_ema_alpha2 reg type: lowpass_ema_alpha - -- --------------------------------------------------------------------------- - blk_lowpass_ema_alpha2 : block - begin -- - inst_lowpass_ema_alpha2: entity work.msk_top_regs_lowpass_ema_alpha - port map( - pi_clock => pi_clock, - pi_reset => pi_reset, - -- to/from adapter - pi_decoder_rd_stb => reg_rd_stb(34), - pi_decoder_wr_stb => reg_wr_stb(34), - pi_decoder_data => reg_data_in, - po_decoder_data => reg_data_out_vect(34), - - pi_reg => pi_addrmap.lowpass_ema_alpha2, - po_reg => po_addrmap.lowpass_ema_alpha2 - ); -- - end block; -- - -- --------------------------------------------------------------------------- - -- reg name: rx_power reg type: rx_power - -- --------------------------------------------------------------------------- - blk_rx_power : block - begin -- - inst_rx_power: entity work.msk_top_regs_rx_power - port map( - pi_clock => pi_clock, - pi_reset => pi_reset, - -- to/from adapter - pi_decoder_rd_stb => reg_rd_stb(35), - pi_decoder_wr_stb => reg_wr_stb(35), - pi_decoder_data => reg_data_in, - po_decoder_data => reg_data_out_vect(35), - - pi_reg => pi_addrmap.rx_power, - po_reg => po_addrmap.rx_power - ); -- - end block; -- - - -- =========================================================================== - -- generated registers instances in regfiles - - -- =========================================================================== - -- Generated Mem Instances - -- - -- --------------------------------------------------------------------------- - - -- =========================================================================== - -- External Busses - -end architecture; diff --git a/rdl/vhdl/msk_top_regs/msk_top_regs_decoder_axi4l.vhd b/rdl/vhdl/msk_top_regs/msk_top_regs_decoder_axi4l.vhd deleted file mode 100644 index 6a4f008..0000000 --- a/rdl/vhdl/msk_top_regs/msk_top_regs_decoder_axi4l.vhd +++ /dev/null @@ -1,536 +0,0 @@ ------------------------------------------------------------------------------- --- ____ _____________ __ -- --- / __ \/ ____/ ___/\ \/ / _ _ _ -- --- / / / / __/ \__ \ \ / / \ / \ / \ -- --- / /_/ / /___ ___/ / / / = ( M | S | K )= -- --- /_____/_____//____/ /_/ \_/ \_/ \_/ -- --- -- ------------------------------------------------------------------------------- ---! @copyright Copyright 2020-2022 DESY ---! SPDX-License-Identifier: Apache-2.0 ------------------------------------------------------------------------------- ---! @date 2020-05-25/2021-10-12 ---! @author Lukasz Butkowski ---! @author Michael Büchler ------------------------------------------------------------------------------- ---! @brief ---! ax4-lite address decoder for DesyRdl ------------------------------------------------------------------------------- - - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library desyrdl; -use desyrdl.common.all; - -entity msk_top_regs_decoder_axi4l is - generic ( - G_ADDR_WIDTH : integer := 32; - G_DATA_WIDTH : integer := 32 - ); - port ( - pi_clock : in std_logic; - pi_reset : in std_logic; - -- - po_reg_rd_stb : out std_logic_vector(36-1 downto 0); - po_reg_wr_stb : out std_logic_vector(36-1 downto 0); - po_reg_data : out std_logic_vector(G_DATA_WIDTH-1 downto 0); - pi_reg_data : in std_logic_vector(G_DATA_WIDTH-1 downto 0); - -- - -- - -- - -- - pi_s_reset : in std_logic; - pi_s_top : in t_axi4l_m2s ; - po_s_top : out t_axi4l_s2m -); -end entity msk_top_regs_decoder_axi4l; - -architecture arch of msk_top_regs_decoder_axi4l is - - type t_target is (REG, NONE ); - - signal rtarget, wtarget : t_target := NONE; - - -- Standard statements - --- INLINE statement with -- # - ---------------------------------------------------------- - -- read - type t_state_read is ( - ST_READ_IDLE, - ST_READ_SELECT, - ST_READ_VALID, - ST_READ_REG_BUSY, -- when no address hit, dummy reg - ST_READ_DONE - ); - signal state_read : t_state_read; - - signal rdata_reg : std_logic_vector(G_DATA_WIDTH-1 downto 0); - signal rdata_rgf : std_logic_vector(G_DATA_WIDTH-1 downto 0); - signal rdata_mem : std_logic_vector(G_DATA_WIDTH-1 downto 0); - signal rdata_ext : std_logic_vector(G_DATA_WIDTH-1 downto 0); - - signal rdata : std_logic_vector(G_DATA_WIDTH-1 downto 0) := (others => '0'); - signal raddr : std_logic_vector(G_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal raddr_int : integer; - - ---------------------------------------------------------- - -- write - type t_state_write is ( - ST_WRITE_IDLE, - ST_WRITE_WAIT_DATA, - ST_WRITE_WAIT_ADDR, - ST_WRITE_SELECT, - ST_WRITE_RESP - ); - signal state_write : t_state_write; - - signal wdata : std_logic_vector(G_DATA_WIDTH-1 downto 0) := (others => '0'); - signal wstrb : std_logic_vector(G_DATA_WIDTH/8-1 downto 0) := (others => '0'); - signal waddr : std_logic_vector(G_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal waddr_int : integer; - signal wvalid : std_logic; - - ----------------------------------------------------------- - signal reg_rd_stb : std_logic_vector(36-1 downto 0) := (others => '0'); - signal reg_wr_stb : std_logic_vector(36-1 downto 0) := (others => '0'); - - -- external bus - - constant read_timeout : natural := 8191; - constant write_timeout : natural := 8191; - signal read_time_cnt : natural := 0; - signal write_time_cnt : natural := 0; - signal invalid_rdata : std_logic ; - - signal reset : std_logic; -begin - - -- main reset - global or bus reset - reset <= pi_reset or pi_s_reset; - - -- =========================================================================== - -- ### read logic - ------------------------------------------------------------------------------ - -- read channel state machine - ------------------------------------------------------------------------------ - prs_state_read: process (pi_clock) - begin - if rising_edge(pi_clock) then - if reset = '1' then - state_read <= ST_READ_IDLE; - invalid_rdata <= '0'; - else - case state_read is - when ST_READ_IDLE => - - if pi_s_top.arvalid = '1' then - state_read <= ST_READ_SELECT; - end if; - invalid_rdata <= '0'; - when ST_READ_SELECT => - case rtarget is - when REG => - state_read <= ST_READ_VALID; - when others => - state_read <= ST_READ_REG_BUSY; - end case; - - when ST_READ_REG_BUSY => - state_read <= ST_READ_VALID; - - when ST_READ_VALID => - if pi_s_top.rready = '1' then - state_read <= ST_READ_DONE; - end if; - - when ST_READ_DONE => - state_read <= ST_READ_IDLE; - - when others => - state_read <= ST_READ_IDLE; - - end case; - - end if; - end if; - end process; - po_s_top.rresp <= "00"; - ------------------------------------------------------------------------------ - -- read data mux - prs_rdata_mux: process(rtarget,rdata_reg,invalid_rdata) - begin - if invalid_rdata = '1' then - po_s_top.rdata <= (others => '0' ) ; - elsif rtarget = REG then - po_s_top.rdata <= rdata_reg ; - else - po_s_top.rdata <= (others => '0' ) ; - end if; - end process prs_rdata_mux; - - ------------------------------------------------------------------------------ - -- ARREADY flag handling - prs_axi_arready: process (state_read) - begin - case state_read is - when ST_READ_IDLE => - po_s_top.arready <= '1'; - when others => - po_s_top.arready <= '0'; - end case; - end process; - - -- RVALID flag handling - prs_axi_rvalid: process ( - state_read) - begin - case state_read is - when ST_READ_VALID => - po_s_top.rvalid <= '1'; - when others => - po_s_top.rvalid <= '0'; - end case; - end process; - - ------------------------------------------------------------------------------ - -- Address decoder - ------------------------------------------------------------------------------ - raddr_int <= to_integer(unsigned(pi_s_top.araddr(G_ADDR_WIDTH-1 downto 0))); - - prs_raddr_decoder: process(pi_clock) - begin - if rising_edge(pi_clock) then - if state_read = ST_READ_IDLE and pi_s_top.arvalid = '1' then - reg_rd_stb <= (others => '0'); - case raddr_int is - when 0 => - rtarget <= REG; - reg_rd_stb(0) <= '1'; - when 4 => - rtarget <= REG; - reg_rd_stb(1) <= '1'; - when 8 => - rtarget <= REG; - reg_rd_stb(2) <= '1'; - when 12 => - rtarget <= REG; - reg_rd_stb(3) <= '1'; - when 16 => - rtarget <= REG; - reg_rd_stb(4) <= '1'; - when 20 => - rtarget <= REG; - reg_rd_stb(5) <= '1'; - when 24 => - rtarget <= REG; - reg_rd_stb(6) <= '1'; - when 28 => - rtarget <= REG; - reg_rd_stb(7) <= '1'; - when 32 => - rtarget <= REG; - reg_rd_stb(8) <= '1'; - when 36 => - rtarget <= REG; - reg_rd_stb(9) <= '1'; - when 40 => - rtarget <= REG; - reg_rd_stb(10) <= '1'; - when 44 => - rtarget <= REG; - reg_rd_stb(11) <= '1'; - when 48 => - rtarget <= REG; - reg_rd_stb(12) <= '1'; - when 52 => - rtarget <= REG; - reg_rd_stb(13) <= '1'; - when 56 => - rtarget <= REG; - reg_rd_stb(14) <= '1'; - when 60 => - rtarget <= REG; - reg_rd_stb(15) <= '1'; - when 64 => - rtarget <= REG; - reg_rd_stb(16) <= '1'; - when 68 => - rtarget <= REG; - reg_rd_stb(17) <= '1'; - when 72 => - rtarget <= REG; - reg_rd_stb(18) <= '1'; - when 76 => - rtarget <= REG; - reg_rd_stb(19) <= '1'; - when 80 => - rtarget <= REG; - reg_rd_stb(20) <= '1'; - when 84 => - rtarget <= REG; - reg_rd_stb(21) <= '1'; - when 88 => - rtarget <= REG; - reg_rd_stb(22) <= '1'; - when 92 => - rtarget <= REG; - reg_rd_stb(23) <= '1'; - when 96 => - rtarget <= REG; - reg_rd_stb(24) <= '1'; - when 100 => - rtarget <= REG; - reg_rd_stb(25) <= '1'; - when 104 => - rtarget <= REG; - reg_rd_stb(26) <= '1'; - when 108 => - rtarget <= REG; - reg_rd_stb(27) <= '1'; - when 112 => - rtarget <= REG; - reg_rd_stb(28) <= '1'; - when 116 => - rtarget <= REG; - reg_rd_stb(29) <= '1'; - when 120 => - rtarget <= REG; - reg_rd_stb(30) <= '1'; - when 124 => - rtarget <= REG; - reg_rd_stb(31) <= '1'; - when 128 => - rtarget <= REG; - reg_rd_stb(32) <= '1'; - when 132 => - rtarget <= REG; - reg_rd_stb(33) <= '1'; - when 136 => - rtarget <= REG; - reg_rd_stb(34) <= '1'; - when 140 => - rtarget <= REG; - reg_rd_stb(35) <= '1'; - when others => - rtarget <= NONE; - end case; - - elsif state_read = ST_READ_DONE then - reg_rd_stb <= (others => '0'); - - end if; - end if; - end process prs_raddr_decoder; - ---------------------------------------------------------- - -- - - -- =========================================================================== - -- ### write logic - ------------------------------------------------------------------------------ - -- Write channel state machine - ------------------------------------------------------------------------------ - prs_state_write: process (pi_clock) - begin - if rising_edge (pi_clock) then - if reset = '1' then - state_write <= ST_WRITE_IDLE; - else - case state_write is - when ST_WRITE_IDLE => - - if pi_s_top.awvalid = '1' and pi_s_top.wvalid = '1' then - state_write <= ST_WRITE_SELECT; - elsif pi_s_top.awvalid = '1' and pi_s_top.wvalid = '0' then - state_write <= ST_WRITE_WAIT_DATA; - elsif pi_s_top.awvalid = '0' and pi_s_top.wvalid = '1' then - state_write <= ST_WRITE_WAIT_ADDR; - end if; - - when ST_WRITE_WAIT_DATA => - if pi_s_top.wvalid = '1' then - state_write <= ST_WRITE_SELECT; - end if; - - when ST_WRITE_WAIT_ADDR => - if pi_s_top.awvalid = '1' then - state_write <= ST_WRITE_SELECT; - end if; - - when ST_WRITE_SELECT => - case wtarget is - when REG => - state_write <= ST_WRITE_RESP; - when others => - state_write <= ST_WRITE_RESP; -- every write transaction must end with response - end case; - - when ST_WRITE_RESP => - if pi_s_top.bready = '1' then - state_write <= ST_WRITE_IDLE; - end if; - - when others => - state_write <= ST_WRITE_IDLE; - - end case; - end if; - end if; - end process; - - ------------------------------------------------------------------------------ - -- WRITE AXI handshaking - po_s_top.bresp <= "00"; - - prs_axi_bvalid: process (state_write) - begin - case state_write is - when ST_WRITE_RESP => - po_s_top.bvalid <= '1'; - when others => - po_s_top.bvalid <= '0'; - end case; - end process; - - prs_axi_awready: process (state_write) - begin - case state_write is - when ST_WRITE_IDLE | ST_WRITE_WAIT_ADDR => - po_s_top.awready <= '1'; - when others => - po_s_top.awready <= '0'; - end case; - end process; - - prs_axi_wready: process (state_write) - begin - case state_write is - when ST_WRITE_IDLE | ST_WRITE_WAIT_DATA => - po_s_top.wready <= '1'; - when others => - po_s_top.wready <= '0'; - end case; - end process; - - ------------------------------------------------------------------------------ - -- write Address decoder - ------------------------------------------------------------------------------ - waddr_int <= to_integer(unsigned(pi_s_top.awaddr(G_ADDR_WIDTH-1 downto 0))); - - prs_waddr_decoder: process(pi_clock) - begin - if rising_edge(pi_clock) then - if (state_write = ST_WRITE_IDLE or state_write = ST_WRITE_WAIT_ADDR ) and pi_s_top.awvalid = '1' then - reg_wr_stb <= (others => '0'); - case waddr_int is - when 8 => - wtarget <= REG; - reg_wr_stb(2) <= '1'; - when 12 => - wtarget <= REG; - reg_wr_stb(3) <= '1'; - when 28 => - wtarget <= REG; - reg_wr_stb(7) <= '1'; - when 32 => - wtarget <= REG; - reg_wr_stb(8) <= '1'; - when 36 => - wtarget <= REG; - reg_wr_stb(9) <= '1'; - when 40 => - wtarget <= REG; - reg_wr_stb(10) <= '1'; - when 44 => - wtarget <= REG; - reg_wr_stb(11) <= '1'; - when 48 => - wtarget <= REG; - reg_wr_stb(12) <= '1'; - when 52 => - wtarget <= REG; - reg_wr_stb(13) <= '1'; - when 56 => - wtarget <= REG; - reg_wr_stb(14) <= '1'; - when 60 => - wtarget <= REG; - reg_wr_stb(15) <= '1'; - when 64 => - wtarget <= REG; - reg_wr_stb(16) <= '1'; - when 68 => - wtarget <= REG; - reg_wr_stb(17) <= '1'; - when 72 => - wtarget <= REG; - reg_wr_stb(18) <= '1'; - when 76 => - wtarget <= REG; - reg_wr_stb(19) <= '1'; - when 100 => - wtarget <= REG; - reg_wr_stb(25) <= '1'; - when 104 => - wtarget <= REG; - reg_wr_stb(26) <= '1'; - when 124 => - wtarget <= REG; - reg_wr_stb(31) <= '1'; - when 128 => - wtarget <= REG; - reg_wr_stb(32) <= '1'; - when 132 => - wtarget <= REG; - reg_wr_stb(33) <= '1'; - when 136 => - wtarget <= REG; - reg_wr_stb(34) <= '1'; - when others => - wtarget <= NONE; - end case; - - elsif state_write = ST_WRITE_RESP then - reg_wr_stb <= (others => '0'); - end if; - end if; - end process prs_waddr_decoder; - ---------------------------------------------------------- - -- - - prs_wvalid_reg : process(pi_clock) - begin - if rising_edge(pi_clock) then - if state_write = ST_WRITE_IDLE or state_write = ST_WRITE_WAIT_DATA then - wvalid <= pi_s_top.wvalid; - elsif state_write = ST_WRITE_RESP then - wvalid <= '0'; - end if; - end if; - end process; - - prs_wdata_reg : process(pi_clock) - begin - if rising_edge(pi_clock) then - if state_write = ST_WRITE_IDLE or state_write = ST_WRITE_WAIT_DATA then - wdata <= pi_s_top.wdata; - end if; - end if; - end process prs_wdata_reg ; - - -- =========================================================================== - -- OUTPUT - -- =========================================================================== - -- registers - ------------------------------------------------------------------------------ - gen_reg_wr_str: for ridx in 0 to 36-1 generate - po_reg_wr_stb(ridx) <= reg_wr_stb(ridx) and wvalid; - end generate; - po_reg_data <= wdata; - po_reg_rd_stb <= reg_rd_stb; - rdata_reg <= pi_reg_data ; - -end architecture arch; diff --git a/rdl/vhdl/msk_top_regs/pkg_msk_top_regs.vhd b/rdl/vhdl/msk_top_regs/pkg_msk_top_regs.vhd deleted file mode 100644 index 42ebf24..0000000 --- a/rdl/vhdl/msk_top_regs/pkg_msk_top_regs.vhd +++ /dev/null @@ -1,3394 +0,0 @@ ------------------------------------------------------------------------------- --- ____ _____________ __ -- --- / __ \/ ____/ ___/\ \/ / _ _ _ -- --- / / / / __/ \__ \ \ / / \ / \ / \ -- --- / /_/ / /___ ___/ / / / = ( M | S | K )= -- --- /_____/_____//____/ /_/ \_/ \_/ \_/ -- --- -- ------------------------------------------------------------------------------- ---! @copyright Copyright 2021-2022 DESY ---! SPDX-License-Identifier: Apache-2.0 ------------------------------------------------------------------------------- ---! @date 2021-10-01 ---! @author Michael Büchler ---! @author Lukasz Butkowski ------------------------------------------------------------------------------- ---! @brief ---! VHDL package of DesyRDL for address space decoder for msk_top_regs ------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library desyrdl; -use desyrdl.common.all; - --- library desy; --- use desy.common_axi.all; - -package pkg_msk_top_regs is - - ----------------------------------------------- - -- per addrmap / module - ----------------------------------------------- - constant C_ADDR_WIDTH : integer := 8; - constant C_DATA_WIDTH : integer := 32; - - -- =========================================================================== - -- --------------------------------------------------------------------------- - -- registers - -- --------------------------------------------------------------------------- - - -- =========================================================================== - -- REGISTERS interface - -- --------------------------------------------------------------------------- - -- register type: msk_hash_lo - ----------------------------------------------- - type t_field_signals_msk_hash_lo_hash_id_lo_in is record - -- no data if field cannot be written from hw - data : std_logic_vector(-1 downto 0); -- - end record; - - type t_field_signals_msk_hash_lo_hash_id_lo_out is record - -- no data if field cannot be written from hw - dummy : std_logic; -- - end record; -- - - -- The actual register types - type t_reg_msk_hash_lo_in is record-- - hash_id_lo : t_field_signals_msk_hash_lo_hash_id_lo_in; -- - end record; - type t_reg_msk_hash_lo_out is record-- - hash_id_lo : t_field_signals_msk_hash_lo_hash_id_lo_out; -- - end record; - type t_reg_msk_hash_lo_2d_in is array (integer range <>) of t_reg_msk_hash_lo_in; - type t_reg_msk_hash_lo_2d_out is array (integer range <>) of t_reg_msk_hash_lo_out; - type t_reg_msk_hash_lo_3d_in is array (integer range <>, integer range <>) of t_reg_msk_hash_lo_in; - type t_reg_msk_hash_lo_3d_out is array (integer range <>, integer range <>) of t_reg_msk_hash_lo_out; - ----------------------------------------------- - -- register type: msk_hash_hi - ----------------------------------------------- - type t_field_signals_msk_hash_hi_hash_id_hi_in is record - -- no data if field cannot be written from hw - data : std_logic_vector(-1 downto 0); -- - end record; - - type t_field_signals_msk_hash_hi_hash_id_hi_out is record - -- no data if field cannot be written from hw - dummy : std_logic; -- - end record; -- - - -- The actual register types - type t_reg_msk_hash_hi_in is record-- - hash_id_hi : t_field_signals_msk_hash_hi_hash_id_hi_in; -- - end record; - type t_reg_msk_hash_hi_out is record-- - hash_id_hi : t_field_signals_msk_hash_hi_hash_id_hi_out; -- - end record; - type t_reg_msk_hash_hi_2d_in is array (integer range <>) of t_reg_msk_hash_hi_in; - type t_reg_msk_hash_hi_2d_out is array (integer range <>) of t_reg_msk_hash_hi_out; - type t_reg_msk_hash_hi_3d_in is array (integer range <>, integer range <>) of t_reg_msk_hash_hi_in; - type t_reg_msk_hash_hi_3d_out is array (integer range <>, integer range <>) of t_reg_msk_hash_hi_out; - ----------------------------------------------- - -- register type: msk_init - ----------------------------------------------- - type t_field_signals_msk_init_txrxinit_in is record - -- no data if field cannot be written from hw - data : std_logic_vector(-1 downto 0); -- - end record; - - type t_field_signals_msk_init_txrxinit_out is record - data : std_logic_vector(1-1 downto 0); -- - end record; -- - type t_field_signals_msk_init_txinit_in is record - -- no data if field cannot be written from hw - data : std_logic_vector(-1 downto 0); -- - end record; - - type t_field_signals_msk_init_txinit_out is record - data : std_logic_vector(1-1 downto 0); -- - end record; -- - type t_field_signals_msk_init_rxinit_in is record - -- no data if field cannot be written from hw - data : std_logic_vector(-1 downto 0); -- - end record; - - type t_field_signals_msk_init_rxinit_out is record - data : std_logic_vector(1-1 downto 0); -- - end record; -- - - -- The actual register types - type t_reg_msk_init_in is record-- - txrxinit : t_field_signals_msk_init_txrxinit_in; -- - txinit : t_field_signals_msk_init_txinit_in; -- - rxinit : t_field_signals_msk_init_rxinit_in; -- - end record; - type t_reg_msk_init_out is record-- - txrxinit : t_field_signals_msk_init_txrxinit_out; -- - txinit : t_field_signals_msk_init_txinit_out; -- - rxinit : t_field_signals_msk_init_rxinit_out; -- - end record; - type t_reg_msk_init_2d_in is array (integer range <>) of t_reg_msk_init_in; - type t_reg_msk_init_2d_out is array (integer range <>) of t_reg_msk_init_out; - type t_reg_msk_init_3d_in is array (integer range <>, integer range <>) of t_reg_msk_init_in; - type t_reg_msk_init_3d_out is array (integer range <>, integer range <>) of t_reg_msk_init_out; - ----------------------------------------------- - -- register type: msk_ctrl - ----------------------------------------------- - type t_field_signals_msk_ctrl_ptt_in is record - -- no data if field cannot be written from hw - data : std_logic_vector(-1 downto 0); -- - end record; - - type t_field_signals_msk_ctrl_ptt_out is record - data : std_logic_vector(1-1 downto 0); -- - end record; -- - type t_field_signals_msk_ctrl_loopback_ena_in is record - -- no data if field cannot be written from hw - data : std_logic_vector(-1 downto 0); -- - end record; - - type t_field_signals_msk_ctrl_loopback_ena_out is record - data : std_logic_vector(1-1 downto 0); -- - end record; -- - type t_field_signals_msk_ctrl_rx_invert_in is record - -- no data if field cannot be written from hw - data : std_logic_vector(-1 downto 0); -- - end record; - - type t_field_signals_msk_ctrl_rx_invert_out is record - data : std_logic_vector(1-1 downto 0); -- - end record; -- - type t_field_signals_msk_ctrl_clear_counts_in is record - -- no data if field cannot be written from hw - data : std_logic_vector(-1 downto 0); -- - end record; - - type t_field_signals_msk_ctrl_clear_counts_out is record - data : std_logic_vector(1-1 downto 0); -- - end record; -- - type t_field_signals_msk_ctrl_diff_encoder_loopback_in is record - -- no data if field cannot be written from hw - data : std_logic_vector(-1 downto 0); -- - end record; - - type t_field_signals_msk_ctrl_diff_encoder_loopback_out is record - data : std_logic_vector(1-1 downto 0); -- - end record; -- - - -- The actual register types - type t_reg_msk_ctrl_in is record-- - ptt : t_field_signals_msk_ctrl_ptt_in; -- - loopback_ena : t_field_signals_msk_ctrl_loopback_ena_in; -- - rx_invert : t_field_signals_msk_ctrl_rx_invert_in; -- - clear_counts : t_field_signals_msk_ctrl_clear_counts_in; -- - diff_encoder_loopback : t_field_signals_msk_ctrl_diff_encoder_loopback_in; -- - end record; - type t_reg_msk_ctrl_out is record-- - ptt : t_field_signals_msk_ctrl_ptt_out; -- - loopback_ena : t_field_signals_msk_ctrl_loopback_ena_out; -- - rx_invert : t_field_signals_msk_ctrl_rx_invert_out; -- - clear_counts : t_field_signals_msk_ctrl_clear_counts_out; -- - diff_encoder_loopback : t_field_signals_msk_ctrl_diff_encoder_loopback_out; -- - end record; - type t_reg_msk_ctrl_2d_in is array (integer range <>) of t_reg_msk_ctrl_in; - type t_reg_msk_ctrl_2d_out is array (integer range <>) of t_reg_msk_ctrl_out; - type t_reg_msk_ctrl_3d_in is array (integer range <>, integer range <>) of t_reg_msk_ctrl_in; - type t_reg_msk_ctrl_3d_out is array (integer range <>, integer range <>) of t_reg_msk_ctrl_out; - ----------------------------------------------- - -- register type: msk_stat_0 - ----------------------------------------------- - type t_field_signals_msk_stat_0_demod_sync_lock_in is record - data : std_logic_vector(1-1 downto 0); -- - end record; - - type t_field_signals_msk_stat_0_demod_sync_lock_out is record - -- no data if field cannot be written from hw - dummy : std_logic; -- - end record; -- - type t_field_signals_msk_stat_0_tx_enable_in is record - data : std_logic_vector(1-1 downto 0); -- - end record; - - type t_field_signals_msk_stat_0_tx_enable_out is record - -- no data if field cannot be written from hw - dummy : std_logic; -- - end record; -- - type t_field_signals_msk_stat_0_rx_enable_in is record - data : std_logic_vector(1-1 downto 0); -- - end record; - - type t_field_signals_msk_stat_0_rx_enable_out is record - -- no data if field cannot be written from hw - dummy : std_logic; -- - end record; -- - type t_field_signals_msk_stat_0_tx_axis_valid_in is record - data : std_logic_vector(1-1 downto 0); -- - end record; - - type t_field_signals_msk_stat_0_tx_axis_valid_out is record - -- no data if field cannot be written from hw - dummy : std_logic; -- - end record; -- - - -- The actual register types - type t_reg_msk_stat_0_in is record-- - demod_sync_lock : t_field_signals_msk_stat_0_demod_sync_lock_in; -- - tx_enable : t_field_signals_msk_stat_0_tx_enable_in; -- - rx_enable : t_field_signals_msk_stat_0_rx_enable_in; -- - tx_axis_valid : t_field_signals_msk_stat_0_tx_axis_valid_in; -- - end record; - type t_reg_msk_stat_0_out is record-- - demod_sync_lock : t_field_signals_msk_stat_0_demod_sync_lock_out; -- - tx_enable : t_field_signals_msk_stat_0_tx_enable_out; -- - rx_enable : t_field_signals_msk_stat_0_rx_enable_out; -- - tx_axis_valid : t_field_signals_msk_stat_0_tx_axis_valid_out; -- - end record; - type t_reg_msk_stat_0_2d_in is array (integer range <>) of t_reg_msk_stat_0_in; - type t_reg_msk_stat_0_2d_out is array (integer range <>) of t_reg_msk_stat_0_out; - type t_reg_msk_stat_0_3d_in is array (integer range <>, integer range <>) of t_reg_msk_stat_0_in; - type t_reg_msk_stat_0_3d_out is array (integer range <>, integer range <>) of t_reg_msk_stat_0_out; - ----------------------------------------------- - -- register type: msk_stat_1 - ----------------------------------------------- - type t_field_signals_msk_stat_1_tx_bit_counter_in is record - data : std_logic_vector(32-1 downto 0); -- - end record; - - type t_field_signals_msk_stat_1_tx_bit_counter_out is record - -- no data if field cannot be written from hw - dummy : std_logic; -- - end record; -- - - -- The actual register types - type t_reg_msk_stat_1_in is record-- - tx_bit_counter : t_field_signals_msk_stat_1_tx_bit_counter_in; -- - end record; - type t_reg_msk_stat_1_out is record-- - tx_bit_counter : t_field_signals_msk_stat_1_tx_bit_counter_out; -- - end record; - type t_reg_msk_stat_1_2d_in is array (integer range <>) of t_reg_msk_stat_1_in; - type t_reg_msk_stat_1_2d_out is array (integer range <>) of t_reg_msk_stat_1_out; - type t_reg_msk_stat_1_3d_in is array (integer range <>, integer range <>) of t_reg_msk_stat_1_in; - type t_reg_msk_stat_1_3d_out is array (integer range <>, integer range <>) of t_reg_msk_stat_1_out; - ----------------------------------------------- - -- register type: msk_stat_2 - ----------------------------------------------- - type t_field_signals_msk_stat_2_tx_ena_counter_in is record - data : std_logic_vector(32-1 downto 0); -- - end record; - - type t_field_signals_msk_stat_2_tx_ena_counter_out is record - -- no data if field cannot be written from hw - dummy : std_logic; -- - end record; -- - - -- The actual register types - type t_reg_msk_stat_2_in is record-- - tx_ena_counter : t_field_signals_msk_stat_2_tx_ena_counter_in; -- - end record; - type t_reg_msk_stat_2_out is record-- - tx_ena_counter : t_field_signals_msk_stat_2_tx_ena_counter_out; -- - end record; - type t_reg_msk_stat_2_2d_in is array (integer range <>) of t_reg_msk_stat_2_in; - type t_reg_msk_stat_2_2d_out is array (integer range <>) of t_reg_msk_stat_2_out; - type t_reg_msk_stat_2_3d_in is array (integer range <>, integer range <>) of t_reg_msk_stat_2_in; - type t_reg_msk_stat_2_3d_out is array (integer range <>, integer range <>) of t_reg_msk_stat_2_out; - ----------------------------------------------- - -- register type: config_nco_fw - ----------------------------------------------- - type t_field_signals_config_nco_fw_config_data_in is record - -- no data if field cannot be written from hw - data : std_logic_vector(-1 downto 0); -- - end record; - - type t_field_signals_config_nco_fw_config_data_out is record - data : std_logic_vector(32-1 downto 0); -- - end record; -- - - -- The actual register types - type t_reg_config_nco_fw_in is record-- - config_data : t_field_signals_config_nco_fw_config_data_in; -- - end record; - type t_reg_config_nco_fw_out is record-- - config_data : t_field_signals_config_nco_fw_config_data_out; -- - end record; - type t_reg_config_nco_fw_2d_in is array (integer range <>) of t_reg_config_nco_fw_in; - type t_reg_config_nco_fw_2d_out is array (integer range <>) of t_reg_config_nco_fw_out; - type t_reg_config_nco_fw_3d_in is array (integer range <>, integer range <>) of t_reg_config_nco_fw_in; - type t_reg_config_nco_fw_3d_out is array (integer range <>, integer range <>) of t_reg_config_nco_fw_out; - ----------------------------------------------- - -- register type: lpf_config_0 - ----------------------------------------------- - type t_field_signals_lpf_config_0_lpf_freeze_in is record - -- no data if field cannot be written from hw - data : std_logic_vector(-1 downto 0); -- - end record; - - type t_field_signals_lpf_config_0_lpf_freeze_out is record - data : std_logic_vector(1-1 downto 0); -- - end record; -- - type t_field_signals_lpf_config_0_lpf_zero_in is record - -- no data if field cannot be written from hw - data : std_logic_vector(-1 downto 0); -- - end record; - - type t_field_signals_lpf_config_0_lpf_zero_out is record - data : std_logic_vector(1-1 downto 0); -- - end record; -- - type t_field_signals_lpf_config_0_prbs_reserved_in is record - -- no data if field cannot be written from hw - data : std_logic_vector(-1 downto 0); -- - end record; - - type t_field_signals_lpf_config_0_prbs_reserved_out is record - data : std_logic_vector(6-1 downto 0); -- - end record; -- - type t_field_signals_lpf_config_0_lpf_alpha_in is record - -- no data if field cannot be written from hw - data : std_logic_vector(-1 downto 0); -- - end record; - - type t_field_signals_lpf_config_0_lpf_alpha_out is record - data : std_logic_vector(24-1 downto 0); -- - end record; -- - - -- The actual register types - type t_reg_lpf_config_0_in is record-- - lpf_freeze : t_field_signals_lpf_config_0_lpf_freeze_in; -- - lpf_zero : t_field_signals_lpf_config_0_lpf_zero_in; -- - prbs_reserved : t_field_signals_lpf_config_0_prbs_reserved_in; -- - lpf_alpha : t_field_signals_lpf_config_0_lpf_alpha_in; -- - end record; - type t_reg_lpf_config_0_out is record-- - lpf_freeze : t_field_signals_lpf_config_0_lpf_freeze_out; -- - lpf_zero : t_field_signals_lpf_config_0_lpf_zero_out; -- - prbs_reserved : t_field_signals_lpf_config_0_prbs_reserved_out; -- - lpf_alpha : t_field_signals_lpf_config_0_lpf_alpha_out; -- - end record; - type t_reg_lpf_config_0_2d_in is array (integer range <>) of t_reg_lpf_config_0_in; - type t_reg_lpf_config_0_2d_out is array (integer range <>) of t_reg_lpf_config_0_out; - type t_reg_lpf_config_0_3d_in is array (integer range <>, integer range <>) of t_reg_lpf_config_0_in; - type t_reg_lpf_config_0_3d_out is array (integer range <>, integer range <>) of t_reg_lpf_config_0_out; - ----------------------------------------------- - -- register type: lpf_config_1 - ----------------------------------------------- - type t_field_signals_lpf_config_1_i_gain_in is record - -- no data if field cannot be written from hw - data : std_logic_vector(-1 downto 0); -- - end record; - - type t_field_signals_lpf_config_1_i_gain_out is record - data : std_logic_vector(24-1 downto 0); -- - end record; -- - type t_field_signals_lpf_config_1_i_shift_in is record - -- no data if field cannot be written from hw - data : std_logic_vector(-1 downto 0); -- - end record; - - type t_field_signals_lpf_config_1_i_shift_out is record - data : std_logic_vector(8-1 downto 0); -- - end record; -- - - -- The actual register types - type t_reg_lpf_config_1_in is record-- - i_gain : t_field_signals_lpf_config_1_i_gain_in; -- - i_shift : t_field_signals_lpf_config_1_i_shift_in; -- - end record; - type t_reg_lpf_config_1_out is record-- - i_gain : t_field_signals_lpf_config_1_i_gain_out; -- - i_shift : t_field_signals_lpf_config_1_i_shift_out; -- - end record; - type t_reg_lpf_config_1_2d_in is array (integer range <>) of t_reg_lpf_config_1_in; - type t_reg_lpf_config_1_2d_out is array (integer range <>) of t_reg_lpf_config_1_out; - type t_reg_lpf_config_1_3d_in is array (integer range <>, integer range <>) of t_reg_lpf_config_1_in; - type t_reg_lpf_config_1_3d_out is array (integer range <>, integer range <>) of t_reg_lpf_config_1_out; - ----------------------------------------------- - -- register type: data_width - ----------------------------------------------- - type t_field_signals_data_width_data_width_in is record - -- no data if field cannot be written from hw - data : std_logic_vector(-1 downto 0); -- - end record; - - type t_field_signals_data_width_data_width_out is record - data : std_logic_vector(8-1 downto 0); -- - end record; -- - - -- The actual register types - type t_reg_data_width_in is record-- - data_width : t_field_signals_data_width_data_width_in; -- - end record; - type t_reg_data_width_out is record-- - data_width : t_field_signals_data_width_data_width_out; -- - end record; - type t_reg_data_width_2d_in is array (integer range <>) of t_reg_data_width_in; - type t_reg_data_width_2d_out is array (integer range <>) of t_reg_data_width_out; - type t_reg_data_width_3d_in is array (integer range <>, integer range <>) of t_reg_data_width_in; - type t_reg_data_width_3d_out is array (integer range <>, integer range <>) of t_reg_data_width_out; - ----------------------------------------------- - -- register type: prbs_ctrl - ----------------------------------------------- - type t_field_signals_prbs_ctrl_prbs_sel_in is record - -- no data if field cannot be written from hw - data : std_logic_vector(-1 downto 0); -- - end record; - - type t_field_signals_prbs_ctrl_prbs_sel_out is record - data : std_logic_vector(1-1 downto 0); -- - end record; -- - type t_field_signals_prbs_ctrl_prbs_error_insert_in is record - -- no data if field cannot be written from hw - data : std_logic_vector(-1 downto 0); -- - end record; - - type t_field_signals_prbs_ctrl_prbs_error_insert_out is record - data : std_logic_vector(1-1 downto 0); -- - end record; -- - type t_field_signals_prbs_ctrl_prbs_clear_in is record - -- no data if field cannot be written from hw - data : std_logic_vector(-1 downto 0); -- - end record; - - type t_field_signals_prbs_ctrl_prbs_clear_out is record - data : std_logic_vector(1-1 downto 0); -- - end record; -- - type t_field_signals_prbs_ctrl_prbs_manual_sync_in is record - -- no data if field cannot be written from hw - data : std_logic_vector(-1 downto 0); -- - end record; - - type t_field_signals_prbs_ctrl_prbs_manual_sync_out is record - data : std_logic_vector(1-1 downto 0); -- - end record; -- - type t_field_signals_prbs_ctrl_prbs_reserved_in is record - -- no data if field cannot be written from hw - data : std_logic_vector(-1 downto 0); -- - end record; - - type t_field_signals_prbs_ctrl_prbs_reserved_out is record - data : std_logic_vector(12-1 downto 0); -- - end record; -- - type t_field_signals_prbs_ctrl_prbs_sync_threshold_in is record - -- no data if field cannot be written from hw - data : std_logic_vector(-1 downto 0); -- - end record; - - type t_field_signals_prbs_ctrl_prbs_sync_threshold_out is record - data : std_logic_vector(16-1 downto 0); -- - end record; -- - - -- The actual register types - type t_reg_prbs_ctrl_in is record-- - prbs_sel : t_field_signals_prbs_ctrl_prbs_sel_in; -- - prbs_error_insert : t_field_signals_prbs_ctrl_prbs_error_insert_in; -- - prbs_clear : t_field_signals_prbs_ctrl_prbs_clear_in; -- - prbs_manual_sync : t_field_signals_prbs_ctrl_prbs_manual_sync_in; -- - prbs_reserved : t_field_signals_prbs_ctrl_prbs_reserved_in; -- - prbs_sync_threshold : t_field_signals_prbs_ctrl_prbs_sync_threshold_in; -- - end record; - type t_reg_prbs_ctrl_out is record-- - prbs_sel : t_field_signals_prbs_ctrl_prbs_sel_out; -- - prbs_error_insert : t_field_signals_prbs_ctrl_prbs_error_insert_out; -- - prbs_clear : t_field_signals_prbs_ctrl_prbs_clear_out; -- - prbs_manual_sync : t_field_signals_prbs_ctrl_prbs_manual_sync_out; -- - prbs_reserved : t_field_signals_prbs_ctrl_prbs_reserved_out; -- - prbs_sync_threshold : t_field_signals_prbs_ctrl_prbs_sync_threshold_out; -- - end record; - type t_reg_prbs_ctrl_2d_in is array (integer range <>) of t_reg_prbs_ctrl_in; - type t_reg_prbs_ctrl_2d_out is array (integer range <>) of t_reg_prbs_ctrl_out; - type t_reg_prbs_ctrl_3d_in is array (integer range <>, integer range <>) of t_reg_prbs_ctrl_in; - type t_reg_prbs_ctrl_3d_out is array (integer range <>, integer range <>) of t_reg_prbs_ctrl_out; - ----------------------------------------------- - -- register type: config_prbs_seed - ----------------------------------------------- - type t_field_signals_config_prbs_seed_config_data_in is record - -- no data if field cannot be written from hw - data : std_logic_vector(-1 downto 0); -- - end record; - - type t_field_signals_config_prbs_seed_config_data_out is record - data : std_logic_vector(32-1 downto 0); -- - end record; -- - - -- The actual register types - type t_reg_config_prbs_seed_in is record-- - config_data : t_field_signals_config_prbs_seed_config_data_in; -- - end record; - type t_reg_config_prbs_seed_out is record-- - config_data : t_field_signals_config_prbs_seed_config_data_out; -- - end record; - type t_reg_config_prbs_seed_2d_in is array (integer range <>) of t_reg_config_prbs_seed_in; - type t_reg_config_prbs_seed_2d_out is array (integer range <>) of t_reg_config_prbs_seed_out; - type t_reg_config_prbs_seed_3d_in is array (integer range <>, integer range <>) of t_reg_config_prbs_seed_in; - type t_reg_config_prbs_seed_3d_out is array (integer range <>, integer range <>) of t_reg_config_prbs_seed_out; - ----------------------------------------------- - -- register type: config_prbs_poly - ----------------------------------------------- - type t_field_signals_config_prbs_poly_config_data_in is record - -- no data if field cannot be written from hw - data : std_logic_vector(-1 downto 0); -- - end record; - - type t_field_signals_config_prbs_poly_config_data_out is record - data : std_logic_vector(32-1 downto 0); -- - end record; -- - - -- The actual register types - type t_reg_config_prbs_poly_in is record-- - config_data : t_field_signals_config_prbs_poly_config_data_in; -- - end record; - type t_reg_config_prbs_poly_out is record-- - config_data : t_field_signals_config_prbs_poly_config_data_out; -- - end record; - type t_reg_config_prbs_poly_2d_in is array (integer range <>) of t_reg_config_prbs_poly_in; - type t_reg_config_prbs_poly_2d_out is array (integer range <>) of t_reg_config_prbs_poly_out; - type t_reg_config_prbs_poly_3d_in is array (integer range <>, integer range <>) of t_reg_config_prbs_poly_in; - type t_reg_config_prbs_poly_3d_out is array (integer range <>, integer range <>) of t_reg_config_prbs_poly_out; - ----------------------------------------------- - -- register type: config_prbs_errmask - ----------------------------------------------- - type t_field_signals_config_prbs_errmask_config_data_in is record - -- no data if field cannot be written from hw - data : std_logic_vector(-1 downto 0); -- - end record; - - type t_field_signals_config_prbs_errmask_config_data_out is record - data : std_logic_vector(32-1 downto 0); -- - end record; -- - - -- The actual register types - type t_reg_config_prbs_errmask_in is record-- - config_data : t_field_signals_config_prbs_errmask_config_data_in; -- - end record; - type t_reg_config_prbs_errmask_out is record-- - config_data : t_field_signals_config_prbs_errmask_config_data_out; -- - end record; - type t_reg_config_prbs_errmask_2d_in is array (integer range <>) of t_reg_config_prbs_errmask_in; - type t_reg_config_prbs_errmask_2d_out is array (integer range <>) of t_reg_config_prbs_errmask_out; - type t_reg_config_prbs_errmask_3d_in is array (integer range <>, integer range <>) of t_reg_config_prbs_errmask_in; - type t_reg_config_prbs_errmask_3d_out is array (integer range <>, integer range <>) of t_reg_config_prbs_errmask_out; - ----------------------------------------------- - -- register type: stat_32_bits - ----------------------------------------------- - type t_field_signals_stat_32_bits_status_data_in is record - data : std_logic_vector(32-1 downto 0); -- - end record; - - type t_field_signals_stat_32_bits_status_data_out is record - -- no data if field cannot be written from hw - dummy : std_logic; -- - end record; -- - - -- The actual register types - type t_reg_stat_32_bits_in is record-- - status_data : t_field_signals_stat_32_bits_status_data_in; -- - end record; - type t_reg_stat_32_bits_out is record-- - status_data : t_field_signals_stat_32_bits_status_data_out; -- - end record; - type t_reg_stat_32_bits_2d_in is array (integer range <>) of t_reg_stat_32_bits_in; - type t_reg_stat_32_bits_2d_out is array (integer range <>) of t_reg_stat_32_bits_out; - type t_reg_stat_32_bits_3d_in is array (integer range <>, integer range <>) of t_reg_stat_32_bits_in; - type t_reg_stat_32_bits_3d_out is array (integer range <>, integer range <>) of t_reg_stat_32_bits_out; - ----------------------------------------------- - -- register type: stat_32_errs - ----------------------------------------------- - type t_field_signals_stat_32_errs_status_data_in is record - data : std_logic_vector(32-1 downto 0); -- - end record; - - type t_field_signals_stat_32_errs_status_data_out is record - -- no data if field cannot be written from hw - dummy : std_logic; -- - end record; -- - - -- The actual register types - type t_reg_stat_32_errs_in is record-- - status_data : t_field_signals_stat_32_errs_status_data_in; -- - end record; - type t_reg_stat_32_errs_out is record-- - status_data : t_field_signals_stat_32_errs_status_data_out; -- - end record; - type t_reg_stat_32_errs_2d_in is array (integer range <>) of t_reg_stat_32_errs_in; - type t_reg_stat_32_errs_2d_out is array (integer range <>) of t_reg_stat_32_errs_out; - type t_reg_stat_32_errs_3d_in is array (integer range <>, integer range <>) of t_reg_stat_32_errs_in; - type t_reg_stat_32_errs_3d_out is array (integer range <>, integer range <>) of t_reg_stat_32_errs_out; - ----------------------------------------------- - -- register type: stat_32_lpf_acc - ----------------------------------------------- - type t_field_signals_stat_32_lpf_acc_status_data_in is record - data : std_logic_vector(32-1 downto 0); -- - end record; - - type t_field_signals_stat_32_lpf_acc_status_data_out is record - -- no data if field cannot be written from hw - dummy : std_logic; -- - end record; -- - - -- The actual register types - type t_reg_stat_32_lpf_acc_in is record-- - status_data : t_field_signals_stat_32_lpf_acc_status_data_in; -- - end record; - type t_reg_stat_32_lpf_acc_out is record-- - status_data : t_field_signals_stat_32_lpf_acc_status_data_out; -- - end record; - type t_reg_stat_32_lpf_acc_2d_in is array (integer range <>) of t_reg_stat_32_lpf_acc_in; - type t_reg_stat_32_lpf_acc_2d_out is array (integer range <>) of t_reg_stat_32_lpf_acc_out; - type t_reg_stat_32_lpf_acc_3d_in is array (integer range <>, integer range <>) of t_reg_stat_32_lpf_acc_in; - type t_reg_stat_32_lpf_acc_3d_out is array (integer range <>, integer range <>) of t_reg_stat_32_lpf_acc_out; - ----------------------------------------------- - -- register type: msk_stat_3 - ----------------------------------------------- - type t_field_signals_msk_stat_3_xfer_count_in is record - data : std_logic_vector(32-1 downto 0); -- - end record; - - type t_field_signals_msk_stat_3_xfer_count_out is record - -- no data if field cannot be written from hw - dummy : std_logic; -- - end record; -- - - -- The actual register types - type t_reg_msk_stat_3_in is record-- - xfer_count : t_field_signals_msk_stat_3_xfer_count_in; -- - end record; - type t_reg_msk_stat_3_out is record-- - xfer_count : t_field_signals_msk_stat_3_xfer_count_out; -- - end record; - type t_reg_msk_stat_3_2d_in is array (integer range <>) of t_reg_msk_stat_3_in; - type t_reg_msk_stat_3_2d_out is array (integer range <>) of t_reg_msk_stat_3_out; - type t_reg_msk_stat_3_3d_in is array (integer range <>, integer range <>) of t_reg_msk_stat_3_in; - type t_reg_msk_stat_3_3d_out is array (integer range <>, integer range <>) of t_reg_msk_stat_3_out; - ----------------------------------------------- - -- register type: rx_sample_discard - ----------------------------------------------- - type t_field_signals_rx_sample_discard_rx_sample_discard_in is record - -- no data if field cannot be written from hw - data : std_logic_vector(-1 downto 0); -- - end record; - - type t_field_signals_rx_sample_discard_rx_sample_discard_out is record - data : std_logic_vector(8-1 downto 0); -- - end record; -- - type t_field_signals_rx_sample_discard_rx_nco_discard_in is record - -- no data if field cannot be written from hw - data : std_logic_vector(-1 downto 0); -- - end record; - - type t_field_signals_rx_sample_discard_rx_nco_discard_out is record - data : std_logic_vector(8-1 downto 0); -- - end record; -- - - -- The actual register types - type t_reg_rx_sample_discard_in is record-- - rx_sample_discard : t_field_signals_rx_sample_discard_rx_sample_discard_in; -- - rx_nco_discard : t_field_signals_rx_sample_discard_rx_nco_discard_in; -- - end record; - type t_reg_rx_sample_discard_out is record-- - rx_sample_discard : t_field_signals_rx_sample_discard_rx_sample_discard_out; -- - rx_nco_discard : t_field_signals_rx_sample_discard_rx_nco_discard_out; -- - end record; - type t_reg_rx_sample_discard_2d_in is array (integer range <>) of t_reg_rx_sample_discard_in; - type t_reg_rx_sample_discard_2d_out is array (integer range <>) of t_reg_rx_sample_discard_out; - type t_reg_rx_sample_discard_3d_in is array (integer range <>, integer range <>) of t_reg_rx_sample_discard_in; - type t_reg_rx_sample_discard_3d_out is array (integer range <>, integer range <>) of t_reg_rx_sample_discard_out; - ----------------------------------------------- - -- register type: lpf_config_2 - ----------------------------------------------- - type t_field_signals_lpf_config_2_p_gain_in is record - -- no data if field cannot be written from hw - data : std_logic_vector(-1 downto 0); -- - end record; - - type t_field_signals_lpf_config_2_p_gain_out is record - data : std_logic_vector(24-1 downto 0); -- - end record; -- - type t_field_signals_lpf_config_2_p_shift_in is record - -- no data if field cannot be written from hw - data : std_logic_vector(-1 downto 0); -- - end record; - - type t_field_signals_lpf_config_2_p_shift_out is record - data : std_logic_vector(8-1 downto 0); -- - end record; -- - - -- The actual register types - type t_reg_lpf_config_2_in is record-- - p_gain : t_field_signals_lpf_config_2_p_gain_in; -- - p_shift : t_field_signals_lpf_config_2_p_shift_in; -- - end record; - type t_reg_lpf_config_2_out is record-- - p_gain : t_field_signals_lpf_config_2_p_gain_out; -- - p_shift : t_field_signals_lpf_config_2_p_shift_out; -- - end record; - type t_reg_lpf_config_2_2d_in is array (integer range <>) of t_reg_lpf_config_2_in; - type t_reg_lpf_config_2_2d_out is array (integer range <>) of t_reg_lpf_config_2_out; - type t_reg_lpf_config_2_3d_in is array (integer range <>, integer range <>) of t_reg_lpf_config_2_in; - type t_reg_lpf_config_2_3d_out is array (integer range <>, integer range <>) of t_reg_lpf_config_2_out; - ----------------------------------------------- - -- register type: observation_data - ----------------------------------------------- - type t_field_signals_observation_data_data32_in is record - data : std_logic_vector(32-1 downto 0); -- - end record; - - type t_field_signals_observation_data_data32_out is record - -- no data if field cannot be written from hw - dummy : std_logic; -- - end record; -- - - -- The actual register types - type t_reg_observation_data_in is record-- - data : t_field_signals_observation_data_data32_in; -- - end record; - type t_reg_observation_data_out is record-- - data : t_field_signals_observation_data_data32_out; -- - end record; - type t_reg_observation_data_2d_in is array (integer range <>) of t_reg_observation_data_in; - type t_reg_observation_data_2d_out is array (integer range <>) of t_reg_observation_data_out; - type t_reg_observation_data_3d_in is array (integer range <>, integer range <>) of t_reg_observation_data_in; - type t_reg_observation_data_3d_out is array (integer range <>, integer range <>) of t_reg_observation_data_out; - ----------------------------------------------- - -- register type: tx_sync_ctrl - ----------------------------------------------- - type t_field_signals_tx_sync_ctrl_tx_sync_ena_in is record - -- no data if field cannot be written from hw - data : std_logic_vector(-1 downto 0); -- - end record; - - type t_field_signals_tx_sync_ctrl_tx_sync_ena_out is record - data : std_logic_vector(1-1 downto 0); -- - end record; -- - type t_field_signals_tx_sync_ctrl_tx_sync_force_in is record - -- no data if field cannot be written from hw - data : std_logic_vector(-1 downto 0); -- - end record; - - type t_field_signals_tx_sync_ctrl_tx_sync_force_out is record - data : std_logic_vector(1-1 downto 0); -- - end record; -- - type t_field_signals_tx_sync_ctrl_tx_sync_f1_in is record - -- no data if field cannot be written from hw - data : std_logic_vector(-1 downto 0); -- - end record; - - type t_field_signals_tx_sync_ctrl_tx_sync_f1_out is record - data : std_logic_vector(1-1 downto 0); -- - end record; -- - type t_field_signals_tx_sync_ctrl_tx_sync_f2_in is record - -- no data if field cannot be written from hw - data : std_logic_vector(-1 downto 0); -- - end record; - - type t_field_signals_tx_sync_ctrl_tx_sync_f2_out is record - data : std_logic_vector(1-1 downto 0); -- - end record; -- - - -- The actual register types - type t_reg_tx_sync_ctrl_in is record-- - tx_sync_ena : t_field_signals_tx_sync_ctrl_tx_sync_ena_in; -- - tx_sync_force : t_field_signals_tx_sync_ctrl_tx_sync_force_in; -- - tx_sync_f1 : t_field_signals_tx_sync_ctrl_tx_sync_f1_in; -- - tx_sync_f2 : t_field_signals_tx_sync_ctrl_tx_sync_f2_in; -- - end record; - type t_reg_tx_sync_ctrl_out is record-- - tx_sync_ena : t_field_signals_tx_sync_ctrl_tx_sync_ena_out; -- - tx_sync_force : t_field_signals_tx_sync_ctrl_tx_sync_force_out; -- - tx_sync_f1 : t_field_signals_tx_sync_ctrl_tx_sync_f1_out; -- - tx_sync_f2 : t_field_signals_tx_sync_ctrl_tx_sync_f2_out; -- - end record; - type t_reg_tx_sync_ctrl_2d_in is array (integer range <>) of t_reg_tx_sync_ctrl_in; - type t_reg_tx_sync_ctrl_2d_out is array (integer range <>) of t_reg_tx_sync_ctrl_out; - type t_reg_tx_sync_ctrl_3d_in is array (integer range <>, integer range <>) of t_reg_tx_sync_ctrl_in; - type t_reg_tx_sync_ctrl_3d_out is array (integer range <>, integer range <>) of t_reg_tx_sync_ctrl_out; - ----------------------------------------------- - -- register type: tx_sync_cnt - ----------------------------------------------- - type t_field_signals_tx_sync_cnt_tx_sync_cnt_in is record - -- no data if field cannot be written from hw - data : std_logic_vector(-1 downto 0); -- - end record; - - type t_field_signals_tx_sync_cnt_tx_sync_cnt_out is record - data : std_logic_vector(24-1 downto 0); -- - end record; -- - - -- The actual register types - type t_reg_tx_sync_cnt_in is record-- - tx_sync_cnt : t_field_signals_tx_sync_cnt_tx_sync_cnt_in; -- - end record; - type t_reg_tx_sync_cnt_out is record-- - tx_sync_cnt : t_field_signals_tx_sync_cnt_tx_sync_cnt_out; -- - end record; - type t_reg_tx_sync_cnt_2d_in is array (integer range <>) of t_reg_tx_sync_cnt_in; - type t_reg_tx_sync_cnt_2d_out is array (integer range <>) of t_reg_tx_sync_cnt_out; - type t_reg_tx_sync_cnt_3d_in is array (integer range <>, integer range <>) of t_reg_tx_sync_cnt_in; - type t_reg_tx_sync_cnt_3d_out is array (integer range <>, integer range <>) of t_reg_tx_sync_cnt_out; - ----------------------------------------------- - -- register type: lowpass_ema_alpha - ----------------------------------------------- - type t_field_signals_lowpass_ema_alpha_alpha_in is record - -- no data if field cannot be written from hw - data : std_logic_vector(-1 downto 0); -- - end record; - - type t_field_signals_lowpass_ema_alpha_alpha_out is record - data : std_logic_vector(18-1 downto 0); -- - end record; -- - - -- The actual register types - type t_reg_lowpass_ema_alpha_in is record-- - alpha : t_field_signals_lowpass_ema_alpha_alpha_in; -- - end record; - type t_reg_lowpass_ema_alpha_out is record-- - alpha : t_field_signals_lowpass_ema_alpha_alpha_out; -- - end record; - type t_reg_lowpass_ema_alpha_2d_in is array (integer range <>) of t_reg_lowpass_ema_alpha_in; - type t_reg_lowpass_ema_alpha_2d_out is array (integer range <>) of t_reg_lowpass_ema_alpha_out; - type t_reg_lowpass_ema_alpha_3d_in is array (integer range <>, integer range <>) of t_reg_lowpass_ema_alpha_in; - type t_reg_lowpass_ema_alpha_3d_out is array (integer range <>, integer range <>) of t_reg_lowpass_ema_alpha_out; - ----------------------------------------------- - -- register type: rx_power - ----------------------------------------------- - type t_field_signals_rx_power_rx_power_in is record - data : std_logic_vector(23-1 downto 0); -- - end record; - - type t_field_signals_rx_power_rx_power_out is record - -- no data if field cannot be written from hw - dummy : std_logic; -- - end record; -- - - -- The actual register types - type t_reg_rx_power_in is record-- - rx_power : t_field_signals_rx_power_rx_power_in; -- - end record; - type t_reg_rx_power_out is record-- - rx_power : t_field_signals_rx_power_rx_power_out; -- - end record; - type t_reg_rx_power_2d_in is array (integer range <>) of t_reg_rx_power_in; - type t_reg_rx_power_2d_out is array (integer range <>) of t_reg_rx_power_out; - type t_reg_rx_power_3d_in is array (integer range <>, integer range <>) of t_reg_rx_power_in; - type t_reg_rx_power_3d_out is array (integer range <>, integer range <>) of t_reg_rx_power_out; - ----------------------------------------------- - - ------------------------------------------------------------------------------ - -- Register types in regfiles -- - - -- =========================================================================== - -- REGFILE interface - -- ----------------------------------------------------------------------------- - - -- =========================================================================== - -- MEMORIES interface - -- --------------------------------------------------------------------------- - - -- =========================================================================== - -- msk_top_regs : Top module address map interface - -- --------------------------------------------------------------------------- - type t_addrmap_msk_top_regs_in is record - -- - Hash_ID_Low : t_reg_msk_hash_lo_in; -- - Hash_ID_High : t_reg_msk_hash_hi_in; -- - MSK_Init : t_reg_msk_init_in; -- - MSK_Control : t_reg_msk_ctrl_in; -- - MSK_Status : t_reg_msk_stat_0_in; -- - Tx_Bit_Count : t_reg_msk_stat_1_in; -- - Tx_Enable_Count : t_reg_msk_stat_2_in; -- - Fb_FreqWord : t_reg_config_nco_fw_in; -- - TX_F1_FreqWord : t_reg_config_nco_fw_in; -- - TX_F2_FreqWord : t_reg_config_nco_fw_in; -- - RX_F1_FreqWord : t_reg_config_nco_fw_in; -- - RX_F2_FreqWord : t_reg_config_nco_fw_in; -- - LPF_Config_0 : t_reg_lpf_config_0_in; -- - LPF_Config_1 : t_reg_lpf_config_1_in; -- - Tx_Data_Width : t_reg_data_width_in; -- - Rx_Data_Width : t_reg_data_width_in; -- - PRBS_Control : t_reg_prbs_ctrl_in; -- - PRBS_Initial_State : t_reg_config_prbs_seed_in; -- - PRBS_Polynomial : t_reg_config_prbs_poly_in; -- - PRBS_Error_Mask : t_reg_config_prbs_errmask_in; -- - PRBS_Bit_Count : t_reg_stat_32_bits_in; -- - PRBS_Error_Count : t_reg_stat_32_errs_in; -- - LPF_Accum_F1 : t_reg_stat_32_lpf_acc_in; -- - LPF_Accum_F2 : t_reg_stat_32_lpf_acc_in; -- - axis_xfer_count : t_reg_msk_stat_3_in; -- - Rx_Sample_Discard : t_reg_rx_sample_discard_in; -- - LPF_Config_2 : t_reg_lpf_config_2_in; -- - f1_nco_adjust : t_reg_observation_data_in; -- - f2_nco_adjust : t_reg_observation_data_in; -- - f1_error : t_reg_observation_data_in; -- - f2_error : t_reg_observation_data_in; -- - Tx_Sync_Ctrl : t_reg_tx_sync_ctrl_in; -- - Tx_Sync_Cnt : t_reg_tx_sync_cnt_in; -- - lowpass_ema_alpha1 : t_reg_lowpass_ema_alpha_in; -- - lowpass_ema_alpha2 : t_reg_lowpass_ema_alpha_in; -- - rx_power : t_reg_rx_power_in; -- - -- - -- - -- - end record; - - type t_addrmap_msk_top_regs_out is record - -- - Hash_ID_Low : t_reg_msk_hash_lo_out; -- - Hash_ID_High : t_reg_msk_hash_hi_out; -- - MSK_Init : t_reg_msk_init_out; -- - MSK_Control : t_reg_msk_ctrl_out; -- - MSK_Status : t_reg_msk_stat_0_out; -- - Tx_Bit_Count : t_reg_msk_stat_1_out; -- - Tx_Enable_Count : t_reg_msk_stat_2_out; -- - Fb_FreqWord : t_reg_config_nco_fw_out; -- - TX_F1_FreqWord : t_reg_config_nco_fw_out; -- - TX_F2_FreqWord : t_reg_config_nco_fw_out; -- - RX_F1_FreqWord : t_reg_config_nco_fw_out; -- - RX_F2_FreqWord : t_reg_config_nco_fw_out; -- - LPF_Config_0 : t_reg_lpf_config_0_out; -- - LPF_Config_1 : t_reg_lpf_config_1_out; -- - Tx_Data_Width : t_reg_data_width_out; -- - Rx_Data_Width : t_reg_data_width_out; -- - PRBS_Control : t_reg_prbs_ctrl_out; -- - PRBS_Initial_State : t_reg_config_prbs_seed_out; -- - PRBS_Polynomial : t_reg_config_prbs_poly_out; -- - PRBS_Error_Mask : t_reg_config_prbs_errmask_out; -- - PRBS_Bit_Count : t_reg_stat_32_bits_out; -- - PRBS_Error_Count : t_reg_stat_32_errs_out; -- - LPF_Accum_F1 : t_reg_stat_32_lpf_acc_out; -- - LPF_Accum_F2 : t_reg_stat_32_lpf_acc_out; -- - axis_xfer_count : t_reg_msk_stat_3_out; -- - Rx_Sample_Discard : t_reg_rx_sample_discard_out; -- - LPF_Config_2 : t_reg_lpf_config_2_out; -- - f1_nco_adjust : t_reg_observation_data_out; -- - f2_nco_adjust : t_reg_observation_data_out; -- - f1_error : t_reg_observation_data_out; -- - f2_error : t_reg_observation_data_out; -- - Tx_Sync_Ctrl : t_reg_tx_sync_ctrl_out; -- - Tx_Sync_Cnt : t_reg_tx_sync_cnt_out; -- - lowpass_ema_alpha1 : t_reg_lowpass_ema_alpha_out; -- - lowpass_ema_alpha2 : t_reg_lowpass_ema_alpha_out; -- - rx_power : t_reg_rx_power_out; -- - -- - -- - -- - end record; - - -- =========================================================================== - -- top level component declaration - -- must come after defining the interfaces - -- --------------------------------------------------------------------------- - subtype t_msk_top_regs_m2s is t_axi4l_m2s; - subtype t_msk_top_regs_s2m is t_axi4l_s2m; - - component msk_top_regs is - port ( - pi_clock : in std_logic; - pi_reset : in std_logic; - -- TOP subordinate memory mapped interface - pi_s_top : in t_msk_top_regs_m2s; - po_s_top : out t_msk_top_regs_s2m; - -- to logic interface - pi_addrmap : in t_addrmap_msk_top_regs_in; - po_addrmap : out t_addrmap_msk_top_regs_out - ); - end component msk_top_regs; - -end package pkg_msk_top_regs; --------------------------------------------------------------------------------- -package body pkg_msk_top_regs is -end package body; - ---============================================================================== - - --------------------------------------------------------------------------------- --- Register types directly in addmap --------------------------------------------------------------------------------- --- --- register type: msk_hash_lo ------------------------------------------------ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library desyrdl; -use desyrdl.common.all; - -use work.pkg_msk_top_regs.all; - -entity msk_top_regs_msk_hash_lo is - port ( - pi_clock : in std_logic; - pi_reset : in std_logic; - -- to/from adapter - pi_decoder_rd_stb : in std_logic; - pi_decoder_wr_stb : in std_logic; - pi_decoder_data : in std_logic_vector(C_DATA_WIDTH-1 downto 0); - po_decoder_data : out std_logic_vector(C_DATA_WIDTH-1 downto 0); - - pi_reg : in t_reg_msk_hash_lo_in ; - po_reg : out t_reg_msk_hash_lo_out - ); -end entity msk_top_regs_msk_hash_lo; - -architecture rtl of msk_top_regs_msk_hash_lo is - - -- assign slices of data_out for each field, but force the rest to constant zeros - function fun_set_data_out ( -- - field_reg_hash_id_lo : std_logic_vector(32-1 downto 0)) -- - return std_logic_vector is - variable v_data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0); - begin - v_data_out := (others => '0'); - -- - v_data_out(31 downto 0) := field_reg_hash_id_lo; -- - return v_data_out; - end function fun_set_data_out; - - signal data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0'); - -- - signal field_reg_hash_id_lo : std_logic_vector(32-1 downto 0) - := std_logic_vector(to_signed(-1431677611,32)); -- -begin - - data_out <= fun_set_data_out( -- - field_reg_hash_id_lo -- - ); - - -- resize field data out to the register bus width - -- do only if 1 field and signed-- - po_decoder_data <= data_out; -- - ------------------------------------------------------------WIRE - hash_id_lo_wire : block -- - begin - -- - field_reg_hash_id_lo <= std_logic_vector(to_signed(-1431677611,32)); -- - --no signal to read by HW - po_reg.hash_id_lo.dummy <= '0'; -- - end block; -- -end rtl; ------------------------------------------------ --- register type: msk_hash_hi ------------------------------------------------ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library desyrdl; -use desyrdl.common.all; - -use work.pkg_msk_top_regs.all; - -entity msk_top_regs_msk_hash_hi is - port ( - pi_clock : in std_logic; - pi_reset : in std_logic; - -- to/from adapter - pi_decoder_rd_stb : in std_logic; - pi_decoder_wr_stb : in std_logic; - pi_decoder_data : in std_logic_vector(C_DATA_WIDTH-1 downto 0); - po_decoder_data : out std_logic_vector(C_DATA_WIDTH-1 downto 0); - - pi_reg : in t_reg_msk_hash_hi_in ; - po_reg : out t_reg_msk_hash_hi_out - ); -end entity msk_top_regs_msk_hash_hi; - -architecture rtl of msk_top_regs_msk_hash_hi is - - -- assign slices of data_out for each field, but force the rest to constant zeros - function fun_set_data_out ( -- - field_reg_hash_id_hi : std_logic_vector(32-1 downto 0)) -- - return std_logic_vector is - variable v_data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0); - begin - v_data_out := (others => '0'); - -- - v_data_out(31 downto 0) := field_reg_hash_id_hi; -- - return v_data_out; - end function fun_set_data_out; - - signal data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0'); - -- - signal field_reg_hash_id_hi : std_logic_vector(32-1 downto 0) - := std_logic_vector(to_signed(1431677610,32)); -- -begin - - data_out <= fun_set_data_out( -- - field_reg_hash_id_hi -- - ); - - -- resize field data out to the register bus width - -- do only if 1 field and signed-- - po_decoder_data <= data_out; -- - ------------------------------------------------------------WIRE - hash_id_hi_wire : block -- - begin - -- - field_reg_hash_id_hi <= std_logic_vector(to_signed(1431677610,32)); -- - --no signal to read by HW - po_reg.hash_id_hi.dummy <= '0'; -- - end block; -- -end rtl; ------------------------------------------------ --- register type: msk_init ------------------------------------------------ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library desyrdl; -use desyrdl.common.all; - -use work.pkg_msk_top_regs.all; - -entity msk_top_regs_msk_init is - port ( - pi_clock : in std_logic; - pi_reset : in std_logic; - -- to/from adapter - pi_decoder_rd_stb : in std_logic; - pi_decoder_wr_stb : in std_logic; - pi_decoder_data : in std_logic_vector(C_DATA_WIDTH-1 downto 0); - po_decoder_data : out std_logic_vector(C_DATA_WIDTH-1 downto 0); - - pi_reg : in t_reg_msk_init_in ; - po_reg : out t_reg_msk_init_out - ); -end entity msk_top_regs_msk_init; - -architecture rtl of msk_top_regs_msk_init is - - -- assign slices of data_out for each field, but force the rest to constant zeros - function fun_set_data_out ( -- - field_reg_txrxinit : std_logic_vector(1-1 downto 0); -- - field_reg_txinit : std_logic_vector(1-1 downto 0); -- - field_reg_rxinit : std_logic_vector(1-1 downto 0)) -- - return std_logic_vector is - variable v_data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0); - begin - v_data_out := (others => '0'); - -- - v_data_out(0 downto 0) := field_reg_txrxinit; -- - v_data_out(1 downto 1) := field_reg_txinit; -- - v_data_out(2 downto 2) := field_reg_rxinit; -- - return v_data_out; - end function fun_set_data_out; - - signal data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0'); - -- - signal field_reg_txrxinit : std_logic_vector(1-1 downto 0) - := std_logic_vector(to_signed(1,1)); -- - signal field_reg_txinit : std_logic_vector(1-1 downto 0) - := std_logic_vector(to_signed(1,1)); -- - signal field_reg_rxinit : std_logic_vector(1-1 downto 0) - := std_logic_vector(to_signed(1,1)); -- -begin - - data_out <= fun_set_data_out( -- - field_reg_txrxinit, -- - field_reg_txinit, -- - field_reg_rxinit -- - ); - - -- resize field data out to the register bus width - -- do only if 1 field and signed-- - po_decoder_data <= data_out; -- - ------------------------------------------------------------STORAGE - txrxinit_storage: block - begin - prs_write : process(pi_clock) - begin - if rising_edge(pi_clock) then - if pi_reset = '1' then - field_reg_txrxinit <= std_logic_vector(to_signed(1,1)); - else - -- HW -- - -- SW -- - if pi_decoder_wr_stb = '1' then - field_reg_txrxinit <= pi_decoder_data(0 downto 0); - end if; - end if; - end if; - end process; - -- - po_reg.txrxinit.data <= field_reg_txrxinit; -- - end block txrxinit_storage; - ------------------------------------------------------------STORAGE - txinit_storage: block - begin - prs_write : process(pi_clock) - begin - if rising_edge(pi_clock) then - if pi_reset = '1' then - field_reg_txinit <= std_logic_vector(to_signed(1,1)); - else - -- HW -- - -- SW -- - if pi_decoder_wr_stb = '1' then - field_reg_txinit <= pi_decoder_data(1 downto 1); - end if; - end if; - end if; - end process; - -- - po_reg.txinit.data <= field_reg_txinit; -- - end block txinit_storage; - ------------------------------------------------------------STORAGE - rxinit_storage: block - begin - prs_write : process(pi_clock) - begin - if rising_edge(pi_clock) then - if pi_reset = '1' then - field_reg_rxinit <= std_logic_vector(to_signed(1,1)); - else - -- HW -- - -- SW -- - if pi_decoder_wr_stb = '1' then - field_reg_rxinit <= pi_decoder_data(2 downto 2); - end if; - end if; - end if; - end process; - -- - po_reg.rxinit.data <= field_reg_rxinit; -- - end block rxinit_storage; - ---------------------------------------------------------- -end rtl; ------------------------------------------------ --- register type: msk_ctrl ------------------------------------------------ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library desyrdl; -use desyrdl.common.all; - -use work.pkg_msk_top_regs.all; - -entity msk_top_regs_msk_ctrl is - port ( - pi_clock : in std_logic; - pi_reset : in std_logic; - -- to/from adapter - pi_decoder_rd_stb : in std_logic; - pi_decoder_wr_stb : in std_logic; - pi_decoder_data : in std_logic_vector(C_DATA_WIDTH-1 downto 0); - po_decoder_data : out std_logic_vector(C_DATA_WIDTH-1 downto 0); - - pi_reg : in t_reg_msk_ctrl_in ; - po_reg : out t_reg_msk_ctrl_out - ); -end entity msk_top_regs_msk_ctrl; - -architecture rtl of msk_top_regs_msk_ctrl is - - -- assign slices of data_out for each field, but force the rest to constant zeros - function fun_set_data_out ( -- - field_reg_ptt : std_logic_vector(1-1 downto 0); -- - field_reg_loopback_ena : std_logic_vector(1-1 downto 0); -- - field_reg_rx_invert : std_logic_vector(1-1 downto 0); -- - field_reg_clear_counts : std_logic_vector(1-1 downto 0); -- - field_reg_diff_encoder_loopback : std_logic_vector(1-1 downto 0)) -- - return std_logic_vector is - variable v_data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0); - begin - v_data_out := (others => '0'); - -- - v_data_out(0 downto 0) := field_reg_ptt; -- - v_data_out(1 downto 1) := field_reg_loopback_ena; -- - v_data_out(2 downto 2) := field_reg_rx_invert; -- - v_data_out(3 downto 3) := field_reg_clear_counts; -- - v_data_out(4 downto 4) := field_reg_diff_encoder_loopback; -- - return v_data_out; - end function fun_set_data_out; - - signal data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0'); - -- - signal field_reg_ptt : std_logic_vector(1-1 downto 0) - := std_logic_vector(to_signed(0,1)); -- - signal field_reg_loopback_ena : std_logic_vector(1-1 downto 0) - := std_logic_vector(to_signed(0,1)); -- - signal field_reg_rx_invert : std_logic_vector(1-1 downto 0) - := std_logic_vector(to_signed(0,1)); -- - signal field_reg_clear_counts : std_logic_vector(1-1 downto 0) - := std_logic_vector(to_signed(0,1)); -- - signal field_reg_diff_encoder_loopback : std_logic_vector(1-1 downto 0) - := std_logic_vector(to_signed(0,1)); -- -begin - - data_out <= fun_set_data_out( -- - field_reg_ptt, -- - field_reg_loopback_ena, -- - field_reg_rx_invert, -- - field_reg_clear_counts, -- - field_reg_diff_encoder_loopback -- - ); - - -- resize field data out to the register bus width - -- do only if 1 field and signed-- - po_decoder_data <= data_out; -- - ------------------------------------------------------------STORAGE - ptt_storage: block - begin - prs_write : process(pi_clock) - begin - if rising_edge(pi_clock) then - if pi_reset = '1' then - field_reg_ptt <= std_logic_vector(to_signed(0,1)); - else - -- HW -- - -- SW -- - if pi_decoder_wr_stb = '1' then - field_reg_ptt <= pi_decoder_data(0 downto 0); - end if; - end if; - end if; - end process; - -- - po_reg.ptt.data <= field_reg_ptt; -- - end block ptt_storage; - ------------------------------------------------------------STORAGE - loopback_ena_storage: block - begin - prs_write : process(pi_clock) - begin - if rising_edge(pi_clock) then - if pi_reset = '1' then - field_reg_loopback_ena <= std_logic_vector(to_signed(0,1)); - else - -- HW -- - -- SW -- - if pi_decoder_wr_stb = '1' then - field_reg_loopback_ena <= pi_decoder_data(1 downto 1); - end if; - end if; - end if; - end process; - -- - po_reg.loopback_ena.data <= field_reg_loopback_ena; -- - end block loopback_ena_storage; - ------------------------------------------------------------STORAGE - rx_invert_storage: block - begin - prs_write : process(pi_clock) - begin - if rising_edge(pi_clock) then - if pi_reset = '1' then - field_reg_rx_invert <= std_logic_vector(to_signed(0,1)); - else - -- HW -- - -- SW -- - if pi_decoder_wr_stb = '1' then - field_reg_rx_invert <= pi_decoder_data(2 downto 2); - end if; - end if; - end if; - end process; - -- - po_reg.rx_invert.data <= field_reg_rx_invert; -- - end block rx_invert_storage; - ------------------------------------------------------------STORAGE - clear_counts_storage: block - begin - prs_write : process(pi_clock) - begin - if rising_edge(pi_clock) then - if pi_reset = '1' then - field_reg_clear_counts <= std_logic_vector(to_signed(0,1)); - else - -- HW -- - -- This is a "singlepulse" register - clear on each clock, - -- unless it is written to with a 1 (see below) - field_reg_clear_counts <= (others => '0'); - -- SW -- - if pi_decoder_wr_stb = '1' then - field_reg_clear_counts <= pi_decoder_data(3 downto 3); - end if; - end if; - end if; - end process; - -- - po_reg.clear_counts.data <= field_reg_clear_counts; -- - end block clear_counts_storage; - ------------------------------------------------------------STORAGE - diff_encoder_loopback_storage: block - begin - prs_write : process(pi_clock) - begin - if rising_edge(pi_clock) then - if pi_reset = '1' then - field_reg_diff_encoder_loopback <= std_logic_vector(to_signed(0,1)); - else - -- HW -- - -- SW -- - if pi_decoder_wr_stb = '1' then - field_reg_diff_encoder_loopback <= pi_decoder_data(4 downto 4); - end if; - end if; - end if; - end process; - -- - po_reg.diff_encoder_loopback.data <= field_reg_diff_encoder_loopback; -- - end block diff_encoder_loopback_storage; - ---------------------------------------------------------- -end rtl; ------------------------------------------------ --- register type: msk_stat_0 ------------------------------------------------ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library desyrdl; -use desyrdl.common.all; - -use work.pkg_msk_top_regs.all; - -entity msk_top_regs_msk_stat_0 is - port ( - pi_clock : in std_logic; - pi_reset : in std_logic; - -- to/from adapter - pi_decoder_rd_stb : in std_logic; - pi_decoder_wr_stb : in std_logic; - pi_decoder_data : in std_logic_vector(C_DATA_WIDTH-1 downto 0); - po_decoder_data : out std_logic_vector(C_DATA_WIDTH-1 downto 0); - - pi_reg : in t_reg_msk_stat_0_in ; - po_reg : out t_reg_msk_stat_0_out - ); -end entity msk_top_regs_msk_stat_0; - -architecture rtl of msk_top_regs_msk_stat_0 is - - -- assign slices of data_out for each field, but force the rest to constant zeros - function fun_set_data_out ( -- - field_reg_demod_sync_lock : std_logic_vector(1-1 downto 0); -- - field_reg_tx_enable : std_logic_vector(1-1 downto 0); -- - field_reg_rx_enable : std_logic_vector(1-1 downto 0); -- - field_reg_tx_axis_valid : std_logic_vector(1-1 downto 0)) -- - return std_logic_vector is - variable v_data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0); - begin - v_data_out := (others => '0'); - -- - v_data_out(0 downto 0) := field_reg_demod_sync_lock; -- - v_data_out(1 downto 1) := field_reg_tx_enable; -- - v_data_out(2 downto 2) := field_reg_rx_enable; -- - v_data_out(3 downto 3) := field_reg_tx_axis_valid; -- - return v_data_out; - end function fun_set_data_out; - - signal data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0'); - -- - signal field_reg_demod_sync_lock : std_logic_vector(1-1 downto 0) - := std_logic_vector(to_signed(0,1)); -- - signal field_reg_tx_enable : std_logic_vector(1-1 downto 0) - := std_logic_vector(to_signed(0,1)); -- - signal field_reg_rx_enable : std_logic_vector(1-1 downto 0) - := std_logic_vector(to_signed(0,1)); -- - signal field_reg_tx_axis_valid : std_logic_vector(1-1 downto 0) - := std_logic_vector(to_signed(0,1)); -- -begin - - data_out <= fun_set_data_out( -- - field_reg_demod_sync_lock, -- - field_reg_tx_enable, -- - field_reg_rx_enable, -- - field_reg_tx_axis_valid -- - ); - - -- resize field data out to the register bus width - -- do only if 1 field and signed-- - po_decoder_data <= data_out; -- - ------------------------------------------------------------WIRE - demod_sync_lock_wire : block -- - begin - -- - field_reg_demod_sync_lock <= pi_reg.demod_sync_lock.data(1-1 downto 0); -- - --no signal to read by HW - po_reg.demod_sync_lock.dummy <= '0'; -- - end block; ----WIRE - tx_enable_wire : block -- - begin - -- - field_reg_tx_enable <= pi_reg.tx_enable.data(1-1 downto 0); -- - --no signal to read by HW - po_reg.tx_enable.dummy <= '0'; -- - end block; ----WIRE - rx_enable_wire : block -- - begin - -- - field_reg_rx_enable <= pi_reg.rx_enable.data(1-1 downto 0); -- - --no signal to read by HW - po_reg.rx_enable.dummy <= '0'; -- - end block; ----WIRE - tx_axis_valid_wire : block -- - begin - -- - field_reg_tx_axis_valid <= pi_reg.tx_axis_valid.data(1-1 downto 0); -- - --no signal to read by HW - po_reg.tx_axis_valid.dummy <= '0'; -- - end block; -- -end rtl; ------------------------------------------------ --- register type: msk_stat_1 ------------------------------------------------ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library desyrdl; -use desyrdl.common.all; - -use work.pkg_msk_top_regs.all; - -entity msk_top_regs_msk_stat_1 is - port ( - pi_clock : in std_logic; - pi_reset : in std_logic; - -- to/from adapter - pi_decoder_rd_stb : in std_logic; - pi_decoder_wr_stb : in std_logic; - pi_decoder_data : in std_logic_vector(C_DATA_WIDTH-1 downto 0); - po_decoder_data : out std_logic_vector(C_DATA_WIDTH-1 downto 0); - - pi_reg : in t_reg_msk_stat_1_in ; - po_reg : out t_reg_msk_stat_1_out - ); -end entity msk_top_regs_msk_stat_1; - -architecture rtl of msk_top_regs_msk_stat_1 is - - -- assign slices of data_out for each field, but force the rest to constant zeros - function fun_set_data_out ( -- - field_reg_tx_bit_counter : std_logic_vector(32-1 downto 0)) -- - return std_logic_vector is - variable v_data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0); - begin - v_data_out := (others => '0'); - -- - v_data_out(31 downto 0) := field_reg_tx_bit_counter; -- - return v_data_out; - end function fun_set_data_out; - - signal data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0'); - -- - signal field_reg_tx_bit_counter : std_logic_vector(32-1 downto 0) - := std_logic_vector(to_signed(0,32)); -- -begin - - data_out <= fun_set_data_out( -- - field_reg_tx_bit_counter -- - ); - - -- resize field data out to the register bus width - -- do only if 1 field and signed-- - po_decoder_data <= data_out; -- - ------------------------------------------------------------WIRE - tx_bit_counter_wire : block -- - begin - -- - field_reg_tx_bit_counter <= pi_reg.tx_bit_counter.data(32-1 downto 0); -- - --no signal to read by HW - po_reg.tx_bit_counter.dummy <= '0'; -- - end block; -- -end rtl; ------------------------------------------------ --- register type: msk_stat_2 ------------------------------------------------ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library desyrdl; -use desyrdl.common.all; - -use work.pkg_msk_top_regs.all; - -entity msk_top_regs_msk_stat_2 is - port ( - pi_clock : in std_logic; - pi_reset : in std_logic; - -- to/from adapter - pi_decoder_rd_stb : in std_logic; - pi_decoder_wr_stb : in std_logic; - pi_decoder_data : in std_logic_vector(C_DATA_WIDTH-1 downto 0); - po_decoder_data : out std_logic_vector(C_DATA_WIDTH-1 downto 0); - - pi_reg : in t_reg_msk_stat_2_in ; - po_reg : out t_reg_msk_stat_2_out - ); -end entity msk_top_regs_msk_stat_2; - -architecture rtl of msk_top_regs_msk_stat_2 is - - -- assign slices of data_out for each field, but force the rest to constant zeros - function fun_set_data_out ( -- - field_reg_tx_ena_counter : std_logic_vector(32-1 downto 0)) -- - return std_logic_vector is - variable v_data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0); - begin - v_data_out := (others => '0'); - -- - v_data_out(31 downto 0) := field_reg_tx_ena_counter; -- - return v_data_out; - end function fun_set_data_out; - - signal data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0'); - -- - signal field_reg_tx_ena_counter : std_logic_vector(32-1 downto 0) - := std_logic_vector(to_signed(0,32)); -- -begin - - data_out <= fun_set_data_out( -- - field_reg_tx_ena_counter -- - ); - - -- resize field data out to the register bus width - -- do only if 1 field and signed-- - po_decoder_data <= data_out; -- - ------------------------------------------------------------WIRE - tx_ena_counter_wire : block -- - begin - -- - field_reg_tx_ena_counter <= pi_reg.tx_ena_counter.data(32-1 downto 0); -- - --no signal to read by HW - po_reg.tx_ena_counter.dummy <= '0'; -- - end block; -- -end rtl; ------------------------------------------------ --- register type: config_nco_fw ------------------------------------------------ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library desyrdl; -use desyrdl.common.all; - -use work.pkg_msk_top_regs.all; - -entity msk_top_regs_config_nco_fw is - port ( - pi_clock : in std_logic; - pi_reset : in std_logic; - -- to/from adapter - pi_decoder_rd_stb : in std_logic; - pi_decoder_wr_stb : in std_logic; - pi_decoder_data : in std_logic_vector(C_DATA_WIDTH-1 downto 0); - po_decoder_data : out std_logic_vector(C_DATA_WIDTH-1 downto 0); - - pi_reg : in t_reg_config_nco_fw_in ; - po_reg : out t_reg_config_nco_fw_out - ); -end entity msk_top_regs_config_nco_fw; - -architecture rtl of msk_top_regs_config_nco_fw is - - -- assign slices of data_out for each field, but force the rest to constant zeros - function fun_set_data_out ( -- - field_reg_config_data : std_logic_vector(32-1 downto 0)) -- - return std_logic_vector is - variable v_data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0); - begin - v_data_out := (others => '0'); - -- - v_data_out(31 downto 0) := field_reg_config_data; -- - return v_data_out; - end function fun_set_data_out; - - signal data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0'); - -- - signal field_reg_config_data : std_logic_vector(32-1 downto 0) - := std_logic_vector(to_signed(0,32)); -- -begin - - data_out <= fun_set_data_out( -- - field_reg_config_data -- - ); - - -- resize field data out to the register bus width - -- do only if 1 field and signed-- - po_decoder_data <= data_out; -- - ------------------------------------------------------------STORAGE - config_data_storage: block - begin - prs_write : process(pi_clock) - begin - if rising_edge(pi_clock) then - if pi_reset = '1' then - field_reg_config_data <= std_logic_vector(to_signed(0,32)); - else - -- HW -- - -- SW -- - if pi_decoder_wr_stb = '1' then - field_reg_config_data <= pi_decoder_data(31 downto 0); - end if; - end if; - end if; - end process; - -- - po_reg.config_data.data <= field_reg_config_data; -- - end block config_data_storage; - ---------------------------------------------------------- -end rtl; ------------------------------------------------ --- register type: lpf_config_0 ------------------------------------------------ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library desyrdl; -use desyrdl.common.all; - -use work.pkg_msk_top_regs.all; - -entity msk_top_regs_lpf_config_0 is - port ( - pi_clock : in std_logic; - pi_reset : in std_logic; - -- to/from adapter - pi_decoder_rd_stb : in std_logic; - pi_decoder_wr_stb : in std_logic; - pi_decoder_data : in std_logic_vector(C_DATA_WIDTH-1 downto 0); - po_decoder_data : out std_logic_vector(C_DATA_WIDTH-1 downto 0); - - pi_reg : in t_reg_lpf_config_0_in ; - po_reg : out t_reg_lpf_config_0_out - ); -end entity msk_top_regs_lpf_config_0; - -architecture rtl of msk_top_regs_lpf_config_0 is - - -- assign slices of data_out for each field, but force the rest to constant zeros - function fun_set_data_out ( -- - field_reg_lpf_freeze : std_logic_vector(1-1 downto 0); -- - field_reg_lpf_zero : std_logic_vector(1-1 downto 0); -- - field_reg_prbs_reserved : std_logic_vector(6-1 downto 0); -- - field_reg_lpf_alpha : std_logic_vector(24-1 downto 0)) -- - return std_logic_vector is - variable v_data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0); - begin - v_data_out := (others => '0'); - -- - v_data_out(0 downto 0) := field_reg_lpf_freeze; -- - v_data_out(1 downto 1) := field_reg_lpf_zero; -- - v_data_out(7 downto 2) := field_reg_prbs_reserved; -- - v_data_out(31 downto 8) := field_reg_lpf_alpha; -- - return v_data_out; - end function fun_set_data_out; - - signal data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0'); - -- - signal field_reg_lpf_freeze : std_logic_vector(1-1 downto 0) - := std_logic_vector(to_signed(0,1)); -- - signal field_reg_lpf_zero : std_logic_vector(1-1 downto 0) - := std_logic_vector(to_signed(0,1)); -- - signal field_reg_prbs_reserved : std_logic_vector(6-1 downto 0) - := std_logic_vector(to_signed(0,6)); -- - signal field_reg_lpf_alpha : std_logic_vector(24-1 downto 0) - := std_logic_vector(to_signed(0,24)); -- -begin - - data_out <= fun_set_data_out( -- - field_reg_lpf_freeze, -- - field_reg_lpf_zero, -- - field_reg_prbs_reserved, -- - field_reg_lpf_alpha -- - ); - - -- resize field data out to the register bus width - -- do only if 1 field and signed-- - po_decoder_data <= data_out; -- - ------------------------------------------------------------STORAGE - lpf_freeze_storage: block - begin - prs_write : process(pi_clock) - begin - if rising_edge(pi_clock) then - if pi_reset = '1' then - field_reg_lpf_freeze <= std_logic_vector(to_signed(0,1)); - else - -- HW -- - -- SW -- - if pi_decoder_wr_stb = '1' then - field_reg_lpf_freeze <= pi_decoder_data(0 downto 0); - end if; - end if; - end if; - end process; - -- - po_reg.lpf_freeze.data <= field_reg_lpf_freeze; -- - end block lpf_freeze_storage; - ------------------------------------------------------------STORAGE - lpf_zero_storage: block - begin - prs_write : process(pi_clock) - begin - if rising_edge(pi_clock) then - if pi_reset = '1' then - field_reg_lpf_zero <= std_logic_vector(to_signed(0,1)); - else - -- HW -- - -- SW -- - if pi_decoder_wr_stb = '1' then - field_reg_lpf_zero <= pi_decoder_data(1 downto 1); - end if; - end if; - end if; - end process; - -- - po_reg.lpf_zero.data <= field_reg_lpf_zero; -- - end block lpf_zero_storage; - ------------------------------------------------------------STORAGE - prbs_reserved_storage: block - begin - prs_write : process(pi_clock) - begin - if rising_edge(pi_clock) then - if pi_reset = '1' then - field_reg_prbs_reserved <= std_logic_vector(to_signed(0,6)); - else - -- HW -- - -- SW -- - if pi_decoder_wr_stb = '1' then - field_reg_prbs_reserved <= pi_decoder_data(7 downto 2); - end if; - end if; - end if; - end process; - -- - po_reg.prbs_reserved.data <= field_reg_prbs_reserved; -- - end block prbs_reserved_storage; - ------------------------------------------------------------STORAGE - lpf_alpha_storage: block - begin - prs_write : process(pi_clock) - begin - if rising_edge(pi_clock) then - if pi_reset = '1' then - field_reg_lpf_alpha <= std_logic_vector(to_signed(0,24)); - else - -- HW -- - -- SW -- - if pi_decoder_wr_stb = '1' then - field_reg_lpf_alpha <= pi_decoder_data(31 downto 8); - end if; - end if; - end if; - end process; - -- - po_reg.lpf_alpha.data <= field_reg_lpf_alpha; -- - end block lpf_alpha_storage; - ---------------------------------------------------------- -end rtl; ------------------------------------------------ --- register type: lpf_config_1 ------------------------------------------------ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library desyrdl; -use desyrdl.common.all; - -use work.pkg_msk_top_regs.all; - -entity msk_top_regs_lpf_config_1 is - port ( - pi_clock : in std_logic; - pi_reset : in std_logic; - -- to/from adapter - pi_decoder_rd_stb : in std_logic; - pi_decoder_wr_stb : in std_logic; - pi_decoder_data : in std_logic_vector(C_DATA_WIDTH-1 downto 0); - po_decoder_data : out std_logic_vector(C_DATA_WIDTH-1 downto 0); - - pi_reg : in t_reg_lpf_config_1_in ; - po_reg : out t_reg_lpf_config_1_out - ); -end entity msk_top_regs_lpf_config_1; - -architecture rtl of msk_top_regs_lpf_config_1 is - - -- assign slices of data_out for each field, but force the rest to constant zeros - function fun_set_data_out ( -- - field_reg_i_gain : std_logic_vector(24-1 downto 0); -- - field_reg_i_shift : std_logic_vector(8-1 downto 0)) -- - return std_logic_vector is - variable v_data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0); - begin - v_data_out := (others => '0'); - -- - v_data_out(23 downto 0) := field_reg_i_gain; -- - v_data_out(31 downto 24) := field_reg_i_shift; -- - return v_data_out; - end function fun_set_data_out; - - signal data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0'); - -- - signal field_reg_i_gain : std_logic_vector(24-1 downto 0) - := std_logic_vector(to_signed(0,24)); -- - signal field_reg_i_shift : std_logic_vector(8-1 downto 0) - := std_logic_vector(to_signed(0,8)); -- -begin - - data_out <= fun_set_data_out( -- - field_reg_i_gain, -- - field_reg_i_shift -- - ); - - -- resize field data out to the register bus width - -- do only if 1 field and signed-- - po_decoder_data <= data_out; -- - ------------------------------------------------------------STORAGE - i_gain_storage: block - begin - prs_write : process(pi_clock) - begin - if rising_edge(pi_clock) then - if pi_reset = '1' then - field_reg_i_gain <= std_logic_vector(to_signed(0,24)); - else - -- HW -- - -- SW -- - if pi_decoder_wr_stb = '1' then - field_reg_i_gain <= pi_decoder_data(23 downto 0); - end if; - end if; - end if; - end process; - -- - po_reg.i_gain.data <= field_reg_i_gain; -- - end block i_gain_storage; - ------------------------------------------------------------STORAGE - i_shift_storage: block - begin - prs_write : process(pi_clock) - begin - if rising_edge(pi_clock) then - if pi_reset = '1' then - field_reg_i_shift <= std_logic_vector(to_signed(0,8)); - else - -- HW -- - -- SW -- - if pi_decoder_wr_stb = '1' then - field_reg_i_shift <= pi_decoder_data(31 downto 24); - end if; - end if; - end if; - end process; - -- - po_reg.i_shift.data <= field_reg_i_shift; -- - end block i_shift_storage; - ---------------------------------------------------------- -end rtl; ------------------------------------------------ --- register type: data_width ------------------------------------------------ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library desyrdl; -use desyrdl.common.all; - -use work.pkg_msk_top_regs.all; - -entity msk_top_regs_data_width is - port ( - pi_clock : in std_logic; - pi_reset : in std_logic; - -- to/from adapter - pi_decoder_rd_stb : in std_logic; - pi_decoder_wr_stb : in std_logic; - pi_decoder_data : in std_logic_vector(C_DATA_WIDTH-1 downto 0); - po_decoder_data : out std_logic_vector(C_DATA_WIDTH-1 downto 0); - - pi_reg : in t_reg_data_width_in ; - po_reg : out t_reg_data_width_out - ); -end entity msk_top_regs_data_width; - -architecture rtl of msk_top_regs_data_width is - - -- assign slices of data_out for each field, but force the rest to constant zeros - function fun_set_data_out ( -- - field_reg_data_width : std_logic_vector(8-1 downto 0)) -- - return std_logic_vector is - variable v_data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0); - begin - v_data_out := (others => '0'); - -- - v_data_out(7 downto 0) := field_reg_data_width; -- - return v_data_out; - end function fun_set_data_out; - - signal data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0'); - -- - signal field_reg_data_width : std_logic_vector(8-1 downto 0) - := std_logic_vector(to_signed(8,8)); -- -begin - - data_out <= fun_set_data_out( -- - field_reg_data_width -- - ); - - -- resize field data out to the register bus width - -- do only if 1 field and signed-- - po_decoder_data <= data_out; -- - ------------------------------------------------------------STORAGE - data_width_storage: block - begin - prs_write : process(pi_clock) - begin - if rising_edge(pi_clock) then - if pi_reset = '1' then - field_reg_data_width <= std_logic_vector(to_signed(8,8)); - else - -- HW -- - -- SW -- - if pi_decoder_wr_stb = '1' then - field_reg_data_width <= pi_decoder_data(7 downto 0); - end if; - end if; - end if; - end process; - -- - po_reg.data_width.data <= field_reg_data_width; -- - end block data_width_storage; - ---------------------------------------------------------- -end rtl; ------------------------------------------------ --- register type: prbs_ctrl ------------------------------------------------ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library desyrdl; -use desyrdl.common.all; - -use work.pkg_msk_top_regs.all; - -entity msk_top_regs_prbs_ctrl is - port ( - pi_clock : in std_logic; - pi_reset : in std_logic; - -- to/from adapter - pi_decoder_rd_stb : in std_logic; - pi_decoder_wr_stb : in std_logic; - pi_decoder_data : in std_logic_vector(C_DATA_WIDTH-1 downto 0); - po_decoder_data : out std_logic_vector(C_DATA_WIDTH-1 downto 0); - - pi_reg : in t_reg_prbs_ctrl_in ; - po_reg : out t_reg_prbs_ctrl_out - ); -end entity msk_top_regs_prbs_ctrl; - -architecture rtl of msk_top_regs_prbs_ctrl is - - -- assign slices of data_out for each field, but force the rest to constant zeros - function fun_set_data_out ( -- - field_reg_prbs_sel : std_logic_vector(1-1 downto 0); -- - field_reg_prbs_error_insert : std_logic_vector(1-1 downto 0); -- - field_reg_prbs_clear : std_logic_vector(1-1 downto 0); -- - field_reg_prbs_manual_sync : std_logic_vector(1-1 downto 0); -- - field_reg_prbs_reserved : std_logic_vector(12-1 downto 0); -- - field_reg_prbs_sync_threshold : std_logic_vector(16-1 downto 0)) -- - return std_logic_vector is - variable v_data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0); - begin - v_data_out := (others => '0'); - -- - v_data_out(0 downto 0) := field_reg_prbs_sel; -- - v_data_out(1 downto 1) := field_reg_prbs_error_insert; -- - v_data_out(2 downto 2) := field_reg_prbs_clear; -- - v_data_out(3 downto 3) := field_reg_prbs_manual_sync; -- - v_data_out(15 downto 4) := field_reg_prbs_reserved; -- - v_data_out(31 downto 16) := field_reg_prbs_sync_threshold; -- - return v_data_out; - end function fun_set_data_out; - - signal data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0'); - -- - signal field_reg_prbs_sel : std_logic_vector(1-1 downto 0) - := std_logic_vector(to_signed(0,1)); -- - signal field_reg_prbs_error_insert : std_logic_vector(1-1 downto 0) - := std_logic_vector(to_signed(0,1)); -- - signal field_reg_prbs_clear : std_logic_vector(1-1 downto 0) - := std_logic_vector(to_signed(0,1)); -- - signal field_reg_prbs_manual_sync : std_logic_vector(1-1 downto 0) - := std_logic_vector(to_signed(0,1)); -- - signal field_reg_prbs_reserved : std_logic_vector(12-1 downto 0) - := std_logic_vector(to_signed(0,12)); -- - signal field_reg_prbs_sync_threshold : std_logic_vector(16-1 downto 0) - := std_logic_vector(to_signed(0,16)); -- -begin - - data_out <= fun_set_data_out( -- - field_reg_prbs_sel, -- - field_reg_prbs_error_insert, -- - field_reg_prbs_clear, -- - field_reg_prbs_manual_sync, -- - field_reg_prbs_reserved, -- - field_reg_prbs_sync_threshold -- - ); - - -- resize field data out to the register bus width - -- do only if 1 field and signed-- - po_decoder_data <= data_out; -- - ------------------------------------------------------------STORAGE - prbs_sel_storage: block - begin - prs_write : process(pi_clock) - begin - if rising_edge(pi_clock) then - if pi_reset = '1' then - field_reg_prbs_sel <= std_logic_vector(to_signed(0,1)); - else - -- HW -- - -- SW -- - if pi_decoder_wr_stb = '1' then - field_reg_prbs_sel <= pi_decoder_data(0 downto 0); - end if; - end if; - end if; - end process; - -- - po_reg.prbs_sel.data <= field_reg_prbs_sel; -- - end block prbs_sel_storage; - ------------------------------------------------------------STORAGE - prbs_error_insert_storage: block - begin - prs_write : process(pi_clock) - begin - if rising_edge(pi_clock) then - if pi_reset = '1' then - field_reg_prbs_error_insert <= std_logic_vector(to_signed(0,1)); - else - -- HW -- - -- This is a "singlepulse" register - clear on each clock, - -- unless it is written to with a 1 (see below) - field_reg_prbs_error_insert <= (others => '0'); - -- SW -- - if pi_decoder_wr_stb = '1' then - field_reg_prbs_error_insert <= pi_decoder_data(1 downto 1); - end if; - end if; - end if; - end process; - -- - po_reg.prbs_error_insert.data <= field_reg_prbs_error_insert; -- - end block prbs_error_insert_storage; - ------------------------------------------------------------STORAGE - prbs_clear_storage: block - begin - prs_write : process(pi_clock) - begin - if rising_edge(pi_clock) then - if pi_reset = '1' then - field_reg_prbs_clear <= std_logic_vector(to_signed(0,1)); - else - -- HW -- - -- This is a "singlepulse" register - clear on each clock, - -- unless it is written to with a 1 (see below) - field_reg_prbs_clear <= (others => '0'); - -- SW -- - if pi_decoder_wr_stb = '1' then - field_reg_prbs_clear <= pi_decoder_data(2 downto 2); - end if; - end if; - end if; - end process; - -- - po_reg.prbs_clear.data <= field_reg_prbs_clear; -- - end block prbs_clear_storage; - ------------------------------------------------------------STORAGE - prbs_manual_sync_storage: block - begin - prs_write : process(pi_clock) - begin - if rising_edge(pi_clock) then - if pi_reset = '1' then - field_reg_prbs_manual_sync <= std_logic_vector(to_signed(0,1)); - else - -- HW -- - -- This is a "singlepulse" register - clear on each clock, - -- unless it is written to with a 1 (see below) - field_reg_prbs_manual_sync <= (others => '0'); - -- SW -- - if pi_decoder_wr_stb = '1' then - field_reg_prbs_manual_sync <= pi_decoder_data(3 downto 3); - end if; - end if; - end if; - end process; - -- - po_reg.prbs_manual_sync.data <= field_reg_prbs_manual_sync; -- - end block prbs_manual_sync_storage; - ------------------------------------------------------------STORAGE - prbs_reserved_storage: block - begin - prs_write : process(pi_clock) - begin - if rising_edge(pi_clock) then - if pi_reset = '1' then - field_reg_prbs_reserved <= std_logic_vector(to_signed(0,12)); - else - -- HW -- - -- SW -- - if pi_decoder_wr_stb = '1' then - field_reg_prbs_reserved <= pi_decoder_data(15 downto 4); - end if; - end if; - end if; - end process; - -- - po_reg.prbs_reserved.data <= field_reg_prbs_reserved; -- - end block prbs_reserved_storage; - ------------------------------------------------------------STORAGE - prbs_sync_threshold_storage: block - begin - prs_write : process(pi_clock) - begin - if rising_edge(pi_clock) then - if pi_reset = '1' then - field_reg_prbs_sync_threshold <= std_logic_vector(to_signed(0,16)); - else - -- HW -- - -- SW -- - if pi_decoder_wr_stb = '1' then - field_reg_prbs_sync_threshold <= pi_decoder_data(31 downto 16); - end if; - end if; - end if; - end process; - -- - po_reg.prbs_sync_threshold.data <= field_reg_prbs_sync_threshold; -- - end block prbs_sync_threshold_storage; - ---------------------------------------------------------- -end rtl; ------------------------------------------------ --- register type: config_prbs_seed ------------------------------------------------ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library desyrdl; -use desyrdl.common.all; - -use work.pkg_msk_top_regs.all; - -entity msk_top_regs_config_prbs_seed is - port ( - pi_clock : in std_logic; - pi_reset : in std_logic; - -- to/from adapter - pi_decoder_rd_stb : in std_logic; - pi_decoder_wr_stb : in std_logic; - pi_decoder_data : in std_logic_vector(C_DATA_WIDTH-1 downto 0); - po_decoder_data : out std_logic_vector(C_DATA_WIDTH-1 downto 0); - - pi_reg : in t_reg_config_prbs_seed_in ; - po_reg : out t_reg_config_prbs_seed_out - ); -end entity msk_top_regs_config_prbs_seed; - -architecture rtl of msk_top_regs_config_prbs_seed is - - -- assign slices of data_out for each field, but force the rest to constant zeros - function fun_set_data_out ( -- - field_reg_config_data : std_logic_vector(32-1 downto 0)) -- - return std_logic_vector is - variable v_data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0); - begin - v_data_out := (others => '0'); - -- - v_data_out(31 downto 0) := field_reg_config_data; -- - return v_data_out; - end function fun_set_data_out; - - signal data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0'); - -- - signal field_reg_config_data : std_logic_vector(32-1 downto 0) - := std_logic_vector(to_signed(0,32)); -- -begin - - data_out <= fun_set_data_out( -- - field_reg_config_data -- - ); - - -- resize field data out to the register bus width - -- do only if 1 field and signed-- - po_decoder_data <= data_out; -- - ------------------------------------------------------------STORAGE - config_data_storage: block - begin - prs_write : process(pi_clock) - begin - if rising_edge(pi_clock) then - if pi_reset = '1' then - field_reg_config_data <= std_logic_vector(to_signed(0,32)); - else - -- HW -- - -- SW -- - if pi_decoder_wr_stb = '1' then - field_reg_config_data <= pi_decoder_data(31 downto 0); - end if; - end if; - end if; - end process; - -- - po_reg.config_data.data <= field_reg_config_data; -- - end block config_data_storage; - ---------------------------------------------------------- -end rtl; ------------------------------------------------ --- register type: config_prbs_poly ------------------------------------------------ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library desyrdl; -use desyrdl.common.all; - -use work.pkg_msk_top_regs.all; - -entity msk_top_regs_config_prbs_poly is - port ( - pi_clock : in std_logic; - pi_reset : in std_logic; - -- to/from adapter - pi_decoder_rd_stb : in std_logic; - pi_decoder_wr_stb : in std_logic; - pi_decoder_data : in std_logic_vector(C_DATA_WIDTH-1 downto 0); - po_decoder_data : out std_logic_vector(C_DATA_WIDTH-1 downto 0); - - pi_reg : in t_reg_config_prbs_poly_in ; - po_reg : out t_reg_config_prbs_poly_out - ); -end entity msk_top_regs_config_prbs_poly; - -architecture rtl of msk_top_regs_config_prbs_poly is - - -- assign slices of data_out for each field, but force the rest to constant zeros - function fun_set_data_out ( -- - field_reg_config_data : std_logic_vector(32-1 downto 0)) -- - return std_logic_vector is - variable v_data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0); - begin - v_data_out := (others => '0'); - -- - v_data_out(31 downto 0) := field_reg_config_data; -- - return v_data_out; - end function fun_set_data_out; - - signal data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0'); - -- - signal field_reg_config_data : std_logic_vector(32-1 downto 0) - := std_logic_vector(to_signed(0,32)); -- -begin - - data_out <= fun_set_data_out( -- - field_reg_config_data -- - ); - - -- resize field data out to the register bus width - -- do only if 1 field and signed-- - po_decoder_data <= data_out; -- - ------------------------------------------------------------STORAGE - config_data_storage: block - begin - prs_write : process(pi_clock) - begin - if rising_edge(pi_clock) then - if pi_reset = '1' then - field_reg_config_data <= std_logic_vector(to_signed(0,32)); - else - -- HW -- - -- SW -- - if pi_decoder_wr_stb = '1' then - field_reg_config_data <= pi_decoder_data(31 downto 0); - end if; - end if; - end if; - end process; - -- - po_reg.config_data.data <= field_reg_config_data; -- - end block config_data_storage; - ---------------------------------------------------------- -end rtl; ------------------------------------------------ --- register type: config_prbs_errmask ------------------------------------------------ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library desyrdl; -use desyrdl.common.all; - -use work.pkg_msk_top_regs.all; - -entity msk_top_regs_config_prbs_errmask is - port ( - pi_clock : in std_logic; - pi_reset : in std_logic; - -- to/from adapter - pi_decoder_rd_stb : in std_logic; - pi_decoder_wr_stb : in std_logic; - pi_decoder_data : in std_logic_vector(C_DATA_WIDTH-1 downto 0); - po_decoder_data : out std_logic_vector(C_DATA_WIDTH-1 downto 0); - - pi_reg : in t_reg_config_prbs_errmask_in ; - po_reg : out t_reg_config_prbs_errmask_out - ); -end entity msk_top_regs_config_prbs_errmask; - -architecture rtl of msk_top_regs_config_prbs_errmask is - - -- assign slices of data_out for each field, but force the rest to constant zeros - function fun_set_data_out ( -- - field_reg_config_data : std_logic_vector(32-1 downto 0)) -- - return std_logic_vector is - variable v_data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0); - begin - v_data_out := (others => '0'); - -- - v_data_out(31 downto 0) := field_reg_config_data; -- - return v_data_out; - end function fun_set_data_out; - - signal data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0'); - -- - signal field_reg_config_data : std_logic_vector(32-1 downto 0) - := std_logic_vector(to_signed(0,32)); -- -begin - - data_out <= fun_set_data_out( -- - field_reg_config_data -- - ); - - -- resize field data out to the register bus width - -- do only if 1 field and signed-- - po_decoder_data <= data_out; -- - ------------------------------------------------------------STORAGE - config_data_storage: block - begin - prs_write : process(pi_clock) - begin - if rising_edge(pi_clock) then - if pi_reset = '1' then - field_reg_config_data <= std_logic_vector(to_signed(0,32)); - else - -- HW -- - -- SW -- - if pi_decoder_wr_stb = '1' then - field_reg_config_data <= pi_decoder_data(31 downto 0); - end if; - end if; - end if; - end process; - -- - po_reg.config_data.data <= field_reg_config_data; -- - end block config_data_storage; - ---------------------------------------------------------- -end rtl; ------------------------------------------------ --- register type: stat_32_bits ------------------------------------------------ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library desyrdl; -use desyrdl.common.all; - -use work.pkg_msk_top_regs.all; - -entity msk_top_regs_stat_32_bits is - port ( - pi_clock : in std_logic; - pi_reset : in std_logic; - -- to/from adapter - pi_decoder_rd_stb : in std_logic; - pi_decoder_wr_stb : in std_logic; - pi_decoder_data : in std_logic_vector(C_DATA_WIDTH-1 downto 0); - po_decoder_data : out std_logic_vector(C_DATA_WIDTH-1 downto 0); - - pi_reg : in t_reg_stat_32_bits_in ; - po_reg : out t_reg_stat_32_bits_out - ); -end entity msk_top_regs_stat_32_bits; - -architecture rtl of msk_top_regs_stat_32_bits is - - -- assign slices of data_out for each field, but force the rest to constant zeros - function fun_set_data_out ( -- - field_reg_status_data : std_logic_vector(32-1 downto 0)) -- - return std_logic_vector is - variable v_data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0); - begin - v_data_out := (others => '0'); - -- - v_data_out(31 downto 0) := field_reg_status_data; -- - return v_data_out; - end function fun_set_data_out; - - signal data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0'); - -- - signal field_reg_status_data : std_logic_vector(32-1 downto 0) - := std_logic_vector(to_signed(0,32)); -- -begin - - data_out <= fun_set_data_out( -- - field_reg_status_data -- - ); - - -- resize field data out to the register bus width - -- do only if 1 field and signed-- - po_decoder_data <= data_out; -- - ------------------------------------------------------------WIRE - status_data_wire : block -- - begin - -- - field_reg_status_data <= pi_reg.status_data.data(32-1 downto 0); -- - --no signal to read by HW - po_reg.status_data.dummy <= '0'; -- - end block; -- -end rtl; ------------------------------------------------ --- register type: stat_32_errs ------------------------------------------------ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library desyrdl; -use desyrdl.common.all; - -use work.pkg_msk_top_regs.all; - -entity msk_top_regs_stat_32_errs is - port ( - pi_clock : in std_logic; - pi_reset : in std_logic; - -- to/from adapter - pi_decoder_rd_stb : in std_logic; - pi_decoder_wr_stb : in std_logic; - pi_decoder_data : in std_logic_vector(C_DATA_WIDTH-1 downto 0); - po_decoder_data : out std_logic_vector(C_DATA_WIDTH-1 downto 0); - - pi_reg : in t_reg_stat_32_errs_in ; - po_reg : out t_reg_stat_32_errs_out - ); -end entity msk_top_regs_stat_32_errs; - -architecture rtl of msk_top_regs_stat_32_errs is - - -- assign slices of data_out for each field, but force the rest to constant zeros - function fun_set_data_out ( -- - field_reg_status_data : std_logic_vector(32-1 downto 0)) -- - return std_logic_vector is - variable v_data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0); - begin - v_data_out := (others => '0'); - -- - v_data_out(31 downto 0) := field_reg_status_data; -- - return v_data_out; - end function fun_set_data_out; - - signal data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0'); - -- - signal field_reg_status_data : std_logic_vector(32-1 downto 0) - := std_logic_vector(to_signed(0,32)); -- -begin - - data_out <= fun_set_data_out( -- - field_reg_status_data -- - ); - - -- resize field data out to the register bus width - -- do only if 1 field and signed-- - po_decoder_data <= data_out; -- - ------------------------------------------------------------WIRE - status_data_wire : block -- - begin - -- - field_reg_status_data <= pi_reg.status_data.data(32-1 downto 0); -- - --no signal to read by HW - po_reg.status_data.dummy <= '0'; -- - end block; -- -end rtl; ------------------------------------------------ --- register type: stat_32_lpf_acc ------------------------------------------------ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library desyrdl; -use desyrdl.common.all; - -use work.pkg_msk_top_regs.all; - -entity msk_top_regs_stat_32_lpf_acc is - port ( - pi_clock : in std_logic; - pi_reset : in std_logic; - -- to/from adapter - pi_decoder_rd_stb : in std_logic; - pi_decoder_wr_stb : in std_logic; - pi_decoder_data : in std_logic_vector(C_DATA_WIDTH-1 downto 0); - po_decoder_data : out std_logic_vector(C_DATA_WIDTH-1 downto 0); - - pi_reg : in t_reg_stat_32_lpf_acc_in ; - po_reg : out t_reg_stat_32_lpf_acc_out - ); -end entity msk_top_regs_stat_32_lpf_acc; - -architecture rtl of msk_top_regs_stat_32_lpf_acc is - - -- assign slices of data_out for each field, but force the rest to constant zeros - function fun_set_data_out ( -- - field_reg_status_data : std_logic_vector(32-1 downto 0)) -- - return std_logic_vector is - variable v_data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0); - begin - v_data_out := (others => '0'); - -- - v_data_out(31 downto 0) := field_reg_status_data; -- - return v_data_out; - end function fun_set_data_out; - - signal data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0'); - -- - signal field_reg_status_data : std_logic_vector(32-1 downto 0) - := std_logic_vector(to_signed(0,32)); -- -begin - - data_out <= fun_set_data_out( -- - field_reg_status_data -- - ); - - -- resize field data out to the register bus width - -- do only if 1 field and signed-- - po_decoder_data <= data_out; -- - ------------------------------------------------------------WIRE - status_data_wire : block -- - begin - -- - field_reg_status_data <= pi_reg.status_data.data(32-1 downto 0); -- - --no signal to read by HW - po_reg.status_data.dummy <= '0'; -- - end block; -- -end rtl; ------------------------------------------------ --- register type: msk_stat_3 ------------------------------------------------ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library desyrdl; -use desyrdl.common.all; - -use work.pkg_msk_top_regs.all; - -entity msk_top_regs_msk_stat_3 is - port ( - pi_clock : in std_logic; - pi_reset : in std_logic; - -- to/from adapter - pi_decoder_rd_stb : in std_logic; - pi_decoder_wr_stb : in std_logic; - pi_decoder_data : in std_logic_vector(C_DATA_WIDTH-1 downto 0); - po_decoder_data : out std_logic_vector(C_DATA_WIDTH-1 downto 0); - - pi_reg : in t_reg_msk_stat_3_in ; - po_reg : out t_reg_msk_stat_3_out - ); -end entity msk_top_regs_msk_stat_3; - -architecture rtl of msk_top_regs_msk_stat_3 is - - -- assign slices of data_out for each field, but force the rest to constant zeros - function fun_set_data_out ( -- - field_reg_xfer_count : std_logic_vector(32-1 downto 0)) -- - return std_logic_vector is - variable v_data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0); - begin - v_data_out := (others => '0'); - -- - v_data_out(31 downto 0) := field_reg_xfer_count; -- - return v_data_out; - end function fun_set_data_out; - - signal data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0'); - -- - signal field_reg_xfer_count : std_logic_vector(32-1 downto 0) - := std_logic_vector(to_signed(0,32)); -- -begin - - data_out <= fun_set_data_out( -- - field_reg_xfer_count -- - ); - - -- resize field data out to the register bus width - -- do only if 1 field and signed-- - po_decoder_data <= data_out; -- - ------------------------------------------------------------WIRE - xfer_count_wire : block -- - begin - -- - field_reg_xfer_count <= pi_reg.xfer_count.data(32-1 downto 0); -- - --no signal to read by HW - po_reg.xfer_count.dummy <= '0'; -- - end block; -- -end rtl; ------------------------------------------------ --- register type: rx_sample_discard ------------------------------------------------ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library desyrdl; -use desyrdl.common.all; - -use work.pkg_msk_top_regs.all; - -entity msk_top_regs_rx_sample_discard is - port ( - pi_clock : in std_logic; - pi_reset : in std_logic; - -- to/from adapter - pi_decoder_rd_stb : in std_logic; - pi_decoder_wr_stb : in std_logic; - pi_decoder_data : in std_logic_vector(C_DATA_WIDTH-1 downto 0); - po_decoder_data : out std_logic_vector(C_DATA_WIDTH-1 downto 0); - - pi_reg : in t_reg_rx_sample_discard_in ; - po_reg : out t_reg_rx_sample_discard_out - ); -end entity msk_top_regs_rx_sample_discard; - -architecture rtl of msk_top_regs_rx_sample_discard is - - -- assign slices of data_out for each field, but force the rest to constant zeros - function fun_set_data_out ( -- - field_reg_rx_sample_discard : std_logic_vector(8-1 downto 0); -- - field_reg_rx_nco_discard : std_logic_vector(8-1 downto 0)) -- - return std_logic_vector is - variable v_data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0); - begin - v_data_out := (others => '0'); - -- - v_data_out(7 downto 0) := field_reg_rx_sample_discard; -- - v_data_out(15 downto 8) := field_reg_rx_nco_discard; -- - return v_data_out; - end function fun_set_data_out; - - signal data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0'); - -- - signal field_reg_rx_sample_discard : std_logic_vector(8-1 downto 0) - := std_logic_vector(to_signed(0,8)); -- - signal field_reg_rx_nco_discard : std_logic_vector(8-1 downto 0) - := std_logic_vector(to_signed(0,8)); -- -begin - - data_out <= fun_set_data_out( -- - field_reg_rx_sample_discard, -- - field_reg_rx_nco_discard -- - ); - - -- resize field data out to the register bus width - -- do only if 1 field and signed-- - po_decoder_data <= data_out; -- - ------------------------------------------------------------STORAGE - rx_sample_discard_storage: block - begin - prs_write : process(pi_clock) - begin - if rising_edge(pi_clock) then - if pi_reset = '1' then - field_reg_rx_sample_discard <= std_logic_vector(to_signed(0,8)); - else - -- HW -- - -- SW -- - if pi_decoder_wr_stb = '1' then - field_reg_rx_sample_discard <= pi_decoder_data(7 downto 0); - end if; - end if; - end if; - end process; - -- - po_reg.rx_sample_discard.data <= field_reg_rx_sample_discard; -- - end block rx_sample_discard_storage; - ------------------------------------------------------------STORAGE - rx_nco_discard_storage: block - begin - prs_write : process(pi_clock) - begin - if rising_edge(pi_clock) then - if pi_reset = '1' then - field_reg_rx_nco_discard <= std_logic_vector(to_signed(0,8)); - else - -- HW -- - -- SW -- - if pi_decoder_wr_stb = '1' then - field_reg_rx_nco_discard <= pi_decoder_data(15 downto 8); - end if; - end if; - end if; - end process; - -- - po_reg.rx_nco_discard.data <= field_reg_rx_nco_discard; -- - end block rx_nco_discard_storage; - ---------------------------------------------------------- -end rtl; ------------------------------------------------ --- register type: lpf_config_2 ------------------------------------------------ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library desyrdl; -use desyrdl.common.all; - -use work.pkg_msk_top_regs.all; - -entity msk_top_regs_lpf_config_2 is - port ( - pi_clock : in std_logic; - pi_reset : in std_logic; - -- to/from adapter - pi_decoder_rd_stb : in std_logic; - pi_decoder_wr_stb : in std_logic; - pi_decoder_data : in std_logic_vector(C_DATA_WIDTH-1 downto 0); - po_decoder_data : out std_logic_vector(C_DATA_WIDTH-1 downto 0); - - pi_reg : in t_reg_lpf_config_2_in ; - po_reg : out t_reg_lpf_config_2_out - ); -end entity msk_top_regs_lpf_config_2; - -architecture rtl of msk_top_regs_lpf_config_2 is - - -- assign slices of data_out for each field, but force the rest to constant zeros - function fun_set_data_out ( -- - field_reg_p_gain : std_logic_vector(24-1 downto 0); -- - field_reg_p_shift : std_logic_vector(8-1 downto 0)) -- - return std_logic_vector is - variable v_data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0); - begin - v_data_out := (others => '0'); - -- - v_data_out(23 downto 0) := field_reg_p_gain; -- - v_data_out(31 downto 24) := field_reg_p_shift; -- - return v_data_out; - end function fun_set_data_out; - - signal data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0'); - -- - signal field_reg_p_gain : std_logic_vector(24-1 downto 0) - := std_logic_vector(to_signed(0,24)); -- - signal field_reg_p_shift : std_logic_vector(8-1 downto 0) - := std_logic_vector(to_signed(0,8)); -- -begin - - data_out <= fun_set_data_out( -- - field_reg_p_gain, -- - field_reg_p_shift -- - ); - - -- resize field data out to the register bus width - -- do only if 1 field and signed-- - po_decoder_data <= data_out; -- - ------------------------------------------------------------STORAGE - p_gain_storage: block - begin - prs_write : process(pi_clock) - begin - if rising_edge(pi_clock) then - if pi_reset = '1' then - field_reg_p_gain <= std_logic_vector(to_signed(0,24)); - else - -- HW -- - -- SW -- - if pi_decoder_wr_stb = '1' then - field_reg_p_gain <= pi_decoder_data(23 downto 0); - end if; - end if; - end if; - end process; - -- - po_reg.p_gain.data <= field_reg_p_gain; -- - end block p_gain_storage; - ------------------------------------------------------------STORAGE - p_shift_storage: block - begin - prs_write : process(pi_clock) - begin - if rising_edge(pi_clock) then - if pi_reset = '1' then - field_reg_p_shift <= std_logic_vector(to_signed(0,8)); - else - -- HW -- - -- SW -- - if pi_decoder_wr_stb = '1' then - field_reg_p_shift <= pi_decoder_data(31 downto 24); - end if; - end if; - end if; - end process; - -- - po_reg.p_shift.data <= field_reg_p_shift; -- - end block p_shift_storage; - ---------------------------------------------------------- -end rtl; ------------------------------------------------ --- register type: observation_data ------------------------------------------------ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library desyrdl; -use desyrdl.common.all; - -use work.pkg_msk_top_regs.all; - -entity msk_top_regs_observation_data is - port ( - pi_clock : in std_logic; - pi_reset : in std_logic; - -- to/from adapter - pi_decoder_rd_stb : in std_logic; - pi_decoder_wr_stb : in std_logic; - pi_decoder_data : in std_logic_vector(C_DATA_WIDTH-1 downto 0); - po_decoder_data : out std_logic_vector(C_DATA_WIDTH-1 downto 0); - - pi_reg : in t_reg_observation_data_in ; - po_reg : out t_reg_observation_data_out - ); -end entity msk_top_regs_observation_data; - -architecture rtl of msk_top_regs_observation_data is - - -- assign slices of data_out for each field, but force the rest to constant zeros - function fun_set_data_out ( -- - field_reg_data32 : std_logic_vector(32-1 downto 0)) -- - return std_logic_vector is - variable v_data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0); - begin - v_data_out := (others => '0'); - -- - v_data_out(31 downto 0) := field_reg_data32; -- - return v_data_out; - end function fun_set_data_out; - - signal data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0'); - -- - signal field_reg_data32 : std_logic_vector(32-1 downto 0) - := std_logic_vector(to_signed(0,32)); -- -begin - - data_out <= fun_set_data_out( -- - field_reg_data32 -- - ); - - -- resize field data out to the register bus width - -- do only if 1 field and signed-- - po_decoder_data <= data_out; -- - ------------------------------------------------------------WIRE - data32_wire : block -- - begin - -- - field_reg_data32 <= pi_reg.data.data(32-1 downto 0); -- - --no signal to read by HW - po_reg.data.dummy <= '0'; -- - end block; -- -end rtl; ------------------------------------------------ --- register type: tx_sync_ctrl ------------------------------------------------ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library desyrdl; -use desyrdl.common.all; - -use work.pkg_msk_top_regs.all; - -entity msk_top_regs_tx_sync_ctrl is - port ( - pi_clock : in std_logic; - pi_reset : in std_logic; - -- to/from adapter - pi_decoder_rd_stb : in std_logic; - pi_decoder_wr_stb : in std_logic; - pi_decoder_data : in std_logic_vector(C_DATA_WIDTH-1 downto 0); - po_decoder_data : out std_logic_vector(C_DATA_WIDTH-1 downto 0); - - pi_reg : in t_reg_tx_sync_ctrl_in ; - po_reg : out t_reg_tx_sync_ctrl_out - ); -end entity msk_top_regs_tx_sync_ctrl; - -architecture rtl of msk_top_regs_tx_sync_ctrl is - - -- assign slices of data_out for each field, but force the rest to constant zeros - function fun_set_data_out ( -- - field_reg_tx_sync_ena : std_logic_vector(1-1 downto 0); -- - field_reg_tx_sync_force : std_logic_vector(1-1 downto 0); -- - field_reg_tx_sync_f1 : std_logic_vector(1-1 downto 0); -- - field_reg_tx_sync_f2 : std_logic_vector(1-1 downto 0)) -- - return std_logic_vector is - variable v_data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0); - begin - v_data_out := (others => '0'); - -- - v_data_out(0 downto 0) := field_reg_tx_sync_ena; -- - v_data_out(1 downto 1) := field_reg_tx_sync_force; -- - v_data_out(2 downto 2) := field_reg_tx_sync_f1; -- - v_data_out(3 downto 3) := field_reg_tx_sync_f2; -- - return v_data_out; - end function fun_set_data_out; - - signal data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0'); - -- - signal field_reg_tx_sync_ena : std_logic_vector(1-1 downto 0) - := std_logic_vector(to_signed(0,1)); -- - signal field_reg_tx_sync_force : std_logic_vector(1-1 downto 0) - := std_logic_vector(to_signed(0,1)); -- - signal field_reg_tx_sync_f1 : std_logic_vector(1-1 downto 0) - := std_logic_vector(to_signed(0,1)); -- - signal field_reg_tx_sync_f2 : std_logic_vector(1-1 downto 0) - := std_logic_vector(to_signed(0,1)); -- -begin - - data_out <= fun_set_data_out( -- - field_reg_tx_sync_ena, -- - field_reg_tx_sync_force, -- - field_reg_tx_sync_f1, -- - field_reg_tx_sync_f2 -- - ); - - -- resize field data out to the register bus width - -- do only if 1 field and signed-- - po_decoder_data <= data_out; -- - ------------------------------------------------------------STORAGE - tx_sync_ena_storage: block - begin - prs_write : process(pi_clock) - begin - if rising_edge(pi_clock) then - if pi_reset = '1' then - field_reg_tx_sync_ena <= std_logic_vector(to_signed(0,1)); - else - -- HW -- - -- SW -- - if pi_decoder_wr_stb = '1' then - field_reg_tx_sync_ena <= pi_decoder_data(0 downto 0); - end if; - end if; - end if; - end process; - -- - po_reg.tx_sync_ena.data <= field_reg_tx_sync_ena; -- - end block tx_sync_ena_storage; - ------------------------------------------------------------STORAGE - tx_sync_force_storage: block - begin - prs_write : process(pi_clock) - begin - if rising_edge(pi_clock) then - if pi_reset = '1' then - field_reg_tx_sync_force <= std_logic_vector(to_signed(0,1)); - else - -- HW -- - -- SW -- - if pi_decoder_wr_stb = '1' then - field_reg_tx_sync_force <= pi_decoder_data(1 downto 1); - end if; - end if; - end if; - end process; - -- - po_reg.tx_sync_force.data <= field_reg_tx_sync_force; -- - end block tx_sync_force_storage; - ------------------------------------------------------------STORAGE - tx_sync_f1_storage: block - begin - prs_write : process(pi_clock) - begin - if rising_edge(pi_clock) then - if pi_reset = '1' then - field_reg_tx_sync_f1 <= std_logic_vector(to_signed(0,1)); - else - -- HW -- - -- SW -- - if pi_decoder_wr_stb = '1' then - field_reg_tx_sync_f1 <= pi_decoder_data(2 downto 2); - end if; - end if; - end if; - end process; - -- - po_reg.tx_sync_f1.data <= field_reg_tx_sync_f1; -- - end block tx_sync_f1_storage; - ------------------------------------------------------------STORAGE - tx_sync_f2_storage: block - begin - prs_write : process(pi_clock) - begin - if rising_edge(pi_clock) then - if pi_reset = '1' then - field_reg_tx_sync_f2 <= std_logic_vector(to_signed(0,1)); - else - -- HW -- - -- SW -- - if pi_decoder_wr_stb = '1' then - field_reg_tx_sync_f2 <= pi_decoder_data(3 downto 3); - end if; - end if; - end if; - end process; - -- - po_reg.tx_sync_f2.data <= field_reg_tx_sync_f2; -- - end block tx_sync_f2_storage; - ---------------------------------------------------------- -end rtl; ------------------------------------------------ --- register type: tx_sync_cnt ------------------------------------------------ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library desyrdl; -use desyrdl.common.all; - -use work.pkg_msk_top_regs.all; - -entity msk_top_regs_tx_sync_cnt is - port ( - pi_clock : in std_logic; - pi_reset : in std_logic; - -- to/from adapter - pi_decoder_rd_stb : in std_logic; - pi_decoder_wr_stb : in std_logic; - pi_decoder_data : in std_logic_vector(C_DATA_WIDTH-1 downto 0); - po_decoder_data : out std_logic_vector(C_DATA_WIDTH-1 downto 0); - - pi_reg : in t_reg_tx_sync_cnt_in ; - po_reg : out t_reg_tx_sync_cnt_out - ); -end entity msk_top_regs_tx_sync_cnt; - -architecture rtl of msk_top_regs_tx_sync_cnt is - - -- assign slices of data_out for each field, but force the rest to constant zeros - function fun_set_data_out ( -- - field_reg_tx_sync_cnt : std_logic_vector(24-1 downto 0)) -- - return std_logic_vector is - variable v_data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0); - begin - v_data_out := (others => '0'); - -- - v_data_out(23 downto 0) := field_reg_tx_sync_cnt; -- - return v_data_out; - end function fun_set_data_out; - - signal data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0'); - -- - signal field_reg_tx_sync_cnt : std_logic_vector(24-1 downto 0) - := std_logic_vector(to_signed(0,24)); -- -begin - - data_out <= fun_set_data_out( -- - field_reg_tx_sync_cnt -- - ); - - -- resize field data out to the register bus width - -- do only if 1 field and signed-- - po_decoder_data <= data_out; -- - ------------------------------------------------------------STORAGE - tx_sync_cnt_storage: block - begin - prs_write : process(pi_clock) - begin - if rising_edge(pi_clock) then - if pi_reset = '1' then - field_reg_tx_sync_cnt <= std_logic_vector(to_signed(0,24)); - else - -- HW -- - -- SW -- - if pi_decoder_wr_stb = '1' then - field_reg_tx_sync_cnt <= pi_decoder_data(23 downto 0); - end if; - end if; - end if; - end process; - -- - po_reg.tx_sync_cnt.data <= field_reg_tx_sync_cnt; -- - end block tx_sync_cnt_storage; - ---------------------------------------------------------- -end rtl; ------------------------------------------------ --- register type: lowpass_ema_alpha ------------------------------------------------ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library desyrdl; -use desyrdl.common.all; - -use work.pkg_msk_top_regs.all; - -entity msk_top_regs_lowpass_ema_alpha is - port ( - pi_clock : in std_logic; - pi_reset : in std_logic; - -- to/from adapter - pi_decoder_rd_stb : in std_logic; - pi_decoder_wr_stb : in std_logic; - pi_decoder_data : in std_logic_vector(C_DATA_WIDTH-1 downto 0); - po_decoder_data : out std_logic_vector(C_DATA_WIDTH-1 downto 0); - - pi_reg : in t_reg_lowpass_ema_alpha_in ; - po_reg : out t_reg_lowpass_ema_alpha_out - ); -end entity msk_top_regs_lowpass_ema_alpha; - -architecture rtl of msk_top_regs_lowpass_ema_alpha is - - -- assign slices of data_out for each field, but force the rest to constant zeros - function fun_set_data_out ( -- - field_reg_alpha : std_logic_vector(18-1 downto 0)) -- - return std_logic_vector is - variable v_data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0); - begin - v_data_out := (others => '0'); - -- - v_data_out(17 downto 0) := field_reg_alpha; -- - return v_data_out; - end function fun_set_data_out; - - signal data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0'); - -- - signal field_reg_alpha : std_logic_vector(18-1 downto 0) - := std_logic_vector(to_signed(0,18)); -- -begin - - data_out <= fun_set_data_out( -- - field_reg_alpha -- - ); - - -- resize field data out to the register bus width - -- do only if 1 field and signed-- - po_decoder_data <= data_out; -- - ------------------------------------------------------------STORAGE - alpha_storage: block - begin - prs_write : process(pi_clock) - begin - if rising_edge(pi_clock) then - if pi_reset = '1' then - field_reg_alpha <= std_logic_vector(to_signed(0,18)); - else - -- HW -- - -- SW -- - if pi_decoder_wr_stb = '1' then - field_reg_alpha <= pi_decoder_data(17 downto 0); - end if; - end if; - end if; - end process; - -- - po_reg.alpha.data <= field_reg_alpha; -- - end block alpha_storage; - ---------------------------------------------------------- -end rtl; ------------------------------------------------ --- register type: rx_power ------------------------------------------------ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library desyrdl; -use desyrdl.common.all; - -use work.pkg_msk_top_regs.all; - -entity msk_top_regs_rx_power is - port ( - pi_clock : in std_logic; - pi_reset : in std_logic; - -- to/from adapter - pi_decoder_rd_stb : in std_logic; - pi_decoder_wr_stb : in std_logic; - pi_decoder_data : in std_logic_vector(C_DATA_WIDTH-1 downto 0); - po_decoder_data : out std_logic_vector(C_DATA_WIDTH-1 downto 0); - - pi_reg : in t_reg_rx_power_in ; - po_reg : out t_reg_rx_power_out - ); -end entity msk_top_regs_rx_power; - -architecture rtl of msk_top_regs_rx_power is - - -- assign slices of data_out for each field, but force the rest to constant zeros - function fun_set_data_out ( -- - field_reg_rx_power : std_logic_vector(23-1 downto 0)) -- - return std_logic_vector is - variable v_data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0); - begin - v_data_out := (others => '0'); - -- - v_data_out(22 downto 0) := field_reg_rx_power; -- - return v_data_out; - end function fun_set_data_out; - - signal data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0'); - -- - signal field_reg_rx_power : std_logic_vector(23-1 downto 0) - := std_logic_vector(to_signed(0,23)); -- -begin - - data_out <= fun_set_data_out( -- - field_reg_rx_power -- - ); - - -- resize field data out to the register bus width - -- do only if 1 field and signed-- - po_decoder_data <= data_out; -- - ------------------------------------------------------------WIRE - rx_power_wire : block -- - begin - -- - field_reg_rx_power <= pi_reg.rx_power.data(23-1 downto 0); -- - --no signal to read by HW - po_reg.rx_power.dummy <= '0'; -- - end block; -- -end rtl; ------------------------------------------------ - --------------------------------------------------------------------------------- --- Register types in regfiles --------------------------------------------------------------------------------- --- \ No newline at end of file diff --git a/src/msk_top_csr.vhd b/src/msk_top_csr.vhd index ba71d22..ee86e51 100644 --- a/src/msk_top_csr.vhd +++ b/src/msk_top_csr.vhd @@ -62,8 +62,7 @@ USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; USE work.axi4lite_intf_pkg.ALL; ---USE work.msk_top_regs_pkg.ALL; -USE work.pkg_msk_top_regs.ALL; +USE work.msk_top_regs_pkg.ALL; ------------------------------------------------------------------------------------------------------ -- ╔═╗┌┐┌┌┬┐┬┌┬┐┬ ┬ From a56c29b6566ff1f01bfe377743d730c3b8a7b56a Mon Sep 17 00:00:00 2001 From: Abraxas3d Date: Mon, 27 Oct 2025 18:22:41 -0700 Subject: [PATCH 12/60] added reg_utils.vhd to /library/msk_top_ip.tcl build script --- library/msk_top_ip.tcl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/library/msk_top_ip.tcl b/library/msk_top_ip.tcl index 3b4c90f..fb9e4c3 100644 --- a/library/msk_top_ip.tcl +++ b/library/msk_top_ip.tcl @@ -8,11 +8,11 @@ adi_ip_create msk_top read_vhdl -library "desyrdl" "../rdl/vhdl/desyrdl/pkg_desyrdl_common.vhd" read_vhdl -vhdl2008 "../rdl/src/axi4lite_intf_pkg.vhd" -read_vhdl "../rdl/vhdl/msk_top_regs/pkg_msk_top_regs.vhd" +read_vhdl "../rdl/src/reg_utils.vhd" +read_vhdl "../rdl/outputs/rtl/msk_top_regs_pkg.vhd" #set_property FILE_TYPE {VHDL 2008} [get_files $ad_hdl_dir/library/msk_top/src/*.vhd] adi_ip_files msk_top [list \ - "../rdl/vhdl/msk_top_regs/msk_top_regs_decoder_axi4l.vhd" \ "../rdl/vhdl/msk_top_regs/msk_top_regs.vhd" \ "../msk_demodulator/src/costas_loop.vhd" \ "../pi_controller/src/pi_controller.vhd" \ From 0550e64185b44b913042acd569c1fe24a8992791 Mon Sep 17 00:00:00 2001 From: Abraxas3d Date: Mon, 27 Oct 2025 18:23:37 -0700 Subject: [PATCH 13/60] removed desyrdl package from /library/msk_top_ip.tcl build script --- library/msk_top_ip.tcl | 1 - 1 file changed, 1 deletion(-) diff --git a/library/msk_top_ip.tcl b/library/msk_top_ip.tcl index fb9e4c3..1e0804a 100644 --- a/library/msk_top_ip.tcl +++ b/library/msk_top_ip.tcl @@ -6,7 +6,6 @@ source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl adi_ip_create msk_top -read_vhdl -library "desyrdl" "../rdl/vhdl/desyrdl/pkg_desyrdl_common.vhd" read_vhdl -vhdl2008 "../rdl/src/axi4lite_intf_pkg.vhd" read_vhdl "../rdl/src/reg_utils.vhd" read_vhdl "../rdl/outputs/rtl/msk_top_regs_pkg.vhd" From 5266d125f202be36fe753917490f50b46ceeea5d Mon Sep 17 00:00:00 2001 From: Abraxas3d Date: Mon, 27 Oct 2025 18:30:08 -0700 Subject: [PATCH 14/60] changed path from rdl/vhdl/msk_top_regs/ to rdl/outputs/rtl --- library/msk_top_ip.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/library/msk_top_ip.tcl b/library/msk_top_ip.tcl index 1e0804a..cf83f3f 100644 --- a/library/msk_top_ip.tcl +++ b/library/msk_top_ip.tcl @@ -12,7 +12,7 @@ read_vhdl "../rdl/outputs/rtl/msk_top_regs_pkg.vhd" #set_property FILE_TYPE {VHDL 2008} [get_files $ad_hdl_dir/library/msk_top/src/*.vhd] adi_ip_files msk_top [list \ - "../rdl/vhdl/msk_top_regs/msk_top_regs.vhd" \ + "../rdl/outputs/msk_top_regs/msk_top_regs.vhd" \ "../msk_demodulator/src/costas_loop.vhd" \ "../pi_controller/src/pi_controller.vhd" \ "../lowpass_ema/src/lowpass_ema.vhd" \ From e3c30b9a36e583b6cf386faec4cc24e7de73a85e Mon Sep 17 00:00:00 2001 From: Abraxas3d Date: Mon, 27 Oct 2025 18:38:30 -0700 Subject: [PATCH 15/60] cast the wrong spell but fixed it to /rdl/outputs/rtl/msk_top_regs.vhd --- library/msk_top_ip.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/library/msk_top_ip.tcl b/library/msk_top_ip.tcl index cf83f3f..356db58 100644 --- a/library/msk_top_ip.tcl +++ b/library/msk_top_ip.tcl @@ -12,7 +12,7 @@ read_vhdl "../rdl/outputs/rtl/msk_top_regs_pkg.vhd" #set_property FILE_TYPE {VHDL 2008} [get_files $ad_hdl_dir/library/msk_top/src/*.vhd] adi_ip_files msk_top [list \ - "../rdl/outputs/msk_top_regs/msk_top_regs.vhd" \ + "../rdl/outputs/rtl/msk_top_regs.vhd" \ "../msk_demodulator/src/costas_loop.vhd" \ "../pi_controller/src/pi_controller.vhd" \ "../lowpass_ema/src/lowpass_ema.vhd" \ From cfe0a8010a03679138a23e0884658007236a00c9 Mon Sep 17 00:00:00 2001 From: Abraxas3d Date: Mon, 27 Oct 2025 18:45:26 -0700 Subject: [PATCH 16/60] vhdl2008 added to reg_utils.vhd to resolve errors --- library/msk_top_ip.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/library/msk_top_ip.tcl b/library/msk_top_ip.tcl index 356db58..d249204 100644 --- a/library/msk_top_ip.tcl +++ b/library/msk_top_ip.tcl @@ -7,7 +7,7 @@ source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl adi_ip_create msk_top read_vhdl -vhdl2008 "../rdl/src/axi4lite_intf_pkg.vhd" -read_vhdl "../rdl/src/reg_utils.vhd" +read_vhdl -vhdl2008 "../rdl/src/reg_utils.vhd" read_vhdl "../rdl/outputs/rtl/msk_top_regs_pkg.vhd" #set_property FILE_TYPE {VHDL 2008} [get_files $ad_hdl_dir/library/msk_top/src/*.vhd] From d821407a6950d658a36196e52729e0848c46ea41 Mon Sep 17 00:00:00 2001 From: Abraxas3d Date: Mon, 27 Oct 2025 18:54:16 -0700 Subject: [PATCH 17/60] vhdl2008 added to msk_top_regs.vhd. Should be the last one? --- library/msk_top_ip.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/library/msk_top_ip.tcl b/library/msk_top_ip.tcl index d249204..055ac37 100644 --- a/library/msk_top_ip.tcl +++ b/library/msk_top_ip.tcl @@ -9,10 +9,10 @@ adi_ip_create msk_top read_vhdl -vhdl2008 "../rdl/src/axi4lite_intf_pkg.vhd" read_vhdl -vhdl2008 "../rdl/src/reg_utils.vhd" read_vhdl "../rdl/outputs/rtl/msk_top_regs_pkg.vhd" +read_vhdl -vhdl2008 "../rdl/outputs/rtl/msk_top_regs.vhd" #set_property FILE_TYPE {VHDL 2008} [get_files $ad_hdl_dir/library/msk_top/src/*.vhd] adi_ip_files msk_top [list \ - "../rdl/outputs/rtl/msk_top_regs.vhd" \ "../msk_demodulator/src/costas_loop.vhd" \ "../pi_controller/src/pi_controller.vhd" \ "../lowpass_ema/src/lowpass_ema.vhd" \ From 86943dddab281fc975662a4ad98ff8863a2f8748 Mon Sep 17 00:00:00 2001 From: Abraxas3d Date: Mon, 27 Oct 2025 19:10:56 -0700 Subject: [PATCH 18/60] added cdc_resync.vhd pulse_detect.vhd and data_capture.vhd to add ip files list in librar/msk_top_ip.tcl --- library/msk_top_ip.tcl | 3 +++ 1 file changed, 3 insertions(+) diff --git a/library/msk_top_ip.tcl b/library/msk_top_ip.tcl index 055ac37..d2a85db 100644 --- a/library/msk_top_ip.tcl +++ b/library/msk_top_ip.tcl @@ -19,6 +19,9 @@ adi_ip_files msk_top [list \ "../power_detector/src/power_detector.vhd" \ "../msk_demodulator/src/msk_demodulator.vhd" \ "../msk_modulator/src/msk_modulator.vhd" \ + "../src/cdc_resync.vhd" \ + "../src/pulse_detect.vhd" \ + "../src/data_capture.vhd" \ "../src/msk_top.vhd" \ "../src/msk_top_csr.vhd" \ "../src/axis_dma_adapter.vhd" \ From dc22efddbbbc1d1a3c5b3c0c5c450ebb235a3514 Mon Sep 17 00:00:00 2001 From: Matthew Wishek Date: Wed, 29 Oct 2025 00:55:10 -0600 Subject: [PATCH 19/60] Update regmap in README.md --- README.md | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/README.md b/README.md index d941e89..4fd5ff4 100644 --- a/README.md +++ b/README.md @@ -15,7 +15,7 @@ The following ORI library components are used as submodules to this repository: 7. [Exponential Moving Average Filter](https://github.com/OpenResearchInstitute/lowpass_ema) ## Building -In oder to build the FPGA bitstream, you first need to install Vivado. Recommended version is 2022.2. In this documentation and in the `Makefile`, the Vivado installation path is assumed to be `/opt/Xilinx/Vivado`. If it is in another directory, change the path in the steps below (for example, to `/tools/Xilinx/Vivado`) or create a symbolic link in `/opt` pointing to the actual installation directory. For example, +In order to build the FPGA bitstream, you first need to install Vivado. Recommended version is 2022.2. In this documentation and in the `Makefile`, the Vivado installation path is assumed to be `/opt/Xilinx/Vivado`. If it is in another directory, change the path in the steps below (for example, to `/tools/Xilinx/Vivado`) or create a symbolic link in `/opt` pointing to the actual installation directory. For example, ``` sudo ln -s /tools/Xilinx /opt/Xilinx ``` @@ -130,6 +130,8 @@ sys 39m46.236s | 0x84 |lowpass_ema_alpha1| Exponential Moving Average Alpha | | 0x88 |lowpass_ema_alpha2| Exponential Moving Average Alpha | | 0x8C | rx_power | Receive Power | +| 0x90 |tx_async_fifo_rd_wr_ptr| Tx async FIFO read and write pointers | +| 0x94 |rx_async_fifo_rd_wr_ptr| Rx async FIFO read and write pointers | See [MSK Top Regs](rdl/msk_top_regs.pdf) for detailed register definitions. From e0dd8892a62e68b2a2bf4aff97987d6659e25def Mon Sep 17 00:00:00 2001 From: Matthew Wishek Date: Tue, 4 Nov 2025 11:47:28 -0700 Subject: [PATCH 20/60] rdl: move away from external registers to a write to capture model --- rdl/outputs/c-header/msk_top_regs.h | 63 +- rdl/outputs/docs/msk_top_regs.md | 92 +- rdl/outputs/docs/msk_top_regs.pdf | Bin 114122 -> 113978 bytes .../msk_top_regs/reg_model/msk_top_regs.py | 310 +-- .../python/msk_top_regs/sim/msk_top_regs.py | 44 +- .../msk_top_regs/tests/test_msk_top_regs.py | 1830 ++++++++++++++--- .../tests/test_sim_msk_top_regs.py | 1162 ++++++++++- rdl/outputs/rtl/msk_top_regs.vhd | 845 ++++++-- rdl/outputs/rtl/msk_top_regs_pkg.vhd | 313 ++- rdl/src/msk_top_regs.rdl | 207 +- sim/msk_test.py | 8 + src/msk_top_csr.vhd | 92 +- 12 files changed, 3902 insertions(+), 1064 deletions(-) diff --git a/rdl/outputs/c-header/msk_top_regs.h b/rdl/outputs/c-header/msk_top_regs.h index accc8fb..58f9611 100644 --- a/rdl/outputs/c-header/msk_top_regs.h +++ b/rdl/outputs/c-header/msk_top_regs.h @@ -78,15 +78,16 @@ extern "C" { #define MSK_TOP_REGS__MSK_STAT_0__TX_AXIS_VALID_reset 0x0 // Reg - msk_top_regs::msk_stat_1 -#define MSK_TOP_REGS__MSK_STAT_1__TX_BIT_COUNTER_bm 0xffffffff -#define MSK_TOP_REGS__MSK_STAT_1__TX_BIT_COUNTER_bp 0 -#define MSK_TOP_REGS__MSK_STAT_1__TX_BIT_COUNTER_bw 32 +#define MSK_TOP_REGS__MSK_STAT_1__DATA_bm 0xffffffff +#define MSK_TOP_REGS__MSK_STAT_1__DATA_bp 0 +#define MSK_TOP_REGS__MSK_STAT_1__DATA_bw 32 +#define MSK_TOP_REGS__MSK_STAT_1__DATA_reset 0x0 // Reg - msk_top_regs::msk_stat_2 -#define MSK_TOP_REGS__MSK_STAT_2__TX_ENA_COUNTER_bm 0xffffffff -#define MSK_TOP_REGS__MSK_STAT_2__TX_ENA_COUNTER_bp 0 -#define MSK_TOP_REGS__MSK_STAT_2__TX_ENA_COUNTER_bw 32 -#define MSK_TOP_REGS__MSK_STAT_2__TX_ENA_COUNTER_reset 0x0 +#define MSK_TOP_REGS__MSK_STAT_2__DATA_bm 0xffffffff +#define MSK_TOP_REGS__MSK_STAT_2__DATA_bp 0 +#define MSK_TOP_REGS__MSK_STAT_2__DATA_bw 32 +#define MSK_TOP_REGS__MSK_STAT_2__DATA_reset 0x0 // Reg - msk_top_regs::config_nco_fw_desc_c4924cc6_name_0c494469 #define MSK_TOP_REGS__CONFIG_NCO_FW_DESC_C4924CC6_NAME_0C494469__CONFIG_DATA_bm 0xffffffff @@ -203,34 +204,34 @@ extern "C" { #define MSK_TOP_REGS__CONFIG_PRBS_ERRMASK__CONFIG_DATA_reset 0x0 // Reg - msk_top_regs::stat_32_bits -#define MSK_TOP_REGS__STAT_32_BITS__STATUS_DATA_bm 0xffffffff -#define MSK_TOP_REGS__STAT_32_BITS__STATUS_DATA_bp 0 -#define MSK_TOP_REGS__STAT_32_BITS__STATUS_DATA_bw 32 -#define MSK_TOP_REGS__STAT_32_BITS__STATUS_DATA_reset 0x0 +#define MSK_TOP_REGS__STAT_32_BITS__DATA_bm 0xffffffff +#define MSK_TOP_REGS__STAT_32_BITS__DATA_bp 0 +#define MSK_TOP_REGS__STAT_32_BITS__DATA_bw 32 +#define MSK_TOP_REGS__STAT_32_BITS__DATA_reset 0x0 // Reg - msk_top_regs::stat_32_errs -#define MSK_TOP_REGS__STAT_32_ERRS__STATUS_DATA_bm 0xffffffff -#define MSK_TOP_REGS__STAT_32_ERRS__STATUS_DATA_bp 0 -#define MSK_TOP_REGS__STAT_32_ERRS__STATUS_DATA_bw 32 -#define MSK_TOP_REGS__STAT_32_ERRS__STATUS_DATA_reset 0x0 +#define MSK_TOP_REGS__STAT_32_ERRS__DATA_bm 0xffffffff +#define MSK_TOP_REGS__STAT_32_ERRS__DATA_bp 0 +#define MSK_TOP_REGS__STAT_32_ERRS__DATA_bw 32 +#define MSK_TOP_REGS__STAT_32_ERRS__DATA_reset 0x0 // Reg - msk_top_regs::stat_32_lpf_acc_desc_8cebc7dc_name_f20c6670 -#define MSK_TOP_REGS__STAT_32_LPF_ACC_DESC_8CEBC7DC_NAME_F20C6670__STATUS_DATA_bm 0xffffffff -#define MSK_TOP_REGS__STAT_32_LPF_ACC_DESC_8CEBC7DC_NAME_F20C6670__STATUS_DATA_bp 0 -#define MSK_TOP_REGS__STAT_32_LPF_ACC_DESC_8CEBC7DC_NAME_F20C6670__STATUS_DATA_bw 32 -#define MSK_TOP_REGS__STAT_32_LPF_ACC_DESC_8CEBC7DC_NAME_F20C6670__STATUS_DATA_reset 0x0 +#define MSK_TOP_REGS__STAT_32_LPF_ACC_DESC_8CEBC7DC_NAME_F20C6670__DATA_bm 0xffffffff +#define MSK_TOP_REGS__STAT_32_LPF_ACC_DESC_8CEBC7DC_NAME_F20C6670__DATA_bp 0 +#define MSK_TOP_REGS__STAT_32_LPF_ACC_DESC_8CEBC7DC_NAME_F20C6670__DATA_bw 32 +#define MSK_TOP_REGS__STAT_32_LPF_ACC_DESC_8CEBC7DC_NAME_F20C6670__DATA_reset 0x0 // Reg - msk_top_regs::stat_32_lpf_acc_desc_dea6bd99_name_758fd0ce -#define MSK_TOP_REGS__STAT_32_LPF_ACC_DESC_DEA6BD99_NAME_758FD0CE__STATUS_DATA_bm 0xffffffff -#define MSK_TOP_REGS__STAT_32_LPF_ACC_DESC_DEA6BD99_NAME_758FD0CE__STATUS_DATA_bp 0 -#define MSK_TOP_REGS__STAT_32_LPF_ACC_DESC_DEA6BD99_NAME_758FD0CE__STATUS_DATA_bw 32 -#define MSK_TOP_REGS__STAT_32_LPF_ACC_DESC_DEA6BD99_NAME_758FD0CE__STATUS_DATA_reset 0x0 +#define MSK_TOP_REGS__STAT_32_LPF_ACC_DESC_DEA6BD99_NAME_758FD0CE__DATA_bm 0xffffffff +#define MSK_TOP_REGS__STAT_32_LPF_ACC_DESC_DEA6BD99_NAME_758FD0CE__DATA_bp 0 +#define MSK_TOP_REGS__STAT_32_LPF_ACC_DESC_DEA6BD99_NAME_758FD0CE__DATA_bw 32 +#define MSK_TOP_REGS__STAT_32_LPF_ACC_DESC_DEA6BD99_NAME_758FD0CE__DATA_reset 0x0 // Reg - msk_top_regs::msk_stat_3 -#define MSK_TOP_REGS__MSK_STAT_3__XFER_COUNT_bm 0xffffffff -#define MSK_TOP_REGS__MSK_STAT_3__XFER_COUNT_bp 0 -#define MSK_TOP_REGS__MSK_STAT_3__XFER_COUNT_bw 32 -#define MSK_TOP_REGS__MSK_STAT_3__XFER_COUNT_reset 0x0 +#define MSK_TOP_REGS__MSK_STAT_3__DATA_bm 0xffffffff +#define MSK_TOP_REGS__MSK_STAT_3__DATA_bp 0 +#define MSK_TOP_REGS__MSK_STAT_3__DATA_bw 32 +#define MSK_TOP_REGS__MSK_STAT_3__DATA_reset 0x0 // Reg - msk_top_regs::rx_sample_discard #define MSK_TOP_REGS__RX_SAMPLE_DISCARD__RX_SAMPLE_DISCARD_bm 0xff @@ -307,10 +308,10 @@ extern "C" { #define MSK_TOP_REGS__LOWPASS_EMA_ALPHA__ALPHA_reset 0x0 // Reg - msk_top_regs::rx_power -#define MSK_TOP_REGS__RX_POWER__RX_POWER_bm 0x7fffff -#define MSK_TOP_REGS__RX_POWER__RX_POWER_bp 0 -#define MSK_TOP_REGS__RX_POWER__RX_POWER_bw 23 -#define MSK_TOP_REGS__RX_POWER__RX_POWER_reset 0x0 +#define MSK_TOP_REGS__RX_POWER__DATA_bm 0x7fffff +#define MSK_TOP_REGS__RX_POWER__DATA_bp 0 +#define MSK_TOP_REGS__RX_POWER__DATA_bw 23 +#define MSK_TOP_REGS__RX_POWER__DATA_reset 0x0 // Reg - msk_top_regs::observation_data_data_cf6acbd7_name_aa4ec676 #define MSK_TOP_REGS__OBSERVATION_DATA_DATA_CF6ACBD7_NAME_AA4EC676__DATA_bm 0xffffffff diff --git a/rdl/outputs/docs/msk_top_regs.md b/rdl/outputs/docs/msk_top_regs.md index e724aaf..b1db448 100644 --- a/rdl/outputs/docs/msk_top_regs.md +++ b/rdl/outputs/docs/msk_top_regs.md @@ -194,11 +194,11 @@ Don't override. Generated from: msk_top_regs

Modem status data

-|Bits| Identifier | Access |Reset| Name | -|----|--------------|--------|-----|------------| -|31:0|tx_bit_counter|r, ruser| — |Tx Bit Count| +|Bits|Identifier|Access|Reset| Name | +|----|----------|------|-----|------------| +|31:0| data | rw | 0x0 |Tx Bit Count| -#### tx_bit_counter field +#### data field

Count of data requests made by modem

@@ -210,11 +210,11 @@ Don't override. Generated from: msk_top_regs

Modem status data

-|Bits| Identifier | Access |Reset| Name | -|----|--------------|--------|-----|---------------| -|31:0|tx_ena_counter|r, ruser| 0x0 |Tx Enable Count| +|Bits|Identifier|Access|Reset| Name | +|----|----------|------|-----|---------------| +|31:0| data | rw | 0x0 |Tx Enable Count| -#### tx_ena_counter field +#### data field

Number of clocks on which Tx Enable is active

@@ -483,11 +483,11 @@ N > 0 : Auto sync after N errors

PRBS Bits Received

-|Bits| Identifier|Access|Reset| Name | -|----|-----------|------|-----|------------------| -|31:0|status_data| r | 0x0 |PRBS Bits Received| +|Bits|Identifier|Access|Reset| Name | +|----|----------|------|-----|------------------| +|31:0| data | rw | 0x0 |PRBS Bits Received| -#### status_data field +#### data field

Number of bits received by the PRBS monitor since last BER can be calculated as the ratio of received bits to errored-bits

@@ -500,11 +500,11 @@ BER can be calculated as the ratio of received bits to errored-bits

PRBS Bit Errors

-|Bits| Identifier|Access|Reset| Name | -|----|-----------|------|-----|---------------| -|31:0|status_data| r | 0x0 |PRBS Bit Errors| +|Bits|Identifier|Access|Reset| Name | +|----|----------|------|-----|---------------| +|31:0| data | rw | 0x0 |PRBS Bit Errors| -#### status_data field +#### data field

Number of errored-bits received by the PRBS monitor since last sync BER can be calculated as the ratio of received bits to errored-bits

@@ -517,11 +517,11 @@ BER can be calculated as the ratio of received bits to errored-bits

Value of the F1 PI Controller Accumulator

-|Bits| Identifier|Access|Reset| Name | -|----|-----------|------|-----|-------------------------------| -|31:0|status_data| r | 0x0 |PI Controller Accumulator Value| +|Bits|Identifier|Access|Reset| Name | +|----|----------|------|-----|-------------------------------| +|31:0| data | rw | 0x0 |PI Controller Accumulator Value| -#### status_data field +#### data field

PI Controller Accumulator Value

@@ -533,11 +533,11 @@ BER can be calculated as the ratio of received bits to errored-bits

Value of the F2 PI Controller Accumulator

-|Bits| Identifier|Access|Reset| Name | -|----|-----------|------|-----|-------------------------------| -|31:0|status_data| r | 0x0 |PI Controller Accumulator Value| +|Bits|Identifier|Access|Reset| Name | +|----|----------|------|-----|-------------------------------| +|31:0| data | rw | 0x0 |PI Controller Accumulator Value| -#### status_data field +#### data field

PI Controller Accumulator Value

@@ -551,9 +551,9 @@ BER can be calculated as the ratio of received bits to errored-bits

|Bits|Identifier|Access|Reset| Name | |----|----------|------|-----|----------------| -|31:0|xfer_count| r | 0x0 |S_AXIS Transfers| +|31:0| data | rw | 0x0 |S_AXIS Transfers| -#### xfer_count field +#### data field

Number completed S_AXIS transfers

@@ -607,9 +607,9 @@ BER can be calculated as the ratio of received bits to errored-bits

Frequency offet applied to the F1 NCO

-|Bits|Identifier| Access |Reset| Name | -|----|----------|--------|-----|-----------------------| -|31:0| data |r, ruser| 0x0 |F1 NCO Frequency Adjust| +|Bits|Identifier|Access|Reset| Name | +|----|----------|------|-----|-----------------------| +|31:0| data | rw | 0x0 |F1 NCO Frequency Adjust| #### data field @@ -623,9 +623,9 @@ BER can be calculated as the ratio of received bits to errored-bits

Frequency offet applied to the F2 NCO

-|Bits|Identifier| Access |Reset| Name | -|----|----------|--------|-----|-----------------------| -|31:0| data |r, ruser| 0x0 |F2 NCO Frequency Adjust| +|Bits|Identifier|Access|Reset| Name | +|----|----------|------|-----|-----------------------| +|31:0| data | rw | 0x0 |F2 NCO Frequency Adjust| #### data field @@ -639,9 +639,9 @@ BER can be calculated as the ratio of received bits to errored-bits

Error value of the F1 Costas loop after each active bit period

-|Bits|Identifier| Access |Reset| Name | -|----|----------|--------|-----|--------------| -|31:0| data |r, ruser| 0x0 |F1 Error Value| +|Bits|Identifier|Access|Reset| Name | +|----|----------|------|-----|--------------| +|31:0| data | rw | 0x0 |F1 Error Value| #### data field @@ -655,9 +655,9 @@ BER can be calculated as the ratio of received bits to errored-bits

Error value of the F2 Costas loop after each active bit period

-|Bits|Identifier| Access |Reset| Name | -|----|----------|--------|-----|--------------| -|31:0| data |r, ruser| 0x0 |F2 Error Value| +|Bits|Identifier|Access|Reset| Name | +|----|----------|------|-----|--------------| +|31:0| data | rw | 0x0 |F2 Error Value| #### data field @@ -762,9 +762,9 @@ signal should be sent after PTT is asserted.

|Bits|Identifier|Access|Reset| Name | |----|----------|------|-----|-------------| -|22:0| rx_power | r | 0x0 |Receive Power| +|22:0| data | rw | 0x0 |Receive Power| -#### rx_power field +#### data field

Value that represent the RMS power of the incoming I;

@@ -774,9 +774,9 @@ signal should be sent after PTT is asserted.

- Base Offset: 0x90 - Size: 0x4 -|Bits|Identifier| Access |Reset|Name| -|----|----------|--------|-----|----| -|31:0| data |r, ruser| 0x0 | — | +|Bits|Identifier|Access|Reset|Name| +|----|----------|------|-----|----| +|31:0| data | rw | 0x0 | — | #### data field @@ -789,9 +789,9 @@ Bits 15:00 -> read pointer (12-bits)

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z1M5dNC26}@Tlza~Ein@3b0Kca-=+;?*W!iYW_c-o@C{op5_BluQPu#8-e#HcC^y8s;$Xyqj(f00+AZ9<@JsuGXIX%dWc|H7NGY)}CL0 zQKZcWsjEmjFwz60tEd$i<$D+>H69YWPr}g;{%7C3J-*9e02~>L{;}gA5C{zO+h9

c?V1$i^|xeuwt+KhSV+K>XCESmX7+bLaEsyXrOX zD@lH=Qi8Vpv`c3Y^s)NeVlO63vu^rWU&j@IYk{l#C$?#AX%aK)k zr`=BO#&u_u$elnBqVC1sNPLh(E8z1Z6~%h;NhgnOQvZLqy-)_h41?T=4Z^_BVi`Dq zY3*Xyh4r@ z8?Yz`G`E1A$7M8zR!lXyok=y*>ILv7j%|#{s9sUG(umJhbeA|GX+82ffYOYX-54h& zW>Q?~sL8vK_G=PVjc~v|&uIm7fj_f~54jGrN~G^w;XW|~)lj$+7R`H)@tWnp6Efcf)BOhFvx{{bM~MGgP} diff --git a/rdl/outputs/python/msk_top_regs/reg_model/msk_top_regs.py b/rdl/outputs/python/msk_top_regs/reg_model/msk_top_regs.py index e9597a8..0ec486a 100644 --- a/rdl/outputs/python/msk_top_regs/reg_model/msk_top_regs.py +++ b/rdl/outputs/python/msk_top_regs/reg_model/msk_top_regs.py @@ -76,7 +76,7 @@ -class msk_top_regs_data32_desc_7b98a70e_cls(FieldAsyncReadOnly): +class msk_top_regs_data32_desc_7b98a70e_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -108,7 +108,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_observation_data_data_cf6acbd7_name_8a90eed1_cls(RegAsyncReadOnly): +class msk_top_regs_observation_data_data_cf6acbd7_name_8a90eed1_cls(RegAsyncReadWrite): """ Class to represent a register in the register model @@ -130,7 +130,7 @@ def __init__(self, accesswidth: int, logger_handle: str, inst_name: str, - parent: Union[AsyncAddressMap,AsyncRegFile,ReadableAsyncMemory]): + parent: Union[AsyncAddressMap,AsyncRegFile,MemoryAsyncReadWrite]): super().__init__(address=address, width=width, @@ -229,7 +229,7 @@ def rdl_name(self) -> str: -class msk_top_regs_data32_desc_7b98a70e_0x0x1075e913_cls(FieldAsyncReadOnly): +class msk_top_regs_data32_desc_7b98a70e_0x0x105c7600_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -261,7 +261,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_observation_data_data_cf6acbd7_name_aa4ec676_cls(RegAsyncReadOnly): +class msk_top_regs_observation_data_data_cf6acbd7_name_aa4ec676_cls(RegAsyncReadWrite): """ Class to represent a register in the register model @@ -283,7 +283,7 @@ def __init__(self, accesswidth: int, logger_handle: str, inst_name: str, - parent: Union[AsyncAddressMap,AsyncRegFile,ReadableAsyncMemory]): + parent: Union[AsyncAddressMap,AsyncRegFile,MemoryAsyncReadWrite]): super().__init__(address=address, width=width, @@ -294,7 +294,7 @@ def __init__(self, # build the field attributes - self.__data:msk_top_regs_data32_desc_7b98a70e_0x0x1075e913_cls = msk_top_regs_data32_desc_7b98a70e_0x0x1075e913_cls( + self.__data:msk_top_regs_data32_desc_7b98a70e_0x0x105c7600_cls = msk_top_regs_data32_desc_7b98a70e_0x0x105c7600_cls( parent_register=self, size_props=FieldSizeProps( width=32, @@ -325,7 +325,7 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field # build the properties for the fields @property - def data(self) -> msk_top_regs_data32_desc_7b98a70e_0x0x1075e913_cls: + def data(self) -> msk_top_regs_data32_desc_7b98a70e_0x0x105c7600_cls: """ Property to access data field of the register @@ -361,7 +361,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_data32_desc_7b98a70e_0x0x1075e913_cls: + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_data32_desc_7b98a70e_0x0x105c7600_cls: return super().get_child_by_system_rdl_name(name) @@ -382,7 +382,7 @@ def rdl_name(self) -> str: -class msk_top_regs_rx_power_rx_power_cls(FieldAsyncReadOnly): +class msk_top_regs_rx_power_data_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -420,7 +420,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_rx_power_cls(RegAsyncReadOnly): +class msk_top_regs_rx_power_cls(RegAsyncReadWrite): """ Class to represent a register in the register model @@ -438,7 +438,7 @@ class msk_top_regs_rx_power_cls(RegAsyncReadOnly): +--------------+-------------------------------------------------------------------------+ """ - __slots__ : list[str] = ['__rx_power'] + __slots__ : list[str] = ['__data'] def __init__(self, address: int, @@ -446,7 +446,7 @@ def __init__(self, accesswidth: int, logger_handle: str, inst_name: str, - parent: Union[AsyncAddressMap,AsyncRegFile,ReadableAsyncMemory]): + parent: Union[AsyncAddressMap,AsyncRegFile,MemoryAsyncReadWrite]): super().__init__(address=address, width=width, @@ -457,7 +457,7 @@ def __init__(self, # build the field attributes - self.__rx_power:msk_top_regs_rx_power_rx_power_cls = msk_top_regs_rx_power_rx_power_cls( + self.__data:msk_top_regs_rx_power_data_cls = msk_top_regs_rx_power_data_cls( parent_register=self, size_props=FieldSizeProps( width=23, @@ -468,8 +468,8 @@ def __init__(self, misc_props=FieldMiscProps( default=0, is_volatile=True), - logger_handle=logger_handle+'.rx_power', - inst_name='rx_power', + logger_handle=logger_handle+'.data', + inst_name='data', field_type=int) @property @@ -477,7 +477,7 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field """ generator that produces has all the fields within the register """ - yield self.rx_power + yield self.data # Empty generator in case there are no children of this type if False: yield @@ -488,9 +488,9 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field # build the properties for the fields @property - def rx_power(self) -> msk_top_regs_rx_power_rx_power_cls: + def data(self) -> msk_top_regs_rx_power_data_cls: """ - Property to access rx_power field of the register + Property to access data field of the register +--------------+-------------------------------------------------------------------------+ | SystemRDL | Value | @@ -505,7 +505,7 @@ def rx_power(self) -> msk_top_regs_rx_power_rx_power_cls: | |

Value that represent the RMS power of the incoming I;

| +--------------+-------------------------------------------------------------------------+ """ - return self.__rx_power + return self.__data @property @@ -517,7 +517,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: Returns: dictionary whose key is the systemRDL names and value it the property name """ - return {'rx_power':'rx_power', + return {'data':'data', } @@ -527,7 +527,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_rx_power_rx_power_cls: + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_rx_power_data_cls: return super().get_child_by_system_rdl_name(name) @@ -720,7 +720,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_lowpass_ema_alpha_alpha_0x0x1075e9a9_cls(FieldAsyncReadWrite): +class msk_top_regs_lowpass_ema_alpha_alpha_0x0x105c7501_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -758,7 +758,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_lowpass_ema_alpha_0x0x1075e9f4_cls(RegAsyncReadWrite): +class msk_top_regs_lowpass_ema_alpha_0x0x105c0c74_cls(RegAsyncReadWrite): """ Class to represent a register in the register model @@ -795,7 +795,7 @@ def __init__(self, # build the field attributes - self.__alpha:msk_top_regs_lowpass_ema_alpha_alpha_0x0x1075e9a9_cls = msk_top_regs_lowpass_ema_alpha_alpha_0x0x1075e9a9_cls( + self.__alpha:msk_top_regs_lowpass_ema_alpha_alpha_0x0x105c7501_cls = msk_top_regs_lowpass_ema_alpha_alpha_0x0x105c7501_cls( parent_register=self, size_props=FieldSizeProps( width=18, @@ -826,7 +826,7 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field # build the properties for the fields @property - def alpha(self) -> msk_top_regs_lowpass_ema_alpha_alpha_0x0x1075e9a9_cls: + def alpha(self) -> msk_top_regs_lowpass_ema_alpha_alpha_0x0x105c7501_cls: """ Property to access alpha field of the register @@ -865,7 +865,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_lowpass_ema_alpha_alpha_0x0x1075e9a9_cls: + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_lowpass_ema_alpha_alpha_0x0x105c7501_cls: return super().get_child_by_system_rdl_name(name) @@ -1484,7 +1484,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_data32_desc_70869502_name_3de9a0d3_cls(FieldAsyncReadOnly): +class msk_top_regs_data32_desc_70869502_name_3de9a0d3_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -1523,7 +1523,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_observation_data_data_272a00b6_desc_70869502_name_3de9a0d3_cls(RegAsyncReadOnly): +class msk_top_regs_observation_data_data_272a00b6_desc_70869502_name_3de9a0d3_cls(RegAsyncReadWrite): """ Class to represent a register in the register model @@ -1550,7 +1550,7 @@ def __init__(self, accesswidth: int, logger_handle: str, inst_name: str, - parent: Union[AsyncAddressMap,AsyncRegFile,ReadableAsyncMemory]): + parent: Union[AsyncAddressMap,AsyncRegFile,MemoryAsyncReadWrite]): super().__init__(address=address, width=width, @@ -1656,7 +1656,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_data32_desc_417e1c96_name_3b640507_cls(FieldAsyncReadOnly): +class msk_top_regs_data32_desc_417e1c96_name_3b640507_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -1695,7 +1695,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_observation_data_data_25a21249_desc_417e1c96_name_3b640507_cls(RegAsyncReadOnly): +class msk_top_regs_observation_data_data_25a21249_desc_417e1c96_name_3b640507_cls(RegAsyncReadWrite): """ Class to represent a register in the register model @@ -1722,7 +1722,7 @@ def __init__(self, accesswidth: int, logger_handle: str, inst_name: str, - parent: Union[AsyncAddressMap,AsyncRegFile,ReadableAsyncMemory]): + parent: Union[AsyncAddressMap,AsyncRegFile,MemoryAsyncReadWrite]): super().__init__(address=address, width=width, @@ -1828,7 +1828,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_data32_desc_ebde6d39_name_2c154788_cls(FieldAsyncReadOnly): +class msk_top_regs_data32_desc_ebde6d39_name_2c154788_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -1866,7 +1866,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_observation_data_data_0515efaa_desc_ebde6d39_name_2c154788_cls(RegAsyncReadOnly): +class msk_top_regs_observation_data_data_0515efaa_desc_ebde6d39_name_2c154788_cls(RegAsyncReadWrite): """ Class to represent a register in the register model @@ -1892,7 +1892,7 @@ def __init__(self, accesswidth: int, logger_handle: str, inst_name: str, - parent: Union[AsyncAddressMap,AsyncRegFile,ReadableAsyncMemory]): + parent: Union[AsyncAddressMap,AsyncRegFile,MemoryAsyncReadWrite]): super().__init__(address=address, width=width, @@ -1997,7 +1997,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_data32_desc_64ff3689_name_d8ad3b25_cls(FieldAsyncReadOnly): +class msk_top_regs_data32_desc_64ff3689_name_d8ad3b25_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -2035,7 +2035,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_observation_data_data_0c017ef4_desc_64ff3689_name_d8ad3b25_cls(RegAsyncReadOnly): +class msk_top_regs_observation_data_data_0c017ef4_desc_64ff3689_name_d8ad3b25_cls(RegAsyncReadWrite): """ Class to represent a register in the register model @@ -2061,7 +2061,7 @@ def __init__(self, accesswidth: int, logger_handle: str, inst_name: str, - parent: Union[AsyncAddressMap,AsyncRegFile,ReadableAsyncMemory]): + parent: Union[AsyncAddressMap,AsyncRegFile,MemoryAsyncReadWrite]): super().__init__(address=address, width=width, @@ -2672,7 +2672,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_msk_stat_3_xfer_count_cls(FieldAsyncReadOnly): +class msk_top_regs_msk_stat_3_data_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -2710,7 +2710,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_msk_stat_3_cls(RegAsyncReadOnly): +class msk_top_regs_msk_stat_3_cls(RegAsyncReadWrite): """ Class to represent a register in the register model @@ -2728,7 +2728,7 @@ class msk_top_regs_msk_stat_3_cls(RegAsyncReadOnly): +--------------+-------------------------------------------------------------------------+ """ - __slots__ : list[str] = ['__xfer_count'] + __slots__ : list[str] = ['__data'] def __init__(self, address: int, @@ -2736,7 +2736,7 @@ def __init__(self, accesswidth: int, logger_handle: str, inst_name: str, - parent: Union[AsyncAddressMap,AsyncRegFile,ReadableAsyncMemory]): + parent: Union[AsyncAddressMap,AsyncRegFile,MemoryAsyncReadWrite]): super().__init__(address=address, width=width, @@ -2747,7 +2747,7 @@ def __init__(self, # build the field attributes - self.__xfer_count:msk_top_regs_msk_stat_3_xfer_count_cls = msk_top_regs_msk_stat_3_xfer_count_cls( + self.__data:msk_top_regs_msk_stat_3_data_cls = msk_top_regs_msk_stat_3_data_cls( parent_register=self, size_props=FieldSizeProps( width=32, @@ -2758,8 +2758,8 @@ def __init__(self, misc_props=FieldMiscProps( default=0, is_volatile=True), - logger_handle=logger_handle+'.xfer_count', - inst_name='xfer_count', + logger_handle=logger_handle+'.data', + inst_name='data', field_type=int) @property @@ -2767,7 +2767,7 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field """ generator that produces has all the fields within the register """ - yield self.xfer_count + yield self.data # Empty generator in case there are no children of this type if False: yield @@ -2778,9 +2778,9 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field # build the properties for the fields @property - def xfer_count(self) -> msk_top_regs_msk_stat_3_xfer_count_cls: + def data(self) -> msk_top_regs_msk_stat_3_data_cls: """ - Property to access xfer_count field of the register + Property to access data field of the register +--------------+-------------------------------------------------------------------------+ | SystemRDL | Value | @@ -2795,7 +2795,7 @@ def xfer_count(self) -> msk_top_regs_msk_stat_3_xfer_count_cls: | |

Number completed S_AXIS transfers

| +--------------+-------------------------------------------------------------------------+ """ - return self.__xfer_count + return self.__data @property @@ -2807,7 +2807,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: Returns: dictionary whose key is the systemRDL names and value it the property name """ - return {'xfer_count':'xfer_count', + return {'data':'data', } @@ -2817,7 +2817,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_msk_stat_3_xfer_count_cls: + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_msk_stat_3_data_cls: return super().get_child_by_system_rdl_name(name) @@ -2841,7 +2841,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_stat_32_lpf_acc_status_data_cls(FieldAsyncReadOnly): +class msk_top_regs_stat_32_lpf_acc_data_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -2879,7 +2879,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_stat_32_lpf_acc_desc_dea6bd99_name_758fd0ce_cls(RegAsyncReadOnly): +class msk_top_regs_stat_32_lpf_acc_desc_dea6bd99_name_758fd0ce_cls(RegAsyncReadWrite): """ Class to represent a register in the register model @@ -2897,7 +2897,7 @@ class msk_top_regs_stat_32_lpf_acc_desc_dea6bd99_name_758fd0ce_cls(RegAsyncReadO +--------------+-------------------------------------------------------------------------+ """ - __slots__ : list[str] = ['__status_data'] + __slots__ : list[str] = ['__data'] def __init__(self, address: int, @@ -2905,7 +2905,7 @@ def __init__(self, accesswidth: int, logger_handle: str, inst_name: str, - parent: Union[AsyncAddressMap,AsyncRegFile,ReadableAsyncMemory]): + parent: Union[AsyncAddressMap,AsyncRegFile,MemoryAsyncReadWrite]): super().__init__(address=address, width=width, @@ -2916,7 +2916,7 @@ def __init__(self, # build the field attributes - self.__status_data:msk_top_regs_stat_32_lpf_acc_status_data_cls = msk_top_regs_stat_32_lpf_acc_status_data_cls( + self.__data:msk_top_regs_stat_32_lpf_acc_data_cls = msk_top_regs_stat_32_lpf_acc_data_cls( parent_register=self, size_props=FieldSizeProps( width=32, @@ -2927,8 +2927,8 @@ def __init__(self, misc_props=FieldMiscProps( default=0, is_volatile=True), - logger_handle=logger_handle+'.status_data', - inst_name='status_data', + logger_handle=logger_handle+'.data', + inst_name='data', field_type=int) @property @@ -2936,7 +2936,7 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field """ generator that produces has all the fields within the register """ - yield self.status_data + yield self.data # Empty generator in case there are no children of this type if False: yield @@ -2947,9 +2947,9 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field # build the properties for the fields @property - def status_data(self) -> msk_top_regs_stat_32_lpf_acc_status_data_cls: + def data(self) -> msk_top_regs_stat_32_lpf_acc_data_cls: """ - Property to access status_data field of the register + Property to access data field of the register +--------------+-------------------------------------------------------------------------+ | SystemRDL | Value | @@ -2964,7 +2964,7 @@ def status_data(self) -> msk_top_regs_stat_32_lpf_acc_status_data_cls: | |

PI Controller Accumulator Value

| +--------------+-------------------------------------------------------------------------+ """ - return self.__status_data + return self.__data @property @@ -2976,7 +2976,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: Returns: dictionary whose key is the systemRDL names and value it the property name """ - return {'status_data':'status_data', + return {'data':'data', } @@ -2986,7 +2986,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_stat_32_lpf_acc_status_data_cls: + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_stat_32_lpf_acc_data_cls: return super().get_child_by_system_rdl_name(name) @@ -3010,7 +3010,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_stat_32_lpf_acc_status_data_0x0x1073cd31_cls(FieldAsyncReadOnly): +class msk_top_regs_stat_32_lpf_acc_data_0x0x105c2672_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -3048,7 +3048,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_stat_32_lpf_acc_desc_8cebc7dc_name_f20c6670_cls(RegAsyncReadOnly): +class msk_top_regs_stat_32_lpf_acc_desc_8cebc7dc_name_f20c6670_cls(RegAsyncReadWrite): """ Class to represent a register in the register model @@ -3066,7 +3066,7 @@ class msk_top_regs_stat_32_lpf_acc_desc_8cebc7dc_name_f20c6670_cls(RegAsyncReadO +--------------+-------------------------------------------------------------------------+ """ - __slots__ : list[str] = ['__status_data'] + __slots__ : list[str] = ['__data'] def __init__(self, address: int, @@ -3074,7 +3074,7 @@ def __init__(self, accesswidth: int, logger_handle: str, inst_name: str, - parent: Union[AsyncAddressMap,AsyncRegFile,ReadableAsyncMemory]): + parent: Union[AsyncAddressMap,AsyncRegFile,MemoryAsyncReadWrite]): super().__init__(address=address, width=width, @@ -3085,7 +3085,7 @@ def __init__(self, # build the field attributes - self.__status_data:msk_top_regs_stat_32_lpf_acc_status_data_0x0x1073cd31_cls = msk_top_regs_stat_32_lpf_acc_status_data_0x0x1073cd31_cls( + self.__data:msk_top_regs_stat_32_lpf_acc_data_0x0x105c2672_cls = msk_top_regs_stat_32_lpf_acc_data_0x0x105c2672_cls( parent_register=self, size_props=FieldSizeProps( width=32, @@ -3096,8 +3096,8 @@ def __init__(self, misc_props=FieldMiscProps( default=0, is_volatile=True), - logger_handle=logger_handle+'.status_data', - inst_name='status_data', + logger_handle=logger_handle+'.data', + inst_name='data', field_type=int) @property @@ -3105,7 +3105,7 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field """ generator that produces has all the fields within the register """ - yield self.status_data + yield self.data # Empty generator in case there are no children of this type if False: yield @@ -3116,9 +3116,9 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field # build the properties for the fields @property - def status_data(self) -> msk_top_regs_stat_32_lpf_acc_status_data_0x0x1073cd31_cls: + def data(self) -> msk_top_regs_stat_32_lpf_acc_data_0x0x105c2672_cls: """ - Property to access status_data field of the register + Property to access data field of the register +--------------+-------------------------------------------------------------------------+ | SystemRDL | Value | @@ -3133,7 +3133,7 @@ def status_data(self) -> msk_top_regs_stat_32_lpf_acc_status_data_0x0x1073cd31_c | |

PI Controller Accumulator Value

| +--------------+-------------------------------------------------------------------------+ """ - return self.__status_data + return self.__data @property @@ -3145,7 +3145,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: Returns: dictionary whose key is the systemRDL names and value it the property name """ - return {'status_data':'status_data', + return {'data':'data', } @@ -3155,7 +3155,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_stat_32_lpf_acc_status_data_0x0x1073cd31_cls: + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_stat_32_lpf_acc_data_0x0x105c2672_cls: return super().get_child_by_system_rdl_name(name) @@ -3179,7 +3179,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_stat_32_errs_status_data_cls(FieldAsyncReadOnly): +class msk_top_regs_stat_32_errs_data_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -3219,7 +3219,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_stat_32_errs_cls(RegAsyncReadOnly): +class msk_top_regs_stat_32_errs_cls(RegAsyncReadWrite): """ Class to represent a register in the register model @@ -3237,7 +3237,7 @@ class msk_top_regs_stat_32_errs_cls(RegAsyncReadOnly): +--------------+-------------------------------------------------------------------------+ """ - __slots__ : list[str] = ['__status_data'] + __slots__ : list[str] = ['__data'] def __init__(self, address: int, @@ -3245,7 +3245,7 @@ def __init__(self, accesswidth: int, logger_handle: str, inst_name: str, - parent: Union[AsyncAddressMap,AsyncRegFile,ReadableAsyncMemory]): + parent: Union[AsyncAddressMap,AsyncRegFile,MemoryAsyncReadWrite]): super().__init__(address=address, width=width, @@ -3256,7 +3256,7 @@ def __init__(self, # build the field attributes - self.__status_data:msk_top_regs_stat_32_errs_status_data_cls = msk_top_regs_stat_32_errs_status_data_cls( + self.__data:msk_top_regs_stat_32_errs_data_cls = msk_top_regs_stat_32_errs_data_cls( parent_register=self, size_props=FieldSizeProps( width=32, @@ -3267,8 +3267,8 @@ def __init__(self, misc_props=FieldMiscProps( default=0, is_volatile=True), - logger_handle=logger_handle+'.status_data', - inst_name='status_data', + logger_handle=logger_handle+'.data', + inst_name='data', field_type=int) @property @@ -3276,7 +3276,7 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field """ generator that produces has all the fields within the register """ - yield self.status_data + yield self.data # Empty generator in case there are no children of this type if False: yield @@ -3287,9 +3287,9 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field # build the properties for the fields @property - def status_data(self) -> msk_top_regs_stat_32_errs_status_data_cls: + def data(self) -> msk_top_regs_stat_32_errs_data_cls: """ - Property to access status_data field of the register + Property to access data field of the register +--------------+-------------------------------------------------------------------------+ | SystemRDL | Value | @@ -3306,7 +3306,7 @@ def status_data(self) -> msk_top_regs_stat_32_errs_status_data_cls: | | errored-bits

| +--------------+-------------------------------------------------------------------------+ """ - return self.__status_data + return self.__data @property @@ -3318,7 +3318,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: Returns: dictionary whose key is the systemRDL names and value it the property name """ - return {'status_data':'status_data', + return {'data':'data', } @@ -3328,7 +3328,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_stat_32_errs_status_data_cls: + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_stat_32_errs_data_cls: return super().get_child_by_system_rdl_name(name) @@ -3352,7 +3352,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_stat_32_bits_status_data_cls(FieldAsyncReadOnly): +class msk_top_regs_stat_32_bits_data_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -3391,7 +3391,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_stat_32_bits_cls(RegAsyncReadOnly): +class msk_top_regs_stat_32_bits_cls(RegAsyncReadWrite): """ Class to represent a register in the register model @@ -3409,7 +3409,7 @@ class msk_top_regs_stat_32_bits_cls(RegAsyncReadOnly): +--------------+-------------------------------------------------------------------------+ """ - __slots__ : list[str] = ['__status_data'] + __slots__ : list[str] = ['__data'] def __init__(self, address: int, @@ -3417,7 +3417,7 @@ def __init__(self, accesswidth: int, logger_handle: str, inst_name: str, - parent: Union[AsyncAddressMap,AsyncRegFile,ReadableAsyncMemory]): + parent: Union[AsyncAddressMap,AsyncRegFile,MemoryAsyncReadWrite]): super().__init__(address=address, width=width, @@ -3428,7 +3428,7 @@ def __init__(self, # build the field attributes - self.__status_data:msk_top_regs_stat_32_bits_status_data_cls = msk_top_regs_stat_32_bits_status_data_cls( + self.__data:msk_top_regs_stat_32_bits_data_cls = msk_top_regs_stat_32_bits_data_cls( parent_register=self, size_props=FieldSizeProps( width=32, @@ -3439,8 +3439,8 @@ def __init__(self, misc_props=FieldMiscProps( default=0, is_volatile=True), - logger_handle=logger_handle+'.status_data', - inst_name='status_data', + logger_handle=logger_handle+'.data', + inst_name='data', field_type=int) @property @@ -3448,7 +3448,7 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field """ generator that produces has all the fields within the register """ - yield self.status_data + yield self.data # Empty generator in case there are no children of this type if False: yield @@ -3459,9 +3459,9 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field # build the properties for the fields @property - def status_data(self) -> msk_top_regs_stat_32_bits_status_data_cls: + def data(self) -> msk_top_regs_stat_32_bits_data_cls: """ - Property to access status_data field of the register + Property to access data field of the register +--------------+-------------------------------------------------------------------------+ | SystemRDL | Value | @@ -3477,7 +3477,7 @@ def status_data(self) -> msk_top_regs_stat_32_bits_status_data_cls: | | be calculated as the ratio of received bits to errored-bits

| +--------------+-------------------------------------------------------------------------+ """ - return self.__status_data + return self.__data @property @@ -3489,7 +3489,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: Returns: dictionary whose key is the systemRDL names and value it the property name """ - return {'status_data':'status_data', + return {'data':'data', } @@ -3499,7 +3499,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_stat_32_bits_status_data_cls: + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_stat_32_bits_data_cls: return super().get_child_by_system_rdl_name(name) @@ -4760,7 +4760,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_data_width_data_width_0x0x107468c8_cls(FieldAsyncReadWrite): +class msk_top_regs_data_width_data_width_0x0x105dda63_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -4836,7 +4836,7 @@ def __init__(self, # build the field attributes - self.__data_width:msk_top_regs_data_width_data_width_0x0x107468c8_cls = msk_top_regs_data_width_data_width_0x0x107468c8_cls( + self.__data_width:msk_top_regs_data_width_data_width_0x0x105dda63_cls = msk_top_regs_data_width_data_width_0x0x105dda63_cls( parent_register=self, size_props=FieldSizeProps( width=8, @@ -4867,7 +4867,7 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field # build the properties for the fields @property - def data_width(self) -> msk_top_regs_data_width_data_width_0x0x107468c8_cls: + def data_width(self) -> msk_top_regs_data_width_data_width_0x0x105dda63_cls: """ Property to access data_width field of the register @@ -4906,7 +4906,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_data_width_data_width_0x0x107468c8_cls: + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_data_width_data_width_0x0x105dda63_cls: return super().get_child_by_system_rdl_name(name) @@ -5752,7 +5752,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_config_nco_fw_config_data_0x0x1074bb14_cls(FieldAsyncReadWrite): +class msk_top_regs_config_nco_fw_config_data_0x0x105dea0f_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -5829,7 +5829,7 @@ def __init__(self, # build the field attributes - self.__config_data:msk_top_regs_config_nco_fw_config_data_0x0x1074bb14_cls = msk_top_regs_config_nco_fw_config_data_0x0x1074bb14_cls( + self.__config_data:msk_top_regs_config_nco_fw_config_data_0x0x105dea0f_cls = msk_top_regs_config_nco_fw_config_data_0x0x105dea0f_cls( parent_register=self, size_props=FieldSizeProps( width=32, @@ -5860,7 +5860,7 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field # build the properties for the fields @property - def config_data(self) -> msk_top_regs_config_nco_fw_config_data_0x0x1074bb14_cls: + def config_data(self) -> msk_top_regs_config_nco_fw_config_data_0x0x105dea0f_cls: """ Property to access config_data field of the register @@ -5901,7 +5901,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_config_nco_fw_config_data_0x0x1074bb14_cls: + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_config_nco_fw_config_data_0x0x105dea0f_cls: return super().get_child_by_system_rdl_name(name) @@ -5925,7 +5925,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_config_nco_fw_config_data_0x0x107566c9_cls(FieldAsyncReadWrite): +class msk_top_regs_config_nco_fw_config_data_0x0x105dea21_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -6002,7 +6002,7 @@ def __init__(self, # build the field attributes - self.__config_data:msk_top_regs_config_nco_fw_config_data_0x0x107566c9_cls = msk_top_regs_config_nco_fw_config_data_0x0x107566c9_cls( + self.__config_data:msk_top_regs_config_nco_fw_config_data_0x0x105dea21_cls = msk_top_regs_config_nco_fw_config_data_0x0x105dea21_cls( parent_register=self, size_props=FieldSizeProps( width=32, @@ -6033,7 +6033,7 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field # build the properties for the fields @property - def config_data(self) -> msk_top_regs_config_nco_fw_config_data_0x0x107566c9_cls: + def config_data(self) -> msk_top_regs_config_nco_fw_config_data_0x0x105dea21_cls: """ Property to access config_data field of the register @@ -6074,7 +6074,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_config_nco_fw_config_data_0x0x107566c9_cls: + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_config_nco_fw_config_data_0x0x105dea21_cls: return super().get_child_by_system_rdl_name(name) @@ -6098,7 +6098,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_config_nco_fw_config_data_0x0x10756468_cls(FieldAsyncReadWrite): +class msk_top_regs_config_nco_fw_config_data_0x0x105dea63_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -6175,7 +6175,7 @@ def __init__(self, # build the field attributes - self.__config_data:msk_top_regs_config_nco_fw_config_data_0x0x10756468_cls = msk_top_regs_config_nco_fw_config_data_0x0x10756468_cls( + self.__config_data:msk_top_regs_config_nco_fw_config_data_0x0x105dea63_cls = msk_top_regs_config_nco_fw_config_data_0x0x105dea63_cls( parent_register=self, size_props=FieldSizeProps( width=32, @@ -6206,7 +6206,7 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field # build the properties for the fields @property - def config_data(self) -> msk_top_regs_config_nco_fw_config_data_0x0x10756468_cls: + def config_data(self) -> msk_top_regs_config_nco_fw_config_data_0x0x105dea63_cls: """ Property to access config_data field of the register @@ -6247,7 +6247,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_config_nco_fw_config_data_0x0x10756468_cls: + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_config_nco_fw_config_data_0x0x105dea63_cls: return super().get_child_by_system_rdl_name(name) @@ -6271,7 +6271,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_config_nco_fw_config_data_0x0x1075c880_cls(FieldAsyncReadWrite): +class msk_top_regs_config_nco_fw_config_data_0x0x105dea75_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -6348,7 +6348,7 @@ def __init__(self, # build the field attributes - self.__config_data:msk_top_regs_config_nco_fw_config_data_0x0x1075c880_cls = msk_top_regs_config_nco_fw_config_data_0x0x1075c880_cls( + self.__config_data:msk_top_regs_config_nco_fw_config_data_0x0x105dea75_cls = msk_top_regs_config_nco_fw_config_data_0x0x105dea75_cls( parent_register=self, size_props=FieldSizeProps( width=32, @@ -6379,7 +6379,7 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field # build the properties for the fields @property - def config_data(self) -> msk_top_regs_config_nco_fw_config_data_0x0x1075c880_cls: + def config_data(self) -> msk_top_regs_config_nco_fw_config_data_0x0x105dea75_cls: """ Property to access config_data field of the register @@ -6420,7 +6420,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_config_nco_fw_config_data_0x0x1075c880_cls: + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_config_nco_fw_config_data_0x0x105dea75_cls: return super().get_child_by_system_rdl_name(name) @@ -6444,7 +6444,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_msk_stat_2_tx_ena_counter_cls(FieldAsyncReadOnly): +class msk_top_regs_msk_stat_2_data_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -6482,7 +6482,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_msk_stat_2_cls(RegAsyncReadOnly): +class msk_top_regs_msk_stat_2_cls(RegAsyncReadWrite): """ Class to represent a register in the register model @@ -6500,7 +6500,7 @@ class msk_top_regs_msk_stat_2_cls(RegAsyncReadOnly): +--------------+-------------------------------------------------------------------------+ """ - __slots__ : list[str] = ['__tx_ena_counter'] + __slots__ : list[str] = ['__data'] def __init__(self, address: int, @@ -6508,7 +6508,7 @@ def __init__(self, accesswidth: int, logger_handle: str, inst_name: str, - parent: Union[AsyncAddressMap,AsyncRegFile,ReadableAsyncMemory]): + parent: Union[AsyncAddressMap,AsyncRegFile,MemoryAsyncReadWrite]): super().__init__(address=address, width=width, @@ -6519,7 +6519,7 @@ def __init__(self, # build the field attributes - self.__tx_ena_counter:msk_top_regs_msk_stat_2_tx_ena_counter_cls = msk_top_regs_msk_stat_2_tx_ena_counter_cls( + self.__data:msk_top_regs_msk_stat_2_data_cls = msk_top_regs_msk_stat_2_data_cls( parent_register=self, size_props=FieldSizeProps( width=32, @@ -6530,8 +6530,8 @@ def __init__(self, misc_props=FieldMiscProps( default=0, is_volatile=True), - logger_handle=logger_handle+'.tx_ena_counter', - inst_name='tx_ena_counter', + logger_handle=logger_handle+'.data', + inst_name='data', field_type=int) @property @@ -6539,7 +6539,7 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field """ generator that produces has all the fields within the register """ - yield self.tx_ena_counter + yield self.data # Empty generator in case there are no children of this type if False: yield @@ -6550,9 +6550,9 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field # build the properties for the fields @property - def tx_ena_counter(self) -> msk_top_regs_msk_stat_2_tx_ena_counter_cls: + def data(self) -> msk_top_regs_msk_stat_2_data_cls: """ - Property to access tx_ena_counter field of the register + Property to access data field of the register +--------------+-------------------------------------------------------------------------+ | SystemRDL | Value | @@ -6567,7 +6567,7 @@ def tx_ena_counter(self) -> msk_top_regs_msk_stat_2_tx_ena_counter_cls: | |

Number of clocks on which Tx Enable is active

| +--------------+-------------------------------------------------------------------------+ """ - return self.__tx_ena_counter + return self.__data @property @@ -6579,7 +6579,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: Returns: dictionary whose key is the systemRDL names and value it the property name """ - return {'tx_ena_counter':'tx_ena_counter', + return {'data':'data', } @@ -6589,7 +6589,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_msk_stat_2_tx_ena_counter_cls: + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_msk_stat_2_data_cls: return super().get_child_by_system_rdl_name(name) @@ -6613,7 +6613,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_msk_stat_1_tx_bit_counter_cls(FieldAsyncReadOnly): +class msk_top_regs_msk_stat_1_data_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -6651,7 +6651,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_msk_stat_1_cls(RegAsyncReadOnly): +class msk_top_regs_msk_stat_1_cls(RegAsyncReadWrite): """ Class to represent a register in the register model @@ -6669,7 +6669,7 @@ class msk_top_regs_msk_stat_1_cls(RegAsyncReadOnly): +--------------+-------------------------------------------------------------------------+ """ - __slots__ : list[str] = ['__tx_bit_counter'] + __slots__ : list[str] = ['__data'] def __init__(self, address: int, @@ -6677,7 +6677,7 @@ def __init__(self, accesswidth: int, logger_handle: str, inst_name: str, - parent: Union[AsyncAddressMap,AsyncRegFile,ReadableAsyncMemory]): + parent: Union[AsyncAddressMap,AsyncRegFile,MemoryAsyncReadWrite]): super().__init__(address=address, width=width, @@ -6688,7 +6688,7 @@ def __init__(self, # build the field attributes - self.__tx_bit_counter:msk_top_regs_msk_stat_1_tx_bit_counter_cls = msk_top_regs_msk_stat_1_tx_bit_counter_cls( + self.__data:msk_top_regs_msk_stat_1_data_cls = msk_top_regs_msk_stat_1_data_cls( parent_register=self, size_props=FieldSizeProps( width=32, @@ -6697,10 +6697,10 @@ def __init__(self, low=0, high=31), misc_props=FieldMiscProps( - default=None, + default=0, is_volatile=True), - logger_handle=logger_handle+'.tx_bit_counter', - inst_name='tx_bit_counter', + logger_handle=logger_handle+'.data', + inst_name='data', field_type=int) @property @@ -6708,7 +6708,7 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field """ generator that produces has all the fields within the register """ - yield self.tx_bit_counter + yield self.data # Empty generator in case there are no children of this type if False: yield @@ -6719,9 +6719,9 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field # build the properties for the fields @property - def tx_bit_counter(self) -> msk_top_regs_msk_stat_1_tx_bit_counter_cls: + def data(self) -> msk_top_regs_msk_stat_1_data_cls: """ - Property to access tx_bit_counter field of the register + Property to access data field of the register +--------------+-------------------------------------------------------------------------+ | SystemRDL | Value | @@ -6736,7 +6736,7 @@ def tx_bit_counter(self) -> msk_top_regs_msk_stat_1_tx_bit_counter_cls: | |

Count of data requests made by modem

| +--------------+-------------------------------------------------------------------------+ """ - return self.__tx_bit_counter + return self.__data @property @@ -6748,7 +6748,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: Returns: dictionary whose key is the systemRDL names and value it the property name """ - return {'tx_bit_counter':'tx_bit_counter', + return {'data':'data', } @@ -6758,7 +6758,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_msk_stat_1_tx_bit_counter_cls: + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_msk_stat_1_data_cls: return super().get_child_by_system_rdl_name(name) @@ -8638,7 +8638,7 @@ def __init__(self, *, inst_name='Tx_Sync_Cnt', parent=self) - self.__lowpass_ema_alpha1:msk_top_regs_lowpass_ema_alpha_0x0x1075e9f4_cls = msk_top_regs_lowpass_ema_alpha_0x0x1075e9f4_cls( + self.__lowpass_ema_alpha1:msk_top_regs_lowpass_ema_alpha_0x0x105c0c74_cls = msk_top_regs_lowpass_ema_alpha_0x0x105c0c74_cls( address=self.address+132, accesswidth=32, width=32, @@ -9340,7 +9340,7 @@ def Tx_Sync_Cnt(self) -> msk_top_regs_tx_sync_cnt_cls: return self.__Tx_Sync_Cnt @property - def lowpass_ema_alpha1(self) -> msk_top_regs_lowpass_ema_alpha_0x0x1075e9f4_cls: + def lowpass_ema_alpha1(self) -> msk_top_regs_lowpass_ema_alpha_0x0x105c0c74_cls: """ Property to access lowpass_ema_alpha1 @@ -9586,7 +9586,7 @@ def get_child_by_system_rdl_name(self, name: Literal["Tx_Sync_Cnt"]) -> msk_top_ @overload - def get_child_by_system_rdl_name(self, name: Literal["lowpass_ema_alpha1"]) -> msk_top_regs_lowpass_ema_alpha_0x0x1075e9f4_cls: ... + def get_child_by_system_rdl_name(self, name: Literal["lowpass_ema_alpha1"]) -> msk_top_regs_lowpass_ema_alpha_0x0x105c0c74_cls: ... @overload @@ -9606,7 +9606,7 @@ def get_child_by_system_rdl_name(self, name: Literal["rx_async_fifo_rd_wr_ptr"]) @overload - def get_child_by_system_rdl_name(self, name: str) -> Union[msk_top_regs_msk_hash_lo_cls, msk_top_regs_msk_hash_hi_cls, msk_top_regs_msk_init_cls, msk_top_regs_msk_ctrl_cls, msk_top_regs_msk_stat_0_cls, msk_top_regs_msk_stat_1_cls, msk_top_regs_msk_stat_2_cls, msk_top_regs_config_nco_fw_desc_c4924cc6_name_0c494469_cls, msk_top_regs_config_nco_fw_desc_94d7aaf5_name_84dd0c1c_cls, msk_top_regs_config_nco_fw_desc_42134a4f_name_d97dbd51_cls, msk_top_regs_config_nco_fw_desc_16fb48c8_name_8d01a20d_cls, msk_top_regs_config_nco_fw_desc_43c0828f_name_bdc60ecf_cls, msk_top_regs_lpf_config_0_cls, msk_top_regs_lpf_config_1_cls, msk_top_regs_data_width_desc_58c848dd_name_2fbd8eba_cls, msk_top_regs_data_width_desc_6097df38_name_4609588b_cls, msk_top_regs_prbs_ctrl_cls, msk_top_regs_config_prbs_seed_cls, msk_top_regs_config_prbs_poly_cls, msk_top_regs_config_prbs_errmask_cls, msk_top_regs_stat_32_bits_cls, msk_top_regs_stat_32_errs_cls, msk_top_regs_stat_32_lpf_acc_desc_8cebc7dc_name_f20c6670_cls, msk_top_regs_stat_32_lpf_acc_desc_dea6bd99_name_758fd0ce_cls, msk_top_regs_msk_stat_3_cls, msk_top_regs_rx_sample_discard_cls, msk_top_regs_lpf_config_2_cls, msk_top_regs_observation_data_data_0c017ef4_desc_64ff3689_name_d8ad3b25_cls, msk_top_regs_observation_data_data_0515efaa_desc_ebde6d39_name_2c154788_cls, msk_top_regs_observation_data_data_25a21249_desc_417e1c96_name_3b640507_cls, msk_top_regs_observation_data_data_272a00b6_desc_70869502_name_3de9a0d3_cls, msk_top_regs_tx_sync_ctrl_cls, msk_top_regs_tx_sync_cnt_cls, msk_top_regs_lowpass_ema_alpha_0x0x1075e9f4_cls, msk_top_regs_lowpass_ema_alpha_cls, msk_top_regs_rx_power_cls, msk_top_regs_observation_data_data_cf6acbd7_name_aa4ec676_cls, msk_top_regs_observation_data_data_cf6acbd7_name_8a90eed1_cls, ]: ... + def get_child_by_system_rdl_name(self, name: str) -> Union[msk_top_regs_msk_hash_lo_cls, msk_top_regs_msk_hash_hi_cls, msk_top_regs_msk_init_cls, msk_top_regs_msk_ctrl_cls, msk_top_regs_msk_stat_0_cls, msk_top_regs_msk_stat_1_cls, msk_top_regs_msk_stat_2_cls, msk_top_regs_config_nco_fw_desc_c4924cc6_name_0c494469_cls, msk_top_regs_config_nco_fw_desc_94d7aaf5_name_84dd0c1c_cls, msk_top_regs_config_nco_fw_desc_42134a4f_name_d97dbd51_cls, msk_top_regs_config_nco_fw_desc_16fb48c8_name_8d01a20d_cls, msk_top_regs_config_nco_fw_desc_43c0828f_name_bdc60ecf_cls, msk_top_regs_lpf_config_0_cls, msk_top_regs_lpf_config_1_cls, msk_top_regs_data_width_desc_58c848dd_name_2fbd8eba_cls, msk_top_regs_data_width_desc_6097df38_name_4609588b_cls, msk_top_regs_prbs_ctrl_cls, msk_top_regs_config_prbs_seed_cls, msk_top_regs_config_prbs_poly_cls, msk_top_regs_config_prbs_errmask_cls, msk_top_regs_stat_32_bits_cls, msk_top_regs_stat_32_errs_cls, msk_top_regs_stat_32_lpf_acc_desc_8cebc7dc_name_f20c6670_cls, msk_top_regs_stat_32_lpf_acc_desc_dea6bd99_name_758fd0ce_cls, msk_top_regs_msk_stat_3_cls, msk_top_regs_rx_sample_discard_cls, msk_top_regs_lpf_config_2_cls, msk_top_regs_observation_data_data_0c017ef4_desc_64ff3689_name_d8ad3b25_cls, msk_top_regs_observation_data_data_0515efaa_desc_ebde6d39_name_2c154788_cls, msk_top_regs_observation_data_data_25a21249_desc_417e1c96_name_3b640507_cls, msk_top_regs_observation_data_data_272a00b6_desc_70869502_name_3de9a0d3_cls, msk_top_regs_tx_sync_ctrl_cls, msk_top_regs_tx_sync_cnt_cls, msk_top_regs_lowpass_ema_alpha_0x0x105c0c74_cls, msk_top_regs_lowpass_ema_alpha_cls, msk_top_regs_rx_power_cls, msk_top_regs_observation_data_data_cf6acbd7_name_aa4ec676_cls, msk_top_regs_observation_data_data_cf6acbd7_name_8a90eed1_cls, ]: ... def get_child_by_system_rdl_name(self, name: Any) -> Any: return super().get_child_by_system_rdl_name(name) diff --git a/rdl/outputs/python/msk_top_regs/sim/msk_top_regs.py b/rdl/outputs/python/msk_top_regs/sim/msk_top_regs.py index 0b442a7..f7af222 100644 --- a/rdl/outputs/python/msk_top_regs/sim/msk_top_regs.py +++ b/rdl/outputs/python/msk_top_regs/sim/msk_top_regs.py @@ -42,12 +42,12 @@ def _build_registers(self) -> dict[int, Union[list[Union[MemoryRegister, Registe fields=[FieldDefinition(high=0, low=0, msb=0, lsb=0, inst_name='demod_sync_lock'),FieldDefinition(high=1, low=1, msb=1, lsb=1, inst_name='tx_enable'),FieldDefinition(high=2, low=2, msb=2, lsb=2, inst_name='rx_enable'),FieldDefinition(high=3, low=3, msb=3, lsb=3, inst_name='tx_axis_valid'), ]), 20 : - Register(width=32, full_inst_name='msk_top_regs.Tx_Bit_Count', readable=True, writable=False, - fields=[FieldDefinition(high=31, low=0, msb=31, lsb=0, inst_name='tx_bit_counter'), + Register(width=32, full_inst_name='msk_top_regs.Tx_Bit_Count', readable=True, writable=True, + fields=[FieldDefinition(high=31, low=0, msb=31, lsb=0, inst_name='data'), ]), 24 : - Register(width=32, full_inst_name='msk_top_regs.Tx_Enable_Count', readable=True, writable=False, - fields=[FieldDefinition(high=31, low=0, msb=31, lsb=0, inst_name='tx_ena_counter'), + Register(width=32, full_inst_name='msk_top_regs.Tx_Enable_Count', readable=True, writable=True, + fields=[FieldDefinition(high=31, low=0, msb=31, lsb=0, inst_name='data'), ]), 28 : Register(width=32, full_inst_name='msk_top_regs.Fb_FreqWord', readable=True, writable=True, @@ -102,24 +102,24 @@ def _build_registers(self) -> dict[int, Union[list[Union[MemoryRegister, Registe fields=[FieldDefinition(high=31, low=0, msb=31, lsb=0, inst_name='config_data'), ]), 80 : - Register(width=32, full_inst_name='msk_top_regs.PRBS_Bit_Count', readable=True, writable=False, - fields=[FieldDefinition(high=31, low=0, msb=31, lsb=0, inst_name='status_data'), + Register(width=32, full_inst_name='msk_top_regs.PRBS_Bit_Count', readable=True, writable=True, + fields=[FieldDefinition(high=31, low=0, msb=31, lsb=0, inst_name='data'), ]), 84 : - Register(width=32, full_inst_name='msk_top_regs.PRBS_Error_Count', readable=True, writable=False, - fields=[FieldDefinition(high=31, low=0, msb=31, lsb=0, inst_name='status_data'), + Register(width=32, full_inst_name='msk_top_regs.PRBS_Error_Count', readable=True, writable=True, + fields=[FieldDefinition(high=31, low=0, msb=31, lsb=0, inst_name='data'), ]), 88 : - Register(width=32, full_inst_name='msk_top_regs.LPF_Accum_F1', readable=True, writable=False, - fields=[FieldDefinition(high=31, low=0, msb=31, lsb=0, inst_name='status_data'), + Register(width=32, full_inst_name='msk_top_regs.LPF_Accum_F1', readable=True, writable=True, + fields=[FieldDefinition(high=31, low=0, msb=31, lsb=0, inst_name='data'), ]), 92 : - Register(width=32, full_inst_name='msk_top_regs.LPF_Accum_F2', readable=True, writable=False, - fields=[FieldDefinition(high=31, low=0, msb=31, lsb=0, inst_name='status_data'), + Register(width=32, full_inst_name='msk_top_regs.LPF_Accum_F2', readable=True, writable=True, + fields=[FieldDefinition(high=31, low=0, msb=31, lsb=0, inst_name='data'), ]), 96 : - Register(width=32, full_inst_name='msk_top_regs.axis_xfer_count', readable=True, writable=False, - fields=[FieldDefinition(high=31, low=0, msb=31, lsb=0, inst_name='xfer_count'), + Register(width=32, full_inst_name='msk_top_regs.axis_xfer_count', readable=True, writable=True, + fields=[FieldDefinition(high=31, low=0, msb=31, lsb=0, inst_name='data'), ]), 100 : Register(width=32, full_inst_name='msk_top_regs.Rx_Sample_Discard', readable=True, writable=True, @@ -130,19 +130,19 @@ def _build_registers(self) -> dict[int, Union[list[Union[MemoryRegister, Registe fields=[FieldDefinition(high=23, low=0, msb=23, lsb=0, inst_name='p_gain'),FieldDefinition(high=31, low=24, msb=31, lsb=24, inst_name='p_shift'), ]), 108 : - Register(width=32, full_inst_name='msk_top_regs.f1_nco_adjust', readable=True, writable=False, + Register(width=32, full_inst_name='msk_top_regs.f1_nco_adjust', readable=True, writable=True, fields=[FieldDefinition(high=31, low=0, msb=31, lsb=0, inst_name='data'), ]), 112 : - Register(width=32, full_inst_name='msk_top_regs.f2_nco_adjust', readable=True, writable=False, + Register(width=32, full_inst_name='msk_top_regs.f2_nco_adjust', readable=True, writable=True, fields=[FieldDefinition(high=31, low=0, msb=31, lsb=0, inst_name='data'), ]), 116 : - Register(width=32, full_inst_name='msk_top_regs.f1_error', readable=True, writable=False, + Register(width=32, full_inst_name='msk_top_regs.f1_error', readable=True, writable=True, fields=[FieldDefinition(high=31, low=0, msb=31, lsb=0, inst_name='data'), ]), 120 : - Register(width=32, full_inst_name='msk_top_regs.f2_error', readable=True, writable=False, + Register(width=32, full_inst_name='msk_top_regs.f2_error', readable=True, writable=True, fields=[FieldDefinition(high=31, low=0, msb=31, lsb=0, inst_name='data'), ]), 124 : @@ -162,15 +162,15 @@ def _build_registers(self) -> dict[int, Union[list[Union[MemoryRegister, Registe fields=[FieldDefinition(high=17, low=0, msb=17, lsb=0, inst_name='alpha'), ]), 140 : - Register(width=32, full_inst_name='msk_top_regs.rx_power', readable=True, writable=False, - fields=[FieldDefinition(high=22, low=0, msb=22, lsb=0, inst_name='rx_power'), + Register(width=32, full_inst_name='msk_top_regs.rx_power', readable=True, writable=True, + fields=[FieldDefinition(high=22, low=0, msb=22, lsb=0, inst_name='data'), ]), 144 : - Register(width=32, full_inst_name='msk_top_regs.tx_async_fifo_rd_wr_ptr', readable=True, writable=False, + Register(width=32, full_inst_name='msk_top_regs.tx_async_fifo_rd_wr_ptr', readable=True, writable=True, fields=[FieldDefinition(high=31, low=0, msb=31, lsb=0, inst_name='data'), ]), 148 : - Register(width=32, full_inst_name='msk_top_regs.rx_async_fifo_rd_wr_ptr', readable=True, writable=False, + Register(width=32, full_inst_name='msk_top_regs.rx_async_fifo_rd_wr_ptr', readable=True, writable=True, fields=[FieldDefinition(high=31, low=0, msb=31, lsb=0, inst_name='data'), ]), } diff --git a/rdl/outputs/python/msk_top_regs/tests/test_msk_top_regs.py b/rdl/outputs/python/msk_top_regs/tests/test_msk_top_regs.py index 2b9468e..c76701a 100644 --- a/rdl/outputs/python/msk_top_regs/tests/test_msk_top_regs.py +++ b/rdl/outputs/python/msk_top_regs/tests/test_msk_top_regs.py @@ -212,12 +212,12 @@ def test_inst_name(self) -> None: with self.subTest(msg='node: msk_top_regs.MSK_Status.tx_axis_valid'): self.assertEqual(self.dut.MSK_Status.tx_axis_valid.inst_name, 'tx_axis_valid') # type: ignore[union-attr] self.assertEqual(self.dut.MSK_Status.tx_axis_valid.full_inst_name, 'msk_top_regs.MSK_Status.tx_axis_valid') # type: ignore[union-attr] - with self.subTest(msg='node: msk_top_regs.Tx_Bit_Count.tx_bit_counter'): - self.assertEqual(self.dut.Tx_Bit_Count.tx_bit_counter.inst_name, 'tx_bit_counter') # type: ignore[union-attr] - self.assertEqual(self.dut.Tx_Bit_Count.tx_bit_counter.full_inst_name, 'msk_top_regs.Tx_Bit_Count.tx_bit_counter') # type: ignore[union-attr] - with self.subTest(msg='node: msk_top_regs.Tx_Enable_Count.tx_ena_counter'): - self.assertEqual(self.dut.Tx_Enable_Count.tx_ena_counter.inst_name, 'tx_ena_counter') # type: ignore[union-attr] - self.assertEqual(self.dut.Tx_Enable_Count.tx_ena_counter.full_inst_name, 'msk_top_regs.Tx_Enable_Count.tx_ena_counter') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.Tx_Bit_Count.data'): + self.assertEqual(self.dut.Tx_Bit_Count.data.inst_name, 'data') # type: ignore[union-attr] + self.assertEqual(self.dut.Tx_Bit_Count.data.full_inst_name, 'msk_top_regs.Tx_Bit_Count.data') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.Tx_Enable_Count.data'): + self.assertEqual(self.dut.Tx_Enable_Count.data.inst_name, 'data') # type: ignore[union-attr] + self.assertEqual(self.dut.Tx_Enable_Count.data.full_inst_name, 'msk_top_regs.Tx_Enable_Count.data') # type: ignore[union-attr] with self.subTest(msg='node: msk_top_regs.Fb_FreqWord.config_data'): self.assertEqual(self.dut.Fb_FreqWord.config_data.inst_name, 'config_data') # type: ignore[union-attr] self.assertEqual(self.dut.Fb_FreqWord.config_data.full_inst_name, 'msk_top_regs.Fb_FreqWord.config_data') # type: ignore[union-attr] @@ -284,21 +284,21 @@ def test_inst_name(self) -> None: with self.subTest(msg='node: msk_top_regs.PRBS_Error_Mask.config_data'): self.assertEqual(self.dut.PRBS_Error_Mask.config_data.inst_name, 'config_data') # type: ignore[union-attr] self.assertEqual(self.dut.PRBS_Error_Mask.config_data.full_inst_name, 'msk_top_regs.PRBS_Error_Mask.config_data') # type: ignore[union-attr] - with self.subTest(msg='node: msk_top_regs.PRBS_Bit_Count.status_data'): - self.assertEqual(self.dut.PRBS_Bit_Count.status_data.inst_name, 'status_data') # type: ignore[union-attr] - self.assertEqual(self.dut.PRBS_Bit_Count.status_data.full_inst_name, 'msk_top_regs.PRBS_Bit_Count.status_data') # type: ignore[union-attr] - with self.subTest(msg='node: msk_top_regs.PRBS_Error_Count.status_data'): - self.assertEqual(self.dut.PRBS_Error_Count.status_data.inst_name, 'status_data') # type: ignore[union-attr] - self.assertEqual(self.dut.PRBS_Error_Count.status_data.full_inst_name, 'msk_top_regs.PRBS_Error_Count.status_data') # type: ignore[union-attr] - with self.subTest(msg='node: msk_top_regs.LPF_Accum_F1.status_data'): - self.assertEqual(self.dut.LPF_Accum_F1.status_data.inst_name, 'status_data') # type: ignore[union-attr] - self.assertEqual(self.dut.LPF_Accum_F1.status_data.full_inst_name, 'msk_top_regs.LPF_Accum_F1.status_data') # type: ignore[union-attr] - with self.subTest(msg='node: msk_top_regs.LPF_Accum_F2.status_data'): - self.assertEqual(self.dut.LPF_Accum_F2.status_data.inst_name, 'status_data') # type: ignore[union-attr] - self.assertEqual(self.dut.LPF_Accum_F2.status_data.full_inst_name, 'msk_top_regs.LPF_Accum_F2.status_data') # type: ignore[union-attr] - with self.subTest(msg='node: msk_top_regs.axis_xfer_count.xfer_count'): - self.assertEqual(self.dut.axis_xfer_count.xfer_count.inst_name, 'xfer_count') # type: ignore[union-attr] - self.assertEqual(self.dut.axis_xfer_count.xfer_count.full_inst_name, 'msk_top_regs.axis_xfer_count.xfer_count') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.PRBS_Bit_Count.data'): + self.assertEqual(self.dut.PRBS_Bit_Count.data.inst_name, 'data') # type: ignore[union-attr] + self.assertEqual(self.dut.PRBS_Bit_Count.data.full_inst_name, 'msk_top_regs.PRBS_Bit_Count.data') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.PRBS_Error_Count.data'): + self.assertEqual(self.dut.PRBS_Error_Count.data.inst_name, 'data') # type: ignore[union-attr] + self.assertEqual(self.dut.PRBS_Error_Count.data.full_inst_name, 'msk_top_regs.PRBS_Error_Count.data') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.LPF_Accum_F1.data'): + self.assertEqual(self.dut.LPF_Accum_F1.data.inst_name, 'data') # type: ignore[union-attr] + self.assertEqual(self.dut.LPF_Accum_F1.data.full_inst_name, 'msk_top_regs.LPF_Accum_F1.data') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.LPF_Accum_F2.data'): + self.assertEqual(self.dut.LPF_Accum_F2.data.inst_name, 'data') # type: ignore[union-attr] + self.assertEqual(self.dut.LPF_Accum_F2.data.full_inst_name, 'msk_top_regs.LPF_Accum_F2.data') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.axis_xfer_count.data'): + self.assertEqual(self.dut.axis_xfer_count.data.inst_name, 'data') # type: ignore[union-attr] + self.assertEqual(self.dut.axis_xfer_count.data.full_inst_name, 'msk_top_regs.axis_xfer_count.data') # type: ignore[union-attr] with self.subTest(msg='node: msk_top_regs.Rx_Sample_Discard.rx_sample_discard'): self.assertEqual(self.dut.Rx_Sample_Discard.rx_sample_discard.inst_name, 'rx_sample_discard') # type: ignore[union-attr] self.assertEqual(self.dut.Rx_Sample_Discard.rx_sample_discard.full_inst_name, 'msk_top_regs.Rx_Sample_Discard.rx_sample_discard') # type: ignore[union-attr] @@ -344,9 +344,9 @@ def test_inst_name(self) -> None: with self.subTest(msg='node: msk_top_regs.lowpass_ema_alpha2.alpha'): self.assertEqual(self.dut.lowpass_ema_alpha2.alpha.inst_name, 'alpha') # type: ignore[union-attr] self.assertEqual(self.dut.lowpass_ema_alpha2.alpha.full_inst_name, 'msk_top_regs.lowpass_ema_alpha2.alpha') # type: ignore[union-attr] - with self.subTest(msg='node: msk_top_regs.rx_power.rx_power'): - self.assertEqual(self.dut.rx_power.rx_power.inst_name, 'rx_power') # type: ignore[union-attr] - self.assertEqual(self.dut.rx_power.rx_power.full_inst_name, 'msk_top_regs.rx_power.rx_power') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.rx_power.data'): + self.assertEqual(self.dut.rx_power.data.inst_name, 'data') # type: ignore[union-attr] + self.assertEqual(self.dut.rx_power.data.full_inst_name, 'msk_top_regs.rx_power.data') # type: ignore[union-attr] with self.subTest(msg='node: msk_top_regs.tx_async_fifo_rd_wr_ptr.data'): self.assertEqual(self.dut.tx_async_fifo_rd_wr_ptr.data.inst_name, 'data') # type: ignore[union-attr] self.assertEqual(self.dut.tx_async_fifo_rd_wr_ptr.data.full_inst_name, 'msk_top_regs.tx_async_fifo_rd_wr_ptr.data') # type: ignore[union-attr] @@ -723,17 +723,17 @@ def test_name_property(self) -> None: - with self.subTest(msg='node: msk_top_regs.Tx_Bit_Count.tx_bit_counter'): + with self.subTest(msg='node: msk_top_regs.Tx_Bit_Count.data'): - self.assertEqual(self.dut.Tx_Bit_Count.tx_bit_counter.rdl_name, "Tx Bit Count") # type: ignore[union-attr] + self.assertEqual(self.dut.Tx_Bit_Count.data.rdl_name, "Tx Bit Count") # type: ignore[union-attr] - with self.subTest(msg='node: msk_top_regs.Tx_Enable_Count.tx_ena_counter'): + with self.subTest(msg='node: msk_top_regs.Tx_Enable_Count.data'): - self.assertEqual(self.dut.Tx_Enable_Count.tx_ena_counter.rdl_name, "Tx Enable Count") # type: ignore[union-attr] + self.assertEqual(self.dut.Tx_Enable_Count.data.rdl_name, "Tx Enable Count") # type: ignore[union-attr] @@ -891,38 +891,38 @@ def test_name_property(self) -> None: - with self.subTest(msg='node: msk_top_regs.PRBS_Bit_Count.status_data'): + with self.subTest(msg='node: msk_top_regs.PRBS_Bit_Count.data'): - self.assertEqual(self.dut.PRBS_Bit_Count.status_data.rdl_name, "PRBS Bits Received") # type: ignore[union-attr] + self.assertEqual(self.dut.PRBS_Bit_Count.data.rdl_name, "PRBS Bits Received") # type: ignore[union-attr] - with self.subTest(msg='node: msk_top_regs.PRBS_Error_Count.status_data'): + with self.subTest(msg='node: msk_top_regs.PRBS_Error_Count.data'): - self.assertEqual(self.dut.PRBS_Error_Count.status_data.rdl_name, "PRBS Bit Errors") # type: ignore[union-attr] + self.assertEqual(self.dut.PRBS_Error_Count.data.rdl_name, "PRBS Bit Errors") # type: ignore[union-attr] - with self.subTest(msg='node: msk_top_regs.LPF_Accum_F1.status_data'): + with self.subTest(msg='node: msk_top_regs.LPF_Accum_F1.data'): - self.assertEqual(self.dut.LPF_Accum_F1.status_data.rdl_name, "PI Controller Accumulator Value") # type: ignore[union-attr] + self.assertEqual(self.dut.LPF_Accum_F1.data.rdl_name, "PI Controller Accumulator Value") # type: ignore[union-attr] - with self.subTest(msg='node: msk_top_regs.LPF_Accum_F2.status_data'): + with self.subTest(msg='node: msk_top_regs.LPF_Accum_F2.data'): - self.assertEqual(self.dut.LPF_Accum_F2.status_data.rdl_name, "PI Controller Accumulator Value") # type: ignore[union-attr] + self.assertEqual(self.dut.LPF_Accum_F2.data.rdl_name, "PI Controller Accumulator Value") # type: ignore[union-attr] - with self.subTest(msg='node: msk_top_regs.axis_xfer_count.xfer_count'): + with self.subTest(msg='node: msk_top_regs.axis_xfer_count.data'): - self.assertEqual(self.dut.axis_xfer_count.xfer_count.rdl_name, "S_AXIS Transfers") # type: ignore[union-attr] + self.assertEqual(self.dut.axis_xfer_count.data.rdl_name, "S_AXIS Transfers") # type: ignore[union-attr] @@ -1031,10 +1031,10 @@ def test_name_property(self) -> None: - with self.subTest(msg='node: msk_top_regs.rx_power.rx_power'): + with self.subTest(msg='node: msk_top_regs.rx_power.data'): - self.assertEqual(self.dut.rx_power.rx_power.rdl_name, "Receive Power") # type: ignore[union-attr] + self.assertEqual(self.dut.rx_power.data.rdl_name, "Receive Power") # type: ignore[union-attr] @@ -1422,17 +1422,17 @@ def test_desc(self) -> None: - with self.subTest(msg='node: msk_top_regs.Tx_Bit_Count.tx_bit_counter'): + with self.subTest(msg='node: msk_top_regs.Tx_Bit_Count.data'): - self.assertEqual(self.dut.Tx_Bit_Count.tx_bit_counter.rdl_desc, "Count of data requests made by modem") # type: ignore[union-attr] + self.assertEqual(self.dut.Tx_Bit_Count.data.rdl_desc, "Count of data requests made by modem") # type: ignore[union-attr] - with self.subTest(msg='node: msk_top_regs.Tx_Enable_Count.tx_ena_counter'): + with self.subTest(msg='node: msk_top_regs.Tx_Enable_Count.data'): - self.assertEqual(self.dut.Tx_Enable_Count.tx_ena_counter.rdl_desc, "Number of clocks on which Tx Enable is active") # type: ignore[union-attr] + self.assertEqual(self.dut.Tx_Enable_Count.data.rdl_desc, "Number of clocks on which Tx Enable is active") # type: ignore[union-attr] @@ -1590,38 +1590,38 @@ def test_desc(self) -> None: - with self.subTest(msg='node: msk_top_regs.PRBS_Bit_Count.status_data'): + with self.subTest(msg='node: msk_top_regs.PRBS_Bit_Count.data'): - self.assertEqual(self.dut.PRBS_Bit_Count.status_data.rdl_desc, "Number of bits received by the PRBS monitor since last\nBER can be calculated as the ratio of received bits to errored-bits") # type: ignore[union-attr] + self.assertEqual(self.dut.PRBS_Bit_Count.data.rdl_desc, "Number of bits received by the PRBS monitor since last\nBER can be calculated as the ratio of received bits to errored-bits") # type: ignore[union-attr] - with self.subTest(msg='node: msk_top_regs.PRBS_Error_Count.status_data'): + with self.subTest(msg='node: msk_top_regs.PRBS_Error_Count.data'): - self.assertEqual(self.dut.PRBS_Error_Count.status_data.rdl_desc, "Number of errored-bits received by the PRBS monitor since last sync\nBER can be calculated as the ratio of received bits to errored-bits") # type: ignore[union-attr] + self.assertEqual(self.dut.PRBS_Error_Count.data.rdl_desc, "Number of errored-bits received by the PRBS monitor since last sync\nBER can be calculated as the ratio of received bits to errored-bits") # type: ignore[union-attr] - with self.subTest(msg='node: msk_top_regs.LPF_Accum_F1.status_data'): + with self.subTest(msg='node: msk_top_regs.LPF_Accum_F1.data'): - self.assertEqual(self.dut.LPF_Accum_F1.status_data.rdl_desc, "PI Controller Accumulator Value") # type: ignore[union-attr] + self.assertEqual(self.dut.LPF_Accum_F1.data.rdl_desc, "PI Controller Accumulator Value") # type: ignore[union-attr] - with self.subTest(msg='node: msk_top_regs.LPF_Accum_F2.status_data'): + with self.subTest(msg='node: msk_top_regs.LPF_Accum_F2.data'): - self.assertEqual(self.dut.LPF_Accum_F2.status_data.rdl_desc, "PI Controller Accumulator Value") # type: ignore[union-attr] + self.assertEqual(self.dut.LPF_Accum_F2.data.rdl_desc, "PI Controller Accumulator Value") # type: ignore[union-attr] - with self.subTest(msg='node: msk_top_regs.axis_xfer_count.xfer_count'): + with self.subTest(msg='node: msk_top_regs.axis_xfer_count.data'): - self.assertEqual(self.dut.axis_xfer_count.xfer_count.rdl_desc, "Number completed S_AXIS transfers") # type: ignore[union-attr] + self.assertEqual(self.dut.axis_xfer_count.data.rdl_desc, "Number completed S_AXIS transfers") # type: ignore[union-attr] @@ -1730,10 +1730,10 @@ def test_desc(self) -> None: - with self.subTest(msg='node: msk_top_regs.rx_power.rx_power'): + with self.subTest(msg='node: msk_top_regs.rx_power.data'): - self.assertEqual(self.dut.rx_power.rx_power.rdl_desc, "Value that represent the RMS power of the incoming I;") # type: ignore[union-attr] + self.assertEqual(self.dut.rx_power.data.rdl_desc, "Value that represent the RMS power of the incoming I;") # type: ignore[union-attr] @@ -2278,9 +2278,9 @@ def test_field_properties(self) -> None: self.assertEqual(fut.default,0) self.assertEqual(fut.is_volatile,True) - with self.subTest(msg='field: msk_top_regs.Tx_Bit_Count.tx_bit_counter'): - # test properties of field: msk_top_regs.Tx_Bit_Count.tx_bit_counter - fut = self.dut.Tx_Bit_Count.tx_bit_counter # type: ignore[union-attr] + with self.subTest(msg='field: msk_top_regs.Tx_Bit_Count.data'): + # test properties of field: msk_top_regs.Tx_Bit_Count.data + fut = self.dut.Tx_Bit_Count.data # type: ignore[union-attr] if not isinstance(fut, Field): raise TypeError('This test relies on node being of type Field') self.assertEqual(fut.lsb,0) @@ -2291,12 +2291,12 @@ def test_field_properties(self) -> None: self.assertEqual(fut.inverse_bitmask,0x0) self.assertEqual(fut.max_value,0xFFFFFFFF) - self.assertEqual(fut.default,None) + self.assertEqual(fut.default,0) self.assertEqual(fut.is_volatile,True) - with self.subTest(msg='field: msk_top_regs.Tx_Enable_Count.tx_ena_counter'): - # test properties of field: msk_top_regs.Tx_Enable_Count.tx_ena_counter - fut = self.dut.Tx_Enable_Count.tx_ena_counter # type: ignore[union-attr] + with self.subTest(msg='field: msk_top_regs.Tx_Enable_Count.data'): + # test properties of field: msk_top_regs.Tx_Enable_Count.data + fut = self.dut.Tx_Enable_Count.data # type: ignore[union-attr] if not isinstance(fut, Field): raise TypeError('This test relies on node being of type Field') self.assertEqual(fut.lsb,0) @@ -2662,9 +2662,9 @@ def test_field_properties(self) -> None: self.assertEqual(fut.default,0) self.assertEqual(fut.is_volatile,False) - with self.subTest(msg='field: msk_top_regs.PRBS_Bit_Count.status_data'): - # test properties of field: msk_top_regs.PRBS_Bit_Count.status_data - fut = self.dut.PRBS_Bit_Count.status_data # type: ignore[union-attr] + with self.subTest(msg='field: msk_top_regs.PRBS_Bit_Count.data'): + # test properties of field: msk_top_regs.PRBS_Bit_Count.data + fut = self.dut.PRBS_Bit_Count.data # type: ignore[union-attr] if not isinstance(fut, Field): raise TypeError('This test relies on node being of type Field') self.assertEqual(fut.lsb,0) @@ -2678,9 +2678,9 @@ def test_field_properties(self) -> None: self.assertEqual(fut.default,0) self.assertEqual(fut.is_volatile,True) - with self.subTest(msg='field: msk_top_regs.PRBS_Error_Count.status_data'): - # test properties of field: msk_top_regs.PRBS_Error_Count.status_data - fut = self.dut.PRBS_Error_Count.status_data # type: ignore[union-attr] + with self.subTest(msg='field: msk_top_regs.PRBS_Error_Count.data'): + # test properties of field: msk_top_regs.PRBS_Error_Count.data + fut = self.dut.PRBS_Error_Count.data # type: ignore[union-attr] if not isinstance(fut, Field): raise TypeError('This test relies on node being of type Field') self.assertEqual(fut.lsb,0) @@ -2694,9 +2694,9 @@ def test_field_properties(self) -> None: self.assertEqual(fut.default,0) self.assertEqual(fut.is_volatile,True) - with self.subTest(msg='field: msk_top_regs.LPF_Accum_F1.status_data'): - # test properties of field: msk_top_regs.LPF_Accum_F1.status_data - fut = self.dut.LPF_Accum_F1.status_data # type: ignore[union-attr] + with self.subTest(msg='field: msk_top_regs.LPF_Accum_F1.data'): + # test properties of field: msk_top_regs.LPF_Accum_F1.data + fut = self.dut.LPF_Accum_F1.data # type: ignore[union-attr] if not isinstance(fut, Field): raise TypeError('This test relies on node being of type Field') self.assertEqual(fut.lsb,0) @@ -2710,9 +2710,9 @@ def test_field_properties(self) -> None: self.assertEqual(fut.default,0) self.assertEqual(fut.is_volatile,True) - with self.subTest(msg='field: msk_top_regs.LPF_Accum_F2.status_data'): - # test properties of field: msk_top_regs.LPF_Accum_F2.status_data - fut = self.dut.LPF_Accum_F2.status_data # type: ignore[union-attr] + with self.subTest(msg='field: msk_top_regs.LPF_Accum_F2.data'): + # test properties of field: msk_top_regs.LPF_Accum_F2.data + fut = self.dut.LPF_Accum_F2.data # type: ignore[union-attr] if not isinstance(fut, Field): raise TypeError('This test relies on node being of type Field') self.assertEqual(fut.lsb,0) @@ -2726,9 +2726,9 @@ def test_field_properties(self) -> None: self.assertEqual(fut.default,0) self.assertEqual(fut.is_volatile,True) - with self.subTest(msg='field: msk_top_regs.axis_xfer_count.xfer_count'): - # test properties of field: msk_top_regs.axis_xfer_count.xfer_count - fut = self.dut.axis_xfer_count.xfer_count # type: ignore[union-attr] + with self.subTest(msg='field: msk_top_regs.axis_xfer_count.data'): + # test properties of field: msk_top_regs.axis_xfer_count.data + fut = self.dut.axis_xfer_count.data # type: ignore[union-attr] if not isinstance(fut, Field): raise TypeError('This test relies on node being of type Field') self.assertEqual(fut.lsb,0) @@ -2982,9 +2982,9 @@ def test_field_properties(self) -> None: self.assertEqual(fut.default,0) self.assertEqual(fut.is_volatile,False) - with self.subTest(msg='field: msk_top_regs.rx_power.rx_power'): - # test properties of field: msk_top_regs.rx_power.rx_power - fut = self.dut.rx_power.rx_power # type: ignore[union-attr] + with self.subTest(msg='field: msk_top_regs.rx_power.data'): + # test properties of field: msk_top_regs.rx_power.data + fut = self.dut.rx_power.data # type: ignore[union-attr] if not isinstance(fut, Field): raise TypeError('This test relies on node being of type Field') self.assertEqual(fut.lsb,0) @@ -3311,13 +3311,13 @@ def test_user_defined_properties(self) -> None: self.assertDictEqual(self.dut.MSK_Status.tx_axis_valid.udp,{}) - with self.subTest(msg='register: msk_top_regs.Tx_Bit_Count.tx_bit_counter'): + with self.subTest(msg='register: msk_top_regs.Tx_Bit_Count.data'): - self.assertDictEqual(self.dut.Tx_Bit_Count.tx_bit_counter.udp,{}) + self.assertDictEqual(self.dut.Tx_Bit_Count.data.udp,{}) - with self.subTest(msg='register: msk_top_regs.Tx_Enable_Count.tx_ena_counter'): + with self.subTest(msg='register: msk_top_regs.Tx_Enable_Count.data'): - self.assertDictEqual(self.dut.Tx_Enable_Count.tx_ena_counter.udp,{}) + self.assertDictEqual(self.dut.Tx_Enable_Count.data.udp,{}) with self.subTest(msg='register: msk_top_regs.Fb_FreqWord.config_data'): @@ -3407,25 +3407,25 @@ def test_user_defined_properties(self) -> None: self.assertDictEqual(self.dut.PRBS_Error_Mask.config_data.udp,{}) - with self.subTest(msg='register: msk_top_regs.PRBS_Bit_Count.status_data'): + with self.subTest(msg='register: msk_top_regs.PRBS_Bit_Count.data'): - self.assertDictEqual(self.dut.PRBS_Bit_Count.status_data.udp,{}) + self.assertDictEqual(self.dut.PRBS_Bit_Count.data.udp,{}) - with self.subTest(msg='register: msk_top_regs.PRBS_Error_Count.status_data'): + with self.subTest(msg='register: msk_top_regs.PRBS_Error_Count.data'): - self.assertDictEqual(self.dut.PRBS_Error_Count.status_data.udp,{}) + self.assertDictEqual(self.dut.PRBS_Error_Count.data.udp,{}) - with self.subTest(msg='register: msk_top_regs.LPF_Accum_F1.status_data'): + with self.subTest(msg='register: msk_top_regs.LPF_Accum_F1.data'): - self.assertDictEqual(self.dut.LPF_Accum_F1.status_data.udp,{}) + self.assertDictEqual(self.dut.LPF_Accum_F1.data.udp,{}) - with self.subTest(msg='register: msk_top_regs.LPF_Accum_F2.status_data'): + with self.subTest(msg='register: msk_top_regs.LPF_Accum_F2.data'): - self.assertDictEqual(self.dut.LPF_Accum_F2.status_data.udp,{}) + self.assertDictEqual(self.dut.LPF_Accum_F2.data.udp,{}) - with self.subTest(msg='register: msk_top_regs.axis_xfer_count.xfer_count'): + with self.subTest(msg='register: msk_top_regs.axis_xfer_count.data'): - self.assertDictEqual(self.dut.axis_xfer_count.xfer_count.udp,{}) + self.assertDictEqual(self.dut.axis_xfer_count.data.udp,{}) with self.subTest(msg='register: msk_top_regs.Rx_Sample_Discard.rx_sample_discard'): @@ -3487,9 +3487,9 @@ def test_user_defined_properties(self) -> None: self.assertDictEqual(self.dut.lowpass_ema_alpha2.alpha.udp,{}) - with self.subTest(msg='register: msk_top_regs.rx_power.rx_power'): + with self.subTest(msg='register: msk_top_regs.rx_power.data'): - self.assertDictEqual(self.dut.rx_power.rx_power.udp,{}) + self.assertDictEqual(self.dut.rx_power.data.udp,{}) with self.subTest(msg='register: msk_top_regs.tx_async_fifo_rd_wr_ptr.data'): @@ -3916,9 +3916,43 @@ async def test_register_read_and_write(self) -> None: - # test that a non-writable register has no write method and attempting one generates and error - with self.assertRaises(AttributeError): - await rut.write(0) # type: ignore[attr-defined] + if not isinstance(rut, (RegAsyncWriteOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Writeable Async Type') + + # test the write with high value + await rut.write(0xFFFFFFFF) + write_callback_mock.assert_called_once_with( + addr=20, + width=32, + accesswidth=rut.accesswidth, + data=0xFFFFFFFF) + write_callback_mock.reset_mock() + + # test the write of a low value + await rut.write(0) + write_callback_mock.assert_called_once_with( + addr=20, + width=32, + accesswidth=rut.accesswidth, + data=0) + write_callback_mock.reset_mock() + + # test the write of a random + random_value = random.randrange(0, 0xFFFFFFFF+1) + await rut.write(random_value) # type: ignore[union-attr] + write_callback_mock.assert_called_once_with( + addr=20, + width=32, + accesswidth=rut.accesswidth, + data=random_value) + write_callback_mock.reset_mock() + + # test writing a value beyond the register range is blocked with an exception being raised + with self.assertRaises(ValueError): + await rut.write(-1) + + with self.assertRaises(ValueError): + await rut.write(0xFFFFFFFF+1) # check the read has not been called in the write test read_callback_mock.assert_not_called() @@ -3974,9 +4008,43 @@ async def test_register_read_and_write(self) -> None: - # test that a non-writable register has no write method and attempting one generates and error - with self.assertRaises(AttributeError): - await rut.write(0) # type: ignore[attr-defined] + if not isinstance(rut, (RegAsyncWriteOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Writeable Async Type') + + # test the write with high value + await rut.write(0xFFFFFFFF) + write_callback_mock.assert_called_once_with( + addr=24, + width=32, + accesswidth=rut.accesswidth, + data=0xFFFFFFFF) + write_callback_mock.reset_mock() + + # test the write of a low value + await rut.write(0) + write_callback_mock.assert_called_once_with( + addr=24, + width=32, + accesswidth=rut.accesswidth, + data=0) + write_callback_mock.reset_mock() + + # test the write of a random + random_value = random.randrange(0, 0xFFFFFFFF+1) + await rut.write(random_value) # type: ignore[union-attr] + write_callback_mock.assert_called_once_with( + addr=24, + width=32, + accesswidth=rut.accesswidth, + data=random_value) + write_callback_mock.reset_mock() + + # test writing a value beyond the register range is blocked with an exception being raised + with self.assertRaises(ValueError): + await rut.write(-1) + + with self.assertRaises(ValueError): + await rut.write(0xFFFFFFFF+1) # check the read has not been called in the write test read_callback_mock.assert_not_called() @@ -5228,9 +5296,43 @@ async def test_register_read_and_write(self) -> None: - # test that a non-writable register has no write method and attempting one generates and error - with self.assertRaises(AttributeError): - await rut.write(0) # type: ignore[attr-defined] + if not isinstance(rut, (RegAsyncWriteOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Writeable Async Type') + + # test the write with high value + await rut.write(0xFFFFFFFF) + write_callback_mock.assert_called_once_with( + addr=80, + width=32, + accesswidth=rut.accesswidth, + data=0xFFFFFFFF) + write_callback_mock.reset_mock() + + # test the write of a low value + await rut.write(0) + write_callback_mock.assert_called_once_with( + addr=80, + width=32, + accesswidth=rut.accesswidth, + data=0) + write_callback_mock.reset_mock() + + # test the write of a random + random_value = random.randrange(0, 0xFFFFFFFF+1) + await rut.write(random_value) # type: ignore[union-attr] + write_callback_mock.assert_called_once_with( + addr=80, + width=32, + accesswidth=rut.accesswidth, + data=random_value) + write_callback_mock.reset_mock() + + # test writing a value beyond the register range is blocked with an exception being raised + with self.assertRaises(ValueError): + await rut.write(-1) + + with self.assertRaises(ValueError): + await rut.write(0xFFFFFFFF+1) # check the read has not been called in the write test read_callback_mock.assert_not_called() @@ -5286,9 +5388,43 @@ async def test_register_read_and_write(self) -> None: - # test that a non-writable register has no write method and attempting one generates and error - with self.assertRaises(AttributeError): - await rut.write(0) # type: ignore[attr-defined] + if not isinstance(rut, (RegAsyncWriteOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Writeable Async Type') + + # test the write with high value + await rut.write(0xFFFFFFFF) + write_callback_mock.assert_called_once_with( + addr=84, + width=32, + accesswidth=rut.accesswidth, + data=0xFFFFFFFF) + write_callback_mock.reset_mock() + + # test the write of a low value + await rut.write(0) + write_callback_mock.assert_called_once_with( + addr=84, + width=32, + accesswidth=rut.accesswidth, + data=0) + write_callback_mock.reset_mock() + + # test the write of a random + random_value = random.randrange(0, 0xFFFFFFFF+1) + await rut.write(random_value) # type: ignore[union-attr] + write_callback_mock.assert_called_once_with( + addr=84, + width=32, + accesswidth=rut.accesswidth, + data=random_value) + write_callback_mock.reset_mock() + + # test writing a value beyond the register range is blocked with an exception being raised + with self.assertRaises(ValueError): + await rut.write(-1) + + with self.assertRaises(ValueError): + await rut.write(0xFFFFFFFF+1) # check the read has not been called in the write test read_callback_mock.assert_not_called() @@ -5344,9 +5480,43 @@ async def test_register_read_and_write(self) -> None: - # test that a non-writable register has no write method and attempting one generates and error - with self.assertRaises(AttributeError): - await rut.write(0) # type: ignore[attr-defined] + if not isinstance(rut, (RegAsyncWriteOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Writeable Async Type') + + # test the write with high value + await rut.write(0xFFFFFFFF) + write_callback_mock.assert_called_once_with( + addr=88, + width=32, + accesswidth=rut.accesswidth, + data=0xFFFFFFFF) + write_callback_mock.reset_mock() + + # test the write of a low value + await rut.write(0) + write_callback_mock.assert_called_once_with( + addr=88, + width=32, + accesswidth=rut.accesswidth, + data=0) + write_callback_mock.reset_mock() + + # test the write of a random + random_value = random.randrange(0, 0xFFFFFFFF+1) + await rut.write(random_value) # type: ignore[union-attr] + write_callback_mock.assert_called_once_with( + addr=88, + width=32, + accesswidth=rut.accesswidth, + data=random_value) + write_callback_mock.reset_mock() + + # test writing a value beyond the register range is blocked with an exception being raised + with self.assertRaises(ValueError): + await rut.write(-1) + + with self.assertRaises(ValueError): + await rut.write(0xFFFFFFFF+1) # check the read has not been called in the write test read_callback_mock.assert_not_called() @@ -5402,9 +5572,43 @@ async def test_register_read_and_write(self) -> None: - # test that a non-writable register has no write method and attempting one generates and error - with self.assertRaises(AttributeError): - await rut.write(0) # type: ignore[attr-defined] + if not isinstance(rut, (RegAsyncWriteOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Writeable Async Type') + + # test the write with high value + await rut.write(0xFFFFFFFF) + write_callback_mock.assert_called_once_with( + addr=92, + width=32, + accesswidth=rut.accesswidth, + data=0xFFFFFFFF) + write_callback_mock.reset_mock() + + # test the write of a low value + await rut.write(0) + write_callback_mock.assert_called_once_with( + addr=92, + width=32, + accesswidth=rut.accesswidth, + data=0) + write_callback_mock.reset_mock() + + # test the write of a random + random_value = random.randrange(0, 0xFFFFFFFF+1) + await rut.write(random_value) # type: ignore[union-attr] + write_callback_mock.assert_called_once_with( + addr=92, + width=32, + accesswidth=rut.accesswidth, + data=random_value) + write_callback_mock.reset_mock() + + # test writing a value beyond the register range is blocked with an exception being raised + with self.assertRaises(ValueError): + await rut.write(-1) + + with self.assertRaises(ValueError): + await rut.write(0xFFFFFFFF+1) # check the read has not been called in the write test read_callback_mock.assert_not_called() @@ -5460,19 +5664,53 @@ async def test_register_read_and_write(self) -> None: - # test that a non-writable register has no write method and attempting one generates and error - with self.assertRaises(AttributeError): - await rut.write(0) # type: ignore[attr-defined] - - # check the read has not been called in the write test - read_callback_mock.assert_not_called() - # test access operations (read and/or write) to register: - # msk_top_regs.Rx_Sample_Discard - with self.subTest(msg='register: msk_top_regs.Rx_Sample_Discard'): - rut=self.dut.Rx_Sample_Discard # type: ignore[union-attr,assignment] - with patch(base_name + '.write_addr_space') as write_callback_mock, \ - patch(base_name + '.read_addr_space', return_value=1) as read_callback_mock: - + if not isinstance(rut, (RegAsyncWriteOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Writeable Async Type') + + # test the write with high value + await rut.write(0xFFFFFFFF) + write_callback_mock.assert_called_once_with( + addr=96, + width=32, + accesswidth=rut.accesswidth, + data=0xFFFFFFFF) + write_callback_mock.reset_mock() + + # test the write of a low value + await rut.write(0) + write_callback_mock.assert_called_once_with( + addr=96, + width=32, + accesswidth=rut.accesswidth, + data=0) + write_callback_mock.reset_mock() + + # test the write of a random + random_value = random.randrange(0, 0xFFFFFFFF+1) + await rut.write(random_value) # type: ignore[union-attr] + write_callback_mock.assert_called_once_with( + addr=96, + width=32, + accesswidth=rut.accesswidth, + data=random_value) + write_callback_mock.reset_mock() + + # test writing a value beyond the register range is blocked with an exception being raised + with self.assertRaises(ValueError): + await rut.write(-1) + + with self.assertRaises(ValueError): + await rut.write(0xFFFFFFFF+1) + + # check the read has not been called in the write test + read_callback_mock.assert_not_called() + # test access operations (read and/or write) to register: + # msk_top_regs.Rx_Sample_Discard + with self.subTest(msg='register: msk_top_regs.Rx_Sample_Discard'): + rut=self.dut.Rx_Sample_Discard # type: ignore[union-attr,assignment] + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=1) as read_callback_mock: + if not isinstance(rut, (RegAsyncReadOnly, RegAsyncReadWrite)): raise TypeError('Register is not a Readable Async Type') @@ -5702,9 +5940,43 @@ async def test_register_read_and_write(self) -> None: - # test that a non-writable register has no write method and attempting one generates and error - with self.assertRaises(AttributeError): - await rut.write(0) # type: ignore[attr-defined] + if not isinstance(rut, (RegAsyncWriteOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Writeable Async Type') + + # test the write with high value + await rut.write(0xFFFFFFFF) + write_callback_mock.assert_called_once_with( + addr=108, + width=32, + accesswidth=rut.accesswidth, + data=0xFFFFFFFF) + write_callback_mock.reset_mock() + + # test the write of a low value + await rut.write(0) + write_callback_mock.assert_called_once_with( + addr=108, + width=32, + accesswidth=rut.accesswidth, + data=0) + write_callback_mock.reset_mock() + + # test the write of a random + random_value = random.randrange(0, 0xFFFFFFFF+1) + await rut.write(random_value) # type: ignore[union-attr] + write_callback_mock.assert_called_once_with( + addr=108, + width=32, + accesswidth=rut.accesswidth, + data=random_value) + write_callback_mock.reset_mock() + + # test writing a value beyond the register range is blocked with an exception being raised + with self.assertRaises(ValueError): + await rut.write(-1) + + with self.assertRaises(ValueError): + await rut.write(0xFFFFFFFF+1) # check the read has not been called in the write test read_callback_mock.assert_not_called() @@ -5760,9 +6032,43 @@ async def test_register_read_and_write(self) -> None: - # test that a non-writable register has no write method and attempting one generates and error - with self.assertRaises(AttributeError): - await rut.write(0) # type: ignore[attr-defined] + if not isinstance(rut, (RegAsyncWriteOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Writeable Async Type') + + # test the write with high value + await rut.write(0xFFFFFFFF) + write_callback_mock.assert_called_once_with( + addr=112, + width=32, + accesswidth=rut.accesswidth, + data=0xFFFFFFFF) + write_callback_mock.reset_mock() + + # test the write of a low value + await rut.write(0) + write_callback_mock.assert_called_once_with( + addr=112, + width=32, + accesswidth=rut.accesswidth, + data=0) + write_callback_mock.reset_mock() + + # test the write of a random + random_value = random.randrange(0, 0xFFFFFFFF+1) + await rut.write(random_value) # type: ignore[union-attr] + write_callback_mock.assert_called_once_with( + addr=112, + width=32, + accesswidth=rut.accesswidth, + data=random_value) + write_callback_mock.reset_mock() + + # test writing a value beyond the register range is blocked with an exception being raised + with self.assertRaises(ValueError): + await rut.write(-1) + + with self.assertRaises(ValueError): + await rut.write(0xFFFFFFFF+1) # check the read has not been called in the write test read_callback_mock.assert_not_called() @@ -5818,9 +6124,43 @@ async def test_register_read_and_write(self) -> None: - # test that a non-writable register has no write method and attempting one generates and error - with self.assertRaises(AttributeError): - await rut.write(0) # type: ignore[attr-defined] + if not isinstance(rut, (RegAsyncWriteOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Writeable Async Type') + + # test the write with high value + await rut.write(0xFFFFFFFF) + write_callback_mock.assert_called_once_with( + addr=116, + width=32, + accesswidth=rut.accesswidth, + data=0xFFFFFFFF) + write_callback_mock.reset_mock() + + # test the write of a low value + await rut.write(0) + write_callback_mock.assert_called_once_with( + addr=116, + width=32, + accesswidth=rut.accesswidth, + data=0) + write_callback_mock.reset_mock() + + # test the write of a random + random_value = random.randrange(0, 0xFFFFFFFF+1) + await rut.write(random_value) # type: ignore[union-attr] + write_callback_mock.assert_called_once_with( + addr=116, + width=32, + accesswidth=rut.accesswidth, + data=random_value) + write_callback_mock.reset_mock() + + # test writing a value beyond the register range is blocked with an exception being raised + with self.assertRaises(ValueError): + await rut.write(-1) + + with self.assertRaises(ValueError): + await rut.write(0xFFFFFFFF+1) # check the read has not been called in the write test read_callback_mock.assert_not_called() @@ -5876,9 +6216,43 @@ async def test_register_read_and_write(self) -> None: - # test that a non-writable register has no write method and attempting one generates and error - with self.assertRaises(AttributeError): - await rut.write(0) # type: ignore[attr-defined] + if not isinstance(rut, (RegAsyncWriteOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Writeable Async Type') + + # test the write with high value + await rut.write(0xFFFFFFFF) + write_callback_mock.assert_called_once_with( + addr=120, + width=32, + accesswidth=rut.accesswidth, + data=0xFFFFFFFF) + write_callback_mock.reset_mock() + + # test the write of a low value + await rut.write(0) + write_callback_mock.assert_called_once_with( + addr=120, + width=32, + accesswidth=rut.accesswidth, + data=0) + write_callback_mock.reset_mock() + + # test the write of a random + random_value = random.randrange(0, 0xFFFFFFFF+1) + await rut.write(random_value) # type: ignore[union-attr] + write_callback_mock.assert_called_once_with( + addr=120, + width=32, + accesswidth=rut.accesswidth, + data=random_value) + write_callback_mock.reset_mock() + + # test writing a value beyond the register range is blocked with an exception being raised + with self.assertRaises(ValueError): + await rut.write(-1) + + with self.assertRaises(ValueError): + await rut.write(0xFFFFFFFF+1) # check the read has not been called in the write test read_callback_mock.assert_not_called() @@ -6302,9 +6676,43 @@ async def test_register_read_and_write(self) -> None: - # test that a non-writable register has no write method and attempting one generates and error - with self.assertRaises(AttributeError): - await rut.write(0) # type: ignore[attr-defined] + if not isinstance(rut, (RegAsyncWriteOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Writeable Async Type') + + # test the write with high value + await rut.write(0xFFFFFFFF) + write_callback_mock.assert_called_once_with( + addr=140, + width=32, + accesswidth=rut.accesswidth, + data=0xFFFFFFFF) + write_callback_mock.reset_mock() + + # test the write of a low value + await rut.write(0) + write_callback_mock.assert_called_once_with( + addr=140, + width=32, + accesswidth=rut.accesswidth, + data=0) + write_callback_mock.reset_mock() + + # test the write of a random + random_value = random.randrange(0, 0xFFFFFFFF+1) + await rut.write(random_value) # type: ignore[union-attr] + write_callback_mock.assert_called_once_with( + addr=140, + width=32, + accesswidth=rut.accesswidth, + data=random_value) + write_callback_mock.reset_mock() + + # test writing a value beyond the register range is blocked with an exception being raised + with self.assertRaises(ValueError): + await rut.write(-1) + + with self.assertRaises(ValueError): + await rut.write(0xFFFFFFFF+1) # check the read has not been called in the write test read_callback_mock.assert_not_called() @@ -6352,17 +6760,51 @@ async def test_register_read_and_write(self) -> None: read_callback_mock.assert_called_once_with( addr=144, width=32, - accesswidth=rut.accesswidth) + accesswidth=rut.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + + + if not isinstance(rut, (RegAsyncWriteOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Writeable Async Type') + + # test the write with high value + await rut.write(0xFFFFFFFF) + write_callback_mock.assert_called_once_with( + addr=144, + width=32, + accesswidth=rut.accesswidth, + data=0xFFFFFFFF) + write_callback_mock.reset_mock() + + # test the write of a low value + await rut.write(0) + write_callback_mock.assert_called_once_with( + addr=144, + width=32, + accesswidth=rut.accesswidth, + data=0) + write_callback_mock.reset_mock() + + # test the write of a random + random_value = random.randrange(0, 0xFFFFFFFF+1) + await rut.write(random_value) # type: ignore[union-attr] + write_callback_mock.assert_called_once_with( + addr=144, + width=32, + accesswidth=rut.accesswidth, + data=random_value) + write_callback_mock.reset_mock() - # at the end of the read tests the write should not have been called - read_callback_mock.reset_mock() - write_callback_mock.assert_not_called() - + # test writing a value beyond the register range is blocked with an exception being raised + with self.assertRaises(ValueError): + await rut.write(-1) - - # test that a non-writable register has no write method and attempting one generates and error - with self.assertRaises(AttributeError): - await rut.write(0) # type: ignore[attr-defined] + with self.assertRaises(ValueError): + await rut.write(0xFFFFFFFF+1) # check the read has not been called in the write test read_callback_mock.assert_not_called() @@ -6418,9 +6860,43 @@ async def test_register_read_and_write(self) -> None: - # test that a non-writable register has no write method and attempting one generates and error - with self.assertRaises(AttributeError): - await rut.write(0) # type: ignore[attr-defined] + if not isinstance(rut, (RegAsyncWriteOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Writeable Async Type') + + # test the write with high value + await rut.write(0xFFFFFFFF) + write_callback_mock.assert_called_once_with( + addr=148, + width=32, + accesswidth=rut.accesswidth, + data=0xFFFFFFFF) + write_callback_mock.reset_mock() + + # test the write of a low value + await rut.write(0) + write_callback_mock.assert_called_once_with( + addr=148, + width=32, + accesswidth=rut.accesswidth, + data=0) + write_callback_mock.reset_mock() + + # test the write of a random + random_value = random.randrange(0, 0xFFFFFFFF+1) + await rut.write(random_value) # type: ignore[union-attr] + write_callback_mock.assert_called_once_with( + addr=148, + width=32, + accesswidth=rut.accesswidth, + data=random_value) + write_callback_mock.reset_mock() + + # test writing a value beyond the register range is blocked with an exception being raised + with self.assertRaises(ValueError): + await rut.write(-1) + + with self.assertRaises(ValueError): + await rut.write(0xFFFFFFFF+1) # check the read has not been called in the write test read_callback_mock.assert_not_called() @@ -7394,9 +7870,9 @@ async def test_int_field_read_and_write(self) -> None: write_callback_mock.assert_not_called() # test access operations (read and/or write) to field: - # msk_top_regs.Tx_Bit_Count.tx_bit_counter - with self.subTest(msg='field: msk_top_regs.Tx_Bit_Count.tx_bit_counter'): - fut = self.dut.Tx_Bit_Count.tx_bit_counter # type: ignore[union-attr] + # msk_top_regs.Tx_Bit_Count.data + with self.subTest(msg='field: msk_top_regs.Tx_Bit_Count.data'): + fut = self.dut.Tx_Bit_Count.data # type: ignore[union-attr] with patch(base_name + '.write_addr_space') as write_callback_mock,\ patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: @@ -7440,11 +7916,43 @@ async def test_int_field_read_and_write(self) -> None: # at the end of the read tests the write should not have been called read_callback_mock.reset_mock() write_callback_mock.assert_not_called() + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0xFFFFFFFF + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0xFFFFFFFF, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.Tx_Bit_Count.data.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_not_called() + write_callback_mock.assert_called_once_with( + addr=20, + width=32, + accesswidth=self.dut.Tx_Bit_Count.data.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0x0) | \ + (0xFFFFFFFF & (field_value << 0))) + + + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0xFFFFFFFF + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) # test access operations (read and/or write) to field: - # msk_top_regs.Tx_Enable_Count.tx_ena_counter - with self.subTest(msg='field: msk_top_regs.Tx_Enable_Count.tx_ena_counter'): - fut = self.dut.Tx_Enable_Count.tx_ena_counter # type: ignore[union-attr] + # msk_top_regs.Tx_Enable_Count.data + with self.subTest(msg='field: msk_top_regs.Tx_Enable_Count.data'): + fut = self.dut.Tx_Enable_Count.data # type: ignore[union-attr] with patch(base_name + '.write_addr_space') as write_callback_mock,\ patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: @@ -7488,6 +7996,38 @@ async def test_int_field_read_and_write(self) -> None: # at the end of the read tests the write should not have been called read_callback_mock.reset_mock() write_callback_mock.assert_not_called() + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0xFFFFFFFF + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0xFFFFFFFF, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.Tx_Enable_Count.data.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_not_called() + write_callback_mock.assert_called_once_with( + addr=24, + width=32, + accesswidth=self.dut.Tx_Enable_Count.data.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0x0) | \ + (0xFFFFFFFF & (field_value << 0))) + + + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0xFFFFFFFF + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) # test access operations (read and/or write) to field: # msk_top_regs.Fb_FreqWord.config_data @@ -9189,9 +9729,9 @@ async def test_int_field_read_and_write(self) -> None: await fut.write(-1) # test access operations (read and/or write) to field: - # msk_top_regs.PRBS_Bit_Count.status_data - with self.subTest(msg='field: msk_top_regs.PRBS_Bit_Count.status_data'): - fut = self.dut.PRBS_Bit_Count.status_data # type: ignore[union-attr] + # msk_top_regs.PRBS_Bit_Count.data + with self.subTest(msg='field: msk_top_regs.PRBS_Bit_Count.data'): + fut = self.dut.PRBS_Bit_Count.data # type: ignore[union-attr] with patch(base_name + '.write_addr_space') as write_callback_mock,\ patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: @@ -9235,11 +9775,43 @@ async def test_int_field_read_and_write(self) -> None: # at the end of the read tests the write should not have been called read_callback_mock.reset_mock() write_callback_mock.assert_not_called() + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0xFFFFFFFF + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0xFFFFFFFF, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.PRBS_Bit_Count.data.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_not_called() + write_callback_mock.assert_called_once_with( + addr=80, + width=32, + accesswidth=self.dut.PRBS_Bit_Count.data.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0x0) | \ + (0xFFFFFFFF & (field_value << 0))) + + + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0xFFFFFFFF + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) # test access operations (read and/or write) to field: - # msk_top_regs.PRBS_Error_Count.status_data - with self.subTest(msg='field: msk_top_regs.PRBS_Error_Count.status_data'): - fut = self.dut.PRBS_Error_Count.status_data # type: ignore[union-attr] + # msk_top_regs.PRBS_Error_Count.data + with self.subTest(msg='field: msk_top_regs.PRBS_Error_Count.data'): + fut = self.dut.PRBS_Error_Count.data # type: ignore[union-attr] with patch(base_name + '.write_addr_space') as write_callback_mock,\ patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: @@ -9283,11 +9855,43 @@ async def test_int_field_read_and_write(self) -> None: # at the end of the read tests the write should not have been called read_callback_mock.reset_mock() write_callback_mock.assert_not_called() + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0xFFFFFFFF + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0xFFFFFFFF, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.PRBS_Error_Count.data.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_not_called() + write_callback_mock.assert_called_once_with( + addr=84, + width=32, + accesswidth=self.dut.PRBS_Error_Count.data.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0x0) | \ + (0xFFFFFFFF & (field_value << 0))) + + + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0xFFFFFFFF + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) # test access operations (read and/or write) to field: - # msk_top_regs.LPF_Accum_F1.status_data - with self.subTest(msg='field: msk_top_regs.LPF_Accum_F1.status_data'): - fut = self.dut.LPF_Accum_F1.status_data # type: ignore[union-attr] + # msk_top_regs.LPF_Accum_F1.data + with self.subTest(msg='field: msk_top_regs.LPF_Accum_F1.data'): + fut = self.dut.LPF_Accum_F1.data # type: ignore[union-attr] with patch(base_name + '.write_addr_space') as write_callback_mock,\ patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: @@ -9331,11 +9935,43 @@ async def test_int_field_read_and_write(self) -> None: # at the end of the read tests the write should not have been called read_callback_mock.reset_mock() write_callback_mock.assert_not_called() + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0xFFFFFFFF + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0xFFFFFFFF, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.LPF_Accum_F1.data.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_not_called() + write_callback_mock.assert_called_once_with( + addr=88, + width=32, + accesswidth=self.dut.LPF_Accum_F1.data.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0x0) | \ + (0xFFFFFFFF & (field_value << 0))) + + + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0xFFFFFFFF + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) # test access operations (read and/or write) to field: - # msk_top_regs.LPF_Accum_F2.status_data - with self.subTest(msg='field: msk_top_regs.LPF_Accum_F2.status_data'): - fut = self.dut.LPF_Accum_F2.status_data # type: ignore[union-attr] + # msk_top_regs.LPF_Accum_F2.data + with self.subTest(msg='field: msk_top_regs.LPF_Accum_F2.data'): + fut = self.dut.LPF_Accum_F2.data # type: ignore[union-attr] with patch(base_name + '.write_addr_space') as write_callback_mock,\ patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: @@ -9379,11 +10015,43 @@ async def test_int_field_read_and_write(self) -> None: # at the end of the read tests the write should not have been called read_callback_mock.reset_mock() write_callback_mock.assert_not_called() + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0xFFFFFFFF + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0xFFFFFFFF, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.LPF_Accum_F2.data.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_not_called() + write_callback_mock.assert_called_once_with( + addr=92, + width=32, + accesswidth=self.dut.LPF_Accum_F2.data.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0x0) | \ + (0xFFFFFFFF & (field_value << 0))) + + + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0xFFFFFFFF + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) # test access operations (read and/or write) to field: - # msk_top_regs.axis_xfer_count.xfer_count - with self.subTest(msg='field: msk_top_regs.axis_xfer_count.xfer_count'): - fut = self.dut.axis_xfer_count.xfer_count # type: ignore[union-attr] + # msk_top_regs.axis_xfer_count.data + with self.subTest(msg='field: msk_top_regs.axis_xfer_count.data'): + fut = self.dut.axis_xfer_count.data # type: ignore[union-attr] with patch(base_name + '.write_addr_space') as write_callback_mock,\ patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: @@ -9422,11 +10090,43 @@ async def test_int_field_read_and_write(self) -> None: read_callback_mock.assert_called_once_with( addr=96, width=32, - accesswidth=fut.parent_register.accesswidth) + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0xFFFFFFFF + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0xFFFFFFFF, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.axis_xfer_count.data.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_not_called() + write_callback_mock.assert_called_once_with( + addr=96, + width=32, + accesswidth=self.dut.axis_xfer_count.data.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0x0) | \ + (0xFFFFFFFF & (field_value << 0))) + - # at the end of the read tests the write should not have been called - read_callback_mock.reset_mock() - write_callback_mock.assert_not_called() + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0xFFFFFFFF + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) # test access operations (read and/or write) to field: # msk_top_regs.Rx_Sample_Discard.rx_sample_discard @@ -9811,6 +10511,38 @@ async def test_int_field_read_and_write(self) -> None: # at the end of the read tests the write should not have been called read_callback_mock.reset_mock() write_callback_mock.assert_not_called() + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0xFFFFFFFF + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0xFFFFFFFF, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.f1_nco_adjust.data.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_not_called() + write_callback_mock.assert_called_once_with( + addr=108, + width=32, + accesswidth=self.dut.f1_nco_adjust.data.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0x0) | \ + (0xFFFFFFFF & (field_value << 0))) + + + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0xFFFFFFFF + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) # test access operations (read and/or write) to field: # msk_top_regs.f2_nco_adjust.data @@ -9859,6 +10591,38 @@ async def test_int_field_read_and_write(self) -> None: # at the end of the read tests the write should not have been called read_callback_mock.reset_mock() write_callback_mock.assert_not_called() + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0xFFFFFFFF + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0xFFFFFFFF, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.f2_nco_adjust.data.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_not_called() + write_callback_mock.assert_called_once_with( + addr=112, + width=32, + accesswidth=self.dut.f2_nco_adjust.data.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0x0) | \ + (0xFFFFFFFF & (field_value << 0))) + + + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0xFFFFFFFF + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) # test access operations (read and/or write) to field: # msk_top_regs.f1_error.data @@ -9907,6 +10671,38 @@ async def test_int_field_read_and_write(self) -> None: # at the end of the read tests the write should not have been called read_callback_mock.reset_mock() write_callback_mock.assert_not_called() + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0xFFFFFFFF + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0xFFFFFFFF, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.f1_error.data.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_not_called() + write_callback_mock.assert_called_once_with( + addr=116, + width=32, + accesswidth=self.dut.f1_error.data.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0x0) | \ + (0xFFFFFFFF & (field_value << 0))) + + + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0xFFFFFFFF + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) # test access operations (read and/or write) to field: # msk_top_regs.f2_error.data @@ -9955,6 +10751,38 @@ async def test_int_field_read_and_write(self) -> None: # at the end of the read tests the write should not have been called read_callback_mock.reset_mock() write_callback_mock.assert_not_called() + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0xFFFFFFFF + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0xFFFFFFFF, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.f2_error.data.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_not_called() + write_callback_mock.assert_called_once_with( + addr=120, + width=32, + accesswidth=self.dut.f2_error.data.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0x0) | \ + (0xFFFFFFFF & (field_value << 0))) + + + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0xFFFFFFFF + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) # test access operations (read and/or write) to field: # msk_top_regs.Tx_Sync_Ctrl.tx_sync_ena @@ -10545,9 +11373,9 @@ async def test_int_field_read_and_write(self) -> None: await fut.write(-1) # test access operations (read and/or write) to field: - # msk_top_regs.rx_power.rx_power - with self.subTest(msg='field: msk_top_regs.rx_power.rx_power'): - fut = self.dut.rx_power.rx_power # type: ignore[union-attr] + # msk_top_regs.rx_power.data + with self.subTest(msg='field: msk_top_regs.rx_power.data'): + fut = self.dut.rx_power.data # type: ignore[union-attr] with patch(base_name + '.write_addr_space') as write_callback_mock,\ patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: @@ -10591,6 +11419,42 @@ async def test_int_field_read_and_write(self) -> None: # at the end of the read tests the write should not have been called read_callback_mock.reset_mock() write_callback_mock.assert_not_called() + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0x7FFFFF + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0x7FFFFF, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.rx_power.data.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_called_once_with( + addr=140, + width=32, + accesswidth=fut.parent_register.accesswidth) + + write_callback_mock.assert_called_once_with( + addr=140, + width=32, + accesswidth=self.dut.rx_power.data.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0xFF800000) | \ + (0x7FFFFF & (field_value << 0))) + + + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0x7FFFFF + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) # test access operations (read and/or write) to field: # msk_top_regs.tx_async_fifo_rd_wr_ptr.data @@ -10639,6 +11503,38 @@ async def test_int_field_read_and_write(self) -> None: # at the end of the read tests the write should not have been called read_callback_mock.reset_mock() write_callback_mock.assert_not_called() + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0xFFFFFFFF + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0xFFFFFFFF, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.tx_async_fifo_rd_wr_ptr.data.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_not_called() + write_callback_mock.assert_called_once_with( + addr=144, + width=32, + accesswidth=self.dut.tx_async_fifo_rd_wr_ptr.data.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0x0) | \ + (0xFFFFFFFF & (field_value << 0))) + + + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0xFFFFFFFF + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) # test access operations (read and/or write) to field: # msk_top_regs.rx_async_fifo_rd_wr_ptr.data @@ -10687,6 +11583,38 @@ async def test_int_field_read_and_write(self) -> None: # at the end of the read tests the write should not have been called read_callback_mock.reset_mock() write_callback_mock.assert_not_called() + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0xFFFFFFFF + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0xFFFFFFFF, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.rx_async_fifo_rd_wr_ptr.data.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_not_called() + write_callback_mock.assert_called_once_with( + addr=148, + width=32, + accesswidth=self.dut.rx_async_fifo_rd_wr_ptr.data.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0x0) | \ + (0xFFFFFFFF & (field_value << 0))) + + + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0xFFFFFFFF + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) @@ -10987,7 +11915,7 @@ async def test_register_read_fields(self) -> None: # from the object with all the read back field # values reference_read_fields = { - 'tx_bit_counter' : await self.dut.Tx_Bit_Count.tx_bit_counter.read() + 'data' : await self.dut.Tx_Bit_Count.data.read() } read_callback_mock.reset_mock() @@ -11019,7 +11947,7 @@ async def test_register_read_fields(self) -> None: # from the object with all the read back field # values reference_read_fields = { - 'tx_ena_counter' : await self.dut.Tx_Enable_Count.tx_ena_counter.read() + 'data' : await self.dut.Tx_Enable_Count.data.read() } read_callback_mock.reset_mock() @@ -11551,7 +12479,7 @@ async def test_register_read_fields(self) -> None: # from the object with all the read back field # values reference_read_fields = { - 'status_data' : await self.dut.PRBS_Bit_Count.status_data.read() + 'data' : await self.dut.PRBS_Bit_Count.data.read() } read_callback_mock.reset_mock() @@ -11583,7 +12511,7 @@ async def test_register_read_fields(self) -> None: # from the object with all the read back field # values reference_read_fields = { - 'status_data' : await self.dut.PRBS_Error_Count.status_data.read() + 'data' : await self.dut.PRBS_Error_Count.data.read() } read_callback_mock.reset_mock() @@ -11615,7 +12543,7 @@ async def test_register_read_fields(self) -> None: # from the object with all the read back field # values reference_read_fields = { - 'status_data' : await self.dut.LPF_Accum_F1.status_data.read() + 'data' : await self.dut.LPF_Accum_F1.data.read() } read_callback_mock.reset_mock() @@ -11647,7 +12575,7 @@ async def test_register_read_fields(self) -> None: # from the object with all the read back field # values reference_read_fields = { - 'status_data' : await self.dut.LPF_Accum_F2.status_data.read() + 'data' : await self.dut.LPF_Accum_F2.data.read() } read_callback_mock.reset_mock() @@ -11679,7 +12607,7 @@ async def test_register_read_fields(self) -> None: # from the object with all the read back field # values reference_read_fields = { - 'xfer_count' : await self.dut.axis_xfer_count.xfer_count.read() + 'data' : await self.dut.axis_xfer_count.data.read() } read_callback_mock.reset_mock() @@ -12091,7 +13019,7 @@ async def test_register_read_fields(self) -> None: # from the object with all the read back field # values reference_read_fields = { - 'rx_power' : await self.dut.rx_power.rx_power.read() + 'data' : await self.dut.rx_power.data.read() } read_callback_mock.reset_mock() @@ -12511,14 +13439,15 @@ async def test_register_read_context_manager(self) -> None: # first read the fields using the "normal" method, then compare the result to reading # via the context manager reference_read_fields = { - 'tx_bit_counter' : await self.dut.Tx_Bit_Count.tx_bit_counter.read() # type: ignore[union-attr] + 'data' : await self.dut.Tx_Bit_Count.data.read() # type: ignore[union-attr] } read_callback_mock.reset_mock() - async with self.dut.Tx_Bit_Count.single_read() as reg_context: # type: ignore[union-attr] - self.assertEqual(reference_read_fields['tx_bit_counter'], - await reg_context.get_child_by_system_rdl_name('tx_bit_counter').read() + async with self.dut.Tx_Bit_Count.single_read_modify_write(skip_write=True) as reg_context: # type: ignore[union-attr] + + self.assertEqual(reference_read_fields['data'], + await reg_context.get_child_by_system_rdl_name('data').read() ) pass @@ -12547,14 +13476,15 @@ async def test_register_read_context_manager(self) -> None: # first read the fields using the "normal" method, then compare the result to reading # via the context manager reference_read_fields = { - 'tx_ena_counter' : await self.dut.Tx_Enable_Count.tx_ena_counter.read() # type: ignore[union-attr] + 'data' : await self.dut.Tx_Enable_Count.data.read() # type: ignore[union-attr] } read_callback_mock.reset_mock() - async with self.dut.Tx_Enable_Count.single_read() as reg_context: # type: ignore[union-attr] - self.assertEqual(reference_read_fields['tx_ena_counter'], - await reg_context.get_child_by_system_rdl_name('tx_ena_counter').read() + async with self.dut.Tx_Enable_Count.single_read_modify_write(skip_write=True) as reg_context: # type: ignore[union-attr] + + self.assertEqual(reference_read_fields['data'], + await reg_context.get_child_by_system_rdl_name('data').read() ) pass @@ -13166,14 +14096,15 @@ async def test_register_read_context_manager(self) -> None: # first read the fields using the "normal" method, then compare the result to reading # via the context manager reference_read_fields = { - 'status_data' : await self.dut.PRBS_Bit_Count.status_data.read() # type: ignore[union-attr] + 'data' : await self.dut.PRBS_Bit_Count.data.read() # type: ignore[union-attr] } read_callback_mock.reset_mock() - async with self.dut.PRBS_Bit_Count.single_read() as reg_context: # type: ignore[union-attr] - self.assertEqual(reference_read_fields['status_data'], - await reg_context.get_child_by_system_rdl_name('status_data').read() + async with self.dut.PRBS_Bit_Count.single_read_modify_write(skip_write=True) as reg_context: # type: ignore[union-attr] + + self.assertEqual(reference_read_fields['data'], + await reg_context.get_child_by_system_rdl_name('data').read() ) pass @@ -13202,14 +14133,15 @@ async def test_register_read_context_manager(self) -> None: # first read the fields using the "normal" method, then compare the result to reading # via the context manager reference_read_fields = { - 'status_data' : await self.dut.PRBS_Error_Count.status_data.read() # type: ignore[union-attr] + 'data' : await self.dut.PRBS_Error_Count.data.read() # type: ignore[union-attr] } read_callback_mock.reset_mock() - async with self.dut.PRBS_Error_Count.single_read() as reg_context: # type: ignore[union-attr] - self.assertEqual(reference_read_fields['status_data'], - await reg_context.get_child_by_system_rdl_name('status_data').read() + async with self.dut.PRBS_Error_Count.single_read_modify_write(skip_write=True) as reg_context: # type: ignore[union-attr] + + self.assertEqual(reference_read_fields['data'], + await reg_context.get_child_by_system_rdl_name('data').read() ) pass @@ -13238,14 +14170,15 @@ async def test_register_read_context_manager(self) -> None: # first read the fields using the "normal" method, then compare the result to reading # via the context manager reference_read_fields = { - 'status_data' : await self.dut.LPF_Accum_F1.status_data.read() # type: ignore[union-attr] + 'data' : await self.dut.LPF_Accum_F1.data.read() # type: ignore[union-attr] } read_callback_mock.reset_mock() - async with self.dut.LPF_Accum_F1.single_read() as reg_context: # type: ignore[union-attr] - self.assertEqual(reference_read_fields['status_data'], - await reg_context.get_child_by_system_rdl_name('status_data').read() + async with self.dut.LPF_Accum_F1.single_read_modify_write(skip_write=True) as reg_context: # type: ignore[union-attr] + + self.assertEqual(reference_read_fields['data'], + await reg_context.get_child_by_system_rdl_name('data').read() ) pass @@ -13274,14 +14207,15 @@ async def test_register_read_context_manager(self) -> None: # first read the fields using the "normal" method, then compare the result to reading # via the context manager reference_read_fields = { - 'status_data' : await self.dut.LPF_Accum_F2.status_data.read() # type: ignore[union-attr] + 'data' : await self.dut.LPF_Accum_F2.data.read() # type: ignore[union-attr] } read_callback_mock.reset_mock() - async with self.dut.LPF_Accum_F2.single_read() as reg_context: # type: ignore[union-attr] - self.assertEqual(reference_read_fields['status_data'], - await reg_context.get_child_by_system_rdl_name('status_data').read() + async with self.dut.LPF_Accum_F2.single_read_modify_write(skip_write=True) as reg_context: # type: ignore[union-attr] + + self.assertEqual(reference_read_fields['data'], + await reg_context.get_child_by_system_rdl_name('data').read() ) pass @@ -13310,14 +14244,15 @@ async def test_register_read_context_manager(self) -> None: # first read the fields using the "normal" method, then compare the result to reading # via the context manager reference_read_fields = { - 'xfer_count' : await self.dut.axis_xfer_count.xfer_count.read() # type: ignore[union-attr] + 'data' : await self.dut.axis_xfer_count.data.read() # type: ignore[union-attr] } read_callback_mock.reset_mock() - async with self.dut.axis_xfer_count.single_read() as reg_context: # type: ignore[union-attr] - self.assertEqual(reference_read_fields['xfer_count'], - await reg_context.get_child_by_system_rdl_name('xfer_count').read() + async with self.dut.axis_xfer_count.single_read_modify_write(skip_write=True) as reg_context: # type: ignore[union-attr] + + self.assertEqual(reference_read_fields['data'], + await reg_context.get_child_by_system_rdl_name('data').read() ) pass @@ -13455,7 +14390,8 @@ async def test_register_read_context_manager(self) -> None: read_callback_mock.reset_mock() - async with self.dut.f1_nco_adjust.single_read() as reg_context: # type: ignore[union-attr] + async with self.dut.f1_nco_adjust.single_read_modify_write(skip_write=True) as reg_context: # type: ignore[union-attr] + self.assertEqual(reference_read_fields['data'], await reg_context.get_child_by_system_rdl_name('data').read() ) @@ -13491,7 +14427,8 @@ async def test_register_read_context_manager(self) -> None: read_callback_mock.reset_mock() - async with self.dut.f2_nco_adjust.single_read() as reg_context: # type: ignore[union-attr] + async with self.dut.f2_nco_adjust.single_read_modify_write(skip_write=True) as reg_context: # type: ignore[union-attr] + self.assertEqual(reference_read_fields['data'], await reg_context.get_child_by_system_rdl_name('data').read() ) @@ -13527,7 +14464,8 @@ async def test_register_read_context_manager(self) -> None: read_callback_mock.reset_mock() - async with self.dut.f1_error.single_read() as reg_context: # type: ignore[union-attr] + async with self.dut.f1_error.single_read_modify_write(skip_write=True) as reg_context: # type: ignore[union-attr] + self.assertEqual(reference_read_fields['data'], await reg_context.get_child_by_system_rdl_name('data').read() ) @@ -13563,7 +14501,8 @@ async def test_register_read_context_manager(self) -> None: read_callback_mock.reset_mock() - async with self.dut.f2_error.single_read() as reg_context: # type: ignore[union-attr] + async with self.dut.f2_error.single_read_modify_write(skip_write=True) as reg_context: # type: ignore[union-attr] + self.assertEqual(reference_read_fields['data'], await reg_context.get_child_by_system_rdl_name('data').read() ) @@ -13787,14 +14726,15 @@ async def test_register_read_context_manager(self) -> None: # first read the fields using the "normal" method, then compare the result to reading # via the context manager reference_read_fields = { - 'rx_power' : await self.dut.rx_power.rx_power.read() # type: ignore[union-attr] + 'data' : await self.dut.rx_power.data.read() # type: ignore[union-attr] } read_callback_mock.reset_mock() - async with self.dut.rx_power.single_read() as reg_context: # type: ignore[union-attr] - self.assertEqual(reference_read_fields['rx_power'], - await reg_context.get_child_by_system_rdl_name('rx_power').read() + async with self.dut.rx_power.single_read_modify_write(skip_write=True) as reg_context: # type: ignore[union-attr] + + self.assertEqual(reference_read_fields['data'], + await reg_context.get_child_by_system_rdl_name('data').read() ) pass @@ -13828,7 +14768,8 @@ async def test_register_read_context_manager(self) -> None: read_callback_mock.reset_mock() - async with self.dut.tx_async_fifo_rd_wr_ptr.single_read() as reg_context: # type: ignore[union-attr] + async with self.dut.tx_async_fifo_rd_wr_ptr.single_read_modify_write(skip_write=True) as reg_context: # type: ignore[union-attr] + self.assertEqual(reference_read_fields['data'], await reg_context.get_child_by_system_rdl_name('data').read() ) @@ -13864,7 +14805,8 @@ async def test_register_read_context_manager(self) -> None: read_callback_mock.reset_mock() - async with self.dut.rx_async_fifo_rd_wr_ptr.single_read() as reg_context: # type: ignore[union-attr] + async with self.dut.rx_async_fifo_rd_wr_ptr.single_read_modify_write(skip_write=True) as reg_context: # type: ignore[union-attr] + self.assertEqual(reference_read_fields['data'], await reg_context.get_child_by_system_rdl_name('data').read() ) @@ -13965,6 +14907,14 @@ async def write_field_combinations(reg: RegAsyncReadWrite, writable_fields:list[ 'clear_counts', 'diff_encoder_loopback' ]) + with self.subTest(msg='register: msk_top_regs.Tx_Bit_Count'): + await write_field_combinations(reg=self.dut.Tx_Bit_Count, + writable_fields = [ 'data' + ]) + with self.subTest(msg='register: msk_top_regs.Tx_Enable_Count'): + await write_field_combinations(reg=self.dut.Tx_Enable_Count, + writable_fields = [ 'data' + ]) with self.subTest(msg='register: msk_top_regs.Fb_FreqWord'): await write_field_combinations(reg=self.dut.Fb_FreqWord, writable_fields = [ 'config_data' @@ -14026,6 +14976,26 @@ async def write_field_combinations(reg: RegAsyncReadWrite, writable_fields:list[ await write_field_combinations(reg=self.dut.PRBS_Error_Mask, writable_fields = [ 'config_data' ]) + with self.subTest(msg='register: msk_top_regs.PRBS_Bit_Count'): + await write_field_combinations(reg=self.dut.PRBS_Bit_Count, + writable_fields = [ 'data' + ]) + with self.subTest(msg='register: msk_top_regs.PRBS_Error_Count'): + await write_field_combinations(reg=self.dut.PRBS_Error_Count, + writable_fields = [ 'data' + ]) + with self.subTest(msg='register: msk_top_regs.LPF_Accum_F1'): + await write_field_combinations(reg=self.dut.LPF_Accum_F1, + writable_fields = [ 'data' + ]) + with self.subTest(msg='register: msk_top_regs.LPF_Accum_F2'): + await write_field_combinations(reg=self.dut.LPF_Accum_F2, + writable_fields = [ 'data' + ]) + with self.subTest(msg='register: msk_top_regs.axis_xfer_count'): + await write_field_combinations(reg=self.dut.axis_xfer_count, + writable_fields = [ 'data' + ]) with self.subTest(msg='register: msk_top_regs.Rx_Sample_Discard'): await write_field_combinations(reg=self.dut.Rx_Sample_Discard, writable_fields = [ 'rx_sample_discard', @@ -14036,6 +15006,22 @@ async def write_field_combinations(reg: RegAsyncReadWrite, writable_fields:list[ writable_fields = [ 'p_gain', 'p_shift' ]) + with self.subTest(msg='register: msk_top_regs.f1_nco_adjust'): + await write_field_combinations(reg=self.dut.f1_nco_adjust, + writable_fields = [ 'data' + ]) + with self.subTest(msg='register: msk_top_regs.f2_nco_adjust'): + await write_field_combinations(reg=self.dut.f2_nco_adjust, + writable_fields = [ 'data' + ]) + with self.subTest(msg='register: msk_top_regs.f1_error'): + await write_field_combinations(reg=self.dut.f1_error, + writable_fields = [ 'data' + ]) + with self.subTest(msg='register: msk_top_regs.f2_error'): + await write_field_combinations(reg=self.dut.f2_error, + writable_fields = [ 'data' + ]) with self.subTest(msg='register: msk_top_regs.Tx_Sync_Ctrl'): await write_field_combinations(reg=self.dut.Tx_Sync_Ctrl, writable_fields = [ 'tx_sync_ena', @@ -14055,6 +15041,18 @@ async def write_field_combinations(reg: RegAsyncReadWrite, writable_fields:list[ await write_field_combinations(reg=self.dut.lowpass_ema_alpha2, writable_fields = [ 'alpha' ]) + with self.subTest(msg='register: msk_top_regs.rx_power'): + await write_field_combinations(reg=self.dut.rx_power, + writable_fields = [ 'data' + ]) + with self.subTest(msg='register: msk_top_regs.tx_async_fifo_rd_wr_ptr'): + await write_field_combinations(reg=self.dut.tx_async_fifo_rd_wr_ptr, + writable_fields = [ 'data' + ]) + with self.subTest(msg='register: msk_top_regs.rx_async_fifo_rd_wr_ptr'): + await write_field_combinations(reg=self.dut.rx_async_fifo_rd_wr_ptr, + writable_fields = [ 'data' + ]) async def test_register_write_fields(self) -> None: """ @@ -14124,6 +15122,20 @@ async def write_field_combinations(reg: RegAsyncReadWrite, writable_fields:list[ 'diff_encoder_loopback' ]) + with self.subTest(msg='register: msk_top_regs.Tx_Bit_Count'): + # test read_fields to register: + # msk_top_regs.Tx_Bit_Count + await write_field_combinations(reg=self.dut.Tx_Bit_Count, + writable_fields = [ 'data' + ]) + + with self.subTest(msg='register: msk_top_regs.Tx_Enable_Count'): + # test read_fields to register: + # msk_top_regs.Tx_Enable_Count + await write_field_combinations(reg=self.dut.Tx_Enable_Count, + writable_fields = [ 'data' + ]) + with self.subTest(msg='register: msk_top_regs.Fb_FreqWord'): # test read_fields to register: # msk_top_regs.Fb_FreqWord @@ -14224,6 +15236,41 @@ async def write_field_combinations(reg: RegAsyncReadWrite, writable_fields:list[ writable_fields = [ 'config_data' ]) + with self.subTest(msg='register: msk_top_regs.PRBS_Bit_Count'): + # test read_fields to register: + # msk_top_regs.PRBS_Bit_Count + await write_field_combinations(reg=self.dut.PRBS_Bit_Count, + writable_fields = [ 'data' + ]) + + with self.subTest(msg='register: msk_top_regs.PRBS_Error_Count'): + # test read_fields to register: + # msk_top_regs.PRBS_Error_Count + await write_field_combinations(reg=self.dut.PRBS_Error_Count, + writable_fields = [ 'data' + ]) + + with self.subTest(msg='register: msk_top_regs.LPF_Accum_F1'): + # test read_fields to register: + # msk_top_regs.LPF_Accum_F1 + await write_field_combinations(reg=self.dut.LPF_Accum_F1, + writable_fields = [ 'data' + ]) + + with self.subTest(msg='register: msk_top_regs.LPF_Accum_F2'): + # test read_fields to register: + # msk_top_regs.LPF_Accum_F2 + await write_field_combinations(reg=self.dut.LPF_Accum_F2, + writable_fields = [ 'data' + ]) + + with self.subTest(msg='register: msk_top_regs.axis_xfer_count'): + # test read_fields to register: + # msk_top_regs.axis_xfer_count + await write_field_combinations(reg=self.dut.axis_xfer_count, + writable_fields = [ 'data' + ]) + with self.subTest(msg='register: msk_top_regs.Rx_Sample_Discard'): # test read_fields to register: # msk_top_regs.Rx_Sample_Discard @@ -14240,6 +15287,34 @@ async def write_field_combinations(reg: RegAsyncReadWrite, writable_fields:list[ 'p_shift' ]) + with self.subTest(msg='register: msk_top_regs.f1_nco_adjust'): + # test read_fields to register: + # msk_top_regs.f1_nco_adjust + await write_field_combinations(reg=self.dut.f1_nco_adjust, + writable_fields = [ 'data' + ]) + + with self.subTest(msg='register: msk_top_regs.f2_nco_adjust'): + # test read_fields to register: + # msk_top_regs.f2_nco_adjust + await write_field_combinations(reg=self.dut.f2_nco_adjust, + writable_fields = [ 'data' + ]) + + with self.subTest(msg='register: msk_top_regs.f1_error'): + # test read_fields to register: + # msk_top_regs.f1_error + await write_field_combinations(reg=self.dut.f1_error, + writable_fields = [ 'data' + ]) + + with self.subTest(msg='register: msk_top_regs.f2_error'): + # test read_fields to register: + # msk_top_regs.f2_error + await write_field_combinations(reg=self.dut.f2_error, + writable_fields = [ 'data' + ]) + with self.subTest(msg='register: msk_top_regs.Tx_Sync_Ctrl'): # test read_fields to register: # msk_top_regs.Tx_Sync_Ctrl @@ -14271,6 +15346,27 @@ async def write_field_combinations(reg: RegAsyncReadWrite, writable_fields:list[ writable_fields = [ 'alpha' ]) + with self.subTest(msg='register: msk_top_regs.rx_power'): + # test read_fields to register: + # msk_top_regs.rx_power + await write_field_combinations(reg=self.dut.rx_power, + writable_fields = [ 'data' + ]) + + with self.subTest(msg='register: msk_top_regs.tx_async_fifo_rd_wr_ptr'): + # test read_fields to register: + # msk_top_regs.tx_async_fifo_rd_wr_ptr + await write_field_combinations(reg=self.dut.tx_async_fifo_rd_wr_ptr, + writable_fields = [ 'data' + ]) + + with self.subTest(msg='register: msk_top_regs.rx_async_fifo_rd_wr_ptr'): + # test read_fields to register: + # msk_top_regs.rx_async_fifo_rd_wr_ptr + await write_field_combinations(reg=self.dut.rx_async_fifo_rd_wr_ptr, + writable_fields = [ 'data' + ]) + @@ -14542,16 +15638,16 @@ def test_adding_attributes(self) -> None: # this line is trying to set an illegal value so by definition should fail the type # checks self.dut.MSK_Status.tx_axis_valid.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] - with self.subTest(msg='node: msk_top_regs.Tx_Bit_Count.tx_bit_counter'): + with self.subTest(msg='node: msk_top_regs.Tx_Bit_Count.data'): with self.assertRaises(AttributeError): # this line is trying to set an illegal value so by definition should fail the type # checks - self.dut.Tx_Bit_Count.tx_bit_counter.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] - with self.subTest(msg='node: msk_top_regs.Tx_Enable_Count.tx_ena_counter'): + self.dut.Tx_Bit_Count.data.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.Tx_Enable_Count.data'): with self.assertRaises(AttributeError): # this line is trying to set an illegal value so by definition should fail the type # checks - self.dut.Tx_Enable_Count.tx_ena_counter.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + self.dut.Tx_Enable_Count.data.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] with self.subTest(msg='node: msk_top_regs.Fb_FreqWord.config_data'): with self.assertRaises(AttributeError): # this line is trying to set an illegal value so by definition should fail the type @@ -14662,31 +15758,31 @@ def test_adding_attributes(self) -> None: # this line is trying to set an illegal value so by definition should fail the type # checks self.dut.PRBS_Error_Mask.config_data.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] - with self.subTest(msg='node: msk_top_regs.PRBS_Bit_Count.status_data'): + with self.subTest(msg='node: msk_top_regs.PRBS_Bit_Count.data'): with self.assertRaises(AttributeError): # this line is trying to set an illegal value so by definition should fail the type # checks - self.dut.PRBS_Bit_Count.status_data.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] - with self.subTest(msg='node: msk_top_regs.PRBS_Error_Count.status_data'): + self.dut.PRBS_Bit_Count.data.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.PRBS_Error_Count.data'): with self.assertRaises(AttributeError): # this line is trying to set an illegal value so by definition should fail the type # checks - self.dut.PRBS_Error_Count.status_data.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] - with self.subTest(msg='node: msk_top_regs.LPF_Accum_F1.status_data'): + self.dut.PRBS_Error_Count.data.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.LPF_Accum_F1.data'): with self.assertRaises(AttributeError): # this line is trying to set an illegal value so by definition should fail the type # checks - self.dut.LPF_Accum_F1.status_data.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] - with self.subTest(msg='node: msk_top_regs.LPF_Accum_F2.status_data'): + self.dut.LPF_Accum_F1.data.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.LPF_Accum_F2.data'): with self.assertRaises(AttributeError): # this line is trying to set an illegal value so by definition should fail the type # checks - self.dut.LPF_Accum_F2.status_data.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] - with self.subTest(msg='node: msk_top_regs.axis_xfer_count.xfer_count'): + self.dut.LPF_Accum_F2.data.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.axis_xfer_count.data'): with self.assertRaises(AttributeError): # this line is trying to set an illegal value so by definition should fail the type # checks - self.dut.axis_xfer_count.xfer_count.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + self.dut.axis_xfer_count.data.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] with self.subTest(msg='node: msk_top_regs.Rx_Sample_Discard.rx_sample_discard'): with self.assertRaises(AttributeError): # this line is trying to set an illegal value so by definition should fail the type @@ -14762,11 +15858,11 @@ def test_adding_attributes(self) -> None: # this line is trying to set an illegal value so by definition should fail the type # checks self.dut.lowpass_ema_alpha2.alpha.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] - with self.subTest(msg='node: msk_top_regs.rx_power.rx_power'): + with self.subTest(msg='node: msk_top_regs.rx_power.data'): with self.assertRaises(AttributeError): # this line is trying to set an illegal value so by definition should fail the type # checks - self.dut.rx_power.rx_power.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + self.dut.rx_power.data.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] with self.subTest(msg='node: msk_top_regs.tx_async_fifo_rd_wr_ptr.data'): with self.assertRaises(AttributeError): # this line is trying to set an illegal value so by definition should fail the type @@ -14966,9 +16062,9 @@ def test_top_traversal_iterators(self) -> None: - + self.dut.Tx_Bit_Count, # type: ignore[union-attr,list-item] - + self.dut.Tx_Enable_Count, # type: ignore[union-attr,list-item] self.dut.Fb_FreqWord, # type: ignore[union-attr,list-item] @@ -14996,27 +16092,27 @@ def test_top_traversal_iterators(self) -> None: self.dut.PRBS_Error_Mask, # type: ignore[union-attr,list-item] - + self.dut.PRBS_Bit_Count, # type: ignore[union-attr,list-item] - + self.dut.PRBS_Error_Count, # type: ignore[union-attr,list-item] - + self.dut.LPF_Accum_F1, # type: ignore[union-attr,list-item] - + self.dut.LPF_Accum_F2, # type: ignore[union-attr,list-item] - + self.dut.axis_xfer_count, # type: ignore[union-attr,list-item] self.dut.Rx_Sample_Discard, # type: ignore[union-attr,list-item] self.dut.LPF_Config_2, # type: ignore[union-attr,list-item] - + self.dut.f1_nco_adjust, # type: ignore[union-attr,list-item] - + self.dut.f2_nco_adjust, # type: ignore[union-attr,list-item] - + self.dut.f1_error, # type: ignore[union-attr,list-item] - + self.dut.f2_error, # type: ignore[union-attr,list-item] self.dut.Tx_Sync_Ctrl, # type: ignore[union-attr,list-item] @@ -15026,11 +16122,11 @@ def test_top_traversal_iterators(self) -> None: self.dut.lowpass_ema_alpha2, # type: ignore[union-attr,list-item] - + self.dut.rx_power, # type: ignore[union-attr,list-item] - + self.dut.tx_async_fifo_rd_wr_ptr, # type: ignore[union-attr,list-item] - + self.dut.rx_async_fifo_rd_wr_ptr, # type: ignore[union-attr,list-item] ] writable_regs = [] @@ -15049,9 +16145,9 @@ def test_top_traversal_iterators(self) -> None: - + self.dut.Tx_Bit_Count, # type: ignore[union-attr,list-item] - + self.dut.Tx_Enable_Count, # type: ignore[union-attr,list-item] self.dut.Fb_FreqWord, # type: ignore[union-attr,list-item] @@ -15079,27 +16175,27 @@ def test_top_traversal_iterators(self) -> None: self.dut.PRBS_Error_Mask, # type: ignore[union-attr,list-item] - + self.dut.PRBS_Bit_Count, # type: ignore[union-attr,list-item] - + self.dut.PRBS_Error_Count, # type: ignore[union-attr,list-item] - + self.dut.LPF_Accum_F1, # type: ignore[union-attr,list-item] - + self.dut.LPF_Accum_F2, # type: ignore[union-attr,list-item] - + self.dut.axis_xfer_count, # type: ignore[union-attr,list-item] self.dut.Rx_Sample_Discard, # type: ignore[union-attr,list-item] self.dut.LPF_Config_2, # type: ignore[union-attr,list-item] - + self.dut.f1_nco_adjust, # type: ignore[union-attr,list-item] - + self.dut.f2_nco_adjust, # type: ignore[union-attr,list-item] - + self.dut.f1_error, # type: ignore[union-attr,list-item] - + self.dut.f2_error, # type: ignore[union-attr,list-item] self.dut.Tx_Sync_Ctrl, # type: ignore[union-attr,list-item] @@ -15109,11 +16205,11 @@ def test_top_traversal_iterators(self) -> None: self.dut.lowpass_ema_alpha2, # type: ignore[union-attr,list-item] - + self.dut.rx_power, # type: ignore[union-attr,list-item] - + self.dut.tx_async_fifo_rd_wr_ptr, # type: ignore[union-attr,list-item] - + self.dut.rx_async_fifo_rd_wr_ptr, # type: ignore[union-attr,list-item] ] writable_regs = [] @@ -15676,7 +16772,7 @@ def test_traversal_iterators(self) -> None: with self.subTest(msg='register: msk_top_regs.Tx_Bit_Count'): - expected_fields = [self.dut.Tx_Bit_Count.tx_bit_counter, # type: ignore[union-attr,list-item] + expected_fields = [self.dut.Tx_Bit_Count.data, # type: ignore[union-attr,list-item] @@ -15686,11 +16782,17 @@ def test_traversal_iterators(self) -> None: fields.append(field) self.assertCountEqual(expected_fields, fields) - # register should not have writable_fields attribute - self.assertFalse(hasattr(self.dut.Tx_Bit_Count, 'writable_fields')) # type: ignore[union-attr] + expected_writable_fields = [self.dut.Tx_Bit_Count.data, # type: ignore[union-attr,list-item] + + + ] + writable_fields = [] + for writable_field in self.dut.Tx_Bit_Count.writable_fields: # type: ignore[union-attr] + writable_fields.append(writable_field) + self.assertCountEqual(expected_writable_fields, writable_fields) - expected_readable_fields = [self.dut.Tx_Bit_Count.tx_bit_counter, # type: ignore[union-attr,list-item] + expected_readable_fields = [self.dut.Tx_Bit_Count.data, # type: ignore[union-attr,list-item] ] @@ -15701,7 +16803,7 @@ def test_traversal_iterators(self) -> None: with self.subTest(msg='register: msk_top_regs.Tx_Enable_Count'): - expected_fields = [self.dut.Tx_Enable_Count.tx_ena_counter, # type: ignore[union-attr,list-item] + expected_fields = [self.dut.Tx_Enable_Count.data, # type: ignore[union-attr,list-item] @@ -15711,11 +16813,17 @@ def test_traversal_iterators(self) -> None: fields.append(field) self.assertCountEqual(expected_fields, fields) - # register should not have writable_fields attribute - self.assertFalse(hasattr(self.dut.Tx_Enable_Count, 'writable_fields')) # type: ignore[union-attr] + expected_writable_fields = [self.dut.Tx_Enable_Count.data, # type: ignore[union-attr,list-item] + + + ] + writable_fields = [] + for writable_field in self.dut.Tx_Enable_Count.writable_fields: # type: ignore[union-attr] + writable_fields.append(writable_field) + self.assertCountEqual(expected_writable_fields, writable_fields) - expected_readable_fields = [self.dut.Tx_Enable_Count.tx_ena_counter, # type: ignore[union-attr,list-item] + expected_readable_fields = [self.dut.Tx_Enable_Count.data, # type: ignore[union-attr,list-item] ] @@ -16192,7 +17300,7 @@ def test_traversal_iterators(self) -> None: with self.subTest(msg='register: msk_top_regs.PRBS_Bit_Count'): - expected_fields = [self.dut.PRBS_Bit_Count.status_data, # type: ignore[union-attr,list-item] + expected_fields = [self.dut.PRBS_Bit_Count.data, # type: ignore[union-attr,list-item] @@ -16202,11 +17310,17 @@ def test_traversal_iterators(self) -> None: fields.append(field) self.assertCountEqual(expected_fields, fields) - # register should not have writable_fields attribute - self.assertFalse(hasattr(self.dut.PRBS_Bit_Count, 'writable_fields')) # type: ignore[union-attr] + expected_writable_fields = [self.dut.PRBS_Bit_Count.data, # type: ignore[union-attr,list-item] + + + ] + writable_fields = [] + for writable_field in self.dut.PRBS_Bit_Count.writable_fields: # type: ignore[union-attr] + writable_fields.append(writable_field) + self.assertCountEqual(expected_writable_fields, writable_fields) - expected_readable_fields = [self.dut.PRBS_Bit_Count.status_data, # type: ignore[union-attr,list-item] + expected_readable_fields = [self.dut.PRBS_Bit_Count.data, # type: ignore[union-attr,list-item] ] @@ -16217,7 +17331,7 @@ def test_traversal_iterators(self) -> None: with self.subTest(msg='register: msk_top_regs.PRBS_Error_Count'): - expected_fields = [self.dut.PRBS_Error_Count.status_data, # type: ignore[union-attr,list-item] + expected_fields = [self.dut.PRBS_Error_Count.data, # type: ignore[union-attr,list-item] @@ -16227,11 +17341,17 @@ def test_traversal_iterators(self) -> None: fields.append(field) self.assertCountEqual(expected_fields, fields) - # register should not have writable_fields attribute - self.assertFalse(hasattr(self.dut.PRBS_Error_Count, 'writable_fields')) # type: ignore[union-attr] + expected_writable_fields = [self.dut.PRBS_Error_Count.data, # type: ignore[union-attr,list-item] + + + ] + writable_fields = [] + for writable_field in self.dut.PRBS_Error_Count.writable_fields: # type: ignore[union-attr] + writable_fields.append(writable_field) + self.assertCountEqual(expected_writable_fields, writable_fields) - expected_readable_fields = [self.dut.PRBS_Error_Count.status_data, # type: ignore[union-attr,list-item] + expected_readable_fields = [self.dut.PRBS_Error_Count.data, # type: ignore[union-attr,list-item] ] @@ -16242,7 +17362,7 @@ def test_traversal_iterators(self) -> None: with self.subTest(msg='register: msk_top_regs.LPF_Accum_F1'): - expected_fields = [self.dut.LPF_Accum_F1.status_data, # type: ignore[union-attr,list-item] + expected_fields = [self.dut.LPF_Accum_F1.data, # type: ignore[union-attr,list-item] @@ -16252,11 +17372,17 @@ def test_traversal_iterators(self) -> None: fields.append(field) self.assertCountEqual(expected_fields, fields) - # register should not have writable_fields attribute - self.assertFalse(hasattr(self.dut.LPF_Accum_F1, 'writable_fields')) # type: ignore[union-attr] + expected_writable_fields = [self.dut.LPF_Accum_F1.data, # type: ignore[union-attr,list-item] + + + ] + writable_fields = [] + for writable_field in self.dut.LPF_Accum_F1.writable_fields: # type: ignore[union-attr] + writable_fields.append(writable_field) + self.assertCountEqual(expected_writable_fields, writable_fields) - expected_readable_fields = [self.dut.LPF_Accum_F1.status_data, # type: ignore[union-attr,list-item] + expected_readable_fields = [self.dut.LPF_Accum_F1.data, # type: ignore[union-attr,list-item] ] @@ -16267,7 +17393,7 @@ def test_traversal_iterators(self) -> None: with self.subTest(msg='register: msk_top_regs.LPF_Accum_F2'): - expected_fields = [self.dut.LPF_Accum_F2.status_data, # type: ignore[union-attr,list-item] + expected_fields = [self.dut.LPF_Accum_F2.data, # type: ignore[union-attr,list-item] @@ -16277,11 +17403,17 @@ def test_traversal_iterators(self) -> None: fields.append(field) self.assertCountEqual(expected_fields, fields) - # register should not have writable_fields attribute - self.assertFalse(hasattr(self.dut.LPF_Accum_F2, 'writable_fields')) # type: ignore[union-attr] + expected_writable_fields = [self.dut.LPF_Accum_F2.data, # type: ignore[union-attr,list-item] + + + ] + writable_fields = [] + for writable_field in self.dut.LPF_Accum_F2.writable_fields: # type: ignore[union-attr] + writable_fields.append(writable_field) + self.assertCountEqual(expected_writable_fields, writable_fields) - expected_readable_fields = [self.dut.LPF_Accum_F2.status_data, # type: ignore[union-attr,list-item] + expected_readable_fields = [self.dut.LPF_Accum_F2.data, # type: ignore[union-attr,list-item] ] @@ -16292,7 +17424,7 @@ def test_traversal_iterators(self) -> None: with self.subTest(msg='register: msk_top_regs.axis_xfer_count'): - expected_fields = [self.dut.axis_xfer_count.xfer_count, # type: ignore[union-attr,list-item] + expected_fields = [self.dut.axis_xfer_count.data, # type: ignore[union-attr,list-item] @@ -16302,11 +17434,17 @@ def test_traversal_iterators(self) -> None: fields.append(field) self.assertCountEqual(expected_fields, fields) - # register should not have writable_fields attribute - self.assertFalse(hasattr(self.dut.axis_xfer_count, 'writable_fields')) # type: ignore[union-attr] + expected_writable_fields = [self.dut.axis_xfer_count.data, # type: ignore[union-attr,list-item] + + + ] + writable_fields = [] + for writable_field in self.dut.axis_xfer_count.writable_fields: # type: ignore[union-attr] + writable_fields.append(writable_field) + self.assertCountEqual(expected_writable_fields, writable_fields) - expected_readable_fields = [self.dut.axis_xfer_count.xfer_count, # type: ignore[union-attr,list-item] + expected_readable_fields = [self.dut.axis_xfer_count.data, # type: ignore[union-attr,list-item] ] @@ -16403,8 +17541,14 @@ def test_traversal_iterators(self) -> None: fields.append(field) self.assertCountEqual(expected_fields, fields) - # register should not have writable_fields attribute - self.assertFalse(hasattr(self.dut.f1_nco_adjust, 'writable_fields')) # type: ignore[union-attr] + expected_writable_fields = [self.dut.f1_nco_adjust.data, # type: ignore[union-attr,list-item] + + + ] + writable_fields = [] + for writable_field in self.dut.f1_nco_adjust.writable_fields: # type: ignore[union-attr] + writable_fields.append(writable_field) + self.assertCountEqual(expected_writable_fields, writable_fields) expected_readable_fields = [self.dut.f1_nco_adjust.data, # type: ignore[union-attr,list-item] @@ -16428,8 +17572,14 @@ def test_traversal_iterators(self) -> None: fields.append(field) self.assertCountEqual(expected_fields, fields) - # register should not have writable_fields attribute - self.assertFalse(hasattr(self.dut.f2_nco_adjust, 'writable_fields')) # type: ignore[union-attr] + expected_writable_fields = [self.dut.f2_nco_adjust.data, # type: ignore[union-attr,list-item] + + + ] + writable_fields = [] + for writable_field in self.dut.f2_nco_adjust.writable_fields: # type: ignore[union-attr] + writable_fields.append(writable_field) + self.assertCountEqual(expected_writable_fields, writable_fields) expected_readable_fields = [self.dut.f2_nco_adjust.data, # type: ignore[union-attr,list-item] @@ -16453,8 +17603,14 @@ def test_traversal_iterators(self) -> None: fields.append(field) self.assertCountEqual(expected_fields, fields) - # register should not have writable_fields attribute - self.assertFalse(hasattr(self.dut.f1_error, 'writable_fields')) # type: ignore[union-attr] + expected_writable_fields = [self.dut.f1_error.data, # type: ignore[union-attr,list-item] + + + ] + writable_fields = [] + for writable_field in self.dut.f1_error.writable_fields: # type: ignore[union-attr] + writable_fields.append(writable_field) + self.assertCountEqual(expected_writable_fields, writable_fields) expected_readable_fields = [self.dut.f1_error.data, # type: ignore[union-attr,list-item] @@ -16478,8 +17634,14 @@ def test_traversal_iterators(self) -> None: fields.append(field) self.assertCountEqual(expected_fields, fields) - # register should not have writable_fields attribute - self.assertFalse(hasattr(self.dut.f2_error, 'writable_fields')) # type: ignore[union-attr] + expected_writable_fields = [self.dut.f2_error.data, # type: ignore[union-attr,list-item] + + + ] + writable_fields = [] + for writable_field in self.dut.f2_error.writable_fields: # type: ignore[union-attr] + writable_fields.append(writable_field) + self.assertCountEqual(expected_writable_fields, writable_fields) expected_readable_fields = [self.dut.f2_error.data, # type: ignore[union-attr,list-item] @@ -16638,7 +17800,7 @@ def test_traversal_iterators(self) -> None: with self.subTest(msg='register: msk_top_regs.rx_power'): - expected_fields = [self.dut.rx_power.rx_power, # type: ignore[union-attr,list-item] + expected_fields = [self.dut.rx_power.data, # type: ignore[union-attr,list-item] @@ -16648,11 +17810,17 @@ def test_traversal_iterators(self) -> None: fields.append(field) self.assertCountEqual(expected_fields, fields) - # register should not have writable_fields attribute - self.assertFalse(hasattr(self.dut.rx_power, 'writable_fields')) # type: ignore[union-attr] + expected_writable_fields = [self.dut.rx_power.data, # type: ignore[union-attr,list-item] + + + ] + writable_fields = [] + for writable_field in self.dut.rx_power.writable_fields: # type: ignore[union-attr] + writable_fields.append(writable_field) + self.assertCountEqual(expected_writable_fields, writable_fields) - expected_readable_fields = [self.dut.rx_power.rx_power, # type: ignore[union-attr,list-item] + expected_readable_fields = [self.dut.rx_power.data, # type: ignore[union-attr,list-item] ] @@ -16673,8 +17841,14 @@ def test_traversal_iterators(self) -> None: fields.append(field) self.assertCountEqual(expected_fields, fields) - # register should not have writable_fields attribute - self.assertFalse(hasattr(self.dut.tx_async_fifo_rd_wr_ptr, 'writable_fields')) # type: ignore[union-attr] + expected_writable_fields = [self.dut.tx_async_fifo_rd_wr_ptr.data, # type: ignore[union-attr,list-item] + + + ] + writable_fields = [] + for writable_field in self.dut.tx_async_fifo_rd_wr_ptr.writable_fields: # type: ignore[union-attr] + writable_fields.append(writable_field) + self.assertCountEqual(expected_writable_fields, writable_fields) expected_readable_fields = [self.dut.tx_async_fifo_rd_wr_ptr.data, # type: ignore[union-attr,list-item] @@ -16698,8 +17872,14 @@ def test_traversal_iterators(self) -> None: fields.append(field) self.assertCountEqual(expected_fields, fields) - # register should not have writable_fields attribute - self.assertFalse(hasattr(self.dut.rx_async_fifo_rd_wr_ptr, 'writable_fields')) # type: ignore[union-attr] + expected_writable_fields = [self.dut.rx_async_fifo_rd_wr_ptr.data, # type: ignore[union-attr,list-item] + + + ] + writable_fields = [] + for writable_field in self.dut.rx_async_fifo_rd_wr_ptr.writable_fields: # type: ignore[union-attr] + writable_fields.append(writable_field) + self.assertCountEqual(expected_writable_fields, writable_fields) expected_readable_fields = [self.dut.rx_async_fifo_rd_wr_ptr.data, # type: ignore[union-attr,list-item] @@ -16800,13 +17980,13 @@ def test_name_map(self) -> None: - self.assertEqual(self.dut.Tx_Bit_Count.get_child_by_system_rdl_name('tx_bit_counter').inst_name, 'tx_bit_counter') + self.assertEqual(self.dut.Tx_Bit_Count.get_child_by_system_rdl_name('data').inst_name, 'data') - self.assertEqual(self.dut.Tx_Enable_Count.get_child_by_system_rdl_name('tx_ena_counter').inst_name, 'tx_ena_counter') + self.assertEqual(self.dut.Tx_Enable_Count.get_child_by_system_rdl_name('data').inst_name, 'data') @@ -16935,31 +18115,31 @@ def test_name_map(self) -> None: - self.assertEqual(self.dut.PRBS_Bit_Count.get_child_by_system_rdl_name('status_data').inst_name, 'status_data') + self.assertEqual(self.dut.PRBS_Bit_Count.get_child_by_system_rdl_name('data').inst_name, 'data') - self.assertEqual(self.dut.PRBS_Error_Count.get_child_by_system_rdl_name('status_data').inst_name, 'status_data') + self.assertEqual(self.dut.PRBS_Error_Count.get_child_by_system_rdl_name('data').inst_name, 'data') - self.assertEqual(self.dut.LPF_Accum_F1.get_child_by_system_rdl_name('status_data').inst_name, 'status_data') + self.assertEqual(self.dut.LPF_Accum_F1.get_child_by_system_rdl_name('data').inst_name, 'data') - self.assertEqual(self.dut.LPF_Accum_F2.get_child_by_system_rdl_name('status_data').inst_name, 'status_data') + self.assertEqual(self.dut.LPF_Accum_F2.get_child_by_system_rdl_name('data').inst_name, 'data') - self.assertEqual(self.dut.axis_xfer_count.get_child_by_system_rdl_name('xfer_count').inst_name, 'xfer_count') + self.assertEqual(self.dut.axis_xfer_count.get_child_by_system_rdl_name('data').inst_name, 'data') @@ -17050,7 +18230,7 @@ def test_name_map(self) -> None: - self.assertEqual(self.dut.rx_power.get_child_by_system_rdl_name('rx_power').inst_name, 'rx_power') + self.assertEqual(self.dut.rx_power.get_child_by_system_rdl_name('data').inst_name, 'data') diff --git a/rdl/outputs/python/msk_top_regs/tests/test_sim_msk_top_regs.py b/rdl/outputs/python/msk_top_regs/tests/test_sim_msk_top_regs.py index f4578fd..f95ff7a 100644 --- a/rdl/outputs/python/msk_top_regs/tests/test_sim_msk_top_regs.py +++ b/rdl/outputs/python/msk_top_regs/tests/test_sim_msk_top_regs.py @@ -279,6 +279,27 @@ async def test_register_read_and_write(self) -> None: + # register write checks + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.Tx_Bit_Count.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.Tx_Bit_Count.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + register_write_callback.assert_called_once_with(value=random_value) + register_read_callback.assert_not_called() + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.Tx_Bit_Count.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + self.assertEqual(await self.dut.Tx_Bit_Count.read(), random_value) + # test access operations (read and/or write) to register: @@ -313,6 +334,27 @@ async def test_register_read_and_write(self) -> None: + # register write checks + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.Tx_Enable_Count.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.Tx_Enable_Count.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + register_write_callback.assert_called_once_with(value=random_value) + register_read_callback.assert_not_called() + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.Tx_Enable_Count.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + self.assertEqual(await self.dut.Tx_Enable_Count.read(), random_value) + # test access operations (read and/or write) to register: @@ -1062,6 +1104,27 @@ async def test_register_read_and_write(self) -> None: + # register write checks + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.PRBS_Bit_Count.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.PRBS_Bit_Count.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + register_write_callback.assert_called_once_with(value=random_value) + register_read_callback.assert_not_called() + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.PRBS_Bit_Count.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + self.assertEqual(await self.dut.PRBS_Bit_Count.read(), random_value) + # test access operations (read and/or write) to register: @@ -1096,6 +1159,27 @@ async def test_register_read_and_write(self) -> None: + # register write checks + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.PRBS_Error_Count.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.PRBS_Error_Count.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + register_write_callback.assert_called_once_with(value=random_value) + register_read_callback.assert_not_called() + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.PRBS_Error_Count.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + self.assertEqual(await self.dut.PRBS_Error_Count.read(), random_value) + # test access operations (read and/or write) to register: @@ -1130,6 +1214,27 @@ async def test_register_read_and_write(self) -> None: + # register write checks + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.LPF_Accum_F1.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.LPF_Accum_F1.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + register_write_callback.assert_called_once_with(value=random_value) + register_read_callback.assert_not_called() + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.LPF_Accum_F1.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + self.assertEqual(await self.dut.LPF_Accum_F1.read(), random_value) + # test access operations (read and/or write) to register: @@ -1164,6 +1269,27 @@ async def test_register_read_and_write(self) -> None: + # register write checks + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.LPF_Accum_F2.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.LPF_Accum_F2.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + register_write_callback.assert_called_once_with(value=random_value) + register_read_callback.assert_not_called() + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.LPF_Accum_F2.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + self.assertEqual(await self.dut.LPF_Accum_F2.read(), random_value) + # test access operations (read and/or write) to register: @@ -1198,6 +1324,27 @@ async def test_register_read_and_write(self) -> None: + # register write checks + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.axis_xfer_count.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.axis_xfer_count.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + register_write_callback.assert_called_once_with(value=random_value) + register_read_callback.assert_not_called() + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.axis_xfer_count.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + self.assertEqual(await self.dut.axis_xfer_count.read(), random_value) + # test access operations (read and/or write) to register: @@ -1342,6 +1489,27 @@ async def test_register_read_and_write(self) -> None: + # register write checks + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.f1_nco_adjust.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.f1_nco_adjust.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + register_write_callback.assert_called_once_with(value=random_value) + register_read_callback.assert_not_called() + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.f1_nco_adjust.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + self.assertEqual(await self.dut.f1_nco_adjust.read(), random_value) + # test access operations (read and/or write) to register: @@ -1376,6 +1544,27 @@ async def test_register_read_and_write(self) -> None: + # register write checks + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.f2_nco_adjust.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.f2_nco_adjust.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + register_write_callback.assert_called_once_with(value=random_value) + register_read_callback.assert_not_called() + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.f2_nco_adjust.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + self.assertEqual(await self.dut.f2_nco_adjust.read(), random_value) + # test access operations (read and/or write) to register: @@ -1410,6 +1599,27 @@ async def test_register_read_and_write(self) -> None: + # register write checks + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.f1_error.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.f1_error.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + register_write_callback.assert_called_once_with(value=random_value) + register_read_callback.assert_not_called() + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.f1_error.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + self.assertEqual(await self.dut.f1_error.read(), random_value) + # test access operations (read and/or write) to register: @@ -1444,6 +1654,27 @@ async def test_register_read_and_write(self) -> None: + # register write checks + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.f2_error.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.f2_error.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + register_write_callback.assert_called_once_with(value=random_value) + register_read_callback.assert_not_called() + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.f2_error.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + self.assertEqual(await self.dut.f2_error.read(), random_value) + # test access operations (read and/or write) to register: @@ -1698,6 +1929,27 @@ async def test_register_read_and_write(self) -> None: + # register write checks + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.rx_power.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.rx_power.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + register_write_callback.assert_called_once_with(value=random_value) + register_read_callback.assert_not_called() + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.rx_power.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + self.assertEqual(await self.dut.rx_power.read(), random_value) + # test access operations (read and/or write) to register: @@ -1732,6 +1984,27 @@ async def test_register_read_and_write(self) -> None: + # register write checks + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.tx_async_fifo_rd_wr_ptr.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.tx_async_fifo_rd_wr_ptr.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + register_write_callback.assert_called_once_with(value=random_value) + register_read_callback.assert_not_called() + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.tx_async_fifo_rd_wr_ptr.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + self.assertEqual(await self.dut.tx_async_fifo_rd_wr_ptr.read(), random_value) + # test access operations (read and/or write) to register: @@ -1766,6 +2039,27 @@ async def test_register_read_and_write(self) -> None: + # register write checks + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.rx_async_fifo_rd_wr_ptr.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.rx_async_fifo_rd_wr_ptr.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + register_write_callback.assert_called_once_with(value=random_value) + register_read_callback.assert_not_called() + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.rx_async_fifo_rd_wr_ptr.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + self.assertEqual(await self.dut.rx_async_fifo_rd_wr_ptr.read(), random_value) + @@ -3148,11 +3442,11 @@ async def test_field_read_and_write(self) -> None: # test access operations (read and/or write) to register: - # msk_top_regs.Tx_Bit_Count.tx_bit_counter - with self.subTest(msg='field: msk_top_regs.Tx_Bit_Count.tx_bit_counter'): + # msk_top_regs.Tx_Bit_Count.data + with self.subTest(msg='field: msk_top_regs.Tx_Bit_Count.data'): sim_register = self.sim.register_by_full_name('msk_top_regs.Tx_Bit_Count') self.assertIsInstance(sim_register, (Register,MemoryRegister)) - sim_field = self.sim.field_by_full_name('msk_top_regs.Tx_Bit_Count.tx_bit_counter') + sim_field = self.sim.field_by_full_name('msk_top_regs.Tx_Bit_Count.data') self.assertIsInstance(sim_field, Field) register_read_callback = Mock() register_write_callback = Mock() @@ -3166,14 +3460,14 @@ async def test_field_read_and_write(self) -> None: sim_register.value = random_value - self.assertEqual(await self.dut.Tx_Bit_Count.tx_bit_counter.read(), random_field_value) + self.assertEqual(await self.dut.Tx_Bit_Count.data.read(), random_field_value) # update the field value via the backdoor in the simulator previous_register_value = random_value random_field_value = random.randrange(0, 0xFFFFFFFF+1) sim_field.value = random_field_value self.assertEqual(sim_register.value, (previous_register_value & 0x0) | (random_field_value << 0)) - self.assertEqual(await self.dut.Tx_Bit_Count.tx_bit_counter.read(), random_field_value) + self.assertEqual(await self.dut.Tx_Bit_Count.data.read(), random_field_value) # hook up the call backs to check they work correctly random_value = random.randrange(0, 0xFFFFFFFF+1) random_field_value = (random_value & 0xFFFFFFFF) >> 0 @@ -3184,7 +3478,7 @@ async def test_field_read_and_write(self) -> None: sim_register.write_callback = register_write_callback sim_field.read_callback = field_read_callback sim_field.write_callback = field_write_callback - self.assertEqual(await self.dut.Tx_Bit_Count.tx_bit_counter.read(), random_field_value) + self.assertEqual(await self.dut.Tx_Bit_Count.data.read(), random_field_value) register_write_callback.assert_not_called() register_read_callback.assert_called_once_with(value=random_value) field_write_callback.assert_not_called() @@ -3204,21 +3498,68 @@ async def test_field_read_and_write(self) -> None: sim_register.value = random_value - self.assertEqual(await self.dut.Tx_Bit_Count.tx_bit_counter.read(), random_field_value) + self.assertEqual(await self.dut.Tx_Bit_Count.data.read(), random_field_value) register_write_callback.assert_not_called() register_read_callback.assert_not_called() field_write_callback.assert_not_called() field_read_callback.assert_not_called() - - - # test access operations (read and/or write) to register: - # msk_top_regs.Tx_Enable_Count.tx_ena_counter - with self.subTest(msg='field: msk_top_regs.Tx_Enable_Count.tx_ena_counter'): - sim_register = self.sim.register_by_full_name('msk_top_regs.Tx_Enable_Count') + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value + + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.Tx_Bit_Count.data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.Tx_Bit_Count.data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + field_write_callback.assert_called_once_with(value=random_field_value) + + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.write_callback = None + sim_field.write_callback = None + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.Tx_Bit_Count.data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # test access operations (read and/or write) to register: + # msk_top_regs.Tx_Enable_Count.data + with self.subTest(msg='field: msk_top_regs.Tx_Enable_Count.data'): + sim_register = self.sim.register_by_full_name('msk_top_regs.Tx_Enable_Count') self.assertIsInstance(sim_register, (Register,MemoryRegister)) - sim_field = self.sim.field_by_full_name('msk_top_regs.Tx_Enable_Count.tx_ena_counter') + sim_field = self.sim.field_by_full_name('msk_top_regs.Tx_Enable_Count.data') self.assertIsInstance(sim_field, Field) register_read_callback = Mock() register_write_callback = Mock() @@ -3232,14 +3573,14 @@ async def test_field_read_and_write(self) -> None: sim_register.value = random_value - self.assertEqual(await self.dut.Tx_Enable_Count.tx_ena_counter.read(), random_field_value) + self.assertEqual(await self.dut.Tx_Enable_Count.data.read(), random_field_value) # update the field value via the backdoor in the simulator previous_register_value = random_value random_field_value = random.randrange(0, 0xFFFFFFFF+1) sim_field.value = random_field_value self.assertEqual(sim_register.value, (previous_register_value & 0x0) | (random_field_value << 0)) - self.assertEqual(await self.dut.Tx_Enable_Count.tx_ena_counter.read(), random_field_value) + self.assertEqual(await self.dut.Tx_Enable_Count.data.read(), random_field_value) # hook up the call backs to check they work correctly random_value = random.randrange(0, 0xFFFFFFFF+1) random_field_value = (random_value & 0xFFFFFFFF) >> 0 @@ -3250,7 +3591,7 @@ async def test_field_read_and_write(self) -> None: sim_register.write_callback = register_write_callback sim_field.read_callback = field_read_callback sim_field.write_callback = field_write_callback - self.assertEqual(await self.dut.Tx_Enable_Count.tx_ena_counter.read(), random_field_value) + self.assertEqual(await self.dut.Tx_Enable_Count.data.read(), random_field_value) register_write_callback.assert_not_called() register_read_callback.assert_called_once_with(value=random_value) field_write_callback.assert_not_called() @@ -3270,13 +3611,60 @@ async def test_field_read_and_write(self) -> None: sim_register.value = random_value - self.assertEqual(await self.dut.Tx_Enable_Count.tx_ena_counter.read(), random_field_value) + self.assertEqual(await self.dut.Tx_Enable_Count.data.read(), random_field_value) register_write_callback.assert_not_called() register_read_callback.assert_not_called() field_write_callback.assert_not_called() field_read_callback.assert_not_called() + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value + + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.Tx_Enable_Count.data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.Tx_Enable_Count.data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + field_write_callback.assert_called_once_with(value=random_field_value) + + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.write_callback = None + sim_field.write_callback = None + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.Tx_Enable_Count.data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() # test access operations (read and/or write) to register: @@ -5634,11 +6022,11 @@ async def test_field_read_and_write(self) -> None: # test access operations (read and/or write) to register: - # msk_top_regs.PRBS_Bit_Count.status_data - with self.subTest(msg='field: msk_top_regs.PRBS_Bit_Count.status_data'): + # msk_top_regs.PRBS_Bit_Count.data + with self.subTest(msg='field: msk_top_regs.PRBS_Bit_Count.data'): sim_register = self.sim.register_by_full_name('msk_top_regs.PRBS_Bit_Count') self.assertIsInstance(sim_register, (Register,MemoryRegister)) - sim_field = self.sim.field_by_full_name('msk_top_regs.PRBS_Bit_Count.status_data') + sim_field = self.sim.field_by_full_name('msk_top_regs.PRBS_Bit_Count.data') self.assertIsInstance(sim_field, Field) register_read_callback = Mock() register_write_callback = Mock() @@ -5652,14 +6040,14 @@ async def test_field_read_and_write(self) -> None: sim_register.value = random_value - self.assertEqual(await self.dut.PRBS_Bit_Count.status_data.read(), random_field_value) + self.assertEqual(await self.dut.PRBS_Bit_Count.data.read(), random_field_value) # update the field value via the backdoor in the simulator previous_register_value = random_value random_field_value = random.randrange(0, 0xFFFFFFFF+1) sim_field.value = random_field_value self.assertEqual(sim_register.value, (previous_register_value & 0x0) | (random_field_value << 0)) - self.assertEqual(await self.dut.PRBS_Bit_Count.status_data.read(), random_field_value) + self.assertEqual(await self.dut.PRBS_Bit_Count.data.read(), random_field_value) # hook up the call backs to check they work correctly random_value = random.randrange(0, 0xFFFFFFFF+1) random_field_value = (random_value & 0xFFFFFFFF) >> 0 @@ -5670,7 +6058,7 @@ async def test_field_read_and_write(self) -> None: sim_register.write_callback = register_write_callback sim_field.read_callback = field_read_callback sim_field.write_callback = field_write_callback - self.assertEqual(await self.dut.PRBS_Bit_Count.status_data.read(), random_field_value) + self.assertEqual(await self.dut.PRBS_Bit_Count.data.read(), random_field_value) register_write_callback.assert_not_called() register_read_callback.assert_called_once_with(value=random_value) field_write_callback.assert_not_called() @@ -5690,21 +6078,68 @@ async def test_field_read_and_write(self) -> None: sim_register.value = random_value - self.assertEqual(await self.dut.PRBS_Bit_Count.status_data.read(), random_field_value) + self.assertEqual(await self.dut.PRBS_Bit_Count.data.read(), random_field_value) register_write_callback.assert_not_called() register_read_callback.assert_not_called() field_write_callback.assert_not_called() field_read_callback.assert_not_called() + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value + + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.PRBS_Bit_Count.data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.PRBS_Bit_Count.data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + field_write_callback.assert_called_once_with(value=random_field_value) + + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.write_callback = None + sim_field.write_callback = None + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.PRBS_Bit_Count.data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() # test access operations (read and/or write) to register: - # msk_top_regs.PRBS_Error_Count.status_data - with self.subTest(msg='field: msk_top_regs.PRBS_Error_Count.status_data'): + # msk_top_regs.PRBS_Error_Count.data + with self.subTest(msg='field: msk_top_regs.PRBS_Error_Count.data'): sim_register = self.sim.register_by_full_name('msk_top_regs.PRBS_Error_Count') self.assertIsInstance(sim_register, (Register,MemoryRegister)) - sim_field = self.sim.field_by_full_name('msk_top_regs.PRBS_Error_Count.status_data') + sim_field = self.sim.field_by_full_name('msk_top_regs.PRBS_Error_Count.data') self.assertIsInstance(sim_field, Field) register_read_callback = Mock() register_write_callback = Mock() @@ -5718,14 +6153,14 @@ async def test_field_read_and_write(self) -> None: sim_register.value = random_value - self.assertEqual(await self.dut.PRBS_Error_Count.status_data.read(), random_field_value) + self.assertEqual(await self.dut.PRBS_Error_Count.data.read(), random_field_value) # update the field value via the backdoor in the simulator previous_register_value = random_value random_field_value = random.randrange(0, 0xFFFFFFFF+1) sim_field.value = random_field_value self.assertEqual(sim_register.value, (previous_register_value & 0x0) | (random_field_value << 0)) - self.assertEqual(await self.dut.PRBS_Error_Count.status_data.read(), random_field_value) + self.assertEqual(await self.dut.PRBS_Error_Count.data.read(), random_field_value) # hook up the call backs to check they work correctly random_value = random.randrange(0, 0xFFFFFFFF+1) random_field_value = (random_value & 0xFFFFFFFF) >> 0 @@ -5736,7 +6171,7 @@ async def test_field_read_and_write(self) -> None: sim_register.write_callback = register_write_callback sim_field.read_callback = field_read_callback sim_field.write_callback = field_write_callback - self.assertEqual(await self.dut.PRBS_Error_Count.status_data.read(), random_field_value) + self.assertEqual(await self.dut.PRBS_Error_Count.data.read(), random_field_value) register_write_callback.assert_not_called() register_read_callback.assert_called_once_with(value=random_value) field_write_callback.assert_not_called() @@ -5756,21 +6191,68 @@ async def test_field_read_and_write(self) -> None: sim_register.value = random_value - self.assertEqual(await self.dut.PRBS_Error_Count.status_data.read(), random_field_value) + self.assertEqual(await self.dut.PRBS_Error_Count.data.read(), random_field_value) register_write_callback.assert_not_called() register_read_callback.assert_not_called() field_write_callback.assert_not_called() field_read_callback.assert_not_called() + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value + + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.PRBS_Error_Count.data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.PRBS_Error_Count.data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + field_write_callback.assert_called_once_with(value=random_field_value) + + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.write_callback = None + sim_field.write_callback = None + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.PRBS_Error_Count.data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() # test access operations (read and/or write) to register: - # msk_top_regs.LPF_Accum_F1.status_data - with self.subTest(msg='field: msk_top_regs.LPF_Accum_F1.status_data'): + # msk_top_regs.LPF_Accum_F1.data + with self.subTest(msg='field: msk_top_regs.LPF_Accum_F1.data'): sim_register = self.sim.register_by_full_name('msk_top_regs.LPF_Accum_F1') self.assertIsInstance(sim_register, (Register,MemoryRegister)) - sim_field = self.sim.field_by_full_name('msk_top_regs.LPF_Accum_F1.status_data') + sim_field = self.sim.field_by_full_name('msk_top_regs.LPF_Accum_F1.data') self.assertIsInstance(sim_field, Field) register_read_callback = Mock() register_write_callback = Mock() @@ -5784,14 +6266,14 @@ async def test_field_read_and_write(self) -> None: sim_register.value = random_value - self.assertEqual(await self.dut.LPF_Accum_F1.status_data.read(), random_field_value) + self.assertEqual(await self.dut.LPF_Accum_F1.data.read(), random_field_value) # update the field value via the backdoor in the simulator previous_register_value = random_value random_field_value = random.randrange(0, 0xFFFFFFFF+1) sim_field.value = random_field_value self.assertEqual(sim_register.value, (previous_register_value & 0x0) | (random_field_value << 0)) - self.assertEqual(await self.dut.LPF_Accum_F1.status_data.read(), random_field_value) + self.assertEqual(await self.dut.LPF_Accum_F1.data.read(), random_field_value) # hook up the call backs to check they work correctly random_value = random.randrange(0, 0xFFFFFFFF+1) random_field_value = (random_value & 0xFFFFFFFF) >> 0 @@ -5802,7 +6284,7 @@ async def test_field_read_and_write(self) -> None: sim_register.write_callback = register_write_callback sim_field.read_callback = field_read_callback sim_field.write_callback = field_write_callback - self.assertEqual(await self.dut.LPF_Accum_F1.status_data.read(), random_field_value) + self.assertEqual(await self.dut.LPF_Accum_F1.data.read(), random_field_value) register_write_callback.assert_not_called() register_read_callback.assert_called_once_with(value=random_value) field_write_callback.assert_not_called() @@ -5822,87 +6304,68 @@ async def test_field_read_and_write(self) -> None: sim_register.value = random_value - self.assertEqual(await self.dut.LPF_Accum_F1.status_data.read(), random_field_value) + self.assertEqual(await self.dut.LPF_Accum_F1.data.read(), random_field_value) register_write_callback.assert_not_called() register_read_callback.assert_not_called() field_write_callback.assert_not_called() field_read_callback.assert_not_called() + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value - - # test access operations (read and/or write) to register: - # msk_top_regs.LPF_Accum_F2.status_data - with self.subTest(msg='field: msk_top_regs.LPF_Accum_F2.status_data'): - sim_register = self.sim.register_by_full_name('msk_top_regs.LPF_Accum_F2') - self.assertIsInstance(sim_register, (Register,MemoryRegister)) - sim_field = self.sim.field_by_full_name('msk_top_regs.LPF_Accum_F2.status_data') - self.assertIsInstance(sim_field, Field) - register_read_callback = Mock() - register_write_callback = Mock() - field_read_callback = Mock() - field_write_callback = Mock() - - # register read checks - # update the register value via the backdoor in the simulator - random_value = random.randrange(0, 0xFFFFFFFF+1) - random_field_value = (random_value & 0xFFFFFFFF) >> 0 - - - sim_register.value = random_value - self.assertEqual(await self.dut.LPF_Accum_F2.status_data.read(), random_field_value) - # update the field value via the backdoor in the simulator - previous_register_value = random_value random_field_value = random.randrange(0, 0xFFFFFFFF+1) - sim_field.value = random_field_value - self.assertEqual(sim_register.value, (previous_register_value & 0x0) | (random_field_value << 0)) - self.assertEqual(await self.dut.LPF_Accum_F2.status_data.read(), random_field_value) - # hook up the call backs to check they work correctly - random_value = random.randrange(0, 0xFFFFFFFF+1) - random_field_value = (random_value & 0xFFFFFFFF) >> 0 - + await self.dut.LPF_Accum_F1.data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) - sim_register.value = random_value - sim_register.read_callback = register_read_callback - sim_register.write_callback = register_write_callback - sim_field.read_callback = field_read_callback - sim_field.write_callback = field_write_callback - self.assertEqual(await self.dut.LPF_Accum_F2.status_data.read(), random_field_value) register_write_callback.assert_not_called() - register_read_callback.assert_called_once_with(value=random_value) + register_read_callback.assert_not_called() field_write_callback.assert_not_called() - field_read_callback.assert_called_once_with(value=random_field_value) + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.LPF_Accum_F1.data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + field_write_callback.assert_called_once_with(value=random_field_value) + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value # revert the callbacks and check again register_write_callback.reset_mock() register_read_callback.reset_mock() field_write_callback.reset_mock() field_read_callback.reset_mock() - sim_register.read_callback = None sim_register.write_callback = None - sim_field.read_callback = None sim_field.write_callback = None - random_value = random.randrange(0, 0xFFFFFFFF+1) - random_field_value = (random_value & 0xFFFFFFFF) >> 0 - + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.LPF_Accum_F1.data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) - sim_register.value = random_value - self.assertEqual(await self.dut.LPF_Accum_F2.status_data.read(), random_field_value) register_write_callback.assert_not_called() register_read_callback.assert_not_called() field_write_callback.assert_not_called() field_read_callback.assert_not_called() - - # test access operations (read and/or write) to register: - # msk_top_regs.axis_xfer_count.xfer_count - with self.subTest(msg='field: msk_top_regs.axis_xfer_count.xfer_count'): - sim_register = self.sim.register_by_full_name('msk_top_regs.axis_xfer_count') + # msk_top_regs.LPF_Accum_F2.data + with self.subTest(msg='field: msk_top_regs.LPF_Accum_F2.data'): + sim_register = self.sim.register_by_full_name('msk_top_regs.LPF_Accum_F2') self.assertIsInstance(sim_register, (Register,MemoryRegister)) - sim_field = self.sim.field_by_full_name('msk_top_regs.axis_xfer_count.xfer_count') + sim_field = self.sim.field_by_full_name('msk_top_regs.LPF_Accum_F2.data') self.assertIsInstance(sim_field, Field) register_read_callback = Mock() register_write_callback = Mock() @@ -5916,14 +6379,14 @@ async def test_field_read_and_write(self) -> None: sim_register.value = random_value - self.assertEqual(await self.dut.axis_xfer_count.xfer_count.read(), random_field_value) + self.assertEqual(await self.dut.LPF_Accum_F2.data.read(), random_field_value) # update the field value via the backdoor in the simulator previous_register_value = random_value random_field_value = random.randrange(0, 0xFFFFFFFF+1) sim_field.value = random_field_value self.assertEqual(sim_register.value, (previous_register_value & 0x0) | (random_field_value << 0)) - self.assertEqual(await self.dut.axis_xfer_count.xfer_count.read(), random_field_value) + self.assertEqual(await self.dut.LPF_Accum_F2.data.read(), random_field_value) # hook up the call backs to check they work correctly random_value = random.randrange(0, 0xFFFFFFFF+1) random_field_value = (random_value & 0xFFFFFFFF) >> 0 @@ -5934,7 +6397,7 @@ async def test_field_read_and_write(self) -> None: sim_register.write_callback = register_write_callback sim_field.read_callback = field_read_callback sim_field.write_callback = field_write_callback - self.assertEqual(await self.dut.axis_xfer_count.xfer_count.read(), random_field_value) + self.assertEqual(await self.dut.LPF_Accum_F2.data.read(), random_field_value) register_write_callback.assert_not_called() register_read_callback.assert_called_once_with(value=random_value) field_write_callback.assert_not_called() @@ -5954,18 +6417,178 @@ async def test_field_read_and_write(self) -> None: sim_register.value = random_value - self.assertEqual(await self.dut.axis_xfer_count.xfer_count.read(), random_field_value) + self.assertEqual(await self.dut.LPF_Accum_F2.data.read(), random_field_value) register_write_callback.assert_not_called() register_read_callback.assert_not_called() field_write_callback.assert_not_called() field_read_callback.assert_not_called() + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value - - # test access operations (read and/or write) to register: - # msk_top_regs.Rx_Sample_Discard.rx_sample_discard - with self.subTest(msg='field: msk_top_regs.Rx_Sample_Discard.rx_sample_discard'): + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.LPF_Accum_F2.data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.LPF_Accum_F2.data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + field_write_callback.assert_called_once_with(value=random_field_value) + + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.write_callback = None + sim_field.write_callback = None + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.LPF_Accum_F2.data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # test access operations (read and/or write) to register: + # msk_top_regs.axis_xfer_count.data + with self.subTest(msg='field: msk_top_regs.axis_xfer_count.data'): + sim_register = self.sim.register_by_full_name('msk_top_regs.axis_xfer_count') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.axis_xfer_count.data') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.axis_xfer_count.data.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0x0) | (random_field_value << 0)) + + self.assertEqual(await self.dut.axis_xfer_count.data.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.axis_xfer_count.data.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFFFFFFFF) >> 0 + + + sim_register.value = random_value + self.assertEqual(await self.dut.axis_xfer_count.data.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value + + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.axis_xfer_count.data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.axis_xfer_count.data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + field_write_callback.assert_called_once_with(value=random_field_value) + + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.write_callback = None + sim_field.write_callback = None + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.axis_xfer_count.data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # test access operations (read and/or write) to register: + # msk_top_regs.Rx_Sample_Discard.rx_sample_discard + with self.subTest(msg='field: msk_top_regs.Rx_Sample_Discard.rx_sample_discard'): sim_register = self.sim.register_by_full_name('msk_top_regs.Rx_Sample_Discard') self.assertIsInstance(sim_register, (Register,MemoryRegister)) sim_field = self.sim.field_by_full_name('msk_top_regs.Rx_Sample_Discard.rx_sample_discard') @@ -6479,6 +7102,53 @@ async def test_field_read_and_write(self) -> None: field_read_callback.assert_not_called() + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value + + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.f1_nco_adjust.data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.f1_nco_adjust.data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + field_write_callback.assert_called_once_with(value=random_field_value) + + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.write_callback = None + sim_field.write_callback = None + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.f1_nco_adjust.data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() # test access operations (read and/or write) to register: @@ -6545,6 +7215,53 @@ async def test_field_read_and_write(self) -> None: field_read_callback.assert_not_called() + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value + + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.f2_nco_adjust.data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.f2_nco_adjust.data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + field_write_callback.assert_called_once_with(value=random_field_value) + + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.write_callback = None + sim_field.write_callback = None + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.f2_nco_adjust.data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() # test access operations (read and/or write) to register: @@ -6611,6 +7328,53 @@ async def test_field_read_and_write(self) -> None: field_read_callback.assert_not_called() + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value + + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.f1_error.data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.f1_error.data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + field_write_callback.assert_called_once_with(value=random_field_value) + + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.write_callback = None + sim_field.write_callback = None + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.f1_error.data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() # test access operations (read and/or write) to register: @@ -6677,6 +7441,53 @@ async def test_field_read_and_write(self) -> None: field_read_callback.assert_not_called() + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value + + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.f2_error.data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.f2_error.data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + field_write_callback.assert_called_once_with(value=random_field_value) + + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.write_callback = None + sim_field.write_callback = None + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.f2_error.data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() # test access operations (read and/or write) to register: @@ -7495,11 +8306,11 @@ async def test_field_read_and_write(self) -> None: # test access operations (read and/or write) to register: - # msk_top_regs.rx_power.rx_power - with self.subTest(msg='field: msk_top_regs.rx_power.rx_power'): + # msk_top_regs.rx_power.data + with self.subTest(msg='field: msk_top_regs.rx_power.data'): sim_register = self.sim.register_by_full_name('msk_top_regs.rx_power') self.assertIsInstance(sim_register, (Register,MemoryRegister)) - sim_field = self.sim.field_by_full_name('msk_top_regs.rx_power.rx_power') + sim_field = self.sim.field_by_full_name('msk_top_regs.rx_power.data') self.assertIsInstance(sim_field, Field) register_read_callback = Mock() register_write_callback = Mock() @@ -7513,14 +8324,14 @@ async def test_field_read_and_write(self) -> None: sim_register.value = random_value - self.assertEqual(await self.dut.rx_power.rx_power.read(), random_field_value) + self.assertEqual(await self.dut.rx_power.data.read(), random_field_value) # update the field value via the backdoor in the simulator previous_register_value = random_value random_field_value = random.randrange(0, 0x7FFFFF+1) sim_field.value = random_field_value self.assertEqual(sim_register.value, (previous_register_value & 0xFF800000) | (random_field_value << 0)) - self.assertEqual(await self.dut.rx_power.rx_power.read(), random_field_value) + self.assertEqual(await self.dut.rx_power.data.read(), random_field_value) # hook up the call backs to check they work correctly random_value = random.randrange(0, 0xFFFFFFFF+1) random_field_value = (random_value & 0x7FFFFF) >> 0 @@ -7531,7 +8342,7 @@ async def test_field_read_and_write(self) -> None: sim_register.write_callback = register_write_callback sim_field.read_callback = field_read_callback sim_field.write_callback = field_write_callback - self.assertEqual(await self.dut.rx_power.rx_power.read(), random_field_value) + self.assertEqual(await self.dut.rx_power.data.read(), random_field_value) register_write_callback.assert_not_called() register_read_callback.assert_called_once_with(value=random_value) field_write_callback.assert_not_called() @@ -7551,13 +8362,60 @@ async def test_field_read_and_write(self) -> None: sim_register.value = random_value - self.assertEqual(await self.dut.rx_power.rx_power.read(), random_field_value) + self.assertEqual(await self.dut.rx_power.data.read(), random_field_value) register_write_callback.assert_not_called() register_read_callback.assert_not_called() field_write_callback.assert_not_called() field_read_callback.assert_not_called() + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value + + random_field_value = random.randrange(0, 0x7FFFFF+1) + + await self.dut.rx_power.data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFF800000) | (0x7FFFFF & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0x7FFFFF+1) + + await self.dut.rx_power.data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFF800000) | (0x7FFFFF & (random_field_value << 0))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0xFF800000) | (0x7FFFFF & (random_field_value << 0))) + field_write_callback.assert_called_once_with(value=random_field_value) + + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.write_callback = None + sim_field.write_callback = None + random_field_value = random.randrange(0, 0x7FFFFF+1) + + await self.dut.rx_power.data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFF800000) | (0x7FFFFF & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() # test access operations (read and/or write) to register: @@ -7624,6 +8482,53 @@ async def test_field_read_and_write(self) -> None: field_read_callback.assert_not_called() + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value + + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.tx_async_fifo_rd_wr_ptr.data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.tx_async_fifo_rd_wr_ptr.data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + field_write_callback.assert_called_once_with(value=random_field_value) + + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.write_callback = None + sim_field.write_callback = None + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.tx_async_fifo_rd_wr_ptr.data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() # test access operations (read and/or write) to register: @@ -7690,6 +8595,53 @@ async def test_field_read_and_write(self) -> None: field_read_callback.assert_not_called() + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value + + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.rx_async_fifo_rd_wr_ptr.data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.rx_async_fifo_rd_wr_ptr.data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + field_write_callback.assert_called_once_with(value=random_field_value) + + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.write_callback = None + sim_field.write_callback = None + random_field_value = random.randrange(0, 0xFFFFFFFF+1) + + await self.dut.rx_async_fifo_rd_wr_ptr.data.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x0) | (0xFFFFFFFF & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() diff --git a/rdl/outputs/rtl/msk_top_regs.vhd b/rdl/outputs/rtl/msk_top_regs.vhd index dc0d5cb..12e679f 100644 --- a/rdl/outputs/rtl/msk_top_regs.vhd +++ b/rdl/outputs/rtl/msk_top_regs.vhd @@ -70,10 +70,6 @@ architecture rtl of msk_top_regs is signal axil_resp_buffer : axil_resp_buffer_array_t(1 downto 0); signal axil_resp_wptr : unsigned(1 downto 0); signal axil_resp_rptr : unsigned(1 downto 0); - signal external_req : std_logic; - signal external_pending : std_logic; - signal external_wr_ack : std_logic; - signal external_rd_ack : std_logic; ---------------------------------------------------------------------------- -- Address Decode Signals @@ -119,8 +115,6 @@ architecture rtl of msk_top_regs is rx_async_fifo_rd_wr_ptr : std_logic; end record; signal decoded_reg_strb : decoded_reg_strb_t; - signal decoded_strb_is_external : std_logic; - signal decoded_req : std_logic; signal decoded_req_is_wr : std_logic; signal decoded_wr_data : std_logic_vector(31 downto 0); @@ -184,6 +178,24 @@ architecture rtl of msk_top_regs is diff_encoder_loopback : \msk_top_regs.MSK_Control.diff_encoder_loopback_combo_t\; end record; + type \msk_top_regs.Tx_Bit_Count.data_combo_t\ is record + next_q : std_logic_vector(31 downto 0); + load_next : std_logic; + end record; + + type \msk_top_regs.Tx_Bit_Count_combo_t\ is record + data : \msk_top_regs.Tx_Bit_Count.data_combo_t\; + end record; + + type \msk_top_regs.Tx_Enable_Count.data_combo_t\ is record + next_q : std_logic_vector(31 downto 0); + load_next : std_logic; + end record; + + type \msk_top_regs.Tx_Enable_Count_combo_t\ is record + data : \msk_top_regs.Tx_Enable_Count.data_combo_t\; + end record; + type \msk_top_regs.Fb_FreqWord.config_data_combo_t\ is record next_q : std_logic_vector(31 downto 0); load_next : std_logic; @@ -355,6 +367,51 @@ architecture rtl of msk_top_regs is config_data : \msk_top_regs.PRBS_Error_Mask.config_data_combo_t\; end record; + type \msk_top_regs.PRBS_Bit_Count.data_combo_t\ is record + next_q : std_logic_vector(31 downto 0); + load_next : std_logic; + end record; + + type \msk_top_regs.PRBS_Bit_Count_combo_t\ is record + data : \msk_top_regs.PRBS_Bit_Count.data_combo_t\; + end record; + + type \msk_top_regs.PRBS_Error_Count.data_combo_t\ is record + next_q : std_logic_vector(31 downto 0); + load_next : std_logic; + end record; + + type \msk_top_regs.PRBS_Error_Count_combo_t\ is record + data : \msk_top_regs.PRBS_Error_Count.data_combo_t\; + end record; + + type \msk_top_regs.LPF_Accum_F1.data_combo_t\ is record + next_q : std_logic_vector(31 downto 0); + load_next : std_logic; + end record; + + type \msk_top_regs.LPF_Accum_F1_combo_t\ is record + data : \msk_top_regs.LPF_Accum_F1.data_combo_t\; + end record; + + type \msk_top_regs.LPF_Accum_F2.data_combo_t\ is record + next_q : std_logic_vector(31 downto 0); + load_next : std_logic; + end record; + + type \msk_top_regs.LPF_Accum_F2_combo_t\ is record + data : \msk_top_regs.LPF_Accum_F2.data_combo_t\; + end record; + + type \msk_top_regs.axis_xfer_count.data_combo_t\ is record + next_q : std_logic_vector(31 downto 0); + load_next : std_logic; + end record; + + type \msk_top_regs.axis_xfer_count_combo_t\ is record + data : \msk_top_regs.axis_xfer_count.data_combo_t\; + end record; + type \msk_top_regs.Rx_Sample_Discard.rx_sample_discard_combo_t\ is record next_q : std_logic_vector(7 downto 0); load_next : std_logic; @@ -385,6 +442,42 @@ architecture rtl of msk_top_regs is p_shift : \msk_top_regs.LPF_Config_2.p_shift_combo_t\; end record; + type \msk_top_regs.f1_nco_adjust.data_combo_t\ is record + next_q : std_logic_vector(31 downto 0); + load_next : std_logic; + end record; + + type \msk_top_regs.f1_nco_adjust_combo_t\ is record + data : \msk_top_regs.f1_nco_adjust.data_combo_t\; + end record; + + type \msk_top_regs.f2_nco_adjust.data_combo_t\ is record + next_q : std_logic_vector(31 downto 0); + load_next : std_logic; + end record; + + type \msk_top_regs.f2_nco_adjust_combo_t\ is record + data : \msk_top_regs.f2_nco_adjust.data_combo_t\; + end record; + + type \msk_top_regs.f1_error.data_combo_t\ is record + next_q : std_logic_vector(31 downto 0); + load_next : std_logic; + end record; + + type \msk_top_regs.f1_error_combo_t\ is record + data : \msk_top_regs.f1_error.data_combo_t\; + end record; + + type \msk_top_regs.f2_error.data_combo_t\ is record + next_q : std_logic_vector(31 downto 0); + load_next : std_logic; + end record; + + type \msk_top_regs.f2_error_combo_t\ is record + data : \msk_top_regs.f2_error.data_combo_t\; + end record; + type \msk_top_regs.Tx_Sync_Ctrl.tx_sync_ena_combo_t\ is record next_q : std_logic; load_next : std_logic; @@ -439,9 +532,38 @@ architecture rtl of msk_top_regs is alpha : \msk_top_regs.lowpass_ema_alpha2.alpha_combo_t\; end record; + type \msk_top_regs.rx_power.data_combo_t\ is record + next_q : std_logic_vector(22 downto 0); + load_next : std_logic; + end record; + + type \msk_top_regs.rx_power_combo_t\ is record + data : \msk_top_regs.rx_power.data_combo_t\; + end record; + + type \msk_top_regs.tx_async_fifo_rd_wr_ptr.data_combo_t\ is record + next_q : std_logic_vector(31 downto 0); + load_next : std_logic; + end record; + + type \msk_top_regs.tx_async_fifo_rd_wr_ptr_combo_t\ is record + data : \msk_top_regs.tx_async_fifo_rd_wr_ptr.data_combo_t\; + end record; + + type \msk_top_regs.rx_async_fifo_rd_wr_ptr.data_combo_t\ is record + next_q : std_logic_vector(31 downto 0); + load_next : std_logic; + end record; + + type \msk_top_regs.rx_async_fifo_rd_wr_ptr_combo_t\ is record + data : \msk_top_regs.rx_async_fifo_rd_wr_ptr.data_combo_t\; + end record; + type field_combo_t is record MSK_Init : \msk_top_regs.MSK_Init_combo_t\; MSK_Control : \msk_top_regs.MSK_Control_combo_t\; + Tx_Bit_Count : \msk_top_regs.Tx_Bit_Count_combo_t\; + Tx_Enable_Count : \msk_top_regs.Tx_Enable_Count_combo_t\; Fb_FreqWord : \msk_top_regs.Fb_FreqWord_combo_t\; TX_F1_FreqWord : \msk_top_regs.TX_F1_FreqWord_combo_t\; TX_F2_FreqWord : \msk_top_regs.TX_F2_FreqWord_combo_t\; @@ -455,12 +577,24 @@ architecture rtl of msk_top_regs is PRBS_Initial_State : \msk_top_regs.PRBS_Initial_State_combo_t\; PRBS_Polynomial : \msk_top_regs.PRBS_Polynomial_combo_t\; PRBS_Error_Mask : \msk_top_regs.PRBS_Error_Mask_combo_t\; + PRBS_Bit_Count : \msk_top_regs.PRBS_Bit_Count_combo_t\; + PRBS_Error_Count : \msk_top_regs.PRBS_Error_Count_combo_t\; + LPF_Accum_F1 : \msk_top_regs.LPF_Accum_F1_combo_t\; + LPF_Accum_F2 : \msk_top_regs.LPF_Accum_F2_combo_t\; + axis_xfer_count : \msk_top_regs.axis_xfer_count_combo_t\; Rx_Sample_Discard : \msk_top_regs.Rx_Sample_Discard_combo_t\; LPF_Config_2 : \msk_top_regs.LPF_Config_2_combo_t\; + f1_nco_adjust : \msk_top_regs.f1_nco_adjust_combo_t\; + f2_nco_adjust : \msk_top_regs.f2_nco_adjust_combo_t\; + f1_error : \msk_top_regs.f1_error_combo_t\; + f2_error : \msk_top_regs.f2_error_combo_t\; Tx_Sync_Ctrl : \msk_top_regs.Tx_Sync_Ctrl_combo_t\; Tx_Sync_Cnt : \msk_top_regs.Tx_Sync_Cnt_combo_t\; lowpass_ema_alpha1 : \msk_top_regs.lowpass_ema_alpha1_combo_t\; lowpass_ema_alpha2 : \msk_top_regs.lowpass_ema_alpha2_combo_t\; + rx_power : \msk_top_regs.rx_power_combo_t\; + tx_async_fifo_rd_wr_ptr : \msk_top_regs.tx_async_fifo_rd_wr_ptr_combo_t\; + rx_async_fifo_rd_wr_ptr : \msk_top_regs.rx_async_fifo_rd_wr_ptr_combo_t\; end record; signal field_combo : field_combo_t; @@ -511,6 +645,22 @@ architecture rtl of msk_top_regs is diff_encoder_loopback : \msk_top_regs.MSK_Control.diff_encoder_loopback_storage_t\; end record; + type \msk_top_regs.Tx_Bit_Count.data_storage_t\ is record + value : std_logic_vector(31 downto 0); + end record; + + type \msk_top_regs.Tx_Bit_Count_storage_t\ is record + data : \msk_top_regs.Tx_Bit_Count.data_storage_t\; + end record; + + type \msk_top_regs.Tx_Enable_Count.data_storage_t\ is record + value : std_logic_vector(31 downto 0); + end record; + + type \msk_top_regs.Tx_Enable_Count_storage_t\ is record + data : \msk_top_regs.Tx_Enable_Count.data_storage_t\; + end record; + type \msk_top_regs.Fb_FreqWord.config_data_storage_t\ is record value : std_logic_vector(31 downto 0); end record; @@ -660,6 +810,46 @@ architecture rtl of msk_top_regs is config_data : \msk_top_regs.PRBS_Error_Mask.config_data_storage_t\; end record; + type \msk_top_regs.PRBS_Bit_Count.data_storage_t\ is record + value : std_logic_vector(31 downto 0); + end record; + + type \msk_top_regs.PRBS_Bit_Count_storage_t\ is record + data : \msk_top_regs.PRBS_Bit_Count.data_storage_t\; + end record; + + type \msk_top_regs.PRBS_Error_Count.data_storage_t\ is record + value : std_logic_vector(31 downto 0); + end record; + + type \msk_top_regs.PRBS_Error_Count_storage_t\ is record + data : \msk_top_regs.PRBS_Error_Count.data_storage_t\; + end record; + + type \msk_top_regs.LPF_Accum_F1.data_storage_t\ is record + value : std_logic_vector(31 downto 0); + end record; + + type \msk_top_regs.LPF_Accum_F1_storage_t\ is record + data : \msk_top_regs.LPF_Accum_F1.data_storage_t\; + end record; + + type \msk_top_regs.LPF_Accum_F2.data_storage_t\ is record + value : std_logic_vector(31 downto 0); + end record; + + type \msk_top_regs.LPF_Accum_F2_storage_t\ is record + data : \msk_top_regs.LPF_Accum_F2.data_storage_t\; + end record; + + type \msk_top_regs.axis_xfer_count.data_storage_t\ is record + value : std_logic_vector(31 downto 0); + end record; + + type \msk_top_regs.axis_xfer_count_storage_t\ is record + data : \msk_top_regs.axis_xfer_count.data_storage_t\; + end record; + type \msk_top_regs.Rx_Sample_Discard.rx_sample_discard_storage_t\ is record value : std_logic_vector(7 downto 0); end record; @@ -686,6 +876,38 @@ architecture rtl of msk_top_regs is p_shift : \msk_top_regs.LPF_Config_2.p_shift_storage_t\; end record; + type \msk_top_regs.f1_nco_adjust.data_storage_t\ is record + value : std_logic_vector(31 downto 0); + end record; + + type \msk_top_regs.f1_nco_adjust_storage_t\ is record + data : \msk_top_regs.f1_nco_adjust.data_storage_t\; + end record; + + type \msk_top_regs.f2_nco_adjust.data_storage_t\ is record + value : std_logic_vector(31 downto 0); + end record; + + type \msk_top_regs.f2_nco_adjust_storage_t\ is record + data : \msk_top_regs.f2_nco_adjust.data_storage_t\; + end record; + + type \msk_top_regs.f1_error.data_storage_t\ is record + value : std_logic_vector(31 downto 0); + end record; + + type \msk_top_regs.f1_error_storage_t\ is record + data : \msk_top_regs.f1_error.data_storage_t\; + end record; + + type \msk_top_regs.f2_error.data_storage_t\ is record + value : std_logic_vector(31 downto 0); + end record; + + type \msk_top_regs.f2_error_storage_t\ is record + data : \msk_top_regs.f2_error.data_storage_t\; + end record; + type \msk_top_regs.Tx_Sync_Ctrl.tx_sync_ena_storage_t\ is record value : std_logic; end record; @@ -733,9 +955,35 @@ architecture rtl of msk_top_regs is alpha : \msk_top_regs.lowpass_ema_alpha2.alpha_storage_t\; end record; + type \msk_top_regs.rx_power.data_storage_t\ is record + value : std_logic_vector(22 downto 0); + end record; + + type \msk_top_regs.rx_power_storage_t\ is record + data : \msk_top_regs.rx_power.data_storage_t\; + end record; + + type \msk_top_regs.tx_async_fifo_rd_wr_ptr.data_storage_t\ is record + value : std_logic_vector(31 downto 0); + end record; + + type \msk_top_regs.tx_async_fifo_rd_wr_ptr_storage_t\ is record + data : \msk_top_regs.tx_async_fifo_rd_wr_ptr.data_storage_t\; + end record; + + type \msk_top_regs.rx_async_fifo_rd_wr_ptr.data_storage_t\ is record + value : std_logic_vector(31 downto 0); + end record; + + type \msk_top_regs.rx_async_fifo_rd_wr_ptr_storage_t\ is record + data : \msk_top_regs.rx_async_fifo_rd_wr_ptr.data_storage_t\; + end record; + type field_storage_t is record MSK_Init : \msk_top_regs.MSK_Init_storage_t\; MSK_Control : \msk_top_regs.MSK_Control_storage_t\; + Tx_Bit_Count : \msk_top_regs.Tx_Bit_Count_storage_t\; + Tx_Enable_Count : \msk_top_regs.Tx_Enable_Count_storage_t\; Fb_FreqWord : \msk_top_regs.Fb_FreqWord_storage_t\; TX_F1_FreqWord : \msk_top_regs.TX_F1_FreqWord_storage_t\; TX_F2_FreqWord : \msk_top_regs.TX_F2_FreqWord_storage_t\; @@ -749,20 +997,30 @@ architecture rtl of msk_top_regs is PRBS_Initial_State : \msk_top_regs.PRBS_Initial_State_storage_t\; PRBS_Polynomial : \msk_top_regs.PRBS_Polynomial_storage_t\; PRBS_Error_Mask : \msk_top_regs.PRBS_Error_Mask_storage_t\; + PRBS_Bit_Count : \msk_top_regs.PRBS_Bit_Count_storage_t\; + PRBS_Error_Count : \msk_top_regs.PRBS_Error_Count_storage_t\; + LPF_Accum_F1 : \msk_top_regs.LPF_Accum_F1_storage_t\; + LPF_Accum_F2 : \msk_top_regs.LPF_Accum_F2_storage_t\; + axis_xfer_count : \msk_top_regs.axis_xfer_count_storage_t\; Rx_Sample_Discard : \msk_top_regs.Rx_Sample_Discard_storage_t\; LPF_Config_2 : \msk_top_regs.LPF_Config_2_storage_t\; + f1_nco_adjust : \msk_top_regs.f1_nco_adjust_storage_t\; + f2_nco_adjust : \msk_top_regs.f2_nco_adjust_storage_t\; + f1_error : \msk_top_regs.f1_error_storage_t\; + f2_error : \msk_top_regs.f2_error_storage_t\; Tx_Sync_Ctrl : \msk_top_regs.Tx_Sync_Ctrl_storage_t\; Tx_Sync_Cnt : \msk_top_regs.Tx_Sync_Cnt_storage_t\; lowpass_ema_alpha1 : \msk_top_regs.lowpass_ema_alpha1_storage_t\; lowpass_ema_alpha2 : \msk_top_regs.lowpass_ema_alpha2_storage_t\; + rx_power : \msk_top_regs.rx_power_storage_t\; + tx_async_fifo_rd_wr_ptr : \msk_top_regs.tx_async_fifo_rd_wr_ptr_storage_t\; + rx_async_fifo_rd_wr_ptr : \msk_top_regs.rx_async_fifo_rd_wr_ptr_storage_t\; end record; signal field_storage : field_storage_t; ---------------------------------------------------------------------------- -- Readback Signals ---------------------------------------------------------------------------- - signal readback_external_rd_ack_c : std_logic; - signal readback_external_rd_ack : std_logic; signal readback_err : std_logic; signal readback_done : std_logic; signal readback_data : std_logic_vector(31 downto 0); @@ -960,32 +1218,10 @@ begin s_axil_o.RRESP <= "00"; end if; end process; - process(clk) begin - if false then -- async reset - external_pending <= '0'; - elsif rising_edge(clk) then - if rst then -- sync reset - external_pending <= '0'; - else - if external_req and not external_wr_ack and not external_rd_ack then - external_pending <= '1'; - elsif external_wr_ack or external_rd_ack then - external_pending <= '0'; - end if; - --pragma translate_off - assert_bad_ext_wr_ack: assert not external_wr_ack or (external_pending or external_req) - report "An external wr_ack strobe was asserted when no external request was active"; - assert_bad_ext_rd_ack: assert not external_rd_ack or (external_pending or external_req) - report "An external rd_ack strobe was asserted when no external request was active"; - --pragma translate_on - end if; - end if; - end process; -- Read & write latencies are balanced. Stalls not required - -- except if external - cpuif_req_stall_rd <= external_pending; - cpuif_req_stall_wr <= external_pending; + cpuif_req_stall_rd <= '0'; + cpuif_req_stall_wr <= '0'; cpuif_req_masked <= cpuif_req and not (not cpuif_req_is_wr and cpuif_req_stall_rd) and not (cpuif_req_is_wr and cpuif_req_stall_wr); @@ -1001,18 +1237,14 @@ begin result := '1' when unsigned(L) = R else '0'; return result; end; - variable is_external: std_logic; begin - is_external := '0'; decoded_reg_strb.Hash_ID_Low <= cpuif_req_masked and (cpuif_addr = 16#0#); decoded_reg_strb.Hash_ID_High <= cpuif_req_masked and (cpuif_addr = 16#4#); decoded_reg_strb.MSK_Init <= cpuif_req_masked and (cpuif_addr = 16#8#); decoded_reg_strb.MSK_Control <= cpuif_req_masked and (cpuif_addr = 16#C#); decoded_reg_strb.MSK_Status <= cpuif_req_masked and (cpuif_addr = 16#10#); decoded_reg_strb.Tx_Bit_Count <= cpuif_req_masked and (cpuif_addr = 16#14#); - is_external := is_external or ((cpuif_req_masked and (cpuif_addr = 16#14#)) and not cpuif_req_is_wr); decoded_reg_strb.Tx_Enable_Count <= cpuif_req_masked and (cpuif_addr = 16#18#); - is_external := is_external or ((cpuif_req_masked and (cpuif_addr = 16#18#)) and not cpuif_req_is_wr); decoded_reg_strb.Fb_FreqWord <= cpuif_req_masked and (cpuif_addr = 16#1C#); decoded_reg_strb.TX_F1_FreqWord <= cpuif_req_masked and (cpuif_addr = 16#20#); decoded_reg_strb.TX_F2_FreqWord <= cpuif_req_masked and (cpuif_addr = 16#24#); @@ -1027,37 +1259,23 @@ begin decoded_reg_strb.PRBS_Polynomial <= cpuif_req_masked and (cpuif_addr = 16#48#); decoded_reg_strb.PRBS_Error_Mask <= cpuif_req_masked and (cpuif_addr = 16#4C#); decoded_reg_strb.PRBS_Bit_Count <= cpuif_req_masked and (cpuif_addr = 16#50#); - is_external := is_external or ((cpuif_req_masked and (cpuif_addr = 16#50#)) and not cpuif_req_is_wr); decoded_reg_strb.PRBS_Error_Count <= cpuif_req_masked and (cpuif_addr = 16#54#); - is_external := is_external or ((cpuif_req_masked and (cpuif_addr = 16#54#)) and not cpuif_req_is_wr); decoded_reg_strb.LPF_Accum_F1 <= cpuif_req_masked and (cpuif_addr = 16#58#); - is_external := is_external or ((cpuif_req_masked and (cpuif_addr = 16#58#)) and not cpuif_req_is_wr); decoded_reg_strb.LPF_Accum_F2 <= cpuif_req_masked and (cpuif_addr = 16#5C#); - is_external := is_external or ((cpuif_req_masked and (cpuif_addr = 16#5C#)) and not cpuif_req_is_wr); decoded_reg_strb.axis_xfer_count <= cpuif_req_masked and (cpuif_addr = 16#60#); - is_external := is_external or ((cpuif_req_masked and (cpuif_addr = 16#60#)) and not cpuif_req_is_wr); decoded_reg_strb.Rx_Sample_Discard <= cpuif_req_masked and (cpuif_addr = 16#64#); decoded_reg_strb.LPF_Config_2 <= cpuif_req_masked and (cpuif_addr = 16#68#); decoded_reg_strb.f1_nco_adjust <= cpuif_req_masked and (cpuif_addr = 16#6C#); - is_external := is_external or ((cpuif_req_masked and (cpuif_addr = 16#6C#)) and not cpuif_req_is_wr); decoded_reg_strb.f2_nco_adjust <= cpuif_req_masked and (cpuif_addr = 16#70#); - is_external := is_external or ((cpuif_req_masked and (cpuif_addr = 16#70#)) and not cpuif_req_is_wr); decoded_reg_strb.f1_error <= cpuif_req_masked and (cpuif_addr = 16#74#); - is_external := is_external or ((cpuif_req_masked and (cpuif_addr = 16#74#)) and not cpuif_req_is_wr); decoded_reg_strb.f2_error <= cpuif_req_masked and (cpuif_addr = 16#78#); - is_external := is_external or ((cpuif_req_masked and (cpuif_addr = 16#78#)) and not cpuif_req_is_wr); decoded_reg_strb.Tx_Sync_Ctrl <= cpuif_req_masked and (cpuif_addr = 16#7C#); decoded_reg_strb.Tx_Sync_Cnt <= cpuif_req_masked and (cpuif_addr = 16#80#); decoded_reg_strb.lowpass_ema_alpha1 <= cpuif_req_masked and (cpuif_addr = 16#84#); decoded_reg_strb.lowpass_ema_alpha2 <= cpuif_req_masked and (cpuif_addr = 16#88#); decoded_reg_strb.rx_power <= cpuif_req_masked and (cpuif_addr = 16#8C#); - is_external := is_external or ((cpuif_req_masked and (cpuif_addr = 16#8C#)) and not cpuif_req_is_wr); decoded_reg_strb.tx_async_fifo_rd_wr_ptr <= cpuif_req_masked and (cpuif_addr = 16#90#); - is_external := is_external or ((cpuif_req_masked and (cpuif_addr = 16#90#)) and not cpuif_req_is_wr); decoded_reg_strb.rx_async_fifo_rd_wr_ptr <= cpuif_req_masked and (cpuif_addr = 16#94#); - is_external := is_external or ((cpuif_req_masked and (cpuif_addr = 16#94#)) and not cpuif_req_is_wr); - decoded_strb_is_external <= is_external; - external_req <= is_external; end process; -- Pass down signals to next stage @@ -1307,11 +1525,69 @@ begin end process; hwif_out.MSK_Control.diff_encoder_loopback.value <= field_storage.MSK_Control.diff_encoder_loopback.value; - hwif_out.Tx_Bit_Count.req <= decoded_reg_strb.Tx_Bit_Count when not decoded_req_is_wr else '0'; - hwif_out.Tx_Bit_Count.req_is_wr <= decoded_req_is_wr; + -- Field: msk_top_regs.Tx_Bit_Count.data + process(all) + variable next_c: std_logic_vector(31 downto 0); + variable load_next_c: std_logic; + begin + next_c := field_storage.Tx_Bit_Count.data.value; + load_next_c := '0'; + if decoded_reg_strb.Tx_Bit_Count and decoded_req_is_wr then -- SW write + next_c := (field_storage.Tx_Bit_Count.data.value and not decoded_wr_biten(31 downto 0)) or (decoded_wr_data(31 downto 0) and decoded_wr_biten(31 downto 0)); + load_next_c := '1'; + elsif hwif_in.Tx_Bit_Count.data.we then -- HW Write - we + next_c := hwif_in.Tx_Bit_Count.data.next_q; + load_next_c := '1'; + end if; + field_combo.Tx_Bit_Count.data.next_q <= next_c; + field_combo.Tx_Bit_Count.data.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.Tx_Bit_Count.data.value <= 32x"0"; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.Tx_Bit_Count.data.value <= 32x"0"; + else + if field_combo.Tx_Bit_Count.data.load_next then + field_storage.Tx_Bit_Count.data.value <= field_combo.Tx_Bit_Count.data.next_q; + end if; + end if; + end if; + end process; + hwif_out.Tx_Bit_Count.data.swmod <= decoded_reg_strb.Tx_Bit_Count and decoded_req_is_wr and or_reduce(decoded_wr_biten(31 downto 0)); - hwif_out.Tx_Enable_Count.req <= decoded_reg_strb.Tx_Enable_Count when not decoded_req_is_wr else '0'; - hwif_out.Tx_Enable_Count.req_is_wr <= decoded_req_is_wr; + -- Field: msk_top_regs.Tx_Enable_Count.data + process(all) + variable next_c: std_logic_vector(31 downto 0); + variable load_next_c: std_logic; + begin + next_c := field_storage.Tx_Enable_Count.data.value; + load_next_c := '0'; + if decoded_reg_strb.Tx_Enable_Count and decoded_req_is_wr then -- SW write + next_c := (field_storage.Tx_Enable_Count.data.value and not decoded_wr_biten(31 downto 0)) or (decoded_wr_data(31 downto 0) and decoded_wr_biten(31 downto 0)); + load_next_c := '1'; + elsif hwif_in.Tx_Enable_Count.data.we then -- HW Write - we + next_c := hwif_in.Tx_Enable_Count.data.next_q; + load_next_c := '1'; + end if; + field_combo.Tx_Enable_Count.data.next_q <= next_c; + field_combo.Tx_Enable_Count.data.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.Tx_Enable_Count.data.value <= 32x"0"; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.Tx_Enable_Count.data.value <= 32x"0"; + else + if field_combo.Tx_Enable_Count.data.load_next then + field_storage.Tx_Enable_Count.data.value <= field_combo.Tx_Enable_Count.data.next_q; + end if; + end if; + end if; + end process; + hwif_out.Tx_Enable_Count.data.swmod <= decoded_reg_strb.Tx_Enable_Count and decoded_req_is_wr and or_reduce(decoded_wr_biten(31 downto 0)); -- Field: msk_top_regs.Fb_FreqWord.config_data process(all) @@ -1960,20 +2236,165 @@ begin end process; hwif_out.PRBS_Error_Mask.config_data.value <= field_storage.PRBS_Error_Mask.config_data.value; - hwif_out.PRBS_Bit_Count.req <= decoded_reg_strb.PRBS_Bit_Count when not decoded_req_is_wr else '0'; - hwif_out.PRBS_Bit_Count.req_is_wr <= decoded_req_is_wr; + -- Field: msk_top_regs.PRBS_Bit_Count.data + process(all) + variable next_c: std_logic_vector(31 downto 0); + variable load_next_c: std_logic; + begin + next_c := field_storage.PRBS_Bit_Count.data.value; + load_next_c := '0'; + if decoded_reg_strb.PRBS_Bit_Count and decoded_req_is_wr then -- SW write + next_c := (field_storage.PRBS_Bit_Count.data.value and not decoded_wr_biten(31 downto 0)) or (decoded_wr_data(31 downto 0) and decoded_wr_biten(31 downto 0)); + load_next_c := '1'; + elsif hwif_in.PRBS_Bit_Count.data.we then -- HW Write - we + next_c := hwif_in.PRBS_Bit_Count.data.next_q; + load_next_c := '1'; + end if; + field_combo.PRBS_Bit_Count.data.next_q <= next_c; + field_combo.PRBS_Bit_Count.data.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.PRBS_Bit_Count.data.value <= 32x"0"; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.PRBS_Bit_Count.data.value <= 32x"0"; + else + if field_combo.PRBS_Bit_Count.data.load_next then + field_storage.PRBS_Bit_Count.data.value <= field_combo.PRBS_Bit_Count.data.next_q; + end if; + end if; + end if; + end process; + hwif_out.PRBS_Bit_Count.data.swmod <= decoded_reg_strb.PRBS_Bit_Count and decoded_req_is_wr and or_reduce(decoded_wr_biten(31 downto 0)); - hwif_out.PRBS_Error_Count.req <= decoded_reg_strb.PRBS_Error_Count when not decoded_req_is_wr else '0'; - hwif_out.PRBS_Error_Count.req_is_wr <= decoded_req_is_wr; + -- Field: msk_top_regs.PRBS_Error_Count.data + process(all) + variable next_c: std_logic_vector(31 downto 0); + variable load_next_c: std_logic; + begin + next_c := field_storage.PRBS_Error_Count.data.value; + load_next_c := '0'; + if decoded_reg_strb.PRBS_Error_Count and decoded_req_is_wr then -- SW write + next_c := (field_storage.PRBS_Error_Count.data.value and not decoded_wr_biten(31 downto 0)) or (decoded_wr_data(31 downto 0) and decoded_wr_biten(31 downto 0)); + load_next_c := '1'; + elsif hwif_in.PRBS_Error_Count.data.we then -- HW Write - we + next_c := hwif_in.PRBS_Error_Count.data.next_q; + load_next_c := '1'; + end if; + field_combo.PRBS_Error_Count.data.next_q <= next_c; + field_combo.PRBS_Error_Count.data.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.PRBS_Error_Count.data.value <= 32x"0"; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.PRBS_Error_Count.data.value <= 32x"0"; + else + if field_combo.PRBS_Error_Count.data.load_next then + field_storage.PRBS_Error_Count.data.value <= field_combo.PRBS_Error_Count.data.next_q; + end if; + end if; + end if; + end process; + hwif_out.PRBS_Error_Count.data.swmod <= decoded_reg_strb.PRBS_Error_Count and decoded_req_is_wr and or_reduce(decoded_wr_biten(31 downto 0)); - hwif_out.LPF_Accum_F1.req <= decoded_reg_strb.LPF_Accum_F1 when not decoded_req_is_wr else '0'; - hwif_out.LPF_Accum_F1.req_is_wr <= decoded_req_is_wr; + -- Field: msk_top_regs.LPF_Accum_F1.data + process(all) + variable next_c: std_logic_vector(31 downto 0); + variable load_next_c: std_logic; + begin + next_c := field_storage.LPF_Accum_F1.data.value; + load_next_c := '0'; + if decoded_reg_strb.LPF_Accum_F1 and decoded_req_is_wr then -- SW write + next_c := (field_storage.LPF_Accum_F1.data.value and not decoded_wr_biten(31 downto 0)) or (decoded_wr_data(31 downto 0) and decoded_wr_biten(31 downto 0)); + load_next_c := '1'; + elsif hwif_in.LPF_Accum_F1.data.we then -- HW Write - we + next_c := hwif_in.LPF_Accum_F1.data.next_q; + load_next_c := '1'; + end if; + field_combo.LPF_Accum_F1.data.next_q <= next_c; + field_combo.LPF_Accum_F1.data.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.LPF_Accum_F1.data.value <= 32x"0"; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.LPF_Accum_F1.data.value <= 32x"0"; + else + if field_combo.LPF_Accum_F1.data.load_next then + field_storage.LPF_Accum_F1.data.value <= field_combo.LPF_Accum_F1.data.next_q; + end if; + end if; + end if; + end process; + hwif_out.LPF_Accum_F1.data.swmod <= decoded_reg_strb.LPF_Accum_F1 and decoded_req_is_wr and or_reduce(decoded_wr_biten(31 downto 0)); - hwif_out.LPF_Accum_F2.req <= decoded_reg_strb.LPF_Accum_F2 when not decoded_req_is_wr else '0'; - hwif_out.LPF_Accum_F2.req_is_wr <= decoded_req_is_wr; + -- Field: msk_top_regs.LPF_Accum_F2.data + process(all) + variable next_c: std_logic_vector(31 downto 0); + variable load_next_c: std_logic; + begin + next_c := field_storage.LPF_Accum_F2.data.value; + load_next_c := '0'; + if decoded_reg_strb.LPF_Accum_F2 and decoded_req_is_wr then -- SW write + next_c := (field_storage.LPF_Accum_F2.data.value and not decoded_wr_biten(31 downto 0)) or (decoded_wr_data(31 downto 0) and decoded_wr_biten(31 downto 0)); + load_next_c := '1'; + elsif hwif_in.LPF_Accum_F2.data.we then -- HW Write - we + next_c := hwif_in.LPF_Accum_F2.data.next_q; + load_next_c := '1'; + end if; + field_combo.LPF_Accum_F2.data.next_q <= next_c; + field_combo.LPF_Accum_F2.data.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.LPF_Accum_F2.data.value <= 32x"0"; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.LPF_Accum_F2.data.value <= 32x"0"; + else + if field_combo.LPF_Accum_F2.data.load_next then + field_storage.LPF_Accum_F2.data.value <= field_combo.LPF_Accum_F2.data.next_q; + end if; + end if; + end if; + end process; + hwif_out.LPF_Accum_F2.data.swmod <= decoded_reg_strb.LPF_Accum_F2 and decoded_req_is_wr and or_reduce(decoded_wr_biten(31 downto 0)); - hwif_out.axis_xfer_count.req <= decoded_reg_strb.axis_xfer_count when not decoded_req_is_wr else '0'; - hwif_out.axis_xfer_count.req_is_wr <= decoded_req_is_wr; + -- Field: msk_top_regs.axis_xfer_count.data + process(all) + variable next_c: std_logic_vector(31 downto 0); + variable load_next_c: std_logic; + begin + next_c := field_storage.axis_xfer_count.data.value; + load_next_c := '0'; + if decoded_reg_strb.axis_xfer_count and decoded_req_is_wr then -- SW write + next_c := (field_storage.axis_xfer_count.data.value and not decoded_wr_biten(31 downto 0)) or (decoded_wr_data(31 downto 0) and decoded_wr_biten(31 downto 0)); + load_next_c := '1'; + elsif hwif_in.axis_xfer_count.data.we then -- HW Write - we + next_c := hwif_in.axis_xfer_count.data.next_q; + load_next_c := '1'; + end if; + field_combo.axis_xfer_count.data.next_q <= next_c; + field_combo.axis_xfer_count.data.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.axis_xfer_count.data.value <= 32x"0"; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.axis_xfer_count.data.value <= 32x"0"; + else + if field_combo.axis_xfer_count.data.load_next then + field_storage.axis_xfer_count.data.value <= field_combo.axis_xfer_count.data.next_q; + end if; + end if; + end if; + end process; + hwif_out.axis_xfer_count.data.swmod <= decoded_reg_strb.axis_xfer_count and decoded_req_is_wr and or_reduce(decoded_wr_biten(31 downto 0)); -- Field: msk_top_regs.Rx_Sample_Discard.rx_sample_discard process(all) @@ -2091,17 +2512,133 @@ begin end process; hwif_out.LPF_Config_2.p_shift.value <= field_storage.LPF_Config_2.p_shift.value; - hwif_out.f1_nco_adjust.req <= decoded_reg_strb.f1_nco_adjust when not decoded_req_is_wr else '0'; - hwif_out.f1_nco_adjust.req_is_wr <= decoded_req_is_wr; + -- Field: msk_top_regs.f1_nco_adjust.data + process(all) + variable next_c: std_logic_vector(31 downto 0); + variable load_next_c: std_logic; + begin + next_c := field_storage.f1_nco_adjust.data.value; + load_next_c := '0'; + if decoded_reg_strb.f1_nco_adjust and decoded_req_is_wr then -- SW write + next_c := (field_storage.f1_nco_adjust.data.value and not decoded_wr_biten(31 downto 0)) or (decoded_wr_data(31 downto 0) and decoded_wr_biten(31 downto 0)); + load_next_c := '1'; + elsif hwif_in.f1_nco_adjust.data.we then -- HW Write - we + next_c := hwif_in.f1_nco_adjust.data.next_q; + load_next_c := '1'; + end if; + field_combo.f1_nco_adjust.data.next_q <= next_c; + field_combo.f1_nco_adjust.data.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.f1_nco_adjust.data.value <= 32x"0"; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.f1_nco_adjust.data.value <= 32x"0"; + else + if field_combo.f1_nco_adjust.data.load_next then + field_storage.f1_nco_adjust.data.value <= field_combo.f1_nco_adjust.data.next_q; + end if; + end if; + end if; + end process; + hwif_out.f1_nco_adjust.data.swmod <= decoded_reg_strb.f1_nco_adjust and decoded_req_is_wr and or_reduce(decoded_wr_biten(31 downto 0)); - hwif_out.f2_nco_adjust.req <= decoded_reg_strb.f2_nco_adjust when not decoded_req_is_wr else '0'; - hwif_out.f2_nco_adjust.req_is_wr <= decoded_req_is_wr; + -- Field: msk_top_regs.f2_nco_adjust.data + process(all) + variable next_c: std_logic_vector(31 downto 0); + variable load_next_c: std_logic; + begin + next_c := field_storage.f2_nco_adjust.data.value; + load_next_c := '0'; + if decoded_reg_strb.f2_nco_adjust and decoded_req_is_wr then -- SW write + next_c := (field_storage.f2_nco_adjust.data.value and not decoded_wr_biten(31 downto 0)) or (decoded_wr_data(31 downto 0) and decoded_wr_biten(31 downto 0)); + load_next_c := '1'; + elsif hwif_in.f2_nco_adjust.data.we then -- HW Write - we + next_c := hwif_in.f2_nco_adjust.data.next_q; + load_next_c := '1'; + end if; + field_combo.f2_nco_adjust.data.next_q <= next_c; + field_combo.f2_nco_adjust.data.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.f2_nco_adjust.data.value <= 32x"0"; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.f2_nco_adjust.data.value <= 32x"0"; + else + if field_combo.f2_nco_adjust.data.load_next then + field_storage.f2_nco_adjust.data.value <= field_combo.f2_nco_adjust.data.next_q; + end if; + end if; + end if; + end process; + hwif_out.f2_nco_adjust.data.swmod <= decoded_reg_strb.f2_nco_adjust and decoded_req_is_wr and or_reduce(decoded_wr_biten(31 downto 0)); - hwif_out.f1_error.req <= decoded_reg_strb.f1_error when not decoded_req_is_wr else '0'; - hwif_out.f1_error.req_is_wr <= decoded_req_is_wr; + -- Field: msk_top_regs.f1_error.data + process(all) + variable next_c: std_logic_vector(31 downto 0); + variable load_next_c: std_logic; + begin + next_c := field_storage.f1_error.data.value; + load_next_c := '0'; + if decoded_reg_strb.f1_error and decoded_req_is_wr then -- SW write + next_c := (field_storage.f1_error.data.value and not decoded_wr_biten(31 downto 0)) or (decoded_wr_data(31 downto 0) and decoded_wr_biten(31 downto 0)); + load_next_c := '1'; + elsif hwif_in.f1_error.data.we then -- HW Write - we + next_c := hwif_in.f1_error.data.next_q; + load_next_c := '1'; + end if; + field_combo.f1_error.data.next_q <= next_c; + field_combo.f1_error.data.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.f1_error.data.value <= 32x"0"; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.f1_error.data.value <= 32x"0"; + else + if field_combo.f1_error.data.load_next then + field_storage.f1_error.data.value <= field_combo.f1_error.data.next_q; + end if; + end if; + end if; + end process; + hwif_out.f1_error.data.swmod <= decoded_reg_strb.f1_error and decoded_req_is_wr and or_reduce(decoded_wr_biten(31 downto 0)); - hwif_out.f2_error.req <= decoded_reg_strb.f2_error when not decoded_req_is_wr else '0'; - hwif_out.f2_error.req_is_wr <= decoded_req_is_wr; + -- Field: msk_top_regs.f2_error.data + process(all) + variable next_c: std_logic_vector(31 downto 0); + variable load_next_c: std_logic; + begin + next_c := field_storage.f2_error.data.value; + load_next_c := '0'; + if decoded_reg_strb.f2_error and decoded_req_is_wr then -- SW write + next_c := (field_storage.f2_error.data.value and not decoded_wr_biten(31 downto 0)) or (decoded_wr_data(31 downto 0) and decoded_wr_biten(31 downto 0)); + load_next_c := '1'; + elsif hwif_in.f2_error.data.we then -- HW Write - we + next_c := hwif_in.f2_error.data.next_q; + load_next_c := '1'; + end if; + field_combo.f2_error.data.next_q <= next_c; + field_combo.f2_error.data.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.f2_error.data.value <= 32x"0"; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.f2_error.data.value <= 32x"0"; + else + if field_combo.f2_error.data.load_next then + field_storage.f2_error.data.value <= field_combo.f2_error.data.next_q; + end if; + end if; + end if; + end process; + hwif_out.f2_error.data.swmod <= decoded_reg_strb.f2_error and decoded_req_is_wr and or_reduce(decoded_wr_biten(31 downto 0)); -- Field: msk_top_regs.Tx_Sync_Ctrl.tx_sync_ena process(all) @@ -2306,54 +2843,112 @@ begin end process; hwif_out.lowpass_ema_alpha2.alpha.value <= field_storage.lowpass_ema_alpha2.alpha.value; - hwif_out.rx_power.req <= decoded_reg_strb.rx_power when not decoded_req_is_wr else '0'; - hwif_out.rx_power.req_is_wr <= decoded_req_is_wr; + -- Field: msk_top_regs.rx_power.data + process(all) + variable next_c: std_logic_vector(22 downto 0); + variable load_next_c: std_logic; + begin + next_c := field_storage.rx_power.data.value; + load_next_c := '0'; + if decoded_reg_strb.rx_power and decoded_req_is_wr then -- SW write + next_c := (field_storage.rx_power.data.value and not decoded_wr_biten(22 downto 0)) or (decoded_wr_data(22 downto 0) and decoded_wr_biten(22 downto 0)); + load_next_c := '1'; + elsif hwif_in.rx_power.data.we then -- HW Write - we + next_c := hwif_in.rx_power.data.next_q; + load_next_c := '1'; + end if; + field_combo.rx_power.data.next_q <= next_c; + field_combo.rx_power.data.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.rx_power.data.value <= 23x"0"; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.rx_power.data.value <= 23x"0"; + else + if field_combo.rx_power.data.load_next then + field_storage.rx_power.data.value <= field_combo.rx_power.data.next_q; + end if; + end if; + end if; + end process; + hwif_out.rx_power.data.swmod <= decoded_reg_strb.rx_power and decoded_req_is_wr and or_reduce(decoded_wr_biten(22 downto 0)); - hwif_out.tx_async_fifo_rd_wr_ptr.req <= decoded_reg_strb.tx_async_fifo_rd_wr_ptr when not decoded_req_is_wr else '0'; - hwif_out.tx_async_fifo_rd_wr_ptr.req_is_wr <= decoded_req_is_wr; + -- Field: msk_top_regs.tx_async_fifo_rd_wr_ptr.data + process(all) + variable next_c: std_logic_vector(31 downto 0); + variable load_next_c: std_logic; + begin + next_c := field_storage.tx_async_fifo_rd_wr_ptr.data.value; + load_next_c := '0'; + if decoded_reg_strb.tx_async_fifo_rd_wr_ptr and decoded_req_is_wr then -- SW write + next_c := (field_storage.tx_async_fifo_rd_wr_ptr.data.value and not decoded_wr_biten(31 downto 0)) or (decoded_wr_data(31 downto 0) and decoded_wr_biten(31 downto 0)); + load_next_c := '1'; + elsif hwif_in.tx_async_fifo_rd_wr_ptr.data.we then -- HW Write - we + next_c := hwif_in.tx_async_fifo_rd_wr_ptr.data.next_q; + load_next_c := '1'; + end if; + field_combo.tx_async_fifo_rd_wr_ptr.data.next_q <= next_c; + field_combo.tx_async_fifo_rd_wr_ptr.data.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.tx_async_fifo_rd_wr_ptr.data.value <= 32x"0"; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.tx_async_fifo_rd_wr_ptr.data.value <= 32x"0"; + else + if field_combo.tx_async_fifo_rd_wr_ptr.data.load_next then + field_storage.tx_async_fifo_rd_wr_ptr.data.value <= field_combo.tx_async_fifo_rd_wr_ptr.data.next_q; + end if; + end if; + end if; + end process; + hwif_out.tx_async_fifo_rd_wr_ptr.data.swmod <= decoded_reg_strb.tx_async_fifo_rd_wr_ptr and decoded_req_is_wr and or_reduce(decoded_wr_biten(31 downto 0)); - hwif_out.rx_async_fifo_rd_wr_ptr.req <= decoded_reg_strb.rx_async_fifo_rd_wr_ptr when not decoded_req_is_wr else '0'; - hwif_out.rx_async_fifo_rd_wr_ptr.req_is_wr <= decoded_req_is_wr; + -- Field: msk_top_regs.rx_async_fifo_rd_wr_ptr.data + process(all) + variable next_c: std_logic_vector(31 downto 0); + variable load_next_c: std_logic; + begin + next_c := field_storage.rx_async_fifo_rd_wr_ptr.data.value; + load_next_c := '0'; + if decoded_reg_strb.rx_async_fifo_rd_wr_ptr and decoded_req_is_wr then -- SW write + next_c := (field_storage.rx_async_fifo_rd_wr_ptr.data.value and not decoded_wr_biten(31 downto 0)) or (decoded_wr_data(31 downto 0) and decoded_wr_biten(31 downto 0)); + load_next_c := '1'; + elsif hwif_in.rx_async_fifo_rd_wr_ptr.data.we then -- HW Write - we + next_c := hwif_in.rx_async_fifo_rd_wr_ptr.data.next_q; + load_next_c := '1'; + end if; + field_combo.rx_async_fifo_rd_wr_ptr.data.next_q <= next_c; + field_combo.rx_async_fifo_rd_wr_ptr.data.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.rx_async_fifo_rd_wr_ptr.data.value <= 32x"0"; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.rx_async_fifo_rd_wr_ptr.data.value <= 32x"0"; + else + if field_combo.rx_async_fifo_rd_wr_ptr.data.load_next then + field_storage.rx_async_fifo_rd_wr_ptr.data.value <= field_combo.rx_async_fifo_rd_wr_ptr.data.next_q; + end if; + end if; + end if; + end process; + hwif_out.rx_async_fifo_rd_wr_ptr.data.swmod <= decoded_reg_strb.rx_async_fifo_rd_wr_ptr and decoded_req_is_wr and or_reduce(decoded_wr_biten(31 downto 0)); ---------------------------------------------------------------------------- -- Write response ---------------------------------------------------------------------------- - process(all) - variable wr_ack: std_logic; - begin - wr_ack := '0'; - - external_wr_ack <= wr_ack; - end process; - cpuif_wr_ack <= external_wr_ack or (decoded_req and decoded_req_is_wr and not decoded_strb_is_external); + cpuif_wr_ack <= decoded_req and decoded_req_is_wr; -- Writes are always granted with no error response cpuif_wr_err <= '0'; ---------------------------------------------------------------------------- -- Readback ---------------------------------------------------------------------------- - process(all) - variable rd_ack: std_logic; - begin - rd_ack := '0'; - rd_ack := rd_ack or hwif_in.Tx_Bit_Count.rd_ack; - rd_ack := rd_ack or hwif_in.Tx_Enable_Count.rd_ack; - rd_ack := rd_ack or hwif_in.PRBS_Bit_Count.rd_ack; - rd_ack := rd_ack or hwif_in.PRBS_Error_Count.rd_ack; - rd_ack := rd_ack or hwif_in.LPF_Accum_F1.rd_ack; - rd_ack := rd_ack or hwif_in.LPF_Accum_F2.rd_ack; - rd_ack := rd_ack or hwif_in.axis_xfer_count.rd_ack; - rd_ack := rd_ack or hwif_in.f1_nco_adjust.rd_ack; - rd_ack := rd_ack or hwif_in.f2_nco_adjust.rd_ack; - rd_ack := rd_ack or hwif_in.f1_error.rd_ack; - rd_ack := rd_ack or hwif_in.f2_error.rd_ack; - rd_ack := rd_ack or hwif_in.rx_power.rd_ack; - rd_ack := rd_ack or hwif_in.tx_async_fifo_rd_wr_ptr.rd_ack; - rd_ack := rd_ack or hwif_in.rx_async_fifo_rd_wr_ptr.rd_ack; - readback_external_rd_ack_c <= rd_ack; - end process; - - readback_external_rd_ack <= readback_external_rd_ack_c; -- Assign readback values to a flattened array readback_array(0)(31 downto 0) <= 32x"AAAA5555" when (decoded_reg_strb.Hash_ID_Low and not decoded_req_is_wr) else (others => '0'); @@ -2373,8 +2968,8 @@ begin readback_array(4)(2 downto 2) <= to_std_logic_vector(hwif_in.MSK_Status.rx_enable.next_q) when (decoded_reg_strb.MSK_Status and not decoded_req_is_wr) else (others => '0'); readback_array(4)(3 downto 3) <= to_std_logic_vector(hwif_in.MSK_Status.tx_axis_valid.next_q) when (decoded_reg_strb.MSK_Status and not decoded_req_is_wr) else (others => '0'); readback_array(4)(31 downto 4) <= (others => '0'); - readback_array(5) <= hwif_in.Tx_Bit_Count.rd_data when hwif_in.Tx_Bit_Count.rd_ack else (others => '0'); - readback_array(6) <= hwif_in.Tx_Enable_Count.rd_data when hwif_in.Tx_Enable_Count.rd_ack else (others => '0'); + readback_array(5)(31 downto 0) <= field_storage.Tx_Bit_Count.data.value when (decoded_reg_strb.Tx_Bit_Count and not decoded_req_is_wr) else (others => '0'); + readback_array(6)(31 downto 0) <= field_storage.Tx_Enable_Count.data.value when (decoded_reg_strb.Tx_Enable_Count and not decoded_req_is_wr) else (others => '0'); readback_array(7)(31 downto 0) <= field_storage.Fb_FreqWord.config_data.value when (decoded_reg_strb.Fb_FreqWord and not decoded_req_is_wr) else (others => '0'); readback_array(8)(31 downto 0) <= field_storage.TX_F1_FreqWord.config_data.value when (decoded_reg_strb.TX_F1_FreqWord and not decoded_req_is_wr) else (others => '0'); readback_array(9)(31 downto 0) <= field_storage.TX_F2_FreqWord.config_data.value when (decoded_reg_strb.TX_F2_FreqWord and not decoded_req_is_wr) else (others => '0'); @@ -2397,20 +2992,20 @@ begin readback_array(17)(31 downto 0) <= field_storage.PRBS_Initial_State.config_data.value when (decoded_reg_strb.PRBS_Initial_State and not decoded_req_is_wr) else (others => '0'); readback_array(18)(31 downto 0) <= field_storage.PRBS_Polynomial.config_data.value when (decoded_reg_strb.PRBS_Polynomial and not decoded_req_is_wr) else (others => '0'); readback_array(19)(31 downto 0) <= field_storage.PRBS_Error_Mask.config_data.value when (decoded_reg_strb.PRBS_Error_Mask and not decoded_req_is_wr) else (others => '0'); - readback_array(20) <= hwif_in.PRBS_Bit_Count.rd_data when hwif_in.PRBS_Bit_Count.rd_ack else (others => '0'); - readback_array(21) <= hwif_in.PRBS_Error_Count.rd_data when hwif_in.PRBS_Error_Count.rd_ack else (others => '0'); - readback_array(22) <= hwif_in.LPF_Accum_F1.rd_data when hwif_in.LPF_Accum_F1.rd_ack else (others => '0'); - readback_array(23) <= hwif_in.LPF_Accum_F2.rd_data when hwif_in.LPF_Accum_F2.rd_ack else (others => '0'); - readback_array(24) <= hwif_in.axis_xfer_count.rd_data when hwif_in.axis_xfer_count.rd_ack else (others => '0'); + readback_array(20)(31 downto 0) <= field_storage.PRBS_Bit_Count.data.value when (decoded_reg_strb.PRBS_Bit_Count and not decoded_req_is_wr) else (others => '0'); + readback_array(21)(31 downto 0) <= field_storage.PRBS_Error_Count.data.value when (decoded_reg_strb.PRBS_Error_Count and not decoded_req_is_wr) else (others => '0'); + readback_array(22)(31 downto 0) <= field_storage.LPF_Accum_F1.data.value when (decoded_reg_strb.LPF_Accum_F1 and not decoded_req_is_wr) else (others => '0'); + readback_array(23)(31 downto 0) <= field_storage.LPF_Accum_F2.data.value when (decoded_reg_strb.LPF_Accum_F2 and not decoded_req_is_wr) else (others => '0'); + readback_array(24)(31 downto 0) <= field_storage.axis_xfer_count.data.value when (decoded_reg_strb.axis_xfer_count and not decoded_req_is_wr) else (others => '0'); readback_array(25)(7 downto 0) <= field_storage.Rx_Sample_Discard.rx_sample_discard.value when (decoded_reg_strb.Rx_Sample_Discard and not decoded_req_is_wr) else (others => '0'); readback_array(25)(15 downto 8) <= field_storage.Rx_Sample_Discard.rx_nco_discard.value when (decoded_reg_strb.Rx_Sample_Discard and not decoded_req_is_wr) else (others => '0'); readback_array(25)(31 downto 16) <= (others => '0'); readback_array(26)(23 downto 0) <= field_storage.LPF_Config_2.p_gain.value when (decoded_reg_strb.LPF_Config_2 and not decoded_req_is_wr) else (others => '0'); readback_array(26)(31 downto 24) <= field_storage.LPF_Config_2.p_shift.value when (decoded_reg_strb.LPF_Config_2 and not decoded_req_is_wr) else (others => '0'); - readback_array(27) <= hwif_in.f1_nco_adjust.rd_data when hwif_in.f1_nco_adjust.rd_ack else (others => '0'); - readback_array(28) <= hwif_in.f2_nco_adjust.rd_data when hwif_in.f2_nco_adjust.rd_ack else (others => '0'); - readback_array(29) <= hwif_in.f1_error.rd_data when hwif_in.f1_error.rd_ack else (others => '0'); - readback_array(30) <= hwif_in.f2_error.rd_data when hwif_in.f2_error.rd_ack else (others => '0'); + readback_array(27)(31 downto 0) <= field_storage.f1_nco_adjust.data.value when (decoded_reg_strb.f1_nco_adjust and not decoded_req_is_wr) else (others => '0'); + readback_array(28)(31 downto 0) <= field_storage.f2_nco_adjust.data.value when (decoded_reg_strb.f2_nco_adjust and not decoded_req_is_wr) else (others => '0'); + readback_array(29)(31 downto 0) <= field_storage.f1_error.data.value when (decoded_reg_strb.f1_error and not decoded_req_is_wr) else (others => '0'); + readback_array(30)(31 downto 0) <= field_storage.f2_error.data.value when (decoded_reg_strb.f2_error and not decoded_req_is_wr) else (others => '0'); readback_array(31)(0 downto 0) <= to_std_logic_vector(field_storage.Tx_Sync_Ctrl.tx_sync_ena.value) when (decoded_reg_strb.Tx_Sync_Ctrl and not decoded_req_is_wr) else (others => '0'); readback_array(31)(1 downto 1) <= to_std_logic_vector(field_storage.Tx_Sync_Ctrl.tx_sync_force.value) when (decoded_reg_strb.Tx_Sync_Ctrl and not decoded_req_is_wr) else (others => '0'); readback_array(31)(2 downto 2) <= to_std_logic_vector(field_storage.Tx_Sync_Ctrl.tx_sync_f1.value) when (decoded_reg_strb.Tx_Sync_Ctrl and not decoded_req_is_wr) else (others => '0'); @@ -2422,15 +3017,16 @@ begin readback_array(33)(31 downto 18) <= (others => '0'); readback_array(34)(17 downto 0) <= field_storage.lowpass_ema_alpha2.alpha.value when (decoded_reg_strb.lowpass_ema_alpha2 and not decoded_req_is_wr) else (others => '0'); readback_array(34)(31 downto 18) <= (others => '0'); - readback_array(35) <= hwif_in.rx_power.rd_data when hwif_in.rx_power.rd_ack else (others => '0'); - readback_array(36) <= hwif_in.tx_async_fifo_rd_wr_ptr.rd_data when hwif_in.tx_async_fifo_rd_wr_ptr.rd_ack else (others => '0'); - readback_array(37) <= hwif_in.rx_async_fifo_rd_wr_ptr.rd_data when hwif_in.rx_async_fifo_rd_wr_ptr.rd_ack else (others => '0'); + readback_array(35)(22 downto 0) <= field_storage.rx_power.data.value when (decoded_reg_strb.rx_power and not decoded_req_is_wr) else (others => '0'); + readback_array(35)(31 downto 23) <= (others => '0'); + readback_array(36)(31 downto 0) <= field_storage.tx_async_fifo_rd_wr_ptr.data.value when (decoded_reg_strb.tx_async_fifo_rd_wr_ptr and not decoded_req_is_wr) else (others => '0'); + readback_array(37)(31 downto 0) <= field_storage.rx_async_fifo_rd_wr_ptr.data.value when (decoded_reg_strb.rx_async_fifo_rd_wr_ptr and not decoded_req_is_wr) else (others => '0'); -- Reduce the array process(all) variable readback_data_var : std_logic_vector(31 downto 0) := (others => '0'); begin - readback_done <= decoded_req and not decoded_req_is_wr and not decoded_strb_is_external; + readback_done <= decoded_req and not decoded_req_is_wr; readback_err <= '0'; readback_data_var := (others => '0'); for i in readback_array'RANGE loop @@ -2439,8 +3035,7 @@ begin readback_data <= readback_data_var; end process; - external_rd_ack <= readback_external_rd_ack; - cpuif_rd_ack <= readback_done or readback_external_rd_ack; + cpuif_rd_ack <= readback_done; cpuif_rd_data <= readback_data; cpuif_rd_err <= readback_err; end architecture rtl; diff --git a/rdl/outputs/rtl/msk_top_regs_pkg.vhd b/rdl/outputs/rtl/msk_top_regs_pkg.vhd index 394906e..c7439ad 100644 --- a/rdl/outputs/rtl/msk_top_regs_pkg.vhd +++ b/rdl/outputs/rtl/msk_top_regs_pkg.vhd @@ -34,92 +34,143 @@ package msk_top_regs_pkg is tx_axis_valid : \msk_top_regs.msk_stat_0.tx_axis_valid_in_t\; end record; - type \msk_top_regs.msk_stat_1__external_in_t\ is record - rd_ack : std_logic; - rd_data : std_logic_vector(31 downto 0); + type \msk_top_regs.msk_stat_1.data_in_t\ is record + next_q : std_logic_vector(31 downto 0); + we : std_logic; end record; - type \msk_top_regs.msk_stat_2__external_in_t\ is record - rd_ack : std_logic; - rd_data : std_logic_vector(31 downto 0); + type \msk_top_regs.msk_stat_1_in_t\ is record + data : \msk_top_regs.msk_stat_1.data_in_t\; end record; - type \msk_top_regs.stat_32_bits__external_in_t\ is record - rd_ack : std_logic; - rd_data : std_logic_vector(31 downto 0); + type \msk_top_regs.msk_stat_2.data_in_t\ is record + next_q : std_logic_vector(31 downto 0); + we : std_logic; end record; - type \msk_top_regs.stat_32_errs__external_in_t\ is record - rd_ack : std_logic; - rd_data : std_logic_vector(31 downto 0); + type \msk_top_regs.msk_stat_2_in_t\ is record + data : \msk_top_regs.msk_stat_2.data_in_t\; end record; - type \msk_top_regs.stat_32_lpf_acc_desc_8cebc7dc_name_f20c6670__external_in_t\ is record - rd_ack : std_logic; - rd_data : std_logic_vector(31 downto 0); + type \msk_top_regs.stat_32_bits.data_in_t\ is record + next_q : std_logic_vector(31 downto 0); + we : std_logic; end record; - type \msk_top_regs.stat_32_lpf_acc_desc_dea6bd99_name_758fd0ce__external_in_t\ is record - rd_ack : std_logic; - rd_data : std_logic_vector(31 downto 0); + type \msk_top_regs.stat_32_bits_in_t\ is record + data : \msk_top_regs.stat_32_bits.data_in_t\; end record; - type \msk_top_regs.msk_stat_3__external_in_t\ is record - rd_ack : std_logic; - rd_data : std_logic_vector(31 downto 0); + type \msk_top_regs.stat_32_errs.data_in_t\ is record + next_q : std_logic_vector(31 downto 0); + we : std_logic; end record; - type \msk_top_regs.observation_data_data_0c017ef4_desc_64ff3689_name_d8ad3b25__external_in_t\ is record - rd_ack : std_logic; - rd_data : std_logic_vector(31 downto 0); + type \msk_top_regs.stat_32_errs_in_t\ is record + data : \msk_top_regs.stat_32_errs.data_in_t\; end record; - type \msk_top_regs.observation_data_data_0515efaa_desc_ebde6d39_name_2c154788__external_in_t\ is record - rd_ack : std_logic; - rd_data : std_logic_vector(31 downto 0); + type \msk_top_regs.stat_32_lpf_acc_desc_8cebc7dc_name_f20c6670.data_in_t\ is record + next_q : std_logic_vector(31 downto 0); + we : std_logic; end record; - type \msk_top_regs.observation_data_data_25a21249_desc_417e1c96_name_3b640507__external_in_t\ is record - rd_ack : std_logic; - rd_data : std_logic_vector(31 downto 0); + type \msk_top_regs.stat_32_lpf_acc_desc_8cebc7dc_name_f20c6670_in_t\ is record + data : \msk_top_regs.stat_32_lpf_acc_desc_8cebc7dc_name_f20c6670.data_in_t\; end record; - type \msk_top_regs.observation_data_data_272a00b6_desc_70869502_name_3de9a0d3__external_in_t\ is record - rd_ack : std_logic; - rd_data : std_logic_vector(31 downto 0); + type \msk_top_regs.stat_32_lpf_acc_desc_dea6bd99_name_758fd0ce.data_in_t\ is record + next_q : std_logic_vector(31 downto 0); + we : std_logic; end record; - type \msk_top_regs.rx_power__external_in_t\ is record - rd_ack : std_logic; - rd_data : std_logic_vector(31 downto 0); + type \msk_top_regs.stat_32_lpf_acc_desc_dea6bd99_name_758fd0ce_in_t\ is record + data : \msk_top_regs.stat_32_lpf_acc_desc_dea6bd99_name_758fd0ce.data_in_t\; end record; - type \msk_top_regs.observation_data_data_cf6acbd7_name_aa4ec676__external_in_t\ is record - rd_ack : std_logic; - rd_data : std_logic_vector(31 downto 0); + type \msk_top_regs.msk_stat_3.data_in_t\ is record + next_q : std_logic_vector(31 downto 0); + we : std_logic; end record; - type \msk_top_regs.observation_data_data_cf6acbd7_name_8a90eed1__external_in_t\ is record - rd_ack : std_logic; - rd_data : std_logic_vector(31 downto 0); + type \msk_top_regs.msk_stat_3_in_t\ is record + data : \msk_top_regs.msk_stat_3.data_in_t\; + end record; + + type \msk_top_regs.data32_desc_64ff3689_name_d8ad3b25_in_t\ is record + next_q : std_logic_vector(31 downto 0); + we : std_logic; + end record; + + type \msk_top_regs.observation_data_data_0c017ef4_desc_64ff3689_name_d8ad3b25_in_t\ is record + data : \msk_top_regs.data32_desc_64ff3689_name_d8ad3b25_in_t\; + end record; + + type \msk_top_regs.data32_desc_ebde6d39_name_2c154788_in_t\ is record + next_q : std_logic_vector(31 downto 0); + we : std_logic; + end record; + + type \msk_top_regs.observation_data_data_0515efaa_desc_ebde6d39_name_2c154788_in_t\ is record + data : \msk_top_regs.data32_desc_ebde6d39_name_2c154788_in_t\; + end record; + + type \msk_top_regs.data32_desc_417e1c96_name_3b640507_in_t\ is record + next_q : std_logic_vector(31 downto 0); + we : std_logic; + end record; + + type \msk_top_regs.observation_data_data_25a21249_desc_417e1c96_name_3b640507_in_t\ is record + data : \msk_top_regs.data32_desc_417e1c96_name_3b640507_in_t\; + end record; + + type \msk_top_regs.data32_desc_70869502_name_3de9a0d3_in_t\ is record + next_q : std_logic_vector(31 downto 0); + we : std_logic; + end record; + + type \msk_top_regs.observation_data_data_272a00b6_desc_70869502_name_3de9a0d3_in_t\ is record + data : \msk_top_regs.data32_desc_70869502_name_3de9a0d3_in_t\; + end record; + + type \msk_top_regs.rx_power.data_in_t\ is record + next_q : std_logic_vector(22 downto 0); + we : std_logic; + end record; + + type \msk_top_regs.rx_power_in_t\ is record + data : \msk_top_regs.rx_power.data_in_t\; + end record; + + type \msk_top_regs.data32_desc_7b98a70e_in_t\ is record + next_q : std_logic_vector(31 downto 0); + we : std_logic; + end record; + + type \msk_top_regs.observation_data_data_cf6acbd7_name_aa4ec676_in_t\ is record + data : \msk_top_regs.data32_desc_7b98a70e_in_t\; + end record; + + type \msk_top_regs.observation_data_data_cf6acbd7_name_8a90eed1_in_t\ is record + data : \msk_top_regs.data32_desc_7b98a70e_in_t\; end record; type msk_top_regs_in_t is record MSK_Status : \msk_top_regs.msk_stat_0_in_t\; - Tx_Bit_Count : \msk_top_regs.msk_stat_1__external_in_t\; - Tx_Enable_Count : \msk_top_regs.msk_stat_2__external_in_t\; - PRBS_Bit_Count : \msk_top_regs.stat_32_bits__external_in_t\; - PRBS_Error_Count : \msk_top_regs.stat_32_errs__external_in_t\; - LPF_Accum_F1 : \msk_top_regs.stat_32_lpf_acc_desc_8cebc7dc_name_f20c6670__external_in_t\; - LPF_Accum_F2 : \msk_top_regs.stat_32_lpf_acc_desc_dea6bd99_name_758fd0ce__external_in_t\; - axis_xfer_count : \msk_top_regs.msk_stat_3__external_in_t\; - f1_nco_adjust : \msk_top_regs.observation_data_data_0c017ef4_desc_64ff3689_name_d8ad3b25__external_in_t\; - f2_nco_adjust : \msk_top_regs.observation_data_data_0515efaa_desc_ebde6d39_name_2c154788__external_in_t\; - f1_error : \msk_top_regs.observation_data_data_25a21249_desc_417e1c96_name_3b640507__external_in_t\; - f2_error : \msk_top_regs.observation_data_data_272a00b6_desc_70869502_name_3de9a0d3__external_in_t\; - rx_power : \msk_top_regs.rx_power__external_in_t\; - tx_async_fifo_rd_wr_ptr : \msk_top_regs.observation_data_data_cf6acbd7_name_aa4ec676__external_in_t\; - rx_async_fifo_rd_wr_ptr : \msk_top_regs.observation_data_data_cf6acbd7_name_8a90eed1__external_in_t\; + Tx_Bit_Count : \msk_top_regs.msk_stat_1_in_t\; + Tx_Enable_Count : \msk_top_regs.msk_stat_2_in_t\; + PRBS_Bit_Count : \msk_top_regs.stat_32_bits_in_t\; + PRBS_Error_Count : \msk_top_regs.stat_32_errs_in_t\; + LPF_Accum_F1 : \msk_top_regs.stat_32_lpf_acc_desc_8cebc7dc_name_f20c6670_in_t\; + LPF_Accum_F2 : \msk_top_regs.stat_32_lpf_acc_desc_dea6bd99_name_758fd0ce_in_t\; + axis_xfer_count : \msk_top_regs.msk_stat_3_in_t\; + f1_nco_adjust : \msk_top_regs.observation_data_data_0c017ef4_desc_64ff3689_name_d8ad3b25_in_t\; + f2_nco_adjust : \msk_top_regs.observation_data_data_0515efaa_desc_ebde6d39_name_2c154788_in_t\; + f1_error : \msk_top_regs.observation_data_data_25a21249_desc_417e1c96_name_3b640507_in_t\; + f2_error : \msk_top_regs.observation_data_data_272a00b6_desc_70869502_name_3de9a0d3_in_t\; + rx_power : \msk_top_regs.rx_power_in_t\; + tx_async_fifo_rd_wr_ptr : \msk_top_regs.observation_data_data_cf6acbd7_name_aa4ec676_in_t\; + rx_async_fifo_rd_wr_ptr : \msk_top_regs.observation_data_data_cf6acbd7_name_8a90eed1_in_t\; end record; type \msk_top_regs.msk_init.txrxinit_out_t\ is record @@ -168,14 +219,20 @@ package msk_top_regs_pkg is diff_encoder_loopback : \msk_top_regs.msk_ctrl.diff_encoder_loopback_out_t\; end record; - type \msk_top_regs.msk_stat_1__external_out_t\ is record - req : std_logic; - req_is_wr : std_logic; + type \msk_top_regs.msk_stat_1.data_out_t\ is record + swmod : std_logic; end record; - type \msk_top_regs.msk_stat_2__external_out_t\ is record - req : std_logic; - req_is_wr : std_logic; + type \msk_top_regs.msk_stat_1_out_t\ is record + data : \msk_top_regs.msk_stat_1.data_out_t\; + end record; + + type \msk_top_regs.msk_stat_2.data_out_t\ is record + swmod : std_logic; + end record; + + type \msk_top_regs.msk_stat_2_out_t\ is record + data : \msk_top_regs.msk_stat_2.data_out_t\; end record; type \msk_top_regs.config_nco_fw_desc_c4924cc6_name_0c494469.config_data_out_t\ is record @@ -327,29 +384,44 @@ package msk_top_regs_pkg is config_data : \msk_top_regs.config_prbs_errmask.config_data_out_t\; end record; - type \msk_top_regs.stat_32_bits__external_out_t\ is record - req : std_logic; - req_is_wr : std_logic; + type \msk_top_regs.stat_32_bits.data_out_t\ is record + swmod : std_logic; + end record; + + type \msk_top_regs.stat_32_bits_out_t\ is record + data : \msk_top_regs.stat_32_bits.data_out_t\; + end record; + + type \msk_top_regs.stat_32_errs.data_out_t\ is record + swmod : std_logic; + end record; + + type \msk_top_regs.stat_32_errs_out_t\ is record + data : \msk_top_regs.stat_32_errs.data_out_t\; + end record; + + type \msk_top_regs.stat_32_lpf_acc_desc_8cebc7dc_name_f20c6670.data_out_t\ is record + swmod : std_logic; + end record; + + type \msk_top_regs.stat_32_lpf_acc_desc_8cebc7dc_name_f20c6670_out_t\ is record + data : \msk_top_regs.stat_32_lpf_acc_desc_8cebc7dc_name_f20c6670.data_out_t\; end record; - type \msk_top_regs.stat_32_errs__external_out_t\ is record - req : std_logic; - req_is_wr : std_logic; + type \msk_top_regs.stat_32_lpf_acc_desc_dea6bd99_name_758fd0ce.data_out_t\ is record + swmod : std_logic; end record; - type \msk_top_regs.stat_32_lpf_acc_desc_8cebc7dc_name_f20c6670__external_out_t\ is record - req : std_logic; - req_is_wr : std_logic; + type \msk_top_regs.stat_32_lpf_acc_desc_dea6bd99_name_758fd0ce_out_t\ is record + data : \msk_top_regs.stat_32_lpf_acc_desc_dea6bd99_name_758fd0ce.data_out_t\; end record; - type \msk_top_regs.stat_32_lpf_acc_desc_dea6bd99_name_758fd0ce__external_out_t\ is record - req : std_logic; - req_is_wr : std_logic; + type \msk_top_regs.msk_stat_3.data_out_t\ is record + swmod : std_logic; end record; - type \msk_top_regs.msk_stat_3__external_out_t\ is record - req : std_logic; - req_is_wr : std_logic; + type \msk_top_regs.msk_stat_3_out_t\ is record + data : \msk_top_regs.msk_stat_3.data_out_t\; end record; type \msk_top_regs.rx_sample_discard.rx_sample_discard_out_t\ is record @@ -378,24 +450,36 @@ package msk_top_regs_pkg is p_shift : \msk_top_regs.lpf_config_2.p_shift_out_t\; end record; - type \msk_top_regs.observation_data_data_0c017ef4_desc_64ff3689_name_d8ad3b25__external_out_t\ is record - req : std_logic; - req_is_wr : std_logic; + type \msk_top_regs.data32_desc_64ff3689_name_d8ad3b25_out_t\ is record + swmod : std_logic; + end record; + + type \msk_top_regs.observation_data_data_0c017ef4_desc_64ff3689_name_d8ad3b25_out_t\ is record + data : \msk_top_regs.data32_desc_64ff3689_name_d8ad3b25_out_t\; + end record; + + type \msk_top_regs.data32_desc_ebde6d39_name_2c154788_out_t\ is record + swmod : std_logic; + end record; + + type \msk_top_regs.observation_data_data_0515efaa_desc_ebde6d39_name_2c154788_out_t\ is record + data : \msk_top_regs.data32_desc_ebde6d39_name_2c154788_out_t\; end record; - type \msk_top_regs.observation_data_data_0515efaa_desc_ebde6d39_name_2c154788__external_out_t\ is record - req : std_logic; - req_is_wr : std_logic; + type \msk_top_regs.data32_desc_417e1c96_name_3b640507_out_t\ is record + swmod : std_logic; end record; - type \msk_top_regs.observation_data_data_25a21249_desc_417e1c96_name_3b640507__external_out_t\ is record - req : std_logic; - req_is_wr : std_logic; + type \msk_top_regs.observation_data_data_25a21249_desc_417e1c96_name_3b640507_out_t\ is record + data : \msk_top_regs.data32_desc_417e1c96_name_3b640507_out_t\; end record; - type \msk_top_regs.observation_data_data_272a00b6_desc_70869502_name_3de9a0d3__external_out_t\ is record - req : std_logic; - req_is_wr : std_logic; + type \msk_top_regs.data32_desc_70869502_name_3de9a0d3_out_t\ is record + swmod : std_logic; + end record; + + type \msk_top_regs.observation_data_data_272a00b6_desc_70869502_name_3de9a0d3_out_t\ is record + data : \msk_top_regs.data32_desc_70869502_name_3de9a0d3_out_t\; end record; type \msk_top_regs.tx_sync_ctrl.tx_sync_ena_out_t\ is record @@ -437,26 +521,31 @@ package msk_top_regs_pkg is alpha : \msk_top_regs.lowpass_ema_alpha.alpha_out_t\; end record; - type \msk_top_regs.rx_power__external_out_t\ is record - req : std_logic; - req_is_wr : std_logic; + type \msk_top_regs.rx_power.data_out_t\ is record + swmod : std_logic; + end record; + + type \msk_top_regs.rx_power_out_t\ is record + data : \msk_top_regs.rx_power.data_out_t\; + end record; + + type \msk_top_regs.data32_desc_7b98a70e_out_t\ is record + swmod : std_logic; end record; - type \msk_top_regs.observation_data_data_cf6acbd7_name_aa4ec676__external_out_t\ is record - req : std_logic; - req_is_wr : std_logic; + type \msk_top_regs.observation_data_data_cf6acbd7_name_aa4ec676_out_t\ is record + data : \msk_top_regs.data32_desc_7b98a70e_out_t\; end record; - type \msk_top_regs.observation_data_data_cf6acbd7_name_8a90eed1__external_out_t\ is record - req : std_logic; - req_is_wr : std_logic; + type \msk_top_regs.observation_data_data_cf6acbd7_name_8a90eed1_out_t\ is record + data : \msk_top_regs.data32_desc_7b98a70e_out_t\; end record; type msk_top_regs_out_t is record MSK_Init : \msk_top_regs.msk_init_out_t\; MSK_Control : \msk_top_regs.msk_ctrl_out_t\; - Tx_Bit_Count : \msk_top_regs.msk_stat_1__external_out_t\; - Tx_Enable_Count : \msk_top_regs.msk_stat_2__external_out_t\; + Tx_Bit_Count : \msk_top_regs.msk_stat_1_out_t\; + Tx_Enable_Count : \msk_top_regs.msk_stat_2_out_t\; Fb_FreqWord : \msk_top_regs.config_nco_fw_desc_c4924cc6_name_0c494469_out_t\; TX_F1_FreqWord : \msk_top_regs.config_nco_fw_desc_94d7aaf5_name_84dd0c1c_out_t\; TX_F2_FreqWord : \msk_top_regs.config_nco_fw_desc_42134a4f_name_d97dbd51_out_t\; @@ -470,23 +559,23 @@ package msk_top_regs_pkg is PRBS_Initial_State : \msk_top_regs.config_prbs_seed_out_t\; PRBS_Polynomial : \msk_top_regs.config_prbs_poly_out_t\; PRBS_Error_Mask : \msk_top_regs.config_prbs_errmask_out_t\; - PRBS_Bit_Count : \msk_top_regs.stat_32_bits__external_out_t\; - PRBS_Error_Count : \msk_top_regs.stat_32_errs__external_out_t\; - LPF_Accum_F1 : \msk_top_regs.stat_32_lpf_acc_desc_8cebc7dc_name_f20c6670__external_out_t\; - LPF_Accum_F2 : \msk_top_regs.stat_32_lpf_acc_desc_dea6bd99_name_758fd0ce__external_out_t\; - axis_xfer_count : \msk_top_regs.msk_stat_3__external_out_t\; + PRBS_Bit_Count : \msk_top_regs.stat_32_bits_out_t\; + PRBS_Error_Count : \msk_top_regs.stat_32_errs_out_t\; + LPF_Accum_F1 : \msk_top_regs.stat_32_lpf_acc_desc_8cebc7dc_name_f20c6670_out_t\; + LPF_Accum_F2 : \msk_top_regs.stat_32_lpf_acc_desc_dea6bd99_name_758fd0ce_out_t\; + axis_xfer_count : \msk_top_regs.msk_stat_3_out_t\; Rx_Sample_Discard : \msk_top_regs.rx_sample_discard_out_t\; LPF_Config_2 : \msk_top_regs.lpf_config_2_out_t\; - f1_nco_adjust : \msk_top_regs.observation_data_data_0c017ef4_desc_64ff3689_name_d8ad3b25__external_out_t\; - f2_nco_adjust : \msk_top_regs.observation_data_data_0515efaa_desc_ebde6d39_name_2c154788__external_out_t\; - f1_error : \msk_top_regs.observation_data_data_25a21249_desc_417e1c96_name_3b640507__external_out_t\; - f2_error : \msk_top_regs.observation_data_data_272a00b6_desc_70869502_name_3de9a0d3__external_out_t\; + f1_nco_adjust : \msk_top_regs.observation_data_data_0c017ef4_desc_64ff3689_name_d8ad3b25_out_t\; + f2_nco_adjust : \msk_top_regs.observation_data_data_0515efaa_desc_ebde6d39_name_2c154788_out_t\; + f1_error : \msk_top_regs.observation_data_data_25a21249_desc_417e1c96_name_3b640507_out_t\; + f2_error : \msk_top_regs.observation_data_data_272a00b6_desc_70869502_name_3de9a0d3_out_t\; Tx_Sync_Ctrl : \msk_top_regs.tx_sync_ctrl_out_t\; Tx_Sync_Cnt : \msk_top_regs.tx_sync_cnt_out_t\; lowpass_ema_alpha1 : \msk_top_regs.lowpass_ema_alpha_out_t\; lowpass_ema_alpha2 : \msk_top_regs.lowpass_ema_alpha_out_t\; - rx_power : \msk_top_regs.rx_power__external_out_t\; - tx_async_fifo_rd_wr_ptr : \msk_top_regs.observation_data_data_cf6acbd7_name_aa4ec676__external_out_t\; - rx_async_fifo_rd_wr_ptr : \msk_top_regs.observation_data_data_cf6acbd7_name_8a90eed1__external_out_t\; + rx_power : \msk_top_regs.rx_power_out_t\; + tx_async_fifo_rd_wr_ptr : \msk_top_regs.observation_data_data_cf6acbd7_name_aa4ec676_out_t\; + rx_async_fifo_rd_wr_ptr : \msk_top_regs.observation_data_data_cf6acbd7_name_8a90eed1_out_t\; end record; end package; diff --git a/rdl/src/msk_top_regs.rdl b/rdl/src/msk_top_regs.rdl index 852fc5f..f8a2598 100644 --- a/rdl/src/msk_top_regs.rdl +++ b/rdl/src/msk_top_regs.rdl @@ -180,10 +180,11 @@ addrmap msk_top_regs { field { name = "Tx Bit Count"; desc = "Count of data requests made by modem"; - sw = r; + sw = rw; hw = w; - onread = ruser; - } tx_bit_counter[31:0]; + we = true; + swmod = true; + } data[31:0] = 0; }; reg msk_stat_2 { @@ -193,10 +194,11 @@ addrmap msk_top_regs { field { desc = "Number of clocks on which Tx Enable is active"; name = "Tx Enable Count"; - sw = r; + sw = rw; hw = w; - onread = ruser; - } tx_ena_counter[31:0] = 0; + we = true; + swmod = true; + } data[31:0] = 0; }; reg config_nco_fw { @@ -362,9 +364,11 @@ addrmap msk_top_regs { name = "PRBS Bits Received"; desc = "Number of bits received by the PRBS monitor since last BER can be calculated as the ratio of received bits to errored-bits"; - sw = r; + sw = rw; hw = w; - } status_data[31:0] = 0; + we = true; + swmod = true; + } data[31:0] = 0; }; reg stat_32_errs { @@ -375,9 +379,11 @@ addrmap msk_top_regs { name = "PRBS Bit Errors"; desc = "Number of errored-bits received by the PRBS monitor since last sync BER can be calculated as the ratio of received bits to errored-bits"; - sw = r; + sw = rw; hw = w; - } status_data[31:0] = 0; + we = true; + swmod = true; + } data[31:0] = 0; }; reg stat_32_lpf_acc { @@ -385,9 +391,11 @@ addrmap msk_top_regs { field { name = "PI Controller Accumulator Value"; desc = "PI Controller Accumulator Value"; - sw = r; + sw = rw; hw = w; - } status_data[31:0] = 0; + we = true; + swmod = true; + } data[31:0] = 0; }; reg msk_stat_3 { @@ -397,9 +405,11 @@ addrmap msk_top_regs { field { desc = "Number completed S_AXIS transfers"; name = "S_AXIS Transfers"; - sw = r; + sw = rw; hw = w; - } xfer_count[31:0] = 0; + we = true; + swmod = true; + } data[31:0] = 0; }; reg tx_sync_ctrl { @@ -463,16 +473,19 @@ addrmap msk_top_regs { field { name = "Receive Power"; desc = "Value that represent the RMS power of the incoming I;"; - sw = r; + sw = rw; hw = w; - } rx_power[22:0] = 0; + we = true; + swmod = true; + } data[22:0] = 0; }; field data32 { fieldwidth = 32; - sw = r; - hw = w; - onread = ruser; + sw = rw; + hw = w; + we = true; + swmod = true; }; reg observation_data { @@ -481,82 +494,82 @@ addrmap msk_top_regs { }; - msk_hash_lo Hash_ID_Low; - msk_hash_hi Hash_ID_High; - msk_init MSK_Init; - msk_ctrl MSK_Control; - msk_stat_0 MSK_Status; - external msk_stat_1 Tx_Bit_Count; - external msk_stat_2 Tx_Enable_Count; - config_nco_fw Fb_FreqWord; - Fb_FreqWord->desc = "Set Modem Data Rate"; - Fb_FreqWord->name = "Bitrate NCO Frequency Control Word"; - config_nco_fw TX_F1_FreqWord; - TX_F1_FreqWord->desc = "Set Modulator F1 Frequency"; - TX_F1_FreqWord->name = "Tx F1 NCO Frequency Control Word"; - config_nco_fw TX_F2_FreqWord; - TX_F2_FreqWord->desc = "Set Modulator F2 Frequency"; - TX_F2_FreqWord->name = "Tx F2 NCO Frequency Control Word"; - config_nco_fw RX_F1_FreqWord; - RX_F1_FreqWord->desc = "Set Demodulator F1 Frequency"; - RX_F1_FreqWord->name = "Rx F1 NCO Frequency Control Word"; - config_nco_fw RX_F2_FreqWord; - RX_F2_FreqWord->desc = "Set Demodulator F2 Frequency"; - RX_F2_FreqWord->name = "Rx F2 NCO Frequency Control Word"; - lpf_config_0 LPF_Config_0; - lpf_config_1 LPF_Config_1; - data_width Tx_Data_Width; - Tx_Data_Width->desc = "Set the parallel data width of the parallel-to-serial converter"; - Tx_Data_Width->name = "Modem Tx Input Data Width"; - data_width Rx_Data_Width; - Rx_Data_Width->desc = "Set the parallel data width of the serial-to-parallel converter"; - Rx_Data_Width->name = "Modem Rx Output Data Width"; - prbs_ctrl PRBS_Control; - config_prbs_seed PRBS_Initial_State; - config_prbs_poly PRBS_Polynomial; - config_prbs_errmask PRBS_Error_Mask; - external stat_32_bits PRBS_Bit_Count; - external stat_32_errs PRBS_Error_Count; - external stat_32_lpf_acc LPF_Accum_F1; - LPF_Accum_F1->name = "F1 PI Controller Accumulator"; - LPF_Accum_F1->desc = "Value of the F1 PI Controller Accumulator"; - external stat_32_lpf_acc LPF_Accum_F2; - LPF_Accum_F2->name = "F2 PI Controller Accumulator"; - LPF_Accum_F2->desc = "Value of the F2 PI Controller Accumulator"; - external msk_stat_3 axis_xfer_count; - rx_sample_discard Rx_Sample_Discard; - lpf_config_2 LPF_Config_2; - external observation_data f1_nco_adjust; - f1_nco_adjust->name = "F1 NCO Frequency Adjust"; - f1_nco_adjust->desc = "Frequency offet applied to the F1 NCO"; - f1_nco_adjust.data->name = "F1 NCO Frequency Adjust"; - f1_nco_adjust.data->desc = "Frequency offet applied to the F1 NCO"; - external observation_data f2_nco_adjust; - f2_nco_adjust->name = "F2 NCO Frequency Adjust"; - f2_nco_adjust->desc = "Frequency offet applied to the F2 NCO"; - f2_nco_adjust.data->name = "F2 NCO Frequency Adjust"; - f2_nco_adjust.data->desc = "Frequency offet applied to the F2 NCO"; - external observation_data f1_error; - f1_error->name = "F1 Error Value"; - f1_error->desc = "Error value of the F1 Costas loop after each active bit period"; - f1_error.data->name = "F1 Error Value"; - f1_error.data->desc = "Error value of the F1 Costas loop after each active bit period"; - external observation_data f2_error; - f2_error->name = "F2 Error Value"; - f2_error->desc = "Error value of the F2 Costas loop after each active bit period"; - f2_error.data->name = "F2 Error Value"; - f2_error.data->desc = "Error value of the F2 Costas loop after each active bit period"; - tx_sync_ctrl Tx_Sync_Ctrl; - tx_sync_cnt Tx_Sync_Cnt; - lowpass_ema_alpha lowpass_ema_alpha1; - lowpass_ema_alpha lowpass_ema_alpha2; - external rx_power rx_power; - external observation_data tx_async_fifo_rd_wr_ptr; - tx_async_fifo_rd_wr_ptr->name = "Tx async FIFO read and write pointers"; - tx_async_fifo_rd_wr_ptr.data->desc = "Bits 31:16 -> write pointer (12-bits) - Bits 15:00 -> read pointer (12-bits)"; - external observation_data rx_async_fifo_rd_wr_ptr; - rx_async_fifo_rd_wr_ptr->name = "Rx async FIFO read and write pointers"; - rx_async_fifo_rd_wr_ptr.data->desc = "Bits 31:16 -> write pointer (12-bits) - Bits 15:00 -> read pointer (12-bits)"; + msk_hash_lo Hash_ID_Low; + msk_hash_hi Hash_ID_High; + msk_init MSK_Init; + msk_ctrl MSK_Control; + msk_stat_0 MSK_Status; + msk_stat_1 Tx_Bit_Count; + msk_stat_2 Tx_Enable_Count; + config_nco_fw Fb_FreqWord; + Fb_FreqWord->desc = "Set Modem Data Rate"; + Fb_FreqWord->name = "Bitrate NCO Frequency Control Word"; + config_nco_fw TX_F1_FreqWord; + TX_F1_FreqWord->desc = "Set Modulator F1 Frequency"; + TX_F1_FreqWord->name = "Tx F1 NCO Frequency Control Word"; + config_nco_fw TX_F2_FreqWord; + TX_F2_FreqWord->desc = "Set Modulator F2 Frequency"; + TX_F2_FreqWord->name = "Tx F2 NCO Frequency Control Word"; + config_nco_fw RX_F1_FreqWord; + RX_F1_FreqWord->desc = "Set Demodulator F1 Frequency"; + RX_F1_FreqWord->name = "Rx F1 NCO Frequency Control Word"; + config_nco_fw RX_F2_FreqWord; + RX_F2_FreqWord->desc = "Set Demodulator F2 Frequency"; + RX_F2_FreqWord->name = "Rx F2 NCO Frequency Control Word"; + lpf_config_0 LPF_Config_0; + lpf_config_1 LPF_Config_1; + data_width Tx_Data_Width; + Tx_Data_Width->desc = "Set the parallel data width of the parallel-to-serial converter"; + Tx_Data_Width->name = "Modem Tx Input Data Width"; + data_width Rx_Data_Width; + Rx_Data_Width->desc = "Set the parallel data width of the serial-to-parallel converter"; + Rx_Data_Width->name = "Modem Rx Output Data Width"; + prbs_ctrl PRBS_Control; + config_prbs_seed PRBS_Initial_State; + config_prbs_poly PRBS_Polynomial; + config_prbs_errmask PRBS_Error_Mask; + stat_32_bits PRBS_Bit_Count; + stat_32_errs PRBS_Error_Count; + stat_32_lpf_acc LPF_Accum_F1; + LPF_Accum_F1->name = "F1 PI Controller Accumulator"; + LPF_Accum_F1->desc = "Value of the F1 PI Controller Accumulator"; + stat_32_lpf_acc LPF_Accum_F2; + LPF_Accum_F2->name = "F2 PI Controller Accumulator"; + LPF_Accum_F2->desc = "Value of the F2 PI Controller Accumulator"; + msk_stat_3 axis_xfer_count; + rx_sample_discard Rx_Sample_Discard; + lpf_config_2 LPF_Config_2; + observation_data f1_nco_adjust; + f1_nco_adjust->name = "F1 NCO Frequency Adjust"; + f1_nco_adjust->desc = "Frequency offet applied to the F1 NCO"; + f1_nco_adjust.data->name = "F1 NCO Frequency Adjust"; + f1_nco_adjust.data->desc = "Frequency offet applied to the F1 NCO"; + observation_data f2_nco_adjust; + f2_nco_adjust->name = "F2 NCO Frequency Adjust"; + f2_nco_adjust->desc = "Frequency offet applied to the F2 NCO"; + f2_nco_adjust.data->name = "F2 NCO Frequency Adjust"; + f2_nco_adjust.data->desc = "Frequency offet applied to the F2 NCO"; + observation_data f1_error; + f1_error->name = "F1 Error Value"; + f1_error->desc = "Error value of the F1 Costas loop after each active bit period"; + f1_error.data->name = "F1 Error Value"; + f1_error.data->desc = "Error value of the F1 Costas loop after each active bit period"; + observation_data f2_error; + f2_error->name = "F2 Error Value"; + f2_error->desc = "Error value of the F2 Costas loop after each active bit period"; + f2_error.data->name = "F2 Error Value"; + f2_error.data->desc = "Error value of the F2 Costas loop after each active bit period"; + tx_sync_ctrl Tx_Sync_Ctrl; + tx_sync_cnt Tx_Sync_Cnt; + lowpass_ema_alpha lowpass_ema_alpha1; + lowpass_ema_alpha lowpass_ema_alpha2; + rx_power rx_power; + observation_data tx_async_fifo_rd_wr_ptr; + tx_async_fifo_rd_wr_ptr->name = "Tx async FIFO read and write pointers"; + tx_async_fifo_rd_wr_ptr.data->desc = "Bits 31:16 -> write pointer (12-bits) + Bits 15:00 -> read pointer (12-bits)"; + observation_data rx_async_fifo_rd_wr_ptr; + rx_async_fifo_rd_wr_ptr->name = "Rx async FIFO read and write pointers"; + rx_async_fifo_rd_wr_ptr.data->desc = "Bits 31:16 -> write pointer (12-bits) + Bits 15:00 -> read pointer (12-bits)"; }; diff --git a/sim/msk_test.py b/sim/msk_test.py index d063eba..c19b048 100755 --- a/sim/msk_test.py +++ b/sim/msk_test.py @@ -265,6 +265,8 @@ async def write_dwords(self,addr, data): async def read(self, addr, width, accesswidth): await RisingEdge(self.aclk) + await RisingEdge(self.aclk) + await RisingEdge(self.aclk) self.arvalid.value = 1 self.araddr.value = addr @@ -826,16 +828,22 @@ async def msk_test_1(dut): sim_time_d = sim_time sim_time = get_sim_time("us") + await regs.f1_nco_adjust.write(0) data = await regs.f1_nco_adjust.read() print("F1 NCO Adjust: ", hex(data)) + await regs.f2_nco_adjust.write(0) data = await regs.f2_nco_adjust.read() print("F2 NCO Adjust: ", hex(data)) + await regs.f1_error.write(0) data = await regs.f1_error.read() print("F1 Error: ", hex(data)) + await regs.f2_error.write(0) data = await regs.f2_error.read() print("F2 Error: ", hex(data)) + await regs.tx_async_fifo_rd_wr_ptr.write(0) data = await regs.tx_async_fifo_rd_wr_ptr.read() print("Tx FIFO Pointers", hex(data)) + await regs.rx_async_fifo_rd_wr_ptr.write(0) data = await regs.rx_async_fifo_rd_wr_ptr.read() print("Rx FIFO Pointers", hex(data)) #data = await regs.read("msk_top_regs", "LPF_Accum_F1") diff --git a/src/msk_top_csr.vhd b/src/msk_top_csr.vhd index ee86e51..830c1c8 100644 --- a/src/msk_top_csr.vhd +++ b/src/msk_top_csr.vhd @@ -301,58 +301,58 @@ BEGIN hwif_in.MSK_Status.tx_axis_valid.next_q <= tx_axis_valid; -- Status Request from AXI to MDM - utbc_r: pulse_detect PORT MAP (clk, csr_init, hwif_out.Tx_Bit_Count.req, tx_bit_counter_req ); - utbe_r: pulse_detect PORT MAP (clk, csr_init, hwif_out.Tx_Enable_Count.req, tx_ena_counter_req ); - utatc_r: pulse_detect PORT MAP (clk, csr_init, hwif_out.axis_xfer_count.req, axis_xfer_count_req ); - utf1e_r: pulse_detect PORT MAP (clk, csr_init, hwif_out.f1_error.req, f1_error_req ); - utf2e_r: pulse_detect PORT MAP (clk, csr_init, hwif_out.f2_error.req, f2_error_req ); - utf1a_r: pulse_detect PORT MAP (clk, csr_init, hwif_out.f1_nco_adjust.req, f1_nco_adjust_req ); - utf2a_r: pulse_detect PORT MAP (clk, csr_init, hwif_out.f2_nco_adjust.req, f2_nco_adjust_req ); - utprb_r: pulse_detect PORT MAP (clk, csr_init, hwif_out.PRBS_Bit_Count.req, prbs_bits_req ); - utpre_r: pulse_detect PORT MAP (clk, csr_init, hwif_out.PRBS_Error_Count.req, prbs_errs_req ); - utlp1_r: pulse_detect PORT MAP (clk, csr_init, hwif_out.LPF_Accum_F1.req, lpf_accum_f1_req ); - utlp2_r: pulse_detect PORT MAP (clk, csr_init, hwif_out.LPF_Accum_F2.req, lpf_accum_f2_req ); - utpwr_r: pulse_detect PORT MAP (clk, csr_init, hwif_out.rx_power.req, pd_power_req ); + utbc_r: pulse_detect PORT MAP (clk, csr_init, hwif_out.Tx_Bit_Count.data.swmod, tx_bit_counter_req ); + utbe_r: pulse_detect PORT MAP (clk, csr_init, hwif_out.Tx_Enable_Count.data.swmod, tx_ena_counter_req ); + utatc_r: pulse_detect PORT MAP (clk, csr_init, hwif_out.axis_xfer_count.data.swmod, axis_xfer_count_req ); + utf1e_r: pulse_detect PORT MAP (clk, csr_init, hwif_out.f1_error.data.swmod, f1_error_req ); + utf2e_r: pulse_detect PORT MAP (clk, csr_init, hwif_out.f2_error.data.swmod, f2_error_req ); + utf1a_r: pulse_detect PORT MAP (clk, csr_init, hwif_out.f1_nco_adjust.data.swmod, f1_nco_adjust_req ); + utf2a_r: pulse_detect PORT MAP (clk, csr_init, hwif_out.f2_nco_adjust.data.swmod, f2_nco_adjust_req ); + utprb_r: pulse_detect PORT MAP (clk, csr_init, hwif_out.PRBS_Bit_Count.data.swmod, prbs_bits_req ); + utpre_r: pulse_detect PORT MAP (clk, csr_init, hwif_out.PRBS_Error_Count.data.swmod, prbs_errs_req ); + utlp1_r: pulse_detect PORT MAP (clk, csr_init, hwif_out.LPF_Accum_F1.data.swmod, lpf_accum_f1_req ); + utlp2_r: pulse_detect PORT MAP (clk, csr_init, hwif_out.LPF_Accum_F2.data.swmod, lpf_accum_f2_req ); + utpwr_r: pulse_detect PORT MAP (clk, csr_init, hwif_out.rx_power.data.swmod, pd_power_req ); -- Status acknowledge from MDM to AXI - utbc_a : pulse_detect PORT MAP (s_axi_aclk, NOT s_axi_aresetn, tx_bit_counter_req, hwif_in.Tx_Bit_Count.rd_ack ); - utbe_a : pulse_detect PORT MAP (s_axi_aclk, NOT s_axi_aresetn, tx_ena_counter_req, hwif_in.Tx_Enable_Count.rd_ack ); - utatc_a: pulse_detect PORT MAP (s_axi_aclk, NOT s_axi_aresetn, axis_xfer_count_req, hwif_in.axis_xfer_count.rd_ack ); - utf1e_a: pulse_detect PORT MAP (s_axi_aclk, NOT s_axi_aresetn, f1_error_req, hwif_in.f1_error.rd_ack ); - utf2e_a: pulse_detect PORT MAP (s_axi_aclk, NOT s_axi_aresetn, f2_error_req, hwif_in.f2_error.rd_ack ); - utf1a_a: pulse_detect PORT MAP (s_axi_aclk, NOT s_axi_aresetn, f1_nco_adjust_req, hwif_in.f1_nco_adjust.rd_ack ); - utf2a_a: pulse_detect PORT MAP (s_axi_aclk, NOT s_axi_aresetn, f2_nco_adjust_req, hwif_in.f2_nco_adjust.rd_ack ); - utprb_a: pulse_detect PORT MAP (s_axi_aclk, NOT s_axi_aresetn, prbs_bits_req, hwif_in.PRBS_Bit_Count.rd_ack ); - utpre_a: pulse_detect PORT MAP (s_axi_aclk, NOT s_axi_aresetn, prbs_errs_req, hwif_in.PRBS_Error_Count.rd_ack ); - utlp1_a: pulse_detect PORT MAP (s_axi_aclk, NOT s_axi_aresetn, lpf_accum_f1_req, hwif_in.LPF_Accum_F1.rd_ack ); - utlp2_a: pulse_detect PORT MAP (s_axi_aclk, NOT s_axi_aresetn, lpf_accum_f2_req, hwif_in.LPF_Accum_F2.rd_ack ); - utpwr_a: pulse_detect PORT MAP (s_axi_aclk, NOT s_axi_aresetn, pd_power_req, hwif_in.rx_power.rd_ack ); + utbc_a : pulse_detect PORT MAP (s_axi_aclk, NOT s_axi_aresetn, tx_bit_counter_req, hwif_in.Tx_Bit_Count.data.we ); + utbe_a : pulse_detect PORT MAP (s_axi_aclk, NOT s_axi_aresetn, tx_ena_counter_req, hwif_in.Tx_Enable_Count.data.we ); + utatc_a: pulse_detect PORT MAP (s_axi_aclk, NOT s_axi_aresetn, axis_xfer_count_req, hwif_in.axis_xfer_count.data.we ); + utf1e_a: pulse_detect PORT MAP (s_axi_aclk, NOT s_axi_aresetn, f1_error_req, hwif_in.f1_error.data.we ); + utf2e_a: pulse_detect PORT MAP (s_axi_aclk, NOT s_axi_aresetn, f2_error_req, hwif_in.f2_error.data.we ); + utf1a_a: pulse_detect PORT MAP (s_axi_aclk, NOT s_axi_aresetn, f1_nco_adjust_req, hwif_in.f1_nco_adjust.data.we ); + utf2a_a: pulse_detect PORT MAP (s_axi_aclk, NOT s_axi_aresetn, f2_nco_adjust_req, hwif_in.f2_nco_adjust.data.we ); + utprb_a: pulse_detect PORT MAP (s_axi_aclk, NOT s_axi_aresetn, prbs_bits_req, hwif_in.PRBS_Bit_Count.data.we ); + utpre_a: pulse_detect PORT MAP (s_axi_aclk, NOT s_axi_aresetn, prbs_errs_req, hwif_in.PRBS_Error_Count.data.we ); + utlp1_a: pulse_detect PORT MAP (s_axi_aclk, NOT s_axi_aresetn, lpf_accum_f1_req, hwif_in.LPF_Accum_F1.data.we ); + utlp2_a: pulse_detect PORT MAP (s_axi_aclk, NOT s_axi_aresetn, lpf_accum_f2_req, hwif_in.LPF_Accum_F2.data.we ); + utpwr_a: pulse_detect PORT MAP (s_axi_aclk, NOT s_axi_aresetn, pd_power_req, hwif_in.rx_power.data.we ); -- Status capture from MDM to AXI - utbc_c : data_capture PORT MAP (clk, csr_init, tx_bit_counter_req, tx_bit_counter, hwif_in.Tx_Bit_Count.rd_data ); - utbe_c : data_capture PORT MAP (clk, csr_init, tx_ena_counter_req, tx_ena_counter, hwif_in.Tx_Enable_Count.rd_data ); - utatc_c: data_capture PORT MAP (clk, csr_init, axis_xfer_count_req, xfer_count, hwif_in.axis_xfer_count.rd_data ); - utf1e_c: data_capture PORT MAP (clk, csr_init, f1_error_req, f1_error, hwif_in.f1_error.rd_data ); - utf2e_c: data_capture PORT MAP (clk, csr_init, f2_error_req, f2_error, hwif_in.f2_error.rd_data ); - utf1a_c: data_capture PORT MAP (clk, csr_init, f1_nco_adjust_req, f1_nco_adjust, hwif_in.f1_nco_adjust.rd_data ); - utf2a_c: data_capture PORT MAP (clk, csr_init, f2_nco_adjust_req, f2_nco_adjust, hwif_in.f2_nco_adjust.rd_data ); - utprb_c: data_capture PORT MAP (clk, csr_init, prbs_bits_req, prbs_bits, hwif_in.PRBS_Bit_Count.rd_data ); - utpre_c: data_capture PORT MAP (clk, csr_init, prbs_errs_req, prbs_errs, hwif_in.PRBS_Error_Count.rd_data); - utlp1_c: data_capture PORT MAP (clk, csr_init, lpf_accum_f1_req, lpf_accum_f1, hwif_in.LPF_Accum_F1.rd_data ); - utlp2_c: data_capture PORT MAP (clk, csr_init, lpf_accum_f2_req, lpf_accum_f2, hwif_in.LPF_Accum_F2.rd_data ); - utpwr_c: data_capture PORT MAP (clk, csr_init, pd_power_req, std_logic_vector(resize(unsigned(pd_power),32)), - hwif_in.rx_power.rd_data); + utbc_c : data_capture PORT MAP (clk, csr_init, tx_bit_counter_req, tx_bit_counter, hwif_in.Tx_Bit_Count.data.next_q ); + utbe_c : data_capture PORT MAP (clk, csr_init, tx_ena_counter_req, tx_ena_counter, hwif_in.Tx_Enable_Count.data.next_q ); + utatc_c: data_capture PORT MAP (clk, csr_init, axis_xfer_count_req, xfer_count, hwif_in.axis_xfer_count.data.next_q ); + utf1e_c: data_capture PORT MAP (clk, csr_init, f1_error_req, f1_error, hwif_in.f1_error.data.next_q ); + utf2e_c: data_capture PORT MAP (clk, csr_init, f2_error_req, f2_error, hwif_in.f2_error.data.next_q ); + utf1a_c: data_capture PORT MAP (clk, csr_init, f1_nco_adjust_req, f1_nco_adjust, hwif_in.f1_nco_adjust.data.next_q ); + utf2a_c: data_capture PORT MAP (clk, csr_init, f2_nco_adjust_req, f2_nco_adjust, hwif_in.f2_nco_adjust.data.next_q ); + utprb_c: data_capture PORT MAP (clk, csr_init, prbs_bits_req, prbs_bits, hwif_in.PRBS_Bit_Count.data.next_q ); + utpre_c: data_capture PORT MAP (clk, csr_init, prbs_errs_req, prbs_errs, hwif_in.PRBS_Error_Count.data.next_q); + utlp1_c: data_capture PORT MAP (clk, csr_init, lpf_accum_f1_req, lpf_accum_f1, hwif_in.LPF_Accum_F1.data.next_q ); + utlp2_c: data_capture PORT MAP (clk, csr_init, lpf_accum_f2_req, lpf_accum_f2, hwif_in.LPF_Accum_F2.data.next_q ); + utpwr_c: data_capture GENERIC MAP (23) + PORT MAP (clk, csr_init, pd_power_req, pd_power, hwif_in.rx_power.data.next_q ); -- FIFO status reads - rx_async_fifo_status_req <= hwif_out.rx_async_fifo_rd_wr_ptr.req; - hwif_in.rx_async_fifo_rd_wr_ptr.rd_ack <= rx_async_fifo_status_ack; - hwif_in.rx_async_fifo_rd_wr_ptr.rd_data <= std_logic_vector(resize(unsigned(rx_async_fifo_wr_ptr), 16) & - resize(unsigned(rx_async_fifo_rd_ptr), 16)); - - tx_async_fifo_status_req <= hwif_out.tx_async_fifo_rd_wr_ptr.req; - hwif_in.tx_async_fifo_rd_wr_ptr.rd_ack <= tx_async_fifo_status_ack; - hwif_in.tx_async_fifo_rd_wr_ptr.rd_data <= std_logic_vector(resize(unsigned(tx_async_fifo_wr_ptr), 16) & - resize(unsigned(tx_async_fifo_rd_ptr), 16)); + rx_async_fifo_status_req <= hwif_out.rx_async_fifo_rd_wr_ptr.data.swmod; + hwif_in.rx_async_fifo_rd_wr_ptr.data.we <= rx_async_fifo_status_ack; + hwif_in.rx_async_fifo_rd_wr_ptr.data.next_q <= std_logic_vector(resize(unsigned(rx_async_fifo_wr_ptr), 16) & + resize(unsigned(rx_async_fifo_rd_ptr), 16)); + + tx_async_fifo_status_req <= hwif_out.tx_async_fifo_rd_wr_ptr.data.swmod; + hwif_in.tx_async_fifo_rd_wr_ptr.data.we <= tx_async_fifo_status_ack; + hwif_in.tx_async_fifo_rd_wr_ptr.data.next_q <= std_logic_vector(resize(unsigned(tx_async_fifo_wr_ptr), 16) & + resize(unsigned(tx_async_fifo_rd_ptr), 16)); -- Control from AXI to MDM u01s: cdc_resync PORT MAP (clk, csr_init, hwif_out.MSK_Init.txrxinit.value, txrxinit ); From fce224f8ff99c6d64876f33ed0e48fa44bc77cd9 Mon Sep 17 00:00:00 2001 From: Matthew Wishek Date: Tue, 4 Nov 2025 12:22:17 -0700 Subject: [PATCH 21/60] rdl: update descriptions for write-to-capture registers --- rdl/outputs/c-header/msk_top_regs.h | 68 +- rdl/outputs/docs/msk_top_regs.md | 182 ++++-- rdl/outputs/docs/msk_top_regs.pdf | Bin 113978 -> 115808 bytes .../msk_top_regs/reg_model/msk_top_regs.py | 596 +++++++++--------- .../msk_top_regs/tests/test_msk_top_regs.py | 82 +-- rdl/outputs/rtl/msk_top_regs_pkg.vhd | 92 +-- rdl/src/msk_top_regs.rdl | 181 +++++- 7 files changed, 693 insertions(+), 508 deletions(-) diff --git a/rdl/outputs/c-header/msk_top_regs.h b/rdl/outputs/c-header/msk_top_regs.h index 58f9611..d5b3d65 100644 --- a/rdl/outputs/c-header/msk_top_regs.h +++ b/rdl/outputs/c-header/msk_top_regs.h @@ -253,29 +253,29 @@ extern "C" { #define MSK_TOP_REGS__LPF_CONFIG_2__P_SHIFT_bw 8 #define MSK_TOP_REGS__LPF_CONFIG_2__P_SHIFT_reset 0x0 -// Reg - msk_top_regs::observation_data_data_0c017ef4_desc_64ff3689_name_d8ad3b25 -#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_0C017EF4_DESC_64FF3689_NAME_D8AD3B25__DATA_bm 0xffffffff -#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_0C017EF4_DESC_64FF3689_NAME_D8AD3B25__DATA_bp 0 -#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_0C017EF4_DESC_64FF3689_NAME_D8AD3B25__DATA_bw 32 -#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_0C017EF4_DESC_64FF3689_NAME_D8AD3B25__DATA_reset 0x0 - -// Reg - msk_top_regs::observation_data_data_0515efaa_desc_ebde6d39_name_2c154788 -#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_0515EFAA_DESC_EBDE6D39_NAME_2C154788__DATA_bm 0xffffffff -#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_0515EFAA_DESC_EBDE6D39_NAME_2C154788__DATA_bp 0 -#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_0515EFAA_DESC_EBDE6D39_NAME_2C154788__DATA_bw 32 -#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_0515EFAA_DESC_EBDE6D39_NAME_2C154788__DATA_reset 0x0 - -// Reg - msk_top_regs::observation_data_data_25a21249_desc_417e1c96_name_3b640507 -#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_25A21249_DESC_417E1C96_NAME_3B640507__DATA_bm 0xffffffff -#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_25A21249_DESC_417E1C96_NAME_3B640507__DATA_bp 0 -#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_25A21249_DESC_417E1C96_NAME_3B640507__DATA_bw 32 -#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_25A21249_DESC_417E1C96_NAME_3B640507__DATA_reset 0x0 - -// Reg - msk_top_regs::observation_data_data_272a00b6_desc_70869502_name_3de9a0d3 -#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_272A00B6_DESC_70869502_NAME_3DE9A0D3__DATA_bm 0xffffffff -#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_272A00B6_DESC_70869502_NAME_3DE9A0D3__DATA_bp 0 -#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_272A00B6_DESC_70869502_NAME_3DE9A0D3__DATA_bw 32 -#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_272A00B6_DESC_70869502_NAME_3DE9A0D3__DATA_reset 0x0 +// Reg - msk_top_regs::observation_data_data_521c7d53_name_d8ad3b25 +#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_521C7D53_NAME_D8AD3B25__DATA_bm 0xffffffff +#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_521C7D53_NAME_D8AD3B25__DATA_bp 0 +#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_521C7D53_NAME_D8AD3B25__DATA_bw 32 +#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_521C7D53_NAME_D8AD3B25__DATA_reset 0x0 + +// Reg - msk_top_regs::observation_data_data_5802c5b1_name_2c154788 +#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_5802C5B1_NAME_2C154788__DATA_bm 0xffffffff +#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_5802C5B1_NAME_2C154788__DATA_bp 0 +#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_5802C5B1_NAME_2C154788__DATA_bw 32 +#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_5802C5B1_NAME_2C154788__DATA_reset 0x0 + +// Reg - msk_top_regs::observation_data_data_f83682dd_name_3b640507 +#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_F83682DD_NAME_3B640507__DATA_bm 0xffffffff +#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_F83682DD_NAME_3B640507__DATA_bp 0 +#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_F83682DD_NAME_3B640507__DATA_bw 32 +#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_F83682DD_NAME_3B640507__DATA_reset 0x0 + +// Reg - msk_top_regs::observation_data_data_0a9850a4_name_3de9a0d3 +#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_0A9850A4_NAME_3DE9A0D3__DATA_bm 0xffffffff +#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_0A9850A4_NAME_3DE9A0D3__DATA_bp 0 +#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_0A9850A4_NAME_3DE9A0D3__DATA_bw 32 +#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_0A9850A4_NAME_3DE9A0D3__DATA_reset 0x0 // Reg - msk_top_regs::tx_sync_ctrl #define MSK_TOP_REGS__TX_SYNC_CTRL__TX_SYNC_ENA_bm 0x1 @@ -313,17 +313,17 @@ extern "C" { #define MSK_TOP_REGS__RX_POWER__DATA_bw 23 #define MSK_TOP_REGS__RX_POWER__DATA_reset 0x0 -// Reg - msk_top_regs::observation_data_data_cf6acbd7_name_aa4ec676 -#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_CF6ACBD7_NAME_AA4EC676__DATA_bm 0xffffffff -#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_CF6ACBD7_NAME_AA4EC676__DATA_bp 0 -#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_CF6ACBD7_NAME_AA4EC676__DATA_bw 32 -#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_CF6ACBD7_NAME_AA4EC676__DATA_reset 0x0 - -// Reg - msk_top_regs::observation_data_data_cf6acbd7_name_8a90eed1 -#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_CF6ACBD7_NAME_8A90EED1__DATA_bm 0xffffffff -#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_CF6ACBD7_NAME_8A90EED1__DATA_bp 0 -#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_CF6ACBD7_NAME_8A90EED1__DATA_bw 32 -#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_CF6ACBD7_NAME_8A90EED1__DATA_reset 0x0 +// Reg - msk_top_regs::observation_data_data_dbd8270c_name_aa4ec676 +#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_DBD8270C_NAME_AA4EC676__DATA_bm 0xffffffff +#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_DBD8270C_NAME_AA4EC676__DATA_bp 0 +#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_DBD8270C_NAME_AA4EC676__DATA_bw 32 +#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_DBD8270C_NAME_AA4EC676__DATA_reset 0x0 + +// Reg - msk_top_regs::observation_data_data_dbd8270c_name_8a90eed1 +#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_DBD8270C_NAME_8A90EED1__DATA_bm 0xffffffff +#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_DBD8270C_NAME_8A90EED1__DATA_bp 0 +#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_DBD8270C_NAME_8A90EED1__DATA_bw 32 +#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_DBD8270C_NAME_8A90EED1__DATA_reset 0x0 // Addrmap - msk_top_regs typedef struct __attribute__ ((__packed__)) { diff --git a/rdl/outputs/docs/msk_top_regs.md b/rdl/outputs/docs/msk_top_regs.md index b1db448..b657208 100644 --- a/rdl/outputs/docs/msk_top_regs.md +++ b/rdl/outputs/docs/msk_top_regs.md @@ -99,18 +99,18 @@ Don't override. Generated from: msk_top_regs #### txrxinit field -

0 -> Normal modem operation -1 -> Initialize Tx and Rx

+

0 -> Normal modem operation

+

1 -> Initialize Tx and Rx

#### txinit field -

0 -> Normal Tx operation -1 -> Initialize Tx

+

0 -> Normal Tx operation

+

1 -> Initialize Tx

#### rxinit field -

0 -> Normal Rx operation -1 -> Initialize Rx

+

0 -> Normal Rx operation

+

1 -> Initialize Rx

### MSK_Control register @@ -135,8 +135,8 @@ Don't override. Generated from: msk_top_regs #### loopback_ena field -

0 -> Modem loopback disabled -1 -> Modem loopback enabled

+

0 -> Modem loopback disabled

+

1 -> Modem loopback enabled

#### rx_invert field @@ -149,8 +149,8 @@ Don't override. Generated from: msk_top_regs #### diff_encoder_loopback field -

0 -> Differential Encoder -> Decoder loopback disabled -1 -> Differential Encoder -> Decoder loopback enabled

+

0 -> Differential Encoder -> Decoder loopback disabled

+

1 -> Differential Encoder -> Decoder loopback enabled

### MSK_Status register @@ -173,18 +173,18 @@ Don't override. Generated from: msk_top_regs #### tx_enable field -

1 -> Data to DAC Enabled -0 -> Data to DAC Disabled

+

1 -> Data to DAC Enabled

+

0 -> Data to DAC Disabled

#### rx_enable field -

1 -> Data from ADC Enabled -0 -> Data from ADC Disabled

+

1 -> Data from ADC Enabled

+

0 -> Data from ADC Disabled

#### tx_axis_valid field -

1 -> S_AXIS_VALID Enabled -0 -> S_AXIS_VALID Disabled

+

1 -> S_AXIS_VALID Enabled

+

0 -> S_AXIS_VALID Disabled

### Tx_Bit_Count register @@ -201,6 +201,10 @@ Don't override. Generated from: msk_top_regs #### data field

Count of data requests made by modem

+

This register is write-to-capture.

+

To read data the following steps are required:

+

1 - Write any value to this register to capture read data

+

2 - Read the register

### Tx_Enable_Count register @@ -217,6 +221,10 @@ Don't override. Generated from: msk_top_regs #### data field

Number of clocks on which Tx Enable is active

+

This register is write-to-capture.

+

To read data the following steps are required:

+

1 - Write any value to this register to capture read data

+

2 - Read the register

### Fb_FreqWord register @@ -320,13 +328,13 @@ where Fn is the desired NCO frequency, and Fs is the NCO sample rate

#### lpf_freeze field -

0 -> Normal operation -1 -> Freeze current value

+

0 -> Normal operation

+

1 -> Freeze current value

#### lpf_zero field -

0 -> Normal operation -1 -> Zero and hold accumulator

+

0 -> Normal operation

+

1 -> Zero and hold accumulator

#### lpf_alpha field @@ -409,23 +417,23 @@ where Fn is the desired NCO frequency, and Fs is the NCO sample rate

#### prbs_error_insert field -

0 -> 1 : Insert bit error in Tx data (both Normal and PRBS) -1 -> 0 : Insert bit error in Tx data (both Normal and PRBS)

+

0 -> 1 : Insert bit error in Tx data (both Normal and PRBS)

+

1 -> 0 : Insert bit error in Tx data (both Normal and PRBS)

#### prbs_clear field -

0 -> 1 : Clear PRBS Counters -1 -> 0 : Clear PRBS Counters

+

0 -> 1 : Clear PRBS Counters

+

1 -> 0 : Clear PRBS Counters

#### prbs_manual_sync field -

0 -> 1 : Synchronize PRBS monitor -1 -> 0 : Synchronize PRBS monitor

+

0 -> 1 : Synchronize PRBS monitor

+

1 -> 0 : Synchronize PRBS monitor

#### prbs_sync_threshold field -

0 : Auto Sync Disabled -N > 0 : Auto sync after N errors

+

0 : Auto Sync Disabled

+

N > 0 : Auto sync after N errors

### PRBS_Initial_State register @@ -491,6 +499,10 @@ N > 0 : Auto sync after N errors

Number of bits received by the PRBS monitor since last BER can be calculated as the ratio of received bits to errored-bits

+

This register is write-to-capture.

+

To read data the following steps are required:

+

1 - Write any value to this register to capture read data

+

2 - Read the register

### PRBS_Error_Count register @@ -508,6 +520,10 @@ BER can be calculated as the ratio of received bits to errored-bits

Number of errored-bits received by the PRBS monitor since last sync BER can be calculated as the ratio of received bits to errored-bits

+

This register is write-to-capture.

+

To read data the following steps are required:

+

1 - Write any value to this register to capture read data

+

2 - Read the register

### LPF_Accum_F1 register @@ -524,6 +540,10 @@ BER can be calculated as the ratio of received bits to errored-bits

#### data field

PI Controller Accumulator Value

+

This register is write-to-capture.

+

To read data the following steps are required:

+

1 - Write any value to this register to capture read data

+

2 - Read the register

### LPF_Accum_F2 register @@ -540,6 +560,10 @@ BER can be calculated as the ratio of received bits to errored-bits

#### data field

PI Controller Accumulator Value

+

This register is write-to-capture.

+

To read data the following steps are required:

+

1 - Write any value to this register to capture read data

+

2 - Read the register

### axis_xfer_count register @@ -556,6 +580,10 @@ BER can be calculated as the ratio of received bits to errored-bits

#### data field

Number completed S_AXIS transfers

+

This register is write-to-capture.

+

To read data the following steps are required:

+

1 - Write any value to this register to capture read data

+

2 - Read the register

### Rx_Sample_Discard register @@ -605,15 +633,17 @@ BER can be calculated as the ratio of received bits to errored-bits

- Base Offset: 0x6C - Size: 0x4 -

Frequency offet applied to the F1 NCO

- -|Bits|Identifier|Access|Reset| Name | -|----|----------|------|-----|-----------------------| -|31:0| data | rw | 0x0 |F1 NCO Frequency Adjust| +|Bits|Identifier|Access|Reset|Name| +|----|----------|------|-----|----| +|31:0| data | rw | 0x0 | — | #### data field

Frequency offet applied to the F1 NCO

+

This register is write-to-capture.

+

To read data the following steps are required:

+

1 - Write any value to this register to capture read data

+

2 - Read the register

### f2_nco_adjust register @@ -621,15 +651,17 @@ BER can be calculated as the ratio of received bits to errored-bits

- Base Offset: 0x70 - Size: 0x4 -

Frequency offet applied to the F2 NCO

- -|Bits|Identifier|Access|Reset| Name | -|----|----------|------|-----|-----------------------| -|31:0| data | rw | 0x0 |F2 NCO Frequency Adjust| +|Bits|Identifier|Access|Reset|Name| +|----|----------|------|-----|----| +|31:0| data | rw | 0x0 | — | #### data field

Frequency offet applied to the F2 NCO

+

This register is write-to-capture.

+

To read data the following steps are required:

+

1 - Write any value to this register to capture read data

+

2 - Read the register

### f1_error register @@ -637,15 +669,17 @@ BER can be calculated as the ratio of received bits to errored-bits

- Base Offset: 0x74 - Size: 0x4 -

Error value of the F1 Costas loop after each active bit period

- -|Bits|Identifier|Access|Reset| Name | -|----|----------|------|-----|--------------| -|31:0| data | rw | 0x0 |F1 Error Value| +|Bits|Identifier|Access|Reset|Name| +|----|----------|------|-----|----| +|31:0| data | rw | 0x0 | — | #### data field

Error value of the F1 Costas loop after each active bit period

+

This register is write-to-capture.

+

To read data the following steps are required:

+

1 - Write any value to this register to capture read data

+

2 - Read the register

### f2_error register @@ -653,15 +687,17 @@ BER can be calculated as the ratio of received bits to errored-bits

- Base Offset: 0x78 - Size: 0x4 -

Error value of the F2 Costas loop after each active bit period

- -|Bits|Identifier|Access|Reset| Name | -|----|----------|------|-----|--------------| -|31:0| data | rw | 0x0 |F2 Error Value| +|Bits|Identifier|Access|Reset|Name| +|----|----------|------|-----|----| +|31:0| data | rw | 0x0 | — | #### data field

Error value of the F2 Costas loop after each active bit period

+

This register is write-to-capture.

+

To read data the following steps are required:

+

1 - Write any value to this register to capture read data

+

2 - Read the register

### Tx_Sync_Ctrl register @@ -680,27 +716,27 @@ BER can be calculated as the ratio of received bits to errored-bits

#### tx_sync_ena field -

0 -> Disable sync transmission -1 -> Enable sync transmission when PTT is asserted

+

0 -> Disable sync transmission

+

1 -> Enable sync transmission when PTT is asserted

#### tx_sync_force field -

0 : Normal operation) -1 : Transmit synchronization pattern)

+

0 : Normal operation

+

1 : Transmit synchronization pattern

#### tx_sync_f1 field

Enables/Disables transmission of F1 tone for receiver synchronization -0 : F1 tone transmission disabled -1 : F1 tone transmission enabled -Both F1 and F2 can be enabled at the same time

+0 : F1 tone transmission disabled

+

1 : F1 tone transmission enabled

+

Both F1 and F2 can be enabled at the same time

#### tx_sync_f2 field

Enables/Disables transmission of F2 tone for receiver synchronization -0 : F2 tone transmission disabled -1 : F2 tone transmission enabled -Both F1 and F2 can be enabled at the same time

+0 : F2 tone transmission disabled

+

1 : F2 tone transmission enabled

+

Both F1 and F2 can be enabled at the same time

### Tx_Sync_Cnt register @@ -716,9 +752,9 @@ Both F1 and F2 can be enabled at the same time

#### tx_sync_cnt field -

Value from 0x00_0000 to 0xFF_FFFF. -This value represents the number bit-times the synchronization -signal should be sent after PTT is asserted.

+

Value from 0x00_0000 to 0xFF_FFFF.

+

This value represents the number bit-times the synchronization

+

signal should be sent after PTT is asserted.

### lowpass_ema_alpha1 register @@ -766,7 +802,11 @@ signal should be sent after PTT is asserted.

#### data field -

Value that represent the RMS power of the incoming I;

+

Value that represent the RMS power of the incoming I

+

This register is write-to-capture.

+

To read data the following steps are required:

+

1 - Write any value to this register to capture read data

+

2 - Read the register

### tx_async_fifo_rd_wr_ptr register @@ -780,8 +820,13 @@ signal should be sent after PTT is asserted.

#### data field -

Bits 31:16 -> write pointer (12-bits) -Bits 15:00 -> read pointer (12-bits)

+

Read and Write Pointers

+

Bits 31:16 - write pointer (12-bits)

+

Bits 15:00 - read pointer (12-bits)

+

This register is write-to-capture.

+

To read data the following steps are required:

+

1 - Write any value to this register to capture read data

+

2 - Read the register

### rx_async_fifo_rd_wr_ptr register @@ -795,5 +840,10 @@ Bits 15:00 -> read pointer (12-bits)

#### data field -

Bits 31:16 -> write pointer (12-bits) -Bits 15:00 -> read pointer (12-bits)

+

Read and Write Pointers

+

Bits 31:16 - write pointer (12-bits)

+

Bits 15:00 - read pointer (12-bits)

+

This register is write-to-capture.

+

To read data the following steps are required:

+

1 - Write any value to this register to capture read data

+

2 - Read the register

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b/rdl/outputs/python/msk_top_regs/reg_model/msk_top_regs.py @@ -76,7 +76,7 @@ -class msk_top_regs_data32_desc_7b98a70e_cls(FieldAsyncReadWrite): +class msk_top_regs_data32_desc_52ad9f96_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -87,8 +87,11 @@ class msk_top_regs_data32_desc_7b98a70e_cls(FieldAsyncReadWrite): +==============+=========================================================================+ | Description | .. raw:: html | | | | - | |

Bits 31:16 -> write pointer (12-bits) Bits 15:00 -> read | - | | pointer (12-bits)

| + | |

Read and Write Pointers

Bits 31:16 - write pointer | + | | (12-bits)

Bits 15:00 - read pointer (12-bits)

This | + | | register is write-to-capture.

To read data the following | + | | steps are required:

1 - Write any value to this register to | + | | capture read data

2 - Read the register

| +--------------+-------------------------------------------------------------------------+ """ @@ -101,14 +104,14 @@ class msk_top_regs_data32_desc_7b98a70e_cls(FieldAsyncReadWrite): @property def rdl_desc(self) -> str: - return "Bits 31:16 -\u003e write pointer (12-bits)\nBits 15:00 -\u003e read pointer (12-bits)" + return "Read and Write Pointers\n\nBits 31:16 - write pointer (12-bits)\n\nBits 15:00 - read pointer (12-bits)\n\nThis register is write-to-capture.\n\nTo read data the following steps are required:\n\n1 - Write any value to this register to capture read data\n\n2 - Read the register" -class msk_top_regs_observation_data_data_cf6acbd7_name_8a90eed1_cls(RegAsyncReadWrite): +class msk_top_regs_observation_data_data_dbd8270c_name_8a90eed1_cls(RegAsyncReadWrite): """ Class to represent a register in the register model @@ -141,7 +144,7 @@ def __init__(self, # build the field attributes - self.__data:msk_top_regs_data32_desc_7b98a70e_cls = msk_top_regs_data32_desc_7b98a70e_cls( + self.__data:msk_top_regs_data32_desc_52ad9f96_cls = msk_top_regs_data32_desc_52ad9f96_cls( parent_register=self, size_props=FieldSizeProps( width=32, @@ -172,7 +175,7 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field # build the properties for the fields @property - def data(self) -> msk_top_regs_data32_desc_7b98a70e_cls: + def data(self) -> msk_top_regs_data32_desc_52ad9f96_cls: """ Property to access data field of the register @@ -182,8 +185,11 @@ def data(self) -> msk_top_regs_data32_desc_7b98a70e_cls: +==============+=========================================================================+ | Description | .. raw:: html | | | | - | |

Bits 31:16 -> write pointer (12-bits) Bits 15:00 -> read | - | | pointer (12-bits)

| + | |

Read and Write Pointers

Bits 31:16 - write pointer | + | | (12-bits)

Bits 15:00 - read pointer (12-bits)

This | + | | register is write-to-capture.

To read data the following | + | | steps are required:

1 - Write any value to this register to | + | | capture read data

2 - Read the register

| +--------------+-------------------------------------------------------------------------+ """ return self.__data @@ -208,7 +214,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_data32_desc_7b98a70e_cls: + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_data32_desc_52ad9f96_cls: return super().get_child_by_system_rdl_name(name) @@ -229,7 +235,7 @@ def rdl_name(self) -> str: -class msk_top_regs_data32_desc_7b98a70e_0x0x105c7600_cls(FieldAsyncReadWrite): +class msk_top_regs_data32_desc_52ad9f96_0x0x105270e0_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -240,8 +246,11 @@ class msk_top_regs_data32_desc_7b98a70e_0x0x105c7600_cls(FieldAsyncReadWrite): +==============+=========================================================================+ | Description | .. raw:: html | | | | - | |

Bits 31:16 -> write pointer (12-bits) Bits 15:00 -> read | - | | pointer (12-bits)

| + | |

Read and Write Pointers

Bits 31:16 - write pointer | + | | (12-bits)

Bits 15:00 - read pointer (12-bits)

This | + | | register is write-to-capture.

To read data the following | + | | steps are required:

1 - Write any value to this register to | + | | capture read data

2 - Read the register

| +--------------+-------------------------------------------------------------------------+ """ @@ -254,14 +263,14 @@ class msk_top_regs_data32_desc_7b98a70e_0x0x105c7600_cls(FieldAsyncReadWrite): @property def rdl_desc(self) -> str: - return "Bits 31:16 -\u003e write pointer (12-bits)\nBits 15:00 -\u003e read pointer (12-bits)" + return "Read and Write Pointers\n\nBits 31:16 - write pointer (12-bits)\n\nBits 15:00 - read pointer (12-bits)\n\nThis register is write-to-capture.\n\nTo read data the following steps are required:\n\n1 - Write any value to this register to capture read data\n\n2 - Read the register" -class msk_top_regs_observation_data_data_cf6acbd7_name_aa4ec676_cls(RegAsyncReadWrite): +class msk_top_regs_observation_data_data_dbd8270c_name_aa4ec676_cls(RegAsyncReadWrite): """ Class to represent a register in the register model @@ -294,7 +303,7 @@ def __init__(self, # build the field attributes - self.__data:msk_top_regs_data32_desc_7b98a70e_0x0x105c7600_cls = msk_top_regs_data32_desc_7b98a70e_0x0x105c7600_cls( + self.__data:msk_top_regs_data32_desc_52ad9f96_0x0x105270e0_cls = msk_top_regs_data32_desc_52ad9f96_0x0x105270e0_cls( parent_register=self, size_props=FieldSizeProps( width=32, @@ -325,7 +334,7 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field # build the properties for the fields @property - def data(self) -> msk_top_regs_data32_desc_7b98a70e_0x0x105c7600_cls: + def data(self) -> msk_top_regs_data32_desc_52ad9f96_0x0x105270e0_cls: """ Property to access data field of the register @@ -335,8 +344,11 @@ def data(self) -> msk_top_regs_data32_desc_7b98a70e_0x0x105c7600_cls: +==============+=========================================================================+ | Description | .. raw:: html | | | | - | |

Bits 31:16 -> write pointer (12-bits) Bits 15:00 -> read | - | | pointer (12-bits)

| + | |

Read and Write Pointers

Bits 31:16 - write pointer | + | | (12-bits)

Bits 15:00 - read pointer (12-bits)

This | + | | register is write-to-capture.

To read data the following | + | | steps are required:

1 - Write any value to this register to | + | | capture read data

2 - Read the register

| +--------------+-------------------------------------------------------------------------+ """ return self.__data @@ -361,7 +373,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_data32_desc_7b98a70e_0x0x105c7600_cls: + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_data32_desc_52ad9f96_0x0x105270e0_cls: return super().get_child_by_system_rdl_name(name) @@ -397,7 +409,10 @@ class msk_top_regs_rx_power_data_cls(FieldAsyncReadWrite): +--------------+-------------------------------------------------------------------------+ | Description | .. raw:: html | | | | - | |

Value that represent the RMS power of the incoming I;

| + | |

Value that represent the RMS power of the incoming I

| + | |

This register is write-to-capture.

To read data the | + | | following steps are required:

1 - Write any value to this | + | | register to capture read data

2 - Read the register

| +--------------+-------------------------------------------------------------------------+ """ @@ -413,7 +428,7 @@ def rdl_name(self) -> str: return "Receive Power" @property def rdl_desc(self) -> str: - return "Value that represent the RMS power of the incoming I;" + return "Value that represent the RMS power of the incoming I\n\nThis register is write-to-capture.\n\nTo read data the following steps are required:\n\n1 - Write any value to this register to capture read data\n\n2 - Read the register" @@ -502,7 +517,10 @@ def data(self) -> msk_top_regs_rx_power_data_cls: +--------------+-------------------------------------------------------------------------+ | Description | .. raw:: html | | | | - | |

Value that represent the RMS power of the incoming I;

| + | |

Value that represent the RMS power of the incoming I

| + | |

This register is write-to-capture.

To read data the | + | | following steps are required:

1 - Write any value to this | + | | register to capture read data

2 - Read the register

| +--------------+-------------------------------------------------------------------------+ """ return self.__data @@ -720,7 +738,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_lowpass_ema_alpha_alpha_0x0x105c7501_cls(FieldAsyncReadWrite): +class msk_top_regs_lowpass_ema_alpha_alpha_0x0x10527152_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -758,7 +776,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_lowpass_ema_alpha_0x0x105c0c74_cls(RegAsyncReadWrite): +class msk_top_regs_lowpass_ema_alpha_0x0x1052719d_cls(RegAsyncReadWrite): """ Class to represent a register in the register model @@ -795,7 +813,7 @@ def __init__(self, # build the field attributes - self.__alpha:msk_top_regs_lowpass_ema_alpha_alpha_0x0x105c7501_cls = msk_top_regs_lowpass_ema_alpha_alpha_0x0x105c7501_cls( + self.__alpha:msk_top_regs_lowpass_ema_alpha_alpha_0x0x10527152_cls = msk_top_regs_lowpass_ema_alpha_alpha_0x0x10527152_cls( parent_register=self, size_props=FieldSizeProps( width=18, @@ -826,7 +844,7 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field # build the properties for the fields @property - def alpha(self) -> msk_top_regs_lowpass_ema_alpha_alpha_0x0x105c7501_cls: + def alpha(self) -> msk_top_regs_lowpass_ema_alpha_alpha_0x0x10527152_cls: """ Property to access alpha field of the register @@ -865,7 +883,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_lowpass_ema_alpha_alpha_0x0x105c7501_cls: + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_lowpass_ema_alpha_alpha_0x0x10527152_cls: return super().get_child_by_system_rdl_name(name) @@ -904,9 +922,9 @@ class msk_top_regs_tx_sync_cnt_tx_sync_cnt_cls(FieldAsyncReadWrite): +--------------+-------------------------------------------------------------------------+ | Description | .. raw:: html | | | | - | |

Value from 0x00_0000 to 0xFF_FFFF. This value represents the | - | | number bit-times the synchronization signal should be sent after | - | | PTT is asserted.

| + | |

Value from 0x00_0000 to 0xFF_FFFF.

This value | + | | represents the number bit-times the synchronization

signal | + | | should be sent after PTT is asserted.

| +--------------+-------------------------------------------------------------------------+ """ @@ -922,7 +940,7 @@ def rdl_name(self) -> str: return "Tx sync duration" @property def rdl_desc(self) -> str: - return "Value from 0x00_0000 to 0xFF_FFFF. \nThis value represents the number bit-times the synchronization \nsignal should be sent after PTT is asserted." + return "Value from 0x00_0000 to 0xFF_FFFF. \n\nThis value represents the number bit-times the synchronization \n\nsignal should be sent after PTT is asserted." @@ -1011,9 +1029,9 @@ def tx_sync_cnt(self) -> msk_top_regs_tx_sync_cnt_tx_sync_cnt_cls: +--------------+-------------------------------------------------------------------------+ | Description | .. raw:: html | | | | - | |

Value from 0x00_0000 to 0xFF_FFFF. This value represents the | - | | number bit-times the synchronization signal should be sent after | - | | PTT is asserted.

| + | |

Value from 0x00_0000 to 0xFF_FFFF.

This value | + | | represents the number bit-times the synchronization

signal | + | | should be sent after PTT is asserted.

| +--------------+-------------------------------------------------------------------------+ """ return self.__tx_sync_cnt @@ -1078,9 +1096,9 @@ class msk_top_regs_tx_sync_ctrl_tx_sync_f2_cls(FieldAsyncReadWrite): | Description | .. raw:: html | | | | | |

Enables/Disables transmission of F2 tone for receiver | - | | synchronization 0 : F2 tone transmission disabled 1 : F2 tone | - | | transmission enabled Both F1 and F2 can be enabled at the same | - | | time

| + | | synchronization 0 : F2 tone transmission disabled

1 : F2 | + | | tone transmission enabled

Both F1 and F2 can be enabled at | + | | the same time

| +--------------+-------------------------------------------------------------------------+ """ @@ -1096,7 +1114,7 @@ def rdl_name(self) -> str: return "Tx F2 Sync Enable" @property def rdl_desc(self) -> str: - return "Enables/Disables transmission of F2 tone for receiver synchronization\n0 : F2 tone transmission disabled\n1 : F2 tone transmission enabled\nBoth F1 and F2 can be enabled at the same time" + return "Enables/Disables transmission of F2 tone for receiver synchronization\n0 : F2 tone transmission disabled\n\n1 : F2 tone transmission enabled\n\nBoth F1 and F2 can be enabled at the same time" @@ -1120,9 +1138,9 @@ class msk_top_regs_tx_sync_ctrl_tx_sync_f1_cls(FieldAsyncReadWrite): | Description | .. raw:: html | | | | | |

Enables/Disables transmission of F1 tone for receiver | - | | synchronization 0 : F1 tone transmission disabled 1 : F1 tone | - | | transmission enabled Both F1 and F2 can be enabled at the same | - | | time

| + | | synchronization 0 : F1 tone transmission disabled

1 : F1 | + | | tone transmission enabled

Both F1 and F2 can be enabled at | + | | the same time

| +--------------+-------------------------------------------------------------------------+ """ @@ -1138,7 +1156,7 @@ def rdl_name(self) -> str: return "Tx F1 Sync Enable" @property def rdl_desc(self) -> str: - return "Enables/Disables transmission of F1 tone for receiver synchronization\n0 : F1 tone transmission disabled\n1 : F1 tone transmission enabled\nBoth F1 and F2 can be enabled at the same time" + return "Enables/Disables transmission of F1 tone for receiver synchronization\n0 : F1 tone transmission disabled\n\n1 : F1 tone transmission enabled\n\nBoth F1 and F2 can be enabled at the same time" @@ -1161,7 +1179,8 @@ class msk_top_regs_tx_sync_ctrl_tx_sync_force_cls(FieldAsyncReadWrite): +--------------+-------------------------------------------------------------------------+ | Description | .. raw:: html | | | | - | |

0 : Normal operation) 1 : Transmit synchronization pattern)

| + | |

0 : Normal operation

1 : Transmit synchronization | + | | pattern

| +--------------+-------------------------------------------------------------------------+ """ @@ -1177,7 +1196,7 @@ def rdl_name(self) -> str: return "Tx Sync Force" @property def rdl_desc(self) -> str: - return "0 : Normal operation)\n1 : Transmit synchronization pattern)" + return "0 : Normal operation\n\n1 : Transmit synchronization pattern" @@ -1200,7 +1219,7 @@ class msk_top_regs_tx_sync_ctrl_tx_sync_ena_cls(FieldAsyncReadWrite): +--------------+-------------------------------------------------------------------------+ | Description | .. raw:: html | | | | - | |

0 -> Disable sync transmission 1 -> Enable sync | + | |

0 -> Disable sync transmission

1 -> Enable sync | | | transmission when PTT is asserted

| +--------------+-------------------------------------------------------------------------+ """ @@ -1217,7 +1236,7 @@ def rdl_name(self) -> str: return "Tx Sync Enable" @property def rdl_desc(self) -> str: - return "0 -\u003e Disable sync transmission\n1 -\u003e Enable sync transmission when PTT is asserted" + return "0 -\u003e Disable sync transmission\n\n1 -\u003e Enable sync transmission when PTT is asserted" @@ -1352,7 +1371,7 @@ def tx_sync_ena(self) -> msk_top_regs_tx_sync_ctrl_tx_sync_ena_cls: +--------------+-------------------------------------------------------------------------+ | Description | .. raw:: html | | | | - | |

0 -> Disable sync transmission 1 -> Enable sync | + | |

0 -> Disable sync transmission

1 -> Enable sync | | | transmission when PTT is asserted

| +--------------+-------------------------------------------------------------------------+ """ @@ -1372,7 +1391,8 @@ def tx_sync_force(self) -> msk_top_regs_tx_sync_ctrl_tx_sync_force_cls: +--------------+-------------------------------------------------------------------------+ | Description | .. raw:: html | | | | - | |

0 : Normal operation) 1 : Transmit synchronization pattern)

| + | |

0 : Normal operation

1 : Transmit synchronization | + | | pattern

| +--------------+-------------------------------------------------------------------------+ """ return self.__tx_sync_force @@ -1392,9 +1412,9 @@ def tx_sync_f1(self) -> msk_top_regs_tx_sync_ctrl_tx_sync_f1_cls: | Description | .. raw:: html | | | | | |

Enables/Disables transmission of F1 tone for receiver | - | | synchronization 0 : F1 tone transmission disabled 1 : F1 tone | - | | transmission enabled Both F1 and F2 can be enabled at the same | - | | time

| + | | synchronization 0 : F1 tone transmission disabled

1 : F1 | + | | tone transmission enabled

Both F1 and F2 can be enabled at | + | | the same time

| +--------------+-------------------------------------------------------------------------+ """ return self.__tx_sync_f1 @@ -1414,9 +1434,9 @@ def tx_sync_f2(self) -> msk_top_regs_tx_sync_ctrl_tx_sync_f2_cls: | Description | .. raw:: html | | | | | |

Enables/Disables transmission of F2 tone for receiver | - | | synchronization 0 : F2 tone transmission disabled 1 : F2 tone | - | | transmission enabled Both F1 and F2 can be enabled at the same | - | | time

| + | | synchronization 0 : F2 tone transmission disabled

1 : F2 | + | | tone transmission enabled

Both F1 and F2 can be enabled at | + | | the same time

| +--------------+-------------------------------------------------------------------------+ """ return self.__tx_sync_f2 @@ -1484,7 +1504,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_data32_desc_70869502_name_3de9a0d3_cls(FieldAsyncReadWrite): +class msk_top_regs_data32_desc_c8bf066a_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -1493,14 +1513,13 @@ class msk_top_regs_data32_desc_70869502_name_3de9a0d3_cls(FieldAsyncReadWrite): | SystemRDL | Value | | Field | | +==============+=========================================================================+ - | Name | .. raw:: html | - | | | - | | F2 Error Value | - +--------------+-------------------------------------------------------------------------+ | Description | .. raw:: html | | | | | |

Error value of the F2 Costas loop after each active bit | - | | period

| + | | period

This register is write-to-capture.

To read | + | | data the following steps are required:

1 - Write any value | + | | to this register to capture read data

2 - Read the | + | | register

| +--------------+-------------------------------------------------------------------------+ """ @@ -1511,19 +1530,16 @@ class msk_top_regs_data32_desc_70869502_name_3de9a0d3_cls(FieldAsyncReadWrite): - @property - def rdl_name(self) -> str: - return "F2 Error Value" @property def rdl_desc(self) -> str: - return "Error value of the F2 Costas loop after each active bit period" + return "Error value of the F2 Costas loop after each active bit period\n\nThis register is write-to-capture.\n\nTo read data the following steps are required:\n\n1 - Write any value to this register to capture read data\n\n2 - Read the register" -class msk_top_regs_observation_data_data_272a00b6_desc_70869502_name_3de9a0d3_cls(RegAsyncReadWrite): +class msk_top_regs_observation_data_data_0a9850a4_name_3de9a0d3_cls(RegAsyncReadWrite): """ Class to represent a register in the register model @@ -1535,11 +1551,6 @@ class msk_top_regs_observation_data_data_272a00b6_desc_70869502_name_3de9a0d3_cl | | | | | F2 Error Value | +--------------+-------------------------------------------------------------------------+ - | Description | .. raw:: html | - | | | - | |

Error value of the F2 Costas loop after each active bit | - | | period

| - +--------------+-------------------------------------------------------------------------+ """ __slots__ : list[str] = ['__data'] @@ -1561,7 +1572,7 @@ def __init__(self, # build the field attributes - self.__data:msk_top_regs_data32_desc_70869502_name_3de9a0d3_cls = msk_top_regs_data32_desc_70869502_name_3de9a0d3_cls( + self.__data:msk_top_regs_data32_desc_c8bf066a_cls = msk_top_regs_data32_desc_c8bf066a_cls( parent_register=self, size_props=FieldSizeProps( width=32, @@ -1592,7 +1603,7 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field # build the properties for the fields @property - def data(self) -> msk_top_regs_data32_desc_70869502_name_3de9a0d3_cls: + def data(self) -> msk_top_regs_data32_desc_c8bf066a_cls: """ Property to access data field of the register @@ -1600,14 +1611,13 @@ def data(self) -> msk_top_regs_data32_desc_70869502_name_3de9a0d3_cls: | SystemRDL | Value | | Field | | +==============+=========================================================================+ - | Name | .. raw:: html | - | | | - | | F2 Error Value | - +--------------+-------------------------------------------------------------------------+ | Description | .. raw:: html | | | | | |

Error value of the F2 Costas loop after each active bit | - | | period

| + | | period

This register is write-to-capture.

To read | + | | data the following steps are required:

1 - Write any value | + | | to this register to capture read data

2 - Read the | + | | register

| +--------------+-------------------------------------------------------------------------+ """ return self.__data @@ -1632,7 +1642,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_data32_desc_70869502_name_3de9a0d3_cls: + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_data32_desc_c8bf066a_cls: return super().get_child_by_system_rdl_name(name) @@ -1646,9 +1656,6 @@ def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_data32_desc_70 @property def rdl_name(self) -> str: return "F2 Error Value" - @property - def rdl_desc(self) -> str: - return "Error value of the F2 Costas loop after each active bit period" @@ -1656,7 +1663,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_data32_desc_417e1c96_name_3b640507_cls(FieldAsyncReadWrite): +class msk_top_regs_data32_desc_83db1b72_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -1665,14 +1672,13 @@ class msk_top_regs_data32_desc_417e1c96_name_3b640507_cls(FieldAsyncReadWrite): | SystemRDL | Value | | Field | | +==============+=========================================================================+ - | Name | .. raw:: html | - | | | - | | F1 Error Value | - +--------------+-------------------------------------------------------------------------+ | Description | .. raw:: html | | | | | |

Error value of the F1 Costas loop after each active bit | - | | period

| + | | period

This register is write-to-capture.

To read | + | | data the following steps are required:

1 - Write any value | + | | to this register to capture read data

2 - Read the | + | | register

| +--------------+-------------------------------------------------------------------------+ """ @@ -1683,19 +1689,16 @@ class msk_top_regs_data32_desc_417e1c96_name_3b640507_cls(FieldAsyncReadWrite): - @property - def rdl_name(self) -> str: - return "F1 Error Value" @property def rdl_desc(self) -> str: - return "Error value of the F1 Costas loop after each active bit period" + return "Error value of the F1 Costas loop after each active bit period\n\nThis register is write-to-capture.\n\nTo read data the following steps are required:\n\n1 - Write any value to this register to capture read data\n\n2 - Read the register" -class msk_top_regs_observation_data_data_25a21249_desc_417e1c96_name_3b640507_cls(RegAsyncReadWrite): +class msk_top_regs_observation_data_data_f83682dd_name_3b640507_cls(RegAsyncReadWrite): """ Class to represent a register in the register model @@ -1707,11 +1710,6 @@ class msk_top_regs_observation_data_data_25a21249_desc_417e1c96_name_3b640507_cl | | | | | F1 Error Value | +--------------+-------------------------------------------------------------------------+ - | Description | .. raw:: html | - | | | - | |

Error value of the F1 Costas loop after each active bit | - | | period

| - +--------------+-------------------------------------------------------------------------+ """ __slots__ : list[str] = ['__data'] @@ -1733,7 +1731,7 @@ def __init__(self, # build the field attributes - self.__data:msk_top_regs_data32_desc_417e1c96_name_3b640507_cls = msk_top_regs_data32_desc_417e1c96_name_3b640507_cls( + self.__data:msk_top_regs_data32_desc_83db1b72_cls = msk_top_regs_data32_desc_83db1b72_cls( parent_register=self, size_props=FieldSizeProps( width=32, @@ -1764,7 +1762,7 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field # build the properties for the fields @property - def data(self) -> msk_top_regs_data32_desc_417e1c96_name_3b640507_cls: + def data(self) -> msk_top_regs_data32_desc_83db1b72_cls: """ Property to access data field of the register @@ -1772,14 +1770,13 @@ def data(self) -> msk_top_regs_data32_desc_417e1c96_name_3b640507_cls: | SystemRDL | Value | | Field | | +==============+=========================================================================+ - | Name | .. raw:: html | - | | | - | | F1 Error Value | - +--------------+-------------------------------------------------------------------------+ | Description | .. raw:: html | | | | | |

Error value of the F1 Costas loop after each active bit | - | | period

| + | | period

This register is write-to-capture.

To read | + | | data the following steps are required:

1 - Write any value | + | | to this register to capture read data

2 - Read the | + | | register

| +--------------+-------------------------------------------------------------------------+ """ return self.__data @@ -1804,7 +1801,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_data32_desc_417e1c96_name_3b640507_cls: + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_data32_desc_83db1b72_cls: return super().get_child_by_system_rdl_name(name) @@ -1818,9 +1815,6 @@ def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_data32_desc_41 @property def rdl_name(self) -> str: return "F1 Error Value" - @property - def rdl_desc(self) -> str: - return "Error value of the F1 Costas loop after each active bit period" @@ -1828,7 +1822,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_data32_desc_ebde6d39_name_2c154788_cls(FieldAsyncReadWrite): +class msk_top_regs_data32_desc_13897f4c_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -1837,13 +1831,12 @@ class msk_top_regs_data32_desc_ebde6d39_name_2c154788_cls(FieldAsyncReadWrite): | SystemRDL | Value | | Field | | +==============+=========================================================================+ - | Name | .. raw:: html | - | | | - | | F2 NCO Frequency Adjust | - +--------------+-------------------------------------------------------------------------+ | Description | .. raw:: html | | | | - | |

Frequency offet applied to the F2 NCO

| + | |

Frequency offet applied to the F2 NCO

This register is | + | | write-to-capture.

To read data the following steps are | + | | required:

1 - Write any value to this register to capture | + | | read data

2 - Read the register

| +--------------+-------------------------------------------------------------------------+ """ @@ -1854,19 +1847,16 @@ class msk_top_regs_data32_desc_ebde6d39_name_2c154788_cls(FieldAsyncReadWrite): - @property - def rdl_name(self) -> str: - return "F2 NCO Frequency Adjust" @property def rdl_desc(self) -> str: - return "Frequency offet applied to the F2 NCO" + return "Frequency offet applied to the F2 NCO\n\nThis register is write-to-capture.\n\nTo read data the following steps are required:\n\n1 - Write any value to this register to capture read data\n\n2 - Read the register" -class msk_top_regs_observation_data_data_0515efaa_desc_ebde6d39_name_2c154788_cls(RegAsyncReadWrite): +class msk_top_regs_observation_data_data_5802c5b1_name_2c154788_cls(RegAsyncReadWrite): """ Class to represent a register in the register model @@ -1878,10 +1868,6 @@ class msk_top_regs_observation_data_data_0515efaa_desc_ebde6d39_name_2c154788_cl | | | | | F2 NCO Frequency Adjust | +--------------+-------------------------------------------------------------------------+ - | Description | .. raw:: html | - | | | - | |

Frequency offet applied to the F2 NCO

| - +--------------+-------------------------------------------------------------------------+ """ __slots__ : list[str] = ['__data'] @@ -1903,7 +1889,7 @@ def __init__(self, # build the field attributes - self.__data:msk_top_regs_data32_desc_ebde6d39_name_2c154788_cls = msk_top_regs_data32_desc_ebde6d39_name_2c154788_cls( + self.__data:msk_top_regs_data32_desc_13897f4c_cls = msk_top_regs_data32_desc_13897f4c_cls( parent_register=self, size_props=FieldSizeProps( width=32, @@ -1934,7 +1920,7 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field # build the properties for the fields @property - def data(self) -> msk_top_regs_data32_desc_ebde6d39_name_2c154788_cls: + def data(self) -> msk_top_regs_data32_desc_13897f4c_cls: """ Property to access data field of the register @@ -1942,13 +1928,12 @@ def data(self) -> msk_top_regs_data32_desc_ebde6d39_name_2c154788_cls: | SystemRDL | Value | | Field | | +==============+=========================================================================+ - | Name | .. raw:: html | - | | | - | | F2 NCO Frequency Adjust | - +--------------+-------------------------------------------------------------------------+ | Description | .. raw:: html | | | | - | |

Frequency offet applied to the F2 NCO

| + | |

Frequency offet applied to the F2 NCO

This register is | + | | write-to-capture.

To read data the following steps are | + | | required:

1 - Write any value to this register to capture | + | | read data

2 - Read the register

| +--------------+-------------------------------------------------------------------------+ """ return self.__data @@ -1973,7 +1958,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_data32_desc_ebde6d39_name_2c154788_cls: + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_data32_desc_13897f4c_cls: return super().get_child_by_system_rdl_name(name) @@ -1987,9 +1972,6 @@ def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_data32_desc_eb @property def rdl_name(self) -> str: return "F2 NCO Frequency Adjust" - @property - def rdl_desc(self) -> str: - return "Frequency offet applied to the F2 NCO" @@ -1997,7 +1979,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_data32_desc_64ff3689_name_d8ad3b25_cls(FieldAsyncReadWrite): +class msk_top_regs_data32_desc_0ed96915_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -2006,13 +1988,12 @@ class msk_top_regs_data32_desc_64ff3689_name_d8ad3b25_cls(FieldAsyncReadWrite): | SystemRDL | Value | | Field | | +==============+=========================================================================+ - | Name | .. raw:: html | - | | | - | | F1 NCO Frequency Adjust | - +--------------+-------------------------------------------------------------------------+ | Description | .. raw:: html | | | | - | |

Frequency offet applied to the F1 NCO

| + | |

Frequency offet applied to the F1 NCO

This register is | + | | write-to-capture.

To read data the following steps are | + | | required:

1 - Write any value to this register to capture | + | | read data

2 - Read the register

| +--------------+-------------------------------------------------------------------------+ """ @@ -2023,19 +2004,16 @@ class msk_top_regs_data32_desc_64ff3689_name_d8ad3b25_cls(FieldAsyncReadWrite): - @property - def rdl_name(self) -> str: - return "F1 NCO Frequency Adjust" @property def rdl_desc(self) -> str: - return "Frequency offet applied to the F1 NCO" + return "Frequency offet applied to the F1 NCO\n\nThis register is write-to-capture.\n\nTo read data the following steps are required:\n\n1 - Write any value to this register to capture read data\n\n2 - Read the register" -class msk_top_regs_observation_data_data_0c017ef4_desc_64ff3689_name_d8ad3b25_cls(RegAsyncReadWrite): +class msk_top_regs_observation_data_data_521c7d53_name_d8ad3b25_cls(RegAsyncReadWrite): """ Class to represent a register in the register model @@ -2047,10 +2025,6 @@ class msk_top_regs_observation_data_data_0c017ef4_desc_64ff3689_name_d8ad3b25_cl | | | | | F1 NCO Frequency Adjust | +--------------+-------------------------------------------------------------------------+ - | Description | .. raw:: html | - | | | - | |

Frequency offet applied to the F1 NCO

| - +--------------+-------------------------------------------------------------------------+ """ __slots__ : list[str] = ['__data'] @@ -2072,7 +2046,7 @@ def __init__(self, # build the field attributes - self.__data:msk_top_regs_data32_desc_64ff3689_name_d8ad3b25_cls = msk_top_regs_data32_desc_64ff3689_name_d8ad3b25_cls( + self.__data:msk_top_regs_data32_desc_0ed96915_cls = msk_top_regs_data32_desc_0ed96915_cls( parent_register=self, size_props=FieldSizeProps( width=32, @@ -2103,7 +2077,7 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field # build the properties for the fields @property - def data(self) -> msk_top_regs_data32_desc_64ff3689_name_d8ad3b25_cls: + def data(self) -> msk_top_regs_data32_desc_0ed96915_cls: """ Property to access data field of the register @@ -2111,13 +2085,12 @@ def data(self) -> msk_top_regs_data32_desc_64ff3689_name_d8ad3b25_cls: | SystemRDL | Value | | Field | | +==============+=========================================================================+ - | Name | .. raw:: html | - | | | - | | F1 NCO Frequency Adjust | - +--------------+-------------------------------------------------------------------------+ | Description | .. raw:: html | | | | - | |

Frequency offet applied to the F1 NCO

| + | |

Frequency offet applied to the F1 NCO

This register is | + | | write-to-capture.

To read data the following steps are | + | | required:

1 - Write any value to this register to capture | + | | read data

2 - Read the register

| +--------------+-------------------------------------------------------------------------+ """ return self.__data @@ -2142,7 +2115,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_data32_desc_64ff3689_name_d8ad3b25_cls: + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_data32_desc_0ed96915_cls: return super().get_child_by_system_rdl_name(name) @@ -2156,9 +2129,6 @@ def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_data32_desc_64 @property def rdl_name(self) -> str: return "F1 NCO Frequency Adjust" - @property - def rdl_desc(self) -> str: - return "Frequency offet applied to the F1 NCO" @@ -2687,7 +2657,10 @@ class msk_top_regs_msk_stat_3_data_cls(FieldAsyncReadWrite): +--------------+-------------------------------------------------------------------------+ | Description | .. raw:: html | | | | - | |

Number completed S_AXIS transfers

| + | |

Number completed S_AXIS transfers

This register is | + | | write-to-capture.

To read data the following steps are | + | | required:

1 - Write any value to this register to capture | + | | read data

2 - Read the register

| +--------------+-------------------------------------------------------------------------+ """ @@ -2703,7 +2676,7 @@ def rdl_name(self) -> str: return "S_AXIS Transfers" @property def rdl_desc(self) -> str: - return "Number completed S_AXIS transfers" + return "Number completed S_AXIS transfers\n\nThis register is write-to-capture.\n\nTo read data the following steps are required:\n\n1 - Write any value to this register to capture read data\n\n2 - Read the register" @@ -2792,7 +2765,10 @@ def data(self) -> msk_top_regs_msk_stat_3_data_cls: +--------------+-------------------------------------------------------------------------+ | Description | .. raw:: html | | | | - | |

Number completed S_AXIS transfers

| + | |

Number completed S_AXIS transfers

This register is | + | | write-to-capture.

To read data the following steps are | + | | required:

1 - Write any value to this register to capture | + | | read data

2 - Read the register

| +--------------+-------------------------------------------------------------------------+ """ return self.__data @@ -2856,7 +2832,10 @@ class msk_top_regs_stat_32_lpf_acc_data_cls(FieldAsyncReadWrite): +--------------+-------------------------------------------------------------------------+ | Description | .. raw:: html | | | | - | |

PI Controller Accumulator Value

| + | |

PI Controller Accumulator Value

This register is write- | + | | to-capture.

To read data the following steps are | + | | required:

1 - Write any value to this register to capture | + | | read data

2 - Read the register

| +--------------+-------------------------------------------------------------------------+ """ @@ -2872,7 +2851,7 @@ def rdl_name(self) -> str: return "PI Controller Accumulator Value" @property def rdl_desc(self) -> str: - return "PI Controller Accumulator Value" + return "PI Controller Accumulator Value\n\nThis register is write-to-capture.\n\nTo read data the following steps are required:\n\n1 - Write any value to this register to capture read data\n\n2 - Read the register" @@ -2961,7 +2940,10 @@ def data(self) -> msk_top_regs_stat_32_lpf_acc_data_cls: +--------------+-------------------------------------------------------------------------+ | Description | .. raw:: html | | | | - | |

PI Controller Accumulator Value

| + | |

PI Controller Accumulator Value

This register is write- | + | | to-capture.

To read data the following steps are | + | | required:

1 - Write any value to this register to capture | + | | read data

2 - Read the register

| +--------------+-------------------------------------------------------------------------+ """ return self.__data @@ -3010,7 +2992,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_stat_32_lpf_acc_data_0x0x105c2672_cls(FieldAsyncReadWrite): +class msk_top_regs_stat_32_lpf_acc_data_0x0x10527359_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -3025,7 +3007,10 @@ class msk_top_regs_stat_32_lpf_acc_data_0x0x105c2672_cls(FieldAsyncReadWrite): +--------------+-------------------------------------------------------------------------+ | Description | .. raw:: html | | | | - | |

PI Controller Accumulator Value

| + | |

PI Controller Accumulator Value

This register is write- | + | | to-capture.

To read data the following steps are | + | | required:

1 - Write any value to this register to capture | + | | read data

2 - Read the register

| +--------------+-------------------------------------------------------------------------+ """ @@ -3041,7 +3026,7 @@ def rdl_name(self) -> str: return "PI Controller Accumulator Value" @property def rdl_desc(self) -> str: - return "PI Controller Accumulator Value" + return "PI Controller Accumulator Value\n\nThis register is write-to-capture.\n\nTo read data the following steps are required:\n\n1 - Write any value to this register to capture read data\n\n2 - Read the register" @@ -3085,7 +3070,7 @@ def __init__(self, # build the field attributes - self.__data:msk_top_regs_stat_32_lpf_acc_data_0x0x105c2672_cls = msk_top_regs_stat_32_lpf_acc_data_0x0x105c2672_cls( + self.__data:msk_top_regs_stat_32_lpf_acc_data_0x0x10527359_cls = msk_top_regs_stat_32_lpf_acc_data_0x0x10527359_cls( parent_register=self, size_props=FieldSizeProps( width=32, @@ -3116,7 +3101,7 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field # build the properties for the fields @property - def data(self) -> msk_top_regs_stat_32_lpf_acc_data_0x0x105c2672_cls: + def data(self) -> msk_top_regs_stat_32_lpf_acc_data_0x0x10527359_cls: """ Property to access data field of the register @@ -3130,7 +3115,10 @@ def data(self) -> msk_top_regs_stat_32_lpf_acc_data_0x0x105c2672_cls: +--------------+-------------------------------------------------------------------------+ | Description | .. raw:: html | | | | - | |

PI Controller Accumulator Value

| + | |

PI Controller Accumulator Value

This register is write- | + | | to-capture.

To read data the following steps are | + | | required:

1 - Write any value to this register to capture | + | | read data

2 - Read the register

| +--------------+-------------------------------------------------------------------------+ """ return self.__data @@ -3155,7 +3143,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_stat_32_lpf_acc_data_0x0x105c2672_cls: + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_stat_32_lpf_acc_data_0x0x10527359_cls: return super().get_child_by_system_rdl_name(name) @@ -3196,7 +3184,10 @@ class msk_top_regs_stat_32_errs_data_cls(FieldAsyncReadWrite): | | | | |

Number of errored-bits received by the PRBS monitor since last | | | sync BER can be calculated as the ratio of received bits to | - | | errored-bits

| + | | errored-bits

This register is write-to-capture.

To | + | | read data the following steps are required:

1 - Write any | + | | value to this register to capture read data

2 - Read the | + | | register

| +--------------+-------------------------------------------------------------------------+ """ @@ -3212,7 +3203,7 @@ def rdl_name(self) -> str: return "PRBS Bit Errors" @property def rdl_desc(self) -> str: - return "Number of errored-bits received by the PRBS monitor since last sync\nBER can be calculated as the ratio of received bits to errored-bits" + return "Number of errored-bits received by the PRBS monitor since last sync\nBER can be calculated as the ratio of received bits to errored-bits\n\nThis register is write-to-capture.\n\nTo read data the following steps are required:\n\n1 - Write any value to this register to capture read data\n\n2 - Read the register" @@ -3303,7 +3294,10 @@ def data(self) -> msk_top_regs_stat_32_errs_data_cls: | | | | |

Number of errored-bits received by the PRBS monitor since last | | | sync BER can be calculated as the ratio of received bits to | - | | errored-bits

| + | | errored-bits

This register is write-to-capture.

To | + | | read data the following steps are required:

1 - Write any | + | | value to this register to capture read data

2 - Read the | + | | register

| +--------------+-------------------------------------------------------------------------+ """ return self.__data @@ -3369,6 +3363,9 @@ class msk_top_regs_stat_32_bits_data_cls(FieldAsyncReadWrite): | | | | |

Number of bits received by the PRBS monitor since last BER can | | | be calculated as the ratio of received bits to errored-bits

| + | |

This register is write-to-capture.

To read data the | + | | following steps are required:

1 - Write any value to this | + | | register to capture read data

2 - Read the register

| +--------------+-------------------------------------------------------------------------+ """ @@ -3384,7 +3381,7 @@ def rdl_name(self) -> str: return "PRBS Bits Received" @property def rdl_desc(self) -> str: - return "Number of bits received by the PRBS monitor since last\nBER can be calculated as the ratio of received bits to errored-bits" + return "Number of bits received by the PRBS monitor since last\nBER can be calculated as the ratio of received bits to errored-bits\n\nThis register is write-to-capture.\n\nTo read data the following steps are required:\n\n1 - Write any value to this register to capture read data\n\n2 - Read the register" @@ -3475,6 +3472,9 @@ def data(self) -> msk_top_regs_stat_32_bits_data_cls: | | | | |

Number of bits received by the PRBS monitor since last BER can | | | be calculated as the ratio of received bits to errored-bits

| + | |

This register is write-to-capture.

To read data the | + | | following steps are required:

1 - Write any value to this | + | | register to capture read data

2 - Read the register

| +--------------+-------------------------------------------------------------------------+ """ return self.__data @@ -4049,7 +4049,8 @@ class msk_top_regs_prbs_ctrl_prbs_sync_threshold_cls(FieldAsyncReadWrite): +--------------+-------------------------------------------------------------------------+ | Description | .. raw:: html | | | | - | |

0 : Auto Sync Disabled N > 0 : Auto sync after N errors

| + | |

0 : Auto Sync Disabled

N > 0 : Auto sync after N | + | | errors

| +--------------+-------------------------------------------------------------------------+ """ @@ -4065,7 +4066,7 @@ def rdl_name(self) -> str: return "PRBS Auto Sync Threshold" @property def rdl_desc(self) -> str: - return "0 : Auto Sync Disabled\nN \u003e 0 : Auto sync after N errors" + return "0 : Auto Sync Disabled\n\nN \u003e 0 : Auto sync after N errors" @@ -4120,8 +4121,8 @@ class msk_top_regs_prbs_ctrl_prbs_manual_sync_cls(FieldAsyncWriteOnly): +--------------+-------------------------------------------------------------------------+ | Description | .. raw:: html | | | | - | |

0 -> 1 : Synchronize PRBS monitor 1 -> 0 : Synchronize | - | | PRBS monitor

| + | |

0 -> 1 : Synchronize PRBS monitor

1 -> 0 : | + | | Synchronize PRBS monitor

| +--------------+-------------------------------------------------------------------------+ """ @@ -4137,7 +4138,7 @@ def rdl_name(self) -> str: return "PRBS Manual Sync" @property def rdl_desc(self) -> str: - return "0 -\u003e 1 : Synchronize PRBS monitor\n1 -\u003e 0 : Synchronize PRBS monitor" + return "0 -\u003e 1 : Synchronize PRBS monitor\n\n1 -\u003e 0 : Synchronize PRBS monitor" @@ -4160,7 +4161,7 @@ class msk_top_regs_prbs_ctrl_prbs_clear_cls(FieldAsyncWriteOnly): +--------------+-------------------------------------------------------------------------+ | Description | .. raw:: html | | | | - | |

0 -> 1 : Clear PRBS Counters 1 -> 0 : Clear PRBS | + | |

0 -> 1 : Clear PRBS Counters

1 -> 0 : Clear PRBS | | | Counters

| +--------------+-------------------------------------------------------------------------+ """ @@ -4177,7 +4178,7 @@ def rdl_name(self) -> str: return "PRBS Clear Counters" @property def rdl_desc(self) -> str: - return "0 -\u003e 1 : Clear PRBS Counters\n1 -\u003e 0 : Clear PRBS Counters" + return "0 -\u003e 1 : Clear PRBS Counters\n\n1 -\u003e 0 : Clear PRBS Counters" @@ -4200,8 +4201,9 @@ class msk_top_regs_prbs_ctrl_prbs_error_insert_cls(FieldAsyncWriteOnly): +--------------+-------------------------------------------------------------------------+ | Description | .. raw:: html | | | | - | |

0 -> 1 : Insert bit error in Tx data (both Normal and PRBS) | - | | 1 -> 0 : Insert bit error in Tx data (both Normal and PRBS)

| + | |

0 -> 1 : Insert bit error in Tx data (both Normal and | + | | PRBS)

1 -> 0 : Insert bit error in Tx data (both Normal | + | | and PRBS)

| +--------------+-------------------------------------------------------------------------+ """ @@ -4217,7 +4219,7 @@ def rdl_name(self) -> str: return "PRBS Error Insert" @property def rdl_desc(self) -> str: - return "0 -\u003e 1 : Insert bit error in Tx data (both Normal and PRBS)\n1 -\u003e 0 : Insert bit error in Tx data (both Normal and PRBS)" + return "0 -\u003e 1 : Insert bit error in Tx data (both Normal and PRBS)\n\n1 -\u003e 0 : Insert bit error in Tx data (both Normal and PRBS)" @@ -4439,8 +4441,9 @@ def prbs_error_insert(self) -> msk_top_regs_prbs_ctrl_prbs_error_insert_cls: +--------------+-------------------------------------------------------------------------+ | Description | .. raw:: html | | | | - | |

0 -> 1 : Insert bit error in Tx data (both Normal and PRBS) | - | | 1 -> 0 : Insert bit error in Tx data (both Normal and PRBS)

| + | |

0 -> 1 : Insert bit error in Tx data (both Normal and | + | | PRBS)

1 -> 0 : Insert bit error in Tx data (both Normal | + | | and PRBS)

| +--------------+-------------------------------------------------------------------------+ """ return self.__prbs_error_insert @@ -4459,7 +4462,7 @@ def prbs_clear(self) -> msk_top_regs_prbs_ctrl_prbs_clear_cls: +--------------+-------------------------------------------------------------------------+ | Description | .. raw:: html | | | | - | |

0 -> 1 : Clear PRBS Counters 1 -> 0 : Clear PRBS | + | |

0 -> 1 : Clear PRBS Counters

1 -> 0 : Clear PRBS | | | Counters

| +--------------+-------------------------------------------------------------------------+ """ @@ -4479,8 +4482,8 @@ def prbs_manual_sync(self) -> msk_top_regs_prbs_ctrl_prbs_manual_sync_cls: +--------------+-------------------------------------------------------------------------+ | Description | .. raw:: html | | | | - | |

0 -> 1 : Synchronize PRBS monitor 1 -> 0 : Synchronize | - | | PRBS monitor

| + | |

0 -> 1 : Synchronize PRBS monitor

1 -> 0 : | + | | Synchronize PRBS monitor

| +--------------+-------------------------------------------------------------------------+ """ return self.__prbs_manual_sync @@ -4514,7 +4517,8 @@ def prbs_sync_threshold(self) -> msk_top_regs_prbs_ctrl_prbs_sync_threshold_cls: +--------------+-------------------------------------------------------------------------+ | Description | .. raw:: html | | | | - | |

0 : Auto Sync Disabled N > 0 : Auto sync after N errors

| + | |

0 : Auto Sync Disabled

N > 0 : Auto sync after N | + | | errors

| +--------------+-------------------------------------------------------------------------+ """ return self.__prbs_sync_threshold @@ -4760,7 +4764,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_data_width_data_width_0x0x105dda63_cls(FieldAsyncReadWrite): +class msk_top_regs_data_width_data_width_0x0x1050d0ec_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -4836,7 +4840,7 @@ def __init__(self, # build the field attributes - self.__data_width:msk_top_regs_data_width_data_width_0x0x105dda63_cls = msk_top_regs_data_width_data_width_0x0x105dda63_cls( + self.__data_width:msk_top_regs_data_width_data_width_0x0x1050d0ec_cls = msk_top_regs_data_width_data_width_0x0x1050d0ec_cls( parent_register=self, size_props=FieldSizeProps( width=8, @@ -4867,7 +4871,7 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field # build the properties for the fields @property - def data_width(self) -> msk_top_regs_data_width_data_width_0x0x105dda63_cls: + def data_width(self) -> msk_top_regs_data_width_data_width_0x0x1050d0ec_cls: """ Property to access data_width field of the register @@ -4906,7 +4910,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_data_width_data_width_0x0x105dda63_cls: + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_data_width_data_width_0x0x1050d0ec_cls: return super().get_child_by_system_rdl_name(name) @@ -5269,7 +5273,8 @@ class msk_top_regs_lpf_config_0_lpf_zero_cls(FieldAsyncReadWrite): +--------------+-------------------------------------------------------------------------+ | Description | .. raw:: html | | | | - | |

0 -> Normal operation 1 -> Zero and hold accumulator

| + | |

0 -> Normal operation

1 -> Zero and hold | + | | accumulator

| +--------------+-------------------------------------------------------------------------+ """ @@ -5285,7 +5290,7 @@ def rdl_name(self) -> str: return "Hold the PI Accumulator at zero" @property def rdl_desc(self) -> str: - return "0 -\u003e Normal operation\n1 -\u003e Zero and hold accumulator" + return "0 -\u003e Normal operation\n\n1 -\u003e Zero and hold accumulator" @@ -5308,7 +5313,8 @@ class msk_top_regs_lpf_config_0_lpf_freeze_cls(FieldAsyncReadWrite): +--------------+-------------------------------------------------------------------------+ | Description | .. raw:: html | | | | - | |

0 -> Normal operation 1 -> Freeze current value

| + | |

0 -> Normal operation

1 -> Freeze current | + | | value

| +--------------+-------------------------------------------------------------------------+ """ @@ -5324,7 +5330,7 @@ def rdl_name(self) -> str: return "Freeze the accumulator\u0027s current value" @property def rdl_desc(self) -> str: - return "0 -\u003e Normal operation\n1 -\u003e Freeze current value" + return "0 -\u003e Normal operation\n\n1 -\u003e Freeze current value" @@ -5458,7 +5464,8 @@ def lpf_freeze(self) -> msk_top_regs_lpf_config_0_lpf_freeze_cls: +--------------+-------------------------------------------------------------------------+ | Description | .. raw:: html | | | | - | |

0 -> Normal operation 1 -> Freeze current value

| + | |

0 -> Normal operation

1 -> Freeze current | + | | value

| +--------------+-------------------------------------------------------------------------+ """ return self.__lpf_freeze @@ -5477,7 +5484,8 @@ def lpf_zero(self) -> msk_top_regs_lpf_config_0_lpf_zero_cls: +--------------+-------------------------------------------------------------------------+ | Description | .. raw:: html | | | | - | |

0 -> Normal operation 1 -> Zero and hold accumulator

| + | |

0 -> Normal operation

1 -> Zero and hold | + | | accumulator

| +--------------+-------------------------------------------------------------------------+ """ return self.__lpf_zero @@ -5752,7 +5760,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_config_nco_fw_config_data_0x0x105dea0f_cls(FieldAsyncReadWrite): +class msk_top_regs_config_nco_fw_config_data_0x0x1050efce_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -5829,7 +5837,7 @@ def __init__(self, # build the field attributes - self.__config_data:msk_top_regs_config_nco_fw_config_data_0x0x105dea0f_cls = msk_top_regs_config_nco_fw_config_data_0x0x105dea0f_cls( + self.__config_data:msk_top_regs_config_nco_fw_config_data_0x0x1050efce_cls = msk_top_regs_config_nco_fw_config_data_0x0x1050efce_cls( parent_register=self, size_props=FieldSizeProps( width=32, @@ -5860,7 +5868,7 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field # build the properties for the fields @property - def config_data(self) -> msk_top_regs_config_nco_fw_config_data_0x0x105dea0f_cls: + def config_data(self) -> msk_top_regs_config_nco_fw_config_data_0x0x1050efce_cls: """ Property to access config_data field of the register @@ -5901,7 +5909,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_config_nco_fw_config_data_0x0x105dea0f_cls: + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_config_nco_fw_config_data_0x0x1050efce_cls: return super().get_child_by_system_rdl_name(name) @@ -5925,7 +5933,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_config_nco_fw_config_data_0x0x105dea21_cls(FieldAsyncReadWrite): +class msk_top_regs_config_nco_fw_config_data_0x0x1050ed7f_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -6002,7 +6010,7 @@ def __init__(self, # build the field attributes - self.__config_data:msk_top_regs_config_nco_fw_config_data_0x0x105dea21_cls = msk_top_regs_config_nco_fw_config_data_0x0x105dea21_cls( + self.__config_data:msk_top_regs_config_nco_fw_config_data_0x0x1050ed7f_cls = msk_top_regs_config_nco_fw_config_data_0x0x1050ed7f_cls( parent_register=self, size_props=FieldSizeProps( width=32, @@ -6033,7 +6041,7 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field # build the properties for the fields @property - def config_data(self) -> msk_top_regs_config_nco_fw_config_data_0x0x105dea21_cls: + def config_data(self) -> msk_top_regs_config_nco_fw_config_data_0x0x1050ed7f_cls: """ Property to access config_data field of the register @@ -6074,7 +6082,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_config_nco_fw_config_data_0x0x105dea21_cls: + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_config_nco_fw_config_data_0x0x1050ed7f_cls: return super().get_child_by_system_rdl_name(name) @@ -6098,7 +6106,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_config_nco_fw_config_data_0x0x105dea63_cls(FieldAsyncReadWrite): +class msk_top_regs_config_nco_fw_config_data_0x0x10511cc5_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -6175,7 +6183,7 @@ def __init__(self, # build the field attributes - self.__config_data:msk_top_regs_config_nco_fw_config_data_0x0x105dea63_cls = msk_top_regs_config_nco_fw_config_data_0x0x105dea63_cls( + self.__config_data:msk_top_regs_config_nco_fw_config_data_0x0x10511cc5_cls = msk_top_regs_config_nco_fw_config_data_0x0x10511cc5_cls( parent_register=self, size_props=FieldSizeProps( width=32, @@ -6206,7 +6214,7 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field # build the properties for the fields @property - def config_data(self) -> msk_top_regs_config_nco_fw_config_data_0x0x105dea63_cls: + def config_data(self) -> msk_top_regs_config_nco_fw_config_data_0x0x10511cc5_cls: """ Property to access config_data field of the register @@ -6247,7 +6255,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_config_nco_fw_config_data_0x0x105dea63_cls: + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_config_nco_fw_config_data_0x0x10511cc5_cls: return super().get_child_by_system_rdl_name(name) @@ -6271,7 +6279,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_config_nco_fw_config_data_0x0x105dea75_cls(FieldAsyncReadWrite): +class msk_top_regs_config_nco_fw_config_data_0x0x10511c86_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -6348,7 +6356,7 @@ def __init__(self, # build the field attributes - self.__config_data:msk_top_regs_config_nco_fw_config_data_0x0x105dea75_cls = msk_top_regs_config_nco_fw_config_data_0x0x105dea75_cls( + self.__config_data:msk_top_regs_config_nco_fw_config_data_0x0x10511c86_cls = msk_top_regs_config_nco_fw_config_data_0x0x10511c86_cls( parent_register=self, size_props=FieldSizeProps( width=32, @@ -6379,7 +6387,7 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field # build the properties for the fields @property - def config_data(self) -> msk_top_regs_config_nco_fw_config_data_0x0x105dea75_cls: + def config_data(self) -> msk_top_regs_config_nco_fw_config_data_0x0x10511c86_cls: """ Property to access config_data field of the register @@ -6420,7 +6428,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_config_nco_fw_config_data_0x0x105dea75_cls: + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_config_nco_fw_config_data_0x0x10511c86_cls: return super().get_child_by_system_rdl_name(name) @@ -6459,7 +6467,10 @@ class msk_top_regs_msk_stat_2_data_cls(FieldAsyncReadWrite): +--------------+-------------------------------------------------------------------------+ | Description | .. raw:: html | | | | - | |

Number of clocks on which Tx Enable is active

| + | |

Number of clocks on which Tx Enable is active

This | + | | register is write-to-capture.

To read data the following | + | | steps are required:

1 - Write any value to this register to | + | | capture read data

2 - Read the register

| +--------------+-------------------------------------------------------------------------+ """ @@ -6475,7 +6486,7 @@ def rdl_name(self) -> str: return "Tx Enable Count" @property def rdl_desc(self) -> str: - return "Number of clocks on which Tx Enable is active" + return "Number of clocks on which Tx Enable is active\n\nThis register is write-to-capture.\n\nTo read data the following steps are required:\n\n1 - Write any value to this register to capture read data\n\n2 - Read the register" @@ -6564,7 +6575,10 @@ def data(self) -> msk_top_regs_msk_stat_2_data_cls: +--------------+-------------------------------------------------------------------------+ | Description | .. raw:: html | | | | - | |

Number of clocks on which Tx Enable is active

| + | |

Number of clocks on which Tx Enable is active

This | + | | register is write-to-capture.

To read data the following | + | | steps are required:

1 - Write any value to this register to | + | | capture read data

2 - Read the register

| +--------------+-------------------------------------------------------------------------+ """ return self.__data @@ -6628,7 +6642,10 @@ class msk_top_regs_msk_stat_1_data_cls(FieldAsyncReadWrite): +--------------+-------------------------------------------------------------------------+ | Description | .. raw:: html | | | | - | |

Count of data requests made by modem

| + | |

Count of data requests made by modem

This register is | + | | write-to-capture.

To read data the following steps are | + | | required:

1 - Write any value to this register to capture | + | | read data

2 - Read the register

| +--------------+-------------------------------------------------------------------------+ """ @@ -6644,7 +6661,7 @@ def rdl_name(self) -> str: return "Tx Bit Count" @property def rdl_desc(self) -> str: - return "Count of data requests made by modem" + return "Count of data requests made by modem\n\nThis register is write-to-capture.\n\nTo read data the following steps are required:\n\n1 - Write any value to this register to capture read data\n\n2 - Read the register" @@ -6733,7 +6750,10 @@ def data(self) -> msk_top_regs_msk_stat_1_data_cls: +--------------+-------------------------------------------------------------------------+ | Description | .. raw:: html | | | | - | |

Count of data requests made by modem

| + | |

Count of data requests made by modem

This register is | + | | write-to-capture.

To read data the following steps are | + | | required:

1 - Write any value to this register to capture | + | | read data

2 - Read the register

| +--------------+-------------------------------------------------------------------------+ """ return self.__data @@ -6797,7 +6817,8 @@ class msk_top_regs_msk_stat_0_tx_axis_valid_cls(FieldAsyncReadOnly): +--------------+-------------------------------------------------------------------------+ | Description | .. raw:: html | | | | - | |

1 -> S_AXIS_VALID Enabled 0 -> S_AXIS_VALID Disabled

| + | |

1 -> S_AXIS_VALID Enabled

0 -> S_AXIS_VALID | + | | Disabled

| +--------------+-------------------------------------------------------------------------+ """ @@ -6813,7 +6834,7 @@ def rdl_name(self) -> str: return "Tx S_AXIS_VALID" @property def rdl_desc(self) -> str: - return "1 -\u003e S_AXIS_VALID Enabled\n0 -\u003e S_AXIS_VALID Disabled" + return "1 -\u003e S_AXIS_VALID Enabled\n\n0 -\u003e S_AXIS_VALID Disabled" @@ -6836,7 +6857,7 @@ class msk_top_regs_msk_stat_0_rx_enable_cls(FieldAsyncReadOnly): +--------------+-------------------------------------------------------------------------+ | Description | .. raw:: html | | | | - | |

1 -> Data from ADC Enabled 0 -> Data from ADC | + | |

1 -> Data from ADC Enabled

0 -> Data from ADC | | | Disabled

| +--------------+-------------------------------------------------------------------------+ """ @@ -6853,7 +6874,7 @@ def rdl_name(self) -> str: return "AD9363 ADC Interface Rx Enable Input Active" @property def rdl_desc(self) -> str: - return "1 -\u003e Data from ADC Enabled\n0 -\u003e Data from ADC Disabled" + return "1 -\u003e Data from ADC Enabled\n\n0 -\u003e Data from ADC Disabled" @@ -6876,7 +6897,8 @@ class msk_top_regs_msk_stat_0_tx_enable_cls(FieldAsyncReadOnly): +--------------+-------------------------------------------------------------------------+ | Description | .. raw:: html | | | | - | |

1 -> Data to DAC Enabled 0 -> Data to DAC Disabled

| + | |

1 -> Data to DAC Enabled

0 -> Data to DAC | + | | Disabled

| +--------------+-------------------------------------------------------------------------+ """ @@ -6892,7 +6914,7 @@ def rdl_name(self) -> str: return "AD9363 DAC Interface Tx Enable Input Active" @property def rdl_desc(self) -> str: - return "1 -\u003e Data to DAC Enabled\n0 -\u003e Data to DAC Disabled" + return "1 -\u003e Data to DAC Enabled\n\n0 -\u003e Data to DAC Disabled" @@ -7084,7 +7106,8 @@ def tx_enable(self) -> msk_top_regs_msk_stat_0_tx_enable_cls: +--------------+-------------------------------------------------------------------------+ | Description | .. raw:: html | | | | - | |

1 -> Data to DAC Enabled 0 -> Data to DAC Disabled

| + | |

1 -> Data to DAC Enabled

0 -> Data to DAC | + | | Disabled

| +--------------+-------------------------------------------------------------------------+ """ return self.__tx_enable @@ -7103,7 +7126,7 @@ def rx_enable(self) -> msk_top_regs_msk_stat_0_rx_enable_cls: +--------------+-------------------------------------------------------------------------+ | Description | .. raw:: html | | | | - | |

1 -> Data from ADC Enabled 0 -> Data from ADC | + | |

1 -> Data from ADC Enabled

0 -> Data from ADC | | | Disabled

| +--------------+-------------------------------------------------------------------------+ """ @@ -7123,7 +7146,8 @@ def tx_axis_valid(self) -> msk_top_regs_msk_stat_0_tx_axis_valid_cls: +--------------+-------------------------------------------------------------------------+ | Description | .. raw:: html | | | | - | |

1 -> S_AXIS_VALID Enabled 0 -> S_AXIS_VALID Disabled

| + | |

1 -> S_AXIS_VALID Enabled

0 -> S_AXIS_VALID | + | | Disabled

| +--------------+-------------------------------------------------------------------------+ """ return self.__tx_axis_valid @@ -7206,8 +7230,9 @@ class msk_top_regs_msk_ctrl_diff_encoder_loopback_cls(FieldAsyncReadWrite): +--------------+-------------------------------------------------------------------------+ | Description | .. raw:: html | | | | - | |

0 -> Differential Encoder -> Decoder loopback disabled 1 | - | | -> Differential Encoder -> Decoder loopback enabled

| + | |

0 -> Differential Encoder -> Decoder loopback | + | | disabled

1 -> Differential Encoder -> Decoder | + | | loopback enabled

| +--------------+-------------------------------------------------------------------------+ """ @@ -7223,7 +7248,7 @@ def rdl_name(self) -> str: return "Differential Encoder -\u003e Decoder Loopback Enable" @property def rdl_desc(self) -> str: - return "0 -\u003e Differential Encoder -\u003e Decoder loopback disabled\n1 -\u003e Differential Encoder -\u003e Decoder loopback enabled" + return "0 -\u003e Differential Encoder -\u003e Decoder loopback disabled\n\n1 -\u003e Differential Encoder -\u003e Decoder loopback enabled" @@ -7324,7 +7349,7 @@ class msk_top_regs_msk_ctrl_loopback_ena_cls(FieldAsyncReadWrite): +--------------+-------------------------------------------------------------------------+ | Description | .. raw:: html | | | | - | |

0 -> Modem loopback disabled 1 -> Modem loopback | + | |

0 -> Modem loopback disabled

1 -> Modem loopback | | | enabled

| +--------------+-------------------------------------------------------------------------+ """ @@ -7341,7 +7366,7 @@ def rdl_name(self) -> str: return "Modem Digital Tx -\u003e Rx Loopback Enable" @property def rdl_desc(self) -> str: - return "0 -\u003e Modem loopback disabled\n1 -\u003e Modem loopback enabled" + return "0 -\u003e Modem loopback disabled\n\n1 -\u003e Modem loopback enabled" @@ -7548,7 +7573,7 @@ def loopback_ena(self) -> msk_top_regs_msk_ctrl_loopback_ena_cls: +--------------+-------------------------------------------------------------------------+ | Description | .. raw:: html | | | | - | |

0 -> Modem loopback disabled 1 -> Modem loopback | + | |

0 -> Modem loopback disabled

1 -> Modem loopback | | | enabled

| +--------------+-------------------------------------------------------------------------+ """ @@ -7606,8 +7631,9 @@ def diff_encoder_loopback(self) -> msk_top_regs_msk_ctrl_diff_encoder_loopback_c +--------------+-------------------------------------------------------------------------+ | Description | .. raw:: html | | | | - | |

0 -> Differential Encoder -> Decoder loopback disabled 1 | - | | -> Differential Encoder -> Decoder loopback enabled

| + | |

0 -> Differential Encoder -> Decoder loopback | + | | disabled

1 -> Differential Encoder -> Decoder | + | | loopback enabled

| +--------------+-------------------------------------------------------------------------+ """ return self.__diff_encoder_loopback @@ -7694,7 +7720,7 @@ class msk_top_regs_msk_init_rxinit_cls(FieldAsyncReadWrite): +--------------+-------------------------------------------------------------------------+ | Description | .. raw:: html | | | | - | |

0 -> Normal Rx operation 1 -> Initialize Rx

| + | |

0 -> Normal Rx operation

1 -> Initialize Rx

| +--------------+-------------------------------------------------------------------------+ """ @@ -7710,7 +7736,7 @@ def rdl_name(self) -> str: return "Rx Init Enable" @property def rdl_desc(self) -> str: - return "0 -\u003e Normal Rx operation \n1 -\u003e Initialize Rx" + return "0 -\u003e Normal Rx operation \n\n1 -\u003e Initialize Rx" @@ -7733,7 +7759,7 @@ class msk_top_regs_msk_init_txinit_cls(FieldAsyncReadWrite): +--------------+-------------------------------------------------------------------------+ | Description | .. raw:: html | | | | - | |

0 -> Normal Tx operation 1 -> Initialize Tx

| + | |

0 -> Normal Tx operation

1 -> Initialize Tx

| +--------------+-------------------------------------------------------------------------+ """ @@ -7749,7 +7775,7 @@ def rdl_name(self) -> str: return "Tx Init Enable" @property def rdl_desc(self) -> str: - return "0 -\u003e Normal Tx operation \n1 -\u003e Initialize Tx" + return "0 -\u003e Normal Tx operation\n\n1 -\u003e Initialize Tx" @@ -7772,8 +7798,8 @@ class msk_top_regs_msk_init_txrxinit_cls(FieldAsyncReadWrite): +--------------+-------------------------------------------------------------------------+ | Description | .. raw:: html | | | | - | |

0 -> Normal modem operation 1 -> Initialize Tx and | - | | Rx

| + | |

0 -> Normal modem operation

1 -> Initialize Tx | + | | and Rx

| +--------------+-------------------------------------------------------------------------+ """ @@ -7789,7 +7815,7 @@ def rdl_name(self) -> str: return "Tx/Rx Init Enable" @property def rdl_desc(self) -> str: - return "0 -\u003e Normal modem operation \n1 -\u003e Initialize Tx and Rx" + return "0 -\u003e Normal modem operation \n\n1 -\u003e Initialize Tx and Rx" @@ -7909,8 +7935,8 @@ def txrxinit(self) -> msk_top_regs_msk_init_txrxinit_cls: +--------------+-------------------------------------------------------------------------+ | Description | .. raw:: html | | | | - | |

0 -> Normal modem operation 1 -> Initialize Tx and | - | | Rx

| + | |

0 -> Normal modem operation

1 -> Initialize Tx | + | | and Rx

| +--------------+-------------------------------------------------------------------------+ """ return self.__txrxinit @@ -7929,7 +7955,7 @@ def txinit(self) -> msk_top_regs_msk_init_txinit_cls: +--------------+-------------------------------------------------------------------------+ | Description | .. raw:: html | | | | - | |

0 -> Normal Tx operation 1 -> Initialize Tx

| + | |

0 -> Normal Tx operation

1 -> Initialize Tx

| +--------------+-------------------------------------------------------------------------+ """ return self.__txinit @@ -7948,7 +7974,7 @@ def rxinit(self) -> msk_top_regs_msk_init_rxinit_cls: +--------------+-------------------------------------------------------------------------+ | Description | .. raw:: html | | | | - | |

0 -> Normal Rx operation 1 -> Initialize Rx

| + | |

0 -> Normal Rx operation

1 -> Initialize Rx

| +--------------+-------------------------------------------------------------------------+ """ return self.__rxinit @@ -8590,7 +8616,7 @@ def __init__(self, *, inst_name='LPF_Config_2', parent=self) - self.__f1_nco_adjust:msk_top_regs_observation_data_data_0c017ef4_desc_64ff3689_name_d8ad3b25_cls = msk_top_regs_observation_data_data_0c017ef4_desc_64ff3689_name_d8ad3b25_cls( + self.__f1_nco_adjust:msk_top_regs_observation_data_data_521c7d53_name_d8ad3b25_cls = msk_top_regs_observation_data_data_521c7d53_name_d8ad3b25_cls( address=self.address+108, accesswidth=32, width=32, @@ -8598,7 +8624,7 @@ def __init__(self, *, inst_name='f1_nco_adjust', parent=self) - self.__f2_nco_adjust:msk_top_regs_observation_data_data_0515efaa_desc_ebde6d39_name_2c154788_cls = msk_top_regs_observation_data_data_0515efaa_desc_ebde6d39_name_2c154788_cls( + self.__f2_nco_adjust:msk_top_regs_observation_data_data_5802c5b1_name_2c154788_cls = msk_top_regs_observation_data_data_5802c5b1_name_2c154788_cls( address=self.address+112, accesswidth=32, width=32, @@ -8606,7 +8632,7 @@ def __init__(self, *, inst_name='f2_nco_adjust', parent=self) - self.__f1_error:msk_top_regs_observation_data_data_25a21249_desc_417e1c96_name_3b640507_cls = msk_top_regs_observation_data_data_25a21249_desc_417e1c96_name_3b640507_cls( + self.__f1_error:msk_top_regs_observation_data_data_f83682dd_name_3b640507_cls = msk_top_regs_observation_data_data_f83682dd_name_3b640507_cls( address=self.address+116, accesswidth=32, width=32, @@ -8614,7 +8640,7 @@ def __init__(self, *, inst_name='f1_error', parent=self) - self.__f2_error:msk_top_regs_observation_data_data_272a00b6_desc_70869502_name_3de9a0d3_cls = msk_top_regs_observation_data_data_272a00b6_desc_70869502_name_3de9a0d3_cls( + self.__f2_error:msk_top_regs_observation_data_data_0a9850a4_name_3de9a0d3_cls = msk_top_regs_observation_data_data_0a9850a4_name_3de9a0d3_cls( address=self.address+120, accesswidth=32, width=32, @@ -8638,7 +8664,7 @@ def __init__(self, *, inst_name='Tx_Sync_Cnt', parent=self) - self.__lowpass_ema_alpha1:msk_top_regs_lowpass_ema_alpha_0x0x105c0c74_cls = msk_top_regs_lowpass_ema_alpha_0x0x105c0c74_cls( + self.__lowpass_ema_alpha1:msk_top_regs_lowpass_ema_alpha_0x0x1052719d_cls = msk_top_regs_lowpass_ema_alpha_0x0x1052719d_cls( address=self.address+132, accesswidth=32, width=32, @@ -8662,7 +8688,7 @@ def __init__(self, *, inst_name='rx_power', parent=self) - self.__tx_async_fifo_rd_wr_ptr:msk_top_regs_observation_data_data_cf6acbd7_name_aa4ec676_cls = msk_top_regs_observation_data_data_cf6acbd7_name_aa4ec676_cls( + self.__tx_async_fifo_rd_wr_ptr:msk_top_regs_observation_data_data_dbd8270c_name_aa4ec676_cls = msk_top_regs_observation_data_data_dbd8270c_name_aa4ec676_cls( address=self.address+144, accesswidth=32, width=32, @@ -8670,7 +8696,7 @@ def __init__(self, *, inst_name='tx_async_fifo_rd_wr_ptr', parent=self) - self.__rx_async_fifo_rd_wr_ptr:msk_top_regs_observation_data_data_cf6acbd7_name_8a90eed1_cls = msk_top_regs_observation_data_data_cf6acbd7_name_8a90eed1_cls( + self.__rx_async_fifo_rd_wr_ptr:msk_top_regs_observation_data_data_dbd8270c_name_8a90eed1_cls = msk_top_regs_observation_data_data_dbd8270c_name_8a90eed1_cls( address=self.address+148, accesswidth=32, width=32, @@ -9217,7 +9243,7 @@ def LPF_Config_2(self) -> msk_top_regs_lpf_config_2_cls: return self.__LPF_Config_2 @property - def f1_nco_adjust(self) -> msk_top_regs_observation_data_data_0c017ef4_desc_64ff3689_name_d8ad3b25_cls: + def f1_nco_adjust(self) -> msk_top_regs_observation_data_data_521c7d53_name_d8ad3b25_cls: """ Property to access f1_nco_adjust @@ -9229,15 +9255,11 @@ def f1_nco_adjust(self) -> msk_top_regs_observation_data_data_0c017ef4_desc_64ff | | | | | F1 NCO Frequency Adjust | +--------------+-------------------------------------------------------------------------+ - | Description | .. raw:: html | - | | | - | |

Frequency offet applied to the F1 NCO

| - +--------------+-------------------------------------------------------------------------+ """ return self.__f1_nco_adjust @property - def f2_nco_adjust(self) -> msk_top_regs_observation_data_data_0515efaa_desc_ebde6d39_name_2c154788_cls: + def f2_nco_adjust(self) -> msk_top_regs_observation_data_data_5802c5b1_name_2c154788_cls: """ Property to access f2_nco_adjust @@ -9249,15 +9271,11 @@ def f2_nco_adjust(self) -> msk_top_regs_observation_data_data_0515efaa_desc_ebde | | | | | F2 NCO Frequency Adjust | +--------------+-------------------------------------------------------------------------+ - | Description | .. raw:: html | - | | | - | |

Frequency offet applied to the F2 NCO

| - +--------------+-------------------------------------------------------------------------+ """ return self.__f2_nco_adjust @property - def f1_error(self) -> msk_top_regs_observation_data_data_25a21249_desc_417e1c96_name_3b640507_cls: + def f1_error(self) -> msk_top_regs_observation_data_data_f83682dd_name_3b640507_cls: """ Property to access f1_error @@ -9269,16 +9287,11 @@ def f1_error(self) -> msk_top_regs_observation_data_data_25a21249_desc_417e1c96_ | | | | | F1 Error Value | +--------------+-------------------------------------------------------------------------+ - | Description | .. raw:: html | - | | | - | |

Error value of the F1 Costas loop after each active bit | - | | period

| - +--------------+-------------------------------------------------------------------------+ """ return self.__f1_error @property - def f2_error(self) -> msk_top_regs_observation_data_data_272a00b6_desc_70869502_name_3de9a0d3_cls: + def f2_error(self) -> msk_top_regs_observation_data_data_0a9850a4_name_3de9a0d3_cls: """ Property to access f2_error @@ -9290,11 +9303,6 @@ def f2_error(self) -> msk_top_regs_observation_data_data_272a00b6_desc_70869502_ | | | | | F2 Error Value | +--------------+-------------------------------------------------------------------------+ - | Description | .. raw:: html | - | | | - | |

Error value of the F2 Costas loop after each active bit | - | | period

| - +--------------+-------------------------------------------------------------------------+ """ return self.__f2_error @@ -9340,7 +9348,7 @@ def Tx_Sync_Cnt(self) -> msk_top_regs_tx_sync_cnt_cls: return self.__Tx_Sync_Cnt @property - def lowpass_ema_alpha1(self) -> msk_top_regs_lowpass_ema_alpha_0x0x105c0c74_cls: + def lowpass_ema_alpha1(self) -> msk_top_regs_lowpass_ema_alpha_0x0x1052719d_cls: """ Property to access lowpass_ema_alpha1 @@ -9400,7 +9408,7 @@ def rx_power(self) -> msk_top_regs_rx_power_cls: return self.__rx_power @property - def tx_async_fifo_rd_wr_ptr(self) -> msk_top_regs_observation_data_data_cf6acbd7_name_aa4ec676_cls: + def tx_async_fifo_rd_wr_ptr(self) -> msk_top_regs_observation_data_data_dbd8270c_name_aa4ec676_cls: """ Property to access tx_async_fifo_rd_wr_ptr @@ -9416,7 +9424,7 @@ def tx_async_fifo_rd_wr_ptr(self) -> msk_top_regs_observation_data_data_cf6acbd7 return self.__tx_async_fifo_rd_wr_ptr @property - def rx_async_fifo_rd_wr_ptr(self) -> msk_top_regs_observation_data_data_cf6acbd7_name_8a90eed1_cls: + def rx_async_fifo_rd_wr_ptr(self) -> msk_top_regs_observation_data_data_dbd8270c_name_8a90eed1_cls: """ Property to access rx_async_fifo_rd_wr_ptr @@ -9562,19 +9570,19 @@ def get_child_by_system_rdl_name(self, name: Literal["LPF_Config_2"]) -> msk_top @overload - def get_child_by_system_rdl_name(self, name: Literal["f1_nco_adjust"]) -> msk_top_regs_observation_data_data_0c017ef4_desc_64ff3689_name_d8ad3b25_cls: ... + def get_child_by_system_rdl_name(self, name: Literal["f1_nco_adjust"]) -> msk_top_regs_observation_data_data_521c7d53_name_d8ad3b25_cls: ... @overload - def get_child_by_system_rdl_name(self, name: Literal["f2_nco_adjust"]) -> msk_top_regs_observation_data_data_0515efaa_desc_ebde6d39_name_2c154788_cls: ... + def get_child_by_system_rdl_name(self, name: Literal["f2_nco_adjust"]) -> msk_top_regs_observation_data_data_5802c5b1_name_2c154788_cls: ... @overload - def get_child_by_system_rdl_name(self, name: Literal["f1_error"]) -> msk_top_regs_observation_data_data_25a21249_desc_417e1c96_name_3b640507_cls: ... + def get_child_by_system_rdl_name(self, name: Literal["f1_error"]) -> msk_top_regs_observation_data_data_f83682dd_name_3b640507_cls: ... @overload - def get_child_by_system_rdl_name(self, name: Literal["f2_error"]) -> msk_top_regs_observation_data_data_272a00b6_desc_70869502_name_3de9a0d3_cls: ... + def get_child_by_system_rdl_name(self, name: Literal["f2_error"]) -> msk_top_regs_observation_data_data_0a9850a4_name_3de9a0d3_cls: ... @overload @@ -9586,7 +9594,7 @@ def get_child_by_system_rdl_name(self, name: Literal["Tx_Sync_Cnt"]) -> msk_top_ @overload - def get_child_by_system_rdl_name(self, name: Literal["lowpass_ema_alpha1"]) -> msk_top_regs_lowpass_ema_alpha_0x0x105c0c74_cls: ... + def get_child_by_system_rdl_name(self, name: Literal["lowpass_ema_alpha1"]) -> msk_top_regs_lowpass_ema_alpha_0x0x1052719d_cls: ... @overload @@ -9598,15 +9606,15 @@ def get_child_by_system_rdl_name(self, name: Literal["rx_power"]) -> msk_top_reg @overload - def get_child_by_system_rdl_name(self, name: Literal["tx_async_fifo_rd_wr_ptr"]) -> msk_top_regs_observation_data_data_cf6acbd7_name_aa4ec676_cls: ... + def get_child_by_system_rdl_name(self, name: Literal["tx_async_fifo_rd_wr_ptr"]) -> msk_top_regs_observation_data_data_dbd8270c_name_aa4ec676_cls: ... @overload - def get_child_by_system_rdl_name(self, name: Literal["rx_async_fifo_rd_wr_ptr"]) -> msk_top_regs_observation_data_data_cf6acbd7_name_8a90eed1_cls: ... + def get_child_by_system_rdl_name(self, name: Literal["rx_async_fifo_rd_wr_ptr"]) -> msk_top_regs_observation_data_data_dbd8270c_name_8a90eed1_cls: ... @overload - def get_child_by_system_rdl_name(self, name: str) -> Union[msk_top_regs_msk_hash_lo_cls, msk_top_regs_msk_hash_hi_cls, msk_top_regs_msk_init_cls, msk_top_regs_msk_ctrl_cls, msk_top_regs_msk_stat_0_cls, msk_top_regs_msk_stat_1_cls, msk_top_regs_msk_stat_2_cls, msk_top_regs_config_nco_fw_desc_c4924cc6_name_0c494469_cls, msk_top_regs_config_nco_fw_desc_94d7aaf5_name_84dd0c1c_cls, msk_top_regs_config_nco_fw_desc_42134a4f_name_d97dbd51_cls, msk_top_regs_config_nco_fw_desc_16fb48c8_name_8d01a20d_cls, msk_top_regs_config_nco_fw_desc_43c0828f_name_bdc60ecf_cls, msk_top_regs_lpf_config_0_cls, msk_top_regs_lpf_config_1_cls, msk_top_regs_data_width_desc_58c848dd_name_2fbd8eba_cls, msk_top_regs_data_width_desc_6097df38_name_4609588b_cls, msk_top_regs_prbs_ctrl_cls, msk_top_regs_config_prbs_seed_cls, msk_top_regs_config_prbs_poly_cls, msk_top_regs_config_prbs_errmask_cls, msk_top_regs_stat_32_bits_cls, msk_top_regs_stat_32_errs_cls, msk_top_regs_stat_32_lpf_acc_desc_8cebc7dc_name_f20c6670_cls, msk_top_regs_stat_32_lpf_acc_desc_dea6bd99_name_758fd0ce_cls, msk_top_regs_msk_stat_3_cls, msk_top_regs_rx_sample_discard_cls, msk_top_regs_lpf_config_2_cls, msk_top_regs_observation_data_data_0c017ef4_desc_64ff3689_name_d8ad3b25_cls, msk_top_regs_observation_data_data_0515efaa_desc_ebde6d39_name_2c154788_cls, msk_top_regs_observation_data_data_25a21249_desc_417e1c96_name_3b640507_cls, msk_top_regs_observation_data_data_272a00b6_desc_70869502_name_3de9a0d3_cls, msk_top_regs_tx_sync_ctrl_cls, msk_top_regs_tx_sync_cnt_cls, msk_top_regs_lowpass_ema_alpha_0x0x105c0c74_cls, msk_top_regs_lowpass_ema_alpha_cls, msk_top_regs_rx_power_cls, msk_top_regs_observation_data_data_cf6acbd7_name_aa4ec676_cls, msk_top_regs_observation_data_data_cf6acbd7_name_8a90eed1_cls, ]: ... + def get_child_by_system_rdl_name(self, name: str) -> Union[msk_top_regs_msk_hash_lo_cls, msk_top_regs_msk_hash_hi_cls, msk_top_regs_msk_init_cls, msk_top_regs_msk_ctrl_cls, msk_top_regs_msk_stat_0_cls, msk_top_regs_msk_stat_1_cls, msk_top_regs_msk_stat_2_cls, msk_top_regs_config_nco_fw_desc_c4924cc6_name_0c494469_cls, msk_top_regs_config_nco_fw_desc_94d7aaf5_name_84dd0c1c_cls, msk_top_regs_config_nco_fw_desc_42134a4f_name_d97dbd51_cls, msk_top_regs_config_nco_fw_desc_16fb48c8_name_8d01a20d_cls, msk_top_regs_config_nco_fw_desc_43c0828f_name_bdc60ecf_cls, msk_top_regs_lpf_config_0_cls, msk_top_regs_lpf_config_1_cls, msk_top_regs_data_width_desc_58c848dd_name_2fbd8eba_cls, msk_top_regs_data_width_desc_6097df38_name_4609588b_cls, msk_top_regs_prbs_ctrl_cls, msk_top_regs_config_prbs_seed_cls, msk_top_regs_config_prbs_poly_cls, msk_top_regs_config_prbs_errmask_cls, msk_top_regs_stat_32_bits_cls, msk_top_regs_stat_32_errs_cls, msk_top_regs_stat_32_lpf_acc_desc_8cebc7dc_name_f20c6670_cls, msk_top_regs_stat_32_lpf_acc_desc_dea6bd99_name_758fd0ce_cls, msk_top_regs_msk_stat_3_cls, msk_top_regs_rx_sample_discard_cls, msk_top_regs_lpf_config_2_cls, msk_top_regs_observation_data_data_521c7d53_name_d8ad3b25_cls, msk_top_regs_observation_data_data_5802c5b1_name_2c154788_cls, msk_top_regs_observation_data_data_f83682dd_name_3b640507_cls, msk_top_regs_observation_data_data_0a9850a4_name_3de9a0d3_cls, msk_top_regs_tx_sync_ctrl_cls, msk_top_regs_tx_sync_cnt_cls, msk_top_regs_lowpass_ema_alpha_0x0x1052719d_cls, msk_top_regs_lowpass_ema_alpha_cls, msk_top_regs_rx_power_cls, msk_top_regs_observation_data_data_dbd8270c_name_aa4ec676_cls, msk_top_regs_observation_data_data_dbd8270c_name_8a90eed1_cls, ]: ... def get_child_by_system_rdl_name(self, name: Any) -> Any: return super().get_child_by_system_rdl_name(name) diff --git a/rdl/outputs/python/msk_top_regs/tests/test_msk_top_regs.py b/rdl/outputs/python/msk_top_regs/tests/test_msk_top_regs.py index c76701a..e6344e7 100644 --- a/rdl/outputs/python/msk_top_regs/tests/test_msk_top_regs.py +++ b/rdl/outputs/python/msk_top_regs/tests/test_msk_top_regs.py @@ -957,28 +957,28 @@ def test_name_property(self) -> None: with self.subTest(msg='node: msk_top_regs.f1_nco_adjust.data'): - self.assertEqual(self.dut.f1_nco_adjust.data.rdl_name, "F1 NCO Frequency Adjust") # type: ignore[union-attr] + self.assertIsNone(self.dut.f1_nco_adjust.data.rdl_name) # type: ignore[union-attr] with self.subTest(msg='node: msk_top_regs.f2_nco_adjust.data'): - self.assertEqual(self.dut.f2_nco_adjust.data.rdl_name, "F2 NCO Frequency Adjust") # type: ignore[union-attr] + self.assertIsNone(self.dut.f2_nco_adjust.data.rdl_name) # type: ignore[union-attr] with self.subTest(msg='node: msk_top_regs.f1_error.data'): - self.assertEqual(self.dut.f1_error.data.rdl_name, "F1 Error Value") # type: ignore[union-attr] + self.assertIsNone(self.dut.f1_error.data.rdl_name) # type: ignore[union-attr] with self.subTest(msg='node: msk_top_regs.f2_error.data'): - self.assertEqual(self.dut.f2_error.data.rdl_name, "F2 Error Value") # type: ignore[union-attr] + self.assertIsNone(self.dut.f2_error.data.rdl_name) # type: ignore[union-attr] @@ -1250,28 +1250,28 @@ def test_desc(self) -> None: with self.subTest(msg='node: msk_top_regs.f1_nco_adjust'): - self.assertEqual(self.dut.f1_nco_adjust.rdl_desc, "Frequency offet applied to the F1 NCO") # type: ignore[union-attr] + self.assertIsNone(self.dut.f1_nco_adjust.rdl_desc) # type: ignore[union-attr] with self.subTest(msg='node: msk_top_regs.f2_nco_adjust'): - self.assertEqual(self.dut.f2_nco_adjust.rdl_desc, "Frequency offet applied to the F2 NCO") # type: ignore[union-attr] + self.assertIsNone(self.dut.f2_nco_adjust.rdl_desc) # type: ignore[union-attr] with self.subTest(msg='node: msk_top_regs.f1_error'): - self.assertEqual(self.dut.f1_error.rdl_desc, "Error value of the F1 Costas loop after each active bit period") # type: ignore[union-attr] + self.assertIsNone(self.dut.f1_error.rdl_desc) # type: ignore[union-attr] with self.subTest(msg='node: msk_top_regs.f2_error'): - self.assertEqual(self.dut.f2_error.rdl_desc, "Error value of the F2 Costas loop after each active bit period") # type: ignore[union-attr] + self.assertIsNone(self.dut.f2_error.rdl_desc) # type: ignore[union-attr] @@ -1341,21 +1341,21 @@ def test_desc(self) -> None: with self.subTest(msg='node: msk_top_regs.MSK_Init.txrxinit'): - self.assertEqual(self.dut.MSK_Init.txrxinit.rdl_desc, "0 -\u003e Normal modem operation \n1 -\u003e Initialize Tx and Rx") # type: ignore[union-attr] + self.assertEqual(self.dut.MSK_Init.txrxinit.rdl_desc, "0 -\u003e Normal modem operation \n\n1 -\u003e Initialize Tx and Rx") # type: ignore[union-attr] with self.subTest(msg='node: msk_top_regs.MSK_Init.txinit'): - self.assertEqual(self.dut.MSK_Init.txinit.rdl_desc, "0 -\u003e Normal Tx operation \n1 -\u003e Initialize Tx") # type: ignore[union-attr] + self.assertEqual(self.dut.MSK_Init.txinit.rdl_desc, "0 -\u003e Normal Tx operation\n\n1 -\u003e Initialize Tx") # type: ignore[union-attr] with self.subTest(msg='node: msk_top_regs.MSK_Init.rxinit'): - self.assertEqual(self.dut.MSK_Init.rxinit.rdl_desc, "0 -\u003e Normal Rx operation \n1 -\u003e Initialize Rx") # type: ignore[union-attr] + self.assertEqual(self.dut.MSK_Init.rxinit.rdl_desc, "0 -\u003e Normal Rx operation \n\n1 -\u003e Initialize Rx") # type: ignore[union-attr] @@ -1369,7 +1369,7 @@ def test_desc(self) -> None: with self.subTest(msg='node: msk_top_regs.MSK_Control.loopback_ena'): - self.assertEqual(self.dut.MSK_Control.loopback_ena.rdl_desc, "0 -\u003e Modem loopback disabled\n1 -\u003e Modem loopback enabled") # type: ignore[union-attr] + self.assertEqual(self.dut.MSK_Control.loopback_ena.rdl_desc, "0 -\u003e Modem loopback disabled\n\n1 -\u003e Modem loopback enabled") # type: ignore[union-attr] @@ -1390,7 +1390,7 @@ def test_desc(self) -> None: with self.subTest(msg='node: msk_top_regs.MSK_Control.diff_encoder_loopback'): - self.assertEqual(self.dut.MSK_Control.diff_encoder_loopback.rdl_desc, "0 -\u003e Differential Encoder -\u003e Decoder loopback disabled\n1 -\u003e Differential Encoder -\u003e Decoder loopback enabled") # type: ignore[union-attr] + self.assertEqual(self.dut.MSK_Control.diff_encoder_loopback.rdl_desc, "0 -\u003e Differential Encoder -\u003e Decoder loopback disabled\n\n1 -\u003e Differential Encoder -\u003e Decoder loopback enabled") # type: ignore[union-attr] @@ -1404,35 +1404,35 @@ def test_desc(self) -> None: with self.subTest(msg='node: msk_top_regs.MSK_Status.tx_enable'): - self.assertEqual(self.dut.MSK_Status.tx_enable.rdl_desc, "1 -\u003e Data to DAC Enabled\n0 -\u003e Data to DAC Disabled") # type: ignore[union-attr] + self.assertEqual(self.dut.MSK_Status.tx_enable.rdl_desc, "1 -\u003e Data to DAC Enabled\n\n0 -\u003e Data to DAC Disabled") # type: ignore[union-attr] with self.subTest(msg='node: msk_top_regs.MSK_Status.rx_enable'): - self.assertEqual(self.dut.MSK_Status.rx_enable.rdl_desc, "1 -\u003e Data from ADC Enabled\n0 -\u003e Data from ADC Disabled") # type: ignore[union-attr] + self.assertEqual(self.dut.MSK_Status.rx_enable.rdl_desc, "1 -\u003e Data from ADC Enabled\n\n0 -\u003e Data from ADC Disabled") # type: ignore[union-attr] with self.subTest(msg='node: msk_top_regs.MSK_Status.tx_axis_valid'): - self.assertEqual(self.dut.MSK_Status.tx_axis_valid.rdl_desc, "1 -\u003e S_AXIS_VALID Enabled\n0 -\u003e S_AXIS_VALID Disabled") # type: ignore[union-attr] + self.assertEqual(self.dut.MSK_Status.tx_axis_valid.rdl_desc, "1 -\u003e S_AXIS_VALID Enabled\n\n0 -\u003e S_AXIS_VALID Disabled") # type: ignore[union-attr] with self.subTest(msg='node: msk_top_regs.Tx_Bit_Count.data'): - self.assertEqual(self.dut.Tx_Bit_Count.data.rdl_desc, "Count of data requests made by modem") # type: ignore[union-attr] + self.assertEqual(self.dut.Tx_Bit_Count.data.rdl_desc, "Count of data requests made by modem\n\nThis register is write-to-capture.\n\nTo read data the following steps are required:\n\n1 - Write any value to this register to capture read data\n\n2 - Read the register") # type: ignore[union-attr] with self.subTest(msg='node: msk_top_regs.Tx_Enable_Count.data'): - self.assertEqual(self.dut.Tx_Enable_Count.data.rdl_desc, "Number of clocks on which Tx Enable is active") # type: ignore[union-attr] + self.assertEqual(self.dut.Tx_Enable_Count.data.rdl_desc, "Number of clocks on which Tx Enable is active\n\nThis register is write-to-capture.\n\nTo read data the following steps are required:\n\n1 - Write any value to this register to capture read data\n\n2 - Read the register") # type: ignore[union-attr] @@ -1474,14 +1474,14 @@ def test_desc(self) -> None: with self.subTest(msg='node: msk_top_regs.LPF_Config_0.lpf_freeze'): - self.assertEqual(self.dut.LPF_Config_0.lpf_freeze.rdl_desc, "0 -\u003e Normal operation\n1 -\u003e Freeze current value") # type: ignore[union-attr] + self.assertEqual(self.dut.LPF_Config_0.lpf_freeze.rdl_desc, "0 -\u003e Normal operation\n\n1 -\u003e Freeze current value") # type: ignore[union-attr] with self.subTest(msg='node: msk_top_regs.LPF_Config_0.lpf_zero'): - self.assertEqual(self.dut.LPF_Config_0.lpf_zero.rdl_desc, "0 -\u003e Normal operation\n1 -\u003e Zero and hold accumulator") # type: ignore[union-attr] + self.assertEqual(self.dut.LPF_Config_0.lpf_zero.rdl_desc, "0 -\u003e Normal operation\n\n1 -\u003e Zero and hold accumulator") # type: ignore[union-attr] @@ -1537,21 +1537,21 @@ def test_desc(self) -> None: with self.subTest(msg='node: msk_top_regs.PRBS_Control.prbs_error_insert'): - self.assertEqual(self.dut.PRBS_Control.prbs_error_insert.rdl_desc, "0 -\u003e 1 : Insert bit error in Tx data (both Normal and PRBS)\n1 -\u003e 0 : Insert bit error in Tx data (both Normal and PRBS)") # type: ignore[union-attr] + self.assertEqual(self.dut.PRBS_Control.prbs_error_insert.rdl_desc, "0 -\u003e 1 : Insert bit error in Tx data (both Normal and PRBS)\n\n1 -\u003e 0 : Insert bit error in Tx data (both Normal and PRBS)") # type: ignore[union-attr] with self.subTest(msg='node: msk_top_regs.PRBS_Control.prbs_clear'): - self.assertEqual(self.dut.PRBS_Control.prbs_clear.rdl_desc, "0 -\u003e 1 : Clear PRBS Counters\n1 -\u003e 0 : Clear PRBS Counters") # type: ignore[union-attr] + self.assertEqual(self.dut.PRBS_Control.prbs_clear.rdl_desc, "0 -\u003e 1 : Clear PRBS Counters\n\n1 -\u003e 0 : Clear PRBS Counters") # type: ignore[union-attr] with self.subTest(msg='node: msk_top_regs.PRBS_Control.prbs_manual_sync'): - self.assertEqual(self.dut.PRBS_Control.prbs_manual_sync.rdl_desc, "0 -\u003e 1 : Synchronize PRBS monitor\n1 -\u003e 0 : Synchronize PRBS monitor") # type: ignore[union-attr] + self.assertEqual(self.dut.PRBS_Control.prbs_manual_sync.rdl_desc, "0 -\u003e 1 : Synchronize PRBS monitor\n\n1 -\u003e 0 : Synchronize PRBS monitor") # type: ignore[union-attr] @@ -1565,7 +1565,7 @@ def test_desc(self) -> None: with self.subTest(msg='node: msk_top_regs.PRBS_Control.prbs_sync_threshold'): - self.assertEqual(self.dut.PRBS_Control.prbs_sync_threshold.rdl_desc, "0 : Auto Sync Disabled\nN \u003e 0 : Auto sync after N errors") # type: ignore[union-attr] + self.assertEqual(self.dut.PRBS_Control.prbs_sync_threshold.rdl_desc, "0 : Auto Sync Disabled\n\nN \u003e 0 : Auto sync after N errors") # type: ignore[union-attr] @@ -1593,35 +1593,35 @@ def test_desc(self) -> None: with self.subTest(msg='node: msk_top_regs.PRBS_Bit_Count.data'): - self.assertEqual(self.dut.PRBS_Bit_Count.data.rdl_desc, "Number of bits received by the PRBS monitor since last\nBER can be calculated as the ratio of received bits to errored-bits") # type: ignore[union-attr] + self.assertEqual(self.dut.PRBS_Bit_Count.data.rdl_desc, "Number of bits received by the PRBS monitor since last\nBER can be calculated as the ratio of received bits to errored-bits\n\nThis register is write-to-capture.\n\nTo read data the following steps are required:\n\n1 - Write any value to this register to capture read data\n\n2 - Read the register") # type: ignore[union-attr] with self.subTest(msg='node: msk_top_regs.PRBS_Error_Count.data'): - self.assertEqual(self.dut.PRBS_Error_Count.data.rdl_desc, "Number of errored-bits received by the PRBS monitor since last sync\nBER can be calculated as the ratio of received bits to errored-bits") # type: ignore[union-attr] + self.assertEqual(self.dut.PRBS_Error_Count.data.rdl_desc, "Number of errored-bits received by the PRBS monitor since last sync\nBER can be calculated as the ratio of received bits to errored-bits\n\nThis register is write-to-capture.\n\nTo read data the following steps are required:\n\n1 - Write any value to this register to capture read data\n\n2 - Read the register") # type: ignore[union-attr] with self.subTest(msg='node: msk_top_regs.LPF_Accum_F1.data'): - self.assertEqual(self.dut.LPF_Accum_F1.data.rdl_desc, "PI Controller Accumulator Value") # type: ignore[union-attr] + self.assertEqual(self.dut.LPF_Accum_F1.data.rdl_desc, "PI Controller Accumulator Value\n\nThis register is write-to-capture.\n\nTo read data the following steps are required:\n\n1 - Write any value to this register to capture read data\n\n2 - Read the register") # type: ignore[union-attr] with self.subTest(msg='node: msk_top_regs.LPF_Accum_F2.data'): - self.assertEqual(self.dut.LPF_Accum_F2.data.rdl_desc, "PI Controller Accumulator Value") # type: ignore[union-attr] + self.assertEqual(self.dut.LPF_Accum_F2.data.rdl_desc, "PI Controller Accumulator Value\n\nThis register is write-to-capture.\n\nTo read data the following steps are required:\n\n1 - Write any value to this register to capture read data\n\n2 - Read the register") # type: ignore[union-attr] with self.subTest(msg='node: msk_top_regs.axis_xfer_count.data'): - self.assertEqual(self.dut.axis_xfer_count.data.rdl_desc, "Number completed S_AXIS transfers") # type: ignore[union-attr] + self.assertEqual(self.dut.axis_xfer_count.data.rdl_desc, "Number completed S_AXIS transfers\n\nThis register is write-to-capture.\n\nTo read data the following steps are required:\n\n1 - Write any value to this register to capture read data\n\n2 - Read the register") # type: ignore[union-attr] @@ -1656,63 +1656,63 @@ def test_desc(self) -> None: with self.subTest(msg='node: msk_top_regs.f1_nco_adjust.data'): - self.assertEqual(self.dut.f1_nco_adjust.data.rdl_desc, "Frequency offet applied to the F1 NCO") # type: ignore[union-attr] + self.assertEqual(self.dut.f1_nco_adjust.data.rdl_desc, "Frequency offet applied to the F1 NCO\n\nThis register is write-to-capture.\n\nTo read data the following steps are required:\n\n1 - Write any value to this register to capture read data\n\n2 - Read the register") # type: ignore[union-attr] with self.subTest(msg='node: msk_top_regs.f2_nco_adjust.data'): - self.assertEqual(self.dut.f2_nco_adjust.data.rdl_desc, "Frequency offet applied to the F2 NCO") # type: ignore[union-attr] + self.assertEqual(self.dut.f2_nco_adjust.data.rdl_desc, "Frequency offet applied to the F2 NCO\n\nThis register is write-to-capture.\n\nTo read data the following steps are required:\n\n1 - Write any value to this register to capture read data\n\n2 - Read the register") # type: ignore[union-attr] with self.subTest(msg='node: msk_top_regs.f1_error.data'): - self.assertEqual(self.dut.f1_error.data.rdl_desc, "Error value of the F1 Costas loop after each active bit period") # type: ignore[union-attr] + self.assertEqual(self.dut.f1_error.data.rdl_desc, "Error value of the F1 Costas loop after each active bit period\n\nThis register is write-to-capture.\n\nTo read data the following steps are required:\n\n1 - Write any value to this register to capture read data\n\n2 - Read the register") # type: ignore[union-attr] with self.subTest(msg='node: msk_top_regs.f2_error.data'): - self.assertEqual(self.dut.f2_error.data.rdl_desc, "Error value of the F2 Costas loop after each active bit period") # type: ignore[union-attr] + self.assertEqual(self.dut.f2_error.data.rdl_desc, "Error value of the F2 Costas loop after each active bit period\n\nThis register is write-to-capture.\n\nTo read data the following steps are required:\n\n1 - Write any value to this register to capture read data\n\n2 - Read the register") # type: ignore[union-attr] with self.subTest(msg='node: msk_top_regs.Tx_Sync_Ctrl.tx_sync_ena'): - self.assertEqual(self.dut.Tx_Sync_Ctrl.tx_sync_ena.rdl_desc, "0 -\u003e Disable sync transmission\n1 -\u003e Enable sync transmission when PTT is asserted") # type: ignore[union-attr] + self.assertEqual(self.dut.Tx_Sync_Ctrl.tx_sync_ena.rdl_desc, "0 -\u003e Disable sync transmission\n\n1 -\u003e Enable sync transmission when PTT is asserted") # type: ignore[union-attr] with self.subTest(msg='node: msk_top_regs.Tx_Sync_Ctrl.tx_sync_force'): - self.assertEqual(self.dut.Tx_Sync_Ctrl.tx_sync_force.rdl_desc, "0 : Normal operation)\n1 : Transmit synchronization pattern)") # type: ignore[union-attr] + self.assertEqual(self.dut.Tx_Sync_Ctrl.tx_sync_force.rdl_desc, "0 : Normal operation\n\n1 : Transmit synchronization pattern") # type: ignore[union-attr] with self.subTest(msg='node: msk_top_regs.Tx_Sync_Ctrl.tx_sync_f1'): - self.assertEqual(self.dut.Tx_Sync_Ctrl.tx_sync_f1.rdl_desc, "Enables/Disables transmission of F1 tone for receiver synchronization\n0 : F1 tone transmission disabled\n1 : F1 tone transmission enabled\nBoth F1 and F2 can be enabled at the same time") # type: ignore[union-attr] + self.assertEqual(self.dut.Tx_Sync_Ctrl.tx_sync_f1.rdl_desc, "Enables/Disables transmission of F1 tone for receiver synchronization\n0 : F1 tone transmission disabled\n\n1 : F1 tone transmission enabled\n\nBoth F1 and F2 can be enabled at the same time") # type: ignore[union-attr] with self.subTest(msg='node: msk_top_regs.Tx_Sync_Ctrl.tx_sync_f2'): - self.assertEqual(self.dut.Tx_Sync_Ctrl.tx_sync_f2.rdl_desc, "Enables/Disables transmission of F2 tone for receiver synchronization\n0 : F2 tone transmission disabled\n1 : F2 tone transmission enabled\nBoth F1 and F2 can be enabled at the same time") # type: ignore[union-attr] + self.assertEqual(self.dut.Tx_Sync_Ctrl.tx_sync_f2.rdl_desc, "Enables/Disables transmission of F2 tone for receiver synchronization\n0 : F2 tone transmission disabled\n\n1 : F2 tone transmission enabled\n\nBoth F1 and F2 can be enabled at the same time") # type: ignore[union-attr] with self.subTest(msg='node: msk_top_regs.Tx_Sync_Cnt.tx_sync_cnt'): - self.assertEqual(self.dut.Tx_Sync_Cnt.tx_sync_cnt.rdl_desc, "Value from 0x00_0000 to 0xFF_FFFF. \nThis value represents the number bit-times the synchronization \nsignal should be sent after PTT is asserted.") # type: ignore[union-attr] + self.assertEqual(self.dut.Tx_Sync_Cnt.tx_sync_cnt.rdl_desc, "Value from 0x00_0000 to 0xFF_FFFF. \n\nThis value represents the number bit-times the synchronization \n\nsignal should be sent after PTT is asserted.") # type: ignore[union-attr] @@ -1733,21 +1733,21 @@ def test_desc(self) -> None: with self.subTest(msg='node: msk_top_regs.rx_power.data'): - self.assertEqual(self.dut.rx_power.data.rdl_desc, "Value that represent the RMS power of the incoming I;") # type: ignore[union-attr] + self.assertEqual(self.dut.rx_power.data.rdl_desc, "Value that represent the RMS power of the incoming I\n\nThis register is write-to-capture.\n\nTo read data the following steps are required:\n\n1 - Write any value to this register to capture read data\n\n2 - Read the register") # type: ignore[union-attr] with self.subTest(msg='node: msk_top_regs.tx_async_fifo_rd_wr_ptr.data'): - self.assertEqual(self.dut.tx_async_fifo_rd_wr_ptr.data.rdl_desc, "Bits 31:16 -\u003e write pointer (12-bits)\nBits 15:00 -\u003e read pointer (12-bits)") # type: ignore[union-attr] + self.assertEqual(self.dut.tx_async_fifo_rd_wr_ptr.data.rdl_desc, "Read and Write Pointers\n\nBits 31:16 - write pointer (12-bits)\n\nBits 15:00 - read pointer (12-bits)\n\nThis register is write-to-capture.\n\nTo read data the following steps are required:\n\n1 - Write any value to this register to capture read data\n\n2 - Read the register") # type: ignore[union-attr] with self.subTest(msg='node: msk_top_regs.rx_async_fifo_rd_wr_ptr.data'): - self.assertEqual(self.dut.rx_async_fifo_rd_wr_ptr.data.rdl_desc, "Bits 31:16 -\u003e write pointer (12-bits)\nBits 15:00 -\u003e read pointer (12-bits)") # type: ignore[union-attr] + self.assertEqual(self.dut.rx_async_fifo_rd_wr_ptr.data.rdl_desc, "Read and Write Pointers\n\nBits 31:16 - write pointer (12-bits)\n\nBits 15:00 - read pointer (12-bits)\n\nThis register is write-to-capture.\n\nTo read data the following steps are required:\n\n1 - Write any value to this register to capture read data\n\n2 - Read the register") # type: ignore[union-attr] diff --git a/rdl/outputs/rtl/msk_top_regs_pkg.vhd b/rdl/outputs/rtl/msk_top_regs_pkg.vhd index c7439ad..e646abe 100644 --- a/rdl/outputs/rtl/msk_top_regs_pkg.vhd +++ b/rdl/outputs/rtl/msk_top_regs_pkg.vhd @@ -97,40 +97,40 @@ package msk_top_regs_pkg is data : \msk_top_regs.msk_stat_3.data_in_t\; end record; - type \msk_top_regs.data32_desc_64ff3689_name_d8ad3b25_in_t\ is record + type \msk_top_regs.data32_desc_0ed96915_in_t\ is record next_q : std_logic_vector(31 downto 0); we : std_logic; end record; - type \msk_top_regs.observation_data_data_0c017ef4_desc_64ff3689_name_d8ad3b25_in_t\ is record - data : \msk_top_regs.data32_desc_64ff3689_name_d8ad3b25_in_t\; + type \msk_top_regs.observation_data_data_521c7d53_name_d8ad3b25_in_t\ is record + data : \msk_top_regs.data32_desc_0ed96915_in_t\; end record; - type \msk_top_regs.data32_desc_ebde6d39_name_2c154788_in_t\ is record + type \msk_top_regs.data32_desc_13897f4c_in_t\ is record next_q : std_logic_vector(31 downto 0); we : std_logic; end record; - type \msk_top_regs.observation_data_data_0515efaa_desc_ebde6d39_name_2c154788_in_t\ is record - data : \msk_top_regs.data32_desc_ebde6d39_name_2c154788_in_t\; + type \msk_top_regs.observation_data_data_5802c5b1_name_2c154788_in_t\ is record + data : \msk_top_regs.data32_desc_13897f4c_in_t\; end record; - type \msk_top_regs.data32_desc_417e1c96_name_3b640507_in_t\ is record + type \msk_top_regs.data32_desc_83db1b72_in_t\ is record next_q : std_logic_vector(31 downto 0); we : std_logic; end record; - type \msk_top_regs.observation_data_data_25a21249_desc_417e1c96_name_3b640507_in_t\ is record - data : \msk_top_regs.data32_desc_417e1c96_name_3b640507_in_t\; + type \msk_top_regs.observation_data_data_f83682dd_name_3b640507_in_t\ is record + data : \msk_top_regs.data32_desc_83db1b72_in_t\; end record; - type \msk_top_regs.data32_desc_70869502_name_3de9a0d3_in_t\ is record + type \msk_top_regs.data32_desc_c8bf066a_in_t\ is record next_q : std_logic_vector(31 downto 0); we : std_logic; end record; - type \msk_top_regs.observation_data_data_272a00b6_desc_70869502_name_3de9a0d3_in_t\ is record - data : \msk_top_regs.data32_desc_70869502_name_3de9a0d3_in_t\; + type \msk_top_regs.observation_data_data_0a9850a4_name_3de9a0d3_in_t\ is record + data : \msk_top_regs.data32_desc_c8bf066a_in_t\; end record; type \msk_top_regs.rx_power.data_in_t\ is record @@ -142,17 +142,17 @@ package msk_top_regs_pkg is data : \msk_top_regs.rx_power.data_in_t\; end record; - type \msk_top_regs.data32_desc_7b98a70e_in_t\ is record + type \msk_top_regs.data32_desc_52ad9f96_in_t\ is record next_q : std_logic_vector(31 downto 0); we : std_logic; end record; - type \msk_top_regs.observation_data_data_cf6acbd7_name_aa4ec676_in_t\ is record - data : \msk_top_regs.data32_desc_7b98a70e_in_t\; + type \msk_top_regs.observation_data_data_dbd8270c_name_aa4ec676_in_t\ is record + data : \msk_top_regs.data32_desc_52ad9f96_in_t\; end record; - type \msk_top_regs.observation_data_data_cf6acbd7_name_8a90eed1_in_t\ is record - data : \msk_top_regs.data32_desc_7b98a70e_in_t\; + type \msk_top_regs.observation_data_data_dbd8270c_name_8a90eed1_in_t\ is record + data : \msk_top_regs.data32_desc_52ad9f96_in_t\; end record; type msk_top_regs_in_t is record @@ -164,13 +164,13 @@ package msk_top_regs_pkg is LPF_Accum_F1 : \msk_top_regs.stat_32_lpf_acc_desc_8cebc7dc_name_f20c6670_in_t\; LPF_Accum_F2 : \msk_top_regs.stat_32_lpf_acc_desc_dea6bd99_name_758fd0ce_in_t\; axis_xfer_count : \msk_top_regs.msk_stat_3_in_t\; - f1_nco_adjust : \msk_top_regs.observation_data_data_0c017ef4_desc_64ff3689_name_d8ad3b25_in_t\; - f2_nco_adjust : \msk_top_regs.observation_data_data_0515efaa_desc_ebde6d39_name_2c154788_in_t\; - f1_error : \msk_top_regs.observation_data_data_25a21249_desc_417e1c96_name_3b640507_in_t\; - f2_error : \msk_top_regs.observation_data_data_272a00b6_desc_70869502_name_3de9a0d3_in_t\; + f1_nco_adjust : \msk_top_regs.observation_data_data_521c7d53_name_d8ad3b25_in_t\; + f2_nco_adjust : \msk_top_regs.observation_data_data_5802c5b1_name_2c154788_in_t\; + f1_error : \msk_top_regs.observation_data_data_f83682dd_name_3b640507_in_t\; + f2_error : \msk_top_regs.observation_data_data_0a9850a4_name_3de9a0d3_in_t\; rx_power : \msk_top_regs.rx_power_in_t\; - tx_async_fifo_rd_wr_ptr : \msk_top_regs.observation_data_data_cf6acbd7_name_aa4ec676_in_t\; - rx_async_fifo_rd_wr_ptr : \msk_top_regs.observation_data_data_cf6acbd7_name_8a90eed1_in_t\; + tx_async_fifo_rd_wr_ptr : \msk_top_regs.observation_data_data_dbd8270c_name_aa4ec676_in_t\; + rx_async_fifo_rd_wr_ptr : \msk_top_regs.observation_data_data_dbd8270c_name_8a90eed1_in_t\; end record; type \msk_top_regs.msk_init.txrxinit_out_t\ is record @@ -450,36 +450,36 @@ package msk_top_regs_pkg is p_shift : \msk_top_regs.lpf_config_2.p_shift_out_t\; end record; - type \msk_top_regs.data32_desc_64ff3689_name_d8ad3b25_out_t\ is record + type \msk_top_regs.data32_desc_0ed96915_out_t\ is record swmod : std_logic; end record; - type \msk_top_regs.observation_data_data_0c017ef4_desc_64ff3689_name_d8ad3b25_out_t\ is record - data : \msk_top_regs.data32_desc_64ff3689_name_d8ad3b25_out_t\; + type \msk_top_regs.observation_data_data_521c7d53_name_d8ad3b25_out_t\ is record + data : \msk_top_regs.data32_desc_0ed96915_out_t\; end record; - type \msk_top_regs.data32_desc_ebde6d39_name_2c154788_out_t\ is record + type \msk_top_regs.data32_desc_13897f4c_out_t\ is record swmod : std_logic; end record; - type \msk_top_regs.observation_data_data_0515efaa_desc_ebde6d39_name_2c154788_out_t\ is record - data : \msk_top_regs.data32_desc_ebde6d39_name_2c154788_out_t\; + type \msk_top_regs.observation_data_data_5802c5b1_name_2c154788_out_t\ is record + data : \msk_top_regs.data32_desc_13897f4c_out_t\; end record; - type \msk_top_regs.data32_desc_417e1c96_name_3b640507_out_t\ is record + type \msk_top_regs.data32_desc_83db1b72_out_t\ is record swmod : std_logic; end record; - type \msk_top_regs.observation_data_data_25a21249_desc_417e1c96_name_3b640507_out_t\ is record - data : \msk_top_regs.data32_desc_417e1c96_name_3b640507_out_t\; + type \msk_top_regs.observation_data_data_f83682dd_name_3b640507_out_t\ is record + data : \msk_top_regs.data32_desc_83db1b72_out_t\; end record; - type \msk_top_regs.data32_desc_70869502_name_3de9a0d3_out_t\ is record + type \msk_top_regs.data32_desc_c8bf066a_out_t\ is record swmod : std_logic; end record; - type \msk_top_regs.observation_data_data_272a00b6_desc_70869502_name_3de9a0d3_out_t\ is record - data : \msk_top_regs.data32_desc_70869502_name_3de9a0d3_out_t\; + type \msk_top_regs.observation_data_data_0a9850a4_name_3de9a0d3_out_t\ is record + data : \msk_top_regs.data32_desc_c8bf066a_out_t\; end record; type \msk_top_regs.tx_sync_ctrl.tx_sync_ena_out_t\ is record @@ -529,16 +529,16 @@ package msk_top_regs_pkg is data : \msk_top_regs.rx_power.data_out_t\; end record; - type \msk_top_regs.data32_desc_7b98a70e_out_t\ is record + type \msk_top_regs.data32_desc_52ad9f96_out_t\ is record swmod : std_logic; end record; - type \msk_top_regs.observation_data_data_cf6acbd7_name_aa4ec676_out_t\ is record - data : \msk_top_regs.data32_desc_7b98a70e_out_t\; + type \msk_top_regs.observation_data_data_dbd8270c_name_aa4ec676_out_t\ is record + data : \msk_top_regs.data32_desc_52ad9f96_out_t\; end record; - type \msk_top_regs.observation_data_data_cf6acbd7_name_8a90eed1_out_t\ is record - data : \msk_top_regs.data32_desc_7b98a70e_out_t\; + type \msk_top_regs.observation_data_data_dbd8270c_name_8a90eed1_out_t\ is record + data : \msk_top_regs.data32_desc_52ad9f96_out_t\; end record; type msk_top_regs_out_t is record @@ -566,16 +566,16 @@ package msk_top_regs_pkg is axis_xfer_count : \msk_top_regs.msk_stat_3_out_t\; Rx_Sample_Discard : \msk_top_regs.rx_sample_discard_out_t\; LPF_Config_2 : \msk_top_regs.lpf_config_2_out_t\; - f1_nco_adjust : \msk_top_regs.observation_data_data_0c017ef4_desc_64ff3689_name_d8ad3b25_out_t\; - f2_nco_adjust : \msk_top_regs.observation_data_data_0515efaa_desc_ebde6d39_name_2c154788_out_t\; - f1_error : \msk_top_regs.observation_data_data_25a21249_desc_417e1c96_name_3b640507_out_t\; - f2_error : \msk_top_regs.observation_data_data_272a00b6_desc_70869502_name_3de9a0d3_out_t\; + f1_nco_adjust : \msk_top_regs.observation_data_data_521c7d53_name_d8ad3b25_out_t\; + f2_nco_adjust : \msk_top_regs.observation_data_data_5802c5b1_name_2c154788_out_t\; + f1_error : \msk_top_regs.observation_data_data_f83682dd_name_3b640507_out_t\; + f2_error : \msk_top_regs.observation_data_data_0a9850a4_name_3de9a0d3_out_t\; Tx_Sync_Ctrl : \msk_top_regs.tx_sync_ctrl_out_t\; Tx_Sync_Cnt : \msk_top_regs.tx_sync_cnt_out_t\; lowpass_ema_alpha1 : \msk_top_regs.lowpass_ema_alpha_out_t\; lowpass_ema_alpha2 : \msk_top_regs.lowpass_ema_alpha_out_t\; rx_power : \msk_top_regs.rx_power_out_t\; - tx_async_fifo_rd_wr_ptr : \msk_top_regs.observation_data_data_cf6acbd7_name_aa4ec676_out_t\; - rx_async_fifo_rd_wr_ptr : \msk_top_regs.observation_data_data_cf6acbd7_name_8a90eed1_out_t\; + tx_async_fifo_rd_wr_ptr : \msk_top_regs.observation_data_data_dbd8270c_name_aa4ec676_out_t\; + rx_async_fifo_rd_wr_ptr : \msk_top_regs.observation_data_data_dbd8270c_name_8a90eed1_out_t\; end record; end package; diff --git a/rdl/src/msk_top_regs.rdl b/rdl/src/msk_top_regs.rdl index f8a2598..6c22529 100644 --- a/rdl/src/msk_top_regs.rdl +++ b/rdl/src/msk_top_regs.rdl @@ -92,18 +92,21 @@ addrmap msk_top_regs { field { name = "Tx/Rx Init Enable"; desc = "0 -> Normal modem operation + 1 -> Initialize Tx and Rx"; } txrxinit = 1; field { name = "Tx Init Enable"; - desc = "0 -> Normal Tx operation + desc = "0 -> Normal Tx operation + 1 -> Initialize Tx"; } txinit = 1; field { name = "Rx Init Enable"; - desc = "0 -> Normal Rx operation + desc = "0 -> Normal Rx operation + 1 -> Initialize Rx"; } rxinit = 1; }; @@ -121,6 +124,7 @@ addrmap msk_top_regs { field { name = "Modem Digital Tx -> Rx Loopback Enable"; desc = "0 -> Modem loopback disabled + 1 -> Modem loopback enabled"; } loopback_ena = 0; field { @@ -136,6 +140,7 @@ addrmap msk_top_regs { field { name = "Differential Encoder -> Decoder Loopback Enable"; desc = "0 -> Differential Encoder -> Decoder loopback disabled + 1 -> Differential Encoder -> Decoder loopback enabled"; } diff_encoder_loopback = 0; }; @@ -153,6 +158,7 @@ addrmap msk_top_regs { field { name = "AD9363 DAC Interface Tx Enable Input Active"; desc = "1 -> Data to DAC Enabled + 0 -> Data to DAC Disabled"; sw = r; hw = w; @@ -160,6 +166,7 @@ addrmap msk_top_regs { field { name = "AD9363 ADC Interface Rx Enable Input Active"; desc = "1 -> Data from ADC Enabled + 0 -> Data from ADC Disabled"; sw = r; hw = w; @@ -167,6 +174,7 @@ addrmap msk_top_regs { field { name = "Tx S_AXIS_VALID"; desc = "1 -> S_AXIS_VALID Enabled + 0 -> S_AXIS_VALID Disabled"; sw = r; hw = w; @@ -179,7 +187,15 @@ addrmap msk_top_regs { regwidth = 32; field { name = "Tx Bit Count"; - desc = "Count of data requests made by modem"; + desc = "Count of data requests made by modem + + This register is write-to-capture. + + To read data the following steps are required: + + 1 - Write any value to this register to capture read data + + 2 - Read the register"; sw = rw; hw = w; we = true; @@ -192,7 +208,15 @@ addrmap msk_top_regs { desc = "Modem status data"; regwidth = 32; field { - desc = "Number of clocks on which Tx Enable is active"; + desc = "Number of clocks on which Tx Enable is active + + This register is write-to-capture. + + To read data the following steps are required: + + 1 - Write any value to this register to capture read data + + 2 - Read the register"; name = "Tx Enable Count"; sw = rw; hw = w; @@ -231,11 +255,13 @@ addrmap msk_top_regs { field { name = "Freeze the accumulator's current value"; desc = "0 -> Normal operation + 1 -> Freeze current value"; } lpf_freeze = 0; field { name = "Hold the PI Accumulator at zero"; desc = "0 -> Normal operation + 1 -> Zero and hold accumulator"; } lpf_zero = 0; field { @@ -295,6 +321,7 @@ addrmap msk_top_regs { field { name = "PRBS Error Insert"; desc = "0 -> 1 : Insert bit error in Tx data (both Normal and PRBS) + 1 -> 0 : Insert bit error in Tx data (both Normal and PRBS)"; sw = w; hw = r; @@ -303,6 +330,7 @@ addrmap msk_top_regs { field { name = "PRBS Clear Counters"; desc = "0 -> 1 : Clear PRBS Counters + 1 -> 0 : Clear PRBS Counters"; sw = w; hw = r; @@ -311,6 +339,7 @@ addrmap msk_top_regs { field { name = "PRBS Manual Sync"; desc = "0 -> 1 : Synchronize PRBS monitor + 1 -> 0 : Synchronize PRBS monitor"; sw = w; hw = r; @@ -322,6 +351,7 @@ addrmap msk_top_regs { field { name = "PRBS Auto Sync Threshold"; desc = "0 : Auto Sync Disabled + N > 0 : Auto sync after N errors"; } prbs_sync_threshold[31:16] = 0; }; @@ -332,6 +362,7 @@ addrmap msk_top_regs { regwidth = 32; field { name = "PRBS Seed"; + desc = "Sets the starting value of the PRBS generator"; } config_data[31:0] = 0; }; @@ -342,6 +373,7 @@ addrmap msk_top_regs { regwidth = 32; field { name = "PRBS Polynomial"; + desc = "Bit positions set to '1' indicate polynomial feedback positions"; } config_data[31:0] = 0; }; @@ -352,6 +384,7 @@ addrmap msk_top_regs { regwidth = 32; field { name = "PRBS Error Mask"; + desc = "Bit positions set to '1' indicate bits that are inverted when a bit error is inserted"; } config_data[31:0] = 0; }; @@ -363,7 +396,15 @@ addrmap msk_top_regs { field { name = "PRBS Bits Received"; desc = "Number of bits received by the PRBS monitor since last - BER can be calculated as the ratio of received bits to errored-bits"; + BER can be calculated as the ratio of received bits to errored-bits + + This register is write-to-capture. + + To read data the following steps are required: + + 1 - Write any value to this register to capture read data + + 2 - Read the register"; sw = rw; hw = w; we = true; @@ -378,7 +419,15 @@ addrmap msk_top_regs { field { name = "PRBS Bit Errors"; desc = "Number of errored-bits received by the PRBS monitor since last sync - BER can be calculated as the ratio of received bits to errored-bits"; + BER can be calculated as the ratio of received bits to errored-bits + + This register is write-to-capture. + + To read data the following steps are required: + + 1 - Write any value to this register to capture read data + + 2 - Read the register"; sw = rw; hw = w; we = true; @@ -390,7 +439,15 @@ addrmap msk_top_regs { regwidth = 32; field { name = "PI Controller Accumulator Value"; - desc = "PI Controller Accumulator Value"; + desc = "PI Controller Accumulator Value + + This register is write-to-capture. + + To read data the following steps are required: + + 1 - Write any value to this register to capture read data + + 2 - Read the register"; sw = rw; hw = w; we = true; @@ -403,8 +460,16 @@ addrmap msk_top_regs { desc = "Modem status data"; regwidth = 32; field { - desc = "Number completed S_AXIS transfers"; name = "S_AXIS Transfers"; + desc = "Number completed S_AXIS transfers + + This register is write-to-capture. + + To read data the following steps are required: + + 1 - Write any value to this register to capture read data + + 2 - Read the register"; sw = rw; hw = w; we = true; @@ -419,25 +484,31 @@ addrmap msk_top_regs { field { name = "Tx Sync Enable"; desc = "0 -> Disable sync transmission + 1 -> Enable sync transmission when PTT is asserted"; } tx_sync_ena = 0; field { name = "Tx Sync Force"; - desc = "0 : Normal operation) - 1 : Transmit synchronization pattern)"; + desc = "0 : Normal operation + + 1 : Transmit synchronization pattern"; } tx_sync_force = 0; field { name = "Tx F1 Sync Enable"; desc = "Enables/Disables transmission of F1 tone for receiver synchronization 0 : F1 tone transmission disabled + 1 : F1 tone transmission enabled + Both F1 and F2 can be enabled at the same time"; } tx_sync_f1 = 0; field { name = "Tx F2 Sync Enable"; desc = "Enables/Disables transmission of F2 tone for receiver synchronization 0 : F2 tone transmission disabled + 1 : F2 tone transmission enabled + Both F1 and F2 can be enabled at the same time"; } tx_sync_f2 = 0; }; @@ -449,7 +520,9 @@ addrmap msk_top_regs { field { name = "Tx sync duration"; desc = "Value from 0x00_0000 to 0xFF_FFFF. + This value represents the number bit-times the synchronization + signal should be sent after PTT is asserted."; sw = rw; hw = r; @@ -472,7 +545,15 @@ addrmap msk_top_regs { regwidth = 32; field { name = "Receive Power"; - desc = "Value that represent the RMS power of the incoming I;"; + desc = "Value that represent the RMS power of the incoming I + + This register is write-to-capture. + + To read data the following steps are required: + + 1 - Write any value to this register to capture read data + + 2 - Read the register"; sw = rw; hw = w; we = true; @@ -541,24 +622,48 @@ addrmap msk_top_regs { lpf_config_2 LPF_Config_2; observation_data f1_nco_adjust; f1_nco_adjust->name = "F1 NCO Frequency Adjust"; - f1_nco_adjust->desc = "Frequency offet applied to the F1 NCO"; - f1_nco_adjust.data->name = "F1 NCO Frequency Adjust"; - f1_nco_adjust.data->desc = "Frequency offet applied to the F1 NCO"; + f1_nco_adjust.data->desc = "Frequency offet applied to the F1 NCO + + This register is write-to-capture. + + To read data the following steps are required: + + 1 - Write any value to this register to capture read data + + 2 - Read the register"; observation_data f2_nco_adjust; f2_nco_adjust->name = "F2 NCO Frequency Adjust"; - f2_nco_adjust->desc = "Frequency offet applied to the F2 NCO"; - f2_nco_adjust.data->name = "F2 NCO Frequency Adjust"; - f2_nco_adjust.data->desc = "Frequency offet applied to the F2 NCO"; + f2_nco_adjust.data->desc = "Frequency offet applied to the F2 NCO + + This register is write-to-capture. + + To read data the following steps are required: + + 1 - Write any value to this register to capture read data + + 2 - Read the register"; observation_data f1_error; f1_error->name = "F1 Error Value"; - f1_error->desc = "Error value of the F1 Costas loop after each active bit period"; - f1_error.data->name = "F1 Error Value"; - f1_error.data->desc = "Error value of the F1 Costas loop after each active bit period"; + f1_error.data->desc = "Error value of the F1 Costas loop after each active bit period + + This register is write-to-capture. + + To read data the following steps are required: + + 1 - Write any value to this register to capture read data + + 2 - Read the register"; observation_data f2_error; f2_error->name = "F2 Error Value"; - f2_error->desc = "Error value of the F2 Costas loop after each active bit period"; - f2_error.data->name = "F2 Error Value"; - f2_error.data->desc = "Error value of the F2 Costas loop after each active bit period"; + f2_error.data->desc = "Error value of the F2 Costas loop after each active bit period + + This register is write-to-capture. + + To read data the following steps are required: + + 1 - Write any value to this register to capture read data + + 2 - Read the register"; tx_sync_ctrl Tx_Sync_Ctrl; tx_sync_cnt Tx_Sync_Cnt; lowpass_ema_alpha lowpass_ema_alpha1; @@ -566,10 +671,32 @@ addrmap msk_top_regs { rx_power rx_power; observation_data tx_async_fifo_rd_wr_ptr; tx_async_fifo_rd_wr_ptr->name = "Tx async FIFO read and write pointers"; - tx_async_fifo_rd_wr_ptr.data->desc = "Bits 31:16 -> write pointer (12-bits) - Bits 15:00 -> read pointer (12-bits)"; + tx_async_fifo_rd_wr_ptr.data->desc = "Read and Write Pointers + + Bits 31:16 - write pointer (12-bits) + + Bits 15:00 - read pointer (12-bits) + + This register is write-to-capture. + + To read data the following steps are required: + + 1 - Write any value to this register to capture read data + + 2 - Read the register"; observation_data rx_async_fifo_rd_wr_ptr; rx_async_fifo_rd_wr_ptr->name = "Rx async FIFO read and write pointers"; - rx_async_fifo_rd_wr_ptr.data->desc = "Bits 31:16 -> write pointer (12-bits) - Bits 15:00 -> read pointer (12-bits)"; + rx_async_fifo_rd_wr_ptr.data->desc = "Read and Write Pointers + + Bits 31:16 - write pointer (12-bits) + + Bits 15:00 - read pointer (12-bits) + + This register is write-to-capture. + + To read data the following steps are required: + + 1 - Write any value to this register to capture read data + + 2 - Read the register"; }; From eadbfcb4a0a50be28ff0fe59a2951cce752b8c5c Mon Sep 17 00:00:00 2001 From: Matthew Wishek Date: Thu, 6 Nov 2025 11:07:54 -0700 Subject: [PATCH 22/60] rdl: update register descriptions, add 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rdl/outputs/docs/html/fonts/FontAwesome/fa-solid-900.woff2 create mode 100644 rdl/outputs/docs/html/fonts/Lato/lato-bold.eot create mode 100644 rdl/outputs/docs/html/fonts/Lato/lato-bold.ttf create mode 100644 rdl/outputs/docs/html/fonts/Lato/lato-bold.woff create mode 100644 rdl/outputs/docs/html/fonts/Lato/lato-bold.woff2 create mode 100644 rdl/outputs/docs/html/fonts/Lato/lato-bolditalic.eot create mode 100644 rdl/outputs/docs/html/fonts/Lato/lato-bolditalic.ttf create mode 100644 rdl/outputs/docs/html/fonts/Lato/lato-bolditalic.woff create mode 100644 rdl/outputs/docs/html/fonts/Lato/lato-bolditalic.woff2 create mode 100644 rdl/outputs/docs/html/fonts/Lato/lato-italic.eot create mode 100644 rdl/outputs/docs/html/fonts/Lato/lato-italic.ttf create mode 100644 rdl/outputs/docs/html/fonts/Lato/lato-italic.woff create mode 100644 rdl/outputs/docs/html/fonts/Lato/lato-italic.woff2 create mode 100644 rdl/outputs/docs/html/fonts/Lato/lato-regular.eot create mode 100644 rdl/outputs/docs/html/fonts/Lato/lato-regular.ttf create mode 100644 rdl/outputs/docs/html/fonts/Lato/lato-regular.woff create mode 100644 rdl/outputs/docs/html/fonts/Lato/lato-regular.woff2 create mode 100644 rdl/outputs/docs/html/fonts/RobotoSlab/roboto-slab-v7-bold.eot create mode 100644 rdl/outputs/docs/html/fonts/RobotoSlab/roboto-slab-v7-bold.ttf create mode 100644 rdl/outputs/docs/html/fonts/RobotoSlab/roboto-slab-v7-bold.woff create mode 100644 rdl/outputs/docs/html/fonts/RobotoSlab/roboto-slab-v7-bold.woff2 create mode 100644 rdl/outputs/docs/html/fonts/RobotoSlab/roboto-slab-v7-regular.eot create mode 100644 rdl/outputs/docs/html/fonts/RobotoSlab/roboto-slab-v7-regular.ttf create mode 100644 rdl/outputs/docs/html/fonts/RobotoSlab/roboto-slab-v7-regular.woff create mode 100644 rdl/outputs/docs/html/fonts/RobotoSlab/roboto-slab-v7-regular.woff2 create mode 100644 rdl/outputs/docs/html/index.html create mode 100644 rdl/outputs/docs/html/js/address_search.js create mode 100644 rdl/outputs/docs/html/js/content_search.js create mode 100644 rdl/outputs/docs/html/js/field_testers.js create mode 100644 rdl/outputs/docs/html/js/index_edit.js create mode 100644 rdl/outputs/docs/html/js/main.js create mode 100644 rdl/outputs/docs/html/js/nav.js create mode 100644 rdl/outputs/docs/html/js/path_search.js create mode 100644 rdl/outputs/docs/html/js/progressbar.min.js create mode 100644 rdl/outputs/docs/html/js/ral.js create mode 100644 rdl/outputs/docs/html/js/search.js create mode 100644 rdl/outputs/docs/html/js/sha1.js create mode 100644 rdl/outputs/docs/html/js/sidebar.js create mode 100644 rdl/outputs/docs/html/launcher-windows-chrome.bat create mode 100644 rdl/outputs/docs/html/launcher-windows-edge.bat create mode 100644 rdl/outputs/docs/html/launcher-windows-firefox.bat create mode 100644 rdl/outputs/docs/html/search/bkt-0.json create mode 100644 rdl/outputs/docs/html/search/bkt_index.js diff --git a/rdl/Makefile b/rdl/Makefile index 901e45d..3d7be10 100644 --- a/rdl/Makefile +++ b/rdl/Makefile @@ -10,6 +10,7 @@ OUTCHEADER = outputs/c-header all: $(OUTDOCS)/msk_top_regs.pdf \ $(OUTDOCS)/msk_top_regs.md \ + $(OUTDOCS)/html/index.html \ $(OUTRTL)/msk_top_regs.vhd \ $(OUTPYTHON)/__init__.py \ $(OUTCHEADER)/msk_top_regs.h @@ -17,20 +18,23 @@ all: $(OUTDOCS)/msk_top_regs.pdf \ $(OUTDOCS)/msk_top_regs.md: $(SRCS) peakrdl markdown $(SRCS) -o $(OUTDOCS)/msk_top_regs.md +$(OUTDOCS)/html/index.html: $(SRCS) + peakrdl html $(SRCS) -o $(OUTDOCS)/html + $(OUTCHEADER)/msk_top_regs.h: $(SRCS) peakrdl c-header $(SRCS) -o outputs/c-header/msk_top_regs.h $(OUTRTL)/msk_top_regs.vhd: $(SRCS) peakrdl regblock-vhdl $(SRCS) -o $(OUTRTL) --cpuif axi4-lite -$(OUTDOCS)/msk_top_regs.pdf: $(OUTDOCS)/msk_top_regs.md - pandoc -o $(OUTDOCS)/msk_top_regs.pdf $(OUTDOCS)/msk_top_regs.md +$(OUTDOCS)/msk_top_regs.pdf: $(OUTDOCS)/html/index.html + pandoc -o $(OUTDOCS)/msk_top_regs.pdf $(OUTDOCS)/html/index.html --pdf-engine=weasyprint --css=$(OUTDOCS)/html/css/theme.css $(OUTPYTHON)/__init__.py: $(SRCS) peakrdl python $(SRCS) --async -o $(OUTPYTHON) clean: - rm outputs/docs/* + rm -r outputs/docs/* rm outputs/c-header/* rm -r outputs/python/* - rm outputs/rtl/* \ No newline at end of file + rm outputs/rtl/* diff --git a/rdl/outputs/c-header/msk_top_regs.h b/rdl/outputs/c-header/msk_top_regs.h index d5b3d65..a290f98 100644 --- a/rdl/outputs/c-header/msk_top_regs.h +++ b/rdl/outputs/c-header/msk_top_regs.h @@ -319,11 +319,11 @@ extern "C" { #define MSK_TOP_REGS__OBSERVATION_DATA_DATA_DBD8270C_NAME_AA4EC676__DATA_bw 32 #define MSK_TOP_REGS__OBSERVATION_DATA_DATA_DBD8270C_NAME_AA4EC676__DATA_reset 0x0 -// Reg - msk_top_regs::observation_data_data_dbd8270c_name_8a90eed1 -#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_DBD8270C_NAME_8A90EED1__DATA_bm 0xffffffff -#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_DBD8270C_NAME_8A90EED1__DATA_bp 0 -#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_DBD8270C_NAME_8A90EED1__DATA_bw 32 -#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_DBD8270C_NAME_8A90EED1__DATA_reset 0x0 +// Reg - msk_top_regs::observation_data_data_91b9abca_name_8a90eed1 +#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_91B9ABCA_NAME_8A90EED1__DATA_bm 0xffffffff +#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_91B9ABCA_NAME_8A90EED1__DATA_bp 0 +#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_91B9ABCA_NAME_8A90EED1__DATA_bw 32 +#define MSK_TOP_REGS__OBSERVATION_DATA_DATA_91B9ABCA_NAME_8A90EED1__DATA_reset 0x0 // Addrmap - msk_top_regs typedef struct __attribute__ ((__packed__)) { diff --git a/rdl/outputs/docs/html/.launcher_data/firefox/user.js b/rdl/outputs/docs/html/.launcher_data/firefox/user.js new file mode 100644 index 0000000..34b966f --- /dev/null +++ b/rdl/outputs/docs/html/.launcher_data/firefox/user.js @@ -0,0 +1,4 @@ +user_pref("app.normandy.first_run", false); +user_pref("toolkit.telemetry.reportingpolicy.firstRun", false); + +user_pref("security.fileuri.strict_origin_policy", false); \ No newline at end of file diff --git a/rdl/outputs/docs/html/content/1211d8a8c3c9175e1c33719680affb67165e68d7.html b/rdl/outputs/docs/html/content/1211d8a8c3c9175e1c33719680affb67165e68d7.html new file mode 100644 index 0000000..74cafaa --- /dev/null +++ b/rdl/outputs/docs/html/content/1211d8a8c3c9175e1c33719680affb67165e68d7.html @@ -0,0 +1,70 @@ + + +
+

Tx async FIFO read and write pointers

+ + +
+
Absolute Address:
+
+
Base Offset:
0x90
+
Size:
0x4
+ +
Source:
msk_top_regs.rdl
+ +
+ +

Contents

+ + + + + + + + + + + + + + + + + + + +
BitsIdentifierAccessResetDecodedName
[31:0]data + rw0x0 + + + - + + +
+

+ +

+

Field Descriptions

+ +

data + +

+
+

Read and Write Pointers

+

Bits 31:16 - write pointer (12-bits)

+

Bits 15:00 - read pointer (12-bits)

+

This register is write-to-capture.

+

To read data the following steps are required:

+

1 - Write any value to this register to capture read data

+

2 - Read the register

+
+
\ No newline at end of file diff --git a/rdl/outputs/docs/html/content/1254c2cce678b196818b4f08e31bc15b1b3e6e8e.html b/rdl/outputs/docs/html/content/1254c2cce678b196818b4f08e31bc15b1b3e6e8e.html new file mode 100644 index 0000000..25659e1 --- /dev/null +++ b/rdl/outputs/docs/html/content/1254c2cce678b196818b4f08e31bc15b1b3e6e8e.html @@ -0,0 +1,95 @@ + + +
+

PI Controller Configuration Configuration Register 1

+ + +
+
Absolute Address:
+
+
Base Offset:
0x34
+
Size:
0x4
+ +
Source:
msk_top_regs.rdl
+ +
+

Description

+
+

Configures PI Controller I-gain and divisor

+
+ +

Contents

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsIdentifierAccessResetDecodedName
[31:24]i_shift + rw0x0 + + + Integral Gain Bit Shift + + +
[23:0]i_gain + rw0x0 + + + Integral Gain Value + + +
+

+ +

+

Field Descriptions

+ +

i_shift - Integral Gain Bit Shift + +

+
+

Value n of 0-32 sets the integral divisor as 2^-n

+
+ +

i_gain - Integral Gain Value + +

+
+

Value m of 0-16,777,215 sets the integral multiplier

+
+
\ No newline at end of file diff --git a/rdl/outputs/docs/html/content/14648ccc7797ab5a2e0a9ce250fc373fb5d1b044.html b/rdl/outputs/docs/html/content/14648ccc7797ab5a2e0a9ce250fc373fb5d1b044.html new file mode 100644 index 0000000..77b6e21 --- /dev/null +++ b/rdl/outputs/docs/html/content/14648ccc7797ab5a2e0a9ce250fc373fb5d1b044.html @@ -0,0 +1,72 @@ + + +
+

F2 PI Controller Accumulator

+ + +
+
Absolute Address:
+
+
Base Offset:
0x5c
+
Size:
0x4
+ +
Source:
msk_top_regs.rdl
+ +
+

Description

+
+

Value of the F2 PI Controller Accumulator

+
+ +

Contents

+ + + + + + + + + + + + + + + + + + + +
BitsIdentifierAccessResetDecodedName
[31:0]data + rw0x0 + + + PI Controller Accumulator Value + + +
+

+ +

+

Field Descriptions

+ +

data - PI Controller Accumulator Value + +

+
+

PI Controller Accumulator Value

+

This register is write-to-capture.

+

To read data the following steps are required:

+

1 - Write any value to this register to capture read data

+

2 - Read the register

+
+
\ No newline at end of file diff --git a/rdl/outputs/docs/html/content/181914803428de754127f501a151f8d9f2f6346f.html b/rdl/outputs/docs/html/content/181914803428de754127f501a151f8d9f2f6346f.html new file mode 100644 index 0000000..f88fad0 --- /dev/null +++ b/rdl/outputs/docs/html/content/181914803428de754127f501a151f8d9f2f6346f.html @@ -0,0 +1,77 @@ + + +
+

Modem Tx Input Data Width

+ + +
+
Absolute Address:
+
+
Base Offset:
0x38
+
Size:
0x4
+ +
Source:
msk_top_regs.rdl
+ +
+

Description

+
+

Set the parallel data width of the parallel-to-serial converter

+
+ +

Contents

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsIdentifierAccessResetDecodedName
[31:8]----
[7:0]data_width + rw0x8 + + + Modem input/output data width + + +
+

+ +

+

Field Descriptions

+ +

data_width - Modem input/output data width + +

+
+

Set the data width of the modem input/output

+
+
\ No newline at end of file diff --git a/rdl/outputs/docs/html/content/1e2385a5df67ff7f5d1fbfe621945563573fbb22.html b/rdl/outputs/docs/html/content/1e2385a5df67ff7f5d1fbfe621945563573fbb22.html new file mode 100644 index 0000000..1d7492d --- /dev/null +++ b/rdl/outputs/docs/html/content/1e2385a5df67ff7f5d1fbfe621945563573fbb22.html @@ -0,0 +1,69 @@ + + +
+

Bitrate NCO Frequency Control Word

+ + +
+
Absolute Address:
+
+
Base Offset:
0x1c
+
Size:
0x4
+ +
Source:
msk_top_regs.rdl
+ +
+

Description

+
+

Set Modem Data Rate

+
+ +

Contents

+ + + + + + + + + + + + + + + + + + + +
BitsIdentifierAccessResetDecodedName
[31:0]config_data + rw0x0 + + + Frequency Control Word + + +
+

+ +

+

Field Descriptions

+ +

config_data - Frequency Control Word + +

+
+

Sets the center frequency of the NCO as FW = Fn * 2^32/Fs, +where Fn is the desired NCO frequency, and Fs is the NCO sample rate

+
+
\ No newline at end of file diff --git a/rdl/outputs/docs/html/content/1e5eb9d33100e7486423224eec5450a659e2203c.html b/rdl/outputs/docs/html/content/1e5eb9d33100e7486423224eec5450a659e2203c.html new file mode 100644 index 0000000..c5617b5 --- /dev/null +++ b/rdl/outputs/docs/html/content/1e5eb9d33100e7486423224eec5450a659e2203c.html @@ -0,0 +1,68 @@ + + +
+

F1 Error Value

+ + +
+
Absolute Address:
+
+
Base Offset:
0x74
+
Size:
0x4
+ +
Source:
msk_top_regs.rdl
+ +
+ +

Contents

+ + + + + + + + + + + + + + + + + + + +
BitsIdentifierAccessResetDecodedName
[31:0]data + rw0x0 + + + - + + +
+

+ +

+

Field Descriptions

+ +

data + +

+
+

Error value of the F1 Costas loop after each active bit period

+

This register is write-to-capture.

+

To read data the following steps are required:

+

1 - Write any value to this register to capture read data

+

2 - Read the register

+
+
\ No newline at end of file diff --git a/rdl/outputs/docs/html/content/1fc360864d8b656cfa1ebcc20f12a51ba4f4f9cc.html b/rdl/outputs/docs/html/content/1fc360864d8b656cfa1ebcc20f12a51ba4f4f9cc.html new file mode 100644 index 0000000..6167fcd --- /dev/null +++ b/rdl/outputs/docs/html/content/1fc360864d8b656cfa1ebcc20f12a51ba4f4f9cc.html @@ -0,0 +1,201 @@ + + +
+

PRBS Control 0

+ + +
+
Absolute Address:
+
+
Base Offset:
0x40
+
Size:
0x4
+ +
Source:
msk_top_regs.rdl
+ +
+

Description

+
+

Configures operation of the PRBS Generator and Monitor

+
+ +

Contents

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsIdentifierAccessResetDecodedName
[31:16]prbs_sync_threshold + rw0x0 + + + PRBS Auto Sync Threshold + + +
[15:4]prbs_reserved + rw0x0 + + + Reserved + + +
[3]prbs_manual_sync + w0x0 + + + PRBS Manual Sync + + +
[2]prbs_clear + w0x0 + + + PRBS Clear Counters + + +
[1]prbs_error_insert + w0x0 + + + PRBS Error Insert + + +
[0]prbs_sel + rw0x0 + + + PRBS Data Select + + +
+

+ +

+

Field Descriptions

+ +

prbs_sync_threshold - PRBS Auto Sync Threshold + +

+
+

0 : Auto Sync Disabled

+

N > 0 : Auto sync after N errors

+
+ +

prbs_manual_sync - PRBS Manual Sync + +

+
+

0 -> 1 : Synchronize PRBS monitor

+

1 -> 0 : Synchronize PRBS monitor

+
+ +

prbs_clear - PRBS Clear Counters + +

+
+

0 -> 1 : Clear PRBS Counters

+

1 -> 0 : Clear PRBS Counters

+
+ +

prbs_error_insert - PRBS Error Insert + +

+
+

0 -> 1 : Insert bit error in Tx data (both Normal and PRBS)

+

1 -> 0 : Insert bit error in Tx data (both Normal and PRBS)

+
+ +

prbs_sel - PRBS Data Select + +

+
+

0 -> Select Normal Tx Data +1 -> Select PRBS Tx Data

+
+
\ No newline at end of file diff --git a/rdl/outputs/docs/html/content/263d902a6f30dcb8d14e261e3eb867f29ae8aa29.html b/rdl/outputs/docs/html/content/263d902a6f30dcb8d14e261e3eb867f29ae8aa29.html new file mode 100644 index 0000000..ac7d09d --- /dev/null +++ b/rdl/outputs/docs/html/content/263d902a6f30dcb8d14e261e3eb867f29ae8aa29.html @@ -0,0 +1,95 @@ + + +
+

PI Controller Configuration Configuration Register 2

+ + +
+
Absolute Address:
+
+
Base Offset:
0x68
+
Size:
0x4
+ +
Source:
msk_top_regs.rdl
+ +
+

Description

+
+

Configures PI Controller I-gain and divisor

+
+ +

Contents

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsIdentifierAccessResetDecodedName
[31:24]p_shift + rw0x0 + + + Proportional Gain Bit Shift + + +
[23:0]p_gain + rw0x0 + + + Proportional Gain Value + + +
+

+ +

+

Field Descriptions

+ +

p_shift - Proportional Gain Bit Shift + +

+
+

Value n of 0-32 sets the proportional divisor as 2^-n

+
+ +

p_gain - Proportional Gain Value + +

+
+

Value m of 0-16,777,215 sets the proportional multiplier

+
+
\ No newline at end of file diff --git a/rdl/outputs/docs/html/content/26afac861ad2452f8ace4d5f4459d66b2ead24dc.html b/rdl/outputs/docs/html/content/26afac861ad2452f8ace4d5f4459d66b2ead24dc.html new file mode 100644 index 0000000..0654293 --- /dev/null +++ b/rdl/outputs/docs/html/content/26afac861ad2452f8ace4d5f4459d66b2ead24dc.html @@ -0,0 +1,68 @@ + + +
+

F1 NCO Frequency Adjust

+ + +
+
Absolute Address:
+
+
Base Offset:
0x6c
+
Size:
0x4
+ +
Source:
msk_top_regs.rdl
+ +
+ +

Contents

+ + + + + + + + + + + + + + + + + + + +
BitsIdentifierAccessResetDecodedName
[31:0]data + rw0x0 + + + - + + +
+

+ +

+

Field Descriptions

+ +

data + +

+
+

Frequency offet applied to the F1 NCO

+

This register is write-to-capture.

+

To read data the following steps are required:

+

1 - Write any value to this register to capture read data

+

2 - Read the register

+
+
\ No newline at end of file diff --git a/rdl/outputs/docs/html/content/2b5b7862ddb3fa504d82685711c9a66bce7f577d.html b/rdl/outputs/docs/html/content/2b5b7862ddb3fa504d82685711c9a66bce7f577d.html new file mode 100644 index 0000000..85a5bfe --- /dev/null +++ b/rdl/outputs/docs/html/content/2b5b7862ddb3fa504d82685711c9a66bce7f577d.html @@ -0,0 +1,72 @@ + + +
+

MSK Modem Status 1

+ + +
+
Absolute Address:
+
+
Base Offset:
0x14
+
Size:
0x4
+ +
Source:
msk_top_regs.rdl
+ +
+

Description

+
+

Modem status data

+
+ +

Contents

+ + + + + + + + + + + + + + + + + + + +
BitsIdentifierAccessResetDecodedName
[31:0]data + rw0x0 + + + Tx Bit Count + + +
+

+ +

+

Field Descriptions

+ +

data - Tx Bit Count + +

+
+

Count of data requests made by modem

+

This register is write-to-capture.

+

To read data the following steps are required:

+

1 - Write any value to this register to capture read data

+

2 - Read the register

+
+
\ No newline at end of file diff --git a/rdl/outputs/docs/html/content/373508e257881c5e4a5502062b7c9aa9a792dc12.html b/rdl/outputs/docs/html/content/373508e257881c5e4a5502062b7c9aa9a792dc12.html new file mode 100644 index 0000000..872c0ab --- /dev/null +++ b/rdl/outputs/docs/html/content/373508e257881c5e4a5502062b7c9aa9a792dc12.html @@ -0,0 +1,68 @@ + + +
+

PRBS Control 3

+ + +
+
Absolute Address:
+
+
Base Offset:
0x4c
+
Size:
0x4
+ +
Source:
msk_top_regs.rdl
+ +
+

Description

+
+

PRBS Error Mask

+
+ +

Contents

+ + + + + + + + + + + + + + + + + + + +
BitsIdentifierAccessResetDecodedName
[31:0]config_data + rw0x0 + + + PRBS Error Mask + + +
+

+ +

+

Field Descriptions

+ +

config_data - PRBS Error Mask + +

+
+

Bit positions set to '1' indicate bits that are inverted when a bit error is inserted

+
+
\ No newline at end of file diff --git a/rdl/outputs/docs/html/content/38738d6efca727bb9bf39e13e872f922349ff15e.html b/rdl/outputs/docs/html/content/38738d6efca727bb9bf39e13e872f922349ff15e.html new file mode 100644 index 0000000..8813da8 --- /dev/null +++ b/rdl/outputs/docs/html/content/38738d6efca727bb9bf39e13e872f922349ff15e.html @@ -0,0 +1,68 @@ + + +
+

PRBS Control 1

+ + +
+
Absolute Address:
+
+
Base Offset:
0x44
+
Size:
0x4
+ +
Source:
msk_top_regs.rdl
+ +
+

Description

+
+

PRBS Initial State

+
+ +

Contents

+ + + + + + + + + + + + + + + + + + + +
BitsIdentifierAccessResetDecodedName
[31:0]config_data + rw0x0 + + + PRBS Seed + + +
+

+ +

+

Field Descriptions

+ +

config_data - PRBS Seed + +

+
+

Sets the starting value of the PRBS generator

+
+
\ No newline at end of file diff --git a/rdl/outputs/docs/html/content/4092c31237c70d2c50e8a1e8a25d3a13f9cec6a2.html b/rdl/outputs/docs/html/content/4092c31237c70d2c50e8a1e8a25d3a13f9cec6a2.html new file mode 100644 index 0000000..96a4a32 --- /dev/null +++ b/rdl/outputs/docs/html/content/4092c31237c70d2c50e8a1e8a25d3a13f9cec6a2.html @@ -0,0 +1,77 @@ + + +
+

Modem Rx Output Data Width

+ + +
+
Absolute Address:
+
+
Base Offset:
0x3c
+
Size:
0x4
+ +
Source:
msk_top_regs.rdl
+ +
+

Description

+
+

Set the parallel data width of the serial-to-parallel converter

+
+ +

Contents

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsIdentifierAccessResetDecodedName
[31:8]----
[7:0]data_width + rw0x8 + + + Modem input/output data width + + +
+

+ +

+

Field Descriptions

+ +

data_width - Modem input/output data width + +

+
+

Set the data width of the modem input/output

+
+
\ No newline at end of file diff --git a/rdl/outputs/docs/html/content/4f916507967fd003316096871c9cb43cb2983373.html b/rdl/outputs/docs/html/content/4f916507967fd003316096871c9cb43cb2983373.html new file mode 100644 index 0000000..6b97b33 --- /dev/null +++ b/rdl/outputs/docs/html/content/4f916507967fd003316096871c9cb43cb2983373.html @@ -0,0 +1,161 @@ + + +
+

MSK Modem Status 0

+ + +
+
Absolute Address:
+
+
Base Offset:
0x10
+
Size:
0x4
+ +
Source:
msk_top_regs.rdl
+ +
+

Description

+
+

Modem status bits

+
+ +

Contents

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsIdentifierAccessResetDecodedName
[31:4]----
[3]tx_axis_valid + r0x0 + + + Tx S_AXIS_VALID + + +
[2]rx_enable + r0x0 + + + AD9363 ADC Interface Rx Enable Input Active + + +
[1]tx_enable + r0x0 + + + AD9363 DAC Interface Tx Enable Input Active + + +
[0]demod_sync_lock + r0x0 + + + Demodulator Sync Status + + +
+

+ +

+

Field Descriptions

+ +

tx_axis_valid - Tx S_AXIS_VALID + +

+
+

1 -> S_AXIS_VALID Enabled

+

0 -> S_AXIS_VALID Disabled

+
+ +

rx_enable - AD9363 ADC Interface Rx Enable Input Active + +

+
+

1 -> Data from ADC Enabled

+

0 -> Data from ADC Disabled

+
+ +

tx_enable - AD9363 DAC Interface Tx Enable Input Active + +

+
+

1 -> Data to DAC Enabled

+

0 -> Data to DAC Disabled

+
+ +

demod_sync_lock - Demodulator Sync Status + +

+
+

Demodulator Sync Status - not currently implemented

+
+
\ No newline at end of file diff --git a/rdl/outputs/docs/html/content/54cea48e8d9edee01f284df7c443e2add40252d9.html b/rdl/outputs/docs/html/content/54cea48e8d9edee01f284df7c443e2add40252d9.html new file mode 100644 index 0000000..7120ffb --- /dev/null +++ b/rdl/outputs/docs/html/content/54cea48e8d9edee01f284df7c443e2add40252d9.html @@ -0,0 +1,189 @@ + + +
+

MSK Modem Control

+ + +
+
Absolute Address:
+
+
Base Offset:
0xc
+
Size:
0x4
+ +
Source:
msk_top_regs.rdl
+ +
+

Description

+
+

MSK Modem Configuration and Control

+
+ +

Contents

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsIdentifierAccessResetDecodedName
[31:5]----
[4]diff_encoder_loopback + rw0x0 + + + Differential Encoder -> Decoder Loopback Enable + + +
[3]clear_counts + rw0x0 + + + Clear Status Counters + + +
[2]rx_invert + rw0x0 + + + Rx Data Invert Enable + + +
[1]loopback_ena + rw0x0 + + + Modem Digital Tx -> Rx Loopback Enable + + +
[0]ptt + rw0x0 + + + Push-to-Talk Enable + + +
+

+ +

+

Field Descriptions

+ +

diff_encoder_loopback - Differential Encoder -> Decoder Loopback Enable + +

+
+

0 -> Differential Encoder -> Decoder loopback disabled

+

1 -> Differential Encoder -> Decoder loopback enabled

+
+ +

clear_counts - Clear Status Counters + +

+
+

Clear Tx Bit Counter and Tx Enable Counter

+
+ +

rx_invert - Rx Data Invert Enable + +

+
+

0 -> Rx data normal +1 -> Rx data inverted

+
+ +

loopback_ena - Modem Digital Tx -> Rx Loopback Enable + +

+
+

0 -> Modem loopback disabled

+

1 -> Modem loopback enabled

+
+ +

ptt - Push-to-Talk Enable + +

+
+

0 -> PTT Disabled +1 -> PTT Enabled

+
+
\ No newline at end of file diff --git a/rdl/outputs/docs/html/content/611b0a3a62ae385442fa3b250263026f7cfdd441.html b/rdl/outputs/docs/html/content/611b0a3a62ae385442fa3b250263026f7cfdd441.html new file mode 100644 index 0000000..019e6eb --- /dev/null +++ b/rdl/outputs/docs/html/content/611b0a3a62ae385442fa3b250263026f7cfdd441.html @@ -0,0 +1,72 @@ + + +
+

MSK Modem Status 2

+ + +
+
Absolute Address:
+
+
Base Offset:
0x18
+
Size:
0x4
+ +
Source:
msk_top_regs.rdl
+ +
+

Description

+
+

Modem status data

+
+ +

Contents

+ + + + + + + + + + + + + + + + + + + +
BitsIdentifierAccessResetDecodedName
[31:0]data + rw0x0 + + + Tx Enable Count + + +
+

+ +

+

Field Descriptions

+ +

data - Tx Enable Count + +

+
+

Number of clocks on which Tx Enable is active

+

This register is write-to-capture.

+

To read data the following steps are required:

+

1 - Write any value to this register to capture read data

+

2 - Read the register

+
+
\ No newline at end of file diff --git a/rdl/outputs/docs/html/content/611d75d5fc9168e025083358f26a5e06ca7b3007.html b/rdl/outputs/docs/html/content/611d75d5fc9168e025083358f26a5e06ca7b3007.html new file mode 100644 index 0000000..7fc73be --- /dev/null +++ b/rdl/outputs/docs/html/content/611d75d5fc9168e025083358f26a5e06ca7b3007.html @@ -0,0 +1,144 @@ + + +
+

PI Controller Configuration and Low-pass Filter Configuration

+ + +
+
Absolute Address:
+
+
Base Offset:
0x30
+
Size:
0x4
+ +
Source:
msk_top_regs.rdl
+ +
+

Description

+
+

Configure PI controller and low-pass filter

+
+ +

Contents

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsIdentifierAccessResetDecodedName
[31:8]lpf_alpha + rw0x0 + + + Lowpass IIR filter alpha + + +
[7:2]prbs_reserved + rw0x0 + + + Reserved + + +
[1]lpf_zero + rw0x0 + + + Hold the PI Accumulator at zero + + +
[0]lpf_freeze + rw0x0 + + + Freeze the accumulator's current value + + +
+

+ +

+

Field Descriptions

+ +

lpf_alpha - Lowpass IIR filter alpha + +

+
+

Value controls the filter rolloff

+
+ +

lpf_zero - Hold the PI Accumulator at zero + +

+
+

0 -> Normal operation

+

1 -> Zero and hold accumulator

+
+ +

lpf_freeze - Freeze the accumulator's current value + +

+
+

0 -> Normal operation

+

1 -> Freeze current value

+
+
\ No newline at end of file diff --git a/rdl/outputs/docs/html/content/6a1cea7d8db3cfd91d0b598d43abc73b85b237e5.html b/rdl/outputs/docs/html/content/6a1cea7d8db3cfd91d0b598d43abc73b85b237e5.html new file mode 100644 index 0000000..c45c2e1 --- /dev/null +++ b/rdl/outputs/docs/html/content/6a1cea7d8db3cfd91d0b598d43abc73b85b237e5.html @@ -0,0 +1,64 @@ + + +
+

Pluto MSK FPGA Hash ID - Lower 32-bits

+ + +
+
Absolute Address:
+
+
Base Offset:
0x0
+
Size:
0x4
+ +
Source:
msk_top_regs.rdl
+ +
+ +

Contents

+ + + + + + + + + + + + + + + + + + + +
BitsIdentifierAccessResetDecodedName
[31:0]hash_id_lo + r0xaaaa5555 + + + Hash ID Lower 32-bits + + +
+

+ +

+

Field Descriptions

+ +

hash_id_lo - Hash ID Lower 32-bits + +

+
+

Lower 32-bits of Pluto MSK FPGA Hash ID

+
+
\ No newline at end of file diff --git a/rdl/outputs/docs/html/content/766520c9b6891107c7d1b147a3b1bed28bebe71c.html b/rdl/outputs/docs/html/content/766520c9b6891107c7d1b147a3b1bed28bebe71c.html new file mode 100644 index 0000000..fb34eaf --- /dev/null +++ b/rdl/outputs/docs/html/content/766520c9b6891107c7d1b147a3b1bed28bebe71c.html @@ -0,0 +1,73 @@ + + +
+

PRBS Status 0

+ + +
+
Absolute Address:
+
+
Base Offset:
0x50
+
Size:
0x4
+ +
Source:
msk_top_regs.rdl
+ +
+

Description

+
+

PRBS Bits Received

+
+ +

Contents

+ + + + + + + + + + + + + + + + + + + +
BitsIdentifierAccessResetDecodedName
[31:0]data + rw0x0 + + + PRBS Bits Received + + +
+

+ +

+

Field Descriptions

+ +

data - PRBS Bits Received + +

+
+

Number of bits received by the PRBS monitor since last +BER can be calculated as the ratio of received bits to errored-bits

+

This register is write-to-capture.

+

To read data the following steps are required:

+

1 - Write any value to this register to capture read data

+

2 - Read the register

+
+
\ No newline at end of file diff --git a/rdl/outputs/docs/html/content/8341423b7e011932aacabd59a183a4c2d7c81b46.html b/rdl/outputs/docs/html/content/8341423b7e011932aacabd59a183a4c2d7c81b46.html new file mode 100644 index 0000000..87df749 --- /dev/null +++ b/rdl/outputs/docs/html/content/8341423b7e011932aacabd59a183a4c2d7c81b46.html @@ -0,0 +1,69 @@ + + +
+

Rx F1 NCO Frequency Control Word

+ + +
+
Absolute Address:
+
+
Base Offset:
0x28
+
Size:
0x4
+ +
Source:
msk_top_regs.rdl
+ +
+

Description

+
+

Set Demodulator F1 Frequency

+
+ +

Contents

+ + + + + + + + + + + + + + + + + + + +
BitsIdentifierAccessResetDecodedName
[31:0]config_data + rw0x0 + + + Frequency Control Word + + +
+

+ +

+

Field Descriptions

+ +

config_data - Frequency Control Word + +

+
+

Sets the center frequency of the NCO as FW = Fn * 2^32/Fs, +where Fn is the desired NCO frequency, and Fs is the NCO sample rate

+
+
\ No newline at end of file diff --git a/rdl/outputs/docs/html/content/aaa99b88ab61eb3569764525c3aef19596c2a4e8.html b/rdl/outputs/docs/html/content/aaa99b88ab61eb3569764525c3aef19596c2a4e8.html new file mode 100644 index 0000000..fbe5ace --- /dev/null +++ b/rdl/outputs/docs/html/content/aaa99b88ab61eb3569764525c3aef19596c2a4e8.html @@ -0,0 +1,72 @@ + + +
+

MSK Modem Status 3

+ + +
+
Absolute Address:
+
+
Base Offset:
0x60
+
Size:
0x4
+ +
Source:
msk_top_regs.rdl
+ +
+

Description

+
+

Modem status data

+
+ +

Contents

+ + + + + + + + + + + + + + + + + + + +
BitsIdentifierAccessResetDecodedName
[31:0]data + rw0x0 + + + S_AXIS Transfers + + +
+

+ +

+

Field Descriptions

+ +

data - S_AXIS Transfers + +

+
+

Number completed S_AXIS transfers

+

This register is write-to-capture.

+

To read data the following steps are required:

+

1 - Write any value to this register to capture read data

+

2 - Read the register

+
+
\ No newline at end of file diff --git a/rdl/outputs/docs/html/content/aab8d61e4e2c8cc1adaabca728671903515e6053.html b/rdl/outputs/docs/html/content/aab8d61e4e2c8cc1adaabca728671903515e6053.html new file mode 100644 index 0000000..77463d4 --- /dev/null +++ b/rdl/outputs/docs/html/content/aab8d61e4e2c8cc1adaabca728671903515e6053.html @@ -0,0 +1,69 @@ + + +
+

Tx F1 NCO Frequency Control Word

+ + +
+
Absolute Address:
+
+
Base Offset:
0x20
+
Size:
0x4
+ +
Source:
msk_top_regs.rdl
+ +
+

Description

+
+

Set Modulator F1 Frequency

+
+ +

Contents

+ + + + + + + + + + + + + + + + + + + +
BitsIdentifierAccessResetDecodedName
[31:0]config_data + rw0x0 + + + Frequency Control Word + + +
+

+ +

+

Field Descriptions

+ +

config_data - Frequency Control Word + +

+
+

Sets the center frequency of the NCO as FW = Fn * 2^32/Fs, +where Fn is the desired NCO frequency, and Fs is the NCO sample rate

+
+
\ No newline at end of file diff --git a/rdl/outputs/docs/html/content/b4c18df4e6a7993047f37ec6f74d05dae744e911.html b/rdl/outputs/docs/html/content/b4c18df4e6a7993047f37ec6f74d05dae744e911.html new file mode 100644 index 0000000..c615bf7 --- /dev/null +++ b/rdl/outputs/docs/html/content/b4c18df4e6a7993047f37ec6f74d05dae744e911.html @@ -0,0 +1,335 @@ + + +
+

Pluto MSK Registers

+ + +
+
Absolute Address:
+
+
Base Offset:
0x0
+
Size:
0x98
+ +
Source:
msk_top_regs.rdl
+ +
+

Description

+
+

MSK Modem Configuration and Status Registers

+
+ +

Contents

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
OffsetIdentifierName
0x00Hash_ID_LowPluto MSK FPGA Hash ID - Lower 32-bits + +
0x04Hash_ID_HighPluto MSK FPGA Hash ID - Upper 32-bits + +
0x08MSK_InitMSK Modem Initialization Control + +
0x0CMSK_ControlMSK Modem Control + +
0x10MSK_StatusMSK Modem Status 0 + +
0x14Tx_Bit_CountMSK Modem Status 1 + +
0x18Tx_Enable_CountMSK Modem Status 2 + +
0x1CFb_FreqWordBitrate NCO Frequency Control Word + +
0x20TX_F1_FreqWordTx F1 NCO Frequency Control Word + +
0x24TX_F2_FreqWordTx F2 NCO Frequency Control Word + +
0x28RX_F1_FreqWordRx F1 NCO Frequency Control Word + +
0x2CRX_F2_FreqWordRx F2 NCO Frequency Control Word + +
0x30LPF_Config_0PI Controller Configuration and Low-pass Filter Configuration + +
0x34LPF_Config_1PI Controller Configuration Configuration Register 1 + +
0x38Tx_Data_WidthModem Tx Input Data Width + +
0x3CRx_Data_WidthModem Rx Output Data Width + +
0x40PRBS_ControlPRBS Control 0 + +
0x44PRBS_Initial_StatePRBS Control 1 + +
0x48PRBS_PolynomialPRBS Control 2 + +
0x4CPRBS_Error_MaskPRBS Control 3 + +
0x50PRBS_Bit_CountPRBS Status 0 + +
0x54PRBS_Error_CountPRBS Status 1 + +
0x58LPF_Accum_F1F1 PI Controller Accumulator + +
0x5CLPF_Accum_F2F2 PI Controller Accumulator + +
0x60axis_xfer_countMSK Modem Status 3 + +
0x64Rx_Sample_DiscardRx Sample Discard + +
0x68LPF_Config_2PI Controller Configuration Configuration Register 2 + +
0x6Cf1_nco_adjustF1 NCO Frequency Adjust + +
0x70f2_nco_adjustF2 NCO Frequency Adjust + +
0x74f1_errorF1 Error Value + +
0x78f2_errorF2 Error Value + +
0x7CTx_Sync_CtrlTransmitter Sync Control + +
0x80Tx_Sync_CntTransmitter Sync Duration + +
0x84lowpass_ema_alpha1Exponential Moving Average Alpha + +
0x88lowpass_ema_alpha2Exponential Moving Average Alpha + +
0x8Crx_powerReceive Power + +
0x90tx_async_fifo_rd_wr_ptrTx async FIFO read and write pointers + +
0x94rx_async_fifo_rd_wr_ptrRx async FIFO read and write pointers + +
+
\ No newline at end of file diff --git a/rdl/outputs/docs/html/content/b54cac1ec3dda403a0b7a1db5c224b03a74f9f9d.html b/rdl/outputs/docs/html/content/b54cac1ec3dda403a0b7a1db5c224b03a74f9f9d.html new file mode 100644 index 0000000..403a6e7 --- /dev/null +++ b/rdl/outputs/docs/html/content/b54cac1ec3dda403a0b7a1db5c224b03a74f9f9d.html @@ -0,0 +1,81 @@ + + +
+

Receive Power

+ + +
+
Absolute Address:
+
+
Base Offset:
0x8c
+
Size:
0x4
+ +
Source:
msk_top_regs.rdl
+ +
+

Description

+
+

Receive power computed from I/Q ssamples

+
+ +

Contents

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsIdentifierAccessResetDecodedName
[31:23]----
[22:0]data + rw0x0 + + + Receive Power + + +
+

+ +

+

Field Descriptions

+ +

data - Receive Power + +

+
+

Value that represent the RMS power of the incoming I

+

This register is write-to-capture.

+

To read data the following steps are required:

+

1 - Write any value to this register to capture read data

+

2 - Read the register

+
+
\ No newline at end of file diff --git a/rdl/outputs/docs/html/content/b60627ebae54f7207a648572a54cbd7f918c0ae7.html b/rdl/outputs/docs/html/content/b60627ebae54f7207a648572a54cbd7f918c0ae7.html new file mode 100644 index 0000000..ae7e2a5 --- /dev/null +++ b/rdl/outputs/docs/html/content/b60627ebae54f7207a648572a54cbd7f918c0ae7.html @@ -0,0 +1,68 @@ + + +
+

F2 Error Value

+ + +
+
Absolute Address:
+
+
Base Offset:
0x78
+
Size:
0x4
+ +
Source:
msk_top_regs.rdl
+ +
+ +

Contents

+ + + + + + + + + + + + + + + + + + + +
BitsIdentifierAccessResetDecodedName
[31:0]data + rw0x0 + + + - + + +
+

+ +

+

Field Descriptions

+ +

data + +

+
+

Error value of the F2 Costas loop after each active bit period

+

This register is write-to-capture.

+

To read data the following steps are required:

+

1 - Write any value to this register to capture read data

+

2 - Read the register

+
+
\ No newline at end of file diff --git a/rdl/outputs/docs/html/content/b883348faf8a0f9a3da26ea0fc3d9e8d47d5d737.html b/rdl/outputs/docs/html/content/b883348faf8a0f9a3da26ea0fc3d9e8d47d5d737.html new file mode 100644 index 0000000..421d85f --- /dev/null +++ b/rdl/outputs/docs/html/content/b883348faf8a0f9a3da26ea0fc3d9e8d47d5d737.html @@ -0,0 +1,69 @@ + + +
+

Tx F2 NCO Frequency Control Word

+ + +
+
Absolute Address:
+
+
Base Offset:
0x24
+
Size:
0x4
+ +
Source:
msk_top_regs.rdl
+ +
+

Description

+
+

Set Modulator F2 Frequency

+
+ +

Contents

+ + + + + + + + + + + + + + + + + + + +
BitsIdentifierAccessResetDecodedName
[31:0]config_data + rw0x0 + + + Frequency Control Word + + +
+

+ +

+

Field Descriptions

+ +

config_data - Frequency Control Word + +

+
+

Sets the center frequency of the NCO as FW = Fn * 2^32/Fs, +where Fn is the desired NCO frequency, and Fs is the NCO sample rate

+
+
\ No newline at end of file diff --git a/rdl/outputs/docs/html/content/c3a0e44e2c6ffcbb57715d4fc6fd621eca17bbe9.html b/rdl/outputs/docs/html/content/c3a0e44e2c6ffcbb57715d4fc6fd621eca17bbe9.html new file mode 100644 index 0000000..c5a4feb --- /dev/null +++ b/rdl/outputs/docs/html/content/c3a0e44e2c6ffcbb57715d4fc6fd621eca17bbe9.html @@ -0,0 +1,166 @@ + + +
+

Transmitter Sync Control

+ + +
+
Absolute Address:
+
+
Base Offset:
0x7c
+
Size:
0x4
+ +
Source:
msk_top_regs.rdl
+ +
+

Description

+
+

Provides control bits for generation of transmitter synchronization patterns

+
+ +

Contents

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsIdentifierAccessResetDecodedName
[31:4]----
[3]tx_sync_f2 + rw0x0 + + + Tx F2 Sync Enable + + +
[2]tx_sync_f1 + rw0x0 + + + Tx F1 Sync Enable + + +
[1]tx_sync_force + rw0x0 + + + Tx Sync Force + + +
[0]tx_sync_ena + rw0x0 + + + Tx Sync Enable + + +
+

+ +

+

Field Descriptions

+ +

tx_sync_f2 - Tx F2 Sync Enable + +

+
+

Enables/Disables transmission of F2 tone for receiver synchronization +0 : F2 tone transmission disabled

+

1 : F2 tone transmission enabled

+

Both F1 and F2 can be enabled at the same time

+
+ +

tx_sync_f1 - Tx F1 Sync Enable + +

+
+

Enables/Disables transmission of F1 tone for receiver synchronization +0 : F1 tone transmission disabled

+

1 : F1 tone transmission enabled

+

Both F1 and F2 can be enabled at the same time

+
+ +

tx_sync_force - Tx Sync Force + +

+
+

0 : Normal operation

+

1 : Transmit synchronization pattern

+
+ +

tx_sync_ena - Tx Sync Enable + +

+
+

0 -> Disable sync transmission

+

1 -> Enable sync transmission when PTT is asserted

+
+
\ No newline at end of file diff --git a/rdl/outputs/docs/html/content/cc5ab06a84343db43279a768a29160c012ea8fcc.html b/rdl/outputs/docs/html/content/cc5ab06a84343db43279a768a29160c012ea8fcc.html new file mode 100644 index 0000000..8ad2a8b --- /dev/null +++ b/rdl/outputs/docs/html/content/cc5ab06a84343db43279a768a29160c012ea8fcc.html @@ -0,0 +1,134 @@ + + +
+

MSK Modem Initialization Control

+ + +
+
Absolute Address:
+
+
Base Offset:
0x8
+
Size:
0x4
+ +
Source:
msk_top_regs.rdl
+ +
+

Description

+
+

Synchronous initialization of MSK Modem functions, does not affect configuration registers.

+
+ +

Contents

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsIdentifierAccessResetDecodedName
[31:3]----
[2]rxinit + rw0x1 + + + Rx Init Enable + + +
[1]txinit + rw0x1 + + + Tx Init Enable + + +
[0]txrxinit + rw0x1 + + + Tx/Rx Init Enable + + +
+

+ +

+

Field Descriptions

+ +

rxinit - Rx Init Enable + +

+
+

0 -> Normal Rx operation

+

1 -> Initialize Rx

+
+ +

txinit - Tx Init Enable + +

+
+

0 -> Normal Tx operation

+

1 -> Initialize Tx

+
+ +

txrxinit - Tx/Rx Init Enable + +

+
+

0 -> Normal modem operation

+

1 -> Initialize Tx and Rx

+
+
\ No newline at end of file diff --git a/rdl/outputs/docs/html/content/ce06e4ec8a024a37ce1f65c5c90a495b4b9555cf.html b/rdl/outputs/docs/html/content/ce06e4ec8a024a37ce1f65c5c90a495b4b9555cf.html new file mode 100644 index 0000000..4392053 --- /dev/null +++ b/rdl/outputs/docs/html/content/ce06e4ec8a024a37ce1f65c5c90a495b4b9555cf.html @@ -0,0 +1,68 @@ + + +
+

F2 NCO Frequency Adjust

+ + +
+
Absolute Address:
+
+
Base Offset:
0x70
+
Size:
0x4
+ +
Source:
msk_top_regs.rdl
+ +
+ +

Contents

+ + + + + + + + + + + + + + + + + + + +
BitsIdentifierAccessResetDecodedName
[31:0]data + rw0x0 + + + - + + +
+

+ +

+

Field Descriptions

+ +

data + +

+
+

Frequency offet applied to the F2 NCO

+

This register is write-to-capture.

+

To read data the following steps are required:

+

1 - Write any value to this register to capture read data

+

2 - Read the register

+
+
\ No newline at end of file diff --git a/rdl/outputs/docs/html/content/d4cb92fc9fcd9a12ab08ab5d411dbc399e12cb62.html b/rdl/outputs/docs/html/content/d4cb92fc9fcd9a12ab08ab5d411dbc399e12cb62.html new file mode 100644 index 0000000..6712c3d --- /dev/null +++ b/rdl/outputs/docs/html/content/d4cb92fc9fcd9a12ab08ab5d411dbc399e12cb62.html @@ -0,0 +1,68 @@ + + +
+

PRBS Control 2

+ + +
+
Absolute Address:
+
+
Base Offset:
0x48
+
Size:
0x4
+ +
Source:
msk_top_regs.rdl
+ +
+

Description

+
+

PRBS Polynomial

+
+ +

Contents

+ + + + + + + + + + + + + + + + + + + +
BitsIdentifierAccessResetDecodedName
[31:0]config_data + rw0x0 + + + PRBS Polynomial + + +
+

+ +

+

Field Descriptions

+ +

config_data - PRBS Polynomial + +

+
+

Bit positions set to '1' indicate polynomial feedback positions

+
+
\ No newline at end of file diff --git a/rdl/outputs/docs/html/content/db8d99c8aadce2aee57600cd3b0212da9c9972cf.html b/rdl/outputs/docs/html/content/db8d99c8aadce2aee57600cd3b0212da9c9972cf.html new file mode 100644 index 0000000..5fdcba9 --- /dev/null +++ b/rdl/outputs/docs/html/content/db8d99c8aadce2aee57600cd3b0212da9c9972cf.html @@ -0,0 +1,64 @@ + + +
+

Pluto MSK FPGA Hash ID - Upper 32-bits

+ + +
+
Absolute Address:
+
+
Base Offset:
0x4
+
Size:
0x4
+ +
Source:
msk_top_regs.rdl
+ +
+ +

Contents

+ + + + + + + + + + + + + + + + + + + +
BitsIdentifierAccessResetDecodedName
[31:0]hash_id_hi + r0x5555aaaa + + + Hash ID Upper 32-bits + + +
+

+ +

+

Field Descriptions

+ +

hash_id_hi - Hash ID Upper 32-bits + +

+
+

Upper 32-bits of Pluto MSK FPGA Hash ID

+
+
\ No newline at end of file diff --git a/rdl/outputs/docs/html/content/dbb506c578ba1e4bb6eaf4767617cd58beb4a3ae.html b/rdl/outputs/docs/html/content/dbb506c578ba1e4bb6eaf4767617cd58beb4a3ae.html new file mode 100644 index 0000000..950a4f9 --- /dev/null +++ b/rdl/outputs/docs/html/content/dbb506c578ba1e4bb6eaf4767617cd58beb4a3ae.html @@ -0,0 +1,79 @@ + + +
+

Transmitter Sync Duration

+ + +
+
Absolute Address:
+
+
Base Offset:
0x80
+
Size:
0x4
+ +
Source:
msk_top_regs.rdl
+ +
+

Description

+
+

Sets the duration of the synchronization tones when enabled

+
+ +

Contents

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsIdentifierAccessResetDecodedName
[31:24]----
[23:0]tx_sync_cnt + rw0x0 + + + Tx sync duration + + +
+

+ +

+

Field Descriptions

+ +

tx_sync_cnt - Tx sync duration + +

+
+

Value from 0x00_0000 to 0xFF_FFFF.

+

This value represents the number bit-times the synchronization

+

signal should be sent after PTT is asserted.

+
+
\ No newline at end of file diff --git a/rdl/outputs/docs/html/content/e3c786425f5920f3a1e885e740599831cfd792bc.html b/rdl/outputs/docs/html/content/e3c786425f5920f3a1e885e740599831cfd792bc.html new file mode 100644 index 0000000..39c2ab1 --- /dev/null +++ b/rdl/outputs/docs/html/content/e3c786425f5920f3a1e885e740599831cfd792bc.html @@ -0,0 +1,72 @@ + + +
+

Rx async FIFO read and write pointers

+ + +
+
Absolute Address:
+
+
Base Offset:
0x94
+
Size:
0x4
+ +
Source:
msk_top_regs.rdl
+ +
+ +

Contents

+ + + + + + + + + + + + + + + + + + + +
BitsIdentifierAccessResetDecodedName
[31:0]data + rw0x0 + + + - + + +
+

+ +

+

Field Descriptions

+ +

data + +

+
+

Read and Write Pointers

+

+Bits 31:16 - write pointer (12-bits)

+

Bits 15:00 - read pointer (12-bits)

+

This register is write-to-capture. To read data the following steps are required:

+
    +
  • Write any value to this register to capture read data
    +
  • Read the register +
+
+
\ No newline at end of file diff --git a/rdl/outputs/docs/html/content/e41b7c226a4ebc36be166e4a2b523cb2a8959870.html b/rdl/outputs/docs/html/content/e41b7c226a4ebc36be166e4a2b523cb2a8959870.html new file mode 100644 index 0000000..bb4822e --- /dev/null +++ b/rdl/outputs/docs/html/content/e41b7c226a4ebc36be166e4a2b523cb2a8959870.html @@ -0,0 +1,104 @@ + + +
+

Rx Sample Discard

+ + +
+
Absolute Address:
+
+
Base Offset:
0x64
+
Size:
0x4
+ +
Source:
msk_top_regs.rdl
+ +
+

Description

+
+

Configure samples discard operation for demodulator

+
+ +

Contents

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsIdentifierAccessResetDecodedName
[31:16]----
[15:8]rx_nco_discard + rw0x0 + + + Rx NCO Sample Discard Value + + +
[7:0]rx_sample_discard + rw0x0 + + + Rx Sample Discard Value + + +
+

+ +

+

Field Descriptions

+ +

rx_nco_discard - Rx NCO Sample Discard Value + +

+
+

Number of NCO samples to discard

+
+ +

rx_sample_discard - Rx Sample Discard Value + +

+
+

Number of Rx samples to discard

+
+
\ No newline at end of file diff --git a/rdl/outputs/docs/html/content/eca580c1f1dcded555681dfd8a6e15e379cf5f0f.html b/rdl/outputs/docs/html/content/eca580c1f1dcded555681dfd8a6e15e379cf5f0f.html new file mode 100644 index 0000000..2688b8b --- /dev/null +++ b/rdl/outputs/docs/html/content/eca580c1f1dcded555681dfd8a6e15e379cf5f0f.html @@ -0,0 +1,72 @@ + + +
+

F1 PI Controller Accumulator

+ + +
+
Absolute Address:
+
+
Base Offset:
0x58
+
Size:
0x4
+ +
Source:
msk_top_regs.rdl
+ +
+

Description

+
+

Value of the F1 PI Controller Accumulator

+
+ +

Contents

+ + + + + + + + + + + + + + + + + + + +
BitsIdentifierAccessResetDecodedName
[31:0]data + rw0x0 + + + PI Controller Accumulator Value + + +
+

+ +

+

Field Descriptions

+ +

data - PI Controller Accumulator Value + +

+
+

PI Controller Accumulator Value

+

This register is write-to-capture.

+

To read data the following steps are required:

+

1 - Write any value to this register to capture read data

+

2 - Read the register

+
+
\ No newline at end of file diff --git a/rdl/outputs/docs/html/content/ee57807489e9b5f5b719044911537b66b3a06bdf.html b/rdl/outputs/docs/html/content/ee57807489e9b5f5b719044911537b66b3a06bdf.html new file mode 100644 index 0000000..bb881fd --- /dev/null +++ b/rdl/outputs/docs/html/content/ee57807489e9b5f5b719044911537b66b3a06bdf.html @@ -0,0 +1,77 @@ + + +
+

Exponential Moving Average Alpha

+ + +
+
Absolute Address:
+
+
Base Offset:
0x88
+
Size:
0x4
+ +
Source:
msk_top_regs.rdl
+ +
+

Description

+
+

Sets the alpha for the EMA

+
+ +

Contents

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsIdentifierAccessResetDecodedName
[31:18]----
[17:0]alpha + rw0x0 + + + EMA alpha + + +
+

+ +

+

Field Descriptions

+ +

alpha - EMA alpha + +

+
+

Value from 0x0_0000 to 0x3_FFFF represent the EMA alpha

+
+
\ No newline at end of file diff --git a/rdl/outputs/docs/html/content/f439a6888cc769d718b5d38d555e7aed6b422371.html b/rdl/outputs/docs/html/content/f439a6888cc769d718b5d38d555e7aed6b422371.html new file mode 100644 index 0000000..1512d5a --- /dev/null +++ b/rdl/outputs/docs/html/content/f439a6888cc769d718b5d38d555e7aed6b422371.html @@ -0,0 +1,77 @@ + + +
+

Exponential Moving Average Alpha

+ + +
+
Absolute Address:
+
+
Base Offset:
0x84
+
Size:
0x4
+ +
Source:
msk_top_regs.rdl
+ +
+

Description

+
+

Sets the alpha for the EMA

+
+ +

Contents

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsIdentifierAccessResetDecodedName
[31:18]----
[17:0]alpha + rw0x0 + + + EMA alpha + + +
+

+ +

+

Field Descriptions

+ +

alpha - EMA alpha + +

+
+

Value from 0x0_0000 to 0x3_FFFF represent the EMA alpha

+
+
\ No newline at end of file diff --git a/rdl/outputs/docs/html/content/f7daaf8ea45f55844cf66da35a46142d55a5253a.html b/rdl/outputs/docs/html/content/f7daaf8ea45f55844cf66da35a46142d55a5253a.html new file mode 100644 index 0000000..d3e7289 --- /dev/null +++ b/rdl/outputs/docs/html/content/f7daaf8ea45f55844cf66da35a46142d55a5253a.html @@ -0,0 +1,69 @@ + + +
+

Rx F2 NCO Frequency Control Word

+ + +
+
Absolute Address:
+
+
Base Offset:
0x2c
+
Size:
0x4
+ +
Source:
msk_top_regs.rdl
+ +
+

Description

+
+

Set Demodulator F2 Frequency

+
+ +

Contents

+ + + + + + + + + + + + + + + + + + + +
BitsIdentifierAccessResetDecodedName
[31:0]config_data + rw0x0 + + + Frequency Control Word + + +
+

+ +

+

Field Descriptions

+ +

config_data - Frequency Control Word + +

+
+

Sets the center frequency of the NCO as FW = Fn * 2^32/Fs, +where Fn is the desired NCO frequency, and Fs is the NCO sample rate

+
+
\ No newline at end of file diff --git a/rdl/outputs/docs/html/content/fd9b9e9189271b3cac659475d0b7621c0ffe0c3f.html b/rdl/outputs/docs/html/content/fd9b9e9189271b3cac659475d0b7621c0ffe0c3f.html new file mode 100644 index 0000000..c4eddb0 --- /dev/null +++ b/rdl/outputs/docs/html/content/fd9b9e9189271b3cac659475d0b7621c0ffe0c3f.html @@ -0,0 +1,73 @@ + + +
+

PRBS Status 1

+ + +
+
Absolute Address:
+
+
Base Offset:
0x54
+
Size:
0x4
+ +
Source:
msk_top_regs.rdl
+ +
+

Description

+
+

PRBS Bit Errors

+
+ +

Contents

+ + + + + + + + + + + + + + + + + + + +
BitsIdentifierAccessResetDecodedName
[31:0]data + rw0x0 + + + PRBS Bit Errors + + +
+

+ +

+

Field Descriptions

+ +

data - PRBS Bit Errors + +

+
+

Number of errored-bits received by the PRBS monitor since last sync +BER can be calculated as the ratio of received bits to errored-bits

+

This register is write-to-capture.

+

To read data the following steps are required:

+

1 - Write any value to this register to capture read data

+

2 - Read the register

+
+
\ No newline at end of file diff --git a/rdl/outputs/docs/html/css/layout.css b/rdl/outputs/docs/html/css/layout.css new file mode 100644 index 0000000..59ab518 --- /dev/null +++ b/rdl/outputs/docs/html/css/layout.css @@ -0,0 +1,209 @@ +/* This file is part of PeakRDL-html . + * and can be redistributed under the terms of GNU GPL v3 . + */ + +/* Base layout */ +html, body { + height: 100%; +} + +button { + cursor: pointer; +} + +img { + max-width: 100%; +} + +#_Sidebar { + height: 100%; +} + +#_SBContents { + width: 19em; + min-width: 19em !important; +} + +#_SBResizer { + width: 6px; + margin-left: -3px; + margin-right: -3px; + cursor: col-resize; +} + +#MainPane { + height: 100%; +} + +#_SBTreeContainer { + display: flex; + flex-direction: column; +} +#_SBTree { + display: inline-flex; + flex-direction: column; + min-width: max-content; +} + +.node { + flex-direction: row; + display: flex; + flex-shrink: 0; +} +.node-link { + flex-grow: 1; +} + +.node-icon { + flex-grow: 0; + flex-shrink: 0; +} + +.node-children { + padding-left: 1em; + display: inline-flex; + flex-direction: column; + min-width: max-content; +} + +.pack-v { + display: flex; + flex-direction: column; +} + +.pack-h { + display: flex; + flex-direction: row; +} + +.scroll-v { + overflow-y: auto; +} + +.scroll-h { + overflow-x: auto; +} + +.stretchy { + flex-grow: 1; + flex-shrink: 1; +} + +.no-stretchy { + flex-grow: 0; + flex-shrink: 0; +} + +#_Overlay { + width: 100%; + height: 100%; + position:absolute; + display:none; + z-index: 2; + cursor:pointer; +} + +#_IdxEditModal { + display: none; /* Hidden by default */ + position: fixed; + z-index: 1; + left: 18.75em; + top: 18.75em; + + padding: 0.625em; +} + +/* arrow thingy on top of modal */ +#_IdxEditModal::before { + content: ""; + width: 0em; + height: 0em; + position: absolute; + left: 2.188em; /* = ([input with] + [modal padding]*2)/2 - [this border_width] */ + top: -1.25em; + border: 0.625em solid transparent; + border-bottom: 0.625em solid; +} + +#_IdxEditInput { + width: 4.375em; +} + +.crumb-idx { + cursor:pointer; +} + +#_AbsAddr div { + cursor: pointer; +} + +#_SearchResults{ + margin: 0em; +} + +#_SearchResults li{ + cursor:pointer; + overflow: hidden; +} + +#_Search, #_SearchBar{ + display: none; +} + +#_SearchInput { + width: 100%; +} + +#_Search { + overflow-wrap: anywhere; +} + +.generic-modal-overlay { + width: 100%; + height: 100%; + position:absolute; + display:none; + z-index: 3; + cursor:pointer; + align-items: center; + justify-content: center; +} + +.generic-modal { + cursor: default; +} + +/* Mobile mode */ +#_Sidebar { + display: none; + position: absolute; + z-index: 3; +} + +#_SBSearchButton, #_SBSearchButtonSpan { + display: none; +} + +/* Desktop mode */ +@media (min-width:950px){ + #_Sidebar { + position: static; + display: flex!important; + z-index: 0; + } + #_SBSearchButton, #_SBSearchButtonSpan { + display: block; + } + + #_MobiTitlebar { + display:none; + } + + #_Overlay { + display: none!important; + } + + .limit-h { + max-width: 900px; + } +} diff --git a/rdl/outputs/docs/html/css/normalize.css b/rdl/outputs/docs/html/css/normalize.css new file mode 100644 index 0000000..47b010e --- /dev/null +++ b/rdl/outputs/docs/html/css/normalize.css @@ -0,0 +1,341 @@ +/*! normalize.css v8.0.0 | MIT License | github.com/necolas/normalize.css */ + +/* Document + ========================================================================== */ + +/** + * 1. Correct the line height in all browsers. + * 2. Prevent adjustments of font size after orientation changes in iOS. + */ + +html { + line-height: 1.15; /* 1 */ + -webkit-text-size-adjust: 100%; /* 2 */ +} + +/* Sections + ========================================================================== */ + +/** + * Remove the margin in all browsers. + */ + +body { + margin: 0; +} + +/** + * Correct the font size and margin on `h1` elements within `section` and + * `article` contexts in Chrome, Firefox, and Safari. + */ + +h1 { + font-size: 2em; + margin: 0.67em 0; +} + +/* Grouping content + ========================================================================== */ + +/** + * 1. Add the correct box sizing in Firefox. + * 2. Show the overflow in Edge and IE. + */ + +hr { + box-sizing: content-box; /* 1 */ + height: 0; /* 1 */ + overflow: visible; /* 2 */ +} + +/** + * 1. Correct the inheritance and scaling of font size in all browsers. + * 2. Correct the odd `em` font sizing in all browsers. + */ + +pre { + font-family: monospace, monospace; /* 1 */ + font-size: 1em; /* 2 */ +} + +/* Text-level semantics + ========================================================================== */ + +/** + * Remove the gray background on active links in IE 10. + */ + +a { + background-color: transparent; +} + +/** + * 1. Remove the bottom border in Chrome 57- + * 2. Add the correct text decoration in Chrome, Edge, IE, Opera, and Safari. + */ + +abbr[title] { + border-bottom: none; /* 1 */ + text-decoration: underline; /* 2 */ + text-decoration: underline dotted; /* 2 */ +} + +/** + * Add the correct font weight in Chrome, Edge, and Safari. + */ + +b, +strong { + font-weight: bolder; +} + +/** + * 1. Correct the inheritance and scaling of font size in all browsers. + * 2. Correct the odd `em` font sizing in all browsers. + */ + +code, +kbd, +samp { + font-family: monospace, monospace; /* 1 */ + font-size: 1em; /* 2 */ +} + +/** + * Add the correct font size in all browsers. + */ + +small { + font-size: 80%; +} + +/** + * Prevent `sub` and `sup` elements from affecting the line height in + * all browsers. + */ + +sub, +sup { + font-size: 75%; + line-height: 0; + position: relative; + vertical-align: baseline; +} + +sub { + bottom: -0.25em; +} + +sup { + top: -0.5em; +} + +/* Embedded content + ========================================================================== */ + +/** + * Remove the border on images inside links in IE 10. + */ + +img { + border-style: none; +} + +/* Forms + ========================================================================== */ + +/** + * 1. Change the font styles in all browsers. + * 2. Remove the margin in Firefox and Safari. + */ + +button, +input, +optgroup, +select, +textarea { + font-family: inherit; /* 1 */ + font-size: 100%; /* 1 */ + line-height: 1.15; /* 1 */ + margin: 0; /* 2 */ +} + +/** + * Show the overflow in IE. + * 1. Show the overflow in Edge. + */ + +button, +input { /* 1 */ + overflow: visible; +} + +/** + * Remove the inheritance of text transform in Edge, Firefox, and IE. + * 1. Remove the inheritance of text transform in Firefox. + */ + +button, +select { /* 1 */ + text-transform: none; +} + +/** + * Correct the inability to style clickable types in iOS and Safari. + */ + +button, +[type="button"], +[type="reset"], +[type="submit"] { + -webkit-appearance: button; +} + +/** + * Remove the inner border and padding in Firefox. + */ + +button::-moz-focus-inner, +[type="button"]::-moz-focus-inner, +[type="reset"]::-moz-focus-inner, +[type="submit"]::-moz-focus-inner { + border-style: none; + padding: 0; +} + +/** + * Restore the focus styles unset by the previous rule. + */ + +button:-moz-focusring, +[type="button"]:-moz-focusring, +[type="reset"]:-moz-focusring, +[type="submit"]:-moz-focusring { + outline: 1px dotted ButtonText; +} + +/** + * Correct the padding in Firefox. + */ + +fieldset { + padding: 0.35em 0.75em 0.625em; +} + +/** + * 1. Correct the text wrapping in Edge and IE. + * 2. Correct the color inheritance from `fieldset` elements in IE. + * 3. Remove the padding so developers are not caught out when they zero out + * `fieldset` elements in all browsers. + */ + +legend { + box-sizing: border-box; /* 1 */ + color: inherit; /* 2 */ + display: table; /* 1 */ + max-width: 100%; /* 1 */ + padding: 0; /* 3 */ + white-space: normal; /* 1 */ +} + +/** + * Add the correct vertical alignment in Chrome, Firefox, and Opera. + */ + +progress { + vertical-align: baseline; +} + +/** + * Remove the default vertical scrollbar in IE 10+. + */ + +textarea { + overflow: auto; +} + +/** + * 1. Add the correct box sizing in IE 10. + * 2. Remove the padding in IE 10. + */ + +[type="checkbox"], +[type="radio"] { + box-sizing: border-box; /* 1 */ + padding: 0; /* 2 */ +} + +/** + * Correct the cursor style of increment and decrement buttons in Chrome. + */ + +[type="number"]::-webkit-inner-spin-button, +[type="number"]::-webkit-outer-spin-button { + height: auto; +} + +/** + * 1. Correct the odd appearance in Chrome and Safari. + * 2. Correct the outline style in Safari. + */ + +[type="search"] { + -webkit-appearance: textfield; /* 1 */ + outline-offset: -2px; /* 2 */ +} + +/** + * Remove the inner padding in Chrome and Safari on macOS. + */ + +[type="search"]::-webkit-search-decoration { + -webkit-appearance: none; +} + +/** + * 1. Correct the inability to style clickable types in iOS and Safari. + * 2. Change font properties to `inherit` in Safari. + */ + +::-webkit-file-upload-button { + -webkit-appearance: button; /* 1 */ + font: inherit; /* 2 */ +} + +/* Interactive + ========================================================================== */ + +/* + * Add the correct display in Edge, IE 10+, and Firefox. + */ + +details { + display: block; +} + +/* + * Add the correct display in all browsers. + */ + +summary { + display: list-item; +} + +/* Misc + ========================================================================== */ + +/** + * Add the correct display in IE 10+. + */ + +template { + display: none; +} + +/** + * Add the correct display in IE 10. + */ + +[hidden] { + display: none; +} diff --git a/rdl/outputs/docs/html/css/theme.css b/rdl/outputs/docs/html/css/theme.css new file mode 100644 index 0000000..303c3b7 --- /dev/null +++ b/rdl/outputs/docs/html/css/theme.css @@ -0,0 +1,903 @@ +/* This file is part of PeakRDL-html . + * and can be redistributed under the terms of GNU GPL v3 . + */ + +/* ------------------------------ Color Scheme ------------------------------ */ +:root { + --main-text-color:#404040; + --title-text-color: #fff; + --title-text-color-hover: #fff; + --footer-text-color: #808080; + --url-color: #2980b9; + --url-color-hover: #3091d1; + --overlay-bg-rgba: 0,0,0,0.5; + --reserved-text-color:#808080; + --content-preview-text-color:#ccc; + + --offpage-bg-color:#eee; + --main-bg-color:#fcfcfc; + --title-bg-color: #2980b9; + --title-bg-color-hover: #2e8ece; + --alt-row-bg-color:#f3f6f6; + --inline-code-block-bg-color: #fff; + --code-block-bg-color: #efc; + --input-bg-color: #fff; + --input-invalid-bg-color: #f99; + --highlight-color: #f1c40f; + --progressbar-color: #f1c40f; + + --content-border-color: #e1e4e5; + --strong-content-border-color: #aaa; + --blockquote-bar-color: #ccc; + + --button-border-color: #949494; + --button-text-color: #4c4c4c; + --button-gradient-top-color: #f5f5f5; + --button-gradient-bottom-color: #dddddd; + + --button-disabled-border-color: #ccc; + --button-disabled-text-color: #999; + --button-disabled-bg-color: #e8e8e8; + + --admonition-title-text-color: #fff; + --admonition-title-bg-color: #6ab0de; + --admonition-bg-color: #e7f2fa; + --admonition-error-title-bg-color: #f29f97; + --admonition-error-bg-color: #fdf3f2; + --admonition-warning-title-bg-color: #f0b37e; + --admonition-warning-bg-color: #ffedcc; + --admonition-note-title-bg-color: #6ab0de; + --admonition-note-bg-color: #e7f2fa; + --admonition-hint-title-bg-color: #1abc9c; + --admonition-hint-bg-color: #dbfaf4; + + --idx-edit-text-color: #fff; + --idx-edit-bg-color: #2e8ece; + --idx-edit-input-border-color: #2472a4; + + --crumb-idx-hover-text-color: #fff; + --crumb-idx-hover-bg-color: #2e8ece; + + --tree-text-color: #d9d9d9; + --tree-bg-color: #303030; + --tree-border-color: #303030; + --tree-hover-text-color: #d9d9d9; + --tree-hover-bg-color: #4e4a4a; + --tree-hover-border-color: #303030; + --tree-selected-text-color: #444; + --tree-selected-border-color: #c9c9c9; + +} + +@media (prefers-color-scheme: dark) { + :root { + --main-text-color: #C0C0C0; + --title-text-color: #ccc; + --title-text-color-hover: #eee; + --footer-text-color: #444; + --url-color: #2e8fcf; + --url-color-hover: #35a0e6; + --overlay-bg-rgba: 0,0,0,0.65; + --reserved-text-color:#444; + --content-preview-text-color:#888; + + --offpage-bg-color: #111; + --main-bg-color: #000; + --title-bg-color: #005e9a; + --title-bg-color-hover: #2e8ece; + --alt-row-bg-color:#222; + --inline-code-block-bg-color: #111; + --code-block-bg-color: #2a301f; + --input-bg-color: #000; + --input-invalid-bg-color: #A33; + --highlight-color: #7e6500; + --progressbar-color: #7e6500; + + --content-border-color: #444; + --strong-content-border-color: #555; + --blockquote-bar-color: #444; + + --button-border-color: #6c6c6c; + --button-text-color: #999; + --button-gradient-top-color: #444; + --button-gradient-bottom-color: #222; + + --button-disabled-border-color: #555; + --button-disabled-text-color: #555; + --button-disabled-bg-color: #222; + + --admonition-title-text-color: #ccc; + --admonition-title-bg-color: #12806a; + --admonition-bg-color: #263330; + --admonition-error-title-bg-color: #730000; + --admonition-error-bg-color: #300; + --admonition-warning-title-bg-color: #8b6b00; + --admonition-warning-bg-color: #342800; + --admonition-note-title-bg-color: #3d6580; + --admonition-note-bg-color: #262e33; + --admonition-hint-title-bg-color: #12806a; + --admonition-hint-bg-color: #263330; + + --idx-edit-text-color: #ccc; + --idx-edit-bg-color: #005e9a; + --idx-edit-input-border-color: #004e80; + + --crumb-idx-hover-text-color: #000; + --crumb-idx-hover-bg-color: #54abe6; + + --tree-text-color: #d9d9d9; + --tree-bg-color: #303030; + --tree-border-color: #303030; + --tree-hover-text-color: #d9d9d9; + --tree-hover-bg-color: #4e4a4a; + --tree-hover-border-color: #303030; + --tree-selected-text-color: #ccc; + --tree-selected-border-color: #222; + } +} + +/* --------------------------------- General -------------------------------- */ + +html{ + background-color: var(--offpage-bg-color); + font-family: "Lato","proxima-nova","Helvetica Neue",Arial,sans-serif; + font-weight: normal; + color: var(--main-text-color); +} + +a { + text-decoration: none; + color: var(--url-color); +} + +a:hover { + color: var(--url-color-hover); +} + +:not(html) { + line-height: inherit; +} + +h1, h2, h3, h4, h5, h6 { + font-weight: 700; + font-family: "Roboto Slab","ff-tisa-web-pro","Georgia",Arial,sans-serif; + color: var(--main-text-color); +} + +table { + border: solid 1px var(--content-border-color); + border-collapse: collapse; + empty-cells: show; + margin-top: 1em; +} + +th { + border-bottom: solid 2px var(--content-border-color); + font-weight: bold; +} + +td, th { + border-color: var(--content-border-color); + padding: 0.5em; +} + +td:first-child, th:first-child { + border-left-width: 0; +} + +tr:nth-child(2n) td { + background-color: var(--alt-row-bg-color); +} + +tr.reserved-field, tr.reserved-addr { + color: var(--reserved-text-color); +} + +td > p:first-child { + margin-top: 0px; +} + +td > p:last-child { + margin-bottom: 0px; +} + +hr { + border: 0; + border-top: solid 1px var(--content-border-color); + margin: 1em 0em; +} + +dt { + font-weight: bold; +} + +blockquote { + margin-left: 0px; + padding-left: 0.25em; + border-left: solid 0.313em var(--blockquote-bar-color); +} + +pre { + background-color: var(--code-block-bg-color); + border: solid 1px var(--content-border-color); + padding: 0.75em; +} + +code { + font-family: SFMono-Regular,Menlo,Monaco,Consolas,"Liberation Mono","Courier New",Courier,monospace; + font-size: 0.75em; + line-height: 1.4; + + /* inline code format */ + background-color: var(--inline-code-block-bg-color); + border: solid 1px var(--content-border-color); + padding: 0.17em 0.41em;; + font-weight: bold; +} + +pre code { + /* undo inline formatting for code block */ + background-color: inherit; + border: none; + padding: 0em; + font-weight: normal; +} + +input { + background-color: var(--input-bg-color); + color: var(--main-text-color); +} + +input.invalid { + background-color: var(--input-invalid-bg-color); +} + +button { + border-style: solid; + border-width: 1px; + border-color: var(--button-border-color); + color: var(--button-text-color); + border-radius: 2px; + background-image: linear-gradient(var(--button-gradient-top-color), var(--button-gradient-bottom-color)); + padding: 0.25em 0.9em; +} + +button:disabled { + border-color: var(--button-disabled-border-color); + color: var(--button-disabled-text-color); + background-color: var(--button-disabled-bg-color); + background-image: none; +} + + +/*:target, :target td {*/ +.target-highlight, .target-highlight td { + background-color: var(--highlight-color)!important; +} + +mark { + background-color: var(--highlight-color); +} + +#_ProgressBar { + width: 15em; + margin: auto; +} + +#_ProgressBar path { + stroke: var(--strong-content-border-color); + stroke-width: 3; +} + +#_ProgressBar path + path { + stroke: var(--progressbar-color); + stroke-width: 8; +} + +.progressbar-text { + color: var(--main-text-color)!important; +} + +/* ------------------------------- Admonitions ------------------------------ */ +.admonition-title:before { + font-family: "Font Awesome 5 Free"; + font-weight: bold; + content: "\f06a"; + margin-right:4px; +} + +.admonition { + padding:12px; + line-height:24px; + margin-bottom:24px; + background: var(--admonition-bg-color); +} + +.admonition-title { + font-weight:bold; + display:block; + color: var(--admonition-title-text-color); + background: var(--admonition-title-bg-color); + margin:-12px; + padding:6px 12px; + margin-bottom:12px; +} + +.admonition p:last-child { + margin-bottom:0; +} + +.admonition.danger, +.admonition.error{ + background: var(--admonition-error-bg-color); +} + +.admonition.danger .admonition-title, +.admonition.error .admonition-title{ + background: var(--admonition-error-title-bg-color); +} + +.admonition.attention, +.admonition.caution, +.admonition.warning { + background: var(--admonition-warning-bg-color); +} + +.admonition.attention .admonition-title, +.admonition.caution .admonition-title, +.admonition.warning .admonition-title { + background: var(--admonition-warning-title-bg-color); +} + +.admonition.note, +.admonition.seealso { + background: var(--admonition-note-bg-color); +} + +.admonition.note .admonition-title, +.admonition.seealso .admonition-title { + background: var(--admonition-note-title-bg-color); +} + +.admonition.hint, +.admonition.important, +.admonition.tip { + background: var(--admonition-hint-bg-color); +} + +.admonition.hint .admonition-title, +.admonition.important .admonition-title, +.admonition.tip .admonition-title { + background: var(--admonition-hint-title-bg-color); +} + +/* ------------------------------- Button Icons ----------------------------- */ + +.collapse-button::before { + font-family: "Font Awesome 5 Free"; + font-weight: bold; + content: "\f146"; +} + +.search-button::before { + font-family: "Font Awesome 5 Free"; + font-weight: bold; + content: "\f002"; +} + +.close-button::before { + font-family: "Font Awesome 5 Free"; + font-weight: bold; + content: "\f00d"; +} + +.menu-button::before { + font-family: "Font Awesome 5 Free"; + font-weight: bold; + content: "\f0c9"; +} + +.home-button::before { + font-family: "Font Awesome 5 Free"; + font-weight: bold; + content: "\f015"; +} + +.help-button::before { + font-family: "Font Awesome 5 Free"; + font-weight: bold; + content: "\f059"; +} + +.copy-button::before { + font-family: "Font Awesome 5 Free"; + font-weight: normal; + content: "\f0c5"; +} + +.reset-button::before { + font-family: "Font Awesome 5 Free"; + font-weight: bold; + content: "\f2ea"; +} + +/* --------------------------------- Sidebar -------------------------------- */ +#_SBTitlebar { + background-color: var(--title-bg-color); +} + +#_SBTitlebox { + font-size: 1.125em; + font-weight: bold; + text-align: center; + vertical-align: middle; + line-height: 2.2em; + + color: var(--title-text-color); +} + +#_Overlay { + background-color: rgba(var(--overlay-bg-rgba)); +} + +#_SBResizer:hover { + background-color: rgba(128, 128, 128, 0.5); +} + +.sb-button-strip { + padding: 0em 0.3em 0.3em 0.3em; +} + +.sb-button-strip button, .sb-button-strip a.button-link{ + background-color: inherit; + background-image: none; + border: none; + width: 1.25em; + height: 1.25em; + font-size: 1.5em; + text-align: center; + vertical-align: middle; + color: var(--title-text-color); + padding: 0em; + border-radius: 3px; +} + +.sb-button-strip button:hover, .sb-button-strip a.button-link:hover{ + color: var(--title-text-color-hover); + background-color: var(--title-bg-color-hover); + border: none; +} + +#_SBTreeContainer { + background-color: var(--tree-bg-color); + color: var(--tree-text-color); +} + +#_SBTree { + padding-top: 0.5em; +} + +#_SBTree a { + color: inherit; +} + +.node { + line-height: 1.3em; + border-color: var(--tree-border-color); + border-top-style: solid; + border-top-width: 1px; + border-bottom-style: solid; + border-bottom-width: 1px; + border-left-style: solid; + border-left-width: 1px; +} + +.node-icon { + width: 1.25em; + text-align: center; +} + +.node:hover{ + color: var(--tree-hover-text-color); + border-color: var(--tree-hover-border-color); + background-color: var(--tree-hover-bg-color); +} + +.node.open .node-icon::before { + font-family: "Font Awesome 5 Free"; + font-weight: normal; + content: "\f146"; +} + +.node.closed .node-icon::before { + font-family: "Font Awesome 5 Free"; + font-weight: normal; + content: "\f0fe"; +} + +.node.leaf .node-icon::before { + font-weight: normal; + content: "\2022"; +} + +.node.selected { + background-color: var(--main-bg-color); + color: var(--tree-selected-text-color); + font-weight: bold; + border-color: var(--tree-selected-border-color); +} + +.node.selected a:focus { + outline: none; +} + +/* ----------------------------- Mobile Titlebar ---------------------------- */ +#_MobiTitlebar { + background-color: var(--title-bg-color); + color: var(--title-text-color); +} + +#_MobiTitlebox { + vertical-align: middle; + font-size: 1.125em; + font-weight: bold; + text-align: center; + line-height: 2em; +} + +#_MobiTitlebar button{ + background-color: inherit; + background-image: none; + border: none; + font-size: 1.5em; + width: 1.5em; + height: 1.5em; + line-height: 1.5em; + text-align: center; + vertical-align: middle; + color: var(--title-text-color); + padding: 0em; +} + +#_MobiTitlebar button:hover{ + color: var(--title-text-color-hover); + background-color: var(--title-bg-color-hover); + border: none; +} +/* ------------------------------- Main Window ------------------------------ */ + +.main { + background-color: var(--main-bg-color); + padding-left: 1.875em; + padding-right: 1.875em; +} + +#_Crumbtrail { + padding-top: 0.875em; +} + +.crumb-separator { + padding: 0em 0.25em; +} + +.crumb-idx { + font-weight: bold; + padding: 0.07em; +} + +.crumb-idx:hover{ + background-color: var(--crumb-idx-hover-bg-color); + color: var(--crumb-idx-hover-text-color); +} + +dl.node-info { + display: grid; + justify-content: start; +} + +.node-info dt{ + grid-column: 1; +} + +.node-info dd { + grid-column: 2; + margin-left: 0.5em; +} + +#_AbsAddr div { + display: inline; + visibility: hidden; + color: var(--url-color); + margin-left: 1em; +} +#_AbsAddr div:hover { + color: var(--url-color-hover); +} + +#_AbsAddr:hover div { + visibility: visible; +} + +#_AbsAddr div::after { + font-family: "Font Awesome 5 Free"; + font-weight: bold; + content: "\f05a"; +} + +div#_AbsAddrDetails { + display: none; + grid-column: 2; + margin-left: 0.5em; + border-left: solid 0.313em var(--blockquote-bar-color); + padding-left: 0.5em; +} + +div#_AbsAddrDetails.open { + display: grid; +} + +#_AbsAddrDetails dt{ + grid-column: 1; +} + +#_AbsAddrDetails dd { + grid-column: 2; + margin-left: 0.5em; +} + + +input.field-value-tester { + border: solid 1px var(--strong-content-border-color); + padding: 0.25em 0.5em; + width: 9em; +} + +select.field-value-enum-tester { + padding: 0.0em 0.25em; + width: 12em; + height: 2.3em; + font-size: 0.75em; +} + +input#_RegValueTester { + border: solid 1px var(--strong-content-border-color); + padding: 0.25em 0.5em; + width: 8em; +} + +footer { + padding-bottom: 0.875em; + color: var(--footer-text-color); +} + +.headerlink { + visibility: hidden; +} + +.headerlink::after { + font-family: "Font Awesome 5 Free"; + font-size: 0.75em; + font-weight: bold; + content: "\f0c1"; +} + +.radix-button { + font-size: 0.79em; + font-weight: bold; + padding: 0.25em 0.48em; + border-style: solid; + border-width: 1px; + border-color: var(--button-border-color); + color: var(--button-text-color); + border-radius: 2px; + background-image: linear-gradient(var(--button-gradient-top-color), var(--button-gradient-bottom-color)); +} + +.reset-button { + font-size: 0.90em; + padding: 0.30em 0.50em; + border-style: solid; + border-width: 1px; + border-color: var(--button-border-color); + color: var(--button-text-color); + border-radius: 2px; + background-image: linear-gradient(var(--button-gradient-top-color), var(--button-gradient-bottom-color)); +} + +h1:hover .headerlink::after, +h2:hover .headerlink::after, +h3:hover .headerlink::after, +h4:hover .headerlink::after, +tr:hover .headerlink::after { + visibility: visible; +} + +/* --------------------------------- Search --------------------------------- */ +#_SearchBar { + padding-top: 0.875em; + padding-bottom: 0.875em; +} + +#_SearchBar input { + border: solid 1px var(--strong-content-border-color); + padding: 0.5em 1em; + font-size: 1.125em; +} + +#_SearchResults { + padding: 0em; + width: 100%; +} + +#_SearchResults li:first-child { + border-top: solid 1px var(--content-border-color); +} + +#_SearchResults li { + display: block; + width: 100%; + padding: 0.5em 0em; + border-bottom: solid 1px var(--content-border-color); +} + +#_SearchResults .selected { + background-color: var(--alt-row-bg-color); +} + +#_SearchResults a { + color: var(--main-text-color); +} + +.search-content-preview { + color: var(--content-preview-text-color); + padding-left: 2em; + padding-top: 0.5em; + } + +/* --------------------------- Index Editor Modal --------------------------- */ +#_IdxEditModal { + background-color: var(--idx-edit-bg-color); + box-shadow: rgba(0, 0, 0, 0.25) 1px 3px 6px 1px; +} + +#_IdxEditModal::before { + border-bottom-color: var(--idx-edit-bg-color); +} + +#_IdxEditInput { + border: solid 1px var(--idx-edit-input-border-color); + padding: 0.25em 0.5em; +} + +#_IdxEditRange { + color: var(--idx-edit-text-color); +} + +/* ------------------------------ Generic Modal ----------------------------- */ +.generic-modal-overlay { + background-color: rgba(var(--overlay-bg-rgba)); +} + +.generic-modal { + background-color: var(--main-bg-color); + border: 1px solid var(--strong-content-border-color); + padding: 0em 1em 1em 1em; +} + +.generic-modal h1 { + font-size: 1.5em; +} + +.generic-modal h2 { + font-size: 1.3em; +} + +.generic-modal h3 { + font-size: 1.1em; +} + +/* ------------------------------- Help Modal ------------------------------- */ +.kb-shortcut-key { + border: solid 1px var(--strong-content-border-color); + background-color: var(--alt-row-bg-color); + padding: 0.125em 0.25em; + margin-left: 0.125em; + margin-right: 0.125em; + border-radius: 0.25em; +} + +.generic-modal dt { + margin-top: 1em; + margin-bottom: 0.1em; +} + +/* ---------------------------------- Fonts --------------------------------- */ +@font-face { + font-family:"Lato"; + font-weight:400; + font-style:normal; + src:url("../fonts/Lato/lato-regular.eot"); + src:url("../fonts/Lato/lato-regular.eot?#iefix") format("embedded-opentype"), + url("../fonts/Lato/lato-regular.woff2") format("woff2"), + url("../fonts/Lato/lato-regular.woff") format("woff"), + url("../fonts/Lato/lato-regular.ttf") format("truetype"); +} +@font-face { + font-family:"Lato"; + font-weight:700; + font-style:normal; + src:url("../fonts/Lato/lato-bold.eot"); + src:url("../fonts/Lato/lato-bold.eot?#iefix") format("embedded-opentype"), + url("../fonts/Lato/lato-bold.woff2") format("woff2"), + url("../fonts/Lato/lato-bold.woff") format("woff"), + url("../fonts/Lato/lato-bold.ttf") format("truetype"); +} +@font-face { + font-family:"Lato"; + font-weight:700; + font-style:italic; + src:url("../fonts/Lato/lato-bolditalic.eot"); + src:url("../fonts/Lato/lato-bolditalic.eot?#iefix") format("embedded-opentype"), + url("../fonts/Lato/lato-bolditalic.woff2") format("woff2"), + url("../fonts/Lato/lato-bolditalic.woff") format("woff"), + url("../fonts/Lato/lato-bolditalic.ttf") format("truetype"); +} +@font-face { + font-family:"Lato"; + font-weight:400; + font-style:italic; + src:url("../fonts/Lato/lato-italic.eot"); + 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+ +### rx_frame_sync_status register + +- Absolute Address: 0x98 +- Base Offset: 0x98 +- Size: 0x4 + +| Bits| Identifier | Access |Reset| Name | +|-----|---------------------|--------|-----|---------------------| +| 0 | frame_sync_locked | rw | 0x0 | Frame Sync Lock | +| 1 |frame_buffer_overflow|rw, rclr| 0x0 |Frame Buffer Overflow| +| 25:2| frames_received | rw | 0x0 | Frames Received | +|31:26| frame_sync_errors | rw | 0x0 | Frames Sync Errors | + +#### frame_sync_locked field + +

0 - Frame sync not locked +1 - Frame sync locked

+ +#### frame_buffer_overflow field + +

0 - Normal operation +1 - Buffer overflow

+ +#### frames_received field + +

Count of frames received since last read. Value is 0x00_0000 to 0xFF_FFFF

+ +#### frame_sync_errors field + +

Count of frame sync errors since last read. Value is 0 to 63. This field will saturate at 63 if more than 63 occur.

diff --git a/rdl/outputs/docs/msk_top_regs.pdf b/rdl/outputs/docs/msk_top_regs.pdf index a9485c2443085004fe447958ed226b3a089d7563..60c703c84fe3af9c951733d32e82e46113b1bf36 100644 GIT binary patch delta 90185 zcmYJaQ*>rs7p)uHwrv{~+qP{xZ*1GC*tVTiY}+;~JoSJ3>~rqc)mp8sHpdu!^#07T z2*}^5kO_JKxym*_?sc~K>kT`eWK%Y6oy+nDa*3qm?a%k1!s6vcrwu8EBrA|NAYZUw zMiz&Lr|V!Id8d=(j4m_y!U>dMZfUOwMsU;>_|#~HvRsobk2Bk5`Ja62A6D(-rL3hP zxYesx8L5Kq1OD$ue+$)Nc~TFF6_mBgizBFxry|4wvOemEKGKd7Vdr5}UD)YM{9Tht z*Tjeea3(kFDb}kSUv4~yIbCnSgsd?G=KJdv9N?ojUJ0o$JKbY3W=8s0sDdMFB<~n2 zy`GrjKufCk%709zDt%hsrh~jwWi2S+_Gi9(C5;2dIm6lh6p^(?3w3iaZs{Ef`Tw~( zuxpP5H1f$dfvhY$KX?fPVY^G_x)x9?hwxNwA8kWkRqxMYB8X3@%&Zz;&KTjfI(u&O zM33L53DJ)+J-BMrkVHUT(|PPkp)U`v;smHd!LICh^&preKk%^-gq^!mv@70R8e$SS z3BiyxTy*vWFO4%Sb%IHtsbm973g*o~kxuym2uumTE@ghqjQ9LPL#U*-a1E`MDJmvb zK2O#&{a9HzC|A?n&CChKBSFZ2kGETk=Nr@yfEpzH z@Dr+Byt-Tv(7dZVq=J06mZk~*j4V(&xRLg$r-x~sZ-bBsY!`E0G_`?;zZ+GBqoBtH z^goO+S!8v=m6x7i4%sOqu1TfI(Liomz!myO z^?1?@YMD@qXBe?(9BfuUXY#WZOZHCzZ7S2-WbCPNzi^0L6+uL79-c?ClfI5mM6l|J zPUF9FFgJIy?8G(lfg7X9M~WKIa3WFm9vA`gaNr!eIL`r!&`eV42r2QM{p2Zf_eY@o^WkZ_i_q_jIasG`hmvWU_5dP8xdwFrLRcgi zpLVWjG4X^-R52yZ#3C%$kEkd3mWs%Zs?#RSD`1!x!%2O)H=Wa^4~NUw_5zh|NB6a{ zqlRa^;e5DN;4Ht%FCn$Wn840RxWOLL===irmtMZcXt-iBAlm!S6Va&kj5Wr|{GSW= zuRgekegJNbi{%m%sCQ522A?rt_5M3yvmLvGr6BYU>LVjSY@GI`VLxbd!)+6ooc%hm zk?iOuTSTA4I55>Z#7 zRInfICb`JBDnv%U@0xF}*aYcKI3ZW1XhFsmyPBNegJ z4m(C#US9+hp>u73uYvz!a21HW+BEA}3)Zr|$5L3!e+P2&Nx&LGh;?j+& zN@|C4_sK|MEV4z9X+DpWgf2{=wQ*0$oWb)g`zy`AG4H7Z^Obq|K3tLB?H4PsK?*OX#@0~=ns!!^X3Yv{pA=Dx#n_X!gc)$9 zKpSeo)Nr5f{O=-ww6Kt$}0_2bqqzTsZ+5gL!Z_=UTg4-(fAh2%ZjT) z=bS`JBARhm(pTxXeJ`MG8ok~h)vl1I9TG*rJ{V2l#yY09LTSMi;P*C$Hj~t78?C`- zi{?&l_iu;&H0%=j!AclN-bCr~uHO|;YJbN*0dL!mK% zrcZhwN+HUSu07%V_MV41T!L~@07$n;@o@}^3(JiuL>)sVg63N8)DV7$N^P?nzMi>j z-EvC*c=YTeyPXd7Kw_LH?qGSEr4)ad4Xn?3o8P;!1A5ev3owgwbWelDI{K;5GS|hX zli_fq03uutz*Ib^6zi6}s*Rj)GBFJf3xkT&mJ2vp{f4r=rQt|qEe|vOUN$1q{V+(< zO4?bLSt)+pyB8-V^at@B#6=BiMv7%*CwL;?kB~Y|utps@Hdv=)!FJ4*7~$(=EX=Mv zdp&-cxB8vY2WarGFk3r6U$1DmX=>?^Jm}a=>KOM+RG-O3@Ub>YL@N;!?HAKd#Fz9% zLMe?{gv=KJUwD~kjNiXQz-xsK7X+O#Y=wn?27_Mi?_l^%QiP+THL`5C9$oBmu>>}T z*OaE$yx(C7{*>OP*iDfCM=|Inr40$sNsNB))u|(92CySe_!yw{XOEc`gCe@Q+LofN z*voa|xRos`B4v+1RC5S@muet>#ue(sc}nC$p?1R8ZBx|3xR50uQ%b8BdNju+0(hqk zt1BWj`~nT@W6bINiJecE7B!p(RYA!;@mo@xuA8zvhXmO=-X<1p*(VrAO1geWVk4Fb zJOt*x4sgvUU&Vrj8mXqhnHVE^`LYhzjqniy6Sykt5>yEU1X@$NESgws>rnN#V|~ui z=?^~xw6UmG6Sh}yF0@Q?`Z-@vtuZDH=fO1CH`r$fc=7;8vxUPoR0rHwL5W?{@Y&nM zn<D|H^CsviPG#pdVo z0k}j82y{XMhFkAd`}!<+U$=jDIYep?AruChkxW3&HM4r2jrs|-G3fE+zNzqghH2S- zWhlrXB`NN~THzFO97ZWrKhi?*7+^MAP#`9|!;%IJt7TcZPn!l{U)HZCcgv@HHMZ`q zwyjUuG6Dh}Jh^A4Z#NWjrr=yNYA-Zi0K6OoQie_^80KE)&aO^6nl-tvNlkf{QBv{@*H;bI=g5B$znCda|L>y#e(q&1*% z6gWxy)aUa{d$oN96-1J%3Rc5|D-YM5;Hcja>*xF)$@4H&$wr7YfEtZS=WI!|?MqtC zLhx(aZ^QK{!tyN37=O__*@;u+YCnZxJ|=E0))-iS4<41DxHsY+q;_S zx>oadok-<3q9u|A=8zdHb6ez750GXfL+Q@lO^fJZY>raCo7-zHOq0%dMR;I_ zgP24}B}9!hFq`y$@zwZs3l>OJuf)P*5aQAakgwsp7F30HA-Fp}OG2%6qv9B6 zJheaL)kphx1KR&uGc{eabm-EX17@L$gFzRlq2r+o*`U=g*S|3FOz-aLp9Gbp?iTI! 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b/rdl/outputs/python/msk_top_regs/reg_model/msk_top_regs.py index 4781613..ef38b6e 100644 --- a/rdl/outputs/python/msk_top_regs/reg_model/msk_top_regs.py +++ b/rdl/outputs/python/msk_top_regs/reg_model/msk_top_regs.py @@ -76,6 +76,410 @@ +class msk_top_regs_frame_sync_status_frame_sync_errors_cls(FieldAsyncReadWrite): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Frames Sync Errors | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Count of frame sync errors since last read. Value is 0 to 63. | + | | This field will saturate at 63 if more than 63 occur.

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "Frames Sync Errors" + @property + def rdl_desc(self) -> str: + return "Count of frame sync errors since last read. Value is 0 to 63. This field will saturate at 63 if more than 63 occur." + + + + + + + +class msk_top_regs_frame_sync_status_frames_received_cls(FieldAsyncReadWrite): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Frames Received | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Count of frames received since last read. Value is 0x00_0000 to | + | | 0xFF_FFFF

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "Frames Received" + @property + def rdl_desc(self) -> str: + return "Count of frames received since last read. Value is 0x00_0000 to 0xFF_FFFF" + + + + + + + +class msk_top_regs_frame_sync_status_frame_buffer_overflow_cls(FieldAsyncReadWrite): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Frame Buffer Overflow | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

0 - Normal operation 1 - Buffer overflow

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "Frame Buffer Overflow" + @property + def rdl_desc(self) -> str: + return "0 - Normal operation\n1 - Buffer overflow" + + + + + + + +class msk_top_regs_frame_sync_status_frame_sync_locked_cls(FieldAsyncReadWrite): + + """ + Class to represent a register field in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Frame Sync Lock | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

0 - Frame sync not locked 1 - Frame sync locked

| + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = [] + + + + + + + @property + def rdl_name(self) -> str: + return "Frame Sync Lock" + @property + def rdl_desc(self) -> str: + return "0 - Frame sync not locked\n1 - Frame sync locked" + + + + + + +class msk_top_regs_frame_sync_status_cls(RegAsyncReadWrite): + """ + Class to represent a register in the register model + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Frame Sync Status | + +--------------+-------------------------------------------------------------------------+ + """ + + __slots__ : list[str] = ['__frame_sync_locked', '__frame_buffer_overflow', '__frames_received', '__frame_sync_errors'] + + def __init__(self, + address: int, + width: int, + accesswidth: int, + logger_handle: str, + inst_name: str, + parent: Union[AsyncAddressMap,AsyncRegFile,MemoryAsyncReadWrite]): + + super().__init__(address=address, + width=width, + accesswidth=accesswidth, + logger_handle=logger_handle, + inst_name=inst_name, + parent=parent) + + # build the field attributes + + self.__frame_sync_locked:msk_top_regs_frame_sync_status_frame_sync_locked_cls = msk_top_regs_frame_sync_status_frame_sync_locked_cls( + parent_register=self, + size_props=FieldSizeProps( + width=1, + lsb=0, + msb=0, + low=0, + high=0), + misc_props=FieldMiscProps( + default=0, + is_volatile=True), + logger_handle=logger_handle+'.frame_sync_locked', + inst_name='frame_sync_locked', + field_type=int) + self.__frame_buffer_overflow:msk_top_regs_frame_sync_status_frame_buffer_overflow_cls = msk_top_regs_frame_sync_status_frame_buffer_overflow_cls( + parent_register=self, + size_props=FieldSizeProps( + width=1, + lsb=1, + msb=1, + low=1, + high=1), + misc_props=FieldMiscProps( + default=0, + is_volatile=True), + logger_handle=logger_handle+'.frame_buffer_overflow', + inst_name='frame_buffer_overflow', + field_type=int) + self.__frames_received:msk_top_regs_frame_sync_status_frames_received_cls = msk_top_regs_frame_sync_status_frames_received_cls( + parent_register=self, + size_props=FieldSizeProps( + width=24, + lsb=2, + msb=25, + low=2, + high=25), + misc_props=FieldMiscProps( + default=0, + is_volatile=True), + logger_handle=logger_handle+'.frames_received', + inst_name='frames_received', + field_type=int) + self.__frame_sync_errors:msk_top_regs_frame_sync_status_frame_sync_errors_cls = msk_top_regs_frame_sync_status_frame_sync_errors_cls( + parent_register=self, + size_props=FieldSizeProps( + width=6, + lsb=26, + msb=31, + low=26, + high=31), + misc_props=FieldMiscProps( + default=0, + is_volatile=True), + logger_handle=logger_handle+'.frame_sync_errors', + inst_name='frame_sync_errors', + field_type=int) + + @property + def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,FieldAsyncReadWrite]]: + """ + generator that produces has all the fields within the register + """ + yield self.frame_sync_locked + yield self.frame_buffer_overflow + yield self.frames_received + yield self.frame_sync_errors + + # Empty generator in case there are no children of this type + if False: yield + + + + + # build the properties for the fields + + @property + def frame_sync_locked(self) -> msk_top_regs_frame_sync_status_frame_sync_locked_cls: + """ + Property to access frame_sync_locked field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Frame Sync Lock | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

0 - Frame sync not locked 1 - Frame sync locked

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__frame_sync_locked + @property + def frame_buffer_overflow(self) -> msk_top_regs_frame_sync_status_frame_buffer_overflow_cls: + """ + Property to access frame_buffer_overflow field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Frame Buffer Overflow | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

0 - Normal operation 1 - Buffer overflow

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__frame_buffer_overflow + @property + def frames_received(self) -> msk_top_regs_frame_sync_status_frames_received_cls: + """ + Property to access frames_received field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Frames Received | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Count of frames received since last read. Value is 0x00_0000 to | + | | 0xFF_FFFF

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__frames_received + @property + def frame_sync_errors(self) -> msk_top_regs_frame_sync_status_frame_sync_errors_cls: + """ + Property to access frame_sync_errors field of the register + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Frames Sync Errors | + +--------------+-------------------------------------------------------------------------+ + | Description | .. raw:: html | + | | | + | |

Count of frame sync errors since last read. Value is 0 to 63. | + | | This field will saturate at 63 if more than 63 occur.

| + +--------------+-------------------------------------------------------------------------+ + """ + return self.__frame_sync_errors + + + @property + def systemrdl_python_child_name_map(self) -> dict[str, str]: + """ + In some cases systemRDL names need to be converted make them python safe, this dictionary + is used to map the original systemRDL names to the names of the python attributes of this + class + + Returns: dictionary whose key is the systemRDL names and value it the property name + """ + return {'frame_sync_locked':'frame_sync_locked','frame_buffer_overflow':'frame_buffer_overflow','frames_received':'frames_received','frame_sync_errors':'frame_sync_errors', + } + + + + + + + + # nodes:4 + + @overload + def get_child_by_system_rdl_name(self, name: Literal["frame_sync_locked"]) -> msk_top_regs_frame_sync_status_frame_sync_locked_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["frame_buffer_overflow"]) -> msk_top_regs_frame_sync_status_frame_buffer_overflow_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["frames_received"]) -> msk_top_regs_frame_sync_status_frames_received_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: Literal["frame_sync_errors"]) -> msk_top_regs_frame_sync_status_frame_sync_errors_cls: ... + + + @overload + def get_child_by_system_rdl_name(self, name: str) -> Union[msk_top_regs_frame_sync_status_frame_sync_locked_cls, msk_top_regs_frame_sync_status_frame_buffer_overflow_cls, msk_top_regs_frame_sync_status_frames_received_cls, msk_top_regs_frame_sync_status_frame_sync_errors_cls, ]: ... + + def get_child_by_system_rdl_name(self, name: Any) -> Any: + return super().get_child_by_system_rdl_name(name) + + + + + + + + + @property + def rdl_name(self) -> str: + return "Frame Sync Status" + + + + + + + class msk_top_regs_status_reg_data_desc_a6882ec4_cls(FieldAsyncReadWrite): """ @@ -244,7 +648,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_status_reg_data_desc_a6882ec4_0x0x1059601d_cls(FieldAsyncReadWrite): +class msk_top_regs_status_reg_data_desc_a6882ec4_0x0x10447444_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -317,7 +721,7 @@ def __init__(self, # build the field attributes - self.__data:msk_top_regs_status_reg_data_desc_a6882ec4_0x0x1059601d_cls = msk_top_regs_status_reg_data_desc_a6882ec4_0x0x1059601d_cls( + self.__data:msk_top_regs_status_reg_data_desc_a6882ec4_0x0x10447444_cls = msk_top_regs_status_reg_data_desc_a6882ec4_0x0x10447444_cls( parent_register=self, size_props=FieldSizeProps( width=32, @@ -348,7 +752,7 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field # build the properties for the fields @property - def data(self) -> msk_top_regs_status_reg_data_desc_a6882ec4_0x0x1059601d_cls: + def data(self) -> msk_top_regs_status_reg_data_desc_a6882ec4_0x0x10447444_cls: """ Property to access data field of the register @@ -388,7 +792,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_status_reg_data_desc_a6882ec4_0x0x1059601d_cls: + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_status_reg_data_desc_a6882ec4_0x0x10447444_cls: return super().get_child_by_system_rdl_name(name) @@ -758,7 +1162,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_lowpass_ema_alpha_alpha_0x0x105960a4_cls(FieldAsyncReadWrite): +class msk_top_regs_lowpass_ema_alpha_alpha_0x0x1042fd22_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -796,7 +1200,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_lowpass_ema_alpha_0x0x105960e6_cls(RegAsyncReadWrite): +class msk_top_regs_lowpass_ema_alpha_0x0x1042fd73_cls(RegAsyncReadWrite): """ Class to represent a register in the register model @@ -833,7 +1237,7 @@ def __init__(self, # build the field attributes - self.__alpha:msk_top_regs_lowpass_ema_alpha_alpha_0x0x105960a4_cls = msk_top_regs_lowpass_ema_alpha_alpha_0x0x105960a4_cls( + self.__alpha:msk_top_regs_lowpass_ema_alpha_alpha_0x0x1042fd22_cls = msk_top_regs_lowpass_ema_alpha_alpha_0x0x1042fd22_cls( parent_register=self, size_props=FieldSizeProps( width=18, @@ -864,7 +1268,7 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field # build the properties for the fields @property - def alpha(self) -> msk_top_regs_lowpass_ema_alpha_alpha_0x0x105960a4_cls: + def alpha(self) -> msk_top_regs_lowpass_ema_alpha_alpha_0x0x1042fd22_cls: """ Property to access alpha field of the register @@ -903,7 +1307,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_lowpass_ema_alpha_alpha_0x0x105960a4_cls: + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_lowpass_ema_alpha_alpha_0x0x1042fd22_cls: return super().get_child_by_system_rdl_name(name) @@ -2874,7 +3278,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_stat_32_lpf_acc_data_0x0x10526299_cls(FieldAsyncReadWrite): +class msk_top_regs_stat_32_lpf_acc_data_0x0x10427b77_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -2952,7 +3356,7 @@ def __init__(self, # build the field attributes - self.__data:msk_top_regs_stat_32_lpf_acc_data_0x0x10526299_cls = msk_top_regs_stat_32_lpf_acc_data_0x0x10526299_cls( + self.__data:msk_top_regs_stat_32_lpf_acc_data_0x0x10427b77_cls = msk_top_regs_stat_32_lpf_acc_data_0x0x10427b77_cls( parent_register=self, size_props=FieldSizeProps( width=32, @@ -2983,7 +3387,7 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field # build the properties for the fields @property - def data(self) -> msk_top_regs_stat_32_lpf_acc_data_0x0x10526299_cls: + def data(self) -> msk_top_regs_stat_32_lpf_acc_data_0x0x10427b77_cls: """ Property to access data field of the register @@ -3025,7 +3429,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_stat_32_lpf_acc_data_0x0x10526299_cls: + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_stat_32_lpf_acc_data_0x0x10427b77_cls: return super().get_child_by_system_rdl_name(name) @@ -4646,7 +5050,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_data_width_data_width_0x0x1059408f_cls(FieldAsyncReadWrite): +class msk_top_regs_data_width_data_width_0x0x10443038_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -4722,7 +5126,7 @@ def __init__(self, # build the field attributes - self.__data_width:msk_top_regs_data_width_data_width_0x0x1059408f_cls = msk_top_regs_data_width_data_width_0x0x1059408f_cls( + self.__data_width:msk_top_regs_data_width_data_width_0x0x10443038_cls = msk_top_regs_data_width_data_width_0x0x10443038_cls( parent_register=self, size_props=FieldSizeProps( width=8, @@ -4753,7 +5157,7 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field # build the properties for the fields @property - def data_width(self) -> msk_top_regs_data_width_data_width_0x0x1059408f_cls: + def data_width(self) -> msk_top_regs_data_width_data_width_0x0x10443038_cls: """ Property to access data_width field of the register @@ -4792,7 +5196,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_data_width_data_width_0x0x1059408f_cls: + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_data_width_data_width_0x0x10443038_cls: return super().get_child_by_system_rdl_name(name) @@ -5642,7 +6046,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_config_nco_fw_config_data_0x0x1059568d_cls(FieldAsyncReadWrite): +class msk_top_regs_config_nco_fw_config_data_0x0x1044472f_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -5719,7 +6123,7 @@ def __init__(self, # build the field attributes - self.__config_data:msk_top_regs_config_nco_fw_config_data_0x0x1059568d_cls = msk_top_regs_config_nco_fw_config_data_0x0x1059568d_cls( + self.__config_data:msk_top_regs_config_nco_fw_config_data_0x0x1044472f_cls = msk_top_regs_config_nco_fw_config_data_0x0x1044472f_cls( parent_register=self, size_props=FieldSizeProps( width=32, @@ -5750,7 +6154,7 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field # build the properties for the fields @property - def config_data(self) -> msk_top_regs_config_nco_fw_config_data_0x0x1059568d_cls: + def config_data(self) -> msk_top_regs_config_nco_fw_config_data_0x0x1044472f_cls: """ Property to access config_data field of the register @@ -5791,7 +6195,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_config_nco_fw_config_data_0x0x1059568d_cls: + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_config_nco_fw_config_data_0x0x1044472f_cls: return super().get_child_by_system_rdl_name(name) @@ -5815,7 +6219,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_config_nco_fw_config_data_0x0x105956cc_cls(FieldAsyncReadWrite): +class msk_top_regs_config_nco_fw_config_data_0x0x10445a0c_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -5892,7 +6296,7 @@ def __init__(self, # build the field attributes - self.__config_data:msk_top_regs_config_nco_fw_config_data_0x0x105956cc_cls = msk_top_regs_config_nco_fw_config_data_0x0x105956cc_cls( + self.__config_data:msk_top_regs_config_nco_fw_config_data_0x0x10445a0c_cls = msk_top_regs_config_nco_fw_config_data_0x0x10445a0c_cls( parent_register=self, size_props=FieldSizeProps( width=32, @@ -5923,7 +6327,7 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field # build the properties for the fields @property - def config_data(self) -> msk_top_regs_config_nco_fw_config_data_0x0x105956cc_cls: + def config_data(self) -> msk_top_regs_config_nco_fw_config_data_0x0x10445a0c_cls: """ Property to access config_data field of the register @@ -5964,7 +6368,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_config_nco_fw_config_data_0x0x105956cc_cls: + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_config_nco_fw_config_data_0x0x10445a0c_cls: return super().get_child_by_system_rdl_name(name) @@ -5988,7 +6392,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_config_nco_fw_config_data_0x0x1059570e_cls(FieldAsyncReadWrite): +class msk_top_regs_config_nco_fw_config_data_0x0x10445a24_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -6065,7 +6469,7 @@ def __init__(self, # build the field attributes - self.__config_data:msk_top_regs_config_nco_fw_config_data_0x0x1059570e_cls = msk_top_regs_config_nco_fw_config_data_0x0x1059570e_cls( + self.__config_data:msk_top_regs_config_nco_fw_config_data_0x0x10445a24_cls = msk_top_regs_config_nco_fw_config_data_0x0x10445a24_cls( parent_register=self, size_props=FieldSizeProps( width=32, @@ -6096,7 +6500,7 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field # build the properties for the fields @property - def config_data(self) -> msk_top_regs_config_nco_fw_config_data_0x0x1059570e_cls: + def config_data(self) -> msk_top_regs_config_nco_fw_config_data_0x0x10445a24_cls: """ Property to access config_data field of the register @@ -6137,7 +6541,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_config_nco_fw_config_data_0x0x1059570e_cls: + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_config_nco_fw_config_data_0x0x10445a24_cls: return super().get_child_by_system_rdl_name(name) @@ -6161,7 +6565,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_config_nco_fw_config_data_0x0x10595720_cls(FieldAsyncReadWrite): +class msk_top_regs_config_nco_fw_config_data_0x0x10445a66_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -6238,7 +6642,7 @@ def __init__(self, # build the field attributes - self.__config_data:msk_top_regs_config_nco_fw_config_data_0x0x10595720_cls = msk_top_regs_config_nco_fw_config_data_0x0x10595720_cls( + self.__config_data:msk_top_regs_config_nco_fw_config_data_0x0x10445a66_cls = msk_top_regs_config_nco_fw_config_data_0x0x10445a66_cls( parent_register=self, size_props=FieldSizeProps( width=32, @@ -6269,7 +6673,7 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field # build the properties for the fields @property - def config_data(self) -> msk_top_regs_config_nco_fw_config_data_0x0x10595720_cls: + def config_data(self) -> msk_top_regs_config_nco_fw_config_data_0x0x10445a66_cls: """ Property to access config_data field of the register @@ -6310,7 +6714,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_config_nco_fw_config_data_0x0x10595720_cls: + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_config_nco_fw_config_data_0x0x10445a66_cls: return super().get_child_by_system_rdl_name(name) @@ -8261,7 +8665,7 @@ class msk_top_regs_cls(AsyncAddressMap): +--------------+-------------------------------------------------------------------------+ """ - __slots__ : list[str] = ['__Hash_ID_Low', '__Hash_ID_High', '__MSK_Init', '__MSK_Control', '__MSK_Status', '__Tx_Bit_Count', '__Tx_Enable_Count', '__Fb_FreqWord', '__TX_F1_FreqWord', '__TX_F2_FreqWord', '__RX_F1_FreqWord', '__RX_F2_FreqWord', '__LPF_Config_0', '__LPF_Config_1', '__Tx_Data_Width', '__Rx_Data_Width', '__PRBS_Control', '__PRBS_Initial_State', '__PRBS_Polynomial', '__PRBS_Error_Mask', '__PRBS_Bit_Count', '__PRBS_Error_Count', '__LPF_Accum_F1', '__LPF_Accum_F2', '__axis_xfer_count', '__Rx_Sample_Discard', '__LPF_Config_2', '__f1_nco_adjust', '__f2_nco_adjust', '__f1_error', '__f2_error', '__Tx_Sync_Ctrl', '__Tx_Sync_Cnt', '__lowpass_ema_alpha1', '__lowpass_ema_alpha2', '__rx_power', '__tx_async_fifo_rd_wr_ptr', '__rx_async_fifo_rd_wr_ptr'] + __slots__ : list[str] = ['__Hash_ID_Low', '__Hash_ID_High', '__MSK_Init', '__MSK_Control', '__MSK_Status', '__Tx_Bit_Count', '__Tx_Enable_Count', '__Fb_FreqWord', '__TX_F1_FreqWord', '__TX_F2_FreqWord', '__RX_F1_FreqWord', '__RX_F2_FreqWord', '__LPF_Config_0', '__LPF_Config_1', '__Tx_Data_Width', '__Rx_Data_Width', '__PRBS_Control', '__PRBS_Initial_State', '__PRBS_Polynomial', '__PRBS_Error_Mask', '__PRBS_Bit_Count', '__PRBS_Error_Count', '__LPF_Accum_F1', '__LPF_Accum_F2', '__axis_xfer_count', '__Rx_Sample_Discard', '__LPF_Config_2', '__f1_nco_adjust', '__f2_nco_adjust', '__f1_error', '__f2_error', '__Tx_Sync_Ctrl', '__Tx_Sync_Cnt', '__lowpass_ema_alpha1', '__lowpass_ema_alpha2', '__rx_power', '__tx_async_fifo_rd_wr_ptr', '__rx_async_fifo_rd_wr_ptr', '__rx_frame_sync_status'] def __init__(self, *, address:int=0, @@ -8546,7 +8950,7 @@ def __init__(self, *, inst_name='Tx_Sync_Cnt', parent=self) - self.__lowpass_ema_alpha1:msk_top_regs_lowpass_ema_alpha_0x0x105960e6_cls = msk_top_regs_lowpass_ema_alpha_0x0x105960e6_cls( + self.__lowpass_ema_alpha1:msk_top_regs_lowpass_ema_alpha_0x0x1042fd73_cls = msk_top_regs_lowpass_ema_alpha_0x0x1042fd73_cls( address=self.address+132, accesswidth=32, width=32, @@ -8585,10 +8989,18 @@ def __init__(self, *, logger_handle=logger_handle+'.rx_async_fifo_rd_wr_ptr', inst_name='rx_async_fifo_rd_wr_ptr', parent=self) + + self.__rx_frame_sync_status:msk_top_regs_frame_sync_status_cls = msk_top_regs_frame_sync_status_cls( + address=self.address+152, + accesswidth=32, + width=32, + logger_handle=logger_handle+'.rx_frame_sync_status', + inst_name='rx_frame_sync_status', parent=self) + @property def size(self) -> int: - return 152 + return 156 @property def Hash_ID_Low(self) -> msk_top_regs_msk_hash_lo_cls: """ @@ -9246,7 +9658,7 @@ def Tx_Sync_Cnt(self) -> msk_top_regs_tx_sync_cnt_cls: return self.__Tx_Sync_Cnt @property - def lowpass_ema_alpha1(self) -> msk_top_regs_lowpass_ema_alpha_0x0x105960e6_cls: + def lowpass_ema_alpha1(self) -> msk_top_regs_lowpass_ema_alpha_0x0x1042fd73_cls: """ Property to access lowpass_ema_alpha1 @@ -9345,6 +9757,22 @@ def rx_async_fifo_rd_wr_ptr(self) -> msk_top_regs_status_reg_data_8a67e1fe_desc_ """ return self.__rx_async_fifo_rd_wr_ptr + @property + def rx_frame_sync_status(self) -> msk_top_regs_frame_sync_status_cls: + """ + Property to access rx_frame_sync_status + + +--------------+-------------------------------------------------------------------------+ + | SystemRDL | Value | + | Field | | + +==============+=========================================================================+ + | Name | .. raw:: html | + | | | + | | Frame Sync Status | + +--------------+-------------------------------------------------------------------------+ + """ + return self.__rx_frame_sync_status + @property @@ -9356,7 +9784,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: Returns: dictionary whose key is the systemRDL names and value it the property name """ - return {'Hash_ID_Low':'Hash_ID_Low','Hash_ID_High':'Hash_ID_High','MSK_Init':'MSK_Init','MSK_Control':'MSK_Control','MSK_Status':'MSK_Status','Tx_Bit_Count':'Tx_Bit_Count','Tx_Enable_Count':'Tx_Enable_Count','Fb_FreqWord':'Fb_FreqWord','TX_F1_FreqWord':'TX_F1_FreqWord','TX_F2_FreqWord':'TX_F2_FreqWord','RX_F1_FreqWord':'RX_F1_FreqWord','RX_F2_FreqWord':'RX_F2_FreqWord','LPF_Config_0':'LPF_Config_0','LPF_Config_1':'LPF_Config_1','Tx_Data_Width':'Tx_Data_Width','Rx_Data_Width':'Rx_Data_Width','PRBS_Control':'PRBS_Control','PRBS_Initial_State':'PRBS_Initial_State','PRBS_Polynomial':'PRBS_Polynomial','PRBS_Error_Mask':'PRBS_Error_Mask','PRBS_Bit_Count':'PRBS_Bit_Count','PRBS_Error_Count':'PRBS_Error_Count','LPF_Accum_F1':'LPF_Accum_F1','LPF_Accum_F2':'LPF_Accum_F2','axis_xfer_count':'axis_xfer_count','Rx_Sample_Discard':'Rx_Sample_Discard','LPF_Config_2':'LPF_Config_2','f1_nco_adjust':'f1_nco_adjust','f2_nco_adjust':'f2_nco_adjust','f1_error':'f1_error','f2_error':'f2_error','Tx_Sync_Ctrl':'Tx_Sync_Ctrl','Tx_Sync_Cnt':'Tx_Sync_Cnt','lowpass_ema_alpha1':'lowpass_ema_alpha1','lowpass_ema_alpha2':'lowpass_ema_alpha2','rx_power':'rx_power','tx_async_fifo_rd_wr_ptr':'tx_async_fifo_rd_wr_ptr','rx_async_fifo_rd_wr_ptr':'rx_async_fifo_rd_wr_ptr', + return {'Hash_ID_Low':'Hash_ID_Low','Hash_ID_High':'Hash_ID_High','MSK_Init':'MSK_Init','MSK_Control':'MSK_Control','MSK_Status':'MSK_Status','Tx_Bit_Count':'Tx_Bit_Count','Tx_Enable_Count':'Tx_Enable_Count','Fb_FreqWord':'Fb_FreqWord','TX_F1_FreqWord':'TX_F1_FreqWord','TX_F2_FreqWord':'TX_F2_FreqWord','RX_F1_FreqWord':'RX_F1_FreqWord','RX_F2_FreqWord':'RX_F2_FreqWord','LPF_Config_0':'LPF_Config_0','LPF_Config_1':'LPF_Config_1','Tx_Data_Width':'Tx_Data_Width','Rx_Data_Width':'Rx_Data_Width','PRBS_Control':'PRBS_Control','PRBS_Initial_State':'PRBS_Initial_State','PRBS_Polynomial':'PRBS_Polynomial','PRBS_Error_Mask':'PRBS_Error_Mask','PRBS_Bit_Count':'PRBS_Bit_Count','PRBS_Error_Count':'PRBS_Error_Count','LPF_Accum_F1':'LPF_Accum_F1','LPF_Accum_F2':'LPF_Accum_F2','axis_xfer_count':'axis_xfer_count','Rx_Sample_Discard':'Rx_Sample_Discard','LPF_Config_2':'LPF_Config_2','f1_nco_adjust':'f1_nco_adjust','f2_nco_adjust':'f2_nco_adjust','f1_error':'f1_error','f2_error':'f2_error','Tx_Sync_Ctrl':'Tx_Sync_Ctrl','Tx_Sync_Cnt':'Tx_Sync_Cnt','lowpass_ema_alpha1':'lowpass_ema_alpha1','lowpass_ema_alpha2':'lowpass_ema_alpha2','rx_power':'rx_power','tx_async_fifo_rd_wr_ptr':'tx_async_fifo_rd_wr_ptr','rx_async_fifo_rd_wr_ptr':'rx_async_fifo_rd_wr_ptr','rx_frame_sync_status':'rx_frame_sync_status', } @@ -9365,7 +9793,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - # nodes:38 + # nodes:39 @overload def get_child_by_system_rdl_name(self, name: Literal["Hash_ID_Low"]) -> msk_top_regs_msk_hash_lo_cls: ... @@ -9500,7 +9928,7 @@ def get_child_by_system_rdl_name(self, name: Literal["Tx_Sync_Cnt"]) -> msk_top_ @overload - def get_child_by_system_rdl_name(self, name: Literal["lowpass_ema_alpha1"]) -> msk_top_regs_lowpass_ema_alpha_0x0x105960e6_cls: ... + def get_child_by_system_rdl_name(self, name: Literal["lowpass_ema_alpha1"]) -> msk_top_regs_lowpass_ema_alpha_0x0x1042fd73_cls: ... @overload @@ -9518,9 +9946,13 @@ def get_child_by_system_rdl_name(self, name: Literal["tx_async_fifo_rd_wr_ptr"]) @overload def get_child_by_system_rdl_name(self, name: Literal["rx_async_fifo_rd_wr_ptr"]) -> msk_top_regs_status_reg_data_8a67e1fe_desc_8a90eed1_name_8a90eed1_cls: ... + + @overload + def get_child_by_system_rdl_name(self, name: Literal["rx_frame_sync_status"]) -> msk_top_regs_frame_sync_status_cls: ... + @overload - def get_child_by_system_rdl_name(self, name: str) -> Union[msk_top_regs_msk_hash_lo_cls, msk_top_regs_msk_hash_hi_cls, msk_top_regs_msk_init_cls, msk_top_regs_msk_ctrl_cls, msk_top_regs_msk_stat_0_cls, msk_top_regs_msk_stat_1_cls, msk_top_regs_msk_stat_2_cls, msk_top_regs_config_nco_fw_desc_c4924cc6_name_0c494469_cls, msk_top_regs_config_nco_fw_desc_94d7aaf5_name_84dd0c1c_cls, msk_top_regs_config_nco_fw_desc_42134a4f_name_d97dbd51_cls, msk_top_regs_config_nco_fw_desc_16fb48c8_name_8d01a20d_cls, msk_top_regs_config_nco_fw_desc_43c0828f_name_bdc60ecf_cls, msk_top_regs_lpf_config_0_cls, msk_top_regs_lpf_config_1_cls, msk_top_regs_data_width_desc_58c848dd_name_2fbd8eba_cls, msk_top_regs_data_width_desc_6097df38_name_4609588b_cls, msk_top_regs_prbs_ctrl_cls, msk_top_regs_config_prbs_seed_cls, msk_top_regs_config_prbs_poly_cls, msk_top_regs_config_prbs_errmask_cls, msk_top_regs_stat_32_bits_cls, msk_top_regs_stat_32_errs_cls, msk_top_regs_stat_32_lpf_acc_desc_8cebc7dc_name_f20c6670_cls, msk_top_regs_stat_32_lpf_acc_desc_dea6bd99_name_758fd0ce_cls, msk_top_regs_msk_stat_3_cls, msk_top_regs_rx_sample_discard_cls, msk_top_regs_lpf_config_2_cls, msk_top_regs_status_reg_data_f53978c8_name_d8ad3b25_cls, msk_top_regs_status_reg_data_05243a4e_name_2c154788_cls, msk_top_regs_status_reg_data_10a2e5b5_name_3b640507_cls, msk_top_regs_status_reg_data_642692cf_name_3de9a0d3_cls, msk_top_regs_tx_sync_ctrl_cls, msk_top_regs_tx_sync_cnt_cls, msk_top_regs_lowpass_ema_alpha_0x0x105960e6_cls, msk_top_regs_lowpass_ema_alpha_cls, msk_top_regs_rx_power_cls, msk_top_regs_status_reg_data_8a67e1fe_desc_aa4ec676_name_aa4ec676_cls, msk_top_regs_status_reg_data_8a67e1fe_desc_8a90eed1_name_8a90eed1_cls, ]: ... + def get_child_by_system_rdl_name(self, name: str) -> Union[msk_top_regs_msk_hash_lo_cls, msk_top_regs_msk_hash_hi_cls, msk_top_regs_msk_init_cls, msk_top_regs_msk_ctrl_cls, msk_top_regs_msk_stat_0_cls, msk_top_regs_msk_stat_1_cls, msk_top_regs_msk_stat_2_cls, msk_top_regs_config_nco_fw_desc_c4924cc6_name_0c494469_cls, msk_top_regs_config_nco_fw_desc_94d7aaf5_name_84dd0c1c_cls, msk_top_regs_config_nco_fw_desc_42134a4f_name_d97dbd51_cls, msk_top_regs_config_nco_fw_desc_16fb48c8_name_8d01a20d_cls, msk_top_regs_config_nco_fw_desc_43c0828f_name_bdc60ecf_cls, msk_top_regs_lpf_config_0_cls, msk_top_regs_lpf_config_1_cls, msk_top_regs_data_width_desc_58c848dd_name_2fbd8eba_cls, msk_top_regs_data_width_desc_6097df38_name_4609588b_cls, msk_top_regs_prbs_ctrl_cls, msk_top_regs_config_prbs_seed_cls, msk_top_regs_config_prbs_poly_cls, msk_top_regs_config_prbs_errmask_cls, msk_top_regs_stat_32_bits_cls, msk_top_regs_stat_32_errs_cls, msk_top_regs_stat_32_lpf_acc_desc_8cebc7dc_name_f20c6670_cls, msk_top_regs_stat_32_lpf_acc_desc_dea6bd99_name_758fd0ce_cls, msk_top_regs_msk_stat_3_cls, msk_top_regs_rx_sample_discard_cls, msk_top_regs_lpf_config_2_cls, msk_top_regs_status_reg_data_f53978c8_name_d8ad3b25_cls, msk_top_regs_status_reg_data_05243a4e_name_2c154788_cls, msk_top_regs_status_reg_data_10a2e5b5_name_3b640507_cls, msk_top_regs_status_reg_data_642692cf_name_3de9a0d3_cls, msk_top_regs_tx_sync_ctrl_cls, msk_top_regs_tx_sync_cnt_cls, msk_top_regs_lowpass_ema_alpha_0x0x1042fd73_cls, msk_top_regs_lowpass_ema_alpha_cls, msk_top_regs_rx_power_cls, msk_top_regs_status_reg_data_8a67e1fe_desc_aa4ec676_name_aa4ec676_cls, msk_top_regs_status_reg_data_8a67e1fe_desc_8a90eed1_name_8a90eed1_cls, msk_top_regs_frame_sync_status_cls, ]: ... def get_child_by_system_rdl_name(self, name: Any) -> Any: return super().get_child_by_system_rdl_name(name) @@ -9661,6 +10093,9 @@ def get_registers(self, unroll:bool=False) -> Iterator[Union[AsyncReg, AsyncRegA yield self.rx_async_fifo_rd_wr_ptr + + yield self.rx_frame_sync_status + # Empty generator in case there are no children of this type if False: yield diff --git a/rdl/outputs/python/msk_top_regs/sim/msk_top_regs.py b/rdl/outputs/python/msk_top_regs/sim/msk_top_regs.py index 8a49d28..5dc9718 100644 --- a/rdl/outputs/python/msk_top_regs/sim/msk_top_regs.py +++ b/rdl/outputs/python/msk_top_regs/sim/msk_top_regs.py @@ -173,6 +173,10 @@ def _build_registers(self) -> dict[int, Union[list[Union[MemoryRegister, Registe Register(width=32, full_inst_name='msk_top_regs.rx_async_fifo_rd_wr_ptr', readable=True, writable=True, fields=[FieldDefinition(high=31, low=0, msb=31, lsb=0, inst_name='data'), ]), + 152 : + Register(width=32, full_inst_name='msk_top_regs.rx_frame_sync_status', readable=True, writable=True, + fields=[FieldDefinition(high=0, low=0, msb=0, lsb=0, inst_name='frame_sync_locked'),FieldDefinition(high=1, low=1, msb=1, lsb=1, inst_name='frame_buffer_overflow'),FieldDefinition(high=25, low=2, msb=25, lsb=2, inst_name='frames_received'),FieldDefinition(high=31, low=26, msb=31, lsb=26, inst_name='frame_sync_errors'), + ]), } def _build_memories(self) -> list[MemoryEntry]: diff --git a/rdl/outputs/python/msk_top_regs/tests/test_msk_top_regs.py b/rdl/outputs/python/msk_top_regs/tests/test_msk_top_regs.py index 5371434..414ee3a 100644 --- a/rdl/outputs/python/msk_top_regs/tests/test_msk_top_regs.py +++ b/rdl/outputs/python/msk_top_regs/tests/test_msk_top_regs.py @@ -170,6 +170,9 @@ def test_inst_name(self) -> None: with self.subTest(msg='node: msk_top_regs.rx_async_fifo_rd_wr_ptr'): self.assertEqual(self.dut.rx_async_fifo_rd_wr_ptr.inst_name, 'rx_async_fifo_rd_wr_ptr') # type: ignore[union-attr] self.assertEqual(self.dut.rx_async_fifo_rd_wr_ptr.full_inst_name, 'msk_top_regs.rx_async_fifo_rd_wr_ptr') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.rx_frame_sync_status'): + self.assertEqual(self.dut.rx_frame_sync_status.inst_name, 'rx_frame_sync_status') # type: ignore[union-attr] + self.assertEqual(self.dut.rx_frame_sync_status.full_inst_name, 'msk_top_regs.rx_frame_sync_status') # type: ignore[union-attr] with self.subTest(msg='node: msk_top_regs.Hash_ID_Low.hash_id_lo'): self.assertEqual(self.dut.Hash_ID_Low.hash_id_lo.inst_name, 'hash_id_lo') # type: ignore[union-attr] self.assertEqual(self.dut.Hash_ID_Low.hash_id_lo.full_inst_name, 'msk_top_regs.Hash_ID_Low.hash_id_lo') # type: ignore[union-attr] @@ -347,6 +350,18 @@ def test_inst_name(self) -> None: with self.subTest(msg='node: msk_top_regs.rx_async_fifo_rd_wr_ptr.data'): self.assertEqual(self.dut.rx_async_fifo_rd_wr_ptr.data.inst_name, 'data') # type: ignore[union-attr] self.assertEqual(self.dut.rx_async_fifo_rd_wr_ptr.data.full_inst_name, 'msk_top_regs.rx_async_fifo_rd_wr_ptr.data') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.rx_frame_sync_status.frame_sync_locked'): + self.assertEqual(self.dut.rx_frame_sync_status.frame_sync_locked.inst_name, 'frame_sync_locked') # type: ignore[union-attr] + self.assertEqual(self.dut.rx_frame_sync_status.frame_sync_locked.full_inst_name, 'msk_top_regs.rx_frame_sync_status.frame_sync_locked') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.rx_frame_sync_status.frame_buffer_overflow'): + self.assertEqual(self.dut.rx_frame_sync_status.frame_buffer_overflow.inst_name, 'frame_buffer_overflow') # type: ignore[union-attr] + self.assertEqual(self.dut.rx_frame_sync_status.frame_buffer_overflow.full_inst_name, 'msk_top_regs.rx_frame_sync_status.frame_buffer_overflow') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.rx_frame_sync_status.frames_received'): + self.assertEqual(self.dut.rx_frame_sync_status.frames_received.inst_name, 'frames_received') # type: ignore[union-attr] + self.assertEqual(self.dut.rx_frame_sync_status.frames_received.full_inst_name, 'msk_top_regs.rx_frame_sync_status.frames_received') # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.rx_frame_sync_status.frame_sync_errors'): + self.assertEqual(self.dut.rx_frame_sync_status.frame_sync_errors.inst_name, 'frame_sync_errors') # type: ignore[union-attr] + self.assertEqual(self.dut.rx_frame_sync_status.frame_sync_errors.full_inst_name, 'msk_top_regs.rx_frame_sync_status.frame_sync_errors') # type: ignore[union-attr] def test_name_property(self) -> None: @@ -619,6 +634,13 @@ def test_name_property(self) -> None: + with self.subTest(msg='node: msk_top_regs.rx_frame_sync_status'): + + + self.assertEqual(self.dut.rx_frame_sync_status.rdl_name, "Frame Sync Status") # type: ignore[union-attr] + + + with self.subTest(msg='node: msk_top_regs.Hash_ID_Low.hash_id_lo'): @@ -1032,6 +1054,34 @@ def test_name_property(self) -> None: + with self.subTest(msg='node: msk_top_regs.rx_frame_sync_status.frame_sync_locked'): + + + self.assertEqual(self.dut.rx_frame_sync_status.frame_sync_locked.rdl_name, "Frame Sync Lock") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.rx_frame_sync_status.frame_buffer_overflow'): + + + self.assertEqual(self.dut.rx_frame_sync_status.frame_buffer_overflow.rdl_name, "Frame Buffer Overflow") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.rx_frame_sync_status.frames_received'): + + + self.assertEqual(self.dut.rx_frame_sync_status.frames_received.rdl_name, "Frames Received") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.rx_frame_sync_status.frame_sync_errors'): + + + self.assertEqual(self.dut.rx_frame_sync_status.frame_sync_errors.rdl_name, "Frames Sync Errors") # type: ignore[union-attr] + + + def test_desc(self) -> None: @@ -1304,6 +1354,13 @@ def test_desc(self) -> None: + with self.subTest(msg='node: msk_top_regs.rx_frame_sync_status'): + + + self.assertIsNone(self.dut.rx_frame_sync_status.rdl_desc) # type: ignore[union-attr] + + + with self.subTest(msg='node: msk_top_regs.Hash_ID_Low.hash_id_lo'): @@ -1717,6 +1774,34 @@ def test_desc(self) -> None: + with self.subTest(msg='node: msk_top_regs.rx_frame_sync_status.frame_sync_locked'): + + + self.assertEqual(self.dut.rx_frame_sync_status.frame_sync_locked.rdl_desc, "0 - Frame sync not locked\n1 - Frame sync locked") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.rx_frame_sync_status.frame_buffer_overflow'): + + + self.assertEqual(self.dut.rx_frame_sync_status.frame_buffer_overflow.rdl_desc, "0 - Normal operation\n1 - Buffer overflow") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.rx_frame_sync_status.frames_received'): + + + self.assertEqual(self.dut.rx_frame_sync_status.frames_received.rdl_desc, "Count of frames received since last read. Value is 0x00_0000 to 0xFF_FFFF") # type: ignore[union-attr] + + + + with self.subTest(msg='node: msk_top_regs.rx_frame_sync_status.frame_sync_errors'): + + + self.assertEqual(self.dut.rx_frame_sync_status.frame_sync_errors.rdl_desc, "Count of frame sync errors since last read. Value is 0 to 63. This field will saturate at 63 if more than 63 occur.") # type: ignore[union-attr] + + + def test_sizes(self) -> None: @@ -1799,12 +1884,14 @@ def test_sizes(self) -> None: self.assertEqual(self.dut.tx_async_fifo_rd_wr_ptr.size, 4) # type: ignore[union-attr] with self.subTest(msg='node: msk_top_regs.rx_async_fifo_rd_wr_ptr'): self.assertEqual(self.dut.rx_async_fifo_rd_wr_ptr.size, 4) # type: ignore[union-attr] + with self.subTest(msg='node: msk_top_regs.rx_frame_sync_status'): + self.assertEqual(self.dut.rx_frame_sync_status.size, 4) # type: ignore[union-attr] # check the size of the address map itself with self.subTest(msg='node: msk_top_regs'): - self.assertEqual(self.dut.size, 152) # type: ignore[union-attr] + self.assertEqual(self.dut.size, 156) # type: ignore[union-attr] @@ -2003,6 +2090,11 @@ def test_register_properties(self) -> None: self.assertEqual(self.dut.rx_async_fifo_rd_wr_ptr.width, 32) # type: ignore[union-attr] self.assertEqual(self.dut.rx_async_fifo_rd_wr_ptr.size, 4) # type: ignore[union-attr] self.assertEqual(self.dut.rx_async_fifo_rd_wr_ptr.accesswidth, 32) # type: ignore[union-attr] + with self.subTest(msg='register: msk_top_regs.rx_frame_sync_status'): + self.assertEqual(self.dut.rx_frame_sync_status.address, 152) # type: ignore[union-attr] + self.assertEqual(self.dut.rx_frame_sync_status.width, 32) # type: ignore[union-attr] + self.assertEqual(self.dut.rx_frame_sync_status.size, 4) # type: ignore[union-attr] + self.assertEqual(self.dut.rx_frame_sync_status.accesswidth, 32) # type: ignore[union-attr] def test_memory_properties(self) -> None: @@ -2964,6 +3056,70 @@ def test_field_properties(self) -> None: self.assertEqual(fut.default,0) self.assertEqual(fut.is_volatile,True) + with self.subTest(msg='field: msk_top_regs.rx_frame_sync_status.frame_sync_locked'): + # test properties of field: msk_top_regs.rx_frame_sync_status.frame_sync_locked + fut = self.dut.rx_frame_sync_status.frame_sync_locked # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,0) + self.assertEqual(fut.msb,0) + self.assertEqual(fut.low,0) + self.assertEqual(fut.high,0) + self.assertEqual(fut.bitmask,0x1) + self.assertEqual(fut.inverse_bitmask,0xFFFFFFFE) + self.assertEqual(fut.max_value,0x1) + + self.assertEqual(fut.default,0) + + self.assertEqual(fut.is_volatile,True) + with self.subTest(msg='field: msk_top_regs.rx_frame_sync_status.frame_buffer_overflow'): + # test properties of field: msk_top_regs.rx_frame_sync_status.frame_buffer_overflow + fut = self.dut.rx_frame_sync_status.frame_buffer_overflow # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,1) + self.assertEqual(fut.msb,1) + self.assertEqual(fut.low,1) + self.assertEqual(fut.high,1) + self.assertEqual(fut.bitmask,0x2) + self.assertEqual(fut.inverse_bitmask,0xFFFFFFFD) + self.assertEqual(fut.max_value,0x1) + + self.assertEqual(fut.default,0) + + self.assertEqual(fut.is_volatile,True) + with self.subTest(msg='field: msk_top_regs.rx_frame_sync_status.frames_received'): + # test properties of field: msk_top_regs.rx_frame_sync_status.frames_received + fut = self.dut.rx_frame_sync_status.frames_received # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,2) + self.assertEqual(fut.msb,25) + self.assertEqual(fut.low,2) + self.assertEqual(fut.high,25) + self.assertEqual(fut.bitmask,0x3FFFFFC) + self.assertEqual(fut.inverse_bitmask,0xFC000003) + self.assertEqual(fut.max_value,0xFFFFFF) + + self.assertEqual(fut.default,0) + + self.assertEqual(fut.is_volatile,True) + with self.subTest(msg='field: msk_top_regs.rx_frame_sync_status.frame_sync_errors'): + # test properties of field: msk_top_regs.rx_frame_sync_status.frame_sync_errors + fut = self.dut.rx_frame_sync_status.frame_sync_errors # type: ignore[union-attr] + if not isinstance(fut, Field): + raise TypeError('This test relies on node being of type Field') + self.assertEqual(fut.lsb,26) + self.assertEqual(fut.msb,31) + self.assertEqual(fut.low,26) + self.assertEqual(fut.high,31) + self.assertEqual(fut.bitmask,0xFC000000) + self.assertEqual(fut.inverse_bitmask,0x3FFFFFF) + self.assertEqual(fut.max_value,0x3F) + + self.assertEqual(fut.default,0) + + self.assertEqual(fut.is_volatile,True) def test_field_encoding_properties(self) -> None: @@ -3025,6 +3181,10 @@ def test_field_encoding_properties(self) -> None: + + + + @@ -3187,6 +3347,10 @@ def test_user_defined_properties(self) -> None: self.assertDictEqual(self.dut.rx_async_fifo_rd_wr_ptr.udp,{}) + with self.subTest(msg='register: msk_top_regs.rx_frame_sync_status'): + + self.assertDictEqual(self.dut.rx_frame_sync_status.udp,{}) + with self.subTest(msg='register: msk_top_regs.Hash_ID_Low.hash_id_lo'): self.assertDictEqual(self.dut.Hash_ID_Low.hash_id_lo.udp,{}) @@ -3423,6 +3587,22 @@ def test_user_defined_properties(self) -> None: self.assertDictEqual(self.dut.rx_async_fifo_rd_wr_ptr.data.udp,{}) + with self.subTest(msg='register: msk_top_regs.rx_frame_sync_status.frame_sync_locked'): + + self.assertDictEqual(self.dut.rx_frame_sync_status.frame_sync_locked.udp,{}) + + with self.subTest(msg='register: msk_top_regs.rx_frame_sync_status.frame_buffer_overflow'): + + self.assertDictEqual(self.dut.rx_frame_sync_status.frame_buffer_overflow.udp,{}) + + with self.subTest(msg='register: msk_top_regs.rx_frame_sync_status.frames_received'): + + self.assertDictEqual(self.dut.rx_frame_sync_status.frames_received.udp,{}) + + with self.subTest(msg='register: msk_top_regs.rx_frame_sync_status.frame_sync_errors'): + + self.assertDictEqual(self.dut.rx_frame_sync_status.frame_sync_errors.udp,{}) + async def test_register_read_and_write(self) -> None: @@ -6824,6 +7004,98 @@ async def test_register_read_and_write(self) -> None: # check the read has not been called in the write test read_callback_mock.assert_not_called() + # test access operations (read and/or write) to register: + # msk_top_regs.rx_frame_sync_status + with self.subTest(msg='register: msk_top_regs.rx_frame_sync_status'): + rut=self.dut.rx_frame_sync_status # type: ignore[union-attr,assignment] + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=1) as read_callback_mock: + + + if not isinstance(rut, (RegAsyncReadOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Readable Async Type') + + # test reading back 1 (the unpatched version returns 0 so this confirms the patch works) + self.assertEqual(await rut.read(), 1) + read_callback_mock.assert_called_once_with( + addr=152, + width=32, + accesswidth=rut.accesswidth) + + # test the read check with high value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFFFFFFFF + self.assertEqual(await rut.read(), 0xFFFFFFFF) + read_callback_mock.assert_called_once_with( + addr=152, + width=32, + accesswidth=rut.accesswidth) + + # test the read of the low value + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0 + self.assertEqual(await rut.read(), 0x0) + read_callback_mock.assert_called_once_with( + addr=152, + width=32, + accesswidth=rut.accesswidth) + + # test the read of a random value + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.reset_mock() + read_callback_mock.return_value = random_value + self.assertEqual(await rut.read(), random_value) + read_callback_mock.assert_called_once_with( + addr=152, + width=32, + accesswidth=rut.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + + + + if not isinstance(rut, (RegAsyncWriteOnly, RegAsyncReadWrite)): + raise TypeError('Register is not a Writeable Async Type') + + # test the write with high value + await rut.write(0xFFFFFFFF) + write_callback_mock.assert_called_once_with( + addr=152, + width=32, + accesswidth=rut.accesswidth, + data=0xFFFFFFFF) + write_callback_mock.reset_mock() + + # test the write of a low value + await rut.write(0) + write_callback_mock.assert_called_once_with( + addr=152, + width=32, + accesswidth=rut.accesswidth, + data=0) + write_callback_mock.reset_mock() + + # test the write of a random + random_value = random.randrange(0, 0xFFFFFFFF+1) + await rut.write(random_value) # type: ignore[union-attr] + write_callback_mock.assert_called_once_with( + addr=152, + width=32, + accesswidth=rut.accesswidth, + data=random_value) + write_callback_mock.reset_mock() + + # test writing a value beyond the register range is blocked with an exception being raised + with self.assertRaises(ValueError): + await rut.write(-1) + + with self.assertRaises(ValueError): + await rut.write(0xFFFFFFFF+1) + + # check the read has not been called in the write test + read_callback_mock.assert_not_called() async def test_int_field_read_and_write(self) -> None: @@ -11372,57 +11644,393 @@ async def test_int_field_read_and_write(self) -> None: with self.assertRaises(ValueError): await fut.write(-1) - + # test access operations (read and/or write) to field: + # msk_top_regs.rx_frame_sync_status.frame_sync_locked + with self.subTest(msg='field: msk_top_regs.rx_frame_sync_status.frame_sync_locked'): + fut = self.dut.rx_frame_sync_status.frame_sync_locked # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: - async def test_register_read_fields(self) -> None: - """ - Walk the register map and check every register read_fields method - """ - reference_read_fields: dict[str, Union[bool, SystemRDLEnum, int]] - - with self.subTest(msg='register: msk_top_regs.Hash_ID_Low'): - # test read_fields to register: - # msk_top_regs.Hash_ID_Low - # build up the register value with a random base value, overlaid with - # a random value for each field - rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) - - - rand_field_value = random.randrange(0, 0xFFFFFFFF + 1) - - - rand_reg_value = (rand_reg_value & 0x0) | (rand_field_value << 0) - - - - with patch(base_name + '.write_addr_space') as write_callback_mock, \ - patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: - # the read_fields method gets a dictionary back - # from the object with all the read back field - # values - reference_read_fields = { - 'hash_id_lo' : await self.dut.Hash_ID_Low.hash_id_lo.read() - } + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0xFFFFFFFE + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=152, + width=32, + accesswidth=fut.parent_register.accesswidth) + # read back - max_value, this is achieved by setting the register to bitmask read_callback_mock.reset_mock() + read_callback_mock.return_value = 0x1 + self.assertEqual(await fut.read(), + 0x1) + read_callback_mock.assert_called_once_with( + addr=152, + width=32, + accesswidth=fut.parent_register.accesswidth) - self.assertDictEqual(await self.dut.Hash_ID_Low.read_fields(), - reference_read_fields) - read_callback_mock.assert_called_once() - write_callback_mock.assert_not_called() - with self.subTest(msg='register: msk_top_regs.Hash_ID_High'): - # test read_fields to register: - # msk_top_regs.Hash_ID_High - # build up the register value with a random base value, overlaid with - # a random value for each field - rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) - - - - rand_field_value = random.randrange(0, 0xFFFFFFFF + 1) - + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0x1) >> 0 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=152, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0x1 + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0x1, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.rx_frame_sync_status.frame_sync_locked.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_called_once_with( + addr=152, + width=32, + accesswidth=fut.parent_register.accesswidth) + + write_callback_mock.assert_called_once_with( + addr=152, + width=32, + accesswidth=self.dut.rx_frame_sync_status.frame_sync_locked.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0xFFFFFFFE) | \ + (0x1 & (field_value << 0))) + + + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0x1 + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) + + # test access operations (read and/or write) to field: + # msk_top_regs.rx_frame_sync_status.frame_buffer_overflow + with self.subTest(msg='field: msk_top_regs.rx_frame_sync_status.frame_buffer_overflow'): + fut = self.dut.rx_frame_sync_status.frame_buffer_overflow # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0xFFFFFFFD + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=152, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0x2 + self.assertEqual(await fut.read(), + 0x1) + read_callback_mock.assert_called_once_with( + addr=152, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0x2) >> 1 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=152, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0x1 + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0x1, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.rx_frame_sync_status.frame_buffer_overflow.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_called_once_with( + addr=152, + width=32, + accesswidth=fut.parent_register.accesswidth) + + write_callback_mock.assert_called_once_with( + addr=152, + width=32, + accesswidth=self.dut.rx_frame_sync_status.frame_buffer_overflow.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0xFFFFFFFD) | \ + (0x2 & (field_value << 1))) + + + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0x1 + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) + + # test access operations (read and/or write) to field: + # msk_top_regs.rx_frame_sync_status.frames_received + with self.subTest(msg='field: msk_top_regs.rx_frame_sync_status.frames_received'): + fut = self.dut.rx_frame_sync_status.frames_received # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0xFC000003 + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=152, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0x3FFFFFC + self.assertEqual(await fut.read(), + 0xFFFFFF) + read_callback_mock.assert_called_once_with( + addr=152, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0x3FFFFFC) >> 2 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=152, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0xFFFFFF + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0xFFFFFF, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.rx_frame_sync_status.frames_received.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_called_once_with( + addr=152, + width=32, + accesswidth=fut.parent_register.accesswidth) + + write_callback_mock.assert_called_once_with( + addr=152, + width=32, + accesswidth=self.dut.rx_frame_sync_status.frames_received.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0xFC000003) | \ + (0x3FFFFFC & (field_value << 2))) + + + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0xFFFFFF + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) + + # test access operations (read and/or write) to field: + # msk_top_regs.rx_frame_sync_status.frame_sync_errors + with self.subTest(msg='field: msk_top_regs.rx_frame_sync_status.frame_sync_errors'): + fut = self.dut.rx_frame_sync_status.frame_sync_errors # type: ignore[union-attr] + with patch(base_name + '.write_addr_space') as write_callback_mock,\ + patch(base_name + '.read_addr_space', return_value=0) as read_callback_mock: + + + + if not isinstance(fut, (FieldAsyncReadOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a readable async field') + + + # read back - zero, this is achieved by setting the register to inverse bitmask + read_callback_mock.return_value = 0x3FFFFFF + self.assertEqual(await fut.read(), + 0) + read_callback_mock.assert_called_once_with( + addr=152, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - max_value, this is achieved by setting the register to bitmask + read_callback_mock.reset_mock() + read_callback_mock.return_value = 0xFC000000 + self.assertEqual(await fut.read(), + 0x3F) + read_callback_mock.assert_called_once_with( + addr=152, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # read back - random value + read_callback_mock.reset_mock() + random_value = random.randrange(0, 0xFFFFFFFF+1) + read_callback_mock.return_value = random_value + random_field_value = (random_value & 0xFC000000) >> 26 + self.assertEqual(await fut.read(), + random_field_value) + read_callback_mock.assert_called_once_with( + addr=152, + width=32, + accesswidth=fut.parent_register.accesswidth) + + # at the end of the read tests the write should not have been called + read_callback_mock.reset_mock() + write_callback_mock.assert_not_called() + # check the write + + if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): + raise TypeError('Test can not proceed as the fut is not a writable async field') + + + random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + random_field_value = random.randrange(0, 0x3F + 1) + for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: + for field_value in [0, 0x3F, random_field_value]: + read_callback_mock.reset_mock() + write_callback_mock.reset_mock() + read_callback_mock.return_value = reg_base_value + + await self.dut.rx_frame_sync_status.frame_sync_errors.write(field_value) # type: ignore[union-attr] + + + read_callback_mock.assert_called_once_with( + addr=152, + width=32, + accesswidth=fut.parent_register.accesswidth) + + write_callback_mock.assert_called_once_with( + addr=152, + width=32, + accesswidth=self.dut.rx_frame_sync_status.frame_sync_errors.parent_register.accesswidth, # type: ignore[union-attr] + data=(reg_base_value & 0x3FFFFFF) | \ + (0xFC000000 & (field_value << 26))) + + + # check invalid write values bounce + with self.assertRaises(ValueError): + await fut.write(0x3F + 1) + + with self.assertRaises(ValueError): + await fut.write(-1) + + + + async def test_register_read_fields(self) -> None: + """ + Walk the register map and check every register read_fields method + """ + reference_read_fields: dict[str, Union[bool, SystemRDLEnum, int]] + + with self.subTest(msg='register: msk_top_regs.Hash_ID_Low'): + # test read_fields to register: + # msk_top_regs.Hash_ID_Low + # build up the register value with a random base value, overlaid with + # a random value for each field + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFFFFFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0x0) | (rand_field_value << 0) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + # the read_fields method gets a dictionary back + # from the object with all the read back field + # values + reference_read_fields = { + 'hash_id_lo' : await self.dut.Hash_ID_Low.hash_id_lo.read() + } + + read_callback_mock.reset_mock() + + self.assertDictEqual(await self.dut.Hash_ID_Low.read_fields(), + reference_read_fields) + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() + with self.subTest(msg='register: msk_top_regs.Hash_ID_High'): + # test read_fields to register: + # msk_top_regs.Hash_ID_High + # build up the register value with a random base value, overlaid with + # a random value for each field + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0xFFFFFFFF + 1) + rand_reg_value = (rand_reg_value & 0x0) | (rand_field_value << 0) @@ -12824,6 +13432,74 @@ async def test_register_read_fields(self) -> None: reference_read_fields) read_callback_mock.assert_called_once() write_callback_mock.assert_not_called() + with self.subTest(msg='register: msk_top_regs.rx_frame_sync_status'): + # test read_fields to register: + # msk_top_regs.rx_frame_sync_status + # build up the register value with a random base value, overlaid with + # a random value for each field + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0x1 + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFFFFFE) | (rand_field_value << 0) + + + + + + + + rand_field_value = random.randrange(0, 0x1 + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFFFFFD) | (rand_field_value << 1) + + + + + + + + rand_field_value = random.randrange(0, 0xFFFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0xFC000003) | (rand_field_value << 2) + + + + + + + + rand_field_value = random.randrange(0, 0x3F + 1) + + + rand_reg_value = (rand_reg_value & 0x3FFFFFF) | (rand_field_value << 26) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + # the read_fields method gets a dictionary back + # from the object with all the read back field + # values + reference_read_fields = { + 'frame_sync_locked' : await self.dut.rx_frame_sync_status.frame_sync_locked.read(), + 'frame_buffer_overflow' : await self.dut.rx_frame_sync_status.frame_buffer_overflow.read(), + 'frames_received' : await self.dut.rx_frame_sync_status.frames_received.read(), + 'frame_sync_errors' : await self.dut.rx_frame_sync_status.frame_sync_errors.read() + } + + read_callback_mock.reset_mock() + + self.assertDictEqual(await self.dut.rx_frame_sync_status.read_fields(), + reference_read_fields) + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() async def test_register_read_context_manager(self) -> None: """ @@ -14516,6 +15192,88 @@ async def test_register_read_context_manager(self) -> None: read_callback_mock.assert_called_once() write_callback_mock.assert_not_called() + # test context manager to register: + # msk_top_regs.rx_frame_sync_status + # build up the register value with a random base value, overlaid with + # a random value for each field + with self.subTest(msg='register: msk_top_regs.rx_frame_sync_status'): + rand_reg_value = random.randrange(0, 0xFFFFFFFF + 1) + + + + rand_field_value = random.randrange(0, 0x1 + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFFFFFE) | (rand_field_value << 0) + + + + + + + + rand_field_value = random.randrange(0, 0x1 + 1) + + + rand_reg_value = (rand_reg_value & 0xFFFFFFFD) | (rand_field_value << 1) + + + + + + + + rand_field_value = random.randrange(0, 0xFFFFFF + 1) + + + rand_reg_value = (rand_reg_value & 0xFC000003) | (rand_field_value << 2) + + + + + + + + rand_field_value = random.randrange(0, 0x3F + 1) + + + rand_reg_value = (rand_reg_value & 0x3FFFFFF) | (rand_field_value << 26) + + + + + with patch(base_name + '.write_addr_space') as write_callback_mock, \ + patch(base_name + '.read_addr_space', return_value=rand_reg_value) as read_callback_mock: + + # first read the fields using the "normal" method, then compare the result to reading + # via the context manager + reference_read_fields = { + 'frame_sync_locked' : await self.dut.rx_frame_sync_status.frame_sync_locked.read(), # type: ignore[union-attr] + 'frame_buffer_overflow' : await self.dut.rx_frame_sync_status.frame_buffer_overflow.read(), # type: ignore[union-attr] + 'frames_received' : await self.dut.rx_frame_sync_status.frames_received.read(), # type: ignore[union-attr] + 'frame_sync_errors' : await self.dut.rx_frame_sync_status.frame_sync_errors.read() # type: ignore[union-attr] + } + read_callback_mock.reset_mock() + + + async with self.dut.rx_frame_sync_status.single_read_modify_write(skip_write=True) as reg_context: # type: ignore[union-attr] + + self.assertEqual(reference_read_fields['frame_sync_locked'], + await reg_context.get_child_by_system_rdl_name('frame_sync_locked').read() + ) + self.assertEqual(reference_read_fields['frame_buffer_overflow'], + await reg_context.get_child_by_system_rdl_name('frame_buffer_overflow').read() + ) + self.assertEqual(reference_read_fields['frames_received'], + await reg_context.get_child_by_system_rdl_name('frames_received').read() + ) + self.assertEqual(reference_read_fields['frame_sync_errors'], + await reg_context.get_child_by_system_rdl_name('frame_sync_errors').read() + ) + pass + + read_callback_mock.assert_called_once() + write_callback_mock.assert_not_called() async def test_register_write_context_manager(self) -> None: """ @@ -14753,6 +15511,13 @@ async def write_field_combinations(reg: RegAsyncReadWrite, writable_fields:list[ await write_field_combinations(reg=self.dut.rx_async_fifo_rd_wr_ptr, writable_fields = [ 'data' ]) + with self.subTest(msg='register: msk_top_regs.rx_frame_sync_status'): + await write_field_combinations(reg=self.dut.rx_frame_sync_status, + writable_fields = [ 'frame_sync_locked', + 'frame_buffer_overflow', + 'frames_received', + 'frame_sync_errors' + ]) async def test_register_write_fields(self) -> None: """ @@ -15065,6 +15830,16 @@ async def write_field_combinations(reg: RegAsyncReadWrite, writable_fields:list[ writable_fields = [ 'data' ]) + with self.subTest(msg='register: msk_top_regs.rx_frame_sync_status'): + # test read_fields to register: + # msk_top_regs.rx_frame_sync_status + await write_field_combinations(reg=self.dut.rx_frame_sync_status, + writable_fields = [ 'frame_sync_locked', + 'frame_buffer_overflow', + 'frames_received', + 'frame_sync_errors' + ]) + @@ -15266,6 +16041,11 @@ def test_adding_attributes(self) -> None: # this line is trying to set an illegal value so by definition should fail the type # checks self.dut.rx_async_fifo_rd_wr_ptr.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.rx_frame_sync_status'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.rx_frame_sync_status.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] with self.subTest(msg='node: msk_top_regs.Hash_ID_Low.hash_id_lo'): with self.assertRaises(AttributeError): # this line is trying to set an illegal value so by definition should fail the type @@ -15561,6 +16341,26 @@ def test_adding_attributes(self) -> None: # this line is trying to set an illegal value so by definition should fail the type # checks self.dut.rx_async_fifo_rd_wr_ptr.data.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.rx_frame_sync_status.frame_sync_locked'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.rx_frame_sync_status.frame_sync_locked.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.rx_frame_sync_status.frame_buffer_overflow'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.rx_frame_sync_status.frame_buffer_overflow.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.rx_frame_sync_status.frames_received'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.rx_frame_sync_status.frames_received.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] + with self.subTest(msg='node: msk_top_regs.rx_frame_sync_status.frame_sync_errors'): + with self.assertRaises(AttributeError): + # this line is trying to set an illegal value so by definition should fail the type + # checks + self.dut.rx_frame_sync_status.frame_sync_errors.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr] @@ -15650,6 +16450,8 @@ def test_top_traversal_iterators(self) -> None: self.dut.rx_async_fifo_rd_wr_ptr, # type: ignore[union-attr,list-item] + self.dut.rx_frame_sync_status, # type: ignore[union-attr,list-item] + ] readable_regs = [] for readable_reg in self.dut.get_readable_registers(unroll=True): # type: ignore[union-attr] @@ -15733,6 +16535,8 @@ def test_top_traversal_iterators(self) -> None: self.dut.rx_async_fifo_rd_wr_ptr, # type: ignore[union-attr,list-item] + self.dut.rx_frame_sync_status, # type: ignore[union-attr,list-item] + ] readable_regs = [] for readable_reg in self.dut.get_readable_registers(unroll=False): # type: ignore[union-attr] @@ -15816,6 +16620,8 @@ def test_top_traversal_iterators(self) -> None: self.dut.rx_async_fifo_rd_wr_ptr, # type: ignore[union-attr,list-item] + self.dut.rx_frame_sync_status, # type: ignore[union-attr,list-item] + ] writable_regs = [] for writable_reg in self.dut.get_writable_registers(unroll=True): # type: ignore[union-attr] @@ -15899,6 +16705,8 @@ def test_top_traversal_iterators(self) -> None: self.dut.rx_async_fifo_rd_wr_ptr, # type: ignore[union-attr,list-item] + self.dut.rx_frame_sync_status, # type: ignore[union-attr,list-item] + ] writable_regs = [] for writable_reg in self.dut.get_writable_registers(unroll=False): # type: ignore[union-attr] @@ -15979,6 +16787,8 @@ def test_top_traversal_iterators(self) -> None: + + @@ -16062,6 +16872,8 @@ def test_top_traversal_iterators(self) -> None: + + @@ -16145,6 +16957,8 @@ def test_top_traversal_iterators(self) -> None: + + @@ -16228,6 +17042,8 @@ def test_top_traversal_iterators(self) -> None: + + @@ -17565,6 +18381,58 @@ def test_traversal_iterators(self) -> None: readable_fields.append(readable_field) self.assertCountEqual(expected_readable_fields, readable_fields) + with self.subTest(msg='register: msk_top_regs.rx_frame_sync_status'): + + expected_fields = [self.dut.rx_frame_sync_status.frame_sync_locked, # type: ignore[union-attr,list-item] + + + self.dut.rx_frame_sync_status.frame_buffer_overflow, # type: ignore[union-attr,list-item] + + + self.dut.rx_frame_sync_status.frames_received, # type: ignore[union-attr,list-item] + + + self.dut.rx_frame_sync_status.frame_sync_errors, # type: ignore[union-attr,list-item] + + + + ] + fields = [] + for field in self.dut.rx_frame_sync_status.fields: # type: ignore[union-attr] + fields.append(field) + self.assertCountEqual(expected_fields, fields) + + expected_writable_fields = [self.dut.rx_frame_sync_status.frame_sync_locked, # type: ignore[union-attr,list-item] + + self.dut.rx_frame_sync_status.frame_buffer_overflow, # type: ignore[union-attr,list-item] + + self.dut.rx_frame_sync_status.frames_received, # type: ignore[union-attr,list-item] + + self.dut.rx_frame_sync_status.frame_sync_errors, # type: ignore[union-attr,list-item] + + + ] + writable_fields = [] + for writable_field in self.dut.rx_frame_sync_status.writable_fields: # type: ignore[union-attr] + writable_fields.append(writable_field) + self.assertCountEqual(expected_writable_fields, writable_fields) + + + expected_readable_fields = [self.dut.rx_frame_sync_status.frame_sync_locked, # type: ignore[union-attr,list-item] + + self.dut.rx_frame_sync_status.frame_buffer_overflow, # type: ignore[union-attr,list-item] + + self.dut.rx_frame_sync_status.frames_received, # type: ignore[union-attr,list-item] + + self.dut.rx_frame_sync_status.frame_sync_errors, # type: ignore[union-attr,list-item] + + + ] + readable_fields = [] + for readable_field in self.dut.rx_frame_sync_status.readable_fields: # type: ignore[union-attr] + readable_fields.append(readable_field) + self.assertCountEqual(expected_readable_fields, readable_fields) + # test all the memories @@ -17912,6 +18780,31 @@ def test_name_map(self) -> None: + self.assertEqual(self.dut.rx_frame_sync_status.get_child_by_system_rdl_name('frame_sync_locked').inst_name, 'frame_sync_locked') + + + + + self.assertEqual(self.dut.rx_frame_sync_status.get_child_by_system_rdl_name('frame_buffer_overflow').inst_name, 'frame_buffer_overflow') + + + + + self.assertEqual(self.dut.rx_frame_sync_status.get_child_by_system_rdl_name('frames_received').inst_name, 'frames_received') + + + + + self.assertEqual(self.dut.rx_frame_sync_status.get_child_by_system_rdl_name('frame_sync_errors').inst_name, 'frame_sync_errors') + + + + + + + + + diff --git a/rdl/outputs/python/msk_top_regs/tests/test_sim_msk_top_regs.py b/rdl/outputs/python/msk_top_regs/tests/test_sim_msk_top_regs.py index b0b98ad..c0ee28a 100644 --- a/rdl/outputs/python/msk_top_regs/tests/test_sim_msk_top_regs.py +++ b/rdl/outputs/python/msk_top_regs/tests/test_sim_msk_top_regs.py @@ -2062,6 +2062,61 @@ async def test_register_read_and_write(self) -> None: + # test access operations (read and/or write) to register: + # msk_top_regs.rx_frame_sync_status + with self.subTest(msg='register: msk_top_regs.rx_frame_sync_status'): + sim_register = self.sim.register_by_full_name('msk_top_regs.rx_frame_sync_status') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + register_read_callback = Mock() + register_write_callback = Mock() + + # register read checks + # update the value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.rx_frame_sync_status.read(), random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = random_value + self.assertEqual(await self.dut.rx_frame_sync_status.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.value = random_value + sim_register.read_callback = None + sim_register.write_callback = None + self.assertEqual(await self.dut.rx_frame_sync_status.read(), random_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + + + + # register write checks + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.rx_frame_sync_status.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + # up to now the callback should not have been called + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.rx_frame_sync_status.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + register_write_callback.assert_called_once_with(value=random_value) + register_read_callback.assert_not_called() + register_write_callback.reset_mock() + register_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + await self.dut.rx_frame_sync_status.write(random_value) # type: ignore[union-attr] + self.assertEqual(sim_register.value, random_value) + self.assertEqual(await self.dut.rx_frame_sync_status.read(), random_value) + + + async def test_field_read_and_write(self) -> None: @@ -8406,6 +8461,470 @@ async def test_field_read_and_write(self) -> None: field_read_callback.assert_not_called() + # test access operations (read and/or write) to register: + # msk_top_regs.rx_frame_sync_status.frame_sync_locked + with self.subTest(msg='field: msk_top_regs.rx_frame_sync_status.frame_sync_locked'): + sim_register = self.sim.register_by_full_name('msk_top_regs.rx_frame_sync_status') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.rx_frame_sync_status.frame_sync_locked') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x1) >> 0 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + self.assertEqual(await self.dut.rx_frame_sync_status.frame_sync_locked.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0x1+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0xFFFFFFFE) | (random_field_value << 0)) + + self.assertEqual(await self.dut.rx_frame_sync_status.frame_sync_locked.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x1) >> 0 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.rx_frame_sync_status.frame_sync_locked.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x1) >> 0 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + self.assertEqual(await self.dut.rx_frame_sync_status.frame_sync_locked.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value + + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.rx_frame_sync_status.frame_sync_locked.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFFE) | (0x1 & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.rx_frame_sync_status.frame_sync_locked.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFFE) | (0x1 & (random_field_value << 0))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0xFFFFFFFE) | (0x1 & (random_field_value << 0))) + field_write_callback.assert_called_once_with(value=random_field_value) + + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.write_callback = None + sim_field.write_callback = None + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.rx_frame_sync_status.frame_sync_locked.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFFE) | (0x1 & (random_field_value << 0))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # test access operations (read and/or write) to register: + # msk_top_regs.rx_frame_sync_status.frame_buffer_overflow + with self.subTest(msg='field: msk_top_regs.rx_frame_sync_status.frame_buffer_overflow'): + sim_register = self.sim.register_by_full_name('msk_top_regs.rx_frame_sync_status') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.rx_frame_sync_status.frame_buffer_overflow') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x2) >> 1 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + self.assertEqual(await self.dut.rx_frame_sync_status.frame_buffer_overflow.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0x1+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0xFFFFFFFD) | (random_field_value << 1)) + + self.assertEqual(await self.dut.rx_frame_sync_status.frame_buffer_overflow.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x2) >> 1 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.rx_frame_sync_status.frame_buffer_overflow.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x2) >> 1 + + random_field_value = self._reverse_bits(value=random_field_value, number_bits=1) + + + sim_register.value = random_value + self.assertEqual(await self.dut.rx_frame_sync_status.frame_buffer_overflow.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value + + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.rx_frame_sync_status.frame_buffer_overflow.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFFD) | (0x2 & (random_field_value << 1))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.rx_frame_sync_status.frame_buffer_overflow.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFFD) | (0x2 & (random_field_value << 1))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0xFFFFFFFD) | (0x2 & (random_field_value << 1))) + field_write_callback.assert_called_once_with(value=random_field_value) + + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.write_callback = None + sim_field.write_callback = None + random_field_value = random.randrange(0, 0x1+1) + + await self.dut.rx_frame_sync_status.frame_buffer_overflow.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFFD) | (0x2 & (random_field_value << 1))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # test access operations (read and/or write) to register: + # msk_top_regs.rx_frame_sync_status.frames_received + with self.subTest(msg='field: msk_top_regs.rx_frame_sync_status.frames_received'): + sim_register = self.sim.register_by_full_name('msk_top_regs.rx_frame_sync_status') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.rx_frame_sync_status.frames_received') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x3FFFFFC) >> 2 + + + sim_register.value = random_value + self.assertEqual(await self.dut.rx_frame_sync_status.frames_received.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0xFFFFFF+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0xFC000003) | (random_field_value << 2)) + + self.assertEqual(await self.dut.rx_frame_sync_status.frames_received.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x3FFFFFC) >> 2 + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.rx_frame_sync_status.frames_received.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0x3FFFFFC) >> 2 + + + sim_register.value = random_value + self.assertEqual(await self.dut.rx_frame_sync_status.frames_received.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value + + random_field_value = random.randrange(0, 0xFFFFFF+1) + + await self.dut.rx_frame_sync_status.frames_received.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFC000003) | (0x3FFFFFC & (random_field_value << 2))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0xFFFFFF+1) + + await self.dut.rx_frame_sync_status.frames_received.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFC000003) | (0x3FFFFFC & (random_field_value << 2))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0xFC000003) | (0x3FFFFFC & (random_field_value << 2))) + field_write_callback.assert_called_once_with(value=random_field_value) + + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.write_callback = None + sim_field.write_callback = None + random_field_value = random.randrange(0, 0xFFFFFF+1) + + await self.dut.rx_frame_sync_status.frames_received.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFC000003) | (0x3FFFFFC & (random_field_value << 2))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # test access operations (read and/or write) to register: + # msk_top_regs.rx_frame_sync_status.frame_sync_errors + with self.subTest(msg='field: msk_top_regs.rx_frame_sync_status.frame_sync_errors'): + sim_register = self.sim.register_by_full_name('msk_top_regs.rx_frame_sync_status') + self.assertIsInstance(sim_register, (Register,MemoryRegister)) + sim_field = self.sim.field_by_full_name('msk_top_regs.rx_frame_sync_status.frame_sync_errors') + self.assertIsInstance(sim_field, Field) + register_read_callback = Mock() + register_write_callback = Mock() + field_read_callback = Mock() + field_write_callback = Mock() + + # register read checks + # update the register value via the backdoor in the simulator + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFC000000) >> 26 + + + sim_register.value = random_value + self.assertEqual(await self.dut.rx_frame_sync_status.frame_sync_errors.read(), random_field_value) + # update the field value via the backdoor in the simulator + previous_register_value = random_value + random_field_value = random.randrange(0, 0x3F+1) + sim_field.value = random_field_value + self.assertEqual(sim_register.value, (previous_register_value & 0x3FFFFFF) | (random_field_value << 26)) + + self.assertEqual(await self.dut.rx_frame_sync_status.frame_sync_errors.read(), random_field_value) + # hook up the call backs to check they work correctly + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFC000000) >> 26 + + + sim_register.value = random_value + sim_register.read_callback = register_read_callback + sim_register.write_callback = register_write_callback + sim_field.read_callback = field_read_callback + sim_field.write_callback = field_write_callback + self.assertEqual(await self.dut.rx_frame_sync_status.frame_sync_errors.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_called_once_with(value=random_value) + field_write_callback.assert_not_called() + field_read_callback.assert_called_once_with(value=random_field_value) + + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.read_callback = None + sim_register.write_callback = None + sim_field.read_callback = None + sim_field.write_callback = None + random_value = random.randrange(0, 0xFFFFFFFF+1) + random_field_value = (random_value & 0xFC000000) >> 26 + + + sim_register.value = random_value + self.assertEqual(await self.dut.rx_frame_sync_status.frame_sync_errors.read(), random_field_value) + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + + # register write checks + # update the register value via the backdoor in the simulator, then perform a field + # write and make sure it is updated + inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) + sim_register.value = inital_reg_random_value + + random_field_value = random.randrange(0, 0x3F+1) + + await self.dut.rx_frame_sync_status.frame_sync_errors.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x3FFFFFF) | (0xFC000000 & (random_field_value << 26))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # hook up the call backs + sim_register.read_callback = None + sim_register.write_callback = register_write_callback + sim_field.read_callback = None + sim_field.write_callback = field_write_callback + random_field_value = random.randrange(0, 0x3F+1) + + await self.dut.rx_frame_sync_status.frame_sync_errors.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x3FFFFFF) | (0xFC000000 & (random_field_value << 26))) + register_write_callback.assert_called_once_with(value=(reg_random_value & 0x3FFFFFF) | (0xFC000000 & (random_field_value << 26))) + field_write_callback.assert_called_once_with(value=random_field_value) + + register_read_callback.assert_not_called() + field_read_callback.assert_not_called() + reg_random_value = sim_register.value + # revert the callbacks and check again + register_write_callback.reset_mock() + register_read_callback.reset_mock() + field_write_callback.reset_mock() + field_read_callback.reset_mock() + sim_register.write_callback = None + sim_field.write_callback = None + random_field_value = random.randrange(0, 0x3F+1) + + await self.dut.rx_frame_sync_status.frame_sync_errors.write(random_field_value) # type: ignore[arg-type] + self.assertEqual(sim_register.value, (inital_reg_random_value & 0x3FFFFFF) | (0xFC000000 & (random_field_value << 26))) + + register_write_callback.assert_not_called() + register_read_callback.assert_not_called() + field_write_callback.assert_not_called() + field_read_callback.assert_not_called() + + diff --git a/rdl/outputs/rtl/msk_top_regs.vhd b/rdl/outputs/rtl/msk_top_regs.vhd index c61b38d..4bda2d8 100644 --- a/rdl/outputs/rtl/msk_top_regs.vhd +++ b/rdl/outputs/rtl/msk_top_regs.vhd @@ -114,6 +114,7 @@ architecture rtl of msk_top_regs is rx_power : std_logic; tx_async_fifo_rd_wr_ptr : std_logic; rx_async_fifo_rd_wr_ptr : std_logic; + rx_frame_sync_status : std_logic; end record; signal decoded_reg_strb : decoded_reg_strb_t; signal decoded_req : std_logic; @@ -548,6 +549,33 @@ architecture rtl of msk_top_regs is data : \msk_top_regs.rx_async_fifo_rd_wr_ptr.data_combo_t\; end record; + type \msk_top_regs.rx_frame_sync_status.frame_sync_locked_combo_t\ is record + next_q : std_logic; + load_next : std_logic; + end record; + + type \msk_top_regs.rx_frame_sync_status.frame_buffer_overflow_combo_t\ is record + next_q : std_logic; + load_next : std_logic; + end record; + + type \msk_top_regs.rx_frame_sync_status.frames_received_combo_t\ is record + next_q : std_logic_vector(23 downto 0); + load_next : std_logic; + end record; + + type \msk_top_regs.rx_frame_sync_status.frame_sync_errors_combo_t\ is record + next_q : std_logic_vector(5 downto 0); + load_next : std_logic; + end record; + + type \msk_top_regs.rx_frame_sync_status_combo_t\ is record + frame_sync_locked : \msk_top_regs.rx_frame_sync_status.frame_sync_locked_combo_t\; + frame_buffer_overflow : \msk_top_regs.rx_frame_sync_status.frame_buffer_overflow_combo_t\; + frames_received : \msk_top_regs.rx_frame_sync_status.frames_received_combo_t\; + frame_sync_errors : \msk_top_regs.rx_frame_sync_status.frame_sync_errors_combo_t\; + end record; + type field_combo_t is record MSK_Init : \msk_top_regs.MSK_Init_combo_t\; MSK_Control : \msk_top_regs.MSK_Control_combo_t\; @@ -584,6 +612,7 @@ architecture rtl of msk_top_regs is rx_power : \msk_top_regs.rx_power_combo_t\; tx_async_fifo_rd_wr_ptr : \msk_top_regs.tx_async_fifo_rd_wr_ptr_combo_t\; rx_async_fifo_rd_wr_ptr : \msk_top_regs.rx_async_fifo_rd_wr_ptr_combo_t\; + rx_frame_sync_status : \msk_top_regs.rx_frame_sync_status_combo_t\; end record; signal field_combo : field_combo_t; @@ -958,6 +987,29 @@ architecture rtl of msk_top_regs is data : \msk_top_regs.rx_async_fifo_rd_wr_ptr.data_storage_t\; end record; + type \msk_top_regs.rx_frame_sync_status.frame_sync_locked_storage_t\ is record + value : std_logic; + end record; + + type \msk_top_regs.rx_frame_sync_status.frame_buffer_overflow_storage_t\ is record + value : std_logic; + end record; + + type \msk_top_regs.rx_frame_sync_status.frames_received_storage_t\ is record + value : std_logic_vector(23 downto 0); + end record; + + type \msk_top_regs.rx_frame_sync_status.frame_sync_errors_storage_t\ is record + value : std_logic_vector(5 downto 0); + end record; + + type \msk_top_regs.rx_frame_sync_status_storage_t\ is record + frame_sync_locked : \msk_top_regs.rx_frame_sync_status.frame_sync_locked_storage_t\; + frame_buffer_overflow : \msk_top_regs.rx_frame_sync_status.frame_buffer_overflow_storage_t\; + frames_received : \msk_top_regs.rx_frame_sync_status.frames_received_storage_t\; + frame_sync_errors : \msk_top_regs.rx_frame_sync_status.frame_sync_errors_storage_t\; + end record; + type field_storage_t is record MSK_Init : \msk_top_regs.MSK_Init_storage_t\; MSK_Control : \msk_top_regs.MSK_Control_storage_t\; @@ -994,6 +1046,7 @@ architecture rtl of msk_top_regs is rx_power : \msk_top_regs.rx_power_storage_t\; tx_async_fifo_rd_wr_ptr : \msk_top_regs.tx_async_fifo_rd_wr_ptr_storage_t\; rx_async_fifo_rd_wr_ptr : \msk_top_regs.rx_async_fifo_rd_wr_ptr_storage_t\; + rx_frame_sync_status : \msk_top_regs.rx_frame_sync_status_storage_t\; end record; signal field_storage : field_storage_t; @@ -1003,7 +1056,7 @@ architecture rtl of msk_top_regs is signal readback_err : std_logic; signal readback_done : std_logic; signal readback_data : std_logic_vector(31 downto 0); - signal readback_array : std_logic_vector_array1(0 to 37)(31 downto 0); + signal readback_array : std_logic_vector_array1(0 to 38)(31 downto 0); begin @@ -1255,6 +1308,7 @@ begin decoded_reg_strb.rx_power <= cpuif_req_masked and (cpuif_addr = 16#8C#); decoded_reg_strb.tx_async_fifo_rd_wr_ptr <= cpuif_req_masked and (cpuif_addr = 16#90#); decoded_reg_strb.rx_async_fifo_rd_wr_ptr <= cpuif_req_masked and (cpuif_addr = 16#94#); + decoded_reg_strb.rx_frame_sync_status <= cpuif_req_masked and (cpuif_addr = 16#98#); end process; -- Pass down signals to next stage @@ -2860,6 +2914,135 @@ begin end process; hwif_out.rx_async_fifo_rd_wr_ptr.data.swmod <= decoded_reg_strb.rx_async_fifo_rd_wr_ptr and decoded_req_is_wr and or_reduce(decoded_wr_biten(31 downto 0)); + -- Field: msk_top_regs.rx_frame_sync_status.frame_sync_locked + process(all) + variable next_c: std_logic; + variable load_next_c: std_logic; + begin + next_c := field_storage.rx_frame_sync_status.frame_sync_locked.value; + load_next_c := '0'; + if decoded_reg_strb.rx_frame_sync_status and decoded_req_is_wr then -- SW write + next_c := (field_storage.rx_frame_sync_status.frame_sync_locked.value and not decoded_wr_biten(0)) or (decoded_wr_data(0) and decoded_wr_biten(0)); + load_next_c := '1'; + else -- HW Write + next_c := hwif_in.rx_frame_sync_status.frame_sync_locked.next_q; + load_next_c := '1'; + end if; + field_combo.rx_frame_sync_status.frame_sync_locked.next_q <= next_c; + field_combo.rx_frame_sync_status.frame_sync_locked.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.rx_frame_sync_status.frame_sync_locked.value <= '0'; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.rx_frame_sync_status.frame_sync_locked.value <= '0'; + else + if field_combo.rx_frame_sync_status.frame_sync_locked.load_next then + field_storage.rx_frame_sync_status.frame_sync_locked.value <= field_combo.rx_frame_sync_status.frame_sync_locked.next_q; + end if; + end if; + end if; + end process; + + -- Field: msk_top_regs.rx_frame_sync_status.frame_buffer_overflow + process(all) + variable next_c: std_logic; + variable load_next_c: std_logic; + begin + next_c := field_storage.rx_frame_sync_status.frame_buffer_overflow.value; + load_next_c := '0'; + if decoded_reg_strb.rx_frame_sync_status and not decoded_req_is_wr then -- SW clear on read + next_c := '0'; + load_next_c := '1'; + elsif decoded_reg_strb.rx_frame_sync_status and decoded_req_is_wr then -- SW write + next_c := (field_storage.rx_frame_sync_status.frame_buffer_overflow.value and not decoded_wr_biten(1)) or (decoded_wr_data(1) and decoded_wr_biten(1)); + load_next_c := '1'; + elsif hwif_in.rx_frame_sync_status.frame_buffer_overflow.we then -- HW Write - we + next_c := hwif_in.rx_frame_sync_status.frame_buffer_overflow.next_q; + load_next_c := '1'; + end if; + field_combo.rx_frame_sync_status.frame_buffer_overflow.next_q <= next_c; + field_combo.rx_frame_sync_status.frame_buffer_overflow.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.rx_frame_sync_status.frame_buffer_overflow.value <= '0'; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.rx_frame_sync_status.frame_buffer_overflow.value <= '0'; + else + if field_combo.rx_frame_sync_status.frame_buffer_overflow.load_next then + field_storage.rx_frame_sync_status.frame_buffer_overflow.value <= field_combo.rx_frame_sync_status.frame_buffer_overflow.next_q; + end if; + end if; + end if; + end process; + + -- Field: msk_top_regs.rx_frame_sync_status.frames_received + process(all) + variable next_c: std_logic_vector(23 downto 0); + variable load_next_c: std_logic; + begin + next_c := field_storage.rx_frame_sync_status.frames_received.value; + load_next_c := '0'; + if decoded_reg_strb.rx_frame_sync_status and decoded_req_is_wr then -- SW write + next_c := (field_storage.rx_frame_sync_status.frames_received.value and not decoded_wr_biten(25 downto 2)) or (decoded_wr_data(25 downto 2) and decoded_wr_biten(25 downto 2)); + load_next_c := '1'; + elsif hwif_in.rx_frame_sync_status.frames_received.we then -- HW Write - we + next_c := hwif_in.rx_frame_sync_status.frames_received.next_q; + load_next_c := '1'; + end if; + field_combo.rx_frame_sync_status.frames_received.next_q <= next_c; + field_combo.rx_frame_sync_status.frames_received.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.rx_frame_sync_status.frames_received.value <= 24x"0"; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.rx_frame_sync_status.frames_received.value <= 24x"0"; + else + if field_combo.rx_frame_sync_status.frames_received.load_next then + field_storage.rx_frame_sync_status.frames_received.value <= field_combo.rx_frame_sync_status.frames_received.next_q; + end if; + end if; + end if; + end process; + hwif_out.rx_frame_sync_status.frames_received.swmod <= decoded_reg_strb.rx_frame_sync_status and decoded_req_is_wr and or_reduce(decoded_wr_biten(25 downto 2)); + + -- Field: msk_top_regs.rx_frame_sync_status.frame_sync_errors + process(all) + variable next_c: std_logic_vector(5 downto 0); + variable load_next_c: std_logic; + begin + next_c := field_storage.rx_frame_sync_status.frame_sync_errors.value; + load_next_c := '0'; + if decoded_reg_strb.rx_frame_sync_status and decoded_req_is_wr then -- SW write + next_c := (field_storage.rx_frame_sync_status.frame_sync_errors.value and not decoded_wr_biten(31 downto 26)) or (decoded_wr_data(31 downto 26) and decoded_wr_biten(31 downto 26)); + load_next_c := '1'; + elsif hwif_in.rx_frame_sync_status.frame_sync_errors.we then -- HW Write - we + next_c := hwif_in.rx_frame_sync_status.frame_sync_errors.next_q; + load_next_c := '1'; + end if; + field_combo.rx_frame_sync_status.frame_sync_errors.next_q <= next_c; + field_combo.rx_frame_sync_status.frame_sync_errors.load_next <= load_next_c; + end process; + process(clk) begin + if false then -- async reset + field_storage.rx_frame_sync_status.frame_sync_errors.value <= 6x"0"; + elsif rising_edge(clk) then + if rst then -- sync reset + field_storage.rx_frame_sync_status.frame_sync_errors.value <= 6x"0"; + else + if field_combo.rx_frame_sync_status.frame_sync_errors.load_next then + field_storage.rx_frame_sync_status.frame_sync_errors.value <= field_combo.rx_frame_sync_status.frame_sync_errors.next_q; + end if; + end if; + end if; + end process; + hwif_out.rx_frame_sync_status.frame_sync_errors.swmod <= decoded_reg_strb.rx_frame_sync_status and decoded_req_is_wr and or_reduce(decoded_wr_biten(31 downto 26)); + ---------------------------------------------------------------------------- -- Write response ---------------------------------------------------------------------------- @@ -2940,6 +3123,10 @@ begin readback_array(35)(31 downto 23) <= (others => '0'); readback_array(36)(31 downto 0) <= field_storage.tx_async_fifo_rd_wr_ptr.data.value when (decoded_reg_strb.tx_async_fifo_rd_wr_ptr and not decoded_req_is_wr) else (others => '0'); readback_array(37)(31 downto 0) <= field_storage.rx_async_fifo_rd_wr_ptr.data.value when (decoded_reg_strb.rx_async_fifo_rd_wr_ptr and not decoded_req_is_wr) else (others => '0'); + readback_array(38)(0 downto 0) <= to_std_logic_vector(field_storage.rx_frame_sync_status.frame_sync_locked.value) when (decoded_reg_strb.rx_frame_sync_status and not decoded_req_is_wr) else (others => '0'); + readback_array(38)(1 downto 1) <= to_std_logic_vector(field_storage.rx_frame_sync_status.frame_buffer_overflow.value) when (decoded_reg_strb.rx_frame_sync_status and not decoded_req_is_wr) else (others => '0'); + readback_array(38)(25 downto 2) <= field_storage.rx_frame_sync_status.frames_received.value when (decoded_reg_strb.rx_frame_sync_status and not decoded_req_is_wr) else (others => '0'); + readback_array(38)(31 downto 26) <= field_storage.rx_frame_sync_status.frame_sync_errors.value when (decoded_reg_strb.rx_frame_sync_status and not decoded_req_is_wr) else (others => '0'); -- Reduce the array process(all) diff --git a/rdl/outputs/rtl/msk_top_regs_pkg.vhd b/rdl/outputs/rtl/msk_top_regs_pkg.vhd index 8634115..a4ca55e 100644 --- a/rdl/outputs/rtl/msk_top_regs_pkg.vhd +++ b/rdl/outputs/rtl/msk_top_regs_pkg.vhd @@ -9,7 +9,7 @@ package msk_top_regs_pkg is constant MSK_TOP_REGS_DATA_WIDTH : positive := 32; constant MSK_TOP_REGS_MIN_ADDR_WIDTH : positive := 8; - constant MSK_TOP_REGS_SIZE : positive := 152; + constant MSK_TOP_REGS_SIZE : positive := 156; type \msk_top_regs.msk_stat_0.demod_sync_lock_in_t\ is record next_q : std_logic; @@ -160,6 +160,32 @@ package msk_top_regs_pkg is data : \msk_top_regs.status_reg_data_8a67e1fe_desc_8a90eed1_name_8a90eed1.data_desc_a6882ec4_in_t\; end record; + type \msk_top_regs.frame_sync_status.frame_sync_locked_in_t\ is record + next_q : std_logic; + end record; + + type \msk_top_regs.frame_sync_status.frame_buffer_overflow_in_t\ is record + next_q : std_logic; + we : std_logic; + end record; + + type \msk_top_regs.frame_sync_status.frames_received_in_t\ is record + next_q : std_logic_vector(23 downto 0); + we : std_logic; + end record; + + type \msk_top_regs.frame_sync_status.frame_sync_errors_in_t\ is record + next_q : std_logic_vector(5 downto 0); + we : std_logic; + end record; + + type \msk_top_regs.frame_sync_status_in_t\ is record + frame_sync_locked : \msk_top_regs.frame_sync_status.frame_sync_locked_in_t\; + frame_buffer_overflow : \msk_top_regs.frame_sync_status.frame_buffer_overflow_in_t\; + frames_received : \msk_top_regs.frame_sync_status.frames_received_in_t\; + frame_sync_errors : \msk_top_regs.frame_sync_status.frame_sync_errors_in_t\; + end record; + type msk_top_regs_in_t is record MSK_Status : \msk_top_regs.msk_stat_0_in_t\; Tx_Bit_Count : \msk_top_regs.msk_stat_1_in_t\; @@ -176,6 +202,7 @@ package msk_top_regs_pkg is rx_power : \msk_top_regs.rx_power_in_t\; tx_async_fifo_rd_wr_ptr : \msk_top_regs.status_reg_data_8a67e1fe_desc_aa4ec676_name_aa4ec676_in_t\; rx_async_fifo_rd_wr_ptr : \msk_top_regs.status_reg_data_8a67e1fe_desc_8a90eed1_name_8a90eed1_in_t\; + rx_frame_sync_status : \msk_top_regs.frame_sync_status_in_t\; end record; type \msk_top_regs.msk_init.txrxinit_out_t\ is record @@ -540,6 +567,19 @@ package msk_top_regs_pkg is data : \msk_top_regs.status_reg_data_8a67e1fe_desc_8a90eed1_name_8a90eed1.data_desc_a6882ec4_out_t\; end record; + type \msk_top_regs.frame_sync_status.frames_received_out_t\ is record + swmod : std_logic; + end record; + + type \msk_top_regs.frame_sync_status.frame_sync_errors_out_t\ is record + swmod : std_logic; + end record; + + type \msk_top_regs.frame_sync_status_out_t\ is record + frames_received : \msk_top_regs.frame_sync_status.frames_received_out_t\; + frame_sync_errors : \msk_top_regs.frame_sync_status.frame_sync_errors_out_t\; + end record; + type msk_top_regs_out_t is record MSK_Init : \msk_top_regs.msk_init_out_t\; MSK_Control : \msk_top_regs.msk_ctrl_out_t\; @@ -576,5 +616,6 @@ package msk_top_regs_pkg is rx_power : \msk_top_regs.rx_power_out_t\; tx_async_fifo_rd_wr_ptr : \msk_top_regs.status_reg_data_8a67e1fe_desc_aa4ec676_name_aa4ec676_out_t\; rx_async_fifo_rd_wr_ptr : \msk_top_regs.status_reg_data_8a67e1fe_desc_8a90eed1_name_8a90eed1_out_t\; + rx_frame_sync_status : \msk_top_regs.frame_sync_status_out_t\; end record; end package; diff --git a/rdl/src/msk_top_regs.rdl b/rdl/src/msk_top_regs.rdl index 6437efd..b1ec87d 100644 --- a/rdl/src/msk_top_regs.rdl +++ b/rdl/src/msk_top_regs.rdl @@ -552,6 +552,48 @@ addrmap msk_top_regs { } data[31:0] = 0; }; + reg frame_sync_status { + name = "Frame Sync Status"; + //desc = "Frame Sync Status"; + regwidth = 32; + field { + name = "Frame Sync Lock"; + desc = "0 - Frame sync not locked + 1 - Frame sync locked"; + fieldwidth = 1; + sw = r; + hw = w; + } frame_sync_locked = 0; + field { + name = "Frame Buffer Overflow"; + desc = "0 - Normal operation + 1 - Buffer overflow"; + fieldwidth = 1; + sw = r; + hw = w; + we = true; + rclr = true; + } frame_buffer_overflow = 0; + field { + name = "Frames Received"; + desc = "Count of frames received since last read. Value is 0x00_0000 to 0xFF_FFFF"; + fieldwidth = 24; + sw = rw; + hw = w; + swmod = true; + we = true; + } frames_received = 0; + field { + name = "Frames Sync Errors"; + desc = "Count of frame sync errors since last read. Value is 0 to 63. This field will saturate at 63 if more than 63 occur."; + fieldwidth = 6; + sw = rw; + hw = w; + swmod = true; + we = true; + } frame_sync_errors = 0; + }; + msk_hash_lo Hash_ID_Low; msk_hash_hi Hash_ID_High; @@ -685,4 +727,6 @@ addrmap msk_top_regs { [*] Read the register [/list]"; + frame_sync_status rx_frame_sync_status; + }; diff --git a/sim/msk_test.py b/sim/msk_test.py index 0b45ed9..7792c44 100755 --- a/sim/msk_test.py +++ b/sim/msk_test.py @@ -849,6 +849,9 @@ async def msk_test_1(dut): await regs.rx_power.write(0) data = await regs.rx_power.read() print("Rx Power", hex(data)) + await regs.rx_frame_sync_status.write(0xFFFF_0000) + data = await regs.rx_frame_sync_status.read() + print("Frame Sync Status", hex(data)) #data = await regs.read("msk_top_regs", "LPF_Accum_F1") # print("F1 Acc: ", hex(data)) # data = await regs.read("msk_top_regs", "LPF_Accum_F2") diff --git a/src/msk_top.vhd b/src/msk_top.vhd index d030c48..47506cd 100644 --- a/src/msk_top.vhd +++ b/src/msk_top.vhd @@ -496,7 +496,7 @@ BEGIN m_axis_tlast => sync_det_tlast, -- Frame synchronization signals - frame_sync_locked => rx_frame_sync_locked, + frame_sync_locked => rx_frame_sync_locked, frames_received => rx_frames_count, frame_sync_errors => rx_frame_sync_errors, frame_buffer_overflow => rx_frame_buffer_overflow, @@ -780,6 +780,11 @@ BEGIN f2_nco_adjust => f2_nco_adjust, f1_error => f1_error, f2_error => f2_error, + pd_power => pd_power, + rx_frame_sync => rx_frame_sync_locked, + rx_frame_buffer_ovf => rx_frame_buffer_overflow, + rx_frame_count => rx_frames_count(23 DOWNTO 0), + rx_frame_sync_err => rx_frame_sync_errors(5 DOWNTO 0), tx_async_fifo_wr_ptr => tx_async_fifo_wr_ptr, tx_async_fifo_rd_ptr => tx_async_fifo_rd_ptr, tx_async_fifo_status_req => tx_async_fifo_status_req, @@ -825,8 +830,7 @@ BEGIN tx_sync_f1 => tx_sync_f1, tx_sync_f2 => tx_sync_f2, pd_alpha1 => pd_alpha1, - pd_alpha2 => pd_alpha2, - pd_power => pd_power + pd_alpha2 => pd_alpha2 ); END ARCHITECTURE struct; diff --git a/src/msk_top_csr.vhd b/src/msk_top_csr.vhd index 830c1c8..e91a01e 100644 --- a/src/msk_top_csr.vhd +++ b/src/msk_top_csr.vhd @@ -128,6 +128,11 @@ ENTITY msk_top_csr IS f2_nco_adjust : IN std_logic_vector(31 DOWNTO 0); f1_error : IN std_logic_vector(31 DOWNTO 0); f2_error : IN std_logic_vector(31 DOWNTO 0); + pd_power : IN std_logic_vector(22 DOWNTO 0); + rx_frame_sync : IN std_logic; + rx_frame_buffer_ovf : IN std_logic; + rx_frame_count : IN std_logic_vector(23 DOWNTO 0); + rx_frame_sync_err : IN std_logic_vector( 5 DOWNTO 0); tx_async_fifo_wr_ptr : IN std_logic_vector(FIFO_ADDR_WIDTH DOWNTO 0); tx_async_fifo_rd_ptr : IN std_logic_vector(FIFO_ADDR_WIDTH DOWNTO 0); @@ -175,8 +180,7 @@ ENTITY msk_top_csr IS tx_sync_f1 : out std_logic; tx_sync_f2 : out std_logic; pd_alpha1 : out std_logic_vector(17 DOWNTO 0); - pd_alpha2 : out std_logic_vector(17 DOWNTO 0); - pd_power : in std_logic_vector(22 DOWNTO 0) + pd_alpha2 : out std_logic_vector(17 DOWNTO 0) ); END ENTITY msk_top_csr; @@ -249,6 +253,9 @@ ARCHITECTURE rtl OF msk_top_csr IS SIGNAL pd_power_req : std_logic; SIGNAL axis_xfer_count_req : std_logic; + SIGNAL frames_received_req : std_logic; + SIGNAL frame_sync_errors_req: std_logic; + BEGIN s_axil_i.AWVALID <= s_axi_awvalid; @@ -294,10 +301,14 @@ BEGIN END IF; END PROCESS csr_init_proc; - ulck_s: cdc_resync PORT MAP (s_axi_aclk, NOT s_axi_aresetn, '0', hwif_in.MSK_Status.demod_sync_lock.next_q); - utxe_s: cdc_resync PORT MAP (s_axi_aclk, NOT s_axi_aresetn, tx_enable, hwif_in.MSK_Status.tx_enable.next_q); - urxe_s: cdc_resync PORT MAP (s_axi_aclk, NOT s_axi_aresetn, rx_enable, hwif_in.MSK_Status.rx_enable.next_q); + ulck_s: cdc_resync PORT MAP (s_axi_aclk, NOT s_axi_aresetn, '0', hwif_in.MSK_Status.demod_sync_lock.next_q); + utxe_s: cdc_resync PORT MAP (s_axi_aclk, NOT s_axi_aresetn, tx_enable, hwif_in.MSK_Status.tx_enable.next_q); + urxe_s: cdc_resync PORT MAP (s_axi_aclk, NOT s_axi_aresetn, rx_enable, hwif_in.MSK_Status.rx_enable.next_q); + urfl_s: cdc_resync PORT MAP (s_axi_aclk, NOT s_axi_aresetn, rx_frame_sync, hwif_in.rx_frame_sync_status.frame_sync_locked.next_q); + + urfo_s: cdc_resync PORT MAP (s_axi_aclk, NOT s_axi_aresetn, rx_frame_buffer_ovf, hwif_in.rx_frame_sync_status.frame_buffer_overflow.we); + hwif_in.MSK_Status.rx_enable.next_q <= '1'; hwif_in.MSK_Status.tx_axis_valid.next_q <= tx_axis_valid; -- Status Request from AXI to MDM @@ -313,6 +324,8 @@ BEGIN utlp1_r: pulse_detect PORT MAP (clk, csr_init, hwif_out.LPF_Accum_F1.data.swmod, lpf_accum_f1_req ); utlp2_r: pulse_detect PORT MAP (clk, csr_init, hwif_out.LPF_Accum_F2.data.swmod, lpf_accum_f2_req ); utpwr_r: pulse_detect PORT MAP (clk, csr_init, hwif_out.rx_power.data.swmod, pd_power_req ); + utfss_r: pulse_detect PORT MAP (clk, csr_init, hwif_out.rx_frame_sync_status.frames_received.swmod, frames_received_req ); + utfsr_r: pulse_detect PORT MAP (clk, csr_init, hwif_out.rx_frame_sync_status.frame_sync_errors.swmod, frame_sync_errors_req ); -- Status acknowledge from MDM to AXI utbc_a : pulse_detect PORT MAP (s_axi_aclk, NOT s_axi_aresetn, tx_bit_counter_req, hwif_in.Tx_Bit_Count.data.we ); @@ -327,6 +340,8 @@ BEGIN utlp1_a: pulse_detect PORT MAP (s_axi_aclk, NOT s_axi_aresetn, lpf_accum_f1_req, hwif_in.LPF_Accum_F1.data.we ); utlp2_a: pulse_detect PORT MAP (s_axi_aclk, NOT s_axi_aresetn, lpf_accum_f2_req, hwif_in.LPF_Accum_F2.data.we ); utpwr_a: pulse_detect PORT MAP (s_axi_aclk, NOT s_axi_aresetn, pd_power_req, hwif_in.rx_power.data.we ); + utfss_a: pulse_detect PORT MAP (s_axi_aclk, NOT s_axi_aresetn, frames_received_req, hwif_in.rx_frame_sync_status.frames_received.we ); + utfsr_a: pulse_detect PORT MAP (s_axi_aclk, NOT s_axi_aresetn, frame_sync_errors_req, hwif_in.rx_frame_sync_status.frame_sync_errors.we ); -- Status capture from MDM to AXI utbc_c : data_capture PORT MAP (clk, csr_init, tx_bit_counter_req, tx_bit_counter, hwif_in.Tx_Bit_Count.data.next_q ); @@ -342,6 +357,10 @@ BEGIN utlp2_c: data_capture PORT MAP (clk, csr_init, lpf_accum_f2_req, lpf_accum_f2, hwif_in.LPF_Accum_F2.data.next_q ); utpwr_c: data_capture GENERIC MAP (23) PORT MAP (clk, csr_init, pd_power_req, pd_power, hwif_in.rx_power.data.next_q ); + utfsc_c: data_capture GENERIC MAP (24) + PORT MAP (clk, csr_init, frames_received_req, rx_frame_count, hwif_in.rx_frame_sync_status.frames_received.next_q ); + utfse_c: data_capture GENERIC MAP (6) + PORT MAP (clk, csr_init, frame_sync_errors_req, rx_frame_sync_err, hwif_in.rx_frame_sync_status.frame_sync_errors.next_q ); -- FIFO status reads rx_async_fifo_status_req <= hwif_out.rx_async_fifo_rd_wr_ptr.data.swmod; From 19c15f17577f893c29ef51d990434172324d3d49 Mon Sep 17 00:00:00 2001 From: Matthew Wishek Date: Wed, 12 Nov 2025 22:38:44 -0700 Subject: [PATCH 34/60] rdl: update outputs --- ...d5d50d18610dbbfe8e1803c2e8d1c73b5a100.html | 4 +- rdl/outputs/docs/html/index.html | 6 +- rdl/outputs/docs/msk_top_regs.docx | Bin 41861 -> 41860 bytes rdl/outputs/docs/msk_top_regs.md | 12 +-- rdl/outputs/docs/msk_top_regs.pdf | Bin 117408 -> 117366 bytes .../msk_top_regs/reg_model/msk_top_regs.py | 78 +++++++-------- .../msk_top_regs/tests/test_msk_top_regs.py | 84 +--------------- .../tests/test_sim_msk_top_regs.py | 94 ------------------ rdl/outputs/rtl/msk_top_regs.vhd | 47 +-------- 9 files changed, 55 insertions(+), 270 deletions(-) diff --git a/rdl/outputs/docs/html/content/9d2d5d50d18610dbbfe8e1803c2e8d1c73b5a100.html b/rdl/outputs/docs/html/content/9d2d5d50d18610dbbfe8e1803c2e8d1c73b5a100.html index 52f0bd5..e1c4393 100644 --- a/rdl/outputs/docs/html/content/9d2d5d50d18610dbbfe8e1803c2e8d1c73b5a100.html +++ b/rdl/outputs/docs/html/content/9d2d5d50d18610dbbfe8e1803c2e8d1c73b5a100.html @@ -69,7 +69,7 @@

Contents

[1] frame_buffer_overflow - rw, rclr + r, rclr 0x0 @@ -89,7 +89,7 @@

Contents

[0] frame_sync_locked - rw + r 0x0 diff --git a/rdl/outputs/docs/html/index.html b/rdl/outputs/docs/html/index.html index b7fb4d4..8fdb151 100644 --- a/rdl/outputs/docs/html/index.html +++ b/rdl/outputs/docs/html/index.html @@ -14,7 +14,7 @@ - - + + diff --git a/rdl/outputs/docs/msk_top_regs.docx b/rdl/outputs/docs/msk_top_regs.docx index 5559d204a8f9e4eb0773419b179f5c1a3f98da56..ac6b82d76b9237cebc39d6873715a18c399a53a7 100644 GIT binary patch delta 948 zcmZoY&eU?8i6_9DnMH(wfq{cz>6VQ=M;MuwZrOZ^Q65ZxW|{`3yII7Uc$aR;iS|-B zv|@!A14IAj^=x{g^&jh&+}iB^aND*Sv2s5=BXyP-|AUB-_&Q%8 zllNSbICU3}8*_nZ0`)Bk?+D}CAYy1RGrv5WsAOFstvJrQ%)-Xcrx z?TmM^vHvvWe}=t2&=bo3>iyxz%|$LTF}25b$)4mY{d=IU_4UE6Rn>P4@_+kyna!!4 zGjYqemkyH68oBqjow+^5FtWPZbkeijn=xmM7OtC?S@l=8*fMdW+{~<-ChFoL$GlGe zU96bJkh?bV-jl^YlS6+u@gQ3Zj2DzhMT^ z&)W^a@{*ksnLzwC-QU@O^yHO9M8(cG z2T{}J+k&X8^KDSm%4E3(M)IK4lh+_EWW>n8aGHgIK?a!QV4#69e{%i;ZII?U3uG8? zPu{se4#c^+K!&N>Z}JR38NL8-MkWzvSUR1oxKM`i&1AcU3Ls?(K+dhnwF{NOmi)F{ zP@K%f!0?-kfk6mn1CVZD?4oQl(TR>6@TCR@xt|`$BN&}u01?CjDuZJaJzA!fR5aAk*ehNscgmX`F=4hUR>}Y z(X8t;???UP%5U75y>r5>TI+6R1eEhX4Uapxw>zi8m~;Oe&yZ7@_x{#Dapc>$@Rhye zC8<~c_b}Yeh+})r>al(1z0Dpw7adE_nc{65o_BP?N(sl$GZbtSj3lp{e~U43Im+Dq z>dyVHTZi`rE?;waN|RWLclq;-|GckwGj1wKUDk1C^4|MuqJqxV=N-#3PVCUMJMpzz z?6|UBz2`!Oje8!fIvsOi$?9X1d%xA+yr}>C?c7(FSg(sqyZ0{syZP0lrN1Wb+*Mz2 z#pagb-QBzX1loOCd#zD&E#H;0qY+!+tv$Ijw`(SE`t~hLY>4T!S-7nu1ME_`h z!wjOIwHtutB|0ZEf%vPtzq0}9$x9|(15q`Tzk@_er-*`8^-P@!)}=o46DvqsdcHk~ zikWW?qNdKb1yNV#+n^?v$+8QKKoWrqWEcx3=Pl3%ab^QKcP8&xAP3^y0CH+3e_fyn z;wUVXVSGE;cA)}@6A$Fvo?Np~8N^u#{iaaP~&TFu`z8sj0 z*%%oZgn={+G%(Jb?6^ot0i?$6)YGebffDLKHF7WoK)QjkaPs7y$qIY{-i%Bl%&^=r zdE+7(#;nQb7O8`6m~f%JGn<)#p;MHBK?p^6<7AP=ieNR1PFzdh%gVseqQJl)j-p0p Na>!yWHoo~FK>%&$dHDbU diff --git a/rdl/outputs/docs/msk_top_regs.md b/rdl/outputs/docs/msk_top_regs.md index c020bbc..c3a221c 100644 --- a/rdl/outputs/docs/msk_top_regs.md +++ b/rdl/outputs/docs/msk_top_regs.md @@ -855,12 +855,12 @@ Bits 15:00 - read pointer (12-bits)

- Base Offset: 0x98 - Size: 0x4 -| Bits| Identifier | Access |Reset| Name | -|-----|---------------------|--------|-----|---------------------| -| 0 | frame_sync_locked | rw | 0x0 | Frame Sync Lock | -| 1 |frame_buffer_overflow|rw, rclr| 0x0 |Frame Buffer Overflow| -| 25:2| frames_received | rw | 0x0 | Frames Received | -|31:26| frame_sync_errors | rw | 0x0 | Frames Sync Errors | +| Bits| Identifier | Access|Reset| Name | +|-----|---------------------|-------|-----|---------------------| +| 0 | frame_sync_locked | r | 0x0 | Frame Sync Lock | +| 1 |frame_buffer_overflow|r, rclr| 0x0 |Frame Buffer Overflow| +| 25:2| frames_received | rw | 0x0 | Frames Received | +|31:26| frame_sync_errors | rw | 0x0 | Frames Sync Errors | #### frame_sync_locked field diff --git a/rdl/outputs/docs/msk_top_regs.pdf b/rdl/outputs/docs/msk_top_regs.pdf index 60c703c84fe3af9c951733d32e82e46113b1bf36..9821309b7b3651ac953d1596086f3c0b93c34422 100644 GIT binary patch delta 15913 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zC*!Zof__THicyRF-RGG=@PUMHiWo^QrslkA;YBb=0zMDgan$(oxP+#{xlw$!4o_wO0wi16O_O#)SaqbFnujKHihr9BZ1xQVaaLQvhT2kqA_N-Z9mLpxfFVjRm zA}R&7fyCjdSZb(!I6jmJD9Hs}Q2n7L>7zBNc3b|=fO=P?{9hs@$sJax^Ww1RGRkRF zSXmOKn*2zLYY^BO7``DALN_5h`Cuw75N6z~M?mgFB>zS!e_3|E@byF*yqfFnuuukQe|ig)oKw?MscqUH+c9D7lZUtUQuK5`xSxQ}TRE`y4#Q%$g2(qF!3|FY-*cMAQ#9&HG= zQVX^cc(MmHfP;&TJH5IOoaBElTW0#ekD*lg*x9+bd3gbBeA1HK03Kd|l(Zx-FON7E zfJ=&tn@dudOz{7=#1Mg1(bCD!-$}1I}oQT@}t%i?h`C11~fdUnrT&5z`?Y zd<8<^lrW}OMf$p-{kyp8Oy^=SZ{7cOE4KonHypgt)C zTZnJJwY;(K0`aY%o)_7AhshwME(RHBY&XoC9f9bA&e8{^*l*bip}otZXo>VuLue2| z=z{6g=h!+g?m5~OlmC~i9TjzlTrhY9ki&MHtsn_87LzFQn3yT4R6vs$zm^XPlFsht z=Ro-=!FSLdmaUJbcp9UPB7}&)pdM zA;?XVuK==on)k8NN+pLI;(s3er&>G&-#j*x4eI|YLnoMO{oYzb3BG9d^xra0t30WH zFK&3IAk`Fp#!JkVe*IG(`iJ str: -class msk_top_regs_frame_sync_status_frame_buffer_overflow_cls(FieldAsyncReadWrite): +class msk_top_regs_frame_sync_status_frame_buffer_overflow_cls(FieldAsyncReadOnly): """ Class to represent a register field in the register model @@ -195,7 +195,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_frame_sync_status_frame_sync_locked_cls(FieldAsyncReadWrite): +class msk_top_regs_frame_sync_status_frame_sync_locked_cls(FieldAsyncReadOnly): """ Class to represent a register field in the register model @@ -648,7 +648,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_status_reg_data_desc_a6882ec4_0x0x10447444_cls(FieldAsyncReadWrite): +class msk_top_regs_status_reg_data_desc_a6882ec4_0x0x1101989e_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -721,7 +721,7 @@ def __init__(self, # build the field attributes - self.__data:msk_top_regs_status_reg_data_desc_a6882ec4_0x0x10447444_cls = msk_top_regs_status_reg_data_desc_a6882ec4_0x0x10447444_cls( + self.__data:msk_top_regs_status_reg_data_desc_a6882ec4_0x0x1101989e_cls = msk_top_regs_status_reg_data_desc_a6882ec4_0x0x1101989e_cls( parent_register=self, size_props=FieldSizeProps( width=32, @@ -752,7 +752,7 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field # build the properties for the fields @property - def data(self) -> msk_top_regs_status_reg_data_desc_a6882ec4_0x0x10447444_cls: + def data(self) -> msk_top_regs_status_reg_data_desc_a6882ec4_0x0x1101989e_cls: """ Property to access data field of the register @@ -792,7 +792,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_status_reg_data_desc_a6882ec4_0x0x10447444_cls: + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_status_reg_data_desc_a6882ec4_0x0x1101989e_cls: return super().get_child_by_system_rdl_name(name) @@ -1162,7 +1162,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_lowpass_ema_alpha_alpha_0x0x1042fd22_cls(FieldAsyncReadWrite): +class msk_top_regs_lowpass_ema_alpha_alpha_0x0x110198d4_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -1200,7 +1200,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_lowpass_ema_alpha_0x0x1042fd73_cls(RegAsyncReadWrite): +class msk_top_regs_lowpass_ema_alpha_0x0x1101991f_cls(RegAsyncReadWrite): """ Class to represent a register in the register model @@ -1237,7 +1237,7 @@ def __init__(self, # build the field attributes - self.__alpha:msk_top_regs_lowpass_ema_alpha_alpha_0x0x1042fd22_cls = msk_top_regs_lowpass_ema_alpha_alpha_0x0x1042fd22_cls( + self.__alpha:msk_top_regs_lowpass_ema_alpha_alpha_0x0x110198d4_cls = msk_top_regs_lowpass_ema_alpha_alpha_0x0x110198d4_cls( parent_register=self, size_props=FieldSizeProps( width=18, @@ -1268,7 +1268,7 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field # build the properties for the fields @property - def alpha(self) -> msk_top_regs_lowpass_ema_alpha_alpha_0x0x1042fd22_cls: + def alpha(self) -> msk_top_regs_lowpass_ema_alpha_alpha_0x0x110198d4_cls: """ Property to access alpha field of the register @@ -1307,7 +1307,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_lowpass_ema_alpha_alpha_0x0x1042fd22_cls: + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_lowpass_ema_alpha_alpha_0x0x110198d4_cls: return super().get_child_by_system_rdl_name(name) @@ -3278,7 +3278,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_stat_32_lpf_acc_data_0x0x10427b77_cls(FieldAsyncReadWrite): +class msk_top_regs_stat_32_lpf_acc_data_0x0x10797426_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -3356,7 +3356,7 @@ def __init__(self, # build the field attributes - self.__data:msk_top_regs_stat_32_lpf_acc_data_0x0x10427b77_cls = msk_top_regs_stat_32_lpf_acc_data_0x0x10427b77_cls( + self.__data:msk_top_regs_stat_32_lpf_acc_data_0x0x10797426_cls = msk_top_regs_stat_32_lpf_acc_data_0x0x10797426_cls( parent_register=self, size_props=FieldSizeProps( width=32, @@ -3387,7 +3387,7 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field # build the properties for the fields @property - def data(self) -> msk_top_regs_stat_32_lpf_acc_data_0x0x10427b77_cls: + def data(self) -> msk_top_regs_stat_32_lpf_acc_data_0x0x10797426_cls: """ Property to access data field of the register @@ -3429,7 +3429,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_stat_32_lpf_acc_data_0x0x10427b77_cls: + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_stat_32_lpf_acc_data_0x0x10797426_cls: return super().get_child_by_system_rdl_name(name) @@ -5050,7 +5050,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_data_width_data_width_0x0x10443038_cls(FieldAsyncReadWrite): +class msk_top_regs_data_width_data_width_0x0x1079ec62_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -5126,7 +5126,7 @@ def __init__(self, # build the field attributes - self.__data_width:msk_top_regs_data_width_data_width_0x0x10443038_cls = msk_top_regs_data_width_data_width_0x0x10443038_cls( + self.__data_width:msk_top_regs_data_width_data_width_0x0x1079ec62_cls = msk_top_regs_data_width_data_width_0x0x1079ec62_cls( parent_register=self, size_props=FieldSizeProps( width=8, @@ -5157,7 +5157,7 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field # build the properties for the fields @property - def data_width(self) -> msk_top_regs_data_width_data_width_0x0x10443038_cls: + def data_width(self) -> msk_top_regs_data_width_data_width_0x0x1079ec62_cls: """ Property to access data_width field of the register @@ -5196,7 +5196,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_data_width_data_width_0x0x10443038_cls: + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_data_width_data_width_0x0x1079ec62_cls: return super().get_child_by_system_rdl_name(name) @@ -6046,7 +6046,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_config_nco_fw_config_data_0x0x1044472f_cls(FieldAsyncReadWrite): +class msk_top_regs_config_nco_fw_config_data_0x0x1079c844_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -6123,7 +6123,7 @@ def __init__(self, # build the field attributes - self.__config_data:msk_top_regs_config_nco_fw_config_data_0x0x1044472f_cls = msk_top_regs_config_nco_fw_config_data_0x0x1044472f_cls( + self.__config_data:msk_top_regs_config_nco_fw_config_data_0x0x1079c844_cls = msk_top_regs_config_nco_fw_config_data_0x0x1079c844_cls( parent_register=self, size_props=FieldSizeProps( width=32, @@ -6154,7 +6154,7 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field # build the properties for the fields @property - def config_data(self) -> msk_top_regs_config_nco_fw_config_data_0x0x1044472f_cls: + def config_data(self) -> msk_top_regs_config_nco_fw_config_data_0x0x1079c844_cls: """ Property to access config_data field of the register @@ -6195,7 +6195,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_config_nco_fw_config_data_0x0x1044472f_cls: + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_config_nco_fw_config_data_0x0x1079c844_cls: return super().get_child_by_system_rdl_name(name) @@ -6219,7 +6219,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_config_nco_fw_config_data_0x0x10445a0c_cls(FieldAsyncReadWrite): +class msk_top_regs_config_nco_fw_config_data_0x0x1079621e_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -6296,7 +6296,7 @@ def __init__(self, # build the field attributes - self.__config_data:msk_top_regs_config_nco_fw_config_data_0x0x10445a0c_cls = msk_top_regs_config_nco_fw_config_data_0x0x10445a0c_cls( + self.__config_data:msk_top_regs_config_nco_fw_config_data_0x0x1079621e_cls = msk_top_regs_config_nco_fw_config_data_0x0x1079621e_cls( parent_register=self, size_props=FieldSizeProps( width=32, @@ -6327,7 +6327,7 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field # build the properties for the fields @property - def config_data(self) -> msk_top_regs_config_nco_fw_config_data_0x0x10445a0c_cls: + def config_data(self) -> msk_top_regs_config_nco_fw_config_data_0x0x1079621e_cls: """ Property to access config_data field of the register @@ -6368,7 +6368,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_config_nco_fw_config_data_0x0x10445a0c_cls: + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_config_nco_fw_config_data_0x0x1079621e_cls: return super().get_child_by_system_rdl_name(name) @@ -6392,7 +6392,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_config_nco_fw_config_data_0x0x10445a24_cls(FieldAsyncReadWrite): +class msk_top_regs_config_nco_fw_config_data_0x0x1079636b_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -6469,7 +6469,7 @@ def __init__(self, # build the field attributes - self.__config_data:msk_top_regs_config_nco_fw_config_data_0x0x10445a24_cls = msk_top_regs_config_nco_fw_config_data_0x0x10445a24_cls( + self.__config_data:msk_top_regs_config_nco_fw_config_data_0x0x1079636b_cls = msk_top_regs_config_nco_fw_config_data_0x0x1079636b_cls( parent_register=self, size_props=FieldSizeProps( width=32, @@ -6500,7 +6500,7 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field # build the properties for the fields @property - def config_data(self) -> msk_top_regs_config_nco_fw_config_data_0x0x10445a24_cls: + def config_data(self) -> msk_top_regs_config_nco_fw_config_data_0x0x1079636b_cls: """ Property to access config_data field of the register @@ -6541,7 +6541,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_config_nco_fw_config_data_0x0x10445a24_cls: + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_config_nco_fw_config_data_0x0x1079636b_cls: return super().get_child_by_system_rdl_name(name) @@ -6565,7 +6565,7 @@ def rdl_desc(self) -> str: -class msk_top_regs_config_nco_fw_config_data_0x0x10445a66_cls(FieldAsyncReadWrite): +class msk_top_regs_config_nco_fw_config_data_0x0x11011ef6_cls(FieldAsyncReadWrite): """ Class to represent a register field in the register model @@ -6642,7 +6642,7 @@ def __init__(self, # build the field attributes - self.__config_data:msk_top_regs_config_nco_fw_config_data_0x0x10445a66_cls = msk_top_regs_config_nco_fw_config_data_0x0x10445a66_cls( + self.__config_data:msk_top_regs_config_nco_fw_config_data_0x0x11011ef6_cls = msk_top_regs_config_nco_fw_config_data_0x0x11011ef6_cls( parent_register=self, size_props=FieldSizeProps( width=32, @@ -6673,7 +6673,7 @@ def fields(self) -> Iterator[Union[FieldAsyncReadOnly, FieldAsyncWriteOnly,Field # build the properties for the fields @property - def config_data(self) -> msk_top_regs_config_nco_fw_config_data_0x0x10445a66_cls: + def config_data(self) -> msk_top_regs_config_nco_fw_config_data_0x0x11011ef6_cls: """ Property to access config_data field of the register @@ -6714,7 +6714,7 @@ def systemrdl_python_child_name_map(self) -> dict[str, str]: - def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_config_nco_fw_config_data_0x0x10445a66_cls: + def get_child_by_system_rdl_name(self, name: Any) -> msk_top_regs_config_nco_fw_config_data_0x0x11011ef6_cls: return super().get_child_by_system_rdl_name(name) @@ -8950,7 +8950,7 @@ def __init__(self, *, inst_name='Tx_Sync_Cnt', parent=self) - self.__lowpass_ema_alpha1:msk_top_regs_lowpass_ema_alpha_0x0x1042fd73_cls = msk_top_regs_lowpass_ema_alpha_0x0x1042fd73_cls( + self.__lowpass_ema_alpha1:msk_top_regs_lowpass_ema_alpha_0x0x1101991f_cls = msk_top_regs_lowpass_ema_alpha_0x0x1101991f_cls( address=self.address+132, accesswidth=32, width=32, @@ -9658,7 +9658,7 @@ def Tx_Sync_Cnt(self) -> msk_top_regs_tx_sync_cnt_cls: return self.__Tx_Sync_Cnt @property - def lowpass_ema_alpha1(self) -> msk_top_regs_lowpass_ema_alpha_0x0x1042fd73_cls: + def lowpass_ema_alpha1(self) -> msk_top_regs_lowpass_ema_alpha_0x0x1101991f_cls: """ Property to access lowpass_ema_alpha1 @@ -9928,7 +9928,7 @@ def get_child_by_system_rdl_name(self, name: Literal["Tx_Sync_Cnt"]) -> msk_top_ @overload - def get_child_by_system_rdl_name(self, name: Literal["lowpass_ema_alpha1"]) -> msk_top_regs_lowpass_ema_alpha_0x0x1042fd73_cls: ... + def get_child_by_system_rdl_name(self, name: Literal["lowpass_ema_alpha1"]) -> msk_top_regs_lowpass_ema_alpha_0x0x1101991f_cls: ... @overload @@ -9952,7 +9952,7 @@ def get_child_by_system_rdl_name(self, name: Literal["rx_frame_sync_status"]) -> @overload - def get_child_by_system_rdl_name(self, name: str) -> Union[msk_top_regs_msk_hash_lo_cls, msk_top_regs_msk_hash_hi_cls, msk_top_regs_msk_init_cls, msk_top_regs_msk_ctrl_cls, msk_top_regs_msk_stat_0_cls, msk_top_regs_msk_stat_1_cls, msk_top_regs_msk_stat_2_cls, msk_top_regs_config_nco_fw_desc_c4924cc6_name_0c494469_cls, msk_top_regs_config_nco_fw_desc_94d7aaf5_name_84dd0c1c_cls, msk_top_regs_config_nco_fw_desc_42134a4f_name_d97dbd51_cls, msk_top_regs_config_nco_fw_desc_16fb48c8_name_8d01a20d_cls, msk_top_regs_config_nco_fw_desc_43c0828f_name_bdc60ecf_cls, msk_top_regs_lpf_config_0_cls, msk_top_regs_lpf_config_1_cls, msk_top_regs_data_width_desc_58c848dd_name_2fbd8eba_cls, msk_top_regs_data_width_desc_6097df38_name_4609588b_cls, msk_top_regs_prbs_ctrl_cls, msk_top_regs_config_prbs_seed_cls, msk_top_regs_config_prbs_poly_cls, msk_top_regs_config_prbs_errmask_cls, msk_top_regs_stat_32_bits_cls, msk_top_regs_stat_32_errs_cls, msk_top_regs_stat_32_lpf_acc_desc_8cebc7dc_name_f20c6670_cls, msk_top_regs_stat_32_lpf_acc_desc_dea6bd99_name_758fd0ce_cls, msk_top_regs_msk_stat_3_cls, msk_top_regs_rx_sample_discard_cls, msk_top_regs_lpf_config_2_cls, msk_top_regs_status_reg_data_f53978c8_name_d8ad3b25_cls, msk_top_regs_status_reg_data_05243a4e_name_2c154788_cls, msk_top_regs_status_reg_data_10a2e5b5_name_3b640507_cls, msk_top_regs_status_reg_data_642692cf_name_3de9a0d3_cls, msk_top_regs_tx_sync_ctrl_cls, msk_top_regs_tx_sync_cnt_cls, msk_top_regs_lowpass_ema_alpha_0x0x1042fd73_cls, msk_top_regs_lowpass_ema_alpha_cls, msk_top_regs_rx_power_cls, msk_top_regs_status_reg_data_8a67e1fe_desc_aa4ec676_name_aa4ec676_cls, msk_top_regs_status_reg_data_8a67e1fe_desc_8a90eed1_name_8a90eed1_cls, msk_top_regs_frame_sync_status_cls, ]: ... + def get_child_by_system_rdl_name(self, name: str) -> Union[msk_top_regs_msk_hash_lo_cls, msk_top_regs_msk_hash_hi_cls, msk_top_regs_msk_init_cls, msk_top_regs_msk_ctrl_cls, msk_top_regs_msk_stat_0_cls, msk_top_regs_msk_stat_1_cls, msk_top_regs_msk_stat_2_cls, msk_top_regs_config_nco_fw_desc_c4924cc6_name_0c494469_cls, msk_top_regs_config_nco_fw_desc_94d7aaf5_name_84dd0c1c_cls, msk_top_regs_config_nco_fw_desc_42134a4f_name_d97dbd51_cls, msk_top_regs_config_nco_fw_desc_16fb48c8_name_8d01a20d_cls, msk_top_regs_config_nco_fw_desc_43c0828f_name_bdc60ecf_cls, msk_top_regs_lpf_config_0_cls, msk_top_regs_lpf_config_1_cls, msk_top_regs_data_width_desc_58c848dd_name_2fbd8eba_cls, msk_top_regs_data_width_desc_6097df38_name_4609588b_cls, msk_top_regs_prbs_ctrl_cls, msk_top_regs_config_prbs_seed_cls, msk_top_regs_config_prbs_poly_cls, msk_top_regs_config_prbs_errmask_cls, msk_top_regs_stat_32_bits_cls, msk_top_regs_stat_32_errs_cls, msk_top_regs_stat_32_lpf_acc_desc_8cebc7dc_name_f20c6670_cls, msk_top_regs_stat_32_lpf_acc_desc_dea6bd99_name_758fd0ce_cls, msk_top_regs_msk_stat_3_cls, msk_top_regs_rx_sample_discard_cls, msk_top_regs_lpf_config_2_cls, msk_top_regs_status_reg_data_f53978c8_name_d8ad3b25_cls, msk_top_regs_status_reg_data_05243a4e_name_2c154788_cls, msk_top_regs_status_reg_data_10a2e5b5_name_3b640507_cls, msk_top_regs_status_reg_data_642692cf_name_3de9a0d3_cls, msk_top_regs_tx_sync_ctrl_cls, msk_top_regs_tx_sync_cnt_cls, msk_top_regs_lowpass_ema_alpha_0x0x1101991f_cls, msk_top_regs_lowpass_ema_alpha_cls, msk_top_regs_rx_power_cls, msk_top_regs_status_reg_data_8a67e1fe_desc_aa4ec676_name_aa4ec676_cls, msk_top_regs_status_reg_data_8a67e1fe_desc_8a90eed1_name_8a90eed1_cls, msk_top_regs_frame_sync_status_cls, ]: ... def get_child_by_system_rdl_name(self, name: Any) -> Any: return super().get_child_by_system_rdl_name(name) diff --git a/rdl/outputs/python/msk_top_regs/tests/test_msk_top_regs.py b/rdl/outputs/python/msk_top_regs/tests/test_msk_top_regs.py index 414ee3a..f3025d6 100644 --- a/rdl/outputs/python/msk_top_regs/tests/test_msk_top_regs.py +++ b/rdl/outputs/python/msk_top_regs/tests/test_msk_top_regs.py @@ -11691,42 +11691,6 @@ async def test_int_field_read_and_write(self) -> None: # at the end of the read tests the write should not have been called read_callback_mock.reset_mock() write_callback_mock.assert_not_called() - # check the write - - if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): - raise TypeError('Test can not proceed as the fut is not a writable async field') - - - random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) - random_field_value = random.randrange(0, 0x1 + 1) - for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: - for field_value in [0, 0x1, random_field_value]: - read_callback_mock.reset_mock() - write_callback_mock.reset_mock() - read_callback_mock.return_value = reg_base_value - - await self.dut.rx_frame_sync_status.frame_sync_locked.write(field_value) # type: ignore[union-attr] - - - read_callback_mock.assert_called_once_with( - addr=152, - width=32, - accesswidth=fut.parent_register.accesswidth) - - write_callback_mock.assert_called_once_with( - addr=152, - width=32, - accesswidth=self.dut.rx_frame_sync_status.frame_sync_locked.parent_register.accesswidth, # type: ignore[union-attr] - data=(reg_base_value & 0xFFFFFFFE) | \ - (0x1 & (field_value << 0))) - - - # check invalid write values bounce - with self.assertRaises(ValueError): - await fut.write(0x1 + 1) - - with self.assertRaises(ValueError): - await fut.write(-1) # test access operations (read and/or write) to field: # msk_top_regs.rx_frame_sync_status.frame_buffer_overflow @@ -11775,42 +11739,6 @@ async def test_int_field_read_and_write(self) -> None: # at the end of the read tests the write should not have been called read_callback_mock.reset_mock() write_callback_mock.assert_not_called() - # check the write - - if not isinstance(fut, (FieldAsyncWriteOnly, FieldAsyncReadWrite)): - raise TypeError('Test can not proceed as the fut is not a writable async field') - - - random_reg_value = random.randrange(0, 0xFFFFFFFF + 1) - random_field_value = random.randrange(0, 0x1 + 1) - for reg_base_value in [0, 0xFFFFFFFF, random_reg_value]: - for field_value in [0, 0x1, random_field_value]: - read_callback_mock.reset_mock() - write_callback_mock.reset_mock() - read_callback_mock.return_value = reg_base_value - - await self.dut.rx_frame_sync_status.frame_buffer_overflow.write(field_value) # type: ignore[union-attr] - - - read_callback_mock.assert_called_once_with( - addr=152, - width=32, - accesswidth=fut.parent_register.accesswidth) - - write_callback_mock.assert_called_once_with( - addr=152, - width=32, - accesswidth=self.dut.rx_frame_sync_status.frame_buffer_overflow.parent_register.accesswidth, # type: ignore[union-attr] - data=(reg_base_value & 0xFFFFFFFD) | \ - (0x2 & (field_value << 1))) - - - # check invalid write values bounce - with self.assertRaises(ValueError): - await fut.write(0x1 + 1) - - with self.assertRaises(ValueError): - await fut.write(-1) # test access operations (read and/or write) to field: # msk_top_regs.rx_frame_sync_status.frames_received @@ -15513,9 +15441,7 @@ async def write_field_combinations(reg: RegAsyncReadWrite, writable_fields:list[ ]) with self.subTest(msg='register: msk_top_regs.rx_frame_sync_status'): await write_field_combinations(reg=self.dut.rx_frame_sync_status, - writable_fields = [ 'frame_sync_locked', - 'frame_buffer_overflow', - 'frames_received', + writable_fields = [ 'frames_received', 'frame_sync_errors' ]) @@ -15834,9 +15760,7 @@ async def write_field_combinations(reg: RegAsyncReadWrite, writable_fields:list[ # test read_fields to register: # msk_top_regs.rx_frame_sync_status await write_field_combinations(reg=self.dut.rx_frame_sync_status, - writable_fields = [ 'frame_sync_locked', - 'frame_buffer_overflow', - 'frames_received', + writable_fields = [ 'frames_received', 'frame_sync_errors' ]) @@ -18402,9 +18326,9 @@ def test_traversal_iterators(self) -> None: fields.append(field) self.assertCountEqual(expected_fields, fields) - expected_writable_fields = [self.dut.rx_frame_sync_status.frame_sync_locked, # type: ignore[union-attr,list-item] + expected_writable_fields = [ - self.dut.rx_frame_sync_status.frame_buffer_overflow, # type: ignore[union-attr,list-item] + self.dut.rx_frame_sync_status.frames_received, # type: ignore[union-attr,list-item] diff --git a/rdl/outputs/python/msk_top_regs/tests/test_sim_msk_top_regs.py b/rdl/outputs/python/msk_top_regs/tests/test_sim_msk_top_regs.py index c0ee28a..3cf4d4b 100644 --- a/rdl/outputs/python/msk_top_regs/tests/test_sim_msk_top_regs.py +++ b/rdl/outputs/python/msk_top_regs/tests/test_sim_msk_top_regs.py @@ -8531,53 +8531,6 @@ async def test_field_read_and_write(self) -> None: field_read_callback.assert_not_called() - # register write checks - # update the register value via the backdoor in the simulator, then perform a field - # write and make sure it is updated - inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) - sim_register.value = inital_reg_random_value - - random_field_value = random.randrange(0, 0x1+1) - - await self.dut.rx_frame_sync_status.frame_sync_locked.write(random_field_value) # type: ignore[arg-type] - self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFFE) | (0x1 & (random_field_value << 0))) - - register_write_callback.assert_not_called() - register_read_callback.assert_not_called() - field_write_callback.assert_not_called() - field_read_callback.assert_not_called() - reg_random_value = sim_register.value - # hook up the call backs - sim_register.read_callback = None - sim_register.write_callback = register_write_callback - sim_field.read_callback = None - sim_field.write_callback = field_write_callback - random_field_value = random.randrange(0, 0x1+1) - - await self.dut.rx_frame_sync_status.frame_sync_locked.write(random_field_value) # type: ignore[arg-type] - self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFFE) | (0x1 & (random_field_value << 0))) - register_write_callback.assert_called_once_with(value=(reg_random_value & 0xFFFFFFFE) | (0x1 & (random_field_value << 0))) - field_write_callback.assert_called_once_with(value=random_field_value) - - register_read_callback.assert_not_called() - field_read_callback.assert_not_called() - reg_random_value = sim_register.value - # revert the callbacks and check again - register_write_callback.reset_mock() - register_read_callback.reset_mock() - field_write_callback.reset_mock() - field_read_callback.reset_mock() - sim_register.write_callback = None - sim_field.write_callback = None - random_field_value = random.randrange(0, 0x1+1) - - await self.dut.rx_frame_sync_status.frame_sync_locked.write(random_field_value) # type: ignore[arg-type] - self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFFE) | (0x1 & (random_field_value << 0))) - - register_write_callback.assert_not_called() - register_read_callback.assert_not_called() - field_write_callback.assert_not_called() - field_read_callback.assert_not_called() # test access operations (read and/or write) to register: @@ -8650,53 +8603,6 @@ async def test_field_read_and_write(self) -> None: field_read_callback.assert_not_called() - # register write checks - # update the register value via the backdoor in the simulator, then perform a field - # write and make sure it is updated - inital_reg_random_value = random.randrange(0, 0xFFFFFFFF+1) - sim_register.value = inital_reg_random_value - - random_field_value = random.randrange(0, 0x1+1) - - await self.dut.rx_frame_sync_status.frame_buffer_overflow.write(random_field_value) # type: ignore[arg-type] - self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFFD) | (0x2 & (random_field_value << 1))) - - register_write_callback.assert_not_called() - register_read_callback.assert_not_called() - field_write_callback.assert_not_called() - field_read_callback.assert_not_called() - reg_random_value = sim_register.value - # hook up the call backs - sim_register.read_callback = None - sim_register.write_callback = register_write_callback - sim_field.read_callback = None - sim_field.write_callback = field_write_callback - random_field_value = random.randrange(0, 0x1+1) - - await self.dut.rx_frame_sync_status.frame_buffer_overflow.write(random_field_value) # type: ignore[arg-type] - self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFFD) | (0x2 & (random_field_value << 1))) - register_write_callback.assert_called_once_with(value=(reg_random_value & 0xFFFFFFFD) | (0x2 & (random_field_value << 1))) - field_write_callback.assert_called_once_with(value=random_field_value) - - register_read_callback.assert_not_called() - field_read_callback.assert_not_called() - reg_random_value = sim_register.value - # revert the callbacks and check again - register_write_callback.reset_mock() - register_read_callback.reset_mock() - field_write_callback.reset_mock() - field_read_callback.reset_mock() - sim_register.write_callback = None - sim_field.write_callback = None - random_field_value = random.randrange(0, 0x1+1) - - await self.dut.rx_frame_sync_status.frame_buffer_overflow.write(random_field_value) # type: ignore[arg-type] - self.assertEqual(sim_register.value, (inital_reg_random_value & 0xFFFFFFFD) | (0x2 & (random_field_value << 1))) - - register_write_callback.assert_not_called() - register_read_callback.assert_not_called() - field_write_callback.assert_not_called() - field_read_callback.assert_not_called() # test access operations (read and/or write) to register: diff --git a/rdl/outputs/rtl/msk_top_regs.vhd b/rdl/outputs/rtl/msk_top_regs.vhd index 4bda2d8..952a997 100644 --- a/rdl/outputs/rtl/msk_top_regs.vhd +++ b/rdl/outputs/rtl/msk_top_regs.vhd @@ -549,11 +549,6 @@ architecture rtl of msk_top_regs is data : \msk_top_regs.rx_async_fifo_rd_wr_ptr.data_combo_t\; end record; - type \msk_top_regs.rx_frame_sync_status.frame_sync_locked_combo_t\ is record - next_q : std_logic; - load_next : std_logic; - end record; - type \msk_top_regs.rx_frame_sync_status.frame_buffer_overflow_combo_t\ is record next_q : std_logic; load_next : std_logic; @@ -570,7 +565,6 @@ architecture rtl of msk_top_regs is end record; type \msk_top_regs.rx_frame_sync_status_combo_t\ is record - frame_sync_locked : \msk_top_regs.rx_frame_sync_status.frame_sync_locked_combo_t\; frame_buffer_overflow : \msk_top_regs.rx_frame_sync_status.frame_buffer_overflow_combo_t\; frames_received : \msk_top_regs.rx_frame_sync_status.frames_received_combo_t\; frame_sync_errors : \msk_top_regs.rx_frame_sync_status.frame_sync_errors_combo_t\; @@ -987,10 +981,6 @@ architecture rtl of msk_top_regs is data : \msk_top_regs.rx_async_fifo_rd_wr_ptr.data_storage_t\; end record; - type \msk_top_regs.rx_frame_sync_status.frame_sync_locked_storage_t\ is record - value : std_logic; - end record; - type \msk_top_regs.rx_frame_sync_status.frame_buffer_overflow_storage_t\ is record value : std_logic; end record; @@ -1004,7 +994,6 @@ architecture rtl of msk_top_regs is end record; type \msk_top_regs.rx_frame_sync_status_storage_t\ is record - frame_sync_locked : \msk_top_regs.rx_frame_sync_status.frame_sync_locked_storage_t\; frame_buffer_overflow : \msk_top_regs.rx_frame_sync_status.frame_buffer_overflow_storage_t\; frames_received : \msk_top_regs.rx_frame_sync_status.frames_received_storage_t\; frame_sync_errors : \msk_top_regs.rx_frame_sync_status.frame_sync_errors_storage_t\; @@ -2914,37 +2903,6 @@ begin end process; hwif_out.rx_async_fifo_rd_wr_ptr.data.swmod <= decoded_reg_strb.rx_async_fifo_rd_wr_ptr and decoded_req_is_wr and or_reduce(decoded_wr_biten(31 downto 0)); - -- Field: msk_top_regs.rx_frame_sync_status.frame_sync_locked - process(all) - variable next_c: std_logic; - variable load_next_c: std_logic; - begin - next_c := field_storage.rx_frame_sync_status.frame_sync_locked.value; - load_next_c := '0'; - if decoded_reg_strb.rx_frame_sync_status and decoded_req_is_wr then -- SW write - next_c := (field_storage.rx_frame_sync_status.frame_sync_locked.value and not decoded_wr_biten(0)) or (decoded_wr_data(0) and decoded_wr_biten(0)); - load_next_c := '1'; - else -- HW Write - next_c := hwif_in.rx_frame_sync_status.frame_sync_locked.next_q; - load_next_c := '1'; - end if; - field_combo.rx_frame_sync_status.frame_sync_locked.next_q <= next_c; - field_combo.rx_frame_sync_status.frame_sync_locked.load_next <= load_next_c; - end process; - process(clk) begin - if false then -- async reset - field_storage.rx_frame_sync_status.frame_sync_locked.value <= '0'; - elsif rising_edge(clk) then - if rst then -- sync reset - field_storage.rx_frame_sync_status.frame_sync_locked.value <= '0'; - else - if field_combo.rx_frame_sync_status.frame_sync_locked.load_next then - field_storage.rx_frame_sync_status.frame_sync_locked.value <= field_combo.rx_frame_sync_status.frame_sync_locked.next_q; - end if; - end if; - end if; - end process; - -- Field: msk_top_regs.rx_frame_sync_status.frame_buffer_overflow process(all) variable next_c: std_logic; @@ -2955,9 +2913,6 @@ begin if decoded_reg_strb.rx_frame_sync_status and not decoded_req_is_wr then -- SW clear on read next_c := '0'; load_next_c := '1'; - elsif decoded_reg_strb.rx_frame_sync_status and decoded_req_is_wr then -- SW write - next_c := (field_storage.rx_frame_sync_status.frame_buffer_overflow.value and not decoded_wr_biten(1)) or (decoded_wr_data(1) and decoded_wr_biten(1)); - load_next_c := '1'; elsif hwif_in.rx_frame_sync_status.frame_buffer_overflow.we then -- HW Write - we next_c := hwif_in.rx_frame_sync_status.frame_buffer_overflow.next_q; load_next_c := '1'; @@ -3123,7 +3078,7 @@ begin readback_array(35)(31 downto 23) <= (others => '0'); readback_array(36)(31 downto 0) <= field_storage.tx_async_fifo_rd_wr_ptr.data.value when (decoded_reg_strb.tx_async_fifo_rd_wr_ptr and not decoded_req_is_wr) else (others => '0'); readback_array(37)(31 downto 0) <= field_storage.rx_async_fifo_rd_wr_ptr.data.value when (decoded_reg_strb.rx_async_fifo_rd_wr_ptr and not decoded_req_is_wr) else (others => '0'); - readback_array(38)(0 downto 0) <= to_std_logic_vector(field_storage.rx_frame_sync_status.frame_sync_locked.value) when (decoded_reg_strb.rx_frame_sync_status and not decoded_req_is_wr) else (others => '0'); + readback_array(38)(0 downto 0) <= to_std_logic_vector(hwif_in.rx_frame_sync_status.frame_sync_locked.next_q) when (decoded_reg_strb.rx_frame_sync_status and not decoded_req_is_wr) else (others => '0'); readback_array(38)(1 downto 1) <= to_std_logic_vector(field_storage.rx_frame_sync_status.frame_buffer_overflow.value) when (decoded_reg_strb.rx_frame_sync_status and not decoded_req_is_wr) else (others => '0'); readback_array(38)(25 downto 2) <= field_storage.rx_frame_sync_status.frames_received.value when (decoded_reg_strb.rx_frame_sync_status and not decoded_req_is_wr) else (others => '0'); readback_array(38)(31 downto 26) <= field_storage.rx_frame_sync_status.frame_sync_errors.value when (decoded_reg_strb.rx_frame_sync_status and not decoded_req_is_wr) else (others => '0'); From 6174fd30cc7fda73d1206414f5cdbe1c06a14a69 Mon Sep 17 00:00:00 2001 From: Matthew Wishek Date: Fri, 14 Nov 2025 14:05:07 -0700 Subject: [PATCH 35/60] rdl: update frame sync status register descriptions. --- rdl/src/msk_top_regs.rdl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/rdl/src/msk_top_regs.rdl b/rdl/src/msk_top_regs.rdl index b1ec87d..4ca52f3 100644 --- a/rdl/src/msk_top_regs.rdl +++ b/rdl/src/msk_top_regs.rdl @@ -576,7 +576,7 @@ addrmap msk_top_regs { } frame_buffer_overflow = 0; field { name = "Frames Received"; - desc = "Count of frames received since last read. Value is 0x00_0000 to 0xFF_FFFF"; + desc = "Count of frames received. Value is 0x00_0000 to 0xFF_FFFF. Counter rolls over when max count is reached."; fieldwidth = 24; sw = rw; hw = w; @@ -585,7 +585,7 @@ addrmap msk_top_regs { } frames_received = 0; field { name = "Frames Sync Errors"; - desc = "Count of frame sync errors since last read. Value is 0 to 63. This field will saturate at 63 if more than 63 occur."; + desc = "Count of frame sync errors. Value is 0 to 63. Counter rolls over when max count is reached."; fieldwidth = 6; sw = rw; hw = w; From 628ca20c35ba02dd359bb071b62055e3397dc50b Mon Sep 17 00:00:00 2001 From: Abraxas3d Date: Fri, 14 Nov 2025 18:00:14 -0800 Subject: [PATCH 36/60] Improved reset of FIFO read and write pointers. Works in sim and hardware. --- src/msk_top.vhd | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/msk_top.vhd b/src/msk_top.vhd index 47506cd..ac0e43c 100644 --- a/src/msk_top.vhd +++ b/src/msk_top.vhd @@ -328,7 +328,7 @@ BEGIN ) PORT MAP ( wr_aclk => s_axis_aclk, - wr_aresetn => s_axis_aresetn, + wr_aresetn => s_axis_aresetn AND NOT txinit, -- add software control s_axis_tdata => adapter_tdata, s_axis_tvalid => adapter_tvalid, @@ -528,7 +528,7 @@ BEGIN -- Read side (AXI clock domain) rd_aclk => s_axis_aclk, -- Use system AXI clock - rd_aresetn => s_axis_aresetn, + rd_aresetn => s_axis_aresetn AND NOT rxinit, -- add software control m_axis_tdata => m_axis_tdata(7 DOWNTO 0), m_axis_tvalid => m_axis_tvalid, From 7708fd88a972cf7aaa802365c8f23491109b4591 Mon Sep 17 00:00:00 2001 From: Abraxas3d Date: Mon, 17 Nov 2025 20:03:41 -0800 Subject: [PATCH 37/60] encoder and decoder tested in loopback and pass. encoder and decoder then installed in msk_top.vhd. Compiles clean. --- src/msk_top.vhd | 120 ++++++++++++- src/ov_frame_decoder.vhd | 351 +++++++++++++++++++++++++++++++++++++ src/ov_frame_encoder.vhd | 362 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 824 insertions(+), 9 deletions(-) create mode 100644 src/ov_frame_decoder.vhd create mode 100644 src/ov_frame_encoder.vhd diff --git a/src/msk_top.vhd b/src/msk_top.vhd index ac0e43c..e14168c 100644 --- a/src/msk_top.vhd +++ b/src/msk_top.vhd @@ -59,6 +59,20 @@ -- MODIFIED FOR MSB-FIRST: Updated sync word from 0xACFA47/0xE25F35 to 0xE25F35/0xE25F35 -- Both TX and RX now use the same sync word pattern (no bit reversal) ------------------------------------------------------------------------------------------------------ +-- PHASE 1: OV ENCODER/DECODER INTEGRATION (Issue #24) +------------------------------------------------------------------------------------------------------ +-- Integrated OV frame encoder (TX) and decoder (RX) into datapath: +-- TX: FIFO → Encoder (134→268 bytes) → Deserializer → Modulator +-- RX: Demodulator → Frame Sync → Decoder (268→134 bytes) → FIFO +-- +-- KNOWN LIMITATION: Frame size mismatch - PS currently sends/expects 268 bytes +-- - Encoder expects 134-byte input but receives 268 bytes +-- - Decoder outputs 134 bytes but PS expects 268 bytes +-- - This will be resolved in Phase 2 by updating PS frame size to 134 bytes +-- +-- Modified: TX Stage 3 (encoder insertion), TX Stage 4 (deserializer rewire) +-- RX Stage 3 (decoder insertion), RX Stage 4 (FIFO rewire) +------------------------------------------------------------------------------------------------------ LIBRARY ieee; USE ieee.std_logic_1164.ALL; @@ -168,6 +182,14 @@ ARCHITECTURE struct OF msk_top IS SIGNAL fifo_tlast : std_logic; SIGNAL frame_complete : std_logic; + + -- TX Encoder signals (OV Frame Encoder - Phase 1) + SIGNAL encoder_tdata : std_logic_vector(7 DOWNTO 0); + SIGNAL encoder_tvalid : std_logic; + SIGNAL encoder_tready : std_logic; + SIGNAL encoder_tlast : std_logic; + SIGNAL tx_frames_encoded : std_logic_vector(31 DOWNTO 0); + SIGNAL tx_encoder_active : std_logic; SIGNAL tx_async_fifo_prog_full : std_logic; SIGNAL tx_async_fifo_prog_empty : std_logic; @@ -205,6 +227,14 @@ ARCHITECTURE struct OF msk_top IS SIGNAL rx_debug_state : std_logic_vector(2 DOWNTO 0); SIGNAL rx_debug_missed_syncs : std_logic_vector(3 DOWNTO 0); SIGNAL rx_debug_consecutive_good: std_logic_vector(3 DOWNTO 0); + + -- RX Decoder signals (OV Frame Decoder - Phase 1) + SIGNAL decoder_tdata : std_logic_vector(7 DOWNTO 0); + SIGNAL decoder_tvalid : std_logic; + SIGNAL decoder_tready : std_logic; + SIGNAL decoder_tlast : std_logic; + SIGNAL rx_frames_decoded : std_logic_vector(31 DOWNTO 0); + SIGNAL rx_decoder_active : std_logic; SIGNAL rx_bit : std_logic; SIGNAL rx_bit_corr : std_logic; @@ -356,20 +386,56 @@ BEGIN fifo_rd_ptr => tx_async_fifo_rd_ptr ); - -- Stage 3: Byte-to-Bit De-serializer (MSB-FIRST VERSION) - u_deserializer : ENTITY work.byte_to_bit_deserializer + ------------------------------------------------------------------------------------------------------ + -- TX Stage 3: OV Frame Encoder (Randomize + FEC + Interleave) - PHASE 1 + ------------------------------------------------------------------------------------------------------ + -- NOTE: Phase 1 limitation - encoder expects 134-byte frames but currently receives 268 bytes + -- This will be corrected in Phase 2 when PS side is updated to send 134-byte frames + ------------------------------------------------------------------------------------------------------ + + u_ov_encoder : ENTITY work.ov_frame_encoder GENERIC MAP ( - BYTE_WIDTH => 8 + PAYLOAD_BYTES => 134, + ENCODED_BYTES => 268, + ENCODED_BITS => 2144, + BYTE_WIDTH => 8 ) PORT MAP ( clk => clk, - init => txinit, + aresetn => NOT txinit, + -- Input from FIFO s_axis_tdata => fifo_tdata, s_axis_tvalid => fifo_tvalid, s_axis_tready => fifo_tready, s_axis_tlast => fifo_tlast, + -- Output to deserializer + m_axis_tdata => encoder_tdata, + m_axis_tvalid => encoder_tvalid, + m_axis_tready => encoder_tready, + m_axis_tlast => encoder_tlast, + + -- Status + frames_encoded => tx_frames_encoded, + encoder_active => tx_encoder_active + ); + + -- Stage 4: Byte-to-Bit De-serializer (MSB-FIRST VERSION) + u_deserializer : ENTITY work.byte_to_bit_deserializer + GENERIC MAP ( + BYTE_WIDTH => 8 + ) + PORT MAP ( + clk => clk, + init => txinit, + + -- Input from encoder (was: from FIFO) + s_axis_tdata => encoder_tdata, + s_axis_tvalid => encoder_tvalid, + s_axis_tready => encoder_tready, + s_axis_tlast => encoder_tlast, + tx_data => tx_data_bit, tx_req => tx_req, @@ -508,7 +574,42 @@ BEGIN ); ------------------------------------------------------------------------------ - -- RX Stage 3: Async FIFO (Clock Domain Crossing) + -- RX Stage 3: OV Frame Decoder (Deinterleave + FEC Decode + Derandomize) - PHASE 1 + ------------------------------------------------------------------------------ + -- NOTE: Phase 1 limitation - decoder outputs 134 bytes but RX FIFO/DMA expects 268 bytes + -- This will be corrected in Phase 2 when PS side is updated to receive 134-byte frames + ------------------------------------------------------------------------------ + + u_ov_decoder : ENTITY work.ov_frame_decoder + GENERIC MAP ( + PAYLOAD_BYTES => 134, + ENCODED_BYTES => 268, + ENCODED_BITS => 2144, + BYTE_WIDTH => 8 + ) + PORT MAP ( + clk => clk, + aresetn => NOT rxinit, + + -- Input from frame sync detector + s_axis_tdata => sync_det_tdata, + s_axis_tvalid => sync_det_tvalid, + s_axis_tready => sync_det_tready, + s_axis_tlast => sync_det_tlast, + + -- Output to RX FIFO + m_axis_tdata => decoder_tdata, + m_axis_tvalid => decoder_tvalid, + m_axis_tready => decoder_tready, + m_axis_tlast => decoder_tlast, + + -- Status + frames_decoded => rx_frames_decoded, + decoder_active => rx_decoder_active + ); + + ------------------------------------------------------------------------------ + -- RX Stage 4: Async FIFO (Clock Domain Crossing) -- Reuses existing axis_async_fifo component! ------------------------------------------------------------------------------ u_rx_async_fifo : ENTITY work.axis_async_fifo @@ -521,10 +622,11 @@ BEGIN wr_aclk => clk, wr_aresetn => NOT rxinit, - s_axis_tdata => sync_det_tdata, - s_axis_tvalid => sync_det_tvalid, - s_axis_tready => sync_det_tready, - s_axis_tlast => sync_det_tlast, + -- Input from decoder (was: from frame sync detector) + s_axis_tdata => decoder_tdata, + s_axis_tvalid => decoder_tvalid, + s_axis_tready => decoder_tready, + s_axis_tlast => decoder_tlast, -- Read side (AXI clock domain) rd_aclk => s_axis_aclk, -- Use system AXI clock diff --git a/src/ov_frame_decoder.vhd b/src/ov_frame_decoder.vhd new file mode 100644 index 0000000..6c792a2 --- /dev/null +++ b/src/ov_frame_decoder.vhd @@ -0,0 +1,351 @@ +------------------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------------------ +-- _______ ________ ______ +-- __ __ \________ _____ _______ ___ __ \_____ _____________ ______ ___________________ /_ +-- _ / / /___ __ \_ _ \__ __ \ __ /_/ /_ _ \__ ___/_ _ \_ __ `/__ ___/_ ___/__ __ \ +-- / /_/ / __ /_/ // __/_ / / / _ _, _/ / __/_(__ ) / __// /_/ / _ / / /__ _ / / / +-- \____/ _ .___/ \___/ /_/ /_/ /_/ |_| \___/ /____/ \___/ \__,_/ /_/ \___/ /_/ /_/ +-- /_/ +-- ________ _____ _____ _____ _____ +-- ____ _/_______ __________ /____(_)__ /_____ ____ /______ +-- __ / __ __ \__ ___/_ __/__ / _ __/_ / / /_ __/_ _ \ +-- __/ / _ / / /_(__ ) / /_ _ / / /_ / /_/ / / /_ / __/ +-- /___/ /_/ /_/ /____/ \__/ /_/ \__/ \__,_/ \__/ \___/ +-- +------------------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------------------ +-- Copyright +------------------------------------------------------------------------------------------------------ +-- +-- Copyright 2025 by Open Research Institute +-- +------------------------------------------------------------------------------------------------------ +-- License +------------------------------------------------------------------------------------------------------ +-- +-- This source describes Open Hardware and is licensed under the CERN-OHL-W v2. +-- +-- You may redistribute and modify this source and make products using it under +-- the terms of the CERN-OHL-W v2 (https://ohwr.org/cern_ohl_w_v2.txt). +-- +-- This source is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING +-- OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR A PARTICULAR PURPOSE. +-- Please see the CERN-OHL-W v2 for applicable conditions. +-- +------------------------------------------------------------------------------------------------------ +-- Block name and description +------------------------------------------------------------------------------------------------------ +-- +-- Opulent Voice Protocol Frame Decoder +-- +-- This module implements the RX path processing for OVP frames (reverse of encoder): +-- 1. Collects 268 bytes of encoded data from AXI-Stream input +-- 2. Deinterleaves bits (reverse 67x32 row-column interleaver) +-- 3. Applies FEC decoding (majority vote on bit pairs) +-- 4. Derandomizes (XOR with same fixed sequence) +-- 5. Outputs 134 bytes of payload via AXI-Stream +-- +-- BUGFIX (2025-11-16): Fixed first-byte-lost issue in IDLE→COLLECT transition +-- Now stores first byte immediately when transitioning states +-- +------------------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------------------ + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY ov_frame_decoder IS + GENERIC ( + PAYLOAD_BYTES : NATURAL := 134; -- Output frame size + ENCODED_BYTES : NATURAL := 268; -- Input frame size + ENCODED_BITS : NATURAL := 2144; -- Encoded bits (268 * 8) + BYTE_WIDTH : NATURAL := 8 + ); + PORT ( + clk : IN std_logic; + aresetn : IN std_logic; + + -- Input AXI-Stream (268-byte encoded frames) + s_axis_tdata : IN std_logic_vector(BYTE_WIDTH-1 DOWNTO 0); + s_axis_tvalid : IN std_logic; + s_axis_tready : OUT std_logic; + s_axis_tlast : IN std_logic; + + -- Output AXI-Stream (134-byte payload frames) + m_axis_tdata : OUT std_logic_vector(BYTE_WIDTH-1 DOWNTO 0); + m_axis_tvalid : OUT std_logic; + m_axis_tready : IN std_logic; + m_axis_tlast : OUT std_logic; + + -- Status outputs + frames_decoded : OUT std_logic_vector(31 DOWNTO 0); + decoder_active : OUT std_logic + ); +END ENTITY ov_frame_decoder; + +ARCHITECTURE rtl OF ov_frame_decoder IS + + -- State machine + TYPE state_t IS (IDLE, COLLECT, DEINTERLEAVE, FEC_DECODE, DERANDOMIZE, OUTPUT); + SIGNAL state : state_t := IDLE; + + -- Buffer types + TYPE byte_buffer_t IS ARRAY(0 TO PAYLOAD_BYTES-1) OF std_logic_vector(BYTE_WIDTH-1 DOWNTO 0); + TYPE bit_buffer_t IS ARRAY(0 TO ENCODED_BITS-1) OF std_logic; + + -- Processing buffers + SIGNAL input_buffer : bit_buffer_t := (OTHERS => '0'); -- Initialize to prevent 'U' + SIGNAL deinterleaved_buffer : bit_buffer_t := (OTHERS => '0'); -- Initialize to prevent 'U' + SIGNAL fec_decoded_buffer : byte_buffer_t; + SIGNAL output_buffer : byte_buffer_t; + + -- Index counters + SIGNAL byte_idx : NATURAL RANGE 0 TO ENCODED_BYTES; + SIGNAL bit_idx : NATURAL RANGE 0 TO ENCODED_BITS; + SIGNAL out_idx : NATURAL RANGE 0 TO PAYLOAD_BYTES; + + -- Frame counter + SIGNAL frame_count : UNSIGNED(31 DOWNTO 0) := (OTHERS => '0'); + + -- Output holding registers + SIGNAL m_tdata_reg : std_logic_vector(BYTE_WIDTH-1 DOWNTO 0); + SIGNAL m_tvalid_reg : std_logic; + SIGNAL m_tlast_reg : std_logic; + + -- OVP Randomizer sequence (same as encoder) + TYPE randomizer_t IS ARRAY(0 TO PAYLOAD_BYTES-1) OF std_logic_vector(7 DOWNTO 0); + CONSTANT RANDOMIZER_SEQUENCE : randomizer_t := ( + x"A3", x"81", x"5C", x"C4", x"C9", x"08", x"0E", x"53", + x"CC", x"A1", x"FB", x"29", x"9E", x"4F", x"16", x"E0", + x"97", x"4E", x"2B", x"57", x"12", x"A7", x"3F", x"C2", + x"4D", x"6B", x"0F", x"08", x"30", x"46", x"11", x"56", + x"0D", x"1A", x"13", x"E7", x"50", x"97", x"61", x"F3", + x"BE", x"E3", x"99", x"B0", x"64", x"39", x"22", x"2C", + x"F0", x"09", x"E1", x"86", x"CF", x"73", x"59", x"C2", + x"5C", x"8E", x"E3", x"D7", x"3F", x"70", x"D4", x"27", + x"C2", x"E0", x"81", x"92", x"DA", x"FC", x"CA", x"5A", + x"80", x"42", x"83", x"15", x"0F", x"A2", x"9E", x"15", + x"9C", x"8B", x"DB", x"A4", x"46", x"1C", x"10", x"9F", + x"B3", x"47", x"6C", x"5E", x"15", x"12", x"1F", x"AD", + x"38", x"3D", x"03", x"BA", x"90", x"8D", x"BE", x"D3", + x"65", x"23", x"32", x"B8", x"AB", x"10", x"62", x"7E", + x"C6", x"26", x"7C", x"13", x"C9", x"65", x"3D", x"15", + x"15", x"ED", x"35", x"F4", x"57", x"F5", x"58", x"11", + x"9D", x"8E", x"E8", x"34", x"C9", x"59" + ); + + -- Deinterleaver address calculation (reverse of interleaver) + FUNCTION deinterleave_address(addr : NATURAL) RETURN NATURAL IS + CONSTANT ROWS : NATURAL := 67; + CONSTANT COLS : NATURAL := 32; + VARIABLE row : NATURAL; + VARIABLE col : NATURAL; + BEGIN + row := addr MOD ROWS; + col := addr / ROWS; + RETURN row * COLS + col; + END FUNCTION; + +BEGIN + + -- Output assignments + m_axis_tdata <= m_tdata_reg; + m_axis_tvalid <= m_tvalid_reg; + m_axis_tlast <= m_tlast_reg; + + frames_decoded <= std_logic_vector(frame_count); + + -- Main FSM + decoder_fsm : PROCESS(clk) + VARIABLE bit_0, bit_1 : std_logic; + BEGIN + IF rising_edge(clk) THEN + IF aresetn = '0' THEN + state <= IDLE; + byte_idx <= 0; + bit_idx <= 0; + out_idx <= 0; + frame_count <= (OTHERS => '0'); + s_axis_tready <= '0'; + m_tvalid_reg <= '0'; + m_tlast_reg <= '0'; + decoder_active <= '0'; + + ELSE + CASE state IS + + -- IDLE: Wait for incoming data and capture first byte + WHEN IDLE => + decoder_active <= '0'; + s_axis_tready <= '1'; -- Ready to accept data + m_tvalid_reg <= '0'; -- Not outputting yet + + IF s_axis_tvalid = '1' THEN + -- *** FIX: Store the FIRST byte immediately! *** + input_buffer(0) <= s_axis_tdata(0); + input_buffer(1) <= s_axis_tdata(1); + input_buffer(2) <= s_axis_tdata(2); + input_buffer(3) <= s_axis_tdata(3); + input_buffer(4) <= s_axis_tdata(4); + input_buffer(5) <= s_axis_tdata(5); + input_buffer(6) <= s_axis_tdata(6); + input_buffer(7) <= s_axis_tdata(7); + + REPORT "DECODER: Stored FIRST byte at index 0, data=" & + INTEGER'IMAGE(to_integer(unsigned(s_axis_tdata))) & + " tlast=" & STD_LOGIC'IMAGE(s_axis_tlast)(2); + + -- Check for edge case: single-byte frame (unlikely with ENCODED_BYTES=268) + IF s_axis_tlast = '1' AND ENCODED_BYTES = 1 THEN + REPORT "DECODER: Single-byte frame received"; + byte_idx <= 0; + bit_idx <= 0; + state <= DEINTERLEAVE; + s_axis_tready <= '0'; + ELSE + -- Normal case: transition to COLLECT for remaining bytes + byte_idx <= 1; -- Next byte will go to index 1 + bit_idx <= 0; + state <= COLLECT; + decoder_active <= '1'; + END IF; + END IF; + + -- COLLECT: Gather remaining bytes (1 through 267) + WHEN COLLECT => + IF s_axis_tvalid = '1' THEN + -- Store incoming byte as 8 bits + input_buffer(byte_idx * 8 + 0) <= s_axis_tdata(0); + input_buffer(byte_idx * 8 + 1) <= s_axis_tdata(1); + input_buffer(byte_idx * 8 + 2) <= s_axis_tdata(2); + input_buffer(byte_idx * 8 + 3) <= s_axis_tdata(3); + input_buffer(byte_idx * 8 + 4) <= s_axis_tdata(4); + input_buffer(byte_idx * 8 + 5) <= s_axis_tdata(5); + input_buffer(byte_idx * 8 + 6) <= s_axis_tdata(6); + input_buffer(byte_idx * 8 + 7) <= s_axis_tdata(7); + + -- Debug: Report first 5 received bytes + IF byte_idx < 5 THEN + REPORT "DECODER: Stored byte at byte_idx=" & INTEGER'IMAGE(byte_idx) & + " data=" & INTEGER'IMAGE(to_integer(unsigned(s_axis_tdata))) & + " tlast=" & STD_LOGIC'IMAGE(s_axis_tlast)(2); + END IF; + + byte_idx <= byte_idx + 1; + + -- Check for frame completion + IF s_axis_tlast = '1' THEN + REPORT "DECODER: Received tlast. Total bytes stored = " & + INTEGER'IMAGE(byte_idx + 1); + + -- Verify we got the expected number of bytes + IF byte_idx + 1 /= ENCODED_BYTES THEN + REPORT "DECODER: WARNING! Expected " & INTEGER'IMAGE(ENCODED_BYTES) & + " bytes but got " & INTEGER'IMAGE(byte_idx + 1) severity warning; + END IF; + + byte_idx <= 0; + bit_idx <= 0; + state <= DEINTERLEAVE; + s_axis_tready <= '0'; + + ELSIF byte_idx + 1 >= ENCODED_BYTES THEN + -- Stored all bytes but no tlast! This is an error condition + REPORT "DECODER: ERROR! Stored " & INTEGER'IMAGE(ENCODED_BYTES) & + " bytes but no tlast received" severity error; + byte_idx <= 0; + state <= IDLE; + s_axis_tready <= '1'; + END IF; + END IF; + + -- DEINTERLEAVE: Reverse the row-column shuffle + WHEN DEINTERLEAVE => + IF bit_idx < ENCODED_BITS THEN + deinterleaved_buffer(deinterleave_address(bit_idx)) <= input_buffer(bit_idx); + bit_idx <= bit_idx + 1; + ELSE + REPORT "DEINTERLEAVE complete"; + byte_idx <= 0; + bit_idx <= 0; + state <= FEC_DECODE; + END IF; + + -- FEC_DECODE: Majority vote on bit pairs + WHEN FEC_DECODE => + IF byte_idx < PAYLOAD_BYTES THEN + -- Process one bit position at a time + IF bit_idx < 8 THEN + bit_0 := deinterleaved_buffer(byte_idx * 16 + bit_idx * 2); + bit_1 := deinterleaved_buffer(byte_idx * 16 + bit_idx * 2 + 1); + fec_decoded_buffer(byte_idx)(bit_idx) <= bit_0 OR bit_1; + bit_idx <= bit_idx + 1; + ELSE + -- Done with this byte, move to next + bit_idx <= 0; + byte_idx <= byte_idx + 1; + END IF; + ELSE + REPORT "FEC_DECODE complete"; + byte_idx <= 0; + state <= DERANDOMIZE; + END IF; + + -- DERANDOMIZE: XOR with same sequence (inverse operation) + WHEN DERANDOMIZE => + IF byte_idx < PAYLOAD_BYTES THEN + output_buffer(byte_idx) <= + fec_decoded_buffer(byte_idx) XOR RANDOMIZER_SEQUENCE(byte_idx); + + -- Debug: Report first 5 derandomized bytes + IF byte_idx < 5 THEN + REPORT "DERANDOMIZE[" & INTEGER'IMAGE(byte_idx) & + "] fec=" & INTEGER'IMAGE(to_integer(unsigned(fec_decoded_buffer(byte_idx)))) & + " rand=" & INTEGER'IMAGE(to_integer(unsigned(RANDOMIZER_SEQUENCE(byte_idx)))) & + " out=" & INTEGER'IMAGE(to_integer(unsigned(fec_decoded_buffer(byte_idx) XOR RANDOMIZER_SEQUENCE(byte_idx)))); + END IF; + + byte_idx <= byte_idx + 1; + ELSE + REPORT "DERANDOMIZE complete"; + out_idx <= 0; + state <= OUTPUT; + END IF; + + -- OUTPUT: Send bytes to next stage + WHEN OUTPUT => + IF m_axis_tready = '1' OR m_tvalid_reg = '0' THEN + IF out_idx < PAYLOAD_BYTES THEN + m_tdata_reg <= output_buffer(out_idx); + m_tvalid_reg <= '1'; + + -- Debug: Report first 5 output bytes + IF out_idx < 5 THEN + REPORT "DECODER OUTPUT byte " & INTEGER'IMAGE(out_idx) & " = " & + INTEGER'IMAGE(to_integer(unsigned(output_buffer(out_idx)))); + END IF; + + -- Set tlast on final byte + IF out_idx = PAYLOAD_BYTES - 1 THEN + m_tlast_reg <= '1'; + ELSE + m_tlast_reg <= '0'; + END IF; + + out_idx <= out_idx + 1; + ELSE + -- Frame complete + m_tvalid_reg <= '0'; + m_tlast_reg <= '0'; + frame_count <= frame_count + 1; + state <= IDLE; + END IF; + END IF; + + END CASE; + END IF; + END IF; + END PROCESS decoder_fsm; + +END ARCHITECTURE rtl; diff --git a/src/ov_frame_encoder.vhd b/src/ov_frame_encoder.vhd new file mode 100644 index 0000000..1772603 --- /dev/null +++ b/src/ov_frame_encoder.vhd @@ -0,0 +1,362 @@ +------------------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------------------ +-- _______ ________ ______ +-- __ __ \________ _____ _______ ___ __ \_____ _____________ ______ ___________________ /_ +-- _ / / /___ __ \_ _ \__ __ \ __ /_/ /_ _ \__ ___/_ _ \_ __ `/__ ___/_ ___/__ __ \ +-- / /_/ / __ /_/ // __/_ / / / _ _, _/ / __/_(__ ) / __// /_/ / _ / / /__ _ / / / +-- \____/ _ .___/ \___/ /_/ /_/ /_/ |_| \___/ /____/ \___/ \__,_/ /_/ \___/ /_/ /_/ +-- /_/ +-- ________ _____ _____ _____ _____ +-- ____ _/_______ __________ /____(_)__ /_____ ____ /______ +-- __ / __ __ \__ ___/_ __/__ / _ __/_ / / /_ __/_ _ \ +-- __/ / _ / / /_(__ ) / /_ _ / / /_ / /_/ / / /_ / __/ +-- /___/ /_/ /_/ /____/ \__/ /_/ \__/ \__,_/ \__/ \___/ +-- +------------------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------------------ +-- Copyright +------------------------------------------------------------------------------------------------------ +-- +-- Copyright 2025 by Open Research Institute +-- +------------------------------------------------------------------------------------------------------ +-- License +------------------------------------------------------------------------------------------------------ +-- +-- This source describes Open Hardware and is licensed under the CERN-OHL-W v2. +-- +-- You may redistribute and modify this source and make products using it under +-- the terms of the CERN-OHL-W v2 (https://ohwr.org/cern_ohl_w_v2.txt). +-- +-- This source is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING +-- OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR A PARTICULAR PURPOSE. +-- Please see the CERN-OHL-W v2 for applicable conditions. +-- +------------------------------------------------------------------------------------------------------ +-- Block name and description +------------------------------------------------------------------------------------------------------ +-- +-- Opulent Voice Protocol Frame Encoder +-- +-- This module implements the TX path processing for OVP frames: +-- 1. Collects 134 bytes of payload from AXI-Stream input +-- 2. Applies randomization (XOR with fixed sequence) +-- 3. Applies FEC (rate 1/2 convolutional - currently simple bit duplication) +-- 4. Applies interleaving (67x32 row-column interleaver) +-- 5. Outputs 268 bytes (2144 bits) via AXI-Stream +-- +-- The module is designed to maintain timing for 40ms frame periods. +-- +-- BUGFIX (2025-11-16): Fixed first-byte-lost issue in IDLE?COLLECT transition +-- Now stores first byte immediately when transitioning states +-- +------------------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------------------ + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY ov_frame_encoder IS + GENERIC ( + PAYLOAD_BYTES : NATURAL := 134; -- Input frame size + ENCODED_BYTES : NATURAL := 268; -- Output frame size (after FEC) + ENCODED_BITS : NATURAL := 2144; -- Encoded bits (268 * 8) + BYTE_WIDTH : NATURAL := 8 + ); + PORT ( + clk : IN std_logic; + aresetn : IN std_logic; + + -- Input AXI-Stream (134-byte frames from async FIFO) + s_axis_tdata : IN std_logic_vector(BYTE_WIDTH-1 DOWNTO 0); + s_axis_tvalid : IN std_logic; + s_axis_tready : OUT std_logic; + s_axis_tlast : IN std_logic; + + -- Output AXI-Stream (268-byte frames to deserializer) + m_axis_tdata : OUT std_logic_vector(BYTE_WIDTH-1 DOWNTO 0); + m_axis_tvalid : OUT std_logic; + m_axis_tready : IN std_logic; + m_axis_tlast : OUT std_logic; + + -- Status outputs + frames_encoded : OUT std_logic_vector(31 DOWNTO 0); + encoder_active : OUT std_logic + ); +END ENTITY ov_frame_encoder; + +ARCHITECTURE rtl OF ov_frame_encoder IS + + -- State machine + TYPE state_t IS (IDLE, COLLECT, RANDOMIZE, FEC_ENCODE, INTERLEAVE, OUTPUT); + SIGNAL state : state_t := IDLE; + + -- Buffer types + TYPE byte_buffer_t IS ARRAY(0 TO PAYLOAD_BYTES-1) OF std_logic_vector(BYTE_WIDTH-1 DOWNTO 0); + TYPE bit_buffer_t IS ARRAY(0 TO ENCODED_BITS-1) OF std_logic; + + -- Processing buffers + SIGNAL input_buffer : byte_buffer_t; + SIGNAL randomized_buffer : byte_buffer_t; + SIGNAL fec_buffer : bit_buffer_t := (OTHERS => '0'); -- Initialize to prevent 'U' + SIGNAL interleaved_buffer : bit_buffer_t := (OTHERS => '0'); -- Initialize to prevent 'U' + + -- Index counters + SIGNAL byte_idx : NATURAL RANGE 0 TO PAYLOAD_BYTES; + SIGNAL bit_idx : NATURAL RANGE 0 TO ENCODED_BITS; + SIGNAL out_idx : NATURAL RANGE 0 TO ENCODED_BYTES; + + -- Frame counter + SIGNAL frame_count : UNSIGNED(31 DOWNTO 0) := (OTHERS => '0'); + + -- Output holding registers + SIGNAL m_tdata_reg : std_logic_vector(BYTE_WIDTH-1 DOWNTO 0); + SIGNAL m_tvalid_reg : std_logic; + SIGNAL m_tlast_reg : std_logic; + + -- OVP Randomizer sequence (from OVP spec) + TYPE randomizer_t IS ARRAY(0 TO PAYLOAD_BYTES-1) OF std_logic_vector(7 DOWNTO 0); + CONSTANT RANDOMIZER_SEQUENCE : randomizer_t := ( + x"A3", x"81", x"5C", x"C4", x"C9", x"08", x"0E", x"53", + x"CC", x"A1", x"FB", x"29", x"9E", x"4F", x"16", x"E0", + x"97", x"4E", x"2B", x"57", x"12", x"A7", x"3F", x"C2", + x"4D", x"6B", x"0F", x"08", x"30", x"46", x"11", x"56", + x"0D", x"1A", x"13", x"E7", x"50", x"97", x"61", x"F3", + x"BE", x"E3", x"99", x"B0", x"64", x"39", x"22", x"2C", + x"F0", x"09", x"E1", x"86", x"CF", x"73", x"59", x"C2", + x"5C", x"8E", x"E3", x"D7", x"3F", x"70", x"D4", x"27", + x"C2", x"E0", x"81", x"92", x"DA", x"FC", x"CA", x"5A", + x"80", x"42", x"83", x"15", x"0F", x"A2", x"9E", x"15", + x"9C", x"8B", x"DB", x"A4", x"46", x"1C", x"10", x"9F", + x"B3", x"47", x"6C", x"5E", x"15", x"12", x"1F", x"AD", + x"38", x"3D", x"03", x"BA", x"90", x"8D", x"BE", x"D3", + x"65", x"23", x"32", x"B8", x"AB", x"10", x"62", x"7E", + x"C6", x"26", x"7C", x"13", x"C9", x"65", x"3D", x"15", + x"15", x"ED", x"35", x"F4", x"57", x"F5", x"58", x"11", + x"9D", x"8E", x"E8", x"34", x"C9", x"59" + ); + + -- Interleaver address calculation (67 rows x 32 cols) + FUNCTION interleave_address(addr : NATURAL) RETURN NATURAL IS + CONSTANT ROWS : NATURAL := 67; + CONSTANT COLS : NATURAL := 32; + VARIABLE row : NATURAL; + VARIABLE col : NATURAL; + BEGIN + row := addr / COLS; + col := addr MOD COLS; + RETURN col * ROWS + row; + END FUNCTION; + +BEGIN + + -- Connect output registers to ports + m_axis_tdata <= m_tdata_reg; + m_axis_tvalid <= m_tvalid_reg; + m_axis_tlast <= m_tlast_reg; + + frames_encoded <= std_logic_vector(frame_count); + + -- Main FSM + encoder_fsm: PROCESS(clk, aresetn) + BEGIN + IF aresetn = '0' THEN + state <= IDLE; + byte_idx <= 0; + bit_idx <= 0; + out_idx <= 0; + s_axis_tready <= '0'; + m_tvalid_reg <= '0'; + m_tlast_reg <= '0'; + frame_count <= (OTHERS => '0'); + + ELSIF rising_edge(clk) THEN + IF aresetn = '1' THEN + CASE state IS + + -- IDLE: Wait for incoming data + WHEN IDLE => + encoder_active <= '0'; + s_axis_tready <= '0'; -- Keep tready LOW to prevent premature handshakes + m_tvalid_reg <= '0'; + byte_idx <= 0; + + IF s_axis_tvalid = '1' THEN + -- Data is waiting, transition to COLLECT and assert tready + state <= COLLECT; + encoder_active <= '1'; + s_axis_tready <= '1'; -- Assert tready ONLY when transitioning + END IF; + + -- COLLECT: Gather ALL bytes (0 through 133) + WHEN COLLECT => + -- DON'T touch tready - it was set to '1' during IDLE transition + -- Leave it alone to prevent FIFO synchronization issues + + IF s_axis_tvalid = '1' AND s_axis_tready = '1' THEN + -- Store the incoming byte + input_buffer(byte_idx) <= s_axis_tdata; + REPORT "ENCODER: Stored byte at byte_idx=" & INTEGER'IMAGE(byte_idx) & + " data=" & INTEGER'IMAGE(to_integer(unsigned(s_axis_tdata))) & + " tlast=" & STD_LOGIC'IMAGE(s_axis_tlast)(2); + + -- Check tlast FIRST + IF s_axis_tlast = '1' THEN + REPORT "ENCODER: Received tlast. Total bytes stored = " & + INTEGER'IMAGE(byte_idx + 1); + + IF byte_idx + 1 /= PAYLOAD_BYTES THEN + REPORT "ENCODER: WARNING! Expected " & INTEGER'IMAGE(PAYLOAD_BYTES) & + " bytes but got " & INTEGER'IMAGE(byte_idx + 1) severity warning; + END IF; + + byte_idx <= 0; + state <= RANDOMIZE; + s_axis_tready <= '0'; -- Deassert when done + + ELSIF byte_idx >= PAYLOAD_BYTES - 1 THEN + -- Just stored the last expected byte but no tlast + REPORT "ENCODER: ERROR! Stored " & INTEGER'IMAGE(byte_idx + 1) & + " bytes but no tlast received" severity error; + byte_idx <= 0; + state <= IDLE; + s_axis_tready <= '0'; -- Deassert on error + ELSE + -- Continue to next byte + byte_idx <= byte_idx + 1; + -- DON'T touch tready! + END IF; + END IF; + + -- RANDOMIZE: XOR with sequence + WHEN RANDOMIZE => + IF byte_idx < PAYLOAD_BYTES THEN + randomized_buffer(byte_idx) <= + input_buffer(byte_idx) XOR RANDOMIZER_SEQUENCE(byte_idx); + + -- Debug: Report first 5 bytes + IF byte_idx < 5 THEN + REPORT "RANDOMIZE[" & INTEGER'IMAGE(byte_idx) & + "] input=" & INTEGER'IMAGE(to_integer(unsigned(input_buffer(byte_idx)))) & + " rand=" & INTEGER'IMAGE(to_integer(unsigned(RANDOMIZER_SEQUENCE(byte_idx)))) & + " out=" & INTEGER'IMAGE(to_integer(unsigned(input_buffer(byte_idx) XOR RANDOMIZER_SEQUENCE(byte_idx)))); + END IF; + + byte_idx <= byte_idx + 1; + ELSE + REPORT "RANDOMIZE complete, " & INTEGER'IMAGE(PAYLOAD_BYTES) & " bytes processed"; + byte_idx <= 0; + bit_idx <= 0; + state <= FEC_ENCODE; + END IF; + + -- FEC_ENCODE: Duplicate each bit (rate 1/2) + WHEN FEC_ENCODE => + IF byte_idx < PAYLOAD_BYTES THEN + -- Process one source bit at a time (produces 2 output bits) + IF bit_idx < 8 THEN + -- Duplicate bit (bit_idx) from current byte + fec_buffer(byte_idx * 16 + bit_idx * 2) <= randomized_buffer(byte_idx)(bit_idx); + fec_buffer(byte_idx * 16 + bit_idx * 2 + 1) <= randomized_buffer(byte_idx)(bit_idx); + bit_idx <= bit_idx + 1; + ELSE + -- Done with this byte, move to next + -- Debug: Report first byte's FEC output + IF byte_idx = 0 THEN + REPORT "FEC_ENCODE byte 0 produces 16 bits: " & + std_logic'IMAGE(fec_buffer(0)) & std_logic'IMAGE(fec_buffer(1)) & " " & + std_logic'IMAGE(fec_buffer(2)) & std_logic'IMAGE(fec_buffer(3)) & " " & + std_logic'IMAGE(fec_buffer(4)) & std_logic'IMAGE(fec_buffer(5)) & " " & + std_logic'IMAGE(fec_buffer(6)) & std_logic'IMAGE(fec_buffer(7)) & " " & + std_logic'IMAGE(fec_buffer(8)) & std_logic'IMAGE(fec_buffer(9)) & " " & + std_logic'IMAGE(fec_buffer(10)) & std_logic'IMAGE(fec_buffer(11)) & " " & + std_logic'IMAGE(fec_buffer(12)) & std_logic'IMAGE(fec_buffer(13)) & " " & + std_logic'IMAGE(fec_buffer(14)) & std_logic'IMAGE(fec_buffer(15)); + END IF; + bit_idx <= 0; + byte_idx <= byte_idx + 1; + END IF; + ELSE + REPORT "FEC_ENCODE complete, " & INTEGER'IMAGE(ENCODED_BITS) & " bits produced"; + byte_idx <= 0; + bit_idx <= 0; + state <= INTERLEAVE; + END IF; + + -- INTERLEAVE: Shuffle bits via row-column interleaver + WHEN INTERLEAVE => + IF bit_idx < ENCODED_BITS THEN + interleaved_buffer(interleave_address(bit_idx)) <= fec_buffer(bit_idx); + bit_idx <= bit_idx + 1; + ELSE + REPORT "INTERLEAVE complete"; + bit_idx <= 0; + out_idx <= 0; + state <= OUTPUT; + END IF; + + -- OUTPUT: Send bytes to deserializer + + + + + WHEN OUTPUT => + IF m_axis_tready = '1' OR m_tvalid_reg = '0' THEN + IF out_idx < ENCODED_BYTES THEN + -- Pack 8 bits into a byte + m_tdata_reg(0) <= interleaved_buffer(out_idx * 8 + 0); + m_tdata_reg(1) <= interleaved_buffer(out_idx * 8 + 1); + m_tdata_reg(2) <= interleaved_buffer(out_idx * 8 + 2); + m_tdata_reg(3) <= interleaved_buffer(out_idx * 8 + 3); + m_tdata_reg(4) <= interleaved_buffer(out_idx * 8 + 4); + m_tdata_reg(5) <= interleaved_buffer(out_idx * 8 + 5); + m_tdata_reg(6) <= interleaved_buffer(out_idx * 8 + 6); + m_tdata_reg(7) <= interleaved_buffer(out_idx * 8 + 7); + + m_tvalid_reg <= '1'; + + -- Debug reports... + IF out_idx < 5 THEN + REPORT "OUTPUT[" & INTEGER'IMAGE(out_idx) & "] bits: " & + std_logic'IMAGE(interleaved_buffer(out_idx * 8 + 7)) & + std_logic'IMAGE(interleaved_buffer(out_idx * 8 + 6)) & + std_logic'IMAGE(interleaved_buffer(out_idx * 8 + 5)) & + std_logic'IMAGE(interleaved_buffer(out_idx * 8 + 4)) & + std_logic'IMAGE(interleaved_buffer(out_idx * 8 + 3)) & + std_logic'IMAGE(interleaved_buffer(out_idx * 8 + 2)) & + std_logic'IMAGE(interleaved_buffer(out_idx * 8 + 1)) & + std_logic'IMAGE(interleaved_buffer(out_idx * 8 + 0)); + END IF; + + -- Set tlast on final byte + IF out_idx = ENCODED_BYTES - 1 THEN + m_tlast_reg <= '1'; + ELSE + m_tlast_reg <= '0'; + END IF; + + out_idx <= out_idx + 1; + ELSE + -- Frame complete + m_tvalid_reg <= '0'; + m_tlast_reg <= '0'; + frame_count <= frame_count + 1; + state <= IDLE; + END IF; + END IF; + + + + + + + + + + END CASE; + END IF; + END IF; + END PROCESS encoder_fsm; + +END ARCHITECTURE rtl; From e0ddf298189d6e5e720c1e21405c80c3a05467d5 Mon Sep 17 00:00:00 2001 From: Abraxas3d Date: Tue, 18 Nov 2025 22:21:07 -0800 Subject: [PATCH 38/60] data now good in loopback - defeated tricky FIFO to encoder timing bug --- src/msk_top.vhd | 4 +- src/ov_frame_encoder.vhd | 228 ++++++++++++++++----------------------- 2 files changed, 93 insertions(+), 139 deletions(-) diff --git a/src/msk_top.vhd b/src/msk_top.vhd index e14168c..2c02f60 100644 --- a/src/msk_top.vhd +++ b/src/msk_top.vhd @@ -62,8 +62,8 @@ -- PHASE 1: OV ENCODER/DECODER INTEGRATION (Issue #24) ------------------------------------------------------------------------------------------------------ -- Integrated OV frame encoder (TX) and decoder (RX) into datapath: --- TX: FIFO → Encoder (134→268 bytes) → Deserializer → Modulator --- RX: Demodulator → Frame Sync → Decoder (268→134 bytes) → FIFO +-- TX: FIFO ? Encoder (134?268 bytes) ? Deserializer ? Modulator +-- RX: Demodulator ? Frame Sync ? Decoder (268?134 bytes) ? FIFO -- -- KNOWN LIMITATION: Frame size mismatch - PS currently sends/expects 268 bytes -- - Encoder expects 134-byte input but receives 268 bytes diff --git a/src/ov_frame_encoder.vhd b/src/ov_frame_encoder.vhd index 1772603..8e1d646 100644 --- a/src/ov_frame_encoder.vhd +++ b/src/ov_frame_encoder.vhd @@ -45,10 +45,10 @@ -- 4. Applies interleaving (67x32 row-column interleaver) -- 5. Outputs 268 bytes (2144 bits) via AXI-Stream -- --- The module is designed to maintain timing for 40ms frame periods. --- --- BUGFIX (2025-11-16): Fixed first-byte-lost issue in IDLE?COLLECT transition --- Now stores first byte immediately when transitioning states +-- BUGFIX (2025-11-18): Completely redesigned collection strategy +-- - Collect ALL bytes into circular buffer +-- - When tlast arrives, count back 134 bytes +-- - This handles any FIFO latency/alignment naturally -- ------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------ @@ -89,23 +89,29 @@ END ENTITY ov_frame_encoder; ARCHITECTURE rtl OF ov_frame_encoder IS -- State machine - TYPE state_t IS (IDLE, COLLECT, RANDOMIZE, FEC_ENCODE, INTERLEAVE, OUTPUT); + TYPE state_t IS (IDLE, COLLECT, EXTRACT, RANDOMIZE, FEC_ENCODE, INTERLEAVE, OUTPUT); SIGNAL state : state_t := IDLE; -- Buffer types TYPE byte_buffer_t IS ARRAY(0 TO PAYLOAD_BYTES-1) OF std_logic_vector(BYTE_WIDTH-1 DOWNTO 0); TYPE bit_buffer_t IS ARRAY(0 TO ENCODED_BITS-1) OF std_logic; + -- Circular collection buffer (larger than needed to handle any transients) + CONSTANT COLLECT_SIZE : NATURAL := 256; + TYPE collect_buffer_t IS ARRAY(0 TO COLLECT_SIZE-1) OF std_logic_vector(BYTE_WIDTH-1 DOWNTO 0); + SIGNAL collect_buffer : collect_buffer_t; + -- Processing buffers SIGNAL input_buffer : byte_buffer_t; SIGNAL randomized_buffer : byte_buffer_t; - SIGNAL fec_buffer : bit_buffer_t := (OTHERS => '0'); -- Initialize to prevent 'U' - SIGNAL interleaved_buffer : bit_buffer_t := (OTHERS => '0'); -- Initialize to prevent 'U' + SIGNAL fec_buffer : bit_buffer_t := (OTHERS => '0'); + SIGNAL interleaved_buffer : bit_buffer_t := (OTHERS => '0'); -- Index counters - SIGNAL byte_idx : NATURAL RANGE 0 TO PAYLOAD_BYTES; - SIGNAL bit_idx : NATURAL RANGE 0 TO ENCODED_BITS; - SIGNAL out_idx : NATURAL RANGE 0 TO ENCODED_BYTES; + SIGNAL collect_idx : NATURAL RANGE 0 TO COLLECT_SIZE; -- Where we're writing in collect_buffer + SIGNAL byte_idx : NATURAL RANGE 0 TO PAYLOAD_BYTES; + SIGNAL bit_idx : NATURAL RANGE 0 TO ENCODED_BITS; + SIGNAL out_idx : NATURAL RANGE 0 TO ENCODED_BYTES; -- Frame counter SIGNAL frame_count : UNSIGNED(31 DOWNTO 0) := (OTHERS => '0'); @@ -160,9 +166,12 @@ BEGIN -- Main FSM encoder_fsm: PROCESS(clk, aresetn) + VARIABLE extract_start : NATURAL; + VARIABLE extract_end : NATURAL; BEGIN IF aresetn = '0' THEN state <= IDLE; + collect_idx <= 0; byte_idx <= 0; bit_idx <= 0; out_idx <= 0; @@ -178,182 +187,127 @@ BEGIN -- IDLE: Wait for incoming data WHEN IDLE => encoder_active <= '0'; - s_axis_tready <= '0'; -- Keep tready LOW to prevent premature handshakes + s_axis_tready <= '0'; m_tvalid_reg <= '0'; - byte_idx <= 0; + collect_idx <= 0; IF s_axis_tvalid = '1' THEN - -- Data is waiting, transition to COLLECT and assert tready state <= COLLECT; encoder_active <= '1'; - s_axis_tready <= '1'; -- Assert tready ONLY when transitioning + s_axis_tready <= '1'; END IF; - -- COLLECT: Gather ALL bytes (0 through 133) + -- COLLECT: Gather ALL bytes into circular buffer until tlast + -- Don't worry about alignment - just collect everything WHEN COLLECT => - -- DON'T touch tready - it was set to '1' during IDLE transition - -- Leave it alone to prevent FIFO synchronization issues + s_axis_tready <= '1'; - IF s_axis_tvalid = '1' AND s_axis_tready = '1' THEN - -- Store the incoming byte - input_buffer(byte_idx) <= s_axis_tdata; - REPORT "ENCODER: Stored byte at byte_idx=" & INTEGER'IMAGE(byte_idx) & - " data=" & INTEGER'IMAGE(to_integer(unsigned(s_axis_tdata))) & + IF s_axis_tvalid = '1' THEN + -- Store byte in circular buffer + collect_buffer(collect_idx MOD COLLECT_SIZE) <= s_axis_tdata; + + REPORT "COLLECT: collect_idx=" & INTEGER'IMAGE(collect_idx) & + " data=0x" & INTEGER'IMAGE(to_integer(unsigned(s_axis_tdata))) & " tlast=" & STD_LOGIC'IMAGE(s_axis_tlast)(2); - -- Check tlast FIRST IF s_axis_tlast = '1' THEN - REPORT "ENCODER: Received tlast. Total bytes stored = " & - INTEGER'IMAGE(byte_idx + 1); - - IF byte_idx + 1 /= PAYLOAD_BYTES THEN - REPORT "ENCODER: WARNING! Expected " & INTEGER'IMAGE(PAYLOAD_BYTES) & - " bytes but got " & INTEGER'IMAGE(byte_idx + 1) severity warning; - END IF; - - byte_idx <= 0; - state <= RANDOMIZE; - s_axis_tready <= '0'; -- Deassert when done - - ELSIF byte_idx >= PAYLOAD_BYTES - 1 THEN - -- Just stored the last expected byte but no tlast - REPORT "ENCODER: ERROR! Stored " & INTEGER'IMAGE(byte_idx + 1) & - " bytes but no tlast received" severity error; + -- Frame boundary! Now extract the last 134 bytes + REPORT "COLLECT: tlast at collect_idx=" & INTEGER'IMAGE(collect_idx); + s_axis_tready <= '0'; + state <= EXTRACT; byte_idx <= 0; - state <= IDLE; - s_axis_tready <= '0'; -- Deassert on error ELSE - -- Continue to next byte - byte_idx <= byte_idx + 1; - -- DON'T touch tready! + collect_idx <= collect_idx + 1; END IF; END IF; - -- RANDOMIZE: XOR with sequence - WHEN RANDOMIZE => + -- EXTRACT: Copy the last 134 bytes from collect_buffer to input_buffer + -- The frame ends at collect_idx, so we want bytes [collect_idx-133 : collect_idx] + WHEN EXTRACT => IF byte_idx < PAYLOAD_BYTES THEN - randomized_buffer(byte_idx) <= - input_buffer(byte_idx) XOR RANDOMIZER_SEQUENCE(byte_idx); + -- Calculate which byte in collect_buffer to read + -- If collect_idx = 133, we want bytes [0:133] + -- If collect_idx = 150, we want bytes [17:150] + extract_start := (collect_idx + 1) - PAYLOAD_BYTES; + extract_end := collect_idx; + + -- Copy byte from circular buffer + input_buffer(byte_idx) <= collect_buffer((extract_start + byte_idx) MOD COLLECT_SIZE); - -- Debug: Report first 5 bytes IF byte_idx < 5 THEN - REPORT "RANDOMIZE[" & INTEGER'IMAGE(byte_idx) & - "] input=" & INTEGER'IMAGE(to_integer(unsigned(input_buffer(byte_idx)))) & - " rand=" & INTEGER'IMAGE(to_integer(unsigned(RANDOMIZER_SEQUENCE(byte_idx)))) & - " out=" & INTEGER'IMAGE(to_integer(unsigned(input_buffer(byte_idx) XOR RANDOMIZER_SEQUENCE(byte_idx)))); + REPORT "EXTRACT[" & INTEGER'IMAGE(byte_idx) & + "] from collect_buffer[" & + INTEGER'IMAGE((extract_start + byte_idx) MOD COLLECT_SIZE) & + "] = 0x" & + INTEGER'IMAGE(to_integer(unsigned(collect_buffer((extract_start + byte_idx) MOD COLLECT_SIZE)))); END IF; byte_idx <= byte_idx + 1; ELSE - REPORT "RANDOMIZE complete, " & INTEGER'IMAGE(PAYLOAD_BYTES) & " bytes processed"; + REPORT "EXTRACT complete, " & INTEGER'IMAGE(PAYLOAD_BYTES) & " bytes copied"; + byte_idx <= 0; + state <= RANDOMIZE; + END IF; + + -- RANDOMIZE: XOR with sequence + WHEN RANDOMIZE => + IF byte_idx < PAYLOAD_BYTES THEN + randomized_buffer(byte_idx) <= + input_buffer(byte_idx) XOR RANDOMIZER_SEQUENCE(byte_idx); + byte_idx <= byte_idx + 1; + ELSE byte_idx <= 0; bit_idx <= 0; state <= FEC_ENCODE; END IF; - -- FEC_ENCODE: Duplicate each bit (rate 1/2) + -- FEC_ENCODE: Simple rate-1/2 code (bit duplication) WHEN FEC_ENCODE => - IF byte_idx < PAYLOAD_BYTES THEN - -- Process one source bit at a time (produces 2 output bits) - IF bit_idx < 8 THEN - -- Duplicate bit (bit_idx) from current byte - fec_buffer(byte_idx * 16 + bit_idx * 2) <= randomized_buffer(byte_idx)(bit_idx); - fec_buffer(byte_idx * 16 + bit_idx * 2 + 1) <= randomized_buffer(byte_idx)(bit_idx); - bit_idx <= bit_idx + 1; - ELSE - -- Done with this byte, move to next - -- Debug: Report first byte's FEC output - IF byte_idx = 0 THEN - REPORT "FEC_ENCODE byte 0 produces 16 bits: " & - std_logic'IMAGE(fec_buffer(0)) & std_logic'IMAGE(fec_buffer(1)) & " " & - std_logic'IMAGE(fec_buffer(2)) & std_logic'IMAGE(fec_buffer(3)) & " " & - std_logic'IMAGE(fec_buffer(4)) & std_logic'IMAGE(fec_buffer(5)) & " " & - std_logic'IMAGE(fec_buffer(6)) & std_logic'IMAGE(fec_buffer(7)) & " " & - std_logic'IMAGE(fec_buffer(8)) & std_logic'IMAGE(fec_buffer(9)) & " " & - std_logic'IMAGE(fec_buffer(10)) & std_logic'IMAGE(fec_buffer(11)) & " " & - std_logic'IMAGE(fec_buffer(12)) & std_logic'IMAGE(fec_buffer(13)) & " " & - std_logic'IMAGE(fec_buffer(14)) & std_logic'IMAGE(fec_buffer(15)); - END IF; - bit_idx <= 0; - byte_idx <= byte_idx + 1; - END IF; + IF bit_idx < ENCODED_BITS THEN + fec_buffer(bit_idx) <= randomized_buffer(bit_idx / 16)((bit_idx / 2) MOD 8); + bit_idx <= bit_idx + 1; ELSE - REPORT "FEC_ENCODE complete, " & INTEGER'IMAGE(ENCODED_BITS) & " bits produced"; - byte_idx <= 0; bit_idx <= 0; state <= INTERLEAVE; END IF; - -- INTERLEAVE: Shuffle bits via row-column interleaver + -- INTERLEAVE: Row-column interleaving WHEN INTERLEAVE => IF bit_idx < ENCODED_BITS THEN interleaved_buffer(interleave_address(bit_idx)) <= fec_buffer(bit_idx); bit_idx <= bit_idx + 1; ELSE - REPORT "INTERLEAVE complete"; - bit_idx <= 0; out_idx <= 0; state <= OUTPUT; + m_tvalid_reg <= '0'; END IF; - -- OUTPUT: Send bytes to deserializer - - - - + -- OUTPUT: Send 268 bytes via AXI-Stream WHEN OUTPUT => - IF m_axis_tready = '1' OR m_tvalid_reg = '0' THEN - IF out_idx < ENCODED_BYTES THEN - -- Pack 8 bits into a byte - m_tdata_reg(0) <= interleaved_buffer(out_idx * 8 + 0); - m_tdata_reg(1) <= interleaved_buffer(out_idx * 8 + 1); - m_tdata_reg(2) <= interleaved_buffer(out_idx * 8 + 2); - m_tdata_reg(3) <= interleaved_buffer(out_idx * 8 + 3); - m_tdata_reg(4) <= interleaved_buffer(out_idx * 8 + 4); - m_tdata_reg(5) <= interleaved_buffer(out_idx * 8 + 5); - m_tdata_reg(6) <= interleaved_buffer(out_idx * 8 + 6); - m_tdata_reg(7) <= interleaved_buffer(out_idx * 8 + 7); - - m_tvalid_reg <= '1'; - - -- Debug reports... - IF out_idx < 5 THEN - REPORT "OUTPUT[" & INTEGER'IMAGE(out_idx) & "] bits: " & - std_logic'IMAGE(interleaved_buffer(out_idx * 8 + 7)) & - std_logic'IMAGE(interleaved_buffer(out_idx * 8 + 6)) & - std_logic'IMAGE(interleaved_buffer(out_idx * 8 + 5)) & - std_logic'IMAGE(interleaved_buffer(out_idx * 8 + 4)) & - std_logic'IMAGE(interleaved_buffer(out_idx * 8 + 3)) & - std_logic'IMAGE(interleaved_buffer(out_idx * 8 + 2)) & - std_logic'IMAGE(interleaved_buffer(out_idx * 8 + 1)) & - std_logic'IMAGE(interleaved_buffer(out_idx * 8 + 0)); - END IF; - - -- Set tlast on final byte - IF out_idx = ENCODED_BYTES - 1 THEN - m_tlast_reg <= '1'; + IF out_idx < ENCODED_BYTES THEN + m_tdata_reg(0) <= interleaved_buffer(out_idx * 8 + 0); + m_tdata_reg(1) <= interleaved_buffer(out_idx * 8 + 1); + m_tdata_reg(2) <= interleaved_buffer(out_idx * 8 + 2); + m_tdata_reg(3) <= interleaved_buffer(out_idx * 8 + 3); + m_tdata_reg(4) <= interleaved_buffer(out_idx * 8 + 4); + m_tdata_reg(5) <= interleaved_buffer(out_idx * 8 + 5); + m_tdata_reg(6) <= interleaved_buffer(out_idx * 8 + 6); + m_tdata_reg(7) <= interleaved_buffer(out_idx * 8 + 7); + + m_tvalid_reg <= '1'; + m_tlast_reg <= '1' WHEN out_idx = (ENCODED_BYTES - 1) ELSE '0'; + + IF m_axis_tready = '1' THEN + IF out_idx = (ENCODED_BYTES - 1) THEN + frame_count <= frame_count + 1; + state <= IDLE; + m_tvalid_reg <= '0'; ELSE - m_tlast_reg <= '0'; + out_idx <= out_idx + 1; END IF; - - out_idx <= out_idx + 1; - ELSE - -- Frame complete - m_tvalid_reg <= '0'; - m_tlast_reg <= '0'; - frame_count <= frame_count + 1; - state <= IDLE; END IF; END IF; - - - - - - - - - + END CASE; END IF; END IF; From f9b7ab04526f7827e85a2bf3dc8cc610b4525be7 Mon Sep 17 00:00:00 2001 From: Abraxas3d Date: Wed, 19 Nov 2025 08:04:14 -0800 Subject: [PATCH 39/60] new encoder and decoder files added to the list in msk_top_ip.tcl --- library/msk_top_ip.tcl | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/library/msk_top_ip.tcl b/library/msk_top_ip.tcl index d2a85db..7ac6586 100644 --- a/library/msk_top_ip.tcl +++ b/library/msk_top_ip.tcl @@ -11,6 +11,10 @@ read_vhdl -vhdl2008 "../rdl/src/reg_utils.vhd" read_vhdl "../rdl/outputs/rtl/msk_top_regs_pkg.vhd" read_vhdl -vhdl2008 "../rdl/outputs/rtl/msk_top_regs.vhd" +# OV frame encoder/decoder require VHDL-2008 for division/modulo operators +read_vhdl -vhdl2008 "../src/ov_frame_encoder.vhd" +read_vhdl -vhdl2008 "../src/ov_frame_decoder.vhd" + #set_property FILE_TYPE {VHDL 2008} [get_files $ad_hdl_dir/library/msk_top/src/*.vhd] adi_ip_files msk_top [list \ "../msk_demodulator/src/costas_loop.vhd" \ @@ -75,4 +79,3 @@ adi_add_bus_clock "s_axis_aclk" "m_axis" "s_axis_aresetn" ipx::save_core [ipx::current_core] ipx::save_core [ipx::current_core] - From eae5b6046ee3c4ac9ace9782a40ae4437c5a7585 Mon Sep 17 00:00:00 2001 From: Abraxas3d Date: Wed, 19 Nov 2025 23:45:26 -0800 Subject: [PATCH 40/60] added hard decision convolutional encoder and decoder --- library/msk_top_ip.tcl | 8 +- msk_demodulator | 2 +- src/conv_encoder_k7.vhd | 162 ++++++++++++++ src/frame_sync_detector.vhd | 4 + src/msk_top.vhd | 7 +- src/ov_frame_decoder.vhd | 79 +++++-- src/ov_frame_encoder.vhd | 53 ++++- src/viterbi_decoder_k7.vhd | 358 ++++++++++++++++++++++++++++++ src/viterbi_decoder_k7_simple.vhd | 251 +++++++++++++++++++++ 9 files changed, 892 insertions(+), 32 deletions(-) create mode 100644 src/conv_encoder_k7.vhd create mode 100644 src/viterbi_decoder_k7.vhd create mode 100644 src/viterbi_decoder_k7_simple.vhd diff --git a/library/msk_top_ip.tcl b/library/msk_top_ip.tcl index 7ac6586..774faa7 100644 --- a/library/msk_top_ip.tcl +++ b/library/msk_top_ip.tcl @@ -15,8 +15,11 @@ read_vhdl -vhdl2008 "../rdl/outputs/rtl/msk_top_regs.vhd" read_vhdl -vhdl2008 "../src/ov_frame_encoder.vhd" read_vhdl -vhdl2008 "../src/ov_frame_decoder.vhd" + #set_property FILE_TYPE {VHDL 2008} [get_files $ad_hdl_dir/library/msk_top/src/*.vhd] adi_ip_files msk_top [list \ + "../src/conv_encoder_k7.vhd" \ + "../src/viterbi_decoder_k7_simple.vhd" \ "../msk_demodulator/src/costas_loop.vhd" \ "../pi_controller/src/pi_controller.vhd" \ "../lowpass_ema/src/lowpass_ema.vhd" \ @@ -31,13 +34,16 @@ adi_ip_files msk_top [list \ "../src/axis_dma_adapter.vhd" \ "../src/axis_async_fifo.vhd" \ "../src/byte_to_bit_deserializer.vhd" \ - "../src/bit_to_byte_serializer.vhd" \ "../src/frame_sync_detector.vhd" \ "../nco/src/nco.vhd" \ "../prbs/src/prbs_gen.vhd" \ "../prbs/src/prbs_mon.vhd" \ "../nco/src/sin_cos_lut.vhd" ] +# Set VHDL-2008 for FEC files +set_property FILE_TYPE {VHDL 2008} [get_files "../src/conv_encoder_k7.vhd"] +set_property FILE_TYPE {VHDL 2008} [get_files "../src/viterbi_decoder_k7_simple.vhd"] + # use this command if we have AXI lite interface for register control adi_ip_properties msk_top diff --git a/msk_demodulator b/msk_demodulator index e837e29..f62469a 160000 --- a/msk_demodulator +++ b/msk_demodulator @@ -1 +1 @@ -Subproject commit e837e291cc2ad3c503b54203de741e27dbe4a6eb +Subproject commit f62469ac3af2481f4f79027ef0eafbec06782c71 diff --git a/src/conv_encoder_k7.vhd b/src/conv_encoder_k7.vhd new file mode 100644 index 0000000..6f3fbe4 --- /dev/null +++ b/src/conv_encoder_k7.vhd @@ -0,0 +1,162 @@ +------------------------------------------------------------------------------------------------------ +-- K=7 Convolutional Encoder (FIXED - No Signal Timing Bugs) +------------------------------------------------------------------------------------------------------ +-- Rate 1/2, constraint length K=7 +-- Generator polynomials: G1 = 171 octal = 1111001 binary +-- G2 = 133 octal = 1011011 binary +------------------------------------------------------------------------------------------------------ + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY conv_encoder_k7 IS + GENERIC ( + PAYLOAD_BYTES : NATURAL := 134; -- Input size in bytes + ENCODED_BYTES : NATURAL := 268 -- Output size in bytes (2x for rate 1/2) + ); + PORT ( + clk : IN std_logic; + aresetn : IN std_logic; + + start : IN std_logic; + busy : OUT std_logic; + done : OUT std_logic; + + input_buffer : IN std_logic_vector(PAYLOAD_BYTES*8-1 DOWNTO 0); + output_buffer : OUT std_logic_vector(ENCODED_BYTES*8-1 DOWNTO 0) + ); +END ENTITY conv_encoder_k7; + +ARCHITECTURE rtl OF conv_encoder_k7 IS + + TYPE state_t IS (IDLE, ENCODE_DATA, FLUSH_TRELLIS, COMPLETE); + SIGNAL state : state_t := IDLE; + + SIGNAL input_bit_count : NATURAL RANGE 0 TO PAYLOAD_BYTES*8; + SIGNAL output_bit_count : NATURAL RANGE 0 TO ENCODED_BYTES*8; + + CONSTANT G1_POLY : std_logic_vector(6 DOWNTO 0) := "1111001"; + CONSTANT G2_POLY : std_logic_vector(6 DOWNTO 0) := "1011011"; + + SIGNAL out_buf : std_logic_vector(ENCODED_BYTES*8-1 DOWNTO 0); + + ATTRIBUTE ram_style : STRING; + ATTRIBUTE ram_style OF out_buf : SIGNAL IS "block"; + + -- Function to compute encoder outputs + FUNCTION compute_outputs( + current_bit : std_logic; + shift_reg : std_logic_vector(5 DOWNTO 0) + ) RETURN std_logic_vector IS + VARIABLE full_state : std_logic_vector(6 DOWNTO 0); + VARIABLE g1, g2 : std_logic; + BEGIN + full_state := current_bit & shift_reg; + + -- G1 output + g1 := '0'; + FOR i IN 0 TO 6 LOOP + IF G1_POLY(i) = '1' THEN + g1 := g1 XOR full_state(6-i); + END IF; + END LOOP; + + -- G2 output + g2 := '0'; + FOR i IN 0 TO 6 LOOP + IF G2_POLY(i) = '1' THEN + g2 := g2 XOR full_state(6-i); + END IF; + END LOOP; + + RETURN g1 & g2; -- Return as 2-bit vector + END FUNCTION; + +BEGIN + + PROCESS(clk, aresetn) + VARIABLE shift_reg : std_logic_vector(5 DOWNTO 0); + VARIABLE current_bit : std_logic; + VARIABLE outputs : std_logic_vector(1 DOWNTO 0); + BEGIN + IF aresetn = '0' THEN + state <= IDLE; + shift_reg := (OTHERS => '0'); + input_bit_count <= 0; + output_bit_count <= 0; + busy <= '0'; + done <= '0'; + out_buf <= (OTHERS => '0'); + + ELSIF rising_edge(clk) THEN + done <= '0'; + + CASE state IS + + WHEN IDLE => + busy <= '0'; + IF start = '1' THEN + state <= ENCODE_DATA; + busy <= '1'; + shift_reg := (OTHERS => '0'); + input_bit_count <= 0; + output_bit_count <= 0; + END IF; + + WHEN ENCODE_DATA => + -- Process 1,070 bits (stop 2 bits early for tail) + IF input_bit_count < PAYLOAD_BYTES*8 - 2 THEN + -- Read input bit (MSB first) + current_bit := input_buffer(PAYLOAD_BYTES*8 - 1 - input_bit_count); + + -- Compute outputs using current state + outputs := compute_outputs(current_bit, shift_reg); + + -- Store outputs (g1 first, then g2) + out_buf(ENCODED_BYTES*8 - 1 - output_bit_count) <= outputs(1); -- g1 + out_buf(ENCODED_BYTES*8 - 2 - output_bit_count) <= outputs(0); -- g2 + + -- Update shift register + shift_reg := shift_reg(4 DOWNTO 0) & current_bit; + + input_bit_count <= input_bit_count + 1; + output_bit_count <= output_bit_count + 2; + ELSE + state <= FLUSH_TRELLIS; + input_bit_count <= 0; + END IF; + + WHEN FLUSH_TRELLIS => + -- Add 2 tail bits (produces 4 encoded bits) + IF input_bit_count < 2 THEN + current_bit := '0'; + + -- Compute outputs + outputs := compute_outputs(current_bit, shift_reg); + + -- Store outputs + out_buf(ENCODED_BYTES*8 - 1 - output_bit_count) <= outputs(1); + out_buf(ENCODED_BYTES*8 - 2 - output_bit_count) <= outputs(0); + + -- Update shift register + shift_reg := shift_reg(4 DOWNTO 0) & '0'; + + input_bit_count <= input_bit_count + 1; + output_bit_count <= output_bit_count + 2; + ELSE + state <= COMPLETE; + END IF; + + WHEN COMPLETE => + done <= '1'; + busy <= '0'; + state <= IDLE; + + END CASE; + END IF; + END PROCESS; + + output_buffer <= out_buf; + +END ARCHITECTURE rtl; diff --git a/src/frame_sync_detector.vhd b/src/frame_sync_detector.vhd index bce92a3..4fbc9ef 100644 --- a/src/frame_sync_detector.vhd +++ b/src/frame_sync_detector.vhd @@ -50,6 +50,10 @@ ENTITY frame_sync_detector IS -- BIT Input Interface rx_bit : IN std_logic; rx_bit_valid : IN std_logic; + + -- soft decision signals + s_axis_soft_tdata : IN signed(15 DOWNTO 0); -- Soft decision input + m_axis_soft_tdata : OUT signed(15 DOWNTO 0); -- Soft decision output -- AXIS Master Interface (to FIFO) m_axis_tdata : OUT std_logic_vector(7 DOWNTO 0); diff --git a/src/msk_top.vhd b/src/msk_top.vhd index 2c02f60..40c3d25 100644 --- a/src/msk_top.vhd +++ b/src/msk_top.vhd @@ -244,6 +244,9 @@ ARCHITECTURE struct OF msk_top IS SIGNAL rx_data_int : std_logic_vector(S_AXIS_DATA_W -1 DOWNTO 0); SIGNAL rx_invert : std_logic; + SIGNAL rx_data_soft : signed(15 downto 0); + SIGNAL rx_data_soft_valid : std_logic; + SIGNAL rx_sample_clk : std_logic; SIGNAL discard_rxsamples: std_logic_vector(7 DOWNTO 0); SIGNAL discard_rxnco : std_logic_vector(7 DOWNTO 0); @@ -555,6 +558,7 @@ BEGIN rx_bit => rx_bit_corr, rx_bit_valid => rx_bit_valid, + s_axis_soft_tdata => (OTHERS => '0'), -- tied to zero for hard decisions m_axis_tdata => sync_det_tdata, m_axis_tvalid => sync_det_tvalid, @@ -745,7 +749,8 @@ BEGIN rx_svalid => rx_sample_clk, rx_samples => rx_samples_dec(11 DOWNTO 0), - rx_data => rx_bit, + rx_data => rx_bit, -- hard decision + rx_data_soft => rx_data_soft, -- soft decision rx_dvalid => rx_bit_valid ); diff --git a/src/ov_frame_decoder.vhd b/src/ov_frame_decoder.vhd index 6c792a2..875e67f 100644 --- a/src/ov_frame_decoder.vhd +++ b/src/ov_frame_decoder.vhd @@ -87,7 +87,7 @@ END ENTITY ov_frame_decoder; ARCHITECTURE rtl OF ov_frame_decoder IS -- State machine - TYPE state_t IS (IDLE, COLLECT, DEINTERLEAVE, FEC_DECODE, DERANDOMIZE, OUTPUT); + TYPE state_t IS (IDLE, COLLECT, DEINTERLEAVE, PREP_FEC_DECODE, FEC_DECODE, DERANDOMIZE, OUTPUT); SIGNAL state : state_t := IDLE; -- Buffer types @@ -135,6 +135,14 @@ ARCHITECTURE rtl OF ov_frame_decoder IS x"9D", x"8E", x"E8", x"34", x"C9", x"59" ); + -- Viterbi decoder signals + SIGNAL decoder_start : std_logic := '0'; + SIGNAL decoder_busy : std_logic; + SIGNAL decoder_done : std_logic; + SIGNAL decoder_input_g1 : std_logic_vector(2143 DOWNTO 0); -- 268*8 bits + SIGNAL decoder_input_g2 : std_logic_vector(2143 DOWNTO 0); + SIGNAL decoder_output_buf : std_logic_vector(1071 DOWNTO 0); -- 134*8 bits + -- Deinterleaver address calculation (reverse of interleaver) FUNCTION deinterleave_address(addr : NATURAL) RETURN NATURAL IS CONSTANT ROWS : NATURAL := 67; @@ -149,6 +157,24 @@ ARCHITECTURE rtl OF ov_frame_decoder IS BEGIN + -- Viterbi Decoder Instantiation (Hard Decision) + U_DECODER : ENTITY work.viterbi_decoder_k7_simple + GENERIC MAP ( + PAYLOAD_BITS => PAYLOAD_BYTES * 8, -- 1072 bits + ENCODED_BITS => ENCODED_BYTES * 8, -- 2144 bits + TRACEBACK_DEPTH => 35 + ) + PORT MAP ( + clk => clk, + aresetn => aresetn, + start => decoder_start, + busy => decoder_busy, + done => decoder_done, + input_bits_g1 => decoder_input_g1, + input_bits_g2 => decoder_input_g2, + output_bits => decoder_output_buf + ); + -- Output assignments m_axis_tdata <= m_tdata_reg; m_axis_tvalid <= m_tvalid_reg; @@ -171,6 +197,7 @@ BEGIN m_tvalid_reg <= '0'; m_tlast_reg <= '0'; decoder_active <= '0'; + decoder_start <= '0'; -- Initialize FEC decoder control ELSE CASE state IS @@ -269,29 +296,37 @@ BEGIN REPORT "DEINTERLEAVE complete"; byte_idx <= 0; bit_idx <= 0; - state <= FEC_DECODE; - END IF; - - -- FEC_DECODE: Majority vote on bit pairs - WHEN FEC_DECODE => - IF byte_idx < PAYLOAD_BYTES THEN - -- Process one bit position at a time - IF bit_idx < 8 THEN - bit_0 := deinterleaved_buffer(byte_idx * 16 + bit_idx * 2); - bit_1 := deinterleaved_buffer(byte_idx * 16 + bit_idx * 2 + 1); - fec_decoded_buffer(byte_idx)(bit_idx) <= bit_0 OR bit_1; - bit_idx <= bit_idx + 1; - ELSE - -- Done with this byte, move to next - bit_idx <= 0; - byte_idx <= byte_idx + 1; - END IF; - ELSE - REPORT "FEC_DECODE complete"; - byte_idx <= 0; - state <= DERANDOMIZE; + state <= PREP_FEC_DECODE; -- Changed to go to prep state first END IF; + -- PREP_FEC_DECODE: Separate deinterleaved bits into G1 and G2 streams +WHEN PREP_FEC_DECODE => + -- **FIX: Pack bits in FORWARD order, not reversed!** + -- deinterleaved_buffer[0] = first g1, [1] = first g2, etc. + FOR i IN 0 TO ENCODED_BITS/2 - 1 LOOP + decoder_input_g1(i) <= deinterleaved_buffer(i*2); -- G1 bits: 0, 2, 4, ... + decoder_input_g2(i) <= deinterleaved_buffer(i*2 + 1); -- G2 bits: 1, 3, 5, ... + END LOOP; + decoder_start <= '1'; + state <= FEC_DECODE; + +WHEN FEC_DECODE => + decoder_start <= '0'; -- Clear start pulse + IF decoder_done = '1' THEN + -- Unpack decoded bits in FORWARD order + -- decoder_output_buf[0] = first bit, goes to byte 0 bit 7 + FOR i IN 0 TO PAYLOAD_BYTES-1 LOOP + FOR j IN 0 TO 7 LOOP + fec_decoded_buffer(i)(7-j) <= decoder_output_buf(i*8 + j); + END LOOP; + END LOOP; + byte_idx <= 0; + state <= DERANDOMIZE; + END IF; + + + + -- DERANDOMIZE: XOR with same sequence (inverse operation) WHEN DERANDOMIZE => IF byte_idx < PAYLOAD_BYTES THEN diff --git a/src/ov_frame_encoder.vhd b/src/ov_frame_encoder.vhd index 8e1d646..cfe24fc 100644 --- a/src/ov_frame_encoder.vhd +++ b/src/ov_frame_encoder.vhd @@ -89,7 +89,7 @@ END ENTITY ov_frame_encoder; ARCHITECTURE rtl OF ov_frame_encoder IS -- State machine - TYPE state_t IS (IDLE, COLLECT, EXTRACT, RANDOMIZE, FEC_ENCODE, INTERLEAVE, OUTPUT); + TYPE state_t IS (IDLE, COLLECT, EXTRACT, RANDOMIZE, PREP_FEC, FEC_ENCODE, INTERLEAVE, OUTPUT); SIGNAL state : state_t := IDLE; -- Buffer types @@ -142,6 +142,13 @@ ARCHITECTURE rtl OF ov_frame_encoder IS x"15", x"ED", x"35", x"F4", x"57", x"F5", x"58", x"11", x"9D", x"8E", x"E8", x"34", x"C9", x"59" ); + + -- Viterbi encoder signals + SIGNAL encoder_start : std_logic := '0'; + SIGNAL encoder_busy : std_logic; + SIGNAL encoder_done : std_logic; + SIGNAL encoder_input_buf : std_logic_vector(1071 DOWNTO 0); -- 134*8 + SIGNAL encoder_output_buf : std_logic_vector(2143 DOWNTO 0); -- 268*8 -- Interleaver address calculation (67 rows x 32 cols) FUNCTION interleave_address(addr : NATURAL) RETURN NATURAL IS @@ -157,6 +164,22 @@ ARCHITECTURE rtl OF ov_frame_encoder IS BEGIN + -- Convolutional Encoder Instantiation + U_ENCODER : ENTITY work.conv_encoder_k7 + GENERIC MAP ( + PAYLOAD_BYTES => PAYLOAD_BYTES, + ENCODED_BYTES => ENCODED_BYTES + ) + PORT MAP ( + clk => clk, + aresetn => aresetn, + start => encoder_start, + busy => encoder_busy, + done => encoder_done, + input_buffer => encoder_input_buf, + output_buffer => encoder_output_buf + ); + -- Connect output registers to ports m_axis_tdata <= m_tdata_reg; m_axis_tvalid <= m_tvalid_reg; @@ -179,6 +202,7 @@ BEGIN m_tvalid_reg <= '0'; m_tlast_reg <= '0'; frame_count <= (OTHERS => '0'); + encoder_start <= '0'; -- Initialize FEC encoder control; ELSIF rising_edge(clk) THEN IF aresetn = '1' THEN @@ -258,18 +282,33 @@ BEGIN ELSE byte_idx <= 0; bit_idx <= 0; - state <= FEC_ENCODE; + state <= PREP_FEC; -- Changed from FEC_ENCODE END IF; - -- FEC_ENCODE: Simple rate-1/2 code (bit duplication) +WHEN PREP_FEC => + -- Pack randomized_buffer MSB-first to match encoder's MSB-first reading + FOR i IN 0 TO PAYLOAD_BYTES-1 LOOP + FOR j IN 0 TO 7 LOOP + -- Put byte 0 at top of buffer, MSB of each byte first + encoder_input_buf(PAYLOAD_BYTES*8 - 1 - (i*8 + j)) <= randomized_buffer(i)(7-j); + END LOOP; + END LOOP; + encoder_start <= '1'; + state <= FEC_ENCODE; + + -- FEC_ENCODE: Wait for convolution encoder to complete WHEN FEC_ENCODE => - IF bit_idx < ENCODED_BITS THEN - fec_buffer(bit_idx) <= randomized_buffer(bit_idx / 16)((bit_idx / 2) MOD 8); - bit_idx <= bit_idx + 1; - ELSE + encoder_start <= '0'; -- Clear start pulse + IF encoder_done = '1' THEN + -- Unpack encoded bits into fec_buffer + FOR i IN 0 TO ENCODED_BITS-1 LOOP + fec_buffer(i) <= encoder_output_buf(ENCODED_BITS - 1 - i); -- MSB-first + --fec_buffer(i) <= encoder_output_buf(i); + END LOOP; bit_idx <= 0; state <= INTERLEAVE; END IF; + -- INTERLEAVE: Row-column interleaving WHEN INTERLEAVE => diff --git a/src/viterbi_decoder_k7.vhd b/src/viterbi_decoder_k7.vhd new file mode 100644 index 0000000..3539c94 --- /dev/null +++ b/src/viterbi_decoder_k7.vhd @@ -0,0 +1,358 @@ +------------------------------------------------------------------------------------------------------ +-- Soft-Decision Viterbi Decoder for K=7 Convolutional Code +------------------------------------------------------------------------------------------------------ +-- Rate 1/2, constraint length K=7, 64 states +-- Generator polynomials: G1 = 171 octal, G2 = 133 octal (NASA Voyager code) +-- +-- Supports both hard-decision (1-bit) and soft-decision (3-4 bit) inputs +-- Uses register-exchange for survivor path management (simpler than traceback memory) +-- +-- Performance: +-- Hard decisions: ~5 dB coding gain at BER=10^-5 +-- 3-bit soft: ~7 dB coding gain (2 dB improvement over hard) +-- 4-bit soft: ~7.3 dB coding gain (marginal improvement over 3-bit) +-- +-- Think of this like a maze solver that tracks 64 parallel adventurer parties, +-- keeping only the most efficient path to each destination +------------------------------------------------------------------------------------------------------ + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY viterbi_decoder_k7 IS + GENERIC ( + PAYLOAD_BYTES : NATURAL := 134; -- Output size in bytes + ENCODED_BYTES : NATURAL := 268; -- Input size in bytes + SOFT_DECISION_WIDTH : NATURAL := 3; -- Bits per soft input (1=hard, 3-4=soft) + TRACEBACK_DEPTH : NATURAL := 35; -- Path memory depth (5*K is typical) + METRIC_WIDTH : NATURAL := 12 -- Path metric width (avoid overflow) + ); + PORT ( + clk : IN std_logic; + aresetn : IN std_logic; + + -- Control + start : IN std_logic; + busy : OUT std_logic; + done : OUT std_logic; + + -- Input buffer (soft decisions, MSB first) + -- For hard decisions: use only MSB of each symbol + -- For soft decisions: full SOFT_DECISION_WIDTH bits represent confidence + -- Most positive value = strong '1', most negative = strong '0' + input_buffer_g1 : IN std_logic_vector(ENCODED_BYTES*4-1 DOWNTO 0); + input_buffer_g2 : IN std_logic_vector(ENCODED_BYTES*4-1 DOWNTO 0); + + -- Output buffer (decoded bits, MSB first) + output_buffer : OUT std_logic_vector(PAYLOAD_BYTES*8-1 DOWNTO 0); + + -- Debug/monitoring + path_metric_min : OUT std_logic_vector(METRIC_WIDTH-1 DOWNTO 0); + path_metric_max : OUT std_logic_vector(METRIC_WIDTH-1 DOWNTO 0) + ); +END ENTITY viterbi_decoder_k7; + +ARCHITECTURE rtl OF viterbi_decoder_k7 IS + + CONSTANT NUM_STATES : NATURAL := 64; -- 2^(K-1) states + CONSTANT TRACEBACK_LENGTH : NATURAL := TRACEBACK_DEPTH; + + -- State machine + TYPE state_t IS (IDLE, INIT_METRICS, DECODE_BITS, TRACEBACK, COMPLETE); + SIGNAL state : state_t := IDLE; + + -- Path metrics: one metric per state (track cumulative "cost" to reach each state) + TYPE metric_array_t IS ARRAY(0 TO NUM_STATES-1) OF signed(METRIC_WIDTH-1 DOWNTO 0); + SIGNAL path_metrics_curr : metric_array_t := (OTHERS => (OTHERS => '0')); + SIGNAL path_metrics_next : metric_array_t := (OTHERS => (OTHERS => '0')); + + -- Survivor path memory: register-exchange method + -- Each state stores its best path history + TYPE path_history_t IS ARRAY(0 TO TRACEBACK_LENGTH-1) OF std_logic; + TYPE survivor_memory_t IS ARRAY(0 TO NUM_STATES-1) OF path_history_t; + SIGNAL survivor_paths_curr : survivor_memory_t; + SIGNAL survivor_paths_next : survivor_memory_t; + + -- Branch metrics: cost to take each transition + SIGNAL branch_metric_00 : signed(METRIC_WIDTH-1 DOWNTO 0); -- Output = 00 + SIGNAL branch_metric_01 : signed(METRIC_WIDTH-1 DOWNTO 0); -- Output = 01 + SIGNAL branch_metric_10 : signed(METRIC_WIDTH-1 DOWNTO 0); -- Output = 10 + SIGNAL branch_metric_11 : signed(METRIC_WIDTH-1 DOWNTO 0); -- Output = 11 + + -- Bit processing + SIGNAL bit_index : NATURAL RANGE 0 TO ENCODED_BYTES*4; + SIGNAL output_bit_index : NATURAL RANGE 0 TO PAYLOAD_BYTES*8; + + -- Current received symbols (soft decisions) + SIGNAL rx_g1 : signed(SOFT_DECISION_WIDTH-1 DOWNTO 0); + SIGNAL rx_g2 : signed(SOFT_DECISION_WIDTH-1 DOWNTO 0); + + -- Trellis butterfly outputs (expected G1, G2 for each input bit) + TYPE output_lut_t IS ARRAY(0 TO NUM_STATES-1, 0 TO 1) OF std_logic_vector(1 DOWNTO 0); + SIGNAL expected_outputs : output_lut_t; + + -- Output buffer working copy + SIGNAL out_buf : std_logic_vector(PAYLOAD_BYTES*8-1 DOWNTO 0); + + -- Best path tracking for traceback + SIGNAL best_state : NATURAL RANGE 0 TO NUM_STATES-1; + SIGNAL traceback_bit : NATURAL RANGE 0 TO TRACEBACK_LENGTH-1; + + -------------------------------------------------------------------------------------------- + -- Precompute expected outputs for each state transition + -- This is the trellis structure for K=7, rate 1/2 code + -------------------------------------------------------------------------------------------- + FUNCTION compute_expected_output( + current_state : NATURAL; + input_bit : std_logic + ) RETURN std_logic_vector IS + VARIABLE full_state : std_logic_vector(6 DOWNTO 0); + VARIABLE g1, g2 : std_logic; + CONSTANT G1_POLY : std_logic_vector(6 DOWNTO 0) := "1111001"; + CONSTANT G2_POLY : std_logic_vector(6 DOWNTO 0) := "1011011"; + BEGIN + -- Construct full state (input bit + 6 state bits) + full_state := input_bit & std_logic_vector(to_unsigned(current_state, 6)); + + -- Compute G1 output + g1 := '0'; + FOR i IN 0 TO 6 LOOP + IF G1_POLY(i) = '1' THEN + g1 := g1 XOR full_state(6-i); + END IF; + END LOOP; + + -- Compute G2 output + g2 := '0'; + FOR i IN 0 TO 6 LOOP + IF G2_POLY(i) = '1' THEN + g2 := g2 XOR full_state(6-i); + END IF; + END LOOP; + + RETURN g1 & g2; + END FUNCTION; + +BEGIN + + -------------------------------------------------------------------------------------------- + -- Initialize expected output LUT (done once at elaboration time) + -------------------------------------------------------------------------------------------- + gen_lut: PROCESS + BEGIN + FOR s IN 0 TO NUM_STATES-1 LOOP + expected_outputs(s, 0) <= compute_expected_output(s, '0'); + expected_outputs(s, 1) <= compute_expected_output(s, '1'); + END LOOP; + WAIT; -- Static initialization + END PROCESS; + + -------------------------------------------------------------------------------------------- + -- Branch Metric Computation + -- For soft decisions: Euclidean distance between received and expected + -- For hard decisions: Hamming distance + -------------------------------------------------------------------------------------------- + PROCESS(rx_g1, rx_g2) + VARIABLE diff_g1, diff_g2 : signed(SOFT_DECISION_WIDTH DOWNTO 0); + VARIABLE metric : signed(METRIC_WIDTH-1 DOWNTO 0); + BEGIN + -- Expected output 00 (both symbols are '0' = most negative value) + diff_g1 := resize(rx_g1, SOFT_DECISION_WIDTH+1) + + to_signed(2**(SOFT_DECISION_WIDTH-1), SOFT_DECISION_WIDTH+1); + diff_g2 := resize(rx_g2, SOFT_DECISION_WIDTH+1) + + to_signed(2**(SOFT_DECISION_WIDTH-1), SOFT_DECISION_WIDTH+1); + branch_metric_00 <= resize(diff_g1*diff_g1 + diff_g2*diff_g2, METRIC_WIDTH); + + -- Expected output 01 (g1='0', g2='1') + diff_g1 := resize(rx_g1, SOFT_DECISION_WIDTH+1) + + to_signed(2**(SOFT_DECISION_WIDTH-1), SOFT_DECISION_WIDTH+1); + diff_g2 := resize(rx_g2, SOFT_DECISION_WIDTH+1) - + to_signed(2**(SOFT_DECISION_WIDTH-1)-1, SOFT_DECISION_WIDTH+1); + branch_metric_01 <= resize(diff_g1*diff_g1 + diff_g2*diff_g2, METRIC_WIDTH); + + -- Expected output 10 + diff_g1 := resize(rx_g1, SOFT_DECISION_WIDTH+1) - + to_signed(2**(SOFT_DECISION_WIDTH-1)-1, SOFT_DECISION_WIDTH+1); + diff_g2 := resize(rx_g2, SOFT_DECISION_WIDTH+1) + + to_signed(2**(SOFT_DECISION_WIDTH-1), SOFT_DECISION_WIDTH+1); + branch_metric_10 <= resize(diff_g1*diff_g1 + diff_g2*diff_g2, METRIC_WIDTH); + + -- Expected output 11 + diff_g1 := resize(rx_g1, SOFT_DECISION_WIDTH+1) - + to_signed(2**(SOFT_DECISION_WIDTH-1)-1, SOFT_DECISION_WIDTH+1); + diff_g2 := resize(rx_g2, SOFT_DECISION_WIDTH+1) - + to_signed(2**(SOFT_DECISION_WIDTH-1)-1, SOFT_DECISION_WIDTH+1); + branch_metric_11 <= resize(diff_g1*diff_g1 + diff_g2*diff_g2, METRIC_WIDTH); + END PROCESS; + + -------------------------------------------------------------------------------------------- + -- Main Viterbi Decoder State Machine + -------------------------------------------------------------------------------------------- + PROCESS(clk, aresetn) + VARIABLE prev_state_0, prev_state_1 : NATURAL RANGE 0 TO NUM_STATES-1; + VARIABLE metric_0, metric_1 : signed(METRIC_WIDTH-1 DOWNTO 0); + VARIABLE input_bit_0, input_bit_1 : std_logic; + VARIABLE expected_out_0, expected_out_1 : std_logic_vector(1 DOWNTO 0); + VARIABLE branch_met_0, branch_met_1 : signed(METRIC_WIDTH-1 DOWNTO 0); + VARIABLE min_metric, max_metric : signed(METRIC_WIDTH-1 DOWNTO 0); + BEGIN + IF aresetn = '0' THEN + state <= IDLE; + busy <= '0'; + done <= '0'; + bit_index <= 0; + output_bit_index <= 0; + path_metrics_curr <= (OTHERS => (OTHERS => '0')); + + ELSIF rising_edge(clk) THEN + done <= '0'; -- Pulse signal + + CASE state IS + + WHEN IDLE => + busy <= '0'; + IF start = '1' THEN + state <= INIT_METRICS; + busy <= '1'; + bit_index <= 0; + output_bit_index <= 0; + END IF; + + WHEN INIT_METRICS => + -- Initialize: state 0 has metric 0, all others have large metric + FOR i IN 0 TO NUM_STATES-1 LOOP + IF i = 0 THEN + path_metrics_curr(i) <= (OTHERS => '0'); + ELSE + path_metrics_curr(i) <= to_signed(2**(METRIC_WIDTH-2), METRIC_WIDTH); + END IF; + -- Clear survivor paths + FOR j IN 0 TO TRACEBACK_LENGTH-1 LOOP + survivor_paths_curr(i)(j) <= '0'; + END LOOP; + END LOOP; + state <= DECODE_BITS; + + WHEN DECODE_BITS => + IF bit_index < (PAYLOAD_BYTES*8 + 6)*2 THEN -- Include 6 flush bits + -- Get received soft symbols + rx_g1 <= signed(input_buffer_g1( + ENCODED_BYTES*4-1 - bit_index*SOFT_DECISION_WIDTH DOWNTO + ENCODED_BYTES*4 - (bit_index+1)*SOFT_DECISION_WIDTH)); + rx_g2 <= signed(input_buffer_g2( + ENCODED_BYTES*4-1 - bit_index*SOFT_DECISION_WIDTH DOWNTO + ENCODED_BYTES*4 - (bit_index+1)*SOFT_DECISION_WIDTH)); + + -- ACS (Add-Compare-Select) for all states + FOR s IN 0 TO NUM_STATES-1 LOOP + -- Each state can be reached from two previous states + -- Previous state that led here with input bit = 0 + prev_state_0 := (s * 2) MOD NUM_STATES; + -- Previous state that led here with input bit = 1 + prev_state_1 := ((s * 2) + 1) MOD NUM_STATES; + + -- Get expected outputs for these transitions + expected_out_0 := expected_outputs(prev_state_0, 0); + expected_out_1 := expected_outputs(prev_state_1, 1); + + -- Branch metrics + CASE expected_out_0 IS + WHEN "00" => branch_met_0 := branch_metric_00; + WHEN "01" => branch_met_0 := branch_metric_01; + WHEN "10" => branch_met_0 := branch_metric_10; + WHEN "11" => branch_met_0 := branch_metric_11; + WHEN OTHERS => branch_met_0 := (OTHERS => '0'); + END CASE; + + CASE expected_out_1 IS + WHEN "00" => branch_met_1 := branch_metric_00; + WHEN "01" => branch_met_1 := branch_metric_01; + WHEN "10" => branch_met_1 := branch_metric_10; + WHEN "11" => branch_met_1 := branch_metric_11; + WHEN OTHERS => branch_met_1 := (OTHERS => '0'); + END CASE; + + -- Add-Compare-Select + metric_0 := path_metrics_curr(prev_state_0) + branch_met_0; + metric_1 := path_metrics_curr(prev_state_1) + branch_met_1; + + IF metric_0 < metric_1 THEN + path_metrics_next(s) <= metric_0; + input_bit_0 := '0'; + -- Shift survivor path and prepend decision + FOR j IN TRACEBACK_LENGTH-1 DOWNTO 1 LOOP + survivor_paths_next(s)(j) <= survivor_paths_curr(prev_state_0)(j-1); + END LOOP; + survivor_paths_next(s)(0) <= input_bit_0; + ELSE + path_metrics_next(s) <= metric_1; + input_bit_1 := '1'; + FOR j IN TRACEBACK_LENGTH-1 DOWNTO 1 LOOP + survivor_paths_next(s)(j) <= survivor_paths_curr(prev_state_1)(j-1); + END LOOP; + survivor_paths_next(s)(0) <= input_bit_1; + END IF; + END LOOP; + + -- Update current metrics + path_metrics_curr <= path_metrics_next; + survivor_paths_curr <= survivor_paths_next; + + bit_index <= bit_index + 2; -- Processed 2 symbols + ELSE + state <= TRACEBACK; + traceback_bit <= 0; + + -- Find best ending state (should be state 0 due to flush bits) + min_metric := path_metrics_curr(0); + best_state <= 0; + FOR i IN 1 TO NUM_STATES-1 LOOP + IF path_metrics_curr(i) < min_metric THEN + min_metric := path_metrics_curr(i); + best_state <= i; + END IF; + END LOOP; + END IF; + + WHEN TRACEBACK => + -- Extract decoded bits from survivor path of best state + IF traceback_bit < PAYLOAD_BYTES*8 THEN + out_buf(PAYLOAD_BYTES*8 - 1 - traceback_bit) <= + survivor_paths_curr(best_state)(TRACEBACK_LENGTH - 1 - traceback_bit); + traceback_bit <= traceback_bit + 1; + ELSE + state <= COMPLETE; + END IF; + + WHEN COMPLETE => + done <= '1'; + busy <= '0'; + state <= IDLE; + + END CASE; + END IF; + END PROCESS; + + -- Output assignment + output_buffer <= out_buf; + + -- Debug outputs + PROCESS(path_metrics_curr) + VARIABLE min_val, max_val : signed(METRIC_WIDTH-1 DOWNTO 0); + BEGIN + min_val := path_metrics_curr(0); + max_val := path_metrics_curr(0); + FOR i IN 1 TO NUM_STATES-1 LOOP + IF path_metrics_curr(i) < min_val THEN + min_val := path_metrics_curr(i); + END IF; + IF path_metrics_curr(i) > max_val THEN + max_val := path_metrics_curr(i); + END IF; + END LOOP; + path_metric_min <= std_logic_vector(min_val); + path_metric_max <= std_logic_vector(max_val); + END PROCESS; + +END ARCHITECTURE rtl; diff --git a/src/viterbi_decoder_k7_simple.vhd b/src/viterbi_decoder_k7_simple.vhd new file mode 100644 index 0000000..533e7db --- /dev/null +++ b/src/viterbi_decoder_k7_simple.vhd @@ -0,0 +1,251 @@ +------------------------------------------------------------------------------------------------------ +-- FIXED Viterbi Decoder for K=7 Code (NASA Voyager) +------------------------------------------------------------------------------------------------------ +-- Corrected Issues: +-- 1. MSB-first bit indexing to match encoder output format +-- 2. Traceback now correctly outputs input bits (LSB of state) not decision bits +------------------------------------------------------------------------------------------------------ + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY viterbi_decoder_k7_simple IS + GENERIC ( + PAYLOAD_BITS : NATURAL := 134*8; -- 1072 bits + ENCODED_BITS : NATURAL := 268*8; -- 2144 bits + TRACEBACK_DEPTH : NATURAL := 35 -- 5*K recommended + ); + PORT ( + clk : IN std_logic; + aresetn : IN std_logic; + + start : IN std_logic; + busy : OUT std_logic; + done : OUT std_logic; + + -- Hard decision inputs (g1 and g2 bits) + input_bits_g1 : IN std_logic_vector(ENCODED_BITS-1 DOWNTO 0); + input_bits_g2 : IN std_logic_vector(ENCODED_BITS-1 DOWNTO 0); + + output_bits : OUT std_logic_vector(PAYLOAD_BITS-1 DOWNTO 0) + ); +END ENTITY viterbi_decoder_k7_simple; + +ARCHITECTURE rtl OF viterbi_decoder_k7_simple IS + + CONSTANT NUM_STATES : INTEGER := 64; + CONSTANT METRIC_WIDTH : INTEGER := 12; + CONSTANT INF_METRIC : INTEGER := 4095; + + TYPE state_t IS (IDLE, INITIALIZE, ACS_COMPUTE, TRACEBACK, COMPLETE); + SIGNAL state : state_t := IDLE; + + -- Path metrics arrays are now VARIABLES in the process + TYPE metric_array_t IS ARRAY(0 TO NUM_STATES-1) OF INTEGER RANGE 0 TO INF_METRIC; + + -- Decision memory: stores which previous state was selected (MSB bit) + TYPE decision_array_t IS ARRAY(0 TO ENCODED_BITS/2) OF std_logic_vector(NUM_STATES-1 DOWNTO 0); + SIGNAL decisions : decision_array_t; + + -- Force synthesis to use BRAM + ATTRIBUTE ram_style : STRING; + ATTRIBUTE ram_style OF decisions : SIGNAL IS "block"; + + -- Counters + SIGNAL time_step : INTEGER RANGE 0 TO ENCODED_BITS/2 + 1; + SIGNAL tb_step : INTEGER RANGE -1 TO ENCODED_BITS/2; + SIGNAL output_idx : INTEGER RANGE 0 TO PAYLOAD_BITS; + + -- Current state during traceback + SIGNAL tb_state : INTEGER RANGE 0 TO NUM_STATES-1; + + -- Output buffer + SIGNAL out_buf : std_logic_vector(PAYLOAD_BITS-1 DOWNTO 0); + + -------------------------------------------------------------------------------------------- + -- Trellis functions + -------------------------------------------------------------------------------------------- + FUNCTION next_state(curr_state : INTEGER; input_bit : std_logic) RETURN INTEGER IS + VARIABLE shift_reg : std_logic_vector(5 DOWNTO 0); + BEGIN + shift_reg := std_logic_vector(to_unsigned(curr_state, 6)); + RETURN to_integer(unsigned(input_bit & shift_reg(5 DOWNTO 1))); + END FUNCTION; + + FUNCTION compute_output(curr_state : INTEGER; input_bit : std_logic) RETURN std_logic_vector IS + CONSTANT G1_POLY : std_logic_vector(6 DOWNTO 0) := "1111001"; + CONSTANT G2_POLY : std_logic_vector(6 DOWNTO 0) := "1011011"; + VARIABLE full_state : std_logic_vector(6 DOWNTO 0); + VARIABLE g1, g2 : std_logic; + BEGIN + full_state := input_bit & std_logic_vector(to_unsigned(curr_state, 6)); + + g1 := '0'; + FOR i IN 0 TO 6 LOOP + IF G1_POLY(i) = '1' THEN + g1 := g1 XOR full_state(6-i); + END IF; + END LOOP; + + g2 := '0'; + FOR i IN 0 TO 6 LOOP + IF G2_POLY(i) = '1' THEN + g2 := g2 XOR full_state(6-i); + END IF; + END LOOP; + + RETURN g1 & g2; + END FUNCTION; + + FUNCTION hamming_distance(a : std_logic_vector; b : std_logic_vector) RETURN INTEGER IS + VARIABLE dist : INTEGER := 0; + BEGIN + FOR i IN a'RANGE LOOP + IF a(i) /= b(i) THEN + dist := dist + 1; + END IF; + END LOOP; + RETURN dist; + END FUNCTION; + +BEGIN + + PROCESS(clk, aresetn) + VARIABLE received_symbol : std_logic_vector(1 DOWNTO 0); + VARIABLE expected_symbol : std_logic_vector(1 DOWNTO 0); + VARIABLE branch_metric : INTEGER; + VARIABLE new_metric : INTEGER; + VARIABLE prev_state_for_0 : INTEGER; + VARIABLE prev_state_for_1 : INTEGER; + VARIABLE metric_via_0 : INTEGER; + VARIABLE metric_via_1 : INTEGER; + VARIABLE min_metric : INTEGER; + VARIABLE best_state : INTEGER; + VARIABLE input_bit_used : INTEGER; + + -- **FIX: Use VARIABLES for metrics, not SIGNALS!** + VARIABLE metrics_old : metric_array_t; + VARIABLE metrics_new : metric_array_t; + BEGIN + IF aresetn = '0' THEN + state <= IDLE; + busy <= '0'; + done <= '0'; + time_step <= 0; + + ELSIF rising_edge(clk) THEN + done <= '0'; + + CASE state IS + + WHEN IDLE => + busy <= '0'; + IF start = '1' THEN + state <= INITIALIZE; + busy <= '1'; + time_step <= 0; + END IF; + + WHEN INITIALIZE => + -- Start with state 0 having metric 0, all others infinity + FOR i IN 0 TO NUM_STATES-1 LOOP + IF i = 0 THEN + metrics_old(i) := 0; + ELSE + metrics_old(i) := INF_METRIC; + END IF; + END LOOP; + state <= ACS_COMPUTE; + + +WHEN ACS_COMPUTE => + IF time_step < ENCODED_BITS/2 THEN + -- **FIX #1: Read bits in order starting from index 0** + -- Frame decoder packs: input_bits_g1(0)=first_g1, input_bits_g2(0)=first_g2 + -- So we read sequentially from index 0 up + received_symbol := input_bits_g1(time_step) & input_bits_g2(time_step); + + -- For each current state, find best path from two possible previous states + FOR curr_st IN 0 TO NUM_STATES-1 LOOP + -- Two prev states can lead here + prev_state_for_0 := curr_st / 2; -- Previous state with MSB=0 + prev_state_for_1 := (curr_st / 2) + 32; -- Previous state with MSB=1 + + -- The input bit that created curr_st is its LSB + input_bit_used := curr_st MOD 2; + + -- Metric via path with previous MSB=0 + expected_symbol := compute_output(prev_state_for_0, std_logic(to_unsigned(input_bit_used, 1)(0))); + branch_metric := hamming_distance(received_symbol, expected_symbol); + metric_via_0 := metrics_old(prev_state_for_0) + branch_metric; + + -- Metric via path with previous MSB=1 + expected_symbol := compute_output(prev_state_for_1, std_logic(to_unsigned(input_bit_used, 1)(0))); + branch_metric := hamming_distance(received_symbol, expected_symbol); + metric_via_1 := metrics_old(prev_state_for_1) + branch_metric; + + -- Select better path and store decision + IF metric_via_0 <= metric_via_1 THEN + metrics_new(curr_st) := metric_via_0; -- Changed to := + decisions(time_step)(curr_st) <= '0'; -- Came from prev_state_for_0 + ELSE + metrics_new(curr_st) := metric_via_1; -- Changed to := + decisions(time_step)(curr_st) <= '1'; -- Came from prev_state_for_1 + END IF; + END LOOP; + + -- Swap buffers (now happens immediately with variables!) + metrics_old := metrics_new; + time_step <= time_step + 1; + + ELSE + -- ACS complete, prepare for traceback + -- Find best final state (should be state 0 after tail bits) + min_metric := metrics_old(0); + best_state := 0; + FOR i IN 1 TO NUM_STATES-1 LOOP + IF metrics_old(i) < min_metric THEN + min_metric := metrics_old(i); + best_state := i; + END IF; + END LOOP; + + tb_state <= best_state; + tb_step <= time_step - 1; + output_idx <= 0; + state <= TRACEBACK; + END IF; + + +WHEN TRACEBACK => + IF tb_step >= 0 THEN + -- Output the decoded input bit (LSB of current state) + -- tb_step counts DOWN from last to first, giving us the natural index + out_buf(tb_step) <= std_logic(to_unsigned(tb_state MOD 2, 1)(0)); + + -- Move to previous state based on decision + IF decisions(tb_step)(tb_state) = '0' THEN + tb_state <= tb_state / 2; -- Previous state had MSB=0 + ELSE + tb_state <= (tb_state / 2) + 32; -- Previous state had MSB=1 + END IF; + + tb_step <= tb_step - 1; + ELSE + state <= COMPLETE; + END IF; + + + WHEN COMPLETE => + done <= '1'; + busy <= '0'; + state <= IDLE; + + END CASE; + END IF; + END PROCESS; + + output_bits <= out_buf; + +END ARCHITECTURE rtl; From 8ba0705263e0ce9b458b2cb911dcfe618edfba41 Mon Sep 17 00:00:00 2001 From: Abraxas3d Date: Thu, 20 Nov 2025 14:29:21 -0800 Subject: [PATCH 41/60] hard decision Viterbit decoder installed and input data equals output data to modem. Randomization, FEC, Interleaving all working as intended. --- src/axis_async_fifo.vhd | 76 +++++--- src/ov_frame_decoder.vhd | 259 +++++++++++++------------ src/ov_frame_encoder.vhd | 4 +- src/viterbi_decoder_k7_simple.vhd | 302 ++++++++++++++++-------------- 4 files changed, 339 insertions(+), 302 deletions(-) diff --git a/src/axis_async_fifo.vhd b/src/axis_async_fifo.vhd index 99fbdb3..215a0cf 100644 --- a/src/axis_async_fifo.vhd +++ b/src/axis_async_fifo.vhd @@ -1,8 +1,10 @@ ------------------------------------------------------------------------------------------------------ -- AXIS-Compliant Asynchronous FIFO ------------------------------------------------------------------------------------------------------ --- FIX: Added safety margin to empty detection to account for 2-cycle synchronization lag --- This prevents reading past actual data and hitting stale tlast markers +-- FIX v3: Proper three-state handling +-- State A: Becoming valid (empty→non-empty): Present first byte, assert tvalid +-- State B: Handshake completes (tvalid='1', tready='1'): Advance pointer, present next byte +-- State C: Valid but not consumed (tvalid='1', tready='0'): HOLD STABLE ------------------------------------------------------------------------------------------------------ -- SIGNAL INITIALIZATION PRACTICES: -- Per FPGA best practices, signals are initialized via reset blocks in their respective clock @@ -41,9 +43,6 @@ ENTITY axis_async_fifo IS m_axis_tready : IN std_logic; m_axis_tlast : OUT std_logic; - -- Control signals - --prog_packet_size: IN std_logic_vector... - -- Status signals prog_full : OUT std_logic; prog_empty : OUT std_logic; @@ -193,12 +192,16 @@ BEGIN END PROCESS write_proc; ------------------------------------------------------------------------------ - -- Read Clock Domain - WITH SYNC LAG FIX + -- Read Clock Domain - CORRECTED THREE-STATE LOGIC + ------------------------------------------------------------------------------ + -- State A: Becoming valid (tvalid_int='0' → '1'): Present first byte + -- State B: Handshake completes (tvalid='1', tready='1'): Advance, present next + -- State C: Valid but stalled (tvalid='1', tready='0'): HOLD STABLE ------------------------------------------------------------------------------ read_proc: PROCESS(rd_aclk) VARIABLE rd_ptr_bin_next : std_logic_vector(ADDR_WIDTH DOWNTO 0); VARIABLE wr_ptr_bin_sync : std_logic_vector(ADDR_WIDTH DOWNTO 0); - VARIABLE empty_next : std_logic; + VARIABLE empty_current : std_logic; BEGIN IF rising_edge(rd_aclk) THEN IF rd_aresetn = '0' THEN @@ -216,44 +219,61 @@ BEGIN wr_ptr_gray_sync2 <= wr_ptr_gray_sync1; wr_ptr_bin_sync := gray_to_bin(wr_ptr_gray_sync2); - -- Calculate next empty status based on CURRENT pointers + -- Check if FIFO is currently empty IF wr_ptr_bin_sync = rd_ptr_bin THEN - empty_next := '1'; + empty_current := '1'; ELSE - empty_next := '0'; + empty_current := '0'; END IF; - -- Present data when not empty - -- This sets up tdata, tlast, and tvalid for the CURRENT cycle - IF empty_next = '0' THEN + ---------------------------------------------------------------------- + -- THREE STATE LOGIC + ---------------------------------------------------------------------- + + -- STATE A: Becoming valid (was invalid, now have data) + -- Action: Present first byte, assert tvalid, DO NOT advance pointer + IF tvalid_int = '0' AND empty_current = '0' THEN m_axis_tdata <= ram_data(to_integer(unsigned(rd_ptr_bin(ADDR_WIDTH-1 DOWNTO 0)))); m_axis_tlast <= ram_last(to_integer(unsigned(rd_ptr_bin(ADDR_WIDTH-1 DOWNTO 0)))); tvalid_int <= '1'; - ELSE - -- When empty, deassert tvalid and clear tlast - -- (tdata is don't care per AXI-Stream spec, but we clear it for cleanliness) - tvalid_int <= '0'; - m_axis_tlast <= '0'; - m_axis_tdata <= (OTHERS => '0'); - END IF; + empty_int <= '0'; + -- rd_ptr_bin stays same! This is the first presentation - -- AXIS read handshake - advance pointer only when: - -- 1. We're presenting valid data (empty_next = '0') - -- 2. Downstream is ready (m_axis_tready = '1') - IF empty_next = '0' AND m_axis_tready = '1' THEN + -- STATE B: Handshake completes (valid and ready) + -- Action: Advance pointer, present next byte OR deassert tvalid + ELSIF tvalid_int = '1' AND m_axis_tready = '1' THEN rd_ptr_bin_next := std_logic_vector(unsigned(rd_ptr_bin) + 1); rd_ptr_bin <= rd_ptr_bin_next; rd_ptr_gray <= bin_to_gray(rd_ptr_bin_next); - -- Update empty status based on where we'll be AFTER this read + -- Check if we'll be empty after this read IF wr_ptr_bin_sync = rd_ptr_bin_next THEN + -- Going empty empty_int <= '1'; + tvalid_int <= '0'; + m_axis_tlast <= '0'; + m_axis_tdata <= (OTHERS => '0'); ELSE + -- More data available - present next byte empty_int <= '0'; + tvalid_int <= '1'; + m_axis_tdata <= ram_data(to_integer(unsigned(rd_ptr_bin_next(ADDR_WIDTH-1 DOWNTO 0)))); + m_axis_tlast <= ram_last(to_integer(unsigned(rd_ptr_bin_next(ADDR_WIDTH-1 DOWNTO 0)))); END IF; + + -- STATE C: Valid but NOT ready (tvalid='1', tready='0') + -- Action: HOLD EVERYTHING STABLE - no changes to tdata, tlast, tvalid, rd_ptr + ELSIF tvalid_int = '1' AND m_axis_tready = '0' THEN + -- Explicitly do nothing - all signals hold their values + -- This is the critical fix: maintain protocol compliance + empty_int <= '0'; -- We know we're not empty if tvalid='1' + + -- All other cases: remain invalid ELSE - -- No advancement - empty_int <= empty_next; + empty_int <= '1'; + tvalid_int <= '0'; + m_axis_tlast <= '0'; + m_axis_tdata <= (OTHERS => '0'); END IF; -- Programmable empty @@ -274,8 +294,6 @@ BEGIN BEGIN IF rising_edge(status_aclk) THEN IF status_aresetn = '0' THEN - --prog_empty <= '0'; - --prog_full <= '0'; fifo_overflow <= '0'; fifo_underflow <= '0'; status_ack <= '0'; diff --git a/src/ov_frame_decoder.vhd b/src/ov_frame_decoder.vhd index 875e67f..9d60f86 100644 --- a/src/ov_frame_decoder.vhd +++ b/src/ov_frame_decoder.vhd @@ -45,8 +45,11 @@ -- 4. Derandomizes (XOR with same fixed sequence) -- 5. Outputs 134 bytes of payload via AXI-Stream -- --- BUGFIX (2025-11-16): Fixed first-byte-lost issue in IDLE→COLLECT transition --- Now stores first byte immediately when transitioning states +-- CIRCULAR BUFFER FIX (2025-11-20): Matching encoder's proven strategy +-- - Collect ALL incoming bytes into circular buffer +-- - When tlast arrives, count back 268 bytes +-- - This handles FIFO timing issues naturally +-- - Never try to time the "first" byte arrival -- ------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------ @@ -86,17 +89,24 @@ END ENTITY ov_frame_decoder; ARCHITECTURE rtl OF ov_frame_decoder IS - -- State machine - TYPE state_t IS (IDLE, COLLECT, DEINTERLEAVE, PREP_FEC_DECODE, FEC_DECODE, DERANDOMIZE, OUTPUT); + -- State machine - ADDED EXTRACT STATE + TYPE state_t IS (IDLE, COLLECT, EXTRACT, DEINTERLEAVE, PREP_FEC_DECODE, FEC_DECODE, DERANDOMIZE, OUTPUT); SIGNAL state : state_t := IDLE; + -- Circular collection buffer (2x encoded size for safety) + CONSTANT COLLECT_SIZE : NATURAL := 512; + TYPE collect_buffer_t IS ARRAY(0 TO COLLECT_SIZE-1) OF std_logic_vector(BYTE_WIDTH-1 DOWNTO 0); + SIGNAL collect_buffer : collect_buffer_t; + SIGNAL collect_idx : NATURAL RANGE 0 TO COLLECT_SIZE-1; + -- Buffer types TYPE byte_buffer_t IS ARRAY(0 TO PAYLOAD_BYTES-1) OF std_logic_vector(BYTE_WIDTH-1 DOWNTO 0); + TYPE encoded_byte_buffer_t IS ARRAY(0 TO ENCODED_BYTES-1) OF std_logic_vector(BYTE_WIDTH-1 DOWNTO 0); TYPE bit_buffer_t IS ARRAY(0 TO ENCODED_BITS-1) OF std_logic; -- Processing buffers - SIGNAL input_buffer : bit_buffer_t := (OTHERS => '0'); -- Initialize to prevent 'U' - SIGNAL deinterleaved_buffer : bit_buffer_t := (OTHERS => '0'); -- Initialize to prevent 'U' + SIGNAL input_buffer : encoded_byte_buffer_t; -- 268 bytes extracted from circular buffer + SIGNAL deinterleaved_buffer : bit_buffer_t := (OTHERS => '0'); SIGNAL fec_decoded_buffer : byte_buffer_t; SIGNAL output_buffer : byte_buffer_t; @@ -139,9 +149,9 @@ ARCHITECTURE rtl OF ov_frame_decoder IS SIGNAL decoder_start : std_logic := '0'; SIGNAL decoder_busy : std_logic; SIGNAL decoder_done : std_logic; - SIGNAL decoder_input_g1 : std_logic_vector(2143 DOWNTO 0); -- 268*8 bits + SIGNAL decoder_input_g1 : std_logic_vector(2143 DOWNTO 0); SIGNAL decoder_input_g2 : std_logic_vector(2143 DOWNTO 0); - SIGNAL decoder_output_buf : std_logic_vector(1071 DOWNTO 0); -- 134*8 bits + SIGNAL decoder_output_buf : std_logic_vector(1071 DOWNTO 0); -- Deinterleaver address calculation (reverse of interleaver) FUNCTION deinterleave_address(addr : NATURAL) RETURN NATURAL IS @@ -160,8 +170,8 @@ BEGIN -- Viterbi Decoder Instantiation (Hard Decision) U_DECODER : ENTITY work.viterbi_decoder_k7_simple GENERIC MAP ( - PAYLOAD_BITS => PAYLOAD_BYTES * 8, -- 1072 bits - ENCODED_BITS => ENCODED_BYTES * 8, -- 2144 bits + PAYLOAD_BITS => PAYLOAD_BYTES * 8, + ENCODED_BITS => ENCODED_BYTES * 8, TRACEBACK_DEPTH => 35 ) PORT MAP ( @@ -182,9 +192,10 @@ BEGIN frames_decoded <= std_logic_vector(frame_count); - -- Main FSM + -- Main FSM with Circular Buffer Collection decoder_fsm : PROCESS(clk) - VARIABLE bit_0, bit_1 : std_logic; + VARIABLE extract_start : INTEGER; + VARIABLE extract_end : INTEGER; BEGIN IF rising_edge(clk) THEN IF aresetn = '0' THEN @@ -192,140 +203,126 @@ BEGIN byte_idx <= 0; bit_idx <= 0; out_idx <= 0; + collect_idx <= 0; frame_count <= (OTHERS => '0'); s_axis_tready <= '0'; m_tvalid_reg <= '0'; m_tlast_reg <= '0'; decoder_active <= '0'; - decoder_start <= '0'; -- Initialize FEC decoder control + decoder_start <= '0'; ELSE CASE state IS - -- IDLE: Wait for incoming data and capture first byte + -- IDLE: Ready to start collecting WHEN IDLE => decoder_active <= '0'; - s_axis_tready <= '1'; -- Ready to accept data - m_tvalid_reg <= '0'; -- Not outputting yet + s_axis_tready <= '0'; -- Keep tready LOW in IDLE + m_tvalid_reg <= '0'; + collect_idx <= 0; IF s_axis_tvalid = '1' THEN - -- *** FIX: Store the FIRST byte immediately! *** - input_buffer(0) <= s_axis_tdata(0); - input_buffer(1) <= s_axis_tdata(1); - input_buffer(2) <= s_axis_tdata(2); - input_buffer(3) <= s_axis_tdata(3); - input_buffer(4) <= s_axis_tdata(4); - input_buffer(5) <= s_axis_tdata(5); - input_buffer(6) <= s_axis_tdata(6); - input_buffer(7) <= s_axis_tdata(7); - - REPORT "DECODER: Stored FIRST byte at index 0, data=" & - INTEGER'IMAGE(to_integer(unsigned(s_axis_tdata))) & - " tlast=" & STD_LOGIC'IMAGE(s_axis_tlast)(2); - - -- Check for edge case: single-byte frame (unlikely with ENCODED_BYTES=268) - IF s_axis_tlast = '1' AND ENCODED_BYTES = 1 THEN - REPORT "DECODER: Single-byte frame received"; - byte_idx <= 0; - bit_idx <= 0; - state <= DEINTERLEAVE; - s_axis_tready <= '0'; - ELSE - -- Normal case: transition to COLLECT for remaining bytes - byte_idx <= 1; -- Next byte will go to index 1 - bit_idx <= 0; - state <= COLLECT; - decoder_active <= '1'; - END IF; + state <= COLLECT; + s_axis_tready <= '1'; -- Set tready HIGH when entering COLLECT END IF; - -- COLLECT: Gather remaining bytes (1 through 267) + -- COLLECT: Continuously store ALL incoming bytes into circular buffer WHEN COLLECT => + s_axis_tready <= '1'; -- Maintain tready HIGH during collection + IF s_axis_tvalid = '1' THEN - -- Store incoming byte as 8 bits - input_buffer(byte_idx * 8 + 0) <= s_axis_tdata(0); - input_buffer(byte_idx * 8 + 1) <= s_axis_tdata(1); - input_buffer(byte_idx * 8 + 2) <= s_axis_tdata(2); - input_buffer(byte_idx * 8 + 3) <= s_axis_tdata(3); - input_buffer(byte_idx * 8 + 4) <= s_axis_tdata(4); - input_buffer(byte_idx * 8 + 5) <= s_axis_tdata(5); - input_buffer(byte_idx * 8 + 6) <= s_axis_tdata(6); - input_buffer(byte_idx * 8 + 7) <= s_axis_tdata(7); + -- Store byte at current circular buffer position + collect_buffer(collect_idx) <= s_axis_tdata; - -- Debug: Report first 5 received bytes - IF byte_idx < 5 THEN - REPORT "DECODER: Stored byte at byte_idx=" & INTEGER'IMAGE(byte_idx) & - " data=" & INTEGER'IMAGE(to_integer(unsigned(s_axis_tdata))) & + -- Debug: Report first few bytes + IF collect_idx < 5 THEN + REPORT "COLLECT: collect_idx=" & INTEGER'IMAGE(collect_idx) & + " data=0x" & INTEGER'IMAGE(to_integer(unsigned(s_axis_tdata))) & " tlast=" & STD_LOGIC'IMAGE(s_axis_tlast)(2); END IF; - byte_idx <= byte_idx + 1; - - -- Check for frame completion + -- Check for tlast IF s_axis_tlast = '1' THEN - REPORT "DECODER: Received tlast. Total bytes stored = " & - INTEGER'IMAGE(byte_idx + 1); - - -- Verify we got the expected number of bytes - IF byte_idx + 1 /= ENCODED_BYTES THEN - REPORT "DECODER: WARNING! Expected " & INTEGER'IMAGE(ENCODED_BYTES) & - " bytes but got " & INTEGER'IMAGE(byte_idx + 1) severity warning; - END IF; + REPORT "COLLECT: tlast at collect_idx=" & INTEGER'IMAGE(collect_idx); - byte_idx <= 0; - bit_idx <= 0; - state <= DEINTERLEAVE; + -- Move to EXTRACT state to count back 268 bytes s_axis_tready <= '0'; - - ELSIF byte_idx + 1 >= ENCODED_BYTES THEN - -- Stored all bytes but no tlast! This is an error condition - REPORT "DECODER: ERROR! Stored " & INTEGER'IMAGE(ENCODED_BYTES) & - " bytes but no tlast received" severity error; byte_idx <= 0; - state <= IDLE; - s_axis_tready <= '1'; + state <= EXTRACT; + ELSE + -- Advance circular buffer pointer (wrap around) + IF collect_idx = COLLECT_SIZE - 1 THEN + collect_idx <= 0; + ELSE + collect_idx <= collect_idx + 1; + END IF; + END IF; + END IF; + + -- EXTRACT: Count back ENCODED_BYTES from where tlast arrived + WHEN EXTRACT => + IF byte_idx < ENCODED_BYTES THEN + -- Calculate which byte in collect_buffer to read + -- If collect_idx = 267, we want bytes [0:267] + -- If collect_idx = 300, we want bytes [33:300] + extract_start := (collect_idx + 1) - ENCODED_BYTES; + extract_end := collect_idx; + + -- Copy byte from circular buffer (with modulo wraparound) + input_buffer(byte_idx) <= collect_buffer((extract_start + byte_idx) MOD COLLECT_SIZE); + + IF byte_idx < 5 THEN + REPORT "EXTRACT[" & INTEGER'IMAGE(byte_idx) & + "] from collect_buffer[" & + INTEGER'IMAGE((extract_start + byte_idx) MOD COLLECT_SIZE) & + "] = 0x" & + INTEGER'IMAGE(to_integer(unsigned(collect_buffer((extract_start + byte_idx) MOD COLLECT_SIZE)))); END IF; + + byte_idx <= byte_idx + 1; + ELSE + REPORT "EXTRACT complete, " & INTEGER'IMAGE(ENCODED_BYTES) & " bytes copied"; + byte_idx <= 0; + bit_idx <= 0; + state <= DEINTERLEAVE; + decoder_active <= '1'; END IF; -- DEINTERLEAVE: Reverse the row-column shuffle WHEN DEINTERLEAVE => IF bit_idx < ENCODED_BITS THEN - deinterleaved_buffer(deinterleave_address(bit_idx)) <= input_buffer(bit_idx); + -- Unpack input_buffer bytes to bits + deinterleaved_buffer(deinterleave_address(bit_idx)) <= + input_buffer(bit_idx / 8)(bit_idx MOD 8); bit_idx <= bit_idx + 1; ELSE REPORT "DEINTERLEAVE complete"; byte_idx <= 0; bit_idx <= 0; - state <= PREP_FEC_DECODE; -- Changed to go to prep state first + state <= PREP_FEC_DECODE; END IF; -- PREP_FEC_DECODE: Separate deinterleaved bits into G1 and G2 streams -WHEN PREP_FEC_DECODE => - -- **FIX: Pack bits in FORWARD order, not reversed!** - -- deinterleaved_buffer[0] = first g1, [1] = first g2, etc. - FOR i IN 0 TO ENCODED_BITS/2 - 1 LOOP - decoder_input_g1(i) <= deinterleaved_buffer(i*2); -- G1 bits: 0, 2, 4, ... - decoder_input_g2(i) <= deinterleaved_buffer(i*2 + 1); -- G2 bits: 1, 3, 5, ... - END LOOP; - decoder_start <= '1'; - state <= FEC_DECODE; - -WHEN FEC_DECODE => - decoder_start <= '0'; -- Clear start pulse - IF decoder_done = '1' THEN - -- Unpack decoded bits in FORWARD order - -- decoder_output_buf[0] = first bit, goes to byte 0 bit 7 - FOR i IN 0 TO PAYLOAD_BYTES-1 LOOP - FOR j IN 0 TO 7 LOOP - fec_decoded_buffer(i)(7-j) <= decoder_output_buf(i*8 + j); - END LOOP; - END LOOP; - byte_idx <= 0; - state <= DERANDOMIZE; - END IF; - - + WHEN PREP_FEC_DECODE => + FOR i IN 0 TO ENCODED_BITS/2 - 1 LOOP + decoder_input_g1(i) <= deinterleaved_buffer(i*2); + decoder_input_g2(i) <= deinterleaved_buffer(i*2 + 1); + END LOOP; + decoder_start <= '1'; + state <= FEC_DECODE; + WHEN FEC_DECODE => + decoder_start <= '0'; + IF decoder_done = '1' THEN + -- Unpack decoded bits in FORWARD order + FOR i IN 0 TO PAYLOAD_BYTES-1 LOOP + FOR j IN 0 TO 7 LOOP + fec_decoded_buffer(i)(7-j) <= decoder_output_buf(i*8 + j); + END LOOP; + END LOOP; + byte_idx <= 0; + state <= DERANDOMIZE; + END IF; -- DERANDOMIZE: XOR with same sequence (inverse operation) WHEN DERANDOMIZE => @@ -333,7 +330,6 @@ WHEN FEC_DECODE => output_buffer(byte_idx) <= fec_decoded_buffer(byte_idx) XOR RANDOMIZER_SEQUENCE(byte_idx); - -- Debug: Report first 5 derandomized bytes IF byte_idx < 5 THEN REPORT "DERANDOMIZE[" & INTEGER'IMAGE(byte_idx) & "] fec=" & INTEGER'IMAGE(to_integer(unsigned(fec_decoded_buffer(byte_idx)))) & @@ -348,34 +344,35 @@ WHEN FEC_DECODE => state <= OUTPUT; END IF; - -- OUTPUT: Send bytes to next stage + -- OUTPUT: Send bytes to next stage (FIXED AXI-Stream handshaking) WHEN OUTPUT => - IF m_axis_tready = '1' OR m_tvalid_reg = '0' THEN - IF out_idx < PAYLOAD_BYTES THEN - m_tdata_reg <= output_buffer(out_idx); - m_tvalid_reg <= '1'; - - -- Debug: Report first 5 output bytes - IF out_idx < 5 THEN - REPORT "DECODER OUTPUT byte " & INTEGER'IMAGE(out_idx) & " = " & - INTEGER'IMAGE(to_integer(unsigned(output_buffer(out_idx)))); - END IF; - - -- Set tlast on final byte - IF out_idx = PAYLOAD_BYTES - 1 THEN - m_tlast_reg <= '1'; - ELSE - m_tlast_reg <= '0'; - END IF; - - out_idx <= out_idx + 1; + IF out_idx < PAYLOAD_BYTES THEN + -- Present current data + m_tdata_reg <= output_buffer(out_idx); + m_tvalid_reg <= '1'; + + IF out_idx < 5 THEN + REPORT "DECODER OUTPUT byte " & INTEGER'IMAGE(out_idx) & " = " & + INTEGER'IMAGE(to_integer(unsigned(output_buffer(out_idx)))); + END IF; + + -- Set tlast on final byte + IF out_idx = PAYLOAD_BYTES - 1 THEN + m_tlast_reg <= '1'; ELSE - -- Frame complete - m_tvalid_reg <= '0'; m_tlast_reg <= '0'; - frame_count <= frame_count + 1; - state <= IDLE; END IF; + + -- Advance on handshake OR on first presentation (tvalid was 0) + IF m_axis_tready = '1' OR m_tvalid_reg = '0' THEN + out_idx <= out_idx + 1; + END IF; + ELSE + -- Frame complete + m_tvalid_reg <= '0'; + m_tlast_reg <= '0'; + frame_count <= frame_count + 1; + state <= IDLE; END IF; END CASE; diff --git a/src/ov_frame_encoder.vhd b/src/ov_frame_encoder.vhd index cfe24fc..0870c0b 100644 --- a/src/ov_frame_encoder.vhd +++ b/src/ov_frame_encoder.vhd @@ -211,14 +211,14 @@ BEGIN -- IDLE: Wait for incoming data WHEN IDLE => encoder_active <= '0'; - s_axis_tready <= '0'; + s_axis_tready <= '0'; -- Keep LOW in IDLE m_tvalid_reg <= '0'; collect_idx <= 0; IF s_axis_tvalid = '1' THEN state <= COLLECT; encoder_active <= '1'; - s_axis_tready <= '1'; + -- tready set HIGH in COLLECT state, not here END IF; -- COLLECT: Gather ALL bytes into circular buffer until tlast diff --git a/src/viterbi_decoder_k7_simple.vhd b/src/viterbi_decoder_k7_simple.vhd index 533e7db..0a1c988 100644 --- a/src/viterbi_decoder_k7_simple.vhd +++ b/src/viterbi_decoder_k7_simple.vhd @@ -1,9 +1,11 @@ ------------------------------------------------------------------------------------------------------ --- FIXED Viterbi Decoder for K=7 Code (NASA Voyager) +-- BRAM-Optimized Viterbi Decoder - SIMPLIFIED TRACEBACK (2 cycles per step) ------------------------------------------------------------------------------------------------------ --- Corrected Issues: --- 1. MSB-first bit indexing to match encoder output format --- 2. Traceback now correctly outputs input bits (LSB of state) not decision bits +-- This version uses 2 clock cycles per traceback step for clarity and correctness: +-- Cycle 1: Fetch decision from BRAM +-- Cycle 2: Use decision, output bit, move to previous state +-- +-- This is slower but eliminates pipeline complexity bugs. ------------------------------------------------------------------------------------------------------ LIBRARY ieee; @@ -12,22 +14,18 @@ USE ieee.numeric_std.ALL; ENTITY viterbi_decoder_k7_simple IS GENERIC ( - PAYLOAD_BITS : NATURAL := 134*8; -- 1072 bits - ENCODED_BITS : NATURAL := 268*8; -- 2144 bits - TRACEBACK_DEPTH : NATURAL := 35 -- 5*K recommended + PAYLOAD_BITS : NATURAL := 134*8; + ENCODED_BITS : NATURAL := 268*8; + TRACEBACK_DEPTH : NATURAL := 35 ); PORT ( clk : IN std_logic; aresetn : IN std_logic; - start : IN std_logic; busy : OUT std_logic; done : OUT std_logic; - - -- Hard decision inputs (g1 and g2 bits) input_bits_g1 : IN std_logic_vector(ENCODED_BITS-1 DOWNTO 0); input_bits_g2 : IN std_logic_vector(ENCODED_BITS-1 DOWNTO 0); - output_bits : OUT std_logic_vector(PAYLOAD_BITS-1 DOWNTO 0) ); END ENTITY viterbi_decoder_k7_simple; @@ -37,43 +35,39 @@ ARCHITECTURE rtl OF viterbi_decoder_k7_simple IS CONSTANT NUM_STATES : INTEGER := 64; CONSTANT METRIC_WIDTH : INTEGER := 12; CONSTANT INF_METRIC : INTEGER := 4095; + CONSTANT NUM_SYMBOLS : INTEGER := ENCODED_BITS/2; - TYPE state_t IS (IDLE, INITIALIZE, ACS_COMPUTE, TRACEBACK, COMPLETE); + TYPE state_t IS (IDLE, INITIALIZE, ACS_COMPUTE, FIND_BEST, + TB_FETCH, TB_USE, COMPLETE); SIGNAL state : state_t := IDLE; - -- Path metrics arrays are now VARIABLES in the process - TYPE metric_array_t IS ARRAY(0 TO NUM_STATES-1) OF INTEGER RANGE 0 TO INF_METRIC; + TYPE metric_array_t IS ARRAY(0 TO NUM_STATES-1) OF unsigned(METRIC_WIDTH-1 DOWNTO 0); + SIGNAL metrics_current : metric_array_t; + SIGNAL metrics_next : metric_array_t; + + CONSTANT DECISION_DEPTH : INTEGER := NUM_SYMBOLS * NUM_STATES; + TYPE decision_mem_t IS ARRAY(0 TO DECISION_DEPTH-1) OF std_logic; + SIGNAL decision_mem : decision_mem_t; - -- Decision memory: stores which previous state was selected (MSB bit) - TYPE decision_array_t IS ARRAY(0 TO ENCODED_BITS/2) OF std_logic_vector(NUM_STATES-1 DOWNTO 0); - SIGNAL decisions : decision_array_t; - - -- Force synthesis to use BRAM ATTRIBUTE ram_style : STRING; - ATTRIBUTE ram_style OF decisions : SIGNAL IS "block"; + ATTRIBUTE ram_style OF decision_mem : SIGNAL IS "block"; - -- Counters - SIGNAL time_step : INTEGER RANGE 0 TO ENCODED_BITS/2 + 1; - SIGNAL tb_step : INTEGER RANGE -1 TO ENCODED_BITS/2; - SIGNAL output_idx : INTEGER RANGE 0 TO PAYLOAD_BITS; + SIGNAL dec_wr_en : std_logic; + SIGNAL dec_wr_addr : INTEGER RANGE 0 TO DECISION_DEPTH-1; + SIGNAL dec_wr_data : std_logic; + SIGNAL dec_rd_addr : INTEGER RANGE 0 TO DECISION_DEPTH-1; + SIGNAL dec_rd_data : std_logic; - -- Current state during traceback + SIGNAL time_step : INTEGER RANGE 0 TO NUM_SYMBOLS; + SIGNAL state_idx : INTEGER RANGE 0 TO NUM_STATES-1; + SIGNAL tb_time : INTEGER RANGE -1 TO NUM_SYMBOLS; SIGNAL tb_state : INTEGER RANGE 0 TO NUM_STATES-1; - -- Output buffer SIGNAL out_buf : std_logic_vector(PAYLOAD_BITS-1 DOWNTO 0); + SIGNAL rx_symbol : std_logic_vector(1 DOWNTO 0); - -------------------------------------------------------------------------------------------- - -- Trellis functions - -------------------------------------------------------------------------------------------- - FUNCTION next_state(curr_state : INTEGER; input_bit : std_logic) RETURN INTEGER IS - VARIABLE shift_reg : std_logic_vector(5 DOWNTO 0); - BEGIN - shift_reg := std_logic_vector(to_unsigned(curr_state, 6)); - RETURN to_integer(unsigned(input_bit & shift_reg(5 DOWNTO 1))); - END FUNCTION; - - FUNCTION compute_output(curr_state : INTEGER; input_bit : std_logic) RETURN std_logic_vector IS + FUNCTION compute_output(curr_state : INTEGER; input_bit : std_logic) + RETURN std_logic_vector IS CONSTANT G1_POLY : std_logic_vector(6 DOWNTO 0) := "1111001"; CONSTANT G2_POLY : std_logic_vector(6 DOWNTO 0) := "1011011"; VARIABLE full_state : std_logic_vector(6 DOWNTO 0); @@ -98,7 +92,7 @@ ARCHITECTURE rtl OF viterbi_decoder_k7_simple IS RETURN g1 & g2; END FUNCTION; - FUNCTION hamming_distance(a : std_logic_vector; b : std_logic_vector) RETURN INTEGER IS + FUNCTION hamming_distance(a, b : std_logic_vector) RETURN INTEGER IS VARIABLE dist : INTEGER := 0; BEGIN FOR i IN a'RANGE LOOP @@ -111,31 +105,39 @@ ARCHITECTURE rtl OF viterbi_decoder_k7_simple IS BEGIN + PROCESS(clk) + BEGIN + IF rising_edge(clk) THEN + IF dec_wr_en = '1' THEN + decision_mem(dec_wr_addr) <= dec_wr_data; + END IF; + END IF; + END PROCESS; + + PROCESS(clk) + BEGIN + IF rising_edge(clk) THEN + dec_rd_data <= decision_mem(dec_rd_addr); + END IF; + END PROCESS; + PROCESS(clk, aresetn) - VARIABLE received_symbol : std_logic_vector(1 DOWNTO 0); - VARIABLE expected_symbol : std_logic_vector(1 DOWNTO 0); - VARIABLE branch_metric : INTEGER; - VARIABLE new_metric : INTEGER; - VARIABLE prev_state_for_0 : INTEGER; - VARIABLE prev_state_for_1 : INTEGER; - VARIABLE metric_via_0 : INTEGER; - VARIABLE metric_via_1 : INTEGER; - VARIABLE min_metric : INTEGER; - VARIABLE best_state : INTEGER; - VARIABLE input_bit_used : INTEGER; - - -- **FIX: Use VARIABLES for metrics, not SIGNALS!** - VARIABLE metrics_old : metric_array_t; - VARIABLE metrics_new : metric_array_t; + VARIABLE prev_state_0, prev_state_1 : INTEGER RANGE 0 TO NUM_STATES-1; + VARIABLE input_bit : std_logic; + VARIABLE expected_0, expected_1 : std_logic_vector(1 DOWNTO 0); + VARIABLE metric_0, metric_1 : unsigned(METRIC_WIDTH-1 DOWNTO 0); + VARIABLE min_metric : unsigned(METRIC_WIDTH-1 DOWNTO 0); + VARIABLE best_state_var : INTEGER RANGE 0 TO NUM_STATES-1; BEGIN IF aresetn = '0' THEN state <= IDLE; busy <= '0'; done <= '0'; - time_step <= 0; + dec_wr_en <= '0'; ELSIF rising_edge(clk) THEN done <= '0'; + dec_wr_en <= '0'; CASE state IS @@ -144,98 +146,118 @@ BEGIN IF start = '1' THEN state <= INITIALIZE; busy <= '1'; - time_step <= 0; + state_idx <= 0; END IF; WHEN INITIALIZE => - -- Start with state 0 having metric 0, all others infinity - FOR i IN 0 TO NUM_STATES-1 LOOP - IF i = 0 THEN - metrics_old(i) := 0; + IF state_idx < NUM_STATES THEN + IF state_idx = 0 THEN + metrics_current(state_idx) <= (OTHERS => '0'); ELSE - metrics_old(i) := INF_METRIC; + metrics_current(state_idx) <= to_unsigned(INF_METRIC, METRIC_WIDTH); END IF; - END LOOP; - state <= ACS_COMPUTE; + state_idx <= state_idx + 1; + ELSE + state <= ACS_COMPUTE; + state_idx <= 0; + time_step <= 0; + END IF; - -WHEN ACS_COMPUTE => - IF time_step < ENCODED_BITS/2 THEN - -- **FIX #1: Read bits in order starting from index 0** - -- Frame decoder packs: input_bits_g1(0)=first_g1, input_bits_g2(0)=first_g2 - -- So we read sequentially from index 0 up - received_symbol := input_bits_g1(time_step) & input_bits_g2(time_step); - - -- For each current state, find best path from two possible previous states - FOR curr_st IN 0 TO NUM_STATES-1 LOOP - -- Two prev states can lead here - prev_state_for_0 := curr_st / 2; -- Previous state with MSB=0 - prev_state_for_1 := (curr_st / 2) + 32; -- Previous state with MSB=1 - - -- The input bit that created curr_st is its LSB - input_bit_used := curr_st MOD 2; - - -- Metric via path with previous MSB=0 - expected_symbol := compute_output(prev_state_for_0, std_logic(to_unsigned(input_bit_used, 1)(0))); - branch_metric := hamming_distance(received_symbol, expected_symbol); - metric_via_0 := metrics_old(prev_state_for_0) + branch_metric; - - -- Metric via path with previous MSB=1 - expected_symbol := compute_output(prev_state_for_1, std_logic(to_unsigned(input_bit_used, 1)(0))); - branch_metric := hamming_distance(received_symbol, expected_symbol); - metric_via_1 := metrics_old(prev_state_for_1) + branch_metric; - - -- Select better path and store decision - IF metric_via_0 <= metric_via_1 THEN - metrics_new(curr_st) := metric_via_0; -- Changed to := - decisions(time_step)(curr_st) <= '0'; -- Came from prev_state_for_0 - ELSE - metrics_new(curr_st) := metric_via_1; -- Changed to := - decisions(time_step)(curr_st) <= '1'; -- Came from prev_state_for_1 - END IF; - END LOOP; - - -- Swap buffers (now happens immediately with variables!) - metrics_old := metrics_new; - time_step <= time_step + 1; - - ELSE - -- ACS complete, prepare for traceback - -- Find best final state (should be state 0 after tail bits) - min_metric := metrics_old(0); - best_state := 0; - FOR i IN 1 TO NUM_STATES-1 LOOP - IF metrics_old(i) < min_metric THEN - min_metric := metrics_old(i); - best_state := i; - END IF; - END LOOP; - - tb_state <= best_state; - tb_step <= time_step - 1; - output_idx <= 0; - state <= TRACEBACK; - END IF; - - -WHEN TRACEBACK => - IF tb_step >= 0 THEN - -- Output the decoded input bit (LSB of current state) - -- tb_step counts DOWN from last to first, giving us the natural index - out_buf(tb_step) <= std_logic(to_unsigned(tb_state MOD 2, 1)(0)); - - -- Move to previous state based on decision - IF decisions(tb_step)(tb_state) = '0' THEN - tb_state <= tb_state / 2; -- Previous state had MSB=0 - ELSE - tb_state <= (tb_state / 2) + 32; -- Previous state had MSB=1 - END IF; - - tb_step <= tb_step - 1; - ELSE - state <= COMPLETE; - END IF; - + WHEN ACS_COMPUTE => + IF time_step < NUM_SYMBOLS THEN + IF state_idx = 0 THEN + rx_symbol <= input_bits_g1(time_step) & input_bits_g2(time_step); + END IF; + + IF state_idx < NUM_STATES THEN + prev_state_0 := state_idx / 2; + prev_state_1 := (state_idx / 2) + 32; + input_bit := std_logic(to_unsigned(state_idx MOD 2, 1)(0)); + + expected_0 := compute_output(prev_state_0, input_bit); + metric_0 := metrics_current(prev_state_0) + + to_unsigned(hamming_distance(rx_symbol, expected_0), METRIC_WIDTH); + + expected_1 := compute_output(prev_state_1, input_bit); + metric_1 := metrics_current(prev_state_1) + + to_unsigned(hamming_distance(rx_symbol, expected_1), METRIC_WIDTH); + + IF metric_0 <= metric_1 THEN + metrics_next(state_idx) <= metric_0; + dec_wr_data <= '0'; + ELSE + metrics_next(state_idx) <= metric_1; + dec_wr_data <= '1'; + END IF; + + dec_wr_addr <= time_step * NUM_STATES + state_idx; + dec_wr_en <= '1'; + state_idx <= state_idx + 1; + ELSE + metrics_current <= metrics_next; + state_idx <= 0; + time_step <= time_step + 1; + END IF; + ELSE + state <= FIND_BEST; + state_idx <= 0; + END IF; + + WHEN FIND_BEST => + IF state_idx = 0 THEN + min_metric := metrics_current(0); + best_state_var := 0; + state_idx <= 1; + ELSIF state_idx < NUM_STATES THEN + IF metrics_current(state_idx) < min_metric THEN + min_metric := metrics_current(state_idx); + best_state_var := state_idx; + END IF; + state_idx <= state_idx + 1; + ELSE + tb_state <= best_state_var; + tb_time <= NUM_SYMBOLS - 1; + dec_rd_addr <= (NUM_SYMBOLS-1) * NUM_STATES + best_state_var; + state <= TB_FETCH; + END IF; + + ------------------------------------------------------------------------------------ + -- SIMPLIFIED 2-CYCLE TRACEBACK + ------------------------------------------------------------------------------------ + WHEN TB_FETCH => + -- Cycle 1: Issue BRAM read for current (tb_time, tb_state) + -- Next cycle, dec_rd_data will be valid + state <= TB_USE; + + WHEN TB_USE => + -- Cycle 2: Use the decision that was fetched + IF tb_time >= 0 THEN + -- Output decoded bit + out_buf(tb_time) <= std_logic(to_unsigned(tb_state MOD 2, 1)(0)); + + -- Move to previous state based on decision + IF dec_rd_data = '0' THEN + tb_state <= tb_state / 2; + ELSE + tb_state <= (tb_state / 2) + 32; + END IF; + + tb_time <= tb_time - 1; + + -- Fetch next decision (if not done) + IF tb_time > 0 THEN + IF dec_rd_data = '0' THEN + dec_rd_addr <= (tb_time-1) * NUM_STATES + (tb_state / 2); + ELSE + dec_rd_addr <= (tb_time-1) * NUM_STATES + ((tb_state / 2) + 32); + END IF; + state <= TB_FETCH; + ELSE + state <= COMPLETE; + END IF; + ELSE + state <= COMPLETE; + END IF; WHEN COMPLETE => done <= '1'; From e4ce3c250d184855f1c429a6fb3c2b46906e8464 Mon Sep 17 00:00:00 2001 From: Abraxas3d Date: Thu, 20 Nov 2025 22:36:48 -0800 Subject: [PATCH 42/60] input matches output but firmware build seg faults. Please send help. --- library/msk_top_ip.tcl | 25 +++++++------------------ src/axis_async_fifo.vhd | 6 +++--- src/msk_top.vhd | 9 ++++++--- src/msk_top_csr.vhd | 2 +- src/ov_frame_encoder.vhd | 6 ++++++ 5 files changed, 23 insertions(+), 25 deletions(-) diff --git a/library/msk_top_ip.tcl b/library/msk_top_ip.tcl index 774faa7..c2a01e8 100644 --- a/library/msk_top_ip.tcl +++ b/library/msk_top_ip.tcl @@ -1,25 +1,22 @@ # ip -# "src/axi_ctrlif.vhd" - source ../hdl/scripts/adi_env.tcl source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl adi_ip_create msk_top +# Register ALL VHDL-2008 files first with read_vhdl -vhdl2008 +# Order matters: dependencies before modules that use them read_vhdl -vhdl2008 "../rdl/src/axi4lite_intf_pkg.vhd" read_vhdl -vhdl2008 "../rdl/src/reg_utils.vhd" read_vhdl "../rdl/outputs/rtl/msk_top_regs_pkg.vhd" read_vhdl -vhdl2008 "../rdl/outputs/rtl/msk_top_regs.vhd" - -# OV frame encoder/decoder require VHDL-2008 for division/modulo operators +read_vhdl -vhdl2008 "../src/conv_encoder_k7.vhd" +read_vhdl -vhdl2008 "../src/viterbi_decoder_k7_simple.vhd" read_vhdl -vhdl2008 "../src/ov_frame_encoder.vhd" read_vhdl -vhdl2008 "../src/ov_frame_decoder.vhd" - -#set_property FILE_TYPE {VHDL 2008} [get_files $ad_hdl_dir/library/msk_top/src/*.vhd] +# Register all non-VHDL-2008 files adi_ip_files msk_top [list \ - "../src/conv_encoder_k7.vhd" \ - "../src/viterbi_decoder_k7_simple.vhd" \ "../msk_demodulator/src/costas_loop.vhd" \ "../pi_controller/src/pi_controller.vhd" \ "../lowpass_ema/src/lowpass_ema.vhd" \ @@ -40,14 +37,9 @@ adi_ip_files msk_top [list \ "../prbs/src/prbs_mon.vhd" \ "../nco/src/sin_cos_lut.vhd" ] -# Set VHDL-2008 for FEC files -set_property FILE_TYPE {VHDL 2008} [get_files "../src/conv_encoder_k7.vhd"] -set_property FILE_TYPE {VHDL 2008} [get_files "../src/viterbi_decoder_k7_simple.vhd"] - -# use this command if we have AXI lite interface for register control +# Configure IP properties adi_ip_properties msk_top - # Remove auto-inferred ADI custom bus interfaces before defining proper AXI-Stream set core [ipx::current_core] foreach intf {rx s_axis tx} { @@ -56,7 +48,7 @@ foreach intf {rx s_axis tx} { } } - +# TX AXIS slave interface (from DMA to MSK) adi_add_bus "s_axis" "slave" \ "xilinx.com:interface:axis_rtl:1.0" \ "xilinx.com:interface:axis:1.0" \ @@ -79,9 +71,6 @@ adi_add_bus "m_axis" "master" \ {"m_axis_tdata" "TDATA"} \ {"m_axis_tlast" "TLAST"}] -# m_axis shares the same clock as the demodulator adi_add_bus_clock "s_axis_aclk" "m_axis" "s_axis_aresetn" ipx::save_core [ipx::current_core] - -ipx::save_core [ipx::current_core] diff --git a/src/axis_async_fifo.vhd b/src/axis_async_fifo.vhd index 215a0cf..c454491 100644 --- a/src/axis_async_fifo.vhd +++ b/src/axis_async_fifo.vhd @@ -68,9 +68,9 @@ ARCHITECTURE rtl OF axis_async_fifo IS SIGNAL ram_data : ram_data_type; SIGNAL ram_last : ram_last_type; - ATTRIBUTE ram_style : STRING; - ATTRIBUTE ram_style OF ram_data : SIGNAL IS "block"; - ATTRIBUTE ram_style OF ram_last : SIGNAL IS "block"; + --ATTRIBUTE ram_style : STRING; + --ATTRIBUTE ram_style OF ram_data : SIGNAL IS "auto"; + --ATTRIBUTE ram_style OF ram_last : SIGNAL IS "auto"; -- Gray code pointers (reset-initialized in respective clock domains) SIGNAL wr_ptr_gray : std_logic_vector(ADDR_WIDTH DOWNTO 0); diff --git a/src/msk_top.vhd b/src/msk_top.vhd index 40c3d25..e11fbd9 100644 --- a/src/msk_top.vhd +++ b/src/msk_top.vhd @@ -97,7 +97,7 @@ ENTITY msk_top IS C_S_AXI_DATA_WIDTH : NATURAL := 32; C_S_AXI_ADDR_WIDTH : NATURAL := 32; SYNC_CNT_W : NATURAL := 24; - FIFO_ADDR_WIDTH : NATURAL := 11 -- 2048 byte FIFO (used in both tx and rx) + FIFO_ADDR_WIDTH : NATURAL := 9 -- 512 byte FIFO (used in both tx and rx) ); PORT ( clk : IN std_logic; @@ -325,6 +325,9 @@ ARCHITECTURE struct OF msk_top IS SIGNAL pd_alpha2 : std_logic_vector(17 DOWNTO 0); SIGNAL pd_power : std_logic_vector(22 DOWNTO 0); + ATTRIBUTE dont_touch : STRING; + ATTRIBUTE dont_touch OF u_async_fifo : LABEL IS "true"; + ATTRIBUTE dont_touch OF u_rx_async_fifo : LABEL IS "true"; BEGIN ------------------------------------------------------------------------------------------------------ @@ -357,7 +360,7 @@ BEGIN u_async_fifo : ENTITY work.axis_async_fifo GENERIC MAP ( DATA_WIDTH => 8, - ADDR_WIDTH => FIFO_ADDR_WIDTH + ADDR_WIDTH => FIFO_ADDR_WIDTH --9 which is 512 bytes ) PORT MAP ( wr_aclk => s_axis_aclk, @@ -619,7 +622,7 @@ BEGIN u_rx_async_fifo : ENTITY work.axis_async_fifo GENERIC MAP ( DATA_WIDTH => 8, - ADDR_WIDTH => FIFO_ADDR_WIDTH -- Reuse generic (11 = 2048 bytes) + ADDR_WIDTH => FIFO_ADDR_WIDTH -- Reuse generic (9 = 512 bytes) ) PORT MAP ( -- Write side (symbol clock domain) diff --git a/src/msk_top_csr.vhd b/src/msk_top_csr.vhd index e91a01e..e5135d5 100644 --- a/src/msk_top_csr.vhd +++ b/src/msk_top_csr.vhd @@ -85,7 +85,7 @@ ENTITY msk_top_csr IS C_S_AXI_DATA_WIDTH : NATURAL := 32; C_S_AXI_ADDR_WIDTH : NATURAL := 32; SYNC_CNT_W : NATURAL := 24; - FIFO_ADDR_WIDTH : NATURAL := 11 + FIFO_ADDR_WIDTH : NATURAL := 9 ); PORT ( clk : IN std_logic; diff --git a/src/ov_frame_encoder.vhd b/src/ov_frame_encoder.vhd index 0870c0b..90d6a3e 100644 --- a/src/ov_frame_encoder.vhd +++ b/src/ov_frame_encoder.vhd @@ -106,6 +106,12 @@ ARCHITECTURE rtl OF ov_frame_encoder IS SIGNAL randomized_buffer : byte_buffer_t; SIGNAL fec_buffer : bit_buffer_t := (OTHERS => '0'); SIGNAL interleaved_buffer : bit_buffer_t := (OTHERS => '0'); + + ATTRIBUTE ram_style : STRING; + --ATTRIBUTE ram_style OF collect_buffer : SIGNAL IS "block"; + --ATTRIBUTE ram_style OF input_buffer : SIGNAL IS "block"; + --ATTRIBUTE ram_style OF randomized_buffer : SIGNAL IS "block"; + ATTRIBUTE ram_style OF interleaved_buffer : SIGNAL IS "register"; -- Index counters SIGNAL collect_idx : NATURAL RANGE 0 TO COLLECT_SIZE; -- Where we're writing in collect_buffer From af474e73c71b941081d275f62cb20b3a3f50d186 Mon Sep 17 00:00:00 2001 From: abraxas3d Date: Sun, 23 Nov 2025 12:46:56 -0800 Subject: [PATCH 43/60] seg fault resolved. needs testing on full test bench on mymelody. --- src/msk_top_csr.vhd | 2 +- src/ov_frame_encoder.vhd | 66 ++++++++++++++++++++++--------- src/viterbi_decoder_k7_simple.vhd | 42 +++++++++++++++++--- 3 files changed, 85 insertions(+), 25 deletions(-) diff --git a/src/msk_top_csr.vhd b/src/msk_top_csr.vhd index e5135d5..c35f891 100644 --- a/src/msk_top_csr.vhd +++ b/src/msk_top_csr.vhd @@ -308,7 +308,7 @@ BEGIN urfo_s: cdc_resync PORT MAP (s_axi_aclk, NOT s_axi_aresetn, rx_frame_buffer_ovf, hwif_in.rx_frame_sync_status.frame_buffer_overflow.we); - hwif_in.MSK_Status.rx_enable.next_q <= '1'; + -- hwif_in.MSK_Status.rx_enable.next_q <= '1'; -- Commented out becuase handled by urxe_s CDC, by Abraxas3d hwif_in.MSK_Status.tx_axis_valid.next_q <= tx_axis_valid; -- Status Request from AXI to MDM diff --git a/src/ov_frame_encoder.vhd b/src/ov_frame_encoder.vhd index 90d6a3e..545c350 100644 --- a/src/ov_frame_encoder.vhd +++ b/src/ov_frame_encoder.vhd @@ -89,12 +89,15 @@ END ENTITY ov_frame_encoder; ARCHITECTURE rtl OF ov_frame_encoder IS -- State machine - TYPE state_t IS (IDLE, COLLECT, EXTRACT, RANDOMIZE, PREP_FEC, FEC_ENCODE, INTERLEAVE, OUTPUT); + TYPE state_t IS (IDLE, COLLECT, EXTRACT, RANDOMIZE, PREP_FEC, FEC_ENCODE, PACK_FEC, INTERLEAVE, OUTPUT); + --TYPE state_t IS (IDLE, COLLECT, EXTRACT, RANDOMIZE, PREP_FEC, FEC_ENCODE, INTERLEAVE, OUTPUT); SIGNAL state : state_t := IDLE; -- Buffer types TYPE byte_buffer_t IS ARRAY(0 TO PAYLOAD_BYTES-1) OF std_logic_vector(BYTE_WIDTH-1 DOWNTO 0); TYPE bit_buffer_t IS ARRAY(0 TO ENCODED_BITS-1) OF std_logic; + TYPE byte_interleave_buffer_t IS ARRAY(0 TO ENCODED_BYTES-1) OF std_logic_vector(7 DOWNTO 0); + -- Circular collection buffer (larger than needed to handle any transients) CONSTANT COLLECT_SIZE : NATURAL := 256; @@ -105,7 +108,12 @@ ARCHITECTURE rtl OF ov_frame_encoder IS SIGNAL input_buffer : byte_buffer_t; SIGNAL randomized_buffer : byte_buffer_t; SIGNAL fec_buffer : bit_buffer_t := (OTHERS => '0'); - SIGNAL interleaved_buffer : bit_buffer_t := (OTHERS => '0'); + --SIGNAL interleaved_buffer : bit_buffer_t := (OTHERS => '0'); + SIGNAL interleaved_buffer : byte_interleave_buffer_t := (OTHERS => (OTHERS => '0')); + + TYPE fec_byte_buffer_t IS ARRAY(0 TO ENCODED_BYTES-1) OF std_logic_vector(7 DOWNTO 0); + SIGNAL fec_buffer_bytes : fec_byte_buffer_t; + ATTRIBUTE ram_style : STRING; --ATTRIBUTE ram_style OF collect_buffer : SIGNAL IS "block"; @@ -156,15 +164,17 @@ ARCHITECTURE rtl OF ov_frame_encoder IS SIGNAL encoder_input_buf : std_logic_vector(1071 DOWNTO 0); -- 134*8 SIGNAL encoder_output_buf : std_logic_vector(2143 DOWNTO 0); -- 268*8 - -- Interleaver address calculation (67 rows x 32 cols) - FUNCTION interleave_address(addr : NATURAL) RETURN NATURAL IS + -- Interleaver address calculation (67 rows x 32 bit cols) + FUNCTION interleave_address_byte(byte_addr : NATURAL) RETURN NATURAL IS CONSTANT ROWS : NATURAL := 67; - CONSTANT COLS : NATURAL := 32; + CONSTANT COLS : NATURAL := 4; --was 32 with bit level. 32/8 = 4 VARIABLE row : NATURAL; VARIABLE col : NATURAL; BEGIN - row := addr / COLS; - col := addr MOD COLS; + --row := addr / COLS; -- bit level + --col := addr MOD COLS; -- bit level + row := byte_addr / COLS; -- byte version + col := byte_addr MOD COLS; -- byte version RETURN col * ROWS + row; END FUNCTION; @@ -315,12 +325,31 @@ WHEN PREP_FEC => state <= INTERLEAVE; END IF; + + + +WHEN PACK_FEC => + IF byte_idx < ENCODED_BYTES THEN + FOR i IN 0 TO 7 LOOP + fec_buffer_bytes(byte_idx)(i) <= fec_buffer(byte_idx * 8 + i); + END LOOP; + byte_idx <= byte_idx + 1; + ELSE + byte_idx <= 0; + state <= INTERLEAVE; + END IF; + + + -- INTERLEAVE: Row-column interleaving WHEN INTERLEAVE => - IF bit_idx < ENCODED_BITS THEN - interleaved_buffer(interleave_address(bit_idx)) <= fec_buffer(bit_idx); - bit_idx <= bit_idx + 1; + IF byte_idx < ENCODED_BYTES THEN + --IF bit_idx < ENCODED_BITS THEN + --interleaved_buffer(interleave_address(bit_idx)) <= fec_buffer(bit_idx); + interleaved_buffer(interleave_address_byte(byte_idx)) <= fec_buffer_bytes(byte_idx); + --bit_idx <= bit_idx + 1; + byte_idx <= byte_idx + 1; ELSE out_idx <= 0; state <= OUTPUT; @@ -330,14 +359,15 @@ WHEN PREP_FEC => -- OUTPUT: Send 268 bytes via AXI-Stream WHEN OUTPUT => IF out_idx < ENCODED_BYTES THEN - m_tdata_reg(0) <= interleaved_buffer(out_idx * 8 + 0); - m_tdata_reg(1) <= interleaved_buffer(out_idx * 8 + 1); - m_tdata_reg(2) <= interleaved_buffer(out_idx * 8 + 2); - m_tdata_reg(3) <= interleaved_buffer(out_idx * 8 + 3); - m_tdata_reg(4) <= interleaved_buffer(out_idx * 8 + 4); - m_tdata_reg(5) <= interleaved_buffer(out_idx * 8 + 5); - m_tdata_reg(6) <= interleaved_buffer(out_idx * 8 + 6); - m_tdata_reg(7) <= interleaved_buffer(out_idx * 8 + 7); + m_tdata_reg <= interleaved_buffer(out_idx); -- Direct byte assignment! + --m_tdata_reg(0) <= interleaved_buffer(out_idx * 8 + 0); + --m_tdata_reg(1) <= interleaved_buffer(out_idx * 8 + 1); + --m_tdata_reg(2) <= interleaved_buffer(out_idx * 8 + 2); + --m_tdata_reg(3) <= interleaved_buffer(out_idx * 8 + 3); + --m_tdata_reg(4) <= interleaved_buffer(out_idx * 8 + 4); + --m_tdata_reg(5) <= interleaved_buffer(out_idx * 8 + 5); + --m_tdata_reg(6) <= interleaved_buffer(out_idx * 8 + 6); + --m_tdata_reg(7) <= interleaved_buffer(out_idx * 8 + 7); m_tvalid_reg <= '1'; m_tlast_reg <= '1' WHEN out_idx = (ENCODED_BYTES - 1) ELSE '0'; diff --git a/src/viterbi_decoder_k7_simple.vhd b/src/viterbi_decoder_k7_simple.vhd index 0a1c988..9a52bbb 100644 --- a/src/viterbi_decoder_k7_simple.vhd +++ b/src/viterbi_decoder_k7_simple.vhd @@ -32,26 +32,54 @@ END ENTITY viterbi_decoder_k7_simple; ARCHITECTURE rtl OF viterbi_decoder_k7_simple IS + CONSTANT NUM_STATES : INTEGER := 64; CONSTANT METRIC_WIDTH : INTEGER := 12; CONSTANT INF_METRIC : INTEGER := 4095; CONSTANT NUM_SYMBOLS : INTEGER := ENCODED_BITS/2; - + TYPE state_t IS (IDLE, INITIALIZE, ACS_COMPUTE, FIND_BEST, - TB_FETCH, TB_USE, COMPLETE); + TB_FETCH, TB_USE, COMPLETE); SIGNAL state : state_t := IDLE; TYPE metric_array_t IS ARRAY(0 TO NUM_STATES-1) OF unsigned(METRIC_WIDTH-1 DOWNTO 0); SIGNAL metrics_current : metric_array_t; SIGNAL metrics_next : metric_array_t; + --CONSTANT DECISION_DEPTH : INTEGER := NUM_SYMBOLS * NUM_STATES; + --TYPE decision_mem_t IS ARRAY(0 TO DECISION_DEPTH-1) OF std_logic; + --SIGNAL decision_mem : decision_mem_t; + + -- ATTRIBUTE ram_style : STRING; + -- ATTRIBUTE ram_style OF decision_mem : SIGNAL IS "ultra"; + -- was block, worked with distributed but was too large of a design, tried ultra + -- still too big. removed entirely tried, was still too big. Then... + + --ATTRIBUTE ram_style : STRING; + --ATTRIBUTE ram_style OF decision_mem : SIGNAL IS "block"; + --ATTRIBUTE ram_extract : STRING; + --ATTRIBUTE ram_extract OF decision_mem : SIGNAL IS "yes"; + --ATTRIBUTE keep : STRING; + --ATTRIBUTE keep OF decision_mem : SIGNAL IS "true"; + -- crashed in a different place + + --CONSTANT DECISION_DEPTH : INTEGER := NUM_SYMBOLS * NUM_STATES; + --CONSTANT CHUNK_SIZE : INTEGER := 4096; + --CONSTANT NUM_CHUNKS : INTEGER := (DECISION_DEPTH + CHUNK_SIZE - 1) / CHUNK_SIZE; + + --TYPE decision_chunk_t IS ARRAY(0 TO CHUNK_SIZE-1) OF std_logic; + --TYPE decision_mem_array_t IS ARRAY(0 TO NUM_CHUNKS-1) OF decision_chunk_t; + --SIGNAL decision_mem : decision_mem_array_t; + + --ATTRIBUTE ram_style : STRING; + --ATTRIBUTE ram_style OF decision_mem : SIGNAL IS "block"; + CONSTANT DECISION_DEPTH : INTEGER := NUM_SYMBOLS * NUM_STATES; TYPE decision_mem_t IS ARRAY(0 TO DECISION_DEPTH-1) OF std_logic; SIGNAL decision_mem : decision_mem_t; - - ATTRIBUTE ram_style : STRING; - ATTRIBUTE ram_style OF decision_mem : SIGNAL IS "block"; - + + + SIGNAL dec_wr_en : std_logic; SIGNAL dec_wr_addr : INTEGER RANGE 0 TO DECISION_DEPTH-1; SIGNAL dec_wr_data : std_logic; @@ -110,6 +138,7 @@ BEGIN IF rising_edge(clk) THEN IF dec_wr_en = '1' THEN decision_mem(dec_wr_addr) <= dec_wr_data; + --decision_mem(dec_wr_addr / CHUNK_SIZE)(dec_wr_addr MOD CHUNK_SIZE) <= dec_wr_data; END IF; END IF; END PROCESS; @@ -118,6 +147,7 @@ BEGIN BEGIN IF rising_edge(clk) THEN dec_rd_data <= decision_mem(dec_rd_addr); + --dec_rd_data <= decision_mem(dec_rd_addr / CHUNK_SIZE)(dec_rd_addr MOD CHUNK_SIZE); END IF; END PROCESS; From dbc5a1ff82ac3d2f2781f622be3c1345e5b2f4e2 Mon Sep 17 00:00:00 2001 From: Abraxas3d Date: Mon, 24 Nov 2025 17:31:36 -0800 Subject: [PATCH 44/60] end to end data corruption resolved. input equals output. --- src/axis_async_fifo.vhd | 17 ++- src/conv_encoder_k7.vhd | 50 ++++----- src/ov_frame_decoder.vhd | 7 +- src/ov_frame_encoder.vhd | 227 +++++++++++++++------------------------ 4 files changed, 131 insertions(+), 170 deletions(-) diff --git a/src/axis_async_fifo.vhd b/src/axis_async_fifo.vhd index c454491..311a24d 100644 --- a/src/axis_async_fifo.vhd +++ b/src/axis_async_fifo.vhd @@ -2,7 +2,7 @@ -- AXIS-Compliant Asynchronous FIFO ------------------------------------------------------------------------------------------------------ -- FIX v3: Proper three-state handling --- State A: Becoming valid (empty→non-empty): Present first byte, assert tvalid +-- State A: Becoming valid (empty?non-empty): Present first byte, assert tvalid -- State B: Handshake completes (tvalid='1', tready='1'): Advance pointer, present next byte -- State C: Valid but not consumed (tvalid='1', tready='0'): HOLD STABLE ------------------------------------------------------------------------------------------------------ @@ -61,6 +61,14 @@ ARCHITECTURE rtl OF axis_async_fifo IS CONSTANT DEPTH : NATURAL := 2**ADDR_WIDTH; + -- Frame-aware programmable full threshold + -- Alert when only fractional frame space remains, allowing N complete frames + -- to buffer without backpressure while maintaining elasticity for system response + CONSTANT FRAME_SIZE : NATURAL := 134; -- OV frame payload size (bytes) + CONSTANT ALERT_THRESHOLD : NATURAL := DEPTH MOD FRAME_SIZE; -- Remainder space + -- Example: 512-byte FIFO holds 3 full frames (402 bytes) + 110 bytes remainder + -- Alerts when ?110 bytes free, giving elasticity while protecting overflow + -- Separate arrays for Block RAM inference TYPE ram_data_type IS ARRAY (0 TO DEPTH-1) OF std_logic_vector(DATA_WIDTH-1 DOWNTO 0); TYPE ram_last_type IS ARRAY (0 TO DEPTH-1) OF std_logic; @@ -174,8 +182,9 @@ BEGIN full_int <= '0'; END IF; - -- Programmable full - IF DEPTH - (unsigned(wr_ptr_bin) - unsigned(rd_ptr_bin_sync)) <= 512 THEN + -- Programmable full - frame-aware threshold + -- Alerts when free space drops below one fractional frame + IF DEPTH - (unsigned(wr_ptr_bin) - unsigned(rd_ptr_bin_sync)) <= ALERT_THRESHOLD THEN prog_full_int <= '1'; ELSE prog_full_int <= '0'; @@ -194,7 +203,7 @@ BEGIN ------------------------------------------------------------------------------ -- Read Clock Domain - CORRECTED THREE-STATE LOGIC ------------------------------------------------------------------------------ - -- State A: Becoming valid (tvalid_int='0' → '1'): Present first byte + -- State A: Becoming valid (tvalid_int='0' ? '1'): Present first byte -- State B: Handshake completes (tvalid='1', tready='1'): Advance, present next -- State C: Valid but stalled (tvalid='1', tready='0'): HOLD STABLE ------------------------------------------------------------------------------ diff --git a/src/conv_encoder_k7.vhd b/src/conv_encoder_k7.vhd index 6f3fbe4..1cc624a 100644 --- a/src/conv_encoder_k7.vhd +++ b/src/conv_encoder_k7.vhd @@ -30,7 +30,8 @@ END ENTITY conv_encoder_k7; ARCHITECTURE rtl OF conv_encoder_k7 IS - TYPE state_t IS (IDLE, ENCODE_DATA, FLUSH_TRELLIS, COMPLETE); + -- TYPE state_t IS (IDLE, ENCODE_DATA, FLUSH_TRELLIS, COMPLETE); + TYPE state_t IS (IDLE, ENCODE_DATA, COMPLETE); SIGNAL state : state_t := IDLE; SIGNAL input_bit_count : NATURAL RANGE 0 TO PAYLOAD_BYTES*8; @@ -106,7 +107,7 @@ BEGIN WHEN ENCODE_DATA => -- Process 1,070 bits (stop 2 bits early for tail) - IF input_bit_count < PAYLOAD_BYTES*8 - 2 THEN + IF input_bit_count < PAYLOAD_BYTES*8 THEN -- Read input bit (MSB first) current_bit := input_buffer(PAYLOAD_BYTES*8 - 1 - input_bit_count); @@ -123,30 +124,31 @@ BEGIN input_bit_count <= input_bit_count + 1; output_bit_count <= output_bit_count + 2; ELSE - state <= FLUSH_TRELLIS; - input_bit_count <= 0; - END IF; - - WHEN FLUSH_TRELLIS => - -- Add 2 tail bits (produces 4 encoded bits) - IF input_bit_count < 2 THEN - current_bit := '0'; - - -- Compute outputs - outputs := compute_outputs(current_bit, shift_reg); - - -- Store outputs - out_buf(ENCODED_BYTES*8 - 1 - output_bit_count) <= outputs(1); - out_buf(ENCODED_BYTES*8 - 2 - output_bit_count) <= outputs(0); - - -- Update shift register - shift_reg := shift_reg(4 DOWNTO 0) & '0'; - - input_bit_count <= input_bit_count + 1; - output_bit_count <= output_bit_count + 2; - ELSE + -- state <= FLUSH_TRELLIS; + -- input_bit_count <= 0; state <= COMPLETE; END IF; + +-- WHEN FLUSH_TRELLIS => +-- -- Add 2 tail bits (produces 4 encoded bits) +-- IF input_bit_count < 2 THEN +-- current_bit := '0'; +-- +-- -- Compute outputs +-- outputs := compute_outputs(current_bit, shift_reg); +-- +-- -- Store outputs +-- out_buf(ENCODED_BYTES*8 - 1 - output_bit_count) <= outputs(1); +-- out_buf(ENCODED_BYTES*8 - 2 - output_bit_count) <= outputs(0); +-- +-- -- Update shift register +-- shift_reg := shift_reg(4 DOWNTO 0) & '0'; +-- +-- input_bit_count <= input_bit_count + 1; +-- output_bit_count <= output_bit_count + 2; +-- ELSE +-- state <= COMPLETE; +-- END IF; WHEN COMPLETE => done <= '1'; diff --git a/src/ov_frame_decoder.vhd b/src/ov_frame_decoder.vhd index 9d60f86..0cf98fe 100644 --- a/src/ov_frame_decoder.vhd +++ b/src/ov_frame_decoder.vhd @@ -314,10 +314,13 @@ BEGIN WHEN FEC_DECODE => decoder_start <= '0'; IF decoder_done = '1' THEN - -- Unpack decoded bits in FORWARD order + -- Unpack decoded bits in REVERSE order to match encoder's bit reversal + -- Viterbi traceback produces bits in reverse order, compensating for + -- conv encoder's MSB-first processing, but we need to reverse again + -- to match how encoder packed the input FOR i IN 0 TO PAYLOAD_BYTES-1 LOOP FOR j IN 0 TO 7 LOOP - fec_decoded_buffer(i)(7-j) <= decoder_output_buf(i*8 + j); + fec_decoded_buffer(i)(j) <= decoder_output_buf(PAYLOAD_BYTES*8 - 1 - i*8 - j); END LOOP; END LOOP; byte_idx <= 0; diff --git a/src/ov_frame_encoder.vhd b/src/ov_frame_encoder.vhd index 545c350..5d192df 100644 --- a/src/ov_frame_encoder.vhd +++ b/src/ov_frame_encoder.vhd @@ -41,14 +41,13 @@ -- This module implements the TX path processing for OVP frames: -- 1. Collects 134 bytes of payload from AXI-Stream input -- 2. Applies randomization (XOR with fixed sequence) --- 3. Applies FEC (rate 1/2 convolutional - currently simple bit duplication) --- 4. Applies interleaving (67x32 row-column interleaver) +-- 3. Applies FEC (rate 1/2 convolutional encoding via conv_encoder_k7) +-- 4. Applies interleaving (67x32 row-column BIT interleaver) -- 5. Outputs 268 bytes (2144 bits) via AXI-Stream -- --- BUGFIX (2025-11-18): Completely redesigned collection strategy --- - Collect ALL bytes into circular buffer --- - When tlast arrives, count back 134 bytes --- - This handles any FIFO latency/alignment naturally +-- FIX (2025-11-24): Restored bit-level 67x32 interleaving +-- Byte-level interleaving broke protocol compatibility +-- Now processes 8 bits/clock for throughput (not 1 bit/clock) -- ------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------ @@ -88,17 +87,14 @@ END ENTITY ov_frame_encoder; ARCHITECTURE rtl OF ov_frame_encoder IS - -- State machine - TYPE state_t IS (IDLE, COLLECT, EXTRACT, RANDOMIZE, PREP_FEC, FEC_ENCODE, PACK_FEC, INTERLEAVE, OUTPUT); - --TYPE state_t IS (IDLE, COLLECT, EXTRACT, RANDOMIZE, PREP_FEC, FEC_ENCODE, INTERLEAVE, OUTPUT); + -- State machine (no PACK_FEC needed with bit-level interleaving) + TYPE state_t IS (IDLE, COLLECT, EXTRACT, RANDOMIZE, PREP_FEC, FEC_ENCODE, INTERLEAVE, OUTPUT); SIGNAL state : state_t := IDLE; -- Buffer types TYPE byte_buffer_t IS ARRAY(0 TO PAYLOAD_BYTES-1) OF std_logic_vector(BYTE_WIDTH-1 DOWNTO 0); TYPE bit_buffer_t IS ARRAY(0 TO ENCODED_BITS-1) OF std_logic; - TYPE byte_interleave_buffer_t IS ARRAY(0 TO ENCODED_BYTES-1) OF std_logic_vector(7 DOWNTO 0); - -- Circular collection buffer (larger than needed to handle any transients) CONSTANT COLLECT_SIZE : NATURAL := 256; TYPE collect_buffer_t IS ARRAY(0 TO COLLECT_SIZE-1) OF std_logic_vector(BYTE_WIDTH-1 DOWNTO 0); @@ -108,21 +104,13 @@ ARCHITECTURE rtl OF ov_frame_encoder IS SIGNAL input_buffer : byte_buffer_t; SIGNAL randomized_buffer : byte_buffer_t; SIGNAL fec_buffer : bit_buffer_t := (OTHERS => '0'); - --SIGNAL interleaved_buffer : bit_buffer_t := (OTHERS => '0'); - SIGNAL interleaved_buffer : byte_interleave_buffer_t := (OTHERS => (OTHERS => '0')); - - TYPE fec_byte_buffer_t IS ARRAY(0 TO ENCODED_BYTES-1) OF std_logic_vector(7 DOWNTO 0); - SIGNAL fec_buffer_bytes : fec_byte_buffer_t; - + SIGNAL interleaved_buffer : bit_buffer_t := (OTHERS => '0'); -- BIT-level buffer! ATTRIBUTE ram_style : STRING; - --ATTRIBUTE ram_style OF collect_buffer : SIGNAL IS "block"; - --ATTRIBUTE ram_style OF input_buffer : SIGNAL IS "block"; - --ATTRIBUTE ram_style OF randomized_buffer : SIGNAL IS "block"; - ATTRIBUTE ram_style OF interleaved_buffer : SIGNAL IS "register"; + ATTRIBUTE ram_style OF interleaved_buffer : SIGNAL IS "distributed"; -- Index counters - SIGNAL collect_idx : NATURAL RANGE 0 TO COLLECT_SIZE; -- Where we're writing in collect_buffer + SIGNAL collect_idx : NATURAL RANGE 0 TO COLLECT_SIZE; SIGNAL byte_idx : NATURAL RANGE 0 TO PAYLOAD_BYTES; SIGNAL bit_idx : NATURAL RANGE 0 TO ENCODED_BITS; SIGNAL out_idx : NATURAL RANGE 0 TO ENCODED_BYTES; @@ -137,6 +125,7 @@ ARCHITECTURE rtl OF ov_frame_encoder IS -- OVP Randomizer sequence (from OVP spec) TYPE randomizer_t IS ARRAY(0 TO PAYLOAD_BYTES-1) OF std_logic_vector(7 DOWNTO 0); + -- OVP Randomizer sequence (from protocol spec - must match decoder!) CONSTANT RANDOMIZER_SEQUENCE : randomizer_t := ( x"A3", x"81", x"5C", x"C4", x"C9", x"08", x"0E", x"53", x"CC", x"A1", x"FB", x"29", x"9E", x"4F", x"16", x"E0", @@ -157,30 +146,29 @@ ARCHITECTURE rtl OF ov_frame_encoder IS x"9D", x"8E", x"E8", x"34", x"C9", x"59" ); - -- Viterbi encoder signals + -- Convolutional encoder signals (matches conv_encoder_k7 interface) SIGNAL encoder_start : std_logic := '0'; SIGNAL encoder_busy : std_logic; SIGNAL encoder_done : std_logic; SIGNAL encoder_input_buf : std_logic_vector(1071 DOWNTO 0); -- 134*8 SIGNAL encoder_output_buf : std_logic_vector(2143 DOWNTO 0); -- 268*8 - -- Interleaver address calculation (67 rows x 32 bit cols) - FUNCTION interleave_address_byte(byte_addr : NATURAL) RETURN NATURAL IS + -- BIT-LEVEL interleaver address calculation (67 rows x 32 cols) + -- This is the CORRECT algorithm - scatters bits across byte boundaries + FUNCTION interleave_address(addr : NATURAL) RETURN NATURAL IS CONSTANT ROWS : NATURAL := 67; - CONSTANT COLS : NATURAL := 4; --was 32 with bit level. 32/8 = 4 + CONSTANT COLS : NATURAL := 32; VARIABLE row : NATURAL; VARIABLE col : NATURAL; BEGIN - --row := addr / COLS; -- bit level - --col := addr MOD COLS; -- bit level - row := byte_addr / COLS; -- byte version - col := byte_addr MOD COLS; -- byte version + row := addr / COLS; + col := addr MOD COLS; RETURN col * ROWS + row; END FUNCTION; BEGIN - -- Convolutional Encoder Instantiation + -- Convolutional Encoder Instantiation (using YOUR actual component) U_ENCODER : ENTITY work.conv_encoder_k7 GENERIC MAP ( PAYLOAD_BYTES => PAYLOAD_BYTES, @@ -202,94 +190,63 @@ BEGIN m_axis_tlast <= m_tlast_reg; frames_encoded <= std_logic_vector(frame_count); + encoder_active <= '1' WHEN state /= IDLE ELSE '0'; + + -- Ready to accept data when IDLE or COLLECT + s_axis_tready <= '1' WHEN (state = IDLE OR state = COLLECT) AND aresetn = '1' ELSE '0'; -- Main FSM - encoder_fsm: PROCESS(clk, aresetn) - VARIABLE extract_start : NATURAL; - VARIABLE extract_end : NATURAL; + encoder_fsm: PROCESS(clk) BEGIN - IF aresetn = '0' THEN - state <= IDLE; - collect_idx <= 0; - byte_idx <= 0; - bit_idx <= 0; - out_idx <= 0; - s_axis_tready <= '0'; - m_tvalid_reg <= '0'; - m_tlast_reg <= '0'; - frame_count <= (OTHERS => '0'); - encoder_start <= '0'; -- Initialize FEC encoder control; - - ELSIF rising_edge(clk) THEN - IF aresetn = '1' THEN + IF rising_edge(clk) THEN + IF aresetn = '0' THEN + state <= IDLE; + collect_idx <= 0; + byte_idx <= 0; + bit_idx <= 0; + out_idx <= 0; + m_tvalid_reg <= '0'; + m_tlast_reg <= '0'; + encoder_start <= '0'; + frame_count <= (OTHERS => '0'); + ELSE CASE state IS - - -- IDLE: Wait for incoming data + -- IDLE: Wait for start of frame WHEN IDLE => - encoder_active <= '0'; - s_axis_tready <= '0'; -- Keep LOW in IDLE m_tvalid_reg <= '0'; - collect_idx <= 0; + m_tlast_reg <= '0'; + encoder_start <= '0'; IF s_axis_tvalid = '1' THEN + collect_buffer(0) <= s_axis_tdata; + collect_idx <= 1; state <= COLLECT; - encoder_active <= '1'; - -- tready set HIGH in COLLECT state, not here END IF; - -- COLLECT: Gather ALL bytes into circular buffer until tlast - -- Don't worry about alignment - just collect everything + -- COLLECT: Gather bytes until tlast WHEN COLLECT => - s_axis_tready <= '1'; - IF s_axis_tvalid = '1' THEN - -- Store byte in circular buffer collect_buffer(collect_idx MOD COLLECT_SIZE) <= s_axis_tdata; - - REPORT "COLLECT: collect_idx=" & INTEGER'IMAGE(collect_idx) & - " data=0x" & INTEGER'IMAGE(to_integer(unsigned(s_axis_tdata))) & - " tlast=" & STD_LOGIC'IMAGE(s_axis_tlast)(2); + collect_idx <= collect_idx + 1; IF s_axis_tlast = '1' THEN - -- Frame boundary! Now extract the last 134 bytes - REPORT "COLLECT: tlast at collect_idx=" & INTEGER'IMAGE(collect_idx); - s_axis_tready <= '0'; - state <= EXTRACT; byte_idx <= 0; - ELSE - collect_idx <= collect_idx + 1; + state <= EXTRACT; END IF; END IF; - -- EXTRACT: Copy the last 134 bytes from collect_buffer to input_buffer - -- The frame ends at collect_idx, so we want bytes [collect_idx-133 : collect_idx] + -- EXTRACT: Pull last 134 bytes from circular buffer WHEN EXTRACT => IF byte_idx < PAYLOAD_BYTES THEN - -- Calculate which byte in collect_buffer to read - -- If collect_idx = 133, we want bytes [0:133] - -- If collect_idx = 150, we want bytes [17:150] - extract_start := (collect_idx + 1) - PAYLOAD_BYTES; - extract_end := collect_idx; - - -- Copy byte from circular buffer - input_buffer(byte_idx) <= collect_buffer((extract_start + byte_idx) MOD COLLECT_SIZE); - - IF byte_idx < 5 THEN - REPORT "EXTRACT[" & INTEGER'IMAGE(byte_idx) & - "] from collect_buffer[" & - INTEGER'IMAGE((extract_start + byte_idx) MOD COLLECT_SIZE) & - "] = 0x" & - INTEGER'IMAGE(to_integer(unsigned(collect_buffer((extract_start + byte_idx) MOD COLLECT_SIZE)))); - END IF; - + input_buffer(byte_idx) <= + collect_buffer((collect_idx - PAYLOAD_BYTES + byte_idx) MOD COLLECT_SIZE); byte_idx <= byte_idx + 1; ELSE - REPORT "EXTRACT complete, " & INTEGER'IMAGE(PAYLOAD_BYTES) & " bytes copied"; byte_idx <= 0; state <= RANDOMIZE; END IF; - -- RANDOMIZE: XOR with sequence + -- RANDOMIZE: XOR with randomizer sequence WHEN RANDOMIZE => IF byte_idx < PAYLOAD_BYTES THEN randomized_buffer(byte_idx) <= @@ -297,59 +254,45 @@ BEGIN byte_idx <= byte_idx + 1; ELSE byte_idx <= 0; - bit_idx <= 0; - state <= PREP_FEC; -- Changed from FEC_ENCODE + state <= PREP_FEC; END IF; -WHEN PREP_FEC => - -- Pack randomized_buffer MSB-first to match encoder's MSB-first reading - FOR i IN 0 TO PAYLOAD_BYTES-1 LOOP - FOR j IN 0 TO 7 LOOP - -- Put byte 0 at top of buffer, MSB of each byte first - encoder_input_buf(PAYLOAD_BYTES*8 - 1 - (i*8 + j)) <= randomized_buffer(i)(7-j); - END LOOP; - END LOOP; - encoder_start <= '1'; - state <= FEC_ENCODE; + -- PREP_FEC: Pack bytes into encoder input vector + WHEN PREP_FEC => + FOR i IN 0 TO PAYLOAD_BYTES-1 LOOP + FOR j IN 0 TO 7 LOOP + encoder_input_buf(i*8 + j) <= randomized_buffer(i)(j); + END LOOP; + END LOOP; + encoder_start <= '1'; + state <= FEC_ENCODE; - -- FEC_ENCODE: Wait for convolution encoder to complete + -- FEC_ENCODE: Wait for convolutional encoder to complete WHEN FEC_ENCODE => - encoder_start <= '0'; -- Clear start pulse + encoder_start <= '0'; IF encoder_done = '1' THEN -- Unpack encoded bits into fec_buffer FOR i IN 0 TO ENCODED_BITS-1 LOOP fec_buffer(i) <= encoder_output_buf(ENCODED_BITS - 1 - i); -- MSB-first - --fec_buffer(i) <= encoder_output_buf(i); END LOOP; bit_idx <= 0; state <= INTERLEAVE; END IF; - - - - -WHEN PACK_FEC => - IF byte_idx < ENCODED_BYTES THEN - FOR i IN 0 TO 7 LOOP - fec_buffer_bytes(byte_idx)(i) <= fec_buffer(byte_idx * 8 + i); - END LOOP; - byte_idx <= byte_idx + 1; - ELSE - byte_idx <= 0; - state <= INTERLEAVE; - END IF; - - - - -- INTERLEAVE: Row-column interleaving + -- INTERLEAVE: Bit-level 67x32 interleaving + -- Process 8 bits per clock for throughput (268 clocks total) WHEN INTERLEAVE => - IF byte_idx < ENCODED_BYTES THEN - --IF bit_idx < ENCODED_BITS THEN - --interleaved_buffer(interleave_address(bit_idx)) <= fec_buffer(bit_idx); - interleaved_buffer(interleave_address_byte(byte_idx)) <= fec_buffer_bytes(byte_idx); - --bit_idx <= bit_idx + 1; - byte_idx <= byte_idx + 1; + IF bit_idx < ENCODED_BITS THEN + -- Write 8 bits in parallel to their interleaved positions + interleaved_buffer(interleave_address(bit_idx + 0)) <= fec_buffer(bit_idx + 0); + interleaved_buffer(interleave_address(bit_idx + 1)) <= fec_buffer(bit_idx + 1); + interleaved_buffer(interleave_address(bit_idx + 2)) <= fec_buffer(bit_idx + 2); + interleaved_buffer(interleave_address(bit_idx + 3)) <= fec_buffer(bit_idx + 3); + interleaved_buffer(interleave_address(bit_idx + 4)) <= fec_buffer(bit_idx + 4); + interleaved_buffer(interleave_address(bit_idx + 5)) <= fec_buffer(bit_idx + 5); + interleaved_buffer(interleave_address(bit_idx + 6)) <= fec_buffer(bit_idx + 6); + interleaved_buffer(interleave_address(bit_idx + 7)) <= fec_buffer(bit_idx + 7); + bit_idx <= bit_idx + 8; ELSE out_idx <= 0; state <= OUTPUT; @@ -357,20 +300,24 @@ WHEN PACK_FEC => END IF; -- OUTPUT: Send 268 bytes via AXI-Stream + -- Pack 8 bits from interleaved buffer into each output byte WHEN OUTPUT => IF out_idx < ENCODED_BYTES THEN - m_tdata_reg <= interleaved_buffer(out_idx); -- Direct byte assignment! - --m_tdata_reg(0) <= interleaved_buffer(out_idx * 8 + 0); - --m_tdata_reg(1) <= interleaved_buffer(out_idx * 8 + 1); - --m_tdata_reg(2) <= interleaved_buffer(out_idx * 8 + 2); - --m_tdata_reg(3) <= interleaved_buffer(out_idx * 8 + 3); - --m_tdata_reg(4) <= interleaved_buffer(out_idx * 8 + 4); - --m_tdata_reg(5) <= interleaved_buffer(out_idx * 8 + 5); - --m_tdata_reg(6) <= interleaved_buffer(out_idx * 8 + 6); - --m_tdata_reg(7) <= interleaved_buffer(out_idx * 8 + 7); + m_tdata_reg(0) <= interleaved_buffer(out_idx * 8 + 0); + m_tdata_reg(1) <= interleaved_buffer(out_idx * 8 + 1); + m_tdata_reg(2) <= interleaved_buffer(out_idx * 8 + 2); + m_tdata_reg(3) <= interleaved_buffer(out_idx * 8 + 3); + m_tdata_reg(4) <= interleaved_buffer(out_idx * 8 + 4); + m_tdata_reg(5) <= interleaved_buffer(out_idx * 8 + 5); + m_tdata_reg(6) <= interleaved_buffer(out_idx * 8 + 6); + m_tdata_reg(7) <= interleaved_buffer(out_idx * 8 + 7); m_tvalid_reg <= '1'; - m_tlast_reg <= '1' WHEN out_idx = (ENCODED_BYTES - 1) ELSE '0'; + IF out_idx = (ENCODED_BYTES - 1) THEN + m_tlast_reg <= '1'; + ELSE + m_tlast_reg <= '0'; + END IF; IF m_axis_tready = '1' THEN IF out_idx = (ENCODED_BYTES - 1) THEN From 184aa7dc902f636975fcf089e6e74a41f1223474 Mon Sep 17 00:00:00 2001 From: Abraxas3d Date: Mon, 24 Nov 2025 18:49:17 -0800 Subject: [PATCH 45/60] works in simulation, comes under LUT limit for PLUTO, but doesn't route. Right before generate byte vs bit interleaver option installed. --- src/ov_frame_encoder.vhd | 171 +++++++++++++++++++++++++++++++++------ 1 file changed, 146 insertions(+), 25 deletions(-) diff --git a/src/ov_frame_encoder.vhd b/src/ov_frame_encoder.vhd index 5d192df..b08d8ea 100644 --- a/src/ov_frame_encoder.vhd +++ b/src/ov_frame_encoder.vhd @@ -107,7 +107,7 @@ ARCHITECTURE rtl OF ov_frame_encoder IS SIGNAL interleaved_buffer : bit_buffer_t := (OTHERS => '0'); -- BIT-level buffer! ATTRIBUTE ram_style : STRING; - ATTRIBUTE ram_style OF interleaved_buffer : SIGNAL IS "distributed"; + ATTRIBUTE ram_style OF interleaved_buffer : SIGNAL IS "block"; -- Index counters SIGNAL collect_idx : NATURAL RANGE 0 TO COLLECT_SIZE; @@ -153,18 +153,146 @@ ARCHITECTURE rtl OF ov_frame_encoder IS SIGNAL encoder_input_buf : std_logic_vector(1071 DOWNTO 0); -- 134*8 SIGNAL encoder_output_buf : std_logic_vector(2143 DOWNTO 0); -- 268*8 - -- BIT-LEVEL interleaver address calculation (67 rows x 32 cols) - -- This is the CORRECT algorithm - scatters bits across byte boundaries - FUNCTION interleave_address(addr : NATURAL) RETURN NATURAL IS - CONSTANT ROWS : NATURAL := 67; - CONSTANT COLS : NATURAL := 32; - VARIABLE row : NATURAL; - VARIABLE col : NATURAL; - BEGIN - row := addr / COLS; - col := addr MOD COLS; - RETURN col * ROWS + row; - END FUNCTION; + -- BIT-LEVEL interleaver address LUT (67 rows x 32 cols) + -- Pre-computed to avoid expensive division/multiply in hardware + -- Formula: row = addr/32, col = addr%32, result = col*67 + row + TYPE address_lut_t IS ARRAY(0 TO 2143) OF NATURAL RANGE 0 TO 2143; + CONSTANT INTERLEAVE_LUT : address_lut_t := ( + 0, 67, 134, 201, 268, 335, 402, 469, 536, 603, 670, 737, 804, 871, 938, 1005, + 1072, 1139, 1206, 1273, 1340, 1407, 1474, 1541, 1608, 1675, 1742, 1809, 1876, 1943, 2010, 2077, + 1, 68, 135, 202, 269, 336, 403, 470, 537, 604, 671, 738, 805, 872, 939, 1006, + 1073, 1140, 1207, 1274, 1341, 1408, 1475, 1542, 1609, 1676, 1743, 1810, 1877, 1944, 2011, 2078, + 2, 69, 136, 203, 270, 337, 404, 471, 538, 605, 672, 739, 806, 873, 940, 1007, + 1074, 1141, 1208, 1275, 1342, 1409, 1476, 1543, 1610, 1677, 1744, 1811, 1878, 1945, 2012, 2079, + 3, 70, 137, 204, 271, 338, 405, 472, 539, 606, 673, 740, 807, 874, 941, 1008, + 1075, 1142, 1209, 1276, 1343, 1410, 1477, 1544, 1611, 1678, 1745, 1812, 1879, 1946, 2013, 2080, + 4, 71, 138, 205, 272, 339, 406, 473, 540, 607, 674, 741, 808, 875, 942, 1009, + 1076, 1143, 1210, 1277, 1344, 1411, 1478, 1545, 1612, 1679, 1746, 1813, 1880, 1947, 2014, 2081, + 5, 72, 139, 206, 273, 340, 407, 474, 541, 608, 675, 742, 809, 876, 943, 1010, + 1077, 1144, 1211, 1278, 1345, 1412, 1479, 1546, 1613, 1680, 1747, 1814, 1881, 1948, 2015, 2082, + 6, 73, 140, 207, 274, 341, 408, 475, 542, 609, 676, 743, 810, 877, 944, 1011, + 1078, 1145, 1212, 1279, 1346, 1413, 1480, 1547, 1614, 1681, 1748, 1815, 1882, 1949, 2016, 2083, + 7, 74, 141, 208, 275, 342, 409, 476, 543, 610, 677, 744, 811, 878, 945, 1012, + 1079, 1146, 1213, 1280, 1347, 1414, 1481, 1548, 1615, 1682, 1749, 1816, 1883, 1950, 2017, 2084, + 8, 75, 142, 209, 276, 343, 410, 477, 544, 611, 678, 745, 812, 879, 946, 1013, + 1080, 1147, 1214, 1281, 1348, 1415, 1482, 1549, 1616, 1683, 1750, 1817, 1884, 1951, 2018, 2085, + 9, 76, 143, 210, 277, 344, 411, 478, 545, 612, 679, 746, 813, 880, 947, 1014, + 1081, 1148, 1215, 1282, 1349, 1416, 1483, 1550, 1617, 1684, 1751, 1818, 1885, 1952, 2019, 2086, + 10, 77, 144, 211, 278, 345, 412, 479, 546, 613, 680, 747, 814, 881, 948, 1015, + 1082, 1149, 1216, 1283, 1350, 1417, 1484, 1551, 1618, 1685, 1752, 1819, 1886, 1953, 2020, 2087, + 11, 78, 145, 212, 279, 346, 413, 480, 547, 614, 681, 748, 815, 882, 949, 1016, + 1083, 1150, 1217, 1284, 1351, 1418, 1485, 1552, 1619, 1686, 1753, 1820, 1887, 1954, 2021, 2088, + 12, 79, 146, 213, 280, 347, 414, 481, 548, 615, 682, 749, 816, 883, 950, 1017, + 1084, 1151, 1218, 1285, 1352, 1419, 1486, 1553, 1620, 1687, 1754, 1821, 1888, 1955, 2022, 2089, + 13, 80, 147, 214, 281, 348, 415, 482, 549, 616, 683, 750, 817, 884, 951, 1018, + 1085, 1152, 1219, 1286, 1353, 1420, 1487, 1554, 1621, 1688, 1755, 1822, 1889, 1956, 2023, 2090, + 14, 81, 148, 215, 282, 349, 416, 483, 550, 617, 684, 751, 818, 885, 952, 1019, + 1086, 1153, 1220, 1287, 1354, 1421, 1488, 1555, 1622, 1689, 1756, 1823, 1890, 1957, 2024, 2091, + 15, 82, 149, 216, 283, 350, 417, 484, 551, 618, 685, 752, 819, 886, 953, 1020, + 1087, 1154, 1221, 1288, 1355, 1422, 1489, 1556, 1623, 1690, 1757, 1824, 1891, 1958, 2025, 2092, + 16, 83, 150, 217, 284, 351, 418, 485, 552, 619, 686, 753, 820, 887, 954, 1021, + 1088, 1155, 1222, 1289, 1356, 1423, 1490, 1557, 1624, 1691, 1758, 1825, 1892, 1959, 2026, 2093, + 17, 84, 151, 218, 285, 352, 419, 486, 553, 620, 687, 754, 821, 888, 955, 1022, + 1089, 1156, 1223, 1290, 1357, 1424, 1491, 1558, 1625, 1692, 1759, 1826, 1893, 1960, 2027, 2094, + 18, 85, 152, 219, 286, 353, 420, 487, 554, 621, 688, 755, 822, 889, 956, 1023, + 1090, 1157, 1224, 1291, 1358, 1425, 1492, 1559, 1626, 1693, 1760, 1827, 1894, 1961, 2028, 2095, + 19, 86, 153, 220, 287, 354, 421, 488, 555, 622, 689, 756, 823, 890, 957, 1024, + 1091, 1158, 1225, 1292, 1359, 1426, 1493, 1560, 1627, 1694, 1761, 1828, 1895, 1962, 2029, 2096, + 20, 87, 154, 221, 288, 355, 422, 489, 556, 623, 690, 757, 824, 891, 958, 1025, + 1092, 1159, 1226, 1293, 1360, 1427, 1494, 1561, 1628, 1695, 1762, 1829, 1896, 1963, 2030, 2097, + 21, 88, 155, 222, 289, 356, 423, 490, 557, 624, 691, 758, 825, 892, 959, 1026, + 1093, 1160, 1227, 1294, 1361, 1428, 1495, 1562, 1629, 1696, 1763, 1830, 1897, 1964, 2031, 2098, + 22, 89, 156, 223, 290, 357, 424, 491, 558, 625, 692, 759, 826, 893, 960, 1027, + 1094, 1161, 1228, 1295, 1362, 1429, 1496, 1563, 1630, 1697, 1764, 1831, 1898, 1965, 2032, 2099, + 23, 90, 157, 224, 291, 358, 425, 492, 559, 626, 693, 760, 827, 894, 961, 1028, + 1095, 1162, 1229, 1296, 1363, 1430, 1497, 1564, 1631, 1698, 1765, 1832, 1899, 1966, 2033, 2100, + 24, 91, 158, 225, 292, 359, 426, 493, 560, 627, 694, 761, 828, 895, 962, 1029, + 1096, 1163, 1230, 1297, 1364, 1431, 1498, 1565, 1632, 1699, 1766, 1833, 1900, 1967, 2034, 2101, + 25, 92, 159, 226, 293, 360, 427, 494, 561, 628, 695, 762, 829, 896, 963, 1030, + 1097, 1164, 1231, 1298, 1365, 1432, 1499, 1566, 1633, 1700, 1767, 1834, 1901, 1968, 2035, 2102, + 26, 93, 160, 227, 294, 361, 428, 495, 562, 629, 696, 763, 830, 897, 964, 1031, + 1098, 1165, 1232, 1299, 1366, 1433, 1500, 1567, 1634, 1701, 1768, 1835, 1902, 1969, 2036, 2103, + 27, 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864, 931, 998, 1065, + 1132, 1199, 1266, 1333, 1400, 1467, 1534, 1601, 1668, 1735, 1802, 1869, 1936, 2003, 2070, 2137, + 61, 128, 195, 262, 329, 396, 463, 530, 597, 664, 731, 798, 865, 932, 999, 1066, + 1133, 1200, 1267, 1334, 1401, 1468, 1535, 1602, 1669, 1736, 1803, 1870, 1937, 2004, 2071, 2138, + 62, 129, 196, 263, 330, 397, 464, 531, 598, 665, 732, 799, 866, 933, 1000, 1067, + 1134, 1201, 1268, 1335, 1402, 1469, 1536, 1603, 1670, 1737, 1804, 1871, 1938, 2005, 2072, 2139, + 63, 130, 197, 264, 331, 398, 465, 532, 599, 666, 733, 800, 867, 934, 1001, 1068, + 1135, 1202, 1269, 1336, 1403, 1470, 1537, 1604, 1671, 1738, 1805, 1872, 1939, 2006, 2073, 2140, + 64, 131, 198, 265, 332, 399, 466, 533, 600, 667, 734, 801, 868, 935, 1002, 1069, + 1136, 1203, 1270, 1337, 1404, 1471, 1538, 1605, 1672, 1739, 1806, 1873, 1940, 2007, 2074, 2141, + 65, 132, 199, 266, 333, 400, 467, 534, 601, 668, 735, 802, 869, 936, 1003, 1070, + 1137, 1204, 1271, 1338, 1405, 1472, 1539, 1606, 1673, 1740, 1807, 1874, 1941, 2008, 2075, 2142, + 66, 133, 200, 267, 334, 401, 468, 535, 602, 669, 736, 803, 870, 937, 1004, 1071, + 1138, 1205, 1272, 1339, 1406, 1473, 1540, 1607, 1674, 1741, 1808, 1875, 1942, 2009, 2076, 2143 + ); BEGIN @@ -279,20 +407,13 @@ BEGIN state <= INTERLEAVE; END IF; - -- INTERLEAVE: Bit-level 67x32 interleaving - -- Process 8 bits per clock for throughput (268 clocks total) + -- INTERLEAVE: Bit-level 67x32 interleaving using pre-computed LUT + -- Process 1 bit per clock - slow but minimal LUTs (2144 clocks = 35us) WHEN INTERLEAVE => IF bit_idx < ENCODED_BITS THEN - -- Write 8 bits in parallel to their interleaved positions - interleaved_buffer(interleave_address(bit_idx + 0)) <= fec_buffer(bit_idx + 0); - interleaved_buffer(interleave_address(bit_idx + 1)) <= fec_buffer(bit_idx + 1); - interleaved_buffer(interleave_address(bit_idx + 2)) <= fec_buffer(bit_idx + 2); - interleaved_buffer(interleave_address(bit_idx + 3)) <= fec_buffer(bit_idx + 3); - interleaved_buffer(interleave_address(bit_idx + 4)) <= fec_buffer(bit_idx + 4); - interleaved_buffer(interleave_address(bit_idx + 5)) <= fec_buffer(bit_idx + 5); - interleaved_buffer(interleave_address(bit_idx + 6)) <= fec_buffer(bit_idx + 6); - interleaved_buffer(interleave_address(bit_idx + 7)) <= fec_buffer(bit_idx + 7); - bit_idx <= bit_idx + 8; + -- Write one bit using LUT for address lookup + interleaved_buffer(INTERLEAVE_LUT(bit_idx)) <= fec_buffer(bit_idx); + bit_idx <= bit_idx + 1; ELSE out_idx <= 0; state <= OUTPUT; From a563e0ad147c11b31fdbeac8bdebd695847597f1 Mon Sep 17 00:00:00 2001 From: Abraxas3d Date: Mon, 24 Nov 2025 19:41:21 -0800 Subject: [PATCH 46/60] simulation looks good for byte level interleaver. byte vs bit now optional. --- src/msk_top.vhd | 6 +- src/ov_frame_decoder.vhd | 58 +++-- src/ov_frame_encoder.vhd | 478 ++++++++++++++++++++------------------- 3 files changed, 289 insertions(+), 253 deletions(-) diff --git a/src/msk_top.vhd b/src/msk_top.vhd index e11fbd9..cb6a1dc 100644 --- a/src/msk_top.vhd +++ b/src/msk_top.vhd @@ -404,7 +404,8 @@ BEGIN PAYLOAD_BYTES => 134, ENCODED_BYTES => 268, ENCODED_BITS => 2144, - BYTE_WIDTH => 8 + BYTE_WIDTH => 8, + USE_BIT_INTERLEAVER => FALSE ) PORT MAP ( clk => clk, @@ -592,7 +593,8 @@ BEGIN PAYLOAD_BYTES => 134, ENCODED_BYTES => 268, ENCODED_BITS => 2144, - BYTE_WIDTH => 8 + BYTE_WIDTH => 8, + USE_BIT_INTERLEAVER => FALSE ) PORT MAP ( clk => clk, diff --git a/src/ov_frame_decoder.vhd b/src/ov_frame_decoder.vhd index 0cf98fe..933e2f6 100644 --- a/src/ov_frame_decoder.vhd +++ b/src/ov_frame_decoder.vhd @@ -60,10 +60,11 @@ USE ieee.numeric_std.ALL; ENTITY ov_frame_decoder IS GENERIC ( - PAYLOAD_BYTES : NATURAL := 134; -- Output frame size - ENCODED_BYTES : NATURAL := 268; -- Input frame size - ENCODED_BITS : NATURAL := 2144; -- Encoded bits (268 * 8) - BYTE_WIDTH : NATURAL := 8 + PAYLOAD_BYTES : NATURAL := 134; -- Output frame size + ENCODED_BYTES : NATURAL := 268; -- Input frame size + ENCODED_BITS : NATURAL := 2144; -- Encoded bits (268 * 8) + BYTE_WIDTH : NATURAL := 8; + USE_BIT_INTERLEAVER : BOOLEAN := TRUE -- Must match encoder setting ); PORT ( clk : IN std_logic; @@ -153,7 +154,7 @@ ARCHITECTURE rtl OF ov_frame_decoder IS SIGNAL decoder_input_g2 : std_logic_vector(2143 DOWNTO 0); SIGNAL decoder_output_buf : std_logic_vector(1071 DOWNTO 0); - -- Deinterleaver address calculation (reverse of interleaver) + -- Bit-level deinterleaver address calculation (67x32 - reverse of interleaver) FUNCTION deinterleave_address(addr : NATURAL) RETURN NATURAL IS CONSTANT ROWS : NATURAL := 67; CONSTANT COLS : NATURAL := 32; @@ -164,6 +165,18 @@ ARCHITECTURE rtl OF ov_frame_decoder IS col := addr / ROWS; RETURN row * COLS + col; END FUNCTION; + + -- Byte-level deinterleaver address calculation (67x4 - reverse of byte interleaver) + FUNCTION deinterleave_address_byte(addr : NATURAL) RETURN NATURAL IS + CONSTANT ROWS : NATURAL := 67; + CONSTANT COLS : NATURAL := 4; + VARIABLE row : NATURAL; + VARIABLE col : NATURAL; + BEGIN + row := addr MOD ROWS; + col := addr / ROWS; + RETURN row * COLS + col; + END FUNCTION; BEGIN @@ -290,16 +303,33 @@ BEGIN -- DEINTERLEAVE: Reverse the row-column shuffle WHEN DEINTERLEAVE => - IF bit_idx < ENCODED_BITS THEN - -- Unpack input_buffer bytes to bits - deinterleaved_buffer(deinterleave_address(bit_idx)) <= - input_buffer(bit_idx / 8)(bit_idx MOD 8); - bit_idx <= bit_idx + 1; + IF USE_BIT_INTERLEAVER THEN + -- BIT-LEVEL mode: Process 1 bit per clock (2144 clocks) + IF bit_idx < ENCODED_BITS THEN + -- Unpack input_buffer bytes to bits + deinterleaved_buffer(deinterleave_address(bit_idx)) <= + input_buffer(bit_idx / 8)(bit_idx MOD 8); + bit_idx <= bit_idx + 1; + ELSE + REPORT "DEINTERLEAVE complete (bit-level)"; + byte_idx <= 0; + bit_idx <= 0; + state <= PREP_FEC_DECODE; + END IF; ELSE - REPORT "DEINTERLEAVE complete"; - byte_idx <= 0; - bit_idx <= 0; - state <= PREP_FEC_DECODE; + -- BYTE-LEVEL mode: Process 1 byte per clock (268 clocks) + IF byte_idx < ENCODED_BYTES THEN + FOR j IN 0 TO 7 LOOP + deinterleaved_buffer(deinterleave_address_byte(byte_idx)*8 + j) <= + input_buffer(byte_idx)(j); + END LOOP; + byte_idx <= byte_idx + 1; + ELSE + REPORT "DEINTERLEAVE complete (byte-level)"; + byte_idx <= 0; + bit_idx <= 0; + state <= PREP_FEC_DECODE; + END IF; END IF; -- PREP_FEC_DECODE: Separate deinterleaved bits into G1 and G2 streams diff --git a/src/ov_frame_encoder.vhd b/src/ov_frame_encoder.vhd index b08d8ea..3c7de28 100644 --- a/src/ov_frame_encoder.vhd +++ b/src/ov_frame_encoder.vhd @@ -1,131 +1,50 @@ ------------------------------------------------------------------------------------------------------ +-- Opulent Voice Protocol Frame Encoder - DUAL MODE (Bit-level or Byte-level Interleaver) ------------------------------------------------------------------------------------------------------ --- _______ ________ ______ --- __ __ \________ _____ _______ ___ __ \_____ _____________ ______ ___________________ /_ --- _ / / /___ __ \_ _ \__ __ \ __ /_/ /_ _ \__ ___/_ _ \_ __ `/__ ___/_ ___/__ __ \ --- / /_/ / __ /_/ // __/_ / / / _ _, _/ / __/_(__ ) / __// /_/ / _ / / /__ _ / / / --- \____/ _ .___/ \___/ /_/ /_/ /_/ |_| \___/ /____/ \___/ \__,_/ /_/ \___/ /_/ /_/ --- /_/ --- ________ _____ _____ _____ _____ --- ____ _/_______ __________ /____(_)__ /_____ ____ /______ --- __ / __ __ \__ ___/_ __/__ / _ __/_ / / /_ __/_ _ \ --- __/ / _ / / /_(__ ) / /_ _ / / /_ / /_/ / / /_ / __/ --- /___/ /_/ /_/ /____/ \__/ /_/ \__/ \__,_/ \__/ \___/ --- ------------------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- --- Copyright ------------------------------------------------------------------------------------------------------- --- --- Copyright 2025 by Open Research Institute --- ------------------------------------------------------------------------------------------------------- --- License ------------------------------------------------------------------------------------------------------- --- --- This source describes Open Hardware and is licensed under the CERN-OHL-W v2. --- --- You may redistribute and modify this source and make products using it under --- the terms of the CERN-OHL-W v2 (https://ohwr.org/cern_ohl_w_v2.txt). --- --- This source is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING --- OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR A PARTICULAR PURPOSE. --- Please see the CERN-OHL-W v2 for applicable conditions. --- ------------------------------------------------------------------------------------------------------- --- Block name and description ------------------------------------------------------------------------------------------------------- --- --- Opulent Voice Protocol Frame Encoder --- --- This module implements the TX path processing for OVP frames: --- 1. Collects 134 bytes of payload from AXI-Stream input --- 2. Applies randomization (XOR with fixed sequence) --- 3. Applies FEC (rate 1/2 convolutional encoding via conv_encoder_k7) --- 4. Applies interleaving (67x32 row-column BIT interleaver) --- 5. Outputs 268 bytes (2144 bits) via AXI-Stream --- --- FIX (2025-11-24): Restored bit-level 67x32 interleaving --- Byte-level interleaving broke protocol compatibility --- Now processes 8 bits/clock for throughput (not 1 bit/clock) --- ------------------------------------------------------------------------------------------------------- +-- Supports both interleaver modes via generic parameter: +-- USE_BIT_INTERLEAVER = TRUE : 67x32 bit-level (correct protocol, requires large FPGA) +-- USE_BIT_INTERLEAVER = FALSE : 67x4 byte-level (fits PlutoSDR, breaks protocol compatibility) ------------------------------------------------------------------------------------------------------ LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; -ENTITY ov_frame_encoder IS +ENTITY ov_frame_encoder IS GENERIC ( - PAYLOAD_BYTES : NATURAL := 134; -- Input frame size - ENCODED_BYTES : NATURAL := 268; -- Output frame size (after FEC) - ENCODED_BITS : NATURAL := 2144; -- Encoded bits (268 * 8) - BYTE_WIDTH : NATURAL := 8 + PAYLOAD_BYTES : NATURAL := 134; + ENCODED_BYTES : NATURAL := 268; + COLLECT_SIZE : NATURAL := 4; + ENCODED_BITS : NATURAL := 2144; -- Kept for compatibility + BYTE_WIDTH : NATURAL := 8; -- Kept for compatibility + USE_BIT_INTERLEAVER : BOOLEAN := TRUE -- TRUE=bit-level(67x32), FALSE=byte-level(67x4) ); PORT ( - clk : IN std_logic; - aresetn : IN std_logic; + clk : IN std_logic; + aresetn : IN std_logic; - -- Input AXI-Stream (134-byte frames from async FIFO) - s_axis_tdata : IN std_logic_vector(BYTE_WIDTH-1 DOWNTO 0); - s_axis_tvalid : IN std_logic; - s_axis_tready : OUT std_logic; - s_axis_tlast : IN std_logic; + -- AXI-Stream Input (from application) + s_axis_tdata : IN std_logic_vector(BYTE_WIDTH-1 DOWNTO 0); + s_axis_tvalid : IN std_logic; + s_axis_tready : OUT std_logic; + s_axis_tlast : IN std_logic; - -- Output AXI-Stream (268-byte frames to deserializer) - m_axis_tdata : OUT std_logic_vector(BYTE_WIDTH-1 DOWNTO 0); - m_axis_tvalid : OUT std_logic; - m_axis_tready : IN std_logic; - m_axis_tlast : OUT std_logic; + -- AXI-Stream Output (to modulator) + m_axis_tdata : OUT std_logic_vector(BYTE_WIDTH-1 DOWNTO 0); + m_axis_tvalid : OUT std_logic; + m_axis_tready : IN std_logic; + m_axis_tlast : OUT std_logic; -- Status outputs - frames_encoded : OUT std_logic_vector(31 DOWNTO 0); - encoder_active : OUT std_logic + frames_encoded : OUT std_logic_vector(31 DOWNTO 0); + encoder_active : OUT std_logic ); END ENTITY ov_frame_encoder; ARCHITECTURE rtl OF ov_frame_encoder IS - -- State machine (no PACK_FEC needed with bit-level interleaving) - TYPE state_t IS (IDLE, COLLECT, EXTRACT, RANDOMIZE, PREP_FEC, FEC_ENCODE, INTERLEAVE, OUTPUT); - SIGNAL state : state_t := IDLE; - - -- Buffer types - TYPE byte_buffer_t IS ARRAY(0 TO PAYLOAD_BYTES-1) OF std_logic_vector(BYTE_WIDTH-1 DOWNTO 0); - TYPE bit_buffer_t IS ARRAY(0 TO ENCODED_BITS-1) OF std_logic; - - -- Circular collection buffer (larger than needed to handle any transients) - CONSTANT COLLECT_SIZE : NATURAL := 256; - TYPE collect_buffer_t IS ARRAY(0 TO COLLECT_SIZE-1) OF std_logic_vector(BYTE_WIDTH-1 DOWNTO 0); - SIGNAL collect_buffer : collect_buffer_t; - - -- Processing buffers - SIGNAL input_buffer : byte_buffer_t; - SIGNAL randomized_buffer : byte_buffer_t; - SIGNAL fec_buffer : bit_buffer_t := (OTHERS => '0'); - SIGNAL interleaved_buffer : bit_buffer_t := (OTHERS => '0'); -- BIT-level buffer! - - ATTRIBUTE ram_style : STRING; - ATTRIBUTE ram_style OF interleaved_buffer : SIGNAL IS "block"; - - -- Index counters - SIGNAL collect_idx : NATURAL RANGE 0 TO COLLECT_SIZE; - SIGNAL byte_idx : NATURAL RANGE 0 TO PAYLOAD_BYTES; - SIGNAL bit_idx : NATURAL RANGE 0 TO ENCODED_BITS; - SIGNAL out_idx : NATURAL RANGE 0 TO ENCODED_BYTES; - - -- Frame counter - SIGNAL frame_count : UNSIGNED(31 DOWNTO 0) := (OTHERS => '0'); - - -- Output holding registers - SIGNAL m_tdata_reg : std_logic_vector(BYTE_WIDTH-1 DOWNTO 0); - SIGNAL m_tvalid_reg : std_logic; - SIGNAL m_tlast_reg : std_logic; - - -- OVP Randomizer sequence (from OVP spec) + -- Randomizer sequence from protocol specification TYPE randomizer_t IS ARRAY(0 TO PAYLOAD_BYTES-1) OF std_logic_vector(7 DOWNTO 0); - -- OVP Randomizer sequence (from protocol spec - must match decoder!) CONSTANT RANDOMIZER_SEQUENCE : randomizer_t := ( x"A3", x"81", x"5C", x"C4", x"C9", x"08", x"0E", x"53", x"CC", x"A1", x"FB", x"29", x"9E", x"4F", x"16", x"E0", @@ -146,18 +65,57 @@ ARCHITECTURE rtl OF ov_frame_encoder IS x"9D", x"8E", x"E8", x"34", x"C9", x"59" ); - -- Convolutional encoder signals (matches conv_encoder_k7 interface) + TYPE state_t IS ( + IDLE, + COLLECT, + EXTRACT, + RANDOMIZE, + PREP_FEC, + FEC_ENCODE, + INTERLEAVE, + OUTPUT + ); + SIGNAL state : state_t := IDLE; + + TYPE byte_buffer_t IS ARRAY(0 TO PAYLOAD_BYTES-1) OF std_logic_vector(7 DOWNTO 0); + TYPE bit_buffer_t IS ARRAY(0 TO ENCODED_BITS-1) OF std_logic; + + SIGNAL input_buffer : byte_buffer_t; + SIGNAL randomized_buffer : byte_buffer_t; + SIGNAL fec_buffer : bit_buffer_t := (OTHERS => '0'); + SIGNAL interleaved_buffer : bit_buffer_t := (OTHERS => '0'); + + ATTRIBUTE ram_style : STRING; + ATTRIBUTE ram_style OF interleaved_buffer : SIGNAL IS "block"; + + -- Index counters + SIGNAL collect_idx : NATURAL RANGE 0 TO COLLECT_SIZE; + SIGNAL byte_idx : NATURAL RANGE 0 TO PAYLOAD_BYTES; + SIGNAL bit_idx : NATURAL RANGE 0 TO ENCODED_BITS; + SIGNAL out_idx : NATURAL RANGE 0 TO ENCODED_BYTES; + + -- AXI-Stream control + SIGNAL s_axis_tready_reg : std_logic := '0'; + SIGNAL m_axis_tdata_reg : std_logic_vector(BYTE_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL m_axis_tvalid_reg : std_logic := '0'; + SIGNAL m_axis_tlast_reg : std_logic := '0'; + + -- Status counters + SIGNAL frames_encoded_reg : unsigned(31 DOWNTO 0) := (OTHERS => '0'); + SIGNAL encoder_active_reg : std_logic := '0'; + + -- Convolutional encoder signals SIGNAL encoder_start : std_logic := '0'; SIGNAL encoder_busy : std_logic; SIGNAL encoder_done : std_logic; - SIGNAL encoder_input_buf : std_logic_vector(1071 DOWNTO 0); -- 134*8 - SIGNAL encoder_output_buf : std_logic_vector(2143 DOWNTO 0); -- 268*8 + SIGNAL encoder_input_buf : std_logic_vector(1071 DOWNTO 0); + SIGNAL encoder_output_buf : std_logic_vector(2143 DOWNTO 0); - -- BIT-LEVEL interleaver address LUT (67 rows x 32 cols) - -- Pre-computed to avoid expensive division/multiply in hardware - -- Formula: row = addr/32, col = addr%32, result = col*67 + row + ---------------------------------------------------------------------------- + -- BIT-LEVEL INTERLEAVER (67x32) - For large FPGAs, correct protocol + ---------------------------------------------------------------------------- TYPE address_lut_t IS ARRAY(0 TO 2143) OF NATURAL RANGE 0 TO 2143; - CONSTANT INTERLEAVE_LUT : address_lut_t := ( + CONSTANT INTERLEAVE_LUT_BIT : address_lut_t := ( 0, 67, 134, 201, 268, 335, 402, 469, 536, 603, 670, 737, 804, 871, 938, 1005, 1072, 1139, 1206, 1273, 1340, 1407, 1474, 1541, 1608, 1675, 1742, 1809, 1876, 1943, 2010, 2077, 1, 68, 135, 202, 269, 336, 403, 470, 537, 604, 671, 738, 805, 872, 939, 1006, @@ -293,10 +251,24 @@ ARCHITECTURE rtl OF ov_frame_encoder IS 66, 133, 200, 267, 334, 401, 468, 535, 602, 669, 736, 803, 870, 937, 1004, 1071, 1138, 1205, 1272, 1339, 1406, 1473, 1540, 1607, 1674, 1741, 1808, 1875, 1942, 2009, 2076, 2143 ); - + + ---------------------------------------------------------------------------- + -- BYTE-LEVEL INTERLEAVER (67x4) - For PlutoSDR, fits in xc7z010 + ---------------------------------------------------------------------------- + FUNCTION interleave_address_byte(addr : NATURAL) RETURN NATURAL IS + CONSTANT ROWS : NATURAL := 67; + CONSTANT COLS : NATURAL := 4; + VARIABLE row : NATURAL; + VARIABLE col : NATURAL; + BEGIN + row := addr / COLS; + col := addr MOD COLS; + RETURN col * ROWS + row; + END FUNCTION; + BEGIN - -- Convolutional Encoder Instantiation (using YOUR actual component) + -- Convolutional Encoder Instantiation U_ENCODER : ENTITY work.conv_encoder_k7 GENERIC MAP ( PAYLOAD_BYTES => PAYLOAD_BYTES, @@ -312,148 +284,180 @@ BEGIN output_buffer => encoder_output_buf ); - -- Connect output registers to ports - m_axis_tdata <= m_tdata_reg; - m_axis_tvalid <= m_tvalid_reg; - m_axis_tlast <= m_tlast_reg; - - frames_encoded <= std_logic_vector(frame_count); - encoder_active <= '1' WHEN state /= IDLE ELSE '0'; + -- AXI-Stream output assignments + s_axis_tready <= s_axis_tready_reg; + m_axis_tdata <= m_axis_tdata_reg; + m_axis_tvalid <= m_axis_tvalid_reg; + m_axis_tlast <= m_axis_tlast_reg; - -- Ready to accept data when IDLE or COLLECT - s_axis_tready <= '1' WHEN (state = IDLE OR state = COLLECT) AND aresetn = '1' ELSE '0'; - - -- Main FSM - encoder_fsm: PROCESS(clk) + -- Status outputs + frames_encoded <= std_logic_vector(frames_encoded_reg); + encoder_active <= encoder_active_reg; + + -- Main State Machine + PROCESS(clk, aresetn) + VARIABLE out_bit_idx : NATURAL RANGE 0 TO 7; BEGIN - IF rising_edge(clk) THEN - IF aresetn = '0' THEN - state <= IDLE; - collect_idx <= 0; - byte_idx <= 0; - bit_idx <= 0; - out_idx <= 0; - m_tvalid_reg <= '0'; - m_tlast_reg <= '0'; - encoder_start <= '0'; - frame_count <= (OTHERS => '0'); - ELSE - CASE state IS - -- IDLE: Wait for start of frame - WHEN IDLE => - m_tvalid_reg <= '0'; - m_tlast_reg <= '0'; - encoder_start <= '0'; - - IF s_axis_tvalid = '1' THEN - collect_buffer(0) <= s_axis_tdata; - collect_idx <= 1; - state <= COLLECT; - END IF; - - -- COLLECT: Gather bytes until tlast - WHEN COLLECT => - IF s_axis_tvalid = '1' THEN - collect_buffer(collect_idx MOD COLLECT_SIZE) <= s_axis_tdata; - collect_idx <= collect_idx + 1; - - IF s_axis_tlast = '1' THEN - byte_idx <= 0; - state <= EXTRACT; - END IF; - END IF; - - -- EXTRACT: Pull last 134 bytes from circular buffer - WHEN EXTRACT => - IF byte_idx < PAYLOAD_BYTES THEN - input_buffer(byte_idx) <= - collect_buffer((collect_idx - PAYLOAD_BYTES + byte_idx) MOD COLLECT_SIZE); - byte_idx <= byte_idx + 1; + IF aresetn = '0' THEN + state <= IDLE; + collect_idx <= 0; + byte_idx <= 0; + bit_idx <= 0; + out_idx <= 0; + s_axis_tready_reg <= '0'; + m_axis_tdata_reg <= (OTHERS => '0'); + m_axis_tvalid_reg <= '0'; + m_axis_tlast_reg <= '0'; + encoder_start <= '0'; + frames_encoded_reg <= (OTHERS => '0'); + encoder_active_reg <= '0'; + + ELSIF rising_edge(clk) THEN + encoder_start <= '0'; + + CASE state IS + + -- IDLE: Wait for input + WHEN IDLE => + s_axis_tready_reg <= '1'; + m_axis_tvalid_reg <= '0'; + m_axis_tlast_reg <= '0'; + encoder_active_reg <= '0'; + IF s_axis_tvalid = '1' AND s_axis_tready_reg = '1' THEN + input_buffer(0) <= s_axis_tdata; + collect_idx <= 1; + encoder_active_reg <= '1'; + state <= COLLECT; + END IF; + + -- COLLECT: Gather 4 bytes before proceeding + WHEN COLLECT => + IF s_axis_tvalid = '1' AND s_axis_tready_reg = '1' THEN + input_buffer(collect_idx) <= s_axis_tdata; + IF collect_idx = COLLECT_SIZE - 1 THEN + collect_idx <= COLLECT_SIZE; -- Continue from position 4, not 0 + s_axis_tready_reg <= '0'; + state <= EXTRACT; ELSE - byte_idx <= 0; - state <= RANDOMIZE; + collect_idx <= collect_idx + 1; END IF; - - -- RANDOMIZE: XOR with randomizer sequence - WHEN RANDOMIZE => - IF byte_idx < PAYLOAD_BYTES THEN - randomized_buffer(byte_idx) <= - input_buffer(byte_idx) XOR RANDOMIZER_SEQUENCE(byte_idx); - byte_idx <= byte_idx + 1; - ELSE - byte_idx <= 0; - state <= PREP_FEC; + END IF; + + -- EXTRACT: Continue collecting remaining bytes + WHEN EXTRACT => + IF collect_idx < PAYLOAD_BYTES THEN + s_axis_tready_reg <= '1'; + IF s_axis_tvalid = '1' AND s_axis_tready_reg = '1' THEN + input_buffer(collect_idx) <= s_axis_tdata; + collect_idx <= collect_idx + 1; END IF; - - -- PREP_FEC: Pack bytes into encoder input vector - WHEN PREP_FEC => - FOR i IN 0 TO PAYLOAD_BYTES-1 LOOP - FOR j IN 0 TO 7 LOOP - encoder_input_buf(i*8 + j) <= randomized_buffer(i)(j); - END LOOP; + ELSE + s_axis_tready_reg <= '0'; + byte_idx <= 0; + state <= RANDOMIZE; + END IF; + + -- RANDOMIZE: XOR with randomizer sequence + WHEN RANDOMIZE => + IF byte_idx < PAYLOAD_BYTES THEN + randomized_buffer(byte_idx) <= + input_buffer(byte_idx) XOR RANDOMIZER_SEQUENCE(byte_idx); + byte_idx <= byte_idx + 1; + ELSE + byte_idx <= 0; + state <= PREP_FEC; + END IF; + + -- PREP_FEC: Pack randomized bytes into encoder input buffer + WHEN PREP_FEC => + IF byte_idx < PAYLOAD_BYTES THEN + FOR j IN 0 TO 7 LOOP + encoder_input_buf(byte_idx*8 + j) <= randomized_buffer(byte_idx)(j); END LOOP; + byte_idx <= byte_idx + 1; + ELSE encoder_start <= '1'; state <= FEC_ENCODE; - - -- FEC_ENCODE: Wait for convolutional encoder to complete - WHEN FEC_ENCODE => - encoder_start <= '0'; - IF encoder_done = '1' THEN - -- Unpack encoded bits into fec_buffer - FOR i IN 0 TO ENCODED_BITS-1 LOOP - fec_buffer(i) <= encoder_output_buf(ENCODED_BITS - 1 - i); -- MSB-first - END LOOP; + END IF; + + -- FEC_ENCODE: Wait for convolutional encoder to complete + WHEN FEC_ENCODE => + encoder_start <= '0'; + IF encoder_done = '1' THEN + -- Copy encoder output to fec_buffer (MSB-first to bit-buffer) + FOR i IN 0 TO ENCODED_BITS-1 LOOP + fec_buffer(i) <= encoder_output_buf(ENCODED_BITS - 1 - i); + END LOOP; + + IF USE_BIT_INTERLEAVER THEN bit_idx <= 0; - state <= INTERLEAVE; + ELSE + byte_idx <= 0; END IF; - - -- INTERLEAVE: Bit-level 67x32 interleaving using pre-computed LUT - -- Process 1 bit per clock - slow but minimal LUTs (2144 clocks = 35us) - WHEN INTERLEAVE => + state <= INTERLEAVE; + END IF; + + ------------------------------------------------------------------------ + -- INTERLEAVE: Dual-mode implementation + ------------------------------------------------------------------------ + WHEN INTERLEAVE => + IF USE_BIT_INTERLEAVER THEN + -- BIT-LEVEL mode: Process 1 bit per clock (2144 clocks) IF bit_idx < ENCODED_BITS THEN - -- Write one bit using LUT for address lookup - interleaved_buffer(INTERLEAVE_LUT(bit_idx)) <= fec_buffer(bit_idx); + interleaved_buffer(INTERLEAVE_LUT_BIT(bit_idx)) <= fec_buffer(bit_idx); bit_idx <= bit_idx + 1; ELSE out_idx <= 0; state <= OUTPUT; - m_tvalid_reg <= '0'; + m_axis_tvalid_reg <= '0'; END IF; - - -- OUTPUT: Send 268 bytes via AXI-Stream - -- Pack 8 bits from interleaved buffer into each output byte - WHEN OUTPUT => - IF out_idx < ENCODED_BYTES THEN - m_tdata_reg(0) <= interleaved_buffer(out_idx * 8 + 0); - m_tdata_reg(1) <= interleaved_buffer(out_idx * 8 + 1); - m_tdata_reg(2) <= interleaved_buffer(out_idx * 8 + 2); - m_tdata_reg(3) <= interleaved_buffer(out_idx * 8 + 3); - m_tdata_reg(4) <= interleaved_buffer(out_idx * 8 + 4); - m_tdata_reg(5) <= interleaved_buffer(out_idx * 8 + 5); - m_tdata_reg(6) <= interleaved_buffer(out_idx * 8 + 6); - m_tdata_reg(7) <= interleaved_buffer(out_idx * 8 + 7); + ELSE + -- BYTE-LEVEL mode: Process 1 byte per clock (268 clocks) + IF byte_idx < ENCODED_BYTES THEN + FOR j IN 0 TO 7 LOOP + interleaved_buffer(interleave_address_byte(byte_idx)*8 + j) <= + fec_buffer(byte_idx*8 + j); + END LOOP; + byte_idx <= byte_idx + 1; + ELSE + out_idx <= 0; + state <= OUTPUT; + m_axis_tvalid_reg <= '0'; + END IF; + END IF; + + -- OUTPUT: Stream interleaved bytes to modulator + WHEN OUTPUT => + IF out_idx < ENCODED_BYTES THEN + IF m_axis_tready = '1' OR m_axis_tvalid_reg = '0' THEN + -- Pack 8 bits from interleaved_buffer into output byte + FOR j IN 0 TO 7 LOOP + out_bit_idx := out_idx*8 + j; + m_axis_tdata_reg(j) <= interleaved_buffer(out_bit_idx); + END LOOP; + m_axis_tvalid_reg <= '1'; - m_tvalid_reg <= '1'; - IF out_idx = (ENCODED_BYTES - 1) THEN - m_tlast_reg <= '1'; + -- Assert tlast on final byte + IF out_idx = ENCODED_BYTES - 1 THEN + m_axis_tlast_reg <= '1'; ELSE - m_tlast_reg <= '0'; + m_axis_tlast_reg <= '0'; END IF; - IF m_axis_tready = '1' THEN - IF out_idx = (ENCODED_BYTES - 1) THEN - frame_count <= frame_count + 1; - state <= IDLE; - m_tvalid_reg <= '0'; - ELSE - out_idx <= out_idx + 1; - END IF; - END IF; + out_idx <= out_idx + 1; END IF; - - END CASE; - END IF; + ELSE + IF m_axis_tready = '1' THEN + m_axis_tvalid_reg <= '0'; + m_axis_tlast_reg <= '0'; + frames_encoded_reg <= frames_encoded_reg + 1; + collect_idx <= 0; + state <= IDLE; + END IF; + END IF; + + END CASE; END IF; - END PROCESS encoder_fsm; + END PROCESS; END ARCHITECTURE rtl; From 2cc8fa595d9fd89c6ee4958504bb042c87a7d0b9 Mon Sep 17 00:00:00 2001 From: Abraxas3d Date: Tue, 25 Nov 2025 09:56:43 -0800 Subject: [PATCH 47/60] simulation now working with yet again the count back from tlast method working for us. added a lot of comments about this to the source code. --- src/ov_frame_encoder.vhd | 176 ++++++++++++++++++++++++++++++++------- 1 file changed, 144 insertions(+), 32 deletions(-) diff --git a/src/ov_frame_encoder.vhd b/src/ov_frame_encoder.vhd index 3c7de28..b26f49c 100644 --- a/src/ov_frame_encoder.vhd +++ b/src/ov_frame_encoder.vhd @@ -5,6 +5,35 @@ -- USE_BIT_INTERLEAVER = TRUE : 67x32 bit-level (correct protocol, requires large FPGA) -- USE_BIT_INTERLEAVER = FALSE : 67x4 byte-level (fits PlutoSDR, breaks protocol compatibility) ------------------------------------------------------------------------------------------------------ +-- CRITICAL DESIGN PRINCIPLE: TLAST-DRIVEN FRAME COLLECTION +------------------------------------------------------------------------------------------------------ +-- This encoder uses AXI-Stream TLAST signal to detect frame boundaries, NOT fixed byte counting! +-- +-- WHY THIS MATTERS: +-- When data flows continuously (e.g., FIFO buffering multiple frames), counting to a fixed +-- number of bytes and ignoring tlast causes the encoder to "steal" bytes from the next frame. +-- This creates cascading byte loss: +-- Frame 3: Missing byte 0 (stolen during Frame 2 collection) +-- Frame 4: Missing bytes 0-1 (stolen during Frame 3 collection) +-- Frame 5: Missing bytes 0-2 (stolen during Frame 4 collection) +-- ... continues until no more data available +-- +-- CORRECT APPROACH (implemented here): +-- 1. IDLE state: Wait for first byte +-- 2. COLLECT state: Accept bytes until s_axis_tlast = '1' (frame boundary marker) +-- 3. Validate we got exactly PAYLOAD_BYTES (134) +-- 4. Process the complete frame through randomization, FEC, interleaving +-- 5. Pre-set s_axis_tready = '1' before returning to IDLE for next frame +-- +-- This approach: +-- ? Respects AXI-Stream protocol (tlast marks frame boundaries) +-- ? Works with continuous data streams (FIFO buffering) +-- ? Prevents byte stealing across frame boundaries +-- ? Validates frame size for error detection +-- ? Works for BOTH bit-level and byte-level interleaving modes +-- +-- NEVER count to a fixed byte number and ignore tlast - this violates AXI-Stream protocol! +------------------------------------------------------------------------------------------------------ LIBRARY ieee; USE ieee.std_logic_1164.ALL; @@ -14,7 +43,7 @@ ENTITY ov_frame_encoder IS GENERIC ( PAYLOAD_BYTES : NATURAL := 134; ENCODED_BYTES : NATURAL := 268; - COLLECT_SIZE : NATURAL := 4; + COLLECT_SIZE : NATURAL := 4; -- DEPRECATED: No longer used (kept for compatibility) ENCODED_BITS : NATURAL := 2144; -- Kept for compatibility BYTE_WIDTH : NATURAL := 8; -- Kept for compatibility USE_BIT_INTERLEAVER : BOOLEAN := TRUE -- TRUE=bit-level(67x32), FALSE=byte-level(67x4) @@ -65,15 +94,37 @@ ARCHITECTURE rtl OF ov_frame_encoder IS x"9D", x"8E", x"E8", x"34", x"C9", x"59" ); + ------------------------------------------------------------------------------ + -- STATE MACHINE DESIGN PHILOSOPHY + ------------------------------------------------------------------------------ + -- CRITICAL: This encoder uses TLAST-DRIVEN frame detection, NOT fixed byte counting! + -- + -- WHY: AXI-Stream protocol uses tlast to mark frame boundaries. Ignoring tlast + -- causes the encoder to "steal" bytes from the next frame when data is + -- continuously available (e.g., from a buffering FIFO). This creates + -- cascading byte loss errors across multiple frames. + -- + -- COLLECT state strategy: + -- 1. Accept bytes one at a time + -- 2. Store each byte in input_buffer[collect_idx] + -- 3. Watch for s_axis_tlast = '1' (frame boundary) + -- 4. When tlast seen, validate we got PAYLOAD_BYTES (134), then process + -- + -- This works for BOTH byte-level and bit-level interleaving modes because: + -- - Collection only fills input_buffer + -- - Interleaving happens later (INTERLEAVE state) on FEC-encoded bits + -- - Interleaver type doesn't affect how we collect input bytes + -- + -- NEVER count to a fixed number and ignore tlast - this violates AXI protocol! + ------------------------------------------------------------------------------ TYPE state_t IS ( - IDLE, - COLLECT, - EXTRACT, - RANDOMIZE, - PREP_FEC, - FEC_ENCODE, - INTERLEAVE, - OUTPUT + IDLE, -- Wait for first byte of frame + COLLECT, -- Gather bytes until tlast (AXI-Stream frame boundary marker) + RANDOMIZE, -- XOR with randomizer sequence + PREP_FEC, -- Prepare for convolutional encoding + FEC_ENCODE, -- Apply K=7 convolutional code + INTERLEAVE, -- Shuffle bits (bit-level) or bytes (byte-level) per generic + OUTPUT -- Stream encoded frame to modulator ); SIGNAL state : state_t := IDLE; @@ -89,7 +140,7 @@ ARCHITECTURE rtl OF ov_frame_encoder IS ATTRIBUTE ram_style OF interleaved_buffer : SIGNAL IS "block"; -- Index counters - SIGNAL collect_idx : NATURAL RANGE 0 TO COLLECT_SIZE; + SIGNAL collect_idx : NATURAL RANGE 0 TO PAYLOAD_BYTES; -- Now collects all bytes until tlast SIGNAL byte_idx : NATURAL RANGE 0 TO PAYLOAD_BYTES; SIGNAL bit_idx : NATURAL RANGE 0 TO ENCODED_BITS; SIGNAL out_idx : NATURAL RANGE 0 TO ENCODED_BYTES; @@ -317,46 +368,95 @@ BEGIN CASE state IS - -- IDLE: Wait for input + ---------------------------------------------------------------------- + -- IDLE: Wait for first byte of frame + ---------------------------------------------------------------------- + -- Ready to accept data. When valid data arrives, capture first byte + -- and check for tlast (single-byte frame, unlikely but possible). + ---------------------------------------------------------------------- WHEN IDLE => - s_axis_tready_reg <= '1'; + s_axis_tready_reg <= '1'; -- Always ready in IDLE m_axis_tvalid_reg <= '0'; m_axis_tlast_reg <= '0'; encoder_active_reg <= '0'; + IF s_axis_tvalid = '1' AND s_axis_tready_reg = '1' THEN + -- Capture first byte input_buffer(0) <= s_axis_tdata; collect_idx <= 1; encoder_active_reg <= '1'; - state <= COLLECT; + + -- Check for single-byte frame (shouldn't happen for 134-byte frames) + IF s_axis_tlast = '1' THEN + s_axis_tready_reg <= '0'; + REPORT "Single-byte frame detected (unexpected)" SEVERITY WARNING; + byte_idx <= 0; + state <= RANDOMIZE; + ELSE + state <= COLLECT; + END IF; END IF; - -- COLLECT: Gather 4 bytes before proceeding + + ---------------------------------------------------------------------- + -- COLLECT: Gather bytes until tlast (AXI-Stream frame boundary) + ---------------------------------------------------------------------- + -- This is the CRITICAL state that prevents byte loss! + -- + -- Strategy: + -- - Keep s_axis_tready = 1 (accept data) + -- - Capture each byte to input_buffer[collect_idx] + -- - Increment collect_idx + -- - WATCH FOR TLAST (frame boundary marker) + -- - When tlast seen, validate frame size and proceed to encoding + -- + -- Why not count to 134 and ignore tlast? + -- Because when FIFO has next frame buffered, we'd keep accepting + -- bytes past the frame boundary, "stealing" from the next frame. + -- This causes cascading byte loss (Frame 3 missing byte 0, + -- Frame 4 missing bytes 0-1, etc.) + -- + -- TLAST is the ONLY reliable frame boundary in AXI-Stream protocol! + ---------------------------------------------------------------------- WHEN COLLECT => + s_axis_tready_reg <= '1'; -- Keep accepting data + IF s_axis_tvalid = '1' AND s_axis_tready_reg = '1' THEN + -- Capture byte input_buffer(collect_idx) <= s_axis_tdata; - IF collect_idx = COLLECT_SIZE - 1 THEN - collect_idx <= COLLECT_SIZE; -- Continue from position 4, not 0 + + -- Check for frame boundary (tlast = end of frame) + IF s_axis_tlast = '1' THEN + -- Frame complete! Stop accepting data s_axis_tready_reg <= '0'; - state <= EXTRACT; + + -- Validate frame size (collect_idx is 0-indexed, so +1 for count) + IF collect_idx + 1 /= PAYLOAD_BYTES THEN + REPORT "Frame size mismatch: expected " & + INTEGER'IMAGE(PAYLOAD_BYTES) & " bytes, got " & + INTEGER'IMAGE(collect_idx + 1) & " bytes" + SEVERITY WARNING; + END IF; + + -- Proceed to randomization (even if size is wrong, try to process) + byte_idx <= 0; + state <= RANDOMIZE; ELSE + -- Not end of frame yet, continue collecting collect_idx <= collect_idx + 1; + + -- Safety check: prevent buffer overflow + IF collect_idx >= PAYLOAD_BYTES - 1 THEN + REPORT "Collected " & INTEGER'IMAGE(PAYLOAD_BYTES) & + " bytes but tlast not seen yet! Frame too large!" + SEVERITY ERROR; + s_axis_tready_reg <= '0'; + byte_idx <= 0; + state <= RANDOMIZE; -- Try to process what we have + END IF; END IF; END IF; - -- EXTRACT: Continue collecting remaining bytes - WHEN EXTRACT => - IF collect_idx < PAYLOAD_BYTES THEN - s_axis_tready_reg <= '1'; - IF s_axis_tvalid = '1' AND s_axis_tready_reg = '1' THEN - input_buffer(collect_idx) <= s_axis_tdata; - collect_idx <= collect_idx + 1; - END IF; - ELSE - s_axis_tready_reg <= '0'; - byte_idx <= 0; - state <= RANDOMIZE; - END IF; - -- RANDOMIZE: XOR with randomizer sequence WHEN RANDOMIZE => IF byte_idx < PAYLOAD_BYTES THEN @@ -426,7 +526,12 @@ BEGIN END IF; END IF; + ---------------------------------------------------------------------- -- OUTPUT: Stream interleaved bytes to modulator + ---------------------------------------------------------------------- + -- Send encoded frame one byte at a time via AXI-Stream. + -- Assert tlast on final byte to mark frame boundary. + ---------------------------------------------------------------------- WHEN OUTPUT => IF out_idx < ENCODED_BYTES THEN IF m_axis_tready = '1' OR m_axis_tvalid_reg = '0' THEN @@ -437,7 +542,7 @@ BEGIN END LOOP; m_axis_tvalid_reg <= '1'; - -- Assert tlast on final byte + -- Assert tlast on final byte (AXI-Stream frame boundary) IF out_idx = ENCODED_BYTES - 1 THEN m_axis_tlast_reg <= '1'; ELSE @@ -447,9 +552,16 @@ BEGIN out_idx <= out_idx + 1; END IF; ELSE + -- Frame output complete IF m_axis_tready = '1' THEN m_axis_tvalid_reg <= '0'; m_axis_tlast_reg <= '0'; + + -- Pre-set ready for next frame BEFORE going to IDLE + -- This ensures s_axis_tready is already high when we + -- enter IDLE, preventing one-clock delay in handshake + s_axis_tready_reg <= '1'; + frames_encoded_reg <= frames_encoded_reg + 1; collect_idx <= 0; state <= IDLE; From 247beadb3597de6dc21dd9ceb8022247a0fba546 Mon Sep 17 00:00:00 2001 From: Abraxas3d Date: Wed, 26 Nov 2025 08:40:30 -0800 Subject: [PATCH 48/60] experiment to isolate encoder as source of lab hardware transmitter stall --- src/axis_async_fifo.vhd | 4 +++ src/msk_top.vhd | 70 ++++++++++++++++++++++------------------- 2 files changed, 42 insertions(+), 32 deletions(-) diff --git a/src/axis_async_fifo.vhd b/src/axis_async_fifo.vhd index 311a24d..28ccfbb 100644 --- a/src/axis_async_fifo.vhd +++ b/src/axis_async_fifo.vhd @@ -157,6 +157,8 @@ BEGIN full_int <= '0'; tready_int <= '0'; prog_full_int <= '0'; + rd_ptr_gray_sync1 <= (OTHERS => '0'); + rd_ptr_gray_sync2 <= (OTHERS => '0'); ELSE -- Synchronize read pointer @@ -221,6 +223,8 @@ BEGIN prog_empty_int <= '1'; m_axis_tdata <= (OTHERS => '0'); m_axis_tlast <= '0'; + wr_ptr_gray_sync1 <= (OTHERS => '0'); + wr_ptr_gray_sync2 <= (OTHERS => '0'); ELSE -- Synchronize write pointer diff --git a/src/msk_top.vhd b/src/msk_top.vhd index cb6a1dc..99edfed 100644 --- a/src/msk_top.vhd +++ b/src/msk_top.vhd @@ -399,34 +399,34 @@ BEGIN -- This will be corrected in Phase 2 when PS side is updated to send 134-byte frames ------------------------------------------------------------------------------------------------------ - u_ov_encoder : ENTITY work.ov_frame_encoder - GENERIC MAP ( - PAYLOAD_BYTES => 134, - ENCODED_BYTES => 268, - ENCODED_BITS => 2144, - BYTE_WIDTH => 8, - USE_BIT_INTERLEAVER => FALSE - ) - PORT MAP ( - clk => clk, - aresetn => NOT txinit, - - -- Input from FIFO - s_axis_tdata => fifo_tdata, - s_axis_tvalid => fifo_tvalid, - s_axis_tready => fifo_tready, - s_axis_tlast => fifo_tlast, - - -- Output to deserializer - m_axis_tdata => encoder_tdata, - m_axis_tvalid => encoder_tvalid, - m_axis_tready => encoder_tready, - m_axis_tlast => encoder_tlast, - - -- Status - frames_encoded => tx_frames_encoded, - encoder_active => tx_encoder_active - ); +-- u_ov_encoder : ENTITY work.ov_frame_encoder +-- GENERIC MAP ( +-- PAYLOAD_BYTES => 134, +-- ENCODED_BYTES => 268, +-- ENCODED_BITS => 2144, +-- BYTE_WIDTH => 8, +-- USE_BIT_INTERLEAVER => FALSE +-- ) +-- PORT MAP ( +-- clk => clk, +-- aresetn => NOT txinit, +-- +-- -- Input from FIFO +-- s_axis_tdata => fifo_tdata, +-- s_axis_tvalid => fifo_tvalid, +-- s_axis_tready => fifo_tready, +-- s_axis_tlast => fifo_tlast, +-- +-- -- Output to deserializer +-- m_axis_tdata => encoder_tdata, +-- m_axis_tvalid => encoder_tvalid, +-- m_axis_tready => encoder_tready, +-- m_axis_tlast => encoder_tlast, +-- +-- -- Status +-- frames_encoded => tx_frames_encoded, +-- encoder_active => tx_encoder_active +-- ); -- Stage 4: Byte-to-Bit De-serializer (MSB-FIRST VERSION) u_deserializer : ENTITY work.byte_to_bit_deserializer @@ -438,10 +438,16 @@ BEGIN init => txinit, -- Input from encoder (was: from FIFO) - s_axis_tdata => encoder_tdata, - s_axis_tvalid => encoder_tvalid, - s_axis_tready => encoder_tready, - s_axis_tlast => encoder_tlast, + --s_axis_tdata => encoder_tdata, + --s_axis_tvalid => encoder_tvalid, + --s_axis_tready => encoder_tready, + --s_axis_tlast => encoder_tlast, + + s_axis_tdata => fifo_tdata, + s_axis_tvalid => fifo_tvalid, + s_axis_tready => fifo_tready, + s_axis_tlast => fifo_tlast, + tx_data => tx_data_bit, tx_req => tx_req, From cd5f27cdc9adc550c9c1c01bef4b0187273522b4 Mon Sep 17 00:00:00 2001 From: Abraxas3d Date: Thu, 27 Nov 2025 11:03:52 -0800 Subject: [PATCH 49/60] decoder created a stall with no gaps between frames. this is a fix for that. works in encoder-decoder testbench and end-to-end testbench. --- src/msk_top.vhd | 75 ++++++++++++++++--------------- src/ov_frame_decoder.vhd | 21 ++++++++- src/viterbi_decoder_k7_simple.vhd | 12 +++-- 3 files changed, 67 insertions(+), 41 deletions(-) diff --git a/src/msk_top.vhd b/src/msk_top.vhd index 99edfed..cabc9ee 100644 --- a/src/msk_top.vhd +++ b/src/msk_top.vhd @@ -399,34 +399,34 @@ BEGIN -- This will be corrected in Phase 2 when PS side is updated to send 134-byte frames ------------------------------------------------------------------------------------------------------ --- u_ov_encoder : ENTITY work.ov_frame_encoder --- GENERIC MAP ( --- PAYLOAD_BYTES => 134, --- ENCODED_BYTES => 268, --- ENCODED_BITS => 2144, --- BYTE_WIDTH => 8, --- USE_BIT_INTERLEAVER => FALSE --- ) --- PORT MAP ( --- clk => clk, --- aresetn => NOT txinit, --- --- -- Input from FIFO --- s_axis_tdata => fifo_tdata, --- s_axis_tvalid => fifo_tvalid, --- s_axis_tready => fifo_tready, --- s_axis_tlast => fifo_tlast, --- --- -- Output to deserializer --- m_axis_tdata => encoder_tdata, --- m_axis_tvalid => encoder_tvalid, --- m_axis_tready => encoder_tready, --- m_axis_tlast => encoder_tlast, --- --- -- Status --- frames_encoded => tx_frames_encoded, --- encoder_active => tx_encoder_active --- ); + u_ov_encoder : ENTITY work.ov_frame_encoder + GENERIC MAP ( + PAYLOAD_BYTES => 134, + ENCODED_BYTES => 268, + ENCODED_BITS => 2144, + BYTE_WIDTH => 8, + USE_BIT_INTERLEAVER => FALSE + ) + PORT MAP ( + clk => clk, + aresetn => NOT txinit, + + -- Input from FIFO + s_axis_tdata => fifo_tdata, + s_axis_tvalid => fifo_tvalid, + s_axis_tready => fifo_tready, + s_axis_tlast => fifo_tlast, + + -- Output to deserializer + m_axis_tdata => encoder_tdata, + m_axis_tvalid => encoder_tvalid, + m_axis_tready => encoder_tready, + m_axis_tlast => encoder_tlast, + + -- Status + frames_encoded => tx_frames_encoded, + encoder_active => tx_encoder_active + ); -- Stage 4: Byte-to-Bit De-serializer (MSB-FIRST VERSION) u_deserializer : ENTITY work.byte_to_bit_deserializer @@ -438,15 +438,16 @@ BEGIN init => txinit, -- Input from encoder (was: from FIFO) - --s_axis_tdata => encoder_tdata, - --s_axis_tvalid => encoder_tvalid, - --s_axis_tready => encoder_tready, - --s_axis_tlast => encoder_tlast, - - s_axis_tdata => fifo_tdata, - s_axis_tvalid => fifo_tvalid, - s_axis_tready => fifo_tready, - s_axis_tlast => fifo_tlast, + s_axis_tdata => encoder_tdata, + s_axis_tvalid => encoder_tvalid, + s_axis_tready => encoder_tready, + s_axis_tlast => encoder_tlast, + + -- if you want to bypass the encoder, then comment out encoder above and use this: + --s_axis_tdata => fifo_tdata, + --s_axis_tvalid => fifo_tvalid, + --s_axis_tready => fifo_tready, + --s_axis_tlast => fifo_tlast, tx_data => tx_data_bit, diff --git a/src/ov_frame_decoder.vhd b/src/ov_frame_decoder.vhd index 933e2f6..5e2e8eb 100644 --- a/src/ov_frame_decoder.vhd +++ b/src/ov_frame_decoder.vhd @@ -51,6 +51,13 @@ -- - This handles FIFO timing issues naturally -- - Never try to time the "first" byte arrival -- +-- VITERBI HANDSHAKE FIX (2025-11-26): Fixed race condition in PREP_FEC_DECODE +-- - decoder_start was only HIGH for 1 clock cycle +-- - If Viterbi was still in COMPLETE state, it missed the pulse +-- - Now holds decoder_start HIGH until decoder_busy='1' +-- - This ensures proper handshake regardless of Viterbi state +-- - Bug only appeared with back-to-back frames (no inter-frame gap) +-- ------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------ @@ -333,13 +340,25 @@ BEGIN END IF; -- PREP_FEC_DECODE: Separate deinterleaved bits into G1 and G2 streams + -- and start the Viterbi decoder with proper handshaking WHEN PREP_FEC_DECODE => + -- Setup G1/G2 streams for Viterbi decoder FOR i IN 0 TO ENCODED_BITS/2 - 1 LOOP decoder_input_g1(i) <= deinterleaved_buffer(i*2); decoder_input_g2(i) <= deinterleaved_buffer(i*2 + 1); END LOOP; + + -- Assert start and WAIT for Viterbi to acknowledge via busy signal + -- FIX: Previously decoder_start was only high for 1 clock cycle. + -- If the Viterbi decoder was still in COMPLETE state (transitioning + -- to IDLE), it would miss the start pulse entirely, causing the + -- frame decoder to wait forever for decoder_done. + -- Now we hold decoder_start high until decoder_busy confirms + -- the Viterbi has accepted the request. decoder_start <= '1'; - state <= FEC_DECODE; + IF decoder_busy = '1' THEN + state <= FEC_DECODE; + END IF; WHEN FEC_DECODE => decoder_start <= '0'; diff --git a/src/viterbi_decoder_k7_simple.vhd b/src/viterbi_decoder_k7_simple.vhd index 9a52bbb..d1a8a82 100644 --- a/src/viterbi_decoder_k7_simple.vhd +++ b/src/viterbi_decoder_k7_simple.vhd @@ -43,8 +43,11 @@ ARCHITECTURE rtl OF viterbi_decoder_k7_simple IS SIGNAL state : state_t := IDLE; TYPE metric_array_t IS ARRAY(0 TO NUM_STATES-1) OF unsigned(METRIC_WIDTH-1 DOWNTO 0); - SIGNAL metrics_current : metric_array_t; - SIGNAL metrics_next : metric_array_t; + -- added initialization to try to get simulation to stop stalling on second frame + SIGNAL metrics_current : metric_array_t := (OTHERS => (OTHERS => '0')); + SIGNAL metrics_next : metric_array_t := (OTHERS => (OTHERS => '0')); + --SIGNAL metrics_current : metric_array_t; + --SIGNAL metrics_next : metric_array_t; --CONSTANT DECISION_DEPTH : INTEGER := NUM_SYMBOLS * NUM_STATES; --TYPE decision_mem_t IS ARRAY(0 TO DECISION_DEPTH-1) OF std_logic; @@ -164,13 +167,16 @@ BEGIN busy <= '0'; done <= '0'; dec_wr_en <= '0'; + time_step <= 0; + state_idx <= 0; + metrics_next <= (OTHERS => (OTHERS => '0')); ELSIF rising_edge(clk) THEN done <= '0'; dec_wr_en <= '0'; CASE state IS - + WHEN IDLE => busy <= '0'; IF start = '1' THEN From 44356f26425e3033648d7e03e42ba19e0fdb7a3c Mon Sep 17 00:00:00 2001 From: Abraxas3d Date: Thu, 27 Nov 2025 16:26:25 -0800 Subject: [PATCH 50/60] Change the encoder to deassert tvalid unconditionally after frame completion. Don't wait for tready. --- src/ov_frame_encoder.vhd | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/src/ov_frame_encoder.vhd b/src/ov_frame_encoder.vhd index b26f49c..0bb4865 100644 --- a/src/ov_frame_encoder.vhd +++ b/src/ov_frame_encoder.vhd @@ -553,19 +553,20 @@ BEGIN END IF; ELSE -- Frame output complete - IF m_axis_tready = '1' THEN - m_axis_tvalid_reg <= '0'; - m_axis_tlast_reg <= '0'; - - -- Pre-set ready for next frame BEFORE going to IDLE - -- This ensures s_axis_tready is already high when we - -- enter IDLE, preventing one-clock delay in handshake - s_axis_tready_reg <= '1'; - - frames_encoded_reg <= frames_encoded_reg + 1; - collect_idx <= 0; - state <= IDLE; - END IF; + -- FIX: Deassert tvalid immediately, don't wait for tready! + -- The last byte's handshake already completed (that's how we got here). + -- Waiting for tready creates a race with the deserializer. + m_axis_tvalid_reg <= '0'; + m_axis_tlast_reg <= '0'; + + -- Pre-set ready for next frame BEFORE going to IDLE + -- This ensures s_axis_tready is already high when we + -- enter IDLE, preventing one-clock delay in handshake + s_axis_tready_reg <= '1'; + + frames_encoded_reg <= frames_encoded_reg + 1; + collect_idx <= 0; + state <= IDLE; END IF; END CASE; From 501c991882773ea04009136b87486f998852cad1 Mon Sep 17 00:00:00 2001 From: Abraxas3d Date: Thu, 27 Nov 2025 16:30:10 -0800 Subject: [PATCH 51/60] Revert "Change the encoder to deassert tvalid unconditionally after frame completion. Don't wait for tready." because it did not work in simulation. This reverts commit 44356f26425e3033648d7e03e42ba19e0fdb7a3c. --- src/ov_frame_encoder.vhd | 27 +++++++++++++-------------- 1 file changed, 13 insertions(+), 14 deletions(-) diff --git a/src/ov_frame_encoder.vhd b/src/ov_frame_encoder.vhd index 0bb4865..b26f49c 100644 --- a/src/ov_frame_encoder.vhd +++ b/src/ov_frame_encoder.vhd @@ -553,20 +553,19 @@ BEGIN END IF; ELSE -- Frame output complete - -- FIX: Deassert tvalid immediately, don't wait for tready! - -- The last byte's handshake already completed (that's how we got here). - -- Waiting for tready creates a race with the deserializer. - m_axis_tvalid_reg <= '0'; - m_axis_tlast_reg <= '0'; - - -- Pre-set ready for next frame BEFORE going to IDLE - -- This ensures s_axis_tready is already high when we - -- enter IDLE, preventing one-clock delay in handshake - s_axis_tready_reg <= '1'; - - frames_encoded_reg <= frames_encoded_reg + 1; - collect_idx <= 0; - state <= IDLE; + IF m_axis_tready = '1' THEN + m_axis_tvalid_reg <= '0'; + m_axis_tlast_reg <= '0'; + + -- Pre-set ready for next frame BEFORE going to IDLE + -- This ensures s_axis_tready is already high when we + -- enter IDLE, preventing one-clock delay in handshake + s_axis_tready_reg <= '1'; + + frames_encoded_reg <= frames_encoded_reg + 1; + collect_idx <= 0; + state <= IDLE; + END IF; END IF; END CASE; From 77336cb046f8b4959c6bcd6eb940a221386f3dd8 Mon Sep 17 00:00:00 2001 From: Abraxas3d Date: Thu, 27 Nov 2025 18:35:05 -0800 Subject: [PATCH 52/60] Prevent Vivado from optimizing away data paths. I think synthesis was tracing through the PRBS mux and determining that the entire TX data path was unused, and then removed the deserializer, the encoder_tdata buses, fifo_tadatoutputs (which gave a no routable loads warning that tipped me off) and tx_data_bit signal. Added do not touch attributes to preserve evertyhing. This may have been the reason we were stalling. --- src/msk_top.vhd | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/msk_top.vhd b/src/msk_top.vhd index cabc9ee..6ffd5cb 100644 --- a/src/msk_top.vhd +++ b/src/msk_top.vhd @@ -328,6 +328,17 @@ ARCHITECTURE struct OF msk_top IS ATTRIBUTE dont_touch : STRING; ATTRIBUTE dont_touch OF u_async_fifo : LABEL IS "true"; ATTRIBUTE dont_touch OF u_rx_async_fifo : LABEL IS "true"; + ATTRIBUTE dont_touch OF u_ov_encoder : LABEL IS "true"; + ATTRIBUTE dont_touch OF u_deserializer : LABEL IS "true"; + ATTRIBUTE dont_touch OF tx_data_bit : SIGNAL IS "true"; + ATTRIBUTE dont_touch OF fifo_tdata : SIGNAL IS "true"; + ATTRIBUTE dont_touch OF fifo_tvalid : SIGNAL IS "true"; + ATTRIBUTE dont_touch OF fifo_tready : SIGNAL IS "true"; + ATTRIBUTE dont_touch OF fifo_tlast : SIGNAL IS "true"; + ATTRIBUTE dont_touch OF encoder_tdata : SIGNAL IS "true"; + ATTRIBUTE dont_touch OF encoder_tvalid : SIGNAL IS "true"; + ATTRIBUTE dont_touch OF encoder_tready : SIGNAL IS "true"; + ATTRIBUTE dont_touch OF encoder_tlast : SIGNAL IS "true"; BEGIN ------------------------------------------------------------------------------------------------------ From e2a45a7f8ec891974f9748323f97a63ca821886f Mon Sep 17 00:00:00 2001 From: Abraxas3d Date: Sun, 30 Nov 2025 23:20:46 -0800 Subject: [PATCH 53/60] transmitter stall resolved. had 134 as loop limit when needed 268. --- src/byte_to_bit_deserializer.vhd | 8 + src/conv_encoder_k7.vhd | 189 ++++++++------- src/msk_top.vhd | 53 ++++- src/msk_top_csr.vhd | 44 +++- src/ov_frame_encoder.vhd | 369 ++++++++++++++++-------------- src/viterbi_decoder_k7_simple.vhd | 82 +++---- 6 files changed, 409 insertions(+), 336 deletions(-) diff --git a/src/byte_to_bit_deserializer.vhd b/src/byte_to_bit_deserializer.vhd index 74cc3f6..a77c208 100644 --- a/src/byte_to_bit_deserializer.vhd +++ b/src/byte_to_bit_deserializer.vhd @@ -48,6 +48,14 @@ ARCHITECTURE rtl OF byte_to_bit_deserializer IS TYPE state_t IS (IDLE, SENDING_SYNC, SHIFTING_DATA); SIGNAL state : state_t; +-- ATTRIBUTE dont_touch : STRING; +-- ATTRIBUTE dont_touch OF state : SIGNAL IS "true"; +-- ATTRIBUTE dont_touch OF ready_int : SIGNAL IS "true"; +-- ATTRIBUTE dont_touch OF last_byte : SIGNAL IS "true"; +-- ATTRIBUTE dont_touch OF shift_reg : SIGNAL IS "true"; +-- ATTRIBUTE dont_touch OF bit_counter : SIGNAL IS "true"; + + BEGIN s_axis_tready <= ready_int; diff --git a/src/conv_encoder_k7.vhd b/src/conv_encoder_k7.vhd index 1cc624a..9c052cf 100644 --- a/src/conv_encoder_k7.vhd +++ b/src/conv_encoder_k7.vhd @@ -1,9 +1,18 @@ ------------------------------------------------------------------------------------------------------ --- K=7 Convolutional Encoder (FIXED - No Signal Timing Bugs) +-- K=7 Convolutional Encoder - Shift Register Version (Corrected Polynomials) ------------------------------------------------------------------------------------------------------ -- Rate 1/2, constraint length K=7 --- Generator polynomials: G1 = 171 octal = 1111001 binary --- G2 = 133 octal = 1011011 binary +-- Generator polynomials: G1 = 171 octal, G2 = 133 octal +-- +-- CRITICAL: The polynomial tap interpretation must match the original! +-- G1_POLY = "1111001" with loop using full_state(6-i) means: +-- G1 = curr_bit XOR sr(3) XOR sr(2) XOR sr(1) XOR sr(0) +-- G2_POLY = "1011011" means: +-- G2 = curr_bit XOR sr(5) XOR sr(3) XOR sr(2) XOR sr(0) +-- +-- RESOURCE OPTIMIZATION: +-- Original version: ~3000 LUTs (variable bit indexing creates massive mux/demux) +-- This version: ~200-400 LUTs (shift registers, fixed-position access only) ------------------------------------------------------------------------------------------------------ LIBRARY ieee; @@ -12,8 +21,8 @@ USE ieee.numeric_std.ALL; ENTITY conv_encoder_k7 IS GENERIC ( - PAYLOAD_BYTES : NATURAL := 134; -- Input size in bytes - ENCODED_BYTES : NATURAL := 268 -- Output size in bytes (2x for rate 1/2) + PAYLOAD_BYTES : NATURAL := 134; + ENCODED_BYTES : NATURAL := 268 ); PORT ( clk : IN std_logic; @@ -30,67 +39,46 @@ END ENTITY conv_encoder_k7; ARCHITECTURE rtl OF conv_encoder_k7 IS - -- TYPE state_t IS (IDLE, ENCODE_DATA, FLUSH_TRELLIS, COMPLETE); - TYPE state_t IS (IDLE, ENCODE_DATA, COMPLETE); + CONSTANT INPUT_BITS : NATURAL := PAYLOAD_BYTES * 8; -- 1072 + CONSTANT OUTPUT_BITS : NATURAL := ENCODED_BYTES * 8; -- 2144 + + TYPE state_t IS (IDLE, ENCODE, COMPLETE); SIGNAL state : state_t := IDLE; - SIGNAL input_bit_count : NATURAL RANGE 0 TO PAYLOAD_BYTES*8; - SIGNAL output_bit_count : NATURAL RANGE 0 TO ENCODED_BYTES*8; + -- Input shift register - shifts MSB out first + SIGNAL in_sr : std_logic_vector(INPUT_BITS-1 DOWNTO 0); - CONSTANT G1_POLY : std_logic_vector(6 DOWNTO 0) := "1111001"; - CONSTANT G2_POLY : std_logic_vector(6 DOWNTO 0) := "1011011"; + -- Output shift register - accumulates encoded bits + SIGNAL out_sr : std_logic_vector(OUTPUT_BITS-1 DOWNTO 0); - SIGNAL out_buf : std_logic_vector(ENCODED_BYTES*8-1 DOWNTO 0); - - ATTRIBUTE ram_style : STRING; - ATTRIBUTE ram_style OF out_buf : SIGNAL IS "block"; + -- Encoder shift register (6 bits of history for K=7) + -- sr(0) = most recent previous bit, sr(5) = oldest + SIGNAL enc_sr : std_logic_vector(5 DOWNTO 0); - -- Function to compute encoder outputs - FUNCTION compute_outputs( - current_bit : std_logic; - shift_reg : std_logic_vector(5 DOWNTO 0) - ) RETURN std_logic_vector IS - VARIABLE full_state : std_logic_vector(6 DOWNTO 0); - VARIABLE g1, g2 : std_logic; - BEGIN - full_state := current_bit & shift_reg; - - -- G1 output - g1 := '0'; - FOR i IN 0 TO 6 LOOP - IF G1_POLY(i) = '1' THEN - g1 := g1 XOR full_state(6-i); - END IF; - END LOOP; - - -- G2 output - g2 := '0'; - FOR i IN 0 TO 6 LOOP - IF G2_POLY(i) = '1' THEN - g2 := g2 XOR full_state(6-i); - END IF; - END LOOP; - - RETURN g1 & g2; -- Return as 2-bit vector - END FUNCTION; + -- Bit counter + SIGNAL bit_count : unsigned(10 DOWNTO 0); -- counts 0 to 1071 + + -- Latched output (stable while not encoding) + SIGNAL out_latched : std_logic_vector(OUTPUT_BITS-1 DOWNTO 0); BEGIN PROCESS(clk, aresetn) - VARIABLE shift_reg : std_logic_vector(5 DOWNTO 0); - VARIABLE current_bit : std_logic; - VARIABLE outputs : std_logic_vector(1 DOWNTO 0); + VARIABLE curr_bit : std_logic; + VARIABLE g1, g2 : std_logic; BEGIN IF aresetn = '0' THEN state <= IDLE; - shift_reg := (OTHERS => '0'); - input_bit_count <= 0; - output_bit_count <= 0; busy <= '0'; done <= '0'; - out_buf <= (OTHERS => '0'); + in_sr <= (OTHERS => '0'); + out_sr <= (OTHERS => '0'); + enc_sr <= (OTHERS => '0'); + bit_count <= (OTHERS => '0'); + out_latched <= (OTHERS => '0'); ELSIF rising_edge(clk) THEN + -- Default: done is single-cycle pulse done <= '0'; CASE state IS @@ -98,57 +86,63 @@ BEGIN WHEN IDLE => busy <= '0'; IF start = '1' THEN - state <= ENCODE_DATA; + -- Parallel load input shift register + in_sr <= input_buffer; + out_sr <= (OTHERS => '0'); + enc_sr <= (OTHERS => '0'); + bit_count <= (OTHERS => '0'); busy <= '1'; - shift_reg := (OTHERS => '0'); - input_bit_count <= 0; - output_bit_count <= 0; + state <= ENCODE; END IF; - WHEN ENCODE_DATA => - -- Process 1,070 bits (stop 2 bits early for tail) - IF input_bit_count < PAYLOAD_BYTES*8 THEN - -- Read input bit (MSB first) - current_bit := input_buffer(PAYLOAD_BYTES*8 - 1 - input_bit_count); - - -- Compute outputs using current state - outputs := compute_outputs(current_bit, shift_reg); - - -- Store outputs (g1 first, then g2) - out_buf(ENCODED_BYTES*8 - 1 - output_bit_count) <= outputs(1); -- g1 - out_buf(ENCODED_BYTES*8 - 2 - output_bit_count) <= outputs(0); -- g2 - - -- Update shift register - shift_reg := shift_reg(4 DOWNTO 0) & current_bit; - - input_bit_count <= input_bit_count + 1; - output_bit_count <= output_bit_count + 2; - ELSE - -- state <= FLUSH_TRELLIS; - -- input_bit_count <= 0; + WHEN ENCODE => + -- Get current input bit from MSB of shift register + curr_bit := in_sr(INPUT_BITS - 1); + + ---------------------------------------------------------------- + -- POLYNOMIAL COMPUTATION - Must match original exactly! + ---------------------------------------------------------------- + -- Original uses: full_state = curr_bit & enc_sr + -- With loop: g1 XOR= full_state(6-i) when G1_POLY(i)='1' + -- + -- G1_POLY = "1111001" (bits 6,5,4,3,0 are '1') + -- i=0: full_state(6) = curr_bit + -- i=3: full_state(3) = enc_sr(3) + -- i=4: full_state(2) = enc_sr(2) + -- i=5: full_state(1) = enc_sr(1) + -- i=6: full_state(0) = enc_sr(0) + -- G1 = curr_bit XOR enc_sr(3) XOR enc_sr(2) XOR enc_sr(1) XOR enc_sr(0) + -- + -- G2_POLY = "1011011" (bits 6,4,3,1,0 are '1') + -- i=0: full_state(6) = curr_bit + -- i=1: full_state(5) = enc_sr(5) + -- i=3: full_state(3) = enc_sr(3) + -- i=4: full_state(2) = enc_sr(2) + -- i=6: full_state(0) = enc_sr(0) + -- G2 = curr_bit XOR enc_sr(5) XOR enc_sr(3) XOR enc_sr(2) XOR enc_sr(0) + ---------------------------------------------------------------- + + g1 := curr_bit XOR enc_sr(3) XOR enc_sr(2) XOR enc_sr(1) XOR enc_sr(0); + g2 := curr_bit XOR enc_sr(5) XOR enc_sr(3) XOR enc_sr(2) XOR enc_sr(0); + + -- Update encoder shift register (shift in current bit at LSB) + enc_sr <= enc_sr(4 DOWNTO 0) & curr_bit; + + -- Shift input register left (next bit moves to MSB position) + in_sr <= in_sr(INPUT_BITS-2 DOWNTO 0) & '0'; + + -- Shift output register left by 2, insert g1 and g2 at LSB + -- g1 goes to higher bit position (matches original out_buf indexing) + out_sr <= out_sr(OUTPUT_BITS-3 DOWNTO 0) & g1 & g2; + + -- Count bits processed + IF bit_count = INPUT_BITS - 1 THEN + -- All bits encoded, latch output + out_latched <= out_sr(OUTPUT_BITS-3 DOWNTO 0) & g1 & g2; state <= COMPLETE; + ELSE + bit_count <= bit_count + 1; END IF; - --- WHEN FLUSH_TRELLIS => --- -- Add 2 tail bits (produces 4 encoded bits) --- IF input_bit_count < 2 THEN --- current_bit := '0'; --- --- -- Compute outputs --- outputs := compute_outputs(current_bit, shift_reg); --- --- -- Store outputs --- out_buf(ENCODED_BYTES*8 - 1 - output_bit_count) <= outputs(1); --- out_buf(ENCODED_BYTES*8 - 2 - output_bit_count) <= outputs(0); --- --- -- Update shift register --- shift_reg := shift_reg(4 DOWNTO 0) & '0'; --- --- input_bit_count <= input_bit_count + 1; --- output_bit_count <= output_bit_count + 2; --- ELSE --- state <= COMPLETE; --- END IF; WHEN COMPLETE => done <= '1'; @@ -159,6 +153,7 @@ BEGIN END IF; END PROCESS; - output_buffer <= out_buf; + -- Output is latched value (stable during next encoding) + output_buffer <= out_latched; END ARCHITECTURE rtl; diff --git a/src/msk_top.vhd b/src/msk_top.vhd index 6ffd5cb..7489f06 100644 --- a/src/msk_top.vhd +++ b/src/msk_top.vhd @@ -190,6 +190,7 @@ ARCHITECTURE struct OF msk_top IS SIGNAL encoder_tlast : std_logic; SIGNAL tx_frames_encoded : std_logic_vector(31 DOWNTO 0); SIGNAL tx_encoder_active : std_logic; + SIGNAL encoder_debug_state : std_logic_vector(2 DOWNTO 0); SIGNAL tx_async_fifo_prog_full : std_logic; SIGNAL tx_async_fifo_prog_empty : std_logic; @@ -330,17 +331,36 @@ ARCHITECTURE struct OF msk_top IS ATTRIBUTE dont_touch OF u_rx_async_fifo : LABEL IS "true"; ATTRIBUTE dont_touch OF u_ov_encoder : LABEL IS "true"; ATTRIBUTE dont_touch OF u_deserializer : LABEL IS "true"; - ATTRIBUTE dont_touch OF tx_data_bit : SIGNAL IS "true"; - ATTRIBUTE dont_touch OF fifo_tdata : SIGNAL IS "true"; - ATTRIBUTE dont_touch OF fifo_tvalid : SIGNAL IS "true"; - ATTRIBUTE dont_touch OF fifo_tready : SIGNAL IS "true"; - ATTRIBUTE dont_touch OF fifo_tlast : SIGNAL IS "true"; - ATTRIBUTE dont_touch OF encoder_tdata : SIGNAL IS "true"; - ATTRIBUTE dont_touch OF encoder_tvalid : SIGNAL IS "true"; - ATTRIBUTE dont_touch OF encoder_tready : SIGNAL IS "true"; - ATTRIBUTE dont_touch OF encoder_tlast : SIGNAL IS "true"; + + --ATTRIBUTE dont_touch OF tx_data_bit : SIGNAL IS "true"; + --ATTRIBUTE dont_touch OF fifo_tdata : SIGNAL IS "true"; + --ATTRIBUTE dont_touch OF fifo_tvalid : SIGNAL IS "true"; + --ATTRIBUTE dont_touch OF fifo_tready : SIGNAL IS "true"; + --ATTRIBUTE dont_touch OF fifo_tlast : SIGNAL IS "true"; + --ATTRIBUTE dont_touch OF encoder_tdata : SIGNAL IS "true"; + --ATTRIBUTE dont_touch OF encoder_tvalid : SIGNAL IS "true"; + --ATTRIBUTE dont_touch OF encoder_tready : SIGNAL IS "true"; + --ATTRIBUTE dont_touch OF encoder_tlast : SIGNAL IS "true"; + + -- RX path protection (add after existing TX dont_touch attributes) + ATTRIBUTE dont_touch OF u_ov_decoder : LABEL IS "true"; + ATTRIBUTE dont_touch OF u_rx_frame_sync : LABEL IS "true"; + + --ATTRIBUTE dont_touch OF decoder_tdata : SIGNAL IS "true"; + --ATTRIBUTE dont_touch OF decoder_tvalid : SIGNAL IS "true"; + --ATTRIBUTE dont_touch OF decoder_tready : SIGNAL IS "true"; + --ATTRIBUTE dont_touch OF decoder_tlast : SIGNAL IS "true"; + --ATTRIBUTE dont_touch OF sync_det_tdata : SIGNAL IS "true"; + --ATTRIBUTE dont_touch OF sync_det_tvalid : SIGNAL IS "true"; + --ATTRIBUTE dont_touch OF sync_det_tready : SIGNAL IS "true"; + --ATTRIBUTE dont_touch OF sync_det_tlast : SIGNAL IS "true"; + + + BEGIN + + ------------------------------------------------------------------------------------------------------ -- OPULENT VOICE TX FIFO CHAIN ------------------------------------------------------------------------------------------------------ @@ -436,7 +456,8 @@ BEGIN -- Status frames_encoded => tx_frames_encoded, - encoder_active => tx_encoder_active + encoder_active => tx_encoder_active, + debug_state => encoder_debug_state ); -- Stage 4: Byte-to-Bit De-serializer (MSB-FIRST VERSION) @@ -960,7 +981,17 @@ BEGIN tx_sync_f1 => tx_sync_f1, tx_sync_f2 => tx_sync_f2, pd_alpha1 => pd_alpha1, - pd_alpha2 => pd_alpha2 + pd_alpha2 => pd_alpha2, + + -- Abraxas3d added these experimental signals for transmitter stall investigation + tx_debug_encoder_tvalid => encoder_tvalid, + tx_debug_encoder_tready => encoder_tready, + tx_debug_fifo_tvalid => fifo_tvalid, + tx_debug_fifo_tready => fifo_tready, + tx_debug_tx_req => tx_req, + tx_debug_encoder_tlast => encoder_tlast, + tx_debug_encoder_state => encoder_debug_state + ); END ARCHITECTURE struct; diff --git a/src/msk_top_csr.vhd b/src/msk_top_csr.vhd index c35f891..b694d23 100644 --- a/src/msk_top_csr.vhd +++ b/src/msk_top_csr.vhd @@ -180,7 +180,18 @@ ENTITY msk_top_csr IS tx_sync_f1 : out std_logic; tx_sync_f2 : out std_logic; pd_alpha1 : out std_logic_vector(17 DOWNTO 0); - pd_alpha2 : out std_logic_vector(17 DOWNTO 0) + pd_alpha2 : out std_logic_vector(17 DOWNTO 0); + + -- Debug signals for TX path + tx_debug_encoder_tvalid : IN std_logic; + tx_debug_encoder_tready : IN std_logic; + tx_debug_fifo_tvalid : IN std_logic; + tx_debug_fifo_tready : IN std_logic; + tx_debug_tx_req : IN std_logic; + tx_debug_encoder_tlast : IN std_logic; + tx_debug_encoder_state : IN std_logic_vector(2 DOWNTO 0) + + ); END ENTITY msk_top_csr; @@ -363,15 +374,28 @@ BEGIN PORT MAP (clk, csr_init, frame_sync_errors_req, rx_frame_sync_err, hwif_in.rx_frame_sync_status.frame_sync_errors.next_q ); -- FIFO status reads - rx_async_fifo_status_req <= hwif_out.rx_async_fifo_rd_wr_ptr.data.swmod; - hwif_in.rx_async_fifo_rd_wr_ptr.data.we <= rx_async_fifo_status_ack; - hwif_in.rx_async_fifo_rd_wr_ptr.data.next_q <= std_logic_vector(resize(unsigned(rx_async_fifo_wr_ptr), 16) & - resize(unsigned(rx_async_fifo_rd_ptr), 16)); - - tx_async_fifo_status_req <= hwif_out.tx_async_fifo_rd_wr_ptr.data.swmod; - hwif_in.tx_async_fifo_rd_wr_ptr.data.we <= tx_async_fifo_status_ack; - hwif_in.tx_async_fifo_rd_wr_ptr.data.next_q <= std_logic_vector(resize(unsigned(tx_async_fifo_wr_ptr), 16) & - resize(unsigned(tx_async_fifo_rd_ptr), 16)); + rx_async_fifo_status_req <= hwif_out.rx_async_fifo_rd_wr_ptr.data.swmod; + hwif_in.rx_async_fifo_rd_wr_ptr.data.we <= rx_async_fifo_status_ack; + hwif_in.rx_async_fifo_rd_wr_ptr.data.next_q <= std_logic_vector(resize(unsigned(rx_async_fifo_wr_ptr), 16) & resize(unsigned(rx_async_fifo_rd_ptr), 16)); + + tx_async_fifo_status_req <= hwif_out.tx_async_fifo_rd_wr_ptr.data.swmod; + hwif_in.tx_async_fifo_rd_wr_ptr.data.we <= tx_async_fifo_status_ack; + -- commented out by Abraxas3d to add more bits to the register in order to investigate transmitter stall + --hwif_in.tx_async_fifo_rd_wr_ptr.data.next_q <= std_logic_vector(resize(unsigned(tx_async_fifo_wr_ptr), 16) & resize(unsigned(tx_async_fifo_rd_ptr), 16)); + +-- experimental register setup by Abraxas3d +hwif_in.tx_async_fifo_rd_wr_ptr.data.next_q <= + tx_debug_encoder_tvalid & -- bit 31 + tx_debug_encoder_tready & -- bit 30 + tx_debug_fifo_tvalid & -- bit 29 + tx_debug_fifo_tready & -- bit 28 + tx_debug_tx_req & -- bit 27 + tx_debug_encoder_tlast & -- bit 26 + tx_debug_encoder_state & -- bits 25:23 + std_logic_vector(resize(unsigned(tx_async_fifo_wr_ptr), 10)) & -- bits 22:13 + "000" & -- bits 12:10 spare + std_logic_vector(resize(unsigned(tx_async_fifo_rd_ptr), 10)); -- bits 9:0 + -- Control from AXI to MDM u01s: cdc_resync PORT MAP (clk, csr_init, hwif_out.MSK_Init.txrxinit.value, txrxinit ); diff --git a/src/ov_frame_encoder.vhd b/src/ov_frame_encoder.vhd index b26f49c..7fa6b28 100644 --- a/src/ov_frame_encoder.vhd +++ b/src/ov_frame_encoder.vhd @@ -26,11 +26,11 @@ -- 5. Pre-set s_axis_tready = '1' before returning to IDLE for next frame -- -- This approach: --- ? Respects AXI-Stream protocol (tlast marks frame boundaries) --- ? Works with continuous data streams (FIFO buffering) --- ? Prevents byte stealing across frame boundaries --- ? Validates frame size for error detection --- ? Works for BOTH bit-level and byte-level interleaving modes +-- Respects AXI-Stream protocol (tlast marks frame boundaries) +-- Works with continuous data streams (FIFO buffering) +-- Prevents byte stealing across frame boundaries +-- Validates frame size for error detection +-- Works for BOTH bit-level and byte-level interleaving modes -- -- NEVER count to a fixed byte number and ignore tlast - this violates AXI-Stream protocol! ------------------------------------------------------------------------------------------------------ @@ -46,7 +46,7 @@ ENTITY ov_frame_encoder IS COLLECT_SIZE : NATURAL := 4; -- DEPRECATED: No longer used (kept for compatibility) ENCODED_BITS : NATURAL := 2144; -- Kept for compatibility BYTE_WIDTH : NATURAL := 8; -- Kept for compatibility - USE_BIT_INTERLEAVER : BOOLEAN := TRUE -- TRUE=bit-level(67x32), FALSE=byte-level(67x4) + USE_BIT_INTERLEAVER : BOOLEAN := FALSE -- TRUE=bit-level(67x32), FALSE=byte-level(67x4) ); PORT ( clk : IN std_logic; @@ -66,7 +66,8 @@ ENTITY ov_frame_encoder IS -- Status outputs frames_encoded : OUT std_logic_vector(31 DOWNTO 0); - encoder_active : OUT std_logic + encoder_active : OUT std_logic; + debug_state : OUT std_logic_vector(2 DOWNTO 0) ); END ENTITY ov_frame_encoder; @@ -141,7 +142,7 @@ ARCHITECTURE rtl OF ov_frame_encoder IS -- Index counters SIGNAL collect_idx : NATURAL RANGE 0 TO PAYLOAD_BYTES; -- Now collects all bytes until tlast - SIGNAL byte_idx : NATURAL RANGE 0 TO PAYLOAD_BYTES; + SIGNAL byte_idx : NATURAL RANGE 0 TO ENCODED_BYTES; SIGNAL bit_idx : NATURAL RANGE 0 TO ENCODED_BITS; SIGNAL out_idx : NATURAL RANGE 0 TO ENCODED_BYTES; @@ -161,147 +162,157 @@ ARCHITECTURE rtl OF ov_frame_encoder IS SIGNAL encoder_done : std_logic; SIGNAL encoder_input_buf : std_logic_vector(1071 DOWNTO 0); SIGNAL encoder_output_buf : std_logic_vector(2143 DOWNTO 0); + + -- preserve the output registers from synthesis optimization + ATTRIBUTE dont_touch : STRING; + ATTRIBUTE dont_touch OF m_axis_tvalid_reg : SIGNAL IS "true"; + ATTRIBUTE dont_touch OF m_axis_tdata_reg : SIGNAL IS "true"; + ATTRIBUTE dont_touch OF m_axis_tlast_reg : SIGNAL IS "true"; + --ATTRIBUTE dont_touch OF interleaved_buffer : SIGNAL IS "true"; + --ATTRIBUTE dont_touch OF out_idx : SIGNAL IS "true"; + ATTRIBUTE dont_touch OF s_axis_tready_reg : SIGNAL IS "true"; + ---------------------------------------------------------------------------- -- BIT-LEVEL INTERLEAVER (67x32) - For large FPGAs, correct protocol ---------------------------------------------------------------------------- - TYPE address_lut_t IS ARRAY(0 TO 2143) OF NATURAL RANGE 0 TO 2143; - CONSTANT INTERLEAVE_LUT_BIT : address_lut_t := ( - 0, 67, 134, 201, 268, 335, 402, 469, 536, 603, 670, 737, 804, 871, 938, 1005, - 1072, 1139, 1206, 1273, 1340, 1407, 1474, 1541, 1608, 1675, 1742, 1809, 1876, 1943, 2010, 2077, - 1, 68, 135, 202, 269, 336, 403, 470, 537, 604, 671, 738, 805, 872, 939, 1006, - 1073, 1140, 1207, 1274, 1341, 1408, 1475, 1542, 1609, 1676, 1743, 1810, 1877, 1944, 2011, 2078, - 2, 69, 136, 203, 270, 337, 404, 471, 538, 605, 672, 739, 806, 873, 940, 1007, - 1074, 1141, 1208, 1275, 1342, 1409, 1476, 1543, 1610, 1677, 1744, 1811, 1878, 1945, 2012, 2079, - 3, 70, 137, 204, 271, 338, 405, 472, 539, 606, 673, 740, 807, 874, 941, 1008, - 1075, 1142, 1209, 1276, 1343, 1410, 1477, 1544, 1611, 1678, 1745, 1812, 1879, 1946, 2013, 2080, - 4, 71, 138, 205, 272, 339, 406, 473, 540, 607, 674, 741, 808, 875, 942, 1009, - 1076, 1143, 1210, 1277, 1344, 1411, 1478, 1545, 1612, 1679, 1746, 1813, 1880, 1947, 2014, 2081, - 5, 72, 139, 206, 273, 340, 407, 474, 541, 608, 675, 742, 809, 876, 943, 1010, - 1077, 1144, 1211, 1278, 1345, 1412, 1479, 1546, 1613, 1680, 1747, 1814, 1881, 1948, 2015, 2082, - 6, 73, 140, 207, 274, 341, 408, 475, 542, 609, 676, 743, 810, 877, 944, 1011, - 1078, 1145, 1212, 1279, 1346, 1413, 1480, 1547, 1614, 1681, 1748, 1815, 1882, 1949, 2016, 2083, - 7, 74, 141, 208, 275, 342, 409, 476, 543, 610, 677, 744, 811, 878, 945, 1012, - 1079, 1146, 1213, 1280, 1347, 1414, 1481, 1548, 1615, 1682, 1749, 1816, 1883, 1950, 2017, 2084, - 8, 75, 142, 209, 276, 343, 410, 477, 544, 611, 678, 745, 812, 879, 946, 1013, - 1080, 1147, 1214, 1281, 1348, 1415, 1482, 1549, 1616, 1683, 1750, 1817, 1884, 1951, 2018, 2085, - 9, 76, 143, 210, 277, 344, 411, 478, 545, 612, 679, 746, 813, 880, 947, 1014, - 1081, 1148, 1215, 1282, 1349, 1416, 1483, 1550, 1617, 1684, 1751, 1818, 1885, 1952, 2019, 2086, - 10, 77, 144, 211, 278, 345, 412, 479, 546, 613, 680, 747, 814, 881, 948, 1015, - 1082, 1149, 1216, 1283, 1350, 1417, 1484, 1551, 1618, 1685, 1752, 1819, 1886, 1953, 2020, 2087, - 11, 78, 145, 212, 279, 346, 413, 480, 547, 614, 681, 748, 815, 882, 949, 1016, - 1083, 1150, 1217, 1284, 1351, 1418, 1485, 1552, 1619, 1686, 1753, 1820, 1887, 1954, 2021, 2088, - 12, 79, 146, 213, 280, 347, 414, 481, 548, 615, 682, 749, 816, 883, 950, 1017, - 1084, 1151, 1218, 1285, 1352, 1419, 1486, 1553, 1620, 1687, 1754, 1821, 1888, 1955, 2022, 2089, - 13, 80, 147, 214, 281, 348, 415, 482, 549, 616, 683, 750, 817, 884, 951, 1018, - 1085, 1152, 1219, 1286, 1353, 1420, 1487, 1554, 1621, 1688, 1755, 1822, 1889, 1956, 2023, 2090, - 14, 81, 148, 215, 282, 349, 416, 483, 550, 617, 684, 751, 818, 885, 952, 1019, - 1086, 1153, 1220, 1287, 1354, 1421, 1488, 1555, 1622, 1689, 1756, 1823, 1890, 1957, 2024, 2091, - 15, 82, 149, 216, 283, 350, 417, 484, 551, 618, 685, 752, 819, 886, 953, 1020, - 1087, 1154, 1221, 1288, 1355, 1422, 1489, 1556, 1623, 1690, 1757, 1824, 1891, 1958, 2025, 2092, - 16, 83, 150, 217, 284, 351, 418, 485, 552, 619, 686, 753, 820, 887, 954, 1021, - 1088, 1155, 1222, 1289, 1356, 1423, 1490, 1557, 1624, 1691, 1758, 1825, 1892, 1959, 2026, 2093, - 17, 84, 151, 218, 285, 352, 419, 486, 553, 620, 687, 754, 821, 888, 955, 1022, - 1089, 1156, 1223, 1290, 1357, 1424, 1491, 1558, 1625, 1692, 1759, 1826, 1893, 1960, 2027, 2094, - 18, 85, 152, 219, 286, 353, 420, 487, 554, 621, 688, 755, 822, 889, 956, 1023, - 1090, 1157, 1224, 1291, 1358, 1425, 1492, 1559, 1626, 1693, 1760, 1827, 1894, 1961, 2028, 2095, - 19, 86, 153, 220, 287, 354, 421, 488, 555, 622, 689, 756, 823, 890, 957, 1024, - 1091, 1158, 1225, 1292, 1359, 1426, 1493, 1560, 1627, 1694, 1761, 1828, 1895, 1962, 2029, 2096, - 20, 87, 154, 221, 288, 355, 422, 489, 556, 623, 690, 757, 824, 891, 958, 1025, - 1092, 1159, 1226, 1293, 1360, 1427, 1494, 1561, 1628, 1695, 1762, 1829, 1896, 1963, 2030, 2097, - 21, 88, 155, 222, 289, 356, 423, 490, 557, 624, 691, 758, 825, 892, 959, 1026, - 1093, 1160, 1227, 1294, 1361, 1428, 1495, 1562, 1629, 1696, 1763, 1830, 1897, 1964, 2031, 2098, - 22, 89, 156, 223, 290, 357, 424, 491, 558, 625, 692, 759, 826, 893, 960, 1027, - 1094, 1161, 1228, 1295, 1362, 1429, 1496, 1563, 1630, 1697, 1764, 1831, 1898, 1965, 2032, 2099, - 23, 90, 157, 224, 291, 358, 425, 492, 559, 626, 693, 760, 827, 894, 961, 1028, - 1095, 1162, 1229, 1296, 1363, 1430, 1497, 1564, 1631, 1698, 1765, 1832, 1899, 1966, 2033, 2100, - 24, 91, 158, 225, 292, 359, 426, 493, 560, 627, 694, 761, 828, 895, 962, 1029, - 1096, 1163, 1230, 1297, 1364, 1431, 1498, 1565, 1632, 1699, 1766, 1833, 1900, 1967, 2034, 2101, - 25, 92, 159, 226, 293, 360, 427, 494, 561, 628, 695, 762, 829, 896, 963, 1030, - 1097, 1164, 1231, 1298, 1365, 1432, 1499, 1566, 1633, 1700, 1767, 1834, 1901, 1968, 2035, 2102, - 26, 93, 160, 227, 294, 361, 428, 495, 562, 629, 696, 763, 830, 897, 964, 1031, - 1098, 1165, 1232, 1299, 1366, 1433, 1500, 1567, 1634, 1701, 1768, 1835, 1902, 1969, 2036, 2103, - 27, 94, 161, 228, 295, 362, 429, 496, 563, 630, 697, 764, 831, 898, 965, 1032, - 1099, 1166, 1233, 1300, 1367, 1434, 1501, 1568, 1635, 1702, 1769, 1836, 1903, 1970, 2037, 2104, - 28, 95, 162, 229, 296, 363, 430, 497, 564, 631, 698, 765, 832, 899, 966, 1033, - 1100, 1167, 1234, 1301, 1368, 1435, 1502, 1569, 1636, 1703, 1770, 1837, 1904, 1971, 2038, 2105, - 29, 96, 163, 230, 297, 364, 431, 498, 565, 632, 699, 766, 833, 900, 967, 1034, - 1101, 1168, 1235, 1302, 1369, 1436, 1503, 1570, 1637, 1704, 1771, 1838, 1905, 1972, 2039, 2106, - 30, 97, 164, 231, 298, 365, 432, 499, 566, 633, 700, 767, 834, 901, 968, 1035, - 1102, 1169, 1236, 1303, 1370, 1437, 1504, 1571, 1638, 1705, 1772, 1839, 1906, 1973, 2040, 2107, - 31, 98, 165, 232, 299, 366, 433, 500, 567, 634, 701, 768, 835, 902, 969, 1036, - 1103, 1170, 1237, 1304, 1371, 1438, 1505, 1572, 1639, 1706, 1773, 1840, 1907, 1974, 2041, 2108, - 32, 99, 166, 233, 300, 367, 434, 501, 568, 635, 702, 769, 836, 903, 970, 1037, - 1104, 1171, 1238, 1305, 1372, 1439, 1506, 1573, 1640, 1707, 1774, 1841, 1908, 1975, 2042, 2109, - 33, 100, 167, 234, 301, 368, 435, 502, 569, 636, 703, 770, 837, 904, 971, 1038, - 1105, 1172, 1239, 1306, 1373, 1440, 1507, 1574, 1641, 1708, 1775, 1842, 1909, 1976, 2043, 2110, - 34, 101, 168, 235, 302, 369, 436, 503, 570, 637, 704, 771, 838, 905, 972, 1039, - 1106, 1173, 1240, 1307, 1374, 1441, 1508, 1575, 1642, 1709, 1776, 1843, 1910, 1977, 2044, 2111, - 35, 102, 169, 236, 303, 370, 437, 504, 571, 638, 705, 772, 839, 906, 973, 1040, - 1107, 1174, 1241, 1308, 1375, 1442, 1509, 1576, 1643, 1710, 1777, 1844, 1911, 1978, 2045, 2112, - 36, 103, 170, 237, 304, 371, 438, 505, 572, 639, 706, 773, 840, 907, 974, 1041, - 1108, 1175, 1242, 1309, 1376, 1443, 1510, 1577, 1644, 1711, 1778, 1845, 1912, 1979, 2046, 2113, - 37, 104, 171, 238, 305, 372, 439, 506, 573, 640, 707, 774, 841, 908, 975, 1042, - 1109, 1176, 1243, 1310, 1377, 1444, 1511, 1578, 1645, 1712, 1779, 1846, 1913, 1980, 2047, 2114, - 38, 105, 172, 239, 306, 373, 440, 507, 574, 641, 708, 775, 842, 909, 976, 1043, - 1110, 1177, 1244, 1311, 1378, 1445, 1512, 1579, 1646, 1713, 1780, 1847, 1914, 1981, 2048, 2115, - 39, 106, 173, 240, 307, 374, 441, 508, 575, 642, 709, 776, 843, 910, 977, 1044, - 1111, 1178, 1245, 1312, 1379, 1446, 1513, 1580, 1647, 1714, 1781, 1848, 1915, 1982, 2049, 2116, - 40, 107, 174, 241, 308, 375, 442, 509, 576, 643, 710, 777, 844, 911, 978, 1045, - 1112, 1179, 1246, 1313, 1380, 1447, 1514, 1581, 1648, 1715, 1782, 1849, 1916, 1983, 2050, 2117, - 41, 108, 175, 242, 309, 376, 443, 510, 577, 644, 711, 778, 845, 912, 979, 1046, - 1113, 1180, 1247, 1314, 1381, 1448, 1515, 1582, 1649, 1716, 1783, 1850, 1917, 1984, 2051, 2118, - 42, 109, 176, 243, 310, 377, 444, 511, 578, 645, 712, 779, 846, 913, 980, 1047, - 1114, 1181, 1248, 1315, 1382, 1449, 1516, 1583, 1650, 1717, 1784, 1851, 1918, 1985, 2052, 2119, - 43, 110, 177, 244, 311, 378, 445, 512, 579, 646, 713, 780, 847, 914, 981, 1048, - 1115, 1182, 1249, 1316, 1383, 1450, 1517, 1584, 1651, 1718, 1785, 1852, 1919, 1986, 2053, 2120, - 44, 111, 178, 245, 312, 379, 446, 513, 580, 647, 714, 781, 848, 915, 982, 1049, - 1116, 1183, 1250, 1317, 1384, 1451, 1518, 1585, 1652, 1719, 1786, 1853, 1920, 1987, 2054, 2121, - 45, 112, 179, 246, 313, 380, 447, 514, 581, 648, 715, 782, 849, 916, 983, 1050, - 1117, 1184, 1251, 1318, 1385, 1452, 1519, 1586, 1653, 1720, 1787, 1854, 1921, 1988, 2055, 2122, - 46, 113, 180, 247, 314, 381, 448, 515, 582, 649, 716, 783, 850, 917, 984, 1051, - 1118, 1185, 1252, 1319, 1386, 1453, 1520, 1587, 1654, 1721, 1788, 1855, 1922, 1989, 2056, 2123, - 47, 114, 181, 248, 315, 382, 449, 516, 583, 650, 717, 784, 851, 918, 985, 1052, - 1119, 1186, 1253, 1320, 1387, 1454, 1521, 1588, 1655, 1722, 1789, 1856, 1923, 1990, 2057, 2124, - 48, 115, 182, 249, 316, 383, 450, 517, 584, 651, 718, 785, 852, 919, 986, 1053, - 1120, 1187, 1254, 1321, 1388, 1455, 1522, 1589, 1656, 1723, 1790, 1857, 1924, 1991, 2058, 2125, - 49, 116, 183, 250, 317, 384, 451, 518, 585, 652, 719, 786, 853, 920, 987, 1054, - 1121, 1188, 1255, 1322, 1389, 1456, 1523, 1590, 1657, 1724, 1791, 1858, 1925, 1992, 2059, 2126, - 50, 117, 184, 251, 318, 385, 452, 519, 586, 653, 720, 787, 854, 921, 988, 1055, - 1122, 1189, 1256, 1323, 1390, 1457, 1524, 1591, 1658, 1725, 1792, 1859, 1926, 1993, 2060, 2127, - 51, 118, 185, 252, 319, 386, 453, 520, 587, 654, 721, 788, 855, 922, 989, 1056, - 1123, 1190, 1257, 1324, 1391, 1458, 1525, 1592, 1659, 1726, 1793, 1860, 1927, 1994, 2061, 2128, - 52, 119, 186, 253, 320, 387, 454, 521, 588, 655, 722, 789, 856, 923, 990, 1057, - 1124, 1191, 1258, 1325, 1392, 1459, 1526, 1593, 1660, 1727, 1794, 1861, 1928, 1995, 2062, 2129, - 53, 120, 187, 254, 321, 388, 455, 522, 589, 656, 723, 790, 857, 924, 991, 1058, - 1125, 1192, 1259, 1326, 1393, 1460, 1527, 1594, 1661, 1728, 1795, 1862, 1929, 1996, 2063, 2130, - 54, 121, 188, 255, 322, 389, 456, 523, 590, 657, 724, 791, 858, 925, 992, 1059, - 1126, 1193, 1260, 1327, 1394, 1461, 1528, 1595, 1662, 1729, 1796, 1863, 1930, 1997, 2064, 2131, - 55, 122, 189, 256, 323, 390, 457, 524, 591, 658, 725, 792, 859, 926, 993, 1060, - 1127, 1194, 1261, 1328, 1395, 1462, 1529, 1596, 1663, 1730, 1797, 1864, 1931, 1998, 2065, 2132, - 56, 123, 190, 257, 324, 391, 458, 525, 592, 659, 726, 793, 860, 927, 994, 1061, - 1128, 1195, 1262, 1329, 1396, 1463, 1530, 1597, 1664, 1731, 1798, 1865, 1932, 1999, 2066, 2133, - 57, 124, 191, 258, 325, 392, 459, 526, 593, 660, 727, 794, 861, 928, 995, 1062, - 1129, 1196, 1263, 1330, 1397, 1464, 1531, 1598, 1665, 1732, 1799, 1866, 1933, 2000, 2067, 2134, - 58, 125, 192, 259, 326, 393, 460, 527, 594, 661, 728, 795, 862, 929, 996, 1063, - 1130, 1197, 1264, 1331, 1398, 1465, 1532, 1599, 1666, 1733, 1800, 1867, 1934, 2001, 2068, 2135, - 59, 126, 193, 260, 327, 394, 461, 528, 595, 662, 729, 796, 863, 930, 997, 1064, - 1131, 1198, 1265, 1332, 1399, 1466, 1533, 1600, 1667, 1734, 1801, 1868, 1935, 2002, 2069, 2136, - 60, 127, 194, 261, 328, 395, 462, 529, 596, 663, 730, 797, 864, 931, 998, 1065, - 1132, 1199, 1266, 1333, 1400, 1467, 1534, 1601, 1668, 1735, 1802, 1869, 1936, 2003, 2070, 2137, - 61, 128, 195, 262, 329, 396, 463, 530, 597, 664, 731, 798, 865, 932, 999, 1066, - 1133, 1200, 1267, 1334, 1401, 1468, 1535, 1602, 1669, 1736, 1803, 1870, 1937, 2004, 2071, 2138, - 62, 129, 196, 263, 330, 397, 464, 531, 598, 665, 732, 799, 866, 933, 1000, 1067, - 1134, 1201, 1268, 1335, 1402, 1469, 1536, 1603, 1670, 1737, 1804, 1871, 1938, 2005, 2072, 2139, - 63, 130, 197, 264, 331, 398, 465, 532, 599, 666, 733, 800, 867, 934, 1001, 1068, - 1135, 1202, 1269, 1336, 1403, 1470, 1537, 1604, 1671, 1738, 1805, 1872, 1939, 2006, 2073, 2140, - 64, 131, 198, 265, 332, 399, 466, 533, 600, 667, 734, 801, 868, 935, 1002, 1069, - 1136, 1203, 1270, 1337, 1404, 1471, 1538, 1605, 1672, 1739, 1806, 1873, 1940, 2007, 2074, 2141, - 65, 132, 199, 266, 333, 400, 467, 534, 601, 668, 735, 802, 869, 936, 1003, 1070, - 1137, 1204, 1271, 1338, 1405, 1472, 1539, 1606, 1673, 1740, 1807, 1874, 1941, 2008, 2075, 2142, - 66, 133, 200, 267, 334, 401, 468, 535, 602, 669, 736, 803, 870, 937, 1004, 1071, - 1138, 1205, 1272, 1339, 1406, 1473, 1540, 1607, 1674, 1741, 1808, 1875, 1942, 2009, 2076, 2143 - ); +-- TYPE address_lut_t IS ARRAY(0 TO 2143) OF NATURAL RANGE 0 TO 2143; +-- CONSTANT INTERLEAVE_LUT_BIT : address_lut_t := ( +-- 0, 67, 134, 201, 268, 335, 402, 469, 536, 603, 670, 737, 804, 871, 938, 1005, +-- 1072, 1139, 1206, 1273, 1340, 1407, 1474, 1541, 1608, 1675, 1742, 1809, 1876, 1943, 2010, 2077, +-- 1, 68, 135, 202, 269, 336, 403, 470, 537, 604, 671, 738, 805, 872, 939, 1006, +-- 1073, 1140, 1207, 1274, 1341, 1408, 1475, 1542, 1609, 1676, 1743, 1810, 1877, 1944, 2011, 2078, +-- 2, 69, 136, 203, 270, 337, 404, 471, 538, 605, 672, 739, 806, 873, 940, 1007, +-- 1074, 1141, 1208, 1275, 1342, 1409, 1476, 1543, 1610, 1677, 1744, 1811, 1878, 1945, 2012, 2079, +-- 3, 70, 137, 204, 271, 338, 405, 472, 539, 606, 673, 740, 807, 874, 941, 1008, +-- 1075, 1142, 1209, 1276, 1343, 1410, 1477, 1544, 1611, 1678, 1745, 1812, 1879, 1946, 2013, 2080, +-- 4, 71, 138, 205, 272, 339, 406, 473, 540, 607, 674, 741, 808, 875, 942, 1009, +-- 1076, 1143, 1210, 1277, 1344, 1411, 1478, 1545, 1612, 1679, 1746, 1813, 1880, 1947, 2014, 2081, +-- 5, 72, 139, 206, 273, 340, 407, 474, 541, 608, 675, 742, 809, 876, 943, 1010, +-- 1077, 1144, 1211, 1278, 1345, 1412, 1479, 1546, 1613, 1680, 1747, 1814, 1881, 1948, 2015, 2082, +-- 6, 73, 140, 207, 274, 341, 408, 475, 542, 609, 676, 743, 810, 877, 944, 1011, +-- 1078, 1145, 1212, 1279, 1346, 1413, 1480, 1547, 1614, 1681, 1748, 1815, 1882, 1949, 2016, 2083, +-- 7, 74, 141, 208, 275, 342, 409, 476, 543, 610, 677, 744, 811, 878, 945, 1012, +-- 1079, 1146, 1213, 1280, 1347, 1414, 1481, 1548, 1615, 1682, 1749, 1816, 1883, 1950, 2017, 2084, +-- 8, 75, 142, 209, 276, 343, 410, 477, 544, 611, 678, 745, 812, 879, 946, 1013, +-- 1080, 1147, 1214, 1281, 1348, 1415, 1482, 1549, 1616, 1683, 1750, 1817, 1884, 1951, 2018, 2085, +-- 9, 76, 143, 210, 277, 344, 411, 478, 545, 612, 679, 746, 813, 880, 947, 1014, +-- 1081, 1148, 1215, 1282, 1349, 1416, 1483, 1550, 1617, 1684, 1751, 1818, 1885, 1952, 2019, 2086, +-- 10, 77, 144, 211, 278, 345, 412, 479, 546, 613, 680, 747, 814, 881, 948, 1015, +-- 1082, 1149, 1216, 1283, 1350, 1417, 1484, 1551, 1618, 1685, 1752, 1819, 1886, 1953, 2020, 2087, +-- 11, 78, 145, 212, 279, 346, 413, 480, 547, 614, 681, 748, 815, 882, 949, 1016, +-- 1083, 1150, 1217, 1284, 1351, 1418, 1485, 1552, 1619, 1686, 1753, 1820, 1887, 1954, 2021, 2088, +-- 12, 79, 146, 213, 280, 347, 414, 481, 548, 615, 682, 749, 816, 883, 950, 1017, +-- 1084, 1151, 1218, 1285, 1352, 1419, 1486, 1553, 1620, 1687, 1754, 1821, 1888, 1955, 2022, 2089, +-- 13, 80, 147, 214, 281, 348, 415, 482, 549, 616, 683, 750, 817, 884, 951, 1018, +-- 1085, 1152, 1219, 1286, 1353, 1420, 1487, 1554, 1621, 1688, 1755, 1822, 1889, 1956, 2023, 2090, +-- 14, 81, 148, 215, 282, 349, 416, 483, 550, 617, 684, 751, 818, 885, 952, 1019, +-- 1086, 1153, 1220, 1287, 1354, 1421, 1488, 1555, 1622, 1689, 1756, 1823, 1890, 1957, 2024, 2091, +-- 15, 82, 149, 216, 283, 350, 417, 484, 551, 618, 685, 752, 819, 886, 953, 1020, +-- 1087, 1154, 1221, 1288, 1355, 1422, 1489, 1556, 1623, 1690, 1757, 1824, 1891, 1958, 2025, 2092, +-- 16, 83, 150, 217, 284, 351, 418, 485, 552, 619, 686, 753, 820, 887, 954, 1021, +-- 1088, 1155, 1222, 1289, 1356, 1423, 1490, 1557, 1624, 1691, 1758, 1825, 1892, 1959, 2026, 2093, +-- 17, 84, 151, 218, 285, 352, 419, 486, 553, 620, 687, 754, 821, 888, 955, 1022, +-- 1089, 1156, 1223, 1290, 1357, 1424, 1491, 1558, 1625, 1692, 1759, 1826, 1893, 1960, 2027, 2094, +-- 18, 85, 152, 219, 286, 353, 420, 487, 554, 621, 688, 755, 822, 889, 956, 1023, +-- 1090, 1157, 1224, 1291, 1358, 1425, 1492, 1559, 1626, 1693, 1760, 1827, 1894, 1961, 2028, 2095, +-- 19, 86, 153, 220, 287, 354, 421, 488, 555, 622, 689, 756, 823, 890, 957, 1024, +-- 1091, 1158, 1225, 1292, 1359, 1426, 1493, 1560, 1627, 1694, 1761, 1828, 1895, 1962, 2029, 2096, +-- 20, 87, 154, 221, 288, 355, 422, 489, 556, 623, 690, 757, 824, 891, 958, 1025, +-- 1092, 1159, 1226, 1293, 1360, 1427, 1494, 1561, 1628, 1695, 1762, 1829, 1896, 1963, 2030, 2097, +-- 21, 88, 155, 222, 289, 356, 423, 490, 557, 624, 691, 758, 825, 892, 959, 1026, +-- 1093, 1160, 1227, 1294, 1361, 1428, 1495, 1562, 1629, 1696, 1763, 1830, 1897, 1964, 2031, 2098, +-- 22, 89, 156, 223, 290, 357, 424, 491, 558, 625, 692, 759, 826, 893, 960, 1027, +-- 1094, 1161, 1228, 1295, 1362, 1429, 1496, 1563, 1630, 1697, 1764, 1831, 1898, 1965, 2032, 2099, +-- 23, 90, 157, 224, 291, 358, 425, 492, 559, 626, 693, 760, 827, 894, 961, 1028, +-- 1095, 1162, 1229, 1296, 1363, 1430, 1497, 1564, 1631, 1698, 1765, 1832, 1899, 1966, 2033, 2100, +-- 24, 91, 158, 225, 292, 359, 426, 493, 560, 627, 694, 761, 828, 895, 962, 1029, +-- 1096, 1163, 1230, 1297, 1364, 1431, 1498, 1565, 1632, 1699, 1766, 1833, 1900, 1967, 2034, 2101, +-- 25, 92, 159, 226, 293, 360, 427, 494, 561, 628, 695, 762, 829, 896, 963, 1030, +-- 1097, 1164, 1231, 1298, 1365, 1432, 1499, 1566, 1633, 1700, 1767, 1834, 1901, 1968, 2035, 2102, +-- 26, 93, 160, 227, 294, 361, 428, 495, 562, 629, 696, 763, 830, 897, 964, 1031, +-- 1098, 1165, 1232, 1299, 1366, 1433, 1500, 1567, 1634, 1701, 1768, 1835, 1902, 1969, 2036, 2103, +-- 27, 94, 161, 228, 295, 362, 429, 496, 563, 630, 697, 764, 831, 898, 965, 1032, +-- 1099, 1166, 1233, 1300, 1367, 1434, 1501, 1568, 1635, 1702, 1769, 1836, 1903, 1970, 2037, 2104, +-- 28, 95, 162, 229, 296, 363, 430, 497, 564, 631, 698, 765, 832, 899, 966, 1033, +-- 1100, 1167, 1234, 1301, 1368, 1435, 1502, 1569, 1636, 1703, 1770, 1837, 1904, 1971, 2038, 2105, +-- 29, 96, 163, 230, 297, 364, 431, 498, 565, 632, 699, 766, 833, 900, 967, 1034, +-- 1101, 1168, 1235, 1302, 1369, 1436, 1503, 1570, 1637, 1704, 1771, 1838, 1905, 1972, 2039, 2106, +-- 30, 97, 164, 231, 298, 365, 432, 499, 566, 633, 700, 767, 834, 901, 968, 1035, +-- 1102, 1169, 1236, 1303, 1370, 1437, 1504, 1571, 1638, 1705, 1772, 1839, 1906, 1973, 2040, 2107, +-- 31, 98, 165, 232, 299, 366, 433, 500, 567, 634, 701, 768, 835, 902, 969, 1036, +-- 1103, 1170, 1237, 1304, 1371, 1438, 1505, 1572, 1639, 1706, 1773, 1840, 1907, 1974, 2041, 2108, +-- 32, 99, 166, 233, 300, 367, 434, 501, 568, 635, 702, 769, 836, 903, 970, 1037, +-- 1104, 1171, 1238, 1305, 1372, 1439, 1506, 1573, 1640, 1707, 1774, 1841, 1908, 1975, 2042, 2109, +-- 33, 100, 167, 234, 301, 368, 435, 502, 569, 636, 703, 770, 837, 904, 971, 1038, +-- 1105, 1172, 1239, 1306, 1373, 1440, 1507, 1574, 1641, 1708, 1775, 1842, 1909, 1976, 2043, 2110, +-- 34, 101, 168, 235, 302, 369, 436, 503, 570, 637, 704, 771, 838, 905, 972, 1039, +-- 1106, 1173, 1240, 1307, 1374, 1441, 1508, 1575, 1642, 1709, 1776, 1843, 1910, 1977, 2044, 2111, +-- 35, 102, 169, 236, 303, 370, 437, 504, 571, 638, 705, 772, 839, 906, 973, 1040, +-- 1107, 1174, 1241, 1308, 1375, 1442, 1509, 1576, 1643, 1710, 1777, 1844, 1911, 1978, 2045, 2112, +-- 36, 103, 170, 237, 304, 371, 438, 505, 572, 639, 706, 773, 840, 907, 974, 1041, +-- 1108, 1175, 1242, 1309, 1376, 1443, 1510, 1577, 1644, 1711, 1778, 1845, 1912, 1979, 2046, 2113, +-- 37, 104, 171, 238, 305, 372, 439, 506, 573, 640, 707, 774, 841, 908, 975, 1042, +-- 1109, 1176, 1243, 1310, 1377, 1444, 1511, 1578, 1645, 1712, 1779, 1846, 1913, 1980, 2047, 2114, +-- 38, 105, 172, 239, 306, 373, 440, 507, 574, 641, 708, 775, 842, 909, 976, 1043, +-- 1110, 1177, 1244, 1311, 1378, 1445, 1512, 1579, 1646, 1713, 1780, 1847, 1914, 1981, 2048, 2115, +-- 39, 106, 173, 240, 307, 374, 441, 508, 575, 642, 709, 776, 843, 910, 977, 1044, +-- 1111, 1178, 1245, 1312, 1379, 1446, 1513, 1580, 1647, 1714, 1781, 1848, 1915, 1982, 2049, 2116, +-- 40, 107, 174, 241, 308, 375, 442, 509, 576, 643, 710, 777, 844, 911, 978, 1045, +-- 1112, 1179, 1246, 1313, 1380, 1447, 1514, 1581, 1648, 1715, 1782, 1849, 1916, 1983, 2050, 2117, +-- 41, 108, 175, 242, 309, 376, 443, 510, 577, 644, 711, 778, 845, 912, 979, 1046, +-- 1113, 1180, 1247, 1314, 1381, 1448, 1515, 1582, 1649, 1716, 1783, 1850, 1917, 1984, 2051, 2118, +-- 42, 109, 176, 243, 310, 377, 444, 511, 578, 645, 712, 779, 846, 913, 980, 1047, +-- 1114, 1181, 1248, 1315, 1382, 1449, 1516, 1583, 1650, 1717, 1784, 1851, 1918, 1985, 2052, 2119, +-- 43, 110, 177, 244, 311, 378, 445, 512, 579, 646, 713, 780, 847, 914, 981, 1048, +-- 1115, 1182, 1249, 1316, 1383, 1450, 1517, 1584, 1651, 1718, 1785, 1852, 1919, 1986, 2053, 2120, +-- 44, 111, 178, 245, 312, 379, 446, 513, 580, 647, 714, 781, 848, 915, 982, 1049, +-- 1116, 1183, 1250, 1317, 1384, 1451, 1518, 1585, 1652, 1719, 1786, 1853, 1920, 1987, 2054, 2121, +-- 45, 112, 179, 246, 313, 380, 447, 514, 581, 648, 715, 782, 849, 916, 983, 1050, +-- 1117, 1184, 1251, 1318, 1385, 1452, 1519, 1586, 1653, 1720, 1787, 1854, 1921, 1988, 2055, 2122, +-- 46, 113, 180, 247, 314, 381, 448, 515, 582, 649, 716, 783, 850, 917, 984, 1051, +-- 1118, 1185, 1252, 1319, 1386, 1453, 1520, 1587, 1654, 1721, 1788, 1855, 1922, 1989, 2056, 2123, +-- 47, 114, 181, 248, 315, 382, 449, 516, 583, 650, 717, 784, 851, 918, 985, 1052, +-- 1119, 1186, 1253, 1320, 1387, 1454, 1521, 1588, 1655, 1722, 1789, 1856, 1923, 1990, 2057, 2124, +-- 48, 115, 182, 249, 316, 383, 450, 517, 584, 651, 718, 785, 852, 919, 986, 1053, +-- 1120, 1187, 1254, 1321, 1388, 1455, 1522, 1589, 1656, 1723, 1790, 1857, 1924, 1991, 2058, 2125, +-- 49, 116, 183, 250, 317, 384, 451, 518, 585, 652, 719, 786, 853, 920, 987, 1054, +-- 1121, 1188, 1255, 1322, 1389, 1456, 1523, 1590, 1657, 1724, 1791, 1858, 1925, 1992, 2059, 2126, +-- 50, 117, 184, 251, 318, 385, 452, 519, 586, 653, 720, 787, 854, 921, 988, 1055, +-- 1122, 1189, 1256, 1323, 1390, 1457, 1524, 1591, 1658, 1725, 1792, 1859, 1926, 1993, 2060, 2127, +-- 51, 118, 185, 252, 319, 386, 453, 520, 587, 654, 721, 788, 855, 922, 989, 1056, +-- 1123, 1190, 1257, 1324, 1391, 1458, 1525, 1592, 1659, 1726, 1793, 1860, 1927, 1994, 2061, 2128, +-- 52, 119, 186, 253, 320, 387, 454, 521, 588, 655, 722, 789, 856, 923, 990, 1057, +-- 1124, 1191, 1258, 1325, 1392, 1459, 1526, 1593, 1660, 1727, 1794, 1861, 1928, 1995, 2062, 2129, +-- 53, 120, 187, 254, 321, 388, 455, 522, 589, 656, 723, 790, 857, 924, 991, 1058, +-- 1125, 1192, 1259, 1326, 1393, 1460, 1527, 1594, 1661, 1728, 1795, 1862, 1929, 1996, 2063, 2130, +-- 54, 121, 188, 255, 322, 389, 456, 523, 590, 657, 724, 791, 858, 925, 992, 1059, +-- 1126, 1193, 1260, 1327, 1394, 1461, 1528, 1595, 1662, 1729, 1796, 1863, 1930, 1997, 2064, 2131, +-- 55, 122, 189, 256, 323, 390, 457, 524, 591, 658, 725, 792, 859, 926, 993, 1060, +-- 1127, 1194, 1261, 1328, 1395, 1462, 1529, 1596, 1663, 1730, 1797, 1864, 1931, 1998, 2065, 2132, +-- 56, 123, 190, 257, 324, 391, 458, 525, 592, 659, 726, 793, 860, 927, 994, 1061, +-- 1128, 1195, 1262, 1329, 1396, 1463, 1530, 1597, 1664, 1731, 1798, 1865, 1932, 1999, 2066, 2133, +-- 57, 124, 191, 258, 325, 392, 459, 526, 593, 660, 727, 794, 861, 928, 995, 1062, +-- 1129, 1196, 1263, 1330, 1397, 1464, 1531, 1598, 1665, 1732, 1799, 1866, 1933, 2000, 2067, 2134, +-- 58, 125, 192, 259, 326, 393, 460, 527, 594, 661, 728, 795, 862, 929, 996, 1063, +-- 1130, 1197, 1264, 1331, 1398, 1465, 1532, 1599, 1666, 1733, 1800, 1867, 1934, 2001, 2068, 2135, +-- 59, 126, 193, 260, 327, 394, 461, 528, 595, 662, 729, 796, 863, 930, 997, 1064, +-- 1131, 1198, 1265, 1332, 1399, 1466, 1533, 1600, 1667, 1734, 1801, 1868, 1935, 2002, 2069, 2136, +-- 60, 127, 194, 261, 328, 395, 462, 529, 596, 663, 730, 797, 864, 931, 998, 1065, +-- 1132, 1199, 1266, 1333, 1400, 1467, 1534, 1601, 1668, 1735, 1802, 1869, 1936, 2003, 2070, 2137, +-- 61, 128, 195, 262, 329, 396, 463, 530, 597, 664, 731, 798, 865, 932, 999, 1066, +-- 1133, 1200, 1267, 1334, 1401, 1468, 1535, 1602, 1669, 1736, 1803, 1870, 1937, 2004, 2071, 2138, +-- 62, 129, 196, 263, 330, 397, 464, 531, 598, 665, 732, 799, 866, 933, 1000, 1067, +-- 1134, 1201, 1268, 1335, 1402, 1469, 1536, 1603, 1670, 1737, 1804, 1871, 1938, 2005, 2072, 2139, +-- 63, 130, 197, 264, 331, 398, 465, 532, 599, 666, 733, 800, 867, 934, 1001, 1068, +-- 1135, 1202, 1269, 1336, 1403, 1470, 1537, 1604, 1671, 1738, 1805, 1872, 1939, 2006, 2073, 2140, +-- 64, 131, 198, 265, 332, 399, 466, 533, 600, 667, 734, 801, 868, 935, 1002, 1069, +-- 1136, 1203, 1270, 1337, 1404, 1471, 1538, 1605, 1672, 1739, 1806, 1873, 1940, 2007, 2074, 2141, +-- 65, 132, 199, 266, 333, 400, 467, 534, 601, 668, 735, 802, 869, 936, 1003, 1070, +-- 1137, 1204, 1271, 1338, 1405, 1472, 1539, 1606, 1673, 1740, 1807, 1874, 1941, 2008, 2075, 2142, +-- 66, 133, 200, 267, 334, 401, 468, 535, 602, 669, 736, 803, 870, 937, 1004, 1071, +-- 1138, 1205, 1272, 1339, 1406, 1473, 1540, 1607, 1674, 1741, 1808, 1875, 1942, 2009, 2076, 2143 +-- ); ---------------------------------------------------------------------------- -- BYTE-LEVEL INTERLEAVER (67x4) - For PlutoSDR, fits in xc7z010 @@ -317,7 +328,17 @@ ARCHITECTURE rtl OF ov_frame_encoder IS RETURN col * ROWS + row; END FUNCTION; -BEGIN +BEGIN + + -- to find the state of the state machine for debug + debug_state <= "000" WHEN state = IDLE ELSE + "001" WHEN state = COLLECT ELSE + "010" WHEN state = RANDOMIZE ELSE + "011" WHEN state = PREP_FEC ELSE + "100" WHEN state = FEC_ENCODE ELSE + "101" WHEN state = INTERLEAVE ELSE + "110" WHEN state = OUTPUT ELSE + "111"; -- Convolutional Encoder Instantiation U_ENCODER : ENTITY work.conv_encoder_k7 @@ -500,31 +521,35 @@ BEGIN ------------------------------------------------------------------------ -- INTERLEAVE: Dual-mode implementation ------------------------------------------------------------------------ - WHEN INTERLEAVE => - IF USE_BIT_INTERLEAVER THEN - -- BIT-LEVEL mode: Process 1 bit per clock (2144 clocks) - IF bit_idx < ENCODED_BITS THEN - interleaved_buffer(INTERLEAVE_LUT_BIT(bit_idx)) <= fec_buffer(bit_idx); - bit_idx <= bit_idx + 1; - ELSE - out_idx <= 0; - state <= OUTPUT; - m_axis_tvalid_reg <= '0'; - END IF; - ELSE - -- BYTE-LEVEL mode: Process 1 byte per clock (268 clocks) - IF byte_idx < ENCODED_BYTES THEN - FOR j IN 0 TO 7 LOOP - interleaved_buffer(interleave_address_byte(byte_idx)*8 + j) <= - fec_buffer(byte_idx*8 + j); - END LOOP; - byte_idx <= byte_idx + 1; - ELSE - out_idx <= 0; - state <= OUTPUT; - m_axis_tvalid_reg <= '0'; - END IF; - END IF; + +WHEN INTERLEAVE => +-- IF USE_BIT_INTERLEAVER THEN +-- -- BIT-LEVEL mode: Process 1 bit per clock (2144 clocks) +-- IF bit_idx < ENCODED_BITS THEN +-- interleaved_buffer(INTERLEAVE_LUT_BIT(bit_idx)) <= fec_buffer(bit_idx); +-- bit_idx <= bit_idx + 1; +-- ELSE +-- out_idx <= 0; +-- state <= OUTPUT; +-- m_axis_tvalid_reg <= '0'; +-- END IF; +-- ELSE + -- BYTE-LEVEL mode: Process 1 byte per clock (268 clocks) + IF byte_idx < ENCODED_BYTES THEN + FOR j IN 0 TO 7 LOOP + interleaved_buffer(interleave_address_byte(byte_idx)*8 + j) <= + fec_buffer(byte_idx*8 + j); + END LOOP; + byte_idx <= byte_idx + 1; + ELSE + out_idx <= 0; + state <= OUTPUT; + m_axis_tvalid_reg <= '0'; + END IF; +-- END IF; + + + ---------------------------------------------------------------------- -- OUTPUT: Stream interleaved bytes to modulator @@ -552,6 +577,7 @@ BEGIN out_idx <= out_idx + 1; END IF; ELSE + -- Frame output complete IF m_axis_tready = '1' THEN m_axis_tvalid_reg <= '0'; @@ -569,6 +595,7 @@ BEGIN END IF; END CASE; + END IF; END PROCESS; diff --git a/src/viterbi_decoder_k7_simple.vhd b/src/viterbi_decoder_k7_simple.vhd index d1a8a82..d70da79 100644 --- a/src/viterbi_decoder_k7_simple.vhd +++ b/src/viterbi_decoder_k7_simple.vhd @@ -1,11 +1,14 @@ ------------------------------------------------------------------------------------------------------ --- BRAM-Optimized Viterbi Decoder - SIMPLIFIED TRACEBACK (2 cycles per step) +-- BRAM-Optimized Viterbi Decoder - SHIFT REGISTER INPUTS ------------------------------------------------------------------------------------------------------ --- This version uses 2 clock cycles per traceback step for clarity and correctness: --- Cycle 1: Fetch decision from BRAM --- Cycle 2: Use decision, output bit, move to previous state +-- This version uses shift registers for the input data to avoid massive muxes. +-- Instead of input_bits_g1(time_step) creating a 1072:1 mux, we: +-- 1. Load the parallel input into a shift register +-- 2. Shift out one bit per time step -- --- This is slower but eliminates pipeline complexity bugs. +-- This saves ~2000 LUTs (2 x 1072:1 mux elimination) +-- +-- Interface is IDENTICAL to original - parallel load happens internally. ------------------------------------------------------------------------------------------------------ LIBRARY ieee; @@ -32,56 +35,26 @@ END ENTITY viterbi_decoder_k7_simple; ARCHITECTURE rtl OF viterbi_decoder_k7_simple IS - CONSTANT NUM_STATES : INTEGER := 64; CONSTANT METRIC_WIDTH : INTEGER := 12; CONSTANT INF_METRIC : INTEGER := 4095; - CONSTANT NUM_SYMBOLS : INTEGER := ENCODED_BITS/2; + CONSTANT NUM_SYMBOLS : INTEGER := ENCODED_BITS/2; -- 1072 TYPE state_t IS (IDLE, INITIALIZE, ACS_COMPUTE, FIND_BEST, - TB_FETCH, TB_USE, COMPLETE); + TB_FETCH, TB_USE, COMPLETE); SIGNAL state : state_t := IDLE; TYPE metric_array_t IS ARRAY(0 TO NUM_STATES-1) OF unsigned(METRIC_WIDTH-1 DOWNTO 0); - -- added initialization to try to get simulation to stop stalling on second frame SIGNAL metrics_current : metric_array_t := (OTHERS => (OTHERS => '0')); SIGNAL metrics_next : metric_array_t := (OTHERS => (OTHERS => '0')); - --SIGNAL metrics_current : metric_array_t; - --SIGNAL metrics_next : metric_array_t; - - --CONSTANT DECISION_DEPTH : INTEGER := NUM_SYMBOLS * NUM_STATES; - --TYPE decision_mem_t IS ARRAY(0 TO DECISION_DEPTH-1) OF std_logic; - --SIGNAL decision_mem : decision_mem_t; - - -- ATTRIBUTE ram_style : STRING; - -- ATTRIBUTE ram_style OF decision_mem : SIGNAL IS "ultra"; - -- was block, worked with distributed but was too large of a design, tried ultra - -- still too big. removed entirely tried, was still too big. Then... - - --ATTRIBUTE ram_style : STRING; - --ATTRIBUTE ram_style OF decision_mem : SIGNAL IS "block"; - --ATTRIBUTE ram_extract : STRING; - --ATTRIBUTE ram_extract OF decision_mem : SIGNAL IS "yes"; - --ATTRIBUTE keep : STRING; - --ATTRIBUTE keep OF decision_mem : SIGNAL IS "true"; - -- crashed in a different place - --CONSTANT DECISION_DEPTH : INTEGER := NUM_SYMBOLS * NUM_STATES; - --CONSTANT CHUNK_SIZE : INTEGER := 4096; - --CONSTANT NUM_CHUNKS : INTEGER := (DECISION_DEPTH + CHUNK_SIZE - 1) / CHUNK_SIZE; - - --TYPE decision_chunk_t IS ARRAY(0 TO CHUNK_SIZE-1) OF std_logic; - --TYPE decision_mem_array_t IS ARRAY(0 TO NUM_CHUNKS-1) OF decision_chunk_t; - --SIGNAL decision_mem : decision_mem_array_t; - - --ATTRIBUTE ram_style : STRING; - --ATTRIBUTE ram_style OF decision_mem : SIGNAL IS "block"; - + -- Decision memory in BRAM CONSTANT DECISION_DEPTH : INTEGER := NUM_SYMBOLS * NUM_STATES; TYPE decision_mem_t IS ARRAY(0 TO DECISION_DEPTH-1) OF std_logic; SIGNAL decision_mem : decision_mem_t; - + ATTRIBUTE ram_style : STRING; + ATTRIBUTE ram_style OF decision_mem : SIGNAL IS "block"; SIGNAL dec_wr_en : std_logic; SIGNAL dec_wr_addr : INTEGER RANGE 0 TO DECISION_DEPTH-1; @@ -96,6 +69,11 @@ ARCHITECTURE rtl OF viterbi_decoder_k7_simple IS SIGNAL out_buf : std_logic_vector(PAYLOAD_BITS-1 DOWNTO 0); SIGNAL rx_symbol : std_logic_vector(1 DOWNTO 0); + + -- SHIFT REGISTERS for input data (replaces massive mux) + -- These shift left, MSB contains current symbol + SIGNAL g1_sr : std_logic_vector(NUM_SYMBOLS-1 DOWNTO 0); + SIGNAL g2_sr : std_logic_vector(NUM_SYMBOLS-1 DOWNTO 0); FUNCTION compute_output(curr_state : INTEGER; input_bit : std_logic) RETURN std_logic_vector IS @@ -136,24 +114,25 @@ ARCHITECTURE rtl OF viterbi_decoder_k7_simple IS BEGIN + -- BRAM write process PROCESS(clk) BEGIN IF rising_edge(clk) THEN IF dec_wr_en = '1' THEN decision_mem(dec_wr_addr) <= dec_wr_data; - --decision_mem(dec_wr_addr / CHUNK_SIZE)(dec_wr_addr MOD CHUNK_SIZE) <= dec_wr_data; END IF; END IF; END PROCESS; + -- BRAM read process PROCESS(clk) BEGIN IF rising_edge(clk) THEN dec_rd_data <= decision_mem(dec_rd_addr); - --dec_rd_data <= decision_mem(dec_rd_addr / CHUNK_SIZE)(dec_rd_addr MOD CHUNK_SIZE); END IF; END PROCESS; + -- Main FSM PROCESS(clk, aresetn) VARIABLE prev_state_0, prev_state_1 : INTEGER RANGE 0 TO NUM_STATES-1; VARIABLE input_bit : std_logic; @@ -169,7 +148,9 @@ BEGIN dec_wr_en <= '0'; time_step <= 0; state_idx <= 0; - metrics_next <= (OTHERS => (OTHERS => '0')); + metrics_next <= (OTHERS => (OTHERS => '0')); + g1_sr <= (OTHERS => '0'); + g2_sr <= (OTHERS => '0'); ELSIF rising_edge(clk) THEN done <= '0'; @@ -183,6 +164,11 @@ BEGIN state <= INITIALIZE; busy <= '1'; state_idx <= 0; + -- PARALLEL LOAD shift registers from input vectors + -- Load bits 0..1071 directly - simple slice, no mux needed + -- We'll read from bit 0 and shift right each time step + g1_sr <= input_bits_g1(NUM_SYMBOLS-1 DOWNTO 0); + g2_sr <= input_bits_g2(NUM_SYMBOLS-1 DOWNTO 0); END IF; WHEN INITIALIZE => @@ -202,7 +188,8 @@ BEGIN WHEN ACS_COMPUTE => IF time_step < NUM_SYMBOLS THEN IF state_idx = 0 THEN - rx_symbol <= input_bits_g1(time_step) & input_bits_g2(time_step); + -- Get current symbol from LSB of shift registers + rx_symbol <= g1_sr(0) & g2_sr(0); END IF; IF state_idx < NUM_STATES THEN @@ -230,9 +217,13 @@ BEGIN dec_wr_en <= '1'; state_idx <= state_idx + 1; ELSE + -- Done with all states for this time step metrics_current <= metrics_next; state_idx <= 0; time_step <= time_step + 1; + -- SHIFT RIGHT: next symbol moves to bit 0 + g1_sr <= '0' & g1_sr(NUM_SYMBOLS-1 DOWNTO 1); + g2_sr <= '0' & g2_sr(NUM_SYMBOLS-1 DOWNTO 1); END IF; ELSE state <= FIND_BEST; @@ -257,12 +248,9 @@ BEGIN state <= TB_FETCH; END IF; - ------------------------------------------------------------------------------------ -- SIMPLIFIED 2-CYCLE TRACEBACK - ------------------------------------------------------------------------------------ WHEN TB_FETCH => -- Cycle 1: Issue BRAM read for current (tb_time, tb_state) - -- Next cycle, dec_rd_data will be valid state <= TB_USE; WHEN TB_USE => From edc5a7b4686c8dd361a64367ef93cd3d570516de Mon Sep 17 00:00:00 2001 From: Abraxas3d Date: Mon, 1 Dec 2025 14:43:15 -0800 Subject: [PATCH 54/60] Add LibreSDR (XC7Z020/AD9363) support - Add projects/libre/ with HDL project files (LVDS interface, XC7Z020-CLG400) - Add firmware/scripts/libre.mk and libre.its for firmware build - Add firmware/ori/libre/ with device tree and config files for submodules - Add setup_libre.sh script to install files into submodules after clone - Update firmware/Makefile to support TARGET=libre Pin constraint fixes from hz12opensource patch: - gpio_status[5]: Moved from T20 to G14 to avoid conflict Build instructions: cd firmware/ori/libre && ./setup_libre.sh cd ~/pluto_msk/firmware make TARGET=libre XSA_FILE=/path/to/system_top.xsa LibreSDR provides 53,200 LUTs vs PlutoSDR's 17,600 (3x capacity) --- firmware/Makefile | 11 +- .../buildroot-configs/zynq_libre_defconfig | 68 +++ .../linux-configs/zynq_libre_linux_defconfig | 286 +++++++++++ firmware/ori/libre/linux-dts/zynq-libre.dts | 60 +++ firmware/ori/libre/linux-dts/zynq-libre.dtsi | 449 ++++++++++++++++++ firmware/ori/libre/setup_libre.sh | 29 ++ .../libre/uboot-configs/zynq_libre_defconfig | 62 +++ .../ori/libre/uboot-dts/zynq-libre-sdr.dts | 111 +++++ firmware/scripts/libre.its | 70 +++ firmware/scripts/libre.mk | 7 + projects/libre/Makefile | 24 + projects/libre/Readme.md | 10 + projects/libre/system_bd.tcl | 395 +++++++++++++++ projects/libre/system_constr.xdc | 133 ++++++ projects/libre/system_project.tcl | 14 + projects/libre/system_top.v | 183 +++++++ 16 files changed, 1908 insertions(+), 4 deletions(-) create mode 100644 firmware/ori/libre/buildroot-configs/zynq_libre_defconfig create mode 100644 firmware/ori/libre/linux-configs/zynq_libre_linux_defconfig create mode 100644 firmware/ori/libre/linux-dts/zynq-libre.dts create mode 100644 firmware/ori/libre/linux-dts/zynq-libre.dtsi create mode 100755 firmware/ori/libre/setup_libre.sh create mode 100644 firmware/ori/libre/uboot-configs/zynq_libre_defconfig create mode 100644 firmware/ori/libre/uboot-dts/zynq-libre-sdr.dts create mode 100644 firmware/scripts/libre.its create mode 100644 firmware/scripts/libre.mk create mode 100644 projects/libre/Makefile create mode 100755 projects/libre/Readme.md create mode 100644 projects/libre/system_bd.tcl create mode 100644 projects/libre/system_constr.xdc create mode 100644 projects/libre/system_project.tcl create mode 100644 projects/libre/system_top.v diff --git a/firmware/Makefile b/firmware/Makefile index 82c136f..4b82183 100644 --- a/firmware/Makefile +++ b/firmware/Makefile @@ -44,7 +44,7 @@ ifneq (1, ${PATCH}) endif TARGET ?= pluto -SUPPORTED_TARGETS:=pluto plutoplus e200 +SUPPORTED_TARGETS:=pluto plutoplus e200 libre #XSA_FILE ?= ori/bitstream/${TARGET}/system_top.xsa $(warning *** Building target $(TARGET),) @@ -54,9 +54,9 @@ include scripts/$(TARGET).mk ifeq (, $(shell which dfu-suffix)) $(warning "No dfu-utils in PATH consider doing: sudo apt-get install dfu-util") -TARGETS = build/pluto.frm build/boot.frm +TARGETS = build/$(TARGET).frm build/boot.frm else -TARGETS = build/$(TARGET).dfu build/uboot-env.dfu build/pluto.frm build/boot.dfu build/boot.frm +TARGETS = build/$(TARGET).dfu build/uboot-env.dfu build/$(TARGET).frm build/boot.dfu build/boot.frm endif ifeq ($(findstring $(TARGET),$(SUPPORTED_TARGETS)),) @@ -199,7 +199,7 @@ else endif ### MSD update firmware file ### -build/pluto.frm: build/$(TARGET).itb +build/$(TARGET).frm: build/$(TARGET).itb md5sum $< | cut -d ' ' -f 1 > $@.md5 cat $< $@.md5 > $@ @@ -235,6 +235,9 @@ endif ifeq ($(TARGET),e200) cp build/zynq-e200.dtb $(SDIMGDIR)/devicetree.dtb endif +ifeq ($(TARGET),libre) + cp build/zynq-libre.dtb $(SDIMGDIR)/devicetree.dtb +endif cp build/uboot-env.txt $(SDIMGDIR)/uEnv.txt cp build/rootfs.cpio.gz $(SDIMGDIR)/ramdisk.image.gz mkimage -A arm -T ramdisk -C gzip -d $(SDIMGDIR)/ramdisk.image.gz $(SDIMGDIR)/uramdisk.image.gz diff --git a/firmware/ori/libre/buildroot-configs/zynq_libre_defconfig b/firmware/ori/libre/buildroot-configs/zynq_libre_defconfig new file mode 100644 index 0000000..0692d2d --- /dev/null +++ b/firmware/ori/libre/buildroot-configs/zynq_libre_defconfig @@ -0,0 +1,68 @@ +BR2_arm=y +BR2_cortex_a9=y +BR2_ARM_ENABLE_NEON=y +BR2_ARM_ENABLE_VFP=y +BR2_ARM_FPU_NEON=y +BR2_TOOLCHAIN_EXTERNAL=y +BR2_TOOLCHAIN_EXTERNAL_LINARO_ARM=y +BR2_OPTIMIZE_3=y +BR2_PACKAGE_ETHTOOL=y +BR2_PACKAGE_ETHTOOL_PRETTY_PRINT=y +BR2_PACKAGE_IPERF3=y +BR2_PACKAGE_HTOP=y +BR2_TARGET_GENERIC_HOSTNAME="libre" +BR2_TARGET_GENERIC_ISSUE="Welcome to LibreSDR" +BR2_ROOTFS_DEVICE_CREATION_DYNAMIC_MDEV=y +BR2_TARGET_GENERIC_ROOT_PASSWD="analog" +BR2_TARGET_GENERIC_GETTY_PORT="ttyPS0" +BR2_ROOTFS_POST_BUILD_SCRIPT="board/libre/post-build.sh" +BR2_PACKAGE_ZSTD=y +BR2_PACKAGE_MTD=y +# BR2_PACKAGE_MTD_NANDDUMP is not set +# BR2_PACKAGE_MTD_NANDTEST is not set +# BR2_PACKAGE_MTD_NANDWRITE is not set +# BR2_PACKAGE_MTD_UBIATTACH is not set +# BR2_PACKAGE_MTD_UBICRC32 is not set +# BR2_PACKAGE_MTD_UBIDETACH is not set +# BR2_PACKAGE_MTD_UBIFORMAT is not set +# BR2_PACKAGE_MTD_UBIMKVOL is not set +# BR2_PACKAGE_MTD_UBINFO is not set +# BR2_PACKAGE_MTD_UBINIZE is not set +# BR2_PACKAGE_MTD_UBIRENAME is not set +# BR2_PACKAGE_MTD_UBIRMVOL is not set +# BR2_PACKAGE_MTD_UBIRSVOL is not set +# BR2_PACKAGE_MTD_UBIUPDATEVOL is not set +# BR2_PACKAGE_MTD_UBIBLOCK is not set +BR2_PACKAGE_LINUX_FIRMWARE=y +BR2_PACKAGE_LINUX_FIRMWARE_RALINK_RT61=y +BR2_PACKAGE_LINUX_FIRMWARE_RALINK_RT73=y +BR2_PACKAGE_LINUX_FIRMWARE_RALINK_RT2XX=y +BR2_PACKAGE_LINUX_FIRMWARE_RTL_81XX=y +BR2_PACKAGE_LINUX_FIRMWARE_RTL_87XX=y +BR2_PACKAGE_LINUX_FIRMWARE_RTL_88XX=y +BR2_PACKAGE_INPUT_EVENT_DAEMON=y +BR2_PACKAGE_UBOOT_TOOLS=y +BR2_PACKAGE_ZLIB=y +BR2_PACKAGE_LIBAD9361_IIO=y +BR2_PACKAGE_LIBGPIOD=y +BR2_PACKAGE_LIBGPIOD_TOOLS=y +BR2_PACKAGE_LIBIIO_IIOD_USBD=y +BR2_PACKAGE_LIBIIO_TESTS=y +BR2_PACKAGE_LIBINI=y +BR2_PACKAGE_AVAHI=y +BR2_PACKAGE_AVAHI_DAEMON=y +BR2_PACKAGE_AVAHI_LIBDNSSD_COMPATIBILITY=y +BR2_PACKAGE_DROPBEAR=y +BR2_PACKAGE_DROPBEAR_LOCALOPTIONS_FILE="board/pluto/dropbrear_localoptions.h" +BR2_PACKAGE_IW=y +BR2_PACKAGE_WPA_SUPPLICANT=y +BR2_PACKAGE_WPA_SUPPLICANT_CLI=y +BR2_PACKAGE_WPA_SUPPLICANT_PASSPHRASE=y +BR2_PACKAGE_POLL_SYSFS=y +BR2_PACKAGE_AD936X_REF_CAL=y +BR2_TARGET_ROOTFS_CPIO=y +BR2_TARGET_ROOTFS_CPIO_GZIP=y +BR2_TARGET_ROOTFS_CPIO_UIMAGE=y +BR2_PACKAGE_HOST_DOSFSTOOLS=y +BR2_PACKAGE_HOST_GENIMAGE=y +BR2_PACKAGE_HOST_MTOOLS=y \ No newline at end of file diff --git a/firmware/ori/libre/linux-configs/zynq_libre_linux_defconfig b/firmware/ori/libre/linux-configs/zynq_libre_linux_defconfig new file mode 100644 index 0000000..73790cc --- /dev/null +++ b/firmware/ori/libre/linux-configs/zynq_libre_linux_defconfig @@ -0,0 +1,286 @@ +CONFIG_SYSVIPC=y +CONFIG_USELIB=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_PREEMPT=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=15 +CONFIG_CGROUPS=y +CONFIG_BLK_DEV_INITRD=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_XZ is not set +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE_O3=y +CONFIG_EMBEDDED=y +CONFIG_PERF_EVENTS=y +CONFIG_SLAB=y +CONFIG_ARCH_ZYNQ=y + + +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_OF_ARASAN=y + +CONFIG_UEVENT_HELPER=y +CONFIG_MACB=y +CONFIG_MDIO_BITBANG=y +CONFIG_MARVELL_PHY=y +CONFIG_XILINX_GMII2RGMII=y +CONFIG_USB_NET_DM9601=y + +CONFIG_XILINX_RESET_CODE=y +CONFIG_PL310_ERRATA_588369=y +CONFIG_PL310_ERRATA_727915=y +CONFIG_PL310_ERRATA_769419=y +# CONFIG_ARM_ERRATA_643719 is not set +CONFIG_ARM_ERRATA_754322=y +CONFIG_ARM_ERRATA_754327=y +CONFIG_ARM_ERRATA_764369=y +CONFIG_ARM_ERRATA_775420=y +CONFIG_SMP=y +CONFIG_SCHED_MC=y +CONFIG_SCHED_SMT=y +CONFIG_HIGHMEM=y +# CONFIG_HIGHPTE is not set +CONFIG_CMDLINE="console=ttyPS0,115200n8 root=/dev/ram rw earlyprintk" +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_ARM_ZYNQ_CPUIDLE=y +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_COMPACTION is not set +CONFIG_CMA=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_NET_IPIP=m +# CONFIG_IPV6 is not set +CONFIG_VLAN_8021Q=m +CONFIG_CFG80211=y +CONFIG_MAC80211=y +CONFIG_MAC80211_LEDS=y +CONFIG_RFKILL=y +CONFIG_RFKILL_INPUT=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=256 +CONFIG_CONNECTOR=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_PHYSMAP_OF=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_SPI_NOR=y +# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=16384 +CONFIG_ADI_AXI_TDD=y +CONFIG_SRAM=y +# CONFIG_MATHWORKS_IP_CORE is not set +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_SG=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_NETDEVICES=y +# CONFIG_NET_VENDOR_ALACRITECH is not set +# CONFIG_NET_VENDOR_AMAZON is not set +# CONFIG_NET_VENDOR_AQUANTIA is not set +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_EZCHIP is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_HISILICON is not set +# CONFIG_NET_VENDOR_HUAWEI is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MELLANOX is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NETRONOME is not set +# CONFIG_NET_VENDOR_QUALCOMM is not set +# CONFIG_NET_VENDOR_RENESAS is not set +# CONFIG_NET_VENDOR_ROCKER is not set +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SOLARFLARE is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SYNOPSYS is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +# CONFIG_NET_VENDOR_XILINX is not set +CONFIG_USB_RTL8152=y +CONFIG_USB_LAN78XX=y +CONFIG_USB_USBNET=y +# CONFIG_USB_NET_CDC_NCM is not set +CONFIG_USB_NET_SMSC75XX=y +CONFIG_USB_NET_SMSC95XX=y +# CONFIG_USB_NET_NET1080 is not set +CONFIG_USB_NET_RNDIS_HOST=y +# CONFIG_USB_NET_CDC_SUBSET is not set +# CONFIG_USB_NET_ZAURUS is not set +# CONFIG_WLAN_VENDOR_ADMTEK is not set +# CONFIG_WLAN_VENDOR_ATH is not set +# CONFIG_WLAN_VENDOR_ATMEL is not set +# CONFIG_WLAN_VENDOR_BROADCOM is not set +# CONFIG_WLAN_VENDOR_CISCO is not set +# CONFIG_WLAN_VENDOR_INTEL is not set +# CONFIG_WLAN_VENDOR_INTERSIL is not set +# CONFIG_WLAN_VENDOR_MARVELL is not set +# CONFIG_WLAN_VENDOR_MEDIATEK is not set +CONFIG_RT2X00=y +CONFIG_RT2500USB=y +CONFIG_RT73USB=y +CONFIG_RT2800USB=y +CONFIG_RT2800USB_RT3573=y +CONFIG_RT2800USB_RT53XX=y +CONFIG_RT2800USB_RT55XX=y +CONFIG_RT2800USB_UNKNOWN=y +CONFIG_RTL8187=y +CONFIG_RTL8192CU=y +# CONFIG_RTLWIFI_DEBUG is not set +CONFIG_RTL8XXXU=y +CONFIG_RTL8XXXU_UNTESTED=y +# CONFIG_WLAN_VENDOR_RSI is not set +# CONFIG_WLAN_VENDOR_ST is not set +# CONFIG_WLAN_VENDOR_TI is not set +# CONFIG_WLAN_VENDOR_ZYDAS is not set +CONFIG_INPUT_FF_MEMLESS=y +CONFIG_INPUT_SPARSEKMAP=y +CONFIG_INPUT_EVDEV=y +CONFIG_KEYBOARD_GPIO=y +# CONFIG_INPUT_MOUSE is not set +CONFIG_VT_HW_CONSOLE_BINDING=y +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_XILINX_PS_UART=y +CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y +# CONFIG_HW_RANDOM is not set +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_CADENCE=y +CONFIG_I2C_GPIO=y +CONFIG_I2C_XILINX=y +CONFIG_SPI=y +CONFIG_SPI_AXI_SPI_ENGINE=y +CONFIG_SPI_CADENCE=y +CONFIG_SPI_XILINX=y +CONFIG_SPI_ZYNQ_QSPI=y +CONFIG_SPI_SPIDEV=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_ZYNQ=y +CONFIG_POWER_SUPPLY=y +CONFIG_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_XILINX_WATCHDOG=y +CONFIG_CADENCE_WATCHDOG=y +CONFIG_SSB=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_HIDRAW=y +CONFIG_USB_HIDDEV=y +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_OTG=y +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +CONFIG_USB_STORAGE=y +CONFIG_USB_CHIPIDEA=y +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_SERIAL=y +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_FTDI_SIO=y +CONFIG_USB_ULPI=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VBUS_DRAW=500 +CONFIG_USB_GADGET_XILINX=y +CONFIG_USB_CONFIGFS=y +CONFIG_USB_CONFIGFS_SERIAL=y +CONFIG_USB_CONFIGFS_ACM=y +CONFIG_USB_CONFIGFS_NCM=y +CONFIG_USB_CONFIGFS_ECM=y +CONFIG_USB_CONFIGFS_ECM_SUBSET=y +CONFIG_USB_CONFIGFS_RNDIS=y +CONFIG_USB_CONFIGFS_EEM=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_ONESHOT=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_DMADEVICES=y +CONFIG_AXI_DMAC=y +CONFIG_UIO=y +CONFIG_UIO_PDRV_GENIRQ=y +CONFIG_UIO_DMEM_GENIRQ=y +CONFIG_UIO_XILINX_APM=y +CONFIG_STAGING=y +CONFIG_R8712U=y +CONFIG_R8188EU=y +CONFIG_COMMON_CLK_AXI_CLKGEN=y +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_MEMORY=y +CONFIG_IIO=y +CONFIG_ADM1177=y +CONFIG_AD9361=y +CONFIG_AD9361_EXT_BAND_CONTROL=y +CONFIG_ADMC=y +CONFIG_XILINX_XADC=y +CONFIG_ONE_BIT_ADC_DAC=y +CONFIG_CF_AXI_DDS=y +CONFIG_ADI_IIO_FAKEDEV=y +CONFIG_FPGA=y +CONFIG_FPGA_MGR_ZYNQ_FPGA=y +CONFIG_EXT4_FS=y +# CONFIG_DNOTIFY is not set +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +# CONFIG_NETWORK_FILESYSTEMS is not set +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_MICHAEL_MIC=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_FS=y +CONFIG_DETECT_HUNG_TASK=y +CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=20 +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_PREEMPT is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +# CONFIG_FTRACE is not set +CONFIG_DEBUG_LL=y +CONFIG_DEBUG_ZYNQ_UART0=y +CONFIG_EARLY_PRINTK=y \ No newline at end of file diff --git a/firmware/ori/libre/linux-dts/zynq-libre.dts b/firmware/ori/libre/linux-dts/zynq-libre.dts new file mode 100644 index 0000000..1c43423 --- /dev/null +++ b/firmware/ori/libre/linux-dts/zynq-libre.dts @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * + * hdl_project: + * board_revision: <5> + * + */ +/dts-v1/; +#include "zynq-libre.dtsi" + + +// &axi_i2c0 { +// current_limiter@5a { +// compatible = "adi,adm1177"; +// reg = <0x5a>; +// adi,r-sense-mohm = <50>; /* 50 mOhm */ +// adi,shutdown-threshold-ma = <1059>; /* 1.059 A */ +// adi,vrange-high-enable; +// }; +// }; + + +&adc0_ad9364 { + /* This property is controlled by u-boot environment. */ + adi,2rx-2tx-mode-enable; +}; + +&cf_ad9364_dac_core_0 { + /* This property is controlled by u-boot environment. */ + compatible = "adi,axi-ad9361-dds-6.00.a"; +}; + + +/ { + + leds { + compatible = "gpio-leds"; + led0 { + label = "led0:green"; + gpios = <&gpio0 15 0>; + linux,default-trigger = "heartbeat"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + button { + interrupt-parent = <&gpio0>; + interrupts = <14 IRQ_TYPE_EDGE_FALLING>; + label = "Button"; + linux,code = ; + }; + + }; +}; + + diff --git a/firmware/ori/libre/linux-dts/zynq-libre.dtsi b/firmware/ori/libre/linux-dts/zynq-libre.dtsi new file mode 100644 index 0000000..eca50e7 --- /dev/null +++ b/firmware/ori/libre/linux-dts/zynq-libre.dtsi @@ -0,0 +1,449 @@ +/* + * Libre SDR (Z7020/AD936x) + * + * + * Licensed under the GPL-2. + */ +#include "zynq.dtsi" +#include +#include +#include + +#define AD9361_EXT_BAND_CTL_SHORTHANDS +#include + +/ { + model = "LibreSDR Rev.5 (Z7020/AD9363)"; + memory { + device_type = "memory"; + reg = <0x00000000 0x40000000>; + }; + + chosen { + stdout-path = "/amba@0/uart@E0000000"; + }; + + + clocks { + ad9364_clkin: clock@0 { + #clock-cells = <0>; + compatible = "adjustable-clock"; + clock-frequency = <40000000>; + clock-accuracy = <200000>; /* 200 ppm (ppb) */ + clock-output-names = "ad9364_ext_refclk"; + }; + }; + + usb_phy0: phy0 { + compatible = "ulpi-phy"; + #phy-cells = <0>; + reg = <0xe0002000 0x1000>; + view-port = <0x0170>; + drv-vbus; + }; + +}; + +&clkc { + ps-clk-frequency = <50000000>; +}; + +&sdhci0 { + status = "okay"; + xlnx,has-cd = <0x0>; + xlnx,has-power = <0x0>; + xlnx,has-wp = <0x0>; +}; + +&watchdog0 { + status = "okay"; + reset-on-timeout; +}; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <&phy0>; + + phy0: phy@0 { /* Marvell 88e1512 */ + reg = <0>; + compatible = "ethernet-phy-ieee802.3-c22"; + reset-gpios = <&gpio0 46 1>; + }; +}; + +&usb0 { + xlnx,phy-reset-gpio = <&gpio0 47 0>; + dr_mode = "otg"; + status = "okay"; + usb-phy = <&usb_phy0>; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&qspi { + status = "okay"; + is-dual = <0>; + num-cs = <1>; + primary_flash: ps7-qspi@0 { + #address-cells = <1>; + #size-cells = <1>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + compatible = "n25q256a", "n25q512a", "jedec,spi-nor"; /* same as S25FL256 */ + reg = <0x0>; + spi-max-frequency = <50000000>; + partition@qspi-fsbl-uboot { + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; /* 1M */ + }; + partition@qspi-uboot-env { + label = "qspi-uboot-env"; + reg = <0x100000 0x20000>; /* 128k */ + }; + partition@qspi-nvmfs { + label = "qspi-nvmfs"; + reg = <0x120000 0xE0000>; /* 1M */ + }; + partition@qspi-linux { + label = "qspi-linux"; + reg = <0x200000 0x1E00000>; /* 30M */ + }; + }; +}; + +&adc { + xlnx,channels { + #address-cells = <1>; + #size-cells = <0>; + channel@0 { + reg = <0>; + }; + }; +}; + +/ { + fpga_axi: fpga-axi@0 { + compatible = "simple-bus"; + #address-cells = <0x1>; + #size-cells = <0x1>; + ranges; + + // axi_i2c0: i2c@41600000 { + // compatible = "xlnx,axi-iic-1.02.a", "xlnx,xps-iic-2.00.a"; + // reg = <0x41600000 0x10000>; + // interrupt-parent = <&intc>; + // interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>; + // clocks = <&clkc 15>; + // clock-names = "pclk"; + + // #address-cells = <1>; + // #size-cells = <0>; + + // }; + + rx_dma: dma@7c400000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x7c400000 0x10000>; + #dma-cells = <1>; + interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clkc 16>; + + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + + dma-channel@0 { + reg = <0>; + adi,source-bus-width = <32>; + adi,source-bus-type = <2>; + adi,destination-bus-width = <64>; + adi,destination-bus-type = <0>; + }; + }; + }; + + tx_dma: dma@7c420000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x7c420000 0x10000>; + #dma-cells = <1>; + interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clkc 16>; + + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + + dma-channel@0 { + reg = <0>; + adi,source-bus-width = <64>; + adi,source-bus-type = <0>; + adi,destination-bus-width = <32>; + adi,destination-bus-type = <2>; + }; + }; + }; + + cf_ad9364_adc_core_0: cf-ad9361-lpc@79020000 { + compatible = "adi,axi-ad9361-6.00.a"; + reg = <0x79020000 0x6000>; + dmas = <&rx_dma 0>; + dma-names = "rx"; + spibus-connected = <&adc0_ad9364>; + adi,axi-decimation-core-available; + }; + + cf_ad9364_dac_core_0: cf-ad9361-dds-core-lpc@79024000 { + compatible = "adi,axi-ad9364-dds-6.00.a"; + reg = <0x79024000 0x1000>; + clocks = <&adc0_ad9364 13>; + clock-names = "sampl_clk"; + dmas = <&tx_dma 0>; + dma-names = "tx"; + adi,axi-interpolation-core-available; + adi,axi-dds-default-scale = <0>; + }; + + mwipcore@43c00000 { + compatible = "mathworks,mwipcore-axi4lite-v1.00"; + reg = <0x43c00000 0xffff>; + }; + }; +}; + +&spi0 { + status = "okay"; + + adc0_ad9364: ad9361-phy@0 { + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + compatible = "adi,ad9361"; + + /* SPI Setup */ + reg = <0>; + spi-cpha; + spi-max-frequency = <10000000>; + + /* Clocks */ + clocks = <&ad9364_clkin 0>; + clock-names = "ad9364_ext_refclk"; + clock-output-names = "rx_sampl_clk", "tx_sampl_clk"; + + /* Digital Interface Control */ + + /* adi,digital-interface-tune-skip-mode: + * 0 = TUNE RX&TX + * 1 = SKIP TX + * 2 = SKIP ALL + */ + adi,digital-interface-tune-skip-mode = <0>; /* TUNE RX & TX */ + + adi,pp-tx-swap-enable; + adi,pp-rx-swap-enable; + adi,rx-frame-pulse-mode-enable; + adi,lvds-mode-enable; + adi,lvds-bias-mV = <150>; + adi,lvds-rx-onchip-termination-enable; + adi,rx-data-delay = <4>; + adi,tx-fb-clock-delay = <7>; + adi,tx-data-delay = <9>; + + adi,xo-disable-use-ext-refclk-enable; + + /* Mode Setup */ + + //adi,split-gain-table-mode-enable; + + /* ENSM Mode */ + adi,frequency-division-duplex-mode-enable; + //adi,ensm-enable-pin-pulse-mode-enable; + //adi,ensm-enable-txnrx-control-enable; + + + /* adi,rx-rf-port-input-select: + * 0 = (RX1A_N & RX1A_P) and (RX2A_N & RX2A_P) enabled; balanced + * 1 = (RX1B_N & RX1B_P) and (RX2B_N & RX2B_P) enabled; balanced + * 2 = (RX1C_N & RX1C_P) and (RX2C_N & RX2C_P) enabled; balanced + * + * 3 = RX1A_N and RX2A_N enabled; unbalanced + * 4 = RX1A_P and RX2A_P enabled; unbalanced + * 5 = RX1B_N and RX2B_N enabled; unbalanced + * 6 = RX1B_P and RX2B_P enabled; unbalanced + * 7 = RX1C_N and RX2C_N enabled; unbalanced + * 8 = RX1C_P and RX2C_P enabled; unbalanced + */ + + adi,rx-rf-port-input-select = <0>; /* (RX1A_N & RX1A_P) and (RX2A_N & RX2A_P) enabled; balanced */ + adi,rx-rf-port-input-select-lock-enable; + + /* adi,tx-rf-port-input-select: + * 0 TX1A, TX2A + * 1 TX1B, TX2B + */ + + adi,tx-rf-port-input-select = <0>; /* TX1A, TX2A */ + adi,tx-rf-port-input-select-lock-enable; + + //adi,update-tx-gain-in-alert-enable; + adi,tx-attenuation-mdB = <10000>; + adi,tx-lo-powerdown-managed-enable; + + adi,rf-rx-bandwidth-hz = <18000000>; + adi,rf-tx-bandwidth-hz = <18000000>; + adi,rx-synthesizer-frequency-hz = /bits/ 64 <2400000000>; + adi,tx-synthesizer-frequency-hz = /bits/ 64 <2450000000>; + + /* BBPLL ADC R2CLK R1CLK CLKRF RSAMPL */ + adi,rx-path-clock-frequencies = <983040000 245760000 122880000 61440000 30720000 30720000>; + /* BBPLL DAC T2CLK T1CLK CLKTF TSAMPL */ + adi,tx-path-clock-frequencies = <983040000 122880000 122880000 61440000 30720000 30720000>; + + /* Gain Control */ + + /* adi,gc-rx[1|2]-mode: + * 0 = RF_GAIN_MGC + * 1 = RF_GAIN_FASTATTACK_AGC + * 2 = RF_GAIN_SLOWATTACK_AGC + * 3 = RF_GAIN_HYBRID_AGC + */ + + adi,gc-rx1-mode = <2>; + adi,gc-rx2-mode = <2>; + adi,gc-adc-ovr-sample-size = <4>; /* sum 4 samples */ + adi,gc-adc-small-overload-thresh = <47>; /* sum of squares */ + adi,gc-adc-large-overload-thresh = <58>; /* sum of squares */ + adi,gc-lmt-overload-high-thresh = <800>; /* mV */ + adi,gc-lmt-overload-low-thresh = <704>; /* mV */ + adi,gc-dec-pow-measurement-duration = <8192>; /* 0..524288 Samples */ + adi,gc-low-power-thresh = <24>; /* 0..-64 dBFS vals are set pos */ + //adi,gc-dig-gain-enable; + //adi,gc-max-dig-gain = <15>; + + /* Manual Gain Control Setup */ + + //adi,mgc-rx1-ctrl-inp-enable; /* uncomment to use ctrl inputs */ + //adi,mgc-rx2-ctrl-inp-enable; /* uncomment to use ctrl inputs */ + adi,mgc-inc-gain-step = <2>; + adi,mgc-dec-gain-step = <2>; + + /* adi,mgc-split-table-ctrl-inp-gain-mode: + * (relevant if adi,split-gain-table-mode-enable is set) + * 0 = AGC determine this + * 1 = only in LPF + * 2 = only in LMT + */ + + adi,mgc-split-table-ctrl-inp-gain-mode = <0>; + + /* Automatic Gain Control Setup */ + + adi,agc-attack-delay-extra-margin-us= <1>; /* us */ + adi,agc-outer-thresh-high = <5>; /* -dBFS */ + adi,agc-outer-thresh-high-dec-steps = <2>; /* 0..15 */ + adi,agc-inner-thresh-high = <10>; /* -dBFS */ + adi,agc-inner-thresh-high-dec-steps = <1>; /* 0..7 */ + adi,agc-inner-thresh-low = <12>; /* -dBFS */ + adi,agc-inner-thresh-low-inc-steps = <1>; /* 0..7 */ + adi,agc-outer-thresh-low = <18>; /* -dBFS */ + adi,agc-outer-thresh-low-inc-steps = <2>; /* 0..15 */ + + adi,agc-adc-small-overload-exceed-counter = <10>; /* 0..15 */ + adi,agc-adc-large-overload-exceed-counter = <10>; /* 0..15 */ + adi,agc-adc-large-overload-inc-steps = <2>; /* 0..15 */ + //adi,agc-adc-lmt-small-overload-prevent-gain-inc-enable; + adi,agc-lmt-overload-large-exceed-counter = <10>; /* 0..15 */ + adi,agc-lmt-overload-small-exceed-counter = <10>; /* 0..15 */ + adi,agc-lmt-overload-large-inc-steps = <2>; /* 0..7 */ + //adi,agc-dig-saturation-exceed-counter = <3>; /* 0..15 */ + //adi,agc-dig-gain-step-size = <4>; /* 1..8 */ + + //adi,agc-sync-for-gain-counter-enable; + adi,agc-gain-update-interval-us = <1000>; /* 1ms */ + //adi,agc-immed-gain-change-if-large-adc-overload-enable; + //adi,agc-immed-gain-change-if-large-lmt-overload-enable; + + /* Fast AGC */ + + adi,fagc-dec-pow-measurement-duration = <64>; /* 64 Samples */ + //adi,fagc-allow-agc-gain-increase-enable; + adi,fagc-lp-thresh-increment-steps = <1>; + adi,fagc-lp-thresh-increment-time = <5>; + + adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <8>; + adi,fagc-final-overrange-count = <3>; + //adi,fagc-gain-increase-after-gain-lock-enable; + adi,fagc-gain-index-type-after-exit-rx-mode = <0>; + adi,fagc-lmt-final-settling-steps = <1>; + adi,fagc-lock-level = <10>; + adi,fagc-lock-level-gain-increase-upper-limit = <5>; + adi,fagc-lock-level-lmt-gain-increase-enable; + + adi,fagc-lpf-final-settling-steps = <1>; + adi,fagc-optimized-gain-offset = <5>; + adi,fagc-power-measurement-duration-in-state5 = <64>; + adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable; + adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <10>; + adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable; + adi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0>; + adi,fagc-rst-gla-large-adc-overload-enable; + adi,fagc-rst-gla-large-lmt-overload-enable; + adi,fagc-rst-gla-stronger-sig-thresh-above-ll = <10>; + adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable; + adi,fagc-state-wait-time-ns = <260>; + adi,fagc-use-last-lock-level-for-set-gain-enable; + + /* RSSI */ + + /* adi,rssi-restart-mode: + * 0 = AGC_IN_FAST_ATTACK_MODE_LOCKS_THE_GAIN, + * 1 = EN_AGC_PIN_IS_PULLED_HIGH, + * 2 = ENTERS_RX_MODE, + * 3 = GAIN_CHANGE_OCCURS, + * 4 = SPI_WRITE_TO_REGISTER, + * 5 = GAIN_CHANGE_OCCURS_OR_EN_AGC_PIN_PULLED_HIGH, + */ + adi,rssi-restart-mode = <3>; + //adi,rssi-unit-is-rx-samples-enable; + adi,rssi-delay = <1>; /* 1us */ + adi,rssi-wait = <1>; /* 1us */ + adi,rssi-duration = <1000>; /* 1ms */ + + /* Control Outputs */ + adi,ctrl-outs-index = <0>; + adi,ctrl-outs-enable-mask = <0xFF>; + + /* AuxADC Temp Sense Control */ + + adi,temp-sense-measurement-interval-ms = <1000>; + adi,temp-sense-offset-signed = <0xCE>; + adi,temp-sense-periodic-measurement-enable; + + /* AuxDAC Control */ + + adi,aux-dac-manual-mode-enable; + + adi,aux-dac1-default-value-mV = <0>; + //adi,aux-dac1-active-in-rx-enable; + //adi,aux-dac1-active-in-tx-enable; + //adi,aux-dac1-active-in-alert-enable; + adi,aux-dac1-rx-delay-us = <0>; + adi,aux-dac1-tx-delay-us = <0>; + + adi,aux-dac2-default-value-mV = <0>; + //adi,aux-dac2-active-in-rx-enable; + //adi,aux-dac2-active-in-tx-enable; + //adi,aux-dac2-active-in-alert-enable; + adi,aux-dac2-rx-delay-us = <0>; + adi,aux-dac2-tx-delay-us = <0>; + + /* Control GPIOs */ + + en_agc-gpios = <&gpio0 66 0>; + reset-gpios = <&gpio0 67 0>; + + }; +}; diff --git a/firmware/ori/libre/setup_libre.sh b/firmware/ori/libre/setup_libre.sh new file mode 100755 index 0000000..f86596e --- /dev/null +++ b/firmware/ori/libre/setup_libre.sh @@ -0,0 +1,29 @@ +#!/bin/bash +# Setup script to install LibreSDR support files into submodules +# Run this after cloning the repo and initializing submodules + +SCRIPT_DIR="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)" +FIRMWARE_DIR="$(dirname "$(dirname "$SCRIPT_DIR")")" + +echo "Installing LibreSDR files..." + +# Linux device tree and config +cp "$SCRIPT_DIR/linux-dts/zynq-libre.dts" "$FIRMWARE_DIR/linux/arch/arm/boot/dts/" +cp "$SCRIPT_DIR/linux-dts/zynq-libre.dtsi" "$FIRMWARE_DIR/linux/arch/arm/boot/dts/" +cp "$SCRIPT_DIR/linux-configs/zynq_libre_linux_defconfig" "$FIRMWARE_DIR/linux/arch/arm/configs/" + +# U-Boot device tree and config +cp "$SCRIPT_DIR/uboot-dts/zynq-libre-sdr.dts" "$FIRMWARE_DIR/u-boot-xlnx/arch/arm/dts/" +cp "$SCRIPT_DIR/uboot-configs/zynq_libre_defconfig" "$FIRMWARE_DIR/u-boot-xlnx/configs/" + +# Add zynq-libre-sdr.dtb to U-Boot DTS Makefile if not present +if ! grep -q "zynq-libre-sdr.dtb" "$FIRMWARE_DIR/u-boot-xlnx/arch/arm/dts/Makefile"; then + sed -i '/zynq-pluto-sdr.dtb/a\ zynq-libre-sdr.dtb \\' "$FIRMWARE_DIR/u-boot-xlnx/arch/arm/dts/Makefile" + echo "Added zynq-libre-sdr.dtb to U-Boot DTS Makefile" +fi + +# Buildroot config +cp "$SCRIPT_DIR/buildroot-configs/zynq_libre_defconfig" "$FIRMWARE_DIR/buildroot/configs/" + +echo "LibreSDR setup complete!" +echo "Build with: make TARGET=libre" diff --git a/firmware/ori/libre/uboot-configs/zynq_libre_defconfig b/firmware/ori/libre/uboot-configs/zynq_libre_defconfig new file mode 100644 index 0000000..c33cb87 --- /dev/null +++ b/firmware/ori/libre/uboot-configs/zynq_libre_defconfig @@ -0,0 +1,62 @@ +CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="zynq_zc70x" +CONFIG_ARCH_ZYNQ=y +CONFIG_SYS_MALLOC_F_LEN=0x800 +CONFIG_DEFAULT_DEVICE_TREE="zynq-libre-sdr" +CONFIG_SPL=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_FIT_SIGNATURE=y +CONFIG_BOOTDELAY=3 +CONFIG_SYS_NO_FLASH=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="LIBRESDR> " +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_FLASH is not set +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_ZYNQ_SDHCI=y +CONFIG_CMD_MMC=y +CONFIG_SD_BOOT=y + +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_NET is not set +# CONFIG_CMD_NFS is not set +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_EMBED=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_ZYNQ_QSPI=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_VBUS_DRAW=500 +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_G_DNL_MANUFACTURER="Analog Devices Inc." +CONFIG_G_DNL_VENDOR_NUM=0x0456 +CONFIG_G_DNL_PRODUCT_NUM=0xb674 +CONFIG_REGEX=y +CONFIG_LIB_RAND=y \ No newline at end of file diff --git a/firmware/ori/libre/uboot-dts/zynq-libre-sdr.dts b/firmware/ori/libre/uboot-dts/zynq-libre-sdr.dts new file mode 100644 index 0000000..8121518 --- /dev/null +++ b/firmware/ori/libre/uboot-dts/zynq-libre-sdr.dts @@ -0,0 +1,111 @@ +/* + * LIBRE board DTS + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/dts-v1/; +#include "zynq-7000.dtsi" + +/ { + model = "LibreSDR"; + compatible = "xlnx,zynq-7000"; + + aliases { + ethernet0 = &gem0; + serial0 = &uart0; + spi0 = &qspi; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x40000000>; + }; + + chosen { + bootargs = "earlyprintk"; + linux,stdout-path = &uart0; + stdout-path = &uart0; + }; + + usb_phy0: phy0 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + button { + label = "Button"; + gpios = <&gpio0 14 0>; + linux,code = <103>; /* up */ + wakeup-source; + autorepeat; + }; + + }; + + +}; + + + + + + +&qspi { + status = "okay"; + is-dual = <0>; + num-cs = <1>; + flash@0 { + compatible = "n25q512a","micron,m25p80"; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <50000000>; + #address-cells = <1>; + #size-cells = <1>; + partition@qspi-fsbl-uboot { + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; /* 1M */ + }; + partition@qspi-uboot-env { + label = "qspi-uboot-env"; + reg = <0x100000 0x20000>; /* 128k */ + }; + partition@qspi-nvmfs { + label = "qspi-nvmfs"; + reg = <0x120000 0xE0000>; /* 1M */ + }; + partition@qspi-linux { + label = "qspi-linux"; + reg = <0x200000 0x1E00000>; /* 30M */ + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; + usb-phy = <&usb_phy0>; +}; +&sdhci0 { + u-boot,dm-pre-reloc; + status = "okay"; + +}; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy0>; + + ethernet_phy0: ethernet-phy@0 { + reg = <0>; + reset-gpios = <&gpio0 46 0>; + }; +}; \ No newline at end of file diff --git a/firmware/scripts/libre.its b/firmware/scripts/libre.its new file mode 100644 index 0000000..37df960 --- /dev/null +++ b/firmware/scripts/libre.its @@ -0,0 +1,70 @@ +/* + * U-Boot uImage source file for LibreSDR + */ + +/dts-v1/; + +/ { + description = "Configuration to load fpga before Kernel"; + magic = "ITB PlutoSDR (ADALM-PLUTO)"; + #address-cells = <1>; + images { + + fdt@1 { + description = "zynq-libre"; + data = /incbin/("../build/zynq-libre.dtb"); + type = "flat_dt"; + arch = "arm"; + compression = "none"; + }; + + fpga@1 { + description = "FPGA"; + data = /incbin/("../build/system_top.bit"); + type = "fpga"; + arch = "arm"; + compression = "none"; + load = <0xF000000>; + hash@1 { + algo = "md5"; + }; + }; + + linux_kernel@1 { + description = "Linux"; + data = /incbin/("../build/zImage"); + type = "kernel"; + arch = "arm"; + os = "linux"; + compression = "none"; + load = <0x8000>; + entry = <0x8000>; + hash@1 { + algo = "md5"; + }; + }; + + ramdisk@1 { + description = "Ramdisk"; + data = /incbin/("../build/rootfs.cpio.gz"); + type = "ramdisk"; + arch = "arm"; + os = "linux"; + compression = "gzip"; + hash@1 { + algo = "md5"; + }; + }; + }; + + configurations { + default = "config@0"; + config@0 { + description = "Linux with fpga LibreSDR"; + fdt = "fdt@1"; + kernel = "linux_kernel@1"; + ramdisk = "ramdisk@1"; + fpga = "fpga@1"; + }; + }; +}; diff --git a/firmware/scripts/libre.mk b/firmware/scripts/libre.mk new file mode 100644 index 0000000..2fb18e9 --- /dev/null +++ b/firmware/scripts/libre.mk @@ -0,0 +1,7 @@ +# Target specific constants go here + +TARGET_DTS_FILES:= zynq-libre.dtb +COMPLETE_NAME:=LIBRE +ZIP_ARCHIVE_PREFIX:=libresdr +DEVICE_VID:=0x0456 +DEVICE_PID:=0xb673 diff --git a/projects/libre/Makefile b/projects/libre/Makefile new file mode 100644 index 0000000..750d349 --- /dev/null +++ b/projects/libre/Makefile @@ -0,0 +1,24 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := libre + +M_DEPS += ../common/xilinx/adi_fir_filter_constr.xdc +M_DEPS += ../common/xilinx/adi_fir_filter_bd.tcl +M_DEPS += ../../library/util_cdc/sync_bits.v +M_DEPS += ../../library/common/util_pulse_gen.v +M_DEPS += ../../library/common/ad_iobuf.v +M_DEPS += ../../library/common/ad_bus_mux.v +M_DEPS += ../../library/axi_tdd/scripts/axi_tdd.tcl +M_DEPS += ../../library/axi_ad9361/axi_ad9361_delay.tcl + +LIB_DEPS += axi_ad9361 +LIB_DEPS += axi_dmac +LIB_DEPS += axi_tdd +LIB_DEPS += util_pack/util_cpack2 +LIB_DEPS += util_pack/util_upack2 + +include ../scripts/project-xilinx.mk diff --git a/projects/libre/Readme.md b/projects/libre/Readme.md new file mode 100755 index 0000000..c42a660 --- /dev/null +++ b/projects/libre/Readme.md @@ -0,0 +1,10 @@ +# PLUTO HDL Project + +Here are some pointers to help you: + * [Board Product Page](https://www.analog.com/adalm-pluto) + * [Board Product Page](https://www.analog.com/cn0566) + * Parts : [RF Agile Transceiver](https://www.analog.com/ad9363) + * Project Doc: https://wiki.analog.com/university/tools/pluto + * Project Doc: https://wiki.analog.com/resources/eval/user-guides/circuits-from-the-lab/cn0566 + * HDL Doc: https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/reference_hdl + * Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers/iio-transceiver/ad9361 diff --git a/projects/libre/system_bd.tcl b/projects/libre/system_bd.tcl new file mode 100644 index 0000000..21813c3 --- /dev/null +++ b/projects/libre/system_bd.tcl @@ -0,0 +1,395 @@ +# create board design + + +source $ad_hdl_dir/projects/common/xilinx/adi_fir_filter_bd.tcl + +# default ports + +create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr +create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 fixed_io + +create_bd_port -dir O spi0_csn_2_o +create_bd_port -dir O spi0_csn_1_o +create_bd_port -dir O spi0_csn_0_o +create_bd_port -dir I spi0_csn_i +create_bd_port -dir I spi0_clk_i +create_bd_port -dir O spi0_clk_o +create_bd_port -dir I spi0_sdo_i +create_bd_port -dir O spi0_sdo_o +create_bd_port -dir I spi0_sdi_i + +create_bd_port -dir I -from 24 -to 0 gpio_i +create_bd_port -dir O -from 24 -to 0 gpio_o +create_bd_port -dir O -from 24 -to 0 gpio_t + +create_bd_port -dir O spi_csn_o +create_bd_port -dir I spi_csn_i +create_bd_port -dir I spi_clk_i +create_bd_port -dir O spi_clk_o +create_bd_port -dir I spi_sdo_i +create_bd_port -dir O spi_sdo_o +create_bd_port -dir I spi_sdi_i + +# instance: sys_ps7 + +ad_ip_instance processing_system7 sys_ps7 + +# ps7 settings + +ad_ip_parameter sys_ps7 CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 3.3V} +ad_ip_parameter sys_ps7 CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 2.5V} +ad_ip_parameter sys_ps7 CONFIG.PCW_PACKAGE_NAME clg400 +ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_MIO_GPIO_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_PERIPHERAL_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_ENET0_IO "MIO 16 .. 27" +ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_GRP_MDIO_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_GRP_MDIO_IO "MIO 52 .. 53" +ad_ip_parameter sys_ps7 CONFIG.PCW_ENET_RESET_SELECT "Separate reset pins" +ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_RESET_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_RESET_IO "MIO 46" +ad_ip_parameter sys_ps7 CONFIG.PCW_USE_S_AXI_HP1 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_USE_S_AXI_HP2 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_EN_CLK1_PORT 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_EN_RST1_PORT 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ 100.0 +ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ 200.0 +ad_ip_parameter sys_ps7 CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ 50 +ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_EMIO_GPIO_IO 25 +ad_ip_parameter sys_ps7 CONFIG.PCW_SPI1_PERIPHERAL_ENABLE 0 +ad_ip_parameter sys_ps7 CONFIG.PCW_I2C0_PERIPHERAL_ENABLE 0 +ad_ip_parameter sys_ps7 CONFIG.PCW_SD0_PERIPHERAL_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ 50 +ad_ip_parameter sys_ps7 CONFIG.PCW_UART0_PERIPHERAL_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_UART0_UART0_IO {MIO 14 .. 15} +ad_ip_parameter sys_ps7 CONFIG.PCW_I2C1_PERIPHERAL_ENABLE 0 +ad_ip_parameter sys_ps7 CONFIG.PCW_QSPI_PERIPHERAL_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_SPI0_PERIPHERAL_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_SPI0_SPI0_IO EMIO +ad_ip_parameter sys_ps7 CONFIG.PCW_TTC0_PERIPHERAL_ENABLE 0 +ad_ip_parameter sys_ps7 CONFIG.PCW_USE_FABRIC_INTERRUPT 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_USB0_PERIPHERAL_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_MIO_GPIO_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_MIO_GPIO_IO MIO +ad_ip_parameter sys_ps7 CONFIG.PCW_USB0_RESET_IO {MIO 47} +ad_ip_parameter sys_ps7 CONFIG.PCW_USB0_RESET_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_IRQ_F2P_INTR 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_IRQ_F2P_MODE REVERSE +ad_ip_parameter sys_ps7 CONFIG.PCW_MIO_0_PULLUP {enabled} +ad_ip_parameter sys_ps7 CONFIG.PCW_MIO_9_PULLUP {enabled} +ad_ip_parameter sys_ps7 CONFIG.PCW_MIO_10_PULLUP {enabled} +ad_ip_parameter sys_ps7 CONFIG.PCW_MIO_11_PULLUP {enabled} +ad_ip_parameter sys_ps7 CONFIG.PCW_MIO_48_PULLUP {enabled} +ad_ip_parameter sys_ps7 CONFIG.PCW_MIO_49_PULLUP {disabled} +ad_ip_parameter sys_ps7 CONFIG.PCW_MIO_53_PULLUP {enabled} +ad_ip_parameter sys_ps7 CONFIG.PCW_APU_PERIPHERAL_FREQMHZ 750 + +# DDR MT41K256M16 HA-125 (32M, 16bit, 8banks) + +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ 525 +# ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41J256M16 RE-125} +# Use Custom memory parameters to allow tuning DDR timings. +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_PARTNO {Custom} +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15} +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_CL {7} +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_CWL {5} +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_T_RCD {7} +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_T_RP {7} +# Increase DDR timing parameters to allow more DDR overclock. +# Tested 7-5-7-7 for 625 MHz, 8-6-8-8 for 700 MHz, 9-7-9-9 for 750 MHz, 10-7-10-10 for 775 MHz. +# ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_CL {9} +# ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_CWL {7} +# ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_T_RCD {9} +# ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_T_RP {9} +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_T_RC {48.91} +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0} +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0} +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.048} +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.050} +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.241} +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.240} +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_ECC {Disabled} +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {32 Bit} +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits} +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1} +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1} +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1} +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0} + +# ad_ip_parameter sys_ps7 CONFIG.PCW_OVERRIDE_BASIC_CLOCK 1 +# ad_ip_parameter sys_ps7 CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 3 +# ad_ip_parameter sys_ps7 CONFIG.PCW_ARMPLL_CTRL_FBDIV 52 +# ad_ip_parameter sys_ps7 CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 3 +# ad_ip_parameter sys_ps7 CONFIG.PCW_DDRPLL_CTRL_FBDIV 32 + +ad_ip_instance xlconcat sys_concat_intc +ad_ip_parameter sys_concat_intc CONFIG.NUM_PORTS 16 + +ad_ip_instance proc_sys_reset sys_rstgen +ad_ip_parameter sys_rstgen CONFIG.C_EXT_RST_WIDTH 1 + +# system reset/clock definitions + +# add external spi + +ad_ip_instance axi_quad_spi axi_spi +ad_ip_parameter axi_spi CONFIG.C_USE_STARTUP 0 +ad_ip_parameter axi_spi CONFIG.C_NUM_SS_BITS 1 +ad_ip_parameter axi_spi CONFIG.C_SCK_RATIO 8 + +ad_connect sys_cpu_clk sys_ps7/FCLK_CLK0 +ad_connect sys_200m_clk sys_ps7/FCLK_CLK1 +ad_connect sys_cpu_reset sys_rstgen/peripheral_reset +ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn +ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk +ad_connect sys_rstgen/ext_reset_in sys_ps7/FCLK_RESET0_N + +# interface connections + +ad_connect ddr sys_ps7/DDR +ad_connect gpio_i sys_ps7/GPIO_I +ad_connect gpio_o sys_ps7/GPIO_O +ad_connect gpio_t sys_ps7/GPIO_T +ad_connect fixed_io sys_ps7/FIXED_IO + +# ps7 spi connections + +ad_connect spi0_csn_2_o sys_ps7/SPI0_SS2_O +ad_connect spi0_csn_1_o sys_ps7/SPI0_SS1_O +ad_connect spi0_csn_0_o sys_ps7/SPI0_SS_O +ad_connect spi0_csn_i sys_ps7/SPI0_SS_I +ad_connect spi0_clk_i sys_ps7/SPI0_SCLK_I +ad_connect spi0_clk_o sys_ps7/SPI0_SCLK_O +ad_connect spi0_sdo_i sys_ps7/SPI0_MOSI_I +ad_connect spi0_sdo_o sys_ps7/SPI0_MOSI_O +ad_connect spi0_sdi_i sys_ps7/SPI0_MISO_I + +# axi spi connections + +ad_connect sys_cpu_clk axi_spi/ext_spi_clk +ad_connect spi_csn_i axi_spi/ss_i +ad_connect spi_csn_o axi_spi/ss_o +ad_connect spi_clk_i axi_spi/sck_i +ad_connect spi_clk_o axi_spi/sck_o +ad_connect spi_sdo_i axi_spi/io0_i +ad_connect spi_sdo_o axi_spi/io0_o +ad_connect spi_sdi_i axi_spi/io1_i + +# interrupts + +ad_connect sys_concat_intc/dout sys_ps7/IRQ_F2P +ad_connect sys_concat_intc/In15 GND +ad_connect sys_concat_intc/In14 GND +ad_connect sys_concat_intc/In13 GND +ad_connect sys_concat_intc/In12 GND +ad_connect sys_concat_intc/In11 GND +ad_connect sys_concat_intc/In10 GND +ad_connect sys_concat_intc/In9 GND +ad_connect sys_concat_intc/In8 GND +ad_connect sys_concat_intc/In7 GND +ad_connect sys_concat_intc/In6 GND +ad_connect sys_concat_intc/In5 GND +ad_connect sys_concat_intc/In4 GND +ad_connect sys_concat_intc/In3 GND +ad_connect sys_concat_intc/In2 GND +ad_connect sys_concat_intc/In1 GND +ad_connect sys_concat_intc/In0 GND + +# iic + +create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_main + +ad_ip_instance axi_iic axi_iic_main + +ad_connect iic_main axi_iic_main/iic +ad_cpu_interconnect 0x41600000 axi_iic_main +ad_cpu_interrupt ps-15 mb-15 axi_iic_main/iic2intc_irpt + +# ad9361 + +create_bd_port -dir I rx_clk_in_p +create_bd_port -dir I rx_clk_in_n +create_bd_port -dir I rx_frame_in_p +create_bd_port -dir I rx_frame_in_n +create_bd_port -dir I -from 5 -to 0 rx_data_in_p +create_bd_port -dir I -from 5 -to 0 rx_data_in_n + +create_bd_port -dir O tx_clk_out_p +create_bd_port -dir O tx_clk_out_n +create_bd_port -dir O tx_frame_out_p +create_bd_port -dir O tx_frame_out_n +create_bd_port -dir O -from 5 -to 0 tx_data_out_p +create_bd_port -dir O -from 5 -to 0 tx_data_out_n + +create_bd_port -dir O enable +create_bd_port -dir O txnrx +create_bd_port -dir I up_enable +create_bd_port -dir I up_txnrx + +# ad9361 core(s) + +ad_ip_instance axi_ad9361 axi_ad9361 +ad_ip_parameter axi_ad9361 CONFIG.ID 0 +ad_ip_parameter axi_ad9361 CONFIG.CMOS_OR_LVDS_N 0 +ad_ip_parameter axi_ad9361 CONFIG.MODE_1R1T 0 +ad_ip_parameter axi_ad9361 CONFIG.ADC_INIT_DELAY 30 + +ad_ip_instance axi_dmac axi_ad9361_dac_dma +ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_TYPE_SRC 0 +ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_TYPE_DEST 1 +ad_ip_parameter axi_ad9361_dac_dma CONFIG.CYCLIC 1 +ad_ip_parameter axi_ad9361_dac_dma CONFIG.AXI_SLICE_SRC 0 +ad_ip_parameter axi_ad9361_dac_dma CONFIG.AXI_SLICE_DEST 0 +ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_2D_TRANSFER 0 +ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_DATA_WIDTH_DEST 64 + +ad_add_interpolation_filter "tx_fir_interpolator" 8 2 1 {61.44} {7.68} \ + "$ad_hdl_dir/library/util_fir_int/coefile_int.coe" +ad_ip_instance xlslice interp_slice +ad_ip_instance util_upack2 tx_upack + +ad_ip_instance axi_dmac axi_ad9361_adc_dma +ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_TYPE_SRC 2 +ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_TYPE_DEST 0 +ad_ip_parameter axi_ad9361_adc_dma CONFIG.CYCLIC 0 +ad_ip_parameter axi_ad9361_adc_dma CONFIG.SYNC_TRANSFER_START 0 +ad_ip_parameter axi_ad9361_adc_dma CONFIG.AXI_SLICE_SRC 0 +ad_ip_parameter axi_ad9361_adc_dma CONFIG.AXI_SLICE_DEST 0 +ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_2D_TRANSFER 0 +ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_DATA_WIDTH_SRC 64 + +ad_add_decimation_filter "rx_fir_decimator" 8 2 1 {61.44} {61.44} \ + "$ad_hdl_dir/library/util_fir_int/coefile_int.coe" +ad_ip_instance xlslice decim_slice +ad_ip_instance util_cpack2 cpack + +# connections + +ad_connect rx_clk_in_p axi_ad9361/rx_clk_in_p +ad_connect rx_clk_in_n axi_ad9361/rx_clk_in_n +ad_connect rx_frame_in_p axi_ad9361/rx_frame_in_p +ad_connect rx_frame_in_n axi_ad9361/rx_frame_in_n +ad_connect rx_data_in_p axi_ad9361/rx_data_in_p +ad_connect rx_data_in_n axi_ad9361/rx_data_in_n +ad_connect tx_clk_out_p axi_ad9361/tx_clk_out_p +ad_connect tx_clk_out_n axi_ad9361/tx_clk_out_n +ad_connect tx_frame_out_p axi_ad9361/tx_frame_out_p +ad_connect tx_frame_out_n axi_ad9361/tx_frame_out_n +ad_connect tx_data_out_p axi_ad9361/tx_data_out_p +ad_connect tx_data_out_n axi_ad9361/tx_data_out_n +ad_connect enable axi_ad9361/enable +ad_connect txnrx axi_ad9361/txnrx +ad_connect up_enable axi_ad9361/up_enable +ad_connect up_txnrx axi_ad9361/up_txnrx + +ad_connect axi_ad9361/tdd_sync GND +ad_connect sys_200m_clk axi_ad9361/delay_clk +ad_connect axi_ad9361/l_clk axi_ad9361/clk + +ad_connect axi_ad9361/l_clk rx_fir_decimator/aclk + +ad_connect axi_ad9361/adc_valid_i0 rx_fir_decimator/valid_in_0 +ad_connect axi_ad9361/adc_enable_i0 rx_fir_decimator/enable_in_0 +ad_connect axi_ad9361/adc_data_i0 rx_fir_decimator/data_in_0 +ad_connect axi_ad9361/adc_valid_q0 rx_fir_decimator/valid_in_1 +ad_connect axi_ad9361/adc_enable_q0 rx_fir_decimator/enable_in_1 +ad_connect axi_ad9361/adc_data_q0 rx_fir_decimator/data_in_1 + +ad_connect axi_ad9361/l_clk cpack/clk +ad_connect axi_ad9361/rst cpack/reset + +ad_connect axi_ad9361/adc_enable_i1 cpack/enable_2 +ad_connect axi_ad9361/adc_data_i1 cpack/fifo_wr_data_2 +ad_connect axi_ad9361/adc_enable_q1 cpack/enable_3 +ad_connect axi_ad9361/adc_data_q1 cpack/fifo_wr_data_3 + +ad_connect cpack/enable_0 rx_fir_decimator/enable_out_0 +ad_connect cpack/enable_1 rx_fir_decimator/enable_out_1 +ad_connect cpack/fifo_wr_data_0 rx_fir_decimator/data_out_0 +ad_connect cpack/fifo_wr_data_1 rx_fir_decimator/data_out_1 +ad_connect rx_fir_decimator/valid_out_0 cpack/fifo_wr_en + +ad_connect axi_ad9361_adc_dma/fifo_wr cpack/packed_fifo_wr +ad_connect axi_ad9361/up_adc_gpio_out decim_slice/Din +ad_connect rx_fir_decimator/active decim_slice/Dout + +ad_connect axi_ad9361/l_clk tx_fir_interpolator/aclk + +ad_connect axi_ad9361/dac_enable_i0 tx_fir_interpolator/dac_enable_0 +ad_connect axi_ad9361/dac_valid_i0 tx_fir_interpolator/dac_valid_0 +ad_connect axi_ad9361/dac_data_i0 tx_fir_interpolator/data_out_0 +ad_connect axi_ad9361/dac_enable_q0 tx_fir_interpolator/dac_enable_1 +ad_connect axi_ad9361/dac_valid_q0 tx_fir_interpolator/dac_valid_1 +ad_connect axi_ad9361/dac_data_q0 tx_fir_interpolator/data_out_1 + +ad_connect axi_ad9361/l_clk tx_upack/clk +ad_connect axi_ad9361/rst tx_upack/reset + +ad_connect tx_upack/fifo_rd_data_0 tx_fir_interpolator/data_in_0 +ad_connect tx_upack/enable_0 tx_fir_interpolator/enable_out_0 +ad_connect tx_upack/fifo_rd_data_1 tx_fir_interpolator/data_in_1 +ad_connect tx_upack/enable_1 tx_fir_interpolator/enable_out_1 + +ad_connect axi_ad9361/dac_enable_i1 tx_upack/enable_2 +ad_connect axi_ad9361/dac_data_i1 tx_upack/fifo_rd_data_2 +ad_connect axi_ad9361/dac_enable_q1 tx_upack/enable_3 +ad_connect axi_ad9361/dac_data_q1 tx_upack/fifo_rd_data_3 + +ad_connect tx_upack/s_axis axi_ad9361_dac_dma/m_axis + +ad_ip_instance util_vector_logic logic_or [list \ + C_OPERATION {or} \ + C_SIZE 1] + +ad_connect logic_or/Op1 tx_fir_interpolator/valid_out_0 +ad_connect logic_or/Op2 axi_ad9361/dac_valid_i1 +ad_connect logic_or/Res tx_upack/fifo_rd_en +ad_connect tx_upack/fifo_rd_underflow axi_ad9361/dac_dunf + +ad_connect axi_ad9361/up_dac_gpio_out interp_slice/Din +ad_connect tx_fir_interpolator/active interp_slice/Dout + +ad_connect axi_ad9361/l_clk axi_ad9361_adc_dma/fifo_wr_clk +ad_connect axi_ad9361/l_clk axi_ad9361_dac_dma/m_axis_aclk +ad_connect cpack/fifo_wr_overflow axi_ad9361/adc_dovf + +# interconnects + +ad_cpu_interconnect 0x79020000 axi_ad9361 +ad_cpu_interconnect 0x7C400000 axi_ad9361_adc_dma +ad_cpu_interconnect 0x7C420000 axi_ad9361_dac_dma +ad_cpu_interconnect 0x7C430000 axi_spi + +ad_ip_parameter sys_ps7 CONFIG.PCW_USE_S_AXI_HP1 {1} +ad_connect sys_cpu_clk sys_ps7/S_AXI_HP1_ACLK +ad_connect axi_ad9361_adc_dma/m_dest_axi sys_ps7/S_AXI_HP1 + +create_bd_addr_seg -range 0x40000000 -offset 0x00000000 \ + [get_bd_addr_spaces axi_ad9361_adc_dma/m_dest_axi] \ + [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] \ + SEG_sys_ps7_HP1_DDR_LOWOCM + +ad_ip_parameter sys_ps7 CONFIG.PCW_USE_S_AXI_HP2 {1} +ad_connect sys_cpu_clk sys_ps7/S_AXI_HP2_ACLK +ad_connect axi_ad9361_dac_dma/m_src_axi sys_ps7/S_AXI_HP2 + +create_bd_addr_seg -range 0x40000000 -offset 0x00000000 \ + [get_bd_addr_spaces axi_ad9361_dac_dma/m_src_axi] \ + [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] \ + SEG_sys_ps7_HP2_DDR_LOWOCM + +ad_connect sys_cpu_clk axi_ad9361_dac_dma/m_src_axi_aclk +ad_connect sys_cpu_clk axi_ad9361_adc_dma/m_dest_axi_aclk +ad_connect sys_cpu_resetn axi_ad9361_adc_dma/m_dest_axi_aresetn +ad_connect sys_cpu_resetn axi_ad9361_dac_dma/m_src_axi_aresetn + +# interrupts + +ad_cpu_interrupt ps-13 mb-13 axi_ad9361_adc_dma/irq +ad_cpu_interrupt ps-12 mb-12 axi_ad9361_dac_dma/irq +ad_cpu_interrupt ps-11 mb-11 axi_spi/ip2intc_irpt diff --git a/projects/libre/system_constr.xdc b/projects/libre/system_constr.xdc new file mode 100644 index 0000000..12547cb --- /dev/null +++ b/projects/libre/system_constr.xdc @@ -0,0 +1,133 @@ +# LibreSDR XC7Z020-CLG400 Pin Constraints +# Extracted from hz12opensource/libresdr hdl.diff patch + +# ============================================================================= +# Clock Constraints +# ============================================================================= + +# AD9363 LVDS RX clock (125 MHz max) +create_clock -name rx_clk -period 8.000 [get_ports rx_clk_in_p] + +# PS7 fabric clocks +create_clock -name clk_fpga_0 -period 10 [get_pins "i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[0]"] +create_clock -name clk_fpga_1 -period 5 [get_pins "i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[1]"] + +# SPI clock +create_clock -name spi0_clk -period 40 [get_pins -hier */EMIOSPI0SCLKO] + +# ============================================================================= +# AD9363 LVDS Interface - Bank 34 (2.5V) +# ============================================================================= + +# RX Clock (differential) +set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports rx_clk_in_p] +set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports rx_clk_in_n] + +# RX Frame (differential) +set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports rx_frame_in_p] +set_property -dict {PACKAGE_PIN U19 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports rx_frame_in_n] + +# RX Data (differential) [5:0] +set_property -dict {PACKAGE_PIN V20 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports {rx_data_in_p[0]}] +set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports {rx_data_in_n[0]}] +set_property -dict {PACKAGE_PIN T20 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports {rx_data_in_p[1]}] +set_property -dict {PACKAGE_PIN U20 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports {rx_data_in_n[1]}] +set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports {rx_data_in_p[2]}] +set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports {rx_data_in_n[2]}] +set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports {rx_data_in_p[3]}] +set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports {rx_data_in_n[3]}] +set_property -dict {PACKAGE_PIN W18 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports {rx_data_in_p[4]}] +set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports {rx_data_in_n[4]}] +set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports {rx_data_in_p[5]}] +set_property -dict {PACKAGE_PIN Y19 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports {rx_data_in_n[5]}] + +# TX Clock (differential) +set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVDS_25} [get_ports tx_clk_out_p] +set_property -dict {PACKAGE_PIN P19 IOSTANDARD LVDS_25} [get_ports tx_clk_out_n] + +# TX Frame (differential) +set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVDS_25} [get_ports tx_frame_out_p] +set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVDS_25} [get_ports tx_frame_out_n] + +# TX Data (differential) [5:0] +set_property -dict {PACKAGE_PIN W14 IOSTANDARD LVDS_25} [get_ports {tx_data_out_p[0]}] +set_property -dict {PACKAGE_PIN Y14 IOSTANDARD LVDS_25} [get_ports {tx_data_out_n[0]}] +set_property -dict {PACKAGE_PIN W15 IOSTANDARD LVDS_25} [get_ports {tx_data_out_p[1]}] +set_property -dict {PACKAGE_PIN W16 IOSTANDARD LVDS_25} [get_ports {tx_data_out_n[1]}] +set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVDS_25} [get_ports {tx_data_out_p[2]}] +set_property -dict {PACKAGE_PIN U15 IOSTANDARD LVDS_25} [get_ports {tx_data_out_n[2]}] +set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVDS_25} [get_ports {tx_data_out_p[3]}] +set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVDS_25} [get_ports {tx_data_out_n[3]}] +set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVDS_25} [get_ports {tx_data_out_p[4]}] +set_property -dict {PACKAGE_PIN W13 IOSTANDARD LVDS_25} [get_ports {tx_data_out_n[4]}] +set_property -dict {PACKAGE_PIN T12 IOSTANDARD LVDS_25} [get_ports {tx_data_out_p[5]}] +set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVDS_25} [get_ports {tx_data_out_n[5]}] + +# ============================================================================= +# AD9363 Control Signals +# ============================================================================= + +# Enable and TxNRx +set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS25} [get_ports enable] +set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS25} [get_ports txnrx] + +# GPIO Reset and AGC +set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS25} [get_ports gpio_resetb] +set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS25} [get_ports gpio_en_agc] + +# ============================================================================= +# GPIO Status [7:0] - Bank 34 (2.5V) +# ============================================================================= + +set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS25} [get_ports {gpio_status[0]}] +set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS25} [get_ports {gpio_status[1]}] +set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS25} [get_ports {gpio_status[2]}] +set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS25} [get_ports {gpio_status[3]}] +set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS25} [get_ports {gpio_status[4]}] +set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS33} [get_ports {gpio_status[5]}] +set_property -dict {PACKAGE_PIN U13 IOSTANDARD LVCMOS25} [get_ports {gpio_status[6]}] +set_property -dict {PACKAGE_PIN V13 IOSTANDARD LVCMOS25} [get_ports {gpio_status[7]}] + +# ============================================================================= +# GPIO Control [3:0] - Mixed Banks +# ============================================================================= + +set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS25} [get_ports {gpio_ctl[0]}] +set_property -dict {PACKAGE_PIN Y11 IOSTANDARD LVCMOS33} [get_ports {gpio_ctl[1]}] +set_property -dict {PACKAGE_PIN V10 IOSTANDARD LVCMOS33} [get_ports {gpio_ctl[2]}] +set_property -dict {PACKAGE_PIN U9 IOSTANDARD LVCMOS33} [get_ports {gpio_ctl[3]}] + +# ============================================================================= +# I2C Interface - Bank 35 (3.3V) +# ============================================================================= + +set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS33 PULLUP true} [get_ports iic_scl] +set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS33 PULLUP true} [get_ports iic_sda] + +# ============================================================================= +# SPI Interface (AD9363) - Bank 34 (2.5V) +# ============================================================================= + +set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports spi_csn] +set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS25} [get_ports spi_clk] +set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS25} [get_ports spi_mosi] +set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS25} [get_ports spi_miso] + +# ============================================================================= +# PL SPI Interface - Bank 35 (3.3V) +# ============================================================================= + +set_property -dict {PACKAGE_PIN K14 IOSTANDARD LVCMOS33} [get_ports pl_spi_clk_o] +set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS33} [get_ports pl_spi_miso] +set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS33} [get_ports pl_spi_mosi] + +# ============================================================================= +# Timing Exceptions +# ============================================================================= + +# False paths for GPIO outputs from axi_ad9361 +set_false_path -from [get_pins i_system_wrapper/system_i/axi_ad9361/inst/i_tdd/i_tdd_control/tdd_enable_reg/C] +set_false_path -from [get_pins i_system_wrapper/system_i/axi_ad9361/inst/i_tdd/i_tdd_control/tdd_tx_only_reg/C] +set_false_path -from [get_pins i_system_wrapper/system_i/axi_ad9361/inst/i_tdd/i_tdd_control/tdd_rx_only_reg/C] +set_false_path -from [get_pins i_system_wrapper/system_i/axi_ad9361/inst/i_tdd/i_tdd_control/tdd_gated_tx_dmapath_reg/C] +set_false_path -from [get_pins i_system_wrapper/system_i/axi_ad9361/inst/i_tdd/i_tdd_control/tdd_gated_rx_dmapath_reg/C] diff --git a/projects/libre/system_project.tcl b/projects/libre/system_project.tcl new file mode 100644 index 0000000..43e2e58 --- /dev/null +++ b/projects/libre/system_project.tcl @@ -0,0 +1,14 @@ +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +adi_project_create libre 0 {} "xc7z020clg400-2" + +adi_project_files libre [list \ + "system_top.v" \ + "system_constr.xdc" \ + "$ad_hdl_dir/library/common/ad_iobuf.v"] + +set_property is_enabled false [get_files *system_sys_ps7_0.xdc] +adi_project_run libre +source $ad_hdl_dir/library/axi_ad9361/axi_ad9361_delay.tcl diff --git a/projects/libre/system_top.v b/projects/libre/system_top.v new file mode 100644 index 0000000..63c4413 --- /dev/null +++ b/projects/libre/system_top.v @@ -0,0 +1,183 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, + + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, + + inout iic_scl, + inout iic_sda, + + input rx_clk_in_p, + input rx_clk_in_n, + input rx_frame_in_p, + input rx_frame_in_n, + input [ 5:0] rx_data_in_p, + input [ 5:0] rx_data_in_n, + output tx_clk_out_p, + output tx_clk_out_n, + output tx_frame_out_p, + output tx_frame_out_n, + output [ 5:0] tx_data_out_p, + output [ 5:0] tx_data_out_n, + + output enable, + output txnrx, + + inout gpio_resetb, + inout gpio_en_agc, + inout [ 3:0] gpio_ctl, + inout [ 7:0] gpio_status, + + output spi_csn, + output spi_clk, + output spi_mosi, + input spi_miso, + + output pl_spi_clk_o, + output pl_spi_mosi, + input pl_spi_miso + + ); + + // internal signals + + wire [24:0] gpio_i; + wire [24:0] gpio_o; + wire [24:0] gpio_t; + + // instantiations + + ad_iobuf #(.DATA_WIDTH(14)) i_iobuf ( + .dio_t (gpio_t[13:0]), + .dio_i (gpio_o[13:0]), + .dio_o (gpio_i[13:0]), + .dio_p ({ gpio_resetb, // 13:13 + gpio_en_agc, // 12:12 + gpio_ctl, // 11: 8 + gpio_status})); // 7: 0 + + assign gpio_i[16:14] = gpio_o[16:14]; + + system_wrapper i_system_wrapper ( + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .enable (enable), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .iic_main_scl_io (iic_scl), + .iic_main_sda_io (iic_sda), + .rx_clk_in_p (rx_clk_in_p), + .rx_clk_in_n (rx_clk_in_n), + .rx_data_in_p (rx_data_in_p), + .rx_data_in_n (rx_data_in_n), + .rx_frame_in_p (rx_frame_in_p), + .rx_frame_in_n (rx_frame_in_n), + + .spi0_clk_i (1'b0), + .spi0_clk_o (spi_clk), + .spi0_csn_0_o (spi_csn), + .spi0_csn_1_o (), + .spi0_csn_2_o (), + .spi0_csn_i (1'b1), + .spi0_sdi_i (spi_miso), + .spi0_sdo_i (1'b0), + .spi0_sdo_o (spi_mosi), + + .spi_clk_i(1'b0), + .spi_clk_o(pl_spi_clk_o), + .spi_csn_i(1'b1), + .spi_csn_o(), + .spi_sdi_i(pl_spi_miso), + .spi_sdo_i(1'b0), + .spi_sdo_o(pl_spi_mosi), + + .tx_clk_out_p (tx_clk_out_p), + .tx_clk_out_n (tx_clk_out_n), + .tx_data_out_p (tx_data_out_p), + .tx_data_out_n (tx_data_out_n), + .tx_frame_out_p (tx_frame_out_p), + .tx_frame_out_n (tx_frame_out_n), + .txnrx (txnrx), + .up_enable (gpio_o[15]), + .up_txnrx (gpio_o[16])); + +endmodule + +// *************************************************************************** +// *************************************************************************** From 91bd71617708263aca1a306803982524066eb3bd Mon Sep 17 00:00:00 2001 From: Abraxas3d Date: Mon, 1 Dec 2025 18:24:46 -0800 Subject: [PATCH 55/60] Improve the LibreSDR build documentation and setup script. The .xsa file was not copying over cleanly and the build was failing. --- firmware/ori/libre/setup_libre.sh | 30 +++++++++++++---- projects/libre/README.md | 54 +++++++++++++++++++++++++++++++ 2 files changed, 78 insertions(+), 6 deletions(-) create mode 100644 projects/libre/README.md diff --git a/firmware/ori/libre/setup_libre.sh b/firmware/ori/libre/setup_libre.sh index f86596e..aea5ed4 100755 --- a/firmware/ori/libre/setup_libre.sh +++ b/firmware/ori/libre/setup_libre.sh @@ -2,28 +2,46 @@ # Setup script to install LibreSDR support files into submodules # Run this after cloning the repo and initializing submodules +set -e + SCRIPT_DIR="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)" FIRMWARE_DIR="$(dirname "$(dirname "$SCRIPT_DIR")")" -echo "Installing LibreSDR files..." +echo "==========================================" +echo "LibreSDR Setup for pluto_msk" +echo "==========================================" -# Linux device tree and config +echo "Installing Linux device tree and config..." cp "$SCRIPT_DIR/linux-dts/zynq-libre.dts" "$FIRMWARE_DIR/linux/arch/arm/boot/dts/" cp "$SCRIPT_DIR/linux-dts/zynq-libre.dtsi" "$FIRMWARE_DIR/linux/arch/arm/boot/dts/" cp "$SCRIPT_DIR/linux-configs/zynq_libre_linux_defconfig" "$FIRMWARE_DIR/linux/arch/arm/configs/" -# U-Boot device tree and config +echo "Installing U-Boot device tree and config..." cp "$SCRIPT_DIR/uboot-dts/zynq-libre-sdr.dts" "$FIRMWARE_DIR/u-boot-xlnx/arch/arm/dts/" cp "$SCRIPT_DIR/uboot-configs/zynq_libre_defconfig" "$FIRMWARE_DIR/u-boot-xlnx/configs/" # Add zynq-libre-sdr.dtb to U-Boot DTS Makefile if not present if ! grep -q "zynq-libre-sdr.dtb" "$FIRMWARE_DIR/u-boot-xlnx/arch/arm/dts/Makefile"; then sed -i '/zynq-pluto-sdr.dtb/a\ zynq-libre-sdr.dtb \\' "$FIRMWARE_DIR/u-boot-xlnx/arch/arm/dts/Makefile" - echo "Added zynq-libre-sdr.dtb to U-Boot DTS Makefile" + echo " Added zynq-libre-sdr.dtb to U-Boot DTS Makefile" fi -# Buildroot config +echo "Installing Buildroot config..." cp "$SCRIPT_DIR/buildroot-configs/zynq_libre_defconfig" "$FIRMWARE_DIR/buildroot/configs/" +echo "" +echo "==========================================" echo "LibreSDR setup complete!" -echo "Build with: make TARGET=libre" +echo "==========================================" +echo "" +echo "To build LibreSDR firmware:" +echo "" +echo " Option 1 - Build HDL first (requires Vivado, ~30 min):" +echo " cd pluto_msk/projects/libre && make" +echo " cd pluto_msk/firmware" +echo " make TARGET=libre" +echo "" +echo " Option 2 - Use pre-built XSA:" +echo " cd pluto_msk/firmware" +echo " make TARGET=libre XSA_FILE=/path/to/system_top.xsa" +echo "" diff --git a/projects/libre/README.md b/projects/libre/README.md new file mode 100644 index 0000000..28a8491 --- /dev/null +++ b/projects/libre/README.md @@ -0,0 +1,54 @@ +# LibreSDR Support + +LibreSDR is a PlutoSDR-compatible board with upgraded hardware: +- **FPGA**: XC7Z020-CLG400 (53,200 LUTs vs PlutoSDR's 17,600) +- **RF**: AD9363 (same as PlutoSDR AD9361 but different frequency range) +- **Memory**: 1GB DDR3 +- **Interface**: LVDS (vs PlutoSDR's CMOS) + +## Building LibreSDR Firmware + +### Prerequisites +- Vivado 2022.2 (for HDL build) +- ARM cross-compiler (arm-none-linux-gnueabihf-) + +### Quick Start +```bash +# 1. Clone and init submodules +git clone --branch encoder-dev https://github.com/OpenResearchInstitute/pluto_msk.git +cd pluto_msk +git submodule update --init --recursive + +# 2. Run LibreSDR setup +cd firmware/ori/libre +./setup_libre.sh + +# 3. Build HDL (requires Vivado) +cd ../../../projects/libre +make + +# 4. Build firmware +cd ../../firmware +make TARGET=libre +``` + +### Using Pre-built XSA + +If you have a pre-built XSA file (from CI or another build): +```bash +cd firmware +make TARGET=libre XSA_FILE=/path/to/system_top.xsa +``` + +### Output + +Firmware files will be in `firmware/build/`: +- `libre.frm` - Main firmware image +- `boot.frm` - Boot image + +### Flashing + +Copy `libre.frm` to the LibreSDR mass storage device, or use DFU: +```bash +dfu-util -D build/libre.dfu -a firmware.dfu +``` From f57ad1570d353bbe4257e8fec416a510282406cd Mon Sep 17 00:00:00 2001 From: Abraxas3d Date: Mon, 1 Dec 2025 18:36:23 -0800 Subject: [PATCH 56/60] Fix LibreSDR project paths for auto-build - Fix projects/libre/Makefile paths to use ../../hdl/projects/scripts/ - Add libre XSA build block to firmware/Makefile Now 'make TARGET=libre' auto-builds HDL like pluto does. --- firmware/Makefile | 4 ++++ projects/libre/Makefile | 21 +++++++++++---------- 2 files changed, 15 insertions(+), 10 deletions(-) diff --git a/firmware/Makefile b/firmware/Makefile index 4b82183..67bfefd 100644 --- a/firmware/Makefile +++ b/firmware/Makefile @@ -175,6 +175,10 @@ ifeq ($(TARGET),e200) bash -c "source $(VIVADO_SETTINGS) && make -C ../hdl/projects/pluto-ori-e200 && cp ../hdl/projects/pluto-ori-e200/e200.sdk/system_top.xsa $@" unzip -l $@ | grep -q ps7_init || cp ../hdl/projects/pluto-ori-e200/e200.srcs/sources_1/bd/system/ip/system_sys_ps7_0/ps7_init* build/ endif +ifeq ($(TARGET),libre) + bash -c "source $(VIVADO_SETTINGS) && make -C ../projects/libre && cp ../projects/libre/libre.sdk/system_top.xsa $@" + unzip -l $@ | grep -q ps7_init || cp ../projects/libre/libre.srcs/sources_1/bd/system/ip/system_sys_ps7_0/ps7_init* build/ +endif #bash -c "source $(VIVADO_SETTINGS) && make -C ../hdl/projects/pluto-ori-plus" endif diff --git a/projects/libre/Makefile b/projects/libre/Makefile index 750d349..f965839 100644 --- a/projects/libre/Makefile +++ b/projects/libre/Makefile @@ -3,17 +3,18 @@ ### SPDX short identifier: BSD-1-Clause ## Auto-generated, do not modify! #################################################################################### - +export ADI_IGNORE_VERSION_CHECK = 1 +export ADI_GENERATE_UTILIZATION = 1 PROJECT_NAME := libre -M_DEPS += ../common/xilinx/adi_fir_filter_constr.xdc -M_DEPS += ../common/xilinx/adi_fir_filter_bd.tcl -M_DEPS += ../../library/util_cdc/sync_bits.v -M_DEPS += ../../library/common/util_pulse_gen.v -M_DEPS += ../../library/common/ad_iobuf.v -M_DEPS += ../../library/common/ad_bus_mux.v -M_DEPS += ../../library/axi_tdd/scripts/axi_tdd.tcl -M_DEPS += ../../library/axi_ad9361/axi_ad9361_delay.tcl +M_DEPS += ../../hdl/projects/common/xilinx/adi_fir_filter_constr.xdc +M_DEPS += ../../hdl/projects/common/xilinx/adi_fir_filter_bd.tcl +M_DEPS += ../../hdl/library/util_cdc/sync_bits.v +M_DEPS += ../../hdl/library/common/util_pulse_gen.v +M_DEPS += ../../hdl/library/common/ad_iobuf.v +M_DEPS += ../../hdl/library/common/ad_bus_mux.v +M_DEPS += ../../hdl/library/axi_tdd/scripts/axi_tdd.tcl +M_DEPS += ../../hdl/library/axi_ad9361/axi_ad9361_delay.tcl LIB_DEPS += axi_ad9361 LIB_DEPS += axi_dmac @@ -21,4 +22,4 @@ LIB_DEPS += axi_tdd LIB_DEPS += util_pack/util_cpack2 LIB_DEPS += util_pack/util_upack2 -include ../scripts/project-xilinx.mk +include ../../hdl/projects/scripts/project-xilinx.mk From 391a18a4b274fa2aa7fe56ad38f65a4eec121c83 Mon Sep 17 00:00:00 2001 From: Abraxas3d Date: Mon, 1 Dec 2025 18:49:09 -0800 Subject: [PATCH 57/60] Fix system_project.tcl path to adi_env.tcl --- projects/libre/system_project.tcl | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/projects/libre/system_project.tcl b/projects/libre/system_project.tcl index 43e2e58..4739b1b 100644 --- a/projects/libre/system_project.tcl +++ b/projects/libre/system_project.tcl @@ -1,4 +1,4 @@ -source ../../scripts/adi_env.tcl +source ../../hdl/scripts/adi_env.tcl source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl source $ad_hdl_dir/projects/scripts/adi_board.tcl @@ -10,5 +10,6 @@ adi_project_files libre [list \ "$ad_hdl_dir/library/common/ad_iobuf.v"] set_property is_enabled false [get_files *system_sys_ps7_0.xdc] + adi_project_run libre source $ad_hdl_dir/library/axi_ad9361/axi_ad9361_delay.tcl From f4a092e7ea58e0c7e8384e8533dc9ecc8caa4904 Mon Sep 17 00:00:00 2001 From: Abraxas3d Date: Mon, 1 Dec 2025 19:12:14 -0800 Subject: [PATCH 58/60] Fix libre XSA path to TARGETlibre/libre.sdk/ --- firmware/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/firmware/Makefile b/firmware/Makefile index 67bfefd..fa50f1c 100644 --- a/firmware/Makefile +++ b/firmware/Makefile @@ -176,8 +176,8 @@ ifeq ($(TARGET),e200) unzip -l $@ | grep -q ps7_init || cp ../hdl/projects/pluto-ori-e200/e200.srcs/sources_1/bd/system/ip/system_sys_ps7_0/ps7_init* build/ endif ifeq ($(TARGET),libre) - bash -c "source $(VIVADO_SETTINGS) && make -C ../projects/libre && cp ../projects/libre/libre.sdk/system_top.xsa $@" - unzip -l $@ | grep -q ps7_init || cp ../projects/libre/libre.srcs/sources_1/bd/system/ip/system_sys_ps7_0/ps7_init* build/ + bash -c "source $(VIVADO_SETTINGS) && make -C ../projects/libre && cp ../projects/libre/TARGETlibre/libre.sdk/system_top.xsa $@" + unzip -l $@ | grep -q ps7_init || cp ../projects/libre/TARGETlibre/libre.srcs/sources_1/bd/system/ip/system_sys_ps7_0/ps7_init* build/ endif #bash -c "source $(VIVADO_SETTINGS) && make -C ../hdl/projects/pluto-ori-plus" endif From b41d0d101dee5a4c127b1fc200b2561f7a5c38a9 Mon Sep 17 00:00:00 2001 From: Abraxas3d Date: Mon, 1 Dec 2025 20:30:27 -0800 Subject: [PATCH 59/60] Fix HDL build directory: clear TARGET to prevent TARGETlibre/ subdirectory --- firmware/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/firmware/Makefile b/firmware/Makefile index fa50f1c..d21245d 100644 --- a/firmware/Makefile +++ b/firmware/Makefile @@ -176,8 +176,8 @@ ifeq ($(TARGET),e200) unzip -l $@ | grep -q ps7_init || cp ../hdl/projects/pluto-ori-e200/e200.srcs/sources_1/bd/system/ip/system_sys_ps7_0/ps7_init* build/ endif ifeq ($(TARGET),libre) - bash -c "source $(VIVADO_SETTINGS) && make -C ../projects/libre && cp ../projects/libre/TARGETlibre/libre.sdk/system_top.xsa $@" - unzip -l $@ | grep -q ps7_init || cp ../projects/libre/TARGETlibre/libre.srcs/sources_1/bd/system/ip/system_sys_ps7_0/ps7_init* build/ + bash -c "source $(VIVADO_SETTINGS) && make -C ../projects/libre TARGET= && cp ../projects/libre/libre.sdk/system_top.xsa $@" + unzip -l $@ | grep -q ps7_init || cp ../projects/libre/libre.srcs/sources_1/bd/system/ip/system_sys_ps7_0/ps7_init* build/ endif #bash -c "source $(VIVADO_SETTINGS) && make -C ../hdl/projects/pluto-ori-plus" endif From 0a1cafe9128ecc81c43f97d4879be8ae25876696 Mon Sep 17 00:00:00 2001 From: Abraxas3d Date: Mon, 1 Dec 2025 21:03:20 -0800 Subject: [PATCH 60/60] Use env -u TARGET to fully unset TARGET variable for HDL sub-build --- firmware/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/firmware/Makefile b/firmware/Makefile index d21245d..540bad4 100644 --- a/firmware/Makefile +++ b/firmware/Makefile @@ -176,7 +176,7 @@ ifeq ($(TARGET),e200) unzip -l $@ | grep -q ps7_init || cp ../hdl/projects/pluto-ori-e200/e200.srcs/sources_1/bd/system/ip/system_sys_ps7_0/ps7_init* build/ endif ifeq ($(TARGET),libre) - bash -c "source $(VIVADO_SETTINGS) && make -C ../projects/libre TARGET= && cp ../projects/libre/libre.sdk/system_top.xsa $@" + bash -c "source $(VIVADO_SETTINGS) && env -u TARGET make -C ../projects/libre && cp ../projects/libre/libre.sdk/system_top.xsa $@" unzip -l $@ | grep -q ps7_init || cp ../projects/libre/libre.srcs/sources_1/bd/system/ip/system_sys_ps7_0/ps7_init* build/ endif #bash -c "source $(VIVADO_SETTINGS) && make -C ../hdl/projects/pluto-ori-plus"