TP: fix compile problem when disable TP by adding 'hastp/tp' parameter (#160)

Author: Ma-YX

src/main/scala/coupledL2/CoupledL2.scala

@@ -75,6 +75,7 @@ trait HasCoupledL2Parameters {
   val hasPrefetchBit = prefetchOpt.nonEmpty && prefetchOpt.get.hasPrefetchBit
   val hasPrefetchSrc = prefetchOpt.nonEmpty && prefetchOpt.get.hasPrefetchSrc
   val topDownOpt = if(cacheParams.elaboratedTopDown) Some(true) else None
+  val hasTPPrefetcher = prefetchOpt.nonEmpty && prefetchOpt.get.hasTPPrefetcher
 
   val enableHintGuidedGrant = true
 

src/main/scala/coupledL2/prefetch/BestOffsetPrefetch.scala

@@ -52,11 +52,13 @@ case class BOPParameters(
     90, 96, 100, 108, 120, 125, 128, 135,
     144, 150, 160, 162, 180, 192, 200, 216,
     225, 240, 243, 250/*, 256*/
-  ))
+  ),
+  hastp: Boolean = true)
     extends PrefetchParameters {
   override val hasPrefetchBit:  Boolean = true
   override val hasPrefetchSrc:  Boolean = true
   override val inflightEntries: Int = 16
+  override val hasTPPrefetcher: Boolean = hastp
 }
 
 trait HasBOPParams extends HasPrefetcherHelper {

src/main/scala/coupledL2/prefetch/PrefetchParameters.scala

@@ -27,6 +27,7 @@ trait PrefetchParameters {
   val hasPrefetchBit:  Boolean
   val hasPrefetchSrc:  Boolean
   val inflightEntries: Int // max num of inflight prefetch reqs
+  val hasTPPrefetcher: Boolean
 }
 
 trait HasPrefetchParameters extends HasCoupledL2Parameters {

src/main/scala/coupledL2/prefetch/PrefetchReceiver.scala

@@ -31,7 +31,7 @@ case class PrefetchReceiverParams(n: Int = 32, tp: Boolean = true) extends Prefe
   override val hasPrefetchBit:  Boolean = true
   override val hasPrefetchSrc:  Boolean = true
   override val inflightEntries: Int = n
-  val hasTPPrefetcher: Boolean = tp
+  override val hasTPPrefetcher: Boolean = tp
 }
 
 class PrefetchReceiver()(implicit p: Parameters) extends PrefetchModule {

src/main/scala/coupledL2/prefetch/Prefetcher.scala

@@ -260,17 +260,28 @@ class Prefetcher(implicit p: Parameters) extends PrefetchModule {
       val pfRcv = Module(new PrefetchReceiver())
       val pbop = Module(new PBestOffsetPrefetch()(p.alterPartial({
         case L2ParamKey => p(L2ParamKey).copy(prefetch = Some(BOPParameters(
+          hastp = prefetchOpt match {
+            case Some(param: PrefetchReceiverParams) =>
+              if (param.hasTPPrefetcher) true else false
+            case _ => false
+          },
           virtualTrain = false,
           badScore = 1,
           offsetList = Seq(
             -32, -30, -27, -25, -24, -20, -18, -16, -15,
             -12, -10, -9, -8, -6, -5, -4, -3, -2, -1,
             1, 2, 3, 4, 5, 6, 8, 9, 10,
             12, 15, 16, 18, 20, 24, 25, 27, 30
-          ))))
+          )
+        )))
       })))
       val vbop = Module(new VBestOffsetPrefetch()(p.alterPartial({
         case L2ParamKey => p(L2ParamKey).copy(prefetch = Some(BOPParameters(
+          hastp = prefetchOpt match {
+            case Some(param: PrefetchReceiverParams) =>
+              if (param.hasTPPrefetcher) true else false
+            case _ => false
+          },
           badScore = 2,
           offsetList = Seq(
             -117,-147,-91,117,147,91,
@@ -295,7 +306,11 @@ class Prefetcher(implicit p: Parameters) extends PrefetchModule {
         case Some(param: PrefetchReceiverParams) =>
           if (param.hasTPPrefetcher) {
             Some(Module(new TemporalPrefetch()(p.alterPartial({
-              case L2ParamKey => p(L2ParamKey).copy(prefetch = Some(TPParameters()))
+              case L2ParamKey => p(L2ParamKey).copy(prefetch = Some(TPParameters(hastp = prefetchOpt match {
+                case Some(param: PrefetchReceiverParams) =>
+                  if (param.hasTPPrefetcher) true else false
+                case _ => false
+              })))
             }))))
           } else None
         case _ => None
@@ -343,7 +358,9 @@ class Prefetcher(implicit p: Parameters) extends PrefetchModule {
       io.req <> pipe.io.out
 
       // tpmeta interface
-      tp.foreach(_.io.tpmeta_port <> tpio.tpmeta_port.get)
+      if (hasTPPrefetcher) {
+        tp.foreach(_.io.tpmeta_port <> tpio.tpmeta_port.get)
+      }
 
       /* pri vbop */
       pftQueue.io.enq.valid := pfRcv.io.req.valid ||

src/main/scala/coupledL2/prefetch/TemporalPrefetch.scala

@@ -36,11 +36,13 @@ case class TPParameters(
     triggerQueueDepth: Int = 4,
     throttleCycles: Int = 4,  // unused yet
     replacementPolicy: String = "random",
-    debug: Boolean = false
+    debug: Boolean = false,
+    hastp: Boolean = true
 ) extends PrefetchParameters {
-  override val hasPrefetchBit:  Boolean = true
-  override val hasPrefetchSrc:  Boolean = true
+  override val hasPrefetchBit: Boolean = true
+  override val hasPrefetchSrc: Boolean = true
   override val inflightEntries: Int = 16
+  override val hasTPPrefetcher: Boolean = hastp
 }
 
 trait HasTPParams extends HasCoupledL2Parameters {