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Update RRIP: more detailed rrpv conditions
* Complementary set dueling * RRPV = 0: demand hit/miss, reuse demant release * RRPV = 1: prefetch miss * RRPV = 2/3: first-use demand release, prefetch release
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5 files changed

+32
-19
lines changed

5 files changed

+32
-19
lines changed

‎src/main/scala/coupledL2/Common.scala

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -30,6 +30,7 @@ class ReplacerInfo(implicit p: Parameters) extends L2Bundle {
3030
val channel = UInt(3.W)
3131
val opcode = UInt(3.W)
3232
val reqSource = UInt(MemReqSource.reqSourceBits.W)
33+
val refill_prefetch = Bool()
3334
}
3435

3536
trait HasChannelBits { this: Bundle =>

‎src/main/scala/coupledL2/Directory.scala

Lines changed: 17 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -274,6 +274,7 @@ class Directory(implicit p: Parameters) extends L2Module {
274274
(req_s3.replacerInfo.opcode === AcquirePerm || req_s3.replacerInfo.opcode === AcquireBlock)
275275
}
276276
val updateRefill = refillReqValid_s3 && !refillRetry
277+
// update replacer when A/C hit or refill
277278
replacerWen := updateHit || updateRefill
278279

279280
// hit-Promotion, miss-Insertion for RRIP, so refill should hit = false.B
@@ -293,10 +294,14 @@ class Directory(implicit p: Parameters) extends L2Module {
293294
)
294295

295296
if(cacheParams.replacement == "srrip"){
296-
// req_type[2]: 0-firstuse, 1-reuse; req_type[1]: 0-acquire, 1-release; req_type[0]: 0-non-prefetch, 1-prefetch
297-
val req_type = WireInit(0.U(3.W))
298-
req_type := Cat(origin_bits_hold(touch_way_s3), req_s3.replacerInfo.channel(2),
299-
(req_s3.replacerInfo.channel(0) && req_s3.replacerInfo.opcode === Hint) || (req_s3.replacerInfo.channel(2) && metaAll_s3(touch_way_s3).prefetch.getOrElse(false.B)))
297+
// req_type[3]: 0-firstuse, 1-reuse; req_type[2]: 0-acquire, 1-release;
298+
// req_type[1]: 0-non-prefetch, 1-prefetch; req_type[0]: 0-not-refill, 1-refill
299+
val req_type = WireInit(0.U(4.W))
300+
req_type := Cat(origin_bits_hold(touch_way_s3),
301+
req_s3.replacerInfo.channel(2),
302+
(req_s3.replacerInfo.channel(0) && req_s3.replacerInfo.opcode === Hint) || (req_s3.replacerInfo.channel(2) && metaAll_s3(touch_way_s3).prefetch.getOrElse(false.B)) || req_s3.replacerInfo.refill_prefetch,
303+
req_s3.refill
304+
)
300305

301306
val next_state_s3 = repl.get_next_state(repl_state_s3, touch_way_s3, rrip_hit_s3, req_type)
302307
val repl_init = Wire(Vec(ways, UInt(2.W)))
@@ -309,10 +314,14 @@ class Directory(implicit p: Parameters) extends L2Module {
309314
)
310315

311316
} else if(cacheParams.replacement == "drrip"){
312-
// req_type[2]: 0-firstuse, 1-reuse; req_type[1]: 0-acquire, 1-release; req_type[0]: 0-non-prefetch, 1-prefetch
313-
val req_type = WireInit(0.U(3.W))
314-
req_type := Cat(origin_bits_hold(touch_way_s3), req_s3.replacerInfo.channel(2),
315-
(req_s3.replacerInfo.channel(0) && req_s3.replacerInfo.opcode === Hint) || (req_s3.replacerInfo.channel(2) && metaAll_s3(touch_way_s3).prefetch.getOrElse(false.B)))
317+
// req_type[3]: 0-firstuse, 1-reuse; req_type[2]: 0-acquire, 1-release;
318+
// req_type[1]: 0-non-prefetch, 1-prefetch; req_type[0]: 0-not-refill, 1-refill
319+
val req_type = WireInit(0.U(4.W))
320+
req_type := Cat(origin_bits_hold(touch_way_s3),
321+
req_s3.replacerInfo.channel(2),
322+
(req_s3.replacerInfo.channel(0) && req_s3.replacerInfo.opcode === Hint) || (req_s3.replacerInfo.channel(2) && metaAll_s3(touch_way_s3).prefetch.getOrElse(false.B)) || req_s3.replacerInfo.refill_prefetch,
323+
req_s3.refill
324+
)
316325

317326
// Set Dueling
318327
val PSEL = RegInit(512.U(10.W)) //32-monitor sets, 10-bits psel

‎src/main/scala/coupledL2/L2Param.scala

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -64,7 +64,7 @@ case class L2Param
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pageBytes: Int = 4096,
6565
channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(32),
6666
clientCaches: Seq[L1Param] = Nil,
67-
replacement: String = "plru",
67+
replacement: String = "drrip",
6868
mshrs: Int = 16,
6969
releaseData: Int = 3,
7070
/* 0 for dirty alone

‎src/main/scala/coupledL2/RequestArb.scala

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -146,6 +146,7 @@ class RequestArb(implicit p: Parameters) extends L2Module {
146146
io.dirRead_s1.bits.replacerInfo.opcode := task_s1.bits.opcode
147147
io.dirRead_s1.bits.replacerInfo.channel := task_s1.bits.channel
148148
io.dirRead_s1.bits.replacerInfo.reqSource := task_s1.bits.reqSource
149+
io.dirRead_s1.bits.replacerInfo.refill_prefetch := s1_needs_replRead && (mshr_task_s1.bits.opcode === HintAck && mshr_task_s1.bits.dsWen)
149150
io.dirRead_s1.bits.refill := s1_needs_replRead
150151
io.dirRead_s1.bits.mshrId := task_s1.bits.mshrId
151152

‎src/main/scala/coupledL2/utils/Replacer.scala

Lines changed: 12 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -330,15 +330,16 @@ class StaticRRIP(n_ways: Int) extends ReplacementPolicy {
330330
}
331331
// hit-Promotion, miss-Insertion & Aging
332332
val increcement = 3.U(2.W) - State(touch_way)
333-
// req_type[2]: 0-firstuse, 1-reuse; req_type[1]: 0-acquire, 1-release; req_type[0]: 0-non-prefetch, 1-prefetch
333+
// req_type[3]: 0-firstuse, 1-reuse; req_type[2]: 0-acquire, 1-release;
334+
// req_type[1]: 0-non-prefetch, 1-prefetch; req_type[0]: 0-not-refill, 1-refill
334335
// rrpv: non-pref_hit/non-pref_refill(miss)/non-pref_release_reuse = 0;
335336
// pref_hit do nothing; pref_refill = 1; non-pref_release_firstuse/pref_release = 2;
336337
nextState.zipWithIndex.map { case (e, i) =>
337338
e := Mux(i.U === touch_way,
338-
Mux((req_type(1,0) === 0.U && hit) || req_type === 6.U, 0.U,
339-
Mux(req_type(1,0) === 1.U, 1.U, //pref_hit also = 1; origin: req_type(1,0) === 1.U && !hit
340-
Mux((req_type(1,0) === 0.U && !hit) || req_type === 2.U || req_type(1,0) === 3.U, 2.U, State(i)))),
341-
//Mux(hit, 0.U(2.W), 2.U(2.W)),
339+
Mux((req_type(2,0) === 0.U && hit) || req_type(2,0) === 1.U || req_type === 12.U, 0.U,
340+
Mux(req_type(2,0) === 3.U, 1.U,
341+
Mux(req_type === 4.U || req_type(2,0) === 6.U, 2.U, State(i)))),
342+
//Mux(hit, 0.U(2.W), 2.U(2.W)),
342343
Mux(hit, State(i), State(i)+increcement)
343344
)
344345
}
@@ -389,14 +390,15 @@ class BRRIP(n_ways: Int) extends ReplacementPolicy {
389390

390391
// hit-Promotion, miss-Insertion & Aging
391392
val increcement = 3.U(2.W) - State(touch_way)
392-
// req_type[2]: 0-firstuse, 1-reuse; req_type[1]: 0-acquire, 1-release; req_type[0]: 0-non-prefetch, 1-prefetch
393+
// req_type[3]: 0-firstuse, 1-reuse; req_type[2]: 0-acquire, 1-release;
394+
// req_type[1]: 0-non-prefetch, 1-prefetch; req_type[0]: 0-not-refill, 1-refill
393395
// rrpv: non-pref_hit/non-pref_refill(miss)/non-pref_release_reuse = 0;
394396
// pref_hit do nothing; pref_refill = 1; non-pref_release_firstuse/pref_release = 3;
395397
nextState.zipWithIndex.map { case (e, i) =>
396-
e := Mux(i.U === touch_way,
397-
Mux((req_type(1,0) === 0.U && hit) || req_type === 6.U, 0.U,
398-
Mux(req_type(1,0) === 1.U, 1.U, //pref_hit also = 1; origin: req_type(1,0) === 1.U && !hit
399-
Mux((req_type(1,0) === 0.U && !hit) || req_type === 2.U || req_type(1,0) === 3.U, 3.U, State(i)))),
398+
e := Mux(i.U === touch_way,
399+
Mux((req_type(2,0) === 0.U && hit) || req_type(2,0) === 1.U || req_type === 12.U, 0.U,
400+
Mux(req_type(2,0) === 3.U, 1.U,
401+
Mux(req_type === 4.U || req_type(2,0) === 6.U, 3.U, State(i)))),
400402
//Mux(hit, 0.U(2.W), 3.U(2.W)),
401403
Mux(hit, State(i), State(i)+increcement)
402404
)

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