fix(MainPipe, MSHR): state transitions of nested WriteCleanFull (#351)

* fix(MainPipe, MSHR): state transitions of nested WriteCleanFull

**SnpOnceX**: SnpOnce, SnpOnceFwd
**SnpToB**: SnpClean, SnpShared, SnpNotSharedDirty, SnpCleanFwd,
            SnpSharedFwd, SnpNotSharedDirtyFwd

* 1) Common: Distinguish WriteBackFull/WriteEvictFull/WriteEvictOrEvict/
     Evict nesting from WriteCleanFull using ```snpHitReleaseToInval```
     and ```snpHitReleaseToClean``` for better robustness and
     readability

* 2) MainPipe: For **SnpOnceX** and **SnpToB** nesting WriteCleanFull,
     redirect cache state to SC

* 3) MainPipe: Update directory meta on **SnpOnceX** nesting
     WriteCleanFull

* 4) MainPipe: For **SnpCleanShared** nesting WriteCleanFull, allow
     transition to UC

* 5) MSHR: Clear dirty flag in directory meta on ```mp_probeack``` of
     **SnpOnceX** nesting WriteCleanFull

* 6) MSHR: For **SnpOnceX** nesting WriteCleanFull, allow PassDirty

* fix(MainPipe): fix SnpRespX state of non-WriteCleanFull nesting

* fix(MSHR): SnpRespDataFwded on SnpOnceFwd with UD -> SC

* fix(MSHR): UD -> SC on SnpOnceX nesting WriteCleanFull with dirty data

* fix(MainPipe): SnpOnce UD -> SC only on nesting WriteCleanFull dirty

* fix(MSHR): unnecessary directory hit predication

* fix(MainPipe): pass meta change on snoops without entering MSHR

* fix(MainPipe): compilation error

* fix(MainPipe): compilation error

* style(MainPipe): code style

* fix(MSHR): consider directory miss and nesting write to I

Author: Kumonda221-CrO3

src/main/scala/coupledL2/Common.scala

@@ -120,7 +120,8 @@ class TaskBundle(implicit p: Parameters) extends L2Bundle
 
   // Used for get data from ReleaseBuf when snoop hit with same PA 
   val snpHitRelease = Bool()
-  val snpHitReleaseToB = Bool()
+  val snpHitReleaseToInval = Bool()
+  val snpHitReleaseToClean = Bool()
   val snpHitReleaseWithData = Bool()
   val snpHitReleaseIdx = UInt(mshrBits.W) 
   val snpHitReleaseState = UInt(2.W)
@@ -227,8 +228,8 @@ class MSHRInfo(implicit p: Parameters) extends L2Bundle with HasTLChannelBits {
 
   val replaceData = Bool() // If there is a replace, WriteBackFull or Evict
 
-  // exclude Release toB for nested snoop of releases
-  val releaseToB = Bool()
+  // release to T with data or UC (e.g. WriteCleanFull)
+  val releaseToClean = Bool()
 }
 
 class RespInfoBundle(implicit p: Parameters) extends L2Bundle

src/main/scala/coupledL2/tl2chi/MSHR.scala

@@ -180,13 +180,18 @@ class MSHR(implicit p: Parameters) extends TL2CHIL2Module with HasCHIOpcodes {
 
   val cmo_cbo = req_cboClean || req_cboFlush || req_cboInval
 
+  // *NOTICE: WriteBack/WriteClean(s) with nested snoops that passed dirty were not considered as
+  //          a nested hit here, which would no longer pass latest data to lower tier memories.
   val hitDirty = dirResult.hit && meta.dirty || probeDirty
-  val hitWriteBack = req.snpHitRelease && req.snpHitReleaseWithData && req.snpHitReleaseDirty
+  val hitWriteBack = req.snpHitRelease && req.snpHitReleaseWithData && req.snpHitReleaseDirty && req.snpHitReleaseToInval
+  val hitWriteClean = req.snpHitRelease && req.snpHitReleaseWithData && req.snpHitReleaseDirty && req.snpHitReleaseToClean
   val hitWriteEvict = req.snpHitRelease && req.snpHitReleaseWithData && !req.snpHitReleaseDirty
-  val hitWriteX = hitWriteBack || hitWriteEvict
-  val hitDirtyOrWriteBack = hitDirty || hitWriteBack
 
-  val releaseToB = req_cboClean
+  val hitWriteX = hitWriteBack || hitWriteClean || hitWriteEvict
+  val hitWriteDirty = hitWriteBack || hitWriteClean
+  val hitDirtyOrWriteDirty = hitDirty || hitWriteDirty
+
+  val releaseToClean = req_cboClean
 
   /**
     * About which snoop should echo SnpRespData[Fwded] instead of SnpResp[Fwded]:
@@ -197,7 +202,7 @@ class MSHR(implicit p: Parameters) extends TL2CHIL2Module with HasCHIOpcodes {
     * 3. When the snoop opcode is non-forwarding non-stashing snoop, echo SnpRespData if RetToSrc = 1 as long as the
     *    cache line is Shared Clean and the snoopee retains a copy of the cache line.
     */
-  val doRespData_dirty = hitDirtyOrWriteBack && (
+  val doRespData_dirty = hitDirtyOrWriteDirty && (
     req_chiOpcode === SnpOnce ||
     snpToB ||
     req_chiOpcode === SnpUnique ||
@@ -216,8 +221,12 @@ class MSHR(implicit p: Parameters) extends TL2CHIL2Module with HasCHIOpcodes {
       (isSnpToBNonFwd(req_chiOpcode) || isSnpToNNonFwd(req_chiOpcode) || isSnpOnce(req_chiOpcode)) ||
     hitWriteEvict &&
        isSnpOnce(req_chiOpcode))
-  // doRespData_once includes SnpOnceFwd(nested) UD -> I and SnpOnce UC -> UC/I(non-nested/nested)
-  val doRespData_once = hitWriteBack &&
+  // doRespData_once includes 
+  //  1. SnpOnceFwd : UD -> I     (nesting WriteBack)
+  //  2. SnpOnceFwd : UD -> SC    (nesting WriteClean)
+  //  3. SnpOnce    : UC -> UC    (non-nesting)
+  //  4. SnpOnce    : UC -> I     (nesting WriteBack)
+  val doRespData_once = (hitWriteBack || hitWriteClean) &&
       isSnpOnceFwd(req_chiOpcode) ||
     (dirResult.hit && !meta.dirty && meta.state =/= BRANCH || hitWriteEvict) &&
       isSnpOnce(req_chiOpcode)
@@ -298,34 +307,35 @@ class MSHR(implicit p: Parameters) extends TL2CHIL2Module with HasCHIOpcodes {
   }
 
   // resp and fwdState
-  val respCacheState = Mux(dirResult.hit, ParallelPriorityMux(Seq(
+  // *NOTICE: Snp*Fwd would enter MSHR on directory missing
+  val respCacheState = ParallelPriorityMux(Seq(
     snpToN -> I,
-    snpToB -> SC,
+    snpToB -> Mux(!dirResult.hit, I, SC),
     isSnpOnceX(req_chiOpcode) ->
-      Mux(
-        req.snpHitRelease,
-        I, // also see 'nestedwb.b_inv_dirty' in MainPipe
+      Mux(!dirResult.hit, I, Mux(
+        req.snpHitReleaseToClean,
+        SC,
         Mux(probeDirty || meta.dirty, UD, metaChi)
-      ),
+      )),
     (isSnpStashX(req_chiOpcode) || isSnpQuery(req_chiOpcode)) ->
       Mux(probeDirty || meta.dirty, UD, metaChi),
     isSnpCleanShared(req_chiOpcode) -> 
       Mux(isT(meta.state), UC, metaChi)
-  )), I)
-  val respPassDirty = hitDirtyOrWriteBack && (
+  ))
+  val respPassDirty = hitDirtyOrWriteDirty && (
     snpToB ||
     req_chiOpcode === SnpUnique ||
     req_chiOpcode === SnpUniqueStash ||
     req_chiOpcode === SnpCleanShared ||
     req_chiOpcode === SnpCleanInvalid ||
-    isSnpOnceX(req_chiOpcode) && hitWriteBack
+    isSnpOnceX(req_chiOpcode) && hitWriteDirty
   )
   val fwdCacheState = Mux(
     isSnpToBFwd(req_chiOpcode),
     SC,
     Mux(isSnpToNFwd(req_chiOpcode), UC /*UC_UD*/, I)
   )
-  val fwdPassDirty = isSnpToNFwd(req_chiOpcode) && hitDirtyOrWriteBack
+  val fwdPassDirty = isSnpToNFwd(req_chiOpcode) && hitDirtyOrWriteDirty
 
   /*TXRSP for CompAck */
   val orsp = io.tasks.txrsp.bits
@@ -630,21 +640,32 @@ class MSHR(implicit p: Parameters) extends TL2CHIL2Module with HasCHIOpcodes {
         * 1. If the snoop belongs to SnpToN
         * 2. If the snoop belongs to SnpToB
         * 3. If the snoop is SnpCleanShared
+        * 4. If the snoop is SnpOnce/SnpOnceFwd and nesting WriteCleanFull
         * Otherwise, the dirty bit should stay the same as before.
         */
-      dirty = !snpToN && !snpToB && req_chiOpcode =/= SnpCleanShared && (dirResult.hit && meta.dirty) ||
-        isSnpOnceX(req_chiOpcode) && probeDirty,
+      dirty = !(
+        !dirResult.hit || !meta.dirty ||
+        snpToN ||
+        snpToB ||
+        isSnpCleanShared(req_chiOpcode) ||
+        isSnpOnceX(req_chiOpcode) && req.snpHitReleaseToClean
+      ) || isSnpOnceX(req_chiOpcode) && probeDirty,
+      // Directory would always be missing on nesting WriteBackFull/WriteEvict*/Evict
       state = Mux(
         snpToN,
         INVALID,
-        Mux(snpToB, BRANCH, meta.state)
+        Mux(
+          // On SnpOnce/SnpOnceFwd nesting WriteCleanFull with UD, we went UD -> SC (T -> B here)
+          snpToB || isSnpOnceX(req_chiOpcode) && hitWriteClean,
+          BRANCH,
+          meta.state)
       ),
       clients = meta.clients & Fill(clientBits, !probeGotN && !snpToN),
       alias = meta.alias, //[Alias] Keep alias bits unchanged
       prefetch = !snpToN && meta_pft,
       accessed = !snpToN && meta.accessed
     )
-    mp_probeack.metaWen := !req.snpHitRelease || req.snpHitReleaseToB
+    mp_probeack.metaWen := !req.snpHitReleaseToInval
     mp_probeack.tagWen := false.B
     mp_probeack.dsWen := !snpToN && probeDirty && meta.clients.orR
     mp_probeack.wayMask := 0.U(cacheParams.ways.W)
@@ -679,7 +700,8 @@ class MSHR(implicit p: Parameters) extends TL2CHIL2Module with HasCHIOpcodes {
     mp_probeack.expCompAck.get := false.B
     mp_probeack.traceTag.get := req.traceTag.get
     mp_probeack.snpHitRelease := req.snpHitRelease
-    mp_probeack.snpHitReleaseToB := req.snpHitReleaseToB
+    mp_probeack.snpHitReleaseToInval := req.snpHitReleaseToInval
+    mp_probeack.snpHitReleaseToClean := req.snpHitReleaseToClean
     mp_probeack.snpHitReleaseWithData := req.snpHitReleaseWithData
     mp_probeack.snpHitReleaseIdx := req.snpHitReleaseIdx
 
@@ -867,7 +889,8 @@ class MSHR(implicit p: Parameters) extends TL2CHIL2Module with HasCHIOpcodes {
     mp_dct.expCompAck.get := false.B // DontCare
     mp_dct.traceTag.get := req.traceTag.get
     mp_dct.snpHitRelease := req.snpHitRelease
-    mp_dct.snpHitReleaseToB := req.snpHitReleaseToB
+    mp_dct.snpHitReleaseToInval := req.snpHitReleaseToInval
+    mp_dct.snpHitReleaseToClean := req.snpHitReleaseToClean
     mp_dct.snpHitReleaseWithData := req.snpHitReleaseWithData
     mp_dct.snpHitReleaseIdx := req.snpHitReleaseIdx
     mp_dct.snpHitReleaseState := req.snpHitReleaseState
@@ -929,7 +952,8 @@ class MSHR(implicit p: Parameters) extends TL2CHIL2Module with HasCHIOpcodes {
     mp_cmometaw.expCompAck.get := false.B // DontCare
     mp_cmometaw.traceTag.get := 0.U
     mp_cmometaw.snpHitRelease := req.snpHitRelease
-    mp_cmometaw.snpHitReleaseToB := req.snpHitReleaseToB
+    mp_cmometaw.snpHitReleaseToInval := req.snpHitReleaseToInval
+    mp_cmometaw.snpHitReleaseToClean := req.snpHitReleaseToClean
     mp_cmometaw.snpHitReleaseWithData := req.snpHitReleaseWithData
     mp_cmometaw.snpHitReleaseIdx := req.snpHitReleaseIdx
     mp_cmometaw.snpHitReleaseState := req.snpHitReleaseState
@@ -1306,7 +1330,7 @@ class MSHR(implicit p: Parameters) extends TL2CHIL2Module with HasCHIOpcodes {
   io.msInfo.bits.w_rprobeacklast := state.w_rprobeacklast
   io.msInfo.bits.replaceData := isT(meta.state) && meta.dirty || probeDirty || // including WriteCleanFull
                                 isWriteEvictFull || isWriteEvictOrEvict
-  io.msInfo.bits.releaseToB := releaseToB
+  io.msInfo.bits.releaseToClean := releaseToClean
   io.msInfo.bits.channel := req.channel
 
   assert(!(c_resp.valid && !io.status.bits.w_c_resp))

src/main/scala/coupledL2/tl2chi/MainPipe.scala

@@ -326,14 +326,21 @@ class MainPipe(implicit p: Parameters) extends TL2CHIL2Module with HasCHIOpcodes
       )
     }
     when (req_s3.chiOpcode.get === SnpCleanShared) {
-      respCacheState := Mux(meta_s3.state === BRANCH, SC, UC)
+      respCacheState := Mux(isT(meta_s3.state), UC, SC)
+    }
+
+    when (req_s3.snpHitReleaseToClean) {
+      // On SnpOnce/SnpOnceFwd nesting WriteCleanFull, turn UD/UC to SC
+      when (isSnpOnceX(req_s3.chiOpcode.get)) {
+        respCacheState := SC
+      }
     }
   }
 
   when (req_s3.snpHitRelease) {
     /**
       * NOTICE: On Stash and Query:
-      * the cache state must maintain unchanged on nested WriteBack
+      * the cache state must maintain unchanged on nested copy-back writes
      */
     when (isSnpStashX(req_s3.chiOpcode.get) || isSnpQuery(req_s3.chiOpcode.get)) {
       respCacheState := Mux(
@@ -361,6 +368,9 @@ class MainPipe(implicit p: Parameters) extends TL2CHIL2Module with HasCHIOpcodes
     }
   }
 
+  val sink_resp_s3_b_meta = MetaEntry()
+  val sink_resp_s3_b_metaWen = Wire(Bool())
+
   sink_resp_s3.valid := task_s3.valid && !mshr_req_s3 && !need_mshr_s3
   sink_resp_s3.bits := task_s3.bits
   sink_resp_s3.bits.mshrId := (1 << (mshrBits-1)).U + sink_resp_s3.bits.sourceId
@@ -392,7 +402,26 @@ class MainPipe(implicit p: Parameters) extends TL2CHIL2Module with HasCHIOpcodes
     )))
     sink_resp_s3.bits.resp.foreach(_ := Mux(
       req_s3.snpHitRelease && !(isSnpStashX(req_s3.chiOpcode.get) || isSnpQuery(req_s3.chiOpcode.get)),
-      setPD(I, req_s3.snpHitReleaseWithData && req_s3.snpHitReleaseDirty && !isSnpMakeInvalidX(req_s3.chiOpcode.get)),
+      setPD(
+        // On directory hit under non-invalidating snoop nesting WriteCleanFull, 
+        // excluding SnpStashX and SnpQuery:
+        //  1. SnpCleanShared[1-sink_resp]  : UD -> UC_PD, UC -> UC, SC -> SC
+        //  2. SnpOnce*[2-sink_resp]        : UD -> SC_PD, UC -> SC, SC -> SC
+        //  3. snpToB                       : UD -> SC_PD, UC -> SC, SC -> SC
+        // 
+        // *NOTE[1-sink_resp]:
+        //    UD -> SC transitions were not used on WriteCleanFull without nesting snoop, and
+        //    only UD -> UC update could be observed on directory in this case
+        //    Therefore, it was unnecessary to observe cache state from nested WriteCleanFull MSHRs, while
+        //    extracting PassDirty from MSHRs
+        //
+        // *NOTE[2-sink_resp]:
+        //    UD -> UC transitions were not allowed on SnpOnce*, while permitting UD -> UD and UC -> UC
+        //    On SnpOnce*, UD/UC were turned into SC on nested WriteClean, on which directory must hit
+        //    Otherwise, the cache state was fast forwarded to I by default
+        //    Directory might be missing after multiple nesting snoops on WriteClean, indicating losing UD
+        Mux(req_s3.snpHitReleaseToClean && !isSnpToN(req_s3.chiOpcode.get), respCacheState, I),
+        req_s3.snpHitReleaseWithData && req_s3.snpHitReleaseDirty && !isSnpMakeInvalidX(req_s3.chiOpcode.get)),
       setPD(respCacheState, respPassDirty && (doRespData || doRespDataHitRelease))
     ))
     sink_resp_s3.bits.fwdState.foreach(_ := setPD(fwdCacheState, fwdPassDirty))
@@ -402,6 +431,8 @@ class MainPipe(implicit p: Parameters) extends TL2CHIL2Module with HasCHIOpcodes
       false.B
     ) // TODO: parameterize this
     sink_resp_s3.bits.size := log2Ceil(blockBytes).U
+    sink_resp_s3.bits.meta := sink_resp_s3_b_meta
+    sink_resp_s3.bits.metaWen := sink_resp_s3_b_metaWen
 
   }.otherwise { // req_s3.fromC
     sink_resp_s3.bits.opcode := ReleaseAck
@@ -477,8 +508,11 @@ class MainPipe(implicit p: Parameters) extends TL2CHIL2Module with HasCHIOpcodes
 
   /* ======== Write Directory ======== */
   val metaW_valid_s3_a = sinkA_req_s3 && !need_mshr_s3_a && !req_get_s3 && !req_prefetch_s3 && !cmo_cbo_s3 // get & prefetch that hit will not write meta
+  // Also write directory on:
+  //  1. SnpOnce nesting WriteCleanFull under UD (SnpOnceFwd always needs MSHR) for UD -> SC
   val metaW_valid_s3_b = sinkB_req_s3 && !need_mshr_s3_b && dirResult_s3.hit &&
-    !isSnpOnceX(req_s3.chiOpcode.get) && !isSnpStashX(req_s3.chiOpcode.get) && !isSnpQuery(req_s3.chiOpcode.get) && (
+    (!isSnpOnce(req_s3.chiOpcode.get) || (req_s3.snpHitReleaseToClean && req_s3.snpHitReleaseDirty)) && 
+    !isSnpStashX(req_s3.chiOpcode.get) && !isSnpQuery(req_s3.chiOpcode.get) && (
       meta_s3.state === TIP || meta_s3.state === BRANCH && isSnpToN(req_s3.chiOpcode.get)
     )
   val metaW_valid_s3_c = sinkC_req_s3 && dirResult_s3.hit
@@ -551,6 +585,9 @@ class MainPipe(implicit p: Parameters) extends TL2CHIL2Module with HasCHIOpcodes
   io.tagWReq.bits.way := Mux(mshr_refill_s3 && req_s3.replTask, io.replResp.bits.way, req_s3.way)
   io.tagWReq.bits.wtag := req_s3.tag
 
+  sink_resp_s3_b_metaWen := metaW_valid_s3_b
+  sink_resp_s3_b_meta := metaW_s3_b
+
   /* ======== Interact with Channels (SourceD/TXREQ/TXRSP/TXDAT) ======== */
   val chnl_fire_s3 = d_s3.fire || txreq_s3.fire || txrsp_s3.fire || txdat_s3.fire
   val req_drop_s3 = !need_write_releaseBuf && (
@@ -625,11 +662,9 @@ class MainPipe(implicit p: Parameters) extends TL2CHIL2Module with HasCHIOpcodes
     * 
     * *NOTICE: Never allow 'b_inv_dirty' on SnpStash*, SnpQuery and other future snoops that would
     *          leave cache line state untouched.
-    * 
-    * *TODO: A SnpOnce* nesting WriteCleanFull would result in SnpResp*_I_PD, which was simple to
-    *        implement but could be further optimized.
+    *          Never allow 'b_inv_dirty' on SnpOnce* nesting WriteCleanFull, which would end with SC.
     */
-  io.nestedwb.b_inv_dirty := task_s3.valid && task_s3.bits.fromB && source_req_s3.snpHitRelease &&
+  io.nestedwb.b_inv_dirty := task_s3.valid && task_s3.bits.fromB && source_req_s3.snpHitReleaseToInval &&
     !(isSnpStashX(req_s3.chiOpcode.get) || isSnpQuery(req_s3.chiOpcode.get))
   io.nestedwb.b_toB.foreach(_ :=
     task_s3.valid && task_s3.bits.fromB && source_req_s3.metaWen && source_req_s3.meta.state === BRANCH

src/main/scala/coupledL2/tl2chi/RXSNP.scala

@@ -88,8 +88,11 @@ class RXSNP(
       (!s.bits.dirHit || !s.bits.s_cmoresp) && s.bits.metaState =/= INVALID &&
       RegNext(s.bits.w_replResp) && s.bits.w_rprobeacklast && !s.bits.w_releaseack
     )).asUInt
-  val releaseToBNestSnpMask = replaceNestSnpMask & VecInit(io.msInfo.map(s =>
-      s.bits.releaseToB
+  val releaseToInvalNestSnpMask = replaceNestSnpMask & VecInit(io.msInfo.map(s =>
+      !s.bits.releaseToClean
+    )).asUInt
+  val releaseToCleanNestSnpMask = replaceNestSnpMask & VecInit(io.msInfo.map(s =>
+      s.bits.releaseToClean
     )).asUInt
   val replaceDataMask = VecInit(io.msInfo.map(_.bits.replaceData)).asUInt
 
@@ -159,7 +162,8 @@ class RXSNP(
     task.mergeA := false.B
     task.aMergeTask := 0.U.asTypeOf(new MergeTaskBundle)
     task.snpHitRelease := replaceNestSnpMask.orR
-    task.snpHitReleaseToB := releaseToBNestSnpMask.orR
+    task.snpHitReleaseToInval := releaseToInvalNestSnpMask.orR
+    task.snpHitReleaseToClean := releaseToCleanNestSnpMask.orR
     task.snpHitReleaseWithData := (replaceNestSnpMask & replaceDataMask).orR
     task.snpHitReleaseState := replaceNestSnpState
     task.snpHitReleaseDirty := replaceNestSnpDirty

src/main/scala/coupledL2/tl2tl/MSHR.scala

@@ -571,7 +571,7 @@ class MSHR(implicit p: Parameters) extends L2Module {
   io.msInfo.bits.w_replResp := state.w_replResp
   io.msInfo.bits.w_rprobeacklast := state.w_rprobeacklast
   io.msInfo.bits.replaceData := mp_release.opcode === ReleaseData
-  io.msInfo.bits.releaseToB := false.B
+  io.msInfo.bits.releaseToClean := false.B
   io.msInfo.bits.metaState := meta.state
   io.msInfo.bits.metaDirty := meta.dirty
   io.msInfo.bits.probeDirty := probeDirty

src/main/scala/coupledL2/tl2tl/MainPipe.scala

@@ -240,7 +240,8 @@ class MainPipe(implicit p: Parameters) extends L2Module with HasPerfEvents {
   ms_task.aMergeTask       := req_s3.aMergeTask
   ms_task.txChannel        := 0.U
   ms_task.snpHitRelease    := false.B
-  ms_task.snpHitReleaseToB := false.B
+  ms_task.snpHitReleaseToInval := false.B
+  ms_task.snpHitReleaseToClean := false.B
   ms_task.snpHitReleaseWithData := false.B
   ms_task.snpHitReleaseIdx := 0.U
   ms_task.snpHitReleaseState := 0.U

src/main/scala/coupledL2/tl2tl/SinkB.scala

@@ -50,7 +50,8 @@ class SinkB(implicit p: Parameters) extends L2Module {
     task.wayMask := Fill(cacheParams.ways, "b1".U)
     task.reqSource := MemReqSource.NoWhere.id.U // Ignore
     task.snpHitRelease := false.B
-    task.snpHitReleaseToB := false.B
+    task.snpHitReleaseToInval := false.B
+    task.snpHitReleaseToClean := false.B
     task.snpHitReleaseWithData := false.B
     task.snpHitReleaseIdx := 0.U
     task.snpHitReleaseState := 0.U