From 1a597121e111077bd24a847ccdaba9fec1dbd0f9 Mon Sep 17 00:00:00 2001 From: zhanglinjuan Date: Wed, 15 May 2024 21:07:31 +0800 Subject: [PATCH 1/2] Directory: fix overloaded method of fire when MFC=1 --- src/main/scala/coupledL2/Directory.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/coupledL2/Directory.scala b/src/main/scala/coupledL2/Directory.scala index 5c5eff670..59f2fca18 100644 --- a/src/main/scala/coupledL2/Directory.scala +++ b/src/main/scala/coupledL2/Directory.scala @@ -283,9 +283,9 @@ class Directory(implicit p: Parameters) extends L2Module { // origin-bit marks whether the data_block is reused val origin_bit_opt = if(random_repl) None else Some(Module(new SRAMTemplate(Bool(), sets, ways, singlePort = true))) - val origin_bits_r = origin_bit_opt.get.io.r(io.read.fire(), io.read.bits.set).resp.data + val origin_bits_r = origin_bit_opt.get.io.r(io.read.fire, io.read.bits.set).resp.data val origin_bits_hold = Wire(Vec(ways, Bool())) - origin_bits_hold := HoldUnless(origin_bits_r, RegNext(io.read.fire(), false.B)) + origin_bits_hold := HoldUnless(origin_bits_r, RegNext(io.read.fire, false.B)) origin_bit_opt.get.io.w( replacerWen, rrip_hit_s3, From 00c8dd3fa45ba4493b60ba4281e487477cbfd604 Mon Sep 17 00:00:00 2001 From: zhanglinjuan Date: Wed, 15 May 2024 21:00:07 +0800 Subject: [PATCH 2/2] RXSNP: add pipeline to ease timing for rxsnp logics --- src/main/scala/coupledL2/tl2chi/RXSNP.scala | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/src/main/scala/coupledL2/tl2chi/RXSNP.scala b/src/main/scala/coupledL2/tl2chi/RXSNP.scala index 8d64e128a..903d415f8 100644 --- a/src/main/scala/coupledL2/tl2chi/RXSNP.scala +++ b/src/main/scala/coupledL2/tl2chi/RXSNP.scala @@ -34,6 +34,10 @@ class RXSNP( val msInfo = Vec(mshrsAll, Flipped(ValidIO(new MSHRInfo()))) }) + val rxsnp = Wire(io.rxsnp.cloneType) + val queue = Module(new Queue(io.rxsnp.bits.cloneType, 2, flow = false)) + rxsnp <> queue.io.deq + queue.io.enq <> io.rxsnp val task = Wire(new TaskBundle) /** @@ -75,24 +79,24 @@ class RXSNP( )).asUInt val replaceDataMask = VecInit(io.msInfo.map(_.bits.replaceData)).asUInt - task := fromSnpToTaskBundle(io.rxsnp.bits) + task := fromSnpToTaskBundle(rxsnp.bits) val stall = reqBlockSnp || replaceBlockSnp // addrConflict || replaceConflict - io.task.valid := io.rxsnp.valid && !stall + io.task.valid := rxsnp.valid && !stall io.task.bits := task - io.rxsnp.ready := io.task.ready && !stall + rxsnp.ready := io.task.ready && !stall val stallCnt = RegInit(0.U(64.W)) - when(io.rxsnp.fire) { + when(rxsnp.fire) { stallCnt := 0.U - }.elsewhen(io.rxsnp.valid && !io.rxsnp.ready) { + }.elsewhen(rxsnp.valid && !rxsnp.ready) { stallCnt := stallCnt + 1.U } val STALL_CNT_MAX = 28000.U - assert(stallCnt <= STALL_CNT_MAX, "stallCnt full! maybe there is a deadlock! addr => 0x%x req_opcode => %d txn_id => %d", io.rxsnp.bits.addr, io.rxsnp.bits.opcode, io.rxsnp.bits.txnID); + assert(stallCnt <= STALL_CNT_MAX, "stallCnt full! maybe there is a deadlock! addr => 0x%x req_opcode => %d txn_id => %d", rxsnp.bits.addr, rxsnp.bits.opcode, rxsnp.bits.txnID); - assert(!(stall && io.rxsnp.fire)) + assert(!(stall && rxsnp.fire)) def fromSnpToTaskBundle(snp: CHISNP): TaskBundle = { val task = WireInit(0.U.asTypeOf(new TaskBundle))