diff --git a/src/main/scala/coupledL2/CoupledL2.scala b/src/main/scala/coupledL2/CoupledL2.scala index 787f1246..172e2b9e 100644 --- a/src/main/scala/coupledL2/CoupledL2.scala +++ b/src/main/scala/coupledL2/CoupledL2.scala @@ -75,6 +75,7 @@ trait HasCoupledL2Parameters { val hasPrefetchBit = prefetchOpt.nonEmpty && prefetchOpt.get.hasPrefetchBit val hasPrefetchSrc = prefetchOpt.nonEmpty && prefetchOpt.get.hasPrefetchSrc val topDownOpt = if(cacheParams.elaboratedTopDown) Some(true) else None + val hasTPPrefetcher = prefetchOpt.nonEmpty && prefetchOpt.get.hasTPPrefetcher val enableHintGuidedGrant = true diff --git a/src/main/scala/coupledL2/prefetch/BestOffsetPrefetch.scala b/src/main/scala/coupledL2/prefetch/BestOffsetPrefetch.scala index 48da3de0..692534e6 100644 --- a/src/main/scala/coupledL2/prefetch/BestOffsetPrefetch.scala +++ b/src/main/scala/coupledL2/prefetch/BestOffsetPrefetch.scala @@ -52,11 +52,13 @@ case class BOPParameters( 90, 96, 100, 108, 120, 125, 128, 135, 144, 150, 160, 162, 180, 192, 200, 216, 225, 240, 243, 250/*, 256*/ - )) + ), + hastp: Boolean = true) extends PrefetchParameters { override val hasPrefetchBit: Boolean = true override val hasPrefetchSrc: Boolean = true override val inflightEntries: Int = 16 + override val hasTPPrefetcher: Boolean = hastp } trait HasBOPParams extends HasPrefetcherHelper { diff --git a/src/main/scala/coupledL2/prefetch/PrefetchParameters.scala b/src/main/scala/coupledL2/prefetch/PrefetchParameters.scala index b1610ca2..57bb1225 100644 --- a/src/main/scala/coupledL2/prefetch/PrefetchParameters.scala +++ b/src/main/scala/coupledL2/prefetch/PrefetchParameters.scala @@ -27,6 +27,7 @@ trait PrefetchParameters { val hasPrefetchBit: Boolean val hasPrefetchSrc: Boolean val inflightEntries: Int // max num of inflight prefetch reqs + val hasTPPrefetcher: Boolean } trait HasPrefetchParameters extends HasCoupledL2Parameters { diff --git a/src/main/scala/coupledL2/prefetch/PrefetchReceiver.scala b/src/main/scala/coupledL2/prefetch/PrefetchReceiver.scala index 7a4a329b..57e4e70c 100644 --- a/src/main/scala/coupledL2/prefetch/PrefetchReceiver.scala +++ b/src/main/scala/coupledL2/prefetch/PrefetchReceiver.scala @@ -31,7 +31,7 @@ case class PrefetchReceiverParams(n: Int = 32, tp: Boolean = true) extends Prefe override val hasPrefetchBit: Boolean = true override val hasPrefetchSrc: Boolean = true override val inflightEntries: Int = n - val hasTPPrefetcher: Boolean = tp + override val hasTPPrefetcher: Boolean = tp } class PrefetchReceiver()(implicit p: Parameters) extends PrefetchModule { diff --git a/src/main/scala/coupledL2/prefetch/Prefetcher.scala b/src/main/scala/coupledL2/prefetch/Prefetcher.scala index a28511fa..23076bf4 100644 --- a/src/main/scala/coupledL2/prefetch/Prefetcher.scala +++ b/src/main/scala/coupledL2/prefetch/Prefetcher.scala @@ -260,6 +260,11 @@ class Prefetcher(implicit p: Parameters) extends PrefetchModule { val pfRcv = Module(new PrefetchReceiver()) val pbop = Module(new PBestOffsetPrefetch()(p.alterPartial({ case L2ParamKey => p(L2ParamKey).copy(prefetch = Some(BOPParameters( + hastp = prefetchOpt match { + case Some(param: PrefetchReceiverParams) => + if (param.hasTPPrefetcher) true else false + case _ => false + }, virtualTrain = false, badScore = 1, offsetList = Seq( @@ -267,10 +272,16 @@ class Prefetcher(implicit p: Parameters) extends PrefetchModule { -12, -10, -9, -8, -6, -5, -4, -3, -2, -1, 1, 2, 3, 4, 5, 6, 8, 9, 10, 12, 15, 16, 18, 20, 24, 25, 27, 30 - )))) + ) + ))) }))) val vbop = Module(new VBestOffsetPrefetch()(p.alterPartial({ case L2ParamKey => p(L2ParamKey).copy(prefetch = Some(BOPParameters( + hastp = prefetchOpt match { + case Some(param: PrefetchReceiverParams) => + if (param.hasTPPrefetcher) true else false + case _ => false + }, badScore = 2, offsetList = Seq( -117,-147,-91,117,147,91, @@ -295,7 +306,11 @@ class Prefetcher(implicit p: Parameters) extends PrefetchModule { case Some(param: PrefetchReceiverParams) => if (param.hasTPPrefetcher) { Some(Module(new TemporalPrefetch()(p.alterPartial({ - case L2ParamKey => p(L2ParamKey).copy(prefetch = Some(TPParameters())) + case L2ParamKey => p(L2ParamKey).copy(prefetch = Some(TPParameters(hastp = prefetchOpt match { + case Some(param: PrefetchReceiverParams) => + if (param.hasTPPrefetcher) true else false + case _ => false + }))) })))) } else None case _ => None @@ -343,7 +358,9 @@ class Prefetcher(implicit p: Parameters) extends PrefetchModule { io.req <> pipe.io.out // tpmeta interface - tp.foreach(_.io.tpmeta_port <> tpio.tpmeta_port.get) + if (hasTPPrefetcher) { + tp.foreach(_.io.tpmeta_port <> tpio.tpmeta_port.get) + } /* pri vbop */ pftQueue.io.enq.valid := pfRcv.io.req.valid || diff --git a/src/main/scala/coupledL2/prefetch/TemporalPrefetch.scala b/src/main/scala/coupledL2/prefetch/TemporalPrefetch.scala index 10688fee..57c845d7 100644 --- a/src/main/scala/coupledL2/prefetch/TemporalPrefetch.scala +++ b/src/main/scala/coupledL2/prefetch/TemporalPrefetch.scala @@ -36,11 +36,13 @@ case class TPParameters( triggerQueueDepth: Int = 4, throttleCycles: Int = 4, // unused yet replacementPolicy: String = "random", - debug: Boolean = false + debug: Boolean = false, + hastp: Boolean = true ) extends PrefetchParameters { - override val hasPrefetchBit: Boolean = true - override val hasPrefetchSrc: Boolean = true + override val hasPrefetchBit: Boolean = true + override val hasPrefetchSrc: Boolean = true override val inflightEntries: Int = 16 + override val hasTPPrefetcher: Boolean = hastp } trait HasTPParams extends HasCoupledL2Parameters { diff --git a/utility b/utility index cf4e24df..708d3eb4 160000 --- a/utility +++ b/utility @@ -1 +1 @@ -Subproject commit cf4e24df4216e1e32cbc7225b6f07be5937e7e68 +Subproject commit 708d3eb44fc231608b87ac1242b28a7445fe6637