feat(Sram): add SRAM_CTL interface (#108)

* add SRAM CTL interface, include:
     * **MCR**
     * **MCW**
     * **RTSEL**
     * **WTSEL**
     * **RCT**
     * **WCT**
     * **KP**

Author: cz4e

src/main/scala/utility/mbist/MbistClockGateCell.scala

@@ -25,10 +25,10 @@ class CgDftBundle extends Bundle {
   val ram_aux_ckbp = Input(Bool())
   val cgen = Input(Bool())
   def fromBroadcast(brc: SramBroadcastBundle): Unit = {
-    ram_aux_clk := brc.ram_aux_clk
-    ram_aux_ckbp := brc.ram_aux_ckbp
-    ram_mcp_hold := brc.ram_mcp_hold
-    cgen := brc.cgen
+    ram_aux_clk := brc.mbist.ram_aux_clk
+    ram_aux_ckbp := brc.mbist.ram_aux_ckbp
+    ram_mcp_hold := brc.mbist.ram_mcp_hold
+    cgen := brc.mbist.cgen
   }
 }
 

src/main/scala/utility/sram/SRAMTemplate.scala

@@ -139,6 +139,7 @@ class SRAMWriteBus[T <: Data](
  * @param latency output setup multicycle, witch means how many cycles the data is ready for capture after read sampling clock edge.
  * @param extraHold enable a extra input hold cycle. User should keep all input for one cycle if this option is enabled.
  * @param extClockGate expose clock control signals to IOs to support using external clock gate when doing MBIST.
+ * @param hasSramCtl enable sram ctl support.
  * @param suffix add suffix in the name of SRAM wrapper
  */
 
@@ -149,7 +150,8 @@ class SRAMTemplate[T <: Data](
   useBitmask: Boolean = false, withClockGate: Boolean = false,
   separateGateClock: Boolean = false,
   hasMbist: Boolean = false, latency: Int = 1, extraHold:Boolean = false,
-  extClockGate: Boolean = false, suffix: Option[String] = None
+  extClockGate: Boolean = false, hasSramCtl: Boolean = false,
+  suffix: Option[String] = None
 )(implicit valName: sourcecode.FullName) extends Module {
   val io = IO(new Bundle {
     val r = Flipped(new SRAMReadBus(gen, set, way))
@@ -191,6 +193,7 @@ class SRAMTemplate[T <: Data](
     latency = latency,
     bist = hasMbist,
     broadcast = io.broadcast,
+    hasSramCtl = hasSramCtl,
     rclk,
     Some(wclk),
     suffix = suffix.getOrElse(SramHelper.getSramSuffix(valName.value)),
@@ -264,7 +267,7 @@ class SRAMTemplate[T <: Data](
   }
 
   private val ramRdata = SramProto.read(array, singlePort, ramRaddr, ramRen)
-  when(ramWen && !brcBd.ram_hold) {
+  when(ramWen && !brcBd.mbist.ram_hold) {
     SramProto.write(array, singlePort, ramWaddr, ramWdata, ramWmask)
   }
 
@@ -338,7 +341,7 @@ class SRAMTemplate[T <: Data](
 
 /**
  * Split large SRAM into smaller ones. This class draws inspiration from coupledL2-SplittedSRAM
- * Since the SplittedSRAM class cannot be fully compatible with the parameters of the 
+ * Since the SplittedSRAM class cannot be fully compatible with the parameters of the
  * FoldedSRAMTemplate class, the SplittedSRAMTemplate class is therefore defined.
  */
 class SplittedSRAMTemplate[T <: Data]
@@ -351,7 +354,8 @@ class SplittedSRAMTemplate[T <: Data]
   useBitmask: Boolean = false, withClockGate: Boolean = false,
   separateGateClock: Boolean = false,
   hasMbist: Boolean = false, latency: Int = 1, extraHold:Boolean = false,
-  extClockGate: Boolean = false, suffix: Option[String] = None  
+  extClockGate: Boolean = false, hasSramCtl: Boolean = false,
+  suffix: Option[String] = None
 )(implicit valName: sourcecode.FullName) extends Module {
   val io = IO(new Bundle() {
     val r = Flipped(new SRAMReadBus(gen, set, way))
@@ -381,7 +385,8 @@ class SplittedSRAMTemplate[T <: Data]
     holdRead, bypassWrite,
     useBitmask,withClockGate,
     separateGateClock, hasMbist, latency, extraHold,
-    extClockGate, Some(suffix.getOrElse(SramHelper.getSramSuffix(valName.value)))
+    extClockGate, hasSramCtl,
+    Some(suffix.getOrElse(SramHelper.getSramSuffix(valName.value)))
     ))
   )))
 
@@ -399,7 +404,6 @@ class SplittedSRAMTemplate[T <: Data]
         if (array(i)(j)(k).extra_reset.isDefined) {
           array(i)(j)(k).extra_reset.get := extra_reset.get
         }
-        
         array(i)(j)(k).io.r.req.bits.apply(r_setIdx)
         array(i)(j)(k).io.r.req.valid := io.r.req.valid && ren
         array(i)(j)(k).io.w.req.valid := io.w.req.valid && wen // && needWrite
@@ -412,7 +416,7 @@ class SplittedSRAMTemplate[T <: Data]
           array(i)(j)(k).io.w.req.bits.apply(
             VecInit(io.w.req.bits.data.slice(innerWays * j, innerWays * (j+1)).map(_.asUInt(innerWidth * (k+1) - 1, innerWidth * k))),
             w_setIdx, waymask
-          )          
+          )
         }
 
       }
@@ -470,7 +474,8 @@ class FoldedSRAMTemplate[T <: Data](
   bypassWrite: Boolean = false, useBitmask: Boolean = false,
   withClockGate: Boolean = false, avoidSameAddr: Boolean = false,
   separateGateClock: Boolean = false, // no effect, only supports independent RW cg, only for API compatibility
-  hasMbist: Boolean = false, latency: Int = 1, suffix: Option[String] = None
+  hasMbist: Boolean = false, latency: Int = 1,
+  hasSramCtl: Boolean = false, suffix: Option[String] = None
 )(implicit valName: sourcecode.FullName) extends Module {
   val io = IO(new Bundle {
     val r = Flipped(new SRAMReadBus(gen, set, way))
@@ -491,7 +496,7 @@ class FoldedSRAMTemplate[T <: Data](
     shouldReset=shouldReset, extraReset=extraReset, holdRead=holdRead,
     singlePort=singlePort, bypassWrite=bypassWrite, useBitmask=useBitmask,
     withClockGate=withClockGate, separateGateClock=separateGateClock,
-    hasMbist=hasMbist, latency=latency, extraHold = false,
+    hasMbist=hasMbist, latency=latency, extraHold = false, hasSramCtl = hasSramCtl,
     suffix = Some(suffix.getOrElse(SramHelper.getSramSuffix(valName.value)))))
   if (array.extra_reset.isDefined) {
     array.extra_reset.get := extra_reset.get
@@ -580,14 +585,15 @@ class FoldedSRAMTemplate[T <: Data](
   }
 }
 class SRAMTemplateWithArbiter[T <: Data](nRead: Int, gen: T, set: Int, way: Int = 1,
-  shouldReset: Boolean = false, hasMbist:Boolean = false, latency:Int = 1) extends Module {
+  shouldReset: Boolean = false, hasMbist:Boolean = false, latency:Int = 1,
+  hasSramCtl: Boolean = false) extends Module {
   val io = IO(new Bundle {
     val r = Flipped(Vec(nRead, new SRAMReadBus(gen, set, way)))
     val w = Flipped(new SRAMWriteBus(gen, set, way))
   })
 
   val ram = Module(new SRAMTemplate(gen, set, way, shouldReset = shouldReset, holdRead = false, singlePort = true,
-    hasMbist = hasMbist, latency = latency))
+    hasMbist = hasMbist, latency = latency, hasSramCtl = hasSramCtl))
   ram.io.w <> io.w
 
   val readArb = Module(new Arbiter(chiselTypeOf(io.r(0).req.bits), nRead))

src/main/scala/utility/sram/SramCtl.scala

@@ -0,0 +1,31 @@
+/**************************************************************************************
+ * Copyright (c) 2025 Institute of Computing Technology, CAS
+ * Copyright (c) 2025 University of Chinese Academy of Sciences
+ *
+ * NutShell is licensed under Mulan PSL v2.
+ * You can use this software according to the terms and conditions of the Mulan PSL v2.
+ * You may obtain a copy of Mulan PSL v2 at:
+ *             http://license.coscl.org.cn/MulanPSL2
+ *
+ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR
+ * FIT FOR A PARTICULAR PURPOSE.
+ *
+ * See the Mulan PSL v2 for more details.
+ ***************************************************************************************/
+
+package utility.sram
+
+import chisel3._
+import chisel3.util._
+import chisel3.experimental.hierarchy.core.Instance
+
+class SramCtlBundle extends Bundle {
+  val MCR   = UInt(2.W)
+  val MCW   = UInt(2.W)
+  val RTSEL = UInt(2.W)
+  val WTSEL = UInt(2.W)
+  val RCT   = UInt(2.W)
+  val WCT   = UInt(2.W)
+  val KP    = UInt(3.W)
+}

src/main/scala/utility/sram/SramHelper.scala

@@ -134,6 +134,7 @@ object SramHelper {
     latency: Int,
     bist: Boolean,
     broadcast: Option[SramBroadcastBundle],
+    hasSramCtl: Boolean,
     rclk: Clock,
     wclk: Option[Clock],
     suffix: String,
@@ -142,7 +143,7 @@ object SramHelper {
     template: RawModule
   ): (Ram2Mbist, Instance[SramArray], String) = {
 
-    val (array, vname) = SramProto(rclk, !dp, set, sp.sramDataBits, sp.sramMaskBits, setup, hold, latency, wclk, bist || broadcast.isDefined, suffix)
+    val (array, vname) = SramProto(rclk, !dp, set, sp.sramDataBits, sp.sramMaskBits, setup, hold, latency, wclk, bist || broadcast.isDefined, hasSramCtl || broadcast.isDefined, suffix)
     val bdParam = Ram2MbistParams(
       sp,
       set,
@@ -164,8 +165,11 @@ object SramHelper {
     mbist.re := false.B
     mbist.wmask := Fill(sp.mbistMaskWidth, true.B)
     if(broadcast.isDefined || bist) {
-      array.mbist.get.dft_ram_bp_clken := broadcast.get.ram_bp_clken
-      array.mbist.get.dft_ram_bypass := broadcast.get.ram_bypass
+      array.mbist.get.dft_ram_bp_clken := broadcast.get.mbist.ram_bp_clken
+      array.mbist.get.dft_ram_bypass := broadcast.get.mbist.ram_bypass
+    }
+    if(broadcast.isDefined || hasSramCtl) {
+      array.sramCtl.get := broadcast.get.sramCtl
     }
     if(bist) {
       dontTouch(mbist)

src/main/scala/utility/sram/SramProto.scala

@@ -28,14 +28,19 @@ class SramMbistIO extends Bundle {
   val dft_ram_bp_clken = Input(Bool())
 }
 
+class SramMbistBundle extends Bundle {
+  val ram_hold     = Bool()
+  val ram_bypass   = Bool()
+  val ram_bp_clken = Bool()
+  val ram_aux_clk  = Bool()
+  val ram_aux_ckbp = Bool()
+  val ram_mcp_hold = Bool()
+  val cgen         = Bool()
+}
+
 class SramBroadcastBundle extends Bundle {
-  val ram_hold = Input(Bool())
-  val ram_bypass = Input(Bool())
-  val ram_bp_clken = Input(Bool())
-  val ram_aux_clk = Input(Bool())
-  val ram_aux_ckbp = Input(Bool())
-  val ram_mcp_hold = Input(Bool())
-  val cgen = Input(Bool())
+  val mbist   = Input(new SramMbistBundle)
+  val sramCtl = Input(new SramCtlBundle)
 }
 
 @instantiable
@@ -44,13 +49,16 @@ abstract class SramArray(
   width: Int,
   maskSegments: Int,
   hasMbist: Boolean,
+  hasSramCtl: Boolean,
   sramName: Option[String] = None,
   singlePort: Boolean
 )
   extends RawModule {
   require(width % maskSegments == 0)
   @public val mbist = if(hasMbist) Some(IO(new SramMbistIO)) else None
   mbist.foreach(dontTouch(_))
+  @public val sramCtl = Option.when(hasSramCtl)(IO(Input(new SramCtlBundle)))
+  sramCtl.foreach(dontTouch(_))
 
   @public val RW0 = if(singlePort) {
     Some(IO(new Bundle() {
@@ -98,8 +106,9 @@ class SramArray1P(
   width: Int,
   maskSegments: Int,
   hasMbist: Boolean,
+  hasSramCtl: Boolean,
   sramName: Option[String] = None,
-) extends SramArray(depth, width, maskSegments, hasMbist, sramName, true) {
+) extends SramArray(depth, width, maskSegments, hasMbist, hasSramCtl, sramName, true) {
   if(maskSegments > 1) {
     val dataType = Vec(maskSegments, UInt((width / maskSegments).W))
     val array = SyncReadMem(depth, dataType)
@@ -129,8 +138,9 @@ class SramArray2P(
   width: Int,
   maskSegments: Int,
   hasMbist: Boolean,
+  hasSramCtl: Boolean,
   sramName: Option[String] = None
-) extends SramArray(depth, width, maskSegments, hasMbist, sramName, false) {
+) extends SramArray(depth, width, maskSegments, hasMbist, hasSramCtl, sramName, false) {
 
   if(maskSegments > 1) {
     val dataType = Vec(maskSegments, UInt((width / maskSegments).W))
@@ -208,6 +218,7 @@ object SramProto {
     latency: Int,
     writeClock: Option[Clock] = None,
     hasMbist: Boolean,
+    hasSramCtl: Boolean,
     suffix: String = ""
   ): (Instance[SramArray], String) = {
     val mcpStr = s"s${setup}h${hold}l${latency}"
@@ -217,14 +228,14 @@ object SramProto {
     val sramName = Some(s"sram_array_${numPort}p${depth}x${width}m$maskWidth$mcpStr${mbist}_$suffix")
     if(!defMap.contains(sramName.get)) {
       val sramDef = if(singlePort) {
-        Definition(new SramArray1P(depth, width, maskSegments, hasMbist, sramName))
+        Definition(new SramArray1P(depth, width, maskSegments, hasMbist, hasSramCtl, sramName))
       } else {
-        Definition(new SramArray2P(depth, width, maskSegments, hasMbist, sramName))
+        Definition(new SramArray2P(depth, width, maskSegments, hasMbist, hasSramCtl, sramName))
       }
       defMap(sramName.get) = sramDef
     }
     val array = Instance(defMap(sramName.get))
     SramProto.init(array, singlePort, clock, writeClock)
     (array, sramName.get)
   }
-}
+}