Upd sim folders

Author: RDSik

.gitignore

@@ -2,11 +2,11 @@ sim/verilator/*
 !si5340_config_loader_tb.py
 !si5340_config_loader.sv
 !test.py
-sim/modelsim/cocotb/*
+sim/cocotb/*
 !test.py
 !si5340_config_loader_tb.py
 !wave.do
-sim/modelsim/hdlmake/*
+sim/modelsim/*
 !Manifest.py
 !wave.do
 syn/*

README.md

@@ -51,14 +51,14 @@ py config_parser.py .\Si5340-RevD-Si5340-Registers.txt
 ```bash
 py -m venv myenv
 .\myenv\Scripts\activate.ps1
-cd .\sim\modelsim\cocotb
+cd .\sim\cocotb
 py -m pytest test.py
 deactivate
 ```
 
 ### Using hdlmake:
 ```bash
-cd .\sim\modelsim\hdlmake\
+cd .\sim\modelsim\
 py -m hdlmake
 make
 ```

…delsim/cocotb/si5340_config_loader_tb.py sim/cocotb/si5340_config_loader_tb.pysim/modelsim/cocotb/si5340_config_loader_tb.py renamed to sim/cocotb/si5340_config_loader_tb.py sim/modelsim/cocotb/si5340_config_loader_tb.py renamed to sim/cocotb/si5340_config_loader_tb.py

@@ -1,5 +1,6 @@
 import cocotb
 import random
+import logging
 from cocotb.clock import Clock
 from cocotb.triggers import Timer, RisingEdge, FallingEdge, ClockCycles
 from cocotb.utils import get_sim_time
@@ -9,9 +10,14 @@
 class Test:
     def __init__(self, dut):
         self.dut = dut
+
+        self.log = logging.getLogger('cocotb.tb')
+        self.log.setLevel(logging.DEBUG)
+
         dut.arstn_i.setimmediatevalue(0)
         dut.load_i.setimmediatevalue(0)
         dut.write_i.setimmediatevalue(0)
+        
         cocotb.start_soon(Clock(self.dut.clk_i, clk_per, units = 'ns').start())
 
     async def init(self):
@@ -28,24 +34,24 @@ async def write(self, n):
         for i in range(n):
             self.dut.load_i = 1
             self.dut.write_i = 1
-            print(f"Load and Write at {get_sim_time('ns')} ns.")
+            self.dut.log.info(f"Load and Write at {get_sim_time('ns')} ns.")
             await Timer(clk_per*2, units="ns")
             self.dut.load_i = 0
             self.dut.write_i = 0
             await Timer(clk_per*256, units="ns")
-            print(f"Get cmd_ack at {get_sim_time('ns')} ns.")
+            self.dut.log.info(f"Get cmd_ack at {get_sim_time('ns')} ns.")
             await Timer(clk_per*750, units="ns")
 
     async def read(self, n):
         for i in range(n):
             self.dut.load_i = 1
             self.dut.write_i = 0
-            print(f"Load and Read at {get_sim_time('ns')} ns.")
+            self.dut.log.info(f"Load and Read at {get_sim_time('ns')} ns.")
             await Timer(clk_per*2, units="ns")
             self.dut.load_i = 0
             self.dut.write_i = 0
             await Timer(clk_per*256, units="ns")
-            print(f"Get cmd_ack at {get_sim_time('ns')} ns.")
+            self.dut.log.info(f"Get cmd_ack at {get_sim_time('ns')} ns.")
             await Timer(clk_per*1300, units="ns")
 
 @cocotb.test()

sim/modelsim/cocotb/test.py sim/cocotb/test.pysim/modelsim/cocotb/test.py renamed to sim/cocotb/test.py

@@ -6,7 +6,7 @@
 from cocotb.runner import get_runner
 
 def test_runner():
-    src = Path("../../../src")
+    src = Path("../../src")
 
     hdl_toplevel_lang = os.getenv("HDL_TOPLEVEL_LANG", "verilog")
     sim = os.getenv("SIM", "questa")

sim/modelsim/cocotb/wave.do sim/cocotb/wave.dosim/modelsim/cocotb/wave.do renamed to sim/cocotb/wave.do

@@ -13,6 +13,6 @@
     ],
 }
 
-mem_file_path = Path("../../../src")
+mem_file_path = Path("../../src")
 
-shutil.copyfile(mem_file_path / 'config.mem', 'config.mem')
+shutil.copyfile(mem_file_path / 'config.mem', 'config.mem')