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1 | | -TOP_NAME := si5340_config_loader |
2 | | -VERILATOR := verilator |
3 | | -GTKWAVE := gtkwave |
4 | | -SRC_DIR := ./ |
5 | | -TB_DIR := tb/ |
6 | | -GTKW_FILE := gtkw.gtkw |
7 | | -SRC_FILES := $(shell find $(SRC_DIR) -name '*.vh') \ |
8 | | - $(shell find $(SRC_DIR) -name '*.svh') \ |
9 | | - $(shell find $(SRC_DIR) -name '*.v') \ |
10 | | - $(shell find $(SRC_DIR) -name '*.sv') \ |
11 | | - $(shell find $(TB_DIR) -name '*.vh') \ |
12 | | - $(shell find $(TB_DIR) -name '*.svh') \ |
13 | | - $(shell find $(TB_DIR) -name '*.v') \ |
14 | | - $(shell find $(TB_DIR) -name '*.sv') |
| 1 | +TOP := si5340_config_loader |
| 2 | + |
| 3 | +SIM ?= verilator |
| 4 | +WAVE := gtkwave |
| 5 | +MACRO_FILE := $(TB_DIR)wave.do |
| 6 | + |
| 7 | +PARSER := config_parser.py |
| 8 | +PYTHON := python3 |
| 9 | +CONFIG_FILE := Si5340-RevD-Si5340-Registers.txt |
| 10 | + |
| 11 | +SRC_DIR := ./ |
| 12 | +TB_DIR := tb/ |
| 13 | + |
| 14 | +SRC_FILES += $(TB_DIR)environment.sv |
| 15 | +SRC_FILES += $(TB_DIR)si5340_config_loader_if.sv |
| 16 | +SRC_FILES += $(TB_DIR)si5340_config_loader_tb.sv |
| 17 | +SRC_FILES += $(SRC_DIR)si5340_config_loader.sv |
| 18 | +SRC_FILES += $(SRC_DIR)i2c_ctrl_if.sv |
| 19 | +SRC_FILES += $(SRC_DIR)cfg_pkg.svh |
| 20 | +SRC_FILES += $(SRC_DIR)i2c_master_bit_ctrl.v |
| 21 | +SRC_FILES += $(SRC_DIR)i2c_master_byte_ctrl.v |
| 22 | +SRC_FILES += $(SRC_DIR)i2c_master_defines.v |
| 23 | +SRC_FILES += $(SRC_DIR)timescale.v |
| 24 | + |
| 25 | +SRC_FILES += $(SRC_DIR)axis_fir_filter.sv |
| 26 | +SRC_FILES += $(SRC_DIR)acc_reg.sv |
| 27 | +SRC_FILES += $(SRC_DIR)sin_gen.sv |
15 | 28 |
|
16 | 29 | .PHONY: all clean |
17 | 30 |
|
18 | | -all: build execute simulate |
| 31 | +all: mem_gen build run wave |
| 32 | + |
| 33 | +mem_gen: |
| 34 | + $(PYTHON) $(TB_DIR)$(PARSER) $(TB_DIR)$(CONFIG_FILE) |
19 | 35 |
|
20 | 36 | build: |
21 | | - $(VERILATOR) --binary $(SRC_FILES) --trace --trace-params --trace-structs -I$(SRC_DIR) -I$(TB_DIR) --top $(TOP_NAME)_tb |
| 37 | +ifeq ($(SIM), verilator) |
| 38 | + $(SIM) --binary $(SRC_FILES) --trace -I$(SRC_DIR) -I$(TB_DIR) --top $(TOP)_tb |
| 39 | +else ifeq ($(SIM), iverilog) |
| 40 | + $(SIM) -o $(TOP_NAME) $(SRC_FILES) |
| 41 | +else ifeq ($(SIM), questa) |
| 42 | + vsim -do $(MACRO_FILE) |
22 | 43 |
|
23 | | -execute: |
24 | | - ./obj_dir/V$(TOP_NAME)_tb |
| 44 | +run: |
| 45 | +ifeq ($(SIM), verilator) |
| 46 | + ./obj_dir/V$(TOP)_tb |
| 47 | +else ifeq ($(SIM), iverilog) |
| 48 | + vvp $(TOP_NAME) |
| 49 | +endif |
25 | 50 |
|
26 | | -simulate: |
27 | | - $(GTKWAVE) $(GTKW_FILE) |
| 51 | +wave: |
| 52 | +ifneq ($(SIM), questa) |
| 53 | + $(WAVE) $(TOP)_tb.vcd |
| 54 | +endif |
28 | 55 |
|
29 | 56 | clean: |
30 | 57 | rm -rf obj_dir |
31 | | - rm $(TOP_NAME)_tb.vcd |
| 58 | + rm *.vcd |
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