Upd tb and create Makefile for docker

Author: RDSik

.gitignore

@@ -9,17 +9,10 @@ sim/modelsim/*
 sim/vivado/*
 !Manifest.py
 !xsim.tcl
-sim/iverilog/*
-!Manifest.py
-sim/cocotb/modelsim/*
+sim/cocotb/*
 !transceiver_tb.py
 !test.py
 !wave.do
-sim/cocotb/icarus/*
-!transceiver_tb.py
-!transceiver_top.v
-!test.py
-!gtkw.gtkw
 platform/xilinx/clk_wiz/*
 !clk_wiz.xci
 myenv

Dockerfile

@@ -20,8 +20,6 @@ RUN git clone https://github.com/steveicarus/iverilog && \
 
 COPY . .
 
-# RUN git clone --recurse-submodules https://github.com/RDSik/verilog-transceiver.git && \
 RUN cd top && \
-    iverilog -o transceiver tb/transceiver_tb.v transceiver_top.v ../modules/bpsk/bpsk_modulator.v  ../modules/bpsk/bpsk_demodulator.v ../modules/bpsk/sin_generator.v ../modules/hamming/hamming_decoder.v ../modules/hamming/hamming_encoder.v  ../modules/uart/UART/Verilog/source/UART_RX.v ../modules/uart/UART/Verilog/source/UART_TX.v && \
-    vvp transceiver
-    
+    make
+    

modules/bpsk/tb/bpsk_modulator_tb.v

@@ -6,38 +6,38 @@ reg        clk;
 reg        arstn;
 reg        en;
 reg [11:0] data;
-reg [11:0] sine_in;
-reg [11:0] neg_sine_in;
+reg [11:0] sin_in;
+reg [11:0] neg_sin_in;
 reg [7:0]  cnt_in;
 
 wire [11:0] signal_out;
 wire [3:0]  sel_cnt;
 wire [11:0] sel;
 
-reg [11:0] sine_rom [255:0];
-reg [11:0] neg_sine_rom [255:0];
+reg [0:11] sin_rom [0:255];
+reg [0:11] neg_sin_rom [0:255];
 
 integer i;
 
 initial 
     begin
-        $readmemb("sine_value.dat", sine_rom);
-        $readmemb("neg_sine_value.dat", neg_sine_rom);
+        $readmemb("sin_value.dat", sin_rom);
+        $readmemb("neg_sine_valu.dat", neg_sin_rom);
     end
 
 bpsk_modulator #(
     .SAMPLE_NUMBER (256),
     .SAMPLE_WIDTH  (12),
     .DATA_WIDTH    (12)
 ) dut (
-    .clk         (clk),
-    .arstn       (arstn),
-    .en          (en),
-    .data        (data),
-    .sine_in     (sine_in),
-    .neg_sine_in (neg_sine_in),
-    .cnt_in      (cnt_in), 
-    .signal_out  (signal_out)
+    .clk        (clk),
+    .arstn      (arstn),
+    .en         (en),
+    .data       (data),
+    .sin_in     (sin_in),
+    .neg_sin_in (neg_sin_in),
+    .cnt_in     (cnt_in), 
+    .signal_out (signal_out)
 );
 
 assign sel_cnt = dut.sel_cnt;
@@ -49,8 +49,8 @@ initial begin
     #1; arstn = 1; en = 1;
     for (i = 0; i <= 2500; i = i + 1) begin
         #2; cnt_in = i; 
-        sine_in = sine_rom[cnt_in]; 
-        neg_sine_in = neg_sine_rom[cnt_in]; 
+        sin_in = sin_rom[cnt_in]; 
+        neg_sin_in = neg_sin_rom[cnt_in]; 
     end 
 end
 

modules/bpsk/tb/bpsk_top_tb.v

@@ -19,7 +19,7 @@ bpsk_top #(
     .DATA_WIDTH    (12)
 ) dut (
     .clk   (clk),
-    .rst_n (arstn),
+    .arstn (arstn),
     .en    (en),
     .data  (data),
     .q     (q)

modules/bpsk/tb/sin_generator_tb.v

@@ -0,0 +1,42 @@
+`timescale 1ps / 1ps
+
+module sin_generator_tb();
+
+reg         clk;
+reg         arstn;
+reg         en;
+
+wire [11:0] sin_out;
+wire [11:0] neg_sin_out;
+wire [7:0]  cnt_out;
+
+sin_generator #(
+    .SAMPLE_NUMBER (256),
+    .SAMPLE_WIDTH  (12)
+) dut (
+    .clk         (clk),
+    .arstn       (arstn),
+    .en          (en),
+    .sin_out     (sin_out),
+    .neg_sin_out (neg_sin_out),
+    .cnt_out     (cnt_out)
+);
+
+initial begin        
+    clk = 0;
+    #1; arstn = 0; en = 0;
+    #1; arstn = 1; en = 1;
+end
+
+always #1 clk = ~clk;
+
+initial 
+    $monitor("time=%g, clk=%b, sin_out=%b, neg_sin_out=%b, cnt_out=%b", $time, clk, sin_out, neg_sin_out, cnt_out);
+	
+initial begin
+    $dumpfile("out.vcd");
+    $dumpvars(0, sin_generator_tb);
+    #8000 $stop;
+end
+
+endmodule

modules/bpsk/tb/sine_generator_tb.v

@@ -13,15 +13,15 @@ module humming_coder12_8 (
 
     hamming_encoder HE(
         .clk    (clk   ),
-        .rst_n  (arstn ),
+        .arstn  (arstn ),
         .wren   (wren  ),
         .data   (data  ),
         .hc_out (hc_out)
     );
 
     hamming_decoder HD(
         .clk   (clk  ),
-        .rst_n (arstn),
+        .arstn (arstn),
         .rden  (rden ),        
         .q     (q    ),
         .hc_in (hc_in)