Unspecified I/O Standard: [...] Problem ports: code[2:0], clk, led, and ok.

[milannedic]

Hello,

Ubuntu 20.04.x + Vivado 2022.1 user here (same result on Vivado 2023.1 as well)
I recently bought Nitefury board and I am having problems regenerating bitstream from sample project from this repo.

[DRC NSTD-1] Unspecified I/O Standard: 6 out of 6 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: code[2:0], clk, led, and ok.

[DRC UCIO-1] Unconstrained Logical Port: 6 out of 6 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: code[2:0], clk, led, and ok.

Does anyone have an idea how to get over this? How can I add additional constraints to solve this?
Here is the location of mentioned ports:

Clock comes from MIG

Existing constraints are default constraints from this repo, no changes.
https://github.com/RHSResearchLLC/NiteFury-and-LiteFury/tree/master/Sample-Projects/Project-0/FPGA/common/Constraints

Thank you for your help.

[milannedic]

https://github.com/RHSResearchLLC/NiteFury-and-LiteFury/issues/56

I now see the same topic listed under Closed issues. Unfortunately, poster doesnt remember how exactly this issue was solved. So, someone please share their ideas. Big thanks

[vrbadev]

I faced the same issue with Vivado 2024.1. The CodeBlinker project in this repo contains multiple bugs.
To fix the errors [DRC NSTD-1] and [DRC UCIO-1], you should set properties of the pins mentioned in the error messages, I appended these lines to the end of the file normal.xdc:

set_property IOSTANDARD LVCMOS33 [get_ports {code[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {code[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {code[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports led]
set_property IOSTANDARD LVCMOS33 [get_ports ok]

set_property PACKAGE_PIN N15 [get_ports {code[0]}]
set_property PACKAGE_PIN R17 [get_ports {code[1]}]
set_property PACKAGE_PIN P16 [get_ports {code[2]}]
set_property PACKAGE_PIN U20 [get_ports clk]
set_property PACKAGE_PIN N13 [get_ports led]
set_property PACKAGE_PIN N14 [get_ports ok]

The IO standard for the Bank 14 should probably be LVCMOS33, not LVCMOS18. But the PDF schematics in this repo are not correct, it shows different connections than the connections configured in Vivado. Also, the Nitefury-II board contains s25fl256sxxxxxx0-spi-x1_x2_x4 configuration memory which is 256Mb, not the 128Mb version shown in the schamtic. Maybe @RHSResearchLLC could explain all the differences and also update the schematics and project files in this repo?

Don't use the Vivado constraint editor to make changes. Because when you save the changes, it will remove most of constraints from the xdc file and you will have to restore the missing parts from the xdc file in this repo.

Anyway, if you also edit the make-mcs.tcl script in the Scripts folder and replace TopWrapper.bit with CodeBlinker.bit, then you should be able to run the rebuild script from the Tcl Console (with the project opened):

cd [get_property DIRECTORY [current_project]]
source ../../common/Scripts/rebuild.tcl

[milannedic]

@vrbadev

I wasnt able to do anything useful with the design they provided. I ended up following step by step here:
https://numato.com/kb/create-pcie-dma-example-design-for-aller/

And this design worked, lspci shows my device and I was able to access BRAM. Unfortunately I am still unable to make any DDR3 design work, looks like everything gets stuck and device is not shown in lspci output.

Do you maybe have some DDR3 reference design to share? Thanks