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26 | 26 |
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27 | 27 | #include "../../../sensorinterface/RegisterInterface.h"
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28 | 28 | #include "callbacks.h"
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| 29 | +#include "sensors/softfusion/magdriver.h" |
29 | 30 |
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30 | 31 | namespace SlimeVR::Sensors::SoftFusion::Drivers {
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31 | 32 |
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@@ -104,6 +105,77 @@ struct ICM45Base {
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104 | 105 |
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105 | 106 | static constexpr uint8_t FifoCount = 0x12;
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106 | 107 | static constexpr uint8_t FifoData = 0x14;
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| 108 | + |
| 109 | + // Indirect Register Access |
| 110 | + |
| 111 | + static constexpr uint32_t IRegWaitTimeMicros = 4; |
| 112 | + |
| 113 | + enum class Bank : uint8_t { |
| 114 | + IMemSram = 0x00, |
| 115 | + IPregBar = 0xa0, |
| 116 | + IPregSys1 = 0xa4, |
| 117 | + IPregSys2 = 0xa5, |
| 118 | + IPregTop1 = 0xa2, |
| 119 | + }; |
| 120 | + |
| 121 | + static constexpr uint8_t IRegAddr = 0x7c; |
| 122 | + static constexpr uint8_t IRegData = 0x7e; |
| 123 | + |
| 124 | + // Mag Support |
| 125 | + |
| 126 | + struct IOCPadScenarioAuxOvrd { |
| 127 | + static constexpr uint8_t reg = 0x30; |
| 128 | + static constexpr uint8_t value = (0b1 << 4) // Enable AUX1 override |
| 129 | + | (0b01 << 2) // Enable I2CM master |
| 130 | + | (0b1 << 1) // Enable AUX1 enable override |
| 131 | + | (0b1 << 0); // Enable AUX1 |
| 132 | + }; |
| 133 | + |
| 134 | + struct I2CMCommand0 { |
| 135 | + static constexpr Bank bank = Bank::IPregTop1; |
| 136 | + static constexpr uint8_t reg = 0x06; |
| 137 | + }; |
| 138 | + |
| 139 | + struct I2CMDevProfile0 { |
| 140 | + static constexpr Bank bank = Bank::IPregTop1; |
| 141 | + static constexpr uint8_t reg = 0x0e; |
| 142 | + }; |
| 143 | + |
| 144 | + struct I2CMDevProfile1 { |
| 145 | + static constexpr Bank bank = Bank::IPregTop1; |
| 146 | + static constexpr uint8_t reg = 0x0f; |
| 147 | + }; |
| 148 | + |
| 149 | + struct I2CMWrData0 { |
| 150 | + static constexpr Bank bank = Bank::IPregTop1; |
| 151 | + static constexpr uint8_t reg = 0x33; |
| 152 | + }; |
| 153 | + |
| 154 | + struct I2CMRdData0 { |
| 155 | + static constexpr Bank bank = Bank::IPregTop1; |
| 156 | + static constexpr uint8_t reg = 0x1b; |
| 157 | + }; |
| 158 | + |
| 159 | + struct DmpExtSenOdrCfg { |
| 160 | + // TODO: todo |
| 161 | + }; |
| 162 | + |
| 163 | + struct I2CMControl { |
| 164 | + static constexpr Bank bank = Bank::IPregTop1; |
| 165 | + static constexpr uint8_t reg = 0x16; |
| 166 | + }; |
| 167 | + |
| 168 | + struct I2CMStatus { |
| 169 | + static constexpr Bank bank = Bank::IPregTop1; |
| 170 | + static constexpr uint8_t reg = 0x18; |
| 171 | + |
| 172 | + static constexpr uint8_t SDAErr = 0b1 << 5; |
| 173 | + static constexpr uint8_t SCLErr = 0b1 << 4; |
| 174 | + static constexpr uint8_t SRSTErr = 0b1 << 3; |
| 175 | + static constexpr uint8_t TimeoutErr = 0b1 << 2; |
| 176 | + static constexpr uint8_t Done = 0b1 << 1; |
| 177 | + static constexpr uint8_t Busy = 0b1 << 0; |
| 178 | + }; |
107 | 179 | };
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108 | 180 |
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109 | 181 | #pragma pack(push, 1)
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@@ -149,6 +221,11 @@ struct ICM45Base {
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149 | 221 | BaseRegs::PwrMgmt0::value
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150 | 222 | );
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151 | 223 |
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| 224 | + m_RegisterInterface.writeReg( |
| 225 | + BaseRegs::IOCPadScenarioAuxOvrd::reg, |
| 226 | + BaseRegs::IOCPadScenarioAuxOvrd::value |
| 227 | + ); |
| 228 | + |
152 | 229 | read_buffer.resize(FullFifoEntrySize * MaxReadings);
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153 | 230 |
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154 | 231 | delay(1);
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@@ -231,6 +308,130 @@ struct ICM45Base {
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231 | 308 | }
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232 | 309 | }
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233 | 310 | }
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| 311 | + |
| 312 | + template <typename Reg> |
| 313 | + uint8_t readBankRegister() { |
| 314 | + uint8_t buffer; |
| 315 | + readBankRegister<Reg>(&buffer, sizeof(buffer)); |
| 316 | + return buffer; |
| 317 | + } |
| 318 | + |
| 319 | + template <typename Reg, typename T> |
| 320 | + void readBankRegister(T* buffer, size_t length) { |
| 321 | + uint8_t data[] = { |
| 322 | + static_cast<uint8_t>(Reg::bank), |
| 323 | + Reg::reg, |
| 324 | + }; |
| 325 | + |
| 326 | + auto* bufferBytes = reinterpret_cast<uint8_t*>(buffer); |
| 327 | + m_RegisterInterface.writeBytes(BaseRegs::IRegAddr, sizeof(data), data); |
| 328 | + delayMicroseconds(BaseRegs::IRegWaitTimeMicros); |
| 329 | + for (size_t i = 0; i < length * sizeof(T); i++) { |
| 330 | + bufferBytes[i] = m_RegisterInterface.readReg(BaseRegs::IRegData); |
| 331 | + delayMicroseconds(BaseRegs::IRegWaitTimeMicros); |
| 332 | + } |
| 333 | + } |
| 334 | + |
| 335 | + template <typename Reg> |
| 336 | + void writeBankRegister() { |
| 337 | + writeBankRegister<Reg>(&Reg::value, sizeof(Reg::value)); |
| 338 | + } |
| 339 | + |
| 340 | + template <typename Reg, typename T> |
| 341 | + void writeBankRegister(T* buffer, size_t length) { |
| 342 | + auto* bufferBytes = reinterpret_cast<uint8_t*>(buffer); |
| 343 | + |
| 344 | + uint8_t data[] = { |
| 345 | + static_cast<uint8_t>(Reg::bank), |
| 346 | + Reg::reg, |
| 347 | + bufferBytes[0], |
| 348 | + }; |
| 349 | + |
| 350 | + m_RegisterInterface.writeBytes(BaseRegs::IRegAddr, sizeof(data), data); |
| 351 | + delayMicroseconds(BaseRegs::IRegWaitTimeMicros); |
| 352 | + for (size_t i = 1; i < length * sizeof(T); i++) { |
| 353 | + m_RegisterInterface.writeReg(BaseRegs::IRegData, bufferBytes[i]); |
| 354 | + delayMicroseconds(BaseRegs::IRegWaitTimeMicros); |
| 355 | + } |
| 356 | + } |
| 357 | + |
| 358 | + template <typename Reg> |
| 359 | + void writeBankRegister(uint8_t value) { |
| 360 | + writeBankRegister<Reg>(&value, sizeof(value)); |
| 361 | + } |
| 362 | + |
| 363 | + void setAuxId(uint8_t deviceId) { |
| 364 | + writeBankRegister<typename BaseRegs::I2CMDevProfile1>(deviceId); |
| 365 | + } |
| 366 | + |
| 367 | + uint8_t readAux(uint8_t address) { |
| 368 | + writeBankRegister<typename BaseRegs::I2CMDevProfile0>(address); |
| 369 | + |
| 370 | + writeBankRegister<typename BaseRegs::I2CMCommand0>( |
| 371 | + (0b1 << 7) // Last transaction |
| 372 | + | (0b0 << 6) // Channel 0 |
| 373 | + | (0b01 << 4) // Read with register |
| 374 | + | (0b0001 << 0) // Read 1 byte |
| 375 | + ); |
| 376 | + writeBankRegister<typename BaseRegs::I2CMControl>( |
| 377 | + (0b0 << 6) // No restarts |
| 378 | + | (0b0 << 3) // Fast mode |
| 379 | + | (0b1 << 0) // Start transaction |
| 380 | + ); |
| 381 | + |
| 382 | + uint8_t lastStatus; |
| 383 | + while ((lastStatus = readBankRegister<typename BaseRegs::I2CMStatus>()) |
| 384 | + & BaseRegs::I2CMStatus::Busy) |
| 385 | + ; |
| 386 | + |
| 387 | + if (lastStatus != BaseRegs::I2CMStatus::Done) { |
| 388 | + m_Logger.error( |
| 389 | + "Aux read from address 0x%02x returned status 0x%02x", |
| 390 | + address, |
| 391 | + lastStatus |
| 392 | + ); |
| 393 | + } |
| 394 | + |
| 395 | + return readBankRegister<typename BaseRegs::I2CMRdData0>(); |
| 396 | + } |
| 397 | + |
| 398 | + void writeAux(uint8_t address, uint8_t value) { |
| 399 | + writeBankRegister<typename BaseRegs::I2CMDevProfile0>(address); |
| 400 | + writeBankRegister<typename BaseRegs::I2CMWrData0>(value); |
| 401 | + writeBankRegister<typename BaseRegs::I2CMCommand0>( |
| 402 | + (0b1 << 7) // Last transaction |
| 403 | + | (0b0 << 6) // Channel 0 |
| 404 | + | (0b01 << 4) // Read with register |
| 405 | + | (0b0001 << 0) // Read 1 byte |
| 406 | + ); |
| 407 | + writeBankRegister<typename BaseRegs::I2CMControl>( |
| 408 | + (0b0 << 6) // No restarts |
| 409 | + | (0b0 << 3) // Fast mode |
| 410 | + | (0b1 << 0) // Start transaction |
| 411 | + ); |
| 412 | + |
| 413 | + uint8_t lastStatus; |
| 414 | + while ((lastStatus = readBankRegister<typename BaseRegs::I2CMStatus>()) |
| 415 | + & BaseRegs::I2CMStatus::Busy) |
| 416 | + ; |
| 417 | + |
| 418 | + if (lastStatus != BaseRegs::I2CMStatus::Done) { |
| 419 | + m_Logger.error( |
| 420 | + "Aux write to address 0x%02x with value 0x%02x returned status 0x%02x", |
| 421 | + address, |
| 422 | + value, |
| 423 | + lastStatus |
| 424 | + ); |
| 425 | + } |
| 426 | + } |
| 427 | + |
| 428 | + void startAuxPolling(uint8_t dataReg, MagDataWidth dataWidth) { |
| 429 | + // TODO: |
| 430 | + } |
| 431 | + |
| 432 | + void stopAuxPolling() { |
| 433 | + // TODO: |
| 434 | + } |
234 | 435 | };
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235 | 436 |
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236 | 437 | }; // namespace SlimeVR::Sensors::SoftFusion::Drivers
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