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Anciety
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Merge pull request #24 from ioo0s/mode_set
Add disasm mode setting support. This should close #23
2 parents ad80245 + 9a6dbae commit d715b3e

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+335
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‎bindings/python/Cargo.toml‎

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Original file line numberDiff line numberDiff line change
@@ -13,6 +13,7 @@ classifier = [
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[dependencies]
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sleighcraft = { path = "../../sleighcraft" }
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num_enum = "0.5.1"
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[dependencies.pyo3]
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version = "0.13.2"

‎bindings/python/bincraft/__init__.py‎

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@@ -13,4 +13,237 @@
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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from .bincraft import *
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from .bincraft import *
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__all__ = [
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'Sleigh',
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'ARCH_6502',
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'ARCH_6805',
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'ARCH_6809',
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'ARCH_8048',
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'ARCH_8051',
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'ARCH_8085',
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'ARCH_68020',
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'ARCH_68030',
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'ARCH_68040',
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'ARCH_80251',
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'ARCH_80390',
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'ARCH_AARCH64',
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'ARCH_AARCH64BE',
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'ARCH_ARM4_BE',
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'ARCH_ARM4_LE',
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'ARCH_ARM4T_BE',
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'ARCH_ARM4T_LE',
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'ARCH_ARM5_BE',
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'ARCH_ARM5_LE',
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'ARCH_ARM5T_BE',
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'ARCH_ARM5T_LE',
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'ARCH_ARM6_BE',
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'ARCH_ARM6_LE',
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'ARCH_ARM7_BE',
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'ARCH_ARM7_LE',
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'ARCH_ARM8_BE',
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'ARCH_ARM8_LE',
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'ARCH_AVR8',
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'ARCH_AVR8E',
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'ARCH_AVR8EIND',
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'ARCH_AVR8XMEGA',
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'ARCH_AVR32A',
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'ARCH_COLDFIRE',
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'ARCH_CP1600',
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'ARCH_CR16B',
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'ARCH_CR16C',
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'ARCH_DALVIK',
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'ARCH_DATA_BE_64',
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'ARCH_DATA_LE_64',
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'ARCH_DSPIC30F',
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'ARCH_DSPIC33C',
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'ARCH_DSPIC33E',
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'ARCH_DSPIC33F',
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'ARCH_HC05',
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'ARCH_HC08',
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'ARCH_HCS08',
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'ARCH_HCS12',
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'ARCH_JVM',
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'ARCH_M8C',
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'ARCH_MCS96',
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'ARCH_MIPS32BE',
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'ARCH_MIPS32LE',
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'ARCH_MIPS32R6BE',
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'ARCH_MIPS32R6LE',
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'ARCH_MIPS64BE',
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'ARCH_MIPS64LE',
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'ARCH_MX51',
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'ARCH_PA_RISC32BE',
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'ARCH_PIC12C5XX',
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'ARCH_PIC16',
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'ARCH_PIC16C5X',
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'ARCH_PIC16F',
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'ARCH_PIC17C7XX',
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'ARCH_PIC18',
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'ARCH_PIC24E',
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'ARCH_PIC24F',
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'ARCH_PIC24H',
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'ARCH_PPC_32_4XX_BE',
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'ARCH_PPC_32_4XX_LE',
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'ARCH_PPC_32_BE',
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'ARCH_PPC_32_LE',
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'ARCH_PPC_32_QUICCIII_BE',
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'ARCH_PPC_32_QUICCIII_LE',
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'ARCH_PPC_64_BE',
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'ARCH_PPC_64_ISA_ALTIVEC_BE',
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'ARCH_PPC_64_ISA_ALTIVEC_LE',
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'ARCH_PPC_64_ISA_ALTIVEC_VLE_BE',
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'ARCH_PPC_64_ISA_BE',
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'ARCH_PPC_64_ISA_LE',
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'ARCH_PPC_64_ISA_VLE_BE',
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'ARCH_PPC_64_LE',
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'ARCH_RISCV',
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'ARCH_SH_1',
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'ARCH_SH_2',
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'ARCH_SH_2A',
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'ARCH_SPARCV9_32',
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'ARCH_SPARCV9_64',
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'ARCH_SUPERH4_BE',
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'ARCH_SUPERH4_LE',
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'ARCH_TI_MSP430',
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'ARCH_TI_MSP430X',
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'ARCH_TOY_BE_POSSTACK',
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'ARCH_TOY_BE',
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'ARCH_TOY_BUILDER_BE_ALIGN2',
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'ARCH_TOY_BUILDER_BE',
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'ARCH_TOY_BUILDER_LE_ALIGN2',
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'ARCH_TOY_BUILDER_LE',
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'ARCH_TOY_LE',
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'ARCH_TOY_WSZ_BE',
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'ARCH_TOY_WSZ_LE',
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'ARCH_TOY64_BE_HARVARD',
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'ARCH_TOY64_BE',
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'ARCH_TOY64_LE',
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'ARCH_TRICORE',
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'ARCH_V850',
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'ARCH_X86_64',
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'ARCH_X86',
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'ARCH_Z80',
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'ARCH_Z180',
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'MODE_16',
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'MODE_32',
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'MODE_64',
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]
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# arch
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ARCH_6502 = "6502"
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ARCH_6805 = "6805"
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ARCH_6809 = "6809"
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ARCH_8048 = "8048"
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ARCH_8051 = "8051"
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ARCH_8085 = "8085"
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ARCH_68020 = "68020"
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ARCH_68030 = "68030"
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ARCH_68040 = "68040"
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ARCH_80251 = "80251"
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ARCH_80390 = "80390"
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ARCH_AARCH64 = "AARCH64"
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ARCH_AARCH64BE = "AARCH64BE"
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ARCH_ARM4_BE = "ARM4_be"
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ARCH_ARM4_LE = "ARM4_le"
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ARCH_ARM4T_BE = "ARM4t_be"
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ARCH_ARM4T_LE = "ARM4t_le"
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ARCH_ARM5_BE = "ARM5_be"
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ARCH_ARM5_LE = "ARM5_le"
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ARCH_ARM5T_BE = "ARM5t_be"
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ARCH_ARM5T_LE = "ARM5t_le"
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ARCH_ARM6_BE = "ARM6_be"
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ARCH_ARM6_LE = "ARM6_le"
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ARCH_ARM7_BE = "ARM7_be"
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ARCH_ARM7_LE = "ARM7_le"
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ARCH_ARM8_BE = "ARM8_be"
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ARCH_ARM8_LE = "ARM8_le"
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ARCH_AVR8 = "avr8"
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ARCH_AVR8E = "avr8e"
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ARCH_AVR8EIND = "avr8eind"
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ARCH_AVR8XMEGA = "avr8xmega"
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ARCH_AVR32A = "avr32a"
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ARCH_COLDFIRE = "coldfire"
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ARCH_CP1600 = "CP1600"
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ARCH_CR16B = "CR16B"
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ARCH_CR16C = "CR16C"
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ARCH_DALVIK = "Dalvik"
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ARCH_DATA_BE_64 = "data-be-64"
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ARCH_DATA_LE_64 = "data-le-64"
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ARCH_DSPIC30F = "dsPIC30F"
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ARCH_DSPIC33C = "dsPIC33C"
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ARCH_DSPIC33E = "dsPIC33E"
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ARCH_DSPIC33F = "dsPIC33F"
178+
ARCH_HC05 = "HC05"
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ARCH_HC08 = "HC08"
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ARCH_HCS08 = "HCS08"
181+
ARCH_HCS12 = "HCS12"
182+
ARCH_JVM = "JVM"
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ARCH_M8C = "m8c"
184+
ARCH_MCS96 = "MCS96"
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ARCH_MIPS32BE = "mips32be"
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ARCH_MIPS32LE = "mips32le"
187+
ARCH_MIPS32R6BE = "mips32R6be"
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ARCH_MIPS32R6LE = "mips32R6le"
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ARCH_MIPS64BE = "mips64be"
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ARCH_MIPS64LE = "mips64le"
191+
ARCH_MX51 = "mx51"
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ARCH_PA_RISC32BE = "pa-risc32be"
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ARCH_PIC12C5XX = "pic12c5xx"
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ARCH_PIC16 = "pic16"
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ARCH_PIC16C5X = "pic16c5x"
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ARCH_PIC16F = "pic16f"
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ARCH_PIC17C7XX = "pic17c7xx"
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ARCH_PIC18 = "pic18"
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ARCH_PIC24E = "PIC24E"
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ARCH_PIC24F = "PIC24F"
201+
ARCH_PIC24H = "PIC24H"
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ARCH_PPC_32_4XX_BE = "ppc_32_4xx_be"
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ARCH_PPC_32_4XX_LE = "ppc_32_4xx_le"
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ARCH_PPC_32_BE = "ppc_32_be"
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ARCH_PPC_32_LE = "ppc_32_le"
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ARCH_PPC_32_QUICCIII_BE = "ppc_32_quicciii_be"
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ARCH_PPC_32_QUICCIII_LE = "ppc_32_quicciii_le"
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ARCH_PPC_64_BE = "ppc_64_be"
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ARCH_PPC_64_ISA_ALTIVEC_BE = "ppc_64_isa_altivec_be"
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ARCH_PPC_64_ISA_ALTIVEC_LE = "ppc_64_isa_altivec_le"
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ARCH_PPC_64_ISA_ALTIVEC_VLE_BE = "ppc_64_isa_altivec_vle_be"
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ARCH_PPC_64_ISA_BE = "ppc_64_isa_be"
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ARCH_PPC_64_ISA_LE = "ppc_64_isa_le"
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ARCH_PPC_64_ISA_VLE_BE = "ppc_64_isa_vle_be"
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ARCH_PPC_64_LE = "ppc_64_le"
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ARCH_RISCV = "riscv"
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ARCH_SH_1 = "sh-1"
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ARCH_SH_2 = "sh-2"
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ARCH_SH_2A = "sh-2a"
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ARCH_SPARCV9_32 = "SparcV9_32"
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ARCH_SPARCV9_64 = "SparcV9_64"
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ARCH_SUPERH4_BE = "SuperH4_be"
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ARCH_SUPERH4_LE = "SuperH4_le"
224+
ARCH_TI_MSP430 = "TI_MSP430"
225+
ARCH_TI_MSP430X = "TI_MSP430X"
226+
ARCH_TOY_BE_POSSTACK = "toy_be_posStack"
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ARCH_TOY_BE = "toy_be"
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ARCH_TOY_BUILDER_BE_ALIGN2 = "toy_builder_be_align2"
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ARCH_TOY_BUILDER_BE = "toy_builder_be"
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ARCH_TOY_BUILDER_LE_ALIGN2 = "toy_builder_le_align2"
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ARCH_TOY_BUILDER_LE = "toy_builder_le"
232+
ARCH_TOY_LE = "toy_le"
233+
ARCH_TOY_WSZ_BE = "toy_wsz_be"
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ARCH_TOY_WSZ_LE = "toy_wsz_le"
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ARCH_TOY64_BE_HARVARD = "toy64_be_harvard"
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ARCH_TOY64_BE = "toy64_be"
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ARCH_TOY64_LE = "toy64_le"
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ARCH_TRICORE = "tricore"
239+
ARCH_V850 = "V850"
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ARCH_X86_64 = "x86-64"
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ARCH_X86 = "x86"
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ARCH_Z80 = "z80"
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ARCH_Z180 = "z180"
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# disasm mode
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MODE_16 = 0
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MODE_32 = 1
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MODE_64 = 2
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‎bindings/python/src/lib.rs‎

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Original file line numberDiff line numberDiff line change
@@ -1,12 +1,12 @@
11
//
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// Copyright 2021 StarCrossTech
3-
//
3+
//
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// Licensed under the Apache License, Version 2.0 (the "License");
55
// you may not use this file except in compliance with the License.
66
// You may obtain a copy of the License at
7-
//
7+
//
88
// http://www.apache.org/licenses/LICENSE-2.0
9-
//
9+
//
1010
// Unless required by applicable law or agreed to in writing, software
1111
// distributed under the License is distributed on an "AS IS" BASIS,
1212
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@@ -17,10 +17,9 @@ use pyo3::class::basic::PyObjectProtocol;
1717
use pyo3::prelude::*;
1818
use pyo3::types::{PyList, PyLong, PyUnicode};
1919
use sleighcraft::error::Error;
20-
use sleighcraft::{
21-
arch, CollectingAssemblyEmit, CollectingPcodeEmit, PlainLoadImage, SleighBuilder,
22-
};
20+
use sleighcraft::{arch, CollectingAssemblyEmit, CollectingPcodeEmit, PlainLoadImage, SleighBuilder, Mode};
2321
use sleighcraft::{Address, Instruction, PcodeInstruction, PcodeVarnodeData};
22+
use std::convert::TryFrom;
2423

2524
#[pyclass]
2625
#[derive(Clone, PartialEq, Eq)]
@@ -263,18 +262,24 @@ impl PyInstruction {
263262
pub struct Sleigh {
264263
spec: Option<String>,
265264
code: Option<Vec<u8>>,
265+
mode: Option<Mode>
266266
}
267267

268268
#[pymethods]
269269
impl Sleigh {
270270
#[new]
271-
pub fn new(spec: &PyUnicode, code: &PyList) -> Self {
271+
#[args(mode = "0")]
272+
pub fn new(spec: &PyUnicode, code: &PyList, mode: i32) -> Self {
272273
let sp: &str = spec.extract().unwrap();
273274
let spec = arch(sp);
274275
let codes: Vec<u8> = code.extract().unwrap();
275276
let spec = Option::from(spec.unwrap().to_string());
277+
let mode = {
278+
let mode =Mode::try_from(mode);
279+
mode.ok()
280+
};
276281
let code = Option::from(codes);
277-
Sleigh { spec, code }
282+
Sleigh { spec, code, mode}
278283
}
279284

280285
#[text_signature = "($self, start, cnt)"]
@@ -285,6 +290,7 @@ impl Sleigh {
285290
let mut loader = PlainLoadImage::from_buf(self.code.as_ref().unwrap().as_ref(), start);
286291
sleigh_builder.loader(&mut loader);
287292
sleigh_builder.spec(self.spec.as_ref().unwrap().as_str());
293+
sleigh_builder.mode(self.mode.unwrap());
288294

289295
let mut asm_emit = CollectingAssemblyEmit::default();
290296
let mut pcode_emit = CollectingPcodeEmit::default();

‎sleighcraft/Cargo.toml‎

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Original file line numberDiff line numberDiff line change
@@ -13,6 +13,7 @@ repository = "https://github.com/ret2lab/bincraft/"
1313
[dependencies]
1414
cxx = "1.0"
1515
once_cell = "1.6.0"
16+
num_enum = "0.5.1"
1617

1718
[dependencies.pyo3]
1819
version = "0.13.2"

‎sleighcraft/src/cpp/bridge/disasm.cpp‎

Lines changed: 8 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -18,22 +18,28 @@
1818
#include <iostream>
1919
#include "proxies/address_proxy.hh"
2020

21-
void SleighProxy::set_spec(const rust::Str spec_content) {
21+
void SleighProxy::set_spec(const rust::Str spec_content, int mode) {
2222
stringstream ss;
2323
ss << spec_content;
2424

2525
Element *root = storage.parseDocument(ss)->getRoot();
2626
storage.registerTag(root);
2727

2828
translator.initialize(storage);
29+
30+
this->ctx.setVariableDefault("addrsize",mode);
31+
this->ctx.setVariableDefault("opsize",mode);
2932
}
3033

31-
void SleighProxy::setSpecFromPath(const rust::Str path) {
34+
void SleighProxy::setSpecFromPath(const rust::Str path,int mode) {
3235
string cxxpath = string(path);
3336
Element *root = storage.openDocument(cxxpath)->getRoot();
3437
storage.registerTag(root);
3538

3639
translator.initialize(storage);
40+
41+
this->ctx.setVariableDefault("addrsize",mode); // Address size is 32-bit
42+
this->ctx.setVariableDefault("opsize",mode); // Operand size is 32-bit
3743
}
3844

3945
unique_ptr<SleighProxy> new_sleigh_proxy(RustLoadImage &ld) {

‎sleighcraft/src/cpp/bridge/disasm.h‎

Lines changed: 2 additions & 2 deletions
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@@ -96,8 +96,8 @@ class SleighProxy {
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public:
9797
SleighProxy(RustLoadImage &ld): loader(ld), translator(&loader, &this->ctx) {}
9898

99-
void setSpecFromPath(const rust::Str path);
100-
void set_spec(const rust::Str spec_content);
99+
void setSpecFromPath(const rust::Str path, int mode);
100+
void set_spec(const rust::Str spec_content, int mode);
101101
void decode_with(RustAssemblyEmit& asm_emit, RustPcodeEmit& pcode_emit, uint64_t start);
102102

103103
private:

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