Look into performance improvements to readback implementation

[rskvprd]

Problem
I had timing and resource utilisation issues with large register map. Significant part of the logic utilisation and timing issues was in readback logic.

Solution
But when i changed implementation from Flat 1-hot array then OR reduce¹ to Flat case statement¹ (in fact, i've generated big if..else..else..else statement), utilisation was significantly reduced and timing issue was fixed.

Proposal
It would be nice to have option like --readback-mux-impl with options like orreduce and case for designs with low budget/large regmaps

Footnotes

1. See readback-mux devnotes ↩ ↩²

[amykyta3]

I will look into optimizing the readback implementation.

Can you share what technology this is for? (FPGA or ASIC)
Generally OR-reduction trees optimize very well, but perhaps this needs to be studied further. I would prefer to find a good all-around solution rather than introducing mode switches.

[rskvprd]

It was Xilinx FPGA