0.12.0

Updates:

• Create output dir prior to export (#30, PeakRDL#19)

0.11.0

Updates:

• Rework PeakRDL command-line plugin mechanism.
• Add org cfg schema to allow loading cpuif classes via PeakRDL TOML config.

0.10.0

Updates:

• Add option to override CPUIF address width. #25

0.9.0

Updates:

• Add UDPs that implement read & write double-buffering. #22
  • Enables atomic access to wide registers, or groups of multiple registers
  • See documentation for Read Buffering and Write Buffering
• Fix misinterpretation of swacc behavior. #21
  • swacc is now asserted for both read and write accesses.
• Add new rd_swacc and wr_swacc UDPs to complement new swacc property behavior.
  • See details in documentation
• Add ability to generate a HWIF report file that shows flattened struct contents. #13
• Add support for extending user-defined CPUIF using the PeakRDL command line tool plugin discovery interface.
  • See details in documentation

0.8.0

Updates:

• Add support for nonuniform regwidths and wide registers (where accesswidth < regwidth). #12
• Fix synthesizability of fields with msb0 ordering

0.7.0

Updates:

• Fix bug in hier mode hwif generation (#17)
• Add support for CPU interfaces that have write strobes. #12
• Add APB4

0.6.0

Updates:

• Add identifier filter to prevent collisions with SystemVerilog keywords (#14)
• Add PeakRDL command line application entry point hook

0.5.0

Switch to use regular non-namespaced package (See SystemRDL/PeakRDL#4)

0.4.0

Updates:

• Add workaround to AXI4-Lite cpuif template to avoid quirk in Vivado xsim handling of non-power-of-2 array indexing. #7
• axi4_cpuif: make response buffer assignments nonblocking in sequential block. #6

0.3.0

minor cosmetic updates