[BUG] an access case that should produce an error passes

[balbal1]

Describe the bug
Just a small bug I noticed, A field that has a sw access as w and hw access as na passes the compiler with no error, this case should give an error according to table 12 in the SystemRDL Standard

The issue is fairly trivial and is easily fixable by adding this case in the following condition during validation. I stumbled on it during experimenting and thought I'd share for completeness of the software.

systemrdl-compiler/src/systemrdl/core/validate.py

Line 340 in e6bd222

if (this_f_sw == rdltypes.AccessType.w) and (this_f_hw == rdltypes.AccessType.w):

[amykyta3]

You are definitely correct in your reading of Table 12. However in practice, I have found that Table 12 is pretty naive in some of its interpretations, and in more advanced RDL use-cases, some of the rows marked as "meaningless" are actually very useful constructs.

Consider the case where you want a software-writable singlepulse field that is used as an internal trigger elsewhere in the register file. In this situation, it is not useful to export the trigger's value outside of the module since it is only used internally, so setting hw = na is useful. See the example I share in this discussion: https://github.com/orgs/SystemRDL/discussions/270

For the compiler, I have chosen to loosen some of the restrictions described in Table 12 for situations that are truly useful in designs.