Skip to content

Commit 857af15

Browse files
TimRudyTim Rudy
TimRudy
authored and
Tim Rudy
committed
Add test benches and fix bugs
1 parent 7bf61a9 commit 857af15

34 files changed

+3342
-8
lines changed

‎Uart8.v

+1-1
Original file line numberDiff line numberDiff line change
@@ -33,7 +33,7 @@ module Uart8 #(
3333
);
3434

3535
// this value cannot be changed in the current implementation
36-
localparam RX_OVERSAMPLE_RATE = 16;
36+
parameter RX_OVERSAMPLE_RATE = 16;
3737

3838
wire rxClk;
3939
wire txClk;

‎Uart8Receiver.v

+7-1
Original file line numberDiff line numberDiff line change
@@ -195,7 +195,13 @@ always @(posedge clk) begin
195195
* {done} signal or the {err} signal
196196
*/
197197
sample_count <= sample_count + 4'b1;
198-
if (&sample_count[3:1]) begin // reached 14 -
198+
if (!err && !in_sample) begin
199+
// accept the trigger to start, immediately following
200+
// transmission stop
201+
valid_count <= sample_count;
202+
sample_count <= 4'b0;
203+
state <= `IDLE;
204+
end else if (&sample_count[3:1]) begin // reached 14 -
199205
// additional tick 15 comes from transitting the READY state
200206
// to the RESET state
201207
state <= `RESET;

‎Uart8Transmitter.v

+16-6
Original file line numberDiff line numberDiff line change
@@ -63,6 +63,7 @@ always @(posedge clk) begin
6363
busy <= 1'b0;
6464
done <= 1'b0;
6565
out <= 1'b1; // line is high for IDLE state
66+
bit_index <= 3'b0;
6667
if (en) begin
6768
state <= `IDLE;
6869
end
@@ -94,13 +95,22 @@ always @(posedge clk) begin
9495
end
9596

9697
`STOP_BIT: begin
97-
done <= 1'b1; // signal transmission stop (one clock cycle)
98-
out <= 1'b1; // transition to the mark state output (high)
99-
if (TURBO_FRAMES && start) begin
100-
in_data <= in; // register the input data
101-
state <= `START_BIT; // go straight to transmit
98+
done <= 1'b1; // signal transmission stop
99+
out <= 1'b1; // transition to mark state output (high)
100+
if (start) begin
101+
if (done == 1'b0) begin // this distinguishes 2 sub-states
102+
in_data <= in; // register the input data
103+
if (TURBO_FRAMES) begin
104+
state <= `START_BIT; // go straight to transmit
105+
end else begin
106+
state <= `STOP_BIT; // keep mark state one extra cycle
107+
end
108+
end else begin // there was extra cycle within this state
109+
done <= 1'b0;
110+
state <= `START_BIT; // now go to transmit
111+
end
102112
end else begin
103-
state <= `RESET; // keep mark state (high) for one extra cycle
113+
state <= `RESET;
104114
end
105115
end
106116

‎tests/1.gtkw

+44
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,44 @@
1+
[*]
2+
[*] GTKWave Analyzer v3.3.81 (w)1999-2017 BSI
3+
[*] Sun Oct 16 19:14:34 2022
4+
[*]
5+
[dumpfile] "1.vcd"
6+
[dumpfile_mtime] "Sun Oct 16 19:12:30 2022"
7+
[dumpfile_size] 1790532
8+
[savefile] "1.gtkw"
9+
[timestart] 0
10+
[size] 1536 937
11+
[pos] -1 -1
12+
*-18.545267 1555000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
13+
[treeopen] test.
14+
[treeopen] test.uart1.
15+
[treeopen] test.uart2.
16+
[sst_width] 197
17+
[signals_width] 210
18+
[sst_expanded] 1
19+
[sst_vpaned_height] 482
20+
@22
21+
test.uart1.txInst.in_data[7:0]
22+
@28
23+
test.uart1.txClk
24+
test.uart1.txEn
25+
test.uart1.txStart
26+
test.uart1.txBusy
27+
test.uart1.txDone
28+
test.uart1.txInst.bit_index[2:0]
29+
test.uart1.txInst.state[2:0]
30+
test.uart1.txInst.out
31+
test.uart2.rxClk
32+
test.uart2.rxEn
33+
test.uart2.rxBusy
34+
test.uart2.rxDone
35+
test.uart2.rxErr
36+
test.uart2.rxInst.in
37+
test.uart2.rxInst.in_sample
38+
test.uart2.rxInst.state[2:0]
39+
test.uart2.rxInst.bit_index[2:0]
40+
@22
41+
test.uart2.rxInst.received_data[7:0]
42+
test.uart2.rxInst.out[7:0]
43+
[pattern_trace] 1
44+
[pattern_trace] 0

‎tests/1.v

+131
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,131 @@
1+
`timescale 100ns/1ns
2+
`default_nettype none
3+
4+
`include "Uart8.v"
5+
6+
module test;
7+
8+
localparam CLOCK_FREQ = 12000000; // Alhambra board
9+
localparam SIM_STEP_FREQ = 1 / 0.0000001 / 2; // this sim timescale 100ns
10+
11+
// for the simulation timeline:
12+
// ratio SIM_STEP_FREQ MHz / CLOCK_FREQ MHz gives the output waveform in proper time
13+
// (*but note all clocks and the timeline are approximate due to rounding)
14+
localparam SIM_TIMESTEP_FACTOR = SIM_STEP_FREQ / CLOCK_FREQ;
15+
16+
localparam ENABLED_BAUD_CLOCK_STEPS = 17;
17+
18+
reg clk;
19+
reg en_1;
20+
reg en_2;
21+
reg txStart_1;
22+
reg txStart_2;
23+
wire txBusy_1;
24+
wire txBusy_2;
25+
wire rxBusy_1;
26+
wire rxBusy_2;
27+
wire txDone_1;
28+
wire txDone_2;
29+
wire rxDone_1;
30+
wire rxDone_2;
31+
wire rxErr_1;
32+
wire rxErr_2;
33+
reg [7:0] txByte_1;
34+
reg [7:0] txByte_2;
35+
wire [7:0] rxByte_1;
36+
wire [7:0] rxByte_2;
37+
wire bus_wire_1_2;
38+
wire bus_wire_2_1;
39+
40+
Uart8 #(.CLOCK_RATE(CLOCK_FREQ)) uart1(
41+
.clk(clk),
42+
43+
// rx interface
44+
.rxEn(en_2),
45+
.rx(bus_wire_2_1),
46+
.rxBusy(rxBusy_1),
47+
.rxDone(rxDone_1),
48+
.rxErr(rxErr_1),
49+
.out(rxByte_1),
50+
51+
// tx interface
52+
.txEn(en_1),
53+
.txStart(txStart_1),
54+
.in(txByte_1),
55+
.txBusy(txBusy_1),
56+
.txDone(txDone_1),
57+
.tx(bus_wire_1_2)
58+
);
59+
60+
Uart8 #(.CLOCK_RATE(CLOCK_FREQ)) uart2(
61+
.clk(clk),
62+
63+
// rx interface
64+
.rxEn(en_1),
65+
.rx(bus_wire_1_2),
66+
.rxBusy(rxBusy_2),
67+
.rxDone(rxDone_2),
68+
.rxErr(rxErr_2),
69+
.out(rxByte_2),
70+
71+
// tx interface
72+
.txEn(en_2),
73+
.txStart(txStart_2),
74+
.in(txByte_2),
75+
.txBusy(txBusy_2),
76+
.txDone(txDone_2),
77+
.tx(bus_wire_2_1)
78+
);
79+
80+
initial clk = 1'b0;
81+
82+
always #SIM_TIMESTEP_FACTOR clk = ~clk;
83+
84+
initial begin
85+
integer t;
86+
87+
$dumpfile(`DUMP_FILE_NAME);
88+
$dumpvars(0, test);
89+
90+
#600
91+
en_1 = 1'b0;
92+
txStart_1 = 1'b0;
93+
#600
94+
en_1 = 1'b1;
95+
96+
txByte_1 = 8'b01000101;
97+
98+
$display(" tx 1 data: %8b", txByte_1);
99+
100+
for (t = 0; t < ENABLED_BAUD_CLOCK_STEPS; t++) begin
101+
// #1000 x 100ns == 0.1ms == 1 tx clock period (approximately) at 9600 baud
102+
#1000
103+
case (t)
104+
1: begin
105+
txStart_1 = 1'b1;
106+
107+
$display("%7.2fms | tx start: %d", $realtime/10000, txStart_1);
108+
$display("%7.2fms | tx busy: %d, tx done: %d", $realtime/10000, txBusy_1, txDone_1);
109+
$display("%7.2fms | rx 2 data: %8b", $realtime/10000, rxByte_2);
110+
end
111+
4: begin
112+
txStart_1 = 1'b0;
113+
114+
$display("%7.2fms | tx start: %d", $realtime/10000, txStart_1);
115+
end
116+
13: begin
117+
// output is ready
118+
119+
$display("%7.2fms | tx busy: %d, tx done: %d", $realtime/10000, txBusy_1, txDone_1);
120+
$display("%7.2fms | rx 2 data: %8b", $realtime/10000, rxByte_2);
121+
end
122+
endcase
123+
end
124+
125+
en_1 = 1'b0;
126+
#2400
127+
128+
$finish();
129+
end
130+
131+
endmodule

‎tests/10.gtkw

+47
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,47 @@
1+
[*]
2+
[*] GTKWave Analyzer v3.3.81 (w)1999-2017 BSI
3+
[*] Sun Oct 23 01:14:48 2022
4+
[*]
5+
[dumpfile] "10.vcd"
6+
[dumpfile_mtime] "Sun Oct 23 01:13:28 2022"
7+
[dumpfile_size] 2768265
8+
[savefile] "10.gtkw"
9+
[timestart] 0
10+
[size] 1536 937
11+
[pos] -1 -1
12+
*-19.167105 1312000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
13+
[treeopen] test.
14+
[treeopen] test.uart1.
15+
[treeopen] test.uart2.
16+
[sst_width] 197
17+
[signals_width] 210
18+
[sst_expanded] 1
19+
[sst_vpaned_height] 482
20+
@22
21+
test.uart1.txInst.in[7:0]
22+
test.uart1.txInst.in_data[7:0]
23+
@28
24+
test.uart1.txClk
25+
test.uart1.txEn
26+
test.uart1.txStart
27+
test.uart1.txBusy
28+
test.uart1.txDone
29+
test.uart1.txInst.bit_index[2:0]
30+
test.uart1.txInst.state[2:0]
31+
test.uart1.txInst.out
32+
test.uart2.rxClk
33+
test.uart2.rxEn
34+
test.uart2.rxBusy
35+
test.uart2.rxDone
36+
test.uart2.rxErr
37+
test.uart2.rxInst.in
38+
test.uart2.rxInst.in_sample
39+
test.uart2.rxInst.state[2:0]
40+
test.uart2.rxInst.bit_index[2:0]
41+
@22
42+
test.uart2.rxInst.sample_count[3:0]
43+
test.uart2.rxInst.valid_count[3:0]
44+
test.uart2.rxInst.received_data[7:0]
45+
test.uart2.rxInst.out[7:0]
46+
[pattern_trace] 1
47+
[pattern_trace] 0

0 commit comments

Comments
 (0)