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Constraint files for Xilinx AC701 board.
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‎ucf/AC701/Bus.IIC.xdc

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##
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## I2C-MainBus
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## -----------------------------------------------------------------------------
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## Bank: 14
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## VCCO: 3.3V (FPGA_3V3)
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## Location: U52 (PCA9548ARGER)
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## Vendor: Texas Instruments
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## Device: PCA9548A-RGER - 8-Channel I2C Switch with Reset
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## I2C-Address: 0x74 (0111 010xb)
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## -----------------------------------------------------------------------------
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## Devices: 8
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## Channel 0: Programmable UserClock
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## Location: U34
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## Vendor: Silicon Labs
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## Device: Si570
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## Address: 0xBA (1011 101xb)
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## Channel 1: FMC Connector 1 (HPC)
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## Location:
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## Channel 2: unused
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## Channel 3: EEPROM
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## Location: U6
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## Vendor:
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## Device: M24C08
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## Address: 0xA8 (1010 100xb)
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## Channel 4: SFP cage
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## Location: P3
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## Address: 0xA0 (1010 000xb)
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## Channel 5: HDMI
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## Location:
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## Vendor:
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## Device:
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## Address: 0x72 (0111 001xb)
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## Channel 6: DDR3
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## Location:
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## Address: 0xA0, 0x30 (1010 000xb, 0011 000xb)
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## Channel 7: SI5324
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## Location: U?? (SI5324-C-GM)
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## Vendor: Silicon Labs
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## Device: SI5324 - Any-Frequency Precision Clock Multiplier/Jitter Attenuator
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## Address: 0xD0 (1101 000xb)
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## -----------------------------------------------------------------------------
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## {INOUT} U52 - Pin 19 - SerialClock
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set_property PACKAGE_PIN N18 [get_ports AC701_IIC_SerialClock]
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## {INOUT} U52 - Pin 20 - SerialData
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set_property PACKAGE_PIN K25 [get_ports AC701_IIC_SerialData]
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## {OUT} #$ U52 - Pin 24 - Reset (low-active)
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set_property PACKAGE_PIN R17 [get_ports AC701_IIC_Switch_Reset_n]
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# set I/O standard
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set_property IOSTANDARD LVCMOS33 [get_ports -regexp {AC701_IIC_.*}]
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# Ignore timings on async I/O pins
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set_false_path -to [get_ports -regexp {AC701_IIC_.*}]
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set_false_path -from [get_ports -regexp {AC701_IIC_Serial.*}]

‎ucf/AC701/Clock.SystemClock.xdc

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## =============================================================================================================================================================
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## Xilinx User Constraint File (UCF)
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## =============================================================================================================================================================
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## Board: Xilinx - Artix-7 AC701
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## FPGA: Xilinx Artix-7
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## Device: XC7A200T
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## Package: FBG676
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## Speedgrade: -2
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##
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## Notes:
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## AC701: VCCO_VADJ is defaulted to 2.5V (choices: 1.8V, 2.5V, 3.3V)
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##
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## =============================================================================================================================================================
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## Clock Sources
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## =============================================================================================================================================================
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##
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## System Clock
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## -----------------------------------------------------------------------------
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## Bank: 34
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## VCCO: 2.5V (FPGA_2V5)
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## Location: U51 (SIT9102)
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## Vendor: SiTime
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## Device: SIT9102AI-243N25E200.0000 - 1 to 220 MHz High Performance Oscillator
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## Frequency: 200 MHz, 50ppm
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set_property PACKAGE_PIN R3 [get_ports AC701_SystemClock_200MHz_p]
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set_property PACKAGE_PIN P3 [get_ports AC701_SystemClock_200MHz_n]
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# set I/O standard
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set_property IOSTANDARD LVDS_25 [get_ports -regexp {AC701_SystemClock_200MHz_[p|n]}]
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# specify a 200 MHz clock
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create_clock -period 5.000 -name PIN_SystemClock_200MHz [get_ports AC701_SystemClock_200MHz_p]

‎ucf/AC701/FanControl.xdc

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## =============================================================================================================================================================
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## General Purpose I/O
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## =============================================================================================================================================================
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##
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## Fan Control
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## -----------------------------------------------------------------------------
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## Bank: 15
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## VCCO: 2.5V (VCC0_VADJ)
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## Location: J61, Q17 (NDT3055L)
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## -----------------------------------------------------------------------------
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## {OUT} Q17.Gate; external 1k pullup resistor; Q17.Drain connects to J61.1 (GND)
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set_property PACKAGE_PIN J26 [get_ports AC701_FanControl_PWM]
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## {IN} J61.3; voltage limited by D15 (MM3Z2V7B; 2.7V zener-diode)
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set_property PACKAGE_PIN J25 [get_ports AC701_FanControl_Tacho]
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# set I/O standard
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set_property IOSTANDARD LVCMOS25 [get_ports -regexp {AC701_FanControl_.*}]
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# Ignore timings on async I/O pins
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set_false_path -to [get_ports AC701_FanControl_PWM]
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set_false_path -from [get_ports AC701_FanControl_Tacho]

‎ucf/AC701/GPIO.Button.Special.xdc

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## =============================================================================================================================================================
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## General Purpose I/O
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## =============================================================================================================================================================
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##
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## Special Buttons
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## -----------------------------------------------------------------------------
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## Bank: 34
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## VCCO: 1.5V (FPGA_1V5)
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## Location: SW8
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## -----------------------------------------------------------------------------
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## {IN} SW8; high-active; external 4k7 pulldown resistor
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set_property PACKAGE_PIN U4 [get_ports AC701_GPIO_Button_CPU_Reset]
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# set I/O standard
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set_property IOSTANDARD LVCMOS15 [get_ports AC701_GPIO_Button_CPU_Reset]
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# Ignore timings on async I/O pins
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set_false_path -from [get_ports AC701_GPIO_Button_CPU_Reset]

‎ucf/AC701/GPIO.LED.xdc

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## =============================================================================================================================================================
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## General Purpose I/O
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## =============================================================================================================================================================
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##
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## LEDs
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## -----------------------------------------------------------------------------
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## Bank: 14
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## VCCO: 3.3V (FPGA_3V3)
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## Location: DS2, DS3, DS4, DS5
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## -----------------------------------------------------------------------------
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## {OUT} DS2;
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set_property PACKAGE_PIN M26 [get_ports AC701_GPIO_LED[0]]
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## {OUT} DS3;
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set_property PACKAGE_PIN T24 [get_ports AC701_GPIO_LED[1]]
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## {OUT} DS4;
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set_property PACKAGE_PIN T25 [get_ports AC701_GPIO_LED[2]]
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## {OUT} DS5;
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set_property PACKAGE_PIN R26 [get_ports AC701_GPIO_LED[3]]
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# set I/O standard
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set_property IOSTANDARD LVCMOS33 [get_ports -regexp {AC701_GPIO_LED\[[0-3]]}]
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# Ignore timings on async I/O pins
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set_false_path -to [get_ports -regexp {AC701_GPIO_LED\[\d\]}]

‎ucf/AC701/USB_UART.xdc

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##
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## USB UART
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## -----------------------------------------------------------------------------
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## Bank: 13
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## VCCO: 1.8V (FPGA_1V8)
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## Location: U44
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## Vendor: Silicon Labs
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## Device: CP2103-GM
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## Baud-Rate: 300 Bd - 1 MBd
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## Note: USB-UART is the master, FPGA is the slave => so TX is an input and RX an output
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## {IN} U44.25 {OUT}
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set_property PACKAGE_PIN T19 [get_ports AC701_USB_UART_TX]
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## {OUT} U44.24 {IN}
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set_property PACKAGE_PIN U19 [get_ports AC701_USB_UART_RX]
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## {IN} U44.23 {OUT} Ready to Transmit (USB-UART has new data)
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set_property PACKAGE_PIN V19 [get_ports AC701_USB_UART_RTS_n]
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## {OUT} U44.22 {IN} Clear to Send (FPGA is able to receive data)
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set_property PACKAGE_PIN W19 [get_ports AC701_USB_UART_CTS_n]
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# set I/O standard
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set_property IOSTANDARD LVCMOS25 [get_ports -regexp {AC701_USB_UART_.*}]
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# Ignore timings on async I/O pins
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set_false_path -from [get_ports AC701_USB_UART_TX]
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set_false_path -to [get_ports AC701_USB_UART_RX]
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set_false_path -from [get_ports AC701_USB_UART_RTS_n]
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set_false_path -to [get_ports AC701_USB_UART_CTS_n]

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