Skip to content

Commit 9d4a4aa

Browse files
author
Martin Zabel
committed
Merge remote-tracking branch 'github/master' (tag 'v1.1.0') into Vivado
# Conflicts: # README.md # src/common/physical.vhdl # src/io/io_FanControl.vhdl # src/io/io_FrequencyCounter.vhdl # src/io/pmod/pmod_KYPD.vhdl # src/io/uart/uart_bclk.vhdl # src/misc/misc_FrequencyMeasurement.vhdl # src/net/arp/arp_Cache.vhdl # src/net/arp/arp_Wrapper.vhdl # src/sim/sim_simulation.v93.vhdl # src/sim/sim_waveform.vhdl # tb/io/io_Debounce_tb.vhdl
2 parents 955cee4 + f9e431c commit 9d4a4aa

File tree

915 files changed

+39222
-15783
lines changed

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

915 files changed

+39222
-15783
lines changed

‎.gitattributes

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,16 @@
1+
*.tpl -whitespace
2+
*.md -whitespace
3+
*.rst -whitespace
4+
*.ini -whitespace
5+
*.pl filter=normalize
6+
*.ps1 filter=normalize
7+
*.psm1 filter=normalize
8+
*.py filter=normalize
9+
*.sh filter=normalize
10+
*.rst filter=normalize_rest
11+
*.vhdl filter=normalize_vhdl
12+
*.ucf filter=normalize
13+
*.xcf filter=normalize
14+
*.ldc filter=normalize
15+
*.sdc filter=normalize
16+
*.xdc filter=normalize

‎.gitignore

Lines changed: 23 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,9 @@
88
# ignore Python caches
99
__pycache__
1010

11+
# ignore build directories
12+
docs/_build/
13+
1114
# ignore files in netlist/
1215
/netlist/
1316
!/netlist/configuration.ini
@@ -16,8 +19,14 @@ __pycache__
1619
!/netlist/template.cgc
1720

1821
# ignore folders
19-
/temp/
20-
/vSim/
22+
/docs/_build/
23+
/py/Wrapper/Hooks/*
24+
!/py/Wrapper/Hooks/README.md
25+
/temp/*
26+
!/temp/.*
27+
!/temp/*.*
28+
/temp/precompiled/*
29+
!/temp/precompiled/.*
2130

2231
# ignore files from PoC
2332
/py/config.private.ini
@@ -43,6 +52,17 @@ __pycache__
4352
/prj/QuestaSim/**/*.*
4453
!/prj/QuestaSim/PoC.mpf
4554

55+
# ignore Lattice Diamond files
56+
other/diamond/._Real_._Math_.vhd
57+
other/diamond/.spread_sheet.ini
58+
other/diamond/.spreadsheet_view.ini
59+
/other/diamond/*/**/*
60+
/other/diamond/*.xml
61+
/other/diamond/*.html
62+
!/other/diamond/*/**/*.lpf
63+
!/other/diamond/*/**/*.ldc
64+
!/other/diamond/*/**/*.vhdl
65+
4666
# ignore Xilinx ISE files
4767
/other/ise/**/*.*
4868
/other/ise/**/ise
@@ -73,4 +93,4 @@ __pycache__
7393
# general whitelist
7494
!.git*
7595
!.publish
76-
!.README.md
96+
!README.md

‎.gitmodules

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7,4 +7,6 @@
77
[submodule "lib/cocotb"]
88
path = lib/cocotb
99
url = https://github.com/VLSI-EDA/cocotb.git
10-
10+
[submodule "docs/_themes/sphinx_rtd_theme"]
11+
path = docs/_themes/sphinx_rtd_theme
12+
url = https://github.com/VLSI-EDA/sphinx_rtd_theme.git

‎.landscape.yml

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -18,6 +18,11 @@ pep8:
1818
enable:
1919
options:
2020
max-line-length: 180
21+
mccabe:
22+
options:
23+
max-complexity: 20
24+
# vulture:
25+
# run: true
2126
ignore-paths:
2227
- lib
2328
- netlist

‎AUTHORS.md

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,7 @@
22

33
Contributor | Contact E-Mail
44
------------------|------------------------------------------------------------
5+
Genßler, Paul | [email protected]
56
Köhler, Steffen | [email protected]
67
Lehmann, Patrick | [email protected]; [email protected]
78
Preußer, Thomas B.| [email protected]; [email protected]

‎CHANGES.md

Lines changed: 93 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -4,29 +4,105 @@
44

55
## 2016
66

7-
##### New in 0.X (DD.MM.2016)
7+
##### New in 1.x (dd.mm.yyyy)
88

9-
- Reworked Python infrastructure
10-
- New command line interface `poc.sh|ps1 [common options] <command> <entity> [options]`
11-
- Removed task specific wrapper scripts: `testbench.sh|ps1`, `netlist.sh|ps1`
9+
- Python Infrastructure
10+
- Common changes
11+
- The classes Simulator and Compiler now share common methods in base class called Shared.
12+
- `*.files` Parser
13+
- Implemented path expressions: sub-directory expression, concatenate expression
14+
- Implemented InterpolateLiteral: access database keys in `*.files` files
15+
- New Path statement, which defines a path constant calculated from a path expression
16+
- Replaced string arguments in statements with path expressions if the desired string was a path
17+
- Replaced simple StringToken matches with Identifier expressions
18+
- All Simulators
19+
-
20+
- All Compilers
21+
-
22+
- GHDL
23+
- Reduced `-P<path>` parameters: Removed doublings
24+
- Documentation
25+
-
26+
- VHDL common packages
27+
-
28+
- VHDL Simulation helpers
29+
- Mark a testbench as failed if (registered) processes are active while finilize is called
30+
31+
- New Entities
32+
-
33+
- New Testbenches
34+
-
35+
- New Constraints
36+
-
37+
- Shipped Tool and Helper Scripts
38+
- Updated and new Notepad++ syntax files
39+
40+
41+
##### New in 1.0 (13.05.2016)
42+
43+
- Python Infrastructure (Completely Reworked)
44+
- New Requirements
45+
- Python 3.5
46+
- py-flags
47+
- New command line interface
48+
- Synopsis: `poc.sh|ps1 [common options] <command> <entity> [options]`
49+
- Removed task specific wrapper scripts: `testbench.sh|ps1`, `netlist.sh|ps1`, ...
50+
- Updated wrapper.ps1 and wrapper.sh files
51+
- New ini-file database
52+
-
53+
- Added a new config.boards.ini file to list known boards (real and virtual ones)
1254
- New parser for `*.files` files
1355
- conditional compiling (if-then-elseif-else)
1456
- include statement - include other `*.files` files
1557
- library statement - reference external VHDL libraries
1658
- prepared for Cocotb testbenches
17-
- Unbuffered outputs from vendor tools (realtime output to stdout from subprocess)
18-
- Output filtering from vendor tools
19-
- verbose message suppression
20-
- error and warning message highlighting
21-
- Added a new config.boards.ini file to list known boards (real and virtual ones)
22-
- Run testbenches for different board or device configurations (see `--board` and `--device` command line options)
23-
- Finished Aldec Active-HDL support (no GUI support)
24-
- GHDLSimulator can distinguish different backends
25-
- Embedded Cocotb in <PoCRoot>/lib/cocotb
26-
- precompiled vendor library support
27-
- Added a new <PoCRoot>/temp/precompiled folder for precompiled vendor libraries
28-
- QuestaSim supports Altera QuartusII, Xilinx ISE and Xilinx Vivado libraries
29-
- GHDL supports Altera QuartusII, Xilinx ISE and Xilinx Vivado libraries
59+
- New parser for `*.rules` files
60+
-
61+
62+
63+
- All Tool Flows
64+
- Unbuffered outputs from vendor tools (realtime output to stdout from subprocess)
65+
- Output filtering from vendor tools
66+
- verbose message suppression
67+
- error and warning message highlighting
68+
- abort flow on vendor tool errors
69+
- All Simulators
70+
- Run testbenches for different board or device configurations (see `--board` and `--device` command line options)
71+
- New Simulators
72+
- Aldec Active-HDL support (no GUI support)
73+
- Tested with Active-HDL from Lattice Diamond
74+
- Tested with Active-HDL Student Edition
75+
- Cocotb (with QuestaSim backend on Linux)
76+
- New Synthesizers
77+
- Altera Quartus II and Quartus Prime
78+
- Command: `quartus`
79+
- Lattice Synthesis Engine (LSE) from Diamond
80+
- Command: `lse`
81+
- Xilinx Vivado
82+
- Command: `vivado`
83+
- GHDL
84+
- GHDLSimulator can distinguish different backends (mcode, gcc, llvm)
85+
- Pre-compiled library support for GHDL
86+
- QuestaSim / ModelSim Altera Edition
87+
- Pre-compiled library support for GHDL
88+
- Vivado Simulator
89+
- Tested Vivado Simulator 2016.1 (xSim) with PoC -> still produces errors or false results
90+
91+
- New Entities
92+
-
93+
- New Testbenches
94+
-
95+
- New Constraints
96+
-
97+
- New dependencies
98+
- Embedded Cocotb in <PoCRoot>/lib/cocotb
99+
- Shipped Tool and Helper Scripts
100+
- Updated and new Notepad++ syntax files
101+
- Pre-compiled vendor library support
102+
- Added a new <PoCRoot>/temp/precompiled folder for precompiled vendor libraries
103+
- QuestaSim supports Altera QuartusII, Xilinx ISE and Xilinx Vivado libraries
104+
- GHDL supports Altera QuartusII, Xilinx ISE and Xilinx Vivado libraries
105+
30106

31107
##### New in 0.21 (17.02.2016)
32108

‎CONTRIBUTING.md

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,16 @@
1+
2+
# Contributing to the PoC-Library
3+
4+
Currently, we have no contribution rules, so feel free to submit pull requests.
5+
6+
7+
### Contributor License Agreement
8+
9+
We require all contributers to sign a Contributor License Agreement (CLA). If you don't know
10+
whatfore a CLA is needed and how it prevents legal issues on both sides, read [this short
11+
blog](https://www.clahub.com/pages/why_cla) post.
12+
13+
So to get started, [sign the Contributor License Agreement (CLA)][CLAHub].
14+
15+
16+
[CLAHub]: https://www.clahub.com/agreements/VLSI-EDA/PoC

0 commit comments

Comments
 (0)