Merge remote-tracking branch 'github/master' (tag 'v1.1.0') into Vivado

# Conflicts:
#	README.md
#	src/common/physical.vhdl
#	src/io/io_FanControl.vhdl
#	src/io/io_FrequencyCounter.vhdl
#	src/io/pmod/pmod_KYPD.vhdl
#	src/io/uart/uart_bclk.vhdl
#	src/misc/misc_FrequencyMeasurement.vhdl
#	src/net/arp/arp_Cache.vhdl
#	src/net/arp/arp_Wrapper.vhdl
#	src/sim/sim_simulation.v93.vhdl
#	src/sim/sim_waveform.vhdl
#	tb/io/io_Debounce_tb.vhdl

.gitattributes

@@ -0,0 +1,16 @@
+*.tpl		-whitespace
+*.md		-whitespace
+*.rst		-whitespace
+*.ini		-whitespace
+*.pl	filter=normalize
+*.ps1	filter=normalize
+*.psm1	filter=normalize
+*.py	filter=normalize
+*.sh	filter=normalize
+*.rst	filter=normalize_rest
+*.vhdl	filter=normalize_vhdl
+*.ucf		filter=normalize
+*.xcf		filter=normalize
+*.ldc		filter=normalize
+*.sdc		filter=normalize
+*.xdc		filter=normalize

.gitignore

@@ -8,6 +8,9 @@
 # ignore Python caches
 __pycache__
 
+# ignore build directories
+docs/_build/
+
 # ignore files in netlist/
 /netlist/
 !/netlist/configuration.ini
@@ -16,8 +19,14 @@ __pycache__
 !/netlist/template.cgc
 
 # ignore folders
-/temp/
-/vSim/
+/docs/_build/
+/py/Wrapper/Hooks/*
+!/py/Wrapper/Hooks/README.md
+/temp/*
+!/temp/.*
+!/temp/*.*
+/temp/precompiled/*
+!/temp/precompiled/.*
 
 # ignore files from PoC
 /py/config.private.ini
@@ -43,6 +52,17 @@ __pycache__
 /prj/QuestaSim/**/*.*
 !/prj/QuestaSim/PoC.mpf
 
+# ignore Lattice Diamond files
+other/diamond/._Real_._Math_.vhd
+other/diamond/.spread_sheet.ini
+other/diamond/.spreadsheet_view.ini
+/other/diamond/*/**/*
+/other/diamond/*.xml
+/other/diamond/*.html
+!/other/diamond/*/**/*.lpf
+!/other/diamond/*/**/*.ldc
+!/other/diamond/*/**/*.vhdl
+
 # ignore Xilinx ISE files
 /other/ise/**/*.*
 /other/ise/**/ise
@@ -73,4 +93,4 @@ __pycache__
 # general whitelist
 !.git*
 !.publish
-!.README.md
+!README.md

.gitmodules

@@ -7,4 +7,6 @@
 [submodule "lib/cocotb"]
 	path = lib/cocotb
 	url = https://github.com/VLSI-EDA/cocotb.git
-
+[submodule "docs/_themes/sphinx_rtd_theme"]
+	path = docs/_themes/sphinx_rtd_theme
+	url = https://github.com/VLSI-EDA/sphinx_rtd_theme.git

.landscape.yml

@@ -18,6 +18,11 @@ pep8:
   enable:
   options:
     max-line-length: 180
+mccabe:
+  options:
+    max-complexity: 20
+# vulture:
+  # run: true
 ignore-paths:
 - lib
 - netlist

AUTHORS.md

@@ -2,6 +2,7 @@
 
 Contributor       | Contact E-Mail
 ------------------|------------------------------------------------------------
+Genßler, Paul     | [email protected]
 Köhler, Steffen   | [email protected]
 Lehmann, Patrick  | [email protected]; [email protected]
 Preußer, Thomas B.| [email protected]; [email protected]

CHANGES.md

@@ -4,29 +4,105 @@
 
 ## 2016
 
-##### New in 0.X (DD.MM.2016)
+##### New in 1.x (dd.mm.yyyy)
 
-  - Reworked Python infrastructure
-      - New command line interface `poc.sh|ps1 [common options] <command> <entity> [options]`
-      - Removed task specific wrapper scripts: `testbench.sh|ps1`, `netlist.sh|ps1`
+  - Python Infrastructure
+	    - Common changes
+			    - The classes Simulator and Compiler now share common methods in base class called Shared.
+	    - `*.files` Parser
+			    - Implemented path expressions: sub-directory expression, concatenate expression
+					- Implemented InterpolateLiteral: access database keys in `*.files` files
+					- New Path statement, which defines a path constant calculated from a path expression
+					- Replaced string arguments in statements with path expressions if the desired string was a path
+					- Replaced simple StringToken matches with Identifier expressions
+			- All Simulators
+				  - 
+			- All Compilers
+				  - 
+			- GHDL
+			    - Reduced `-P<path>` parameters: Removed doublings
+	- Documentation
+	    - 
+	- VHDL common packages
+	    - 	
+	- VHDL Simulation helpers
+	    - Mark a testbench as failed if (registered) processes are active while finilize is called
+			
+	- New Entities
+	    - 
+	- New Testbenches
+	    - 
+	- New Constraints
+	    - 
+  - Shipped Tool and Helper Scripts
+	    - Updated and new Notepad++ syntax files
+			
+			
+##### New in 1.0 (13.05.2016)
+
+  - Python Infrastructure (Completely Reworked)
+	    - New Requirements
+			    - Python 3.5
+			    - py-flags
+      - New command line interface
+			    - Synopsis: `poc.sh|ps1 [common options] <command> <entity> [options]`
+					- Removed task specific wrapper scripts: `testbench.sh|ps1`, `netlist.sh|ps1`, ...
+					- Updated wrapper.ps1 and wrapper.sh files
+			- New ini-file database
+					- 
+					- Added a new config.boards.ini file to list known boards (real and virtual ones)
       - New parser for `*.files` files
           - conditional compiling (if-then-elseif-else)
           - include statement - include other `*.files` files
           - library statement - reference external VHDL libraries
           - prepared for Cocotb testbenches
-      - Unbuffered outputs from vendor tools (realtime output to stdout from subprocess)
-      - Output filtering from vendor tools
-          - verbose message suppression
-          - error and warning message highlighting
-      - Added a new config.boards.ini file to list known boards (real and virtual ones)
-      - Run testbenches for different board or device configurations (see `--board` and `--device` command line options)
-      - Finished Aldec Active-HDL support (no GUI support)
-      - GHDLSimulator can distinguish different backends 
-	- Embedded Cocotb in <PoCRoot>/lib/cocotb
-  - precompiled vendor library support
-      - Added a new <PoCRoot>/temp/precompiled folder for precompiled vendor libraries
-      - QuestaSim supports Altera QuartusII, Xilinx ISE and Xilinx Vivado libraries
-      - GHDL supports Altera QuartusII, Xilinx ISE and Xilinx Vivado libraries
+			- New parser for `*.rules` files
+					- 
+			
+			
+			- All Tool Flows
+          - Unbuffered outputs from vendor tools (realtime output to stdout from subprocess)
+          - Output filtering from vendor tools
+              - verbose message suppression
+              - error and warning message highlighting
+              - abort flow on vendor tool errors
+      - All Simulators
+          - Run testbenches for different board or device configurations (see `--board` and `--device` command line options)
+			- New Simulators
+					- Aldec Active-HDL support (no GUI support)
+							- Tested with Active-HDL from Lattice Diamond
+							- Tested with Active-HDL Student Edition
+					- Cocotb (with QuestaSim backend on Linux)
+			- New Synthesizers
+					- Altera Quartus II and Quartus Prime
+					    - Command: `quartus`
+					- Lattice Synthesis Engine (LSE) from Diamond
+					    - Command: `lse`
+					- Xilinx Vivado
+					    - Command: `vivado`
+			- GHDL
+	  			- GHDLSimulator can distinguish different backends (mcode, gcc, llvm)
+					- Pre-compiled library support for GHDL
+			- QuestaSim / ModelSim Altera Edition
+					- Pre-compiled library support for GHDL
+			- Vivado Simulator
+			    - Tested Vivado Simulator 2016.1 (xSim) with PoC -> still produces errors or false results
+
+	- New Entities
+		  - 
+	- New Testbenches
+		  - 
+	- New Constraints
+		  - 
+	- New dependencies
+	    - Embedded Cocotb in <PoCRoot>/lib/cocotb
+  - Shipped Tool and Helper Scripts
+	    - Updated and new Notepad++ syntax files
+	    - Pre-compiled vendor library support
+          - Added a new <PoCRoot>/temp/precompiled folder for precompiled vendor libraries
+          - QuestaSim supports Altera QuartusII, Xilinx ISE and Xilinx Vivado libraries
+          - GHDL supports Altera QuartusII, Xilinx ISE and Xilinx Vivado libraries
+
 
 ##### New in 0.21 (17.02.2016)
 

CONTRIBUTING.md

@@ -0,0 +1,16 @@
+
+# Contributing to the PoC-Library
+
+Currently, we have no contribution rules, so feel free to submit pull requests.
+
+
+### Contributor License Agreement
+
+We require all contributers to sign a Contributor License Agreement (CLA). If you don't know
+whatfore a CLA is needed and how it prevents legal issues on both sides, read [this short
+blog](https://www.clahub.com/pages/why_cla) post.
+
+So to get started, [sign the Contributor License Agreement (CLA)][CLAHub].
+
+
+ [CLAHub]: https://www.clahub.com/agreements/VLSI-EDA/PoC