diff --git a/.gitattributes b/.gitattributes new file mode 100644 index 00000000..b00763c2 --- /dev/null +++ b/.gitattributes @@ -0,0 +1,16 @@ +*.tpl -whitespace +*.md -whitespace +*.rst -whitespace +*.ini -whitespace +*.pl filter=normalize +*.ps1 filter=normalize +*.psm1 filter=normalize +*.py filter=normalize +*.sh filter=normalize +*.rst filter=normalize_rest +*.vhdl filter=normalize_vhdl +*.ucf filter=normalize +*.xcf filter=normalize +*.ldc filter=normalize +*.sdc filter=normalize +*.xdc filter=normalize diff --git a/.gitignore b/.gitignore index 5bc6b220..a673e46e 100644 --- a/.gitignore +++ b/.gitignore @@ -8,6 +8,9 @@ # ignore Python caches __pycache__ +# ignore build directories +docs/_build/ + # ignore files in netlist/ /netlist/ !/netlist/configuration.ini @@ -16,8 +19,14 @@ __pycache__ !/netlist/template.cgc # ignore folders -/temp/ -/vSim/ +/docs/_build/ +/py/Wrapper/Hooks/* +!/py/Wrapper/Hooks/README.md +/temp/* +!/temp/.* +!/temp/*.* +/temp/precompiled/* +!/temp/precompiled/.* # ignore files from PoC /py/config.private.ini @@ -43,6 +52,17 @@ __pycache__ /prj/QuestaSim/**/*.* !/prj/QuestaSim/PoC.mpf +# ignore Lattice Diamond files +other/diamond/._Real_._Math_.vhd +other/diamond/.spread_sheet.ini +other/diamond/.spreadsheet_view.ini +/other/diamond/*/**/* +/other/diamond/*.xml +/other/diamond/*.html +!/other/diamond/*/**/*.lpf +!/other/diamond/*/**/*.ldc +!/other/diamond/*/**/*.vhdl + # ignore Xilinx ISE files /other/ise/**/*.* /other/ise/**/ise @@ -73,4 +93,4 @@ __pycache__ # general whitelist !.git* !.publish -!.README.md +!README.md diff --git a/.gitmodules b/.gitmodules index f33fc63b..06b72da2 100644 --- a/.gitmodules +++ b/.gitmodules @@ -7,4 +7,6 @@ [submodule "lib/cocotb"] path = lib/cocotb url = https://github.com/VLSI-EDA/cocotb.git - +[submodule "docs/_themes/sphinx_rtd_theme"] + path = docs/_themes/sphinx_rtd_theme + url = https://github.com/VLSI-EDA/sphinx_rtd_theme.git diff --git a/.landscape.yml b/.landscape.yml index 45dc9cba..45d79860 100644 --- a/.landscape.yml +++ b/.landscape.yml @@ -18,6 +18,11 @@ pep8: enable: options: max-line-length: 180 +mccabe: + options: + max-complexity: 20 +# vulture: + # run: true ignore-paths: - lib - netlist diff --git a/AUTHORS.md b/AUTHORS.md index 57ec8f21..2ef43e42 100644 --- a/AUTHORS.md +++ b/AUTHORS.md @@ -2,6 +2,7 @@ Contributor | Contact E-Mail ------------------|------------------------------------------------------------ +Genßler, Paul | paul.genssler@tu-dresden.de Köhler, Steffen | steffen.koehler@tu-dresden.de Lehmann, Patrick | patrick.lehmann@tu-dresden.de; paebbels@gmail.com Preußer, Thomas B.| thomas.preusser@tu-dresden.de; thomas.preusser@utexas.edu diff --git a/CHANGES.md b/CHANGES.md index 83aefee1..914d617e 100644 --- a/CHANGES.md +++ b/CHANGES.md @@ -4,29 +4,105 @@ ## 2016 -##### New in 0.X (DD.MM.2016) +##### New in 1.x (dd.mm.yyyy) - - Reworked Python infrastructure - - New command line interface `poc.sh|ps1 [common options] [options]` - - Removed task specific wrapper scripts: `testbench.sh|ps1`, `netlist.sh|ps1` + - Python Infrastructure + - Common changes + - The classes Simulator and Compiler now share common methods in base class called Shared. + - `*.files` Parser + - Implemented path expressions: sub-directory expression, concatenate expression + - Implemented InterpolateLiteral: access database keys in `*.files` files + - New Path statement, which defines a path constant calculated from a path expression + - Replaced string arguments in statements with path expressions if the desired string was a path + - Replaced simple StringToken matches with Identifier expressions + - All Simulators + - + - All Compilers + - + - GHDL + - Reduced `-P` parameters: Removed doublings + - Documentation + - + - VHDL common packages + - + - VHDL Simulation helpers + - Mark a testbench as failed if (registered) processes are active while finilize is called + + - New Entities + - + - New Testbenches + - + - New Constraints + - + - Shipped Tool and Helper Scripts + - Updated and new Notepad++ syntax files + + +##### New in 1.0 (13.05.2016) + + - Python Infrastructure (Completely Reworked) + - New Requirements + - Python 3.5 + - py-flags + - New command line interface + - Synopsis: `poc.sh|ps1 [common options] [options]` + - Removed task specific wrapper scripts: `testbench.sh|ps1`, `netlist.sh|ps1`, ... + - Updated wrapper.ps1 and wrapper.sh files + - New ini-file database + - + - Added a new config.boards.ini file to list known boards (real and virtual ones) - New parser for `*.files` files - conditional compiling (if-then-elseif-else) - include statement - include other `*.files` files - library statement - reference external VHDL libraries - prepared for Cocotb testbenches - - Unbuffered outputs from vendor tools (realtime output to stdout from subprocess) - - Output filtering from vendor tools - - verbose message suppression - - error and warning message highlighting - - Added a new config.boards.ini file to list known boards (real and virtual ones) - - Run testbenches for different board or device configurations (see `--board` and `--device` command line options) - - Finished Aldec Active-HDL support (no GUI support) - - GHDLSimulator can distinguish different backends - - Embedded Cocotb in /lib/cocotb - - precompiled vendor library support - - Added a new /temp/precompiled folder for precompiled vendor libraries - - QuestaSim supports Altera QuartusII, Xilinx ISE and Xilinx Vivado libraries - - GHDL supports Altera QuartusII, Xilinx ISE and Xilinx Vivado libraries + - New parser for `*.rules` files + - + + + - All Tool Flows + - Unbuffered outputs from vendor tools (realtime output to stdout from subprocess) + - Output filtering from vendor tools + - verbose message suppression + - error and warning message highlighting + - abort flow on vendor tool errors + - All Simulators + - Run testbenches for different board or device configurations (see `--board` and `--device` command line options) + - New Simulators + - Aldec Active-HDL support (no GUI support) + - Tested with Active-HDL from Lattice Diamond + - Tested with Active-HDL Student Edition + - Cocotb (with QuestaSim backend on Linux) + - New Synthesizers + - Altera Quartus II and Quartus Prime + - Command: `quartus` + - Lattice Synthesis Engine (LSE) from Diamond + - Command: `lse` + - Xilinx Vivado + - Command: `vivado` + - GHDL + - GHDLSimulator can distinguish different backends (mcode, gcc, llvm) + - Pre-compiled library support for GHDL + - QuestaSim / ModelSim Altera Edition + - Pre-compiled library support for GHDL + - Vivado Simulator + - Tested Vivado Simulator 2016.1 (xSim) with PoC -> still produces errors or false results + + - New Entities + - + - New Testbenches + - + - New Constraints + - + - New dependencies + - Embedded Cocotb in /lib/cocotb + - Shipped Tool and Helper Scripts + - Updated and new Notepad++ syntax files + - Pre-compiled vendor library support + - Added a new /temp/precompiled folder for precompiled vendor libraries + - QuestaSim supports Altera QuartusII, Xilinx ISE and Xilinx Vivado libraries + - GHDL supports Altera QuartusII, Xilinx ISE and Xilinx Vivado libraries + ##### New in 0.21 (17.02.2016) diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md new file mode 100644 index 00000000..bbf73cdb --- /dev/null +++ b/CONTRIBUTING.md @@ -0,0 +1,16 @@ + +# Contributing to the PoC-Library + +Currently, we have no contribution rules, so feel free to submit pull requests. + + +### Contributor License Agreement + +We require all contributers to sign a Contributor License Agreement (CLA). If you don't know +whatfore a CLA is needed and how it prevents legal issues on both sides, read [this short +blog](https://www.clahub.com/pages/why_cla) post. + +So to get started, [sign the Contributor License Agreement (CLA)][CLAHub]. + + + [CLAHub]: https://www.clahub.com/agreements/VLSI-EDA/PoC diff --git a/README.md b/README.md index 8f4d3ddf..dae6e3be 100644 --- a/README.md +++ b/README.md @@ -1,199 +1,155 @@ + # The PoC-Library [![Python Infrastructure tested by Landscape.io](https://landscape.io/github/VLSI-EDA/PoC/Vivado/landscape.svg?style=flat)](https://landscape.io/github/VLSI-EDA/PoC/Vivado) [![Build Status by Travis-CI](https://travis-ci.org/VLSI-EDA/PoC.svg?branch=Vivado)](https://travis-ci.org/VLSI-EDA/PoC/branches) -[![Join the chat at https://gitter.im/VLSI-EDA/PoC](https://badges.gitter.im/VLSI-EDA/PoC.svg)](https://gitter.im/VLSI-EDA/PoC?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge&utm_content=badge) +[![Documentation Status](https://readthedocs.org/projects/poc-library/badge/?version=latest)](http://poc-library.readthedocs.io/en/latest/?badge=latest) +[![Join the chat at https://gitter.im/VLSI-EDA/PoC](https://badges.gitter.im/VLSI-EDA/PoC.svg)](https://gitter.im/VLSI-EDA/PoC) ![Latest tag](https://img.shields.io/github/tag/VLSI-EDA/PoC.svg?style=flat) [![Latest release](https://img.shields.io/github/release/VLSI-EDA/PoC.svg?style=flat)](https://github.com/VLSI-EDA/PoC/releases) [![Apache License 2.0](https://img.shields.io/github/license/VLSI-EDA/PoC.svg?style=flat)](LICENSE.md) This library is published and maintained by **Chair for VLSI Design, Diagnostics and Architecture** - -Faculty of Computer Science, Technische Universität Dresden, Germany +Faculty of Computer Science, Technische Universität Dresden, Germany **http://vlsi-eda.inf.tu-dresden.de** -![Logo: Technische Universität Dresden](https://github.com/VLSI-EDA/PoC/wiki/images/logo_tud.gif) +![Technische Universität Dresden](https://github.com/VLSI-EDA/PoC/wiki/images/logo_tud.gif) Table of Content: -------------------------------------------------------------------------------- 1. [Overview](#1-overview) - 2. [Download](#2-download) - 3. [Requirements](#3-requirements) - 4. [Dependencies](#4-dependencies) - 5. [Configuring PoC on a Local System (Stand Alone)](#5-configuring-poc-on-a-local-system-stand-alone) - 6. [Integrating PoC into Projects](#6-integrating-poc-into-projects) - 7. [Using PoC](#7-using-poc) - 8. [Updating PoC](#8-updating-poc) - 9. [References](#9-references) + 2. [Quick Start Guide](#2-quick-start-guide) + 2.1. [Requirements and Dependencies](#21-requirements-and-dependencies) + 2.2. [Download](#22-download) + 2.3. [Configuring PoC on a Local System](#23-configuring-poc-on-a-local-system) + 2.4. [Integration](#24-integration) + 2.5. [Updating](#25-updating) + 3. [Common Notes](#3-common-notes) + 4. [Cite the PoC-Library](#4-cite-the-poc-library) -------------------------------------------------------------------------------- ## 1 Overview -PoC - "Pile of Cores" provides implementations for often required hardware -functions such as FIFOs, RAM wrapper, and ALUs. The hardware modules are -typically provided as VHDL or Verilog source code, so it can be easily re-used -in a variety of hardware designs. +PoC - “Pile of Cores” provides implementations for often required hardware functions such as +Arithmetic Units, Caches, Clock-Domain-Crossing Circuits, FIFOs, RAM wrappers, and I/O Controllers. +The hardware modules are typically provided as VHDL or Verilog source code, so it can be easily +re-used in a variety of hardware designs. -TODO TODO TODO +All hardware modules use a common set of VHDL packages to share new VHDL types, sub-programs and +constants. Additionally, a set of simulation helper packages eases the writing of testbenches. +Because PoC hosts a huge amount of IP cores, all cores are grouped into sub-namespaces to build a +clear hierachy. -Related repositories: [PoC-Examples][poc_ex] +Various simulation and synthesis tool chains are supported to interoperate with PoC. To generalize +all supported free and commercial vendor tool chains, PoC is shipped with a Python based +infrastructure to offer a command line based frontend. - [poc_ex]: https://github.com/VLSI-EDA/PoC-Examples +## 2 Quick Start Guide -## 2 Download +This **Quick Start Guide** gives a fast and simple introduction into PoC. All topics can be found in +the [Using PoC][201] section at [ReadTheDocs.io][202] with much more details and examples. -**The PoC-Library** can be downloaded as a [zip-file][download] (latest 'master' branch) or -cloned with `git clone` from GitHub. GitHub offers HTTPS and SSH as transfer protocols. -See the [Download][wiki:download] wiki page for more details. +### 2.1 Requirements and Dependencies -For HTTPS protocol use the URL `https://github.com/VLSI-EDA/PoC.git` or command -line instruction: +The PoC-Library comes with some scripts to ease most of the common tasks, like running testbenches or +generating IP cores. PoC uses Python 3 as a platform independent scripting environment. All Python +scripts are wrapped in Bash or PowerShell scripts, to hide some platform specifics of Darwin, Linux or +Windows. See [Requirements][211] for further details. -```PowerShell -cd -git clone --recursive https://github.com/VLSI-EDA/PoC.git PoC -``` - -For SSH protocol use the URL `ssh://git@github.com:VLSI-EDA/PoC.git` or command -line instruction: - -```PowerShell -cd -git clone --recursive ssh://git@github.com:VLSI-EDA/PoC.git PoC -``` - -**Note:** The option `--recursive` performs a recursive clone operation for all -linked [git submodules][git_submod]. An additional `git submodule init` and -`git submodule update` call is not needed anymore. - - [download]: https://github.com/VLSI-EDA/PoC/archive/master.zip - [git_submod]: http://git-scm.com/book/en/v2/Git-Tools-Submodules - -**Note:** The created folder `\PoC` is used as `` in later instructions. - - -## 3 Requirements +[211]: http://poc-library.readthedocs.io/en/latest/UsingPoC/Requirements.html -**The PoC-Library** comes with some scripts to ease most of the common tasks, like -running testbenches or generating IP cores. We choose to use Python as a platform -independent scripting environment. All Python scripts are wrapped in PowerShell -or Bash scripts, to hide some platform specifics of Windows or Linux. See the -[Requirements][wiki:requirements] wiki page for more details and download sources. -##### Common requirements: +#### PoC requires: + - A [supported synthesis tool chain][2111], if you want to synthezise IP cores. + - A [supported simulator tool chain][2112], if you want to simulate IP cores. + - The **Python 3** programming language and runtime, if you want to use PoC's infrastructure. + - A shell to execute shell scripts: + - **Bash** on Linux and OS X + - **PowerShell** on Windows - - Programming languages and runtimes: - - [Python 3][python] (≥ 3.5): - - [colorama][colorama] - - [py-flags][pyflags] - - All Python requirements are listed in [`requirements.txt`][pip3-req] and can be installed via: - `sudo python3.5 -m pip install -r requirements.txt` - - Synthesis tool chains: - - Altera Quartus-II ≥ 13.0 or - - Lattice Diamond or - - Xilinx ISE 14.7 or - - Xilinx Vivado (restricted, see [section 7.7](#7.7-in-xilinx-vivado-synth-and-xsim)) - - Simulation tool chains: - - Aldec Active-HDL or - - Mentor Graphics ModelSim Altera Edition or - - Mentor Graphics QuestaSim or - - Xilinx ISE Simulator 14.7 or - - Xilinx Vivado Simulator ≥ 2016.1 or - - [GHDL][ghdl] ≥ 0.34dev and [GTKWave][gtkwave] ≥ 3.3.70 +[2111]: http://poc-library.readthedocs.io/en/latest/WhatIsPoC/SupportedToolChains.html +[2112]: http://poc-library.readthedocs.io/en/latest/WhatIsPoC/SupportedToolChains.html - [python]: https://www.python.org/downloads/ - [colorama]: https://pypi.python.org/pypi/colorama - [pyflags]: https://pypi.python.org/pypi/py-flags - [ghdl]: https://sourceforge.net/projects/ghdl-updates/ - [gtkwave]: http://gtkwave.sourceforge.net/ - [pip3-req]: requirements.txt +#### PoC optionally requires: + - **Git command line** tools or + - **Git User Interface**, if you want to check out the latest 'master' or 'release' branch. -##### Linux specific requirements: - - - Debian specific: - - bash is configured as `/bin/sh` ([read more](https://wiki.debian.org/DashAsBinSh)) - `dpkg-reconfigure dash` - -##### Windows specific requirements: - - PowerShell 4.0 ([Windows Management Framework 4.0][wmf40]) - - Allow local script execution ([read more][execpol]) - `Set-ExecutionPolicy RemoteSigned` - - PowerShell Community Extensions 3.2 ([pscx.codeplex.com][pscx]) +#### PoC depends on third part libraries: + - [Cocotb][2131] + A coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python. + - [OS-VVM][2132] + Open Source VHDL Verification Methodology. + - [VUnit][2133] + An unit testing framework for VHDL. + +All dependencies are available as GitHub repositories and are linked to PoC as Git submodules into the +[`PoCRoot\lib`][205] directory. See [Third Party Libraries][206] for more details on these libraries. - [wmf40]: http://www.microsoft.com/en-US/download/details.aspx?id=40855 - [execpol]: https://technet.microsoft.com/en-us/library/hh849812.aspx - [pscx]: http://pscx.codeplex.com/ +[2131]: https://github.com/potentialventures/cocotb +[2132]: https://github.com/JimLewis/OSVVM +[2133]: https://github.com/VUnit/vunit +[201]: http://poc-library.readthedocs.io/en/latest/UsingPoC/index.html +[202]: http://poc-library.readthedocs.io/ +[205]: https://github.com/VLSI-EDA/PoC/tree/Vivado/lib +[206]: http://poc-library.readthedocs.io/en/latest/Miscelaneous/ThirdParty.html -## 4 Dependencies -**The PoC-Library** depends on: +### 2.2 Download - - [**Cocotb**][cocotb] - A coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python - - [**OS-VVM**][osvvm] - Open Source VHDL Verification Methodology. - - [**VUnit**][vunit] - An unit testing framework for VHDL. +The PoC-Library can be downloaded as a [zip-file][221] (latest 'release' branch), cloned with `git clone` +or embedded with `git submodule add` from GitHub. GitHub offers HTTPS and SSH as transfer protocols. See +the [Download][222] page for further details. The installation directory is referred to as `PoCRoot`. -All dependencies are available as GitHub repositories and are linked to -PoC as git submodules into the [`\lib\`][lib] directory. +Protocol | Git Clone Command +-------- | :----------------------------------------------------------- +HTTPS | `git clone --recursive https://github.com/VLSI-EDA/PoC.git PoC` +SSH | `git clone --recursive ssh://git@github.com:VLSI-EDA/PoC.git PoC` - [cocotb]: https://github.com/potentialventures/cocotb - [osvvm]: https://github.com/JimLewis/OSVVM - [vunit]: https://github.com/VUnit/vunit +[221]: https://github.com/VLSI-EDA/PoC/archive/Vivado.zip +[222]: http://poc-library.readthedocs.io/en/latest/UsingPoC/Download.html +### 2.3 Configuring PoC on a Local System -## 5 Configuring PoC on a Local System (Stand Alone) - -To explore PoC's full potential, it's required to configure some paths and -synthesis or simulation tool chains. The following commands start a guided -configuration process. Please follow the instructions. It's possible to -relaunch the process at every time, for example to register new tools or to -update tool versions. See the [Configuration][wiki:configuration] wiki page -for more details. - -> All Windows command line instructions are intended for **Windows PowerShell**, -> if not marked otherwise. So executing the following instructions in Windows -> Command Prompt (`cmd.exe`) won't function or result in errors! See the -> [Requirements][wiki:requirements] wiki page on where to download or update -> PowerShell. - -Run the following command line instructions to configure PoC on your local system. +To explore PoC's full potential, it's required to configure some paths and synthesis or simulation tool +chains. The following commands start a guided configuration process. Please follow the instructions on +screen. It's possible to relaunch the process at any time, for example to register new tools or to update +tool versions. See [Configuration][231] for more details. Run the following command line instructions to +configure PoC on your local system: ```PowerShell -cd +cd PoCRoot .\poc.ps1 configure ``` -**Note:** The configuration process can be re-run at every time to add, remove -or update choices made. +Use the keyboard buttons: `Y` to accept, `N` to decline, `P` to skip/pass a step and `Return` to accept +a default value displayed in brackets. -If you want to check your installation, you can run one of our testbenches as described in [tb/README.md][tb_readme] +[231]: http://poc-library.readthedocs.io/en/latest/UsingPoC/PoCConfiguration.html - [tb_readme]: tb/README.md - -## 6 Integrating PoC into Projects +### 2.4 Integration -**The PoC-Library** is meant to be integrated into HDL projects. Therefore it's -recommended to create a library folder and add the PoC-Library as a git submodule. -After the repository linking is done, some short configuration steps are required -to setup paths and tool chains. The following command line instructions show a -short example on how to integrate PoC. A detailed list of steps can be found on the -[Integration][wiki:integration] wiki page. +The PoC-Library is meant to be integrated into other HDL projects. Therefore it's recommended to create +a library folder and add the PoC-Library as a Git submodule. After the repository linking is done, some +short configuration steps are required to setup paths, tool chains and the target platform. The following +command line instructions show a short example on how to integrate PoC. -#### 6.1 Adding the Library as a git submodule +#### a) Adding the Library as a Git submodule -The following command line instructions will create the folder `lib\PoC\` and clone -the PoC-Library as a git [submodule][git_submod] into that folder. +The following command line instructions will create the folder `lib\PoC\` and clone the PoC-Library as a +[Git submodule][2411] into that folder. `ProjectRoot` is the directory of the hosting Git. A detailed list +of steps can be found at [Integration][2412]. -```PowerShell -cd +```powershell +cd ProjectRoot mkdir lib | cd -git submodule add git@github.com:VLSI-EDA/PoC.git PoC +git submodule add https://github.com:VLSI-EDA/PoC.git PoC cd PoC git remote rename origin github cd ..\.. @@ -201,194 +157,143 @@ git add .gitmodules lib\PoC git commit -m "Added new git submodule PoC in 'lib\PoC' (PoC-Library)." ``` - [git_submod]: http://git-scm.com/book/en/v2/Git-Tools-Submodules +[2411]: http://git-scm.com/book/en/v2/Git-Tools-Submodules +[2412]: http://poc-library.readthedocs.io/en/latest/UsingPoC/Integration.html -#### 6.2 Configuring PoC +#### b) Configuring PoC -**The PoC-Library** needs to be configured. +The PoC-Library should be configured to explore its full potential. See [Configuration][2421] for more +details. The following command lines will start the configuration process: -```PowerShell -cd -cd lib\PoC\ -.\poc.ps1 configure +```powershell +cd ProjectRoot +.\lib\PoC\poc.ps1 configure ``` -#### 6.3 Creating PoC's my_config and my_project Files +[2421]: http://poc-library.readthedocs.io/en/latest/UsingPoC/PoCConfiguration.html -**The PoC-Library** needs two VHDL files for it's configuration. These files are used to -determine the most suitable implementation depending on the provided platform information. -Copy these two template files into your project's source folder. Rename these files to -*.vhdl and configure the VHDL constants in these files. +#### c) Creating PoC's `my_config.vhdl` and `my_project.vhdl` Files -```PowerShell -cd +The PoC-Library needs two VHDL files for its configuration. These files are used to determine the most +suitable implementation depending on the provided target information. Copy the following two template +files into your project's source folder. Rename these files to \*.vhdl and configure the VHDL constants +in the files: + +```powershell +cd ProjectRoot cp lib\PoC\src\common\my_config.vhdl.template src\common\my_config.vhdl cp lib\PoC\src\common\my_project.vhdl.template src\common\my_project.vhdl ``` -`my_config.vhdl` defines two global constants, which need to be adjusted: +[my_config.vhdl](https://github.com/VLSI-EDA/PoC/blob/Vivado/src/common/my_config.vhdl.template) defines +two global constants, which need to be adjusted: -```VHDL +```vhdl constant MY_BOARD : string := "CHANGE THIS"; -- e.g. Custom, ML505, KC705, Atlys constant MY_DEVICE : string := "CHANGE THIS"; -- e.g. None, XC5VLX50T-1FF1136, EP2SGX90FF1508C3 ``` -`my_project.vhdl` also defines two global constants, which need to be adjusted: +[my_project.vhdl](https://github.com/VLSI-EDA/PoC/blob/Vivado/src/common/my_project.vhdl.template) also +defines two global constants, which need to be adjusted: -```VHDL +```vhdl constant MY_PROJECT_DIR : string := "CHANGE THIS"; -- e.g. d:/vhdl/myproject/, /home/me/projects/myproject/" constant MY_OPERATING_SYSTEM : string := "CHANGE THIS"; -- e.g. WINDOWS, LINUX ``` -#### 6.4 Compile shipped Xilinx IP cores (*.xco files) to Netlists +Further informations are provided at [Creating my_config/my_project.vhdl][2431]. -**The PoC-Library** is shipped with some pre-configured IP cores from Xilinx. These -IP cores are shipped as \*.xco files and need to be compiled to netlists (\*.ngc -files) and there auxillary files (\*.ncf files; \*.vhdl files; ...). This can be -done by invoking PoC's Service Tool through one of the provided wrapper scripts: -`poc.[sh|ps1]`. +[2431]: http://poc-library.readthedocs.io/en/latest/UsingPoC/VHDLConfiguration.html -The following example compiles `PoC.xil.ChipScopeICON_1` from `\src\xil\xil_ChipScopeICON_1.xco` -for a Kintex-7 325T device into `/netlist/XC7K325T-2FFG900/xil/`. +#### d) Adding PoC's Common Packages to a Synthesis or Simulation Project -```PowerShell -cd /netlist -..\poc.ps1 coregen PoC.xil.ChipScopeICON_1 --board=KC705 -``` +PoC is shipped with a set of common packages, which are used by most of its modules. These packages are +stored in the `PoCRoot\src\common` directory. PoC also provides a VHDL context in `common.vhdl` , which +can be used to reference all packages at once. -## 7 Using PoC -**The PoC-Library** is structured into several sub-folders naming the purpose of -the folder like [`src`][src] for sources files or [`tb`][tb] for testbench files. -The structure within these folders is always the same and based on PoC's -[sub-namespace tree][wiki:subnamespacetree]. +#### e) Adding PoC's Simulation Packages to a Simulation Project -**Main directory overview:** - - - [`lib`][lib] - Embedded or linked external libraries. - - [`netlist`][netlist] - Configuration files and output directory for - pre-configured netlist synthesis results from vendor IP cores or from complex PoC controllers. - - [`py`][py] - Supporting Python scripts. - - [`sim`][sim] - Pre-configured waveform views for selected testbenches. - - [`src`][src] - PoC's source files grouped into sub-folders according to the [sub-namespace tree][wiki:subnamespacetree]. - - [`tb`][tb] - Testbench files. - - [`tcl`][tcl] - Tcl files. - - [`temp`][temp] - A created temporary directors for various tools used by PoC's Python scripts. - - [`tools`][tools] - Settings/highlighting files and helpers for supported tools. - - [`ucf`][ucf] - Pre-configured constraint files (\*.ucf, \*.xdc, \*.sdc) for supported FPGA boards. - - [`xst`][xst] - Configuration files to synthesize PoC modules with Xilinx XST into a netlist. - -#### 7.1 Common Notes - -All VHDL source files should be compiled into the VHDL library `PoC`. -If not indicated otherwise, all source files can be compiled using the -VHDL-93 or VHDL-2008 language version. Incompatible files are named -`*.v93.vhdl` and `*.v08.vhdl` to denote the highest supported language -version. - -#### 7.2 Standalone +Simulation projects additionally require PoC's simulation helper packages, which are located in the +`PoCRoot\src\sim` directory. Because some VHDL version are incompatible among each other, PoC uses +version suffixes like `*.v93.vhdl` or `*.v08.vhdl` in the file name to denote the supported VHDL version +of a file. -#### 7.3 In Altera Quartus II -#### 7.4 In GHDL +#### f) Compiling Shipped IP Cores -#### 7.5 In ModelSim/QuestaSim +Some IP Cores are shipped as pre-configured vendor IP Cores. If such IP cores shall be used in a HDL +project, it's recommended to use PoC to create, compile and if needed patch these IP cores. See +[Synthesis][2461] for more details. +[2461]: http://poc-library.readthedocs.io/en/latest/UsingPoC/Synthesis.html -#### 7.6 In Xilinx ISE (XST and iSim) -**The PoC-Library** was originally designed for the Xilinx ISE -design flow. The latest version (14.7) is supported and required to -explore PoC's full potential. Don't forget to activate the new -XST parser in new projects and to append the IP core search -directory if generated netlists are used. +### 2.5 Updating - 1. **Activating the New Parser in XST** - PoC requires XST to use the *new* source file parser, introduced - with the Virtex-6 FPGA family. It is backward compatible. +The PoC-Library can be updated by using `git fetch` and `git merge`. - **->** Open the *XST Process Property* window and add `-use_new_parser yes` - to the option `Other XST Command Line Options`. - - 2. **Setting the IP Core Search Directory for Generated Netlists** - PoC can generate netlists for bundled source files or for - pre-configured IP cores. These netlists are copied into the - `\netlist\` folder. This folder and its subfolders - need to be added to the IP core search directory. - - **->** Open the *XST Process Property* window and append the directory to the `-sd` option. - **->** Open *Translate Process Property* and append the paths here, too. - - D:\git\PoC\netlist\XC7VX485T-2FFG1761| ↩ - D:\git\PoC\netlist\XC7VX485T-2FFG1761\xil| ↩ - D:\git\PoC\netlist\XC7VX485T-2FFG1761\sata - - **Note:** The IP core search directory value is a `|` seperated list of directories. A recursive search is not performed, so sub-folders need to be named individually. - -#### 7.7 In Xilinx Vivado (Synth and xSim) +```PowerShell +cd PoCRoot +# update the local repository +git fetch --prune +# review the commit tree and messages, using the 'treea' alias +git treea +# if all changes are OK, do a fast-forward merge +git merge +``` -**The PoC-Library** has no full Vivado support, because of the incomplete -VHDL-93 support in Vivado's synthesis tool. Especially the incorrect implementation of -physical types causes errors in PoC's I/O modules. +**See also:** + - [**Running one or more testbenches**][251] + The installation can be checked by running one or more of PoC's testbenches. + - [**Running one or more netlist generation flows**][252] + The installation can also be checked by running one or more of PoC's synthesis flows. -Vivado's simulator xSim is not affected. +[251]: http://poc-library.readthedocs.io/en/latest/UsingPoC/Simulation.html +[252]: http://poc-library.readthedocs.io/en/latest/UsingPoC/Synthesis.html -**Experimental [`Vivado`](tree/Vivado) Branch:** -We provide a `vivado` branch, which can be used for Vivado synthesis. This branch contains workarounds to let Vivado synthesize our modules. As an effect some interfaces (mostly generics have changed). +## 3. Common Notes -## 8 Updating PoC +**The PoC-Library** is structured into several sub-folders naming the purpose of the folder like +[`src`](src) for sources files or [`tb`](tb) for testbench files. The structure within these folders +is always the same and based on PoC's sub-namespace tree. -**The PoC-Library** can be updated by using `git fetch`: +**Main directory overview:** -```PowerShell -cd \PoC -git fetch -# review the commit tree and messages, using the 'treea' alias -git tree --all -# if all changes are OK, do a fast-forward merge -git merge + - [`lib`](lib) - Embedded or linked external libraries. + - [`netlist`](netlist) - Configuration files and output directory for pre-configured netlist synthesis + results from vendor IP cores or from complex PoC controllers. + - [`py`](py) - Supporting Python scripts. + - [`sim`](sim) - Pre-configured waveform views for selected testbenches. + - [`src`](src) - PoC's source files grouped into sub-folders according to the sub-namespace tree. + - [`tb`](tb) - Testbench files. + - [`tcl`](tcl) - Tcl files. + - [`temp`](temp) - Automatically created temporary directors for various tools used by PoC's Python scripts. + - [`tools`](tools) - Settings/highlighting files and helpers for supported tools. + - [`ucf`](ucf) - Pre-configured constraint files (\*.ucf, \*.xdc, \*.sdc) for supported FPGA boards. + - [`xst`](xst) - Configuration files to synthesize PoC modules with Xilinx XST into a netlist. + + +All VHDL source files should be compiled into the VHDL library `PoC`. If not indicated otherwise, all +source files can be compiled using the VHDL-93 or VHDL-2008 language version. Incompatible files are +named `*.v93.vhdl` and `*.v08.vhdl` to denote the highest supported language version. + + +## 4 Cite the PoC-Library + +If you are using the PoC-Library, please let us know. We are grateful for your project's reference. +The PoC-Library hosted at [GitHub.com](https://www.github.com). Please use the following +[biblatex](https://www.ctan.org/pkg/biblatex) entry to cite us: + +```bibtex +# BibLaTex example entry +@online{poc, + title={{PoC - Pile of Cores}}, + author={{Chair of VLSI Design, Diagnostics and Architecture}}, + organization={{Technische Universität Dresden}}, + year={2016}, + url={https://github.com/VLSI-EDA/PoC}, + urldate={2016-10-28}, +} ``` - - -## 9 References - - - [PoC-Examples][poc_ex]: - A list of examples and reference implementations for the PoC-Library - - [The Q27 Project][q27]: - 27-Queens Puzzle: Massively Parellel Enumeration and Solution Counting - - [PicoBlaze-Library][pb_lib]: - The PicoBlaze-Library offers several PicoBlaze devices and code routines - to extend a common PicoBlaze environment to a little System on a Chip (SoC - or SoFPGA). - - [PicoBlaze-Examples][pb_ex]: - A SoFPGA reference implementation, based on the PoC-Library and the - PicoBlaze-Library. - - [poc_ex]: https://github.com/VLSI-EDA/PoC-Examples - [q27]: https://github.com/preusser/q27 - [pb_lib]: https://github.com/Paebbels/PicoBlaze-Library - [pb_ex]: https://github.com/Paebbels/PicoBlaze-Examples - - -If you are using the PoC-Library, please let us know. We are grateful for -your project's reference. - - [lib]: lib - [netlist]: netlist - [py]: py - [sim]: sim - [src]: src - [tb]: tb - [tcl]: tcl - [temp]: temp - [tools]: tools - [ucf]: ucf - [xst]: xst - - [wiki:download]: https://github.com/VLSI-EDA/PoC/wiki/Download - [wiki:requirements]: https://github.com/VLSI-EDA/PoC/wiki/Requirements - [wiki:configuration]: https://github.com/VLSI-EDA/PoC/wiki/Configuration - [wiki:integration]: https://github.com/VLSI-EDA/PoC/wiki/Integration - - [wiki:subnamespacetree]: https://github.com/VLSI-EDA/PoC/wiki/SubnamespaceTree diff --git a/README.tpl b/README.tpl new file mode 100644 index 00000000..c68ec27a --- /dev/null +++ b/README.tpl @@ -0,0 +1,298 @@ +{@GENERATED_HEADER@} +# The PoC-Library + +[![Python Infrastructure tested by Landscape.io](https://landscape.io/github/VLSI-EDA/PoC/{@BRANCH@}/landscape.svg?style=flat)](https://landscape.io/github/VLSI-EDA/PoC/{@BRANCH@}) +[![Build Status by Travis-CI](https://travis-ci.org/VLSI-EDA/PoC.svg?branch={@BRANCH@})](https://travis-ci.org/VLSI-EDA/PoC/branches) +[![Documentation Status](https://readthedocs.org/projects/poc-library/badge/?version=latest)](http://poc-library.readthedocs.io/en/latest/?badge=latest) +[![Join the chat at https://gitter.im/VLSI-EDA/PoC](https://badges.gitter.im/VLSI-EDA/PoC.svg)](https://gitter.im/VLSI-EDA/PoC) +![Latest tag](https://img.shields.io/github/tag/VLSI-EDA/PoC.svg?style=flat) +[![Latest release](https://img.shields.io/github/release/VLSI-EDA/PoC.svg?style=flat)](https://github.com/VLSI-EDA/PoC/releases) +[![Apache License 2.0](https://img.shields.io/github/license/VLSI-EDA/PoC.svg?style=flat)](LICENSE.md) + +This library is published and maintained by **Chair for VLSI Design, Diagnostics and Architecture** - +Faculty of Computer Science, Technische Universität Dresden, Germany +**http://vlsi-eda.inf.tu-dresden.de** + +![Technische Universität Dresden](https://github.com/VLSI-EDA/PoC/wiki/images/logo_tud.gif) + +Table of Content: +-------------------------------------------------------------------------------- + 1. [Overview](#1-overview) + 2. [Quick Start Guide](#2-quick-start-guide) + 2.1. [Requirements and Dependencies](#21-requirements-and-dependencies) + 2.2. [Download](#22-download) + 2.3. [Configuring PoC on a Local System](#23-configuring-poc-on-a-local-system) + 2.4. [Integration](#24-integration) + 2.5. [Updating](#25-updating) + 3. [Common Notes](#3-common-notes) + 4. [Cite the PoC-Library](#4-cite-the-poc-library) + +-------------------------------------------------------------------------------- + +## 1 Overview + +PoC - “Pile of Cores” provides implementations for often required hardware functions such as +Arithmetic Units, Caches, Clock-Domain-Crossing Circuits, FIFOs, RAM wrappers, and I/O Controllers. +The hardware modules are typically provided as VHDL or Verilog source code, so it can be easily +re-used in a variety of hardware designs. + +All hardware modules use a common set of VHDL packages to share new VHDL types, sub-programs and +constants. Additionally, a set of simulation helper packages eases the writing of testbenches. +Because PoC hosts a huge amount of IP cores, all cores are grouped into sub-namespaces to build a +clear hierachy. + +Various simulation and synthesis tool chains are supported to interoperate with PoC. To generalize +all supported free and commercial vendor tool chains, PoC is shipped with a Python based +infrastructure to offer a command line based frontend. + + +## 2 Quick Start Guide + +This **Quick Start Guide** gives a fast and simple introduction into PoC. All topics can be found in the +[Using PoC][201] section at [ReadTheDocs.io][202] with much more details and examples. + + +### 2.1 Requirements and Dependencies + +The PoC-Library comes with some scripts to ease most of the common tasks, like running testbenches or +generating IP cores. PoC uses Python 3 as a platform independent scripting environment. All Python +scripts are wrapped in Bash or PowerShell scripts, to hide some platform specifics of Darwin, Linux or +Windows. See [Requirements][211] for further details. + +[211]: http://poc-library.readthedocs.io/en/latest/UsingPoC/Requirements.html + + +#### PoC requires: + - A [supported synthesis tool chain][2111], if you want to synthezise IP cores. + - A [supported simulator tool chain][2112], if you want to simulate IP cores. + - The **Python 3** programming language and runtime, if you want to use PoC's infrastructure. + - A shell to execute shell scripts: + - **Bash** on Linux and OS X + - **PowerShell** on Windows + +[2111]: http://poc-library.readthedocs.io/en/latest/WhatIsPoC/SupportedToolChains.html +[2112]: http://poc-library.readthedocs.io/en/latest/WhatIsPoC/SupportedToolChains.html + + +#### PoC optionally requires: + - **Git command line** tools or + - **Git User Interface**, if you want to check out the latest 'master' or 'release' branch. + + +#### PoC depends on third part libraries: + - [Cocotb][2131] + A coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python. + - [OS-VVM][2132] + Open Source VHDL Verification Methodology. + - [VUnit][2133] + An unit testing framework for VHDL. + +All dependencies are available as GitHub repositories and are linked to PoC as Git submodules into the +[`PoCRoot\lib`][205] directory. See [Third Party Libraries][206] for more details on these libraries. + +[2131]: https://github.com/potentialventures/cocotb +[2132]: https://github.com/JimLewis/OSVVM +[2133]: https://github.com/VUnit/vunit + +[201]: http://poc-library.readthedocs.io/en/latest/UsingPoC/index.html +[202]: http://poc-library.readthedocs.io/ +[205]: https://github.com/VLSI-EDA/PoC/tree/{@BRANCH@}/lib +[206]: http://poc-library.readthedocs.io/en/latest/Miscelaneous/ThirdParty.html + + +### 2.2 Download + +The PoC-Library can be downloaded as a [zip-file][221] (latest 'release' branch), cloned with `git clone` +or embedded with `git submodule add` from GitHub. GitHub offers HTTPS and SSH as transfer protocols. See +the [Download][222] page for further details. The installation directory is referred to as `PoCRoot`. + +Protocol | Git Clone Command +-------- | :----------------------------------------------------------- +HTTPS | `git clone --recursive https://github.com/VLSI-EDA/PoC.git PoC` +SSH | `git clone --recursive ssh://git@github.com:VLSI-EDA/PoC.git PoC` + +[221]: https://github.com/VLSI-EDA/PoC/archive/{@BRANCH@}.zip +[222]: http://poc-library.readthedocs.io/en/latest/UsingPoC/Download.html + +### 2.3 Configuring PoC on a Local System + +To explore PoC's full potential, it's required to configure some paths and synthesis or simulation tool +chains. The following commands start a guided configuration process. Please follow the instructions on +screen. It's possible to relaunch the process at any time, for example to register new tools or to update +tool versions. See [Configuration][231] for more details. Run the following command line instructions to +configure PoC on your local system: + +```PowerShell +cd PoCRoot +.\poc.ps1 configure +``` + +Use the keyboard buttons: `Y` to accept, `N` to decline, `P` to skip/pass a step and `Return` to accept +a default value displayed in brackets. + +[231]: http://poc-library.readthedocs.io/en/latest/UsingPoC/PoCConfiguration.html + +### 2.4 Integration + +The PoC-Library is meant to be integrated into other HDL projects. Therefore it's recommended to create +a library folder and add the PoC-Library as a Git submodule. After the repository linking is done, some +short configuration steps are required to setup paths, tool chains and the target platform. The following +command line instructions show a short example on how to integrate PoC. + +#### a) Adding the Library as a Git submodule + +The following command line instructions will create the folder `lib\PoC\` and clone the PoC-Library as a +[Git submodule][2411] into that folder. `ProjectRoot` is the directory of the hosting Git. A detailed list +of steps can be found at [Integration][2412]. + +```powershell +cd ProjectRoot +mkdir lib | cd +git submodule add https://github.com:VLSI-EDA/PoC.git PoC +cd PoC +git remote rename origin github +cd ..\.. +git add .gitmodules lib\PoC +git commit -m "Added new git submodule PoC in 'lib\PoC' (PoC-Library)." +``` + +[2411]: http://git-scm.com/book/en/v2/Git-Tools-Submodules +[2412]: http://poc-library.readthedocs.io/en/latest/UsingPoC/Integration.html + +#### b) Configuring PoC + +The PoC-Library should be configured to explore its full potential. See [Configuration][2421] for more +details. The following command lines will start the configuration process: + +```powershell +cd ProjectRoot +.\lib\PoC\poc.ps1 configure +``` + +[2421]: http://poc-library.readthedocs.io/en/latest/UsingPoC/PoCConfiguration.html + +#### c) Creating PoC's `my_config.vhdl` and `my_project.vhdl` Files + +The PoC-Library needs two VHDL files for its configuration. These files are used to determine the most +suitable implementation depending on the provided target information. Copy the following two template +files into your project's source folder. Rename these files to \*.vhdl and configure the VHDL constants +in the files: + +```powershell +cd ProjectRoot +cp lib\PoC\src\common\my_config.vhdl.template src\common\my_config.vhdl +cp lib\PoC\src\common\my_project.vhdl.template src\common\my_project.vhdl +``` + +[my_config.vhdl](https://github.com/VLSI-EDA/PoC/blob/{@BRANCH@}/src/common/my_config.vhdl.template) defines +two global constants, which need to be adjusted: + +```vhdl +constant MY_BOARD : string := "CHANGE THIS"; -- e.g. Custom, ML505, KC705, Atlys +constant MY_DEVICE : string := "CHANGE THIS"; -- e.g. None, XC5VLX50T-1FF1136, EP2SGX90FF1508C3 +``` + +[my_project.vhdl](https://github.com/VLSI-EDA/PoC/blob/{@BRANCH@}/src/common/my_project.vhdl.template) also +defines two global constants, which need to be adjusted: + +```vhdl +constant MY_PROJECT_DIR : string := "CHANGE THIS"; -- e.g. d:/vhdl/myproject/, /home/me/projects/myproject/" +constant MY_OPERATING_SYSTEM : string := "CHANGE THIS"; -- e.g. WINDOWS, LINUX +``` + +Further informations are provided at [Creating my_config/my_project.vhdl][2431]. + +[2431]: http://poc-library.readthedocs.io/en/latest/UsingPoC/VHDLConfiguration.html + +#### d) Adding PoC's Common Packages to a Synthesis or Simulation Project + +PoC is shipped with a set of common packages, which are used by most of its modules. These packages are +stored in the `PoCRoot\src\common` directory. PoC also provides a VHDL context in `common.vhdl` , which +can be used to reference all packages at once. + + +#### e) Adding PoC's Simulation Packages to a Simulation Project + +Simulation projects additionally require PoC's simulation helper packages, which are located in the +`PoCRoot\src\sim` directory. Because some VHDL version are incompatible among each other, PoC uses +version suffixes like `*.v93.vhdl` or `*.v08.vhdl` in the file name to denote the supported VHDL version +of a file. + + +#### f) Compiling Shipped IP Cores + +Some IP Cores are shipped as pre-configured vendor IP Cores. If such IP cores shall be used in a HDL +project, it's recommended to use PoC to create, compile and if needed patch these IP cores. See +[Synthesis][2461] for more details. + +[2461]: http://poc-library.readthedocs.io/en/latest/UsingPoC/Synthesis.html + + +### 2.5 Updating + +The PoC-Library can be updated by using `git fetch` and `git merge`. + +```PowerShell +cd PoCRoot +# update the local repository +git fetch --prune +# review the commit tree and messages, using the 'treea' alias +git treea +# if all changes are OK, do a fast-forward merge +git merge +``` + +**See also:** + - [**Running one or more testbenches**][251] + The installation can be checked by running one or more of PoC's testbenches. + - [**Running one or more netlist generation flows**][252] + The installation can also be checked by running one or more of PoC's synthesis flows. + +[251]: http://poc-library.readthedocs.io/en/latest/UsingPoC/Simulation.html +[252]: http://poc-library.readthedocs.io/en/latest/UsingPoC/Synthesis.html + + +## 3. Common Notes + +**The PoC-Library** is structured into several sub-folders naming the purpose of the folder like +[`src`](src) for sources files or [`tb`](tb) for testbench files. The structure within these folders +is always the same and based on PoC's sub-namespace tree. + +**Main directory overview:** + + - [`lib`](lib) - Embedded or linked external libraries. + - [`netlist`](netlist) - Configuration files and output directory for pre-configured netlist synthesis + results from vendor IP cores or from complex PoC controllers. + - [`py`](py) - Supporting Python scripts. + - [`sim`](sim) - Pre-configured waveform views for selected testbenches. + - [`src`](src) - PoC's source files grouped into sub-folders according to the sub-namespace tree. + - [`tb`](tb) - Testbench files. + - [`tcl`](tcl) - Tcl files. + - [`temp`](temp) - Automatically created temporary directors for various tools used by PoC's Python scripts. + - [`tools`](tools) - Settings/highlighting files and helpers for supported tools. + - [`ucf`](ucf) - Pre-configured constraint files (\*.ucf, \*.xdc, \*.sdc) for supported FPGA boards. + - [`xst`](xst) - Configuration files to synthesize PoC modules with Xilinx XST into a netlist. + + +All VHDL source files should be compiled into the VHDL library `PoC`. If not indicated otherwise, all +source files can be compiled using the VHDL-93 or VHDL-2008 language version. Incompatible files are +named `*.v93.vhdl` and `*.v08.vhdl` to denote the highest supported language version. + + +## 4 Cite the PoC-Library + +If you are using the PoC-Library, please let us know. We are grateful for your project's reference. +The PoC-Library hosted at [GitHub.com](https://www.github.com). Please use the following +[biblatex](https://www.ctan.org/pkg/biblatex) entry to cite us: + +```bibtex +# BibLaTex example entry +@online{poc, + title={{PoC - Pile of Cores}}, + author={{Chair of VLSI Design, Diagnostics and Architecture}}, + organization={{Technische Universität Dresden}}, + year={2016}, + url={https://github.com/VLSI-EDA/PoC}, + urldate={2016-10-28}, +} +``` diff --git a/docs/ConstraintFiles/Altera/CycloneIII/DE0.rst b/docs/ConstraintFiles/Altera/CycloneIII/DE0.rst new file mode 100644 index 00000000..05ba9f97 --- /dev/null +++ b/docs/ConstraintFiles/Altera/CycloneIII/DE0.rst @@ -0,0 +1,4 @@ + +ECP5 Versa +########## + diff --git a/docs/ConstraintFiles/Altera/CycloneIII/DE0nano.rst b/docs/ConstraintFiles/Altera/CycloneIII/DE0nano.rst new file mode 100644 index 00000000..05ba9f97 --- /dev/null +++ b/docs/ConstraintFiles/Altera/CycloneIII/DE0nano.rst @@ -0,0 +1,4 @@ + +ECP5 Versa +########## + diff --git a/docs/ConstraintFiles/Altera/CycloneIII/index.rst b/docs/ConstraintFiles/Altera/CycloneIII/index.rst new file mode 100644 index 00000000..dc69dbd7 --- /dev/null +++ b/docs/ConstraintFiles/Altera/CycloneIII/index.rst @@ -0,0 +1,12 @@ + +Cyclone III +########### + + * DE0 + * DE0 nano + +.. toctree:: + :hidden: + + DE0 + DE0nano diff --git a/docs/ConstraintFiles/Altera/StratixIV/DE4.rst b/docs/ConstraintFiles/Altera/StratixIV/DE4.rst new file mode 100644 index 00000000..af207c3d --- /dev/null +++ b/docs/ConstraintFiles/Altera/StratixIV/DE4.rst @@ -0,0 +1,4 @@ + +DE4 +### + diff --git a/docs/ConstraintFiles/Altera/StratixIV/index.rst b/docs/ConstraintFiles/Altera/StratixIV/index.rst new file mode 100644 index 00000000..2f8c8ed9 --- /dev/null +++ b/docs/ConstraintFiles/Altera/StratixIV/index.rst @@ -0,0 +1,10 @@ + +Stratix IV +########## + + * DE4 + +.. toctree:: + :hidden: + + DE4 diff --git a/docs/ConstraintFiles/Altera/StratixV/DE5.rst b/docs/ConstraintFiles/Altera/StratixV/DE5.rst new file mode 100644 index 00000000..7e65621b --- /dev/null +++ b/docs/ConstraintFiles/Altera/StratixV/DE5.rst @@ -0,0 +1,4 @@ + +DE5 +### + diff --git a/docs/ConstraintFiles/Altera/StratixV/index.rst b/docs/ConstraintFiles/Altera/StratixV/index.rst new file mode 100644 index 00000000..fb6d772a --- /dev/null +++ b/docs/ConstraintFiles/Altera/StratixV/index.rst @@ -0,0 +1,10 @@ + +Stratix V +######### + + * DE5 + +.. toctree:: + :hidden: + + DE5 diff --git a/docs/ConstraintFiles/Altera/index.rst b/docs/ConstraintFiles/Altera/index.rst new file mode 100644 index 00000000..af7e06d7 --- /dev/null +++ b/docs/ConstraintFiles/Altera/index.rst @@ -0,0 +1,18 @@ + +Altera +###### + + * Cyclone III + * DE0 + * DE0 nano + * Stratix IV + * DE4 + * Stratix V + * DE5 + +.. toctree:: + :hidden: + + CycloneIII/index + StratixIV/index + StratixV/index diff --git a/docs/ConstraintFiles/Lattice/ECP5/ECP5Versa.rst b/docs/ConstraintFiles/Lattice/ECP5/ECP5Versa.rst new file mode 100644 index 00000000..05ba9f97 --- /dev/null +++ b/docs/ConstraintFiles/Lattice/ECP5/ECP5Versa.rst @@ -0,0 +1,4 @@ + +ECP5 Versa +########## + diff --git a/docs/ConstraintFiles/Lattice/ECP5/index.rst b/docs/ConstraintFiles/Lattice/ECP5/index.rst new file mode 100644 index 00000000..38228765 --- /dev/null +++ b/docs/ConstraintFiles/Lattice/ECP5/index.rst @@ -0,0 +1,10 @@ + +ECP5 +#### + + * ECP5 Versa + +.. toctree:: + :hidden: + + ECP5Versa diff --git a/docs/ConstraintFiles/Lattice/index.rst b/docs/ConstraintFiles/Lattice/index.rst new file mode 100644 index 00000000..c0090dd2 --- /dev/null +++ b/docs/ConstraintFiles/Lattice/index.rst @@ -0,0 +1,11 @@ + +Lattice +####### + + * ECP5 + * ECP5 Versa + +.. toctree:: + :hidden: + + ECP5/index diff --git a/docs/ConstraintFiles/Xilinx/Artix7/AC701.rst b/docs/ConstraintFiles/Xilinx/Artix7/AC701.rst new file mode 100644 index 00000000..e031cc2e --- /dev/null +++ b/docs/ConstraintFiles/Xilinx/Artix7/AC701.rst @@ -0,0 +1,4 @@ + +AC701 +##### + diff --git a/docs/ConstraintFiles/Xilinx/Artix7/index.rst b/docs/ConstraintFiles/Xilinx/Artix7/index.rst new file mode 100644 index 00000000..9306e9bf --- /dev/null +++ b/docs/ConstraintFiles/Xilinx/Artix7/index.rst @@ -0,0 +1,10 @@ + +Artix-7 +####### + + * AC701 + +.. toctree:: + :hidden: + + AC701 diff --git a/docs/ConstraintFiles/Xilinx/Kintex7/KC705.rst b/docs/ConstraintFiles/Xilinx/Kintex7/KC705.rst new file mode 100644 index 00000000..8fb45f28 --- /dev/null +++ b/docs/ConstraintFiles/Xilinx/Kintex7/KC705.rst @@ -0,0 +1,4 @@ + +KC705 +##### + diff --git a/docs/ConstraintFiles/Xilinx/Kintex7/index.rst b/docs/ConstraintFiles/Xilinx/Kintex7/index.rst new file mode 100644 index 00000000..0f036eeb --- /dev/null +++ b/docs/ConstraintFiles/Xilinx/Kintex7/index.rst @@ -0,0 +1,10 @@ + +Kintex-7 +######## + + * KC705 + +.. toctree:: + :hidden: + + KC705 diff --git a/docs/ConstraintFiles/Xilinx/Spartan3/S3ESK.rst b/docs/ConstraintFiles/Xilinx/Spartan3/S3ESK.rst new file mode 100644 index 00000000..a921a923 --- /dev/null +++ b/docs/ConstraintFiles/Xilinx/Spartan3/S3ESK.rst @@ -0,0 +1,4 @@ + +S3ESK +##### + diff --git a/docs/ConstraintFiles/Xilinx/Spartan3/S3SK.rst b/docs/ConstraintFiles/Xilinx/Spartan3/S3SK.rst new file mode 100644 index 00000000..91f756a1 --- /dev/null +++ b/docs/ConstraintFiles/Xilinx/Spartan3/S3SK.rst @@ -0,0 +1,4 @@ + +S3SK +#### + diff --git a/docs/ConstraintFiles/Xilinx/Spartan3/index.rst b/docs/ConstraintFiles/Xilinx/Spartan3/index.rst new file mode 100644 index 00000000..a78e77a5 --- /dev/null +++ b/docs/ConstraintFiles/Xilinx/Spartan3/index.rst @@ -0,0 +1,12 @@ + +Spartan-3 +######### + + * Spartan-3 Starter Kit (S3SK) + * Spartan-3E Starter Kit (S3ESK) + +.. toctree:: + :hidden: + + S3SK + S3ESK diff --git a/docs/ConstraintFiles/Xilinx/Spartan6/Atlys.rst b/docs/ConstraintFiles/Xilinx/Spartan6/Atlys.rst new file mode 100644 index 00000000..d6164828 --- /dev/null +++ b/docs/ConstraintFiles/Xilinx/Spartan6/Atlys.rst @@ -0,0 +1,4 @@ + +Atlys +##### + diff --git a/docs/ConstraintFiles/Xilinx/Spartan6/index.rst b/docs/ConstraintFiles/Xilinx/Spartan6/index.rst new file mode 100644 index 00000000..a8cb8d10 --- /dev/null +++ b/docs/ConstraintFiles/Xilinx/Spartan6/index.rst @@ -0,0 +1,10 @@ + +Spartan-6 +######### + + * Atlys + +.. toctree:: + :hidden: + + Atlys diff --git a/docs/ConstraintFiles/Xilinx/Virtex5/ML505.rst b/docs/ConstraintFiles/Xilinx/Virtex5/ML505.rst new file mode 100644 index 00000000..6e3180f9 --- /dev/null +++ b/docs/ConstraintFiles/Xilinx/Virtex5/ML505.rst @@ -0,0 +1,4 @@ + +ML505 +##### + diff --git a/docs/ConstraintFiles/Xilinx/Virtex5/ML506.rst b/docs/ConstraintFiles/Xilinx/Virtex5/ML506.rst new file mode 100644 index 00000000..29a94894 --- /dev/null +++ b/docs/ConstraintFiles/Xilinx/Virtex5/ML506.rst @@ -0,0 +1,4 @@ + +ML506 +##### + diff --git a/docs/ConstraintFiles/Xilinx/Virtex5/XUPV5.rst b/docs/ConstraintFiles/Xilinx/Virtex5/XUPV5.rst new file mode 100644 index 00000000..aba4d0ea --- /dev/null +++ b/docs/ConstraintFiles/Xilinx/Virtex5/XUPV5.rst @@ -0,0 +1,4 @@ + +XUPV5 +##### + diff --git a/docs/ConstraintFiles/Xilinx/Virtex5/index.rst b/docs/ConstraintFiles/Xilinx/Virtex5/index.rst new file mode 100644 index 00000000..7d4d6633 --- /dev/null +++ b/docs/ConstraintFiles/Xilinx/Virtex5/index.rst @@ -0,0 +1,14 @@ + +Virtex-5 +######## + + * ML505 + * ML506 + * XUPV5 + +.. toctree:: + :hidden: + + ML505 + ML506 + XUPV5 diff --git a/docs/ConstraintFiles/Xilinx/Virtex6/ML605.rst b/docs/ConstraintFiles/Xilinx/Virtex6/ML605.rst new file mode 100644 index 00000000..c9e8ab68 --- /dev/null +++ b/docs/ConstraintFiles/Xilinx/Virtex6/ML605.rst @@ -0,0 +1,4 @@ + +ML605 +##### + diff --git a/docs/ConstraintFiles/Xilinx/Virtex6/index.rst b/docs/ConstraintFiles/Xilinx/Virtex6/index.rst new file mode 100644 index 00000000..54daf458 --- /dev/null +++ b/docs/ConstraintFiles/Xilinx/Virtex6/index.rst @@ -0,0 +1,10 @@ + +Virtex-6 +######## + + * ML605 + +.. toctree:: + :hidden: + + ML605 diff --git a/docs/ConstraintFiles/Xilinx/Virtex7/VC707.rst b/docs/ConstraintFiles/Xilinx/Virtex7/VC707.rst new file mode 100644 index 00000000..57025086 --- /dev/null +++ b/docs/ConstraintFiles/Xilinx/Virtex7/VC707.rst @@ -0,0 +1,4 @@ + +VC707 +##### + diff --git a/docs/ConstraintFiles/Xilinx/Virtex7/index.rst b/docs/ConstraintFiles/Xilinx/Virtex7/index.rst new file mode 100644 index 00000000..b18ca5df --- /dev/null +++ b/docs/ConstraintFiles/Xilinx/Virtex7/index.rst @@ -0,0 +1,10 @@ + +Virtex-7 +######## + + * VC707 + +.. toctree:: + :hidden: + + VC707 diff --git a/docs/ConstraintFiles/Xilinx/Zynq7000/ZC706.rst b/docs/ConstraintFiles/Xilinx/Zynq7000/ZC706.rst new file mode 100644 index 00000000..a0758a15 --- /dev/null +++ b/docs/ConstraintFiles/Xilinx/Zynq7000/ZC706.rst @@ -0,0 +1,4 @@ + +ZC706 +##### + diff --git a/docs/ConstraintFiles/Xilinx/Zynq7000/ZedBoard.rst b/docs/ConstraintFiles/Xilinx/Zynq7000/ZedBoard.rst new file mode 100644 index 00000000..0f5c1822 --- /dev/null +++ b/docs/ConstraintFiles/Xilinx/Zynq7000/ZedBoard.rst @@ -0,0 +1,4 @@ + +ZedBoard +######## + diff --git a/docs/ConstraintFiles/Xilinx/Zynq7000/index.rst b/docs/ConstraintFiles/Xilinx/Zynq7000/index.rst new file mode 100644 index 00000000..476316a5 --- /dev/null +++ b/docs/ConstraintFiles/Xilinx/Zynq7000/index.rst @@ -0,0 +1,12 @@ + +Zynq-7000 +######### + + * ZC706 + * ZedBoard + +.. toctree:: + :hidden: + + ZC706 + ZedBoard diff --git a/docs/ConstraintFiles/Xilinx/index.rst b/docs/ConstraintFiles/Xilinx/index.rst new file mode 100644 index 00000000..27125f6c --- /dev/null +++ b/docs/ConstraintFiles/Xilinx/index.rst @@ -0,0 +1,36 @@ + +Xilinx +###### + + * Spartan-3 Boards + * Spartan-3 Starter Kit (S3SK) + * Spartan-3E Starter Kit (S3ESK) + * Spartan-6 Boards + * Atlys + * Artix-7 + * AC701 + * Kintex-7 + * KC705 + * Virtex-5 + * ML505 + * ML506 + * XUPV5 + * Virtex-6 + * ML605 + * Virtex-7 + * VC707 + * Zynq-7000 + * ZC706 + * ZedBoard + +.. toctree:: + :hidden: + + Spartan3/index + Spartan6/index + Artix7/index + Kintex7/index + Virtex5/index + Virtex6/index + Virtex7/index + Zynq7000/index diff --git a/docs/ConstraintFiles/fifo/fifo_ic_got.rst b/docs/ConstraintFiles/fifo/fifo_ic_got.rst new file mode 100644 index 00000000..14dbfa85 --- /dev/null +++ b/docs/ConstraintFiles/fifo/fifo_ic_got.rst @@ -0,0 +1,4 @@ + +fifo_ic_got +########### + diff --git a/docs/ConstraintFiles/fifo/index.rst b/docs/ConstraintFiles/fifo/index.rst new file mode 100644 index 00000000..540dc893 --- /dev/null +++ b/docs/ConstraintFiles/fifo/index.rst @@ -0,0 +1,10 @@ + +fifo +#### + + * fifo_ic_got + +.. toctree:: + :hidden: + + fifo_ic_got diff --git a/docs/ConstraintFiles/index.rst b/docs/ConstraintFiles/index.rst new file mode 100644 index 00000000..294ef1e9 --- /dev/null +++ b/docs/ConstraintFiles/index.rst @@ -0,0 +1,61 @@ + +Constraint Files +################ + +IP Core Contraint Files +*********************** + + * fifo + * misc + * sync + * net + * eth + +.. only:: PoCInternal + + * sata + * xilinx + +.. #PoCInternal + +.. toctree:: + :hidden: + + fifo/index + misc/index + net/index + +.. only:: PoCInternal + + .. toctree:: + :hidden: + + sata/index +.. #PoCInternal + + +Board Contraint Files +********************* + + * Altera Boards + * Cyclone III + * Stratix IV + * Stratix V + * Lattice Boards + * Xilinx Boards + * Spartan-3 Boards + * Spartan-6 Boards + * Artix-7 + * Kintex-7 + * Virtex-5 + * Virtex-6 + * Virtex-7 + * Zynq-7000 + + +.. toctree:: + :hidden: + + Altera/index + Lattice/index + Xilinx/index diff --git a/docs/ConstraintFiles/misc/index.rst b/docs/ConstraintFiles/misc/index.rst new file mode 100644 index 00000000..5eda1e35 --- /dev/null +++ b/docs/ConstraintFiles/misc/index.rst @@ -0,0 +1,10 @@ + +misc +#### + + * sync + +.. toctree:: + :hidden: + + sync/index diff --git a/docs/ConstraintFiles/misc/sync/index.rst b/docs/ConstraintFiles/misc/sync/index.rst new file mode 100644 index 00000000..7ba6db76 --- /dev/null +++ b/docs/ConstraintFiles/misc/sync/index.rst @@ -0,0 +1,16 @@ + +sync +#### + + * sync_Bits + * sync_Reset + * sync_Vector + * sync_Command + +.. toctree:: + :hidden: + + sync_Bits + sync_Reset + sync_Vector + sync_Command diff --git a/docs/ConstraintFiles/misc/sync/sync_Bits.rst b/docs/ConstraintFiles/misc/sync/sync_Bits.rst new file mode 100644 index 00000000..14dbfa85 --- /dev/null +++ b/docs/ConstraintFiles/misc/sync/sync_Bits.rst @@ -0,0 +1,4 @@ + +fifo_ic_got +########### + diff --git a/docs/ConstraintFiles/misc/sync/sync_Command.rst b/docs/ConstraintFiles/misc/sync/sync_Command.rst new file mode 100644 index 00000000..14dbfa85 --- /dev/null +++ b/docs/ConstraintFiles/misc/sync/sync_Command.rst @@ -0,0 +1,4 @@ + +fifo_ic_got +########### + diff --git a/docs/ConstraintFiles/misc/sync/sync_Reset.rst b/docs/ConstraintFiles/misc/sync/sync_Reset.rst new file mode 100644 index 00000000..14dbfa85 --- /dev/null +++ b/docs/ConstraintFiles/misc/sync/sync_Reset.rst @@ -0,0 +1,4 @@ + +fifo_ic_got +########### + diff --git a/docs/ConstraintFiles/misc/sync/sync_Vector.rst b/docs/ConstraintFiles/misc/sync/sync_Vector.rst new file mode 100644 index 00000000..14dbfa85 --- /dev/null +++ b/docs/ConstraintFiles/misc/sync/sync_Vector.rst @@ -0,0 +1,4 @@ + +fifo_ic_got +########### + diff --git a/docs/ConstraintFiles/net/eth/eth_RSLayer_GMII_GMII_KC705.rst b/docs/ConstraintFiles/net/eth/eth_RSLayer_GMII_GMII_KC705.rst new file mode 100644 index 00000000..a25138a0 --- /dev/null +++ b/docs/ConstraintFiles/net/eth/eth_RSLayer_GMII_GMII_KC705.rst @@ -0,0 +1,4 @@ + +eth_RSLayer_GMII_GMII_KC705 +########################### + diff --git a/docs/ConstraintFiles/net/eth/eth_RSLayer_GMII_GMII_ML505.rst b/docs/ConstraintFiles/net/eth/eth_RSLayer_GMII_GMII_ML505.rst new file mode 100644 index 00000000..61e65831 --- /dev/null +++ b/docs/ConstraintFiles/net/eth/eth_RSLayer_GMII_GMII_ML505.rst @@ -0,0 +1,4 @@ + +eth_RSLayer_GMII_GMII_ML505 +########################### + diff --git a/docs/ConstraintFiles/net/eth/eth_RSLayer_GMII_GMII_ML605.rst b/docs/ConstraintFiles/net/eth/eth_RSLayer_GMII_GMII_ML605.rst new file mode 100644 index 00000000..0895535b --- /dev/null +++ b/docs/ConstraintFiles/net/eth/eth_RSLayer_GMII_GMII_ML605.rst @@ -0,0 +1,4 @@ + +eth_RSLayer_GMII_GMII_ML605 +########################### + diff --git a/docs/ConstraintFiles/net/eth/index.rst b/docs/ConstraintFiles/net/eth/index.rst new file mode 100644 index 00000000..aba52065 --- /dev/null +++ b/docs/ConstraintFiles/net/eth/index.rst @@ -0,0 +1,14 @@ + +eth +### + + * eth_RSLayer_GMII_GMII_KC705 + * eth_RSLayer_GMII_GMII_ML505 + * eth_RSLayer_GMII_GMII_ML605 + +.. toctree:: + :hidden: + + eth_RSLayer_GMII_GMII_KC705 + eth_RSLayer_GMII_GMII_ML505 + eth_RSLayer_GMII_GMII_ML605 diff --git a/docs/ConstraintFiles/net/index.rst b/docs/ConstraintFiles/net/index.rst new file mode 100644 index 00000000..d3aced86 --- /dev/null +++ b/docs/ConstraintFiles/net/index.rst @@ -0,0 +1,10 @@ + +net +### + + * eth + +.. toctree:: + :hidden: + + eth/index diff --git a/docs/GetInvolved/Authors.rst b/docs/GetInvolved/Authors.rst new file mode 100644 index 00000000..bb7b061f --- /dev/null +++ b/docs/GetInvolved/Authors.rst @@ -0,0 +1,21 @@ +.. + Include this file. + +========================= ============================================================ +Contributor [#f1]_ Contact E-Mail +========================= ============================================================ +Genßler, Paul paul.genssler@tu-dresden.de +Köhler, Steffen steffen.koehler@tu-dresden.de +Lehmann, Patrick [#f2]_ patrick.lehmann@tu-dresden.de; paebbels@gmail.com +Preußer, Thomas B. [#f2]_ thomas.preusser@tu-dresden.de; thomas.preusser@utexas.edu +Reichel, Peter peter.reichel@eas.iis.fraunhofer.de; peter@peterreichel.info +Schirok, Jan janschirok@gmx.net +Voß, Jens jens.voss@mailbox.tu-dresden.de +Zabel, Martin [#f2]_ martin.zabel@tu-dresden.de +========================= ============================================================ + + +.. rubric:: Footnotes + +.. [#f1] In alphabetical order. +.. [#f2] Maintainer. diff --git a/docs/GetInvolved/index.rst b/docs/GetInvolved/index.rst new file mode 100644 index 00000000..c8ad85ae --- /dev/null +++ b/docs/GetInvolved/index.rst @@ -0,0 +1,237 @@ + +Get Involved +############ + +A first step might be to use and explore PoC and it's infrastructure in an own +project. Moreover, we encurage to read our `online help `_ +which covers all aspects from quickstart example up to detailed IP core +documentation. While using PoC, you might discover issues or missing feature. +Please report them as `listed below <#report-a-bug>`_. If you have an +interresting project, please send us feedback or get listed on our +:doc:`Who uses PoC? ` + +If you are more familiar with PoC and it's components, you might start asking +youself how components internally work. Please read our more advanced topics in +the online help, read our inline source code comments or start a discussion on +`Gitter <#discuss-with-us-on-gitter>`_ to ask us directly. + +Now you should be very familiar with our work and you might be interessted in +developing own components and contribute them to the main repository. See the +`next section <#contribute-to-poc>`_ for detailed instructions on the Git fork, +commit, push and pull-request flow. + +PoC ships some :doc:`third-party libraries `. If you +are interessted in getting your library or components shipped as part of PoC or +as a third-party components, please contact us. + + +Report a Bug +************ + +.. image:: https://img.shields.io/github/issues/VLSI-EDA/PoC.svg + :target: https://github.com/VLSI-EDA/PoC/issues +.. image:: https://img.shields.io/github/issues-closed/VLSI-EDA/PoC.svg + :target: https://github.com/VLSI-EDA/PoC/issues + +Please report issues of any kind in our Git provider's issue tracker. This allows +us to categorize issues into groups and assign developers to them. You can track +the issue's state and see how it's getting closed. All enhancements and feature +requests are tracked on GitHub at +`GitHub Issues `_. + + +Feature Request +*************** + +Please report missing features of any kind. We are allways looking forward to +provide a full feature set. Please use our Git provider's issue tracker to report +enhancements and feature requests, so you can track the request's status and +implementation. All enhancements and feature requests are tracked on GitHub at +`GitHub Issues `_. + + +Talk to us on Gitter +******************** + +.. image:: https://badges.gitter.im/VLSI-EDA/PoC.svg + :target: https://gitter.im/VLSI-EDA/PoC + +You can chat with us on `Gitter `_ in our Giiter Room +`VLSI-EDA/PoC `_. You can use Gitter for free +with your GitHub account. + + +Contributers License Agreement +****************************** + +We require all contributers to sign a Contributor License Agreement (CLA). If +you don't know whatfore a CLA is needed and how it prevents legal issues on both +sides, read `this short blog `_ post.PoC +uses the :doc:`Apache Contributor License Agreement ` +to match the :doc:`Apache License 2.0 `. + +So to get started, `sign the Contributor License Agreement (CLA) `_ +at `CLAHub.com `_. You can can login with your GitHub +account. + + +Contribute to PoC +***************** + +.. image:: https://img.shields.io/github/contributors/VLSI-EDA/PoC.svg + +Contibuting source code via Git is very easy. We don't provide direct write +access to our repositories. Git offers the fork and pull-request philosophy, +which means: You clone a repository, provide you changes in your own repository +and notify us about outstanding changes via pull-requests. + + +The steps 1 to 5 are done only once for setting up a forked repository. + +1. Fork our Repository +====================== + +.. image:: https://img.shields.io/github/forks/VLSI-EDA/PoC.svg + :target: https://github.com/VLSI-EDA/PoC/network/members + +Git repositories can be cloned on a Git provider's server. This procedure is +called *forking*. This allows Git providers to track the repositories network +and if repositories are related to each other and if pull-requests are possible. + +Fork our repository ``VLSI-EDA/PoC`` on GitHub into your or your's Git +organisation's account. In the following the forked repository is referenced as +``/PoC``. + +2. Clone the new Fork +===================== + +Clone this new fork to your machine. See :doc:`Downloading via git clone ` +for more details on how to clone PoC. If you have already cloned PoC, then you +can setup the new fork as an additional *remote*. You should set ``VLSI-EDA/PoC`` +as fetch target and the new fork ``/PoC`` as push target. + +**Shell Commands for Cloning:** + +.. code-block:: PowerShell + + cd GitRoot + git clone --recursive "ssh://git@github.com:/PoC.git" PoC + cd PoC + git remote rename origin github + git remote add upstream "ssh://git@github.com:VLSI-EDA/PoC.git" + git fetch --prune --tags + +**Shell Commands for Editing an existing Clone:** + +.. code-block:: PowerShell + + cd PoCRoot + git remote rename github upstream + git remote add github "ssh://git@github.com:/PoC.git" + git fetch --prune --tags + +*These commands work for Git submodules too.* + + +3. Checkout a Branch +==================== +Checkout the ``master`` or ``release`` branch and maybe stash outstanding changes. + +.. code-block:: PowerShell + + cd PoCRoot + git checkout master + + +4. Setup PoC for Developers +=========================== +Run PoC's :doc:`configuration routines ` and setup +the developer tools. You can skip (:kbd:`P`) all tool chain questions until you +reach the Git questions. + +.. code-block:: PowerShell + + cd PoCRoot + .\PoC.ps1 configure + +5. Create your own ``master`` Branch +==================================== +Each developer has his own ``master`` branch. So create one and check it out. + +.. code-block:: PowerShell + + cd PoCRoot + git branch /master + git checkout /master + git push github /master + +If PoC's branches are moving forward, you can update your own master branch by +merging changes into your branch. + +6. Create your Feature Branch +============================= + +Each new feature or bugfix is developed on a feature branch. Examples for +branch names: + ++-----------------+--------------------------------------+ +| Branch name | Description | ++=================+======================================+ +| bugfix-utils | Fixes a bug in ``utils.vhdl`` | ++-----------------+--------------------------------------+ +| docs-spelling | Fixes the documentation | ++-----------------+--------------------------------------+ +| spi-controller | A new SPI controller implementation | ++-----------------+--------------------------------------+ + + +.. code-block:: PowerShell + + cd PoCRoot + git branch / + git checkout / + git push github / + +7. Commit and Push Changes +========================== +Commit your porposed changes to your feature branch and push all changes to GitHub. + +.. code-block:: PowerShell + + cd PoCRoot + # git add .... + git commit -m "Fixed a bug in function bounds() in utils.vhdl." + git push github / + +8. Create a Pull-Request +======================== + +.. image:: https://img.shields.io/github/issues-pr/VLSI-EDA/PoC.svg + :target: https://github.com/VLSI-EDA/PoC/pulls +.. image:: https://img.shields.io/github/issues-pr-closed/VLSI-EDA/PoC.svg + :target: https://github.com/VLSI-EDA/PoC/pulls + +Go to your forked repository and klick on "Compare and Pull-Request" or go to +our PoC repository and create a new `pull request `_. + +If this is your first Pull-Request, you need to sign our Contributers License +Agreement (CLA). + +9. Keep your ``master`` up-to-date +=================================== + +.. TODO:: undocumented + + +Give us Feedback +**************** + +Please send us feedback about the PoC documentation, our IP cores or your user +story on how you use PoC. + + +List of Contributers +******************** + +.. include:: ./Authors.rst + diff --git a/docs/Miscelaneous/ChangeLog.rst b/docs/Miscelaneous/ChangeLog.rst new file mode 100644 index 00000000..f07b88bd --- /dev/null +++ b/docs/Miscelaneous/ChangeLog.rst @@ -0,0 +1,514 @@ +Change Log +########## + +.. contents:: Content of this page + :local: + +**************************************************************************************************************************************************************** +2016 +**************************************************************************************************************************************************************** + +.. This is a comment block. Copy this block for a new release version. + + New in 1.x (upcomming) + ======================= + + Already documented changes are available on the ``release`` branch at GitHub. + + * Python Infrastructure + * Common changes + * All Simulators + * Aldec Active-HDL + * GHDL + * Mentor QuestaSim + * Xilinx ISE Simulator + * Xilinx Vivado Simulator + * All Compilers + * Altera Quartus Synthesis + * Lattice Diamond (LSE) + * Xilinx ISE (XST) + * Xilinx ISE Core Generator + * Xilinx Vivado Synthesis + * Documentation + * VHDL common packages + * VHDL Simulation helpers + * New Entities + * New Testbenches + * New Constraints + * Shipped Tool and Helper Scripts + + +New in 1.x (upcomming) +======================= + +Already documented changes are available on the ``release`` branch at GitHub. + +* Python Infrastructure + + * Common changes + + * The classes ``Simulator`` and ``Compiler`` now share common methods in base class called ``Shared``. + + * ``*.files`` Parser + + * Implemented path expressions: sub-directory expression, concatenate expression + * Implemented InterpolateLiteral: access database keys in ``*.files`` files + * New Path statement, which defines a path constant calculated from a path expression + * Replaced string arguments in statements with path expressions if the desired string was a path + * Replaced simple StringToken matches with Identifier expressions + + * All Simulators + + * + + * All Compilers + + * + + * GHDL + + * Reduced ``-P`` parameters: Removed doublings + +* Documentation + + * + +* VHDL common packages + + * + +* VHDL Simulation helpers + + * Mark a testbench as failed if (registered) processes are active while finilize is called + +* New Entities + + * + +* New Testbenches + + * + +* New Constraints + + * + +* Shipped Tool and Helper Scripts + + * Updated and new Notepad++ syntax files + + +New in 1.0 (13.05.2016) +================================================================================================================================================================ + +* Python Infrastructure (Completely Reworked) + + * New Requirements + + * Python 3.5 + * py-flags + + * New command line interface + + * Synopsis: ``poc.sh|ps1 [common options] [options]`` + * Removed task specific wrapper scripts: ``testbench.sh|ps1``, ``netlist.sh|ps1``, ... + * Updated ``wrapper.ps1`` and ``wrapper.sh`` files + + * New ini-file database + + * + * Added a new config.boards.ini file to list known boards (real and virtual ones) + + * New parser for ``*.files`` files + + * conditional compiling (if-then-elseif-else) + * include statement - include other ``*.files`` files + * library statement - reference external VHDL libraries + * prepared for Cocotb testbenches + + * New parser for ``*.rules`` files + + * + + * All Tool Flows + + * Unbuffered outputs from vendor tools (realtime output to stdout from subprocess) + * Output filtering from vendor tools + + * verbose message suppression + * error and warning message highlighting + * abort flow on vendor tool errors + + * All Simulators + + * Run testbenches for different board or device configurations (see ``--board`` and ``--device`` command line options) + + * New Simulators + + * Aldec Active-HDL support (no GUI support) + + * Tested with Active-HDL from Lattice Diamond + * Tested with Active-HDL Student Edition + + * Cocotb (with QuestaSim backend on Linux) + + * New Synthesizers + + * Altera Quartus II and Quartus Prime + + * Command: ``quartus`` + + * Lattice Synthesis Engine (LSE) from Diamond + + * Command: ``lse`` + + * Xilinx Vivado + + * Command: ``vivado`` + + * GHDL + + * GHDLSimulator can distinguish different backends (mcode, gcc, llvm) + * Pre-compiled library support for GHDL + + * QuestaSim / ModelSim Altera Edition + + * Pre-compiled library support for GHDL + + * Vivado Simulator + + * Tested Vivado Simulator 2016.1 (xSim) with PoC -> still produces errors or false results + +* New Entities + + * + +* New Testbenches + + * + +* New Constraints + + * + +* New dependencies + + * Embedded Cocotb in ``/lib/cocotb`` + +* Shipped Tool and Helper Scripts + + * Updated and new Notepad++ syntax files + * Pre-compiled vendor library support + + * Added a new ``/temp/precompiled`` folder for precompiled vendor libraries + * QuestaSim supports Altera QuartusII, Xilinx ISE and Xilinx Vivado libraries + * GHDL supports Altera QuartusII, Xilinx ISE and Xilinx Vivado libraries + + +New in 0.21 (17.02.2016) +================================================================================================================================================================ + + +New in 0.20 (16.01.2016) +================================================================================================================================================================ + + +New in 0.19 (16.01.2016) +================================================================================================================================================================ + +**************************************************************************************************************************************************************** +2015 +**************************************************************************************************************************************************************** + +New in 0.18 (16.12.2015) +================================================================================================================================================================ + + +New in 0.17 (08.12.2015) +================================================================================================================================================================ + + +New in 0.16 (01.12.2015) +================================================================================================================================================================ + + +New in 0.15 (13.11.2015) +================================================================================================================================================================ + + +New in 0.14 (28.09.2015) +================================================================================================================================================================ + + +New in 0.13 (04.09.2015) +================================================================================================================================================================ + + +New in 0.12 (25.08.2015) +================================================================================================================================================================ + + +New in 0.11 (07.08.2015) +================================================================================================================================================================ + + +New in 0.10 (23.07.2015) +================================================================================================================================================================ + + +New in 0.9 (21.07.2015) +================================================================================================================================================================ + + +New in 0.8 (03.07.2015) +================================================================================================================================================================ + + +New in 0.7 (27.06.2015) +================================================================================================================================================================ + + +New in 0.6 (09.06.2015) +================================================================================================================================================================ + + +New in 0.5 (27.05.2015) +================================================================================================================================================================ + +* Updated Python infrastructure +* New testbenches: + + * sync_Reset_tb + * sync_Flag_tb + * sync_Strobe_tb + * sync_Vector_tb + * sync_Command_tb + +* Updated modules: + + * sync_Vector + * sync_Command + +* Updated packages: + + * physical + * utils + * vectors + * xil + +New in 0.4 (29.04.2015) +================================================================================================================================================================ + +* New Python infrastructure + + * Added simulators for: + + * GHDL + GTKWave + * Mentor Graphic QuestaSim + * Xilinx ISE Simulator + * Xilinx Vivado Simulator + +* New packages: + + * simulation + +* New modules: + + * PoC.comm - communication modules + + * comm_crc + + * PoC.comm.remote - remote communication modules + + * remote_terminal_control + +* New testbenches: + + * arith_addw_tb + * arith_counter_bcd_tb + * arith_prefix_and_tb + * arith_prefix_or_tb + * arith_prng_tb + +* Updated packages: + + * board + * config + * physical + * strings + * utils + +* Updated modules: + + * io_Debounce + * misc_FrequencyMeasurement + * sync_Bits + * sync_Reset + +New in 0.3 (31.03.20015) +================================================================================================================================================================ + +* Added Python infrastructure + + * Added platform wrapper scripts (\*.sh, \*.ps1) + * Added IP-core compiler scripts Netlist.py + +* Added Tools + + * Notepad++ syntax file for Xilinx UCF/XCF files + * Git configuration script to register global aliases + +* New packages: + + * components - hardware described as functions + * physical - physical types like frequency, memory and baudrate + * io + +* New modules: + + * PoC.misc + + * misc_FrequencyMeasurement + + * PoC.io - Low-speed I/O interfaces + + * io_7SegmentMux_BCD + * io_7SegmentMux_HEX + * io_FanControl + * io_PulseWidthModulation + * io_TimingCounter + * io_Debounce + * io_GlitchFilter + +* New IP-cores: + + * PoC.xil - Xilinx specific modules + + * xil_ChipScopeICON_1 + * xil_ChipScopeICON_2 + * xil_ChipScopeICON_3 + * xil_ChipScopeICON_4 + * xil_ChipScopeICON_6 + * xil_ChipScopeICON_7 + * xil_ChipScopeICON_8 + * xil_ChipScopeICON_9 + * xil_ChipScopeICON_10 + * xil_ChipScopeICON_11 + * xil_ChipScopeICON_12 + * xil_ChipScopeICON_13 + * xil_ChipScopeICON_14 + * xil_ChipScopeICON_15 + +* New constraint files: + + * ML605 + * KC705 + * VC707 + * MetaStability + * xil_Sync + +* Updated packages: + + * board + * config + +* Updated modules: + + * xil_BSCAN + +New in 0.2 (09.03.2015) +================================================================================================================================================================ + +* New packages: + + * xil + * stream + +* New modules: + + * PoC.bus - Modules for busses + + * bus_Arbiter + + * PoC.bus.stream - Modules for the PoC.Stream protocol + + * stream_Buffer + * stream_DeMux + * stream_FrameGenerator + * stream_Mirror + * stream_Mux + * stream_Source + + * PoC.misc.sync - Cross-Clock Synchronizers + + * sync_Reset + * sync_Flag + * sync_Strobe + * sync_Vector + * sync_Command + + * PoC.xil - Xilinx specific modules + + * xil_SyncBits + * xil_SyncReset + * xil_BSCAN + * xil_Reconfigurator + * xil_SystemMonitor_Virtex6 + * xil_SystemMonitor_Series7 + +* Updated packages: + + * utils + * arith + +New in 0.1 (19.02.2015) +================================================================================================================================================================ + +* New packages: + + * board - common development board configurations + * config - extract configuration parameters from device names + * utils - common utility functions + * strings - a helper package for string handling + * vectors - a helper package for std_logic_vector and std_logic_matrix + * arith + * fifo + +* New modules + + * PoC.arith - arithmetic modules + + * arith_counter_gray + * arith_counter_ring + * arith_div + * arith_prefix_and + * arith_prefix_or + * arith_prng + * arith_scaler + * arith_sqrt + + * PoC.fifo - FIFOs + + * fifo_cc_got + * fifo_cc_got_tempgot + * fifo_cc_got_tempput + * fifo_ic_got + * fifo_glue + * fifo_shift + + * PoC.mem.ocram - On-Chip RAMs + + * ocram_sp + * ocram_sdp + * ocram_esdp + * ocram_tdp + * ocram_wb + +**************************************************************************************************************************************************************** +2014 +**************************************************************************************************************************************************************** + +New in 0.0 (16.12.2014) +================================================================================================================================================================ + +* Initial commit diff --git a/docs/Miscelaneous/ThirdParty.rst b/docs/Miscelaneous/ThirdParty.rst new file mode 100644 index 00000000..b5b6caf5 --- /dev/null +++ b/docs/Miscelaneous/ThirdParty.rst @@ -0,0 +1,126 @@ +Third Party Libraries +##################### + +The PoC-Library is shiped with different third party libraries, which are +located in the ``/lib/`` folder. This document lists all these +libraries, their websites and licenses. + + +Cocotb +****** + +`Cocotb `_ is a coroutine based cosimulation +library for writing VHDL and Verilog testbenches in Python. + ++--------------------+-----------------------------------------------------------------------------------------------------------+ +| **Folder:** | ``\lib\cocotb\`` | ++--------------------+-----------------------------------------------------------------------------------------------------------+ +| **Copyright:** | Copyright © 2013, `Potential Ventures Ltd. `_, SolarFlare Communications Inc. | ++--------------------+-----------------------------------------------------------------------------------------------------------+ +| **License:** | :doc:`Revised BSD License (local copy) ` | ++--------------------+-----------------------------------------------------------------------------------------------------------+ +| **Documentation:** | `http://cocotb.readthedocs.org/ `_ | ++--------------------+-----------------------------------------------------------------------------------------------------------+ +| **Source:** | `https://github.com/potentialventures/cocotb `_ | ++--------------------+-----------------------------------------------------------------------------------------------------------+ + + +OSVVM +***** + +**Open Source VHDL Verification Methodology (OS-VVM)** is an intelligent +testbench methodology that allows mixing of “Intelligent Coverage” (coverage +driven randomization) with directed, algorithmic, file based, and constrained +random test approaches. The methodology can be adopted in part or in whole as +needed. With OSVVM you can add advanced verification methodologies to your +current testbench without having to learn a new language or throw out your +existing testbench or testbench models. + ++----------------+---------------------------------------------------------------------------------------+ +| **Folder:** | ``\lib\osvvm\`` | ++----------------+---------------------------------------------------------------------------------------+ +| **Copyright:** | Copyright © 2012-2016 by `SynthWorks Design Inc. `_ | ++----------------+---------------------------------------------------------------------------------------+ +| **License:** | :doc:`Artistic License 2.0 (local copy) ` | ++----------------+---------------------------------------------------------------------------------------+ +| **Website:** | `http://osvvm.org/ `_ | ++----------------+---------------------------------------------------------------------------------------+ +| **Source:** | `https://github.com/JimLewis/OSVVM `_ | ++----------------+---------------------------------------------------------------------------------------+ + + +VUnit +***** + +`VUnit `_ is an open source unit testing framework for +VHDL released under the terms of :doc:`Mozilla Public License, v. 2.0 `. +It features the functionality needed to realize continuous and automated testing +of your VHDL code. VUnit doesn't replace but rather complements traditional +testing methodologies by supporting a "test early and often" approach through +automation. + ++----------------+---------------------------------------------------------------------------------------------------------------+ +| **Folder:** | ``\lib\vunit\`` | ++----------------+---------------------------------------------------------------------------------------------------------------+ +| **Copyright:** | Copyright © 2014-2016, Lars Asplund `lars.anders.asplund@gmail.com `_ | ++----------------+---------------------------------------------------------------------------------------------------------------+ +| **License:** | :doc:`Mozilla Public License, Version 2.0 (local copy) ` | ++----------------+---------------------------------------------------------------------------------------------------------------+ +| **Website:** | `https://vunit.github.io/ `_ | ++----------------+---------------------------------------------------------------------------------------------------------------+ +| **Source:** | `https://github.com/VUnit/vunit `_ | ++----------------+---------------------------------------------------------------------------------------------------------------+ + + +Updating Linked Git Submodules +****************************** + +The third party libraries are embedded as Git submodules. So if the PoC-Library +was not cloned with option ``--recursive`` it's required to run the sub-module +initialization manually: + +On Linux +======== + +.. code-block:: Bash + + cd PoCRoot + git submodule init + git submodule update + +We recommend to rename the default remote repository name from 'origin' to +'github'. + +.. code-block:: Bash + + cd PoCRoot\lib\ + +.. todo:: write Bash code for Linux + +On OS X +======== + +Please see the Linux instructions. + +On Windows +========== + + +.. code-block:: PowerShell + + cd PoCRoot + git submodule init + git submodule update + +We recommend to rename the default remote repository name from 'origin' to +'github'. + +.. code-block:: PowerShell + + cd PoCRoot\lib\ + foreach($dir in (dir -Directory)) { + cd $dir + git remote rename origin github + cd .. + } + diff --git a/docs/PoC/alt/index.rst b/docs/PoC/alt/index.rst new file mode 100644 index 00000000..a54a3239 --- /dev/null +++ b/docs/PoC/alt/index.rst @@ -0,0 +1,5 @@ + +alt +=== + +.. TODO:: This namespace is reserved for Altera specific entities. diff --git a/docs/PoC/arith/arith.pkg.rst b/docs/PoC/arith/arith.pkg.rst new file mode 100644 index 00000000..bbf3b007 --- /dev/null +++ b/docs/PoC/arith/arith.pkg.rst @@ -0,0 +1,34 @@ + +Package +======== + +This package holds all component declarations for this namespace. + +.. rubric:: Exported Enumerations + + * ``tArch`` + * ``tBlocking`` + * ``tSkipping`` + +.. rubric:: Exported Functions + + * ``arith_div_latency`` + +.. rubric:: Exported Components + + * :doc:`PoC.arith.addw ` + * :doc:`PoC.arith.carrychain_inc_xilinx ` + * :doc:`PoC.arith.counter_bcd ` + * :doc:`PoC.arith.counter_gray ` + * :doc:`PoC.arith.div ` + * :doc:`PoC.arith.firstone ` + * :doc:`PoC.arith.inc_ovcy_xilinx ` + * :doc:`PoC.arith.muls_wide ` + * :doc:`PoC.arith.prefix_and_xilinx ` + * :doc:`PoC.arith.prefix_or_xilinx ` + * :doc:`PoC.arith.prng ` + * :doc:`PoC.arith.same ` + * :doc:`PoC.arith.sqrt ` + +Source file: `arith/arith.pkg.vhdl `_ + diff --git a/docs/PoC/arith/arith_addw.rst b/docs/PoC/arith/arith_addw.rst new file mode 100644 index 00000000..b96675bc --- /dev/null +++ b/docs/PoC/arith/arith_addw.rst @@ -0,0 +1,34 @@ + +arith_addw +########## + + Implements wide addition providing several options all based + on an adaptation of a carry-select approach. + + References: + * Hong Diep Nguyen and Bogdan Pasca and Thomas B. Preusser: + FPGA-Specific Arithmetic Optimizations of Short-Latency Adders, + FPL 2011. + -> ARCH: AAM, CAI, CCA + -> SKIPPING: CCC + + * Marcin Rogawski, Kris Gaj and Ekawat Homsirikamol: + A Novel Modular Adder for One Thousand Bits and More + Using Fast Carry Chains of Modern FPGAs, FPL 2014. + -> ARCH: PAI + -> SKIPPING: PPN_KS, PPN_BK + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/arith/arith_addw.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 53-70 + +Source file: `arith/arith_addw.vhdl `_ + + + diff --git a/docs/PoC/arith/arith_bcdcollect.rst b/docs/PoC/arith/arith_bcdcollect.rst new file mode 100644 index 00000000..05298e28 --- /dev/null +++ b/docs/PoC/arith/arith_bcdcollect.rst @@ -0,0 +1,20 @@ + +arith_bcdcollect +################ + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/arith/arith_bcdcollect.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 37-55 + +Source file: `arith/arith_bcdcollect.vhdl `_ + + + diff --git a/docs/PoC/arith/arith_carrychain_inc.rst b/docs/PoC/arith/arith_carrychain_inc.rst new file mode 100644 index 00000000..c9cbaf9a --- /dev/null +++ b/docs/PoC/arith/arith_carrychain_inc.rst @@ -0,0 +1,22 @@ + +arith_carrychain_inc +#################### + + This is a generic carry-chain abstraction for increment by one operations. + + Y <= X + (0...0) & Cin + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/arith/arith_carrychain_inc.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 43-52 + +Source file: `arith/arith_carrychain_inc.vhdl `_ + + + diff --git a/docs/PoC/arith/arith_cca.rst b/docs/PoC/arith/arith_cca.rst new file mode 100644 index 00000000..c1ffd14b --- /dev/null +++ b/docs/PoC/arith/arith_cca.rst @@ -0,0 +1,55 @@ + +arith_cca +######### + +Carry-Compact Adder for Xilinx Virtex-5 architectures and newer. + A carry-compact adder (CCA) utilizes the fast carry chain of contemporary + FPGA devices to implement a fast and even compacted binary word addition. + For wide operands, it accounts for the delay encountered even on this fast + signal path and uses the associated time to perform a significantly + shorter but effective LUT-based parallel computation that reduces the + length of the internal ripple-carry adder without affecting the critical + path length. + The compaction performed by the CCA is performed hierarchical on + potentially multiple levels. The number of levels may be restricted by the + optional generic parameter X. A linear compaction on a single level may + be of special interest as it typically does not increase the LUT demand + in comparison to a standard RCA implementation. + The parameter L is architecture-dependent and estimates the delay of a LUT + stage in terms of carry-chain hops. It is a tuning parameter. Values + around 20 are a good starting point. + + For a detailed description see: http://dx.doi.org/10.1109/ARITH.2011.22 + + Preusser, T.B.; Zabel, M.; Spallek, R.G.: + "Accelerating Computations on FPGA Carry Chains by Operand Compaction", + 20th IEEE Symposium on Computer Arithmetic (ARITH), 2011. + +Author: Thomas B. Preusser +================================================================================ +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +=================================================================================== + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/arith/arith_cca.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 49-61 + +Source file: `arith/arith_cca.vhdl `_ + + + diff --git a/docs/PoC/arith/arith_convert_bin2bcd.rst b/docs/PoC/arith/arith_convert_bin2bcd.rst new file mode 100644 index 00000000..01e101cc --- /dev/null +++ b/docs/PoC/arith/arith_convert_bin2bcd.rst @@ -0,0 +1,20 @@ + +arith_convert_bin2bcd +##################### + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/arith/arith_convert_bin2bcd.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 40-58 + +Source file: `arith/arith_convert_bin2bcd.vhdl `_ + + + diff --git a/docs/PoC/arith/arith_counter_bcd.rst b/docs/PoC/arith/arith_counter_bcd.rst new file mode 100644 index 00000000..c41824ec --- /dev/null +++ b/docs/PoC/arith/arith_counter_bcd.rst @@ -0,0 +1,31 @@ + +arith_counter_bcd +################# + +Counter with output in binary coded decimal (BCD). The number of BCD digits +is configurable by ``DIGITS``. + +All control signals (reset ``rst``, increment ``inc``) are high-active and +synchronous to clock ``clk``. The output ``val`` is the current counter +state. Groups of 4 bit represent one BCD digit. The lowest significant digit +is specified by ``val(3 downto 0)``. + +.. TODO:: + + * implement a ``dec`` input for decrementing + * implement a ``load`` input to load a value + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/arith/arith_counter_bcd.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 51-61 + +Source file: `arith/arith_counter_bcd.vhdl `_ + + + diff --git a/docs/PoC/arith/arith_counter_free.rst b/docs/PoC/arith/arith_counter_free.rst new file mode 100644 index 00000000..b62a3526 --- /dev/null +++ b/docs/PoC/arith/arith_counter_free.rst @@ -0,0 +1,27 @@ + +arith_counter_free +################## + +Implements a free-running counter that generates a strobe signal every +DIVIDER-th cycle the increment input was asserted. There is deliberately no +output or specification of the counter value so as to allow an implementation +to optimize as much as possible. + +The implementation guarantees a strobe output directly from a register. It is +asserted exactly for one clock after DIVIDER cycles of an asserted increment +input have been observed. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/arith/arith_counter_free.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 41-53 + +Source file: `arith/arith_counter_free.vhdl `_ + + + diff --git a/docs/PoC/arith/arith_counter_gray.rst b/docs/PoC/arith/arith_counter_gray.rst new file mode 100644 index 00000000..af2e3fc5 --- /dev/null +++ b/docs/PoC/arith/arith_counter_gray.rst @@ -0,0 +1,20 @@ + +arith_counter_gray +################## + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/arith/arith_counter_gray.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 38-51 + +Source file: `arith/arith_counter_gray.vhdl `_ + + + diff --git a/docs/PoC/arith/arith_counter_ring.rst b/docs/PoC/arith/arith_counter_ring.rst new file mode 100644 index 00000000..0a27c8c6 --- /dev/null +++ b/docs/PoC/arith/arith_counter_ring.rst @@ -0,0 +1,23 @@ + +arith_counter_ring +################## + +This module implements an up/down ring-counter with loadable initial value +(``seed``) on reset. The counter can be configured to a Johnson counter by +enabling ``INVERT_FEEDBACK``. The number of counter bits is configurable with +``BITS``. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/arith/arith_counter_ring.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 41-54 + +Source file: `arith/arith_counter_ring.vhdl `_ + + + diff --git a/docs/PoC/arith/arith_div.rst b/docs/PoC/arith/arith_div.rst new file mode 100644 index 00000000..aa2a1b0d --- /dev/null +++ b/docs/PoC/arith/arith_div.rst @@ -0,0 +1,24 @@ + +arith_div +######### + +Implementation of a Non-Performing restoring divider with a configurable radix. +The multi-cycle division is controlled by 'start' / 'rdy'. A new division is +started by asserting 'start'. The result Q = A/D is available when 'rdy' +returns to '1'. A division by zero is identified by output Z. The Q and R +outputs are undefined in this case. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/arith/arith_div.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 38-61 + +Source file: `arith/arith_div.vhdl `_ + + + diff --git a/docs/PoC/arith/arith_firstone.rst b/docs/PoC/arith/arith_firstone.rst new file mode 100644 index 00000000..d5e5a5b3 --- /dev/null +++ b/docs/PoC/arith/arith_firstone.rst @@ -0,0 +1,33 @@ + +arith_firstone +############## + +Computes from an input word, a word of the same size that has, at most, +one bit set. The output contains a set bit at the position of the rightmost +set bit of the input if and only if such a set bit exists in the input. + +A typical use case for this computation would be an arbitration over +requests with a fixed and strictly ordered priority. The terminology of +the interface assumes this use case and provides some useful extras: + +* Set tin <= '0' (no input token) to disallow grants altogether. +* Read tout (unused token) to see whether or any grant was issued. +* Read bin to obtain the binary index of the rightmost detected one bit. + The index starts at zero (0) in the rightmost bit position. + +This implementation uses carry chains for wider implementations. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/arith/arith_firstone.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 50-61 + +Source file: `arith/arith_firstone.vhdl `_ + + + diff --git a/docs/PoC/arith/arith_muls_wide.rst b/docs/PoC/arith/arith_muls_wide.rst new file mode 100644 index 00000000..80bb5fb7 --- /dev/null +++ b/docs/PoC/arith/arith_muls_wide.rst @@ -0,0 +1,22 @@ + +arith_muls_wide +############### + +Signed wide multiplication spanning multiple DSP or MULT blocks. +Small partial products are calculated through LUTs. +For detailed documentation see below. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/arith/arith_muls_wide.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 38-49 + +Source file: `arith/arith_muls_wide.vhdl `_ + + + diff --git a/docs/PoC/arith/arith_prefix_and.rst b/docs/PoC/arith/arith_prefix_and.rst new file mode 100644 index 00000000..8e939c2f --- /dev/null +++ b/docs/PoC/arith/arith_prefix_and.rst @@ -0,0 +1,22 @@ + +arith_prefix_and +################ + +Prefix AND computation: +``y(i) <= '1' when x(i downto 0) = (i downto 0 => '1') else '0';`` +This implementation uses carry chains for wider implementations. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/arith/arith_prefix_and.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 43-51 + +Source file: `arith/arith_prefix_and.vhdl `_ + + + diff --git a/docs/PoC/arith/arith_prefix_or.rst b/docs/PoC/arith/arith_prefix_or.rst new file mode 100644 index 00000000..3c40904b --- /dev/null +++ b/docs/PoC/arith/arith_prefix_or.rst @@ -0,0 +1,22 @@ + +arith_prefix_or +############### + +Prefix OR computation: +``y(i) <= '0' when x(i downto 0) = (i downto 0 => '0') else '1';`` +This implementation uses carry chains for wider implementations. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/arith/arith_prefix_or.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 43-51 + +Source file: `arith/arith_prefix_or.vhdl `_ + + + diff --git a/docs/PoC/arith/arith_prng.rst b/docs/PoC/arith/arith_prng.rst new file mode 100644 index 00000000..4c56a7d2 --- /dev/null +++ b/docs/PoC/arith/arith_prng.rst @@ -0,0 +1,26 @@ + +arith_prng +########## + +This module implementes a Pseudo-Random Number Generator (PRNG) with +configurable bit count (``BITS``). This module uses an internal list of FPGA +optimized polynomials from 3 to 168 bits. The polynomials have at most 5 tap +positions, so that long shift registers can be inferred instead of single +flip-flops. + +The generated number sequence includes the value all-zeros, but not all-ones. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/arith/arith_prng.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 46-57 + +Source file: `arith/arith_prng.vhdl `_ + + + diff --git a/docs/PoC/arith/arith_same.rst b/docs/PoC/arith/arith_same.rst new file mode 100644 index 00000000..2a54dbc5 --- /dev/null +++ b/docs/PoC/arith/arith_same.rst @@ -0,0 +1,27 @@ + +arith_same +########## + +This circuit may, for instance, be used to detect the first sign change +and, thus, the range of a two's complement number. + +These components may be chained by using the output of the predecessor as +guard input. This chaining allows to have intermediate results available +while still ensuring the use of a fast carry chain on supporting FPGA +architectures. When chaining, make sure to overlap both vector slices by one +bit position as to avoid an undetected sign change between the slices. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/arith/arith_same.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 48-57 + +Source file: `arith/arith_same.vhdl `_ + + + diff --git a/docs/PoC/arith/arith_scaler.rst b/docs/PoC/arith/arith_scaler.rst new file mode 100644 index 00000000..ab1d609d --- /dev/null +++ b/docs/PoC/arith/arith_scaler.rst @@ -0,0 +1,34 @@ + +arith_scaler +############ + +A flexible scaler for fixed-point values. The scaler is implemented for a set +of multiplier and divider values. Each individual scaling operation can +arbitrarily select one value from each these sets. + +The computation calculates: ``unsigned(arg) * MULS(msel) / DIVS(dsel)`` +rounded to the nearest (tie upwards) fixed-point result of the same precision +as ``arg``. + +The computation is started by asserting ``start`` to high for one cycle. If a +computation is running, it will be restarted. The completion of a calculation +is signaled via ``done``. ``done`` is high when no computation is in progress. +The result of the last scaling operation is stable and can be read from +``res``. The weight of the LSB of ``res`` is the same as the LSB of ``arg``. +Make sure to tap a sufficient number of result bits in accordance to the +highest scaling ratio to be used in order to avoid a truncation overflow. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/arith/arith_scaler.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 52-69 + +Source file: `arith/arith_scaler.vhdl `_ + + + diff --git a/docs/PoC/arith/arith_shifter_barrel.rst b/docs/PoC/arith/arith_shifter_barrel.rst new file mode 100644 index 00000000..309c3295 --- /dev/null +++ b/docs/PoC/arith/arith_shifter_barrel.rst @@ -0,0 +1,26 @@ + +arith_shifter_barrel +#################### + +This Barrel-Shifter supports: + +* shifting and rotating +* right and left operations +* arithmetic and logic mode (only valid for shift operations) + +This is equivalent to the CPU instructions: SLL, SLA, SRL, SRA, RL, RR + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/arith/arith_shifter_barrel.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 45-57 + +Source file: `arith/arith_shifter_barrel.vhdl `_ + + + diff --git a/docs/PoC/arith/arith_sqrt.rst b/docs/PoC/arith/arith_sqrt.rst new file mode 100644 index 00000000..8f3d9fb8 --- /dev/null +++ b/docs/PoC/arith/arith_sqrt.rst @@ -0,0 +1,22 @@ + +arith_sqrt +########## + +Iterative Square Root Extractor. + +Its computation requires (N+1)/2 steps for an argument bit width of N. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/arith/arith_sqrt.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 38-55 + +Source file: `arith/arith_sqrt.vhdl `_ + + + diff --git a/docs/PoC/arith/index.rst b/docs/PoC/arith/index.rst new file mode 100644 index 00000000..786577f1 --- /dev/null +++ b/docs/PoC/arith/index.rst @@ -0,0 +1,52 @@ +arith +===== + +These are arithmetic entities.... + +**Package** + +:doc:`PoC.arith ` + +**Entities** + + * :doc:`PoC.arith.addw ` + * :doc:`PoC.arith.carrychain_inc ` + * :doc:`PoC.arith.convert_bin2bcd ` + * :doc:`PoC.arith.counter_bcd ` + * :doc:`PoC.arith.counter_free ` + * :doc:`PoC.arith.counter_gray ` + * :doc:`PoC.arith.counter_ring ` + * :doc:`PoC.arith.div ` + * :doc:`PoC.arith.firstone ` + * :doc:`PoC.arith.muls_wide ` + * :doc:`PoC.arith.prefix_and ` + * :doc:`PoC.arith.prefix_or ` + * :doc:`PoC.arith.prng ` + * :doc:`PoC.arith.same ` + * :doc:`PoC.arith.scaler ` + * :doc:`PoC.arith.shifter_barrel ` + * :doc:`PoC.arith.sqrt ` + + +.. toctree:: + :hidden: + + arith.pkg + + arith_addw + arith_carrychain_inc + arith_convert_bin2bcd + arith_counter_bcd + arith_counter_free + arith_counter_gray + arith_counter_ring + arith_div + arith_firstone + arith_muls_wide + arith_prefix_and + arith_prefix_or + arith_prng + arith_same + arith_scaler + arith_shifter_barrel + arith_sqrt diff --git a/docs/PoC/bus/bus_Arbiter.rst b/docs/PoC/bus/bus_Arbiter.rst new file mode 100644 index 00000000..2fbef755 --- /dev/null +++ b/docs/PoC/bus/bus_Arbiter.rst @@ -0,0 +1,23 @@ + +bus_Arbiter +########### + +This module implements a generic arbiter. It currently supports the +following arbitration strategies: + +* Round Robin (RR) + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/bus/bus_Arbiter.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-60 + +Source file: `bus/bus_Arbiter.vhdl `_ + + + diff --git a/docs/PoC/bus/index.rst b/docs/PoC/bus/index.rst new file mode 100644 index 00000000..911fe07b --- /dev/null +++ b/docs/PoC/bus/index.rst @@ -0,0 +1,22 @@ + +bus +=== + +These are bus entities.... + +**Sub-namespaces** + + * :doc:`PoC.bus.stream ` + * :doc:`PoC.bus.wb ` + +**Entities** + + * :doc:`PoC.bus.Arbiter ` + +.. toctree:: + :hidden: + + stream/index + wb/index + + bus_Arbiter diff --git a/docs/PoC/bus/stream/index.rst b/docs/PoC/bus/stream/index.rst new file mode 100644 index 00000000..7d23fbf0 --- /dev/null +++ b/docs/PoC/bus/stream/index.rst @@ -0,0 +1,15 @@ + +stream +^^^^^^ + +PoC.Stream modules ... + +.. toctree:: + + stream_Buffer + stream_DeMux + stream_Mux + stream_Mirror + stream_Sink + stream_Source + stream_FrameGenerator diff --git a/docs/PoC/bus/stream/stream_Buffer.rst b/docs/PoC/bus/stream/stream_Buffer.rst new file mode 100644 index 00000000..0cab881a --- /dev/null +++ b/docs/PoC/bus/stream/stream_Buffer.rst @@ -0,0 +1,23 @@ + +stream_Buffer +############# + +This module implements a generic buffer (FIFO) for the +:doc:`PoC.Stream ` protocol. It is generic in +``DATA_BITS`` and in ``META_BITS`` as well as in FIFO depths for data and +meta information. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/bus/stream/stream_Buffer.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 44-74 + +Source file: `bus/stream/stream_Buffer.vhdl `_ + + + diff --git a/docs/PoC/bus/stream/stream_DeMux.rst b/docs/PoC/bus/stream/stream_DeMux.rst new file mode 100644 index 00000000..4a75cdc4 --- /dev/null +++ b/docs/PoC/bus/stream/stream_DeMux.rst @@ -0,0 +1,20 @@ + +stream_DeMux +############ + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/bus/stream/stream_DeMux.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 41-70 + +Source file: `bus/stream/stream_DeMux.vhdl `_ + + + diff --git a/docs/PoC/bus/stream/stream_FrameGenerator.rst b/docs/PoC/bus/stream/stream_FrameGenerator.rst new file mode 100644 index 00000000..83531c5d --- /dev/null +++ b/docs/PoC/bus/stream/stream_FrameGenerator.rst @@ -0,0 +1,20 @@ + +stream_FrameGenerator +##################### + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/bus/stream/stream_FrameGenerator.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 40-66 + +Source file: `bus/stream/stream_FrameGenerator.vhdl `_ + + + diff --git a/docs/PoC/bus/stream/stream_Mirror.rst b/docs/PoC/bus/stream/stream_Mirror.rst new file mode 100644 index 00000000..166f44b3 --- /dev/null +++ b/docs/PoC/bus/stream/stream_Mirror.rst @@ -0,0 +1,20 @@ + +stream_Mirror +############# + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/bus/stream/stream_Mirror.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 41-70 + +Source file: `bus/stream/stream_Mirror.vhdl `_ + + + diff --git a/docs/PoC/bus/stream/stream_Mux.rst b/docs/PoC/bus/stream/stream_Mux.rst new file mode 100644 index 00000000..4f8f069b --- /dev/null +++ b/docs/PoC/bus/stream/stream_Mux.rst @@ -0,0 +1,20 @@ + +stream_Mux +########## + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/bus/stream/stream_Mux.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 41-69 + +Source file: `bus/stream/stream_Mux.vhdl `_ + + + diff --git a/docs/PoC/bus/stream/stream_Sink.rst b/docs/PoC/bus/stream/stream_Sink.rst new file mode 100644 index 00000000..718ef6c0 --- /dev/null +++ b/docs/PoC/bus/stream/stream_Sink.rst @@ -0,0 +1,20 @@ + +stream_Sink +########### + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/bus/stream/stream_Sink.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-59 + +Source file: `bus/stream/stream_Sink.vhdl `_ + + + diff --git a/docs/PoC/bus/stream/stream_Source.rst b/docs/PoC/bus/stream/stream_Source.rst new file mode 100644 index 00000000..5f182b9b --- /dev/null +++ b/docs/PoC/bus/stream/stream_Source.rst @@ -0,0 +1,20 @@ + +stream_Source +############# + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/bus/stream/stream_Source.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-58 + +Source file: `bus/stream/stream_Source.vhdl `_ + + + diff --git a/docs/PoC/bus/wb/index.rst b/docs/PoC/bus/wb/index.rst new file mode 100644 index 00000000..1248d92b --- /dev/null +++ b/docs/PoC/bus/wb/index.rst @@ -0,0 +1,12 @@ + +wb +^^ + +WishBone modules ... + +**Entities:** + +.. toctree:: + wb_ocram + wb_fifo_adapter + wb_uart_wrapper diff --git a/docs/PoC/bus/wb/wb_fifo_adapter.rst b/docs/PoC/bus/wb/wb_fifo_adapter.rst new file mode 100644 index 00000000..bbffb8e4 --- /dev/null +++ b/docs/PoC/bus/wb/wb_fifo_adapter.rst @@ -0,0 +1,27 @@ + +wb_fifo_adapter +############### + +Small FIFOs are included in this module, if larger or asynchronous +transmit / receive FIFOs are required, then they must be connected +externally. + +old comments: + UART BAUD rate generator + bclk_r = bit clock is rising + bclk_x8_r = bit clock times 8 is rising + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/bus/wb/wb_fifo_adapter.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 80-104 + +Source file: `bus/wb/wb_fifo_adapter.vhdl `_ + + + diff --git a/docs/PoC/bus/wb/wb_ocram.rst b/docs/PoC/bus/wb/wb_ocram.rst new file mode 100644 index 00000000..89a2daf7 --- /dev/null +++ b/docs/PoC/bus/wb/wb_ocram.rst @@ -0,0 +1,39 @@ + +ocram_wb +######## + +This slave supports Wishbone Registered Feedback bus cycles (aka. burst +transfers / advanced synchronous cycle termination). The mode "Incrementing +burst cycle" (CTI = 010) with "Linear burst" (BTE = 00) is supported. + +If your master does support Wishbone Classis bus cycles only, then connect +wb_cti_i = "000" and wb_bte_i = "00". + +Connect the ocram of your choice to the ram_* port signals. (Every RAM with +single cyle read latency is supported.) + +Configuration: +-------------- +PIPE_STAGES = 1 + The RAM output is directly connected to the bus. Thus, the + read access latency (one cycle) is short. But, the RAM's read timing delay + must be respected. + +PIPE_STAGES = 2 + The RAM output is registered again. Thus, the read access + latency is two cycles. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/bus/wb/wb_ocram.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 54-80 + +Source file: `bus/wb/wb_ocram.vhdl `_ + + + diff --git a/docs/PoC/bus/wb/wb_uart_wrapper.rst b/docs/PoC/bus/wb/wb_uart_wrapper.rst new file mode 100644 index 00000000..48e5bd7c --- /dev/null +++ b/docs/PoC/bus/wb/wb_uart_wrapper.rst @@ -0,0 +1,22 @@ + +uart_wb +####### + +Wrapper module for :doc:`PoC.io.uart.rx ` and +:doc:`PoC.io.uart.tx ` to support the Wishbone +interface. Synchronized reset is used. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/bus/wb/wb_uart_wrapper.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 40-69 + +Source file: `bus/wb/wb_uart_wrapper.vhdl `_ + + + diff --git a/docs/PoC/cache/cache_par.rst b/docs/PoC/cache/cache_par.rst new file mode 100644 index 00000000..0ba198f5 --- /dev/null +++ b/docs/PoC/cache/cache_par.rst @@ -0,0 +1,55 @@ + +cache_par +######### + +All inputs are synchronous to the rising-edge of the clock `clock`. + +**Command truth table:** + ++---------+-----------+-------------+---------+---------------------------------+ +| Request | ReadWrite | Invalidate | Replace | Command | ++=========+===========+=============+=========+=================================+ +| 0 | 0 | 0 | 0 | None | ++---------+-----------+-------------+---------+---------------------------------+ +| 1 | 0 | 0 | 0 | Read cache line | ++---------+-----------+-------------+---------+---------------------------------+ +| 1 | 1 | 0 | 0 | Update cache line | ++---------+-----------+-------------+---------+---------------------------------+ +| 1 | 0 | 1 | 0 | Read cache line and discard it | ++---------+-----------+-------------+---------+---------------------------------+ +| 1 | 1 | 1 | 0 | Write cache line and discard it | ++---------+-----------+-------------+---------+---------------------------------+ +| 0 | | 0 | 1 | Replace cache line. | ++---------+-----------+-------------+---------+---------------------------------+ + +All commands use ``Address`` to lookup (request) or replace a cache line. +``Address`` and ``OldAddress`` do not include the word/byte select part. +Each command is completed within one clock cycle, but outputs are delayed as +described below. + +Upon requests, the outputs ``CacheMiss`` and ``CacheHit`` indicate (high-active) +whether the ``Address`` is stored within the cache, or not. Both outputs have a +latency of one clock cycle. + +Upon writing a cache line, the new content is given by ``CacheLineIn``. +Upon reading a cache line, the current content is outputed on ``CacheLineOut`` +with a latency of one clock cycle. + +Upon replacing a cache line, the new content is given by ``CacheLineIn``. The +old content is outputed on ``CacheLineOut`` and the old tag on ``OldAddress``, +both with a latency of one clock cycle. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/cache/cache_par.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 76-100 + +Source file: `cache/cache_par.vhdl `_ + + + diff --git a/docs/PoC/cache/cache_replacement_policy.rst b/docs/PoC/cache/cache_replacement_policy.rst new file mode 100644 index 00000000..edd0530d --- /dev/null +++ b/docs/PoC/cache/cache_replacement_policy.rst @@ -0,0 +1,62 @@ + +cache_replacement_policy +######################## + + +**Supported policies:** + ++----------+-----------------------+-----------+ +| Abbr. | Policies | supported | ++==========+=======================+===========+ +| RR | round robin | not yet | ++----------+-----------------------+-----------+ +| RAND | random | not yet | ++----------+-----------------------+-----------+ +| CLOCK | clock algorithm | not yet | ++----------+-----------------------+-----------+ +| LRU | least recently used | YES | ++----------+-----------------------+-----------+ +| LFU | least frequently used | not yet | ++----------+-----------------------+-----------+ + +**Command thruth table:** + ++-----------+-----------+-------------+---------+-----------------------------------------------------+ +| TagAccess | ReadWrite | Invalidate | Replace | Command | ++===========+===========+=============+=========+=====================================================+ +| 0 | | | 0 | None | ++-----------+-----------+-------------+---------+-----------------------------------------------------+ +| 1 | 0 | 0 | 0 | TagHit and reading a cache line | ++-----------+-----------+-------------+---------+-----------------------------------------------------+ +| 1 | 1 | 0 | 0 | TagHit and writing a cache line | ++-----------+-----------+-------------+---------+-----------------------------------------------------+ +| 1 | 0 | 1 | 0 | TagHit and invalidate a cache line (while reading) | ++-----------+-----------+-------------+---------+-----------------------------------------------------+ +| 1 | 1 | 1 | 0 | TagHit and invalidate a cache line (while writing) | ++-----------+-----------+-------------+---------+-----------------------------------------------------+ +| 0 | | 0 | 1 | Replace cache line | ++-----------+-----------+-------------+---------+-----------------------------------------------------+ + +In a set-associative cache, each cache-set has its own instance of this component. + +The input ``HitWay`` specifies the accessed way in a fully-associative or +set-associative cache. + +The output ``ReplaceWay`` identifies the way which will be replaced as next by +a replace command. In a set-associative cache, this is the way in a specific +cache set (see above). + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/cache/cache_replacement_policy.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 85-104 + +Source file: `cache/cache_replacement_policy.vhdl `_ + + + diff --git a/docs/PoC/cache/cache_tagunit_par.rst b/docs/PoC/cache/cache_tagunit_par.rst new file mode 100644 index 00000000..5f31022f --- /dev/null +++ b/docs/PoC/cache/cache_tagunit_par.rst @@ -0,0 +1,55 @@ + +cache_tagunit_par +################# + +All inputs are synchronous to the rising-edge of the clock ``clock``. + +**Command thruth table:** + ++---------+-----------+-------------+---------+----------------------------------+ +| Request | ReadWrite | Invalidate | Replace | Command | ++=========+===========+=============+=========+==================================+ +| 0 | 0 | 0 | 0 | None | ++---------+-----------+-------------+---------+----------------------------------+ +| 1 | 0 | 0 | 0 | Read cache line | ++---------+-----------+-------------+---------+----------------------------------+ +| 1 | 1 | 0 | 0 | Update cache line | ++---------+-----------+-------------+---------+----------------------------------+ +| 1 | 0 | 1 | 0 | Read cache line and discard it | ++---------+-----------+-------------+---------+----------------------------------+ +| 1 | 1 | 1 | 0 | Write cache line and discard it | ++---------+-----------+-------------+---------+----------------------------------+ +| 0 | | 0 | 1 | Replace cache line. | ++---------+-----------+-------------+---------+----------------------------------+ + +All commands use ``Address`` to lookup (request) or replace a cache line. +Each command is completed within one clock cycle. + +Upon requests, the outputs ``CacheMiss`` and ``CacheHit`` indicate (high-active) +immediately (combinational) whether the ``Address`` is stored within the cache, or not. +But, the cache-line usage is updated at the rising-edge of the clock. +If hit, ``LineIndex`` specifies the cache line where to find the content. + +The output ``ReplaceLineIndex`` indicates which cache line will be replaced as +next by a replace command. The output ``OldAddress`` specifies the old tag stored at this +index. The replace command will store the ``NewAddress`` and update the cache-line +usage at the rising-edge of the clock. + +For a direct-mapped cache, the number of ``CACHE_LINES`` must be a power of 2. +For a set-associative cache, the expression ``CACHE_LINES / ASSOCIATIVITY`` +must be a power of 2. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/cache/cache_tagunit_par.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 75-99 + +Source file: `cache/cache_tagunit_par.vhdl `_ + + + diff --git a/docs/PoC/cache/cache_tagunit_seq.rst b/docs/PoC/cache/cache_tagunit_seq.rst new file mode 100644 index 00000000..1268786c --- /dev/null +++ b/docs/PoC/cache/cache_tagunit_seq.rst @@ -0,0 +1,20 @@ + +cache_tagunit_seq +################# + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/cache/cache_tagunit_seq.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 39-73 + +Source file: `cache/cache_tagunit_seq.vhdl `_ + + + diff --git a/docs/PoC/cache/index.rst b/docs/PoC/cache/index.rst new file mode 100644 index 00000000..a49a74df --- /dev/null +++ b/docs/PoC/cache/index.rst @@ -0,0 +1,20 @@ + +cache +===== + +These are cache entities.... + +**Entities** + + * :doc:`PoC.cache.par ` + * :doc:`PoC.cache.tagunit_par ` + * :doc:`PoC.cache.tagunit_seq ` + + +.. toctree:: + :hidden: + + cache_par + cache_replacement_policy + cache_tagunit_par + cache_tagunit_seq diff --git a/docs/PoC/comm/comm_crc.rst b/docs/PoC/comm/comm_crc.rst new file mode 100644 index 00000000..f50c7508 --- /dev/null +++ b/docs/PoC/comm/comm_crc.rst @@ -0,0 +1,26 @@ + +comm_crc +######## + +Computes the Cyclic Redundancy Check (CRC) for a data packet as remainder +of the polynomial division of the message by the given generator +polynomial (GEN). + +The computation is unrolled so as to process an arbitrary number of +message bits per step. The generated CRC is independent from the chosen +processing width. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/comm/comm_crc.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 45-64 + +Source file: `comm/comm_crc.vhdl `_ + + + diff --git a/docs/PoC/comm/comm_scramble.rst b/docs/PoC/comm/comm_scramble.rst new file mode 100644 index 00000000..1a6d0c3d --- /dev/null +++ b/docs/PoC/comm/comm_scramble.rst @@ -0,0 +1,22 @@ + +comm_scramble +############# + +The LFSR computation is unrolled to generate an arbitrary number of mask +bits in parallel. The mask are output in little endian. The generated bit +sequence is independent from the chosen output width. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/comm/comm_scramble.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 37-51 + +Source file: `comm/comm_scramble.vhdl `_ + + + diff --git a/docs/PoC/comm/index.rst b/docs/PoC/comm/index.rst new file mode 100644 index 00000000..5063c228 --- /dev/null +++ b/docs/PoC/comm/index.rst @@ -0,0 +1,10 @@ + +comm +==== + +These are communication entities.... + +.. toctree:: + + comm_crc + comm_scramble diff --git a/docs/PoC/common/components.rst b/docs/PoC/common/components.rst new file mode 100644 index 00000000..d431ee48 --- /dev/null +++ b/docs/PoC/common/components.rst @@ -0,0 +1,9 @@ + +components +^^^^^^^^^^ + +Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. +At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor +sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et +accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet + diff --git a/docs/PoC/common/config.rst b/docs/PoC/common/config.rst new file mode 100644 index 00000000..18e86ed9 --- /dev/null +++ b/docs/PoC/common/config.rst @@ -0,0 +1,9 @@ + +config +^^^^^^ + +Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. +At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor +sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et +accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet + diff --git a/docs/PoC/common/context.rst b/docs/PoC/common/context.rst new file mode 100644 index 00000000..05c4c6ea --- /dev/null +++ b/docs/PoC/common/context.rst @@ -0,0 +1,9 @@ + +context +^^^^^^^ + +Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. +At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor +sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et +accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet + diff --git a/docs/PoC/common/fileio.rst b/docs/PoC/common/fileio.rst new file mode 100644 index 00000000..7ea9ca85 --- /dev/null +++ b/docs/PoC/common/fileio.rst @@ -0,0 +1,9 @@ + +fileio +^^^^^^ + +Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. +At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor +sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et +accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet + diff --git a/docs/PoC/common/index.rst b/docs/PoC/common/index.rst new file mode 100644 index 00000000..e96eda89 --- /dev/null +++ b/docs/PoC/common/index.rst @@ -0,0 +1,16 @@ + +Common Packages +=============== + +These are common packages.... + +.. toctree:: + + components + context + config + fileio + math + strings + utils + vectors diff --git a/docs/PoC/common/math.rst b/docs/PoC/common/math.rst new file mode 100644 index 00000000..c038a7b4 --- /dev/null +++ b/docs/PoC/common/math.rst @@ -0,0 +1,9 @@ + +math +^^^^ + +Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. +At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor +sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et +accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet + diff --git a/docs/PoC/common/strings.rst b/docs/PoC/common/strings.rst new file mode 100644 index 00000000..aef6f3f3 --- /dev/null +++ b/docs/PoC/common/strings.rst @@ -0,0 +1,9 @@ + +strings +^^^^^^^ + +Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. +At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor +sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et +accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet + diff --git a/docs/PoC/common/utils.rst b/docs/PoC/common/utils.rst new file mode 100644 index 00000000..1885f47b --- /dev/null +++ b/docs/PoC/common/utils.rst @@ -0,0 +1,9 @@ + +utils +^^^^^ + +Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. +At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor +sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et +accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet + diff --git a/docs/PoC/common/vectors.rst b/docs/PoC/common/vectors.rst new file mode 100644 index 00000000..b42511a3 --- /dev/null +++ b/docs/PoC/common/vectors.rst @@ -0,0 +1,9 @@ + +vectors +^^^^^^^ + +Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. +At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor +sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et +accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet + diff --git a/docs/PoC/fifo/fifo.pkg.rst b/docs/PoC/fifo/fifo.pkg.rst new file mode 100644 index 00000000..967ddd16 --- /dev/null +++ b/docs/PoC/fifo/fifo.pkg.rst @@ -0,0 +1,7 @@ + +Package +======== + +This package holds all component declarations for this namespace. + +Source file: `fifo/fifo.pkg.vhdl `_ diff --git a/docs/PoC/fifo/fifo_cc_got.rst b/docs/PoC/fifo/fifo_cc_got.rst new file mode 100644 index 00000000..da288a1c --- /dev/null +++ b/docs/PoC/fifo/fifo_cc_got.rst @@ -0,0 +1,75 @@ + +fifo_cc_got +########### + +This module implements a regular FIFO with common clock (cc), pipelined +interface. Common clock means read and write port use the same clock. The +FIFO size can be configured in word width (``D_BITS``) and minimum word count +``MIN_DEPTH``. The specified depth is rounded up to the next suitable value. + +``DATA_REG`` (=true) is a hint, that distributed memory or registers should +be used as data storage. The actual memory type depends on the device +architecture. See implementation for details. + +``*STATE_*_BITS`` defines the granularity of the fill state indicator +``*state_*``. If a fill state is not of interest, set ``*STATE_*_BITS = 0``. +``fstate_rd`` is associated with the read clock domain and outputs the +guaranteed number of words available in the FIFO. ``estate_wr`` is associated +with the write clock domain and outputs the number of words that is +guaranteed to be accepted by the FIFO without a capacity overflow. Note that +both these indicators cannot replace the ``full`` or ``valid`` outputs as +they may be implemented as giving pessimistic bounds that are minimally off +the true fill state. + +``fstate_rd`` and ``estate_wr`` are combinatorial outputs and include an address +comparator (subtractor) in their path. + +.. rubric:: Examples: + +* FSTATE_RD_BITS = 1: + + +-----------+----------------------+ + | fstate_rd | filled (at least) | + +===========+======================+ + | 0 | 0/2 full | + +-----------+----------------------+ + | 1 | 1/2 full (half full) | + +-----------+----------------------+ + +* FSTATE_RD_BITS = 2: + + +-----------+----------------------+ + | fstate_rd | filled (at least) | + +===========+======================+ + | 0 | 0/4 full | + +-----------+----------------------+ + | 1 | 1/4 full | + +-----------+----------------------+ + | 2 | 2/4 full (half full) | + +-----------+----------------------+ + | 3 | 3/4 full | + +-----------+----------------------+ + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/fifo/fifo_cc_got.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 98-124 + +Source file: `fifo/fifo_cc_got.vhdl `_ + +.. seealso:: + + :doc:`PoC.fifo.dc_got ` + For a FIFO with dependent clocks. + :doc:`PoC.fifo.ic_got ` + For a FIFO with independent clocks (cross-clock FIFO). + :doc:`PoC.fifo.glue ` + For a minimal FIFO / pipeline decoupling. + + + diff --git a/docs/PoC/fifo/fifo_cc_got_tempgot.rst b/docs/PoC/fifo/fifo_cc_got_tempgot.rst new file mode 100644 index 00000000..1cca8eec --- /dev/null +++ b/docs/PoC/fifo/fifo_cc_got_tempgot.rst @@ -0,0 +1,56 @@ + +fifo_cc_got_tempgot +################### + +The specified depth (``MIN_DEPTH``) is rounded up to the next suitable value. + +As uncommitted reads occupy FIFO space that is not yet available for +writing, an instance of this FIFO can, indeed, report ``full`` and ``not vld`` +at the same time. While a ``commit`` would eventually make space available for +writing (``not ful``), a ``rollback`` would re-iterate data for reading +(``vld``). + +``commit`` and ``rollback`` are inclusive and apply to all reads (``got``) since +the previous ``commit`` or ``rollback`` up to and including a potentially +simultaneous read. + +The FIFO state upon a simultaneous assertion of ``commit`` and ``rollback`` is +*undefined*! + +``*STATE_*_BITS`` defines the granularity of the fill state indicator +``*state_*``. ``fstate_rd`` is associated with the read clock domain and outputs +the guaranteed number of words available in the FIFO. ``estate_wr`` is +associated with the write clock domain and outputs the number of words that +is guaranteed to be accepted by the FIFO without a capacity overflow. Note +that both these indicators cannot replace the ``full`` or ``valid`` outputs as +they may be implemented as giving pessimistic bounds that are minimally off +the true fill state. + +If a fill state is not of interest, set ``*STATE_*_BITS = 0``. + +``fstate_rd`` and ``estate_wr`` are combinatorial outputs and include an address +comparator (subtractor) in their path. + +Examples: +- FSTATE_RD_BITS = 1: fstate_rd == 0 => 0/2 full + fstate_rd == 1 => 1/2 full (half full) + +- FSTATE_RD_BITS = 2: fstate_rd == 0 => 0/4 full + fstate_rd == 1 => 1/4 full + fstate_rd == 2 => 2/4 full + fstate_rd == 3 => 3/4 full + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/fifo/fifo_cc_got_tempgot.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 80-109 + +Source file: `fifo/fifo_cc_got_tempgot.vhdl `_ + + + diff --git a/docs/PoC/fifo/fifo_cc_got_tempput.rst b/docs/PoC/fifo/fifo_cc_got_tempput.rst new file mode 100644 index 00000000..40a9a611 --- /dev/null +++ b/docs/PoC/fifo/fifo_cc_got_tempput.rst @@ -0,0 +1,56 @@ + +fifo_cc_got_tempput +################### + +The specified depth (``MIN_DEPTH``) is rounded up to the next suitable value. + +As uncommitted writes populate FIFO space that is not yet available for +reading, an instance of this FIFO can, indeed, report ``full`` and ``not vld`` +at the same time. While a ``commit`` would eventually make data available for +reading (``vld``), a ``rollback`` would free the space for subsequent writing +(``not ful``). + +``commit`` and ``rollback`` are inclusive and apply to all writes (``put``) since +the previous 'commit' or 'rollback' up to and including a potentially +simultaneous write. + +The FIFO state upon a simultaneous assertion of ``commit`` and ``rollback`` is +*undefined*. + +``*STATE_*_BITS`` defines the granularity of the fill state indicator +``*state_*``. ``fstate_rd`` is associated with the read clock domain and outputs +the guaranteed number of words available in the FIFO. ``estate_wr`` is +associated with the write clock domain and outputs the number of words that +is guaranteed to be accepted by the FIFO without a capacity overflow. Note +that both these indicators cannot replace the ``full`` or ``valid`` outputs as +they may be implemented as giving pessimistic bounds that are minimally off +the true fill state. + +If a fill state is not of interest, set ``*STATE_*_BITS = 0``. + +``fstate_rd`` and ``estate_wr`` are combinatorial outputs and include an address +comparator (subtractor) in their path. + +Examples: +- FSTATE_RD_BITS = 1: fstate_rd == 0 => 0/2 full + fstate_rd == 1 => 1/2 full (half full) + +- FSTATE_RD_BITS = 2: fstate_rd == 0 => 0/4 full + fstate_rd == 1 => 1/4 full + fstate_rd == 2 => 2/4 full + fstate_rd == 3 => 3/4 full + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/fifo/fifo_cc_got_tempput.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 80-109 + +Source file: `fifo/fifo_cc_got_tempput.vhdl `_ + + + diff --git a/docs/PoC/fifo/fifo_dc_got_sm.rst b/docs/PoC/fifo/fifo_dc_got_sm.rst new file mode 100644 index 00000000..573c8d58 --- /dev/null +++ b/docs/PoC/fifo/fifo_dc_got_sm.rst @@ -0,0 +1,43 @@ + +fifo_dc_got_sm +############## + +Dependent clocks meens, that one clock must be a multiple of the other one. +And your synthesis tool must check for setup- and hold-time violations. + +This implementation uses a small register-file for storing data. Your +synthesis tool might infer memory. This memory must +- either support asynchronous reads (as an register-file) +- or a synchronous read with mixed-port read-during-write (write-first). + +First-word-fall-through (FWFT) mode is implemented, so data can be read out +as soon as 'valid' goes high. After the data has been captured, then the +signal 'got' must be asserted. + +The advantage of the register file is, that data is available at the read +port after the rising edge of the write clock it has been written to. + +Because implementing register-files onto a FPGA might require a lot of LUT +logic, use this implementation only for small FIFOs. + +Another disadvantage is, that the signals 'full' and +'valid' are combinatorial and include an adress comparator in their path. + +The specified depth (MIN_DEPTH) is rounded up to the next suitable value. + +Synchronous reset is used. Both resets must overlap. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/fifo/fifo_dc_got_sm.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 62-85 + +Source file: `fifo/fifo_dc_got_sm.vhdl `_ + + + diff --git a/docs/PoC/fifo/fifo_glue.rst b/docs/PoC/fifo/fifo_glue.rst new file mode 100644 index 00000000..5ec75bcb --- /dev/null +++ b/docs/PoC/fifo/fifo_glue.rst @@ -0,0 +1,22 @@ + +fifo_glue +######### + +Its primary use is the decoupling of enable domains in a processing +pipeline. Data storage is limited to two words only so as to allow both +the ``ful`` and the ``vld`` indicators to be driven by registers. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/fifo/fifo_glue.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 36-55 + +Source file: `fifo/fifo_glue.vhdl `_ + + + diff --git a/docs/PoC/fifo/fifo_ic_assembly.rst b/docs/PoC/fifo/fifo_ic_assembly.rst new file mode 100644 index 00000000..52c30ac4 --- /dev/null +++ b/docs/PoC/fifo/fifo_ic_assembly.rst @@ -0,0 +1,31 @@ + +fifo_ic_assembly +################ + +This module assembles a FIFO stream from data blocks that may arrive +slightly out of order. The arriving data is ordered according to their +address. The streamed output starts with the data word written to +address zero (0) and may proceed all the way to just before the first yet +missing data. The association of data with addresses is used on the input +side for the sole purpose of reconstructing the correct order of the data. +It is assumed to wrap so as to allow an infinite input sequence. Addresses +are not actively exposed to the purely stream-based FIFO output. + +The implemented functionality enables the reconstruction of streams that +are tunnelled across address-based transports that are allowed to reorder +the transmission of data blocks. This applies to many DMA implementations. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/fifo/fifo_ic_assembly.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 45-78 + +Source file: `fifo/fifo_ic_assembly.vhdl `_ + + + diff --git a/docs/PoC/fifo/fifo_ic_got.rst b/docs/PoC/fifo/fifo_ic_got.rst new file mode 100644 index 00000000..493f7940 --- /dev/null +++ b/docs/PoC/fifo/fifo_ic_got.rst @@ -0,0 +1,55 @@ + +fifo_ic_got +########### + +Independent clocks meens that read and write clock are unrelated. + +This implementation uses dedicated block RAM for storing data. + +First-word-fall-through (FWFT) mode is implemented, so data can be read out +as soon as ``valid`` goes high. After the data has been captured, then the +signal ``got`` must be asserted. + +Synchronous reset is used. Both resets may overlap. + +``DATA_REG`` (=true) is a hint, that distributed memory or registers should be +used as data storage. The actual memory type depends on the device +architecture. See implementation for details. + +``*STATE_*_BITS`` defines the granularity of the fill state indicator +``*state_*``. ``fstate_rd`` is associated with the read clock domain and outputs +the guaranteed number of words available in the FIFO. ``estate_wr`` is +associated with the write clock domain and outputs the number of words that +is guaranteed to be accepted by the FIFO without a capacity overflow. Note +that both these indicators cannot replace the ``full`` or ``valid`` outputs as +they may be implemented as giving pessimistic bounds that are minimally off +the true fill state. + +If a fill state is not of interest, set *STATE_*_BITS = 0. + +``fstate_rd`` and ``estate_wr`` are combinatorial outputs and include an address +comparator (subtractor) in their path. + +Examples: +- FSTATE_RD_BITS = 1: fstate_rd == 0 => 0/2 full + fstate_rd == 1 => 1/2 full (half full) + +- FSTATE_RD_BITS = 2: fstate_rd == 0 => 0/4 full + fstate_rd == 1 => 1/4 full + fstate_rd == 2 => 2/4 full + fstate_rd == 3 => 3/4 full + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/fifo/fifo_ic_got.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 77-103 + +Source file: `fifo/fifo_ic_got.vhdl `_ + + + diff --git a/docs/PoC/fifo/fifo_shift.rst b/docs/PoC/fifo/fifo_shift.rst new file mode 100644 index 00000000..eafbe1cb --- /dev/null +++ b/docs/PoC/fifo/fifo_shift.rst @@ -0,0 +1,26 @@ + +fifo_shift +########## + +This FIFO implementation is based on an internal shift register. This is +especially useful for smaller FIFO sizes, which can be implemented in LUT +storage on some devices (e.g. Xilinx' SRLs). Only a single read pointer is +maintained, which determines the number of valid entries within the +underlying shift register. + +The specified depth (``MIN_DEPTH``) is rounded up to the next suitable value. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/fifo/fifo_shift.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 44-64 + +Source file: `fifo/fifo_shift.vhdl `_ + + + diff --git a/docs/PoC/fifo/index.rst b/docs/PoC/fifo/index.rst new file mode 100644 index 00000000..b05de404 --- /dev/null +++ b/docs/PoC/fifo/index.rst @@ -0,0 +1,50 @@ + +fifo +==== + +The namespace `PoC.fifo` offers different :abbr:`FIFO (first-in, first-out)` implementations. + +**Package** + +The package :doc:`PoC.fifo ` holds all component declarations for this namespace. + +**Entities** + +PoC offers FIFOs with a `got`-interface. This means, the current read-pointer value +is available on the output. Asserting the `got`-input, acknoledge the processing of +the current output signals and moves the read-pointer to the next value, if available. + +All FIFOs implement a bidirectional flow control (`put`/`full` and `valid`/`got`). +Each FIFO also offers a EmptyState (write-side) and FullState (read-side) to indicate +the current fill-state. + +The prefixes `cc_` (common clock), `dc_` (dependent clock) and `ic_` (independent +clock) refer to the write- and read-side clock relationship. + + * :doc:`PoC.fifo.cc_got ` implements a regular FIFO (one common clock, + got-interface) + * :doc:`PoC.fifo.cc_got_tempgot ` implements a regular FIFO (one common + clock, got-interface), extended by a transactional `tempgot`-interface (read-side). + * :doc:`PoC.fifo.cc_got_tempput ` implements a regular FIFO (one common + clock, got-interface), extended by a transactional `tempput`-interface (write-side). + * :doc:`PoC.fifo.dc_got ` implements a cross-clock FIFO (two related clocks, + got-interface) + * :doc:`PoC.fifo.ic_got ` implements a cross-clock FIFO (two independent clocks, + got-interface) + * :doc:`PoC.fifo.glue ` implements a two-stage FIFO (one common clock, + got-interface) + * :doc:`PoC.fifo.shift ` implements a regular FIFO (one common clock, + got-interface, optimized for FPGAs with shifter primitives) + +.. toctree:: + :hidden: + + fifo.pkg + + fifo_cc_got + fifo_cc_got_tempgot + fifo_cc_got_tempput + fifo_glue + fifo_ic_assembly + fifo_ic_got + fifo_shift diff --git a/docs/PoC/index.rst b/docs/PoC/index.rst new file mode 100644 index 00000000..ea416c0b --- /dev/null +++ b/docs/PoC/index.rst @@ -0,0 +1,36 @@ + +IP Core Documentations +###################### + +Namespace for Packages: + +.. toctree:: + + common/index + sim/index + +Namespaces for Entities: + +.. toctree:: + + alt/index + arith/index + bus/index + cache/index + comm/index + dstruct/index + fifo/index + io/index + mem/index + misc/index + net/index + +.. only:: PoCInternal + + .. toctree:: + sata/index + +.. toctree:: + + sort/index + xil/index diff --git a/docs/PoC/io/ddrio/ddrio_in.rst b/docs/PoC/io/ddrio/ddrio_in.rst new file mode 100644 index 00000000..32f3b50b --- /dev/null +++ b/docs/PoC/io/ddrio/ddrio_in.rst @@ -0,0 +1,42 @@ + +ddrio_in +######## + +Instantiates chip-specific :abbr:`DDR (Double Data Rate)` input registers. + +Both data ``DataIn_high/low`` are synchronously outputted to the on-chip logic +with the rising edge of ``Clock``. ``DataIn_high`` is the value at the ``Pad`` +sampled with the same rising edge. ``DataIn_low`` is the value sampled with +the falling edge directly before this rising edge. Thus sampling starts with +the falling edge of the clock as depicted in the following waveform. + +.. code-block:: none + + __ ____ ____ __ + Clock |____| |____| |____| + Pad < 0 >< 1 >< 2 >< 3 >< 4 >< 5 > + DataIn_low ... >< 0 >< 2 >< + DataIn_high ... >< 1 >< 3 >< + + < i > is the value of the i-th data bit on the line. + +After power-up, the output ports ``DataIn_high`` and ``DataIn_low`` both equal +INIT_VALUE. + +``Pad`` must be connected to a PAD because FPGAs only have these registers in +IOBs. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/ddrio/ddrio_in.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 64-76 + +Source file: `io/ddrio/ddrio_in.vhdl `_ + + + diff --git a/docs/PoC/io/ddrio/ddrio_inout.rst b/docs/PoC/io/ddrio/ddrio_inout.rst new file mode 100644 index 00000000..95fd3698 --- /dev/null +++ b/docs/PoC/io/ddrio/ddrio_inout.rst @@ -0,0 +1,48 @@ + +ddrio_inout +########### + +Instantiates chip-specific :abbr:`DDR (Double Data Rate)` input and output +registers. + +Both data ``DataOut_high/low`` as well as ``OutputEnable`` are sampled with +the ``rising_edge(Clock)`` from the on-chip logic. ``DataOut_high`` is brought +out with this rising edge. ``DataOut_low`` is brought out with the falling +edge. + +``OutputEnable`` (Tri-State) is high-active. It is automatically inverted if +necessary. Output is disabled after power-up. + +Both data ``DataIn_high/low`` are synchronously outputted to the on-chip logic +with the rising edge of ``Clock``. ``DataIn_high`` is the value at the ``Pad`` +sampled with the same rising edge. ``DataIn_low`` is the value sampled with +the falling edge directly before this rising edge. Thus sampling starts with +the falling edge of the clock as depicted in the following waveform. + +.. code-block:: none + + __ ____ ____ __ + Clock |____| |____| |____| + Pad < 0 >< 1 >< 2 >< 3 >< 4 >< 5 > + DataIn_low ... >< 0 >< 2 >< + DataIn_high ... >< 1 >< 3 >< + + < i > is the value of the i-th data bit on the line. + +``Pad`` must be connected to a PAD because FPGAs only have these registers in +IOBs. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/ddrio/ddrio_inout.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 70-88 + +Source file: `io/ddrio/ddrio_inout.vhdl `_ + + + diff --git a/docs/PoC/io/ddrio/ddrio_out.rst b/docs/PoC/io/ddrio/ddrio_out.rst new file mode 100644 index 00000000..43c9fab6 --- /dev/null +++ b/docs/PoC/io/ddrio/ddrio_out.rst @@ -0,0 +1,35 @@ + +ddrio_out +######### + +Instantiates chip-specific :abbr:`DDR (Double Data Rate)` output registers. + +Both data ``DataOut_high/low`` as well as ``OutputEnable`` are sampled with +the ``rising_edge(Clock)`` from the on-chip logic. ``DataOut_high`` is brought +out with this rising edge. ``DataOut_low`` is brought out with the falling +edge. + +``OutputEnable`` (Tri-State) is high-active. It is automatically inverted if +necessary. If an output enable is not required, you may save some logic by +setting ``NO_OUTPUT_ENABLE = true``. + +If ``NO_OUTPUT_ENABLE = false`` then output is disabled after power-up. +If ``NO_OUTPUT_ENABLE = true`` then output after power-up equals ``INIT_VALUE``. + +``Pad`` must be connected to a PAD because FPGAs only have these registers in +IOBs. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/ddrio/ddrio_out.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 57-71 + +Source file: `io/ddrio/ddrio_out.vhdl `_ + + + diff --git a/docs/PoC/io/ddrio/index.rst b/docs/PoC/io/ddrio/index.rst new file mode 100644 index 00000000..0be35a42 --- /dev/null +++ b/docs/PoC/io/ddrio/index.rst @@ -0,0 +1,19 @@ + +ddrio +===== + +These are :abbr:`DDR-I/O (Double Data Rate - Input/Output)` entities.... + +**Entities** + + * :doc:`PoC.io.ddrio.in ` + * :doc:`PoC.io.ddrio.inout ` + * :doc:`PoC.io.ddrio.out ` + + +.. toctree:: + :hidden: + + ddrio_in + ddrio_inout + ddrio_out diff --git a/docs/PoC/io/iic/iic_BusController.rst b/docs/PoC/io/iic/iic_BusController.rst new file mode 100644 index 00000000..139e99e1 --- /dev/null +++ b/docs/PoC/io/iic/iic_BusController.rst @@ -0,0 +1,23 @@ + +iic_BusController +################# + +The I2C BusController transmitts bits over the I2C bus (SerialClock - SCL, +SerialData - SDA) and also receives them. To send/receive words over the +I2C bus, use the I2C Controller, which utilizes this controller. This +controller is compatible to the System Management Bus (SMBus). + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/iic/iic_BusController.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 47-70 + +Source file: `io/iic/iic_BusController.vhdl `_ + + + diff --git a/docs/PoC/io/iic/iic_Controller.rst b/docs/PoC/io/iic/iic_Controller.rst new file mode 100644 index 00000000..25ced5c3 --- /dev/null +++ b/docs/PoC/io/iic/iic_Controller.rst @@ -0,0 +1,23 @@ + +iic_Controller +############## + +The I2C Controller transmitts words over the I2C bus (SerialClock - SCL, +SerialData - SDA) and also receives them. This controller utilizes the +I2C BusController to send/receive bits over the I2C bus. This controller +is compatible to the System Management Bus (SMBus). + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/iic/iic_Controller.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 47-87 + +Source file: `io/iic/iic_Controller.vhdl `_ + + + diff --git a/docs/PoC/io/iic/iic_Controller_SFF8431.rst b/docs/PoC/io/iic/iic_Controller_SFF8431.rst new file mode 100644 index 00000000..87280961 --- /dev/null +++ b/docs/PoC/io/iic/iic_Controller_SFF8431.rst @@ -0,0 +1,18 @@ + +IICController_SFF8431 +##################### + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/iic/iic_Controller_SFF8431.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 15-49 + +Source file: `io/iic/iic_Controller_SFF8431.vhdl `_ + + + diff --git a/docs/PoC/io/iic/iic_Switch_PCA9548A.rst b/docs/PoC/io/iic/iic_Switch_PCA9548A.rst new file mode 100644 index 00000000..b4da4a8b --- /dev/null +++ b/docs/PoC/io/iic/iic_Switch_PCA9548A.rst @@ -0,0 +1,20 @@ + +iic_Switch_PCA9548A +################### + +.. TODO:: No documentation available. TODO + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/iic/iic_Switch_PCA9548A.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-90 + +Source file: `io/iic/iic_Switch_PCA9548A.vhdl `_ + + + diff --git a/docs/PoC/io/iic/index.rst b/docs/PoC/io/iic/index.rst new file mode 100644 index 00000000..04460025 --- /dev/null +++ b/docs/PoC/io/iic/index.rst @@ -0,0 +1,11 @@ + +iic +===== + +These are I2C entities.... + +.. toctree:: + + iic_BusController + iic_Controller + iic_Switch_PCA9548A diff --git a/docs/PoC/io/index.rst b/docs/PoC/io/index.rst new file mode 100644 index 00000000..65c21ad4 --- /dev/null +++ b/docs/PoC/io/index.rst @@ -0,0 +1,60 @@ + +io +== + +The namespace ``PoC.io`` offers different general purpose I/O (GPIO) implementations, +as well as low-speed bus protocol controllers. + +**Sub-namespaces** + + * :doc:`PoC.io.ddrio ` - Double-Data-Rate (DDR) input/output abstraction layer. + * :doc:`PoC.io.iic ` - I²C bus controllers + * :doc:`PoC.io.jtag ` - JTAG implementations + * :doc:`PoC.io.lcd ` - LC-Display bus controllers + * :doc:`PoC.io.mdio ` - Management Data I/O (MDIO) controllers for Ethernet PHYs + * :doc:`PoC.io.ow ` - OneWire / iButton bus controllers + * :doc:`PoC.io.ps2 ` - Periphery bus of the Personal System/2 (PS/2) + * :doc:`PoC.io.uart ` - Universal Asynchronous Receiver Transmitter (UART) controllers + * :doc:`PoC.io.vga ` - VGA, DVI, HDMI controllers + +**Package** + +The package :doc:`PoC.io ` holds all enum, function and component declarations for this namespace. + +**Entities** + + * :doc:`PoC.io.Debounce ` + * :doc:`PoC.io.7SegmentMux_BCD ` + * :doc:`PoC.io.7SegmentMux_HEX ` + * :doc:`PoC.io.FanControl ` + * :doc:`PoC.io.FrequencyCounter ` + * :doc:`PoC.io.GlitchFilter ` + * :doc:`PoC.io.PulseWidthModulation ` + * :doc:`PoC.io.TimingCounter ` + +.. toctree:: + :hidden: + + ddrio/index + iic/index + jtag/index + lcd/index + mdio/index + ow/index + pio/index + pmod/index + ps2/index + uart/index + vga/index + + io.pkg + + io_7SegmentMux_BCD + io_7SegmentMux_HEX + io_Debounce + io_FanControl + io_FrequencyCounter + io_GlitchFilter + io_KeyPadScanner + io_PulseWidthModulation + io_TimingCounter diff --git a/docs/PoC/io/io.pkg.rst b/docs/PoC/io/io.pkg.rst new file mode 100644 index 00000000..00a8c8a5 --- /dev/null +++ b/docs/PoC/io/io.pkg.rst @@ -0,0 +1,7 @@ + +Package +======== + +This package holds all component declarations for this namespace. + +Source file: `io/io.pkg.vhdl `_ diff --git a/docs/PoC/io/io_7SegmentMux_BCD.rst b/docs/PoC/io/io_7SegmentMux_BCD.rst new file mode 100644 index 00000000..be066af6 --- /dev/null +++ b/docs/PoC/io/io_7SegmentMux_BCD.rst @@ -0,0 +1,23 @@ + +io_7SegmentMux_BCD +################## + +This module is a 7 segment display controller that uses time multiplexing +to control a common anode for each digit in the display. The shown characters +are BCD encoded. A dot per digit is optional. A minus sign for negative +numbers is supported. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/io/io_7SegmentMux_BCD.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 45-60 + +Source file: `io/io_7SegmentMux_BCD.vhdl `_ + + + diff --git a/docs/PoC/io/io_7SegmentMux_HEX.rst b/docs/PoC/io/io_7SegmentMux_HEX.rst new file mode 100644 index 00000000..4926b941 --- /dev/null +++ b/docs/PoC/io/io_7SegmentMux_HEX.rst @@ -0,0 +1,22 @@ + +io_7SegmentMux_HEX +################## + +This module is a 7 segment display controller that uses time multiplexing +to control a common anode for each digit in the display. The shown characters +are HEX encoded. A dot per digit is optional. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/io/io_7SegmentMux_HEX.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 45-60 + +Source file: `io/io_7SegmentMux_HEX.vhdl `_ + + + diff --git a/docs/PoC/io/io_Debounce.rst b/docs/PoC/io/io_Debounce.rst new file mode 100644 index 00000000..4e0c4b86 --- /dev/null +++ b/docs/PoC/io/io_Debounce.rst @@ -0,0 +1,31 @@ + +io_Debounce +########### + +This module debounces several input pins preventing input changes +following a previous one within the configured ``BOUNCE_TIME`` to pass. +Internally, the forwarded state is locked for, at least, this ``BOUNCE_TIME``. +As the backing timer is restarted on every input fluctuation, the next +passing input update must have seen a stabilized input. + +The parameter ``COMMON_LOCK`` uses a single internal timer for all processed +inputs. Thus, all inputs must stabilize before any one may pass changed. +This option is usually fully acceptable for user inputs such as push buttons. + +The parameter ``ADD_INPUT_SYNCHRONIZERS`` triggers the optional instantiation +of a two-FF input synchronizer on each input bit. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/io/io_Debounce.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 52-67 + +Source file: `io/io_Debounce.vhdl `_ + + + diff --git a/docs/PoC/io/io_FanControl.rst b/docs/PoC/io/io_FanControl.rst new file mode 100644 index 00000000..f91d7bfa --- /dev/null +++ b/docs/PoC/io/io_FanControl.rst @@ -0,0 +1,39 @@ + +io_FanControl +############# + +.. code-block:: none + + This module generates a PWM signal for a 3-pin (transistor controlled) or + 4-pin fan header. The FPGAs temperature is read from device specific system + monitors (normal, user temperature, over temperature). + + For example the Xilinx System Monitors are configured as follows: + + | /-----\ + Temp_ov on=80 | - - - - - - /-------/ \ + | / | \ + Temp_ov off=60 | - - - - - / - - - - | - - - - \----\ + | / | \ + | / | | \ + Temp_us on=35 | - /---/ | | \ + Temp_us off=30 | - / - -|- - - - - - | - - - - - - -|- \------\ + | / | | | \ + ----------------|--------|------------|--------------|----------|--------- + pwm = | min | medium | max | medium | min + + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/io/io_FanControl.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 63-81 + +Source file: `io/io_FanControl.vhdl `_ + + + diff --git a/docs/PoC/io/io_FrequencyCounter.rst b/docs/PoC/io/io_FrequencyCounter.rst new file mode 100644 index 00000000..80e9bc94 --- /dev/null +++ b/docs/PoC/io/io_FrequencyCounter.rst @@ -0,0 +1,20 @@ + +io_FrequencyCounter +################### + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/io/io_FrequencyCounter.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 40-52 + +Source file: `io/io_FrequencyCounter.vhdl `_ + + + diff --git a/docs/PoC/io/io_GlitchFilter.rst b/docs/PoC/io/io_GlitchFilter.rst new file mode 100644 index 00000000..48c4f1bf --- /dev/null +++ b/docs/PoC/io/io_GlitchFilter.rst @@ -0,0 +1,21 @@ + +io_GlitchFilter +############### + +This module filters glitches on a wire. The high and low spike suppression +cycle counts can be configured. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/io/io_GlitchFilter.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 41-51 + +Source file: `io/io_GlitchFilter.vhdl `_ + + + diff --git a/docs/PoC/io/io_KeyPadScanner.rst b/docs/PoC/io/io_KeyPadScanner.rst new file mode 100644 index 00000000..b1b06f23 --- /dev/null +++ b/docs/PoC/io/io_KeyPadScanner.rst @@ -0,0 +1,24 @@ + +io_KeyPadScanner +################ + +This module drives a one-hot encoded column vector to read back a rows +vector. By scanning column-by-column it's possible to extract the current +button state of the whole keypad. The scanner uses high-active logic. The +keypad size and scan frequency can be configured. The outputed signal +matrix is not debounced. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/io/io_KeyPadScanner.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 46-63 + +Source file: `io/io_KeyPadScanner.vhdl `_ + + + diff --git a/docs/PoC/io/io_PulseWidthModulation.rst b/docs/PoC/io/io_PulseWidthModulation.rst new file mode 100644 index 00000000..f130f1dc --- /dev/null +++ b/docs/PoC/io/io_PulseWidthModulation.rst @@ -0,0 +1,21 @@ + +io_PulseWidthModulation +####################### + +This module generates a pulse width modulated signal, that can be configured +in frequency (``PWM_FREQ``) and modulation granularity (``PWM_RESOLUTION``). + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/io/io_PulseWidthModulation.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 41-53 + +Source file: `io/io_PulseWidthModulation.vhdl `_ + + + diff --git a/docs/PoC/io/io_TimingCounter.rst b/docs/PoC/io/io_TimingCounter.rst new file mode 100644 index 00000000..02862613 --- /dev/null +++ b/docs/PoC/io/io_TimingCounter.rst @@ -0,0 +1,23 @@ + +io_TimingCounter +################ + +This down-counter can be configured with a ``TIMING_TABLE`` (a ROM), from which +the initial counter value is loaded. The table index can be selected by +``Slot``. ``Timeout`` is a registered output. Up to 16 values fit into one ROM +consisting of ``log2ceilnz(imax(TIMING_TABLE)) + 1`` 6-input LUTs. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/io/io_TimingCounter.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 43-54 + +Source file: `io/io_TimingCounter.vhdl `_ + + + diff --git a/docs/PoC/io/jtag/index.rst b/docs/PoC/io/jtag/index.rst new file mode 100644 index 00000000..0ed83f3e --- /dev/null +++ b/docs/PoC/io/jtag/index.rst @@ -0,0 +1,8 @@ + +jtag +==== + +These are JTAG entities.... + +.. toctree:: + diff --git a/docs/PoC/io/lcd/BCDDigit.rst b/docs/PoC/io/lcd/BCDDigit.rst new file mode 100644 index 00000000..ac5e9eea --- /dev/null +++ b/docs/PoC/io/lcd/BCDDigit.rst @@ -0,0 +1,18 @@ + +BCDDigit +######## + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/lcd/BCDDigit.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 10-22 + +Source file: `io/lcd/BCDDigit.vhdl `_ + + + diff --git a/docs/PoC/io/lcd/index.rst b/docs/PoC/io/lcd/index.rst new file mode 100644 index 00000000..144729aa --- /dev/null +++ b/docs/PoC/io/lcd/index.rst @@ -0,0 +1,12 @@ + +lcd +=== + +These are LCD entities.... + +.. toctree:: + + lcd_LCDBuffer + lcd_LCDBusController + lcd_LCDController_KS0066U + lcd_LCDSynchronizer diff --git a/docs/PoC/io/lcd/lcd_LCDBuffer.rst b/docs/PoC/io/lcd/lcd_LCDBuffer.rst new file mode 100644 index 00000000..da24ae53 --- /dev/null +++ b/docs/PoC/io/lcd/lcd_LCDBuffer.rst @@ -0,0 +1,20 @@ + +lcd_LCDBuffer +############# + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/lcd/lcd_LCDBuffer.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-58 + +Source file: `io/lcd/lcd_LCDBuffer.vhdl `_ + + + diff --git a/docs/PoC/io/lcd/lcd_LCDBusController.rst b/docs/PoC/io/lcd/lcd_LCDBusController.rst new file mode 100644 index 00000000..5512701f --- /dev/null +++ b/docs/PoC/io/lcd/lcd_LCDBusController.rst @@ -0,0 +1,20 @@ + +lcd_LCDBusController +#################### + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/lcd/lcd_LCDBusController.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 43-67 + +Source file: `io/lcd/lcd_LCDBusController.vhdl `_ + + + diff --git a/docs/PoC/io/lcd/lcd_LCDController_KS0066U.rst b/docs/PoC/io/lcd/lcd_LCDController_KS0066U.rst new file mode 100644 index 00000000..9ca3f647 --- /dev/null +++ b/docs/PoC/io/lcd/lcd_LCDController_KS0066U.rst @@ -0,0 +1,20 @@ + +lcd_LCDController_KS0066U +######################### + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/lcd/lcd_LCDController_KS0066U.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-64 + +Source file: `io/lcd/lcd_LCDController_KS0066U.vhdl `_ + + + diff --git a/docs/PoC/io/lcd/lcd_LCDSynchronizer.rst b/docs/PoC/io/lcd/lcd_LCDSynchronizer.rst new file mode 100644 index 00000000..1ad67e80 --- /dev/null +++ b/docs/PoC/io/lcd/lcd_LCDSynchronizer.rst @@ -0,0 +1,20 @@ + +lcd_LCDSynchronizer +################### + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/lcd/lcd_LCDSynchronizer.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-64 + +Source file: `io/lcd/lcd_LCDSynchronizer.vhdl `_ + + + diff --git a/docs/PoC/io/lcd/lcd_dotmatrix.rst b/docs/PoC/io/lcd/lcd_dotmatrix.rst new file mode 100644 index 00000000..fe397947 --- /dev/null +++ b/docs/PoC/io/lcd/lcd_dotmatrix.rst @@ -0,0 +1,20 @@ + +lcd_dotmatrix +############# + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/lcd/lcd_dotmatrix.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 36-67 + +Source file: `io/lcd/lcd_dotmatrix.vhdl `_ + + + diff --git a/docs/PoC/io/mdio/index.rst b/docs/PoC/io/mdio/index.rst new file mode 100644 index 00000000..67b40b87 --- /dev/null +++ b/docs/PoC/io/mdio/index.rst @@ -0,0 +1,11 @@ + +mdio +==== + +These are MDIO entities.... + +.. toctree:: + + mdio_BusController + mdio_Controller + mdio_IIC_Adapter diff --git a/docs/PoC/io/mdio/mdio_BusController.rst b/docs/PoC/io/mdio/mdio_BusController.rst new file mode 100644 index 00000000..313d17f5 --- /dev/null +++ b/docs/PoC/io/mdio/mdio_BusController.rst @@ -0,0 +1,9 @@ + +mdio_BusController +^^^^^^^^^^^^^^^^^^ + +Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. +At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor +sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et +accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet + diff --git a/docs/PoC/io/mdio/mdio_Controller.rst b/docs/PoC/io/mdio/mdio_Controller.rst new file mode 100644 index 00000000..f06789d2 --- /dev/null +++ b/docs/PoC/io/mdio/mdio_Controller.rst @@ -0,0 +1,20 @@ + +mdio_Controller +############### + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/mdio/mdio_Controller.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 44-73 + +Source file: `io/mdio/mdio_Controller.vhdl `_ + + + diff --git a/docs/PoC/io/mdio/mdio_IIC_Adapter.rst b/docs/PoC/io/mdio/mdio_IIC_Adapter.rst new file mode 100644 index 00000000..65373fe9 --- /dev/null +++ b/docs/PoC/io/mdio/mdio_IIC_Adapter.rst @@ -0,0 +1,20 @@ + +mdio_IIC_Adapter +################ + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/mdio/mdio_IIC_Adapter.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 44-80 + +Source file: `io/mdio/mdio_IIC_Adapter.vhdl `_ + + + diff --git a/docs/PoC/io/ow/index.rst b/docs/PoC/io/ow/index.rst new file mode 100644 index 00000000..436fb3f4 --- /dev/null +++ b/docs/PoC/io/ow/index.rst @@ -0,0 +1,10 @@ + +ow +== + +These are OneWire entities.... + +.. toctree:: + + ow_BusController + ow_Controller diff --git a/docs/PoC/io/ow/ow_BusController.rst b/docs/PoC/io/ow/ow_BusController.rst new file mode 100644 index 00000000..cf864542 --- /dev/null +++ b/docs/PoC/io/ow/ow_BusController.rst @@ -0,0 +1,9 @@ + +ow_BusController +^^^^^^^^^^^^^^^^ + +Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. +At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor +sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et +accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet + diff --git a/docs/PoC/io/ow/ow_Controller.rst b/docs/PoC/io/ow/ow_Controller.rst new file mode 100644 index 00000000..02c66a47 --- /dev/null +++ b/docs/PoC/io/ow/ow_Controller.rst @@ -0,0 +1,9 @@ + +ow_Controller +^^^^^^^^^^^^^ + +Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. +At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor +sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et +accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet + diff --git a/docs/PoC/io/pio/index.rst b/docs/PoC/io/pio/index.rst new file mode 100644 index 00000000..69dd0a40 --- /dev/null +++ b/docs/PoC/io/pio/index.rst @@ -0,0 +1,12 @@ + +pio +### + +These are Pmod entities.... + +.. toctree:: + + pio_in + pio_out + pio_fifo_in + pio_fifo_out diff --git a/docs/PoC/io/pio/pio_fifo_in.rst b/docs/PoC/io/pio/pio_fifo_in.rst new file mode 100644 index 00000000..f09a6af0 --- /dev/null +++ b/docs/PoC/io/pio/pio_fifo_in.rst @@ -0,0 +1,19 @@ + +pio_fifo_in +########### + + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/pio/pio_fifo_in.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 38-55 + +Source file: `io/pio/pio_fifo_in.vhdl `_ + + + diff --git a/docs/PoC/io/pio/pio_fifo_out.rst b/docs/PoC/io/pio/pio_fifo_out.rst new file mode 100644 index 00000000..49fffc17 --- /dev/null +++ b/docs/PoC/io/pio/pio_fifo_out.rst @@ -0,0 +1,19 @@ + +pio_fifo_out +############ + + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/pio/pio_fifo_out.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 38-55 + +Source file: `io/pio/pio_fifo_out.vhdl `_ + + + diff --git a/docs/PoC/io/pio/pio_in.rst b/docs/PoC/io/pio/pio_in.rst new file mode 100644 index 00000000..e7eccec2 --- /dev/null +++ b/docs/PoC/io/pio/pio_in.rst @@ -0,0 +1,19 @@ + +pio_in +###### + + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/pio/pio_in.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 40-55 + +Source file: `io/pio/pio_in.vhdl `_ + + + diff --git a/docs/PoC/io/pio/pio_out.rst b/docs/PoC/io/pio/pio_out.rst new file mode 100644 index 00000000..2e36dd20 --- /dev/null +++ b/docs/PoC/io/pio/pio_out.rst @@ -0,0 +1,19 @@ + +pio_out +####### + + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/pio/pio_out.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 40-55 + +Source file: `io/pio/pio_out.vhdl `_ + + + diff --git a/docs/PoC/io/pmod/index.rst b/docs/PoC/io/pmod/index.rst new file mode 100644 index 00000000..adfaf17a --- /dev/null +++ b/docs/PoC/io/pmod/index.rst @@ -0,0 +1,19 @@ + +pmod +#### + +These are Pmod entities.... + +**Entities** + + * :doc:`PoC.io.pmod.KYPD ` + * :doc:`PoC.io.pmod.SSD ` + * :doc:`PoC.io.pmod.USBUART ` + + +.. toctree:: + :hidden: + + pmod_KYPD + pmod_SSD + pmod_USBUART diff --git a/docs/PoC/io/pmod/pmod_KYPD.rst b/docs/PoC/io/pmod/pmod_KYPD.rst new file mode 100644 index 00000000..b160a86b --- /dev/null +++ b/docs/PoC/io/pmod/pmod_KYPD.rst @@ -0,0 +1,25 @@ + +pmod_KYPD +######### + +This module drives a 4-bit one-cold encoded column vector to read back a +4-bit rows vector. By scanning column-by-column it's possible to extract +the current button state of the whole keypad. This wrapper converts the +high-active signals from :doc:`PoC.io.KeypadScanner <../io_KeyPadScanner>` +to low-active signals for the pmod. An additional debounce circuit filters +the button signals. The scan frequency and bounce time can be configured. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/pmod/pmod_KYPD.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 46-61 + +Source file: `io/pmod/pmod_KYPD.vhdl `_ + + + diff --git a/docs/PoC/io/pmod/pmod_SSD.rst b/docs/PoC/io/pmod/pmod_SSD.rst new file mode 100644 index 00000000..113c74ef --- /dev/null +++ b/docs/PoC/io/pmod/pmod_SSD.rst @@ -0,0 +1,33 @@ + +pmod_SSD +######## + +This module drives a dual-digit 7-segment display (Pmod_SSD). The module +expects two binary encoded 4-bit ``Digit`` signals and drives a 2x6 bit +Pmod connector (7 anode bits, 1 cathode bit). + +-- code-block:. none + + Segment Pos./ Index + AAA | 000 + F B | 5 1 + F B | 5 1 + GGG | 666 + E C | 4 2 + E C | 4 2 + DDD DOT | 333 7 + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/pmod/pmod_SSD.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 56-69 + +Source file: `io/pmod/pmod_SSD.vhdl `_ + + + diff --git a/docs/PoC/io/pmod/pmod_USBUART.rst b/docs/PoC/io/pmod/pmod_USBUART.rst new file mode 100644 index 00000000..a5a1c9b4 --- /dev/null +++ b/docs/PoC/io/pmod/pmod_USBUART.rst @@ -0,0 +1,23 @@ + +pmod_USBUART +############ + +This module abstracts a FTDI FT232R USB-UART bridge by instantiating a +:doc:`PoC.io.uart.fifo <../uart/uart_fifo>`. The FT232R supports up to +3 MBaud. A synchronous FIFO interface with a 32 words buffer is provided. +Hardware flow control (RTS_CTS) is enabled. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/pmod/pmod_USBUART.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 43-65 + +Source file: `io/pmod/pmod_USBUART.vhdl `_ + + + diff --git a/docs/PoC/io/ps2/index.rst b/docs/PoC/io/ps2/index.rst new file mode 100644 index 00000000..3638c2f7 --- /dev/null +++ b/docs/PoC/io/ps2/index.rst @@ -0,0 +1,8 @@ + +ps2 +=== + +These are PS/2 entities.... + +.. toctree:: + diff --git a/docs/PoC/io/uart/index.rst b/docs/PoC/io/uart/index.rst new file mode 100644 index 00000000..f356581c --- /dev/null +++ b/docs/PoC/io/uart/index.rst @@ -0,0 +1,21 @@ + +uart +==== + +These are :abbr:`UART (Universal Asynchronous Receiver Transmitter)` entities.... + +**Entities** + + * :doc:`PoC.io.uart.bclk ` + * :doc:`PoC.io.uart.rx ` + * :doc:`PoC.io.uart.tx ` + * :doc:`PoC.io.uart.fifo ` + + +.. toctree:: + :hidden: + + uart_bclk + uart_rx + uart_tx + uart_fifo diff --git a/docs/PoC/io/uart/uart_bclk.rst b/docs/PoC/io/uart/uart_bclk.rst new file mode 100644 index 00000000..b6fc0837 --- /dev/null +++ b/docs/PoC/io/uart/uart_bclk.rst @@ -0,0 +1,26 @@ + +uart_bclk +######### + +.. TODO:: No documentation available. + +old comments: + :abbr:`UART (Universal Asynchronous Receiver Transmitter)` BAUD rate generator + bclk_r = bit clock is rising + bclk_x8_r = bit clock times 8 is rising + + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/uart/uart_bclk.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 50-61 + +Source file: `io/uart/uart_bclk.vhdl `_ + + + diff --git a/docs/PoC/io/uart/uart_fifo.rst b/docs/PoC/io/uart/uart_fifo.rst new file mode 100644 index 00000000..283e63bd --- /dev/null +++ b/docs/PoC/io/uart/uart_fifo.rst @@ -0,0 +1,28 @@ + +uart_fifo +######### + +Small :abbr:`FIFO (first-in, first-out)` s are included in this module, if +larger or asynchronous transmit / receive FIFOs are required, then they must +be connected externally. + +old comments: + :abbr:`UART (Universal Asynchronous Receiver Transmitter)` BAUD rate generator + bclk = bit clock is rising + bclk_x8 = bit clock times 8 is rising + + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/uart/uart_fifo.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 52-94 + +Source file: `io/uart/uart_fifo.vhdl `_ + + + diff --git a/docs/PoC/io/uart/uart_ft245.rst b/docs/PoC/io/uart/uart_ft245.rst new file mode 100644 index 00000000..8152cb77 --- /dev/null +++ b/docs/PoC/io/uart/uart_ft245.rst @@ -0,0 +1,20 @@ + +uart_ft245 +########## + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/uart/uart_ft245.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 37-63 + +Source file: `io/uart/uart_ft245.vhdl `_ + + + diff --git a/docs/PoC/io/uart/uart_rx.rst b/docs/PoC/io/uart/uart_rx.rst new file mode 100644 index 00000000..85f74718 --- /dev/null +++ b/docs/PoC/io/uart/uart_rx.rst @@ -0,0 +1,21 @@ + +uart_rx +####### + +:abbr:`UART (Universal Asynchronous Receiver Transmitter)` Receiver: +1 Start + 8 Data + 1 Stop + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/uart/uart_rx.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 39-56 + +Source file: `io/uart/uart_rx.vhdl `_ + + + diff --git a/docs/PoC/io/uart/uart_tx.rst b/docs/PoC/io/uart/uart_tx.rst new file mode 100644 index 00000000..b4c63f15 --- /dev/null +++ b/docs/PoC/io/uart/uart_tx.rst @@ -0,0 +1,21 @@ + +uart_tx +####### + +:abbr:`UART (Universal Asynchronous Receiver Transmitter)` Transmitter: +1 Start + 8 Data + 1 Stop + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/uart/uart_tx.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 35-50 + +Source file: `io/uart/uart_tx.vhdl `_ + + + diff --git a/docs/PoC/io/vga/index.rst b/docs/PoC/io/vga/index.rst new file mode 100644 index 00000000..9cdebbc4 --- /dev/null +++ b/docs/PoC/io/vga/index.rst @@ -0,0 +1,11 @@ + +vga +=== + +These are VGA entities.... + +.. toctree:: + + vga_phy + vga_phy_ch7301c + vga_timing diff --git a/docs/PoC/io/vga/vga_phy.rst b/docs/PoC/io/vga/vga_phy.rst new file mode 100644 index 00000000..8ed5ade8 --- /dev/null +++ b/docs/PoC/io/vga/vga_phy.rst @@ -0,0 +1,24 @@ + +vga_phy +####### + + The clock frequency must be the same as used for the timing module. + + The number of color-bits per pixel can be configured with the generic + "COLOR_BITS". The format of the pixel data is defined the picture generator + in use. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/vga/vga_phy.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 43-55 + +Source file: `io/vga/vga_phy.vhdl `_ + + + diff --git a/docs/PoC/io/vga/vga_phy_ch7301c.rst b/docs/PoC/io/vga/vga_phy_ch7301c.rst new file mode 100644 index 00000000..b8889bf5 --- /dev/null +++ b/docs/PoC/io/vga/vga_phy_ch7301c.rst @@ -0,0 +1,44 @@ + +vga_phy_ch7301c +############### + + The clock frequency must be the same as used for the timing module, + e.g., 25 MHZ for VGA 640x480. A phase-shifted clock must be provided: + - clk0 : 0 degrees + - clk90 : 90 degrees + + pixel_data(23 downto 16) : red + pixel_data(15 downto 8) : green + pixel_data( 7 downto 0) : blue + + The "reset_b"-pin must be driven by other logic (such as the reset button). + + The IIC_interface is not part of this modules, as an IIC-master controls + several slaves. The following registers must be set, see + tests/ml505/vga_test_ml505.vhdl for an example. + + Register Value Description + ----------------------------------- + 0x49 PM 0xC0 Enable DVI, RGB bypass off + or 0xD0 Enable DVI, RGB bypass on + 0x33 TPCP 0x08 if clk_freq <= 65 MHz else 0x06 + 0x34 TPD 0x16 if clk_freq <= 65 MHz else 0x26 + 0x36 TPF 0x60 if clk_freq <= 65 MHz else 0xA0 + 0x1F IDF 0x80 when using SMT (VS0, HS0) + or 0x90 when using CVT (VS1, HS0) + 0x21 DC 0x09 Enable DAC if RGB bypass is on + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/vga/vga_phy_ch7301c.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 63-76 + +Source file: `io/vga/vga_phy_ch7301c.vhdl `_ + + + diff --git a/docs/PoC/io/vga/vga_timing.rst b/docs/PoC/io/vga/vga_timing.rst new file mode 100644 index 00000000..445402bf --- /dev/null +++ b/docs/PoC/io/vga/vga_timing.rst @@ -0,0 +1,59 @@ + +vga_timing +########## + + Configuration: + -------------- + MODE = 0: VGA mode with 640x480 pixels, 60 Hz, frequency(clk) ~ 25 MHz + MODE = 1: HD 720p with 1280x720 pixels, 60 Hz, frequency(clk) = 74,5 MHz + MODE = 2: HD 1080p with 1920x1080 pixels, 60 Hz, frequency(clk) = 138,5 MHz + + MODE = 2 uses reduced blanking => only suitable for LCDs. + + For MODE = 0, CVT can be configured: + - CVT = false: Use Safe Mode Timing (SMT). + The legacy fall-back mode supported by CRTs as well as LCDs. + HSync: low-active. VSync: low-active. + frequency(clk) = 25.175 MHz. (25 MHz works => 31 kHz / 59 Hz) + - CVT = true: The "new" Coordinated Video Timing (since 2003). + The CVT supports some new features, such as reduced blanking (for LCDs) or + aspect ratio encoding. See the web for more details. + Standard CRT-based timing (CVT-GTF) has been implemented for best + compatibility: + HSync: low-active. VSync: high-active. + frequency(clk) = 23.75 MHz. (25 MHz works => 31 kHz / 62 Hz) + + Usage: + ------ + The frequency of 'clk' must be equal to the pixel clock frequency of the + selected video mode, see also above. + + When using analog output, the VGA color signals must be blanked, during + horizontal and vertical beam return. This could be achieved by + combinatorial "anding" the color value with "beam_on" (part of "phy_ctrl") + inside the PHY. + + When using digital output (DVI), then "beam_on" is equal to "DE" + (Data Enable) of the DVI transmitter. + + xvalid and yvalid show if xpos respectivly ypos are in a valid range. + beam_on is '1' iff both xvalid and yvalid = '1'. + + xpos and ypos also show the pixel location during blanking. + This might be useful in some applications. But be careful, that the ranges + differ between SMT and CVT. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/vga/vga_timing.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 80-96 + +Source file: `io/vga/vga_timing.vhdl `_ + + + diff --git a/docs/PoC/mem/index.rst b/docs/PoC/mem/index.rst new file mode 100644 index 00000000..7ac07d59 --- /dev/null +++ b/docs/PoC/mem/index.rst @@ -0,0 +1,35 @@ + +mem +=== + +The namespace ``PoC.mem`` offers different on-chip and off-chip memory and memory-controller +implementations. + + +**Sub-Namespaces** + + * :doc:`PoC.mem.ddr3 ` - DDR3 memory controllers + * :doc:`PoC.mem.is61lv ` - ISSI - IS61LV SRAM controller + * :doc:`PoC.mem.is61nlp ` - ISSI - IS61NLP SRAM controller + * :doc:`PoC.mem.lut ` - Lookup-Table (LUT) implementations + * :doc:`PoC.mem.ocram ` - On-Chip RAM abstraction layer + * :doc:`PoC.mem.ocrom ` - On-Chip ROM abstraction layer + * :doc:`PoC.mem.sdram ` - SDRAM controllers + +**Package** + +:doc:`PoC.mem ` + + +.. toctree:: + :hidden: + + ddr3/index + is61lv/index + is61nlp/index + lut/index + ocram/index + ocrom/index + sdram/index + + mem.pkg diff --git a/docs/PoC/mem/is61lv/index.rst b/docs/PoC/mem/is61lv/index.rst new file mode 100644 index 00000000..cda93f51 --- /dev/null +++ b/docs/PoC/mem/is61lv/index.rst @@ -0,0 +1,8 @@ + +is61lv +====== + +These are IS61LV entities.... + +.. toctree:: + diff --git a/docs/PoC/mem/is61nlp/index.rst b/docs/PoC/mem/is61nlp/index.rst new file mode 100644 index 00000000..5a697cca --- /dev/null +++ b/docs/PoC/mem/is61nlp/index.rst @@ -0,0 +1,8 @@ + +is61nlp +======== + +These are IS61NLP entities.... + +.. toctree:: + diff --git a/docs/PoC/mem/lut/index.rst b/docs/PoC/mem/lut/index.rst new file mode 100644 index 00000000..0bd93772 --- /dev/null +++ b/docs/PoC/mem/lut/index.rst @@ -0,0 +1,9 @@ + +lut +=== + +These are Lookup-Table entities.... + +.. toctree:: + + lut_Sine diff --git a/docs/PoC/mem/lut/lut_Sine.rst b/docs/PoC/mem/lut/lut_Sine.rst new file mode 100644 index 00000000..ea7d1b82 --- /dev/null +++ b/docs/PoC/mem/lut/lut_Sine.rst @@ -0,0 +1,20 @@ + +lut_Sine +######## + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/mem/lut/lut_Sine.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 41-54 + +Source file: `mem/lut/lut_Sine.vhdl `_ + + + diff --git a/docs/PoC/mem/mem.pkg.rst b/docs/PoC/mem/mem.pkg.rst new file mode 100644 index 00000000..cb5820d1 --- /dev/null +++ b/docs/PoC/mem/mem.pkg.rst @@ -0,0 +1,7 @@ + +Package +======== + +This package holds all component declarations for this namespace. + +Source file: `mem/mem.pkg.vhdl `_ diff --git a/docs/PoC/mem/ocram/index.rst b/docs/PoC/mem/ocram/index.rst new file mode 100644 index 00000000..a824c7ed --- /dev/null +++ b/docs/PoC/mem/ocram/index.rst @@ -0,0 +1,33 @@ + +ocram +===== + +These are On-Chip RAM (OCRAM) entities... + +**Package** + +The package PoC.mem.ocram holds all component declarations for this namespace. + +.. code-block:: VHDL + + library PoC; + use PoC.ocram.all; + + +**Entities** + + * :doc:`PoC.mem.ocram.sp ` - An on-chip RAM with a single port interface. + * :doc:`PoC.mem.ocram.sdp ` - An on-chip RAM with a simple dual port interface. + * :doc:`PoC.mem.ocram.tdp ` - An on-chip RAM with a true dual port interface. + +**Deprecated Entities** + + * :doc:`PoC.mem.ocram.esdp ` - An on-chip RAM with an extended simple dual port interface. + +.. toctree:: + :hidden: + + ocram_sp + ocram_esdp + ocram_sdp + ocram_tdp diff --git a/docs/PoC/mem/ocram/ocram_esdp.rst b/docs/PoC/mem/ocram/ocram_esdp.rst new file mode 100644 index 00000000..3c181384 --- /dev/null +++ b/docs/PoC/mem/ocram/ocram_esdp.rst @@ -0,0 +1,74 @@ + +ocram_esdp +########## + +Inferring / instantiating enhanced simple dual-port memory, with: + +* dual clock, clock enable, +* 1 read/write port (1st port) plus 1 read port (2nd port). + +.. NOTE:: + This component is **deprecated**. + Please use :doc:`PoC.mem.ocram.tdp ` for new designs. + This component has been provided because older FPGA compilers where not + able to infer true dual-port memory from an RTL description. + +Command truth table for port 1: + +=== === ================ +ce1 we1 Command +=== === ================ +0 X No operation +1 0 Read from memory +1 1 Write to memory +=== === ================ + +Command truth table for port 2: + +=== ================ +ce2 Command +=== ================ +0 No operation +1 Read from memory +=== ================ + +Both reading and writing are synchronous to the rising-edge of the clock. +Thus, when reading, the memory data will be outputted after the +clock edge, i.e, in the following clock cycle. + +The generalized behavior across Altera and Xilinx FPGAs since +Stratix/Cyclone and Spartan-3/Virtex-5, respectively, is as follows: + +Same-Port Read-During-Write + When writing data through port 1, the read output of the same port + (``q1``) will output the new data (``d1``, in the following clock cycle) + which is aka. "write-first behavior". This behavior also applies to Altera + M20K memory blocks as described in the Altera: "Stratix 5 Device Handbook" + (S5-5V1). The documentation in the Altera: "Embedded Memory User Guide" + (UG-01068) is wrong. + +Mixed-Port Read-During-Write + When reading at the write address, the read value will be unknown which is + aka. "don't care behavior". This applies to all reads (at the same + address) which are issued during the write-cycle time, which starts at the + rising-edge of the write clock (``clk1``) and (in the worst case) extends + until the next rising-edge of the write clock. + +.. WARNING:: + The simulated behavior on RT-level is too optimistic. When reading + at the write address always the new data will be returned. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/mem/ocram/ocram_esdp.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 101-119 + +Source file: `mem/ocram/ocram_esdp.vhdl `_ + + + diff --git a/docs/PoC/mem/ocram/ocram_sdp.rst b/docs/PoC/mem/ocram/ocram_sdp.rst new file mode 100644 index 00000000..eec1100e --- /dev/null +++ b/docs/PoC/mem/ocram/ocram_sdp.rst @@ -0,0 +1,40 @@ + +ocram_sdp +######### + +Inferring / instantiating simple dual-port memory, with: + +* dual clock, clock enable, +* 1 read port plus 1 write port. + +The generalized behavior across Altera and Xilinx FPGAs since +Stratix/Cyclone and Spartan-3/Virtex-5, respectively, is as follows: + +Mixed-Port Read-During-Write + When reading at the write address, the read value will be unknown which is + aka. "don't care behavior". This applies to all reads (at the same + address) which are issued during the write-cycle time, which starts at the + rising-edge of the write clock and (in the worst case) extends until the + next rising-edge of the write clock. + +.. WARNING:: + The simulated behavior on RT-level is too optimistic. The + mixed-port read-during-write behavior is only valid if the read and write + clock are in phase. Otherwise, simulation will always show known data. + +.. TODO:: Implement correct behavior for RT-level simulation. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/mem/ocram/ocram_sdp.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 65-82 + +Source file: `mem/ocram/ocram_sdp.vhdl `_ + + + diff --git a/docs/PoC/mem/ocram/ocram_sp.rst b/docs/PoC/mem/ocram/ocram_sp.rst new file mode 100644 index 00000000..131c4b5f --- /dev/null +++ b/docs/PoC/mem/ocram/ocram_sp.rst @@ -0,0 +1,43 @@ + +ocram_sp +######## + +Inferring / instantiating single port memory, with: + +* single clock, clock enable, +* 1 read/write port. + +Command Truth Table: + +== == ================ +ce we Command +== == ================ +0 X No operation +1 0 Read from memory +1 1 Write to memory +== == ================ + +Both reading and writing are synchronous to the rising-edge of the clock. +Thus, when reading, the memory data will be outputted after the +clock edge, i.e, in the following clock cycle. + +When writing data, the read output will output the new data (in the +following clock cycle) which is aka. "write-first behavior". This behavior +also applies to Altera M20K memory blocks as described in the Altera: +"Stratix 5 Device Handbook" (S5-5V1). The documentation in the Altera: +"Embedded Memory User Guide" (UG-01068) is wrong. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/mem/ocram/ocram_sp.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 68-82 + +Source file: `mem/ocram/ocram_sp.vhdl `_ + + + diff --git a/docs/PoC/mem/ocram/ocram_tdp.rst b/docs/PoC/mem/ocram/ocram_tdp.rst new file mode 100644 index 00000000..8690b8fc --- /dev/null +++ b/docs/PoC/mem/ocram/ocram_tdp.rst @@ -0,0 +1,59 @@ + +ocram_tdp +######### + +Inferring / instantiating true dual-port memory, with: + +* dual clock, clock enable, +* 2 read/write ports. + +Command truth table for port 1, same applies to port 2: + +=== === ================ +ce1 we1 Command +=== === ================ +0 X No operation +1 0 Read from memory +1 1 Write to memory +=== === ================ + +The generalized behavior across Altera and Xilinx FPGAs since +Stratix/Cyclone and Spartan-3/Virtex-5, respectively, is as follows: + +Same-Port Read-During-Write + When writing data through port 1, the read output of the same port + (``q1``) will output the new data (``d1``, in the following clock cycle) + which is aka. "write-first behavior". This behavior also applies to Altera + M20K memory blocks as described in the Altera: "Stratix 5 Device Handbook" + (S5-5V1). The documentation in the Altera: "Embedded Memory User Guide" + (UG-01068) is wrong. + + Same applies to port 2. + +Mixed-Port Read-During-Write + When reading at the write address, the read value will be unknown which is + aka. "don't care behavior". This applies to all reads (at the same + address) which are issued during the write-cycle time, which starts at the + rising-edge of the write clock and (in the worst case) extends + until the next rising-edge of that write clock. + +.. WARNING:: + The simulated behavior on RT-level is too optimistic. When reading + at the write address always the new data will be returned. + +.. TODO:: Implement correct behavior for RT-level simulation. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/mem/ocram/ocram_tdp.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 84-104 + +Source file: `mem/ocram/ocram_tdp.vhdl `_ + + + diff --git a/docs/PoC/mem/ocrom/index.rst b/docs/PoC/mem/ocrom/index.rst new file mode 100644 index 00000000..5a5b0260 --- /dev/null +++ b/docs/PoC/mem/ocrom/index.rst @@ -0,0 +1,37 @@ + +ocrom +===== + +These are On-Chip ROM (OCROM) entities.... + +# Namespace `PoC.mem.ocrom` + +The namespace `PoC.mem.ocrom` offers different on-chip ROM abstractions. + + +## Package(s) + +The package [`ocrom`][ocrom.pkg] holds all component declarations for this namespace. + +```VHDL +library PoC; +use PoC.ocrom.all; +``` + + +## Entities + + - [`ocrom_sp`][ocrom_sp] is a on-chip RAM with a single port interface. + - [`ocrom_dp`][ocrom_dp] is a on-chip RAM with a dual port interface. + + + [ocrom.pkg]: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ocrom/ocrom.pkg.vhdl + [ocrom_sp]: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ocrom/ocrom_sp.vhdl + [ocrom_dp]: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ocrom/ocrom_dp.vhdl + + + +.. toctree:: + + ocrom_sp + ocrom_dp diff --git a/docs/PoC/mem/ocrom/ocrom_dp.rst b/docs/PoC/mem/ocrom/ocrom_dp.rst new file mode 100644 index 00000000..c889d0ec --- /dev/null +++ b/docs/PoC/mem/ocrom/ocrom_dp.rst @@ -0,0 +1,31 @@ + +ocrom_dp +######## + +Inferring / instantiating dual-port read-only memory, with: + +* dual clock, clock enable, +* 2 read ports. + +The generalized behavior across Altera and Xilinx FPGAs since +Stratix/Cyclone and Spartan-3/Virtex-5, respectively, is as follows: + +WARNING: The simulated behavior on RT-level is not correct. + +TODO: add timing diagram +TODO: implement correct behavior for RT-level simulation + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/mem/ocrom/ocrom_dp.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 60-76 + +Source file: `mem/ocrom/ocrom_dp.vhdl `_ + + + diff --git a/docs/PoC/mem/ocrom/ocrom_sp.rst b/docs/PoC/mem/ocrom/ocrom_sp.rst new file mode 100644 index 00000000..6bf43afa --- /dev/null +++ b/docs/PoC/mem/ocrom/ocrom_sp.rst @@ -0,0 +1,24 @@ + +ocrom_sp +######## + +Inferring / instantiating single-port read-only memory + +- single clock, clock enable +- 1 read port + + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/mem/ocrom/ocrom_sp.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 53-65 + +Source file: `mem/ocrom/ocrom_sp.vhdl `_ + + + diff --git a/docs/PoC/mem/sdram/index.rst b/docs/PoC/mem/sdram/index.rst new file mode 100644 index 00000000..eee9bb1b --- /dev/null +++ b/docs/PoC/mem/sdram/index.rst @@ -0,0 +1,8 @@ + +sdram +===== + +These are SDRAM entities.... + +.. toctree:: + diff --git a/docs/PoC/mem/sdram/sdram_ctrl_de0.rst b/docs/PoC/mem/sdram/sdram_ctrl_de0.rst new file mode 100644 index 00000000..a0b80eda --- /dev/null +++ b/docs/PoC/mem/sdram/sdram_ctrl_de0.rst @@ -0,0 +1,39 @@ + +sdram_ctrl_de0 +############## + +Complete controller for ISSI SDR-SDRAM for Altera DE0 Board. +SDRAM Device: IS42S16400F + +CLK_PERIOD = clock period in nano seconds. All SDRAM timings are +calculated for the device stated above. + +CL = cas latency, choose according to clock frequency. +BL = burst length. + +Command, address and write data is sampled with clk. + +Tested with: CLK_PERIOD = 7.5 (133 MHz), CL=2, BL=1. + +Read data is aligned with clk. Either process data in this clock +domain, or connect a FIFO to transfer data into another clock domain of your +choice. + +For description on 'clkout' see sdram_ctrl_phy_de0.vhdl. + +Synchronous resets are used. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/mem/sdram/sdram_ctrl_de0.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 77-109 + +Source file: `mem/sdram/sdram_ctrl_de0.vhdl `_ + + + diff --git a/docs/PoC/mem/sdram/sdram_ctrl_fsm.rst b/docs/PoC/mem/sdram/sdram_ctrl_fsm.rst new file mode 100644 index 00000000..4db5364f --- /dev/null +++ b/docs/PoC/mem/sdram/sdram_ctrl_fsm.rst @@ -0,0 +1,82 @@ + +sdram_ctrl_fsm +############## + +This file contains the FSM as well as parts of the datapath. +The board specific physical layer is defined in another file +sdram_ctrl_phy_*.vhdl + +Generics: +--------- +SDRAM_TYPE activates some special cases: +- 0 for SDR-SDRAM +- 1 for DDR-SDRAM +- 2 for DDR2-SDRAM (no special support yet like ODT) + +2**A_BITS specifies the number of memory cells in the SDRAM. This is the +size of th memory in bits divided by the native data-path width of the SDRAM +(also in bits). + +D_BITS is the native data-path width of the SDRAM. The width might be doubled +by the physical interface for DDR interfaces. + +Furthermore, the memory array is divided into +2**R_BITS rows, 2**C_BITS columns and 2**B_BITS banks. + +For example, the MT46V32M16 has 512 Mbit = 8M x 4 banks x 16 bit = +32M cells x 16 bit, with 8K rows and 1K columns. +- A_BITS = log2ceil(32M) = 25 +- D_BITS = 16 +- data-path width of phy on user side: 32-bit because of DDR +- R_BITS = log2ceil(8K) = 13 +- C_BITS = log2ceil(1K) = 10 +- B_BITS = log2ceil(4) = 2 + +Set cas latency (CL, MR_CL) and burst length (BL, MR_BL) according to +your needs. + +If you have a DDR-SDRAM then set INIT_DLL = true, otherwise false. + +The definition and values of generics T_* can be calculated from the +datasheets of the specific SDRAM (e.g. MT46V). Just divide the +minimum/maximum times by clock period. +Auto refreshs are applied periodically, the datasheet either specifies the +average refresh interval (T_REFI) or the total refresh cycle time (T_REF). +In the latter case, divide the total time by the row count to get the +average refresh interval. Substract about 50 clock cycles to +account for pending read/writes. + +INIT_WAIT specifies the time period to wait after the SDRAM is powered up. +It is typically 100--200 us long, see datasheet. The waiting time is +specified in number of average refresh periods (specified by T_REFI): +INIT_WAIT = ceil(wait_time / clock_period / T_REFI) +e.g. INIT_WAIT = ceil(200 us / 10 ns / 700) = 29 + +Signals: +-------- + +After user_cmd_valid is asserted high, the command (user_write) and address +(user_addr) must be hold until user_got_cmd is asserted. + +The FSM automatically waits for user_wdata_valid on writes. The data should +be available soon. Otherwise the auto refresh might fail. The FSM only waits +for the first word to write. All successive words of a burst must be valid +in the following cycles. (A burst can't be stalled.) ATTENTION: During +writes, user_cmd_got is asserted only if user_wdata_valid is set. + +The write data must directly connected to the physical layer. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/mem/sdram/sdram_ctrl_fsm.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 120-164 + +Source file: `mem/sdram/sdram_ctrl_fsm.vhdl `_ + + + diff --git a/docs/PoC/mem/sdram/sdram_ctrl_phy_de0.rst b/docs/PoC/mem/sdram/sdram_ctrl_phy_de0.rst new file mode 100644 index 00000000..49030a40 --- /dev/null +++ b/docs/PoC/mem/sdram/sdram_ctrl_phy_de0.rst @@ -0,0 +1,42 @@ + +sdram_ctrl_phy_de0 +################## + +Physical layer used by module 'sdram_ctrl_de0' + +Instantiates input and output buffer components and adjusts timing for +the Altera DE0 board. + +Command signals and write data are sampled with clk. +Read data is also aligned with clk. + +clk : Base clock for command and write data path. +rst : Reset for clk. + +Write and read enable (wren_nxt, rden_nxt) must be hold for + 1 clock cycle if BL = 1, + 2 clock cycles if BL = 2, or + 4 clock cycles if BL = 4, or + 8 clock cycles if BL = 8. +They must be first asserted with the read and write command. Proper delay is +included in this unit. + +The first word to write must be asserted with the write command. Proper +delay is included in this unit. + +Synchronous resets are used. Reset must be hold for at least two cycles. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/mem/sdram/sdram_ctrl_phy_de0.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 79-112 + +Source file: `mem/sdram/sdram_ctrl_phy_de0.vhdl `_ + + + diff --git a/docs/PoC/mem/sdram/sdram_ctrl_phy_s3esk.rst b/docs/PoC/mem/sdram/sdram_ctrl_phy_s3esk.rst new file mode 100644 index 00000000..e5625bd2 --- /dev/null +++ b/docs/PoC/mem/sdram/sdram_ctrl_phy_s3esk.rst @@ -0,0 +1,67 @@ + +sdram_ctrl_phy_s3esk +#################### + +Physical layer used by module 'sdram_ctrl_s3esk' + +Instantiates input and output buffer components and adjusts timing for +the Spartan-3E Starter Kit Board. + +Command signals and write data are sampled with clk. + +Read data is aligned with clk_fb90_n. Either process data in this clock +domain, or connect a FIFO to transfer data into another clock domain of your +choice. This FIFO should capable of storing at least one burst (size BL/2) ++ start of next burst (size 1). + +clk : base clock for command and write data path. +clk_n : clk phase shifted by 180 degrees. +clk90 : clk phase shifted by 90 degrees. +clk90_n : clk phase shifted by 270 degrees. + +clk_fb : driven by external feedback (sd_ck_fb) of DDR-SDRAM clock + (sd_ck_p). (Actually unused, just for reference.) +clk_fb90 : clk_fb phase shifted by 90 degrees. +clk_fb90_n : clk_fb phase shifted by 270 degrees. + +rst : Reset for clk. +rst180 : Reset for clk_n. +rst90 : Reset for clk90. +rst270 : Reset for clk270. +rst_fb90 : Reset for clk_fb90. +rst_fb90_n : Reset for clk_fb90_n. + +Write and read enable (wren_nxt, rden_nxt) must be hold for + 1 clock cycle if BL = 2, + 2 clock cycles if BL = 4, or + 4 clock cycles if BL = 8. +They must be first asserted with the read and write command. Proper delay is +included in this unit. + +The first word to write must be asserted with the write command. Proper +delay is included in this unit. + +The SDRAM clock is regenerated in this module. The following timing is +chosen for minimum latency. (Should work up to 100 MHz.) + rising_edge(clk90) triggers rising_edge(sd_ck_p) + rising_edge(clk90_n) triggers falling_edge(sd_ck_p) + + +XST options: Disable equivalent register removal. + +Synchronous resets are used. Reset must be hold for at least two cycles. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/mem/sdram/sdram_ctrl_phy_s3esk.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 104-148 + +Source file: `mem/sdram/sdram_ctrl_phy_s3esk.vhdl `_ + + + diff --git a/docs/PoC/mem/sdram/sdram_ctrl_s3esk.rst b/docs/PoC/mem/sdram/sdram_ctrl_s3esk.rst new file mode 100644 index 00000000..4b464ed1 --- /dev/null +++ b/docs/PoC/mem/sdram/sdram_ctrl_s3esk.rst @@ -0,0 +1,38 @@ + +sdram_ctrl_s3esk +################ + +Controller for Micron DDR-SDRAM on Spartan-3E Starter Kit Board. +SDRAM Device: MT46V32M16-6T + +CLK_PERIOD = clock period in nano seconds. All SDRAM timings are +calculated for the device stated above. + +CL = cas latency, choose according to clock frequency. +BL = burst length. + +Tested with: CLK_PERIOD = 10.0, CL=2, BL=2. + +Command, address and write data is sampled with clk. + +Read data is aligned with clk_fb90_n. Either process data in this clock +domain, or connect a FIFO to transfer data into another clock domain of your +choice. This FIFO should capable of storing at least one burst (size BL/2) ++ start of next burst (size 1). + +Synchronous resets are used. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/mem/sdram/sdram_ctrl_s3esk.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 76-119 + +Source file: `mem/sdram/sdram_ctrl_s3esk.vhdl `_ + + + diff --git a/docs/PoC/misc/filter/filter_and.rst b/docs/PoC/misc/filter/filter_and.rst new file mode 100644 index 00000000..b5b9508d --- /dev/null +++ b/docs/PoC/misc/filter/filter_and.rst @@ -0,0 +1,20 @@ + +filter_and +########## + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/misc/filter/filter_and.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 37-48 + +Source file: `misc/filter/filter_and.vhdl `_ + + + diff --git a/docs/PoC/misc/filter/filter_mean.rst b/docs/PoC/misc/filter/filter_mean.rst new file mode 100644 index 00000000..09812062 --- /dev/null +++ b/docs/PoC/misc/filter/filter_mean.rst @@ -0,0 +1,20 @@ + +filter_mean +########### + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/misc/filter/filter_mean.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 37-48 + +Source file: `misc/filter/filter_mean.vhdl `_ + + + diff --git a/docs/PoC/misc/filter/filter_or.rst b/docs/PoC/misc/filter/filter_or.rst new file mode 100644 index 00000000..18f5377e --- /dev/null +++ b/docs/PoC/misc/filter/filter_or.rst @@ -0,0 +1,20 @@ + +filter_or +######### + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/misc/filter/filter_or.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 37-48 + +Source file: `misc/filter/filter_or.vhdl `_ + + + diff --git a/docs/PoC/misc/filter/index.rst b/docs/PoC/misc/filter/index.rst new file mode 100644 index 00000000..3e6e224d --- /dev/null +++ b/docs/PoC/misc/filter/index.rst @@ -0,0 +1,18 @@ + +filter +====== + +These are filter entities.... + +**Entities** + + * :doc:`PoC.misc.filter.and ` + * :doc:`PoC.misc.filter.mean ` + * :doc:`PoC.misc.filter.or ` + +.. toctree:: + :hidden: + + filter_and + filter_mean + filter_or diff --git a/docs/PoC/misc/gearbox/gearbox_down_cc.rst b/docs/PoC/misc/gearbox/gearbox_down_cc.rst new file mode 100644 index 00000000..73f094b0 --- /dev/null +++ b/docs/PoC/misc/gearbox/gearbox_down_cc.rst @@ -0,0 +1,24 @@ + +gearbox_down_cc +############### + + This module provides a downscaling gearbox with a common clock (cc) + interface. It perfoems a 'word' to 'byte' splitting. The default order is + LITTLE_ENDIAN (starting at byte(0)). Input "In_Data" and output "Out_Data" + are of the same clock domain "Clock". Optional input and output registers + can be added by enabling (ADD_***PUT_REGISTERS = TRUE). + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/misc/gearbox/gearbox_down_cc.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 46-70 + +Source file: `misc/gearbox/gearbox_down_cc.vhdl `_ + + + diff --git a/docs/PoC/misc/gearbox/gearbox_down_dc.rst b/docs/PoC/misc/gearbox/gearbox_down_dc.rst new file mode 100644 index 00000000..6e26413f --- /dev/null +++ b/docs/PoC/misc/gearbox/gearbox_down_dc.rst @@ -0,0 +1,29 @@ + +gearbox_down_dc +############### + + This module provides a downscaling gearbox with a dependent clock (dc) + interface. It perfoems a 'word' to 'byte' splitting. The default order is + LITTLE_ENDIAN (starting at byte(0)). Input "In_Data" is of clock domain + "Clock1"; output "Out_Data" is of clock domain "Clock2". Optional input and + output registers can be added by enabling (ADD_***PUT_REGISTERS = TRUE). + +Assertions: +=========== + - Clock periods of Clock1 and Clock2 MUST be multiples of each other. + - Clock1 and Clock2 MUST be phase aligned (related) to each other. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/misc/gearbox/gearbox_down_dc.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 50-64 + +Source file: `misc/gearbox/gearbox_down_dc.vhdl `_ + + + diff --git a/docs/PoC/misc/gearbox/gearbox_up_cc.rst b/docs/PoC/misc/gearbox/gearbox_up_cc.rst new file mode 100644 index 00000000..86042b81 --- /dev/null +++ b/docs/PoC/misc/gearbox/gearbox_up_cc.rst @@ -0,0 +1,24 @@ + +gearbox_up_cc +############# + + This module provides a downscaling gearbox with a common clock (cc) + interface. It perfoems a 'byte' to 'word' collection. The default order is + LITTLE_ENDIAN (starting at byte(0)). Input "In_Data" and output "Out_Data" + are of the same clock domain "Clock". Optional input and output registers + can be added by enabling (ADD_***PUT_REGISTERS = TRUE). + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/misc/gearbox/gearbox_up_cc.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 46-69 + +Source file: `misc/gearbox/gearbox_up_cc.vhdl `_ + + + diff --git a/docs/PoC/misc/gearbox/gearbox_up_dc.rst b/docs/PoC/misc/gearbox/gearbox_up_dc.rst new file mode 100644 index 00000000..8d90a465 --- /dev/null +++ b/docs/PoC/misc/gearbox/gearbox_up_dc.rst @@ -0,0 +1,30 @@ + +gearbox_up_dc +############# + + This module provides a upscaling gearbox with a dependent clock (dc) + interface. It perfoems a 'byte' to 'word' collection. The default order is + LITTLE_ENDIAN (starting at byte(0)). Input "In_Data" is of clock domain + "Clock1"; output "Out_Data" is of clock domain "Clock2". The "In_Align" + is required to mark the starting byte in the word. An optional input + register can be added by enabling (ADD_INPUT_REGISTERS = TRUE). + +Assertions: +=========== + - Clock periods of Clock1 and Clock2 MUST be multiples of each other. + - Clock1 and Clock2 MUST be phase aligned (related) to each other. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/misc/gearbox/gearbox_up_dc.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 51-66 + +Source file: `misc/gearbox/gearbox_up_dc.vhdl `_ + + + diff --git a/docs/PoC/misc/gearbox/index.rst b/docs/PoC/misc/gearbox/index.rst new file mode 100644 index 00000000..765ae347 --- /dev/null +++ b/docs/PoC/misc/gearbox/index.rst @@ -0,0 +1,20 @@ + +gearbox +======== + +These are gearbox entities.... + +**Entities** + + * :doc:`PoC.misc.gearbox.down_cc ` + * :doc:`PoC.misc.gearbox.down_dc ` + * :doc:`PoC.misc.gearbox.up_cc ` + * :doc:`PoC.misc.gearbox.up_dc ` + +.. toctree:: + :hidden: + + gearbox_down_cc + gearbox_down_dc + gearbox_up_cc + gearbox_up_dc diff --git a/docs/PoC/misc/index.rst b/docs/PoC/misc/index.rst new file mode 100644 index 00000000..7651ed65 --- /dev/null +++ b/docs/PoC/misc/index.rst @@ -0,0 +1,43 @@ + +misc +==== + +The namespace ``PoC.misc`` offers different yet uncathegorized entities. + +**Sub-Namespaces** + + * :doc:`PoC.misc.filter ` contains 1-bit filter algorithms. + * :doc:`PoC.misc.stat ` contains statistic modules. + * :doc:`PoC.misc.sync ` offers clock-domain-crossing (CDC) modules. + +**Package** + +The package :doc:`PoC.misc ` holds all component declarations for this namespace. + +**Entities** + + * :doc:`PoC.misc.Delay ` + * :doc:`PoC.misc.FrequencyMeasurement ` + * :doc:`PoC.misc.PulseTrain ` + * :doc:`PoC.misc.Sequencer ` + * :doc:`PoC.misc.StrobeGenerator ` + * :doc:`PoC.misc.StrobeLimiter ` + * :doc:`PoC.misc.WordAligner ` + +.. toctree:: + :hidden: + + filter/index + gearbox/index + stat/index + sync/index + + misc.pkg + + misc_Delay + misc_FrequencyMeasurement + misc_PulseTrain + misc_Sequencer + misc_StrobeGenerator + misc_StrobeLimiter + misc_WordAligner diff --git a/docs/PoC/misc/misc.pkg.rst b/docs/PoC/misc/misc.pkg.rst new file mode 100644 index 00000000..7ea587d9 --- /dev/null +++ b/docs/PoC/misc/misc.pkg.rst @@ -0,0 +1,7 @@ + +Package +======== + +This package holds all component declarations for this namespace. + +Source file: `misc/misc.pkg.vhdl `_ diff --git a/docs/PoC/misc/misc_BitwidthConverter.rst b/docs/PoC/misc/misc_BitwidthConverter.rst new file mode 100644 index 00000000..2b78114f --- /dev/null +++ b/docs/PoC/misc/misc_BitwidthConverter.rst @@ -0,0 +1,18 @@ + +misc_BitwidthConverter +###################### + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/misc/misc_BitwidthConverter.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 32-45 + +Source file: `misc/misc_BitwidthConverter.vhdl `_ + + + diff --git a/docs/PoC/misc/misc_ByteAligner.rst b/docs/PoC/misc/misc_ByteAligner.rst new file mode 100644 index 00000000..b7024d4f --- /dev/null +++ b/docs/PoC/misc/misc_ByteAligner.rst @@ -0,0 +1,20 @@ + +misc_ByteAligner +################ + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/misc/misc_ByteAligner.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 40-53 + +Source file: `misc/misc_ByteAligner.vhdl `_ + + + diff --git a/docs/PoC/misc/misc_Delay.rst b/docs/PoC/misc/misc_Delay.rst new file mode 100644 index 00000000..edd17178 --- /dev/null +++ b/docs/PoC/misc/misc_Delay.rst @@ -0,0 +1,20 @@ + +misc_Delay +########## + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/misc/misc_Delay.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 38-50 + +Source file: `misc/misc_Delay.vhdl `_ + + + diff --git a/docs/PoC/misc/misc_FrequencyMeasurement.rst b/docs/PoC/misc/misc_FrequencyMeasurement.rst new file mode 100644 index 00000000..c8d13954 --- /dev/null +++ b/docs/PoC/misc/misc_FrequencyMeasurement.rst @@ -0,0 +1,22 @@ + +misc_FrequencyMeasurement +######################### + +This module counts 1 second in a reference timer at reference clock. This +reference time is used to start and stop a timer at input clock. The counter +value is the measured frequency in Hz. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/misc/misc_FrequencyMeasurement.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 44-56 + +Source file: `misc/misc_FrequencyMeasurement.vhdl `_ + + + diff --git a/docs/PoC/misc/misc_PulseTrain.rst b/docs/PoC/misc/misc_PulseTrain.rst new file mode 100644 index 00000000..d0a88636 --- /dev/null +++ b/docs/PoC/misc/misc_PulseTrain.rst @@ -0,0 +1,21 @@ + +misc_PulseTrain +############### + + This module generates pulse trains. This module was written as a answer for + a StackOverflow question: http://stackoverflow.com/questions/25783320 + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/misc/misc_PulseTrain.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 41-51 + +Source file: `misc/misc_PulseTrain.vhdl `_ + + + diff --git a/docs/PoC/misc/misc_Sequencer.rst b/docs/PoC/misc/misc_Sequencer.rst new file mode 100644 index 00000000..73209bb0 --- /dev/null +++ b/docs/PoC/misc/misc_Sequencer.rst @@ -0,0 +1,20 @@ + +misc_Sequencer +############## + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/misc/misc_Sequencer.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 40-56 + +Source file: `misc/misc_Sequencer.vhdl `_ + + + diff --git a/docs/PoC/misc/misc_StrobeGenerator.rst b/docs/PoC/misc/misc_StrobeGenerator.rst new file mode 100644 index 00000000..8471f24f --- /dev/null +++ b/docs/PoC/misc/misc_StrobeGenerator.rst @@ -0,0 +1,20 @@ + +misc_StrobeGenerator +#################### + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/misc/misc_StrobeGenerator.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 40-49 + +Source file: `misc/misc_StrobeGenerator.vhdl `_ + + + diff --git a/docs/PoC/misc/misc_StrobeLimiter.rst b/docs/PoC/misc/misc_StrobeLimiter.rst new file mode 100644 index 00000000..7eea3f38 --- /dev/null +++ b/docs/PoC/misc/misc_StrobeLimiter.rst @@ -0,0 +1,20 @@ + +misc_StrobeLimiter +################## + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/misc/misc_StrobeLimiter.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 39-51 + +Source file: `misc/misc_StrobeLimiter.vhdl `_ + + + diff --git a/docs/PoC/misc/misc_WordAligner.rst b/docs/PoC/misc/misc_WordAligner.rst new file mode 100644 index 00000000..e016b427 --- /dev/null +++ b/docs/PoC/misc/misc_WordAligner.rst @@ -0,0 +1,19 @@ + +WordAligner +########### + +.. TODO:: No documentation available. + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/misc/misc_WordAligner.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 39-52 + +Source file: `misc/misc_WordAligner.vhdl `_ + + + diff --git a/docs/PoC/misc/misc_bit_lz.rst b/docs/PoC/misc/misc_bit_lz.rst new file mode 100644 index 00000000..10b20231 --- /dev/null +++ b/docs/PoC/misc/misc_bit_lz.rst @@ -0,0 +1,56 @@ + +misc_bit_lz +########### + + + An LZ77-based bit stream compressor. + + Output Format + + 1 | Literal + A literal bit string of length COUNT_BITS+OFFSET_BITS. + + 0 | | + Repetition starting at in history buffer of length + +COUNT_BITS+OFFSET_BITS where < 2^COUNT_BITS-1. + Unless = 2^COUNT_BITS-2, this repetition is + followed by a trailing non-matching, i.e. inverted, bit. + The most recent bit just preceding the repetition is considered to be at + offset zero(0). Older bits are at higher offsets accordingly. The + reported length of the repetition may actually be greater than the + offset. In this case, the repetition is reoccuring in itself. The + reconstruction must then be performed in several steps. + + 0 | <1:COUNT_BITS> | + This marks the end of the message. The field alters the + semantics of the immediately preceding message: + + a)If the preceding message was a repetition, specifies the value + of the trailing bit explicitly in its rightmost bit. The implicit + trailing non-matching bit is overridden. + b)If the preceding message was a literal, is a non-positive + number d given in its one's complement representation. The value + ~d specifies the number of bits, which this literal repeated of the + preceding output. These bits must be deleted from the reconstructed + stream. + + + Parameter Constraints + + COUNT_BITS <= OFFSET_BITS < 2**COUNT_BITS - COUNT_BITS + +============================================================================= + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/misc/misc_bit_lz.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 69-91 + +Source file: `misc/misc_bit_lz.vhdl `_ + + + diff --git a/docs/PoC/misc/stat/index.rst b/docs/PoC/misc/stat/index.rst new file mode 100644 index 00000000..542f6f0c --- /dev/null +++ b/docs/PoC/misc/stat/index.rst @@ -0,0 +1,21 @@ + +stat +==== + +These are stat entities.... + +**Entities** + + * :doc:`PoC.misc.stat.Average ` + * :doc:`PoC.misc.stat.Histogram ` + * :doc:`PoC.misc.stat.Maximum ` + * :doc:`PoC.misc.stat.Minimum ` + + +.. toctree:: + :hidden: + + stat_Average + stat_Histogram + stat_Maximum + stat_Minimum diff --git a/docs/PoC/misc/stat/stat_Average.rst b/docs/PoC/misc/stat/stat_Average.rst new file mode 100644 index 00000000..6d149fd1 --- /dev/null +++ b/docs/PoC/misc/stat/stat_Average.rst @@ -0,0 +1,20 @@ + +stat_Average +############ + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/misc/stat/stat_Average.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 41-58 + +Source file: `misc/stat/stat_Average.vhdl `_ + + + diff --git a/docs/PoC/misc/stat/stat_Histogram.rst b/docs/PoC/misc/stat/stat_Histogram.rst new file mode 100644 index 00000000..3fa0400f --- /dev/null +++ b/docs/PoC/misc/stat/stat_Histogram.rst @@ -0,0 +1,20 @@ + +stat_Histogram +############## + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/misc/stat/stat_Histogram.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 40-54 + +Source file: `misc/stat/stat_Histogram.vhdl `_ + + + diff --git a/docs/PoC/misc/stat/stat_Maximum.rst b/docs/PoC/misc/stat/stat_Maximum.rst new file mode 100644 index 00000000..36f9adeb --- /dev/null +++ b/docs/PoC/misc/stat/stat_Maximum.rst @@ -0,0 +1,20 @@ + +stat_Maximum +############ + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/misc/stat/stat_Maximum.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 40-57 + +Source file: `misc/stat/stat_Maximum.vhdl `_ + + + diff --git a/docs/PoC/misc/stat/stat_Minimum.rst b/docs/PoC/misc/stat/stat_Minimum.rst new file mode 100644 index 00000000..e98f7545 --- /dev/null +++ b/docs/PoC/misc/stat/stat_Minimum.rst @@ -0,0 +1,20 @@ + +stat_Minimum +############ + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/misc/stat/stat_Minimum.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 40-57 + +Source file: `misc/stat/stat_Minimum.vhdl `_ + + + diff --git a/docs/PoC/misc/sync/index.rst b/docs/PoC/misc/sync/index.rst new file mode 100644 index 00000000..8468f00f --- /dev/null +++ b/docs/PoC/misc/sync/index.rst @@ -0,0 +1,77 @@ +sync +==== + +The namespace ``PoC.misc.sync`` offers different clock-domain-crossing (CDC) +synchronizer circuits. All synchronizers are based on the basic 2 flip-flop +synchonizer called :doc:`sync_Bits `. PoC has two +platform specific implementations for Altera and Xilinx, which are choosen, +if the appropriate ``MY_DEVICE`` constant is configured in :doc:`my_config.vhdl `. + +**Decision Table:** + ++----------+-------------------------------------------------+---------------------------------------------------+--------------------+-----------------------------------------------+-----------------------------------------------+ +| Behavior | Flag [#f1]_ | Strobe [#f2]_ | Continuous Data | Reset [#f4]_ | Pulse [#f3]_ | ++==========+=================================================+===================================================+====================+===============================================+===============================================+ +| 1 Bit | :doc:`sync_Bits ` | :doc:`sync_Strobe ` | fifo_ic_got [#f5]_ | :doc:`sync_Reset ` | :doc:`sync_Pulse ` | ++----------+-------------------------------------------------+---------------------------------------------------+--------------------+-----------------------------------------------+-----------------------------------------------+ +| n Bit | :doc:`sync_Vector ` | :doc:`sync_Command ` | fifo_ic_got [#f5]_ | | | ++----------+-------------------------------------------------+---------------------------------------------------+--------------------+-----------------------------------------------+-----------------------------------------------+ + +.. rubric:: Basic 2 Flip-Flop Synchronizer + +The basic 2 flip-flop synchronizer is called :doc:`sync_Bits `. It's +possible to configure the bit count of indivital bits. If a vector shall be +synchronized, use one of the special synchronizers like `sync_Vector`. The +vendor specific implementations are named ``sync_Bits_Altera`` and +``sync_Bits_Xilinx`` respectivily. + +A second variant of the 2-FF synchronizer is called :doc:`sync_Reset `. +It's for ``Reset``-signals, implementing asynchronous assertion and synchronous +deassertion. The vendor specific implementations are named ``sync_Reset_Altera`` +and ``sync_Reset_Xilinx`` respectivily. + +A third variant of a 2-FF synchronizer is called :doc:`sync_Pulse `. +It's for very short ``Pulsed``-signals. It uses an addition asynchronous capture FF to latch the +very short pulse. The vendor specific implementations are named ``sync_Pulse_Altera`` and +``sync_Pulse_Xilinx`` respectivily. + +.. rubric:: Special Synchronizers + +Based on the 2-FF synchronizer, several "high-level" synchronizers are build. + +* :doc:`sync_Strobe ` synchronizer ``strobe``-signals + across clock-domain-boundaries. A busy signal indicates the synchronization + status and can be used as a internal gate-signal to disallow new incoming + strobes. A ``strobe``-signal is only for one clock period active. +* :doc:`sync_Command ` like ``sync_Strobe``, it synchronizes + a one clock period active signal across the clock-domain-boundary, but the + input has multiple bits. After the multi bit strobe (Command) was transfered, + the output goes to its idle value. +* :doc:`sync_Vector ` synchronizes a complete vector + across the clock-domain-boundary. A changed detection on the input vector + causes a register to latch the current state. The changed event is transfered + to the new clock-domain and triggers a register to store the latched content, + but in the new clock domain. + +.. seealso:: + + :doc:`PoC.fifo.ic_got ` + For a cross-clock capable FIFO. + +.. rubric:: Footnotes + +.. [#f1] A *flag* or *status* signal is a continuous, long time stable signal. +.. [#f2] A *strobe* signal is active for only one cycle. +.. [#f3] A *pulse* signal is a very short event. +.. [#f4] To be documented +.. [#f5] See the ``PoC.fifo`` namespace for cross-clock capable FIFOs. + +.. toctree:: + :hidden: + + sync_Bits + sync_Command + sync_Pulse + sync_Reset + sync_Strobe + sync_Vector diff --git a/docs/PoC/misc/sync/sync_Bits.rst b/docs/PoC/misc/sync/sync_Bits.rst new file mode 100644 index 00000000..0c88cfae --- /dev/null +++ b/docs/PoC/misc/sync/sync_Bits.rst @@ -0,0 +1,49 @@ + +sync_Bits +######### + +This module synchronizes multiple flag bits into clock-domain ``Clock``. +The clock-domain boundary crossing is done by two synchronizer D-FFs. All +bits are independent from each other. If a known vendor like Altera or Xilinx +are recognized, a vendor specific implementation is choosen. + +.. ATTENTION:: + Use this synchronizer only for long time stable signals (flags). + +Constraints: + General: + Please add constraints for meta stability to all '_meta' signals and + timing ignore constraints to all '_async' signals. + + Xilinx: + In case of a Xilinx device, this module will instantiate the optimized + module PoC.xil.sync.Bits. Please attend to the notes of sync_Bits.vhdl. + + Altera sdc file: + TODO + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/misc/sync/sync_Bits.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 68-79 + +Source file: `misc/sync/sync_Bits.vhdl `_ + +.. seealso:: + + :doc:`PoC.misc.sync.Reset ` + For a special 2 D-FF synchronizer for *reset*-signals. + :doc:`PoC.misc.sync.Pulse ` + For a special 1+2 D-FF synchronizer for *pulse*-signals. + :doc:`PoC.misc.sync.Strobe ` + For a synchronizer for *strobe*-signals. + :doc:`PoC.misc.sync.Vector ` + For a multiple bits capable synchronizer. + + + diff --git a/docs/PoC/misc/sync/sync_Command.rst b/docs/PoC/misc/sync/sync_Command.rst new file mode 100644 index 00000000..8224d838 --- /dev/null +++ b/docs/PoC/misc/sync/sync_Command.rst @@ -0,0 +1,30 @@ + +sync_Command +############ + +This module synchronizes a vector of bits from clock-domain ``Clock1`` to +clock-domain ``Clock2``. The clock-domain boundary crossing is done by a +change comparator, a T-FF, two synchronizer D-FFs and a reconstructive +XOR indicating a value change on the input. This changed signal is used +to capture the input for the new output. A busy flag is additionally +calculated for the input clock-domain. The output has strobe character +and is reset to it's ``INIT`` value after one clock cycle. + +Constraints: + This module uses sub modules which need to be constrained. Please + attend to the notes of the instantiated sub modules. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/misc/sync/sync_Command.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 50-63 + +Source file: `misc/sync/sync_Command.vhdl `_ + + + diff --git a/docs/PoC/misc/sync/sync_Pulse.rst b/docs/PoC/misc/sync/sync_Pulse.rst new file mode 100644 index 00000000..90c685ff --- /dev/null +++ b/docs/PoC/misc/sync/sync_Pulse.rst @@ -0,0 +1,49 @@ + +sync_Pulse +########## + +This module synchronizes multiple pulsed bits into the clock-domain ``Clock``. +The clock-domain boundary crossing is done by two synchronizer D-FFs. All bits +are independent from each other. If a known vendor like Altera or Xilinx are +recognized, a vendor specific implementation is choosen. + +.. ATTENTION:: + Use this synchronizer for very short signals (pulse). + +Constraints: + General: + Please add constraints for meta stability to all '_meta' signals and + timing ignore constraints to all '_async' signals. + + Xilinx: + In case of a Xilinx device, this module will instantiate the optimized + module PoC.xil.sync.Pulse. Please attend to the notes of sync_Bits.vhdl. + + Altera sdc file: + TODO + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/misc/sync/sync_Pulse.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 68-78 + +Source file: `misc/sync/sync_Pulse.vhdl `_ + +.. seealso:: + + :doc:`PoC.misc.sync.Bits ` + For a common 2 D-FF synchronizer for *flag*-signals. + :doc:`PoC.misc.sync.Reset ` + For a special 2 D-FF synchronizer for *reset*-signals. + :doc:`PoC.misc.sync.Strobe ` + For a synchronizer for *strobe*-signals. + :doc:`PoC.misc.sync.Vector ` + For a multiple bits capable synchronizer. + + + diff --git a/docs/PoC/misc/sync/sync_Reset.rst b/docs/PoC/misc/sync/sync_Reset.rst new file mode 100644 index 00000000..191a0f65 --- /dev/null +++ b/docs/PoC/misc/sync/sync_Reset.rst @@ -0,0 +1,40 @@ + +sync_Reset +########## + +This module synchronizes an asynchronous reset signal to the clock +``Clock``. The ``Input`` can be asserted and de-asserted at any time. +The ``Output`` is asserted asynchronously and de-asserted synchronously +to the clock. + +.. ATTENTION:: + Use this synchronizer only to asynchronously reset your design. + The 'Output' should be feed by global buffer to the destination FFs, so + that, it reaches their reset inputs within one clock cycle. + +Constraints: + General: + Please add constraints for meta stability to all '_meta' signals and + timing ignore constraints to all '_async' signals. + + Xilinx: + In case of a Xilinx device, this module will instantiate the optimized + module xil_SyncReset. Please attend to the notes of xil_SyncReset. + + Altera sdc file: + TODO + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/misc/sync/sync_Reset.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 60-69 + +Source file: `misc/sync/sync_Reset.vhdl `_ + + + diff --git a/docs/PoC/misc/sync/sync_Strobe.rst b/docs/PoC/misc/sync/sync_Strobe.rst new file mode 100644 index 00000000..84e566a8 --- /dev/null +++ b/docs/PoC/misc/sync/sync_Strobe.rst @@ -0,0 +1,32 @@ + +sync_Strobe +########### + +This module synchronizes multiple high-active bits from clock-domain +``Clock1`` to clock-domain ``Clock2``. The clock-domain boundary crossing is +done by a T-FF, two synchronizer D-FFs and a reconstructive XOR. A busy +flag is additionally calculated and can be used to block new inputs. All +bits are independent from each other. Multiple consecutive strobes are +suppressed by a rising edge detection. + +.. ATTENTION:: + Use this synchronizer only for one-cycle high-active signals (strobes). + +Constraints: + This module uses sub modules which need to be constrained. Please + attend to the notes of the instantiated sub modules. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/misc/sync/sync_Strobe.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 51-63 + +Source file: `misc/sync/sync_Strobe.vhdl `_ + + + diff --git a/docs/PoC/misc/sync/sync_Vector.rst b/docs/PoC/misc/sync/sync_Vector.rst new file mode 100644 index 00000000..c2ace981 --- /dev/null +++ b/docs/PoC/misc/sync/sync_Vector.rst @@ -0,0 +1,29 @@ + +sync_Vector +########### + +This module synchronizes a vector of bits from clock-domain ``Clock1`` to +clock-domain ``Clock2``. The clock-domain boundary crossing is done by a +change comparator, a T-FF, two synchronizer D-FFs and a reconstructive +XOR indicating a value change on the input. This changed signal is used +to capture the input for the new output. A busy flag is additionally +calculated for the input clock domain. + +Constraints: + This module uses sub modules which need to be constrainted. Please + attend to the notes of the instantiated sub modules. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/misc/sync/sync_Vector.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 49-63 + +Source file: `misc/sync/sync_Vector.vhdl `_ + + + diff --git a/docs/PoC/net/arp/arp_BroadCast_Receiver.rst b/docs/PoC/net/arp/arp_BroadCast_Receiver.rst new file mode 100644 index 00000000..9aeca321 --- /dev/null +++ b/docs/PoC/net/arp/arp_BroadCast_Receiver.rst @@ -0,0 +1,20 @@ + +arp_BroadCast_Receiver +###################### + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/arp/arp_BroadCast_Receiver.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-74 + +Source file: `net/arp/arp_BroadCast_Receiver.vhdl `_ + + + diff --git a/docs/PoC/net/arp/arp_BroadCast_Requester.rst b/docs/PoC/net/arp/arp_BroadCast_Requester.rst new file mode 100644 index 00000000..45f11821 --- /dev/null +++ b/docs/PoC/net/arp/arp_BroadCast_Requester.rst @@ -0,0 +1,20 @@ + +arp_BroadCast_Requester +####################### + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/arp/arp_BroadCast_Requester.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-73 + +Source file: `net/arp/arp_BroadCast_Requester.vhdl `_ + + + diff --git a/docs/PoC/net/arp/arp_Cache.rst b/docs/PoC/net/arp/arp_Cache.rst new file mode 100644 index 00000000..5007fdb0 --- /dev/null +++ b/docs/PoC/net/arp/arp_Cache.rst @@ -0,0 +1,20 @@ + +arp_Cache +######### + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/arp/arp_Cache.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 44-75 + +Source file: `net/arp/arp_Cache.vhdl `_ + + + diff --git a/docs/PoC/net/arp/arp_IPPool.rst b/docs/PoC/net/arp/arp_IPPool.rst new file mode 100644 index 00000000..dceffcdf --- /dev/null +++ b/docs/PoC/net/arp/arp_IPPool.rst @@ -0,0 +1,20 @@ + +arp_IPPool +########## + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/arp/arp_IPPool.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 43-63 + +Source file: `net/arp/arp_IPPool.vhdl `_ + + + diff --git a/docs/PoC/net/arp/arp_Tester.rst b/docs/PoC/net/arp/arp_Tester.rst new file mode 100644 index 00000000..39ce6b01 --- /dev/null +++ b/docs/PoC/net/arp/arp_Tester.rst @@ -0,0 +1,20 @@ + +arp_Tester +########## + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/arp/arp_Tester.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 43-65 + +Source file: `net/arp/arp_Tester.vhdl `_ + + + diff --git a/docs/PoC/net/arp/arp_UniCast_Receiver.rst b/docs/PoC/net/arp/arp_UniCast_Receiver.rst new file mode 100644 index 00000000..518ba0ea --- /dev/null +++ b/docs/PoC/net/arp/arp_UniCast_Receiver.rst @@ -0,0 +1,20 @@ + +arp_UniCast_Receiver +#################### + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/arp/arp_UniCast_Receiver.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-76 + +Source file: `net/arp/arp_UniCast_Receiver.vhdl `_ + + + diff --git a/docs/PoC/net/arp/arp_UniCast_Responder.rst b/docs/PoC/net/arp/arp_UniCast_Responder.rst new file mode 100644 index 00000000..6cb4e232 --- /dev/null +++ b/docs/PoC/net/arp/arp_UniCast_Responder.rst @@ -0,0 +1,20 @@ + +arp_UniCast_Responder +##################### + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/arp/arp_UniCast_Responder.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-73 + +Source file: `net/arp/arp_UniCast_Responder.vhdl `_ + + + diff --git a/docs/PoC/net/arp/arp_Wrapper.rst b/docs/PoC/net/arp/arp_Wrapper.rst new file mode 100644 index 00000000..5a480ad7 --- /dev/null +++ b/docs/PoC/net/arp/arp_Wrapper.rst @@ -0,0 +1,20 @@ + +arp_Wrapper +########### + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/arp/arp_Wrapper.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 44-100 + +Source file: `net/arp/arp_Wrapper.vhdl `_ + + + diff --git a/docs/PoC/net/arp/index.rst b/docs/PoC/net/arp/index.rst new file mode 100644 index 00000000..f4dd1fe2 --- /dev/null +++ b/docs/PoC/net/arp/index.rst @@ -0,0 +1,16 @@ + +arp +=== + +These are ARP entities.... + +.. toctree:: + + arp_BroadCast_Receiver + arp_BroadCast_Requester + arp_Cache + arp_IPPool + arp_Tester + arp_UniCast_Receiver + arp_UniCast_Responder + arp_Wrapper diff --git a/docs/PoC/net/eth/eth_GEMAC_GMII.rst b/docs/PoC/net/eth/eth_GEMAC_GMII.rst new file mode 100644 index 00000000..75094c88 --- /dev/null +++ b/docs/PoC/net/eth/eth_GEMAC_GMII.rst @@ -0,0 +1,20 @@ + +eth_GEMAC_GMII +############## + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/eth/eth_GEMAC_GMII.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-101 + +Source file: `net/eth/eth_GEMAC_GMII.vhdl `_ + + + diff --git a/docs/PoC/net/eth/eth_GEMAC_RX.rst b/docs/PoC/net/eth/eth_GEMAC_RX.rst new file mode 100644 index 00000000..24745ee6 --- /dev/null +++ b/docs/PoC/net/eth/eth_GEMAC_RX.rst @@ -0,0 +1,20 @@ + +Eth_GEMAC_RX +############ + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/eth/eth_GEMAC_RX.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-62 + +Source file: `net/eth/eth_GEMAC_RX.vhdl `_ + + + diff --git a/docs/PoC/net/eth/eth_GEMAC_TX.rst b/docs/PoC/net/eth/eth_GEMAC_TX.rst new file mode 100644 index 00000000..6cbfea27 --- /dev/null +++ b/docs/PoC/net/eth/eth_GEMAC_TX.rst @@ -0,0 +1,20 @@ + +Eth_GEMAC_TX +############ + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/eth/eth_GEMAC_TX.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-65 + +Source file: `net/eth/eth_GEMAC_TX.vhdl `_ + + + diff --git a/docs/PoC/net/eth/eth_PHYController.rst b/docs/PoC/net/eth/eth_PHYController.rst new file mode 100644 index 00000000..dd91ac10 --- /dev/null +++ b/docs/PoC/net/eth/eth_PHYController.rst @@ -0,0 +1,20 @@ + +Eth_PHYController +################# + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/eth/eth_PHYController.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 45-68 + +Source file: `net/eth/eth_PHYController.vhdl `_ + + + diff --git a/docs/PoC/net/eth/eth_PHYController_Marvell_88E1111.rst b/docs/PoC/net/eth/eth_PHYController_Marvell_88E1111.rst new file mode 100644 index 00000000..8be2545e --- /dev/null +++ b/docs/PoC/net/eth/eth_PHYController_Marvell_88E1111.rst @@ -0,0 +1,20 @@ + +Eth_PHYController_Marvell_88E1111 +################################# + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/eth/eth_PHYController_Marvell_88E1111.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 44-71 + +Source file: `net/eth/eth_PHYController_Marvell_88E1111.vhdl `_ + + + diff --git a/docs/PoC/net/eth/eth_Wrapper.rst b/docs/PoC/net/eth/eth_Wrapper.rst new file mode 100644 index 00000000..f54362b9 --- /dev/null +++ b/docs/PoC/net/eth/eth_Wrapper.rst @@ -0,0 +1,20 @@ + +Eth_Wrapper +########### + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/eth/eth_Wrapper.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 68-112 + +Source file: `net/eth/eth_Wrapper.vhdl `_ + + + diff --git a/docs/PoC/net/eth/index.rst b/docs/PoC/net/eth/index.rst new file mode 100644 index 00000000..555d552e --- /dev/null +++ b/docs/PoC/net/eth/index.rst @@ -0,0 +1,14 @@ + +eth +=== + +These are eth entities.... + +.. toctree:: + + eth_GEMAC_GMII + eth_GEMAC_RX + eth_GEMAC_TX + eth_PHYController + eth_PHYController_Marvell_88E1111 + eth_Wrapper diff --git a/docs/PoC/net/icmpv4/icmpv4_RX.rst b/docs/PoC/net/icmpv4/icmpv4_RX.rst new file mode 100644 index 00000000..32d296c8 --- /dev/null +++ b/docs/PoC/net/icmpv4/icmpv4_RX.rst @@ -0,0 +1,20 @@ + +icmpv4_RX +######### + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/icmpv4/icmpv4_RX.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-88 + +Source file: `net/icmpv4/icmpv4_RX.vhdl `_ + + + diff --git a/docs/PoC/net/icmpv4/icmpv4_TX.rst b/docs/PoC/net/icmpv4/icmpv4_TX.rst new file mode 100644 index 00000000..67986f7c --- /dev/null +++ b/docs/PoC/net/icmpv4/icmpv4_TX.rst @@ -0,0 +1,20 @@ + +icmpv4_TX +######### + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/icmpv4/icmpv4_TX.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-78 + +Source file: `net/icmpv4/icmpv4_TX.vhdl `_ + + + diff --git a/docs/PoC/net/icmpv4/icmpv4_Wrapper.rst b/docs/PoC/net/icmpv4/icmpv4_Wrapper.rst new file mode 100644 index 00000000..c08141e8 --- /dev/null +++ b/docs/PoC/net/icmpv4/icmpv4_Wrapper.rst @@ -0,0 +1,20 @@ + +icmpv4_Wrapper +############## + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/icmpv4/icmpv4_Wrapper.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-91 + +Source file: `net/icmpv4/icmpv4_Wrapper.vhdl `_ + + + diff --git a/docs/PoC/net/icmpv4/index.rst b/docs/PoC/net/icmpv4/index.rst new file mode 100644 index 00000000..e8276ba9 --- /dev/null +++ b/docs/PoC/net/icmpv4/index.rst @@ -0,0 +1,11 @@ + +icmpv4 +====== + +These are icmpv4 entities.... + +.. toctree:: + + icmpv4_RX + icmpv4_TX + icmpv4_Wrapper diff --git a/docs/PoC/net/icmpv6/icmpv6_RX.rst b/docs/PoC/net/icmpv6/icmpv6_RX.rst new file mode 100644 index 00000000..9a57ab9f --- /dev/null +++ b/docs/PoC/net/icmpv6/icmpv6_RX.rst @@ -0,0 +1,20 @@ + +icmpv6_RX +######### + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/icmpv6/icmpv6_RX.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-57 + +Source file: `net/icmpv6/icmpv6_RX.vhdl `_ + + + diff --git a/docs/PoC/net/icmpv6/icmpv6_TX.rst b/docs/PoC/net/icmpv6/icmpv6_TX.rst new file mode 100644 index 00000000..24e6dee4 --- /dev/null +++ b/docs/PoC/net/icmpv6/icmpv6_TX.rst @@ -0,0 +1,20 @@ + +icmpv6_TX +######### + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/icmpv6/icmpv6_TX.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-56 + +Source file: `net/icmpv6/icmpv6_TX.vhdl `_ + + + diff --git a/docs/PoC/net/icmpv6/icmpv6_Wrapper.rst b/docs/PoC/net/icmpv6/icmpv6_Wrapper.rst new file mode 100644 index 00000000..23718664 --- /dev/null +++ b/docs/PoC/net/icmpv6/icmpv6_Wrapper.rst @@ -0,0 +1,20 @@ + +icmpv6_Wrapper +############## + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/icmpv6/icmpv6_Wrapper.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-67 + +Source file: `net/icmpv6/icmpv6_Wrapper.vhdl `_ + + + diff --git a/docs/PoC/net/icmpv6/index.rst b/docs/PoC/net/icmpv6/index.rst new file mode 100644 index 00000000..2586053b --- /dev/null +++ b/docs/PoC/net/icmpv6/index.rst @@ -0,0 +1,11 @@ + +icmpv6 +====== + +These are icmpv6 entities.... + +.. toctree:: + + icmpv6_RX + icmpv6_TX + icmpv6_Wrapper diff --git a/docs/PoC/net/index.rst b/docs/PoC/net/index.rst new file mode 100644 index 00000000..728d253f --- /dev/null +++ b/docs/PoC/net/index.rst @@ -0,0 +1,43 @@ + +net +=== + +These are bus entities.... + +**Sub-Namespaces** + + * :doc:`PoC.net.arp ` + * :doc:`PoC.net.eth ` + * :doc:`PoC.net.icmpv4 ` + * :doc:`PoC.net.icmpv6 ` + * :doc:`PoC.net.ipv4 ` + * :doc:`PoC.net.ipv6 ` + * :doc:`PoC.net.mac ` + * :doc:`PoC.net.ndp ` + * :doc:`PoC.net.stack ` + * :doc:`PoC.net.udp ` + +**Entities** + + * :doc:`PoC.net.FrameChecksum ` + * :doc:`PoC.net.FrameLoopback ` + +.. toctree:: + :hidden: + + arp/index + eth/index + icmpv4/index + icmpv6/index + ipv4/index + ipv6/index + mac/index + ndp/index + stack/index + udp/index + +.. toctree:: + :hidden: + + net_FrameChecksum + net_FrameLoopback diff --git a/docs/PoC/net/ipv4/index.rst b/docs/PoC/net/ipv4/index.rst new file mode 100644 index 00000000..abd71311 --- /dev/null +++ b/docs/PoC/net/ipv4/index.rst @@ -0,0 +1,12 @@ + +ipv4 +==== + +These are ipv4 entities.... + +.. toctree:: + + ipv4_RX + ipv4_TX + ipv4_FrameLoopback + ipv4_Wrapper diff --git a/docs/PoC/net/ipv4/ipv4_FrameLoopback.rst b/docs/PoC/net/ipv4/ipv4_FrameLoopback.rst new file mode 100644 index 00000000..d551fa49 --- /dev/null +++ b/docs/PoC/net/ipv4/ipv4_FrameLoopback.rst @@ -0,0 +1,20 @@ + +ipv4_FrameLoopback +################## + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/ipv4/ipv4_FrameLoopback.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-74 + +Source file: `net/ipv4/ipv4_FrameLoopback.vhdl `_ + + + diff --git a/docs/PoC/net/ipv4/ipv4_RX.rst b/docs/PoC/net/ipv4/ipv4_RX.rst new file mode 100644 index 00000000..71f65197 --- /dev/null +++ b/docs/PoC/net/ipv4/ipv4_RX.rst @@ -0,0 +1,20 @@ + +ipv4_RX +####### + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/ipv4/ipv4_RX.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-82 + +Source file: `net/ipv4/ipv4_RX.vhdl `_ + + + diff --git a/docs/PoC/net/ipv4/ipv4_TX.rst b/docs/PoC/net/ipv4/ipv4_TX.rst new file mode 100644 index 00000000..c7143b05 --- /dev/null +++ b/docs/PoC/net/ipv4/ipv4_TX.rst @@ -0,0 +1,20 @@ + +ipv4_TX +####### + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/ipv4/ipv4_TX.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-81 + +Source file: `net/ipv4/ipv4_TX.vhdl `_ + + + diff --git a/docs/PoC/net/ipv4/ipv4_Wrapper.rst b/docs/PoC/net/ipv4/ipv4_Wrapper.rst new file mode 100644 index 00000000..587c5e1e --- /dev/null +++ b/docs/PoC/net/ipv4/ipv4_Wrapper.rst @@ -0,0 +1,20 @@ + +ipv4_Wrapper +############ + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/ipv4/ipv4_Wrapper.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-112 + +Source file: `net/ipv4/ipv4_Wrapper.vhdl `_ + + + diff --git a/docs/PoC/net/ipv6/index.rst b/docs/PoC/net/ipv6/index.rst new file mode 100644 index 00000000..ca51fd7e --- /dev/null +++ b/docs/PoC/net/ipv6/index.rst @@ -0,0 +1,12 @@ + +ipv6 +==== + +These are ipv6 entities.... + +.. toctree:: + + ipv6_RX + ipv6_TX + ipv6_FrameLoopback + ipv6_Wrapper diff --git a/docs/PoC/net/ipv6/ipv6_FrameLoopback.rst b/docs/PoC/net/ipv6/ipv6_FrameLoopback.rst new file mode 100644 index 00000000..8262fcc3 --- /dev/null +++ b/docs/PoC/net/ipv6/ipv6_FrameLoopback.rst @@ -0,0 +1,20 @@ + +ipv6_FrameLoopback +################## + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/ipv6/ipv6_FrameLoopback.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-74 + +Source file: `net/ipv6/ipv6_FrameLoopback.vhdl `_ + + + diff --git a/docs/PoC/net/ipv6/ipv6_RX.rst b/docs/PoC/net/ipv6/ipv6_RX.rst new file mode 100644 index 00000000..c364261b --- /dev/null +++ b/docs/PoC/net/ipv6/ipv6_RX.rst @@ -0,0 +1,20 @@ + +ipv6_RX +####### + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/ipv6/ipv6_RX.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-84 + +Source file: `net/ipv6/ipv6_RX.vhdl `_ + + + diff --git a/docs/PoC/net/ipv6/ipv6_TX.rst b/docs/PoC/net/ipv6/ipv6_TX.rst new file mode 100644 index 00000000..48dfb6ff --- /dev/null +++ b/docs/PoC/net/ipv6/ipv6_TX.rst @@ -0,0 +1,20 @@ + +ipv6_TX +####### + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/ipv6/ipv6_TX.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-84 + +Source file: `net/ipv6/ipv6_TX.vhdl `_ + + + diff --git a/docs/PoC/net/ipv6/ipv6_Wrapper.rst b/docs/PoC/net/ipv6/ipv6_Wrapper.rst new file mode 100644 index 00000000..20470586 --- /dev/null +++ b/docs/PoC/net/ipv6/ipv6_Wrapper.rst @@ -0,0 +1,20 @@ + +ipv6_Wrapper +############ + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/ipv6/ipv6_Wrapper.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-116 + +Source file: `net/ipv6/ipv6_Wrapper.vhdl `_ + + + diff --git a/docs/PoC/net/mac/index.rst b/docs/PoC/net/mac/index.rst new file mode 100644 index 00000000..88884649 --- /dev/null +++ b/docs/PoC/net/mac/index.rst @@ -0,0 +1,16 @@ + +mac +=== + +These are mac entities.... + +.. toctree:: + + mac_RX_DestMAC_Switch + mac_RX_SrcMAC_Filter + mac_RX_Type_Switch + mac_TX_SrcMAC_Prepender + mac_TX_DestMAC_Prepender + mac_TX_Type_Prepender + mac_FrameLoopback + mac_Wrapper diff --git a/docs/PoC/net/mac/mac_FrameLoopback.rst b/docs/PoC/net/mac/mac_FrameLoopback.rst new file mode 100644 index 00000000..9306aa6e --- /dev/null +++ b/docs/PoC/net/mac/mac_FrameLoopback.rst @@ -0,0 +1,20 @@ + +mac_FrameLoopback +################# + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/mac/mac_FrameLoopback.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-72 + +Source file: `net/mac/mac_FrameLoopback.vhdl `_ + + + diff --git a/docs/PoC/net/mac/mac_RX_DestMAC_Switch.rst b/docs/PoC/net/mac/mac_RX_DestMAC_Switch.rst new file mode 100644 index 00000000..f030f20b --- /dev/null +++ b/docs/PoC/net/mac/mac_RX_DestMAC_Switch.rst @@ -0,0 +1,20 @@ + +mac_RX_DestMAC_Switch +##################### + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/mac/mac_RX_DestMAC_Switch.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-67 + +Source file: `net/mac/mac_RX_DestMAC_Switch.vhdl `_ + + + diff --git a/docs/PoC/net/mac/mac_RX_SrcMAC_Filter.rst b/docs/PoC/net/mac/mac_RX_SrcMAC_Filter.rst new file mode 100644 index 00000000..5a167feb --- /dev/null +++ b/docs/PoC/net/mac/mac_RX_SrcMAC_Filter.rst @@ -0,0 +1,20 @@ + +mac_RX_SrcMAC_Filter +#################### + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/mac/mac_RX_SrcMAC_Filter.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-72 + +Source file: `net/mac/mac_RX_SrcMAC_Filter.vhdl `_ + + + diff --git a/docs/PoC/net/mac/mac_RX_Type_Switch.rst b/docs/PoC/net/mac/mac_RX_Type_Switch.rst new file mode 100644 index 00000000..895056a6 --- /dev/null +++ b/docs/PoC/net/mac/mac_RX_Type_Switch.rst @@ -0,0 +1,20 @@ + +mac_RX_Type_Switch +################## + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/mac/mac_RX_Type_Switch.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-74 + +Source file: `net/mac/mac_RX_Type_Switch.vhdl `_ + + + diff --git a/docs/PoC/net/mac/mac_TX_DestMAC_Prepender.rst b/docs/PoC/net/mac/mac_TX_DestMAC_Prepender.rst new file mode 100644 index 00000000..84ae9d79 --- /dev/null +++ b/docs/PoC/net/mac/mac_TX_DestMAC_Prepender.rst @@ -0,0 +1,20 @@ + +mac_TX_DestMAC_Prepender +######################## + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/mac/mac_TX_DestMAC_Prepender.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-65 + +Source file: `net/mac/mac_TX_DestMAC_Prepender.vhdl `_ + + + diff --git a/docs/PoC/net/mac/mac_TX_SrcMAC_Prepender.rst b/docs/PoC/net/mac/mac_TX_SrcMAC_Prepender.rst new file mode 100644 index 00000000..c2dcf82c --- /dev/null +++ b/docs/PoC/net/mac/mac_TX_SrcMAC_Prepender.rst @@ -0,0 +1,20 @@ + +mac_TX_SrcMAC_Prepender +####################### + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/mac/mac_TX_SrcMAC_Prepender.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-69 + +Source file: `net/mac/mac_TX_SrcMAC_Prepender.vhdl `_ + + + diff --git a/docs/PoC/net/mac/mac_TX_Type_Prepender.rst b/docs/PoC/net/mac/mac_TX_Type_Prepender.rst new file mode 100644 index 00000000..fcb6f29e --- /dev/null +++ b/docs/PoC/net/mac/mac_TX_Type_Prepender.rst @@ -0,0 +1,20 @@ + +mac_TX_Type_Prepender +##################### + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/mac/mac_TX_Type_Prepender.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-69 + +Source file: `net/mac/mac_TX_Type_Prepender.vhdl `_ + + + diff --git a/docs/PoC/net/mac/mac_Wrapper.rst b/docs/PoC/net/mac/mac_Wrapper.rst new file mode 100644 index 00000000..16be2b8a --- /dev/null +++ b/docs/PoC/net/mac/mac_Wrapper.rst @@ -0,0 +1,20 @@ + +mac_Wrapper +########### + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/mac/mac_Wrapper.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-84 + +Source file: `net/mac/mac_Wrapper.vhdl `_ + + + diff --git a/docs/PoC/net/ndp/index.rst b/docs/PoC/net/ndp/index.rst new file mode 100644 index 00000000..f054b692 --- /dev/null +++ b/docs/PoC/net/ndp/index.rst @@ -0,0 +1,12 @@ + +ndp +=== + +These are ndp entities.... + +.. toctree:: + + ndp_DestinationCache + ndp_FSMQuery + ndp_NeighborCache + ndp_Wrapper diff --git a/docs/PoC/net/ndp/ndp_DestinationCache.rst b/docs/PoC/net/ndp/ndp_DestinationCache.rst new file mode 100644 index 00000000..b1ef4627 --- /dev/null +++ b/docs/PoC/net/ndp/ndp_DestinationCache.rst @@ -0,0 +1,20 @@ + +ndp_DestinationCache +#################### + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/ndp/ndp_DestinationCache.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-65 + +Source file: `net/ndp/ndp_DestinationCache.vhdl `_ + + + diff --git a/docs/PoC/net/ndp/ndp_FSMQuery.rst b/docs/PoC/net/ndp/ndp_FSMQuery.rst new file mode 100644 index 00000000..842125a4 --- /dev/null +++ b/docs/PoC/net/ndp/ndp_FSMQuery.rst @@ -0,0 +1,20 @@ + +ndp_FSMQuery +############ + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/ndp/ndp_FSMQuery.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-79 + +Source file: `net/ndp/ndp_FSMQuery.vhdl `_ + + + diff --git a/docs/PoC/net/ndp/ndp_NeighborCache.rst b/docs/PoC/net/ndp/ndp_NeighborCache.rst new file mode 100644 index 00000000..7b5647c5 --- /dev/null +++ b/docs/PoC/net/ndp/ndp_NeighborCache.rst @@ -0,0 +1,20 @@ + +ndp_NeighborCache +################# + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/ndp/ndp_NeighborCache.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-65 + +Source file: `net/ndp/ndp_NeighborCache.vhdl `_ + + + diff --git a/docs/PoC/net/ndp/ndp_Wrapper.rst b/docs/PoC/net/ndp/ndp_Wrapper.rst new file mode 100644 index 00000000..b7e5a34b --- /dev/null +++ b/docs/PoC/net/ndp/ndp_Wrapper.rst @@ -0,0 +1,20 @@ + +NDP_Wrapper +########### + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/ndp/ndp_Wrapper.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 43-65 + +Source file: `net/ndp/ndp_Wrapper.vhdl `_ + + + diff --git a/docs/PoC/net/net_FrameChecksum.rst b/docs/PoC/net/net_FrameChecksum.rst new file mode 100644 index 00000000..ed1530a3 --- /dev/null +++ b/docs/PoC/net/net_FrameChecksum.rst @@ -0,0 +1,20 @@ + +net_FrameChecksum +################# + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/net/net_FrameChecksum.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 41-72 + +Source file: `net/net_FrameChecksum.vhdl `_ + + + diff --git a/docs/PoC/net/net_FrameLoopback.rst b/docs/PoC/net/net_FrameLoopback.rst new file mode 100644 index 00000000..71e0148a --- /dev/null +++ b/docs/PoC/net/net_FrameLoopback.rst @@ -0,0 +1,20 @@ + +FrameLoopback +############# + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/net/net_FrameLoopback.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 41-65 + +Source file: `net/net_FrameLoopback.vhdl `_ + + + diff --git a/docs/PoC/net/net_FramePerformanceCounter.rst b/docs/PoC/net/net_FramePerformanceCounter.rst new file mode 100644 index 00000000..0ed18f58 --- /dev/null +++ b/docs/PoC/net/net_FramePerformanceCounter.rst @@ -0,0 +1,18 @@ + +LocalLink_PerformanceCounter +############################ + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/net/net_FramePerformanceCounter.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 11-35 + +Source file: `net/net_FramePerformanceCounter.vhdl `_ + + + diff --git a/docs/PoC/net/stack/index.rst b/docs/PoC/net/stack/index.rst new file mode 100644 index 00000000..21b64c1f --- /dev/null +++ b/docs/PoC/net/stack/index.rst @@ -0,0 +1,13 @@ + +stack +===== + +These are udp entities.... + +.. toctree:: + + stack_IPv4 + stack_IPv6 + stack_UDPv4 + stack_UDPv6 + stack_MAC diff --git a/docs/PoC/net/stack/stack_IPv4.rst b/docs/PoC/net/stack/stack_IPv4.rst new file mode 100644 index 00000000..fcf72f1a --- /dev/null +++ b/docs/PoC/net/stack/stack_IPv4.rst @@ -0,0 +1,9 @@ + +stack_IPv4 +^^^^^^^^^^ + +Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. +At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor +sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et +accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet + diff --git a/docs/PoC/net/stack/stack_IPv6.rst b/docs/PoC/net/stack/stack_IPv6.rst new file mode 100644 index 00000000..63a909b5 --- /dev/null +++ b/docs/PoC/net/stack/stack_IPv6.rst @@ -0,0 +1,9 @@ + +stack_IPv6 +^^^^^^^^^^ + +Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. +At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor +sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et +accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet + diff --git a/docs/PoC/net/stack/stack_MAC.rst b/docs/PoC/net/stack/stack_MAC.rst new file mode 100644 index 00000000..07c4237d --- /dev/null +++ b/docs/PoC/net/stack/stack_MAC.rst @@ -0,0 +1,9 @@ + +stack_MAC +^^^^^^^^^ + +Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. +At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor +sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et +accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet + diff --git a/docs/PoC/net/stack/stack_UDPv4.rst b/docs/PoC/net/stack/stack_UDPv4.rst new file mode 100644 index 00000000..fbaf061d --- /dev/null +++ b/docs/PoC/net/stack/stack_UDPv4.rst @@ -0,0 +1,20 @@ + +stack_UDPv4 +########### + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/stack/stack_UDPv4.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 44-111 + +Source file: `net/stack/stack_UDPv4.vhdl `_ + + + diff --git a/docs/PoC/net/stack/stack_UDPv6.rst b/docs/PoC/net/stack/stack_UDPv6.rst new file mode 100644 index 00000000..b2794cc3 --- /dev/null +++ b/docs/PoC/net/stack/stack_UDPv6.rst @@ -0,0 +1,9 @@ + +stack_UDPv6 +^^^^^^^^^^^ + +Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. +At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor +sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et +accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet + diff --git a/docs/PoC/net/udp/index.rst b/docs/PoC/net/udp/index.rst new file mode 100644 index 00000000..e58e8535 --- /dev/null +++ b/docs/PoC/net/udp/index.rst @@ -0,0 +1,12 @@ + +udp +=== + +These are udp entities.... + +.. toctree:: + + udp_RX + udp_TX + udp_FrameLoopback + udp_Wrapper diff --git a/docs/PoC/net/udp/udp_FrameLoopback.rst b/docs/PoC/net/udp/udp_FrameLoopback.rst new file mode 100644 index 00000000..eb379923 --- /dev/null +++ b/docs/PoC/net/udp/udp_FrameLoopback.rst @@ -0,0 +1,20 @@ + +udp_FrameLoopback +################# + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/udp/udp_FrameLoopback.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-77 + +Source file: `net/udp/udp_FrameLoopback.vhdl `_ + + + diff --git a/docs/PoC/net/udp/udp_RX.rst b/docs/PoC/net/udp/udp_RX.rst new file mode 100644 index 00000000..80d4854a --- /dev/null +++ b/docs/PoC/net/udp/udp_RX.rst @@ -0,0 +1,20 @@ + +udp_RX +###### + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/udp/udp_RX.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-95 + +Source file: `net/udp/udp_RX.vhdl `_ + + + diff --git a/docs/PoC/net/udp/udp_TX.rst b/docs/PoC/net/udp/udp_TX.rst new file mode 100644 index 00000000..9c8cdb84 --- /dev/null +++ b/docs/PoC/net/udp/udp_TX.rst @@ -0,0 +1,20 @@ + +udp_TX +###### + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/udp/udp_TX.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-78 + +Source file: `net/udp/udp_TX.vhdl `_ + + + diff --git a/docs/PoC/net/udp/udp_Wrapper.rst b/docs/PoC/net/udp/udp_Wrapper.rst new file mode 100644 index 00000000..01d8c187 --- /dev/null +++ b/docs/PoC/net/udp/udp_Wrapper.rst @@ -0,0 +1,20 @@ + +udp_Wrapper +########### + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/udp/udp_Wrapper.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-120 + +Source file: `net/udp/udp_Wrapper.vhdl `_ + + + diff --git a/docs/PoC/sim/index.rst b/docs/PoC/sim/index.rst new file mode 100644 index 00000000..4eb0873b --- /dev/null +++ b/docs/PoC/sim/index.rst @@ -0,0 +1,14 @@ + +Simulation Packages +################### + +.. toctree:: + + sim_types + sim_global.v93 + sim_global.v08 + sim_unprotected.v93 + sim_protected.v08 + sim_simulation.v93 + sim_simulation.v08 + sim_waveform diff --git a/docs/PoC/sim/sim_global.v08.rst b/docs/PoC/sim/sim_global.v08.rst new file mode 100644 index 00000000..f9bbcd5a --- /dev/null +++ b/docs/PoC/sim/sim_global.v08.rst @@ -0,0 +1,9 @@ + +sim_global (VHDL-2008) +^^^^^^^^^^^^^^^^^^^^^^ + +Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. +At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor +sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et +accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet + diff --git a/docs/PoC/sim/sim_global.v93.rst b/docs/PoC/sim/sim_global.v93.rst new file mode 100644 index 00000000..170726a9 --- /dev/null +++ b/docs/PoC/sim/sim_global.v93.rst @@ -0,0 +1,9 @@ + +sim_global (VHDL-93) +^^^^^^^^^^^^^^^^^^^^ + +Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. +At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor +sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et +accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet + diff --git a/docs/PoC/sim/sim_protected.v08.rst b/docs/PoC/sim/sim_protected.v08.rst new file mode 100644 index 00000000..779ce715 --- /dev/null +++ b/docs/PoC/sim/sim_protected.v08.rst @@ -0,0 +1,9 @@ + +sim_protected (VHDL-2008) +^^^^^^^^^^^^^^^^^^^^^^^^^ + +Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. +At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor +sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et +accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet + diff --git a/docs/PoC/sim/sim_simulation.v08.rst b/docs/PoC/sim/sim_simulation.v08.rst new file mode 100644 index 00000000..9856c2a5 --- /dev/null +++ b/docs/PoC/sim/sim_simulation.v08.rst @@ -0,0 +1,9 @@ + +simulation (VHDL-2008) +^^^^^^^^^^^^^^^^^^^^^^ + +Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. +At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor +sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et +accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet + diff --git a/docs/PoC/sim/sim_simulation.v93.rst b/docs/PoC/sim/sim_simulation.v93.rst new file mode 100644 index 00000000..862e246f --- /dev/null +++ b/docs/PoC/sim/sim_simulation.v93.rst @@ -0,0 +1,9 @@ + +simulation (VHDL-93) +^^^^^^^^^^^^^^^^^^^^ + +Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. +At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor +sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et +accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet + diff --git a/docs/PoC/sim/sim_types.rst b/docs/PoC/sim/sim_types.rst new file mode 100644 index 00000000..921587f4 --- /dev/null +++ b/docs/PoC/sim/sim_types.rst @@ -0,0 +1,9 @@ + +sim_types +^^^^^^^^^ + +Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. +At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor +sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et +accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet + diff --git a/docs/PoC/sim/sim_unprotected.v93.rst b/docs/PoC/sim/sim_unprotected.v93.rst new file mode 100644 index 00000000..2b7181ca --- /dev/null +++ b/docs/PoC/sim/sim_unprotected.v93.rst @@ -0,0 +1,9 @@ + +sim_unprotected (VHDL-93) +^^^^^^^^^^^^^^^^^^^^^^^^^ + +Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. +At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor +sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et +accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet + diff --git a/docs/PoC/sim/sim_waveform.rst b/docs/PoC/sim/sim_waveform.rst new file mode 100644 index 00000000..9c6d656d --- /dev/null +++ b/docs/PoC/sim/sim_waveform.rst @@ -0,0 +1,9 @@ + +sim_waveform +^^^^^^^^^^^^ + +Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. +At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor +sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et +accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet + diff --git a/docs/PoC/sort/index.rst b/docs/PoC/sort/index.rst new file mode 100644 index 00000000..c9993826 --- /dev/null +++ b/docs/PoC/sort/index.rst @@ -0,0 +1,31 @@ + +sort +==== + +These are sorting entities.... + +**Sub-Namespaces** + + * :doc:`PoC.sort.sortnet ` + +**Entities** + + * :doc:`PoC.sort.ExpireList ` + * :doc:`PoC.sort.InsertSort ` + * :doc:`PoC.sort.LeastFrequentlyUsed ` + * :doc:`PoC.sort.lru_cache ` + * :doc:`PoC.sort.lru_list ` + +.. toctree:: + :hidden: + + sortnet/index + +.. toctree:: + :hidden: + + sort_ExpireList + sort_InsertSort + sort_LeastFrequentlyUsed + sort_lru_cache + sort_lru_list diff --git a/docs/PoC/sort/sort_ExpireList.rst b/docs/PoC/sort/sort_ExpireList.rst new file mode 100644 index 00000000..f73f680c --- /dev/null +++ b/docs/PoC/sort/sort_ExpireList.rst @@ -0,0 +1,20 @@ + +list_expire +########### + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/sort/sort_ExpireList.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-61 + +Source file: `sort/sort_ExpireList.vhdl `_ + + + diff --git a/docs/PoC/sort/sort_InsertSort.rst b/docs/PoC/sort/sort_InsertSort.rst new file mode 100644 index 00000000..8bcb56f4 --- /dev/null +++ b/docs/PoC/sort/sort_InsertSort.rst @@ -0,0 +1,20 @@ + +list_lru_systolic +################# + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/sort/sort_InsertSort.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 44-64 + +Source file: `sort/sort_InsertSort.vhdl `_ + + + diff --git a/docs/PoC/sort/sort_LeastFrequentlyUsed.rst b/docs/PoC/sort/sort_LeastFrequentlyUsed.rst new file mode 100644 index 00000000..ac1d9ea8 --- /dev/null +++ b/docs/PoC/sort/sort_LeastFrequentlyUsed.rst @@ -0,0 +1,20 @@ + +sort_LeastFrequentlyUsed +######################## + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/sort/sort_LeastFrequentlyUsed.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 36-53 + +Source file: `sort/sort_LeastFrequentlyUsed.vhdl `_ + + + diff --git a/docs/PoC/sort/sort_lru_cache.rst b/docs/PoC/sort/sort_lru_cache.rst new file mode 100644 index 00000000..870aaf75 --- /dev/null +++ b/docs/PoC/sort/sort_lru_cache.rst @@ -0,0 +1,34 @@ + +sort_lru_cache +############## + +This is an optimized implementation of ``sort_lru_list`` to be used for caches. +Only keys are stored within this list, and these keys are the index of the +cache lines. The list initially contains all indizes from 0 to ELEMENTS-1. +The least-recently used index ``KeyOut`` is always valid. + +The first outputed least-recently used index will be ELEMENTS-1. + +The inputs ``Insert``, ``Free``, ``KeyIn``, and ``Reset`` are synchronous to the +rising-edge of the clock ``clock``. All control signals are high-active. + +Supported operations: + * **Insert:** Mark index ``KeyIn`` as recently used, e.g., when a cache-line + was accessed. + * **Free:** Mark index ``KeyIn`` as least-recently used. Apply this operation, + when a cache-line gets invalidated. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/sort/sort_lru_cache.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 56-70 + +Source file: `sort/sort_lru_cache.vhdl `_ + + + diff --git a/docs/PoC/sort/sort_lru_list.rst b/docs/PoC/sort/sort_lru_list.rst new file mode 100644 index 00000000..8a199844 --- /dev/null +++ b/docs/PoC/sort/sort_lru_list.rst @@ -0,0 +1,32 @@ + +sort_lru_list +############# + +List storing ``(key, value)`` pairs. The least-recently inserted pair is +outputed on ``DataOut`` if ``Valid = '1'``. If ``Valid = '0'``, then the list +empty. + +The inputs ``Insert``, ``Remove``, ``DataIn``, and ``Reset`` are synchronous +to the rising-edge of the clock ``clock``. All control signals are high-active. + +Supported operations: + * **Insert:** Insert ``DataIn`` as recently used ``(key, value)`` pair. If + key is already within the list, then the corresponding value is updated and + the pair is moved to the recently used position. + * **Remove:** Remove ``(key, value)`` pair with the given key. The list is not + modified if key is not within the list. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/sort/sort_lru_list.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 55-74 + +Source file: `sort/sort_lru_list.vhdl `_ + + + diff --git a/docs/PoC/sort/sortnet/index.rst b/docs/PoC/sort/sortnet/index.rst new file mode 100644 index 00000000..e62cee53 --- /dev/null +++ b/docs/PoC/sort/sortnet/index.rst @@ -0,0 +1,26 @@ + +sortnet +======== + +This sub-namespace contains sorting network implementations. + +**Entities** + + * :doc:`PoC.sort.sortnet.BitonicSort ` + * :doc:`PoC.sort.sortnet.MergeSort_Streamed ` + * :doc:`PoC.sort.sortnet.OddEvenMergeSort ` + * :doc:`PoC.sort.sortnet.OddEvenSort ` + * :doc:`PoC.sort.sortnet.Stream_Adapter ` + * :doc:`PoC.sort.sortnet.Stream_Adapter2 ` + * :doc:`PoC.sort.sortnet.Transform ` + +.. toctree:: + :hidden: + + sortnet_BitonicSort + sortnet_MergeSort_Streamed + sortnet_OddEvenMergeSort + sortnet_OddEvenSort + sortnet_Stream_Adapter + sortnet_Stream_Adapter2 + sortnet_Transform diff --git a/docs/PoC/sort/sortnet/sortnet_BitonicSort.rst b/docs/PoC/sort/sortnet/sortnet_BitonicSort.rst new file mode 100644 index 00000000..01d04f8e --- /dev/null +++ b/docs/PoC/sort/sortnet/sortnet_BitonicSort.rst @@ -0,0 +1,20 @@ + +sortnet_BitonicSort +################### + +This sorting network uses the *bitonic sort* algorithm. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/sort/sortnet/sortnet_BitonicSort.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 43-69 + +Source file: `sort/sortnet/sortnet_BitonicSort.vhdl `_ + + + diff --git a/docs/PoC/sort/sortnet/sortnet_MergeSort_Streamed.rst b/docs/PoC/sort/sortnet/sortnet_MergeSort_Streamed.rst new file mode 100644 index 00000000..88d64260 --- /dev/null +++ b/docs/PoC/sort/sortnet/sortnet_MergeSort_Streamed.rst @@ -0,0 +1,20 @@ + +sortnet_MergeSort_Streamed +########################## + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/sort/sortnet/sortnet_MergeSort_Streamed.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 41-68 + +Source file: `sort/sortnet/sortnet_MergeSort_Streamed.vhdl `_ + + + diff --git a/docs/PoC/sort/sortnet/sortnet_OddEvenMergeSort.rst b/docs/PoC/sort/sortnet/sortnet_OddEvenMergeSort.rst new file mode 100644 index 00000000..88007f23 --- /dev/null +++ b/docs/PoC/sort/sortnet/sortnet_OddEvenMergeSort.rst @@ -0,0 +1,20 @@ + +sortnet_OddEvenMergeSort +######################## + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/sort/sortnet/sortnet_OddEvenMergeSort.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 43-69 + +Source file: `sort/sortnet/sortnet_OddEvenMergeSort.vhdl `_ + + + diff --git a/docs/PoC/sort/sortnet/sortnet_OddEvenSort.rst b/docs/PoC/sort/sortnet/sortnet_OddEvenSort.rst new file mode 100644 index 00000000..32a53603 --- /dev/null +++ b/docs/PoC/sort/sortnet/sortnet_OddEvenSort.rst @@ -0,0 +1,20 @@ + +sortnet_OddEvenSort +################### + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/sort/sortnet/sortnet_OddEvenSort.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-68 + +Source file: `sort/sortnet/sortnet_OddEvenSort.vhdl `_ + + + diff --git a/docs/PoC/sort/sortnet/sortnet_Stream_Adapter.rst b/docs/PoC/sort/sortnet/sortnet_Stream_Adapter.rst new file mode 100644 index 00000000..21e0f97a --- /dev/null +++ b/docs/PoC/sort/sortnet/sortnet_Stream_Adapter.rst @@ -0,0 +1,20 @@ + +sortnet_Stream_Adapter +###################### + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/sort/sortnet/sortnet_Stream_Adapter.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-68 + +Source file: `sort/sortnet/sortnet_Stream_Adapter.vhdl `_ + + + diff --git a/docs/PoC/sort/sortnet/sortnet_Stream_Adapter2.rst b/docs/PoC/sort/sortnet/sortnet_Stream_Adapter2.rst new file mode 100644 index 00000000..6d893c7e --- /dev/null +++ b/docs/PoC/sort/sortnet/sortnet_Stream_Adapter2.rst @@ -0,0 +1,20 @@ + +sortnet_Stream_Adapter2 +####################### + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/sort/sortnet/sortnet_Stream_Adapter2.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-76 + +Source file: `sort/sortnet/sortnet_Stream_Adapter2.vhdl `_ + + + diff --git a/docs/PoC/sort/sortnet/sortnet_Transform.rst b/docs/PoC/sort/sortnet/sortnet_Transform.rst new file mode 100644 index 00000000..503e4450 --- /dev/null +++ b/docs/PoC/sort/sortnet/sortnet_Transform.rst @@ -0,0 +1,20 @@ + +sortnet_Transform +################# + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/sort/sortnet/sortnet_Transform.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 41-61 + +Source file: `sort/sortnet/sortnet_Transform.vhdl `_ + + + diff --git a/docs/PoC/xil/index.rst b/docs/PoC/xil/index.rst new file mode 100644 index 00000000..9d89b376 --- /dev/null +++ b/docs/PoC/xil/index.rst @@ -0,0 +1,42 @@ + +xil +=== + +This namespace is for Xilinx specific modules. + +**Sub-Namespaces** + + * :doc:`PoC.xil.mig ` + * :doc:`PoC.xil.reconfig ` + +**Entities** + + * :doc:`PoC.xil.BSCAN ` + * :doc:`PoC.xil.ChipScopeICON ` + * :doc:`PoC.xil.DRP_BusMux ` + * :doc:`PoC.xil.DRP_BusSync ` + * :doc:`PoC.xil.ICAP ` + * :doc:`PoC.xil.Reconfigurator ` + * :doc:`PoC.xil.SystemMonitor ` + * :doc:`PoC.xil.SystemMonitor_Virtex6 ` + * :doc:`PoC.xil.SystemMonitor_Series7 ` + + +.. toctree:: + :hidden: + + mig/index + reconfig/index + +.. toctree:: + :hidden: + + xil_BSCAN + xil_ChipScopeICON + xil_DRP_BusMux + xil_DRP_BusSync + xil_ICAP + xil_Reconfigurator + xil_SystemMonitor + xil_SystemMonitor_Virtex6 + xil_SystemMonitor_Series7 diff --git a/docs/PoC/xil/mig/index.rst b/docs/PoC/xil/mig/index.rst new file mode 100644 index 00000000..001fd816 --- /dev/null +++ b/docs/PoC/xil/mig/index.rst @@ -0,0 +1,23 @@ + +mig +=== + +The namespace ``PoC.xil.mig`` offers pre-configured memory controllers generated +with Xilinx's Memory Interface Generator (MIG). + +* **for Spartan-6 boards:** + + * :doc:`mig_Atlys_1x128 ` - A DDR2 memory controller for the Digilent Atlys board. + +* **for Kintex-7 boards:** + + * :doc:`mig_KC705_MT8JTF12864HZ_1G6 ` - A DDR3 memory controller for the Xilinx KC705 board. + +* **for Virtex-7 boards:** + + +.. toctree:: + :hidden: + + mig_Atlys_1x128 + mig_KC705_MT8JTF12864HZ_1G6 diff --git a/docs/PoC/xil/mig/mig_Atlys_1x128.rst b/docs/PoC/xil/mig/mig_Atlys_1x128.rst new file mode 100644 index 00000000..337b1f3a --- /dev/null +++ b/docs/PoC/xil/mig/mig_Atlys_1x128.rst @@ -0,0 +1,19 @@ + +mig_Atlys_1x128 +############### + +This DDR2 memory controller is pre-configured for the Digilent Atlys development +board. The board is equipped with a single 1 GiBit DDR2 memory chip (128 MiByte) +from MIRA (MIRA P3R1GE3EGF G8E DDR2). + +Run the following two steps to create the IP core: + +1. Generate the source files from the IP core using Xilinx MIG and afterwards patch them |br| + ``PS> .\poc.ps1 coregen PoC.xil.mig.Atlys_1x128 --board=Atlys`` + +2. Compile the patched sources into a ready to use netlist (\*.ngc) and constraint file (\*.ucf) |br| + ``PS> .\poc.ps1 xst PoC.xil.mig.Atlys_1x128 --board=Atlys`` + +.. seealso:: + :doc:`Using PoC -> Synthesis ` + For how to run Core Generator and XST from PoC. diff --git a/docs/PoC/xil/mig/mig_KC705_MT8JTF12864HZ_1G6.rst b/docs/PoC/xil/mig/mig_KC705_MT8JTF12864HZ_1G6.rst new file mode 100644 index 00000000..5e66ef52 --- /dev/null +++ b/docs/PoC/xil/mig/mig_KC705_MT8JTF12864HZ_1G6.rst @@ -0,0 +1,20 @@ + +mig_KC705_MT8JTF12864HZ_1G6 +########################### + +This DDR2 memory controller is pre-configured for the Xilinx KC705 development +board. The board is equipped with a single 1 GiBit DDR3 memory chip (128 MiByte) +from Micron Technology (MT8JTF12864HZ-1G6G1). + +Run the following two steps to create the IP core: + +1. Generate the source files from the IP core using Xilinx MIG and afterwards patch them |br| + ``PS> .\poc.ps1 coregen PoC.xil.mig.KC705_MT8JTF12864HZ_1G6 --board=KC705`` + +2. Compile the patched sources into a ready to use netlist (\*.ngc) and constraint file (\*.ucf) |br| + ``PS> .\poc.ps1 xst PoC.xil.mig.KC705_MT8JTF12864HZ_1G6 --board=KC705`` + +.. seealso:: + :doc:`Using PoC -> Synthesis ` + For how to run Core Generator and XST from PoC. + diff --git a/docs/PoC/xil/reconfig/index.rst b/docs/PoC/xil/reconfig/index.rst new file mode 100644 index 00000000..0f84f4d5 --- /dev/null +++ b/docs/PoC/xil/reconfig/index.rst @@ -0,0 +1,16 @@ + +reconfig +======== + +These are reconfig entities.... + +**Entities** + + * :doc:`PoC.xil.reconfig.icap_fsm ` + * :doc:`PoC.xil.reconfig.icap_wrapper ` + +.. toctree:: + :hidden: + + reconfig_icap_fsm + reconfig_icap_wrapper diff --git a/docs/PoC/xil/reconfig/reconfig_icap_fsm.rst b/docs/PoC/xil/reconfig/reconfig_icap_fsm.rst new file mode 100644 index 00000000..3a53c1b4 --- /dev/null +++ b/docs/PoC/xil/reconfig/reconfig_icap_fsm.rst @@ -0,0 +1,24 @@ + +reconfig_icap_fsm +################# + +This module parses the data stream to the Xilinx "Internal Configuration Access Port" (ICAP) +primitives to generate control signals. Tested on: + +* Virtex-6 +* Virtex-7 + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/xil/reconfig/reconfig_icap_fsm.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-63 + +Source file: `xil/reconfig/reconfig_icap_fsm.vhdl `_ + + + diff --git a/docs/PoC/xil/reconfig/reconfig_icap_wrapper.rst b/docs/PoC/xil/reconfig/reconfig_icap_wrapper.rst new file mode 100644 index 00000000..baabe148 --- /dev/null +++ b/docs/PoC/xil/reconfig/reconfig_icap_wrapper.rst @@ -0,0 +1,23 @@ + +reconfig_icap_wrapper +##################### + +This module was designed to connect the Xilinx "Internal Configuration Access Port" (ICAP) +to a PCIe endpoint on a Dini board. Tested on: + +tbd + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/xil/reconfig/reconfig_icap_wrapper.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 43-68 + +Source file: `xil/reconfig/reconfig_icap_wrapper.vhdl `_ + + + diff --git a/docs/PoC/xil/xil_BSCAN.rst b/docs/PoC/xil/xil_BSCAN.rst new file mode 100644 index 00000000..2eb45615 --- /dev/null +++ b/docs/PoC/xil/xil_BSCAN.rst @@ -0,0 +1,25 @@ + +xil_BSCAN +######### + +This module wraps Xilinx "Boundary Scan" (JTAG) primitives in a generic +module. |br| +Supported devices are: + * Spartan-3, Spartan-6 + * Virtex-5, Virtex-6 + * Series-7 (Artix-7, Kintex-7, Virtex-7, Zynq-7000) + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/xil/xil_BSCAN.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 47-65 + +Source file: `xil/xil_BSCAN.vhdl `_ + + + diff --git a/docs/PoC/xil/xil_ChipScopeICON.rst b/docs/PoC/xil/xil_ChipScopeICON.rst new file mode 100644 index 00000000..ee254a98 --- /dev/null +++ b/docs/PoC/xil/xil_ChipScopeICON.rst @@ -0,0 +1,38 @@ + +xil_ChipScopeICON +################# + +This module wraps 15 ChipScope ICON IP core netlists generated from ChipScope +ICON xco files. The generic parameter ``PORTS`` selects the apropriate ICON +instance with 1 to 15 ICON ``ControlBus`` ports. Each ``ControlBus`` port is +of type ``T_XIL_CHIPSCOPE_CONTROL`` and of mode ``inout``. + +.. rubric:: Compile required CoreGenerator IP Cores to Netlists with PoC + +Please use the provided Xilinx ISE compile command ``ise`` in PoC to recreate +the needed source and netlist files on your local machine. + +.. code-block:: PowerShell + + cd PoCRoot + .\poc.ps1 ise PoC.xil.ChipScopeICON --board=KC705 + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/xil/xil_ChipScopeICON.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 56-63 + +Source file: `xil/xil_ChipScopeICON.vhdl `_ + +.. seealso:: + + :doc:`Using PoC -> Synthesis ` + For how to run synthesis with PoC and CoreGenerator. + + + diff --git a/docs/PoC/xil/xil_DRP_BusMux.rst b/docs/PoC/xil/xil_DRP_BusMux.rst new file mode 100644 index 00000000..f5d79d77 --- /dev/null +++ b/docs/PoC/xil/xil_DRP_BusMux.rst @@ -0,0 +1,20 @@ + +xil_DRP_BusMux +############## + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/xil/xil_DRP_BusMux.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-65 + +Source file: `xil/xil_DRP_BusMux.vhdl `_ + + + diff --git a/docs/PoC/xil/xil_DRP_BusSync.rst b/docs/PoC/xil/xil_DRP_BusSync.rst new file mode 100644 index 00000000..31baf6b0 --- /dev/null +++ b/docs/PoC/xil/xil_DRP_BusSync.rst @@ -0,0 +1,20 @@ + +xil_DRP_BusSync +############### + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/xil/xil_DRP_BusSync.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 40-58 + +Source file: `xil/xil_DRP_BusSync.vhdl `_ + + + diff --git a/docs/PoC/xil/xil_ICAP.rst b/docs/PoC/xil/xil_ICAP.rst new file mode 100644 index 00000000..b445d6a9 --- /dev/null +++ b/docs/PoC/xil/xil_ICAP.rst @@ -0,0 +1,25 @@ + +xil_ICAP +######## + +This module wraps Xilinx "Internal Configuration Access Port" (ICAP) primitives in a generic +module. |br| +Supported devices are: + * Spartan-6 + * Virtex-4, Virtex-5, Virtex-6 + * Series-7 (Artix-7, Kintex-7, Virtex-7, Zynq-7000) + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/xil/xil_ICAP.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 47-66 + +Source file: `xil/xil_ICAP.vhdl `_ + + + diff --git a/docs/PoC/xil/xil_Reconfigurator.rst b/docs/PoC/xil/xil_Reconfigurator.rst new file mode 100644 index 00000000..99f35b93 --- /dev/null +++ b/docs/PoC/xil/xil_Reconfigurator.rst @@ -0,0 +1,28 @@ + +xil_Reconfigurator +################## + +Many complex primitives in a Xilinx device offer a Dynamic Reconfiguration +Port (DRP) to reconfigure a primitive at runtime without reconfiguring the +whole FPGA. + +This module is a DRP master that can be pre-configured at compile time with +different configuration sets. The configuration sets are mapped into a ROM. +The user can select a stored configuration with ``ConfigSelect``. Sending a +strobe to ``Reconfig`` will start the reconfiguration process. The operation +completes with another strobe on ``ReconfigDone``. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/xil/xil_Reconfigurator.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 51-72 + +Source file: `xil/xil_Reconfigurator.vhdl `_ + + + diff --git a/docs/PoC/xil/xil_SystemMonitor.rst b/docs/PoC/xil/xil_SystemMonitor.rst new file mode 100644 index 00000000..43a64195 --- /dev/null +++ b/docs/PoC/xil/xil_SystemMonitor.rst @@ -0,0 +1,38 @@ + +xil_SystemMonitor +################# + +This module generates a PWM signal for a 3-pin (transistor controlled) or +4-pin fan header. The FPGAs temperature is read from device specific system +monitors (normal, user temperature, over temperature). + +**For example the Xilinx System Monitors are configured as follows:** + +.. code-block:: none + + | /-----\ + Temp_ov on=80 | - - - - - - /-------/ \ + | / | \ + Temp_ov off=60 | - - - - - / - - - - | - - - - \----\ + | / | |\ + | / | | \ + Temp_us on=35 | - /---/ | | \ + Temp_us off=30 | - / - -|- - - - - - |- - - - - - - |- -\------\ + | / | | | \ + ----------------|--------|------------|--------------|-----------|-------- + pwm = | min | medium | max | medium | min + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/xil/xil_SystemMonitor.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 62-73 + +Source file: `xil/xil_SystemMonitor.vhdl `_ + + + diff --git a/docs/PoC/xil/xil_SystemMonitor_Series7.rst b/docs/PoC/xil/xil_SystemMonitor_Series7.rst new file mode 100644 index 00000000..23d050ce --- /dev/null +++ b/docs/PoC/xil/xil_SystemMonitor_Series7.rst @@ -0,0 +1,37 @@ + +xil_SystemMonitor_Series7 +######################### + +This module wraps a Series-7 XADC to report if preconfigured temperature values +are overrun. The XADC was formerly known as "System Monitor". + +.. rubric:: Temperature Curve + +.. code-block:: none + + | /-----\ + Temp_ov on=80 | - - - - - - /-------/ \ + | / | \ + Temp_ov off=60 | - - - - - / - - - - | - - - - \----\ + | / | |\ + | / | | \ + Temp_us on=35 | - /---/ | | \ + Temp_us off=30 | - / - -|- - - - - - |- - - - - - - |- -\------\ + | / | | | \ + ----------------|--------|------------|--------------|-----------|-------- + pwm = | min | medium | max | medium | min + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/xil/xil_SystemMonitor_Series7.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 56-66 + +Source file: `xil/xil_SystemMonitor_Series7.vhdl `_ + + + diff --git a/docs/PoC/xil/xil_SystemMonitor_Virtex6.rst b/docs/PoC/xil/xil_SystemMonitor_Virtex6.rst new file mode 100644 index 00000000..a56624dc --- /dev/null +++ b/docs/PoC/xil/xil_SystemMonitor_Virtex6.rst @@ -0,0 +1,37 @@ + +xil_SystemMonitor_Virtex6 +######################### + +This module wraps a Virtex-6 System Monitor primitive to report if preconfigured +temperature values are overrun. + +.. rubric:: Temperature Curve + +.. code-block:: none + + | /-----\ + Temp_ov on=80 | - - - - - - /-------/ \ + | / | \ + Temp_ov off=60 | - - - - - / - - - - | - - - - \----\ + | / | |\ + | / | | \ + Temp_us on=35 | - /---/ | | \ + Temp_us off=30 | - / - -|- - - - - - |- - - - - - - |- -\------\ + | / | | | \ + ----------------|--------|------------|--------------|-----------|-------- + pwm = | min | medium | max | medium | min + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/xil/xil_SystemMonitor_Virtex6.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 56-66 + +Source file: `xil/xil_SystemMonitor_Virtex6.vhdl `_ + + + diff --git a/docs/QuickStart.rst b/docs/QuickStart.rst new file mode 100644 index 00000000..8e12e863 --- /dev/null +++ b/docs/QuickStart.rst @@ -0,0 +1,272 @@ + +Quick Start Guide +################# + +This **quick start guide** gives a fast and simple introduction into PoC. All +topics can be found in the :doc:`Using PoC ` section with much +more details and examples. + +.. contents:: Contents of this Page + :local: + + +Requirements and Dependencies +***************************** + +The PoC-Library comes with some scripts to ease most of the common tasks, like +running testbenches or generating IP cores. PoC uses Python 3 as a platform +independent scripting environment. All Python scripts are wrapped in Bash or +PowerShell scripts, to hide some platform specifics of Darwin, Linux or Windows. +See :doc:`/UsingPoC/Requirements` for further details. + + +.. rubric:: PoC requires: + +* A :doc:`supported synthesis tool chain `, if you want to synthezise IP cores. +* A :doc:`supported simulator too chain `, if you want to simulate IP cores. +* The **Python 3** programming language and runtime, if you want to use PoC's infrastructure. +* A shell to execute shell scripts: + + * **Bash** on Linux and OS X + * **PowerShell** on Windows + + +.. rubric:: PoC optionally requires: + +* **Git command line** tools or +* **Git User Interface**, if you want to check out the latest 'master' or 'release' branch. + + +.. rubric:: PoC depends on third part libraries: + +* `Cocotb `_ |br| + A coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python. +* `OS-VVM `_ |br| + Open Source VHDL Verification Methodology. +* `VUnit `_ |br| + An unit testing framework for VHDL. + +All dependencies are available as GitHub repositories and are linked to +PoC as Git submodules into the `PoCRoot\\lib `_ +directory. See :doc:`Third Party Libraries ` for more details on these libraries. + + +Download +******** + +The PoC-Library can be downloaded as a `zip-file `_ +(latest 'master' branch), cloned with ``git clone`` or embedded with +``git submodule add`` from GitHub. GitHub offers HTTPS and SSH as transfer +protocols. See the :doc:`Download ` page for further +details. The installation directory is referred to as ``PoCRoot``. + ++----------+---------------------------------------------------------------------+ +| Protocol | Git Clone Command | ++==========+=====================================================================+ +| HTTPS | ``git clone --recursive https://github.com/VLSI-EDA/PoC.git PoC`` | ++----------+---------------------------------------------------------------------+ +| SSH | ``git clone --recursive ssh://git@github.com:VLSI-EDA/PoC.git PoC`` | ++----------+---------------------------------------------------------------------+ + + +Configuring PoC on a Local System +********************************* + +To explore PoC's full potential, it's required to configure some paths and +synthesis or simulation tool chains. The following commands start a guided +configuration process. Please follow the instructions on screen. It's possible +to relaunch the process at any time, for example to register new tools or to +update tool versions. See :doc:`Configuration ` for +more details. Run the following command line instructions to configure PoC on +your local system: + +.. code-block:: PowerShell + + cd PoCRoot + .\poc.ps1 configure + +Use the keyboard buttons: :kbd:`Y` to accept, :kbd:`N` to decline, :kbd:`P` to +skip/pass a step and :kbd:`Return` to accept a default value displayed in brackets. + + +Integration +*********** + +The PoC-Library is meant to be integrated into other HDL projects. Therefore +it's recommended to create a library folder and add the PoC-Library as a Git +submodule. After the repository linking is done, some short configuration +steps are required to setup paths, tool chains and the target platform. The +following command line instructions show a short example on how to integrate +PoC. + +.. rubric:: 1. Adding the Library as a Git submodule + +The following command line instructions will create the folder ``lib\PoC\`` and +clone the PoC-Library as a Git `submodule `_ +into that folder. ``ProjectRoot`` is the directory of the hosting Git. A detailed +list of steps can be found at :doc:`Integration `. + +.. code-block:: powershell + + cd ProjectRoot + mkdir lib | cd + git submodule add https://github.com:VLSI-EDA/PoC.git PoC + cd PoC + git remote rename origin github + cd ..\.. + git add .gitmodules lib\PoC + git commit -m "Added new git submodule PoC in 'lib\PoC' (PoC-Library)." + +.. rubric:: 2. Configuring PoC + +The PoC-Library should be configured to explore its full potential. See +:doc:`Configuration ` for more details. The +following command lines will start the configuration process: + +.. code-block:: powershell + + cd ProjectRoot + .\lib\PoC\poc.ps1 configure + + +.. rubric:: 3. Creating PoC's ``my_config.vhdl`` and ``my_project.vhdl`` Files + +The PoC-Library needs two VHDL files for its configuration. These files are +used to determine the most suitable implementation depending on the provided +target information. Copy the following two template files into your project's +source folder. Rename these files to \*.vhdl and configure the VHDL constants +in the files: + +.. code-block:: powershell + + cd ProjectRoot + cp lib\PoC\src\common\my_config.vhdl.template src\common\my_config.vhdl + cp lib\PoC\src\common\my_project.vhdl.template src\common\my_project.vhdl + +`my_config.vhdl `_ defines two global constants, which need to be adjusted: + +.. code-block:: vhdl + + constant MY_BOARD : string := "CHANGE THIS"; -- e.g. Custom, ML505, KC705, Atlys + constant MY_DEVICE : string := "CHANGE THIS"; -- e.g. None, XC5VLX50T-1FF1136, EP2SGX90FF1508C3 + +`my_project.vhdl `_ +also defines two global constants, which need to be adjusted: + +.. code-block:: vhdl + + constant MY_PROJECT_DIR : string := "CHANGE THIS"; -- e.g. d:/vhdl/myproject/, /home/me/projects/myproject/" + constant MY_OPERATING_SYSTEM : string := "CHANGE THIS"; -- e.g. WINDOWS, LINUX + +Further informations are provided at +:doc:`Creating my_config/my_project.vhdl `. + +.. rubric:: 4. Adding PoC's Common Packages to a Synthesis or Simulation Project + +PoC is shipped with a set of common packages, which are used by most of its +modules. These packages are stored in the ``PoCRoot\src\common`` directory. +PoC also provides a VHDL context in ``common.vhdl`` , which can be used to +reference all packages at once. + + +.. rubric:: 5. Adding PoC's Simulation Packages to a Simulation Project + +Simulation projects additionally require PoC's simulation helper packages, which +are located in the ``PoCRoot\src\sim`` directory. Because some VHDL version are +incompatible among each other, PoC uses version suffixes like ``*.v93.vhdl`` or +``*.v08.vhdl`` in the file name to denote the supported VHDL version of a file. + + +.. rubric:: 6. Compiling Shipped IP Cores + +Some IP Cores are shipped are pre-configured vendor IP Cores. If such IP cores +shall be used in a HDL project, it's recommended to use PoC to create, compile +and if needed patch these IP cores. See :doc:`Synthesis ` +for more details. + + +Run a Simulation +**************** + +The following quick example uses the GHDL Simulator to analyze, elaborate and +simulate a testbench for the module ``arith_prng`` (Pseudo Random Number +Generator - PRNG). The VHDL file ``arith_prng.vhdl`` is located at +``PoCRoot\src\arith`` and virtually a member in the `PoC.arith` namespace. +So the module can be identified by an unique name: ``PoC.arith.prng``, which is +passed to the frontend script. + +.. rubric:: Example: + +.. code-block:: PowerShell + + cd PoCRoot + .\poc.ps1 ghdl PoC.arith.prng + +The CLI command ``ghdl`` chooses *GHDL Simulator* as the simulator and +passes the fully qualified PoC entity name ``PoC.arith.prng`` as a parameter +to the tool. All required source file are gathered and compiled to an +executable. Afterwards this executable is launched in CLI mode and its outputs +are displayed in console: + +.. image:: /_static/images/ghdl/arith_prng_tb.posh.png + :target: /_static/images/ghdl/arith_prng_tb.posh.png + :alt: PowerShell console output after running PoC.arith.prng with GHDL. + +Each testbench uses PoC's simulation helper packages to count asserts and to +track active stimuli and checker processes. After a completed simulation run, +an report is written to STDOUT or the simulator's console. Note the line +``SIMULATION RESULT = PASSED``. For each simulated PoC entity, a line in the +overall report is created. It lists the runtime per testbench and the simulation +status (``... ERROR``, ``FAILED``, ``NO ASSERTS`` or ``PASSED``). See +:doc:`Simulation ` for more details. + + +Run a Synthesis +*************** + +The following quick example uses the Xilinx Systesis Tool (XST) to synthesize a +netlist for IP core ``arith_prng`` (Pseudo Random Number Generator - PRNG). The +VHDL file ``arith_prng.vhdl`` is located at ``PoCRoot\src\arith`` and virtually +a member in the `PoC.arith` namespace. So the module can be identified by an +unique name: ``PoC.arith.prng``, which is passed to the frontend script. + +.. rubric:: Example: + +.. code-block:: PowerShell + + cd PoCRoot + .\poc.ps1 xst PoC.arith.prng --board=KC705 + +The CLI command ``xst`` chooses *Xilinx Synthesis Tool* as the synthesizer and +passes the fully qualified PoC entity name ``PoC.arith.prng`` as a parameter +to the tool. Additionally, the development board name is required to load the +correct ``my_config.vhdl`` file. All required source file are gathered and +synthesized to a netlist. + +.. image:: /_static/images/xst/arith_prng.posh.png + :target: /_static/images/xst/arith_prng.posh.png + :alt: PowerShell console output after running PoC.arith.prng with XST. + + +Updating +******** + +The PoC-Library can be updated by using ``git fetch`` and ``git merge``. + +.. code-block:: PowerShell + + cd PoCRoot + # update the local repository + git fetch --prune + # review the commit tree and messages, using the 'treea' alias + git treea + # if all changes are OK, do a fast-forward merge + git merge + + +.. seealso:: + :doc:`Running one or more testbenches ` + The installation can be checked by running one or more of PoC's testbenches. + :doc:`Running one or more netlist generation flows ` + The installation can also be checked by running one or more of PoC's + synthesis flows. diff --git a/docs/References/CommandReference.rst b/docs/References/CommandReference.rst new file mode 100644 index 00000000..5aea0ba5 --- /dev/null +++ b/docs/References/CommandReference.rst @@ -0,0 +1,32 @@ + +Command Reference +################# + +.. contents:: Contents of this Page + + +Headline 4 +********************** + +Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. +At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor +sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et +accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet + + +Headline 5 +********************** + +Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. +At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor +sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et +accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet + + +Headline 6 +******************* + +Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. +At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor +sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et +accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet diff --git a/docs/References/FileFormats/FilesFormat.rst b/docs/References/FileFormats/FilesFormat.rst new file mode 100644 index 00000000..e724121b --- /dev/null +++ b/docs/References/FileFormats/FilesFormat.rst @@ -0,0 +1,132 @@ + +*.files Format +############## + +.. contents:: Contents of this Page + :local: + +Files files are used to ... + +Line comments start with ``#``. + +Document +******** + + +Source File Statements +********************** + +Bla :token:`VHDLStatement` blub + + +* ``vhdl Library ""`` + This statement references a VHDL source file. + +* ``verilog ""`` + This statement references a Verilog source file. + +* ``cocotb ""`` + This statement references a Cocotb testbench file (Python file). + +* ``ucf ""`` + This statement references a Xilinx User Constraint File (UCF). + +* ``sdc ""`` + This statement references a Synopsys Design Constraint file (SDC). + +* ``xdc ""`` + This statement references a Xilinx Design Constraint file (XDC). + +* ``ldc ""`` + This statement references a Lattice Design Constraint file (LDC). + + +Conditional Statements +********************** + + +* ``If () Then ... [ElseIf () Then ...][Else ...] End IF`` + This allows the user to define conditions, when to load a source file into + the file list. The ``ElseIF`` and ``Else`` clause of an ``If`` statement are optional. + + +Boolean Expressions +******************* + + +Unary operators +--------------- + +* ``!`` - not +* ``[...]`` - list construction +* ``?`` - file exists + +Binary operators +---------------- + +* ``and`` - and +* ``or`` - or +* ``xor`` - exclusive or +* ``in`` - in list +* ``=`` - equal +* ``!=`` - unequal +* ``<`` - less than +* ``<=`` - less than or equal +* ``>`` - greater than +* ``>=`` - greater than or equal + +Literals +-------- + +* ```` - a pre-defined constant +* ``""`` - Strings are enclosed in quote signs +* ```` - Integers as decimal values + +Pre-defined constants +--------------------- + +* Environment Variables: + + * ``Environment`` + Values: + + * ``"Simulation"`` + * ``"Synthesis"`` + + * ``ToolChain`` - The used tool chain. E.g. ``"Xilinx_ISE"`` + * ``Tool`` - The used tool. E.g. ``"Mentor_QuestaSim"`` or ``"Xilinx_XST"`` + * ``VHDL`` - The used VHDL version. ``1987``, ``1993``, ``2002``, ``2008`` + +* Board Variables: + + * ``BoardName`` - A string. E.g. ``"KC705"`` + +* Device Variables: + + * ``DeviceVendor`` - The vendor of the device. E.g. ``"Altera"`` + * ``DeviceDevice`` - + * ``DeviceFamily`` - + * ``DeviceGeneration`` - + * ``DeviceSeries`` - + + +Path Expressions +**************** + + +* ``/`` - sub-directory +* ``&`` - string concat + + +### Other Statements + +* ``include ""`` + Include another \*.files file. + +* ``library ""`` + Reference an existing (pre-compiled) VHDL library, which is passed to the simulator, if external libraries are supported. + +* ``report ""`` + Print a critical warning in the log window. This critical warning is treated as an error. + + diff --git a/docs/References/FileFormats/RulesFormat.rst b/docs/References/FileFormats/RulesFormat.rst new file mode 100644 index 00000000..617ca121 --- /dev/null +++ b/docs/References/FileFormats/RulesFormat.rst @@ -0,0 +1,32 @@ + +*.rules Format +############## + +.. contents:: Contents of this Page + + +Headline 1 +********************** + +Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. +At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor +sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et +accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet + + +Headline 2 +********************** + +Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. +At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor +sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et +accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet + + +Headline 3 +******************* + +Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. +At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor +sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et +accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet diff --git a/docs/References/FileFormats/index.rst b/docs/References/FileFormats/index.rst new file mode 100644 index 00000000..a379df4e --- /dev/null +++ b/docs/References/FileFormats/index.rst @@ -0,0 +1,9 @@ + +File Formats +############ + +.. toctree:: + :maxdepth: 1 + + FilesFormat + RulesFormat diff --git a/docs/References/Glossary.rst b/docs/References/Glossary.rst new file mode 100644 index 00000000..afc37f7f --- /dev/null +++ b/docs/References/Glossary.rst @@ -0,0 +1,48 @@ + +Glossary +######## + +Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. +At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor +sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et +accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet + +.. glossary:: + + cc - Common clock + All ports of a module use the same clock. + + dc - Dependent clock + The clock inputs of a module have a known relation in phase or are + multiples of a shared base clock. + + *flag*-signal + No documentation available. + + FWFT - First-word-fall-through + No documentation available. + + ic - Independent clock + The clock inputs have no known relation and are considdered independent. + Modules with ic interfaces implement clock domain crossing (CDC) circuits. + + OCRAM - On-Chip RAM + OCROM - On-Chip ROM + An On-Chip RAM is a embedded memory block, mostly called BlockRAM, + Dirstributed Memory, ... + + PoC.CSE - Command-Status-Error + A control and monitoring protocol in a layer-based architecture. + + PoC.Stream + A streaming optimized, FIFO-like on-chip protocol. + + PoCRoot + The PoC root directory. + + ProjectRoot + The project's root directory, which hosts PoC. + + *strobe*-signal + No documentation available. + diff --git a/docs/References/Interfaces/CommandStatusError.rst b/docs/References/Interfaces/CommandStatusError.rst new file mode 100644 index 00000000..d7207f10 --- /dev/null +++ b/docs/References/Interfaces/CommandStatusError.rst @@ -0,0 +1,6 @@ + +PoC.CSE +####### + +.. TODO:: + Define the PoC.CSE (Command-Status-Error) interface used in ... diff --git a/docs/References/Interfaces/Memory.rst b/docs/References/Interfaces/Memory.rst new file mode 100644 index 00000000..c02c66c9 --- /dev/null +++ b/docs/References/Interfaces/Memory.rst @@ -0,0 +1,6 @@ + +PoC.Mem +####### + +.. TODO:: + Define the PoC.Memory interface used in ... diff --git a/docs/References/Interfaces/Stream.rst b/docs/References/Interfaces/Stream.rst new file mode 100644 index 00000000..38ef2d0f --- /dev/null +++ b/docs/References/Interfaces/Stream.rst @@ -0,0 +1,6 @@ + +PoC.Stream +########## + +.. TODO:: + Define the PoC.Stream interface used in PoC.net.* and ``PoC.bus.stream.*`` ... diff --git a/docs/References/Interfaces/index.rst b/docs/References/Interfaces/index.rst new file mode 100644 index 00000000..895d4e56 --- /dev/null +++ b/docs/References/Interfaces/index.rst @@ -0,0 +1,11 @@ + +Interfaces +########## + +.. toctree:: + :maxdepth: 1 + + CommandStatusError + Memory + Stream + diff --git a/docs/References/KnownIssues.rst b/docs/References/KnownIssues.rst new file mode 100644 index 00000000..2521b483 --- /dev/null +++ b/docs/References/KnownIssues.rst @@ -0,0 +1,39 @@ + +Known Issues +############ + +Aldec +***** + +Active-HDL Student-Edition +========================== + +* Aliases to functions and protected type methods + +Altera +****** + +Quartus-II +========== + +* Generic types of type strings filled with NUL + +GHDL +**** + +* Aliases to protected type methods + +Xilinx +****** + +ISE +=== + +* Shared Variables in Simulation (VHDL-93) + +Vivado +====== + +* Physical types in synthesis +* VHDL-2008 mode in simulation +* Shared variables in simulation (VHDL-93 and VHDL-2008)) diff --git a/docs/References/Licenses/ApacheLicense2.0.rst b/docs/References/Licenses/ApacheLicense2.0.rst new file mode 100644 index 00000000..446982df --- /dev/null +++ b/docs/References/Licenses/ApacheLicense2.0.rst @@ -0,0 +1,137 @@ +.. Note:: This is a local copy of the `Apache License Version 2.0 `_. + +Apache License 2.0 +################## + +Version 2.0, January 2004 + +**TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION** + + +1. Definitions. +=============== +**"License"** shall mean the terms and conditions for use, reproduction, and distribution as defined by Sections 1 through 9 of this document. + +**"Licensor"** shall mean the copyright owner or entity authorized by the copyright owner that is granting the License. + +**"Legal Entity"** shall mean the union of the acting entity and all other entities that control, are controlled by, or are under common control with that +entity. For the purposes of this definition, **"control"** means (i) the power, direct or indirect, to cause the direction or management of such entity, whether +by contract or otherwise, or (ii) ownership of fifty percent (50%) or more of the outstanding shares, or (iii) beneficial ownership of such entity. + +**"You"** (or **"Your"**) shall mean an individual or Legal Entity exercising permissions granted by this License. + +**"Source"** form shall mean the preferred form for making modifications, including but not limited to software source code, documentation source, and +configuration files. + +**"Object"** form shall mean any form resulting from mechanical transformation or translation of a Source form, including but not limited to compiled object +code, generated documentation, and conversions to other media types. + +**"Work"** shall mean the work of authorship, whether in Source or Object form, made available under the License, as indicated by a copyright notice that is +included in or attached to the work (an example is provided in the Appendix below). + +**"Derivative Works"** shall mean any work, whether in Source or Object form, that is based on (or derived from) the Work and for which the editorial revisions, +annotations, elaborations, or other modifications represent, as a whole, an original work of authorship. For the purposes of this License, Derivative Works +shall not include works that remain separable from, or merely link (or bind by name) to the interfaces of, the Work and Derivative Works thereof. + +**"Contribution"** shall mean any work of authorship, including the original version of the Work and any modifications or additions to that Work or Derivative +Works thereof, that is intentionally submitted to Licensor for inclusion in the Work by the copyright owner or by an individual or Legal Entity authorized to +submit on behalf of the copyright owner. For the purposes of this definition, **"submitted"** means any form of electronic, verbal, or written communication +sent to the Licensor or its representatives, including but not limited to communication on electronic mailing lists, source code control systems, and issue +tracking systems that are managed by, or on behalf of, the Licensor for the purpose of discussing and improving the Work, but excluding communication that is +conspicuously marked or otherwise designated in writing by the copyright owner as **"Not a Contribution."** + +**"Contributor"** shall mean Licensor and any individual or Legal Entity on behalf of whom a Contribution has been received by Licensor and subsequently +incorporated within the Work. + +2. Grant of Copyright License. +============================== +Subject to the terms and conditions of this License, each Contributor hereby grants to You a perpetual, worldwide, non-exclusive, no-charge, royalty-free, +irrevocable copyright license to reproduce, prepare Derivative Works of, publicly display, publicly perform, sublicense, and distribute the Work and such +Derivative Works in Source or Object form. + +3. Grant of Patent License. +=========================== +Subject to the terms and conditions of this License, each Contributor hereby grants to You a perpetual, worldwide, non-exclusive, no-charge, royalty-free, +irrevocable (except as stated in this section) patent license to make, have made, use, offer to sell, sell, import, and otherwise transfer the Work, where such +license applies only to those patent claims licensable by such Contributor that are necessarily infringed by their Contribution(s) alone or by combination of +their Contribution(s) with the Work to which such Contribution(s) was submitted. If You institute patent litigation against any entity (including a cross-claim +or counterclaim in a lawsuit) alleging that the Work or a Contribution incorporated within the Work constitutes direct or contributory patent infringement, then +any patent licenses granted to You under this License for that Work shall terminate as of the date such litigation is filed. + +4. Redistribution. +================== +You may reproduce and distribute copies of the Work or Derivative Works thereof in any medium, with or without modifications, and in Source or Object form, +provided that You meet the following conditions: + +* You must give any other recipients of the Work or Derivative Works a copy of this License; and +* You must cause any modified files to carry prominent notices stating that You changed the files; and +* You must retain, in the Source form of any Derivative Works that You distribute, all copyright, patent, trademark, and attribution notices from the Source + form of the Work, excluding those notices that do not pertain to any part of the Derivative Works; and +* If the Work includes a **"NOTICE"** text file as part of its distribution, then any Derivative Works that You distribute must include a readable copy of the + attribution notices contained within such NOTICE file, excluding those notices that do not pertain to any part of the Derivative Works, in at least one of the + following places: within a NOTICE text file distributed as part of the Derivative Works; within the Source form or documentation, if provided along with the + Derivative Works; or, within a display generated by the Derivative Works, if and wherever such third-party notices normally appear. The contents of the NOTICE + file are for informational purposes only and do not modify the License. You may add Your own attribution notices within Derivative Works that You distribute, + alongside or as an addendum to the NOTICE text from the Work, provided that such additional attribution notices cannot be construed as modifying the License. + +You may add Your own copyright statement to Your modifications and may provide additional or different license terms and conditions for use, reproduction, or +distribution of Your modifications, or for any such Derivative Works as a whole, provided Your use, reproduction, and distribution of the Work otherwise +complies with the conditions stated in this License. + +5. Submission of Contributions. +=============================== +Unless You explicitly state otherwise, any Contribution intentionally submitted for inclusion in the Work by You to the Licensor shall be under the terms and +conditions of this License, without any additional terms or conditions. Notwithstanding the above, nothing herein shall supersede or modify the terms of any +separate license agreement you may have executed with Licensor regarding such Contributions. + +6. Trademarks. +============== +This License does not grant permission to use the trade names, trademarks, service marks, or product names of the Licensor, except as required for reasonable +and customary use in describing the origin of the Work and reproducing the content of the NOTICE file. + +7. Disclaimer of Warranty. +========================== +Unless required by applicable law or agreed to in writing, Licensor provides the Work (and each Contributor provides its Contributions) on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, including, without limitation, any warranties or conditions of TITLE, NON-INFRINGEMENT, +MERCHANTABILITY, or FITNESS FOR A PARTICULAR PURPOSE. You are solely responsible for determining the appropriateness of using or redistributing the Work and +assume any risks associated with Your exercise of permissions under this License. + +8. Limitation of Liability. +=========================== +In no event and under no legal theory, whether in tort (including negligence), contract, or otherwise, unless required by applicable law (such as deliberate +and grossly negligent acts) or agreed to in writing, shall any Contributor be liable to You for damages, including any direct, indirect, special, incidental, or +consequential damages of any character arising as a result of this License or out of the use or inability to use the Work (including but not limited to damages +for loss of goodwill, work stoppage, computer failure or malfunction, or any and all other commercial damages or losses), even if such Contributor has been +advised of the possibility of such damages. + +9. Accepting Warranty or Additional Liability. +============================================== +While redistributing the Work or Derivative Works thereof, You may choose to offer, and charge a fee for, acceptance of support, warranty, indemnity, or other +liability obligations and/or rights consistent with this License. However, in accepting such obligations, You may act only on Your own behalf and on Your sole +responsibility, not on behalf of any other Contributor, and only if You agree to indemnify, defend, and hold each Contributor harmless for any liability +incurred by, or claims asserted against, such Contributor by reason of your accepting any such warranty or additional liability. + +---------------------------------------------------------------------------------------------------------------------------------------------------------------- + +**Appendix: How to apply the Apache License to your work** + +To apply the Apache License to your work, attach the following boilerplate notice, with the fields enclosed by brackets "[]" replaced with your own identifying +information. (Don't include the brackets!) The text should be enclosed in the appropriate comment syntax for the file format. We also recommend that a file or +class name and description of purpose be included on the same "printed page" as the copyright notice for easier identification within third-party archives. + +.. code-block:: none + + Copyright [yyyy] [name of copyright owner] + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + diff --git a/docs/References/Licenses/ArtisticLicense2.0.rst b/docs/References/Licenses/ArtisticLicense2.0.rst new file mode 100644 index 00000000..0a2cdd5c --- /dev/null +++ b/docs/References/Licenses/ArtisticLicense2.0.rst @@ -0,0 +1,186 @@ +.. Note:: This is a local copy of the `Artistic License 2.0 `_. + +Artistic License 2.0 +#################### + +Copyright © 2000-2006, The Perl Foundation. + +Everyone is permitted to copy and distribute verbatim copies of this license +document, but changing it is not allowed. + +Preamble +======== + +This license establishes the terms under which a given free software Package +may be copied, modified, distributed, and/or redistributed. The intent is that +the Copyright Holder maintains some artistic control over the development of +that Package while still keeping the Package available as open source and free +software. +You are always permitted to make arrangements wholly outside of this license +directly with the Copyright Holder of a given Package. If the terms of this +license do not permit the full use that you propose to make of the Package, +you should contact the Copyright Holder and seek a different licensing +arrangement. + +Definitions +=========== + +**"Copyright Holder"** means the individual(s) or organization(s) named in the +copyright notice for the entire Package. + +**"Contributor"** means any party that has contributed code or other material +to the Package, in accordance with the Copyright Holder's procedures. + +**"You"** and **"your"** means any person who would like to copy, distribute, +or modify the Package. + +**"Package"** means the collection of files distributed by the Copyright +Holder, and derivatives of that collection and/or of those files. A given +Package may consist of either the Standard Version, or a Modified Version. + +**"Distribute"** means providing a copy of the Package or making it accessible +to anyone else, or in the case of a company or organization, to others outside +of your company or organization. + +**"Distributor Fee"** means any fee that you charge for Distributing this +Package or providing support for this Package to another party. It does not +mean licensing fees. + +**"Standard Version"** refers to the Package if it has not been modified, or +has been modified only in ways explicitly requested by the Copyright Holder. + +**"Modified Version"** means the Package, if it has been changed, and such +changes were not explicitly requested by the Copyright Holder. + +**"Original License"** means this Artistic License as Distributed with the +Standard Version of the Package, in its current version or as it may be +modified by The Perl Foundation in the future. + +**"Source"** form means the source code, documentation source, and +configuration files for the Package. + +**"Compiled"** form means the compiled bytecode, object code, binary, or any +other form resulting from mechanical transformation or translation of the +Source form. + +Permission for Use and Modification Without Distribution +======================================================== + +(1) You are permitted to use the Standard Version and create and use Modified +Versions for any purpose without restriction, provided that you do not +Distribute the Modified Version. + +Permissions for Redistribution of the Standard Version +====================================================== + +(2) You may Distribute verbatim copies of the Source form of the Standard +Version of this Package in any medium without restriction, either gratis or +for a Distributor Fee, provided that you duplicate all of the original +copyright notices and associated disclaimers. At your discretion, such +verbatim copies may or may not include a Compiled form of the Package. + +(3) You may apply any bug fixes, portability changes, and other modifications +made available from the Copyright Holder. The resulting Package will still be +considered the Standard Version, and as such will be subject to the Original +License. + +Distribution of Modified Versions of the Package as Source +========================================================== + +(4) You may Distribute your Modified Version as Source (either gratis or for a +Distributor Fee, and with or without a Compiled form of the Modified Version) +provided that you clearly document how it differs from the Standard Version, +including, but not limited to, documenting any non-standard features, +executables, or modules, and provided that you do at least ONE of the following: + + - (a) make the Modified Version available to the Copyright Holder of the + Standard Version, under the Original License, so that the Copyright Holder + may include your modifications in the Standard Version. + - (b) ensure that installation of your Modified Version does not prevent the + user installing or running the Standard Version. In addition, the Modified + Version must bear a name that is different from the name of the Standard + Version. + - (c) allow anyone who receives a copy of the Modified Version to make the + Source form of the Modified Version available to others under + (i) the Original License or + (ii) a license that permits the licensee to freely copy, modify and + redistribute the Modified Version using the same licensing terms that + apply to the copy that the licensee received, and requires that the Source + form of the Modified Version, and of any works derived from it, be made + freely available in that license fees are prohibited but Distributor Fees + are allowed. + +Distribution of Compiled Forms of the Standard Version or Modified Versions without the Source +============================================================================================== + +(5) You may Distribute Compiled forms of the Standard Version without the +Source, provided that you include complete instructions on how to get the +Source of the Standard Version. Such instructions must be valid at the time of +your distribution. If these instructions, at any time while you are carrying +out such distribution, become invalid, you must provide new instructions on +demand or cease further distribution. If you provide valid instructions or +cease distribution within thirty days after you become aware that the +instructions are invalid, then you do not forfeit any of your rights under +this license. + +(6) You may Distribute a Modified Version in Compiled form without the Source, +provided that you comply with Section 4 with respect to the Source of the +Modified Version. + +Aggregating or Linking the Package +================================== + +(7) You may aggregate the Package (either the Standard Version or Modified +Version) with other packages and Distribute the resulting aggregation provided +that you do not charge a licensing fee for the Package. Distributor Fees are +permitted, and licensing fees for other components in the aggregation are +permitted. The terms of this license apply to the use and Distribution of the +Standard or Modified Versions as included in the aggregation. + +(8) You are permitted to link Modified and Standard Versions with other works, +to embed the Package in a larger work of your own, or to build stand-alone +binary or bytecode versions of applications that include the Package, and +Distribute the result without restriction, provided the result does not expose +a direct interface to the Package. + +Items That are Not Considered Part of a Modified Version +======================================================== + +(9) Works (including, but not limited to, modules and scripts) that merely +extend or make use of the Package, do not, by themselves, cause the Package to +be a Modified Version. In addition, such works are not considered parts of the +Package itself, and are not subject to the terms of this license. + +General Provisions +================== + +(10) Any use, modification, and distribution of the Standard or Modified +Versions is governed by this Artistic License. By using, modifying or +distributing the Package, you accept this license. Do not use, modify, or +distribute the Package, if you do not accept this license. + +(11) If your Modified Version has been derived from a Modified Version made by +someone other than you, you are nevertheless required to ensure that your +Modified Version complies with the requirements of this license. + +(12) This license does not grant you the right to use any trademark, service +mark, tradename, or logo of the Copyright Holder. + +(13) This license includes the non-exclusive, worldwide, free-of-charge patent +license to make, have made, use, offer to sell, sell, import and otherwise +transfer the Package with respect to any patent claims licensable by the +Copyright Holder that are necessarily infringed by the Package. If you +institute patent litigation (including a cross-claim or counterclaim) against +any party alleging that the Package constitutes direct or contributory patent +infringement, then this Artistic License to you shall terminate on the date +that such litigation is filed. + +(14) Disclaimer of Warranty: + +**THE PACKAGE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS IS' AND +WITHOUT ANY EXPRESS OR IMPLIED WARRANTIES. THE IMPLIED WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ARE +DISCLAIMED TO THE EXTENT PERMITTED BY YOUR LOCAL LAW. UNLESS REQUIRED BY LAW, +NO COPYRIGHT HOLDER OR CONTRIBUTOR WILL BE LIABLE FOR ANY DIRECT, INDIRECT, +INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING IN ANY WAY OUT OF THE USE OF THE +PACKAGE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.** diff --git a/docs/References/Licenses/BSDLicense_Cocotb.rst b/docs/References/Licenses/BSDLicense_Cocotb.rst new file mode 100644 index 00000000..17eda5c8 --- /dev/null +++ b/docs/References/Licenses/BSDLicense_Cocotb.rst @@ -0,0 +1,43 @@ +.. Note:: + This is a local copy of the `(Revised) BSD License `_ + used in the Cocotb project. The original can be found in file :file:`LICENSE` in the + Cocotb source tree. + +.. TODO:: Check link to the lib/cocotb/LICENSE file. + +-------------------------------------------------------------------------------- + +BSD License for Cocotb +###################### + +Cocotb is licensed under the Revised BSD License. Full license text below. + +**Copyright (c) 2013 Potential Ventures Ltd** |br| +**Copyright (c) 2013 SolarFlare Communications Inc** |br| +**All rights reserved.** + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +* Neither the name of Potential Ventures Ltd, + SolarFlare Communications Inc nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + +**THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL POTENTIAL VENTURES LTD BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.** diff --git a/docs/References/Licenses/CCLA.rst b/docs/References/Licenses/CCLA.rst new file mode 100644 index 00000000..47f53e83 --- /dev/null +++ b/docs/References/Licenses/CCLA.rst @@ -0,0 +1,119 @@ +.. image:: /_static/images/logo_tud.jpg + :scale: 10 + :alt: Logo: Technische Universität Dresden + +Modified Apache Corporate Contributor License Agreement v2.0 +############################################################ + +Thank you for your interest in the **Chair for VLSI Design, Diagnostics +and Architecture** - Faculty of Computer Science, Technische Universität +Dresden, Germany (the "Chair"). In order to clarify the intellectual property license +granted with Contributions from any person or entity, the Chair +must have a Contributor License Agreement (CLA) on file that has been +signed by each Contributor, indicating agreement to the license terms +below. This license is for your protection as a Contributor as well +as the protection of the Chair and its users; it does not change +your rights to use your own Contributions for any other purpose. + +This version of the Agreement allows an entity (the "Corporation") to +submit Contributions to the Chair, to authorize Contributions +submitted by its designated employees to the Chair, and to grant +copyright and patent licenses thereto. + + +The following CLA is an adaption of the `Apache Corporate Contributor License Agreement v2.0 `_ + +-------- + +You accept and agree to the following terms and conditions for Your +present and future Contributions submitted to the Chair. In +return, the Chair shall not use Your Contributions in a way that +is contrary to the public benefit or inconsistent with its nonprofit +status and bylaws in effect at the time of the Contribution. Except +for the license granted herein to the Chair and recipients of +software distributed by the Chair, You reserve all right, title, +and interest in and to Your Contributions. + + 1. **Definitions.** |br| + *"You"* (or *"Your"*) shall mean the copyright owner or legal entity + authorized by the copyright owner that is making this Agreement + with the Chair. For legal entities, the entity making a + Contribution and all other entities that control, are controlled by, + or are under common control with that entity are considered to be a + single Contributor. For the purposes of this definition, "control" + means (i) the power, direct or indirect, to cause the direction or + management of such entity, whether by contract or otherwise, or + (ii) ownership of fifty percent (50%) or more of the outstanding + shares, or (iii) beneficial ownership of such entity. + + *"Contribution"* shall mean the code, documentation or other original + works of authorship expressly identified in Schedule B, as well as + any original work of authorship, including + any modifications or additions to an existing work, that is intentionally + submitted by You to the Chair for inclusion in, or + documentation of, any of the products owned or managed by the + Chair (the "Work"). For the purposes of this definition, + "submitted" means any form of electronic, verbal, or written + communication sent to the Chair or its representatives, + including but not limited to communication on electronic mailing + lists, source code control systems, and issue tracking systems + that are managed by, or on behalf of, the Chair for the + purpose of discussing and improving the Work, but excluding + communication that is conspicuously marked or otherwise designated + in writing by You as **"Not a Contribution."** + + 2. **Grant of Copyright License.** Subject to the terms and conditions + of this Agreement, You hereby grant to the Chair and to + recipients of software distributed by the Chair a perpetual, + worldwide, non-exclusive, no-charge, royalty-free, irrevocable + copyright license to reproduce, prepare derivative works of, + publicly display, publicly perform, sublicense, and distribute + Your Contributions and such derivative works. + + 3. **Grant of Patent License.** Subject to the terms and conditions of + this Agreement, You hereby grant to the Chair and to recipients + of software distributed by the Chair a perpetual, worldwide, + non-exclusive, no-charge, royalty-free, irrevocable (except as + stated in this section) patent license to make, have made, use, + offer to sell, sell, import, and otherwise transfer the Work, + where such license applies only to those patent claims licensable + by You that are necessarily infringed by Your Contribution(s) + alone or by combination of Your Contribution(s) with the Work to + which such Contribution(s) were submitted. If any entity institutes + patent litigation against You or any other entity (including a + cross-claim or counterclaim in a lawsuit) alleging that your + Contribution, or the Work to which you have contributed, constitutes + direct or contributory patent infringement, then any patent licenses + granted to that entity under this Agreement for that Contribution or + Work shall terminate as of the date such litigation is filed. + + 4. You represent that You are legally entitled to grant the above + license. You represent further that each employee of the + Corporation designated on Schedule A below (or in a subsequent + written modification to that Schedule) is authorized to submit + Contributions on behalf of the Corporation. + + 5. You represent that each of Your Contributions is Your original + creation (see section 7 for submissions on behalf of others). + + 6. You are not expected to provide support for Your Contributions, + except to the extent You desire to provide support. You may provide + support for free, for a fee, or not at all. Unless required by + applicable law or agreed to in writing, You provide Your + Contributions on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS + OF ANY KIND, either express or implied, including, without + limitation, any warranties or conditions of TITLE, NON-INFRINGEMENT, + MERCHANTABILITY, or FITNESS FOR A PARTICULAR PURPOSE. + + 7. Should You wish to submit work that is not Your original creation, + You may submit it to the Chair separately from any + Contribution, identifying the complete details of its source and + of any license or other restriction (including, but not limited + to, related patents, trademarks, and license agreements) of which + you are personally aware, and conspicuously marking the work as + **"Submitted on behalf of a third-party: [named here]"**. + + 8. It is your responsibility to notify the Chair when any change + is required to the list of designated employees authorized to submit + Contributions on behalf of the Corporation, or to the Corporation's + Point of Contact with the Chair. diff --git a/docs/References/Licenses/ICLA.rst b/docs/References/Licenses/ICLA.rst new file mode 100644 index 00000000..acf5b704 --- /dev/null +++ b/docs/References/Licenses/ICLA.rst @@ -0,0 +1,118 @@ +.. image:: /_static/images/logo_tud.jpg + :scale: 10 + :alt: Logo: Technische Universität Dresden + +Modified Apache Contributor License Agreement v2.0 +################################################## + +Thank you for your interest in the **Chair for VLSI Design, Diagnostics +and Architecture** - Faculty of Computer Science, Technische Universität +Dresden, Germany (the "Chair"). In order to clarify the intellectual +property license granted with Contributions from any person or entity, the +Chair must have a Contributor License Agreement ("CLA") on file that has +been signed by each Contributor, indicating agreement to the license +terms below. This license is for your protection as a Contributor as +well as the protection of the Chair and its users; it does not +change your rights to use your own Contributions for any other purpose. + +The following CLA is an adaption of the `Apache Contributor License Agreement v2.0 `_ + +------- + +You accept and agree to the following terms and conditions for Your +present and future Contributions submitted to the Chair. In +return, the Chair shall not use Your Contributions in a way that +is contrary to the public benefit or inconsistent with its nonprofit +status and bylaws in effect at the time of the Contribution. Except +for the license granted herein to the Chair and recipients of +software distributed by the Chair, You reserve all right, title, +and interest in and to Your Contributions. + + 1. **Definitions.** |br| + *"You"* (or *"Your"*) shall mean the copyright owner or legal entity + authorized by the copyright owner that is making this Agreement + with the Chair. For legal entities, the entity making a + Contribution and all other entities that control, are controlled + by, or are under common control with that entity are considered to + be a single Contributor. For the purposes of this definition, + *"control"* means (i) the power, direct or indirect, to cause the + direction or management of such entity, whether by contract or + otherwise, or (ii) ownership of fifty percent (50%) or more of the + outstanding shares, or (iii) beneficial ownership of such entity. + + *"Contribution"* shall mean any original work of authorship, + including any modifications or additions to an existing work, that + is intentionally submitted by You to the Chair for inclusion + in, or documentation of, any of the products owned or managed by + the Chair (the *"Work"*). For the purposes of this definition, + "submitted" means any form of electronic, verbal, or written + communication sent to the Chair or its representatives, + including but not limited to communication on electronic mailing + lists, source code control systems, and issue tracking systems that + are managed by, or on behalf of, the Chair for the purpose of + discussing and improving the Work, but excluding communication that + is conspicuously marked or otherwise designated in writing by You + as **"Not a Contribution."** + + 2. **Grant of Copyright License.** Subject to the terms and conditions of + this Agreement, You hereby grant to the Chair and to + recipients of software distributed by the Chair a perpetual, + worldwide, non-exclusive, no-charge, royalty-free, irrevocable + copyright license to reproduce, prepare derivative works of, + publicly display, publicly perform, sublicense, and distribute Your + Contributions and such derivative works. + + 3. **Grant of Patent License.** Subject to the terms and conditions of + this Agreement, You hereby grant to the Chair and to + recipients of software distributed by the Chair a perpetual, + worldwide, non-exclusive, no-charge, royalty-free, irrevocable + (except as stated in this section) patent license to make, have + made, use, offer to sell, sell, import, and otherwise transfer the + Work, where such license applies only to those patent claims + licensable by You that are necessarily infringed by Your + Contribution(s) alone or by combination of Your Contribution(s) + with the Work to which such Contribution(s) was submitted. If any + entity institutes patent litigation against You or any other entity + (including a cross-claim or counterclaim in a lawsuit) alleging + that your Contribution, or the Work to which you have contributed, + constitutes direct or contributory patent infringement, then any + patent licenses granted to that entity under this Agreement for + that Contribution or Work shall terminate as of the date such + litigation is filed. + + 4. You represent that you are legally entitled to grant the above + license. If your employer(s) has rights to intellectual property + that you create that includes your Contributions, you represent + that you have received permission to make Contributions on behalf + of that employer, that your employer has waived such rights for + your Contributions to the Chair, or that your employer has + executed a separate :doc:`Corporate CLA ` with the Chair. + + 5. You represent that each of Your Contributions is Your original + creation (see section 7 for submissions on behalf of others). You + represent that Your Contribution submissions include complete + details of any third-party license or other restriction (including, + but not limited to, related patents and trademarks) of which you + are personally aware and which are associated with any part of Your + Contributions. + + 6. You are not expected to provide support for Your Contributions, + except to the extent You desire to provide support. You may provide + support for free, for a fee, or not at all. Unless required by + applicable law or agreed to in writing, You provide Your + Contributions on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS + OF ANY KIND, either express or implied, including, without + limitation, any warranties or conditions of TITLE, NON- + INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A PARTICULAR PURPOSE. + + 7. Should You wish to submit work that is not Your original creation, + You may submit it to the Chair separately from any + Contribution, identifying the complete details of its source and of + any license or other restriction (including, but not limited to, + related patents, trademarks, and license agreements) of which you + are personally aware, and conspicuously marking the work as + **"Submitted on behalf of a third-party: [named here]"**. + + 8. You agree to notify the Chair of any facts or circumstances of + which you become aware that would make these representations + inaccurate in any respect. diff --git a/docs/References/Licenses/License.rst b/docs/References/Licenses/License.rst new file mode 100644 index 00000000..446982df --- /dev/null +++ b/docs/References/Licenses/License.rst @@ -0,0 +1,137 @@ +.. Note:: This is a local copy of the `Apache License Version 2.0 `_. + +Apache License 2.0 +################## + +Version 2.0, January 2004 + +**TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION** + + +1. Definitions. +=============== +**"License"** shall mean the terms and conditions for use, reproduction, and distribution as defined by Sections 1 through 9 of this document. + +**"Licensor"** shall mean the copyright owner or entity authorized by the copyright owner that is granting the License. + +**"Legal Entity"** shall mean the union of the acting entity and all other entities that control, are controlled by, or are under common control with that +entity. For the purposes of this definition, **"control"** means (i) the power, direct or indirect, to cause the direction or management of such entity, whether +by contract or otherwise, or (ii) ownership of fifty percent (50%) or more of the outstanding shares, or (iii) beneficial ownership of such entity. + +**"You"** (or **"Your"**) shall mean an individual or Legal Entity exercising permissions granted by this License. + +**"Source"** form shall mean the preferred form for making modifications, including but not limited to software source code, documentation source, and +configuration files. + +**"Object"** form shall mean any form resulting from mechanical transformation or translation of a Source form, including but not limited to compiled object +code, generated documentation, and conversions to other media types. + +**"Work"** shall mean the work of authorship, whether in Source or Object form, made available under the License, as indicated by a copyright notice that is +included in or attached to the work (an example is provided in the Appendix below). + +**"Derivative Works"** shall mean any work, whether in Source or Object form, that is based on (or derived from) the Work and for which the editorial revisions, +annotations, elaborations, or other modifications represent, as a whole, an original work of authorship. For the purposes of this License, Derivative Works +shall not include works that remain separable from, or merely link (or bind by name) to the interfaces of, the Work and Derivative Works thereof. + +**"Contribution"** shall mean any work of authorship, including the original version of the Work and any modifications or additions to that Work or Derivative +Works thereof, that is intentionally submitted to Licensor for inclusion in the Work by the copyright owner or by an individual or Legal Entity authorized to +submit on behalf of the copyright owner. For the purposes of this definition, **"submitted"** means any form of electronic, verbal, or written communication +sent to the Licensor or its representatives, including but not limited to communication on electronic mailing lists, source code control systems, and issue +tracking systems that are managed by, or on behalf of, the Licensor for the purpose of discussing and improving the Work, but excluding communication that is +conspicuously marked or otherwise designated in writing by the copyright owner as **"Not a Contribution."** + +**"Contributor"** shall mean Licensor and any individual or Legal Entity on behalf of whom a Contribution has been received by Licensor and subsequently +incorporated within the Work. + +2. Grant of Copyright License. +============================== +Subject to the terms and conditions of this License, each Contributor hereby grants to You a perpetual, worldwide, non-exclusive, no-charge, royalty-free, +irrevocable copyright license to reproduce, prepare Derivative Works of, publicly display, publicly perform, sublicense, and distribute the Work and such +Derivative Works in Source or Object form. + +3. Grant of Patent License. +=========================== +Subject to the terms and conditions of this License, each Contributor hereby grants to You a perpetual, worldwide, non-exclusive, no-charge, royalty-free, +irrevocable (except as stated in this section) patent license to make, have made, use, offer to sell, sell, import, and otherwise transfer the Work, where such +license applies only to those patent claims licensable by such Contributor that are necessarily infringed by their Contribution(s) alone or by combination of +their Contribution(s) with the Work to which such Contribution(s) was submitted. If You institute patent litigation against any entity (including a cross-claim +or counterclaim in a lawsuit) alleging that the Work or a Contribution incorporated within the Work constitutes direct or contributory patent infringement, then +any patent licenses granted to You under this License for that Work shall terminate as of the date such litigation is filed. + +4. Redistribution. +================== +You may reproduce and distribute copies of the Work or Derivative Works thereof in any medium, with or without modifications, and in Source or Object form, +provided that You meet the following conditions: + +* You must give any other recipients of the Work or Derivative Works a copy of this License; and +* You must cause any modified files to carry prominent notices stating that You changed the files; and +* You must retain, in the Source form of any Derivative Works that You distribute, all copyright, patent, trademark, and attribution notices from the Source + form of the Work, excluding those notices that do not pertain to any part of the Derivative Works; and +* If the Work includes a **"NOTICE"** text file as part of its distribution, then any Derivative Works that You distribute must include a readable copy of the + attribution notices contained within such NOTICE file, excluding those notices that do not pertain to any part of the Derivative Works, in at least one of the + following places: within a NOTICE text file distributed as part of the Derivative Works; within the Source form or documentation, if provided along with the + Derivative Works; or, within a display generated by the Derivative Works, if and wherever such third-party notices normally appear. The contents of the NOTICE + file are for informational purposes only and do not modify the License. You may add Your own attribution notices within Derivative Works that You distribute, + alongside or as an addendum to the NOTICE text from the Work, provided that such additional attribution notices cannot be construed as modifying the License. + +You may add Your own copyright statement to Your modifications and may provide additional or different license terms and conditions for use, reproduction, or +distribution of Your modifications, or for any such Derivative Works as a whole, provided Your use, reproduction, and distribution of the Work otherwise +complies with the conditions stated in this License. + +5. Submission of Contributions. +=============================== +Unless You explicitly state otherwise, any Contribution intentionally submitted for inclusion in the Work by You to the Licensor shall be under the terms and +conditions of this License, without any additional terms or conditions. Notwithstanding the above, nothing herein shall supersede or modify the terms of any +separate license agreement you may have executed with Licensor regarding such Contributions. + +6. Trademarks. +============== +This License does not grant permission to use the trade names, trademarks, service marks, or product names of the Licensor, except as required for reasonable +and customary use in describing the origin of the Work and reproducing the content of the NOTICE file. + +7. Disclaimer of Warranty. +========================== +Unless required by applicable law or agreed to in writing, Licensor provides the Work (and each Contributor provides its Contributions) on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, including, without limitation, any warranties or conditions of TITLE, NON-INFRINGEMENT, +MERCHANTABILITY, or FITNESS FOR A PARTICULAR PURPOSE. You are solely responsible for determining the appropriateness of using or redistributing the Work and +assume any risks associated with Your exercise of permissions under this License. + +8. Limitation of Liability. +=========================== +In no event and under no legal theory, whether in tort (including negligence), contract, or otherwise, unless required by applicable law (such as deliberate +and grossly negligent acts) or agreed to in writing, shall any Contributor be liable to You for damages, including any direct, indirect, special, incidental, or +consequential damages of any character arising as a result of this License or out of the use or inability to use the Work (including but not limited to damages +for loss of goodwill, work stoppage, computer failure or malfunction, or any and all other commercial damages or losses), even if such Contributor has been +advised of the possibility of such damages. + +9. Accepting Warranty or Additional Liability. +============================================== +While redistributing the Work or Derivative Works thereof, You may choose to offer, and charge a fee for, acceptance of support, warranty, indemnity, or other +liability obligations and/or rights consistent with this License. However, in accepting such obligations, You may act only on Your own behalf and on Your sole +responsibility, not on behalf of any other Contributor, and only if You agree to indemnify, defend, and hold each Contributor harmless for any liability +incurred by, or claims asserted against, such Contributor by reason of your accepting any such warranty or additional liability. + +---------------------------------------------------------------------------------------------------------------------------------------------------------------- + +**Appendix: How to apply the Apache License to your work** + +To apply the Apache License to your work, attach the following boilerplate notice, with the fields enclosed by brackets "[]" replaced with your own identifying +information. (Don't include the brackets!) The text should be enclosed in the appropriate comment syntax for the file format. We also recommend that a file or +class name and description of purpose be included on the same "printed page" as the copyright notice for easier identification within third-party archives. + +.. code-block:: none + + Copyright [yyyy] [name of copyright owner] + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + diff --git a/docs/References/Licenses/MozillaPublicLicense2.0.rst b/docs/References/Licenses/MozillaPublicLicense2.0.rst new file mode 100644 index 00000000..1222832c --- /dev/null +++ b/docs/References/Licenses/MozillaPublicLicense2.0.rst @@ -0,0 +1,366 @@ +.. Note:: This is a local copy of the `Mozilla Public License, Version 2.0 `_. + +Mozilla Public License, v. 2.0 +############################## + +1. Definitions +************** + +1.1. "Contributor" + means each individual or legal entity that creates, contributes to the + creation of, or owns Covered Software. + +1.2. "Contributor Version" + means the combination of the Contributions of others (if any) used by a + Contributor and that particular Contributor's Contribution. + +1.3. "Contribution" + means Covered Software of a particular Contributor. + +1.4. "Covered Software" + means Source Code Form to which the initial Contributor has attached the + notice in Exhibit A, the Executable Form of such Source Code Form, and + Modifications of such Source Code Form, in each case including portions + thereof. + +1.5. "Incompatible With Secondary Licenses" + means + + * that the initial Contributor has attached the notice described in Exhibit + B to the Covered Software; or + * that the Covered Software was made available under the terms of version + 1.1 or earlier of the License, but not also under the terms of a Secondary + License. + +1.6. "Executable Form" + means any form of the work other than Source Code Form. + +1.7. "Larger Work" + means a work that combines Covered Software with other material, in a + separate file or files, that is not Covered Software. + +1.8. "License" + means this document. + +1.9. "Licensable" + means having the right to grant, to the maximum extent possible, whether at + the time of the initial grant or subsequently, any and all of the rights + conveyed by this License. + +1.10. "Modifications" + means any of the following: + + * any file in Source Code Form that results from an addition to, deletion + from, or modification of the contents of Covered Software; or + * any new file in Source Code Form that contains any Covered Software. + +1.11. "Patent Claims" of a Contributor + means any patent claim(s), including without limitation, method, process, + and apparatus claims, in any patent Licensable by such Contributor that + would be infringed, but for the grant of the License, by the making, using, + selling, offering for sale, having made, import, or transfer of either its + Contributions or its Contributor Version. + +1.12. "Secondary License" + means either the GNU General Public License, Version 2.0, the GNU Lesser + General Public License, Version 2.1, the GNU Affero General Public License, + Version 3.0, or any later versions of those licenses. + +1.13. "Source Code Form" + means the form of the work preferred for making modifications. + +1.14. "You" (or "Your") + means an individual or a legal entity exercising rights under this License. + For legal entities, "You" includes any entity that controls, is controlled + by, or is under common control with You. For purposes of this definition, + "control" means (a) the power, direct or indirect, to cause the direction or + management of such entity, whether by contract or otherwise, or (b) + ownership of more than fifty percent (50%) of the outstanding shares or + beneficial ownership of such entity. + + +2. License Grants and Conditions +******************************** + +2.1. Grants +=========== + +Each Contributor hereby grants You a world-wide, royalty-free, non-exclusive +license: + +* under intellectual property rights (other than patent or trademark) + Licensable by such Contributor to use, reproduce, make available, modify, + display, perform, distribute, and otherwise exploit its Contributions, either + on an unmodified basis, with Modifications, or as part of a Larger Work; and +* under Patent Claims of such Contributor to make, use, sell, offer for sale, + have made, import, and otherwise transfer either its Contributions or its + Contributor Version. + +2.2. Effective Date +=================== + +The licenses granted in Section 2.1 with respect to any Contribution become +effective for each Contribution on the date the Contributor first distributes +such Contribution. + +2.3. Limitations on Grant Scope +=============================== + +The licenses granted in this Section 2 are the only rights granted under this +License. No additional rights or licenses will be implied from the +distribution or licensing of Covered Software under this License. +Notwithstanding Section 2.1(b) above, no patent license is granted by a +Contributor: + +* for any code that a Contributor has removed from Covered Software; or +* for infringements caused by: (i) Your and any other third party's + modifications of Covered Software, or (ii) the combination of its + Contributions with other software (except as part of its Contributor + Version); or +* under Patent Claims infringed by Covered Software in the absence of its + Contributions. + +This License does not grant any rights in the trademarks, service marks, or +logos of any Contributor (except as may be necessary to comply with the notice +requirements in Section 3.4). + +2.4. Subsequent Licenses +======================== + +No Contributor makes additional grants as a result of Your choice to +distribute the Covered Software under a subsequent version of this License +(see Section 10.2) or under the terms of a Secondary License (if permitted +under the terms of Section 3.3). + +2.5. Representation +======================== + +Each Contributor represents that the Contributor believes its Contributions +are its original creation(s) or it has sufficient rights to grant the rights +to its Contributions conveyed by this License. + +2.6. Fair Use +================== + +This License is not intended to limit any rights You have under applicable +copyright doctrines of fair use, fair dealing, or other equivalents. + +2.7. Conditions +====================================== + +Sections 3.1, 3.2, 3.3, and 3.4 are conditions of the licenses granted in +Section 2.1. + +3. Responsibilities +******************* + +3.1. Distribution of Source Form +================================ + +All distribution of Covered Software in Source Code Form, including any +Modifications that You create or to which You contribute, must be under the +terms of this License. You must inform recipients that the Source Code Form of +the Covered Software is governed by the terms of this License, and how they +can obtain a copy of this License. You may not attempt to alter or restrict +the recipients' rights in the Source Code Form. + +3.2. Distribution of Executable Form +==================================== + +If You distribute Covered Software in Executable Form then: + +* such Covered Software must also be made available in Source Code Form, as + described in Section 3.1, and You must inform recipients of the Executable + Form how they can obtain a copy of such Source Code Form by reasonable means + in a timely manner, at a charge no more than the cost of distribution to the + recipient; and +* You may distribute such Executable Form under the terms of this License, or + sublicense it under different terms, provided that the license for the + Executable Form does not attempt to limit or alter the recipients' rights in + the Source Code Form under this License. + +3.3. Distribution of a Larger Work +================================== + +You may create and distribute a Larger Work under terms of Your choice, +provided that You also comply with the requirements of this License for the +Covered Software. If the Larger Work is a combination of Covered Software with +a work governed by one or more Secondary Licenses, and the Covered Software is +not Incompatible With Secondary Licenses, this License permits You to +additionally distribute such Covered Software under the terms of such +Secondary License(s), so that the recipient of the Larger Work may, at their +option, further distribute the Covered Software under the terms of either this +License or such Secondary License(s). + +3.4. Notices +============ + +You may not remove or alter the substance of any license notices (including +copyright notices, patent notices, disclaimers of warranty, or limitations of +liability) contained within the Source Code Form of the Covered Software, +except that You may alter any license notices to the extent required to remedy +known factual inaccuracies. + +3.5. Application of Additional Terms +==================================== + +You may choose to offer, and to charge a fee for, warranty, support, indemnity +or liability obligations to one or more recipients of Covered Software. +However, You may do so only on Your own behalf, and not on behalf of any +Contributor. You must make it absolutely clear that any such warranty, +support, indemnity, or liability obligation is offered by You alone, and You +hereby agree to indemnify every Contributor for any liability incurred by such +Contributor as a result of warranty, support, indemnity or liability terms You +offer. You may include additional disclaimers of warranty and limitations of +liability specific to any jurisdiction. + +4. Inability to Comply Due to Statute or Regulation +*************************************************** + +If it is impossible for You to comply with any of the terms of this License +with respect to some or all of the Covered Software due to statute, judicial +order, or regulation then You must: (a) comply with the terms of this License +to the maximum extent possible; and (b) describe the limitations and the code +they affect. Such description must be placed in a text file included with all +distributions of the Covered Software under this License. Except to the extent +prohibited by statute or regulation, such description must be sufficiently +detailed for a recipient of ordinary skill to be able to understand it. + +5. Termination +************** + +**5.1.** The rights granted under this License will terminate automatically if +You fail to comply with any of its terms. However, if You become compliant, +then the rights granted under this License from a particular Contributor are +reinstated (a) provisionally, unless and until such Contributor explicitly and +finally terminates Your grants, and (b) on an ongoing basis, if such +Contributor fails to notify You of the non-compliance by some reasonable means +prior to 60 days after You have come back into compliance. Moreover, Your +grants from a particular Contributor are reinstated on an ongoing basis if +such Contributor notifies You of the non-compliance by some reasonable means, +this is the first time You have received notice of non-compliance with this +License from such Contributor, and You become compliant prior to 30 days after +Your receipt of the notice. + +**5.2.** If You initiate litigation against any entity by asserting a patent +infringement claim (excluding declaratory judgment actions, counter-claims, +and cross-claims) alleging that a Contributor Version directly or indirectly +infringes any patent, then the rights granted to You by any and all +Contributors for the Covered Software under Section 2.1 of this License shall +terminate. + +**5.3.** In the event of termination under Sections 5.1 or 5.2 above, all end +user license agreements (excluding distributors and resellers) which have been +validly granted by You or Your distributors under this License prior to +termination shall survive termination. + +6. Disclaimer of Warranty +************************* + + Covered Software is provided under this License on an "as is" basis, without + warranty of any kind, either expressed, implied, or statutory, including, + without limitation, warranties that the Covered Software is free of defects, + merchantable, fit for a particular purpose or non-infringing. The entire risk + as to the quality and performance of the Covered Software is with You. Should + any Covered Software prove defective in any respect, You (not any Contributor) + assume the cost of any necessary servicing, repair, or correction. This + disclaimer of warranty constitutes an essential part of this License. No use + of any Covered Software is authorized under this License except under this + disclaimer. + +7. Limitation of Liability +************************** + + Under no circumstances and under no legal theory, whether tort (including + negligence), contract, or otherwise, shall any Contributor, or anyone who + distributes Covered Software as permitted above, be liable to You for any + direct, indirect, special, incidental, or consequential damages of any + character including, without limitation, damages for lost profits, loss of + goodwill, work stoppage, computer failure or malfunction, or any and all other + commercial damages or losses, even if such party shall have been informed of + the possibility of such damages. This limitation of liability shall not apply + to liability for death or personal injury resulting from such party's + negligence to the extent applicable law prohibits such limitation. Some + jurisdictions do not allow the exclusion or limitation of incidental or + consequential damages, so this exclusion and limitation may not apply to You. + +8. Litigation +************* + +Any litigation relating to this License may be brought only in the courts of a +jurisdiction where the defendant maintains its principal place of business and +such litigation shall be governed by laws of that jurisdiction, without +reference to its conflict-of-law provisions. Nothing in this Section shall +prevent a party's ability to bring cross-claims or counter-claims. + +9. Miscellaneous +**************** + +This License represents the complete agreement concerning the subject matter +hereof. If any provision of this License is held to be unenforceable, such +provision shall be reformed only to the extent necessary to make it +enforceable. Any law or regulation which provides that the language of a +contract shall be construed against the drafter shall not be used to construe +this License against a Contributor. + +10. Versions of the License +*************************** + +10.1. New Versions +================== + +Mozilla Foundation is the license steward. Except as provided in Section 10.3, +no one other than the license steward has the right to modify or publish new +versions of this License. Each version will be given a distinguishing version +number. + +10.2. Effect of New Versions +============================ + +You may distribute the Covered Software under the terms of the version of the +License under which You originally received the Covered Software, or under the +terms of any subsequent version published by the license steward. + +10.3. Modified Versions +======================= + +If you create software not governed by this License, and you want to create a +new license for such software, you may create and use a modified version of +this License if you rename the license and remove any references to the name +of the license steward (except to note that such modified license differs from +this License). + +10.4. Distributing Source Code Form that is Incompatible With Secondary Licenses +================================================================================ + +If You choose to distribute Source Code Form that is Incompatible With +Secondary Licenses under the terms of this version of the License, the notice +described in Exhibit B of this License must be attached. + +---------------------------------------------------------------- + +Exhibit A - Source Code Form License Notice +******************************************* + +.. code-block:: raw + + This Source Code Form is subject to the terms of the Mozilla Public + License, v. 2.0. If a copy of the MPL was not distributed with this file, + You can obtain one at http://mozilla.org/MPL/2.0/. + +If it is not possible or desirable to put the notice in a particular file, +then You may include the notice in a location (such as a LICENSE file in a +relevant directory) where a recipient would be likely to look for such a notice. + +You may add additional accurate notices of copyright ownership. + + +Exhibit B - "Incompatible With Secondary Licenses" Notice +********************************************************* + +.. code-block:: raw + + This Source Code Form is "Incompatible With Secondary Licenses", as + defined by the Mozilla Public License, v. 2.0. + + diff --git a/docs/References/Licenses/index.rst b/docs/References/Licenses/index.rst new file mode 100644 index 00000000..d648002d --- /dev/null +++ b/docs/References/Licenses/index.rst @@ -0,0 +1,26 @@ + +Local License Copies +#################### + +This documentation contains local copies of all used licenses by either PoC +itself or embedded libraries or IP cores. Each formatted [#f1]_ license text +can be downloaded from the original source. Therefor see the top-most INFO box, +which contains a link to the orginal license file source. + +.. toctree:: + :maxdepth: 1 + + ApacheLicense2.0 + ICLA + CCLA + ArtisticLicense2.0 + BSDLicense_Cocotb + MozillaPublicLicense2.0 + +.. rubric:: Footnotes + +.. [#f1] Formatted means, that reStructured Test (reST) markup is used to + highlight headlines, to display lists as unordered or ordered lists and to + emphasis special wording in bold. There is no change in words, spelling or + paragraph numbering. The formatting is needed to allow a proper rendering + with Sphinx and to create a correct toctree (Table of Content Tree). diff --git a/docs/References/ListOfBoards.rst b/docs/References/ListOfBoards.rst new file mode 100644 index 00000000..cbb31470 --- /dev/null +++ b/docs/References/ListOfBoards.rst @@ -0,0 +1,61 @@ + +.. include:: + +List of Supported Boards +######################## + ++-------------+----------------------------------+--------------------------+ +| Board Name | Device String | Device Name | ++=============+==================================+==========================+ +| GENERIC | GENERIC | Generic board and device | ++-------------+----------------------------------+--------------------------+ +| **Altera** | |DoubleRightArrow| **DE4** | | ++-------------+----------------------------------+--------------------------+ +| DE0 | EP3C16F484 | Altera Cyclone III | ++-------------+----------------------------------+--------------------------+ +| S2GXAV | EP2SGX90FF1508C3 | Altera Stratix II | ++-------------+----------------------------------+--------------------------+ +| DE4 | EP4SGX230KF40C2 | Altera Stratix IV | ++-------------+----------------------------------+--------------------------+ +| DE5 | EP5SGXEA7N2F45C2 | Altera Stratix V | ++-------------+----------------------------------+--------------------------+ +| **Lattice** | |DoubleRightArrow| **ECP5Versa** | | ++-------------+----------------------------------+--------------------------+ +| ECP5Versa | LFE5UM-45F-6BG381C | Lattice ECP5 | ++-------------+----------------------------------+--------------------------+ +| **Xilinx** | |DoubleRightArrow| **KC705** | | ++-------------+----------------------------------+--------------------------+ +| S3SK200 | XC3S200FT256 | Xilinx Spartan-3 | ++-------------+----------------------------------+--------------------------+ +| S3ESK500 | XC3S500EFT256 | Xilinx Spartan-3 | ++-------------+----------------------------------+--------------------------+ +| S3SK1000 | XC3S1000FT256 | Xilinx Spartan-3 | ++-------------+----------------------------------+--------------------------+ +| S3ESK1600 | XC3S1600EFT256 | Xilinx Spartan-3 | ++-------------+----------------------------------+--------------------------+ +| ATLYS | XC6SLX45-3CSG324 | Xilinx Spartan-6 | ++-------------+----------------------------------+--------------------------+ +| ZC706 | XC7Z045-2FFG900 | Xilinx Zynq-7000 | ++-------------+----------------------------------+--------------------------+ +| ZedBoard | XC7Z020-1CLG484 | Xilinx Zynq-7000 | ++-------------+----------------------------------+--------------------------+ +| AC701 | XC7A200T-2FBG676C | Xilinx Artix-7 | ++-------------+----------------------------------+--------------------------+ +| KC705 | XC7K325T-2FFG900C | Xilinx Kintex-7 | ++-------------+----------------------------------+--------------------------+ +| ML505 | XC5VLX50T-1FF1136 | Xilinx Virtex-5 | ++-------------+----------------------------------+--------------------------+ +| ML506 | XC5VSX50T-1FFG1136 | Xilinx Virtex-5 | ++-------------+----------------------------------+--------------------------+ +| ML507 | XC5VFX70T-1FFG1136 | Xilinx Virtex-5 | ++-------------+----------------------------------+--------------------------+ +| XUPV5 | XC5VLX110T-1FF1136 | Xilinx Virtex-5 | ++-------------+----------------------------------+--------------------------+ +| ML605 | XC6VLX240T-1FF1156 | Xilinx Virtex-6 | ++-------------+----------------------------------+--------------------------+ +| VC707 | XC7VX485T-2FFG1761C | Xilinx Virtex-7 | ++-------------+----------------------------------+--------------------------+ +| VC709 | XC7VX690T-2FFG1761C | Xilinx Virtex-7 | ++-------------+----------------------------------+--------------------------+ +| **Custom** | **** | | ++-------------+----------------------------------+--------------------------+ diff --git a/docs/References/ListOfDevices.rst b/docs/References/ListOfDevices.rst new file mode 100644 index 00000000..aca4cf37 --- /dev/null +++ b/docs/References/ListOfDevices.rst @@ -0,0 +1,31 @@ + +List of Supported FPGA Devices +############################## + ++---------+-------------+--------------------------------------------------------------------------------+ +| Vendor | Family | Device Name | ++=========+=============+================================================================================+ +| Altera | Max | Max-II, Max 10 | ++---------+-------------+--------------------------------------------------------------------------------+ +| | Cyclone | Cyclone III, Cyclone V | ++---------+-------------+--------------------------------------------------------------------------------+ +| | Stratix | Stratix II, Stratix IV, Stratix V, Stratix 10 | ++---------+-------------+--------------------------------------------------------------------------------+ +| | Arria | Arria II, Arria V | ++---------+-------------+--------------------------------------------------------------------------------+ +| Lattice | Mach | MachXO | ++---------+-------------+--------------------------------------------------------------------------------+ +| | ECP | ECP3, ECP5 | ++---------+-------------+--------------------------------------------------------------------------------+ +| Xilinx | Coolrunner | Coolrunner-II | ++---------+-------------+--------------------------------------------------------------------------------+ +| | Spartan | Spartan-3, Spartan-6 | ++---------+-------------+--------------------------------------------------------------------------------+ +| | Artix | Artix-7 | ++---------+-------------+--------------------------------------------------------------------------------+ +| | Kintex | Kintex-7, Kintex UltraScale, Kintex UltraScale+ | ++---------+-------------+--------------------------------------------------------------------------------+ +| | Virtex | Virtex-II, Virtex-4, Virtex-5, Virtex-7, Virtex UltraScale, Virtex UltraScale+ | ++---------+-------------+--------------------------------------------------------------------------------+ +| | Zynq | Zynq-7000 | ++---------+-------------+--------------------------------------------------------------------------------+ diff --git a/docs/References/NamingConventions.rst b/docs/References/NamingConventions.rst new file mode 100644 index 00000000..875e205d --- /dev/null +++ b/docs/References/NamingConventions.rst @@ -0,0 +1,178 @@ + +Naming Conventions +################## + +.. TODO:: Write an intruduction paragraph for this page. + + +Root Directory Overview (PoCRoot) +********************************* + +The PoC-Library is structured into several sub-directories, naming the purpose +of the directory like ``src`` for sources files or ``tb`` for testbench files. +The structure within these directories is most likely the same and based on +PoC's :doc:`sub-namespace tree `. PoC's installation directory is +also referred to as ``PoCRoot``. + +* ``lib`` + Third party libraries like Coctb, OSVVM or VUnit are shipped in this folder. + The external library is stored in a sub directory named like the library. If + a library is available as a Git submodule, then it is linked as a submodule + for better version tracking. +* ``netlist`` + This is the output directory for pre-configured netlists, synthesized by PoC. + Netlists and related constaint files are the result of IP core synthesis + flows, either from PoC's source files or from vendor specific IP core files + like \*.xco files from Xilinx Core Generator. Generated IP cores are stored + in device sub-directories, because most netlists formats are device specific. + For example the IP core ``PoC.arith.prng`` created from source file + ``src\arith\arith_prng.vhdl`` generated for a Kintex-7 325T mounted on a + KC705 board will be copied to ``netlist\XC7K325T-2FFG900\arith\arith_prng.ngc`` + if Xilinx ISE XST is used for synthesis. +* ``py`` + The supporting Python infrastructure, the configuration files and the IP + core 'database' is stored in this directory. +* ``sim`` + Some of PoC's testbenches are shipped with pre-configured waveform views/ + waveform configuration files for selected simulators or waveform viewers. + If a testbench is launched in GUI mode (``--gui``) and a waveform view for + the choosen simulator is found, it's loaded as the default view. +* ``src`` + The source files of PoC's IP cores are stored in this directory. The IP + cores are grouped by their sub-namespace into sub-directories according to + the :doc:`sub-namespace tree `. See the paragraph below, for + how IP cores are named and how PoC core names map to the sub-namespace + hierachy and the resulting sub-namespace directory structure. +* ``tb`` + PoC is shipped with testbenches. All testbenches are categorized and stored + in sub-directories like the IP core, which is tested. +* ``tcl`` + Supporting Tcl files. +* ``temp`` + A pre-created temporary directors for various tool's intermediate outputs. + In case of errors in a used vendor tool or in PoC's infrastructure, this + directory contains intermediate files, log files and report files, which + can be used to analyze the error. +* ``tools`` + This directory contains miscelaneous files or scripts for external tools + like emacs, git or text editor syntax highlighting files. + +* ``ucf`` + Pre-configured constraint files (\*.ucf, \*.xdc, \*.sdc) for many FPGA + boards, containing physical (pin, placement) and timing constraints. + +* ``xst`` + Configuration files to synthesize PoC modules with Xilinx XST into a + netlist. + + +Namespaces and Modules +********************** + +Namespaces +========== + +PoC uses namespaces and sub-namespaces to categorize all VHDL and Verilog +modules. Despite VHDL doesn't support sub-namespaces yet, PoC already uses +sub-namespaces enforced by a strict naming schema. + +**Rules:** |br| +1. Namespace names are lower-case, underscore free, valid VHDL identifiers. |br| +2. A namespace name is unique, but can be part of a entity name. + + +Module Names +============ + +Module names are prefixed with its parents namespace name. A module name can +contain underscores to denote implementation variants of a module. + +**Rules:** |br| +3. Modul names are valid VHDL identifiers prefixed with its parent namespace's name. |br| +4. The first part of module name must not contain the parents namespace name. |br| + + +.. rubric:: Example 1 - ``PoC.fifo.cc_got`` + +For example a FIFO module with a common clock interface and a *got* +semantic is named ``PoC.fifo.cc_got`` (fully qualified name). This name can +be split at every dot and underscore sign, resulting in the following table of +name parts: + ++----------------+---------------+------------------------+--------------+ +| PoC | fifo | cc | got | ++================+===============+========================+==============+ +| Root Namespace | Sub-Namespace | Common Clock Interface | Got Semantic | ++----------------+---------------+------------------------+--------------+ + +Because ``PoC.fifo.cc_got`` refers to an IP core, the source file is located in +the ``\src`` directory. The (sub-)namespace of the PoC entity is +``fifo``, so it's stored in the sub-directory ``fifo``. The file name ``cc_got`` +FIFO is prefixed with the last sub-namespace: In this case ``fifo_``. This is +summarized in the following table: + ++----------------------------+---------------------------------------------+ +| Property | Value | ++============================+=============================================+ +| Fully Qualified Name | PoC.fifo.cc_got | ++----------------------------+---------------------------------------------+ +| VHDL entity name | fifo_cc_got | ++----------------------------+---------------------------------------------+ +| File name | fifo_cc_got.vhdl | ++----------------------------+---------------------------------------------+ +| IP Core Description File | \\src\\fifo\\fifo_cc_got.files | ++----------------------------+---------------------------------------------+ +| Source File Location | \\src\\fifo\\fifo_cc_got.vhdl | ++----------------------------+---------------------------------------------+ +| Testbench Location | \\tb\\fifo\\fifo_cc_got_tb.vhdl | ++----------------------------+---------------------------------------------+ +| Testbench Description File | \\tb\\fifo\\fifo_cc_got_tb.files | ++----------------------------+---------------------------------------------+ +| Waveform Description Files | \\sim\\fifo\\fifo_cc_got_tb.* | ++----------------------------+---------------------------------------------+ + +Other implementation variants are: + +* ``_dc`` – dependent clock / related clock +* ``_ic`` – independent clock / cross clock +* ``_got_tempgot`` – got interface extended by a temporary got interface +* ``_got_tempput`` – got interface extended by a temporary put interface + + +.. rubric:: Example 2 - ``PoC.mem.ocram.tdp`` + ++----------------+---------------+---------------+------------------------+ +| PoC | mem | ocram | tdp | ++================+===============+===============+========================+ +| Root Namespace | Sub-Namespace | Sub-Namespace | True-Dual-Port | ++----------------+---------------+---------------+------------------------+ + ++----------------------------+-----------------------------------------------+ +| Property | Value | ++============================+===============================================+ +| Fully Qualified Name | PoC.mem.ocram.tdp | ++----------------------------+-----------------------------------------------+ +| VHDL entity name | ocram_tdp | ++----------------------------+-----------------------------------------------+ +| File name | ocram_tdp.vhdl | ++----------------------------+-----------------------------------------------+ +| IP Core Description File | \\src\\mem\\ocram\\ocram_tdp.files | ++----------------------------+-----------------------------------------------+ +| Source File Location | \\src\\mem\\ocram\\ocram_tdp.vhdl | ++----------------------------+-----------------------------------------------+ +| Testbench Location | \\tb\\mem\\ocram\\ocram_tdp_tb.vhdl | ++----------------------------+-----------------------------------------------+ +| Testbench Description File | \\tb\\mem\\ocram\\ocram_tdp_tb.files | ++----------------------------+-----------------------------------------------+ +| Waveform Description Files | \\sim\\mem\\ocram\\ocram_tdp_tb.* | ++----------------------------+-----------------------------------------------+ + + +Note: Not all sub-namespace parts are include as a prefix in the name, only +the last one. + + +Signal Names +************ + +.. todo:: No documentation available. diff --git a/docs/References/WrapperScriptHookFiles.rst b/docs/References/WrapperScriptHookFiles.rst new file mode 100644 index 00000000..ad24a121 --- /dev/null +++ b/docs/References/WrapperScriptHookFiles.rst @@ -0,0 +1,85 @@ +Wrapper Script Hook Files +######################### + +The shell scripts ``poc.ps1`` and ``poc.sh`` can be customized though hook +files, which are executed before and after a PoC command is executed. The +wrapper scripts support 4 kinds of hook files: + * VendorPreHookFile + * ToolPreHookFile + * VendorPostHookFile + * ToolPostHookFile + +The wrapper scans the arguments given to the front-end script and searches +for known commands. If one is found, the hook files are scheduled before and +after the execution of the wrapped executable. The hook files are sourced +into the current execution and need to be located in the ``./py/Wrapper/Hooks`` +directory. + +A common use case is the preparation of special vendor or tool chain +environments. For example many EDA tools are using FlexLM as a license manager, +which needs the environments variable ``LM_LICENSE_FILE`` to be set. A +``PreHookFile`` can be used to load/export such an environment variable. + + + +Examples +******** + +**Mentor QuestaSim on Linux:** + +The PoC infrastructure is called with this command line: + +.. code-block:: Bash + + ./poc.sh -v vsim PoC.arith.prng + +The ``vsim`` command is recognized and the following events are scheduled: + + 1. ``source ./py/Wrapper/Hooks/Mentor.pre.sh`` + 2. ``source ./py/Wrapper/Hooks/Mentor.QuestaSim.pre.sh`` + 3. Execute ``./py/PoC.py -v vsim PoC.arith.prng`` + 4. ``source ./py/Wrapper/Hooks/Mentor.QuestaSim.post.sh`` + 5. ``source ./py/Wrapper/Hooks/Mentor.post.sh`` + +If a hook files doesn't exist, it's skipped. + + +**Mentor QuestaSim on Windows:** + +The PoC infrastructure is called with this command line: + +.. code-block:: PowerShell + + .\poc.ps1 -v vsim PoC.arith.prng + +The ``vsim`` command is recognized and the following events are scheduled: + + 1. ``. .\py\Wrapper\Hooks\Mentor.pre.ps1`` + 2. ``. .\py\Wrapper\Hooks\Mentor.QuestaSim.pre.ps1`` + 3. Execute ``.\py\PoC.py -v vsim PoC.arith.prng`` + 4. ``. .\py\Wrapper\Hooks\Mentor.QuestaSim.post.ps1`` + 5. ``. .\py\Wrapper\Hooks\Mentor.post.ps1`` + +If a hook files doesn't exist, it's skipped. + +FlexLM +****** + +Many EDA tools require an environment variable called ``LM_LICENSE_FILE``. +If no other tool settings are required, a common ``FlexLM.sh`` can be +generated. This file is used as a symlink target for each tool specific +hook file. + +**Content of the `FlexLM.sh` script:** + +.. code-block:: Bash + + export LM_LICENSE_FILE=1234@flexlm.company.com + + +**Create symlinks:** + +.. code-block:: Bash + + ln -s FlexLM.sh Altera.Quartus.pre.sh + ln -s FlexLM.sh Mentor.QuestaSim.pre.sh diff --git a/docs/References/index.rst b/docs/References/index.rst new file mode 100644 index 00000000..a25607cb --- /dev/null +++ b/docs/References/index.rst @@ -0,0 +1,17 @@ + +References +########## + +.. toctree:: + :maxdepth: 1 + + CommandReference + WrapperScriptHookFiles + FileFormats/index + Interfaces/index + NamingConventions + ListOfDevices + ListOfBoards + Glossary + KnownIssues + Licenses/index diff --git a/docs/UsingPoC/AddingIPCores.rst b/docs/UsingPoC/AddingIPCores.rst new file mode 100644 index 00000000..ee96bc4c --- /dev/null +++ b/docs/UsingPoC/AddingIPCores.rst @@ -0,0 +1,27 @@ + +Adding IP Cores to a Project +############################ + +Manually Addind IP Cores +************************ + +Adding IP Cores to Altera Quartus +================================= + +.. TODO:: No documentation available. + +Adding IP Cores to Lattice Diamond +================================== + +.. TODO:: No documentation available. + +Adding IP Cores to Xilinx ISE +============================= + +.. TODO:: No documentation available. + +Adding IP Cores to Xilinx Vivado +================================ + +.. TODO:: No documentation available. + diff --git a/docs/UsingPoC/Download.rst b/docs/UsingPoC/Download.rst new file mode 100644 index 00000000..64bbfbd6 --- /dev/null +++ b/docs/UsingPoC/Download.rst @@ -0,0 +1,198 @@ + +Downloading PoC +############### + +.. contents:: Contents of this Page + :local: + +Downloading from GitHub +*********************** + +The PoC-Library can be downloaded as a zip-file from GitHub. See the following +table, to choose your desired git branch. + ++----------+--------------------------------------------------------------------+ +| Branch | download link | ++==========+====================================================================+ +| master | `zip-file `_ | ++----------+--------------------------------------------------------------------+ +| release | `zip-file `_ | ++----------+--------------------------------------------------------------------+ + + +Downloading via ``git clone`` +***************************** + +The PoC-Library can be downloaded (cloned) with ``git clone`` from GitHub. +GitHub offers the transfer protocols HTTPS and SSH. You should use SSH if you +have a GitHub account and have already uploaded an OpenSSH public key to GitHub, +otherwise use HTTPS if you have no account or you want to use login credentials. + +The created folder :file:`\PoC` is used as :file:`` in later +instructions or on other pages in this documentation. + ++----------+----------------------------------------+ +| Protocol | GitHub Repository URL | ++==========+========================================+ +| HTTPS | https://github.com/VLSI-EDA/PoC.git | ++----------+----------------------------------------+ +| SSH | ssh://git@github.com:VLSI-EDA/PoC.git | ++----------+----------------------------------------+ + + +On Linux +======== + +Command line instructions to clone the PoC-Library onto a Linux machine with +HTTPS protocol: + +.. code-block:: Bash + + cd GitRoot + git clone --recursive "https://github.com/VLSI-EDA/PoC.git" PoC + cd PoC + git remote rename origin github + +Command line instructions to clone the PoC-Library onto a Linux machine machine +with SSH protocol: + +.. code-block:: Bash + + cd GitRoot + git clone --recursive "ssh://git@github.com:VLSI-EDA/PoC.git" PoC + cd PoC + git remote rename origin github + + +On OS X +======== + +Please see the Linux instructions. + + +On Windows +========== + +.. NOTE:: + + All Windows command line instructions are intended for :program:`Windows PowerShell`, + if not marked otherwise. So executing the following instructions in Windows + Command Prompt (:program:`cmd.exe`) won't function or result in errors! See + the :doc:`Requirements section ` on where to + download or update PowerShell. + +Command line instructions to clone the PoC-Library onto a Windows machine with +HTTPS protocol: + +.. code-block:: PowerShell + + cd GitRoot + git clone --recursive "https://github.com/VLSI-EDA/PoC.git" PoC + cd PoC + git remote rename origin github + +Command line instructions to clone the PoC-Library onto a Windows machine with +SSH protocol: + +.. code-block:: PowerShell + + cd GitRoot + git clone --recursive "ssh://git@github.com:VLSI-EDA/PoC.git" PoC + cd PoC + git remote rename origin github + + +.. NOTE:: + The option ``--recursive`` performs a recursive clone operation for all + linked `git submodules `_. + An additional ``git submodule init`` and ``git submodule update`` call is not + needed anymore. + + +Downloading via ``git submodule add`` +************************************* + +The PoC-Library is meant to be integrated into other HDL projects (preferably +Git versioned projects). Therefore it's recommended to create a library folder +and add the PoC-Library as a `git submodule `_. + +The following command line instructions will create a library folder :file:`lib\` +and clone PoC as a git submodule into the subfolder :file:`\lib\PoC\`. + +On Linux +======== + +Command line instructions to clone the PoC-Library onto a Linux machine with +HTTPS protocol: + +.. code-block:: Bash + + cd ProjectRoot + mkdir lib + git submodule add "https://github.com/VLSI-EDA/PoC.git" lib/PoC + cd lib/PoC + git remote rename origin github + cd ../.. + git add .gitmodules lib/PoC + git commit -m "Added new git submodule PoC in 'lib/PoC' (PoC-Library)." + +Command line instructions to clone the PoC-Library onto a Linux machine machine +with SSH protocol: + +.. code-block:: Bash + + cd ProjectRoot + mkdir lib + git submodule add "ssh://git@github.com:VLSI-EDA/PoC.git" lib/PoC + cd lib/PoC + git remote rename origin github + cd ../.. + git add .gitmodules lib/PoC + git commit -m "Added new git submodule PoC in 'lib/PoC' (PoC-Library)." + + +On OS X +======== + +Please see the Linux instructions. + + +On Windows +========== + +.. NOTE:: + + All Windows command line instructions are intended for :program:`Windows PowerShell`, + if not marked otherwise. So executing the following instructions in Windows + Command Prompt (:program:`cmd.exe`) won't function or result in errors! See + the :doc:`Requirements section ` on where to + download or update PowerShell. + +Command line instructions to clone the PoC-Library onto a Windows machine with +HTTPS protocol: + +.. code-block:: PowerShell + + cd + mkdir lib | cd + git submodule add "https://github.com/VLSI-EDA/PoC.git" PoC + cd PoC + git remote rename origin github + cd ..\.. + git add .gitmodules lib\PoC + git commit -m "Added new git submodule PoC in 'lib\PoC' (PoC-Library)." + +Command line instructions to clone the PoC-Library onto a Windows machine with +SSH protocol: + +.. code-block:: PowerShell + + cd + mkdir lib | cd + git submodule add "ssh://git@github.com:VLSI-EDA/PoC.git" PoC + cd PoC + git remote rename origin github + cd ..\.. + git add .gitmodules lib\PoC + git commit -m "Added new git submodule PoC in 'lib\PoC' (PoC-Library)." + diff --git a/docs/UsingPoC/Integration.rst b/docs/UsingPoC/Integration.rst new file mode 100644 index 00000000..ab106804 --- /dev/null +++ b/docs/UsingPoC/Integration.rst @@ -0,0 +1,179 @@ + +Integrating PoC into Projects +############################# + +.. contents:: Contents of this page + :local: + :depth: 2 + + +As a Git submodule +****************** + +The following command line instructions will integrate PoC into a existing Git +repository and register PoC as a Git submodule. Therefore a directory ``lib\PoC\`` +is created and the PoC-Library is cloned as a Git submodule into that directory. + + +On Linux +======== + +.. code-block:: Bash + + cd ProjectRoot + mkdir lib + cd lib + git submodule add https://github.com/VLSI-EDA/PoC.git PoC + cd PoC + git remote rename origin github + cd ../.. + git add .gitmodules lib\PoC + git commit -m "Added new git submodule PoC in 'lib/PoC' (PoC-Library)." + +On OS X +======== + +Please see the Linux instructions. + + +On Windows +========== + +.. NOTE:: + + All Windows command line instructions are intended for :program:`Windows PowerShell`, + if not marked otherwise. So executing the following instructions in Windows + Command Prompt (:program:`cmd.exe`) won't function or result in errors! See + the :doc:`Requirements section ` on where to + download or update PowerShell. + +.. code-block:: powershell + + cd ProjectRoot + mkdir lib | cd + git submodule add https://github.com/VLSI-EDA/PoC.git PoC + cd PoC + git remote rename origin github + cd ..\.. + git add .gitmodules lib\PoC + git commit -m "Added new git submodule PoC in 'lib\PoC' (PoC-Library)." + +.. seealso:: + :doc:`Configuring PoC on a Local System ` + + :doc:`Create PoC's VHDL Configuration Files ` + + + + +.. # + ## 3. Creating PoC's my_config and my_project Files + + The PoC-Library needs two VHDL files for it's configuration. These files are used + to determine the most suitable implementation depending on the provided platform + information. + + 1. The **my_config** file can easily be created from a template file provided by + PoC in `\src\common\my_config.vhdl.template`. + + The file should to be copyed into a projects source directory and rename into + `my_config.vhdl`. This file should be included into version control systems + and shared with other systems. my_config.vhdl defines two global constants, + which need to be adjusted: + + ```VHDL + constant MY_BOARD : string := "CHANGE THIS"; -- e.g. Custom, ML505, KC705, Atlys + constant MY_DEVICE : string := "CHANGE THIS"; -- e.g. None, XC5VLX50T-1FF1136, EP2SGX90FF1508C3 + ``` + + + Source file: `common/my_config.vhdl.template `_ + + + The easiest way is to define a board name and set `MY_DEVICE` to `None`. So + the device name is infered from the board information stored in `\src\common\board.vhdl`. + If the requested board is not known to PoC or it's custom made, then set + `MY_BOARD` to `Custom` and `MY_DEVICE` to the full FPGA device string. + + ##### Example 1: A "Stratix II GX Audio Video Development Kit" board: + + ```VHDL + constant MY_BOARD : string := "S2GXAV"; -- Stratix II GX Audio Video Development Kit + constant MY_DEVICE : string := "None"; -- infer from MY_BOARD + ``` + + ##### Example 2: A custom made Spartan-6 LX45 board: + + ```VHDL + constant MY_BOARD : string := "Custom"; + constant MY_DEVICE : string := "XC6SLX45-3CSG324"; + ``` + + 2. The **my_project** file can also be created from a template provided by PoC + in `\src\common\my_project.vhdl.template`. + + The file should to be copyed into a projects source directory and rename into + `my_project.vhdl`. This file **must not** be included into version control + systems - it's private to a host computer. my_project.vhdl defines two global + constants, which need to be adjusted: + + ```VHDL + constant MY_PROJECT_DIR : string := "CHANGE THIS"; -- e.g. "d:/vhdl/myproject/", "/home/me/projects/myproject/" + constant MY_OPERATING_SYSTEM : string := "CHANGE THIS"; -- e.g. "WINDOWS", "LINUX" + ``` + + ##### Example 1: A Windows System: + + ```VHDL + constant MY_PROJECT_DIR : string := "D:/git/GitHub/PoC/"; + constant MY_OPERATING_SYSTEM : string := "WINDOWS"; + ``` + + ##### Example 2: A Debian System: + + ```VHDL + constant MY_PROJECT_DIR : string := "/home/lehmann/git/GitHub/PoC/"; + constant MY_OPERATING_SYSTEM : string := "LINUX"; + ``` + + ## 4. Compiling shipped Xilinx IP cores to Netlists + + The PoC-Library are shipped with some pre-configured IP cores from Xilinx. These + IP cores are shipped as \*.xco files and need to be compiled to netlists (\*.ngc + files) and there auxillary files (\*.ncf files; \*.vhdl files; ...). This can be + done by invoking `PoC.py` through one of the provided wrapper scripts: + poc.[sh|ps1]. + + > **Is PoC already configured on the system?** If not, run the following + > configuration step, to tell PoC which tool chains are installed and where. + > Follow the instructions on the screen. See the [Configuration](Configuration) + > wiki page for more details. + > + > ```powershell + > cd + > .\poc.ps1 configure + > ``` + + Compiling needed IP cores from PoC for a KC705 board: + + ##### Linux: + + ```Bash + cd + cd lib/PoC + for i in `seq 1 15`; do + ./poc.sh coregen PoC.xil.ChipScopeICON_$i --board=KC705 + done + ``` + + ##### Windows (PowerShell): + + ```PowerShell + cd + cd lib\PoC + foreach ($i in 1..15) { + .\poc.ps1 coregen PoC.xil.ChipScopeICON_$i --board=KC705 + } + ``` + + diff --git a/docs/UsingPoC/Miscellaneous.rst b/docs/UsingPoC/Miscellaneous.rst new file mode 100644 index 00000000..b73c3e76 --- /dev/null +++ b/docs/UsingPoC/Miscellaneous.rst @@ -0,0 +1,44 @@ + +Miscellaneous +############# + +The directory ``PoCRoot\tools\`` contains several tools and addons to ease the +work with the PoC-Library and VHDL. + + +GNU Emacs +********* + +.. TODO:: No documentation available. + + +Git +*** + +* ``git-alias.setup.ps1``/``git-alias.setup.sh`` registers new global aliasses in Git + + * ``git tree`` - Prints the colored commit tree into the console + * ``git treea`` - Prints the colored commit tree into the console + + .. code-block:: Bash + + git config --global alias.tree 'log --decorate --pretty=oneline --abbrev-commit --date-order --graph' + git config --global alias.tree 'log --decorate --pretty=oneline --abbrev-commit --date-order --graph --all' + +Browse the `Git directory `_. + + +Notepad++ +********* + +The PoC-Library is shipped with syntax highlighting rules for `Notepad++ `_. +The following additional file types are supported: + +* PoC Configuration Files (*.ini) +* PoC *.Files Files (*.files) +* PoC *.Rules Files (*.rules) +* Xilinx User Constraint Files (*.ucf): ``Syntax Highlighting - Xilinx UCF`` + +Browse the `Notepad++ directory `_. + + diff --git a/docs/UsingPoC/PoCConfiguration.rst b/docs/UsingPoC/PoCConfiguration.rst new file mode 100644 index 00000000..66e08875 --- /dev/null +++ b/docs/UsingPoC/PoCConfiguration.rst @@ -0,0 +1,258 @@ + +Configuring PoC's Infrastructure +################################ + +To explore PoC's full potential, it's required to configure some paths and +synthesis or simulation tool chains. It's possible to relaunch the process +at any time, for example to register new tools or to update tool versions. + +.. contents:: Contents of this page + :local: + :depth: 2 + + +Overview +======== + +The setup process is started by invoking PoC's frontend script with the command +``configure``. Please follow the instructions on screen. Use the keyboard +buttons: :kbd:`Y` to accept, :kbd:`N` to decline, :kbd:`P` to skip/pass a step +and :kbd:`Return` to accept a default value displayed in brackets. + +Optionally, a vendor or tool chain name can be passed to the configuration +process to launch only its configuration routines. + +**On Linux:** + +.. code-block:: Bash + + cd ProjectRoot + ./lib/PoC/poc.sh configure + # with tool chain name + ./lib/PoC/poc.sh configure Xilinx.Vivado + +**On OS X** + +Please see the Linux instructions. + + +**On Windows** + +.. NOTE:: + + All Windows command line instructions are intended for :program:`Windows PowerShell`, + if not marked otherwise. So executing the following instructions in Windows + Command Prompt (:program:`cmd.exe`) won't function or result in errors! See + the :doc:`Requirements section ` on where to + download or update PowerShell. + +.. code-block:: PowerShell + + cd ProjectRoot + .\lib\PoC\poc.ps1 configure + # with tool chain name + .\lib\PoC\poc.ps1 configure Xilinx.Vivado + + +**Introduction screen:** + +.. code-block:: none + + PS D:\git\PoC> .\poc.ps1 configure + ================================================================================ + The PoC-Library - Service Tool + ================================================================================ + Explanation of abbreviations: + Y - yes P - pass (jump to next question) + N - no Ctrl + C - abort (no changes are saved) + Upper case or value in '[...]' means default value + -------------------------------------------------------------------------------- + + Configuring PoC + PoC version: v1.0.1 (found in git) + Installation directory: D:\git\PoC (found in environment variable) + + +The PoC-Library +=============== +PoC itself has a fully automated configuration routine. It detects if PoC is +under Git control. If so, it extracts the current version number from the latest +Git tag. The installation directory is infered from ``$PoCRootDirectory`` setup +by ``PoC.ps1`` or ``poc.sh``. + +.. code-block:: none + + Configuring PoC + PoC version: v1.0.1 (found in git) + Installation directory: D:\git\PoC (found in environment variable) + +Git +=== +.. NOTE:: + Setting up Git and Git developer settings, is an advanced feature recommended + for all developers interrested in providing Git pull requests or patches. + +.. code-block:: none + + Configuring Git + Git installation directory [C:\Program Files\Git]: + Install Git mechanisms for PoC developers? [y/N/p]: y + Install Git filters? [Y/n/p]: + Installing Git filters... + Install Git hooks? [Y/n/p]: + Installing Git hooks... + Setting 'pre-commit' hook for PoC... + +Aldec +===== +Configure the installation directory for all Aldec tools. + +.. code-block:: none + + Configuring Aldec + Are Aldec products installed on your system? [Y/n/p]: Y + Aldec installation directory [C:\Aldec]: + +Active-HDL +---------- +.. code-block:: none + + Configuring Aldec Active-HDL + Is Aldec Active-HDL installed on your system? [Y/n/p]: Y + Aldec Active-HDL version [10.3]: + Aldec Active-HDL installation directory [C:\Aldec\Active-HDL]: C:\Aldec\Active-HDL-Student-Edition + +Altera +====== +Configure the installation directory for all Altera tools. + +.. code-block:: none + + Configuring Altera + Are Altera products installed on your system? [Y/n/p]: Y + Altera installation directory [C:\Altera]: + +Quartus +------- +.. code-block:: none + + Configuring Altera Quartus + Is Altera Quartus-II or Quartus Prime installed on your system? [Y/n/p]: Y + Altera Quartus version [15.1]: 16.0 + Altera Quartus installation directory [C:\Altera\16.0\quartus]: + +ModelSim Altera Edition +----------------------- +.. code-block:: none + + Configuring ModelSim Altera Edition + Is ModelSim Altera Edition installed on your system? [Y/n/p]: Y + ModelSim Altera Edition installation directory [C:\Altera\15.0\modelsim_ae]: C:\Altera\16.0\modelsim_ase + +Lattice +======== +Configure the installation directory for all Lattice Semiconductor tools. + +.. code-block:: none + + Configuring Lattice + Are Lattice products installed on your system? [Y/n/p]: Y + Lattice installation directory [D:\Lattice]: + +Diamond +------- +.. code-block:: none + + Configuring Lattice Diamond + Is Lattice Diamond installed on your system? [Y/n/p]: > + Lattice Diamond version [3.7]: + Lattice Diamond installation directory [D:\Lattice\Diamond\3.7_x64]: + +Active-HDL Lattice Edition +-------------------------- +.. code-block:: none + + Configuring Active-HDL Lattice Edition + Is Aldec Active-HDL installed on your system? [Y/n/p]: Y + Active-HDL Lattice Edition version [10.2]: + Active-HDL Lattice Edition installation directory [D:\Lattice\Diamond\3.7_x64\active-hdl]: + +Mentor Graphics +=============== +Configure the installation directory for all mentor Graphics tools. + +.. code-block:: none + + Configuring Mentor + Are Mentor products installed on your system? [Y/n/p]: Y + Mentor installation directory [C:\Mentor]: + +QuestaSim +--------- +.. code-block:: none + + Configuring Mentor QuestaSim + Is Mentor QuestaSim installed on your system? [Y/n/p]: Y + Mentor QuestaSim version [10.4d]: 10.4c + Mentor QuestaSim installation directory [C:\Mentor\QuestaSim\10.4c]: C:\Mentor\QuestaSim64\10.4c + +Xilinx +====== +Configure the installation directory for all Xilinx tools. + +.. + If Xilinx products are available and they shall be configured in PoC, then + answer the following questions: + +.. code-block:: none + + Configuring Xilinx + Are Xilinx products installed on your system? [Y/n/p]: Y + Xilinx installation directory [C:\Xilinx]: + +ISE +--- +If an Xilinx ISE environment is available and shall be configured in PoC, then +answer the following questions: + +.. code-block:: none + + Configuring Xilinx ISE + Is Xilinx ISE installed on your system? [Y/n/p]: Y + Xilinx ISE installation directory [C:\Xilinx\14.7\ISE_DS]: + +Vivado +------ +If an Xilinx ISE environment is available and shall be configured in PoC, then +answer the following questions: + +.. code-block:: none + + Configuring Xilinx Vivado + Is Xilinx Vivado installed on your system? [Y/n/p]: Y + Xilinx Vivado version [2016.2]: + Xilinx Vivado installation directory [C:\Xilinx\Vivado\2016.2]: + +GHDL +==== +.. code-block:: none + + Configuring GHDL + Is GHDL installed on your system? [Y/n/p]: Y + GHDL installation directory [C:\Tools\GHDL\0.34dev]: + +GTKWave +======== +.. code-block:: none + + Configuring GTKWave + Is GTKWave installed on your system? [Y/n/p]: Y + GTKWave installation directory [C:\Tools\GTKWave\3.3.71]: + +Hook Files +========== + +PoC's wrapper scripts can be customized through pre- and post-hook file. See +:doc:`Wrapper Script Hook Files ` for +more details. + diff --git a/docs/UsingPoC/PrecompilingVendorLibraries.rst b/docs/UsingPoC/PrecompilingVendorLibraries.rst new file mode 100644 index 00000000..1f28f2c8 --- /dev/null +++ b/docs/UsingPoC/PrecompilingVendorLibraries.rst @@ -0,0 +1,477 @@ + +Pre-Compiling Vendor Libraries +############################## + +.. contents:: Contents of this Page + :local: + + +Overview +******** + +Running vendor specific testbenches may require pre-compiled vendor libraries. +Some vendors ship their simulators with diverse pre-compiled libraries, but these +don't include primitive libraries from hardware vendors. More over, many auxillary +libraries are outdated. Hardware vendors ship their tool chains with pre-compile +scripts or user guides to pre-compile the primitive libraries for a list of +supported simulators on a target system. + +PoC is shipped with a set of pre-compile scripts to offer a unified interface +and common storage for all supported vendor's pre-compile procedures. The scripts +are located in ``\tools\precompile\`` and the output is stored in +``\temp\precompiled\\``. + + +Supported Simulators +******************** + +The current set of pre-compile scripts support these simulators: + ++------------+------------------------------+--------------+--------------+---------------+--------------------+ +| Vendor | Simulator and Edition | Altera | Lattice | Xilinx (ISE) | Xilinx (Vivado) | ++============+==============================+==============+==============+===============+====================+ +| T. Gingold | GHDL with ``--std=93c`` |br| | yes |br| | yes |br| | yes |br| | yes |br| | +| | GHDL with ``--std=08`` | yes | yes | yes | yes | ++------------+------------------------------+--------------+--------------+---------------+--------------------+ +| Aldec | Active-HDL |br| | planned |br| | planned |br| | planned |br| | planned |br| | +| | Active-HDL Lattice Ed. |br| | planned |br| | shipped |br| | planned |br| | planned |br| | +| | Reviera-PRO | planned | planned | planned | planned | ++------------+------------------------------+--------------+--------------+---------------+--------------------+ +| Mentor | ModelSim |br| | yes |br| | yes |br| | yes |br| | yes |br| | +| | ModelSim Altera Ed. |br| | shipped |br| | yes |br| | yes |br| | yes |br| | +| | QuestaSim | yes | yes | yes | yes | ++------------+------------------------------+--------------+--------------+---------------+--------------------+ +| Xilinx | ISE Simulator |br| | | | shipped |br| | not supported |br| | +| | Vivado Simulator | | | not supported | shipped | ++------------+------------------------------+--------------+--------------+---------------+--------------------+ + + +FPGA Vendor's Primitive Libraries +********************************* + +Altera +====== + +.. note:: + The Altera Quartus tool chain needs to be configured in PoC. |br| + See :doc:`Configuring PoC's Infrastruture ` for further details. + +On Linux +-------- + +.. code-block:: Bash + + # Example 1 - Compile for all Simulators + ./tools/precompile/compile-altera.sh --all + # Example 2 - Compile only for GHDL and VHDL-2008 + ./tools/precompile/compile-altera.sh --ghdl --vhdl2008 + +**List of command line arguments:** + ++------------------+-------------------------------+ +| Common Option | Description | ++=====+============+===============================+ +| -h | --help | Print embedded help page(s) | ++-----+------------+-------------------------------+ +| -c | --clean | Clean-up directories | ++-----+------------+-------------------------------+ +| -a | --all | Compile for all simulators | ++-----+------------+-------------------------------+ +| | --ghdl | Compile for GHDL | ++-----+------------+-------------------------------+ +| | --questa | Compile for QuestaSim | ++-----+------------+-------------------------------+ +| | --vhdl93 | Compile only for VHDL-93 | ++-----+------------+-------------------------------+ +| | --vhdl2008 | Compile only for VHDL-2008 | ++-----+------------+-------------------------------+ + + +On Windows +---------- + +.. code-block:: PowerShell + + # Example 1 - Compile for all Simulators + .\tools\precompile\compile-altera.ps1 -All + # Example 2 - Compile only for GHDL and VHDL-2008 + .\tools\precompile\compile-altera.ps1 -GHDL -VHDL2008 + +**List of command line arguments:** + ++-----------------+-------------------------------+ +| Common Option | Description | ++=====+===========+===============================+ +| -h | -Help | Print embedded help page(s) | ++-----+-----------+-------------------------------+ +| -c | -Clean | Clean-up directories | ++-----+-----------+-------------------------------+ +| -a | -All | Compile for all simulators | ++-----+-----------+-------------------------------+ +| | -GHDL | Compile for GHDL | ++-----+-----------+-------------------------------+ +| | -Questa | Compile for QuestaSim | ++-----+-----------+-------------------------------+ +| | -VHDL93 | Compile only for VHDL-93 | ++-----+-----------+-------------------------------+ +| | -VHDL2008 | Compile only for VHDL-2008 | ++-----+-----------+-------------------------------+ + + +Lattice +======== + +.. note:: + The Lattice Diamond tool chain needs to be configured in PoC. |br| + See :doc:`Configuring PoC's Infrastruture ` for further details. + +On Linux +-------- + +.. code-block:: Bash + + # Example 1 - Compile for all Simulators + ./tools/precompile/compile-lattice.sh --all + # Example 2 - Compile only for GHDL and VHDL-2008 + ./tools/precompile/compile-lattice.sh --ghdl --vhdl2008 + +**List of command line arguments:** + ++------------------+-------------------------------+ +| Common Option | Description | ++=====+============+===============================+ +| -h | --help | Print embedded help page(s) | ++-----+------------+-------------------------------+ +| -c | --clean | Clean-up directories | ++-----+------------+-------------------------------+ +| -a | --all | Compile for all simulators | ++-----+------------+-------------------------------+ +| | --ghdl | Compile for GHDL | ++-----+------------+-------------------------------+ +| | --questa | Compile for QuestaSim | ++-----+------------+-------------------------------+ +| | --vhdl93 | Compile only for VHDL-93 | ++-----+------------+-------------------------------+ +| | --vhdl2008 | Compile only for VHDL-2008 | ++-----+------------+-------------------------------+ + + +On Windows +---------- + +.. code-block:: PowerShell + + # Example 1 - Compile for all Simulators + .\tools\precompile\compile-lattice.ps1 -All + # Example 2 - Compile only for GHDL and VHDL-2008 + .\tools\precompile\compile-lattice.ps1 -GHDL -VHDL2008 + +**List of command line arguments:** + ++-----------------+-------------------------------+ +| Common Option | Description | ++=====+===========+===============================+ +| -h | -Help | Print embedded help page(s) | ++-----+-----------+-------------------------------+ +| -c | -Clean | Clean-up directories | ++-----+-----------+-------------------------------+ +| -a | -All | Compile for all simulators | ++-----+-----------+-------------------------------+ +| | -GHDL | Compile for GHDL | ++-----+-----------+-------------------------------+ +| | -Questa | Compile for QuestaSim | ++-----+-----------+-------------------------------+ +| | -VHDL93 | Compile only for VHDL-93 | ++-----+-----------+-------------------------------+ +| | -VHDL2008 | Compile only for VHDL-2008 | ++-----+-----------+-------------------------------+ + +Xilinx ISE +========== + +.. note:: + The Xilinx ISE tool chain needs to be configured in PoC. |br| + See :doc:`Configuring PoC's Infrastruture ` for further details. + +On Linux +-------- + +.. code-block:: Bash + + # Example 1 - Compile for all Simulators + ./tools/precompile/compile-xilinx-ise.sh --all + # Example 2 - Compile only for GHDL and VHDL-2008 + ./tools/precompile/compile-xilinx-ise.sh --ghdl --vhdl2008 + +**List of command line arguments:** + ++------------------+-------------------------------+ +| Common Option | Description | ++=====+============+===============================+ +| -h | --help | Print embedded help page(s) | ++-----+------------+-------------------------------+ +| -c | --clean | Clean-up directories | ++-----+------------+-------------------------------+ +| -a | --all | Compile for all simulators | ++-----+------------+-------------------------------+ +| | --ghdl | Compile for GHDL | ++-----+------------+-------------------------------+ +| | --questa | Compile for QuestaSim | ++-----+------------+-------------------------------+ +| | --vhdl93 | Compile only for VHDL-93 | ++-----+------------+-------------------------------+ +| | --vhdl2008 | Compile only for VHDL-2008 | ++-----+------------+-------------------------------+ + + +On Windows +---------- + +.. code-block:: PowerShell + + # Example 1 - Compile for all Simulators + .\tools\precompile\compile-xilinx-ise.ps1 -All + # Example 2 - Compile only for GHDL and VHDL-2008 + .\tools\precompile\compile-xilinx-ise.ps1 -GHDL -VHDL2008 + +**List of command line arguments:** + ++-----------------+-------------------------------+ +| Common Option | Description | ++=====+===========+===============================+ +| -h | -Help | Print embedded help page(s) | ++-----+-----------+-------------------------------+ +| -c | -Clean | Clean-up directories | ++-----+-----------+-------------------------------+ +| -a | -All | Compile for all simulators | ++-----+-----------+-------------------------------+ +| | -GHDL | Compile for GHDL | ++-----+-----------+-------------------------------+ +| | -Questa | Compile for QuestaSim | ++-----+-----------+-------------------------------+ +| | -VHDL93 | Compile only for VHDL-93 | ++-----+-----------+-------------------------------+ +| | -VHDL2008 | Compile only for VHDL-2008 | ++-----+-----------+-------------------------------+ + +Xilinx Vivado +============= + +.. note:: + The Xilinx Vivado tool chain needs to be configured in PoC. |br| + See :doc:`Configuring PoC's Infrastruture ` for further details. + +On Linux +-------- + +.. code-block:: Bash + + # Example 1 - Compile for all Simulators + ./tools/precompile/compile-xilinx-vivado.sh --all + # Example 2 - Compile only for GHDL and VHDL-2008 + ./tools/precompile/compile-xilinx-vivado.sh --ghdl --vhdl2008 + +**List of command line arguments:** + ++------------------+-------------------------------+ +| Common Option | Description | ++=====+============+===============================+ +| -h | --help | Print embedded help page(s) | ++-----+------------+-------------------------------+ +| -c | --clean | Clean-up directories | ++-----+------------+-------------------------------+ +| -a | --all | Compile for all simulators | ++-----+------------+-------------------------------+ +| | --ghdl | Compile for GHDL | ++-----+------------+-------------------------------+ +| | --questa | Compile for QuestaSim | ++-----+------------+-------------------------------+ +| | --vhdl93 | Compile only for VHDL-93 | ++-----+------------+-------------------------------+ +| | --vhdl2008 | Compile only for VHDL-2008 | ++-----+------------+-------------------------------+ + + +On Windows +---------- + +.. code-block:: PowerShell + + # Example 1 - Compile for all Simulators + .\tools\precompile\compile-xilinx-vivado.ps1 -All + # Example 2 - Compile only for GHDL and VHDL-2008 + .\tools\precompile\compile-xilinx-vivado.ps1 -GHDL -VHDL2008 + +**List of command line arguments:** + ++-----------------+-------------------------------+ +| Common Option | Description | ++=====+===========+===============================+ +| -h | -Help | Print embedded help page(s) | ++-----+-----------+-------------------------------+ +| -c | -Clean | Clean-up directories | ++-----+-----------+-------------------------------+ +| -a | -All | Compile for all simulators | ++-----+-----------+-------------------------------+ +| | -GHDL | Compile for GHDL | ++-----+-----------+-------------------------------+ +| | -Questa | Compile for QuestaSim | ++-----+-----------+-------------------------------+ +| | -VHDL93 | Compile only for VHDL-93 | ++-----+-----------+-------------------------------+ +| | -VHDL2008 | Compile only for VHDL-2008 | ++-----+-----------+-------------------------------+ + +Third-Party Libraries +********************* + +OSVVM +===== + +On Linux +-------- + +.. code-block:: Bash + + # Example 1 - Compile for all Simulators + ./tools/precompile/compile-osvvm.sh --all + # Example 2 - Compile only for GHDL + ./tools/precompile/compile-osvvm.sh --ghdl + +**List of command line arguments:** + ++------------------+-------------------------------+ +| Common Option | Description | ++=====+============+===============================+ +| -h | --help | Print embedded help page(s) | ++-----+------------+-------------------------------+ +| -c | --clean | Clean-up directories | ++-----+------------+-------------------------------+ +| -a | --all | Compile for all simulators | ++-----+------------+-------------------------------+ +| | --ghdl | Compile for GHDL | ++-----+------------+-------------------------------+ +| | --questa | Compile for QuestaSim | ++-----+------------+-------------------------------+ + + +On Windows +---------- + +.. code-block:: PowerShell + + # Example 1 - Compile for all Simulators + .\tools\precompile\compile-osvvm.ps1 -All + # Example 2 - Compile only for GHDL + .\tools\precompile\compile-osvvm.ps1 -GHDL + +**List of command line arguments:** + ++-----------------+-------------------------------+ +| Common Option | Description | ++=====+===========+===============================+ +| -h | -Help | Print embedded help page(s) | ++-----+-----------+-------------------------------+ +| -c | -Clean | Clean-up directories | ++-----+-----------+-------------------------------+ +| -a | -All | Compile for all simulators | ++-----+-----------+-------------------------------+ +| | -GHDL | Compile for GHDL | ++-----+-----------+-------------------------------+ +| | -Questa | Compile for QuestaSim | ++-----+-----------+-------------------------------+ + + +Simulator Adapters +****************** + +Cocotb +====== + + +On Linux +-------- + +.. attention:: + This is an experimental compile script. + +.. code-block:: Bash + + # Example 1 - Compile for all Simulators + ./tools/precompile/compile-cocotb.sh --all + # Example 2 - Compile only for GHDL + ./tools/precompile/compile-cocotb.sh --ghdl + +**List of command line arguments:** + ++------------------+-------------------------------+ +| Common Option | Description | ++=====+============+===============================+ +| -h | --help | Print embedded help page(s) | ++-----+------------+-------------------------------+ +| -c | --clean | Clean-up directories | ++-----+------------+-------------------------------+ +| -a | --all | Compile for all simulators | ++-----+------------+-------------------------------+ +| | --ghdl | Compile for GHDL | ++-----+------------+-------------------------------+ +| | --questa | Compile for QuestaSim | ++-----+------------+-------------------------------+ + + +On Windows +---------- + +.. attention:: + This is an experimental compile script. + +.. code-block:: PowerShell + + # Example 1 - Compile for all Simulators + .\tools\precompile\compile-cocotb.ps1 -All + # Example 2 - Compile only for GHDL + .\tools\precompile\compile-cocotb.ps1 -GHDL + +**List of command line arguments:** + ++-----------------+-------------------------------+ +| Common Option | Description | ++=====+===========+===============================+ +| -h | -Help | Print embedded help page(s) | ++-----+-----------+-------------------------------+ +| -c | -Clean | Clean-up directories | ++-----+-----------+-------------------------------+ +| -a | -All | Compile for all simulators | ++-----+-----------+-------------------------------+ +| | -GHDL | Compile for GHDL | ++-----+-----------+-------------------------------+ +| | -Questa | Compile for QuestaSim | ++-----+-----------+-------------------------------+ + +.. comment + + Supported Simulators: + + +--------------------------------+------------------------------------------------------------------------------+ + | Simulator Name | Comment | + +================================+==============================================================================+ + | GHDL | VHDL-93 version is compiled with ``--std=93c`` and ``--ieee=synopsys``. |br| | + | | VHDL-2008 version is compiled with ``--std=08`` and ``--ieee=synopsys``. | + +--------------------------------+------------------------------------------------------------------------------+ + | Mentor ModelSim Altera Edition | Already includes all Altera primitives. | + +--------------------------------+------------------------------------------------------------------------------+ + | Mentor QuestaSim | | + +--------------------------------+------------------------------------------------------------------------------+ + + +---------------------------------------------------+--------------------------------------------+ + | Compile Script Location (Bash) | Output Directory | + +===================================================+============================================+ + | ``/tools/precompile/compile-altera.sh`` | ``/temp/precompiled/vsim/altera`` | + +---------------------------------------------------+--------------------------------------------+ + + +---------------------------------------------------+--------------------------------------------+ + | Compile Script Location (PowerShell) | Output Directory | + +===================================================+============================================+ + | ``\tools\precompile\compile-altera.ps1`` | ``\temp\precompiled\vsim\altera`` | + +---------------------------------------------------+--------------------------------------------+ + diff --git a/docs/UsingPoC/ProjectManagement.rst b/docs/UsingPoC/ProjectManagement.rst new file mode 100644 index 00000000..0343913e --- /dev/null +++ b/docs/UsingPoC/ProjectManagement.rst @@ -0,0 +1,14 @@ + +Project Management +################## + +Overview +******** + + +Solutions +********* + + +Projects +******** diff --git a/docs/UsingPoC/Requirements.rst b/docs/UsingPoC/Requirements.rst new file mode 100644 index 00000000..be08a693 --- /dev/null +++ b/docs/UsingPoC/Requirements.rst @@ -0,0 +1,141 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + +.. include:: + + +Requirements +############ + +.. contents:: Contents of this Page + :local: + +The PoC-Library comes with some scripts to ease most of the common tasks, like +running testbenches or generating IP cores. We choose to use Python 3 as a +platform independent scripting environment. All Python scripts are wrapped in +Bash or PowerShell scripts, to hide some platform specifics of Darwin, Linux or +Windows. + +Common requirements: +******************** + +* Programming Languages and Runtime Environments: + + * `Python 3 `_ (|geq| 3.5): + + * `colorama `_ + * `py-flags `_ + + All Python requirements are listed in `requirements.txt `_ and can be installed via: |br| + ``sudo python3.5 -m pip install -r requirements.txt`` + +* Synthesis tool chains: + + * Altera Quartus |geq| 13.0 or + * Lattice Diamond or + * Xilinx ISE 14.7 [#f1]_ or + * Xilinx Vivado [#f2]_ + +* Simulation tool chains + + * Aldec Active-HDL or + * Mentor Graphics ModelSim Altera Edition or + * Mentor Graphics QuestaSim or + * Xilinx ISE Simulator 14.7 or + * Xilinx Vivado Simulator |geq| 2016.1 [#f3]_ or + * `GHDL `_ |geq| 0.34dev and `GTKWave `_ |geq| 3.3.70 + + +Linux specific requirements: +**************************** + +* Debian and Ubuntu specific: + + * bash is configured as :file:`/bin/sh` (`read more `_) |br| + ``dpkg-reconfigure dash`` + + +Optional Tools on Linux: +======================== + +* Git + The command line tools to manage Git repositories. It's possible to extend + the shell prompt with Git information. + +* SmartGit + A Git client to handle complex Git flows in a GUI. + +* `Generic Colouriser `_ (grc) |geq| 1.9 + Colorizes outputs of foreign scripts and programs. GRC is hosted on `GitHub `_ + The latest *.deb installation packages can be downloaded `here `_. + + +Mac OS specific requirements: +***************************** + +* Bash |geq| 4.3 + Mac OS is shipped with Bash 3.2. Use Homebrew to install an up-to-date Bash |br| + ``brew install bash`` + +* coreutils + Mac OS' ``readlink`` program has a different behavior than the Linux version. + The ``coreutils`` package installs a GNU readlink clone called ``greadlink``. |br| + ``brew install coreutils`` + + +Optional Tools on Mac OS: +========================= + +* Git + The command line tools to manage Git repositories. It's possible to extend + the shell prompt with Git information. + +* SmartGit or SourceTree + A Git client to handle complex Git flows in a GUI. + +* `Generic Colouriser `_ (grc) |geq| 1.9 + Colorizes outputs of foreign scripts and programs. GRC is hosted on `GitHub `_ |br| + ``brew install Grc`` + + +Windows specific requirements: +****************************** + +* PowerShell |geq| 4.0 + PowerShell shipped with Windows since Vista. It is a part if the Windows + Management Framework. If the required version not already included in + Windows, it can be downloaded from microsoft.com: `WMF 4.0 `_, + `WMF 5.0 `_ (recommended). + + * Allow local script execution (`read more `_) |br| + ``Set-ExecutionPolicy RemoteSigned`` + * PowerShell Community Extensions (PSCX) |geq| 3.2 |br| + The latest PSCX can be downloaded from `PowerShellGallery `_ + + +Optional Tools on Windows: +========================== + +* Git (MSys-Git) + The command line tools to manage Git repositories. + +* SmartGit or SourceTree + A Git client to handle complex Git flows in a GUI. + +* `posh-git `_ + PowerShell integration for Git |br| + Installing posh-git with `PsGet `_ package manager: ``Install-Module posh-git`` + + +------------------------------------------ + +.. rubric:: Footnotes + +.. [#f1] Xilinx discontinued ISE since Oct. 2013. The last release was 14.7. +.. [#f2] Due to numerous bugs in the Xilinx Vivado Synthesis (incl. 2016.1), PoC + can offer only a restricted Vivado support. See PoC's ``Vivado`` branch for a + set of workarounds. The list of issues is documented on the + :doc:`Known Issues ` page. +.. [#f3] Due to numerous bugs in the Xilinx Simulator (incl. 2016.1), PoC can + offer only a restricted Vivado support. The list of issues is documented on + the :doc:`Known Issues ` page. diff --git a/docs/UsingPoC/Simulation.rst b/docs/UsingPoC/Simulation.rst new file mode 100644 index 00000000..c48e1519 --- /dev/null +++ b/docs/UsingPoC/Simulation.rst @@ -0,0 +1,420 @@ + +Simulation +########## + +.. contents:: Contents of this Page + :local: + + +Overview +******** + +The Python Infrastructure shipped with the PoC-Library can launch manual, +half-automated and fully automated testbenches. The testbench can be run in +command line or GUI mode. If available, the used simulator is launched with +pre-configured waveform files. This can be done by invoking one of PoC's +frontend script: + +* **poc.sh:** ``poc.sh `` |br| + Use this fronend script on Darwin, Linux and Unix platforms. +* **poc.ps1:** ``poc.ps1 `` |br| + Use this frontend script Windows platforms. |br| + + .. ATTENTION:: + All Windows command line instructions are intended for Windows + PowerShell, if not marked otherwise. So executing the following instructions + in Windows Command Prompt (``cmd.exe``) won't function or result in errors! + +.. seealso:: + + :doc:`PoC Configuration ` + See the Configuration page on how to configure PoC and your installed + simulator tool chains. This is required to invoke the simulators. + :doc:`Supported Simulators ` + See the Intruction page for a list of supported simulators. + + +Quick Example +************* + +The following quick example uses the GHDL Simulator to analyze, elaborate and +simulate a testbench for the module ``arith_prng`` (Pseudo Random Number +Generator - PRNG). The VHDL file ``arith_prng.vhdl`` is located at +``PoCRoot\src\arith`` and virtually a member in the `PoC.arith` namespace. +So the module can be identified by an unique name: ``PoC.arith.prng``, which is +passed to the frontend script. + +.. rubric:: Example 1: + +.. code-block:: PowerShell + + cd PoCRoot + .\poc.ps1 ghdl PoC.arith.prng + +The CLI command ``ghdl`` chooses *GHDL Simulator* as the simulator and +passes the fully qualified PoC entity name ``PoC.arith.prng`` as a parameter +to the tool. All required source file are gathered and compiled to an +executable. Afterwards this executable is launched in CLI mode and it's outputs +are displayed in console: + +.. image:: /_static/images/ghdl/arith_prng_tb.posh.png + :target: /_static/images/ghdl/arith_prng_tb.posh.png + :alt: PowerShell console output after running PoC.arith.prng with GHDL. + +Each testbench uses PoC's simulation helper packages to count asserts and to +track active stimuli and checker processes. After a completed simulation run, +an report is written to STDOUT or the simulator's console. Note the line +``SIMULATION RESULT = PASSED``. For each simulated PoC entity, a line in the +overall report is created. It lists the runtime per testbench and the simulation +status (``... ERROR``, ``FAILED``, ``NO ASSERTS`` or ``PASSED``). + +.. rubric:: Example 2: + +Passing an additional option ``--gui`` to the service tool, opens the testbench +in GUI-mode. If a waveform configuration file is present (e.g. a ``*.gtkw`` +file for GTKWave), then it is preloaded into the simulator's waveform viewer. + +.. code-block:: PowerShell + + cd PoCRoot + .\poc.ps1 ghdl PoC.arith.prng --gui + +The opened waveform viewer and displayed waveform should look like this: + +.. image:: /_static/images/gtkwave/arith_prng_tb.png + :target: /_static/images/gtkwave/arith_prng_tb.png + :alt: GTKWave waveform view of PoC.arith.prng. + + +Vendor Specific Testbenches +*************************** + +PoC is shipped with a set of well known FPGA development boards. This set is +extended by a list of generic boards, named after each supported FPGA vendor. +These generic boards can be used in simulations to select a representative +FPGA of a supported device vendor. If no board or device name is passed to a +testbench run, the ``GENERIC`` board is chosen. + ++--------------+--------------+-----------------+ +| Board Name | Target Board | Target Device | ++==============+==============+=================+ +| GENERIC | GENERIC | GENERIC | ++--------------+--------------+-----------------+ +| Altera | DE4 | Stratix-IV 230 | ++--------------+--------------+-----------------+ +| Lattice | ECP5Versa | ECP5-45UM | ++--------------+--------------+-----------------+ +| Xilinx | KC705 | Kintex-7 325T | ++--------------+--------------+-----------------+ + +A vendor specific testbench can be launched by passing either ``--board=xxx`` or +``--device=yyy`` as an additional parameter to the PoC scripts. + +.. code-block:: PowerShell + + # Example 1 - A Lattice board + .\poc.ps1 ghdl PoC.arith.prng --board=Lattice + # Example 2 - A Altera Stratix IV board + .\poc.ps1 ghdl PoC.arith.prng --board=DE4 + # Example 3 - A Xilinx Kintex-7 325T device + .\poc.ps1 ghdl PoC.arith.prng --device=XC7K325T-2FFG900 + +.. note:: + Running vendor specific testbenches may require pre-compiled vendor libraries. + Some simulators are shipped with diverse pre-compiled libraries, others include + scripts or user guides to pre-compile them on the target system. + + PoC is shipped with a set of pre-compile scripts to offer a unified interface + and common storage for all supported vendor's pre-compile procedures. See + :doc:`Pre-Compiling Vendor Libraries `. + +Running a Single Testbench +************************** + +A testbench run is supervised by PoC's ``PoCRoot\py\PoC.py`` service tool, +which offers a consistent interface to all simulators. Unfortunately, every +platform has it's specialties, so a wrapper script is needed as abstraction from +the host's operating system. Depending on the choosen tool chain, the wrapper +script will source or invoke the vendor tool's environment scripts to pre-load +the needed environment variables, paths or license file settings. + +The order of options to the frontend script is as following: +`` `` + +The frontend offers several common options: + ++-----------------+-------------------------------+ +| Common Option | Description | ++=====+===========+===============================+ +| -q | --quiet | Quiet-mode (print nothing) | ++-----+-----------+-------------------------------+ +| -v | --verbose | Print more messages | ++-----+-----------+-------------------------------+ +| -d | --debug | Debug mode (print everything) | ++-----+-----------+-------------------------------+ +| | --dryrun | Run in dry-run mode | ++-----+-----------+-------------------------------+ + +One of the following supported simulators can be choosen, if installed and +configured in PoC: + ++-----------+---------------------------------------------+ +| Simulator | Description | ++===========+=============================================+ +| asim | Active-HDL Simulator | ++-----------+---------------------------------------------+ +| cocotb | Cocotb simulation using QuestaSim Simulator | ++-----------+---------------------------------------------+ +| ghdl | GHDL Simulator | ++-----------+---------------------------------------------+ +| isim | Xilinx ISE Simulator | ++-----------+---------------------------------------------+ +| vsim | QuestaSim Simulator or ModelSim | ++-----------+---------------------------------------------+ +| xsim | Xilinx Vivado Simulator | ++-----------+---------------------------------------------+ + +A testbench run can be interrupted by sending a keyboard interrupt to Python. +On most operating systems this is done by pressing :kbd:`Ctrl` + :kbd:`C`. If +PoC runs multiple testbenches at once, all finished testbenches are reported with +there testbench result. The aborted testbench will be listed as errored. + + +Aldec Active-HDL +================ + +The command to invoke a simulation using Active-HDL is ``asim`` followed by a list of +PoC entities. The following options are supported for Active-HDL: + ++--------------------------+---------------------------------------------------------+ +| Simulator Option | Description | ++====+=====================+=========================================================+ +| | --board= | Specify a target board. | ++----+---------------------+---------------------------------------------------------+ +| | --device= | Specify a target device. | ++----+---------------------+---------------------------------------------------------+ +| | --std=[87|93|02|08] | Select a VHDL standard. Default: 08 | ++----+---------------------+---------------------------------------------------------+ + +.. NOTE:: + GUI mode for Active-HDL is not yet supported. + +.. rubric:: Example: + +.. code-block:: PowerShell + + cd PoCRoot + .\poc.ps1 asim PoC.arith.prng --std=93 + + +Cocotb with QuestaSim backend +============================= + +The command to invoke a Cocotb simulation using QuestaSim is ``cocotb`` followed +by a list of PoC entities. The following options are supported for Cocotb: + ++--------------------------+---------------------------------------------------------+ +| Simulator Option | Description | ++====+=====================+=========================================================+ +| | --board= | Specify a target board. | ++----+---------------------+---------------------------------------------------------+ +| | --device= | Specify a target device. | ++----+---------------------+---------------------------------------------------------+ +| -g | --gui | Start the simulation in the QuestaSim GUI. | ++----+---------------------+---------------------------------------------------------+ + +.. NOTE:: + Cocotb is currently only on Linux with QuestaSim supported. We are working to + support the Windows platform and the GHDL backend. + +.. rubric:: Example: + +.. code-block:: Bash + + cd PoCRoot + .\poc.ps1 cocotb PoC.cache.par + + +GHDL (plus GTKwave) +=================== + +The command to invoke a simulation using GHDL is ``ghdl`` followed by a list of +PoC entities. The following options are supported for GHDL: + ++--------------------------+---------------------------------------------------------+ +| Simulator Option | Description | ++====+=====================+=========================================================+ +| | --board= | Specify a target board. | ++----+---------------------+---------------------------------------------------------+ +| | --device= | Specify a target device. | ++----+---------------------+---------------------------------------------------------+ +| -g | --gui | Start GTKwave, if installed. Open *.gtkw, if available. | ++----+---------------------+---------------------------------------------------------+ +| | --std=[87|93|02|08] | Select a VHDL standard. Default: 08 | ++----+---------------------+---------------------------------------------------------+ + +.. rubric:: Example: + +.. code-block:: PowerShell + + cd PoCRoot + .\poc.ps1 ghdl PoC.arith.prng --board=Atlys -g + + +Mentor Graphics QuestaSim +========================= + +The command to invoke a simulation using QuestaSim or ModelSim is ``vsim`` +followed by a list of PoC entities. The following options are supported for +QuestaSim: + ++--------------------------+---------------------------------------------------------+ +| Simulator Option | Description | ++====+=====================+=========================================================+ +| | --board= | Specify a target board. | ++----+---------------------+---------------------------------------------------------+ +| | --device= | Specify a target device. | ++----+---------------------+---------------------------------------------------------+ +| -g | --gui | Start the simulation in the QuestaSim GUI. | ++----+---------------------+---------------------------------------------------------+ +| | --std=[87|93|02|08] | Select a VHDL standard. Default: 08 | ++----+---------------------+---------------------------------------------------------+ + +.. rubric:: Example: + +.. code-block:: PowerShell + + cd PoCRoot + .\poc.ps1 vsim PoC.arith.prng --board=DE4 --gui + + +Xilinx ISE Simulator +==================== + +The command to invoke a simulation using ISE Simulator (isim) is ``isim`` +followed by a list of PoC entities. The following options are supported for +ISE Simulator: + ++--------------------------+---------------------------------------------------------+ +| Simulator Option | Description | ++====+=====================+=========================================================+ +| | --board= | Specify a target board. | ++----+---------------------+---------------------------------------------------------+ +| | --device= | Specify a target device. | ++----+---------------------+---------------------------------------------------------+ +| -g | --gui | Start the simulation in the ISE Simulator GUI (iSim). | ++----+---------------------+---------------------------------------------------------+ + +.. rubric:: Example: + +.. code-block:: PowerShell + + cd PoCRoot + .\poc.ps1 isim PoC.arith.prng --board=Atlys -g + + +Xilinx Vivado Simulator +======================= + +The command to invoke a simulation using Vivado Simulator (isim) is ``xsim`` +followed by a list of PoC entities. The following options are supported for +Vivado Simulator: + ++--------------------------+---------------------------------------------------------+ +| Simulator Option | Description | ++====+=====================+=========================================================+ +| | --board= | Specify a target board. | ++----+---------------------+---------------------------------------------------------+ +| | --device= | Specify a target device. | ++----+---------------------+---------------------------------------------------------+ +| -g | --gui | Start Vivado in simulation mode. | ++----+---------------------+---------------------------------------------------------+ +| | --std=[93|08] | Select a VHDL standard. Default: 93 | ++----+---------------------+---------------------------------------------------------+ + +.. rubric:: Example: + +.. code-block:: PowerShell + + cd PoCRoot + .\poc.ps1 xsim PoC.arith.prng --board=Atlys -g + + +Running a Group of Testbenches +****************************** + +Each simulator can be invoked with a space seperated list of PoC entiries or a +wildcard at the end of the fully qualified entity name. + +Supported wildcard patterns are ``*`` and ``?``. Question mark refers to all +entities in a PoC (sub-)namespace. Asterisk refers to all PoC entiries in the +current namespace and all sub-namespaces. + +**Examples for testbenches groups:** + ++--------------------------------------+-----------------------------------------------------------------------------------+ +| PoC entity list | Description | ++======================================+===================================================================================+ +| PoC.arith.prng | A single PoC entity: ``arith_prng`` | ++--------------------------------------+-----------------------------------------------------------------------------------+ +| PoC.* | All entities in the whole library | ++--------------------------------------+-----------------------------------------------------------------------------------+ +| PoC.io.ddrio.? | All entities in ``PoC.io.ddrio``: ``ddrio_in``, ``ddrio_inout``, ``ddrio_out`` | ++--------------------------------------+-----------------------------------------------------------------------------------+ +| PoC.fifo.* PoC.cache.* PoC.dstruct.* | All FIFO, cache and data-structure testbenches. | ++--------------------------------------+-----------------------------------------------------------------------------------+ + + + +.. code-block:: PowerShell + + cd PoCRoot + .\poc.ps1 -q asim PoC.arith.prng PoC.io.ddrio.* PoC.sort.lru_cache + +**Resulting output:** + +.. image:: /_static/images/active-hdl/multiple.png + :target: /_static/images/active-hdl/multiple.png + :alt: Report after running multiple testbenches in Active-HDL. + + +Continuous Integration (CI) +*************************** + +All PoC testbenches are executed on every GitHub upload (push) via Travis-CI. +The testsuite runs all testbenches for the virtual board ``GENERIC`` with an +FPGA device called ``GENERIC``. We can't run vendor dependent testbenches, +because we can't upload the vendor simulation libraries to Travis-CI. + +To reproduce the Travis-CI results on a local machine, run the following command. +The ``-q`` option, launches the frontend in quiet mode to reduce the command line +messages: + +.. code-block:: PowerShell + + cd PoCRoot + .\poc.ps1 -q ghdl PoC.* + +.. image:: /_static/images/ghdl/PoC_all.png + :target: /_static/images/ghdl/PoC_all.png + :alt: Overall testbench report after running all PoC testbenches in GHDL. + +If the vendor libraries are available and pre-compiled, then it's also possible +to run a CI flow for a specific vendor. This is an Altera example for the +Terrasic DE4 board: + +.. code-block:: PowerShell + + cd PoCRoot + .\poc.ps1 -q vsim PoC.* --board=DE4 + + +.. seealso:: + + :doc:`PoC Configuration ` + See the Configuration page on how to configure PoC and your installed + simulator tool chains. This is required to invoke the simulators. + `Latest Travis-CI Report `_ + Browse the list of branches at Travis-CI.org. + + diff --git a/docs/UsingPoC/Synthesis.rst b/docs/UsingPoC/Synthesis.rst new file mode 100644 index 00000000..7c533070 --- /dev/null +++ b/docs/UsingPoC/Synthesis.rst @@ -0,0 +1,328 @@ + +Synthesis +######### + +.. contents:: Contents of this Page + :local: + + +Overview +******** + +The Python infrastructure shipped with the PoC-Library can launch manual, +half-automated and fully automated synthesis runs. This can be done by invoking +one of PoC's frontend script: + +* **poc.sh:** ``poc.sh `` |br| + Use this fronend script on Darwin, Linux and Unix platforms. +* **poc.ps1:** ``poc.ps1 `` |br| + Use this frontend script Windows platforms. |br| + + .. ATTENTION:: + All Windows command line instructions are intended for Windows + PowerShell, if not marked otherwise. So executing the following instructions + in Windows Command Prompt (``cmd.exe``) won't function or result in errors! + +.. seealso:: + + :doc:`PoC Configuration ` + See the Configuration page on how to configure PoC and your installed + synthesis tool chains. This is required to invoke the compilers. + :doc:`Supported Compiler ` + See the Intruction page for a list of supported compilers. + + +.. seealso:: + :doc:`List of Supported FPGA Devices ` + See this list to find a supported and well known target device. + :doc:`List of Supported Development Boards ` + See this list to find a supported and well known development board. + +Quick Example +************* + +The following quick example uses the Xilinx Systesis Tool (XST) to synthesize a +netlist for IP core ``arith_prng`` (Pseudo Random Number Generator - PRNG). The +VHDL file ``arith_prng.vhdl`` is located at ``PoCRoot\src\arith`` and +virtually a member in the `PoC.arith` namespace. So the module can be identified +by an unique name: ``PoC.arith.prng``, which is passed to the frontend script. + +.. rubric:: Example 1: + +.. code-block:: PowerShell + + cd PoCRoot + .\poc.ps1 xst PoC.arith.prng --board=KC705 + +The CLI command ``xst`` chooses *Xilinx Synthesis Tool* as the synthesizer and +passes the fully qualified PoC entity name ``PoC.arith.prng`` as a parameter +to the tool. Additionally, the development board name is required to load the +correct ``my_config.vhdl`` file. All required source file are gathered and +synthesized to a netlist. + +.. image:: /_static/images/xst/arith_prng.posh.png + :target: /_static/images/xst/arith_prng.posh.png + :alt: PowerShell console output after running PoC.arith.prng with XST. + + +Running a single Synthesis +************************** + +A synthesis run is supervised by PoC's ``PoCRoot\py\PoC.py`` service tool, +which offers a consistent interface to all synthesizers. Unfortunately, every +platform has it's specialties, so a wrapper script is needed as abstraction from +the host's operating system. Depending on the choosen tool chain, the wrapper +script will source or invoke the vendor tool's environment scripts to pre-load +the needed environment variables, paths or license file settings. + +The order of options to the frontend script is as following: +`` `` + +The frontend offers several common options: + ++-----------------+-------------------------------+ +| Common Option | Description | ++=====+===========+===============================+ +| -q | --quiet | Quiet-mode (print nothing) | ++-----+-----------+-------------------------------+ +| -v | --verbose | Print more messages | ++-----+-----------+-------------------------------+ +| -d | --debug | Debug mode (print everything) | ++-----+-----------+-------------------------------+ +| | --dryrun | Run in dry-run mode | ++-----+-----------+-------------------------------+ + +One of the following supported synthesizers can be choosen, if installed and +configured in PoC: + ++-----------+--------------------------------------------------+ +| Simulator | Description | ++===========+==================================================+ +| quartus | Altera Quartus II or Quartus Prime | ++-----------+--------------------------------------------------+ +| lse | Lattice Diamond - Lattice Synthesis Engine (LSE) | ++-----------+--------------------------------------------------+ +| xst | Xilinx ISE Systhesis Tool (XST) | ++-----------+--------------------------------------------------+ +| coregen | Xilinx ISE Core Generator (CoreGen) | ++-----------+--------------------------------------------------+ +| vivado | Xilinx Vivado Synthesis | ++-----------+--------------------------------------------------+ + + +Altera Quartus +============== + +The command to invoke a synthesis using Altera Quartus II or Quartus Prime is +``quartus`` followed by a list of PoC entities. The following options are +supported for Quartus: + ++--------------------------+---------------------------------------------------------+ +| Simulator Option | Description | ++====+=====================+=========================================================+ +| | --board= | Specify a target board. | ++----+---------------------+---------------------------------------------------------+ +| | --device= | Specify a target device. | ++----+---------------------+---------------------------------------------------------+ + +.. rubric:: Example: + +.. code-block:: PowerShell + + cd PoCRoot + .\poc.ps1 quartus PoC.arith.prng --board=DE4 + + +Lattice Diamond +=============== + +The command to invoke a synthesis using Altera Quartus II or Quartus Prime is +``quartus`` followed by a list of PoC entities. The following options are +supported for Quartus: + ++--------------------------+---------------------------------------------------------+ +| Simulator Option | Description | ++====+=====================+=========================================================+ +| | --board= | Specify a target board. | ++----+---------------------+---------------------------------------------------------+ +| | --device= | Specify a target device. | ++----+---------------------+---------------------------------------------------------+ + +.. rubric:: Example: + +.. code-block:: PowerShell + + cd PoCRoot + .\poc.ps1 quartus PoC.arith.prng --board=DE4 + + +Xilinx ISE Synthesis Tool (XST) +=============================== + +The command to invoke a synthesis using Altera Quartus II or Quartus Prime is +``quartus`` followed by a list of PoC entities. The following options are +supported for Quartus: + ++--------------------------+---------------------------------------------------------+ +| Simulator Option | Description | ++====+=====================+=========================================================+ +| | --board= | Specify a target board. | ++----+---------------------+---------------------------------------------------------+ +| | --device= | Specify a target device. | ++----+---------------------+---------------------------------------------------------+ + +.. rubric:: Example: + +.. code-block:: PowerShell + + cd PoCRoot + .\poc.ps1 quartus PoC.arith.prng --board=DE4 + + +Xilinx ISE Core Generator +========================= + +The command to invoke a synthesis using Altera Quartus II or Quartus Prime is +``quartus`` followed by a list of PoC entities. The following options are +supported for Quartus: + ++--------------------------+---------------------------------------------------------+ +| Simulator Option | Description | ++====+=====================+=========================================================+ +| | --board= | Specify a target board. | ++----+---------------------+---------------------------------------------------------+ +| | --device= | Specify a target device. | ++----+---------------------+---------------------------------------------------------+ + +.. rubric:: Example: + +.. code-block:: PowerShell + + cd PoCRoot + .\poc.ps1 quartus PoC.arith.prng --board=DE4 + +Xilinx Vivado Synthesis +======================= + +The command to invoke a synthesis using Altera Quartus II or Quartus Prime is +``quartus`` followed by a list of PoC entities. The following options are +supported for Quartus: + ++--------------------------+---------------------------------------------------------+ +| Simulator Option | Description | ++====+=====================+=========================================================+ +| | --board= | Specify a target board. | ++----+---------------------+---------------------------------------------------------+ +| | --device= | Specify a target device. | ++----+---------------------+---------------------------------------------------------+ + +.. rubric:: Example: + +.. code-block:: PowerShell + + cd PoCRoot + .\poc.ps1 quartus PoC.arith.prng --board=DE4 + + + + + + + + + + + + + + + + + +.. # + + Generated Netlists from PoC and IP Core Generators + ************************************************** + + The PoC-Library supports the generation of netlists from pre-configured + vendor IP cores (e.g. Xilinx Core Generator) or from bundled and pre-configured + PoC entities. This can be done by invoking PoC's Service Tool through the wrapper + script: `poc.[sh|ps1]`. + + 1 Common Explanations + ********************* + + A netlist is always compiled for a specific platform. In case of an FPGA it's + the exact device name. The name can be passed by `--device=` command + line option to the script. An alternative is the `--board=` option. For + a list of well-known board names, PoC knows the soldered FPGA device. + + + 2 Compiling pre-configured Xilinx IP Cores (*.xco files) to Netlists + ********************************************************************** + + **The PoC-Library** is shipped with some pre-configured IP cores from Xilinx. + These IP cores are shipped as \*.xco files and need to be compiled to netlists + (\*.ngc files) and there auxillary files (\*.ncf files; \*.vhdl files; ...). IP + core configuration files (e.g. *.xco) are stored as regular source files in the + `\src` directory. + + ```PowerShell + .\poc.ps1 [-q] [-v] [-d] coregen [--device=|--board=] + ``` + + Use Case - Compiling all ChipScopeICON IP Cores + =============================================== + + PoC has an abstraction layer [`PoC.xil.ChipScopeICON`][xil_ChipScopeICON] to + abstract all possible Chipscope Integrated Controller (ICON) cores + configurations in one VHDL module. An ICON can be configured with 1 to 15 + ChipScope control ports. To use the abstraction layer it's required to + pre-compile all 15 IP core variations. + + The following example compiles the first IP core with 1 port for a Kintex-7 + 325T as soldered onto a KC705 board. The resulting netlist and auxillary files + are copied to `PoCRoot\netlist\XC7K325T-2FFG900\xil\`. The Xilinx ISE tool + flow requires an extension IP core search directory for *XST* and *Translate* + (`-sd` option). + + ```PowerShell + cd + .\poc.ps1 coregen PoC.xil.ChipScopeICON_1 --board=KC705 + ``` + + The compilation can be automated in a for-each loop for all IP cores: + + ```PowerShell + cd + foreach ($i in 1..15) + { .\poc.ps1 coregen PoC.xil.ChipScopeICON_$_ --board=KC705 + } + ``` + + + Compiling pre-configured PoC IP Cores (bundle of VHDL files) to Netlists + ************************************************************************** + + *Documentation is still incomplete* + + The IP core filelist file (*.files) and the XST option file (*.xst) are stored + in the ``PoCRoot\xst\`` directory. + + ```PowerShell + .\poc.ps1 [-q] [-v] [-d] xst [--device=|--board=] + ``` + + Use Case - Compiling a Gigabit Ethernet UDP/IP Stack for a KC705 board + ====================================================================== + + `PoC.net.stack.UDPv4` + + *Documentation is still incomplete* + + The resulting netlist and auxillary files + are copied to ``PoCRoot\netlist\XC7K325T-2FFG900\net\stack``. The Xilinx ISE tool + flow requires an extension IP core search directory for *XST* and *Translate* + (`-sd` option). + + [xil_ChipScopeICON]: ../src/xil/xil_ChipScopeICON.vhdl diff --git a/docs/UsingPoC/VHDLConfiguration.rst b/docs/UsingPoC/VHDLConfiguration.rst new file mode 100644 index 00000000..84abc147 --- /dev/null +++ b/docs/UsingPoC/VHDLConfiguration.rst @@ -0,0 +1,84 @@ + +Creating my_config/my_project.vhdl +################################## + +The PoC-Library needs two VHDL files for it's configuration. These files are +used to determine the most suitable implementation depending on the provided +platform information. These files are also used to select appropiate work +arounds. + +Create my_config.vhdl +********************* + +The **my_config.vhdl** file can easily be created from the template file +``my_config.vhdl.template`` provided by PoC in ``PoCRoot\src\common``. +(View source on `GitHub `_.) +Copy this file into the projects source directory and renamed into +``my_config.vhdl``. + +This file should be included into version control systems and shared with other +systems. ``my_config.vhdl`` defines three global constants, which need to be +adjusted: + +.. code-block:: VHDL + + constant MY_BOARD : string := "CHANGE THIS"; -- e.g. Custom, ML505, KC705, Atlys + constant MY_DEVICE : string := "CHANGE THIS"; -- e.g. None, XC5VLX50T-1FF1136, EP2SGX90FF1508C3 + constant MY_VERBOSE : boolean := FALSE; -- activate report statements in VHDL subprograms + +The easiest way is to define a board name and set ``MY_DEVICE`` to ``None``. +So the device name is infered from the board information stored in ``PoCRoot\src\common\board.vhdl``. +If the requested board is not known to PoC or it's custom made, then set +``MY_BOARD`` to ``Custom`` and ``MY_DEVICE`` to the full FPGA device string. + +**Example 1: A "Stratix II GX Audio Video Development Kit" board:** + +.. code-block:: VHDL + + constant MY_BOARD : string := "S2GXAV"; -- Stratix II GX Audio Video Development Kit + constant MY_DEVICE : string := "None"; -- infer from MY_BOARD + +**Example 2: A custom made Spartan-6 LX45 board:** + +.. code-block:: VHDL + + constant MY_BOARD : string := "Custom"; + constant MY_DEVICE : string := "XC6SLX45-3CSG324"; + + +Create my_project.vhdl +********************** + +The **my_project.vhdl** file can also be created from a template file +``my_project.vhdl.template`` provided by PoC in ``PoCRoot\src\common``. + +The file should to be copyed into a projects source directory and renamed +into ``my_project.vhdl``. This file **must not** be included into version +control systems -- it's private to a computer. ``my_project.vhdl`` defines two +global constants, which need to be adjusted: + +.. code-block:: VHDL + + constant MY_PROJECT_DIR : string := "CHANGE THIS"; -- e.g. "d:/vhdl/myproject/", "/home/me/projects/myproject/" + constant MY_OPERATING_SYSTEM : string := "CHANGE THIS"; -- e.g. "WINDOWS", "LINUX" + +**Example 1: A Windows System:** + +.. code-block:: VHDL + + constant MY_PROJECT_DIR : string := "D:/git/GitHub/PoC/"; + constant MY_OPERATING_SYSTEM : string := "WINDOWS"; + +**Example 2: A Debian System:** + +.. code-block:: VHDL + + constant MY_PROJECT_DIR : string := "/home/paebbels/git/GitHub/PoC/"; + constant MY_OPERATING_SYSTEM : string := "LINUX"; + +.. seealso:: + :doc:`Running one or more testbenches ` + The installation can be checked by running one or more of PoC's testbenches. + :doc:`Running one or more netlist generation flows ` + The installation can also be checked by running one or more of PoC's + synthesis flows. diff --git a/docs/UsingPoC/index.rst b/docs/UsingPoC/index.rst new file mode 100644 index 00000000..4e0c6206 --- /dev/null +++ b/docs/UsingPoC/index.rst @@ -0,0 +1,87 @@ + +Using PoC +######### + +PoC can be used in several ways, if all :doc:`Requirements ` +are fulfilled. Chose one of the following integration kinds: + +* Stand-Alone IP Core Library: + Download PoC as archive file (\*.zip) from GitHub as latest branch copy or + as tagged release file. IP cores can be copyed into one or more destination + projects or the projects link to the selected IP core source files. + + **Advantages:** + + * Simple and fast setup, configuring PoC is optional. + * Needs less disk space than a Git repository. + * After a configuration, PoC's additional features: simulation, synthesis, + etc. can be used. + + **Disadvantages:** + + * Manual updating via download and file overwrites. + * Updated IP cores need to be copyed again into the destination project. + * Using different PoC versions in different projects is not possible. + * No possibility to contribute bugfixes and extensions via Git pull requests. + + **Next steps:** |br| + 1. See :doc:`Downloads ` for how to download a stand-alone version (*.zip-file) of the PoC-Library. |br| + 2. See :doc:`Configuration ` for how to configure PoC on a local system. + +* Stand-Alone IP Core Library cloned from Git: + Download PoC via ``git clone`` from GitHub as latest branch copy. IP cores + can be copyed into one or more destination projects or the projects link to + the selected IP core source files. + + **Advantages:** + + * Simple and fast setup, configuring PoC is optional. + * Access to the newest commits on a branch: New IP cores, new features, bugfixes. + * Fast and simple updates via ``git pull``. + * After a configuration, PoC's additional features: simulation, synthesis, + etc. can be used. + * Contribute bugfixes and extensions via Git pull requests. + + **Disadvantages:** + + * Updated IP cores need to be copyed again into the destination project. + * Using different PoC versions in different projects is not possible + + **Next steps:** |br| + 1. See :doc:`Downloads ` for how to clone a stand-alone version of the PoC-Library. |br| + 2. See :doc:`Configuration ` for how to configure PoC on a local system. + +* Embedded IP Core Library as Git Submodule: + Integrate PoC as a Git submodule into the destination projects Git repository. + + **Advantages:** + + * Simple and fast setup, configuring PoC is optional, but recommended. + * Access to the newest commits on a branch: New IP cores, new features, bugfixes. + * Fast and simple updates via ``git pull``. + * After a configuration, PoC's additional features: simulation, synthesis, + etc. can be used. + * Moreover, some PoC infrastructure features can be used in the hosting + repository and project as well. + * Contribute bugfixes and extensions via Git pull requests. + * Version linking between hosting Git and PoC. + + **Next steps:** |br| + 1. See :doc:`Integration ` for how to integrate PoC as a Git submodule into an existing Git. |br| + 2. See :doc:`Configuration ` for how to configure PoC on a local system. + + +.. toctree:: + :hidden: + + Requirements + Download + Integration + PoCConfiguration + VHDLConfiguration + AddingIPCores + Simulation + Synthesis + ProjectManagement + PrecompilingVendorLibraries + Miscellaneous diff --git a/docs/WhatIsPoC/History.rst b/docs/WhatIsPoC/History.rst new file mode 100644 index 00000000..6d650d05 --- /dev/null +++ b/docs/WhatIsPoC/History.rst @@ -0,0 +1,51 @@ + +What is the History of PoC? +########################### + +In the past years, a lot of "IP cores" were developed at the chair of VLSI +design [#f1]_ . This lose set of HDL designs was gathered in an old-fashioned +CVS repository and grow over the years to a collection of basic HDL +implementations like ALUs, FIFOs, UARTs or RAM controllers. For their final +projects (bachelor, master, diploma thesis) students got access to PoC, so they +could focus more on their main tasks than wasting time in developing and +testing basic IP implementations from scratch. But the library was initially +for internal and educational use only. + +As a university chair for VLSI design, we have a wide range of different FPGA +prototyping boards from various vendors and device families as well as +generations. So most of the IP cores were developed for both major FPGA vendor +platforms and their specific vendor tool chains. The main focus was to describe +hardware in a more flexible and generic way, so that an IP core could be reused +on multiple target platforms. + +As the number of cores increased, the set of common functions and types +increased too. In the end PoC is not only a collection of IP cores, its also +shipped with a set of packages containing utility functions, new types and type +conversions, which are used by most of the cores. This makes PoC a *library*, +not only a *collection* of IPs. + +As we started to search for ways to publish IP cores and maybe the whole +PoC-Library, we found several platforms on the Internet, but none was very +convincing. Some collective websites contained inactive projects, others were +controlled by companies without the possibility to contribute and the majority +was a long list of private projects with at most a handful of IP cores. Another +disagreement were the used license types for these projects. We decided to use +the Apache License, because it has no copyleft rule, a patent clause and allows +commercial usage. + +We transformed the old CVS repository into three Git repositories: An internal +repository for the full set of IP cores (incl. classified code), a public one +and a repository for examples, called PoC-Examples, both hosted on GitHub. PoC +itself can be integrated into other HDL projects as a library directory or a Git +submodule. The preferred usage is the submodule integration, which has the +advantage of linked repository versions from hosting Git and the submodule Git. +This is already exemplified by our PoC-Examples repository. + +---------------------------------------------------- + +.. rubric:: Footnotes + +.. [#f1] The PoC-Library is published and maintained by the **Chair for VLSI + Design, Diagnostics and Architecture** - Faculty of Computer Science, + Technische Universität Dresden, Germany |br| + `http://tu-dresden.de/inf/vlsi-eda `_ diff --git a/docs/WhatIsPoC/SupportedToolChains.rst b/docs/WhatIsPoC/SupportedToolChains.rst new file mode 100644 index 00000000..1798587e --- /dev/null +++ b/docs/WhatIsPoC/SupportedToolChains.rst @@ -0,0 +1,52 @@ + +.. include:: + +Which Tool Chains are supported? +################################ + +The PoC-Library and its Python-based infrastructure currently supports the following free and commercial vendor tool chains: + +* Synthesis Tool Chains: + + * **Altera Quartus** |br| + Tested with Quartus-II |geq| 13.0. |br| + Tested with Quartus Prime |geq| 15.1. + + * **Lattice Diamond** |br| + Tested with Diamond |geq| 3.6. + + * **Xilinx ISE** |br| + Only ISE 14.7 inclusive Core Generator 14.7 is supported. + + * **Xilinx PlanAhead** |br| + Only PlanAhead 14.7 is supported. + + * **Xilinx Vivado** |br| + Tested with Vivado |geq| 2015.4. |br| + Due to a limited VHDL language support compared to ISE 14.7, some PoC IP cores need special work arounds. See the synthesis documention section for Vivado for more details. + + +* Simulation Tool Chains: + + * **Aldec Active-HDL** |br| + Tested with Active-HDL Student-Edition 10.3 |br| + Tested with Active-HDL Lattice Edition 10.2 + + * **Cocotb with Mentor QuestaSim backend** |br| + Tested with Mentor QuestaSim 10.4d + + * **Mentor Graphics QuestaSim/ModelSim** |br| + Tested with ModelSim Altera Edition 10.3d and ModelSim Altera Starter Edition 10.3d |br| + Tested with Mentor QuestaSim 10.4d + + * **Xilinx ISE Simulator** |br| + Tested with ISE Simulator (iSim) 14.7. |br| + The Python infrastructure supports isim, but PoC's simulation helper packages and testbenches rely on VHDL-2008 features, which are not supported by isim. + + * **Xilinx Vivado Simulator** |br| + Tested with Vivado Simulator (xsim) |geq| 2016.1. |br| + The Python infrastructure supports xsim, but PoC's simulation helper packages and testbenches rely on VHDL-2008 features, which are not fully supported by xsim, yet. + + * **GHDL** + **GTKWave** |br| + Tested with `GHDL `_ |geq| 0.34dev and `GTKWave `_ |geq| 3.3.70 |br| + Due to ungoing development and bugfixes, we encourage to use the newest GHDL version. diff --git a/docs/WhatIsPoC/WhoUsesPoC.rst b/docs/WhatIsPoC/WhoUsesPoC.rst new file mode 100644 index 00000000..dd026e2d --- /dev/null +++ b/docs/WhatIsPoC/WhoUsesPoC.rst @@ -0,0 +1,23 @@ + +Who uses PoC? +############# + +PoC has a related Git repository called `PoC-Examples `_ +on GitHub. This repository hosts a list of example and reference implementations +of the PoC-Library. Additional to reading an IP cores documention and viewing +its characteristic stimulus waveform in a simulation, it can helper to +investigate an IP core usage example from that repository. + + +* `The Q27 Project `_ |br| + 27-Queens Puzzle: Massively Parellel Enumeration and Solution Counting + +* `Reconfigurable Cloud Computing Framework (RC2F) `_ |br| + An FPGA computing framework for virtualization and cloud integration. + +* `PicoBlaze-Library `_ |br| + The PicoBlaze-Library offers several PicoBlaze devices and code routines to + extend a common PicoBlaze environment to a little System on a Chip (SoC or SoFPGA). + +* `PicoBlaze-Examples `_ |br| + A SoFPGA reference implementation, based on the PoC-Library and the PicoBlaze-Library. diff --git a/docs/WhatIsPoC/WhyShouldIUsePoC.rst b/docs/WhatIsPoC/WhyShouldIUsePoC.rst new file mode 100644 index 00000000..c34748f9 --- /dev/null +++ b/docs/WhatIsPoC/WhyShouldIUsePoC.rst @@ -0,0 +1,31 @@ + +Why should I use PoC? +##################### + +Here is a brief list of advantages: + +* We explicitly use the wording *PoC-Library* rather then *collection*, because + PoC's packages and IP cores build an ecosystem. Complex IP cores are build + on-top of basic IP cores - they are no lose set of cores. The cores offer a + clean interface and can be configured by many generic parameters. + +* PoC is target independent: It's possible to switch the target device or even + the device vendor without switching the IP core. + + +.. TODO:: + + Use a well tested set of packages to ease the use of VHDL + + Use a well tested set of simulation helpers + + Run testbenches in various simulators. + + Run synthesis tests in varous synthesis tools. + + Compare hardware usage for different target platfroms. + + Supports simulation with vendor primitive libraries, ships with script to pre-compile vendor libraries. + + Vendor tools have bugs, check you IP cores when a new tool release is available, before changing code base + diff --git a/docs/WhatIsPoC/index.rst b/docs/WhatIsPoC/index.rst new file mode 100644 index 00000000..3a757407 --- /dev/null +++ b/docs/WhatIsPoC/index.rst @@ -0,0 +1,59 @@ + +What is PoC? +############ + +PoC - "Pile of Cores" provides implementations for often required hardware +functions such as Arithmetic Units, Caches, Clock-Domain-Crossing Circuits, +FIFOs, RAM wrappers, and I/O Controllers. The hardware modules are typically +provided as VHDL or Verilog source code, so it can be easily re-used in a +variety of hardware designs. + +All hardware modules use a common set of VHDL packages to share new VHDL types, +sub-programs and constants. Additionally, a set of simulation helper packages +eases the writing of testbenches. Because PoC hosts a huge amount of IP cores, +all cores are grouped into sub-namespaces to build a better hierachy. + +Various simulation and synthesis tool chains are supported to interoperate with +PoC. To generalize all supported free and commercial vendor tool chains, PoC is +shipped with a Python based Infrastruture to offer a command line based frontend. + + +.. rubric:: The PoC-Library pursues the following five goals: + +* independence in the platform, target, vendor and tool chain +* generic, efficient, resource sparing and fast implementations of IP cores +* optimized for several device architectures, if suitable +* supportive scripts to ease the IP core handling with all supported + vendor tools on all listed operating systems +* ship all IP cores with testbenches for local and online verification + +.. rubric:: In detail the PoC-Library is: + +* synthesizable for ASIC and FPGA devices, e.g. from Altera, Lattice, Xilinx, ..., +* supports a wide range of simulation and synthesis tool chains, and is +* executable on several host platforms: Darwin, Linux or Windows. + +This is achieved by using generic HDL descriptions, which work with most +synthesis and simulation tools mentioned above. If this is not the case, then +PoC uses vendor or tool dependent work-arounds. These work-arounds can be +different implementations switched by VHDL `generate` statements as well as +different source files containing modified implementations. + +One special feature of PoC is it, that the user has not to take care of such +implementation switchings. PoC's IP cores decide on their own what's the *best* +implementation for the chosen target platform. For this feature, PoC implements +a configuration package, which accepts a well-known development board name or a +target device string. For example a FPGA device string is decoded into: vendor, +device, generation, family, subtype, speed grade, pin count, etc. Out of these +information, the PoC component can for example implement a vendor specific +carry-chain description to speed up an algorithm or group computation units to +effectively use 6-input LUTs. + + +.. toctree:: + :hidden: + + History + SupportedToolChains + WhyShouldIUsePoC + WhoUsesPoC diff --git a/docs/_static/.gitempty b/docs/_static/.gitempty new file mode 100644 index 00000000..e69de29b diff --git a/docs/_static/images/.gitempty b/docs/_static/images/.gitempty new file mode 100644 index 00000000..e69de29b diff --git a/docs/_static/images/active-hdl/multiple.png b/docs/_static/images/active-hdl/multiple.png new file mode 100644 index 00000000..6e154d21 Binary files /dev/null and b/docs/_static/images/active-hdl/multiple.png differ diff --git a/docs/_static/images/ghdl/PoC_all.png b/docs/_static/images/ghdl/PoC_all.png new file mode 100644 index 00000000..f07a2bf2 Binary files /dev/null and b/docs/_static/images/ghdl/PoC_all.png differ diff --git a/docs/_static/images/ghdl/arith_prng_tb.posh.png b/docs/_static/images/ghdl/arith_prng_tb.posh.png new file mode 100644 index 00000000..f35103ee Binary files /dev/null and b/docs/_static/images/ghdl/arith_prng_tb.posh.png differ diff --git a/docs/_static/images/gtkwave/arith_prng_tb.png b/docs/_static/images/gtkwave/arith_prng_tb.png new file mode 100644 index 00000000..413780fe Binary files /dev/null and b/docs/_static/images/gtkwave/arith_prng_tb.png differ diff --git a/docs/_static/images/sync_strobe.png b/docs/_static/images/sync_strobe.png new file mode 100644 index 00000000..76548819 Binary files /dev/null and b/docs/_static/images/sync_strobe.png differ diff --git a/docs/_static/images/sync_strobe.svg b/docs/_static/images/sync_strobe.svg new file mode 100644 index 00000000..7d24595b --- /dev/null +++ b/docs/_static/images/sync_strobe.svg @@ -0,0 +1,288 @@ + + Created by CircuitLab https://www.circuitlab.com/ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + D0 + + + + + + + + + + + + + D0_meta + + + + + + + + + + + + + D1_sync + + + + + + + + AND1 + + + + + + + NOT1 + + + + + + + + + + Input + + + 2-FF Synchronizer (sync_Bits) + + + + + + + + + + + + + D2 + + + + + + + + XOR1 + + + + + + Rising Edge Detection + + + + + + + + XOR2 + + + + + + + + + + + + + T1 + + + + Clock1 + + + + + Busy + + + + + + + + AND2 + + + + + + + + NOT2 + + + + + + + + + + + Blocking + + + Signal Transformation + + + + + + + + Signal Reconstruction + + + + + Output + + + + Clock2 + + + + + + + + + + + + + + D0_meta + + + + + + + + + + + + + D1_sync + + + + + + + + 2-FF Synchronizer (sync_Bits) + + + + + + + + XOR3 + + + + + + + + + + + + + + + + Changed_Clk1 + + + + Changed_Clk2 + + + + + Required Hardware: + 6x D-FF + 1x T-FF (D-FF + XOR) + 2x AND + 2x XOR + 2x NOT + + + PoC.misc.sync.Strobe + + + + + + + + + + + + + + + + + + + + + diff --git a/docs/_static/images/xst/arith_prng.posh.png b/docs/_static/images/xst/arith_prng.posh.png new file mode 100644 index 00000000..f6318dff Binary files /dev/null and b/docs/_static/images/xst/arith_prng.posh.png differ diff --git a/docs/_static/logos/GitHub-Mark-32px.png b/docs/_static/logos/GitHub-Mark-32px.png new file mode 100644 index 00000000..8b25551a Binary files /dev/null and b/docs/_static/logos/GitHub-Mark-32px.png differ diff --git a/docs/_static/logos/tu-dresden-resized.jpg b/docs/_static/logos/tu-dresden-resized.jpg new file mode 100644 index 00000000..edd5eab0 Binary files /dev/null and b/docs/_static/logos/tu-dresden-resized.jpg differ diff --git a/docs/_static/logos/tu-dresden.jpg b/docs/_static/logos/tu-dresden.jpg new file mode 100644 index 00000000..02cae909 Binary files /dev/null and b/docs/_static/logos/tu-dresden.jpg differ diff --git a/docs/_templates/.gitempty b/docs/_templates/.gitempty new file mode 100644 index 00000000..e69de29b diff --git a/docs/_themes/.gitempty b/docs/_themes/.gitempty new file mode 100644 index 00000000..e69de29b diff --git a/docs/_themes/sphinx_rtd_theme b/docs/_themes/sphinx_rtd_theme new file mode 160000 index 00000000..eeff5645 --- /dev/null +++ b/docs/_themes/sphinx_rtd_theme @@ -0,0 +1 @@ +Subproject commit eeff5645dc4eeb7a5c4910d39c17131961045dce diff --git a/docs/conf.py b/docs/conf.py new file mode 100644 index 00000000..fdbd4b99 --- /dev/null +++ b/docs/conf.py @@ -0,0 +1,316 @@ +#!/usr/bin/env python3 +# -*- coding: utf-8 -*- +# +# The PoC-Library documentation build configuration file, created by +# sphinx-quickstart on Fri May 6 11:28:20 2016. +# +# This file is execfile()d with the current directory set to its +# containing dir. +# +# Note that not all possible configuration values are present in this +# autogenerated file. +# +# All configuration values have a default; values that are commented out +# serve to show the default. + +import sys +import os + +# If extensions (or modules to document with autodoc) are in another directory, +# add these directories to sys.path here. If the directory is relative to the +# documentation root, use os.path.abspath to make it absolute, like shown here. +sys.path.insert(0, os.path.abspath('.')) + +# -- General configuration ------------------------------------------------ + +# If your documentation needs a minimal Sphinx version, state it here. +#needs_sphinx = '1.0' + +# Add any Sphinx extension module names here, as strings. They can be +# extensions coming with Sphinx (named 'sphinx.ext.*') or your custom +# ones. +extensions = [ + 'sphinx.ext.autodoc', + 'sphinx.ext.intersphinx', + 'sphinx.ext.todo', + 'sphinx.ext.coverage', + 'sphinx.ext.mathjax', + 'sphinx.ext.ifconfig', + 'sphinx.ext.viewcode', + # 'sphinx.ext.githubpages', + 'poc' +] + +if (not (tags.has('PoCExternal') or tags.has('PoCInternal'))): + tags.add('PoCExternal') + + +# Add any paths that contain templates here, relative to this directory. +templates_path = ['_templates', '_themes'] + +# The suffix(es) of source filenames. +# You can specify multiple suffix as a list of string: +# source_suffix = ['.rst', '.md'] +source_suffix = '.rst' + +# The encoding of source files. +#source_encoding = 'utf-8-sig' + +# The master toctree document. +master_doc = 'index' + +# General information about the project. +project = 'The PoC-Library' +copyright = '2007-2016 Technische Universitaet Dresden - Germany, Chair for VLSI-Design, Diagnostics and Architecture' +author = 'Patrick Lehmann, Thomas B. Preusser, Martin Zabel' + +# The version info for the project you're documenting, acts as replacement for +# |version| and |release|, also used in various other places throughout the +# built documents. +# +# The short X.Y version. +version = '1.0' +# The full version, including alpha/beta/rc tags. +release = '1.0.0' + +# The language for content autogenerated by Sphinx. Refer to documentation +# for a list of supported languages. +# +# This is also used if you do content translation via gettext catalogs. +# Usually you set "language" from the command line for these cases. +language = None + +# There are two options for replacing |today|: either, you set today to some +# non-false value, then it is used: +#today = '' +# Else, today_fmt is used as the format for a strftime call. +#today_fmt = '%d.%m.%Y' + +# List of patterns, relative to source directory, that match files and +# directories to ignore when looking for source files. +# This patterns also effect to html_static_path and html_extra_path +exclude_patterns = [] + +# The reST default role (used for this markup: `text`) to use for all +# documents. +#default_role = None + +# If true, '()' will be appended to :func: etc. cross-reference text. +#add_function_parentheses = True + +# If true, the current module name will be prepended to all description +# unit titles (such as .. function::). +#add_module_names = True + +# If true, sectionauthor and moduleauthor directives will be shown in the +# output. They are ignored by default. +#show_authors = False + +# The name of the Pygments (syntax highlighting) style to use. +pygments_style = 'sphinx' + +# A list of ignored prefixes for module index sorting. +#modindex_common_prefix = [] + +# If true, keep warnings as "system message" paragraphs in the built documents. +#keep_warnings = False + +# If true, `todo` and `todoList` produce output, else they produce nothing. +todo_include_todos = True +todo_link_only = True + +# reST settings + +rst_prolog = """\ +.. |br| raw:: html + +
+ +""" + +# -- Options for HTML output ---------------------------------------------- + +# The theme to use for HTML and HTML Help pages. See the documentation for +# a list of builtin themes. +# html_theme = 'alabaster' +html_theme = "sphinx_rtd_theme" + +# Theme options are theme-specific and customize the look and feel of a theme +# further. For a list of options available for each theme, see the +# documentation. +#html_theme_options = {} + +# Add any paths that contain custom themes here, relative to this directory. +#html_theme_path = [] +html_theme_path = ["_themes", ] + +# The name for this set of Sphinx documents. +# " v documentation" by default. +#html_title = 'The PoC-Library v1.0.0' + +# A shorter title for the navigation bar. Default is the same as html_title. +#html_short_title = None + +# The name of an image file (relative to this directory) to place at the top +# of the sidebar. +#html_logo = None + +# The name of an image file (relative to this directory) to use as a favicon of +# the docs. This file should be a Windows icon file (.ico) being 16x16 or 32x32 +# pixels large. +#html_favicon = None + +# Add any paths that contain custom static files (such as style sheets) here, +# relative to this directory. They are copied after the builtin static files, +# so a file named "default.css" will overwrite the builtin "default.css". +html_static_path = ['_static'] + +# Add any extra paths that contain custom files (such as robots.txt or +# .htaccess) here, relative to this directory. These files are copied +# directly to the root of the documentation. +#html_extra_path = [] + +# If not None, a 'Last updated on:' timestamp is inserted at every page +# bottom, using the given strftime format. +# The empty string is equivalent to '%b %d, %Y'. +html_last_updated_fmt = "%b %d, %Y" + +# If true, SmartyPants will be used to convert quotes and dashes to +# typographically correct entities. +#html_use_smartypants = True + +# Custom sidebar templates, maps document names to template names. +#html_sidebars = {} + +# Additional templates that should be rendered to pages, maps page names to +# template names. +#html_additional_pages = {} + +# If false, no module index is generated. +#html_domain_indices = True + +# If false, no index is generated. +#html_use_index = True + +# If true, the index is split into individual pages for each letter. +#html_split_index = False + +# If true, links to the reST sources are added to the pages. +#html_show_sourcelink = True + +# If true, "Created using Sphinx" is shown in the HTML footer. Default is True. +#html_show_sphinx = True + +# If true, "(C) Copyright ..." is shown in the HTML footer. Default is True. +#html_show_copyright = True + +# If true, an OpenSearch description file will be output, and all pages will +# contain a tag referring to it. The value of this option must be the +# base URL from which the finished HTML is served. +#html_use_opensearch = '' + +# This is the file name suffix for HTML files (e.g. ".xhtml"). +#html_file_suffix = None + +# Language to be used for generating the HTML full-text search index. +# Sphinx supports the following languages: +# 'da', 'de', 'en', 'es', 'fi', 'fr', 'h', 'it', 'ja' +# 'nl', 'no', 'pt', 'ro', 'r', 'sv', 'tr', 'zh' +#html_search_language = 'en' + +# A dictionary with options for the search language support, empty by default. +# 'ja' uses this config value. +# 'zh' user can custom change `jieba` dictionary path. +#html_search_options = {'type': 'default'} + +# The name of a javascript file (relative to the configuration directory) that +# implements a search results scorer. If empty, the default will be used. +#html_search_scorer = 'scorer.js' + +# Output file base name for HTML help builder. +htmlhelp_basename = 'ThePoC-Librarydoc' + +# -- Options for LaTeX output --------------------------------------------- + +latex_elements = { +# The paper size ('letterpaper' or 'a4paper'). + 'papersize': 'a4paper', + +# The font size ('10pt', '11pt' or '12pt'). +#'pointsize': '10pt', + +# Additional stuff for the LaTeX preamble. +#'preamble': '', + +# Latex figure (float) alignment +#'figure_align': 'htbp', +} + +# Grouping the document tree into LaTeX files. List of tuples +# (source start file, target name, title, +# author, documentclass [howto, manual, or own class]). +latex_documents = [ + (master_doc, 'ThePoC-Library.tex', 'The PoC-Library Documentation', + 'Patrick Lehmann, Thomas B. Preusser, Martin Zabel', 'manual'), +] + +# The name of an image file (relative to this directory) to place at the top of +# the title page. +#latex_logo = None + +# For "manual" documents, if this is true, then toplevel headings are parts, +# not chapters. +#latex_use_parts = False + +# If true, show page references after internal links. +#latex_show_pagerefs = False + +# If true, show URL addresses after external links. +#latex_show_urls = False + +# Documents to append as an appendix to all manuals. +#latex_appendices = [] + +# If false, no module index is generated. +#latex_domain_indices = True + + +# -- Options for manual page output --------------------------------------- + +# One entry per manual page. List of tuples +# (source start file, name, description, authors, manual section). +man_pages = [ + (master_doc, 'thepoc-library', 'The PoC-Library Documentation', + [author], 1) +] + +# If true, show URL addresses after external links. +#man_show_urls = False + + +# -- Options for Texinfo output ------------------------------------------- + +# Grouping the document tree into Texinfo files. List of tuples +# (source start file, target name, title, author, +# dir menu entry, description, category) +texinfo_documents = [ + (master_doc, 'ThePoC-Library', 'The PoC-Library Documentation', + author, 'ThePoC-Library', 'One line description of project.', + 'Miscellaneous'), +] + +# Documents to append as an appendix to all manuals. +#texinfo_appendices = [] + +# If false, no module index is generated. +#texinfo_domain_indices = True + +# How to display URL addresses: 'footnote', 'no', or 'inline'. +#texinfo_show_urls = 'footnote' + +# If true, do not generate a @detailmenu in the "Top" node's menu. +#texinfo_no_detailmenu = False + + +# Example configuration for intersphinx: refer to the Python standard library. +intersphinx_mapping = {'https://docs.python.org/': None} diff --git a/docs/index.rst b/docs/index.rst new file mode 100644 index 00000000..c4978f7c --- /dev/null +++ b/docs/index.rst @@ -0,0 +1,97 @@ +This library is published and maintained by **Chair for VLSI Design, Diagnostics +and Architecture** - Faculty of Computer Science, Technische Universität Dresden, +Germany |br| +`https://tu-dresden.de/ing/informatik/ti/vlsi `_ + +.. image:: _static/logos/tu-dresden.jpg + :scale: 10 + :alt: Technische Universität Dresden + +-------------------------------------------------------------------------------- + +.. image:: _static/logos/GitHub-Mark-32px.png + :scale: 60 + :target: https://www.github.com/VLSI-EDA/PoC + :alt: Source Code on GitHub +.. image:: https://landscape.io/github/VLSI-EDA/PoC/release/landscape.svg?style=flat + :target: https://landscape.io/github/VLSI-EDA/PoC/release + :alt: Code Health +.. image:: https://travis-ci.org/VLSI-EDA/PoC.svg?branch=release + :target: https://travis-ci.org/VLSI-EDA/PoC + :alt: Build Results +.. image:: https://badges.gitter.im/VLSI-EDA/PoC.svg + :target: https://gitter.im/VLSI-EDA/PoC + :alt: Join +.. image:: https://img.shields.io/github/tag/VLSI-EDA/PoC.svg?style=flat + :alt: Latest tag +.. image:: https://img.shields.io/github/release/VLSI-EDA/PoC.svg?style=flat + :target: https://github.com/VLSI-EDA/PoC/releases + :alt: Latest release +.. image:: https://img.shields.io/github/license/VLSI-EDA/PoC.svg?style=flat + :target: References/Licenses/License.html + :alt: Apache License 2.0 + +-------------------------------------------------------------------------------- + +The PoC-Library Documentation +############################# + +PoC - "Pile of Cores" provides implementations for often required hardware +functions such as Arithmetic Units, Caches, Clock-Domain-Crossing Circuits, +FIFOs, RAM wrappers, and I/O Controllers. The hardware modules are typically +provided as VHDL or Verilog source code, so it can be easily re-used in a +variety of hardware designs. + +All hardware modules use a common set of VHDL packages to share new VHDL types, +sub-programs and constants. Additionally, a set of simulation helper packages +eases the writing of testbenches. Because PoC hosts a huge amount of IP cores, +all cores are grouped into sub-namespaces to build a better hierachy. + +Various simulation and synthesis tool chains are supported to interoperate with +PoC. To generalize all supported free and commercial vendor tool chains, PoC is +shipped with a Python based infrastructure to offer a command line based frontend. + + +News +**** + +13.05.2016 - PoC 1.0.0 was released. +==================================== + +Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. +At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor +sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et +accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet + +Cite the PoC-Library +******************** + +The PoC-Library hosted at `GitHub.com `_. Please use the +following `biblatex `_ entry to cite us: + +.. code-block:: tex + + # BibLaTex example entry + @online{poc, + title={{PoC - Pile of Cores}}, + author={{Chair of VLSI Design, Diagnostics and Architecture}}, + organization={{Technische Universität Dresden}}, + year={2016}, + url={https://github.com/VLSI-EDA/PoC}, + urldate={2016-10-28}, + } + + +.. toctree:: + :hidden: + + WhatIsPoC/index + QuickStart + UsingPoC/index + PoC/index + Miscelaneous/ThirdParty + ConstraintFiles/index + References/index + GetInvolved/index + Miscelaneous/ChangeLog + References/Licenses/License diff --git a/docs/poc.py b/docs/poc.py new file mode 100644 index 00000000..47e9112e --- /dev/null +++ b/docs/poc.py @@ -0,0 +1,237 @@ +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# +# ============================================================================== +# Authors: Patrick Lehmann +# Thomas B. Preußer +# +# Python Script: Extract embedded ReST documentation from VHDL primary units +# +# Description: +# ------------------------------------ +# undocumented +# +# License: +# ============================================================================== +# Copyright 2007-2016 Technische Universitaet Dresden - Germany +# Chair for VLSI-Design, Diagnostics and Architecture +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================== +from enum import Enum +from pathlib import Path +from re import compile as re_compile +from textwrap import dedent + +def setup(app): + pass + +class SourceCodeRange: + def __init__(self, file, startRow, endRow): + self.SourceFile = file + self.StartRow = startRow + self.EndRow = endRow + +class SourceFile: + def __init__(self, entitySourceCodeRange): #, entityName, entitySourceCodeRange, summary, description, seeAlso): + self.File = entitySourceCodeRange.SourceFile + self.EntityName = "" # entityName + self.EntitySourceCodeRange = entitySourceCodeRange + self.Authors = [] + self.Summary = "" # summary + self.Description = "" # description + self.SeeAlso = "" # seeAlso + + +class Extract: + def __init__(self): + self.sourceDirectory = Path("../src") + self.outputDirectory = Path("PoC") + self.relSourceDirectory = Path("../../src") + + self.templateFile = Path("Entity.template") + self.templateContent = "" + + def Run(self): + result = self.recursion(self.sourceDirectory) + + print("Reading template file...") + with self.templateFile.open('r') as templateFileHandle: + self.templateContent = templateFileHandle.read() + + print("Writing reStructuredText files...") + self.recursion2(result) + + def recursion(self, sourceDirectory): + result = {} + + for item in sourceDirectory.iterdir(): + if item.is_dir(): + stem = item.stem + if ((stem not in ["Altera", "altera", "Lattice", "lattice", "Xilinx", "xilinx"]) and not stem.startswith(("cvs_", "old_"))): + print("cd {0}".format(stem)) + result[stem] = self.recursion(item) + elif item.is_file(): + if (item.suffix == ".vhdl"): + if (not item.stem.endswith(("Altera", "altera", "Lattice", "lattice", "Xilinx", "xilinx")) and not item.stem.startswith(("cvs_", "old_"))): + try: + result[item.stem] = self.ExtractComments(item) + except Exception as ex: + print(" " + str(ex)) + + return result + + def recursion2(self, result): + for item in result.values(): + if isinstance(item, dict): + self.recursion2(item) + elif isinstance(item, SourceFile): + self.writeReST(item) + + def writeReST(self, sourceFile): + relPath = sourceFile.File.relative_to(self.sourceDirectory) + outputFile = self.outputDirectory / relPath.with_suffix(".rst") + relSourceFile = ("../" * (len(relPath.parents) - 1)) / self.relSourceDirectory / relPath + + print("Writing reST file '{0!s}'.".format(outputFile)) + + # print(" Authors: {0}".format(", ".join(sourceFile.Authors))) + # print(" Summary: {0}".format(sourceFile.Summary)) + # print(" Entity '{0}' at {1}..{2}.".format(sourceFile.EntityName, sourceFile.EntitySourceCodeRange.StartRow, sourceFile.EntitySourceCodeRange.EndRow)) + + if (sourceFile.SeeAlso != ""): + seeAlsoBox = ".. seealso::\n \n" + for line in sourceFile.SeeAlso.splitlines(): + seeAlsoBox += " {line}\n".format(line=line) + else: + seeAlsoBox = "" + + outputContent = self.templateContent.format( + EntityName=sourceFile.EntityName, + EntityNameUnderline="#" * len(sourceFile.EntityName), + EntityDescription=sourceFile.Description, + EntityFilePath=relSourceFile.as_posix(), + EntityDeclarationFromTo="{0}-{1}".format(sourceFile.EntitySourceCodeRange.StartRow, sourceFile.EntitySourceCodeRange.EndRow), + GitHubSourceFile="`{relPath} `_".format(relPath=relPath.as_posix()), + SeeAlsoBox=seeAlsoBox + ) + + with outputFile.open('w') as restructuredTextHandle: + restructuredTextHandle.write(outputContent) + + def ExtractComments(self, sourceFile): + """ + Extracts the documentation from the header of a PoC VHDL source. + - The documentation header starts with a separator line matching /^--\s*={16,}$/. + - The documentation header continues through all immediately following comment lines. + - The contained information is added to the currently active section. + - A specific section is opened by a line matching /^--\s*(?P
\w+):/ with +
as one of Authors|Entity|Description|SeeAlso|License. + - An underline /^-- -+$/ immediately following a section opening is ignored. + - After the documentation header, the entity name is extracted from the entity declaration. + """ + class State(Enum): + BeforeDocHeader = 0 + InDocHeader = 1 + BeforeEntityDecl = 2 + InEntityDecl = 3 + Done = 4 + + sectionStrip = { + 'Authors': True, + 'Entity': True, + 'Description': False, + 'SeeAlso': False, + 'License': False + } + sections = { + 'Authors': '', + 'Entity': '', + 'Description': '', + 'SeeAlso': '', + 'License': '' + } + + headerStartRE = re_compile(r'^--\s*={16,}$') + sectionStartRE = re_compile(r'^--\s*(?P
'+('|'.join(sections.keys()))+r'):\s*(?P.*)$') + underlineRE = re_compile(r'^-- -+$') + commentStripRE = re_compile(r'^-- ?') + + entityStartRE = re_compile(r"(?i)entity\s+(?P\w+)\s+is") + entityEndRE = re_compile(r"(?i)end\s+(?P\w+)(\s+\w+)?\s*;") + + entityName = "" + entityStartLine = 0 + entityEndLine = 0 + + # Parse the Source File + print(" Reading '{0!s}'...".format(sourceFile)) + state = State.BeforeDocHeader + with sourceFile.open('r') as vhdlFileHandle: + lineNumber = 0 + for line in vhdlFileHandle: + lineNumber += 1 + + # Parse Documentation Header into Sections + if state is State.BeforeDocHeader: + if headerStartRE.match(line): + section = None + state = State.InDocHeader + + elif state is State.InDocHeader: + if not line.startswith('--'): + state = State.BeforeEntityDecl + else: + m = sectionStartRE.match(line) + if m: + section = m.group('Section') + sections[section] += m.group('Content') + elif sections[section] != '' or not underlineRE.match(line): + line = commentStripRE.sub('', line) + sections[section] += line.lstrip() if sectionStrip[section] else line + + # Parse Entity Declaration + if state is State.BeforeDocHeader or state is State.BeforeEntityDecl: + m = entityStartRE.match(line) + if m: + entityName = m.group("EntityName") + entityStartLine = lineNumber + state = State.InEntityDecl + + elif state is State.InEntityDecl: + m = entityEndRE.match(line) + if m: + name = m.group('EntityName') + if name == 'entity' or name == entityName: + entityEndLine = lineNumber + state = State.Done + break + + if state is not State.Done: + raise Exception("No entity found. LastState = {0}".format(state.name)) + + # Construct Result Object + result = SourceFile(SourceCodeRange(sourceFile, 0, 0)) + result.Authors = [author for author in sections['Authors'].splitlines()] + result.Summary = sections['Entity'] + result.Description = sections['Description'] + result.SeeAlso = sections['SeeAlso'] + result.EntityName = entityName + result.EntitySourceCodeRange.StartRow = entityStartLine + result.EntitySourceCodeRange.EndRow = entityEndLine + return result + +if (__name__ == "__main__"): + e = Extract() + e.Run() diff --git a/lib/Altera.files b/lib/Altera.files index 80ce62eb..b143cd9b 100644 --- a/lib/Altera.files +++ b/lib/Altera.files @@ -4,18 +4,72 @@ # ============================================================================== # Note: all files are relative to PoC root directory # -if (VHDL >= 2002) then - report "Altera primitives don't support VHDL-200x." -else - if ((Tool = "GHDL") and ?("temp/precompiled/ghdl/altera")) then - library altera_mf "temp/precompiled/ghdl/altera" - elseif ((Tool in ["Mentor_vSim", "Cocotb_QuestaSim"]) and ?("temp/precompiled/vsim/altera")) then - library altera_mf "temp/precompiled/vsim/altera" - elseif (ToolChain = "Altera_Quartus") then - # implicitly referenced; nothing to reference - elseif (Tool = "Aldec_aSim") then - # Active-HDL is shipped with Xilinx libraries. +path PreCompiled = ${CONFIG.DirectoryNames:PrecompiledFiles} + +if (Tool = "GHDL") then + path GHDL_Directory = (PreCompiled / ${CONFIG.DirectoryNames:GHDLFiles}) + path Altera_Directory = (GHDL_Directory / ${CONFIG.DirectoryNames:AlteraSpecificFiles}) + if (VHDLVersion < 2002) then + if ?{Altera_Directory} then + if ?{(Altera_Directory / "lpm/v93/lpm-obj93.cf")} then + library lpm Altera_Directory + end if + if ?{(Altera_Directory / "sgate/v93/sgate-obj93.cf")} then + library sgate Altera_Directory + end if + if ?{(Altera_Directory / "altera/v93/altera-obj93.cf")} then + library altera Altera_Directory + end if + if ?{(Altera_Directory / "altera_mf/v93/altera_mf-obj93.cf")} then + library altera_mf Altera_Directory + end if + if ?{(Altera_Directory / "altera_lnsim/v93/altera_lnsim-obj93.cf")} then + library altera_lnsim Altera_Directory + end if + # TODO: add device libraries if needed + else + report "No precompiled Altera primitives for GHDL and VHDL-93 found." + end if + elseif (VHDLVersion <= 2008) then + if ?{Altera_Directory} then + if ?{(Altera_Directory / "lpm/v08/lpm-obj08.cf")} then + library lpm Altera_Directory + end if + if ?{(Altera_Directory / "sgate/v08/sgate-obj08.cf")} then + library sgate Altera_Directory + end if + if ?{(Altera_Directory / "altera/v08/altera-obj08.cf")} then + library altera Altera_Directory + end if + if ?{(Altera_Directory / "altera_mf/v08/altera_mf-obj08.cf")} then + library altera_mf Altera_Directory + end if + if ?{(Altera_Directory / "altera_lnsim/v08/altera_lnsim-obj08.cf")} then + library altera_lnsim Altera_Directory + end if + # TODO: add device libraries if needed + else + report "No precompiled Altera primitives for GHDL and VHDL-2008 found." + end if + else + report "No precompiled Altera primitives for GHDL found." + end if +elseif (Tool in ["Mentor_vSim", "Cocotb_QuestaSim"]) then + path Altera_Directory = (PreCompiled / (${CONFIG.DirectoryNames:ModelSimFiles} / ${CONFIG.DirectoryNames:AlteraSpecificFiles})) + if ?{Altera_Directory} then + library lpm Altera_Directory + library sgate Altera_Directory + library altera Altera_Directory + library altera_mf Altera_Directory + library altera_lnsim Altera_Directory + # TODO: add device libraries if needed else - report "No precompiled Altera primitives found." + report "No precompiled Altera primitives for QuestaSim/ModelSim found." end if +elseif (ToolChain = "Altera_Quartus") then + # implicitly referenced; nothing to reference +elseif (Tool = "Aldec_aSim") then + # Active-HDL is shipped with Altera libraries. +else + report "No precompiled Altera primitives found." end if diff --git a/lib/OSVVM.files b/lib/OSVVM.files index a976e3e0..358a4529 100644 --- a/lib/OSVVM.files +++ b/lib/OSVVM.files @@ -4,12 +4,28 @@ # ============================================================================== # Note: all files are relative to PoC root directory # -if (VHDL = 2008) then - if ((Tool = "GHDL") and ?("temp/precompiled/ghdl/osvvm")) then - library osvvm "temp/precompiled/ghdl/osvvm" - elseif ((Tool = "Mentor_vSim") and ?("temp/precompiled/vsim/osvvm")) then - library osvvm "temp/precompiled/vsim/osvvm" +path PreCompiled = ${CONFIG.DirectoryNames:PrecompiledFiles} +path OSVVM_Directory = "osvvm" + +if (VHDLVersion < 2008) then + report "OSVVM requires VHDL-2008; See OSVVM documentation for VHDL-2002 support." +elseif (VHDLVersion = 2008) then + if (Tool = "GHDL") then + path GHDLPath = (PreCompiled / ${CONFIG.DirectoryNames:GHDLFiles}) + if ?{((GHDLPath / OSVVM_Directory) / "v08/osvvm-obj08.cf")} then + library osvvm GHDLPath + else + report "No precompiled OSVVM library for GHDL found." + end if + elseif (Tool = "Mentor_vSim") then + path OSVVM_LibraryPath = (PreCompiled / (${CONFIG.DirectoryNames:ModelSimFiles} / OSVVM_Directory)) + if ?{OSVVM_LibraryPath} then + library osvvm OSVVM_LibraryPath + else + report "No precompiled QuestaSim/ModelSim library for GHDL found." + end if else + # TODO self-compile section? vhdl osvvm "lib/osvvm/NamePkg.vhd" # OSVVM vhdl osvvm "lib/osvvm/OsvvmGlobalPkg.vhd" # OSVVM vhdl osvvm "lib/osvvm/TextUtilPkg.vhd" # OSVVM @@ -24,5 +40,5 @@ if (VHDL = 2008) then vhdl osvvm "lib/osvvm/OsvvmContext.vhd" # OSVVM end if else - report "OSVVM requires VHDL-2008" + report "VHDL version not supported by OSVVM." end if diff --git a/lib/README.md b/lib/README.md index aa79a8fb..844ff8b2 100644 --- a/lib/README.md +++ b/lib/README.md @@ -21,6 +21,20 @@ foreach($dir in (dir -Directory)) { } ``` +## Cocotb + +**Folder:** `\lib\cocotb\` +**Copyright:** Copyright © 2013, [Potential Ventures Ltd.](http://potential.ventures/), SolarFlare Communications Inc. +**License:** Revised BSD License, see [local copy](Cocotb BSD License.md) + +[Cocotb][10] is a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python. + +Documentation: [http://cocotb.readthedocs.org/en/latest/index.html][10] +Source: [https://github.com/potentialventures/cocotb][11] + + [10]: http://cocotb.readthedocs.org/en/latest/index.html + [11]: https://github.com/potentialventures/cocotb + ## Open Source VHDL Verification Methodology (OS-VVM) @@ -28,7 +42,7 @@ foreach($dir in (dir -Directory)) { **Copyright:** Copyright © 2012-2016 by [SynthWorks Design Inc.](http://www.synthworks.com/) **License:** [Artistic License 2.0][PAL2.0] -[**Open Source VHDL Verification Methodology (OS-VVM)**][10] is an intelligent +[**Open Source VHDL Verification Methodology (OS-VVM)**][20] is an intelligent testbench methodology that allows mixing of “Intelligent Coverage” (coverage driven randomization) with directed, algorithmic, file based, and constrained random test approaches. The methodology can be adopted in part or in whole as @@ -36,11 +50,11 @@ needed. With OSVVM you can add advanced verification methodologies to your current testbench without having to learn a new language or throw out your existing testbench or testbench models. -Website: [http://osvvm.org/][10] -Source: [https://github.com/JimLewis/OSVVM][11] +Website: [http://osvvm.org/][20] +Source: [https://github.com/JimLewis/OSVVM][21] - [10]: http://osvvm.org/ - [11]: https://github.com/JimLewis/OSVVM + [20]: http://osvvm.org/ + [21]: https://github.com/JimLewis/OSVVM ## VUnit @@ -61,19 +75,20 @@ Source: [https://github.com/VUnit/vunit][31] [30]: https://vunit.github.io/ [31]: https://github.com/VUnit/vunit -## Cocotb + +## Xillybus -**Folder:** `\lib\cocotb\` -**Copyright:** Copyright © 2013, [Potential Ventures Ltd.](http://potential.ventures/), SolarFlare Communications Inc. -**License:** Revised BSD License, see [local copy](Cocotb BSD License.md) +**Folder:** `\lib\xillybus\` +**Copyright:** TODO +**License:** TODO, see [local copy](Xillybus License.md) -[Cocotb][40] is a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python. +[xillybus][40] TODO -Documentation: [http://cocotb.readthedocs.org/en/latest/index.html][40] -Source: [https://github.com/potentialventures/cocotb][41] +Documentation: [http://xillybus.com][40] +Source: [http://xillybus.com][41] - [40]: http://cocotb.readthedocs.org/en/latest/index.html - [41]: https://github.com/potentialventures/cocotb + [40]: http://xillybus.com + [41]: http://xillybus.com [PAL2.0]: http://www.perlfoundation.org/artistic_license_2_0 diff --git a/lib/Xilinx.files b/lib/Xilinx.files index 74a87084..a5e0008c 100644 --- a/lib/Xilinx.files +++ b/lib/Xilinx.files @@ -4,10 +4,58 @@ # ============================================================================== # Note: all files are relative to PoC root directory # -if ((Tool = "GHDL") and ?("temp/precompiled/ghdl/xilinx")) then - library unisim "temp/precompiled/ghdl/xilinx" -elseif ((Tool in ["Mentor_vSim", "Cocotb_QuestaSim"]) and ?("temp/precompiled/vsim/xilinx")) then - library unisim "temp/precompiled/vsim/xilinx" +path PreCompiled = ${CONFIG.DirectoryNames:PrecompiledFiles} + +if (Tool = "GHDL") then + path GHDL_Directory = (PreCompiled / ${CONFIG.DirectoryNames:GHDLFiles}) + path Xilinx_Directory = (GHDL_Directory / ${CONFIG.DirectoryNames:XilinxSpecificFiles}) + if (VHDLVersion < 2002) then + if ?{Xilinx_Directory} then + if ?{(Xilinx_Directory / "unisim/v93/unisim-obj93.cf")} then + library unisim Xilinx_Directory + end if + if ?{(Xilinx_Directory / "unimacro/v93/unimacro-obj93.cf")} then + library unimacro Xilinx_Directory + end if + if ?{(Xilinx_Directory / "secureip/v93/secureip-obj93.cf")} then + library secureip Xilinx_Directory + end if + if ?{(Xilinx_Directory / "simprim/v93/simprim-obj93.cf")} then + library simprim Xilinx_Directory + end if + else + report "No precompiled Xilinx primitives for GHDL and VHDL-93 found." + end if + elseif (VHDLVersion <= 2008) then + if ?{Xilinx_Directory} then + if ?{(Xilinx_Directory / "unisim/v08/unisim-obj08.cf")} then + library unisim Xilinx_Directory + end if + if ?{(Xilinx_Directory / "unimacro/v08/unimacro-obj08.cf")} then + library unimacro Xilinx_Directory + end if + if ?{(Xilinx_Directory / "secureip/v08/secureip-obj08.cf")} then + library secureip Xilinx_Directory + end if + if ?{(Xilinx_Directory / "simprim/v08/simprim-obj08.cf")} then + library simprim Xilinx_Directory + end if + else + report "No precompiled Xilinx primitives for GHDL and VHDL-2008 found." + end if + else + report "No precompiled Xilinx primitives for GHDL found." + end if +elseif (Tool in ["Mentor_vSim", "Cocotb_QuestaSim"]) then + path Xilinx_Directory = (PreCompiled / (${CONFIG.DirectoryNames:ModelSimFiles} / ${CONFIG.DirectoryNames:XilinxSpecificFiles})) + if ?{Xilinx_Directory} then + library unisim Xilinx_Directory + library unimacro Xilinx_Directory + library secureip Xilinx_Directory + library simprim Xilinx_Directory + else + report "No precompiled Xilinx primitives for vSim found." + end if elseif (ToolChain in ["Xilinx_ISE", "Xilinx_Vivado"]) then # implicitly referenced; nothing to reference elseif (Tool = "Aldec_aSim") then diff --git a/lib/cocotb b/lib/cocotb index 02d2a30f..4391cdfe 160000 --- a/lib/cocotb +++ b/lib/cocotb @@ -1 +1 @@ -Subproject commit 02d2a30f967496f792abaa5bff350aa4b7328ad1 +Subproject commit 4391cdfe3b15e25c4b26c1ffa6b5837d13718ca6 diff --git a/lib/osvvm b/lib/osvvm index 2424c9cd..c3f8221b 160000 --- a/lib/osvvm +++ b/lib/osvvm @@ -1 +1 @@ -Subproject commit 2424c9cdc6fb63e6dc337cd9218d17178007f434 +Subproject commit c3f8221b891f0d03d7cf3477a0dc41c2e3b068b5 diff --git a/lib/vunit b/lib/vunit index 1e134142..48c9aaec 160000 --- a/lib/vunit +++ b/lib/vunit @@ -1 +1 @@ -Subproject commit 1e1341425b1988bcc97606a88ae43becdabb4290 +Subproject commit 48c9aaecb5d786b1fee680bb064b75664627c975 diff --git a/poc.ps1 b/poc.ps1 index bbdca197..4228bfe7 100644 --- a/poc.ps1 +++ b/poc.ps1 @@ -1,12 +1,12 @@ # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2; replace-tabs off; indent-width 2; -# +# # ============================================================================== # Authors: Patrick Lehmann -# +# # PowerShell Script: Wrapper Script to execute /py/PoC.py -# +# # Description: # ------------------------------------ # This is a bash wrapper script (executable) which: @@ -17,38 +17,82 @@ # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany # Chair for VLSI-Design, Diagnostics and Architecture -# +# # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at -# +# # http://www.apache.org/licenses/LICENSE-2.0 -# +# # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # See the License for the specific language governing permissions and # limitations under the License. # ============================================================================== - -# configure wrapper here -$PyWrapper_PoShScriptDir = "py" -$PyWrapper_Script = "PoC.py" -$PyWrapper_MinVersion = "3.5.0" - -$PyWrapper_RelPath = "." -$PyWrapper_Solution = "" +# +# Change this, if PoC solutions and PoC projects are used +$PoC_RelPath = "." # relative path to PoC root directory +$PoC_Solution = "" # solution name # save parameters and current working directory -$PyWrapper_Parameters = $args $PyWrapper_WorkingDir = Get-Location -$PoC_RootDir_AbsPath = Convert-Path (Resolve-Path ($PSScriptRoot + "\" + $PyWrapper_RelPath)) -# invoke main wrapper -. ("$PoC_RootDir_AbsPath\$PyWrapper_PoShScriptDir\Wrapper.ps1") +# Configure PoC environment here +$PoC_PythonDir = "py" +$PoC_ScriptPy = "$PoC_PythonDir\PoC.py" +$PoC_WrapperDir = "py\Wrapper" +$PoC_Module = "PoC" +$PoC_Wrapper = "Wrapper.ps1" + +# load PoC module +$PoCRootDir = Convert-Path (Resolve-Path ($PSScriptRoot + "\" + $PoC_RelPath)) +Import-Module "$PoCRootDir\$PoC_WrapperDir\$PoC_Module.psm1" -ArgumentList @($PoCRootDir) + +# scan script parameters and mark environment to be loaded +$Debug, $PyWrapper_LoadEnv = Get-PoCEnvironmentArray $args +# execute vendor and tool pre-hook files if present +Invoke-OpenEnvironment $PyWrapper_LoadEnv | Out-Null + +# print debug messages +if ($Debug -eq $true ) { + Write-Host "This is the PoC-Library script wrapper operating in debug mode." -ForegroundColor Yellow + Write-Host "" + Write-Host "Directories:" -ForegroundColor Yellow + Write-Host " PoC Root $PoC_RootDir" -ForegroundColor Yellow + Write-Host " Working $PyWrapper_WorkingDir" -ForegroundColor Yellow + Write-Host "Script:" -ForegroundColor Yellow + Write-Host " Filename $PoC_ScriptPy" -ForegroundColor Yellow + Write-Host " Solution $PoC_Solution" -ForegroundColor Yellow + Write-Host " Parameters $args" -ForegroundColor Yellow + Write-Host "Load Environment:" -ForegroundColor Yellow + Write-Host " Lattice Diamond $($PyWrapper_LoadEnv['Lattice']['Tools']['Diamond']['Load'])" -ForegroundColor Yellow + Write-Host " Xilinx ISE $($PyWrapper_LoadEnv['Xilinx']['Tools']['ISE']['Load'])" -ForegroundColor Yellow + Write-Host " Xilinx Vivado $($PyWrapper_LoadEnv['Xilinx']['Tools']['Vivado']['Load'])" -ForegroundColor Yellow + Write-Host "" +} + +# execute script with appropriate Python interpreter and all given parameters +if ($PoC_Solution -eq "") +{ $Command = "$Python_Interpreter $Python_Parameters $PoC_RootDir\$PoC_ScriptPy $args" } +else +{ $Command = "$Python_Interpreter $Python_Parameters $PoC_RootDir\$PoC_ScriptPy --sln=$PoC_Solution $args" } + +# execute script with appropriate Python interpreter and all given parameters +if ($Debug -eq $true) { Write-Host "launching: '$Command'" -ForegroundColor Yellow } +Invoke-Expression $Command +$PyWrapper_ExitCode = $LastExitCode + + +Invoke-CloseEnvironment $PyWrapper_LoadEnv | Out-Null + +# unload PowerShell module +Remove-Module $PoC_Module +# clean up environment variables +$env:PoCRootDirectory = $null # restore working directory if changed Set-Location $PyWrapper_WorkingDir # return exit status -exit $PoC_ExitCode +exit $PyWrapper_ExitCode diff --git a/poc.sh b/poc.sh index 151b0a71..dd9a270a 100755 --- a/poc.sh +++ b/poc.sh @@ -1,13 +1,14 @@ -#! /bin/bash +#! /usr/bin/env bash # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2; replace-tabs off; indent-width 2; -# +# # ============================================================================== # Authors: Patrick Lehmann -# +# Martin Zabel +# # Bash Script: Wrapper Script to execute /py/PoC.py -# +# # Description: # ------------------------------------ # This is a bash wrapper script (executable) which: @@ -18,13 +19,13 @@ # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany # Chair for VLSI-Design, Diagnostics and Architecture -# +# # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at -# +# # http://www.apache.org/licenses/LICENSE-2.0 -# +# # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -33,19 +34,22 @@ # ============================================================================== # configure wrapper here -PyWrapper_BashScriptDir="py" +PyWrapper_BashScriptDir="py/Wrapper" PyWrapper_Script=PoC.py PyWrapper_MinVersion=3.5.0 PyWrapper_RelPath="." PyWrapper_Solution="" +# work around for Darwin (Mac OS) +READLINK=readlink; if [[ $(uname) == "Darwin" ]]; then READLINK=greadlink; fi + # resolve script directory -# solution is taken from http://stackoverflow.com/questions/59895/can-a-bash-script-tell-what-directory-its-stored-in +# solution is from http://stackoverflow.com/questions/59895/can-a-bash-script-tell-what-directory-its-stored-in SOURCE="${BASH_SOURCE[0]}" while [ -h "$SOURCE" ]; do # resolve $SOURCE until the file is no longer a symlink DIR="$( cd -P "$( dirname "$SOURCE" )" && pwd )" - SOURCE="$(readlink "$SOURCE")" + SOURCE="$($READLINK "$SOURCE")" [[ $SOURCE != /* ]] && SOURCE="$DIR/$SOURCE" # if $SOURCE was a relative symlink, we need to resolve it relative to the path where the symlink file was located done SCRIPT_DIR="$( cd -P "$( dirname "$SOURCE" )" && pwd )" @@ -54,10 +58,10 @@ SCRIPT_DIR="$( cd -P "$( dirname "$SOURCE" )" && pwd )" PyWrapper_Parameters=$@ PyWrapper_WorkingDir=$(pwd) PoC_RootDir_RelPath="$SCRIPT_DIR/." -PoC_RootDir_AbsPath=$(cd "$PoC_RootDir_RelPath/$PyWrapper_RelPath" && pwd) +PoC_RootDir=$(cd "$PoC_RootDir_RelPath/$PyWrapper_RelPath" && pwd) # invoke main wrapper -source "$PoC_RootDir_AbsPath/$PyWrapper_BashScriptDir/wrapper.sh" +source "$PoC_RootDir/$PyWrapper_BashScriptDir/wrapper.sh" # return exit status exit $PoC_ExitCode diff --git a/py/.idea/misc.xml b/py/.idea/misc.xml index 4d9ef769..58450a2b 100644 --- a/py/.idea/misc.xml +++ b/py/.idea/misc.xml @@ -10,5 +10,5 @@ - + \ No newline at end of file diff --git a/py/.idea/py.iml b/py/.idea/py.iml index ec26f275..eaaad0b1 100644 --- a/py/.idea/py.iml +++ b/py/.idea/py.iml @@ -6,7 +6,7 @@ - + diff --git a/py/.idea/workspace.xml b/py/.idea/workspace.xml index 5d6266b5..66b83662 100644 --- a/py/.idea/workspace.xml +++ b/py/.idea/workspace.xml @@ -3,16 +3,12 @@ + + - - - - - - - - - + + + @@ -23,7 +19,6 @@ - @@ -33,24 +28,72 @@ - - + + - - + + - - + + - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -58,68 +101,62 @@ - - + + - + - - + + - - - - - + + + - - + + - - - - - + + + - - + + - - + + - + - - + + - - - - - + + + - - + + - - + + @@ -140,19 +177,6 @@ @@ -213,7 +250,7 @@ - PyRedundantParenthesesInspection + PyPep8Inspection @@ -244,6 +281,24 @@ + + + + + + + + + + + + + + @@ -272,7 +327,25 @@ + + + + + + + + + @@ -290,22 +363,18 @@ - - - - - - - - - @@ -313,7 +382,7 @@ - + @@ -334,6 +403,13 @@ + + + + + + + @@ -341,15 +417,19 @@ - - - - - - - - + + + + + - - - + - - - - - - - - - - + + + + + + + + + + @@ -713,20 +786,21 @@ - + - + - - - - - - + + + + + + + - + @@ -754,11 +828,6 @@ 234 - + - - - + + - + - - + + - - + - - + + - + - - + + - + + - - + + - + - - + + - + - - + + - + - - + + - + - - + + - - + - - + + - + - - + + - + - - + + - + - - + + - + - - + + - + - - + + - + - - + + - + - - + + - + - - + + - + - - + + - + - - + + - + - - + + - + - - + + + - + - - + + + - + - - + + + - + - - + + - + - - + + - + - - - - - + + - + - - + + - + - - - + + - + - - - + + - + - - + + - + - - + + - + - - - - - + + - + - - - + + - + - - + + - + - - + + - + - - + + - + - + - - - - - + + - + + + + + + + + - - + + - + - - + + - + - - + + - + - - + + - + - + - - + + - + - - + + - + - - - - - + + + - + - - - - - + + + - + - - - - - + + + - + - - - - - + + + - + - - - - - + + + diff --git a/py/Base/Compiler.py b/py/Base/Compiler.py index 9f8973a0..f2b62193 100644 --- a/py/Base/Compiler.py +++ b/py/Base/Compiler.py @@ -1,30 +1,30 @@ # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2; replace-tabs off; indent-width 2; -# +# # ============================================================================== # Authors: Patrick Lehmann # Martin Zabel -# +# # Python Class: Base class for all PoC***Compilers -# +# # Description: # ------------------------------------ # TODO: -# - -# - +# - +# - # # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany # Chair for VLSI-Design, Diagnostics and Architecture -# +# # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at -# +# # http://www.apache.org/licenses/LICENSE-2.0 -# +# # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -44,22 +44,23 @@ # load dependencies import re import shutil +from enum import Enum, unique from pathlib import Path -from os import chdir from lib.Functions import Init from lib.Parser import ParserException -from Base.Exceptions import ExceptionBase -from Base.Logging import ILogable -from Base.Project import ToolChain, Tool, VHDLVersion, Environment, FileTypes -from Parser.RulesParser import CopyRuleMixIn, ReplaceRuleMixIn, DeleteRuleMixIn -from PoC.Solution import VirtualProject, FileListFile, RulesFile +from Base.Exceptions import ExceptionBase, SkipableException +from Base.Project import VHDLVersion, Environment, FileTypes +from Base.Shared import Shared, to_time +from Parser.RulesParser import CopyRuleMixIn, ReplaceRuleMixIn, DeleteRuleMixIn, AppendLineRuleMixIn +from PoC.Solution import RulesFile +from PoC.TestCase import SynthesisSuite, Synthesis, CompileStatus class CompilerException(ExceptionBase): pass -class SkipableCompilerException(CompilerException): +class SkipableCompilerException(CompilerException, SkipableException): pass class CopyTask(CopyRuleMixIn): @@ -71,143 +72,142 @@ class DeleteTask(DeleteRuleMixIn): class ReplaceTask(ReplaceRuleMixIn): pass +class AppendLineTask(AppendLineRuleMixIn): + pass -class Compiler(ILogable): - _TOOL_CHAIN = ToolChain.Any - _TOOL = Tool.Any - class __Directories__: - Working = None - PoCRoot = None - Netlist = None - Source = None +@unique +class CompileState(Enum): + Prepare = 0 + PreCopy = 10 + PrePatch = 11 + + Compile = 50 + # Analyze = 61 + # Elaborate = 62 + # Optimize = 63 + # Translate = 64 + # Map = 65 + # Place = 66 + # Route = 67 + + PostCopy = 90 + PostPatch = 91 + PostDelete = 92 + CleanUp = 99 + +@unique +class CompileResult(Enum): + NotRun = 0 + Error = 1 + Failed = 2 + Success = 3 + + +class Compiler(Shared): + _ENVIRONMENT = Environment.Synthesis + _vhdlVersion = VHDLVersion.VHDL93 + + class __Directories__(Shared.__Directories__): + Netlist = None + Source = None Destination = None def __init__(self, host, dryRun, noCleanUp): - if isinstance(host, ILogable): - ILogable.__init__(self, host.Logger) - else: - ILogable.__init__(self, None) - - self.__host = host - self._noCleanUp = noCleanUp - self._dryRun = dryRun + super().__init__(host, dryRun) - self._vhdlVersion = VHDLVersion.VHDL93 - self._pocProject = None + self._noCleanUp = noCleanUp - self._directories = self.__Directories__() + self._testSuite = SynthesisSuite() # TODO: This includes not the read ini files phases ... + self._state = CompileState.Prepare + self._preTasksTime = None + self._compileTime = None + self._postTasksTime = None - # class properties - # ============================================================================ - @property - def Host(self): return self.__host - @property - def PoCProject(self): return self._pocProject @property - def Directories(self): return self._directories + def NoCleanUp(self): return self._noCleanUp + + def _PrepareCompiler(self): + self._Prepare() def TryRun(self, netlist, *args, **kwargs): + """Try to run a testbench. Skip skipable exceptions by printing the error and its cause.""" + __COMPILE_STATE_TO_SYNTHESIS_STATUS__ = { + CompileState.Prepare: CompileStatus.InternalError, + CompileState.PreCopy: CompileStatus.SystemError, + CompileState.PrePatch: CompileStatus.SystemError, + CompileState.Compile: CompileStatus.CompileError, + CompileState.PostCopy: CompileStatus.SystemError, + CompileState.PostPatch: CompileStatus.SystemError, + CompileState.PostDelete: CompileStatus.SystemError + } + + synthesis = Synthesis(netlist) + self._testSuite.AddSynthesis(synthesis) + synthesis.StartTimer() try: self.Run(netlist, *args, **kwargs) + # synthesis.UpdateStatus(netlist.Result) + synthesis.Status = CompileStatus.CompileSuccess except SkipableCompilerException as ex: - self._LogQuiet(" {RED}ERROR:{NOCOLOR} {0}".format(ex.message, **Init.Foreground)) + synthesis.Status = __COMPILE_STATE_TO_SYNTHESIS_STATUS__[self._state] + + self.LogQuiet(" {RED}ERROR:{NOCOLOR} {0}".format(ex.message, **Init.Foreground)) cause = ex.__cause__ if (cause is not None): - self._LogQuiet(" {YELLOW}{ExType}:{NOCOLOR} {ExMsg!s}".format(ExType=cause.__class__.__name__, ExMsg=cause, **Init.Foreground)) + self.LogQuiet(" {YELLOW}{ExType}:{NOCOLOR} {ExMsg!s}".format(ExType=cause.__class__.__name__, ExMsg=cause, **Init.Foreground)) cause = cause.__cause__ if (cause is not None): - self._LogQuiet(" {YELLOW}{ExType}:{NOCOLOR} {ExMsg!s}".format(ExType=cause.__class__.__name__, ExMsg=cause, **Init.Foreground)) - self._LogQuiet(" {RED}[SKIPPED DUE TO ERRORS]{NOCOLOR}".format(**Init.Foreground)) + self.LogQuiet(" {YELLOW}{ExType}:{NOCOLOR} {ExMsg!s}".format(ExType=cause.__class__.__name__, ExMsg=cause, **Init.Foreground)) + self.LogQuiet(" {RED}[SKIPPED DUE TO ERRORS]{NOCOLOR}".format(**Init.Foreground)) + except CompilerException: + synthesis.Status = __COMPILE_STATE_TO_SYNTHESIS_STATUS__[self._state] + raise + except ExceptionBase: + synthesis.Status = CompileStatus.SystemError + raise + finally: + synthesis.StopTimer() def Run(self, netlist, board): - self._LogQuiet("{CYAN}IP core:{NOCOLOR} {0!s}".format(netlist.Parent, **Init.Foreground)) + self.LogQuiet("{CYAN}IP core: {0!s}{NOCOLOR}".format(netlist.Parent, **Init.Foreground)) + # # TODO: refactor + # self.LogNormal("Checking for dependencies:") + # for dependency in netlist.Dependencies: + # print(" " + str(dependency)) # setup all needed paths to execute fuse self._PrepareCompilerEnvironment(board.Device) self._WriteSpecialSectionIntoConfig(board.Device) - self._CreatePoCProject(netlist, board) - if netlist.FilesFile is not None: self._AddFileListFile(netlist.FilesFile) - if (netlist.RulesFile is not None): - self._AddRulesFiles(netlist.RulesFile) + self._CreatePoCProject(netlist.ModuleName, board) + if netlist.FilesFile is not None: self._AddFileListFile(netlist.FilesFile) + if (netlist.RulesFile is not None): self._AddRulesFiles(netlist.RulesFile) def _PrepareCompilerEnvironment(self, device): - self._LogNormal("Preparing synthesis environment...") + self.LogNormal("Preparing synthesis environment...") self.Directories.Destination = self.Directories.Netlist / str(device) - # create temporary directory for the compiler if not existent - self._LogVerbose("Creating temporary directory for synthesizer files.") - self._LogDebug("Temporary directory: {0!s}".format(self.Directories.Working)) - if (self.Directories.Working.exists()): - try: - shutil.rmtree(str(self.Directories.Working)) - except OSError as ex: - raise CompilerException("Error while deleting '{0!s}'.".format(self.Directories.Working)) from ex - try: - self.Directories.Working.mkdir(parents=True) - except OSError as ex: - raise CompilerException("Error while creating '{0!s}'.".format(self.Directories.Working)) from ex - - # change working directory to temporary iSim path - self._LogVerbose("Changing working directory to temporary directory.") - self._LogDebug("cd \"{0!s}\"".format(self.Directories.Working)) - try: - chdir(str(self.Directories.Working)) - except OSError as ex: - raise CompilerException("Error while changing to '{0!s}'.".format(self.Directories.Working)) from ex + self._PrepareEnvironment() # create output directory for CoreGen if not existent if (not self.Directories.Destination.exists()) : - self._LogVerbose("Creating output directory for generated files.") - self._LogDebug("Output directory: {0!s}.".format(self.Directories.Destination)) - self.Directories.Destination.mkdir(parents=True) + self.LogVerbose("Creating output directory for generated files.") + self.LogDebug("Output directory: {0!s}.".format(self.Directories.Destination)) + try: + self.Directories.Destination.mkdir(parents=True) + except OSError as ex: + raise CompilerException("Error while creating '{0!s}'.".format(self.Directories.Destination)) from ex def _WriteSpecialSectionIntoConfig(self, device): # add the key Device to section SPECIAL at runtime to change interpolation results self.Host.PoCConfig['SPECIAL'] = {} self.Host.PoCConfig['SPECIAL']['Device'] = device.ShortName self.Host.PoCConfig['SPECIAL']['DeviceSeries'] = device.Series - self.Host.PoCConfig['SPECIAL']['OutputDir'] = self.Directories.Working.as_posix() - - def _CreatePoCProject(self, netlist, board): - # create a PoCProject and read all needed files - self._LogVerbose("Creating a PoC project '{0}'".format(netlist.ModuleName)) - pocProject = VirtualProject(netlist.ModuleName) - - # configure the project - pocProject.RootDirectory = self.Host.Directories.Root - pocProject.Environment = Environment.Synthesis - pocProject.ToolChain = self._TOOL_CHAIN - pocProject.Tool = self._TOOL - pocProject.VHDLVersion = self._vhdlVersion - pocProject.Board = board - - self._pocProject = pocProject - - def _AddFileListFile(self, fileListFilePath): - self._LogVerbose("Reading filelist '{0!s}'".format(fileListFilePath)) - # add the *.files file, parse and evaluate it - try: - fileListFile = self._pocProject.AddFile(FileListFile(fileListFilePath)) - fileListFile.Parse() - fileListFile.CopyFilesToFileSet() - fileListFile.CopyExternalLibraries() - self._pocProject.ExtractVHDLLibrariesFromVHDLSourceFiles() - except ParserException as ex: - raise CompilerException("Error while parsing '{0!s}'.".format(fileListFilePath)) from ex - - self._LogDebug("=" * 78) - self._LogDebug("Pretty printing the PoCProject...") - self._LogDebug(self._pocProject.pprint(2)) - self._LogDebug("=" * 78) - if (len(fileListFile.Warnings) > 0): - for warn in fileListFile.Warnings: - self._LogWarning(warn) - raise CompilerException("Found critical warnings while parsing '{0!s}'".format(fileListFilePath)) + self.Host.PoCConfig['SPECIAL']['OutputDir'] = self.Directories.Working.as_posix() def _AddRulesFiles(self, rulesFilePath): - self._LogVerbose("Reading rules from '{0!s}'".format(rulesFilePath)) + self.LogVerbose("Reading rules from '{0!s}'".format(rulesFilePath)) # add the *.rules file, parse and evaluate it try: rulesFile = self._pocProject.AddFile(RulesFile(rulesFilePath)) @@ -215,15 +215,15 @@ def _AddRulesFiles(self, rulesFilePath): except ParserException as ex: raise SkipableCompilerException("Error while parsing '{0!s}'.".format(rulesFilePath)) from ex - self._LogDebug("Pre-process rules:") + self.LogDebug("Pre-process rules:") for rule in rulesFile.PreProcessRules: - self._LogDebug(" {0!s}".format(rule)) - self._LogDebug("Post-process rules:") + self.LogDebug(" {0!s}".format(rule)) + self.LogDebug("Post-process rules:") for rule in rulesFile.PostProcessRules: - self._LogDebug(" {0!s}".format(rule)) + self.LogDebug(" {0!s}".format(rule)) def _RunPreCopy(self, netlist): - self._LogVerbose("copy further input files into temporary directory...") + self.LogVerbose("Copy further input files into temporary directory...") rulesFiles = [file for file in self.PoCProject.Files(fileType=FileTypes.RulesFile)] # FIXME: get rulefile from netlist object as a rulefile object instead of a path preCopyTasks = [] if (rulesFiles): @@ -235,16 +235,15 @@ def _RunPreCopy(self, netlist): preCopyTasks.append(task) else: preCopyRules = self.Host.PoCConfig[netlist.ConfigSectionName]['PreCopyRules'] - if (len(preCopyRules) != 0): - self._ParseCopyRules(preCopyRules, preCopyTasks) + self._ParseCopyRules(preCopyRules, preCopyTasks, "pre") if (len(preCopyTasks) != 0): self._ExecuteCopyTasks(preCopyTasks, "pre") else: - self._LogDebug("nothing to copy") + self.LogDebug("Nothing to copy") def _RunPostCopy(self, netlist): - self._LogVerbose("copy generated files into netlist directory...") + self.LogVerbose("copy generated files into netlist directory...") rulesFiles = [file for file in self.PoCProject.Files(fileType=FileTypes.RulesFile)] # FIXME: get rulefile from netlist object as a rulefile object instead of a path postCopyTasks = [] if (rulesFiles): @@ -256,23 +255,22 @@ def _RunPostCopy(self, netlist): postCopyTasks.append(task) else: postCopyRules = self.Host.PoCConfig[netlist.ConfigSectionName]['PostCopyRules'] - if (len(postCopyRules) != 0): - self._ParseCopyRules(postCopyRules, postCopyTasks) + self._ParseCopyRules(postCopyRules, postCopyTasks, "post") if (len(postCopyTasks) != 0): self._ExecuteCopyTasks(postCopyTasks, "post") else: - self._LogDebug("nothing to copy") + self.LogDebug("Nothing to copy") - def _ParseCopyRules(self, rawList, copyTasks): + def _ParseCopyRules(self, rawList, copyTasks, text): # read copy tasks if (len(rawList) != 0): + self.LogDebug("Parsing {0}-copy tasks from config file:".format(text)) rawList = rawList.split("\n") - self._LogDebug("Copy tasks from config file:\n " + ("\n ".join(rawList))) - copyRegExpStr = r"^\s*(?P.*?)" # Source filename - copyRegExpStr += r"\s->\s" # Delimiter signs - copyRegExpStr += r"(?P.*?)$" # Destination filename + copyRegExpStr = r"^\s*(?P.*?)" # Source filename + copyRegExpStr += r"\s->\s" # Delimiter signs + copyRegExpStr += r"(?P.*?)$" # Destination filename copyRegExp = re.compile(copyRegExpStr) for item in rawList: @@ -280,23 +278,40 @@ def _ParseCopyRules(self, rawList, copyTasks): if (preCopyRegExpMatch is None): raise CompilerException("Error in copy rule '{0}'.".format(item)) - copyTasks.append(CopyTask(Path(preCopyRegExpMatch.group('SourceFilename')), Path(preCopyRegExpMatch.group('DestFilename')))) + task = CopyTask( + Path(preCopyRegExpMatch.group('SourceFilename')), + Path(preCopyRegExpMatch.group('DestFilename')) + ) + copyTasks.append(task) + self.LogDebug(" {0!s}".format(task)) + else: + self.LogDebug("No {0}-copy tasks specified in config file.".format(text)) def _ExecuteCopyTasks(self, tasks, text): for task in tasks: - if not task.SourcePath.exists(): raise CompilerException("Cannot {0}-copy '{1!s}' to destination.".format(text, task.SourcePath)) from FileNotFoundError(str(task.SourcePath)) + if (not self.DryRun and not task.SourcePath.exists()): + raise CompilerException("Cannot {0}-copy '{1!s}' to destination.".format(text, task.SourcePath)) from FileNotFoundError(str(task.SourcePath)) if not task.DestinationPath.parent.exists(): - task.DestinationPath.parent.mkdir(parents=True) - - self._LogDebug("{0}-copying '{1!s}'.".format(text, task.SourcePath)) - try: - shutil.copy(str(task.SourcePath), str(task.DestinationPath)) - except OSError as ex: - raise CompilerException("Error while copying '{0!s}'.".format(task.SourcePath)) from ex + if self.DryRun: + self.LogDryRun("mkdir '{0!s}'.".format(task.DestinationPath.parent)) + else: + try: + task.DestinationPath.parent.mkdir(parents=True) + except OSError as ex: + raise CompilerException("Error while creating '{0!s}'.".format(task.DestinationPath.parent)) from ex + + self.LogDebug("{0}-copying '{1!s}'.".format(text, task.SourcePath)) + if self.DryRun: + self.LogDryRun("Copy '{0!s}' to '{1!s}'.".format(task.SourcePath, task.DestinationPath)) + else: + try: + shutil.copy(str(task.SourcePath), str(task.DestinationPath)) + except OSError as ex: + raise CompilerException("Error while copying '{0!s}'.".format(task.SourcePath)) from ex def _RunPostDelete(self, netlist): - self._LogVerbose("copy generated files into netlist directory...") + self.LogVerbose("copy generated files into netlist directory...") rulesFiles = [file for file in self.PoCProject.Files(fileType=FileTypes.RulesFile)] # FIXME: get rulefile from netlist object as a rulefile object instead of a path postDeleteTasks = [] if (rulesFiles): @@ -307,21 +322,20 @@ def _RunPostDelete(self, netlist): postDeleteTasks.append(task) else: postDeleteRules = self.Host.PoCConfig[netlist.ConfigSectionName]['PostDeleteRules'] - if (len(postDeleteRules) != 0): - self._ParseDeleteRules(postDeleteRules, postDeleteTasks) + self._ParseDeleteRules(postDeleteRules, postDeleteTasks, "post") - if (self._noCleanUp is True): - self._LogWarning("Disabled cleanup. Skipping post-delete rules.") + if self.NoCleanUp: + self.LogWarning("Disabled cleanup. Skipping post-delete rules.") elif (len(postDeleteTasks) != 0): self._ExecuteDeleteTasks(postDeleteTasks, "post") else: - self._LogDebug("nothing to delete") + self.LogDebug("Nothing to delete") - def _ParseDeleteRules(self, rawList, deleteTasks): + def _ParseDeleteRules(self, rawList, deleteTasks, text): # read delete tasks if (len(rawList) != 0): + self.LogDebug("Parse {0}-delete tasks from config file:".format(text)) rawList = rawList.split("\n") - self._LogDebug("Delete tasks from config file:\n " + ("\n ".join(rawList))) deleteRegExpStr = r"^\s*(?P.*?)$" # filename deleteRegExp = re.compile(deleteRegExpStr) @@ -331,105 +345,192 @@ def _ParseDeleteRules(self, rawList, deleteTasks): if (deleteRegExpMatch is None): raise CompilerException("Error in delete rule '{0}'.".format(item)) - deleteTasks.append(DeleteTask(Path(deleteRegExpMatch.group('Filename')))) + task = DeleteTask(Path(deleteRegExpMatch.group('Filename'))) + deleteTasks.append(task) + self.LogDebug(" {0!s}".format(task)) + else: + self.LogDebug("No {0}-delete tasks specified in config file.".format(text)) def _ExecuteDeleteTasks(self, tasks, text): for task in tasks: - if not task.FilePath.exists(): raise CompilerException("Cannot {0}-delete '{1!s}'.".format(text, task.FilePath)) from FileNotFoundError(str(task.FilePath)) - - self._LogDebug("{0}-deleting '{1!s}'.".format(text, task.FilePath)) - task.FilePath.unlink() + if (not self.DryRun and not task.FilePath.exists()): + raise CompilerException("Cannot {0}-delete '{1!s}'.".format(text, task.FilePath)) from FileNotFoundError(str(task.FilePath)) + + self.LogDebug("{0}-deleting '{1!s}'.".format(text, task.FilePath)) + if self.DryRun: + self.LogDryRun("Delete '{0!s}'.".format(task.FilePath)) + else: + try: + task.FilePath.unlink() + except OSError as ex: + raise CompilerException("Error while deleting '{0!s}'.".format(task.FilePath)) from ex def _RunPreReplace(self, netlist): - self._LogVerbose("patching files in temporary directory...") + self.LogVerbose("Patching files in temporary directory...") rulesFiles = [file for file in self.PoCProject.Files(fileType=FileTypes.RulesFile)] # FIXME: get rulefile from netlist object as a rulefile object instead of a path preReplaceTasks = [] if (rulesFiles): for rule in rulesFiles[0].PreProcessRules: if isinstance(rule, ReplaceRuleMixIn): filePath = self.Host.PoCConfig.Interpolation.interpolate(self.Host.PoCConfig, netlist.ConfigSectionName, "RulesFile", rule.FilePath, {}) - searchPattern = self.Host.PoCConfig.Interpolation.interpolate(self.Host.PoCConfig, netlist.ConfigSectionName, "RulesFile", rule.SearchPattern, {}) + searchPattern = self.Host.PoCConfig.Interpolation.interpolate(self.Host.PoCConfig, netlist.ConfigSectionName, "RulesFile", rule.SearchPattern, {}) replacePattern = self.Host.PoCConfig.Interpolation.interpolate(self.Host.PoCConfig, netlist.ConfigSectionName, "RulesFile", rule.ReplacePattern, {}) task = ReplaceTask(Path(filePath), searchPattern, replacePattern, rule.RegExpOption_MultiLine, rule.RegExpOption_DotAll, rule.RegExpOption_CaseInsensitive) preReplaceTasks.append(task) + elif isinstance(rule, AppendLineRuleMixIn): + filePath = self.Host.PoCConfig.Interpolation.interpolate(self.Host.PoCConfig, netlist.ConfigSectionName, "RulesFile", rule.FilePath, {}) + appendPattern = self.Host.PoCConfig.Interpolation.interpolate(self.Host.PoCConfig, netlist.ConfigSectionName, "RulesFile", rule.AppendPattern, {}) + task = AppendLineTask(Path(filePath), appendPattern) + preReplaceTasks.append(task) + elif isinstance(rule, CopyRuleMixIn): + pass + else: + raise CompilerException("Unknown pre-process rule '{0!s}'.".format(rule)) else: preReplaceRules = self.Host.PoCConfig[netlist.ConfigSectionName]['PreReplaceRules'] - if (len(preReplaceRules) != 0): - self._ParseReplaceRules(preReplaceRules, preReplaceTasks) + self._ParseReplaceRules(preReplaceRules, preReplaceTasks, "pre") if (len(preReplaceTasks) != 0): self._ExecuteReplaceTasks(preReplaceTasks, "pre") else: - self._LogDebug("nothing to patch") + self.LogDebug("Nothing to patch.") def _RunPostReplace(self, netlist): - self._LogVerbose("patching files in netlist directory...") + self.LogVerbose("Patching files in netlist directory...") rulesFiles = [file for file in self.PoCProject.Files(fileType=FileTypes.RulesFile)] # FIXME: get rulefile from netlist object as a rulefile object instead of a path postReplaceTasks = [] if (rulesFiles): for rule in rulesFiles[0].PostProcessRules: if isinstance(rule, ReplaceRuleMixIn): filePath = self.Host.PoCConfig.Interpolation.interpolate(self.Host.PoCConfig, netlist.ConfigSectionName, "RulesFile", rule.FilePath, {}) - searchPattern = self.Host.PoCConfig.Interpolation.interpolate(self.Host.PoCConfig, netlist.ConfigSectionName, "RulesFile", rule.SearchPattern, {}) + searchPattern = self.Host.PoCConfig.Interpolation.interpolate(self.Host.PoCConfig, netlist.ConfigSectionName, "RulesFile", rule.SearchPattern, {}) replacePattern = self.Host.PoCConfig.Interpolation.interpolate(self.Host.PoCConfig, netlist.ConfigSectionName, "RulesFile", rule.ReplacePattern, {}) task = ReplaceTask(Path(filePath), searchPattern, replacePattern, rule.RegExpOption_MultiLine, rule.RegExpOption_DotAll, rule.RegExpOption_CaseInsensitive) postReplaceTasks.append(task) + elif isinstance(rule, AppendLineRuleMixIn): + filePath = self.Host.PoCConfig.Interpolation.interpolate(self.Host.PoCConfig, netlist.ConfigSectionName, "RulesFile", rule.FilePath, {}) + appendPattern = self.Host.PoCConfig.Interpolation.interpolate(self.Host.PoCConfig, netlist.ConfigSectionName, "RulesFile", rule.AppendPattern, {}) + task = AppendLineTask(Path(filePath), appendPattern) + postReplaceTasks.append(task) + elif isinstance(rule, (CopyRuleMixIn, DeleteRuleMixIn)): + pass + else: + raise CompilerException("Unknown post-process rule '{0!s}'.".format(rule)) else: postReplaceRules = self.Host.PoCConfig[netlist.ConfigSectionName]['PostReplaceRules'] - if (len(postReplaceRules) != 0): - self._ParseReplaceRules(postReplaceRules, postReplaceTasks) + self._ParseReplaceRules(postReplaceRules, postReplaceTasks, "post") if (len(postReplaceTasks) != 0): self._ExecuteReplaceTasks(postReplaceTasks, "post") else: - self._LogDebug("nothing to patch") - - def _ParseReplaceRules(self, rawList, replaceTasks): - rawList = rawList.split("\n") - self._LogDebug("Replacement tasks:\n " + ("\n ".join(rawList))) - - # FIXME: Rework inline replace rule syntax. - replaceRegExpStr = r"^\s*(?P.*?)\s+:" # Filename - replaceRegExpStr += r"(?P[dim]{0,3}):\s+" # RegExp options - replaceRegExpStr += r"\"(?P.*?)\"\s+->\s+" # Search regexp - replaceRegExpStr += r"\"(?P.*?)\"$" # Replace regexp - replaceRegExp = re.compile(replaceRegExpStr) - - for item in rawList: - replaceRegExpMatch = replaceRegExp.match(item) - - if (replaceRegExpMatch is None): - raise CompilerException("Error in replace rule '{0}'.".format(item)) - - replaceTasks.append(ReplaceTask( - Path(replaceRegExpMatch.group('Filename')), - replaceRegExpMatch.group('Search'), - replaceRegExpMatch.group('Replace'), - # replaceRegExpMatch.group('Options'), # FIXME: - # replaceRegExpMatch.group('Options'), # FIXME: - # replaceRegExpMatch.group('Options'), # FIXME: - False, False, False - )) + self.LogDebug("Nothing to patch.") + + def _ParseReplaceRules(self, rawList, replaceTasks, text): + # read replace tasks + if (len(rawList) != 0): + self.LogDebug("Parsing {0}-replacement tasks:".format(text)) + rawList = rawList.split("\n") + + # FIXME: Rework inline replace rule syntax. + replaceRegExpStr = r"^\s*(?P.*?)\s+:" # Filename + replaceRegExpStr += r"(?P[dim]{0,3}):\s+" # RegExp options + replaceRegExpStr += r"\"(?P.*?)\"\s+->\s+" # Search regexp + replaceRegExpStr += r"\"(?P.*?)\"$" # Replace regexp + replaceRegExp = re.compile(replaceRegExpStr) + + for item in rawList: + replaceRegExpMatch = replaceRegExp.match(item) + + if (replaceRegExpMatch is None): + raise CompilerException("Error in replace rule '{0}'.".format(item)) + + task = ReplaceTask( + Path(replaceRegExpMatch.group('Filename')), + replaceRegExpMatch.group('Search'), + replaceRegExpMatch.group('Replace'), + # replaceRegExpMatch.group('Options'), # FIXME: + # replaceRegExpMatch.group('Options'), # FIXME: + # replaceRegExpMatch.group('Options'), # FIXME: + False, False, False + ) + replaceTasks.append(task) + self.LogDebug(" {0!s}".format(task)) + else: + self.LogDebug("No {0}-replace tasks specified in config file.".format(text)) def _ExecuteReplaceTasks(self, tasks, text): for task in tasks: - if not task.FilePath.exists(): raise CompilerException("Cannot {0}-replace in file '{1!s}'.".format(text, task.FilePath)) from FileNotFoundError(str(task.FilePath)) - self._LogDebug("{0}-replace in file '{1!s}': search for '{2}' replace by '{3}'.".format(text, task.FilePath, task.SearchPattern, task.ReplacePattern)) - - regExpFlags = 0 - if task.RegExpOption_CaseInsensitive: regExpFlags |= re.IGNORECASE - if task.RegExpOption_MultiLine: regExpFlags |= re.MULTILINE - if task.RegExpOption_DotAll: regExpFlags |= re.DOTALL - - # compile regexp - regExp = re.compile(task.SearchPattern, regExpFlags) - # open file and read all lines - with task.FilePath.open('r') as fileHandle: - FileContent = fileHandle.read() - # replace - NewContent,replaceCount = re.subn(regExp, task.ReplacePattern, FileContent) - if (replaceCount == 0): - self._LogWarning(" Search pattern '{0}' not found in file '{1!s}'.".format(task.SearchPattern, task.FilePath)) - # open file to write the replaced data - with task.FilePath.open('w') as fileHandle: - fileHandle.write(NewContent) + if (not self.DryRun and not task.FilePath.exists()): + raise CompilerException("Cannot {0}-replace in file '{1!s}'.".format(text, task.FilePath)) from FileNotFoundError(str(task.FilePath)) + self.LogDebug("{0}-replace in file '{1!s}': search for '{2}' replace by '{3}'.".format(text, task.FilePath, task.SearchPattern, task.ReplacePattern)) + + if self.DryRun: + self.LogDryRun("Patch '{0!s}'.".format(task.FilePath)) + else: + regExpFlags = 0 + if task.RegExpOption_CaseInsensitive: regExpFlags |= re.IGNORECASE + if task.RegExpOption_MultiLine: regExpFlags |= re.MULTILINE + if task.RegExpOption_DotAll: regExpFlags |= re.DOTALL + + # compile regexp + regExp = re.compile(task.SearchPattern, regExpFlags) + # open file and read all lines + with task.FilePath.open('r') as fileHandle: + FileContent = fileHandle.read() + # replace + NewContent,replaceCount = re.subn(regExp, task.ReplacePattern, FileContent) + if (replaceCount == 0): + self.LogWarning(" Search pattern '{0}' not found in file '{1!s}'.".format(task.SearchPattern, task.FilePath)) + # open file to write the replaced data + with task.FilePath.open('w') as fileHandle: + fileHandle.write(NewContent) + + def PrintOverallCompileReport(self): + self.LogQuiet("{HEADLINE}{line}{NOCOLOR}".format(line="=" * 80, **Init.Foreground)) + self.LogQuiet("{HEADLINE}{headline: ^80s}{NOCOLOR}".format(headline="Overall Compile Report", **Init.Foreground)) + self.LogQuiet("{HEADLINE}{line}{NOCOLOR}".format(line="=" * 80, **Init.Foreground)) + # table header + self.LogQuiet("{Name: <24} | {Duration: >5} | {Status: ^11}".format(Name="Name", Duration="Time", Status="Status")) + self.LogQuiet("-" * 80) + self.PrintCompileReportLine(self._testSuite, 0, 24) + + self.LogQuiet("{HEADLINE}{line}{NOCOLOR}".format(line="=" * 80, **Init.Foreground)) + self.LogQuiet("Time: {time: >5} Count: {count: <3} Success: {success: <3} Failed: {failed: <2} Errors: {error: <2}".format( + time=to_time(self._testSuite.OverallRunTime), + count=self._testSuite.Count, + success=self._testSuite.SuccessCount, + failed=self._testSuite.FailedCount, + error=self._testSuite.ErrorCount + )) + self.LogQuiet("{HEADLINE}{line}{NOCOLOR}".format(line="=" * 80, **Init.Foreground)) + + __COMPILE_REPORT_COLOR_TABLE__ = { + CompileStatus.Unknown: "RED", + CompileStatus.InternalError: "DARK_RED", + CompileStatus.SystemError: "DARK_RED", + CompileStatus.CompileError: "RED", + CompileStatus.CompileSuccess: "GREEN" + } + + __COMPILE_REPORT_STATUS_TEXT_TABLE__ = { + CompileStatus.Unknown: "-- ?? --", + CompileStatus.InternalError: "INT. ERROR", + CompileStatus.SystemError: "SYS. ERROR", + CompileStatus.CompileError: "COMP. ERROR", + CompileStatus.CompileSuccess: "SUCCESS" + } + + def PrintCompileReportLine(self, testObject, indent, nameColumnWidth): + _indent = " " * indent + for group in testObject.Groups.values(): + pattern = "{indent}{{groupName: <{nameColumnWidth}}} | | ".format(indent=_indent, nameColumnWidth=nameColumnWidth) + self.LogQuiet(pattern.format(groupName=group.Name)) + self.PrintCompileReportLine(group, indent + 1, nameColumnWidth - 2) + for synthesis in testObject.Synthesises.values(): + pattern = "{indent}{{netlistName: <{nameColumnWidth}}} | {{duration: >5}} | {{{color}}}{{status: ^11}}{{NOCOLOR}}".format( + indent=_indent, nameColumnWidth=nameColumnWidth, color=self.__COMPILE_REPORT_COLOR_TABLE__[synthesis.Status]) + self.LogQuiet(pattern.format( + netlistName=synthesis.Name, + duration=to_time(synthesis.OverallRunTime), + status=self.__COMPILE_REPORT_STATUS_TEXT_TABLE__[synthesis.Status], **Init.Foreground + )) diff --git a/py/Base/Configuration.py b/py/Base/Configuration.py index 604472ec..63fe308d 100644 --- a/py/Base/Configuration.py +++ b/py/Base/Configuration.py @@ -77,14 +77,18 @@ class SkipConfigurationException(ExceptionBase): # return self._subclasses class Configuration: #(ISubClassRegistration): - _vendor = "Unknown" - _toolName = "Unknown" - _section = "ERROR" - _template = {} + _vendor = "Unknown" + _toolName = "Unknown" + _section = "ERROR" + _template = {} def __init__(self, host): self._host = host + @property + def Host(self): + return self._host + def IsSupportedPlatform(self): if (self._host.Platform not in self._template): return ("ALL" in self._template) @@ -198,8 +202,8 @@ def _TestDefaultInstallPath(self, defaults): def _ConfigureVersion(self): """ - Asks for version and updates section. Returns version as string. - If no version was configured before, then _GetDefaultVersion is called. + If no version was configured before, then _GetDefaultVersion is called. + Asks for version and updates section. Returns version as string. """ if self._host.PoCConfig.has_option(self._section, 'Version'): defaultVersion = self._host.PoCConfig[self._section]['Version'] @@ -229,13 +233,13 @@ def _ConfigureBinaryDirectory(self): unresolved = self._template[self._host.Platform][self._section]['BinaryDirectory'] self._host.PoCConfig[self._section]['BinaryDirectory'] = unresolved # create entry defaultPath = Path(self._host.PoCConfig[self._section]['BinaryDirectory']) # resolve entry - + binPath = defaultPath # may be more complex in the future if (not binPath.exists()): raise ConfigurationException("{0!s} binary directory '{1!s}' does not exist.".format(self, binPath)) \ from NotADirectoryError(str(binPath)) - + return binPath def RunPostConfigurationTasks(self): diff --git a/py/Base/Exceptions.py b/py/Base/Exceptions.py index d4f3891d..d19b183e 100644 --- a/py/Base/Exceptions.py +++ b/py/Base/Exceptions.py @@ -1,29 +1,29 @@ # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2; replace-tabs off; indent-width 2; -# +# # ============================================================================== # Authors: Patrick Lehmann -# +# # Python Class: TODO -# +# # Description: # ------------------------------------ # TODO: -# - -# - +# - +# - # # License: # ============================================================================== # Copyright 2007-2015 Technische Universitaet Dresden - Germany # Chair for VLSI-Design, Diagnostics and Architecture -# +# # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at -# +# # http://www.apache.org/licenses/LICENSE-2.0 -# +# # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -47,7 +47,7 @@ def __init__(self, message=""): def __str__(self): return self.message - + class EnvironmentException(ExceptionBase): pass @@ -57,11 +57,11 @@ class PlatformNotSupportedException(ExceptionBase): class NotConfiguredException(ExceptionBase): pass +class SkipableException(ExceptionBase): + pass + class CommonException(ExceptionBase): pass -class TestbenchException(ExceptionBase): - def __init__(self, pocEntity, testbench, message): - super().__init__(message) - self.pocEntity = pocEntity - self.testbench = testbench +class SkipableCommonException(CommonException, SkipableException): + pass diff --git a/py/Base/Executable.py b/py/Base/Executable.py index ae5346d1..645c3b67 100644 --- a/py/Base/Executable.py +++ b/py/Base/Executable.py @@ -1,29 +1,29 @@ # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2; replace-tabs off; indent-width 2; -# +# # ============================================================================== # Authors: Patrick Lehmann -# +# # Python Class: TODO -# +# # Description: # ------------------------------------ # TODO: -# - -# - +# - +# - # # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany # Chair for VLSI-Design, Diagnostics and Architecture -# +# # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at -# +# # http://www.apache.org/licenses/LICENSE-2.0 -# +# # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -56,7 +56,7 @@ def __init__(self, message=""): class CommandLineArgument(type): _value = None - + # def __new__(mcls, name, bases, nmspc): # print("CommandLineArgument.new: %s - %s" % (name, nmspc)) # return super(CommandLineArgument, mcls).__new__(mcls, name, bases, nmspc) @@ -69,16 +69,53 @@ def Value(self): @Value.setter def Value(self, value): if isinstance(value, str): self._value = value - elif isinstance(value, Path): self._value = str(value) - else: raise ValueError("Parameter 'value' is not of type str or Path.") + elif isinstance(value, Path): self._value = str(value) + else: raise ValueError("Parameter 'value' is not of type str or Path.") def __str__(self): - if (self._value is None): return "" - else: return self._value + if (self._value is None): return "" + else: return self._value + + def AsArgument(self): + if (self._value is None): raise ValueError("Executable argument is still empty.") + else: return self._value + + +class NamedCommandLineArgument(CommandLineArgument): + _name = None # set in sub-classes + + @property + def Name(self): + return self._name + + +class CommandArgument(NamedCommandLineArgument): + _pattern = "{0}" + + @property + def Value(self): + return self._value + + @Value.setter + def Value(self, value): + if (value is None): self._value = None + elif isinstance(value, bool): self._value = value + else: raise ValueError("Parameter 'value' is not of type bool.") + + def __str__(self): + if (self._value is None): return "" + elif self._value: return self._pattern.format(self._name) + else: return "" def AsArgument(self): - if (self._value is None): raise ValueError("Executable argument is still empty.") - else: return self._value + if (self._value is None): return None + elif self._value: return self._pattern.format(self._name) + else: return None + +class ShortCommandArgument(CommandArgument): _pattern = "-{0}" +class LongCommandArgument(CommandArgument): _pattern = "--{0}" +class WindowsCommandArgument(CommandArgument): _pattern = "/{0}" + class StringArgument(CommandLineArgument): _pattern = "{0}" @@ -114,18 +151,18 @@ def Value(self): @Value.setter def Value(self, value): - if (value is None): self._value = None + if (value is None): self._value = None elif isinstance(value, (tuple, list)): self._value = [] try: - for item in value: self._value.append(str(value)) - except TypeError as ex: raise ValueError("Item '{0}' in parameter 'value' cannot be converted to type str.".format(item)) from ex - else: raise ValueError("Parameter 'value' is no list or tuple.") + for item in value: self._value.append(str(item)) + except TypeError as ex: raise ValueError("Item '{0}' in parameter 'value' cannot be converted to type str.".format(item)) from ex + else: raise ValueError("Parameter 'value' is no list or tuple.") def __str__(self): - if (self._value is None): return "" - elif self._value: return " ".join([self._pattern.format(item) for item in self._value]) - else: return "" + if (self._value is None): return "" + elif self._value: return " ".join([self._pattern.format(item) for item in self._value]) + else: return "" def AsArgument(self): if (self._value is None): return None @@ -156,14 +193,6 @@ def AsArgument(self): else: return str(self._value) -class NamedCommandLineArgument(CommandLineArgument): - _name = None # set in sub-classes - - @property - def Name(self): - return self._name - - class FlagArgument(NamedCommandLineArgument): _pattern = "{0}" @@ -173,23 +202,23 @@ def Value(self): @Value.setter def Value(self, value): - if (value is None): self._value = None - elif isinstance(value, bool): self._value = value - else: raise ValueError("Parameter 'value' is not of type bool.") + if (value is None): self._value = None + elif isinstance(value, bool): self._value = value + else: raise ValueError("Parameter 'value' is not of type bool.") def __str__(self): - if (self._value is None): return "" - elif self._value: return self._pattern.format(self._name) - else: return "" + if (self._value is None): return "" + elif self._value: return self._pattern.format(self._name) + else: return "" def AsArgument(self): - if (self._value is None): return None - elif self._value: return self._pattern.format(self._name) - else: return None + if (self._value is None): return None + elif self._value: return self._pattern.format(self._name) + else: return None -class ShortFlagArgument(FlagArgument): _pattern = "-{0}" -class LongFlagArgument(FlagArgument): _pattern = "--{0}" -class WindowsFlagArgument(FlagArgument): _pattern = "/{0}" +class ShortFlagArgument(FlagArgument): _pattern = "-{0}" +class LongFlagArgument(FlagArgument): _pattern = "--{0}" +class WindowsFlagArgument(FlagArgument): _pattern = "/{0}" class ValuedFlagArgument(NamedCommandLineArgument): _pattern = "{0}={1}" @@ -200,24 +229,24 @@ def Value(self): @Value.setter def Value(self, value): - if (value is None): self._value = None + if (value is None): self._value = None elif isinstance(value, str): self._value = value else: try: self._value = str(value) - except Exception as ex: raise ValueError("Parameter 'value' cannot be converted to type str.") from ex - + except Exception as ex: raise ValueError("Parameter 'value' cannot be converted to type str.") from ex + def __str__(self): - if (self._value is None): return "" - elif self._value: return self._pattern.format(self._name, self._value) - else: return "" - + if (self._value is None): return "" + elif self._value: return self._pattern.format(self._name, self._value) + else: return "" + def AsArgument(self): - if (self._value is None): return None - elif self._value: return self._pattern.format(self._name, self._value) - else: return None + if (self._value is None): return None + elif self._value: return self._pattern.format(self._name, self._value) + else: return None class ShortValuedFlagArgument(ValuedFlagArgument): _pattern = "-{0}={1}" -class LongValuedFlagArgument(ValuedFlagArgument): _pattern = "--{0}={1}" +class LongValuedFlagArgument(ValuedFlagArgument): _pattern = "--{0}={1}" class ValuedFlagListArgument(NamedCommandLineArgument): _pattern = "{0}={1}" @@ -233,21 +262,21 @@ def Value(self, value): else: raise ValueError("Parameter 'value' is not of type tuple or list.") def __str__(self): - if (self._value is None): return "" + if (self._value is None): return "" elif (len(self._value) > 0): return " ".join([self._pattern.format(self._name, item) for item in self._value]) - else: return "" + else: return "" def AsArgument(self): - if (self._value is None): return None + if (self._value is None): return None elif (len(self._value) > 0): return [self._pattern.format(self._name, item) for item in self._value] - else: return None + else: return None class ShortValuedFlagListArgument(ValuedFlagListArgument): _pattern = "-{0}={1}" -class LongValuedFlagListArgument(ValuedFlagListArgument): _pattern = "--{0}={1}" +class LongValuedFlagListArgument(ValuedFlagListArgument): _pattern = "--{0}={1}" class TupleArgument(NamedCommandLineArgument): _switchPattern = "{0}" - _valuePattern = "{0}" + _valuePattern = "{0}" @property def Value(self): @@ -255,24 +284,24 @@ def Value(self): @Value.setter def Value(self, value): - if (value is None): self._value = None + if (value is None): self._value = None elif isinstance(value, str): self._value = value else: try: self._value = str(value) - except TypeError as ex: raise ValueError("Parameter 'value' cannot be converted to type str.") from ex - + except TypeError as ex: raise ValueError("Parameter 'value' cannot be converted to type str.") from ex + def __str__(self): - if (self._value is None): return "" - elif self._value: return self._switchPattern.format(self._name) + " \"" + self._valuePattern.format(self._value) + "\"" - else: return "" - + if (self._value is None): return "" + elif self._value: return self._switchPattern.format(self._name) + " \"" + self._valuePattern.format(self._value) + "\"" + else: return "" + def AsArgument(self): - if (self._value is None): return None - elif self._value: return [self._switchPattern.format(self._name), self._valuePattern.format(self._value)] - else: return None + if (self._value is None): return None + elif self._value: return [self._switchPattern.format(self._name), self._valuePattern.format(self._value)] + else: return None class ShortTupleArgument(TupleArgument): _switchPattern = "-{0}" -class LongTupleArgument(TupleArgument): _switchPattern = "--{0}" +class LongTupleArgument(TupleArgument): _switchPattern = "--{0}" class CommandLineArgumentList(list): def __init__(self, *args): @@ -283,39 +312,42 @@ def __init__(self, *args): def __getitem__(self, key): i = self.index(key) return super().__getitem__(i).Value - + def __setitem__(self, key, value): i = self.index(key) super().__getitem__(i).Value = value - + def __delitem__(self, key): i = self.index(key) super().__getitem__(i).Value = None - + def ToArgumentList(self): result = [] for item in self: arg = item.AsArgument() - if (arg is None): pass + if (arg is None): pass elif isinstance(arg, str): result.append(arg) - elif isinstance(arg, list): result += arg - else: raise TypeError() + elif isinstance(arg, list): result += arg + else: raise TypeError() return result class Executable(ILogable): _POC_BOUNDARY = "====== POC BOUNDARY ======" - def __init__(self, platform, executablePath, logger=None): + def __init__(self, platform, dryrun, executablePath, logger=None): super().__init__(logger) self._platform = platform - self._process = None - + self._dryrun = dryrun + self._process = None + if isinstance(executablePath, str): executablePath = Path(executablePath) elif (not isinstance(executablePath, Path)): raise ValueError("Parameter 'executablePath' is not of type str or Path.") - if (not executablePath.exists()): raise CommonException("Executable '{0!s}' cannot be found.".format(executablePath)) from FileNotFoundError(str(executablePath)) - + if (not executablePath.exists()): + if dryrun: self.LogDryRun("File check for '{0!s}' failed. [SKIPPING]".format(executablePath)) + else: raise CommonException("Executable '{0!s}' not found.".format(executablePath)) from FileNotFoundError(str(executablePath)) + # prepend the executable self._executablePath = executablePath self._iterator = None @@ -327,10 +359,13 @@ def Path(self): def StartProcess(self, parameterList): # start child process # parameterList.insert(0, str(self._executablePath)) - try: - self._process = Subprocess_Popen(parameterList, stdin=Subprocess_Pipe, stdout=Subprocess_Pipe, stderr=Subprocess_StdOut, universal_newlines=True, bufsize=256) - except OSError as ex: - raise CommonException("Error while accessing '{0!s}'.".format(self._executablePath)) from ex + if (not self._dryrun): + try: + self._process = Subprocess_Popen(parameterList, stdin=Subprocess_Pipe, stdout=Subprocess_Pipe, stderr=Subprocess_StdOut, universal_newlines=True, bufsize=256) + except OSError as ex: + raise CommonException("Error while accessing '{0!s}'.".format(self._executablePath)) from ex + else: + self.LogDryRun("Start process: {0}".format(" ".join(parameterList))) def Send(self, line, end="\n"): self._process.stdin.write(line + end) @@ -344,7 +379,6 @@ def Terminate(self): def GetReader(self): try: - # for line in self._process.stdout.readlines(): for line in iter(self._process.stdout.readline, ""): yield line[:-1] except Exception as ex: @@ -361,4 +395,4 @@ def ReadUntilBoundary(self, indent=0): print(__indent + line) if (self._POC_BOUNDARY in line): break - self._LogDebug("Quartus II is ready") + self.LogDebug("Quartus II is ready") diff --git a/py/Base/Logging.py b/py/Base/Logging.py index 854d76e2..7a4dee56 100644 --- a/py/Base/Logging.py +++ b/py/Base/Logging.py @@ -1,7 +1,7 @@ # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2; replace-tabs off; indent-width 2; -# +# # ============================================================================== # Authors: Patrick Lehmann # Thomas B. Preusser @@ -11,20 +11,20 @@ # Description: # ------------------------------------ # TODO: -# - -# - +# - +# - # # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany # Chair for VLSI-Design, Diagnostics and Architecture -# +# # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at -# +# # http://www.apache.org/licenses/LICENSE-2.0 -# +# # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -40,9 +40,12 @@ from lib.Functions import Exit Exit.printThisIsNoExecutableFile("The PoC-Library - Python Module Base.PoCBase") -from colorama import Fore as Foreground -from enum import Enum, unique - + +from enum import Enum, unique + +from lib.Functions import Init + + @unique class Severity(Enum): Fatal = 30 @@ -50,6 +53,7 @@ class Severity(Enum): Quiet = 20 Warning = 15 Info = 10 + DryRun = 5 Normal = 4 Verbose = 2 Debug = 1 @@ -60,7 +64,9 @@ def __init__(self, *_): for k,v in self.__class__.__VHDL_SEVERITY_LEVEL_MAP__.items(): if ((not isinstance(v, self.__class__)) and (v == self.value)): self.__class__.__VHDL_SEVERITY_LEVEL_MAP__[k] = self - break + + def __hash__(self): + return hash(self.name) def __eq__(self, other): return self.value == other.value def __ne__(self, other): return self.value != other.value @@ -86,140 +92,161 @@ def __init__(self, message, severity=Severity.Normal, indent=0): self._severity = severity self._message = message self._indent = indent - + + _Log_MESSAGE_FORMAT__ = { + Severity.Fatal: "FATAL: {message}", + Severity.Error: "ERROR: {message}", + Severity.Warning: "WARNING: {message}", + Severity.Info: "INFO: {message}", + Severity.Quiet: "{message}", + Severity.Normal: "{message}", + Severity.Verbose: "VERBOSE: {message}", + Severity.Debug: "DEBUG: {message}", + Severity.DryRun: "DRYRUN: {message}" + } + @property - def Severity(self): return self._severity + def Severity(self): return self._severity @property - def Indent(self): return self._indent + def Indent(self): return self._indent @property def Message(self): return (" " * self._indent) + self._message def IndentBy(self, indent): self._indent += indent - + def __str__(self): - if (self._severity is Severity.Fatal): return "FATAL: " + self._message - elif (self._severity is Severity.Error): return "ERROR: " + self._message - elif (self._severity is Severity.Warning): return "WARNING: " + self._message - elif (self._severity is Severity.Info): return "INFO: " + self._message - elif (self._severity is Severity.Quiet): return self._message - elif (self._severity is Severity.Normal): return self._message - elif (self._severity is Severity.Verbose): return "VERBOSE: " + self._message - elif (self._severity is Severity.Debug): return "DEBUG: " + self._message + return self._Log_MESSAGE_FORMAT__[self._severity].format(message=self._message) class Logger: def __init__(self, host, logLevel, printToStdOut=True): - self._host = host - self._logLevel = logLevel - self._printToStdOut = printToStdOut - self._entries = [] - + self._host = host + self._LogLevel = logLevel + self._printToStdOut = printToStdOut + self._entries = [] + self._baseIndent = 0 + @property - def LogLevel(self): - return self._logLevel + def LogLevel(self): return self._LogLevel @LogLevel.setter - def LogLevel(self, value): - self._logLevel = value - + def LogLevel(self, value): self._LogLevel = value + + @property + def BaseIndent(self): return self._baseIndent + @BaseIndent.setter + def BaseIndent(self, value): self._baseIndent = value + + _Log_MESSAGE_FORMAT__ = { + Severity.Fatal: "{DARKRED}{message}{NOCOLOR}", + Severity.Error: "{RED}{message}{NOCOLOR}", + Severity.Quiet: "{WHITE}{message}{NOCOLOR}", + Severity.Warning: "{YELLOW}{message}{NOCOLOR}", + Severity.Info: "{WHITE}{message}{NOCOLOR}", + Severity.DryRun: "{DARK_CYAN}{message}{NOCOLOR}", + Severity.Normal: "{WHITE}{message}{NOCOLOR}", + Severity.Verbose: "{GRAY}{message}{NOCOLOR}", + Severity.Debug: "{DARK_GRAY}{message}{NOCOLOR}" + } + def Write(self, entry): - if (entry.Severity >= self._logLevel): + if (entry.Severity >= self._LogLevel): self._entries.append(entry) if self._printToStdOut: - if (entry.Severity is Severity.Fatal): print("{0}{1}{2}".format(Foreground.RED, entry.Message, Foreground.RESET)) - elif (entry.Severity is Severity.Error): print("{0}{1}{2}".format(Foreground.LIGHTRED_EX, entry.Message, Foreground.RESET)) - elif (entry.Severity is Severity.Quiet): print(entry.Message) - elif (entry.Severity is Severity.Warning): print("{0}{1}{2}".format(Foreground.LIGHTYELLOW_EX, entry.Message, Foreground.RESET)) - elif (entry.Severity is Severity.Info): print("{0}{1}{2}".format(Foreground.CYAN, entry.Message, Foreground.RESET)) - elif (entry.Severity is Severity.Normal): print(entry.Message) - elif (entry.Severity is Severity.Verbose): print("{0}{1}{2}".format(Foreground.WHITE, entry.Message, Foreground.RESET)) - elif (entry.Severity is Severity.Debug): print("{0}{1}{2}".format(Foreground.LIGHTBLACK_EX, entry.Message, Foreground.RESET)) - + print(self._Log_MESSAGE_FORMAT__[entry.Severity].format(message=entry.Message, **Init.Foreground)) return True else: return False def TryWrite(self, entry): - return (entry.Severity >= self._logLevel) - + return (entry.Severity >= self._LogLevel) + def WriteFatal(self, message): return self.Write(LogEntry(message, Severity.Fatal)) - + def WriteError(self, message): return self.Write(LogEntry(message, Severity.Error)) - + def WriteWarning(self, message): return self.Write(LogEntry(message, Severity.Warning)) - + def WriteInfo(self, message): return self.Write(LogEntry(message, Severity.Info)) - + def WriteQuiet(self, message): return self.Write(LogEntry(message, Severity.Quiet)) - + def WriteNormal(self, message, indent=0): - return self.Write(LogEntry(message, Severity.Normal, indent)) - + return self.Write(LogEntry(message, Severity.Normal, self._baseIndent + indent)) + def WriteVerbose(self, message, indent=1): - return self.Write(LogEntry(message, Severity.Verbose, indent)) - + return self.Write(LogEntry(message, Severity.Verbose, self._baseIndent + indent)) + def WriteDebug(self, message, indent=2): - return self.Write(LogEntry(message, Severity.Debug, indent)) - - + return self.Write(LogEntry(message, Severity.Debug, self._baseIndent + indent)) + + def WriteDryRun(self, message, indent=2): + return self.Write(LogEntry(message, Severity.DryRun, self._baseIndent + indent)) + + class ILogable: def __init__(self, logger=None): - self.__logger = logger + self._Logger = logger @property def Logger(self): - return self.__logger + return self._Logger - def _Log(self, entry): - if self.__logger is not None: - return self.__logger.Write(entry) + def Log(self, entry): + if self._Logger is not None: + return self._Logger.Write(entry) return False def _TryLog(self, *args, **kwargs): - if self.__logger is not None: - return self.__logger.TryWrite(*args, **kwargs) + if self._Logger is not None: + return self._Logger.TryWrite(*args, **kwargs) return False - def _LogFatal(self, *args, **kwargs): - if self.__logger is not None: - return self.__logger.WriteFatal(*args, **kwargs) + def LogFatal(self, *args, **kwargs): + if self._Logger is not None: + return self._Logger.WriteFatal(*args, **kwargs) return False - def _LogError(self, *args, **kwargs): - if self.__logger is not None: - return self.__logger.WriteError(*args, **kwargs) + def LogError(self, *args, **kwargs): + if self._Logger is not None: + return self._Logger.WriteError(*args, **kwargs) return False - - def _LogWarning(self, *args, **kwargs): - if self.__logger is not None: - return self.__logger.WriteWarning(*args, **kwargs) + + def LogWarning(self, *args, **kwargs): + if self._Logger is not None: + return self._Logger.WriteWarning(*args, **kwargs) return False - - def _LogInfo(self, *args, **kwargs): - if self.__logger is not None: - return self.__logger.WriteInfo(*args, **kwargs) + + def LogInfo(self, *args, **kwargs): + if self._Logger is not None: + return self._Logger.WriteInfo(*args, **kwargs) return False - - def _LogQuiet(self, *args, **kwargs): - if self.__logger is not None: - return self.__logger.WriteQuiet(*args, **kwargs) + + def LogQuiet(self, *args, **kwargs): + if self._Logger is not None: + return self._Logger.WriteQuiet(*args, **kwargs) return False - - def _LogNormal(self, *args, **kwargs): - if self.__logger is not None: - return self.__logger.WriteNormal(*args, **kwargs) + + def LogNormal(self, *args, **kwargs): + if self._Logger is not None: + return self._Logger.WriteNormal(*args, **kwargs) return False - - def _LogVerbose(self, *args, **kwargs): - if self.__logger is not None: - return self.__logger.WriteVerbose(*args, **kwargs) + + def LogVerbose(self, *args, **kwargs): + if self._Logger is not None: + return self._Logger.WriteVerbose(*args, **kwargs) + return False + + def LogDebug(self, *args, **kwargs): + if self._Logger is not None: + return self._Logger.WriteDebug(*args, **kwargs) return False - - def _LogDebug(self, *args, **kwargs): - if self.__logger is not None: - return self.__logger.WriteDebug(*args, **kwargs) + + def LogDryRun(self, *args, **kwargs): + if self._Logger is not None: + return self._Logger.WriteDryRun(*args, **kwargs) return False diff --git a/py/Base/Project.py b/py/Base/Project.py index b3b7ec7f..e1c4fdd7 100644 --- a/py/Base/Project.py +++ b/py/Base/Project.py @@ -1,13 +1,13 @@ # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2; replace-tabs off; indent-width 2; -# +# # ============================================================================== # Authors: Patrick Lehmann # Martin Zabel # # Python Module: TODO -# +# # Description: # ------------------------------------ # TODO: @@ -16,13 +16,13 @@ # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany # Chair for VLSI-Design, Diagnostics and Architecture -# +# # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at -# +# # http://www.apache.org/licenses/LICENSE-2.0 -# +# # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -63,23 +63,26 @@ class FileTypes(Flags): SettingsFile = () QuartusSettingsFile = () + __FILE_EXTENSION_MAPPING__ = { + Text: "txt", + FileListFile: "files", + RulesFile: "rules", + VHDLSourceFile: "vhdl", + VerilogSourceFile: "v", + PythonSourceFile: "py", + CocotbSourceFile: "py", + UcfConstraintFile: "ucf", + XdcConstraintFile: "xdc", + SdcConstraintFile: "sdc", + LdcConstraintFile: "ldc", + QuartusSettingsFile: "qsf" + } + def Extension(self): - if (self == FileTypes.Unknown): raise CommonException("Unknown file type.") - elif (self == FileTypes.Any): raise CommonException("Generic file type.") - elif (self == FileTypes.Text): return "txt" - elif (self == FileTypes.FileListFile): return "files" - elif (self == FileTypes.SourceFile): raise CommonException("Generic file type.") - elif (self == FileTypes.VHDLSourceFile): return "vhdl" - elif (self == FileTypes.VerilogSourceFile): return "v" - elif (self == FileTypes.CocotbSourceFile): return "py" - elif (self == FileTypes.ConstraintFile): raise CommonException("Generic file type.") - elif (self == FileTypes.UcfConstraintFile): return "ucf" - elif (self == FileTypes.XdcConstraintFile): return "xdc" - elif (self == FileTypes.SdcConstraintFile): return "sdc" - elif (self == FileTypes.LdcConstraintFile): return "ldc" - elif (self == FileTypes.SettingsFile): raise CommonException("Generic file type.") - elif (self == FileTypes.QuartusSettingsFile): return "qsf" - else: raise CommonException("This is not an enum member.") + try: + return self.__FILE_EXTENSION_MAPPING__[self] + except KeyError: + raise CommonException("Generic file type.") def __str__(self): return self.name @@ -93,7 +96,7 @@ class Environment(Enum): @unique class ToolChain(Enum): - Any = 0 + Any = 0 Aldec_ActiveHDL = 10 Altera_Quartus = 20 Altera_ModelSim = 21 @@ -107,58 +110,96 @@ class ToolChain(Enum): @unique -class Tool(Enum): +class Tool(Enum): # ID Short Name Long Name Any = 0 - Aldec_aSim = 10 - Altera_Quartus_Map = 20 - Cocotb_QuestaSim = 30 - GHDL = 40 - GTKwave = 41 - Lattice_LSE = 50 - Mentor_vSim = 60 - Xilinx_iSim = 70 - Xilinx_XST = 71 - Xilinx_CoreGen = 72 - Xilinx_xSim = 80 - Xilinx_Synth = 81 + Aldec_aSim = ("ASIM", "Aldec Active-HDL", "Aldec Active-HDL") + Altera_Quartus_Map = ("QMAP", "Quartus Map", "Altera Quartus Map (quartus_map)") + Cocotb_QuestaSim = ("COCO", "Cocotb", "Coroutine Cosimulation Testbench (Cocotb)") + GHDL = ("GHDL", "GHDL", "GHDL") + GTKwave = ("GTKW", "GTKWave", "GTKWave") + Lattice_LSE = ("LSE", "Lattice LSE", "Lattice Synthesis Engine (LSE)") + Mentor_vSim = ("VSIM", "Mentor QuestaSim", "Mentor Graphics QuestaSim (vSim)") + Xilinx_iSim = ("XSIM", "Xilinx iSim", "Xilinx ISE Simulator (iSim)") + Xilinx_XST = ("XST", "Xilinx XST", "Xilinx Synthesis Tool (XST)") + Xilinx_CoreGen = ("CG", "Xilinx CoreGen", "Xilinx Core Generator Tool (CoreGen)") + Xilinx_xSim = ("XSIM", "Xilinx xSim", "Xilinx Vivado Simulator (xSim)") + Xilinx_Synth = ("VIVADO", "Xilinx Vivado Synthesis", "Xilinx Vivado Synthesis (synth)") + Xilinx_IPCatalog = ("XCI", "Xilinx Vivado IP Catalog", "Xilinx Vivado IP Catalog") + + def __init__(self, *_): + """Patch the embedded MAP dictionary""" + for k, v in self.__class__.__TOOL_ID_MAPPINGS__.items(): + if ((not isinstance(v, self.__class__)) and (v == self.value)): + self.__class__.__TOOL_ID_MAPPINGS__[k] = self + + __TOOL_ID_MAPPINGS__ = { + "QMAP": Altera_Quartus_Map, + "LSE": Lattice_LSE, + "CG": Xilinx_CoreGen, + "XST": Xilinx_XST, + "XCI": Xilinx_IPCatalog + } + + @classmethod + def Parse(cls, value): + try: + return cls.__TOOL_ID_MAPPINGS__[value] + except KeyError: + ValueError("Value '{0!s}' cannot be parsed to member of {1}.".format(value, cls.__name__)) + + @property + def ID(self): return self.value[0] + @property + def ShortName(self): return self.value[1] + @property + def LongName(self): return self.value[2] + + def __str__(self): return self.ShortName + def __repr__(self): return self.ID class VHDLVersion(Enum): Any = 0 - VHDL87 = 1987 - VHDL93 = 1993 - VHDL02 = 2002 - VHDL08 = 2008 - VHDL1987 = 1987 - VHDL1993 = 1993 + VHDL87 = 87 + VHDL93 = 93 VHDL2002 = 2002 VHDL2008 = 2008 + def __init__(self, *_): + """Patch the embedded MAP dictionary""" + for k, v in self.__class__.__VHDL_VERSION_MAPPINGS__.items(): + if ((not isinstance(v, self.__class__)) and (v == self.value)): + self.__class__.__VHDL_VERSION_MAPPINGS__[k] = self + + __VHDL_VERSION_MAPPINGS__ = { + 87: VHDL87, + 93: VHDL93, + 2: VHDL2002, + 8: VHDL2008, + 1987: VHDL87, + 1993: VHDL93, + 2002: VHDL2002, + 2008: VHDL2008, + "87": VHDL87, + "93": VHDL93, + "02": VHDL2002, + "08": VHDL2008, + "1987": VHDL87, + "1993": VHDL93, + "2002": VHDL2002, + "2008": VHDL2008 + } + @classmethod - def parse(cls, value): - if isinstance(value, int): - if (value == 87): return cls.VHDL87 - elif (value == 93): return cls.VHDL93 - elif (value == 2): return cls.VHDL02 - elif (value == 8): return cls.VHDL08 - elif (value == 1987): return cls.VHDL87 - elif (value == 1993): return cls.VHDL93 - elif (value == 2002): return cls.VHDL02 - elif (value == 2008): return cls.VHDL08 - elif isinstance(value, str): - if (value == "87"): return cls.VHDL87 - elif (value == "93"): return cls.VHDL93 - elif (value == "02"): return cls.VHDL02 - elif (value == "08"): return cls.VHDL08 - elif (value == "1987"): return cls.VHDL87 - elif (value == "1993"): return cls.VHDL93 - elif (value == "2002"): return cls.VHDL02 - elif (value == "2008"): return cls.VHDL08 - raise ValueError("'{0!s}' is not a member of {1}.".format(value, cls.__name__)) - - def __lt__(self, other): return self.value < other.value + def Parse(cls, value): + try: + return cls.__VHDL_VERSION_MAPPINGS__[value] + except KeyError: + ValueError("Value '{0!s}' cannot be parsed to member of {1}.".format(value, cls.__name__)) + + def __lt__(self, other): return self.value < other.value def __le__(self, other): return self.value <= other.value - def __gt__(self, other): return self.value > other.value + def __gt__(self, other): return self.value > other.value def __ge__(self, other): return self.value >= other.value def __ne__(self, other): return self.value != other.value def __eq__(self, other): @@ -168,13 +209,10 @@ def __eq__(self, other): return (self.value == other.value) def __str__(self): - return "VHDL'" + self.__repr__() + return "VHDL'" + str(self.value)[-2:] def __repr__(self): - if (self == VHDLVersion.VHDL87): return "87" - elif (self == VHDLVersion.VHDL93): return "93" - elif (self == VHDLVersion.VHDL02): return "02" - elif (self == VHDLVersion.VHDL08): return "08" + return str(self.value) class Project: @@ -185,68 +223,68 @@ def __init__(self, name): self._defaultFileSet = None self._vhdlLibraries = {} self._externalVHDLLibraries = [] - + self._board = None self._device = None self._environment = Environment.Any self._toolChain = ToolChain.Any self._tool = Tool.Any self._vhdlVersion = VHDLVersion.Any - + self.CreateFileSet("default", setDefault=True) - + @property def Name(self): return self._name - + @property def RootDirectory(self): return self._rootDirectory - + @RootDirectory.setter def RootDirectory(self, value): if isinstance(value, str): value = Path(value) self._rootDirectory = value - + @property def Board(self): return self._board - + @Board.setter def Board(self, value): if isinstance(value, str): value = Board(value) elif (not isinstance(value, Board)): raise ValueError("Parameter 'board' is not of type Board.") - self._board = value + self._board = value self._device = value.Device - + @property def Device(self): return self._device - + @Device.setter def Device(self, value): if isinstance(value, (str, Device)): board = Board("custom", value) else: raise ValueError("Parameter 'device' is not of type str or Device.") - self._board = board + self._board = board self._device = board.Device - + @property def Environment(self): return self._environment @Environment.setter def Environment(self, value): self._environment = value - + @property def ToolChain(self): return self._toolChain @ToolChain.setter def ToolChain(self, value): self._toolChain = value - + @property def Tool(self): return self._tool @Tool.setter def Tool(self, value): self._tool = value - + @property def VHDLVersion(self): return self._vhdlVersion @VHDLVersion.setter @@ -258,7 +296,7 @@ def CreateFileSet(self, name, setDefault=True): self._fileSets[name] = fs if (setDefault is True): self._defaultFileSet = fs - + def AddFileSet(self, fileSet): if (not isinstance(fileSet, FileSet)): raise ValueError("Parameter 'fileSet' is not of type Base.Project.FileSet.") @@ -268,17 +306,17 @@ def AddFileSet(self, fileSet): raise CommonException("Project already contains a fileset named '{0}'.".format(fileSet.Name)) fileSet.Project = self self._fileSets[fileSet.Name] = fileSet - + # TODO: assign all files to this project - + @property def FileSets(self): return [i for i in self._fileSets.values()] - + @property def DefaultFileSet(self): return self._defaultFileSet - + @DefaultFileSet.setter def DefaultFileSet(self, value): if isinstance(value, str): @@ -288,7 +326,7 @@ def DefaultFileSet(self, value): if (value not in self.FileSets): raise CommonException("Fileset '{0}' is not associated to this project.".format(value)) self._defaultFileSet = value else: raise ValueError("Unsupported parameter type for 'value'.") - + def AddFile(self, file, fileSet = None): # print("Project.AddFile: file={0}".format(file)) if (not isinstance(file, File)): raise ValueError("Parameter 'file' is not of type Base.Project.File.") @@ -302,7 +340,7 @@ def AddFile(self, file, fileSet = None): else: raise ValueError("Unsupported parameter type for 'fileSet'.") fileSet.AddFile(file) return file - + def AddSourceFile(self, file, fileSet = None): # print("Project.AddSourceFile: file={0}".format(file)) if (not isinstance(file, SourceFile)): raise ValueError("Parameter 'file' is not of type Base.Project.SourceFile.") @@ -316,7 +354,7 @@ def AddSourceFile(self, file, fileSet = None): else: raise ValueError("Unsupported parameter type for 'fileSet'.") fileSet.AddSourceFile(file) return file - + def Files(self, fileType=FileTypes.Any, fileSet=None): if (fileSet is None): if (self._defaultFileSet is None): raise CommonException("Neither the parameter 'fileSet' set nor a default file set is given.") @@ -325,7 +363,7 @@ def Files(self, fileType=FileTypes.Any, fileSet=None): for file in fileSet.Files: if (file.FileType in fileType): yield file - + def ExtractVHDLLibrariesFromVHDLSourceFiles(self): for file in self.Files(fileType=FileTypes.VHDLSourceFile): libraryName = file.LibraryName.lower() @@ -335,7 +373,7 @@ def ExtractVHDLLibrariesFromVHDLSourceFiles(self): library = self._vhdlLibraries[libraryName] library.AddFile(file) file.VHDLLibrary = library - + @property def VHDLLibraries(self): return self._vhdlLibraries.values() @property @@ -343,18 +381,18 @@ def ExternalVHDLLibraries(self): return self._externalVHDLLibraries def AddExternalVHDLLibraries(self, library): self._externalVHDLLibraries.append(library) - + def GetVariables(self): result = { - "ProjectName" : self._name, - "RootDirectory" : str(self._rootDirectory), - "Environment" : self._environment.name, - "ToolChain" : self._toolChain.name, - "Tool" : self._tool.name, - "VHDL" : self._vhdlVersion.value + "ProjectName": self._name, + "RootDirectory": str(self._rootDirectory), + "Environment": self._environment.name, + "ToolChain": self._toolChain.name, + "Tool": self._tool.name, + "VHDLVersion": self._vhdlVersion.value } return merge(result, self._board.GetVariables(), self._device.GetVariables()) - + def pprint(self, indent=0): _indent = " " * indent buffer = "Project: {0}\n".format(self.Name) @@ -374,7 +412,7 @@ def pprint(self, indent=0): for lib in self._externalVHDLLibraries: buffer += "\n{0}| o-{1} -> {2}".format(_indent, lib.Name, lib.Path) return buffer - + def __str__(self): return self._name @@ -382,26 +420,26 @@ class FileSet: def __init__(self, name, project = None): # print("FileSet.__init__: name={0} project={0}".format(name, project)) self._name = name - self._project = project - self._files = [] - + self._project = project + self._files = [] + @property def Name(self): return self._name - + @property def Project(self): return self._project - + @Project.setter def Project(self, value): if not isinstance(value, Project): raise ValueError("Parameter 'value' is not of type Base.Project.Project.") self._project = value - + @property def Files(self): return self._files - + def AddFile(self, file): # print("FileSet.AddFile: file={0}".format(file)) if isinstance(file, str): @@ -443,26 +481,26 @@ def __str__(self): class VHDLLibrary: def __init__(self, name, project = None): self._name = name - self._project = project - self._files = [] - + self._project = project + self._files = [] + @property def Name(self): return self._name - + @property def Project(self): return self._project - + @Project.setter def Project(self, value): if not isinstance(value, Project): raise ValueError("Parameter 'value' is not of type Base.Project.Project.") self._project = value - + @property def Files(self): return self._files - + def AddFile(self, file): if (not isinstance(file, VHDLSourceFile)): raise ValueError("Unsupported parameter type for 'file'.") file.VHDLLibrary = self @@ -471,7 +509,7 @@ def AddFile(self, file): if (f.FileName == file.FileName): break else: self._files.append(file) - + def __str__(self): return self._name @@ -482,53 +520,53 @@ class File: def __init__(self, file, project = None, fileSet = None): self._handle = None self._content = None - + if isinstance(file, str): file = Path(file) self._file = file - self._project = project - self._fileSet = fileSet - + self._project = project + self._fileSet = fileSet + @property def Project(self): return self._project - + @Project.setter def Project(self, value): if not isinstance(value, Project): raise ValueError("Parameter 'value' is not of type Base.Project.Project.") # print("File.Project(setter): value={0}".format(value)) self._project = value - + @property def FileSet(self): return self._fileSet - + @FileSet.setter def FileSet(self, value): if (value is None): raise ValueError("'value' is None") # print("File.FileSet(setter): value={0}".format(value)) - self._fileSet = value - self._project = value.Project + self._fileSet = value + self._project = value.Project @property def FileType(self): return self._FileType - + @property def FileName(self): return str(self._file) - + @property def Path(self): return self._file - + def Open(self): if (not self._file.exists()): raise CommonException("File '{0!s}' not found.".format(self._file)) from FileNotFoundError(str(self._file)) try: self._handle = self._file.open('r') except Exception as ex: raise CommonException("Error while opening file '{0!s}'.".format(self._file)) from ex - + def ReadFile(self): if self._handle is None: self.Open() @@ -536,11 +574,11 @@ def ReadFile(self): self._content = self._handle.read() except Exception as ex: raise CommonException("Error while reading file '{0!s}'.".format(self._file)) from ex - + # interface method for FilesParserMixIn def _ReadContent(self): self.ReadFile() - + def __str__(self): return str(self._file) @@ -580,7 +618,7 @@ def __init__(self, file, vhdlLibraryName, project = None, fileSet = None): def Parse(self): self._Parse()# only available via late binding - + def __str__(self): return "VHDL file: '{0!s}".format(self._file) diff --git a/py/Base/Shared.py b/py/Base/Shared.py new file mode 100644 index 00000000..eaf1f65d --- /dev/null +++ b/py/Base/Shared.py @@ -0,0 +1,190 @@ +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# +# ============================================================================== +# Authors: Patrick Lehmann +# +# Python Class: Base class for *** +# +# Description: +# ------------------------------------ +# TODO: +# - +# - +# +# License: +# ============================================================================== +# Copyright 2007-2016 Technische Universitaet Dresden - Germany +# Chair for VLSI-Design, Diagnostics and Architecture +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================== +# +# entry point +if __name__ != "__main__": + # place library initialization code here + pass +else: + from lib.Functions import Exit + Exit.printThisIsNoExecutableFile("The PoC-Library - Python Class PoCCompiler") + + +# load dependencies +import shutil +from datetime import datetime +from os import chdir + +from lib.Parser import ParserException +from Base.Exceptions import CommonException, SkipableCommonException +from Base.Logging import ILogable +from Base.Project import ToolChain, Tool, VHDLVersion, Environment +from PoC.Solution import VirtualProject, FileListFile + + +# local helper function +def to_time(seconds): + """Convert n seconds to a str with pattern {min}:{sec:02}.""" + minutes = int(seconds / 60) + seconds = seconds - (minutes * 60) + return "{min}:{sec:02}".format(min=minutes, sec=seconds) + + +class Shared(ILogable): + _ENVIRONMENT = Environment.Any + _TOOL_CHAIN = ToolChain.Any + _TOOL = Tool.Any + _vhdlVersion = VHDLVersion.VHDL2008 + + class __Directories__: + Working = None + PoCRoot = None + + def __init__(self, host, dryRun): + if isinstance(host, ILogable): + ILogable.__init__(self, host.Logger) + else: + ILogable.__init__(self, None) + + self._host = host + self._dryRun = dryRun + + self._pocProject = None + self._directories = self.__Directories__() + + self._testSuite = None + self._startAt = datetime.now() + self._endAt = None + self._lastEvent = self._startAt + self._prepareTime = None + + # class properties + # ============================================================================ + @property + def Host(self): return self._host + @property + def DryRun(self): return self._dryRun + @property + def VHDLVersion(self): return self._vhdlVersion + @property + def PoCProject(self): return self._pocProject + @property + def Directories(self): return self._directories + + def _GetTimeDeltaSinceLastEvent(self): + now = datetime.now() + result = now - self._lastEvent + self._lastEvent = now + return result + + def _Prepare(self): + self.LogNormal("Preparing {0}.".format(self._TOOL.LongName)) + + def _PrepareEnvironment(self): + # create fresh temporary directory + self.LogVerbose("Creating fresh temporary directory.") + if (self.Directories.Working.exists()): + self.LogDebug("Purging temporary directory: {0!s}".format(self.Directories.Working)) + for item in self.Directories.Working.iterdir(): + try: + if item.is_dir(): + shutil.rmtree(str(item)) + elif item.is_file(): + item.unlink() + except OSError as ex: + raise CommonException("Error while deleting '{0!s}'.".format(item)) from ex + else: + self.LogDebug("Creating temporary directory: {0!s}".format(self.Directories.Working)) + try: + self.Directories.Working.mkdir(parents=True) + except OSError as ex: + raise CommonException("Error while creating '{0!s}'.".format(self.Directories.Working)) from ex + + # change working directory to temporary path + self.LogVerbose("Changing working directory to temporary directory.") + self.LogDebug("cd \"{0!s}\"".format(self.Directories.Working)) + try: + chdir(str(self.Directories.Working)) + except OSError as ex: + raise CommonException("Error while changing to '{0!s}'.".format(self.Directories.Working)) from ex + + def _CreatePoCProject(self, projectName, board): + # create a PoCProject and read all needed files + self.LogVerbose("Creating PoC project '{0}'".format(projectName)) + pocProject = VirtualProject(projectName) + + # configure the project + pocProject.RootDirectory = self.Host.Directories.Root + pocProject.Environment = self._ENVIRONMENT + pocProject.ToolChain = self._TOOL_CHAIN + pocProject.Tool = self._TOOL + pocProject.VHDLVersion = self._vhdlVersion + pocProject.Board = board + + self._pocProject = pocProject + + def _AddFileListFile(self, fileListFilePath): + self.LogVerbose("Reading filelist '{0!s}'".format(fileListFilePath)) + # add the *.files file, parse and evaluate it + # if (not fileListFilePath.exists()): raise SimulatorException("Files file '{0!s}' not found.".format(fileListFilePath)) from FileNotFoundError(str(fileListFilePath)) + + try: + fileListFile = self._pocProject.AddFile(FileListFile(fileListFilePath)) + fileListFile.Parse(self._host) + fileListFile.CopyFilesToFileSet() + fileListFile.CopyExternalLibraries() + self._pocProject.ExtractVHDLLibrariesFromVHDLSourceFiles() + except (ParserException, CommonException) as ex: + raise SkipableCommonException("Error while parsing '{0!s}'.".format(fileListFilePath)) from ex + + self.LogDebug("=" * 78) + self.LogDebug("Pretty printing the PoCProject...") + self.LogDebug(self._pocProject.pprint(2)) + self.LogDebug("=" * 78) + if (len(fileListFile.Warnings) > 0): + for warn in fileListFile.Warnings: + self.LogWarning(warn) + raise SkipableCommonException("Found critical warnings while parsing '{0!s}'".format(fileListFilePath)) + + def _GetHDLParameters(self, configSectionName): + """Parse option 'HDLParameters' for Verilog Parameters / VHDL Generics.""" + result = {} + hdlParameters = self.Host.PoCConfig[configSectionName]["HDLParameters"] + if (len(hdlParameters) > 0): + for keyValuePair in hdlParameters.split(";"): + try: + key,value = keyValuePair.split("=") + except ValueError as ex: + raise CommonException("Syntax error in option 'HDLParameters' within section {section}.".format(section=configSectionName)) + result[key.strip()] = value.strip() + return result diff --git a/py/Base/Simulator.py b/py/Base/Simulator.py index a3d6ec26..dc50ef81 100644 --- a/py/Base/Simulator.py +++ b/py/Base/Simulator.py @@ -1,30 +1,30 @@ # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2; replace-tabs off; indent-width 2; -# +# # ============================================================================== # Authors: Patrick Lehmann # Martin Zabel -# +# # Python Class: TODO -# +# # Description: # ------------------------------------ # TODO: -# - -# - +# - +# - # # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany # Chair for VLSI-Design, Diagnostics and Architecture -# +# # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at -# +# # http://www.apache.org/licenses/LICENSE-2.0 -# +# # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -42,19 +42,16 @@ # load dependencies -import shutil -from datetime import datetime -from enum import Enum, unique -from os import chdir +from datetime import datetime +from enum import Enum, unique -from lib.Functions import Init -from lib.Parser import ParserException -from Base.Exceptions import ExceptionBase, CommonException -from Base.Logging import ILogable, LogEntry -from Base.Project import Environment, ToolChain, Tool, VHDLVersion -from PoC.Entity import WildCard -from PoC.Solution import VirtualProject, FileListFile -from PoC.TestCase import TestSuite, TestCase, Status +from lib.Functions import Init +from Base.Exceptions import ExceptionBase, SkipableException +from Base.Logging import LogEntry +from Base.Project import Environment, VHDLVersion +from Base.Shared import Shared, to_time +from PoC.Entity import WildCard +from PoC.TestCase import TestCase, SimulationStatus, TestSuite VHDL_TESTBENCH_LIBRARY_NAME = "test" @@ -63,7 +60,7 @@ class SimulatorException(ExceptionBase): pass -class SkipableSimulatorException(SimulatorException): +class SkipableSimulatorException(SimulatorException, SkipableException): pass @@ -84,40 +81,19 @@ class SimulationResult(Enum): NoAsserts = 3 Passed = 4 -# local helper function -def to_time(seconds): - """Convert n seconds to a str with pattern {min}:{sec:02}.""" - minutes = int(seconds / 60) - seconds = seconds - (minutes * 60) - return "{min}:{sec:02}".format(min=minutes, sec=seconds) -class Simulator(ILogable): - _TOOL_CHAIN = ToolChain.Any - _TOOL = Tool.Any +class Simulator(Shared): + _ENVIRONMENT = Environment.Simulation + _vhdlVersion = VHDLVersion.VHDL2008 - class __Directories__: - Working = None - PoCRoot = None + class __Directories__(Shared.__Directories__): PreCompiled = None - def __init__(self, host): - if isinstance(host, ILogable): - ILogable.__init__(self, host.Logger) - else: - ILogable.__init__(self, None) - - self.__host = host - - self._vhdlVersion = VHDLVersion.VHDL2008 - self._directories = self.__Directories__() - self._pocProject = None - self._testSuite = TestSuite() # TODO: This includes not the read ini files phases ... + def __init__(self, host, dryRun): + super().__init__(host, dryRun) + self._testSuite = TestSuite() # TODO: This includes not the read ini files phases ... self._state = SimulationState.Prepare - self._startAt = datetime.now() - self._endAt = None - self._lastEvent = self._startAt - self._prepareTime = None self._analyzeTime = None self._elaborationTime = None self._simulationTime = None @@ -126,58 +102,31 @@ def __init__(self, host): # class properties # ============================================================================ @property - def Host(self): return self.__host - @property - def Directories(self): return self._directories - @property - def PoCProject(self): return self._pocProject - @property def TestSuite(self): return self._testSuite - def _GetTimeDeltaSinceLastEvent(self): - now = datetime.now() - result = now - self._lastEvent - self._lastEvent = now - return result + def _PrepareSimulator(self): + self._Prepare() def _PrepareSimulationEnvironment(self): - self._LogNormal("Preparing simulation environment...") - - # create fresh temporary directory - self._LogVerbose("Creating fresh temporary directory for simulator files.") - self._LogDebug("Temporary directory: {0!s}".format(self.Directories.Working)) - if (self.Directories.Working.exists()): - try: - shutil.rmtree(str(self.Directories.Working)) - except OSError as ex: - raise SimulatorException("Error while deleting '{0!s}'.".format(self.Directories.Working)) from ex - try: - self.Directories.Working.mkdir(parents=True) - except OSError as ex: - raise SimulatorException("Error while creating '{0!s}'.".format(self.Directories.Working)) from ex - - # change working directory to temporary path - self._LogVerbose("Changing working directory to temporary directory.") - self._LogDebug("cd \"{0!s}\"".format(self.Directories.Working)) - try: - chdir(str(self.Directories.Working)) - except OSError as ex: - raise SimulatorException("Error while changing to '{0!s}'.".format(self.Directories.Working)) from ex + self.LogNormal("Preparing simulation environment...") + self._PrepareEnvironment() def RunAll(self, fqnList, *args, **kwargs): """Run a list of testbenches. Expand wildcards to all selected testbenches.""" self._testSuite.StartTimer() + self.Logger.BaseIndent = int(len(fqnList) > 1) try: for fqn in fqnList: entity = fqn.Entity if (isinstance(entity, WildCard)): + self.Logger.BaseIndent = 1 for testbench in entity.GetVHDLTestbenches(): self.TryRun(testbench, *args, **kwargs) else: testbench = entity.VHDLTestbench self.TryRun(testbench, *args, **kwargs) except KeyboardInterrupt: - self._LogError("Received a keyboard interrupt.") + self.LogError("Received a keyboard interrupt.") finally: self._testSuite.StopTimer() @@ -188,11 +137,11 @@ def RunAll(self, fqnList, *args, **kwargs): def TryRun(self, testbench, *args, **kwargs): """Try to run a testbench. Skip skipable exceptions by printing the error and its cause.""" __SIMULATION_STATE_TO_TESTCASE_STATUS__ = { - SimulationState.Prepare: Status.InternalError, - SimulationState.Analyze: Status.AnalyzeError, - SimulationState.Elaborate: Status.ElaborationError, - SimulationState.Optimize: Status.ElaborationError, - SimulationState.Simulate: Status.SimulationError + SimulationState.Prepare: SimulationStatus.InternalError, + SimulationState.Analyze: SimulationStatus.AnalyzeError, + SimulationState.Elaborate: SimulationStatus.ElaborationError, + SimulationState.Optimize: SimulationStatus.ElaborationError, + SimulationState.Simulate: SimulationStatus.SimulationError } testCase = TestCase(testbench) @@ -204,96 +153,58 @@ def TryRun(self, testbench, *args, **kwargs): except SkipableSimulatorException as ex: testCase.Status = __SIMULATION_STATE_TO_TESTCASE_STATUS__[self._state] - self._LogQuiet(" {RED}ERROR:{NOCOLOR} {ExMsg}".format(ExMsg=ex.message, **Init.Foreground)) + self.LogQuiet(" {RED}ERROR:{NOCOLOR} {ExMsg}".format(ExMsg=ex.message, **Init.Foreground)) cause = ex.__cause__ if (cause is not None): - self._LogQuiet(" {YELLOW}{ExType}:{NOCOLOR} {ExMsg!s}".format(ExType=cause.__class__.__name__, ExMsg=cause, **Init.Foreground)) + self.LogQuiet(" {YELLOW}{ExType}:{NOCOLOR} {ExMsg!s}".format(ExType=cause.__class__.__name__, ExMsg=cause, **Init.Foreground)) cause = cause.__cause__ if (cause is not None): - self._LogQuiet(" {YELLOW}{ExType}:{NOCOLOR} {ExMsg!s}".format(ExType=cause.__class__.__name__, ExMsg=cause, **Init.Foreground)) - self._LogQuiet(" {RED}[SKIPPED DUE TO ERRORS]{NOCOLOR}".format(**Init.Foreground)) + self.LogQuiet(" {YELLOW}{ExType}:{NOCOLOR} {ExMsg!s}".format(ExType=cause.__class__.__name__, ExMsg=cause, **Init.Foreground)) + self.LogQuiet(" {RED}[SKIPPED DUE TO ERRORS]{NOCOLOR}".format(**Init.Foreground)) except SimulatorException: testCase.Status = __SIMULATION_STATE_TO_TESTCASE_STATUS__[self._state] raise except ExceptionBase: - testCase.Status = Status.SystemError + testCase.Status = SimulationStatus.SystemError raise finally: testCase.StopTimer() def Run(self, testbench, board, vhdlVersion, vhdlGenerics=None, guiMode=False): """Write the Testbench message line, create a PoCProject and add the first *.files file to it.""" - self._LogQuiet("{CYAN}Testbench:{NOCOLOR} {0!s}".format(testbench.Parent, **Init.Foreground)) + self.LogQuiet("{CYAN}Testbench: {0!s}{NOCOLOR}".format(testbench.Parent, **Init.Foreground)) - self._vhdlVersion = vhdlVersion + self._vhdlVersion = vhdlVersion self._vhdlGenerics = vhdlGenerics # setup all needed paths to execute fuse - self._CreatePoCProject(testbench, board) + self._CreatePoCProject(testbench.ModuleName, board) self._AddFileListFile(testbench.FilesFile) self._prepareTime = self._GetTimeDeltaSinceLastEvent() - self._LogNormal("Running analysis for every vhdl file...") + self.LogNormal("Running analysis for every vhdl file...") self._state = SimulationState.Analyze self._RunAnalysis(testbench) self._analyzeTime = self._GetTimeDeltaSinceLastEvent() - self._LogNormal("Running elaboration...") + self.LogNormal("Running elaboration...") self._state = SimulationState.Elaborate self._RunElaboration(testbench) self._elaborationTime = self._GetTimeDeltaSinceLastEvent() - self._LogNormal("Running simulation...") + self.LogNormal("Running simulation...") self._state = SimulationState.Simulate self._RunSimulation(testbench) self._simulationTime = self._GetTimeDeltaSinceLastEvent() if (guiMode is True): - self._LogNormal("Executing waveform viewer...") + self.LogNormal("Executing waveform viewer...") self._state = SimulationState.View self._RunView(testbench) self._endAt = datetime.now() - def _CreatePoCProject(self, testbench, board): - # create a PoCProject and read all needed files - self._LogVerbose("Creating a PoC project '{0}'".format(testbench.ModuleName)) - pocProject = VirtualProject(testbench.ModuleName) - - # configure the project - pocProject.RootDirectory = self.Host.Directories.Root - pocProject.Environment = Environment.Simulation - pocProject.ToolChain = self._TOOL_CHAIN - pocProject.Tool = self._TOOL - pocProject.VHDLVersion = self._vhdlVersion - pocProject.Board = board - - self._pocProject = pocProject - - def _AddFileListFile(self, fileListFilePath): - self._LogVerbose("Reading filelist '{0!s}'".format(fileListFilePath)) - # add the *.files file, parse and evaluate it - # if (not fileListFilePath.exists()): raise SimulatorException("Files file '{0!s}' not found.".format(fileListFilePath)) from FileNotFoundError(str(fileListFilePath)) - - try: - fileListFile = self._pocProject.AddFile(FileListFile(fileListFilePath)) - fileListFile.Parse() - fileListFile.CopyFilesToFileSet() - fileListFile.CopyExternalLibraries() - self._pocProject.ExtractVHDLLibrariesFromVHDLSourceFiles() - except (ParserException, CommonException) as ex: - raise SkipableSimulatorException("Error while parsing '{0!s}'.".format(fileListFilePath)) from ex - - self._LogDebug("=" * 78) - self._LogDebug("Pretty printing the PoCProject...") - self._LogDebug(self._pocProject.pprint(2)) - self._LogDebug("=" * 78) - if (len(fileListFile.Warnings) > 0): - for warn in fileListFile.Warnings: - self._LogWarning(warn) - raise SkipableSimulatorException("Found critical warnings while parsing '{0!s}'".format(fileListFilePath)) - def _RunAnalysis(self, testbench): pass @@ -307,16 +218,16 @@ def _RunView(self, testbench): pass def PrintOverallSimulationReport(self): - self._LogQuiet("{HEADLINE}{line}{NOCOLOR}".format(line="=" * 80, **Init.Foreground)) - self._LogQuiet("{HEADLINE}{headline: ^80s}{NOCOLOR}".format(headline="Overall Simulation Report", **Init.Foreground)) - self._LogQuiet("{HEADLINE}{line}{NOCOLOR}".format(line="=" * 80, **Init.Foreground)) + self.LogQuiet("{HEADLINE}{line}{NOCOLOR}".format(line="=" * 80, **Init.Foreground)) + self.LogQuiet("{HEADLINE}{headline: ^80s}{NOCOLOR}".format(headline="Overall Simulation Report", **Init.Foreground)) + self.LogQuiet("{HEADLINE}{line}{NOCOLOR}".format(line="=" * 80, **Init.Foreground)) # table header - self._LogQuiet("{Name: <24} | {Duration: >5} | {Status: ^11}".format(Name="Name", Duration="Time", Status="Status")) - self._LogQuiet("-" * 80) + self.LogQuiet("{Name: <24} | {Duration: >5} | {Status: ^11}".format(Name="Name", Duration="Time", Status="Status")) + self.LogQuiet("-" * 80) self.PrintSimulationReportLine(self._testSuite, 0, 24) - self._LogQuiet("{HEADLINE}{line}{NOCOLOR}".format(line="=" * 80, **Init.Foreground)) - self._LogQuiet("Time: {time: >5} Count: {count: <3} Passed: {passed: <3} No Asserts: {noassert: <2} Failed: {failed: <2} Errors: {error: <2}".format( + self.LogQuiet("{HEADLINE}{line}{NOCOLOR}".format(line="=" * 80, **Init.Foreground)) + self.LogQuiet("Time: {time: >5} Count: {count: <3} Passed: {passed: <3} No Asserts: {noassert: <2} Failed: {failed: <2} Errors: {error: <2}".format( time=to_time(self._testSuite.OverallRunTime), count=self._testSuite.Count, passed=self._testSuite.PassedCount, @@ -324,42 +235,42 @@ def PrintOverallSimulationReport(self): failed=self._testSuite.FailedCount, error=self._testSuite.ErrorCount )) - self._LogQuiet("{HEADLINE}{line}{NOCOLOR}".format(line="=" * 80, **Init.Foreground)) + self.LogQuiet("{HEADLINE}{line}{NOCOLOR}".format(line="=" * 80, **Init.Foreground)) __SIMULATION_REPORT_COLOR_TABLE__ = { - Status.Unknown: "RED", - Status.InternalError: "DARK_RED", - Status.SystemError: "DARK_RED", - Status.AnalyzeError: "DARK_RED", - Status.ElaborationError: "DARK_RED", - Status.SimulationError: "RED", - Status.SimulationFailed: "RED", - Status.SimulationNoAsserts: "YELLOW", - Status.SimulationSuccess: "GREEN" + SimulationStatus.Unknown: "RED", + SimulationStatus.InternalError: "DARK_RED", + SimulationStatus.SystemError: "DARK_RED", + SimulationStatus.AnalyzeError: "DARK_RED", + SimulationStatus.ElaborationError: "DARK_RED", + SimulationStatus.SimulationError: "RED", + SimulationStatus.SimulationFailed: "RED", + SimulationStatus.SimulationNoAsserts: "YELLOW", + SimulationStatus.SimulationSuccess: "GREEN" } __SIMULATION_REPORT_STATUS_TEXT_TABLE__ = { - Status.Unknown: "-- ?? --", - Status.InternalError: "INT. ERROR", - Status.SystemError: "SYS. ERROR", - Status.AnalyzeError: "ANA. ERROR", - Status.ElaborationError: "ELAB. ERROR", - Status.SimulationError: "SIM. ERROR", - Status.SimulationFailed: "FAILED", - Status.SimulationNoAsserts: "NO ASSERTS", - Status.SimulationSuccess: "PASSED" + SimulationStatus.Unknown: "-- ?? --", + SimulationStatus.InternalError: "INT. ERROR", + SimulationStatus.SystemError: "SYS. ERROR", + SimulationStatus.AnalyzeError: "ANA. ERROR", + SimulationStatus.ElaborationError: "ELAB. ERROR", + SimulationStatus.SimulationError: "SIM. ERROR", + SimulationStatus.SimulationFailed: "FAILED", + SimulationStatus.SimulationNoAsserts: "NO ASSERTS", + SimulationStatus.SimulationSuccess: "PASSED" } def PrintSimulationReportLine(self, testObject, indent, nameColumnWidth): _indent = " " * indent - for group in testObject.TestGroups.values(): + for group in testObject.Groups.values(): pattern = "{indent}{{groupName: <{nameColumnWidth}}} | | ".format(indent=_indent, nameColumnWidth=nameColumnWidth) - self._LogQuiet(pattern.format(groupName=group.Name)) + self.LogQuiet(pattern.format(groupName=group.Name)) self.PrintSimulationReportLine(group, indent + 1, nameColumnWidth - 2) for testCase in testObject.TestCases.values(): pattern = "{indent}{{testcaseName: <{nameColumnWidth}}} | {{duration: >5}} | {{{color}}}{{status: ^11}}{{NOCOLOR}}".format( indent=_indent, nameColumnWidth=nameColumnWidth, color=self.__SIMULATION_REPORT_COLOR_TABLE__[testCase.Status]) - self._LogQuiet(pattern.format(testcaseName=testCase.Name, duration=to_time(testCase.OverallRunTime), + self.LogQuiet(pattern.format(testcaseName=testCase.Name, duration=to_time(testCase.OverallRunTime), status=self.__SIMULATION_REPORT_STATUS_TEXT_TABLE__[testCase.Status], **Init.Foreground)) diff --git a/py/Base/__init__.py b/py/Base/__init__.py index e8757c4c..72e3442d 100644 --- a/py/Base/__init__.py +++ b/py/Base/__init__.py @@ -1,28 +1,28 @@ # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2; replace-tabs off; indent-width 2; -# +# # ============================================================================== # Authors: Patrick Lehmann -# +# # Python Sub Module: Saves The PoC-Library configuration as python source code. -# +# # Description: # ------------------------------------ # TODO: -# +# # # License: # ============================================================================== # Copyright 2007-2015 Technische Universitaet Dresden - Germany # Chair for VLSI-Design, Diagnostics and Architecture -# +# # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at -# +# # http://www.apache.org/licenses/LICENSE-2.0 -# +# # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. diff --git a/py/Compiler/ISECompiler.py b/py/Compiler/ISECompiler.py new file mode 100644 index 00000000..eb6be960 --- /dev/null +++ b/py/Compiler/ISECompiler.py @@ -0,0 +1,88 @@ +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# +# ============================================================================== +# Authors: Patrick Lehmann +# +# Python Class: This ISECompiler compiles any IPCores for the ISE tool chain +# +# Description: +# ------------------------------------ +# TODO: +# - +# - +# +# License: +# ============================================================================== +# Copyright 2007-2016 Technische Universitaet Dresden - Germany +# Chair for VLSI-Design, Diagnostics and Architecture +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================== +# +# entry point +if __name__ != "__main__": + # place library initialization code here + pass +else: + from lib.Functions import Exit + Exit.printThisIsNoExecutableFile("The PoC-Library - Python Module Compiler.XCOCompiler") + + +# load dependencies +from Base.Project import ToolChain, Tool +from Base.Compiler import Compiler as BaseCompiler +from PoC.Entity import WildCard, FQN, EntityTypes +from Compiler.XCOCompiler import Compiler as XCOCompiler +from Compiler.XSTCompiler import Compiler as XSTCompiler + + +class Compiler(BaseCompiler): + _TOOL_CHAIN = ToolChain.Xilinx_ISE + _TOOL = Tool.Any + + def __init__(self, host, dryRun, noCleanUp): + super().__init__(host, dryRun, noCleanUp) + + self._PrepareCompiler() + + def _PrepareCompiler(self): + self.LogVerbose("Preparing Meta-Compiler for the Xilinx ISE tool chain.") + + def RunAll(self, fqnList, *args, **kwargs): + for fqn in fqnList: + entity = fqn.Entity + if (isinstance(entity, WildCard)): + for ent in entity.GetEntities(): + self.Run(ent, args, kwargs) + else: + self.Run(entity, args, kwargs) + + def Run(self, entity, args, kwargs): + self.LogVerbose("Checking '{0!s}' for dependencies...".format(entity)) + dependencies = [] + for dependency in entity.Dependencies: + toolName, entityName = dependency.split(":") + dependencyFQN = FQN(self.Host, entityName, defaultLibrary="PoC", defaultType=EntityTypes.NetList) + tool = Tool.Parse(toolName) + dependencies.append((tool, dependencyFQN)) + self.LogVerbose(" IP core: {1!s} compile with {0!s}".format(dependencyFQN, tool)) + + for tool,fqn in dependencies: + if (tool is Tool.Xilinx_CoreGen): + compiler = XCOCompiler(self.Host, self.DryRun, self.NoCleanUp) + compiler.RunAll([fqn], *args, **kwargs) + elif (tool is Tool.Xilinx_XST): + compiler = XSTCompiler(self.Host, self.DryRun, self.NoCleanUp) + compiler.RunAll([fqn], *args, **kwargs) diff --git a/py/Compiler/LSECompiler.py b/py/Compiler/LSECompiler.py index 36929d1a..a3cd3e3b 100644 --- a/py/Compiler/LSECompiler.py +++ b/py/Compiler/LSECompiler.py @@ -1,30 +1,30 @@ # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2; replace-tabs off; indent-width 2; -# +# # ============================================================================== # Authors: Patrick Lehmann # Martin Zabel -# -# Python Class: This PoCXCOCompiler compiles xco IPCores to netlists -# +# +# Python Class: This PoCXCOCompiler compiles xco IPCores to netlists +# # Description: # ------------------------------------ # TODO: -# - -# - +# - +# - # # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany # Chair for VLSI-Design, Diagnostics and Architecture -# +# # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at -# +# # http://www.apache.org/licenses/LICENSE-2.0 -# +# # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -33,9 +33,6 @@ # ============================================================================== # # entry point -from Base.Exceptions import PlatformNotSupportedException - - if __name__ != "__main__": # place library initialization code here pass @@ -45,13 +42,15 @@ # load dependencies -from pathlib import Path +from datetime import datetime +from pathlib import Path -from Base.Compiler import Compiler as BaseCompiler, CompilerException, SkipableCompilerException -from Base.Project import ToolChain, Tool -from PoC.Entity import WildCard -from ToolChains.Lattice.Diamond import Diamond, SynthesisArgumentFile +from Base.Exceptions import PlatformNotSupportedException +from Base.Compiler import Compiler as BaseCompiler, CompilerException, SkipableCompilerException, CompileState +from Base.Project import ToolChain, Tool, VHDLVersion +from PoC.Entity import WildCard from ToolChains.Lattice.Lattice import LatticeException +from ToolChains.Lattice.Diamond import Diamond, SynthesisArgumentFile class Compiler(BaseCompiler): @@ -61,36 +60,48 @@ class Compiler(BaseCompiler): def __init__(self, host, dryRun, noCleanUp): super().__init__(host, dryRun, noCleanUp) - self._toolChain = None + self._toolChain = None + self._vhdlVersion = VHDLVersion.VHDL2008 configSection = host.PoCConfig['CONFIG.DirectoryNames'] self.Directories.Working = host.Directories.Temp / configSection['LatticeSynthesisFiles'] self.Directories.Netlist = host.Directories.Root / configSection['NetlistFiles'] - + self._PrepareCompiler() def _PrepareCompiler(self): - self._LogVerbose("Preparing Lattice Synthesis Engine (LSE).") + super()._PrepareCompiler() + diamondSection = self.Host.PoCConfig['INSTALL.Lattice.Diamond'] - if (self.Host.Platform == "Linux"): - binaryPath = Path(diamondSection['BinaryDirectory2']) - elif (self.Host.Platform == "Windows"): - binaryPath = Path(diamondSection['BinaryDirectory']) - else: - raise PlatformNotSupportedException(self.Host.Platform) + if (self.Host.Platform == "Linux"): binaryPath = Path(diamondSection['BinaryDirectory2']) # ispFPGA directory + elif (self.Host.Platform == "Windows"): binaryPath = Path(diamondSection['BinaryDirectory2']) # ispFPGA directory + else: raise PlatformNotSupportedException(self.Host.Platform) version = diamondSection['Version'] - self._toolChain = Diamond(self.Host.Platform, binaryPath, version, logger=self.Logger) + self._toolChain = Diamond(self.Host.Platform, self.DryRun, binaryPath, version, logger=self.Logger) def RunAll(self, fqnList, *args, **kwargs): - for fqn in fqnList: - entity = fqn.Entity - if (isinstance(entity, WildCard)): - for netlist in entity.GetLatticeNetlists(): + """Run a list of netlist compilations. Expand wildcards to all selected netlists.""" + self._testSuite.StartTimer() + self.Logger.BaseIndent = int(len(fqnList) > 1) + try: + for fqn in fqnList: + entity = fqn.Entity + if (isinstance(entity, WildCard)): + self.Logger.BaseIndent = 1 + for netlist in entity.GetLatticeNetlists(): + self.TryRun(netlist, *args, **kwargs) + else: + netlist = entity.LatticeNetlist self.TryRun(netlist, *args, **kwargs) - else: - netlist = entity.LatticeNetlist - self.TryRun(netlist, *args, **kwargs) + except KeyboardInterrupt: + self.LogError("Received a keyboard interrupt.") + finally: + self._testSuite.StopTimer() + + self.PrintOverallCompileReport() + + return self._testSuite.IsAllSuccess def Run(self, netlist, board): super().Run(netlist, board) @@ -98,18 +109,30 @@ def Run(self, netlist, board): netlist.PrjFile = self.Directories.Working / (netlist.ModuleName + ".prj") lseArgumentFile = self._WriteLSEProjectFile(netlist, board) + self._prepareTime = self._GetTimeDeltaSinceLastEvent() - self._LogNormal("Executing pre-processing tasks...") + self.LogNormal("Executing pre-processing tasks...") + self._state = CompileState.PreCopy self._RunPreCopy(netlist) + self._state = CompileState.PrePatch self._RunPreReplace(netlist) + self._preTasksTime = self._GetTimeDeltaSinceLastEvent() - self._LogNormal("Running Lattice Diamond LSE...") + self.LogNormal("Running Lattice Diamond LSE...") + self._state = CompileState.Compile self._RunCompile(netlist, lseArgumentFile) # attach to netlist + self._compileTime = self._GetTimeDeltaSinceLastEvent() - self._LogNormal("Executing post-processing tasks...") + self.LogNormal("Executing post-processing tasks...") + self._state = CompileState.PostCopy self._RunPostCopy(netlist) + self._state = CompileState.PostPatch self._RunPostReplace(netlist) + self._state = CompileState.PostDelete self._RunPostDelete(netlist) + self._postTasksTime = self._GetTimeDeltaSinceLastEvent() + + self._endAt = datetime.now() def _WriteLSEProjectFile(self, netlist, board): device = board.Device @@ -120,6 +143,9 @@ def _WriteLSEProjectFile(self, netlist, board): argumentFile.Package = "{0!s}{1!s}".format(device.Package, device.PinCount) argumentFile.TopLevel = netlist.ModuleName argumentFile.LogFile = self.Directories.Working / (netlist.ModuleName + ".lse.log") + argumentFile.VHDLVersion = self._vhdlVersion + + argumentFile.HDLParams.update(self._GetHDLParameters(netlist.ConfigSectionName)) argumentFile.Write(self.PoCProject) return argumentFile @@ -133,4 +159,4 @@ def _RunCompile(self, netlist, lseArgumentFile): except LatticeException as ex: raise CompilerException("Error while compiling '{0!s}'.".format(netlist)) from ex if synth.HasErrors: - raise SkipableCompilerException("Error while compiling '{0!s}'.".format(netlist)) + raise SkipableCompilerException("Error while compiling '{0!s}'.".format(netlist)) diff --git a/py/Compiler/QuartusCompiler.py b/py/Compiler/QuartusCompiler.py index 1be1193e..0b898598 100644 --- a/py/Compiler/QuartusCompiler.py +++ b/py/Compiler/QuartusCompiler.py @@ -1,30 +1,30 @@ # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2; replace-tabs off; indent-width 2; -# +# # ============================================================================== # Authors: Patrick Lehmann # Martin Zabel -# +# # Python Class: This PoCXCOCompiler compiles xco IPCores to netlists -# +# # Description: # ------------------------------------ # TODO: -# - -# - +# - +# - # # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany # Chair for VLSI-Design, Diagnostics and Architecture -# +# # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at -# +# # http://www.apache.org/licenses/LICENSE-2.0 -# +# # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -42,12 +42,13 @@ # load dependencies +from datetime import datetime from pathlib import Path -from Base.Project import ToolChain, Tool -from Base.Compiler import Compiler as BaseCompiler, CompilerException, SkipableCompilerException -from PoC.Entity import WildCard -from ToolChains.Altera.Quartus import QuartusException, Quartus, QuartusSettingsFile, QuartusProjectFile +from Base.Project import ToolChain, Tool +from Base.Compiler import Compiler as BaseCompiler, CompilerException, SkipableCompilerException, CompileState +from PoC.Entity import WildCard +from ToolChains.Altera.Quartus import QuartusException, Quartus, QuartusSettings, QuartusProjectFile class Compiler(BaseCompiler): @@ -66,21 +67,35 @@ def __init__(self, host, dryRun, noCleanUp): self._PrepareCompiler() def _PrepareCompiler(self): - self._LogVerbose("Preparing Quartus-II Map (quartus_map).") + super()._PrepareCompiler() + quartusSection = self.Host.PoCConfig['INSTALL.Altera.Quartus'] binaryPath = Path(quartusSection['BinaryDirectory']) version = quartusSection['Version'] - self._toolChain = Quartus(self.Host.Platform, binaryPath, version, logger=self.Logger) + self._toolChain = Quartus(self.Host.Platform, self.DryRun, binaryPath, version, logger=self.Logger) def RunAll(self, fqnList, *args, **kwargs): - for fqn in fqnList: - entity = fqn.Entity - if (isinstance(entity, WildCard)): - for netlist in entity.GetQuartusNetlists(): + """Run a list of netlist compilations. Expand wildcards to all selected netlists.""" + self._testSuite.StartTimer() + self.Logger.BaseIndent = int(len(fqnList) > 1) + try: + for fqn in fqnList: + entity = fqn.Entity + if (isinstance(entity, WildCard)): + self.Logger.BaseIndent = 1 + for netlist in entity.GetQuartusNetlists(): + self.TryRun(netlist, *args, **kwargs) + else: + netlist = entity.QuartusNetlist self.TryRun(netlist, *args, **kwargs) - else: - netlist = entity.QuartusNetlist - self.TryRun(netlist, *args, **kwargs) + except KeyboardInterrupt: + self.LogError("Received a keyboard interrupt.") + finally: + self._testSuite.StopTimer() + + self.PrintOverallCompileReport() + + return self._testSuite.IsAllSuccess def Run(self, netlist, board): super().Run(netlist, board) @@ -89,18 +104,30 @@ def Run(self, netlist, board): netlist.QsfFile = self.Directories.Working / (netlist.ModuleName + ".qsf") self._WriteQuartusProjectFile(netlist, board.Device) + self._prepareTime = self._GetTimeDeltaSinceLastEvent() - self._LogNormal("Executing pre-processing tasks...") + self.LogNormal("Executing pre-processing tasks...") + self._state = CompileState.PreCopy self._RunPreCopy(netlist) + self._state = CompileState.PrePatch self._RunPreReplace(netlist) + self._preTasksTime = self._GetTimeDeltaSinceLastEvent() - self._LogNormal("Running Altera Quartus Map...") + self.LogNormal("Running Altera Quartus Map...") + self._state = CompileState.Compile self._RunCompile(netlist) + self._compileTime = self._GetTimeDeltaSinceLastEvent() - self._LogNormal("Executing post-processing tasks...") + self.LogNormal("Executing post-processing tasks...") + self._state = CompileState.PostCopy self._RunPostCopy(netlist) + self._state = CompileState.PostPatch self._RunPostReplace(netlist) + self._state = CompileState.PostDelete self._RunPostDelete(netlist) + self._postTasksTime = self._GetTimeDeltaSinceLastEvent() + + self._endAt = datetime.now() def _WriteSpecialSectionIntoConfig(self, device): # add the key Device to section SPECIAL at runtime to change interpolation results @@ -113,15 +140,17 @@ def _WriteSpecialSectionIntoConfig(self, device): def _WriteQuartusProjectFile(self, netlist, device): quartusProjectFile = QuartusProjectFile(netlist.QsfFile) - quartusProject = QuartusSettingsFile(netlist.ModuleName, quartusProjectFile) - quartusProject.GlobalAssignments['FAMILY'] = "\"{0}\"".format(device.Series) - quartusProject.GlobalAssignments['DEVICE'] = device.ShortName - quartusProject.GlobalAssignments['TOP_LEVEL_ENTITY'] = netlist.ModuleName - quartusProject.GlobalAssignments['VHDL_INPUT_VERSION'] = "VHDL_2008" + quartusSettings = QuartusSettings(netlist.ModuleName, quartusProjectFile) + quartusSettings.GlobalAssignments['FAMILY'] = "\"{0}\"".format(device.Series) + quartusSettings.GlobalAssignments['DEVICE'] = device.ShortName + quartusSettings.GlobalAssignments['TOP_LEVEL_ENTITY'] = netlist.ModuleName + quartusSettings.GlobalAssignments['VHDL_INPUT_VERSION'] = "VHDL_2008" + quartusSettings.Parameters.update(self._GetHDLParameters(netlist.ConfigSectionName)) - quartusProject.CopySourceFilesFromProject(self.PoCProject) + # transform files from PoCProject to global assignment commands in a QSF files + quartusSettings.CopySourceFilesFromProject(self.PoCProject) - quartusProject.Write() + quartusSettings.Write() def _RunCompile(self, netlist): q2map = self._toolChain.GetMap() diff --git a/py/Compiler/VivadoCompiler.py b/py/Compiler/VivadoCompiler.py index 12fe5ca4..23000667 100644 --- a/py/Compiler/VivadoCompiler.py +++ b/py/Compiler/VivadoCompiler.py @@ -1,29 +1,29 @@ # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2; replace-tabs off; indent-width 2; -# +# # ============================================================================== # Authors: Patrick Lehmann -# -# Python Class: This SynthCompiler compiles VHDL source files to design checkpoints -# +# +# Python Class: This SynthCompiler compiles VHDL source files to design checkpoints +# # Description: # ------------------------------------ # TODO: -# - -# - +# - +# - # # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany # Chair for VLSI-Design, Diagnostics and Architecture -# +# # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at -# +# # http://www.apache.org/licenses/LICENSE-2.0 -# +# # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -32,6 +32,8 @@ # ============================================================================== # # entry point + + if __name__ != "__main__": # place library initialization code here pass @@ -41,12 +43,13 @@ # load dependencies +from datetime import datetime from pathlib import Path -from Base.Project import ToolChain, Tool, FileTypes -from Base.Compiler import Compiler as BaseCompiler, CompilerException, SkipableCompilerException -from PoC.Entity import WildCard -from ToolChains.Xilinx.Vivado import Vivado, VivadoException +from Base.Project import ToolChain, Tool, FileTypes +from Base.Compiler import Compiler as BaseCompiler, CompilerException, SkipableCompilerException, CompileState +from PoC.Entity import WildCard +from ToolChains.Xilinx.Vivado import Vivado, VivadoException class Compiler(BaseCompiler): @@ -57,63 +60,89 @@ def __init__(self, host, dryRun, noCleanUp): super().__init__(host, dryRun, noCleanUp) self._device = None - self._toolChain = None + self._toolChain = None configSection = host.PoCConfig['CONFIG.DirectoryNames'] - self.Directories.Working = host.Directories.Temp / configSection['VivadoSynthesisFiles'] + self.Directories.Working = host.Directories.Temp / configSection['VivadoSynthesisFiles'] self.Directories.XSTFiles = host.Directories.Root / configSection['VivadoSynthesisFiles'] - self.Directories.Netlist = host.Directories.Root / configSection['NetlistFiles'] + self.Directories.Netlist = host.Directories.Root / configSection['NetlistFiles'] self._PrepareCompiler() def _PrepareCompiler(self): - self._LogVerbose("Preparing Xilinx Vivado Synthesis.") - iseSection = self.Host.PoCConfig['INSTALL.Xilinx.Vivado'] - binaryPath = Path(iseSection['BinaryDirectory']) - version = iseSection['Version'] - self._toolChain = Vivado(self.Host.Platform, binaryPath, version, logger=self.Logger) + super()._PrepareCompiler() + + vivadoSection = self.Host.PoCConfig['INSTALL.Xilinx.Vivado'] + binaryPath = Path(vivadoSection['BinaryDirectory']) + version = vivadoSection['Version'] + self._toolChain = Vivado(self.Host.Platform, self.DryRun, binaryPath, version, logger=self.Logger) def RunAll(self, fqnList, *args, **kwargs): - for fqn in fqnList: - entity = fqn.Entity - if (isinstance(entity, WildCard)): - for netlist in entity.GetVivadoNetlists(): + """Run a list of netlist compilations. Expand wildcards to all selected netlists.""" + self._testSuite.StartTimer() + self.Logger.BaseIndent = int(len(fqnList) > 1) + try: + for fqn in fqnList: + entity = fqn.Entity + if (isinstance(entity, WildCard)): + self.Logger.BaseIndent = 1 + for netlist in entity.GetVivadoNetlists(): + self.TryRun(netlist, *args, **kwargs) + else: + netlist = entity.VivadoNetlist self.TryRun(netlist, *args, **kwargs) - else: - netlist = entity.VivadoNetlist - self.TryRun(netlist, *args, **kwargs) + except KeyboardInterrupt: + self.LogError("Received a keyboard interrupt.") + finally: + self._testSuite.StopTimer() + + self.PrintOverallCompileReport() + + return self._testSuite.IsAllSuccess def Run(self, netlist, board): super().Run(netlist, board) netlist.TclFile = self.Directories.Working / (netlist.ModuleName + ".tcl") self._WriteTclFile(netlist,board.Device) + self._prepareTime = self._GetTimeDeltaSinceLastEvent() - self._LogNormal("Executing pre-processing tasks...") + self.LogNormal("Executing pre-processing tasks...") + self._state = CompileState.PreCopy self._RunPreCopy(netlist) + self._state = CompileState.PrePatch self._RunPreReplace(netlist) + self._preTasksTime = self._GetTimeDeltaSinceLastEvent() - self._LogNormal("Running Xilinx Vivado Synthesis...") + self.LogNormal("Running Xilinx Vivado Synthesis...") + self._state = CompileState.Compile self._RunCompile(netlist) + self._compileTime = self._GetTimeDeltaSinceLastEvent() - self._LogNormal("Executing post-processing tasks...") + self.LogNormal("Executing post-processing tasks...") + self._state = CompileState.PostCopy self._RunPostCopy(netlist) + self._state = CompileState.PostPatch self._RunPostReplace(netlist) + self._state = CompileState.PostDelete self._RunPostDelete(netlist) - + self._postTasksTime = self._GetTimeDeltaSinceLastEvent() + + self._endAt = datetime.now() + def _WriteSpecialSectionIntoConfig(self, device): # add the key Device to section SPECIAL at runtime to change interpolation results self.Host.PoCConfig['SPECIAL'] = {} self.Host.PoCConfig['SPECIAL']['Device'] = device.FullName self.Host.PoCConfig['SPECIAL']['DeviceSeries'] = device.Series - self.Host.PoCConfig['SPECIAL']['OutputDir'] = self.Directories.Working.as_posix() + self.Host.PoCConfig['SPECIAL']['OutputDir'] = self.Directories.Working.as_posix() def _RunCompile(self, netlist): reportFilePath = self.Directories.Working / (netlist.ModuleName + ".log") synth = self._toolChain.GetSynthesizer() synth.Parameters[synth.SwitchSourceFile] = netlist.ModuleName + ".tcl" - synth.Parameters[synth.SwitchLogFile] = str(reportFilePath) + synth.Parameters[synth.SwitchLogFile] = str(reportFilePath) try: synth.Compile() except VivadoException as ex: @@ -130,10 +159,18 @@ def _WriteTclFile(self, netlist, device): buffer += "read_verilog {file} \n". \ format(file=file.Path.as_posix()) - buffer += "synth_design -top {top} -part {part} \n".format(top=netlist.ModuleName, part=device.ShortName) + topLevelGenerics = "" + for keyValuePair in self._GetHDLParameters(netlist.ConfigSectionName).items(): + topLevelGenerics += " -generic {{{0}={1}}}".format(*keyValuePair) + + buffer += "synth_design -top {top} -part {part}{TopLevelGenerics}\n".format( + top=netlist.ModuleName, + part=device.ShortName, + TopLevelGenerics=topLevelGenerics + ) buffer += "write_checkpoint -noxdef {top}.dcp \n".format(top=netlist.ModuleName) buffer += "catch {{ report_utilization -file {top}_synth.rpt -pb {top}_synth.pb }}\n".format(top=netlist.ModuleName) - self._LogDebug("Writing Vivado TCL file to '{0!s}'".format(netlist.TclFile)) + self.LogDebug("Writing Vivado TCL file to '{0!s}'".format(netlist.TclFile)) with netlist.TclFile.open('w') as tclFileHandle: tclFileHandle.write(buffer) diff --git a/py/Compiler/XCICompiler.py b/py/Compiler/XCICompiler.py new file mode 100644 index 00000000..a461e3f3 --- /dev/null +++ b/py/Compiler/XCICompiler.py @@ -0,0 +1,281 @@ +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# +# ============================================================================== +# Authors: Patrick Lehmann +# +# Python Class: This XCICompiler compiles xci IPCores to netlists +# +# Description: +# ------------------------------------ +# TODO: +# - +# - +# +# License: +# ============================================================================== +# Copyright 2007-2016 Technische Universitaet Dresden - Germany +# Chair for VLSI-Design, Diagnostics and Architecture +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================== +# +# entry point +if __name__ != "__main__": + # place library initialization code here + pass +else: + from lib.Functions import Exit + Exit.printThisIsNoExecutableFile("The PoC-Library - Python Module Compiler.XCICompiler") + + +# load dependencies +import shutil +from datetime import datetime +from os import chdir +from pathlib import Path +from textwrap import dedent + +from Base.Project import ToolChain, Tool +from Base.Compiler import Compiler as BaseCompiler, CompilerException, SkipableCompilerException, CompileState +from PoC.Entity import WildCard +from ToolChains.Xilinx.Vivado import Vivado, VivadoException + + +class Compiler(BaseCompiler): + _TOOL_CHAIN = ToolChain.Xilinx_Vivado + _TOOL = Tool.Xilinx_IPCatalog + + def __init__(self, host, dryRun, noCleanUp): + super().__init__(host, dryRun, noCleanUp) + + self._toolChain = None + + configSection = host.PoCConfig['CONFIG.DirectoryNames'] + self.Directories.Working = host.Directories.Temp / configSection['VivadoIPCatalogFiles'] + self.Directories.Netlist = host.Directories.Root / configSection['NetlistFiles'] + + self._PrepareCompiler() + + def _PrepareCompiler(self): + super()._PrepareCompiler() + + vivadoSection = self.Host.PoCConfig['INSTALL.Xilinx.Vivado'] + binaryPath = Path(vivadoSection['BinaryDirectory']) + version = vivadoSection['Version'] + self._toolChain = Vivado(self.Host.Platform, self.DryRun, binaryPath, version, logger=self.Logger) + + def RunAll(self, fqnList, *args, **kwargs): + """Run a list of netlist compilations. Expand wildcards to all selected netlists.""" + self._testSuite.StartTimer() + self.Logger.BaseIndent = int(len(fqnList) > 1) + try: + for fqn in fqnList: + entity = fqn.Entity + if (isinstance(entity, WildCard)): + self.Logger.BaseIndent = 1 + for netlist in entity.GetCoreGenNetlists(): + self.TryRun(netlist, *args, **kwargs) + else: + netlist = entity.CGNetlist + self.TryRun(netlist, *args, **kwargs) + except KeyboardInterrupt: + self.LogError("Received a keyboard interrupt.") + finally: + self._testSuite.StopTimer() + + self.PrintOverallCompileReport() + + return self._testSuite.IsAllSuccess + + def Run(self, netlist, board): + super().Run(netlist, board) + self._prepareTime = self._GetTimeDeltaSinceLastEvent() + + self.LogNormal("Executing pre-processing tasks...") + self._state = CompileState.PreCopy + self._RunPreCopy(netlist) + self._state = CompileState.PrePatch + self._RunPreReplace(netlist) + self._preTasksTime = self._GetTimeDeltaSinceLastEvent() + + self.LogNormal("Running Xilinx Core Generator...") + self._state = CompileState.Compile + self._RunCompile(netlist, board.Device) + self._compileTime = self._GetTimeDeltaSinceLastEvent() + + self.LogNormal("Executing post-processing tasks...") + self._state = CompileState.PostCopy + self._RunPostCopy(netlist) + self._state = CompileState.PostPatch + self._RunPostReplace(netlist) + self._state = CompileState.PostDelete + self._RunPostDelete(netlist) + self._postTasksTime = self._GetTimeDeltaSinceLastEvent() + + self._endAt = datetime.now() + + def _WriteSpecialSectionIntoConfig(self, device): + # add the key Device to section SPECIAL at runtime to change interpolation results + self.Host.PoCConfig['SPECIAL'] = {} + self.Host.PoCConfig['SPECIAL']['Device'] = device.FullName + self.Host.PoCConfig['SPECIAL']['DeviceSeries'] = device.Series + self.Host.PoCConfig['SPECIAL']['OutputDir'] = self.Directories.Working.as_posix() + + def _RunCompile(self, netlist, device): + self.LogVerbose("Patching coregen.cgp and .cgc files...") + # read netlist settings from configuration file + xciInputFilePath = netlist.XciFile + cgcTemplateFilePath = self.Directories.Netlist / "template.cgc" + cgpFilePath = self.Directories.Working / "coregen.cgp" + cgcFilePath = self.Directories.Working / "coregen.cgc" + xciFilePath = self.Directories.Working / xciInputFilePath.name + + if (self.Host.Platform == "Windows"): + WorkingDirectory = ".\\temp\\" + else: + WorkingDirectory = "./temp/" + + # write CoreGenerator project file + cgProjectFileContent = dedent("""\ + SET addpads = false + SET asysymbol = false + SET busformat = BusFormatAngleBracketNotRipped + SET createndf = false + SET designentry = VHDL + SET device = {Device} + SET devicefamily = {DeviceFamily} + SET flowvendor = Other + SET formalverification = false + SET foundationsym = false + SET implementationfiletype = Ngc + SET package = {Package} + SET removerpms = false + SET simulationfiles = Behavioral + SET speedgrade = {SpeedGrade} + SET verilogsim = false + SET vhdlsim = true + SET workingdirectory = {WorkingDirectory} + """.format( + Device=device.ShortName.lower(), + DeviceFamily=device.FamilyName.lower(), + Package=(str(device.Package).lower() + str(device.PinCount)), + SpeedGrade=device.SpeedGrade, + WorkingDirectory=WorkingDirectory + )) + + self.LogDebug("Writing CoreGen project file to '{0}'.".format(cgpFilePath)) + with cgpFilePath.open('w') as cgpFileHandle: + cgpFileHandle.write(cgProjectFileContent) + + # write CoreGenerator content? file + self.LogDebug("Reading CoreGen content file to '{0}'.".format(cgcTemplateFilePath)) + with cgcTemplateFilePath.open('r') as cgcFileHandle: + cgContentFileContent = cgcFileHandle.read() + + cgContentFileContent = cgContentFileContent.format( + name="lcd_ChipScopeVIO", + device=device.ShortName, + devicefamily=device.FamilyName, + package=(str(device.Package) + str(device.PinCount)), + speedgrade=device.SpeedGrade + ) + + self.LogDebug("Writing CoreGen content file to '{0}'.".format(cgcFilePath)) + with cgcFilePath.open('w') as cgcFileHandle: + cgcFileHandle.write(cgContentFileContent) + + # copy xci file into temporary directory + self.LogVerbose("Copy CoreGen xci file to '{0}'.".format(xciFilePath)) + self.LogDebug("cp {0!s} {1!s}".format(xciInputFilePath, self.Directories.Working)) + try: + shutil.copy(str(xciInputFilePath), str(xciFilePath), follow_symlinks=True) + except OSError as ex: + raise CompilerException("Error while copying '{0!s}'.".format(xciInputFilePath)) from ex + + # change working directory to temporary CoreGen path + self.LogDebug("cd {0!s}".format(self.Directories.Working)) + try: + chdir(str(self.Directories.Working)) + except OSError as ex: + raise CompilerException("Error while changing to '{0!s}'.".format(self.Directories.Working)) from ex + + # running CoreGen + # ========================================================================== + self.LogVerbose("Executing CoreGen...") + coreGen = self._toolChain.GetCoreGenerator() + coreGen.Parameters[coreGen.SwitchProjectFile] = "." # use current directory and the default project name + coreGen.Parameters[coreGen.SwitchBatchFile] = str(xciFilePath) + coreGen.Parameters[coreGen.FlagRegenerate] = True + + try: + coreGen.Generate() + except VivadoException as ex: + raise CompilerException("Error while compiling '{0!s}'.".format(netlist)) from ex + if coreGen.HasErrors: + raise SkipableCompilerException("Error while compiling '{0!s}'.".format(netlist)) + + def _WriteTclFile(self, netlist, device): + buffer = dedent("""\ + create_project -in_memory -part {part} + + set_param synth.vivado.isSynthRun true + set_property target_language VHDL [current_project] + + read_ip -quiet {xciFile}go + + synth_design -top {ipCoreName} -part {part} -mode out_of_context + + write_checkpoint -noxdef {top}.dcp + + if { [catch { + report_utilization -file {top}_synth.rpt -pb {top}_synth.pb + } _RESULT ] } { + puts "CRITICAL WARNING: Error reported: $_RESULT" + } + + if { [catch { + write_verilog -force -mode synth_stub {xciFilebaseName}_stub.v + } _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. Error reported: $_RESULT" + } + + if { [catch { + write_vhdl -force -mode synth_stub {xciFilebaseName}_stub.vhdl + } _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. Error reported: $_RESULT" + } + + if { [catch { + write_verilog -force -mode funcsim {xciFilebaseName}_sim_netlist.v + } _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Error reported: $_RESULT" + } + + if { [catch { + write_vhdl -force -mode funcsim {xciFilebaseName}_sim_netlist.vhdl + } _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Error reported: $_RESULT" + } + """).format( + part=device.FullName2, + xciFile=xciFile.as_posix(), + xciFilebaseName=xciFile.BaseName, + top=netlist.ModuleName, + ipCoreName="foo.xci" + ) + + self.LogDebug("Writing Vivado TCL file to '{0!s}'".format(netlist.TclFile)) + with netlist.TclFile.open('w') as tclFileHandle: + tclFileHandle.write(buffer) diff --git a/py/Compiler/XCOCompiler.py b/py/Compiler/XCOCompiler.py index f55f1517..4cd5bcff 100644 --- a/py/Compiler/XCOCompiler.py +++ b/py/Compiler/XCOCompiler.py @@ -1,30 +1,30 @@ # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2; replace-tabs off; indent-width 2; -# +# # ============================================================================== # Authors: Patrick Lehmann # Martin Zabel -# -# Python Class: This XCOCompiler compiles xco IPCores to netlists -# +# +# Python Class: This XCOCompiler compiles xco IPCores to netlists +# # Description: # ------------------------------------ # TODO: -# - -# - +# - +# - # # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany # Chair for VLSI-Design, Diagnostics and Architecture -# +# # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at -# +# # http://www.apache.org/licenses/LICENSE-2.0 -# +# # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -40,22 +40,23 @@ from lib.Functions import Exit Exit.printThisIsNoExecutableFile("The PoC-Library - Python Module Compiler.XCOCompiler") - + # load dependencies import shutil +from datetime import datetime from os import chdir from pathlib import Path from textwrap import dedent from Base.Project import ToolChain, Tool -from Base.Compiler import Compiler as BaseCompiler, CompilerException, SkipableCompilerException +from Base.Compiler import Compiler as BaseCompiler, CompilerException, SkipableCompilerException, CompileState from PoC.Entity import WildCard from ToolChains.Xilinx.ISE import ISE, ISEException class Compiler(BaseCompiler): - _TOOL_CHAIN = ToolChain.Xilinx_ISE - _TOOL = Tool.Xilinx_CoreGen + _TOOL_CHAIN = ToolChain.Xilinx_ISE + _TOOL = Tool.Xilinx_CoreGen def __init__(self, host, dryRun, noCleanUp): super().__init__(host, dryRun, noCleanUp) @@ -69,46 +70,72 @@ def __init__(self, host, dryRun, noCleanUp): self._PrepareCompiler() def _PrepareCompiler(self): - self._LogVerbose("Preparing Xilinx Core Generator Tool (CoreGen).") + super()._PrepareCompiler() + iseSection = self.Host.PoCConfig['INSTALL.Xilinx.ISE'] binaryPath = Path(iseSection['BinaryDirectory']) version = iseSection['Version'] - self._toolChain = ISE(self.Host.Platform, binaryPath, version, logger=self.Logger) + self._toolChain = ISE(self.Host.Platform, self.DryRun, binaryPath, version, logger=self.Logger) def RunAll(self, fqnList, *args, **kwargs): - for fqn in fqnList: - entity = fqn.Entity - if (isinstance(entity, WildCard)): - for netlist in entity.GetCoreGenNetlists(): + """Run a list of netlist compilations. Expand wildcards to all selected netlists.""" + self._testSuite.StartTimer() + self.Logger.BaseIndent = int(len(fqnList) > 1) + try: + for fqn in fqnList: + entity = fqn.Entity + if (isinstance(entity, WildCard)): + self.Logger.BaseIndent = 1 + for netlist in entity.GetCoreGenNetlists(): + self.TryRun(netlist, *args, **kwargs) + else: + netlist = entity.CGNetlist self.TryRun(netlist, *args, **kwargs) - else: - netlist = entity.CGNetlist - self.TryRun(netlist, *args, **kwargs) + except KeyboardInterrupt: + self.LogError("Received a keyboard interrupt.") + finally: + self._testSuite.StopTimer() + + self.PrintOverallCompileReport() + + return self._testSuite.IsAllSuccess def Run(self, netlist, board): super().Run(netlist, board) + self._prepareTime = self._GetTimeDeltaSinceLastEvent() - self._LogNormal("Executing pre-processing tasks...") + self.LogNormal("Executing pre-processing tasks...") + self._state = CompileState.PreCopy self._RunPreCopy(netlist) + self._state = CompileState.PrePatch self._RunPreReplace(netlist) + self._preTasksTime = self._GetTimeDeltaSinceLastEvent() - self._LogNormal("Running Xilinx Core Generator...") + self.LogNormal("Running Xilinx Core Generator...") + self._state = CompileState.Compile self._RunCompile(netlist, board.Device) + self._compileTime = self._GetTimeDeltaSinceLastEvent() - self._LogNormal("Executing post-processing tasks...") + self.LogNormal("Executing post-processing tasks...") + self._state = CompileState.PostCopy self._RunPostCopy(netlist) + self._state = CompileState.PostPatch self._RunPostReplace(netlist) + self._state = CompileState.PostDelete self._RunPostDelete(netlist) + self._postTasksTime = self._GetTimeDeltaSinceLastEvent() + + self._endAt = datetime.now() def _WriteSpecialSectionIntoConfig(self, device): # add the key Device to section SPECIAL at runtime to change interpolation results self.Host.PoCConfig['SPECIAL'] = {} self.Host.PoCConfig['SPECIAL']['Device'] = device.FullName self.Host.PoCConfig['SPECIAL']['DeviceSeries'] = device.Series - self.Host.PoCConfig['SPECIAL']['OutputDir'] = self.Directories.Working.as_posix() + self.Host.PoCConfig['SPECIAL']['OutputDir'] = self.Directories.Working.as_posix() def _RunCompile(self, netlist, device): - self._LogVerbose("Patching coregen.cgp and .cgc files...") + self.LogVerbose("Patching coregen.cgp and .cgc files...") # read netlist settings from configuration file xcoInputFilePath = netlist.XcoFile cgcTemplateFilePath = self.Directories.Netlist / "template.cgc" @@ -149,12 +176,12 @@ def _RunCompile(self, netlist, device): WorkingDirectory=WorkingDirectory )) - self._LogDebug("Writing CoreGen project file to '{0}'.".format(cgpFilePath)) + self.LogDebug("Writing CoreGen project file to '{0}'.".format(cgpFilePath)) with cgpFilePath.open('w') as cgpFileHandle: cgpFileHandle.write(cgProjectFileContent) # write CoreGenerator content? file - self._LogDebug("Reading CoreGen content file to '{0}'.".format(cgcTemplateFilePath)) + self.LogDebug("Reading CoreGen content file to '{0}'.".format(cgcTemplateFilePath)) with cgcTemplateFilePath.open('r') as cgcFileHandle: cgContentFileContent = cgcFileHandle.read() @@ -166,20 +193,20 @@ def _RunCompile(self, netlist, device): speedgrade=device.SpeedGrade ) - self._LogDebug("Writing CoreGen content file to '{0}'.".format(cgcFilePath)) + self.LogDebug("Writing CoreGen content file to '{0}'.".format(cgcFilePath)) with cgcFilePath.open('w') as cgcFileHandle: cgcFileHandle.write(cgContentFileContent) # copy xco file into temporary directory - self._LogVerbose("Copy CoreGen xco file to '{0}'.".format(xcoFilePath)) - self._LogDebug("cp {0!s} {1!s}".format(xcoInputFilePath, self.Directories.Working)) + self.LogVerbose("Copy CoreGen xco file to '{0}'.".format(xcoFilePath)) + self.LogDebug("cp {0!s} {1!s}".format(xcoInputFilePath, self.Directories.Working)) try: shutil.copy(str(xcoInputFilePath), str(xcoFilePath), follow_symlinks=True) except OSError as ex: raise CompilerException("Error while copying '{0!s}'.".format(xcoInputFilePath)) from ex # change working directory to temporary CoreGen path - self._LogDebug("cd {0!s}".format(self.Directories.Working)) + self.LogDebug("cd {0!s}".format(self.Directories.Working)) try: chdir(str(self.Directories.Working)) except OSError as ex: @@ -187,7 +214,7 @@ def _RunCompile(self, netlist, device): # running CoreGen # ========================================================================== - self._LogVerbose("Executing CoreGen...") + self.LogVerbose("Executing CoreGen...") coreGen = self._toolChain.GetCoreGenerator() coreGen.Parameters[coreGen.SwitchProjectFile] = "." # use current directory and the default project name coreGen.Parameters[coreGen.SwitchBatchFile] = str(xcoFilePath) diff --git a/py/Compiler/XSTCompiler.py b/py/Compiler/XSTCompiler.py index d69fb633..dfcae207 100644 --- a/py/Compiler/XSTCompiler.py +++ b/py/Compiler/XSTCompiler.py @@ -1,30 +1,30 @@ # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2; replace-tabs off; indent-width 2; -# +# # ============================================================================== # Authors: Patrick Lehmann # Martin Zabel -# +# # Python Class: This XSTCompiler compiles VHDL source files to netlists -# +# # Description: # ------------------------------------ # TODO: -# - -# - +# - +# - # # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany # Chair for VLSI-Design, Diagnostics and Architecture -# +# # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at -# +# # http://www.apache.org/licenses/LICENSE-2.0 -# +# # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -42,12 +42,13 @@ # load dependencies +from datetime import datetime from pathlib import Path -from Base.Project import ToolChain, Tool -from Base.Compiler import Compiler as BaseCompiler, CompilerException, SkipableCompilerException -from PoC.Entity import WildCard -from ToolChains.Xilinx.Xilinx import XilinxProjectExportMixIn +from Base.Project import ToolChain, Tool +from Base.Compiler import Compiler as BaseCompiler, CompilerException, SkipableCompilerException, CompileState +from PoC.Entity import WildCard +from ToolChains.Xilinx.Xilinx import XilinxProjectExportMixIn from ToolChains.Xilinx.ISE import ISE, ISEException @@ -72,21 +73,35 @@ def __init__(self, host, dryRun, noCleanUp): self._PrepareCompiler() def _PrepareCompiler(self): - self._LogVerbose("Preparing Xilinx Synthesis Tool (XST).") + super()._PrepareCompiler() + iseSection = self.Host.PoCConfig['INSTALL.Xilinx.ISE'] binaryPath = Path(iseSection['BinaryDirectory']) version = iseSection['Version'] - self._toolChain = ISE(self.Host.Platform, binaryPath, version, logger=self.Logger) + self._toolChain = ISE(self.Host.Platform, self.DryRun, binaryPath, version, logger=self.Logger) def RunAll(self, fqnList, *args, **kwargs): - for fqn in fqnList: - entity = fqn.Entity - if (isinstance(entity, WildCard)): - for netlist in entity.GetXSTNetlists(): + """Run a list of netlist compilations. Expand wildcards to all selected netlists.""" + self._testSuite.StartTimer() + self.Logger.BaseIndent = int(len(fqnList) > 1) + try: + for fqn in fqnList: + entity = fqn.Entity + if (isinstance(entity, WildCard)): + self.Logger.BaseIndent = 1 + for netlist in entity.GetXSTNetlists(): + self.TryRun(netlist, *args, **kwargs) + else: + netlist = entity.XSTNetlist self.TryRun(netlist, *args, **kwargs) - else: - netlist = entity.XSTNetlist - self.TryRun(netlist, *args, **kwargs) + except KeyboardInterrupt: + self.LogError("Received a keyboard interrupt.") + finally: + self._testSuite.StopTimer() + + self.PrintOverallCompileReport() + + return self._testSuite.IsAllSuccess def Run(self, netlist, board): super().Run(netlist, board) @@ -96,18 +111,30 @@ def Run(self, netlist, board): self._WriteXilinxProjectFile(netlist.PrjFile, "XST") self._WriteXstOptionsFile(netlist, board.Device) + self._prepareTime = self._GetTimeDeltaSinceLastEvent() - self._LogNormal("Executing pre-processing tasks...") + self.LogNormal("Executing pre-processing tasks...") + self._state = CompileState.PreCopy self._RunPreCopy(netlist) + self._state = CompileState.PrePatch self._RunPreReplace(netlist) + self._preTasksTime = self._GetTimeDeltaSinceLastEvent() - self._LogNormal("Running Xilinx Synthesis Tool...") + self.LogNormal("Running Xilinx Synthesis Tool...") + self._state = CompileState.Compile self._RunCompile(netlist) + self._compileTime = self._GetTimeDeltaSinceLastEvent() - self._LogNormal("Executing post-processing tasks...") + self.LogNormal("Executing post-processing tasks...") + self._state = CompileState.PostCopy self._RunPostCopy(netlist) + self._state = CompileState.PostPatch self._RunPostReplace(netlist) + self._state = CompileState.PostDelete self._RunPostDelete(netlist) + self._postTasksTime = self._GetTimeDeltaSinceLastEvent() + + self._endAt = datetime.now() def _WriteSpecialSectionIntoConfig(self, device): # add the key Device to section SPECIAL at runtime to change interpolation results @@ -132,10 +159,10 @@ def _RunCompile(self, netlist): def _WriteXstOptionsFile(self, netlist, device): - self._LogVerbose("Generating XST options file.") + self.LogVerbose("Generating XST options file.") # read XST options file template - self._LogDebug("Reading Xilinx Compiler Tool option file from '{0!s}'".format(netlist.XstTemplateFile)) + self.LogDebug("Reading Xilinx Compiler Tool option file from '{0!s}'".format(netlist.XstTemplateFile)) if (not netlist.XstTemplateFile.exists()): raise CompilerException("XST template files '{0!s}' not found.".format(netlist.XstTemplateFile))\ from FileNotFoundError(str(netlist.XstTemplateFile)) @@ -209,9 +236,13 @@ def _WriteXstOptionsFile(self, netlist, device): xstFileContent = xstFileContent.format(**xstTemplateDictionary) - if (self.Host.PoCConfig.has_option(netlist.ConfigSectionName, 'XSTOption.Generics')): - xstFileContent += "-generics {{ {0} }}".format(self.Host.PoCConfig[netlist.ConfigSectionName]['XSTOption.Generics']) + hdlParameters=self._GetHDLParameters(netlist.ConfigSectionName) + if(len(hdlParameters)>0): + xstFileContent += "-generics {" + for keyValuePair in hdlParameters.items(): + xstFileContent += " {0}={1}".format(*keyValuePair) + xstFileContent += " }\n" - self._LogDebug("Writing Xilinx Compiler Tool option file to '{0!s}'".format(netlist.XstFile)) + self.LogDebug("Writing Xilinx Compiler Tool option file to '{0!s}'".format(netlist.XstFile)) with netlist.XstFile.open('w') as fileHandle: fileHandle.write(xstFileContent) diff --git a/py/Compiler/__init__.py b/py/Compiler/__init__.py index c7937423..2d70fe94 100644 --- a/py/Compiler/__init__.py +++ b/py/Compiler/__init__.py @@ -1,28 +1,28 @@ # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2; replace-tabs off; indent-width 2; -# +# # ============================================================================== # Authors: Patrick Lehmann -# +# # Python Sub Module: TODO: -# +# # Description: # ------------------------------------ # TODO: -# +# # # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany # Chair for VLSI-Design, Diagnostics and Architecture -# +# # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at -# +# # http://www.apache.org/licenses/LICENSE-2.0 -# +# # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. diff --git a/py/FILES.md b/py/FILES.md deleted file mode 100644 index f8eb7380..00000000 --- a/py/FILES.md +++ /dev/null @@ -1,85 +0,0 @@ - -# `*.files` Files - -Files files are used to ... - -Line comments start with `#`. - -### Source File Statements - - - `vhdl ""` - This statement references a VHDL source file. - - `verilog ""` - This statement references a Verilog source file. - - `cocotb ""` - This statement references a Cocotb testbench file (Python file). - - `ucf ""` - This statement references a Xilinx User Constraint File (UCF). - - `sdc ""` - This statement references a Synopsys Design Constraint file (SDC). - - `xdc ""` - This statement references a Xilinx Design Constraint file (XDC). - - `ldc ""` - This statement references a Lattice Design Constraint file (LDC). - -### Conditional Statements - - - `If () Then ... [ElseIf () Then ...][Else ...] End IF` - This allows the user to define conditions, when to load a source file into - the file list. The `ElseIF` and `Else` clause of an `If` statement are optional. - - List of unary operators supported in the expressions: - - - `!` - not - - `[...]` - list construction - - `?` - file exists - - List of binary operators supported in the expressions: - - `and` - and - - `or` - or - - `xor` - exclusive or - - `in` - in list - - `=` - equal - - `!=` - unequal - - `<` - less than - - `<=` - less than or equal - - `>` - greater than - - `>=` - greater than or equal - - List of supported literals: - - - `` - a pre-defined constant - - `""` - Strings are enclosed in quote signs - - `` - Integers as decimal values - - List of pre-defined constants: - - - Environment Variables: - - - `Environment` - `"Simulation"` or `"Synthesis"` - - `ToolChain` - The used tool chain. E.g. `"Xilinx_ISE"` - - `Tool` - The used tool. E.g. `"Mentor_QuestaSim"` or `"Xilinx_XST"` - - `VHDL` - The used VHDL version. `1987`, `1993`, `2002`, `2008` - - - Board Variables: - - - `BoardName` - A string. E.g. `"KC705"` - - - Device Variables: - - - `DeviceVendor` - The vendor of the device. E.g. `"Altera"` - - `DeviceDevice` - - - `DeviceFamily` - - - `DeviceGeneration` - - - `DeviceSeries` - - -### Other Statements - - - `include ""` - Include another *.files file. - - `library ""` - Reference an existing (pre-compiled) VHDL library, which is passed to the - simulator, if external libraries are supported. - - `report ""` - Print a critical warning in the log window. This critical warning is - treated as an error. diff --git a/py/Parser/CodeDOM.py b/py/Parser/CodeDOM.py deleted file mode 100644 index 154233f5..00000000 --- a/py/Parser/CodeDOM.py +++ /dev/null @@ -1,107 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# -# ============================================================================== -# Authors: Patrick Lehmann -# Martin Zabel -# -# Python Module: TODO -# -# Description: -# ------------------------------------ -# TODO: -# -# License: -# ============================================================================== -# Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# ============================================================================== -# -from lib.Parser import CodeDOMObject, SpaceToken, CharacterToken, MismatchingParserResult, MatchingParserResult, Statement - - -# ============================================================================== -# Empty and comment lines -# ============================================================================== -class EmptyLine(CodeDOMObject): - def __init__(self): - super().__init__() - - @classmethod - def GetParser(cls): - # match for optional whitespace - token = yield - if isinstance(token, SpaceToken): token = yield - - # match for delimiter sign: \n - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult() - if (token.Value.lower() != "\n"): raise MismatchingParserResult() - - # construct result - result = cls() - raise MatchingParserResult(result) - - def __str__(self, indent=0): - return " " * indent + "" - - -class CommentLine(CodeDOMObject): - def __init__(self, commentText): - super().__init__() - self._commentText = commentText - - @property - def Text(self): - return self._commentText - - @classmethod - def GetParser(cls): - # match for optional whitespace - token = yield - if isinstance(token, SpaceToken): token = yield - - # match for sign: # - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult() - if (token.Value.lower() != "#"): raise MismatchingParserResult() - - # match for any until line end - commentText = "" - while True: - token = yield - if isinstance(token, CharacterToken): - if (token.Value == "\n"): break - commentText += token.Value - - # construct result - result = cls(commentText) - raise MatchingParserResult(result) - - def __str__(self, indent=0): - return "{0}#{1}".format(" " * indent, self._commentText) - -# ============================================================================== -# Blocked Statements (Forward declaration) -# ============================================================================== -class BlockedStatement(Statement): - _allowedStatements = [] - - @classmethod - def AddChoice(cls, value): - cls._allowedStatements.append(value) - - @classmethod - def GetParser(cls): - return cls.GetChoiceParser(cls._allowedStatements) diff --git a/py/Parser/FilesCodeDOM.py b/py/Parser/FilesCodeDOM.py index a72c592b..75088fd2 100644 --- a/py/Parser/FilesCodeDOM.py +++ b/py/Parser/FilesCodeDOM.py @@ -1,13 +1,13 @@ # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2; replace-tabs off; indent-width 2; -# +# # ============================================================================== # Authors: Patrick Lehmann # Martin Zabel -# +# # Python Module: TODO -# +# # Description: # ------------------------------------ # TODO: @@ -16,13 +16,13 @@ # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany # Chair for VLSI-Design, Diagnostics and Architecture -# +# # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at -# +# # http://www.apache.org/licenses/LICENSE-2.0 -# +# # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -30,78 +30,291 @@ # limitations under the License. # ============================================================================== # +from lib.Parser import MismatchingParserResult, MatchingParserResult, GreedyMatchingParserResult, StartOfDocumentToken +from lib.Parser import SpaceToken, CharacterToken, StringToken, NumberToken +from lib.CodeDOM import AndExpression, OrExpression, XorExpression, NotExpression, InExpression, NotInExpression, Literal, BinaryExpression +from lib.CodeDOM import EmptyLine, CommentLine, BlockedStatement as BlockedStatementBase, ExpressionChoice +from lib.CodeDOM import EqualExpression, UnequalExpression, LessThanExpression, LessThanEqualExpression, GreaterThanExpression, GreaterThanEqualExpression +from lib.CodeDOM import Statement, BlockStatement, ConditionalBlockStatement, Function, Expression, ListElement +from lib.CodeDOM import StringLiteral, IntegerLiteral, Identifier -from lib.Parser import MismatchingParserResult, MatchingParserResult -from lib.Parser import SpaceToken, CharacterToken, StringToken, NumberToken -from lib.Parser import Statement, BlockStatement, ConditionalBlockStatement, Expressions -from Parser.CodeDOM import EmptyLine, CommentLine, BlockedStatement as BlockedStatementBase +DEBUG = False#True # ============================================================================== -# Blocked Statements (Forward declaration) +# Forward declarations # ============================================================================== class BlockedStatement(BlockedStatementBase): _allowedStatements = [] +class IfThenElseExpressions(ExpressionChoice): + _allowedExpressions = [] + +class ListElementExpressions(ExpressionChoice): + _allowedExpressions = [] + +# class ListConstructorExpression(ExpressionChoice): +# _allowedExpressions = [] + +class PathExpressions(ExpressionChoice): + _allowedExpressions = [] + +# ============================================================================== +# Expressions +# ============================================================================== +NotExpression.__PARSER_EXPRESSIONS__ = IfThenElseExpressions + +EqualExpression.__PARSER_LHS_EXPRESSIONS__ = IfThenElseExpressions +EqualExpression.__PARSER_RHS_EXPRESSIONS__ = IfThenElseExpressions + +UnequalExpression.__PARSER_LHS_EXPRESSIONS__ = IfThenElseExpressions +UnequalExpression.__PARSER_RHS_EXPRESSIONS__ = IfThenElseExpressions + +LessThanExpression.__PARSER_LHS_EXPRESSIONS__ = IfThenElseExpressions +LessThanExpression.__PARSER_RHS_EXPRESSIONS__ = IfThenElseExpressions + +LessThanEqualExpression.__PARSER_LHS_EXPRESSIONS__ = IfThenElseExpressions +LessThanEqualExpression.__PARSER_RHS_EXPRESSIONS__ = IfThenElseExpressions + +GreaterThanExpression.__PARSER_LHS_EXPRESSIONS__ = IfThenElseExpressions +GreaterThanExpression.__PARSER_RHS_EXPRESSIONS__ = IfThenElseExpressions + +GreaterThanEqualExpression.__PARSER_LHS_EXPRESSIONS__ = IfThenElseExpressions +GreaterThanEqualExpression.__PARSER_RHS_EXPRESSIONS__ = IfThenElseExpressions + +AndExpression.__PARSER_LHS_EXPRESSIONS__ = IfThenElseExpressions +AndExpression.__PARSER_RHS_EXPRESSIONS__ = IfThenElseExpressions + +OrExpression.__PARSER_LHS_EXPRESSIONS__ = IfThenElseExpressions +OrExpression.__PARSER_RHS_EXPRESSIONS__ = IfThenElseExpressions + +XorExpression.__PARSER_LHS_EXPRESSIONS__ = IfThenElseExpressions +XorExpression.__PARSER_RHS_EXPRESSIONS__ = IfThenElseExpressions + +ListElement.__PARSER_LIST_ELEMENT_EXPRESSIONS__ = ListElementExpressions + + +class ListConstructorExpression(Expression): + def __init__(self): + super().__init__() + self._list = [] + + @property + def List(self): + return self._list + + def AddElement(self, element): + self._list.append(element) + + @classmethod + def GetParser(cls): + if DEBUG: print("init ListConstructorExpressionParser") + + # match for sign "[" + token = yield + if (not isinstance(token, CharacterToken)): raise MismatchingParserResult() + if (token.Value != "["): raise MismatchingParserResult() + # match for optional whitespace + token = yield + if isinstance(token, SpaceToken): token = yield + + result = cls() + parser = ListElementExpressions.GetParser() + parser.send(None) + + try: + while True: + parser.send(token) + token = yield + except MatchingParserResult as ex: + result.AddElement(ex.value) + + parser = cls.GetRepeatParser(result.AddElement, ListElement.GetParser) + parser.send(None) + + try: + while True: + token = yield + parser.send(token) + except MatchingParserResult: + pass + + # match for optional whitespace + if isinstance(token, SpaceToken): token = yield + # match for delimiter sign: \n + if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("ListConstructorExpressionParser: Expected end of line or comment") + if (token.Value != "]"): raise MismatchingParserResult("ListConstructorExpressionParser: Expected end of line or comment") + + # construct result + if DEBUG: print("ListConstructorExpressionParser: matched {0}".format(result)) + raise MatchingParserResult(result) + + def __str__(self): + buffer = "[{0}".format(self._list[0]) + for item in self._list[1:]: + buffer += ", {0}".format(item) + buffer += "]" + return buffer + + +InExpression.__PARSER_LHS_EXPRESSIONS__ = IfThenElseExpressions +InExpression.__PARSER_RHS_EXPRESSIONS__ = ListConstructorExpression + +NotInExpression.__PARSER_LHS_EXPRESSIONS__ = IfThenElseExpressions +NotInExpression.__PARSER_RHS_EXPRESSIONS__ = ListConstructorExpression + + +class SubDirectoryExpression(BinaryExpression): + __PARSER_NAME__ = "SubDirectoryExpressionParser" + __PARSER_LHS_EXPRESSIONS__ = PathExpressions + __PARSER_RHS_EXPRESSIONS__ = PathExpressions + __PARSER_OPERATOR__ = ("/",) + +class ConcatenateExpression(BinaryExpression): + __PARSER_NAME__ = "ConcatenateExpressionParser" + __PARSER_LHS_EXPRESSIONS__ = PathExpressions + __PARSER_RHS_EXPRESSIONS__ = PathExpressions + __PARSER_OPERATOR__ = ("&",) + + +class ExistsFunction(Function): + def __init__(self, expression): + super().__init__() + self._expression = expression + + @property + def Expression(self): + return self._expression + + @classmethod + def GetParser(cls): + if DEBUG: print("init ExistsFunctionParser") + + # match for EXISTS keyword + token = yield + # if (not isinstance(token, StringToken)): raise MismatchingParserResult() + # if (token.Value != "exists"): raise MismatchingParserResult() + if (not isinstance(token, CharacterToken)): raise MismatchingParserResult() + if (token.Value != "?"): raise MismatchingParserResult() + + # match for opening ( + token = yield + if (not isinstance(token, CharacterToken)): raise MismatchingParserResult() + if (token.Value != "{"): raise MismatchingParserResult() + # match for optional whitespace + token = yield + if isinstance(token, SpaceToken): token = yield + + # match for path expressions + parser = PathExpressions.GetParser() + parser.send(None) + pathExpression = None + try: + while True: + parser.send(token) + token = yield + except GreedyMatchingParserResult as ex: + pathExpression = ex.value + except MatchingParserResult as ex: + pathExpression = ex.value + token = yield + + # match for optional whitespace + if isinstance(token, SpaceToken): token = yield + # match for closing sign: } + if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("ExistsFunctionParser: Expected end of line or comment") + if (token.Value != "}"): raise MismatchingParserResult("ExistsFunctionParser: Expected end of line or comment") + + # construct result + result = cls(pathExpression) + if DEBUG: print("ExistsFunctionParser: matched {0}".format(result)) + raise MatchingParserResult(result) + + def __str__(self): + return "exists{{{0!s}}}".format(self._expression) + +IfThenElseExpressions.AddChoice(Identifier) +IfThenElseExpressions.AddChoice(StringLiteral) +IfThenElseExpressions.AddChoice(IntegerLiteral) +IfThenElseExpressions.AddChoice(NotExpression) +IfThenElseExpressions.AddChoice(ExistsFunction) +IfThenElseExpressions.AddChoice(AndExpression) +IfThenElseExpressions.AddChoice(OrExpression) +IfThenElseExpressions.AddChoice(XorExpression) +IfThenElseExpressions.AddChoice(EqualExpression) +IfThenElseExpressions.AddChoice(UnequalExpression) +IfThenElseExpressions.AddChoice(LessThanExpression) +IfThenElseExpressions.AddChoice(LessThanEqualExpression) +IfThenElseExpressions.AddChoice(GreaterThanExpression) +IfThenElseExpressions.AddChoice(GreaterThanEqualExpression) +IfThenElseExpressions.AddChoice(InExpression) +IfThenElseExpressions.AddChoice(NotInExpression) + +ListElementExpressions.AddChoice(Identifier) +ListElementExpressions.AddChoice(StringLiteral) +ListElementExpressions.AddChoice(IntegerLiteral) + + # ============================================================================== # File Reference Statements # ============================================================================== class VHDLStatement(Statement): - def __init__(self, libraryName, fileName, commentText): + def __init__(self, libraryName, pathExpression, commentText): super().__init__(commentText) - self._libraryName = libraryName - self._fileName = fileName + self._libraryName = libraryName + self._pathExpression = pathExpression @property - def LibraryName(self): return self._libraryName + def LibraryName(self): return self._libraryName @property - def FileName(self): return self._fileName + def PathExpression(self): return self._pathExpression - @classmethod + @classmethod # mccabe:disable=MC0001 def GetParser(cls): # match for optional whitespace token = yield - if isinstance(token, SpaceToken): token = yield - + if isinstance(token, SpaceToken): token = yield # match for VHDL keyword if (not isinstance(token, StringToken)): raise MismatchingParserResult("VHDLParser: Expected VHDL keyword.") - if (token.Value.lower() != "vhdl"): raise MismatchingParserResult("VHDLParser: Expected VHDL keyword.") - + if (token.Value.lower() != "vhdl"): raise MismatchingParserResult("VHDLParser: Expected VHDL keyword.") # match for whitespace token = yield - if (not isinstance(token, SpaceToken)): raise MismatchingParserResult("VHDLParser: Expected whitespace before VHDL library name.") - - # match for library name - library = "" - while True: - token = yield - if isinstance(token, StringToken): library += token.Value - elif isinstance(token, NumberToken): library += token.Value - elif (isinstance(token, CharacterToken) and (token.Value == "_")): - library += token.Value - else: - break + if (not isinstance(token, SpaceToken)): raise MismatchingParserResult("VHDLParser: Expected whitespace before VHDL library name.") + # match for identifier: library + parser = Identifier.GetParser() + parser.send(None) + library = None + try: + while True: + token = yield + parser.send(token) + except GreedyMatchingParserResult as ex: + library = ex.value.Name + except MatchingParserResult as ex: + library = ex.value.Name + token = yield # match for whitespace - if (not isinstance(token, SpaceToken)): raise MismatchingParserResult("VHDLParser: Expected whitespace before VHDL fileName.") - - # match for delimiter sign: " - token = yield - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("VHDLParser: Expected double quote sign before VHDL fileName.") - if (token.Value.lower() != "\""): raise MismatchingParserResult("VHDLParser: Expected double quote sign before VHDL fileName.") + if (not isinstance(token, SpaceToken)): raise MismatchingParserResult("VHDLParser: Expected whitespace before VHDL fileName.") - # match for string: fileName - fileName = "" - while True: - token = yield - if (isinstance(token, CharacterToken)and (token.Value == "\"")): break - fileName += token.Value + # match for a path: pathExpression + parser = PathExpressions.GetParser() + parser.send(None) + pathExpression = None + try: + while True: + token = yield + parser.send(token) + except GreedyMatchingParserResult as ex: + pathExpression = ex.value + except MatchingParserResult as ex: + pathExpression = ex.value + token = yield # match for optional whitespace - token = yield - if isinstance(token, SpaceToken): token = yield + if isinstance(token, SpaceToken): token = yield # match for delimiter sign: \n commentText = "" - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("VHDLParser: Expected end of line or comment") + if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("VHDLParser: Expected end of line or comment") if (token.Value == "\n"): pass elif (token.Value == "#"): @@ -112,61 +325,59 @@ def GetParser(cls): commentText += token.Value else: raise MismatchingParserResult("VHDLParser: Expected end of line or comment") - + # construct result - result = cls(library, fileName, commentText) + result = cls(library, pathExpression, commentText) raise MatchingParserResult(result) - + def __str__(self, indent=0): if (self._commentText != ""): - return "{0}VHDL {1} \"{2}\" # {3}".format((" " * indent), self._libraryName, self._fileName, self._commentText) + return "{0}VHDL {1} {2!s} # {3}".format((" " * indent), self._libraryName, self._pathExpression, self._commentText) else: - return "{0}VHDL {1} \"{2}\"".format((" " * indent), self._libraryName, self._fileName) + return "{0}VHDL {1} {2!s}".format((" " * indent), self._libraryName, self._pathExpression) class VerilogStatement(Statement): - def __init__(self, fileName, commentText): + def __init__(self, pathExpression, commentText): super().__init__() - self._fileName = fileName - self._commentText = commentText - + self._pathExpression = pathExpression + self._commentText = commentText + @property - def FileName(self): - return self._fileName - + def PathExpression(self): + return self._pathExpression + @classmethod def GetParser(cls): # match for optional whitespace token = yield - if isinstance(token, SpaceToken): - token = yield - + if isinstance(token, SpaceToken): token = yield # match for keyword: VERILOG if (not isinstance(token, StringToken)): raise MismatchingParserResult("VerilogParser: Expected VERILOG keyword.") if (token.Value.lower() != "verilog"): raise MismatchingParserResult("VerilogParser: Expected VERILOG keyword.") - # match for whitespace token = yield - if (not isinstance(token, SpaceToken)): raise MismatchingParserResult("VerilogParser: Expected whitespace before Verilog fileName.") - - # match for delimiter sign: " - token = yield - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("VerilogParser: Expected double quote sign before Verilog fileName.") - if (token.Value.lower() != "\""): raise MismatchingParserResult("VerilogParser: Expected double quote sign before Verilog fileName.") - - # match for string: fileName - fileName = "" - while True: + if (not isinstance(token, SpaceToken)): raise MismatchingParserResult("VerilogParser: Expected whitespace before Verilog fileName.") + + # match for string: fileName; use a StringLiteralParser to parse the pattern + parser = PathExpressions.GetParser() + parser.send(None) + pathExpression = None + try: + while True: + token = yield + parser.send(token) + except GreedyMatchingParserResult as ex: + pathExpression = ex.value + except MatchingParserResult as ex: + pathExpression = ex.value token = yield - if (isinstance(token, CharacterToken) and (token.Value == "\"")): break - fileName += token.Value # match for optional whitespace - token = yield - if isinstance(token, SpaceToken): token = yield + if isinstance(token, SpaceToken): token = yield # match for delimiter sign: \n commentText = "" - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("VerilogParser: Expected end of line or comment") + if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("VerilogParser: Expected end of line or comment") if (token.Value == "\n"): pass elif (token.Value == "#"): @@ -177,58 +388,56 @@ def GetParser(cls): commentText += token.Value else: raise MismatchingParserResult("VerilogParser: Expected end of line or comment") - + # construct result - result = cls(fileName, commentText) + result = cls(pathExpression, commentText) raise MatchingParserResult(result) - + def __str__(self, indent=0): - return "{0}Verilog \"{1}\"".format(" " * indent, self._fileName) + return "{0}Verilog {1!s}".format(" " * indent, self._pathExpression) class CocotbStatement(Statement): - def __init__(self, fileName, commentText): + def __init__(self, pathExpression, commentText): super().__init__() - self._fileName = fileName - self._commentText = commentText - + self._pathExpression = pathExpression + self._commentText = commentText + @property - def FileName(self): - return self._fileName - + def PathExpression(self): + return self._pathExpression + @classmethod def GetParser(cls): # match for optional whitespace token = yield - if isinstance(token, SpaceToken): token = yield - + if isinstance(token, SpaceToken): token = yield # match for keyword: COCOTB if (not isinstance(token, StringToken)): raise MismatchingParserResult("CocotbParser: Expected COCOTB keyword.") - if (token.Value.lower() != "cocotb"): raise MismatchingParserResult("CocotbParser: Expected COCOTB keyword.") - + if (token.Value.lower() != "cocotb"): raise MismatchingParserResult("CocotbParser: Expected COCOTB keyword.") # match for whitespace token = yield - if (not isinstance(token, SpaceToken)): raise MismatchingParserResult("CocotbParser: Expected whitespace before Python fileName.") - - # match for delimiter sign: " - token = yield - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("CocotbParser: Expected double quote sign before Python fileName.") - if (token.Value.lower() != "\""): raise MismatchingParserResult("CocotbParser: Expected double quote sign before Python fileName.") - - # match for string: fileName - fileName = "" - while True: + if (not isinstance(token, SpaceToken)): raise MismatchingParserResult("CocotbParser: Expected whitespace before Python fileName.") + + # match for string: fileName; use a StringLiteralParser to parse the pattern + parser = PathExpressions.GetParser() + parser.send(None) + pathExpression = None + try: + while True: + token = yield + parser.send(token) + except GreedyMatchingParserResult as ex: + pathExpression = ex.value + except MatchingParserResult as ex: + pathExpression = ex.value token = yield - if (isinstance(token, CharacterToken) and (token.Value == "\"")): break - fileName += token.Value # match for optional whitespace - token = yield - if isinstance(token, SpaceToken): token = yield - + if isinstance(token, SpaceToken): token = yield # match for delimiter sign: \n commentText = "" - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("CocotbParser: Expected end of line or comment") + if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("CocotbParser: Expected end of line or comment") if (token.Value == "\n"): pass elif (token.Value == "#"): @@ -239,58 +448,59 @@ def GetParser(cls): commentText += token.Value else: raise MismatchingParserResult("CocotbParser: Expected end of line or comment") - + # construct result - result = cls(fileName, commentText) + result = cls(pathExpression, commentText) raise MatchingParserResult(result) - + def __str__(self, indent=0): - return "{0}Cocotb \"{1}\"".format(" " * indent, self._fileName) + return "{0}Cocotb {1!s}".format(" " * indent, self._pathExpression) -class UcfStatement(Statement): - def __init__(self, fileName, commentText): +class ConstraintStatement(Statement): + __PARSER_NAME__ = None + __PARSER_KEYWORD__ = None + + def __init__(self, pathExpression, commentText): super().__init__() - self._fileName = fileName - self._commentText = commentText + self._pathExpression = pathExpression + self._commentText = commentText @property - def FileName(self): - return self._fileName + def PathExpression(self): + return self._pathExpression @classmethod def GetParser(cls): # match for optional whitespace token = yield - if isinstance(token, SpaceToken): token = yield - - # match for keyword: UCF - if (not isinstance(token, StringToken)): raise MismatchingParserResult("UcfParser: Expected UCF keyword.") - if (token.Value.lower() != "ucf"): raise MismatchingParserResult("UcfParser: Expected UCF keyword.") - + if isinstance(token, SpaceToken): token = yield + # match for keyword: __PARSER_KEYWORD__ + if (not isinstance(token, StringToken)): raise MismatchingParserResult(cls.__PARSER_NAME__ + ": Expected UCF keyword.") + if (token.Value.lower() != cls.__PARSER_KEYWORD__): raise MismatchingParserResult(cls.__PARSER_NAME__ + ": Expected UCF keyword.") # match for whitespace token = yield - if (not isinstance(token, SpaceToken)): raise MismatchingParserResult("UcfParser: Expected whitespace before UCF fileName.") + if (not isinstance(token, SpaceToken)): raise MismatchingParserResult(cls.__PARSER_NAME__ + ": Expected whitespace before UCF fileName.") - # match for delimiter sign: " - token = yield - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("UcfParser: Expected double quote sign before UCF fileName.") - if (token.Value.lower() != "\""): raise MismatchingParserResult("UcfParser: Expected double quote sign before UCF fileName.") - - # match for string: fileName - fileName = "" - while True: + # match for string: fileName; use a StringLiteralParser to parse the pattern + parser = PathExpressions.GetParser() + parser.send(None) + pathExpression = None + try: + while True: + token = yield + parser.send(token) + except GreedyMatchingParserResult as ex: + pathExpression = ex.value + except MatchingParserResult as ex: + pathExpression = ex.value token = yield - if (isinstance(token, CharacterToken) and (token.Value == "\"")): break - fileName += token.Value # match for optional whitespace - token = yield - if isinstance(token, SpaceToken): token = yield - + if isinstance(token, SpaceToken): token = yield # match for delimiter sign: \n commentText = "" - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("UcfParser: Expected end of line or comment") + if (not isinstance(token, CharacterToken)): raise MismatchingParserResult(cls.__PARSER_NAME__ + ": Expected end of line or comment") if (token.Value == "\n"): pass elif (token.Value == "#"): @@ -300,121 +510,177 @@ def GetParser(cls): if (isinstance(token, CharacterToken) and (token.Value == "\n")): break commentText += token.Value else: - raise MismatchingParserResult("UcfParser: Expected end of line or comment") + raise MismatchingParserResult(cls.__PARSER_NAME__ + ": Expected end of line or comment") # construct result - result = cls(fileName, commentText) + result = cls(pathExpression, commentText) raise MatchingParserResult(result) def __str__(self, indent=0): - return "{0}UCF \"{1}\"".format(" " * indent, self._fileName) + return "{indent}{kw} {filename!s}".format(indent=" " * indent, kw=self.__PARSER_KEYWORD__, filename=self._pathExpression) + + +class LDCStatement(ConstraintStatement): + __PARSER_NAME__ = "LdcParser" + __PARSER_KEYWORD__ = "ldc" -class XdcStatement(Statement): - def __init__(self, fileName, commentText): +class SDCStatement(ConstraintStatement): + __PARSER_NAME__ = "SdcParser" + __PARSER_KEYWORD__ = "sdc" + + +class UCFStatement(ConstraintStatement): + __PARSER_NAME__ = "UcfParser" + __PARSER_KEYWORD__ = "ucf" + + +class XDCStatement(ConstraintStatement): + __PARSER_NAME__ = "XdcParser" + __PARSER_KEYWORD__ = "xdc" + + +class InterpolateLiteral(Literal): + def __init__(self, sectionName, optionName): super().__init__() - self._fileName = fileName - self._commentText = commentText + self._sectionName = sectionName + self._optionName = optionName + + @property + def SectionName(self): + return self._sectionName @property - def FileName(self): - return self._fileName + def OptionName(self): + return self._optionName @classmethod def GetParser(cls): - # match for optional whitespace - token = yield - if isinstance(token, SpaceToken): token = yield - - # match for keyword: XDC - if (not isinstance(token, StringToken)): raise MismatchingParserResult("XdcParser: Expected XDC keyword.") - if (token.Value.lower() != "xdc"): raise MismatchingParserResult("XdcParser: Expected XDC keyword.") + if DEBUG: print("init InterpolateLiteralParser") - # match for whitespace + # match for opening ${ token = yield - if (not isinstance(token, SpaceToken)): raise MismatchingParserResult("XdcParser: Expected whitespace before XDC fileName.") - - # match for delimiter sign: " + if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("InterpolateLiteralParser: ") + if (token.Value != "$"): raise MismatchingParserResult("InterpolateLiteralParser: ") token = yield - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("XdcParser: Expected double quote sign before XDC fileName.") - if (token.Value.lower() != "\""): raise MismatchingParserResult("XdcParser: Expected double quote sign before XDC fileName.") + if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("InterpolateLiteralParser: ") + if (token.Value != "{"): raise MismatchingParserResult("InterpolateLiteralParser: ") - # match for string: fileName - fileName = "" + # match for interpolate value + value = {False: "", True: ""} + foundDelimiter = False while True: token = yield - if (isinstance(token, CharacterToken) and (token.Value == "\"")): break - fileName += token.Value - - # match for optional whitespace - token = yield - if isinstance(token, SpaceToken): token = yield + if isinstance(token, CharacterToken): + if (token.Value == ":"): + if (foundDelimiter == False): + foundDelimiter = True + else: + raise MismatchingParserResult("InterpolateLiteralParser: ") + elif (token.Value == "}"): + break + elif (token.Value in "._-"): + value[foundDelimiter] += token.Value + else: + raise MismatchingParserResult("InterpolateLiteralParser: ") + elif isinstance(token, (StringToken, NumberToken)): + value[foundDelimiter] += token.Value + else: + raise MismatchingParserResult("InterpolateLiteralParser: ") - # match for delimiter sign: \n - commentText = "" - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("XdcParser: Expected end of line or comment") - if (token.Value == "\n"): - pass - elif (token.Value == "#"): - # match for any until line end - while True: - token = yield - if (isinstance(token, CharacterToken) and (token.Value == "\n")): break - commentText += token.Value + if (foundDelimiter == True): + sectionName = value[False] + optionName = value[True] else: - raise MismatchingParserResult("XdcParser: Expected end of line or comment") + sectionName = None + optionName = value[False] # construct result - result = cls(fileName, commentText) + result = cls(sectionName, optionName) + if DEBUG: print("InterpolateLiteralParser: matched {0}".format(result)) raise MatchingParserResult(result) - def __str__(self, indent=0): - return "{0}XDC \"{1}\"".format(" " * indent, self._fileName) + def __str__(self): + if (self._sectionName is None): + return "${{{optionName}}}".format(optionName=self._optionName) + else: + return "${{{sectionName}:{optionName}}}".format(sectionName=self._sectionName, optionName=self._optionName) -class SdcStatement(Statement): - def __init__(self, fileName, commentText): +PathExpressions.AddChoice(Identifier) +PathExpressions.AddChoice(StringLiteral) +PathExpressions.AddChoice(InterpolateLiteral) +PathExpressions.AddChoice(SubDirectoryExpression) +PathExpressions.AddChoice(ConcatenateExpression) + + +class PathStatement(Statement): + def __init__(self, variable, pathExpression, commentText): super().__init__() - self._fileName = fileName - self._commentText = commentText + self._variable = variable + self._pathExpression = pathExpression + self._commentText = commentText @property - def FileName(self): - return self._fileName + def Variable(self): + return self._variable - @classmethod + @property + def PathExpression(self): + return self._pathExpression + + @classmethod # mccabe:disable=MC0001 def GetParser(cls): # match for optional whitespace token = yield - if isinstance(token, SpaceToken): token = yield - - # match for keyword: SDC - if (not isinstance(token, StringToken)): raise MismatchingParserResult("SdcParser: Expected SDC keyword.") - if (token.Value.lower() != "sdc"): raise MismatchingParserResult("SdcParser: Expected SDC keyword.") - + if isinstance(token, SpaceToken): token = yield + # match for keyword: path + if (not isinstance(token, StringToken)): raise MismatchingParserResult("PathParser: Expected UCF keyword.") + if (token.Value.lower() != "path"): raise MismatchingParserResult("PathParser: Expected UCF keyword.") # match for whitespace token = yield - if (not isinstance(token, SpaceToken)): raise MismatchingParserResult("SdcParser: Expected whitespace before SDC fileName.") + if (not isinstance(token, SpaceToken)): raise MismatchingParserResult("PathParser: Expected whitespace before variable.") + # match for identifier: variable + parser = Identifier.GetParser() + parser.send(None) + variable = None + try: + while True: + token = yield + parser.send(token) + except GreedyMatchingParserResult as ex: + variable = ex.value.Name + except MatchingParserResult as ex: + variable = ex.value.Name + token = yield - # match for delimiter sign: " + # match for optional whitespace + if isinstance(token, SpaceToken): token = yield + # match for delimiter sign: = + if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("PathParser: Expected '=' sign before expression.") + if (token.Value.lower() != "="): raise MismatchingParserResult("PathParser: Expected '=' sign before expression.") + # match for optional whitespace token = yield - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("SdcParser: Expected double quote sign before SDC fileName.") - if (token.Value.lower() != "\""): raise MismatchingParserResult("SdcParser: Expected double quote sign before SDC fileName.") + if isinstance(token, SpaceToken): token = yield - # match for string: fileName - fileName = "" - while True: + # match for expression + # ========================================================================== + parser = PathExpressions.GetParser() + parser.send(None) + pathExpression = None + try: + while True: + parser.send(token) + token = yield + except GreedyMatchingParserResult as ex: + pathExpression = ex.value + except MatchingParserResult as ex: + pathExpression = ex.value token = yield - if (isinstance(token, CharacterToken) and (token.Value == "\"")): break - fileName += token.Value - - # match for optional whitespace - token = yield - if isinstance(token, SpaceToken): token = yield # match for delimiter sign: \n commentText = "" - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("SdcParser: Expected end of line or comment") + if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("PathParser: Expected end of line or comment") if (token.Value == "\n"): pass elif (token.Value == "#"): @@ -424,59 +690,57 @@ def GetParser(cls): if (isinstance(token, CharacterToken) and (token.Value == "\n")): break commentText += token.Value else: - raise MismatchingParserResult("SdcParser: Expected end of line or comment") + raise MismatchingParserResult("PathParser: Expected end of line or comment") # construct result - result = cls(fileName, commentText) + result = cls(variable, pathExpression, commentText) raise MatchingParserResult(result) def __str__(self, indent=0): - return "{0}Cocotb \"{1}\"".format(" " * indent, self._fileName) + return "{indent}Path {var} := {expr!s}".format(indent=" " * indent, var=self._variable, expr=self._pathExpression) + __repr__ = __str__ class ReportStatement(Statement): def __init__(self, message, commentText): super().__init__() - self._message = message - self._commentText = commentText - + self._message = message + self._commentText = commentText + @property def Message(self): return self._message - + @classmethod def GetParser(cls): # match for optional whitespace token = yield - if isinstance(token, SpaceToken): token = yield - + if isinstance(token, SpaceToken): token = yield # match for keyword: VERILOG if (not isinstance(token, StringToken)): raise MismatchingParserResult("ReportParser: Expected REPORT keyword.") - if (token.Value.lower() != "report"): raise MismatchingParserResult("ReportParser: Expected REPORT keyword.") - + if (token.Value.lower() != "report"): raise MismatchingParserResult("ReportParser: Expected REPORT keyword.") # match for whitespace token = yield - if (not isinstance(token, SpaceToken)): raise MismatchingParserResult("ReportParser: Expected whitespace before report message.") - - # match for delimiter sign: " - token = yield - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("ReportParser: Expected double quote sign before report message.") - if (token.Value.lower() != "\""): raise MismatchingParserResult("ReportParser: Expected double quote sign before report message.") - - # match for string: message - message = "" - while True: - token = yield - if (isinstance(token, CharacterToken) and (token.Value == "\"")): break - message += token.Value + if (not isinstance(token, SpaceToken)): raise MismatchingParserResult("ReportParser: Expected whitespace before report message.") + + # match for string: fileName; use a StringLiteralParser to parse the pattern + parser = StringLiteral.GetParser() + parser.send(None) + + message = None + try: + while True: + token = yield + parser.send(token) + except MatchingParserResult as ex: + message = ex.value.Value # match for optional whitespace token = yield - if isinstance(token, SpaceToken): token = yield - + if isinstance(token, SpaceToken): token = yield # match for delimiter sign: \n commentText = "" - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("ReportParser: Expected end of line or comment") + if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("ReportParser: Expected end of line or comment") if (token.Value == "\n"): pass elif (token.Value == "#"): @@ -487,43 +751,41 @@ def GetParser(cls): commentText += token.Value else: raise MismatchingParserResult("ReportParser: Expected end of line or comment") - + # construct result result = cls(message, commentText) raise MatchingParserResult(result) - + def __str__(self, indent=0): - return "{0}report \"{1}\"".format(" " * indent, self._message) + return "{0}Report \"{1}\"".format(" " * indent, self._message) class LibraryStatement(Statement): - def __init__(self, library, directoryName, commentText): + def __init__(self, library, pathExpression, commentText): super().__init__() - self._library = library - self._directoryName = directoryName - self._commentText = commentText - + self._library = library + self._pathExpression = pathExpression + self._commentText = commentText + @property def Library(self): return self._library - + @property - def DirectoryName(self): - return self._directoryName - - @classmethod + def PathExpression(self): + return self._pathExpression + + @classmethod # mccabe:disable=MC0001 def GetParser(cls): # match for optional whitespace token = yield - if isinstance(token, SpaceToken): token = yield - + if isinstance(token, SpaceToken): token = yield + # match for keyword: LIBRARY if (not isinstance(token, StringToken)): raise MismatchingParserResult("LibraryParser: Expected LIBRARY keyword.") if (token.Value.lower() != "library"): raise MismatchingParserResult("LibraryParser: Expected LIBRARY keyword.") - # match for whitespace token = yield - if (not isinstance(token, SpaceToken)): raise MismatchingParserResult("LibraryParser: Expected whitespace before LIBRARY library name.") - + if (not isinstance(token, SpaceToken)): raise MismatchingParserResult("LibraryParser: Expected whitespace before LIBRARY library name.") # match for library name library = "" while True: @@ -536,29 +798,28 @@ def GetParser(cls): library += token.Value else: break - # match for whitespace - if (not isinstance(token, SpaceToken)): raise MismatchingParserResult("LibraryParser: Expected whitespace before LIBRARY directoryName.") - - # match for delimiter sign: " - token = yield - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("LibraryParser: Expected double quote sign before LIBRARY directoryName.") - if (token.Value.lower() != "\""): raise MismatchingParserResult("LibraryParser: Expected double quote sign before LIBRARY directoryName.") - - # match for string: directoryName - directoryName = "" - while True: + if (not isinstance(token, SpaceToken)): raise MismatchingParserResult("LibraryParser: Expected whitespace before LIBRARY directoryName.") + + # match for string: fileName; use a StringLiteralParser to parse the pattern + parser = PathExpressions.GetParser() + parser.send(None) + pathExpression = None + try: + while True: + token = yield + parser.send(token) + except GreedyMatchingParserResult as ex: + pathExpression = ex.value + except MatchingParserResult as ex: + pathExpression = ex.value token = yield - if (isinstance(token, CharacterToken) and (token.Value == "\"")): break - directoryName += token.Value # match for optional whitespace - token = yield - if isinstance(token, SpaceToken): token = yield - + if isinstance(token, SpaceToken): token = yield # match for delimiter sign: \n commentText = "" - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("LibraryParser: Expected end of line or comment") + if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("LibraryParser: Expected end of line or comment") if (token.Value == "\n"): pass elif (token.Value == "#"): @@ -569,56 +830,56 @@ def GetParser(cls): commentText += token.Value else: raise MismatchingParserResult("LibraryParser: Expected end of line or comment") - + # construct result - result = cls(library, directoryName, commentText) + result = cls(library, pathExpression, commentText) raise MatchingParserResult(result) - + def __str__(self, indent=0): - return "{0}Library {1} \"{2}\"".format(" " * indent, self._library, self._directoryName) + return "{0}Library {1} {2!s}".format(" " * indent, self._library, self._pathExpression) class IncludeStatement(Statement): - def __init__(self, fileName, commentText): + def __init__(self, pathExpression, commentText): super().__init__() - self._fileName = fileName - self._commentText = commentText - + self._pathExpression = pathExpression + self._commentText = commentText + @property - def FileName(self): - return self._fileName - + def PathExpression(self): + return self._pathExpression + @classmethod def GetParser(cls): # match for optional whitespace token = yield - if isinstance(token, SpaceToken): token = yield - + if isinstance(token, SpaceToken): token = yield + # match for keyword: INCLUDE if (not isinstance(token, StringToken)): raise MismatchingParserResult("IncludeParser: Expected INCLUDE keyword.") if (token.Value.lower() != "include"): raise MismatchingParserResult("IncludeParser: Expected INCLUDE keyword.") - # match for whitespace token = yield - if (not isinstance(token, SpaceToken)): raise MismatchingParserResult("IncludeParser: Expected whitespace before INCLUDE fileName.") - - # match for delimiter sign: " - token = yield - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("IncludeParser: Expected double quote sign before include fileName.") - if (token.Value.lower() != "\""): raise MismatchingParserResult("IncludeParser: Expected double quote sign before include fileName.") - - # match for string: fileName - fileName = "" - while True: + if (not isinstance(token, SpaceToken)): raise MismatchingParserResult("IncludeParser: Expected whitespace before INCLUDE fileName.") + + # match for string: fileName; use a StringLiteralParser to parse the pattern + parser = PathExpressions.GetParser() + parser.send(None) + pathExpression = None + try: + while True: + token = yield + parser.send(token) + except GreedyMatchingParserResult as ex: + pathExpression = ex.value + except MatchingParserResult as ex: + pathExpression = ex.value token = yield - if (isinstance(token, CharacterToken) and (token.Value == "\"")): break - fileName += token.Value # match for optional whitespace - token = yield - if isinstance(token, SpaceToken): token = yield + if isinstance(token, SpaceToken): token = yield # match for delimiter sign: \n commentText = "" - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("IncludeParser: Expected end of line or comment") + if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("IncludeParser: Expected end of line or comment") if (token.Value == "\n"): pass elif (token.Value == "#"): @@ -629,13 +890,13 @@ def GetParser(cls): commentText += token.Value else: raise MismatchingParserResult("IncludeParser: Expected end of line or comment") - + # construct result - result = cls(fileName, commentText) + result = cls(pathExpression, commentText) raise MatchingParserResult(result) - + def __str__(self, indent=0): - return "{0}Include \"{1}\"".format(" " * indent, self._fileName) + return "{0}Include {1!s}".format(" " * indent, self._pathExpression) # ============================================================================== # Conditional Statements @@ -643,28 +904,27 @@ def __str__(self, indent=0): class IfStatement(ConditionalBlockStatement): def __init__(self, expression, commentText): super().__init__(expression) - self._commentText = commentText + self._commentText = commentText - @classmethod + @classmethod # mccabe:disable=MC0001 def GetParser(cls): # match for IF clause # ========================================================================== # match for optional whitespace token = yield - if isinstance(token, SpaceToken): token = yield - + if isinstance(token, SpaceToken): token = yield + # match for keyword: IF if (not isinstance(token, StringToken)): raise MismatchingParserResult() - if (token.Value.lower() != "if"): raise MismatchingParserResult() - + if (token.Value.lower() != "if"): raise MismatchingParserResult() # match for whitespace token = yield - if (not isinstance(token, SpaceToken)): raise MismatchingParserResult() - + if (not isinstance(token, SpaceToken)): raise MismatchingParserResult() + # match for expression # ========================================================================== - parser = Expressions.GetParser() + parser = IfThenElseExpressions.GetParser() parser.send(None) - + expressionRoot = None try: while True: @@ -672,23 +932,20 @@ def GetParser(cls): parser.send(token) except MatchingParserResult as ex: expressionRoot = ex.value - + # match for whitespace token = yield - if (not isinstance(token, SpaceToken)): raise MismatchingParserResult() - + if (not isinstance(token, SpaceToken)): raise MismatchingParserResult() # match for keyword: THEN token = yield if (not isinstance(token, StringToken)): raise MismatchingParserResult() - if (token.Value.lower() != "then"): raise MismatchingParserResult() - + if (token.Value.lower() != "then"): raise MismatchingParserResult() # match for optional whitespace token = yield - if isinstance(token, SpaceToken): token = yield - + if isinstance(token, SpaceToken): token = yield # match for delimiter sign: \n commentText = "" - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("IfStatementParser: Expected end of line or comment") + if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("IfStatementParser: Expected end of line or comment") if (token.Value == "\n"): pass elif (token.Value == "#"): @@ -699,14 +956,14 @@ def GetParser(cls): commentText += token.Value else: raise MismatchingParserResult("IfStatementParser: Expected end of line or comment") - + # match for inner statements # ========================================================================== # construct result result = cls(expressionRoot, commentText) parser = cls.GetRepeatParser(result.AddStatement, BlockedStatement.GetParser) parser.send(None) - + try: while True: token = yield @@ -715,38 +972,36 @@ def GetParser(cls): raise MatchingParserResult(result) def __str__(self, indent=0): - _indent = " " * indent - buffer = _indent + "IfStatement " + self._expression.__str__() + buffer = (" " * indent) + "IfClause " + self._expression.__str__() for stmt in self._statements: - buffer += "\n{0}{1}".format(_indent, stmt.__str__(indent + 1)) + buffer += "\n{0}".format(stmt.__str__(indent + 1)) return buffer class ElseIfStatement(ConditionalBlockStatement): def __init__(self, expression, commentText): super().__init__(expression) - self._commentText = commentText + self._commentText = commentText - @classmethod + @classmethod # mccabe:disable=MC0001 def GetParser(cls): # match for multiple ELSEIF clauses # ========================================================================== token = yield # match for optional whitespace - if isinstance(token, SpaceToken): token = yield - + if isinstance(token, SpaceToken): token = yield # match for keyword: ELSEIF if (not isinstance(token, StringToken)): raise MismatchingParserResult() - if (token.Value.lower() != "elseif"): raise MismatchingParserResult() + if (token.Value.lower() != "elseif"): raise MismatchingParserResult() # match for whitespace token = yield - if (not isinstance(token, SpaceToken)): raise MismatchingParserResult() - + if (not isinstance(token, SpaceToken)): raise MismatchingParserResult() + # match for expression # ========================================================================== - parser = Expressions.GetParser() + parser = IfThenElseExpressions.GetParser() parser.send(None) - + expressionRoot = None try: while True: @@ -754,16 +1009,14 @@ def GetParser(cls): parser.send(token) except MatchingParserResult as ex: expressionRoot = ex.value - + # match for whitespace token = yield - if (not isinstance(token, SpaceToken)): raise MismatchingParserResult() - + if (not isinstance(token, SpaceToken)): raise MismatchingParserResult() # match for keyword: THEN token = yield if (not isinstance(token, StringToken)): raise MismatchingParserResult() - if (token.Value.lower() != "then"): raise MismatchingParserResult() - + if (token.Value.lower() != "then"): raise MismatchingParserResult() # match for optional whitespace token = yield if isinstance(token, SpaceToken): token = yield @@ -780,14 +1033,14 @@ def GetParser(cls): commentText += token.Value else: raise MismatchingParserResult("ElseIfStatementParser: Expected end of line or comment") - + # match for inner statements # ========================================================================== # construct result result = cls(expressionRoot, commentText) parser = cls.GetRepeatParser(result.AddStatement, BlockedStatement.GetParser) parser.send(None) - + try: while True: token = yield @@ -796,17 +1049,16 @@ def GetParser(cls): raise MatchingParserResult(result) def __str__(self, indent=0): - _indent = " " * indent - buffer = _indent + "ElseIfStatement" + self._expression.__str__() + buffer = (" " * indent) + "ElseIfClause" + self._expression.__str__() for stmt in self._statements: - buffer += "\n{0}{1}".format(_indent, stmt.__str__(indent + 1)) + buffer += "\n{0}".format(stmt.__str__(indent + 1)) return buffer class ElseStatement(BlockStatement): def __init__(self, commentText): super().__init__() - self._commentText = commentText + self._commentText = commentText @classmethod def GetParser(cls): @@ -814,18 +1066,16 @@ def GetParser(cls): # ========================================================================== # match for optional whitespace token = yield - if isinstance(token, SpaceToken): token = yield - + if isinstance(token, SpaceToken): token = yield # match for keyword: ELSE if (not isinstance(token, StringToken)): raise MismatchingParserResult() - if (token.Value.lower() != "else"): raise MismatchingParserResult() - + if (token.Value.lower() != "else"): raise MismatchingParserResult() # match for optional whitespace token = yield - if isinstance(token, SpaceToken): token = yield + if isinstance(token, SpaceToken): token = yield # match for delimiter sign: \n commentText = "" - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("ElseStatementParser: Expected end of line or comment") + if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("ElseStatementParser: Expected end of line or comment") if (token.Value == "\n"): pass elif (token.Value == "#"): @@ -836,14 +1086,14 @@ def GetParser(cls): commentText += token.Value else: raise MismatchingParserResult("ElseStatementParser: Expected end of line or comment") - + # match for inner statements # ========================================================================== # construct result result = cls(commentText) parser = cls.GetRepeatParser(result.AddStatement, BlockedStatement.GetParser) parser.send(None) - + try: while True: token = yield @@ -852,10 +1102,9 @@ def GetParser(cls): raise MatchingParserResult(result) def __str__(self, indent=0): - _indent = " " * indent - buffer = _indent + "ElseStatement" + buffer = (" " * indent) + "ElseClause" for stmt in self._statements: - buffer += "\n{0}{1}".format(_indent, stmt.__str__(indent + 1)) + buffer += "\n{0}".format(stmt.__str__(indent + 1)) return buffer @@ -863,7 +1112,7 @@ class IfElseIfElseStatement(Statement): def __init__(self): super().__init__() self._ifClause = None - self._elseIfClauses = None + self._elseIfClauses = None self._elseClause = None @property @@ -879,11 +1128,11 @@ def ElseClause(self): return self._elseClause @ElseClause.setter def ElseClause(self, value): self._elseClause = value - @classmethod + @classmethod # mccabe:disable=MC0001 def GetParser(cls): # construct result result = cls() - + # match for IF clause # ========================================================================== parser = IfStatement.GetParser() @@ -894,14 +1143,14 @@ def GetParser(cls): parser.send(token) except MatchingParserResult as ex: result.IfClause = ex.value - + # match for multiple ELSEIF clauses # ========================================================================== try: while True: parser = ElseIfStatement.GetParser() parser.send(None) - + try: parser.send(token) while True: @@ -919,7 +1168,7 @@ def GetParser(cls): # match for inner statements parser = ElseStatement.GetParser() parser.send(None) - + try: parser.send(token) while True: @@ -933,27 +1182,23 @@ def GetParser(cls): # match for END IF clause # ========================================================================== # match for optional whitespace - if isinstance(token, SpaceToken): token = yield - + if isinstance(token, SpaceToken): token = yield # match for keyword: END if (not isinstance(token, StringToken)): raise MismatchingParserResult() if (token.Value.lower() != "end"): raise MismatchingParserResult() - # match for whitespace token = yield - if (not isinstance(token, SpaceToken)): raise MismatchingParserResult() - + if (not isinstance(token, SpaceToken)): raise MismatchingParserResult() # match for keyword: IF token = yield if (not isinstance(token, StringToken)): raise MismatchingParserResult() - if (token.Value.lower() != "if"): raise MismatchingParserResult() - + if (token.Value.lower() != "if"): raise MismatchingParserResult() # match for optional whitespace token = yield - if isinstance(token, SpaceToken): token = yield + if isinstance(token, SpaceToken): token = yield # match for delimiter sign: \n # commentText = "" - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("IfElseIfElseStatementParser: Expected end of line or comment") + if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("IfElseIfElseStatementParser: Expected end of line or comment") if (token.Value == "\n"): pass elif (token.Value == "#"): @@ -964,9 +1209,9 @@ def GetParser(cls): # commentText += token.Value else: raise MismatchingParserResult("IfElseIfElseStatementParser: Expected end of line or comment") - + raise MatchingParserResult(result) - + def __str__(self, indent=0): _indent = " " * indent buffer = _indent + "IfElseIfElseStatement\n" @@ -978,21 +1223,25 @@ def __str__(self, indent=0): buffer += "\n" + self.ElseClause.__str__(indent + 1) return buffer - + class Document(BlockStatement): @classmethod def GetParser(cls): result = cls() parser = cls.GetRepeatParser(result.AddStatement, BlockedStatement.GetParser) parser.send(None) - + + token = yield + if (not isinstance(token, StartOfDocumentToken)): + raise MismatchingParserResult("Expected a StartOfDocumentToken, got {0!s}.".format(token)) + try: while True: token = yield parser.send(token) except MatchingParserResult: raise MatchingParserResult(result) - + def __str__(self, indent=0): buffer = " " * indent + "Document" for stmt in self._statements: @@ -1003,10 +1252,12 @@ def __str__(self, indent=0): BlockedStatement.AddChoice(LibraryStatement) BlockedStatement.AddChoice(VHDLStatement) BlockedStatement.AddChoice(VerilogStatement) -BlockedStatement.AddChoice(UcfStatement) -BlockedStatement.AddChoice(XdcStatement) -BlockedStatement.AddChoice(SdcStatement) BlockedStatement.AddChoice(CocotbStatement) +BlockedStatement.AddChoice(LDCStatement) +BlockedStatement.AddChoice(SDCStatement) +BlockedStatement.AddChoice(UCFStatement) +BlockedStatement.AddChoice(XDCStatement) +BlockedStatement.AddChoice(PathStatement) BlockedStatement.AddChoice(ReportStatement) BlockedStatement.AddChoice(IfElseIfElseStatement) BlockedStatement.AddChoice(CommentLine) diff --git a/py/Parser/FilesParser.py b/py/Parser/FilesParser.py index 68f41c2c..c293b6e7 100644 --- a/py/Parser/FilesParser.py +++ b/py/Parser/FilesParser.py @@ -1,13 +1,13 @@ # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2; replace-tabs off; indent-width 2; -# +# # ============================================================================== # Authors: Patrick Lehmann # Martin Zabel # # Python Module: TODO -# +# # Description: # ------------------------------------ # TODO: @@ -16,13 +16,13 @@ # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany # Chair for VLSI-Design, Diagnostics and Architecture -# +# # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at -# +# # http://www.apache.org/licenses/LICENSE-2.0 -# +# # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -30,18 +30,20 @@ # limitations under the License. # ============================================================================== # - -from lib.Parser import AndExpression, OrExpression, XorExpression, NotExpression, InExpression, NotInExpression -from lib.Parser import EqualExpression, UnequalExpression, LessThanExpression, LessThanEqualExpression, GreaterThanExpression, GreaterThanEqualExpression -from lib.Parser import ExistsFunction, ListConstructorExpression +from lib.Functions import Init from lib.Parser import ParserException -from lib.Parser import StringLiteral, IntegerLiteral, Identifier -from Parser.FilesCodeDOM import Document +from lib.CodeDOM import AndExpression, OrExpression, XorExpression, NotExpression, InExpression, NotInExpression +from lib.CodeDOM import EqualExpression, UnequalExpression, LessThanExpression, LessThanEqualExpression, GreaterThanExpression, GreaterThanEqualExpression +from lib.CodeDOM import StringLiteral, IntegerLiteral, Identifier +from Parser.FilesCodeDOM import Document, InterpolateLiteral, SubDirectoryExpression, ConcatenateExpression +from Parser.FilesCodeDOM import ExistsFunction, ListConstructorExpression, PathStatement from Parser.FilesCodeDOM import IfElseIfElseStatement, ReportStatement from Parser.FilesCodeDOM import IncludeStatement, LibraryStatement -from Parser.FilesCodeDOM import UcfStatement, XdcStatement, SdcStatement +from Parser.FilesCodeDOM import LDCStatement, SDCStatement, UCFStatement, XDCStatement from Parser.FilesCodeDOM import VHDLStatement, VerilogStatement, CocotbStatement +# to print the reconstructed files file after parsing, set DEBUG to True +DEBUG = not True class FileReference: def __init__(self, file): @@ -83,37 +85,42 @@ def __str__(self): return "Cocotb file: '{0!s}'".format(self._file) -class UcfSourceFileMixIn(FileReference): +class LDCSourceFileMixIn(FileReference): def __str__(self): - return "UCF file: '{0!s}'".format(self._file) + return "LDC file: '{0!s}'".format(self._file) -class XdcSourceFileMixIn(FileReference): +class SDCSourceFileMixIn(FileReference): def __str__(self): - return "XDC file: '{0!s}'".format(self._file) + return "SDC file: '{0!s}'".format(self._file) -class SdcSourceFileMixIn(FileReference): +class UCFSourceFileMixIn(FileReference): def __str__(self): - return "SDC file: '{0!s}'".format(self._file) + return "UCF file: '{0!s}'".format(self._file) + + +class XDCSourceFileMixIn(FileReference): + def __str__(self): + return "XDC file: '{0!s}'".format(self._file) class VHDLLibraryReference: def __init__(self, name, path): self._name = name.lower() self._path = path - + @property def Name(self): return self._name - + @property def Path(self): return self._path - + def __str__(self): return "VHDL library: {0} in '{1}'".format(self._name, str(self._path)) - + __repr__ = __str__ @@ -122,61 +129,78 @@ class FilesParserMixIn: _classVHDLSourceFile = VHDLSourceFileMixIn _classVerilogSourceFile = VerilogSourceFileMixIn _classCocotbSourceFile = CocotbSourceFileMixIn - _classUcfSourceFile = UcfSourceFileMixIn - _classXdcSourceFile = XdcSourceFileMixIn - _classSdcSourceFile = SdcSourceFileMixIn + _classLDCSourceFile = LDCSourceFileMixIn + _classSDCSourceFile = SDCSourceFileMixIn + _classUCFSourceFile = UCFSourceFileMixIn + _classXDCSourceFile = XDCSourceFileMixIn def __init__(self): - self._rootDirectory = None + self._rootDirectory = None self._document = None - - self._files = [] + + self._files = [] self._includes = [] - self._libraries = [] + self._libraries = [] self._warnings = [] - + def _Parse(self): self._ReadContent() #only available via late binding - self._document = Document.parse(self._content, printChar=not True) #self._content only available via late binding - # print(Fore.LIGHTBLACK_EX + str(self._document) + Fore.RESET) - - def _Resolve(self, statements=None): - # print("Resolving {0}".format(str(self._file))) + self._document = Document.Parse(self._content, printChar=not True) #self._content only available via late binding + + if DEBUG: + print("{DARK_GRAY}{line}{NOCOLOR}".format(line="*"*80, **Init.Foreground)) + print("{DARK_GRAY}{doc!s}{NOCOLOR}".format(doc=self._document, **Init.Foreground)) + print("{DARK_GRAY}{line}{NOCOLOR}".format(line="*"*80, **Init.Foreground)) + + # FIXME: is there a better way to passthrough/access host? + def _Resolve(self, host, statements=None): # mccabe:disable=MC0001 if (statements is None): statements = self._document.Statements - + for stmt in statements: if isinstance(stmt, VHDLStatement): - file = self._rootDirectory / stmt.FileName - vhdlSrcFile = self._classVHDLSourceFile(file, stmt.LibraryName) # stmt.Library, + path = self._EvaluatePath(host, stmt.PathExpression) + file = self._rootDirectory / path + vhdlSrcFile = self._classVHDLSourceFile(file, stmt.LibraryName) self._files.append(vhdlSrcFile) elif isinstance(stmt, VerilogStatement): - file = self._rootDirectory / stmt.FileName + path = self._EvaluatePath(host, stmt.PathExpression) + file = self._rootDirectory / path verilogSrcFile = self._classVerilogSourceFile(file) self._files.append(verilogSrcFile) elif isinstance(stmt, CocotbStatement): - file = self._rootDirectory / stmt.FileName + path = self._EvaluatePath(host, stmt.PathExpression) + file = self._rootDirectory / path cocotbSrcFile = self._classCocotbSourceFile(file) self._files.append(cocotbSrcFile) - elif isinstance(stmt, UcfStatement): - file = self._rootDirectory / stmt.FileName - ucfSrcFile = self._classCocotbSourceFile(file) + elif isinstance(stmt, LDCStatement): + path = self._EvaluatePath(host, stmt.PathExpression) + file = self._rootDirectory / path + ldcSrcFile = self._classLDCSourceFile(file) + self._files.append(ldcSrcFile) + elif isinstance(stmt, SDCStatement): + path = self._EvaluatePath(host, stmt.PathExpression) + file = self._rootDirectory / path + sdcSrcFile = self._classSDCSourceFile(file) + self._files.append(sdcSrcFile) + elif isinstance(stmt, UCFStatement): + path = self._EvaluatePath(host, stmt.PathExpression) + file = self._rootDirectory / path + ucfSrcFile = self._classUCFSourceFile(file) self._files.append(ucfSrcFile) - elif isinstance(stmt, XdcStatement): - file = self._rootDirectory / stmt.FileName - xdcSrcFile = self._classCocotbSourceFile(file) + elif isinstance(stmt, XDCStatement): + path = self._EvaluatePath(host, stmt.PathExpression) + file = self._rootDirectory / path + xdcSrcFile = self._classXDCSourceFile(file) self._files.append(xdcSrcFile) - elif isinstance(stmt, SdcStatement): - file = self._rootDirectory / stmt.FileName - sdcSrcFile = self._classCocotbSourceFile(file) - self._files.append(sdcSrcFile) elif isinstance(stmt, IncludeStatement): # add the include file to the fileset - file = self._rootDirectory / stmt.FileName + path = self._EvaluatePath(host, stmt.PathExpression) + file = self._rootDirectory / path includeFile = self._classFileListFile(file) #self._classFileListFile only available via late binding self._fileSet.AddFile(includeFile) #self._fileSet only available via late binding - includeFile.Parse() - + includeFile.Parse(host) + self._includes.append(includeFile) for srcFile in includeFile.Files: self._files.append(srcFile) @@ -185,75 +209,106 @@ def _Resolve(self, statements=None): for warn in includeFile.Warnings: self._warnings.append(warn) elif isinstance(stmt, LibraryStatement): - lib = self._rootDirectory / stmt.DirectoryName + path = self._EvaluatePath(host, stmt.PathExpression) + lib = self._rootDirectory / path vhdlLibRef = VHDLLibraryReference(stmt.Library, lib) self._libraries.append(vhdlLibRef) + elif isinstance(stmt, PathStatement): + path = self._EvaluatePath(host, stmt.PathExpression) + self._variables[stmt.Variable] = path elif isinstance(stmt, IfElseIfElseStatement): - exprValue = self._Evaluate(stmt.IfClause.Expression) + exprValue = self._Evaluate(host, stmt.IfClause.Expression) if (exprValue is True): - self._Resolve(stmt.IfClause.Statements) + self._Resolve(host, stmt.IfClause.Statements) elif (stmt.ElseIfClauses is not None): for elseif in stmt.ElseIfClauses: - exprValue = self._Evaluate(elseif.Expression) + exprValue = self._Evaluate(host, elseif.Expression) if (exprValue is True): - self._Resolve(elseif.Statements) + self._Resolve(host, elseif.Statements) break if ((exprValue is False) and (stmt.ElseClause is not None)): - self._Resolve(stmt.ElseClause.Statements) + self._Resolve(host, stmt.ElseClause.Statements) elif isinstance(stmt, ReportStatement): self._warnings.append("WARNING: {0}".format(stmt.Message)) else: - ParserException("Found unknown statement type '{0}'.".format(stmt.__class__.__name__)) - - def _Evaluate(self, expr): + ParserException("Found unknown statement type '{0!s}'.".format(type(stmt))) + + def _Evaluate(self, host, expr): # mccabe:disable=MC0001 if isinstance(expr, Identifier): try: return self._variables[expr.Name] #self._variables only available via late binding - except KeyError as ex: raise ParserException("Identifier '{0}' not found.".format(expr.Name)) from ex + except KeyError as ex: + raise ParserException("Identifier '{0}' not found.".format(expr.Name)) from ex elif isinstance(expr, StringLiteral): return expr.Value elif isinstance(expr, IntegerLiteral): return expr.Value elif isinstance(expr, ExistsFunction): - return (self._rootDirectory / expr.Path).exists() + path = self._EvaluatePath(host, expr.Expression) + return (self._rootDirectory / path).exists() elif isinstance(expr, ListConstructorExpression): - return [self._Evaluate(item) for item in expr.List] + return [self._Evaluate(host, item) for item in expr.List] elif isinstance(expr, NotExpression): - return not self._Evaluate(expr.Child) + return not self._Evaluate(host, expr.Child) elif isinstance(expr, InExpression): - return self._Evaluate(expr.LeftChild) in self._Evaluate(expr.RightChild) + return self._Evaluate(host, expr.LeftChild) in self._Evaluate(host, expr.RightChild) elif isinstance(expr, NotInExpression): - return self._Evaluate(expr.LeftChild) not in self._Evaluate(expr.RightChild) + return self._Evaluate(host, expr.LeftChild) not in self._Evaluate(host, expr.RightChild) elif isinstance(expr, AndExpression): - return self._Evaluate(expr.LeftChild) and self._Evaluate(expr.RightChild) + return self._Evaluate(host, expr.LeftChild) and self._Evaluate(host, expr.RightChild) elif isinstance(expr, OrExpression): - return self._Evaluate(expr.LeftChild) or self._Evaluate(expr.RightChild) + return self._Evaluate(host, expr.LeftChild) or self._Evaluate(host, expr.RightChild) elif isinstance(expr, XorExpression): - l = self._Evaluate(expr.LeftChild) - r = self._Evaluate(expr.RightChild) + l = self._Evaluate(host, expr.LeftChild) + r = self._Evaluate(host, expr.RightChild) return (not l and r) or (l and not r) elif isinstance(expr, EqualExpression): - return self._Evaluate(expr.LeftChild) == self._Evaluate(expr.RightChild) + return self._Evaluate(host, expr.LeftChild) == self._Evaluate(host, expr.RightChild) elif isinstance(expr, UnequalExpression): - return self._Evaluate(expr.LeftChild) != self._Evaluate(expr.RightChild) + return self._Evaluate(host, expr.LeftChild) != self._Evaluate(host, expr.RightChild) elif isinstance(expr, LessThanExpression): - return self._Evaluate(expr.LeftChild) < self._Evaluate(expr.RightChild) + return self._Evaluate(host, expr.LeftChild) < self._Evaluate(host, expr.RightChild) elif isinstance(expr, LessThanEqualExpression): - return self._Evaluate(expr.LeftChild) <= self._Evaluate(expr.RightChild) + return self._Evaluate(host, expr.LeftChild) <= self._Evaluate(host, expr.RightChild) elif isinstance(expr, GreaterThanExpression): - return self._Evaluate(expr.LeftChild) > self._Evaluate(expr.RightChild) + return self._Evaluate(host, expr.LeftChild) > self._Evaluate(host, expr.RightChild) elif isinstance(expr, GreaterThanEqualExpression): - return self._Evaluate(expr.LeftChild) >= self._Evaluate(expr.RightChild) - else: raise ParserException("Unsupported expression type '{0}'".format(type(expr))) + return self._Evaluate(host, expr.LeftChild) >= self._Evaluate(host, expr.RightChild) + else: + raise ParserException("Unsupported expression type '{0!s}'".format(type(expr))) + + def _EvaluatePath(self, host, expr): + if isinstance(expr, Identifier): + try: + return self._variables[expr.Name] # self._variables only available via late binding + except KeyError as ex: + raise ParserException("Identifier '{0}' not found.".format(expr.Name)) from ex + elif isinstance(expr, StringLiteral): + return expr.Value + elif isinstance(expr, IntegerLiteral): + return str(expr.Value) + elif isinstance(expr, InterpolateLiteral): + config = host.PoCConfig + return config.Interpolation.interpolate(config, "CONFIG.DirectoryNames", "xxxx", str(expr), {}) + elif isinstance(expr, SubDirectoryExpression): + l = self._EvaluatePath(host, expr.LeftChild) + r = self._EvaluatePath(host, expr.RightChild) + return l + "/" + r + elif isinstance(expr, ConcatenateExpression): + l = self._EvaluatePath(host, expr.LeftChild) + r = self._EvaluatePath(host, expr.RightChild) + return l + r + else: + raise ParserException("Unsupported path expression type '{0!s}'".format(type(expr))) @property def Files(self): return self._files @property def Includes(self): return self._includes - @property + @property def Libraries(self): return self._libraries @property def Warnings(self): return self._warnings def __str__(self): return "FILES file: '{0!s}'".format(self._file) #self._file only available via late binding - def __repr__(self): return self.__str__() + __repr__ = __str__ diff --git a/py/Parser/RulesCodeDOM.py b/py/Parser/RulesCodeDOM.py index 0bf3be20..831bb6a9 100644 --- a/py/Parser/RulesCodeDOM.py +++ b/py/Parser/RulesCodeDOM.py @@ -1,12 +1,12 @@ # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2; replace-tabs off; indent-width 2; -# +# # ============================================================================== # Authors: Patrick Lehmann # # Python Module: TODO -# +# # Description: # ------------------------------------ # TODO: @@ -15,13 +15,13 @@ # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany # Chair for VLSI-Design, Diagnostics and Architecture -# +# # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at -# +# # http://www.apache.org/licenses/LICENSE-2.0 -# +# # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -29,10 +29,10 @@ # limitations under the License. # ============================================================================== # -from lib.Parser import MismatchingParserResult, MatchingParserResult, EmptyChoiseParserResult -from lib.Parser import SpaceToken, CharacterToken, StringToken -from lib.Parser import Statement, BlockStatement -from Parser.CodeDOM import EmptyLine, CommentLine, BlockedStatement as BlockStatementBase +from lib.Parser import MismatchingParserResult, MatchingParserResult, EmptyChoiseParserResult, StartOfDocumentToken +from lib.Parser import SpaceToken, CharacterToken, StringToken +from lib.CodeDOM import EmptyLine, CommentLine, BlockedStatement as BlockStatementBase, StringLiteral +from lib.CodeDOM import Statement, BlockStatement # ============================================================================== @@ -58,61 +58,67 @@ class CopyStatement(Statement): def __init__(self, source, destination, commentText): super().__init__() self._sourcePath = source - self._destinationPath = destination - self._commentText = commentText + self._destinationPath = destination + self._commentText = commentText @property - def SourcePath(self): return self._sourcePath + def SourcePath(self): return self._sourcePath @property def DestinationPath(self): return self._destinationPath - - @classmethod + + @classmethod # mccabe:disable=MC0001 def GetParser(cls): # match for optional whitespacex token = yield - if isinstance(token, SpaceToken): token = yield + if isinstance(token, SpaceToken): token = yield # match for COPY keyword if (not isinstance(token, StringToken)): raise MismatchingParserResult("CopyParser: Expected COPY keyword.") - if (token.Value.lower() != "copy"): raise MismatchingParserResult("CopyParser: Expected COPY keyword.") + if (token.Value.lower() != "copy"): raise MismatchingParserResult("CopyParser: Expected COPY keyword.") # match for whitespace token = yield - if (not isinstance(token, SpaceToken)): raise MismatchingParserResult("CopyParser: Expected whitespace before source filename.") - # match for delimiter sign: " - token = yield - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("CopyParser: Expected double quote sign before source fileName.") - if (token.Value.lower() != "\""): raise MismatchingParserResult("CopyParser: Expected double quote sign before source fileName.") - # match for string: source filename - sourceFile = "" - while True: - token = yield - if (isinstance(token, CharacterToken) and (token.Value == "\"")): break - sourceFile += token.Value + if (not isinstance(token, SpaceToken)): raise MismatchingParserResult("CopyParser: Expected whitespace before source filename.") + + # match for string: sourceFile; use a StringLiteralParser to parse the pattern + parser = StringLiteral.GetParser() + parser.send(None) + + sourceFile = None + try: + while True: + token = yield + parser.send(token) + except MatchingParserResult as ex: + sourceFile = ex.value.Value + # match for whitespace token = yield - if (not isinstance(token, SpaceToken)): raise MismatchingParserResult("CopyParser: Expected whitespace before TO keyword.") + if (not isinstance(token, SpaceToken)): raise MismatchingParserResult("CopyParser: Expected whitespace before TO keyword.") # match for TO keyword token = yield if (not isinstance(token, StringToken)): raise MismatchingParserResult("CopyParser: Expected TO keyword.") - if (token.Value.lower() != "to"): raise MismatchingParserResult("CopyParser: Expected TO keyword.") + if (token.Value.lower() != "to"): raise MismatchingParserResult("CopyParser: Expected TO keyword.") # match for whitespace token = yield - if (not isinstance(token, SpaceToken)): raise MismatchingParserResult("CopyParser: Expected whitespace before destination directory.") - # match for delimiter sign: " - token = yield - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("CopyParser: Expected double quote sign before destination directory.") - if (token.Value.lower() != "\""): raise MismatchingParserResult("CopyParser: Expected double quote sign before destination directory.") - # match for string: fileName - destinationDirectory = "" - while True: - token = yield - if (isinstance(token, CharacterToken) and (token.Value == "\"")): break - destinationDirectory += token.Value + if (not isinstance(token, SpaceToken)): raise MismatchingParserResult("CopyParser: Expected whitespace before destination directory.") + + # match for string: destinationDirectory; use a StringLiteralParser to parse the pattern + parser = StringLiteral.GetParser() + parser.send(None) + + destinationDirectory = None + try: + while True: + token = yield + parser.send(token) + except MatchingParserResult as ex: + destinationDirectory = ex.value.Value + # match for optional whitespace token = yield - if isinstance(token, SpaceToken): token = yield + if isinstance(token, SpaceToken): token = yield # match for delimiter sign: \n commentText = "" - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("CopyParser: Expected end of line or comment") + if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("CopyParser: Expected end of line or comment") if (token.Value == "\n"): pass elif (token.Value == "#"): @@ -123,11 +129,11 @@ def GetParser(cls): commentText += token.Value else: raise MismatchingParserResult("CopyParser: Expected end of line or comment") - + # construct result result = cls(sourceFile, destinationDirectory, commentText) raise MatchingParserResult(result) - + def __str__(self, indent=0): if (self._commentText != ""): return "{0}Copy \"{1!s}\" To \"{2!s}\" # {3}".format((" " * indent), self._sourcePath, self._destinationPath, self._commentText) @@ -137,39 +143,42 @@ def __str__(self, indent=0): class DeleteStatement(Statement): def __init__(self, file, commentText): super().__init__() - self._filePath = file - self._commentText = commentText + self._filePath = file + self._commentText = commentText @property - def FilePath(self): return self._filePath + def FilePath(self): return self._filePath @classmethod def GetParser(cls): # match for optional whitespacex token = yield - if isinstance(token, SpaceToken): token = yield + if isinstance(token, SpaceToken): token = yield # match for DELETE keyword if (not isinstance(token, StringToken)): raise MismatchingParserResult("DeleteParser: Expected DELETE keyword.") - if (token.Value.lower() != "delete"): raise MismatchingParserResult("DeleteParser: Expected DELETE keyword.") + if (token.Value.lower() != "delete"): raise MismatchingParserResult("DeleteParser: Expected DELETE keyword.") # match for whitespace token = yield - if (not isinstance(token, SpaceToken)): raise MismatchingParserResult("DeleteParser: Expected whitespace before filename.") - # match for delimiter sign: " - token = yield - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("DeleteParser: Expected double quote sign before fileName.") - if (token.Value.lower() != "\""): raise MismatchingParserResult("DeleteParser: Expected double quote sign before fileName.") - # match for string: filename - file = "" - while True: - token = yield - if (isinstance(token, CharacterToken) and (token.Value == "\"")): break - file += token.Value - token = yield + if (not isinstance(token, SpaceToken)): raise MismatchingParserResult("DeleteParser: Expected whitespace before filename.") + + # match for string: file; use a StringLiteralParser to parse the pattern + parser = StringLiteral.GetParser() + parser.send(None) + + file = None + try: + while True: + token = yield + parser.send(token) + except MatchingParserResult as ex: + file = ex.value.Value + # match for optional whitespace - if isinstance(token, SpaceToken): token = yield + token = yield + if isinstance(token, SpaceToken): token = yield # match for delimiter sign: \n commentText = "" - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("DeleteParser: Expected end of line or comment") + if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("DeleteParser: Expected end of line or comment") if (token.Value == "\n"): pass elif (token.Value == "#"): @@ -195,110 +204,83 @@ def __str__(self, indent=0): class ReplaceStatement(Statement): def __init__(self, searchPattern, replacePattern, caseInsensitive, multiLine, dotAll, commentText): super().__init__() - self._searchPattern = searchPattern + self._searchPattern = searchPattern self._replacePattern = replacePattern - self._caseInsensitive = caseInsensitive - self._multiLine = multiLine + self._caseInsensitive = caseInsensitive + self._multiLine = multiLine self._dotAll = dotAll - self._commentText = commentText + self._commentText = commentText @property def SearchPattern(self): return self._searchPattern @property - def ReplacePattern(self): return self._replacePattern + def ReplacePattern(self): return self._replacePattern @property - def CaseInsensitive(self): return self._caseInsensitive + def CaseInsensitive(self): return self._caseInsensitive @property def MultiLine(self): return self._multiLine @property - def DotAll(self): return self._dotAll - - @classmethod + def DotAll(self): return self._dotAll + + @classmethod # mccabe:disable=MC0001 def GetParser(cls): - multiLine = False + multiLine = False dotAll = False - caseInsensitive = False - + caseInsensitive = False + # match for optional whitespace token = yield - if isinstance(token, SpaceToken): token = yield + if isinstance(token, SpaceToken): token = yield # match for keyword: REPLACE if (not isinstance(token, StringToken)): raise MismatchingParserResult("ReplaceParser: Expected REPLACE keyword.") if (token.Value.lower() != "replace"): raise MismatchingParserResult("ReplaceParser: Expected REPLACE keyword.") # match for whitespace token = yield - if (not isinstance(token, SpaceToken)): raise MismatchingParserResult("ReplaceParser: Expected whitespace before search pattern.") - # match for delimiter sign: " - token = yield - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("ReplaceParser: Expected double quote sign before search pattern.") - if (token.Value.lower() != "\""): raise MismatchingParserResult("ReplaceParser: Expected double quote sign before search pattern.") - # match for string: searchPattern - searchPattern = "" - wasEscapeSign = False - while True: - token = yield - if isinstance(token, CharacterToken): - if (token.Value == "\""): - if (wasEscapeSign is True): - wasEscapeSign = False - searchPattern += "\"" - continue - else: - break - elif (token.Value == "\\"): - if (wasEscapeSign is True): - wasEscapeSign = False - searchPattern += "\\" - continue - else: - wasEscapeSign = True - continue - searchPattern += token.Value + if (not isinstance(token, SpaceToken)): raise MismatchingParserResult("ReplaceParser: Expected whitespace before search pattern.") + + # match for string: searchPattern; use a StringLiteralParser to parse the pattern + parser = StringLiteral.GetParser() + parser.send(None) + searchPattern = None + try: + while True: + token = yield + parser.send(token) + except MatchingParserResult as ex: + searchPattern = ex.value.Value + # match for whitespace token = yield - if (not isinstance(token, SpaceToken)): raise MismatchingParserResult("ReplaceParser: Expected whitespace before WITH keyword.") + if (not isinstance(token, SpaceToken)): raise MismatchingParserResult("ReplaceParser: Expected whitespace before WITH keyword.") # match for WITH keyword token = yield if (not isinstance(token, StringToken)): raise MismatchingParserResult("ReplaceParser: Expected WITH keyword.") - if (token.Value.lower() != "with"): raise MismatchingParserResult("ReplaceParser: Expected WITH keyword.") + if (token.Value.lower() != "with"): raise MismatchingParserResult("ReplaceParser: Expected WITH keyword.") # match for whitespace token = yield - if (not isinstance(token, SpaceToken)): raise MismatchingParserResult("ReplaceParser: Expected whitespace before replace pattern.") - # match for delimiter sign: " - token = yield - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("ReplaceParser: Expected double quote sign before replace pattern.") - if (token.Value.lower() != "\""): raise MismatchingParserResult("ReplaceParser: Expected double quote sign before replace pattern.") - # match for string: replacePattern - replacePattern = "" - wasEscapeSign = False - while True: - token = yield - if isinstance(token, CharacterToken): - if (token.Value == "\""): - if (wasEscapeSign is True): - wasEscapeSign = False - replacePattern += "\"" - continue - else: - break - elif (token.Value == "\\"): - if (wasEscapeSign is True): - wasEscapeSign = False - replacePattern += "\\" - continue - else: - wasEscapeSign = True - continue - replacePattern += token.Value + if (not isinstance(token, SpaceToken)): raise MismatchingParserResult("ReplaceParser: Expected whitespace before replace pattern.") + + # match for string: replacePattern; use a StringLiteralParser to parse the pattern + parser = StringLiteral.GetParser() + parser.send(None) + + replacePattern = None + try: + while True: + token = yield + parser.send(token) + except MatchingParserResult as ex: + replacePattern = ex.value.Value + # match for optional whitespace token = yield - if isinstance(token, SpaceToken): token = yield + if isinstance(token, SpaceToken): token = yield # match for line end, comment or OPTIONS keyword if isinstance(token, StringToken): if (token.Value.lower() == "options"): # match for whitespace token = yield - if (not isinstance(token, SpaceToken)): raise MismatchingParserResult("ReplaceParser: Expected whitespace before MULTILINE, DOTALL or CASEINSENSITIVE keyword.") + if (not isinstance(token, SpaceToken)): raise MismatchingParserResult("ReplaceParser: Expected whitespace before MULTILINE, DOTALL or CASEINSENSITIVE keyword.") for _ in range(3): # match for MULTILINE, DOTALL or CASEINSENSITIVE keyword token = yield @@ -322,10 +304,10 @@ def GetParser(cls): continue else: break - + # match for delimiter sign: \n or # commentText = "" - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("ReplaceParser: Expected end of line or comment") + if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("ReplaceParser: Expected end of line or comment") if (token.Value == "\n"): pass elif (token.Value == "#"): @@ -344,93 +326,44 @@ def GetParser(cls): def __str__(self, indent=0): return "{0}Replace {1} by {2}".format(" " * indent, self._searchPattern, self._replacePattern) -# ============================================================================== -# Block Statements -# ============================================================================== -class FileStatement(BlockStatement): - def __init__(self, file, commentText): +class AppendLineStatement(Statement): + def __init__(self, appendPattern, commentText): super().__init__() - self._filePath = file - self._commentText = commentText + self._appendPattern = appendPattern + self._commentText = commentText @property - def FilePath(self): return self._filePath + def AppendPattern(self): return self._appendPattern @classmethod def GetParser(cls): - # match for IN ... FILE clause - # ========================================================================== # match for optional whitespace token = yield - if isinstance(token, SpaceToken): token = yield - # match for keyword: FILE - if (not isinstance(token, StringToken)): raise MismatchingParserResult("FileParser: Expected FILE keyword.") - if (token.Value.lower() != "file"): raise MismatchingParserResult("FileParser: Expected FILE keyword.") + if isinstance(token, SpaceToken): token = yield + # match for keyword: APPENDLINE + if (not isinstance(token, StringToken)): raise MismatchingParserResult("AppendLineParser: Expected APPENDLINE keyword.") + if (token.Value.lower() != "appendline"): raise MismatchingParserResult("AppendLineParser: Expected APPENDLINE keyword.") # match for whitespace token = yield - if (not isinstance(token, SpaceToken)): raise MismatchingParserResult("FileParser: Expected whitespace before filename.") - # match for delimiter sign: " - token = yield - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("FileParser: Expected double quote sign before fileName.") - if (token.Value.lower() != "\""): raise MismatchingParserResult("FileParser: Expected double quote sign before fileName.") - # match for string: source filename - replaceFilename = "" - while True: - token = yield - if (isinstance(token, CharacterToken) and (token.Value == "\"")): break - replaceFilename += token.Value - # match for optional whitespace - token = yield - if isinstance(token, SpaceToken): token = yield - # match for delimiter sign: \n - commentText = "" - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("FileParser: Expected end of line or comment") - if (token.Value == "\n"): - pass - elif (token.Value == "#"): - # match for any until line end - while True: - token = yield - if (isinstance(token, CharacterToken) and (token.Value == "\n")): break - commentText += token.Value - else: - raise MismatchingParserResult("FileParser: Expected end of line or comment") - - # match for inner statements - # ========================================================================== - # construct result - result = cls(replaceFilename, commentText) - parser = cls.GetRepeatParser(result.AddStatement, InFileStatements.GetParser) - parser.send(None) + if (not isinstance(token, SpaceToken)): raise MismatchingParserResult("AppendLineParser: Expected whitespace before append pattern.") + # match for string: appendPattern; use a StringLiteralParser to parse the pattern + parser = StringLiteral.GetParser() + parser.send(None) + appendPattern = None try: while True: token = yield parser.send(token) - except EmptyChoiseParserResult: - print("ERROR in *.rules file -> fix me") - except MatchingParserResult: - pass - - # match for END FILE clause - # ========================================================================== - # match for optional whitespace - if isinstance(token, SpaceToken): token = yield - # match for keyword: END - if (not isinstance(token, StringToken)): raise MismatchingParserResult("FileParser: Expected END keyword.") - if (token.Value.lower() != "end"): raise MismatchingParserResult("FileParser: Expected END keyword.") - # match for whitespace - token = yield - if (not isinstance(token, SpaceToken)): raise MismatchingParserResult("FileParser: Expected whitespace before FILE keyword.") - # match for keyword: FILE - token = yield - if (not isinstance(token, StringToken)): raise MismatchingParserResult("FileParser: Expected FILE keyword.") - if (token.Value.lower() != "file"): raise MismatchingParserResult("FileParser: Expected FILE keyword.") + except MatchingParserResult as ex: + appendPattern = ex.value.Value + # match for optional whitespace token = yield - if isinstance(token, SpaceToken): token = yield + if isinstance(token, SpaceToken): token = yield # match for delimiter sign: \n - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("FileParser: Expected end of line or comment") + commentText = "" + if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("AppendLineParser: Expected end of line or comment") if (token.Value == "\n"): pass elif (token.Value == "#"): @@ -438,41 +371,61 @@ def GetParser(cls): while True: token = yield if (isinstance(token, CharacterToken) and (token.Value == "\n")): break + commentText += token.Value else: - raise MismatchingParserResult("FileParser: Expected end of line or comment") - - result.CommentText = commentText + raise MismatchingParserResult("AppendLineParser: Expected end of line or comment") + # construct result + result = cls(appendPattern, commentText) raise MatchingParserResult(result) def __str__(self, indent=0): - _indent = " " * indent - buffer = _indent + "FileParser" - for stmt in self._statements: - buffer += "\n{0}{1}".format(_indent, stmt.__str__(indent + 1)) - return buffer + return "{0}AppendLine {1}".format(" " * indent, self._appendPattern) -class PreProcessRulesStatement(BlockStatement): - def __init__(self, commentText): +# ============================================================================== +# Block Statements +# ============================================================================== +class FileStatement(BlockStatement): + def __init__(self, file, commentText): super().__init__() + self._filePath = file self._commentText = commentText - @classmethod + @property + def FilePath(self): return self._filePath + + @classmethod # mccabe:disable=MC0001 def GetParser(cls): - # match for PREPROCESSRULES clause + # match for IN ... FILE clause # ========================================================================== # match for optional whitespace token = yield - if isinstance(token, SpaceToken): token = yield - # match for keyword: PREPROCESSRULES - if (not isinstance(token, StringToken)): raise MismatchingParserResult("PreProcessRulesParser: Expected PREPROCESSRULES keyword.") - if (token.Value.lower() != "preprocessrules"): raise MismatchingParserResult("PreProcessRulesParser: Expected PREPROCESSRULES keyword.") + if isinstance(token, SpaceToken): token = yield + # match for keyword: FILE + if (not isinstance(token, StringToken)): raise MismatchingParserResult("FileParser: Expected FILE keyword.") + if (token.Value.lower() != "file"): raise MismatchingParserResult("FileParser: Expected FILE keyword.") + # match for whitespace + token = yield + if (not isinstance(token, SpaceToken)): raise MismatchingParserResult("FileParser: Expected whitespace before filename.") + + # match for string: replaceFilename; use a StringLiteralParser to parse the pattern + parser = StringLiteral.GetParser() + parser.send(None) + + replaceFilename = None + try: + while True: + token = yield + parser.send(token) + except MatchingParserResult as ex: + replaceFilename = ex.value.Value + # match for optional whitespace token = yield - if isinstance(token, SpaceToken): token = yield + if isinstance(token, SpaceToken): token = yield # match for delimiter sign: \n commentText = "" - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("PreProcessRulesParser: Expected end of line or comment") + if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("FileParser: Expected end of line or comment") if (token.Value == "\n"): pass elif (token.Value == "#"): @@ -482,42 +435,43 @@ def GetParser(cls): if (isinstance(token, CharacterToken) and (token.Value == "\n")): break commentText += token.Value else: - raise MismatchingParserResult("PreProcessRulesParser: Expected end of line or comment") + raise MismatchingParserResult("FileParser: Expected end of line or comment") # match for inner statements # ========================================================================== # construct result - result = cls(commentText) - parser = cls.GetRepeatParser(result.AddStatement, PreProcessStatements.GetParser) + result = cls(replaceFilename, commentText) + parser = cls.GetRepeatParser(result.AddStatement, InFileStatements.GetParser) parser.send(None) try: while True: token = yield parser.send(token) + except EmptyChoiseParserResult: + print("ERROR in *.rules file -> fix me") except MatchingParserResult: pass - # match for END PREPROCESSRULES + # match for END FILE clause # ========================================================================== # match for optional whitespace - if isinstance(token, SpaceToken): token = yield + if isinstance(token, SpaceToken): token = yield # match for keyword: END - if (not isinstance(token, StringToken)): raise MismatchingParserResult("PreProcessRulesParser: Expected END keyword.") - if (token.Value.lower() != "end"): raise MismatchingParserResult("PreProcessRulesParser: Expected END keyword.") + if (not isinstance(token, StringToken)): raise MismatchingParserResult("FileParser: Expected END keyword.") + if (token.Value.lower() != "end"): raise MismatchingParserResult("FileParser: Expected END keyword.") # match for whitespace token = yield - if (not isinstance(token, SpaceToken)): raise MismatchingParserResult("PreProcessRulesParser: Expected whitespace before PREPROCESSRULES keyword.") - # match for keyword: PREPROCESSRULES + if (not isinstance(token, SpaceToken)): raise MismatchingParserResult("FileParser: Expected whitespace before FILE keyword.") + # match for keyword: FILE token = yield - if (not isinstance(token, StringToken)): raise MismatchingParserResult("PreProcessRulesParser: Expected PREPROCESSRULES keyword.") - if (token.Value.lower() != "preprocessrules"): raise MismatchingParserResult("PreProcessRulesParser: Expected PREPROCESSRULES keyword.") + if (not isinstance(token, StringToken)): raise MismatchingParserResult("FileParser: Expected FILE keyword.") + if (token.Value.lower() != "file"): raise MismatchingParserResult("FileParser: Expected FILE keyword.") # match for optional whitespace token = yield - if isinstance(token, SpaceToken): token = yield + if isinstance(token, SpaceToken): token = yield # match for delimiter sign: \n - # commentText = "" - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("PreProcessRulesParser: Expected end of line or comment") + if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("FileParser: Expected end of line or comment") if (token.Value == "\n"): pass elif (token.Value == "#"): @@ -525,41 +479,44 @@ def GetParser(cls): while True: token = yield if (isinstance(token, CharacterToken) and (token.Value == "\n")): break - # commentText += token.Value else: - raise MismatchingParserResult("PreProcessRulesParser: Expected end of line or comment") + raise MismatchingParserResult("FileParser: Expected end of line or comment") + + result.CommentText = commentText raise MatchingParserResult(result) def __str__(self, indent=0): _indent = " " * indent - buffer = _indent + "PreProcessRulesParser" + buffer = _indent + "FileParser" for stmt in self._statements: buffer += "\n{0}{1}".format(_indent, stmt.__str__(indent + 1)) return buffer -class PostProcessStatement(BlockStatement): +class ProcessRulesBlockStatement(BlockStatement): + __PARSER_NAME__ = None + __PARSER_BLOCK_NAME__ = None + __PARSER_STATEMENTS__ = None + def __init__(self, commentText): super().__init__() - self._commentText = commentText + self._commentText = commentText - @classmethod + @classmethod # mccabe:disable=MC0001 def GetParser(cls): - # match for POSTPRECESSRULES clause - # ========================================================================== # match for optional whitespace token = yield - if isinstance(token, SpaceToken): token = yield - # match for keyword: POSTPRECESSRULES - if (not isinstance(token, StringToken)): raise MismatchingParserResult("PostProcessRulesParser: Expected POSTPRECESSRULES keyword.") - if (token.Value.lower() != "postprocessrules"): raise MismatchingParserResult("PostProcessRulesParser: Expected POSTPRECESSRULES keyword.") + if isinstance(token, SpaceToken): token = yield + # match for keyword: __PARSER_BLOCK_NAME__ + if (not isinstance(token, StringToken)): raise MismatchingParserResult(cls.__PARSER_NAME__ + ": Expected " + cls.__PARSER_BLOCK_NAME__ + " keyword.") + if (token.Value.lower() != cls.__PARSER_BLOCK_NAME__): raise MismatchingParserResult(cls.__PARSER_NAME__ + ": Expected " + cls.__PARSER_BLOCK_NAME__ + " keyword.") # match for optional whitespace token = yield - if isinstance(token, SpaceToken): token = yield + if isinstance(token, SpaceToken): token = yield # match for delimiter sign: \n commentText = "" - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("PostProcessRulesParser: Expected end of line or comment") + if (not isinstance(token, CharacterToken)): raise MismatchingParserResult(cls.__PARSER_NAME__ + ": Expected end of line or comment") if (token.Value == "\n"): pass elif (token.Value == "#"): @@ -569,44 +526,42 @@ def GetParser(cls): if (isinstance(token, CharacterToken) and (token.Value == "\n")): break commentText += token.Value else: - raise MismatchingParserResult("PostProcessRulesParser: Expected end of line or comment") + raise MismatchingParserResult(cls.__PARSER_NAME__ + ": Expected end of line or comment") # match for inner statements # ========================================================================== # construct result result = cls(commentText) - parser = cls.GetRepeatParser(result.AddStatement, PostProcessStatements.GetParser) + parser = cls.GetRepeatParser(result.AddStatement, cls.__PARSER_STATEMENTS__.GetParser) parser.send(None) try: while True: token = yield parser.send(token) - except EmptyChoiseParserResult: - print("ERROR in *.rules file -> fix me 2") except MatchingParserResult: pass - # match for END POSTPROCESSRULES + # match for END __PARSER_BLOCK_NAME__ # ========================================================================== # match for optional whitespace - if isinstance(token, SpaceToken): token = yield + if isinstance(token, SpaceToken): token = yield # match for keyword: END - if (not isinstance(token, StringToken)): raise MismatchingParserResult("PostProcessRulesParser: Expected END keyword.") - if (token.Value.lower() != "end"): raise MismatchingParserResult("PostProcessRulesParser: Expected END keyword.") + if (not isinstance(token, StringToken)): raise MismatchingParserResult(cls.__PARSER_NAME__ + ": Expected END keyword.") + if (token.Value.lower() != "end"): raise MismatchingParserResult(cls.__PARSER_NAME__ + ": Expected END keyword.") # match for whitespace token = yield - if (not isinstance(token, SpaceToken)): raise MismatchingParserResult("PostProcessRulesParser: Expected whitespace before POSTPROCESSRULES keyword.") - # match for keyword: POSTPROCESSRULES + if (not isinstance(token, SpaceToken)): raise MismatchingParserResult(cls.__PARSER_NAME__ + ": Expected whitespace before " + cls.__PARSER_BLOCK_NAME__ + " keyword.") + # match for keyword: __PARSER_BLOCK_NAME__ token = yield - if (not isinstance(token, StringToken)): raise MismatchingParserResult("PostProcessRulesParser: Expected POSTPROCESSRULES keyword.") - if (token.Value.lower() != "postprocessrules"): raise MismatchingParserResult("PostProcessRulesParser: Expected POSTPROCESSRULES keyword.") + if (not isinstance(token, StringToken)): raise MismatchingParserResult(cls.__PARSER_NAME__ + ": Expected " + cls.__PARSER_BLOCK_NAME__ + " keyword.") + if (token.Value.lower() != cls.__PARSER_BLOCK_NAME__): raise MismatchingParserResult(cls.__PARSER_NAME__ + ": Expected " + cls.__PARSER_BLOCK_NAME__ + " keyword.") # match for optional whitespace token = yield - if isinstance(token, SpaceToken): token = yield + if isinstance(token, SpaceToken): token = yield # match for delimiter sign: \n # commentText = "" - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("PostProcessRulesParser: Expected end of line or comment") + if (not isinstance(token, CharacterToken)): raise MismatchingParserResult(cls.__PARSER_NAME__ + ": Expected end of line or comment") if (token.Value == "\n"): pass elif (token.Value == "#"): @@ -616,39 +571,57 @@ def GetParser(cls): if (isinstance(token, CharacterToken) and (token.Value == "\n")): break # commentText += token.Value else: - raise MismatchingParserResult("PostProcessRulesParser: Expected end of line or comment") + raise MismatchingParserResult(cls.__PARSER_NAME__ + ": Expected end of line or comment") raise MatchingParserResult(result) def __str__(self, indent=0): _indent = " " * indent - buffer = _indent + "PostProcessRulesStatement" + buffer = _indent + self.__PARSER_NAME__ for stmt in self._statements: buffer += "\n{0}{1}".format(_indent, stmt.__str__(indent + 1)) return buffer +class PreProcessRulesStatement(ProcessRulesBlockStatement): + __PARSER_NAME__ = "PreProcessRulesParser" + __PARSER_BLOCK_NAME__ = "preprocessrules" + __PARSER_STATEMENTS__ = PreProcessStatements + + +class PostProcessRulesStatement(ProcessRulesBlockStatement): + __PARSER_NAME__ = "PostProcessRulesParser" + __PARSER_BLOCK_NAME__ = "postprocessrules" + __PARSER_STATEMENTS__ = PostProcessStatements + + class Document(BlockStatement): @classmethod def GetParser(cls): result = cls() parser = cls.GetRepeatParser(result.AddStatement, DocumentStatements.GetParser) parser.send(None) - + + token = yield + if (not isinstance(token, StartOfDocumentToken)): + raise MismatchingParserResult("Expected a StartOfDocumentToken, got {0!s}.".format(token)) + try: while True: token = yield parser.send(token) except MatchingParserResult: raise MatchingParserResult(result) - + def __str__(self, indent=0): buffer = " " * indent + "Document" for stmt in self._statements: buffer += "\n{0}".format(stmt.__str__(indent + 1)) return buffer + InFileStatements.AddChoice(ReplaceStatement) +InFileStatements.AddChoice(AppendLineStatement) InFileStatements.AddChoice(CommentLine) InFileStatements.AddChoice(EmptyLine) @@ -664,6 +637,6 @@ def __str__(self, indent=0): PostProcessStatements.AddChoice(EmptyLine) DocumentStatements.AddChoice(PreProcessRulesStatement) -DocumentStatements.AddChoice(PostProcessStatement) +DocumentStatements.AddChoice(PostProcessRulesStatement) DocumentStatements.AddChoice(CommentLine) DocumentStatements.AddChoice(EmptyLine) diff --git a/py/Parser/RulesParser.py b/py/Parser/RulesParser.py index 3877646c..10e21414 100644 --- a/py/Parser/RulesParser.py +++ b/py/Parser/RulesParser.py @@ -1,12 +1,12 @@ # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2; replace-tabs off; indent-width 2; -# +# # ============================================================================== # Authors: Patrick Lehmann # # Python Module: TODO -# +# # Description: # ------------------------------------ # TODO: @@ -15,13 +15,13 @@ # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany # Chair for VLSI-Design, Diagnostics and Architecture -# +# # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at -# +# # http://www.apache.org/licenses/LICENSE-2.0 -# +# # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -30,7 +30,8 @@ # ============================================================================== # from lib.Parser import ParserException -from Parser.RulesCodeDOM import Document, PreProcessRulesStatement, PostProcessStatement, CopyStatement, ReplaceStatement, FileStatement, DeleteStatement +from Parser.RulesCodeDOM import Document, PreProcessRulesStatement, PostProcessRulesStatement, CopyStatement, ReplaceStatement, FileStatement, DeleteStatement, \ + AppendLineStatement class Rule: @@ -40,10 +41,10 @@ class Rule: class CopyRuleMixIn(Rule): def __init__(self, sourcePath, destinationPath): self._source = sourcePath - self._destination = destinationPath + self._destination = destinationPath @property - def SourcePath(self): return self._source + def SourcePath(self): return self._source @property def DestinationPath(self): return self._destination @@ -65,53 +66,67 @@ def __str__(self): class ReplaceRuleMixIn(Rule): def __init__(self, filePath, searchPattern, replacePattern, multiLine, dotAll, caseInSensitive): self._filePath = filePath - self._searchPattern = searchPattern + self._searchPattern = searchPattern self._replacePattern = replacePattern - self._multiLine = multiLine + self._multiLine = multiLine self._dotAll = dotAll - self._caseInsensitive = caseInSensitive + self._caseInsensitive = caseInSensitive @property - def FilePath(self): return self._filePath + def FilePath(self): return self._filePath @property def SearchPattern(self): return self._searchPattern @property - def ReplacePattern(self): return self._replacePattern + def ReplacePattern(self): return self._replacePattern @property - def RegExpOption_MultiLine(self): return self._multiLine + def RegExpOption_MultiLine(self): return self._multiLine @property def RegExpOption_DotAll(self): return self._dotAll @property - def RegExpOption_CaseInsensitive(self): return self._caseInsensitive + def RegExpOption_CaseInsensitive(self): return self._caseInsensitive def __str__(self): return "Replace rule: in '{0!s}' replace '{1}' with '{2}'".format(self._filePath, self._searchPattern, self._replacePattern) +class AppendLineRuleMixIn(Rule): + def __init__(self, filePath, appendPattern): + self._filePath = filePath + self._appendPattern = appendPattern + + @property + def FilePath(self): return self._filePath + @property + def AppendPattern(self): return self._appendPattern + + def __str__(self): + return "AppendLine rule: in '{0!s}' append '{1}'".format(self._filePath, self._appendPattern) + class RulesParserMixIn: _classCopyRule = CopyRuleMixIn _classDeleteRule = DeleteRuleMixIn - _classReplaceRule = ReplaceRuleMixIn + _classReplaceRule = ReplaceRuleMixIn + _classAppendLineRule = AppendLineRuleMixIn def __init__(self): - self._rootDirectory = None + self._rootDirectory = None self._document = None - - self._preProcessRules = [] + + self._preProcessRules = [] self._postProcessRules = [] def _Parse(self): self._ReadContent() #only available via late binding - self._document = Document.parse(self._content, printChar=not True) #self._content only available via late binding + self._document = Document.Parse(self._content, printChar=not True) #self._content only available via late binding # print("{DARK_GRAY}{0!s}{NOCOLOR}".format(self._document, **Init.Foreground)) - + def _Resolve(self): # print("Resolving {0}".format(str(self._file))) for stmt in self._document.Statements: if isinstance(stmt, PreProcessRulesStatement): for ruleStatement in stmt.Statements: self._ResolveRule(ruleStatement, self._preProcessRules) - elif isinstance(stmt, PostProcessStatement): + elif isinstance(stmt, PostProcessRulesStatement): for ruleStatement in stmt.Statements: self._ResolveRule(ruleStatement, self._postProcessRules) else: @@ -128,22 +143,25 @@ def _ResolveRule(self, ruleStatement, lst): rule = self._classDeleteRule(file) lst.append(rule) elif isinstance(ruleStatement, FileStatement): - # FIXME: Currently, all replace rules are stored in individual rule instances. + # FIXME: Currently, all replace and append rules are stored in individual rule instances. # FIXME: This prevents the system from creating a single task of multiple sub-rules -> just one open/close would be required filePath = ruleStatement.FilePath - for replaceRule in ruleStatement.Statements: - if isinstance(replaceRule, ReplaceStatement): - rule = self._classReplaceRule(filePath, replaceRule.SearchPattern, replaceRule.ReplacePattern, replaceRule.MultiLine, replaceRule.DotAll, replaceRule.CaseInsensitive) + for nestedStatement in ruleStatement.Statements: + if isinstance(nestedStatement, ReplaceStatement): + rule = self._classReplaceRule(filePath, nestedStatement.SearchPattern, nestedStatement.ReplacePattern, nestedStatement.MultiLine, nestedStatement.DotAll, nestedStatement.CaseInsensitive) + lst.append(rule) + elif isinstance(nestedStatement, AppendLineStatement): + rule = self._classAppendLineRule(filePath, nestedStatement.AppendPattern) lst.append(rule) else: - ParserException("Found unknown statement type '{0}'.".format(replaceRule.__class__.__name__)) + ParserException("Found unknown statement type '{0}'.".format(nestedStatement.__class__.__name__)) else: ParserException("Found unknown statement type '{0}'.".format(ruleStatement.__class__.__name__)) @property def PreProcessRules(self): return self._preProcessRules @property - def PostProcessRules(self): return self._postProcessRules + def PostProcessRules(self): return self._postProcessRules def __str__(self): return "RULES file: '{0!s}'".format(self._file) #self._file only available via late binding def __repr__(self): return self.__str__() diff --git a/py/Parser/__init__.py b/py/Parser/__init__.py index c7937423..2d70fe94 100644 --- a/py/Parser/__init__.py +++ b/py/Parser/__init__.py @@ -1,28 +1,28 @@ # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2; replace-tabs off; indent-width 2; -# +# # ============================================================================== # Authors: Patrick Lehmann -# +# # Python Sub Module: TODO: -# +# # Description: # ------------------------------------ # TODO: -# +# # # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany # Chair for VLSI-Design, Diagnostics and Architecture -# +# # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at -# +# # http://www.apache.org/licenses/LICENSE-2.0 -# +# # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. diff --git a/py/PoC.py b/py/PoC.py index b5b15f33..9f42ef74 100644 --- a/py/PoC.py +++ b/py/PoC.py @@ -1,13 +1,13 @@ # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2; replace-tabs off; indent-width 2; -# +# # ============================================================================== -# Authors: Patrick Lehmann +# Authors: Patrick Lehmann # Martin Zabel -# -# Python Main Module: Entry point to the testbench tools in PoC repository. -# +# +# Python Main Module: Entry point to the testbench tools in PoC repository. +# # Description: # ------------------------------------ # This is a python main module (executable) which: @@ -18,13 +18,13 @@ # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany # Chair for VLSI-Design, Diagnostics and Architecture -# +# # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at -# +# # http://www.apache.org/licenses/LICENSE-2.0 -# +# # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # distributed under the License is distributed on an "AS IS" BASIS,default @@ -33,51 +33,53 @@ # limitations under the License. # ============================================================================== -from argparse import RawDescriptionHelpFormatter +from argparse import RawDescriptionHelpFormatter from collections import OrderedDict -from configparser import Error as ConfigParser_Error, DuplicateOptionError -from os import environ +from configparser import Error as ConfigParser_Error, DuplicateOptionError +from os import environ from pathlib import Path -from platform import system as platform_system +from platform import system as platform_system from sys import argv as sys_argv -from textwrap import dedent +from textwrap import dedent from Base.Compiler import CompilerException -from Base.Configuration import ConfigurationException, SkipConfigurationException +from Base.Configuration import ConfigurationException, SkipConfigurationException from Base.Exceptions import ExceptionBase, CommonException, PlatformNotSupportedException, EnvironmentException, NotConfiguredException -from Base.Logging import ILogable, Logger, Severity -from Base.Project import VHDLVersion -from Base.Simulator import SimulatorException -from Base.ToolChain import ToolChainException -from Compiler.LSECompiler import Compiler as LSECompiler -from Compiler.QuartusCompiler import Compiler as MapCompiler -from Compiler.XCOCompiler import Compiler as XCOCompiler -from Compiler.XSTCompiler import Compiler as XSTCompiler -from Compiler.VivadoCompiler import Compiler as VivadoCompiler -from PoC.Config import Board -from PoC.Entity import NamespaceRoot, FQN, EntityTypes, WildCard, TestbenchKind, NetlistKind -from PoC.Solution import Repository +from Base.Logging import ILogable, Logger, Severity +from Base.Project import VHDLVersion +from Base.Simulator import SimulatorException, Simulator as BaseSimulator +from Base.ToolChain import ToolChainException +from Compiler.LSECompiler import Compiler as LSECompiler +from Compiler.QuartusCompiler import Compiler as MapCompiler +from Compiler.ISECompiler import Compiler as ISECompiler +from Compiler.XCICompiler import Compiler as XCICompiler +from Compiler.XCOCompiler import Compiler as XCOCompiler +from Compiler.XSTCompiler import Compiler as XSTCompiler +from Compiler.VivadoCompiler import Compiler as VivadoCompiler +from PoC.Config import Board +from PoC.Entity import NamespaceRoot, FQN, EntityTypes, WildCard, TestbenchKind, NetlistKind +from PoC.Solution import Repository from PoC.Query import Query -from Simulator.ActiveHDLSimulator import Simulator as ActiveHDLSimulator -from Simulator.CocotbSimulator import Simulator as CocotbSimulator -from Simulator.GHDLSimulator import Simulator as GHDLSimulator -from Simulator.ISESimulator import Simulator as ISESimulator -from Simulator.QuestaSimulator import Simulator as QuestaSimulator -from Simulator.VivadoSimulator import Simulator as VivadoSimulator -from ToolChains import Configurations -from ToolChains.GHDL import Configuration as GHDLConfiguration -from lib.ArgParseAttributes import ArgParseMixin -from lib.ArgParseAttributes import CommandAttribute, CommandGroupAttribute, ArgumentAttribute, SwitchArgumentAttribute, DefaultAttribute -from lib.ArgParseAttributes import CommonArgumentAttribute, CommonSwitchArgumentAttribute -from lib.ConfigParser import ExtendedConfigParser -from lib.Functions import Init, Exit -from lib.Parser import ParserException -from lib.pyAttribute import Attribute +from Simulator.ActiveHDLSimulator import Simulator as ActiveHDLSimulator +from Simulator.CocotbSimulator import Simulator as CocotbSimulator +from Simulator.GHDLSimulator import Simulator as GHDLSimulator +from Simulator.ISESimulator import Simulator as ISESimulator +from Simulator.QuestaSimulator import Simulator as QuestaSimulator +from Simulator.VivadoSimulator import Simulator as VivadoSimulator +from ToolChains import Configurations +from ToolChains.GHDL import Configuration as GHDLConfiguration +from lib.pyAttribute.ArgParseAttributes import ArgParseMixin +from lib.pyAttribute.ArgParseAttributes import CommandAttribute, CommandGroupAttribute, ArgumentAttribute, SwitchArgumentAttribute, DefaultAttribute +from lib.pyAttribute.ArgParseAttributes import CommonArgumentAttribute, CommonSwitchArgumentAttribute +from lib.ConfigParser import ExtendedConfigParser +from lib.Functions import Init, Exit +from lib.Parser import ParserException +from lib.pyAttribute import Attribute class PoCEntityAttribute(Attribute): def __call__(self, func): - self._AppendAttribute(func, ArgumentAttribute(metavar="", dest="FQN", type=str, nargs='+', help="A space seperated list of PoC entities.")) + self._AppendAttribute(func, ArgumentAttribute(metavar="", dest="FQN", type=str, nargs='+', help="A space separated list of PoC entities.")) return func class BoardDeviceAttributeGroup(Attribute): @@ -174,7 +176,7 @@ def __init__(self, *args, **kwargs): self.__repo = None self.__directories = {} - self.__SimulationDefaultVHDLVersion = VHDLVersion.VHDL08 + self.__SimulationDefaultVHDLVersion = BaseSimulator._vhdlVersion self.__SimulationDefaultBoard = None self._directories = self.__Directories__() @@ -215,7 +217,7 @@ def __CheckEnvironment(self): # read PoC configuration # ============================================================================ def __ReadPoCConfiguration(self): - self._LogVerbose("Reading configuration files...") + self.LogVerbose("Reading configuration files...") configFiles = [ (self.ConfigFiles.Private, "private"), @@ -226,19 +228,19 @@ def __ReadPoCConfiguration(self): ] # create parser instance - self._LogDebug("Reading PoC configuration from:") + self.LogDebug("Reading PoC configuration from:") self.__pocConfig = ExtendedConfigParser() self.__pocConfig.optionxform = str try: # process first file (private) file, name = configFiles[0] - self._LogDebug(" {0!s}".format(file)) + self.LogDebug(" {0!s}".format(file)) if not file.exists(): raise NotConfiguredException("PoC's {0} configuration file '{1!s}' does not exist.".format(name, file)) from FileNotFoundError(str(file)) self.__pocConfig.read(str(file)) for file, name in configFiles[1:]: - self._LogDebug(" {0!s}".format(file)) + self.LogDebug(" {0!s}".format(file)) if not file.exists(): raise ConfigurationException("PoC's {0} configuration file '{1!s}' does not exist.".format(name, file)) from FileNotFoundError(str(file)) self.__pocConfig.read(str(file)) except DuplicateOptionError as ex: @@ -270,7 +272,7 @@ def __WritePoCConfiguration(self): self.__pocConfig.remove_section("SOLUTION.DEFAULTS") # Writing configuration to disc - self._LogNormal("Writing configuration file to '{0!s}'".format(self._configFiles.Private)) + self.LogNormal("Writing configuration file to '{0!s}'".format(self._configFiles.Private)) with self._configFiles.Private.open('w') as configFileHandle: self.PoCConfig.write(configFileHandle) @@ -278,11 +280,11 @@ def __PrepareForConfiguration(self): self.__ReadPoCConfiguration() def __PrepareForSimulation(self): - self._LogNormal("Initializing PoC-Library Service Tool for simulations") + self.LogNormal("Initializing PoC-Library Service Tool for simulations") self.__ReadPoCConfiguration() def __PrepareForSynthesis(self): - self._LogNormal("Initializing PoC-Library Service Tool for synthesis") + self.LogNormal("Initializing PoC-Library Service Tool for synthesis") self.__ReadPoCConfiguration() # ============================================================================ @@ -290,19 +292,20 @@ def __PrepareForSynthesis(self): # ============================================================================ # common arguments valid for all commands # ---------------------------------------------------------------------------- - @CommonSwitchArgumentAttribute("-D", dest="DEBUG", help="enable script wrapper debug mode") - @CommonSwitchArgumentAttribute("-d", "--debug", dest="debug", help="enable debug mode") - @CommonSwitchArgumentAttribute("-v", "--verbose", dest="verbose", help="print out detailed messages") - @CommonSwitchArgumentAttribute("-q", "--quiet", dest="quiet", help="reduce messages to a minimum") + @CommonSwitchArgumentAttribute("-D", dest="DEBUG", help="enable script wrapper debug mode") + @CommonSwitchArgumentAttribute( "--dryrun", dest="DryRun", help="enable script wrapper debug mode") + @CommonSwitchArgumentAttribute("-d", "--debug", dest="debug", help="enable debug mode") + @CommonSwitchArgumentAttribute("-v", "--verbose", dest="verbose", help="print out detailed messages") + @CommonSwitchArgumentAttribute("-q", "--quiet", dest="quiet", help="reduce messages to a minimum") @CommonArgumentAttribute("--sln", metavar="", dest="SolutionID", help="Solution name") @CommonArgumentAttribute("--prj", metavar="", dest="ProjectID", help="Solution name") def Run(self): ArgParseMixin.Run(self) def PrintHeadline(self): - self._LogNormal("{HEADLINE}{line}{NOCOLOR}".format(line="="*80, **Init.Foreground)) - self._LogNormal("{HEADLINE}{headline: ^80s}{NOCOLOR}".format(headline=self.HeadLine, **Init.Foreground)) - self._LogNormal("{HEADLINE}{line}{NOCOLOR}".format(line="="*80, **Init.Foreground)) + self.LogNormal("{HEADLINE}{line}{NOCOLOR}".format(line="="*80, **Init.Foreground)) + self.LogNormal("{HEADLINE}{headline: ^80s}{NOCOLOR}".format(headline=self.HeadLine, **Init.Foreground)) + self.LogNormal("{HEADLINE}{line}{NOCOLOR}".format(line="="*80, **Init.Foreground)) # ---------------------------------------------------------------------------- # fallback handler if no command was recognized @@ -346,9 +349,10 @@ def HandleHelp(self, args): # ============================================================================ # create the sub-parser for the "configure" command # ---------------------------------------------------------------------------- - @CommandGroupAttribute("Configuration commands") + @CommandGroupAttribute("Configuration commands") # mccabe:disable=MC0001 @CommandAttribute("configure", help="Configure vendor tools for PoC.") - def HandleConfiguration(self, _): + @ArgumentAttribute(metavar="", dest="ToolChain", type=str, nargs="?", help="Specify a tool chain to be configured.") + def HandleConfiguration(self, args): self.PrintHeadline() if (self.Platform not in ["Darwin", "Linux", "Windows"]): raise PlatformNotSupportedException(self.Platform) @@ -359,16 +363,27 @@ def HandleConfiguration(self, _): except NotConfiguredException: self._InitializeConfiguration() - self._LogVerbose("starting manual configuration...") + self.LogVerbose("starting manual configuration...") print("Explanation of abbreviations:") - print(" y - yes") - print(" n - no") - print(" p - pass (jump to next question)") - print("Upper case means default value") - print() + print(" {YELLOW}Y{NOCOLOR} - yes {YELLOW}P{NOCOLOR} - pass (jump to next question)".format(**Init.Foreground)) + print(" {YELLOW}N{NOCOLOR} - no {YELLOW}Ctrl + C{NOCOLOR} - abort (no changes are saved)".format(**Init.Foreground)) + print("Upper case or value in '[...]' means default value") + print("-"*80) + + # select tool chains for configuration + toolChain = args.ToolChain + if (toolChain is None): + configurators = [config(self) for config in Configurations] + elif (toolChain != ""): + sectionName = "INSTALL.{0}".format(toolChain) + configurators = [config(self) for config in Configurations if (config._section.lower().startswith(sectionName.lower()))] + + if (len(configurators) == 0): + self.LogError("{RED}No configuration named '{0}' found.{NOCOLOR}".format(toolChain, **Init.Foreground)) + return # configure each vendor or tool of a tool chain - configurators = [config(self) for config in Configurations] + print() for configurator in configurators: # skip configuration with unsupported platforms @@ -378,11 +393,11 @@ def HandleConfiguration(self, _): configurator.ClearSection() continue - self._LogNormal("{CYAN}Configuring {0!s}{NOCOLOR}".format(configurator, **Init.Foreground)) + self.LogNormal("{CYAN}Configuring {0!s}{NOCOLOR}".format(configurator, **Init.Foreground)) nxt = False while (nxt is False): try: - if (self.Platform == "Darwin"): configurator.ConfigureForDarwin() + if (self.Platform == "Darwin"): configurator.ConfigureForDarwin() elif (self.Platform == "Linux"): configurator.ConfigureForLinux() elif (self.Platform == "Windows"): configurator.ConfigureForWindows() @@ -397,11 +412,12 @@ def HandleConfiguration(self, _): self.__ReadPoCConfiguration() # run post-configuration tasks + self.LogNormal("{CYAN}Running post configuration tasks{NOCOLOR}".format(**Init.Foreground)) for configurator in configurators: configurator.RunPostConfigurationTasks() def _InitializeConfiguration(self): - self._LogWarning("No private configuration found. Generating an empty PoC configuration...") + self.LogWarning("No private configuration found. Generating an empty PoC configuration...") for config in Configurations: for sectionName in config.GetSections(self.Platform): @@ -415,9 +431,9 @@ def __UpdateConfiguration(self): delSections = pocSections.difference(configSections) if addSections: - self._LogWarning("Adding new sections to configuration...") + self.LogWarning("Adding new sections to configuration...") for sectionName in addSections: - self._LogWarning(" Adding [{0}]".format(sectionName)) + self.LogWarning(" Adding [{0}]".format(sectionName)) self.__pocConfig[sectionName] = OrderedDict() if delSections: @@ -433,7 +449,7 @@ def HandleAddSolution(self, _): #args self.PrintHeadline() self.__PrepareForConfiguration() - self._LogNormal("Register a new solutions in PoC") + self.LogNormal("Register a new solutions in PoC") solutionName = input(" Solution name: ") if (solutionName == ""): raise ConfigurationException("Empty input. Aborting!") @@ -453,11 +469,14 @@ def HandleAddSolution(self, _): #args elif (createPath not in ['y', 'Y']): raise ConfigurationException("Unsupported choice '{0}'".format(createPath)) - solutionRootPath.mkdir(parents=True) + try: + solutionRootPath.mkdir(parents=True) + except OSError as ex: + raise ConfigurationException("Error while creating '{0!s}'.".format(solutionRootPath)) from ex self.__repo.AddSolution(solutionID, solutionName, solutionRootPath) self.__WritePoCConfiguration() - self._LogNormal("Solution {GREEN}successfully{NOCOLOR} created.".format(**Init.Foreground)) + self.LogNormal("Solution {GREEN}successfully{NOCOLOR} created.".format(**Init.Foreground)) # ---------------------------------------------------------------------------- @@ -469,17 +488,17 @@ def HandleListSolution(self, _): #args self.PrintHeadline() self.__PrepareForConfiguration() - self._LogNormal("Registered solutions in PoC:") + self.LogNormal("Registered solutions in PoC:") if self.__repo.Solutions: for solution in self.__repo.Solutions: - self._LogNormal(" {id: <10}{name}".format(id=solution.ID, name=solution.Name)) + self.LogNormal(" {id: <10}{name}".format(id=solution.ID, name=solution.Name)) if (self.Logger.LogLevel <= Severity.Verbose): - self._LogVerbose(" Path: {path!s}".format(path=solution.Path)) - self._LogVerbose(" Projects:") + self.LogVerbose(" Path: {path!s}".format(path=solution.Path)) + self.LogVerbose(" Projects:") for project in solution.Projects: - self._LogVerbose(" {id: <6}{name}".format(id=project.ID, name=project.Name)) + self.LogVerbose(" {id: <6}{name}".format(id=project.ID, name=project.Name)) else: - self._LogNormal(" {RED}No registered solutions found.{NOCOLOR}".format(**Init.Foreground)) + self.LogNormal(" {RED}No registered solutions found.{NOCOLOR}".format(**Init.Foreground)) # ---------------------------------------------------------------------------- # create the sub-parser for the "remove-solution" command @@ -493,7 +512,7 @@ def HandleRemoveSolution(self, args): solution = self.__repo[args.SolutionID] - self._LogNormal("Removing solution '{0}'.".format(solution.Name)) + self.LogNormal("Removing solution '{0}'.".format(solution.Name)) remove = input("Do you really want to remove this solution? [N/y]: ") remove = remove if remove != "" else "N" if (remove in ['n', 'N']): @@ -504,7 +523,7 @@ def HandleRemoveSolution(self, args): self.__repo.RemoveSolution(solution) self.__WritePoCConfiguration() - self._LogNormal("Solution {GREEN}successfully{NOCOLOR} removed.".format(**Init.Foreground)) + self.LogNormal("Solution {GREEN}successfully{NOCOLOR} removed.".format(**Init.Foreground)) # ---------------------------------------------------------------------------- @@ -515,7 +534,7 @@ def HandleRemoveSolution(self, args): # def HandleAddProject(self, args): # self.PrintHeadline() # self.__PrepareForConfiguration() - + # ---------------------------------------------------------------------------- # create the sub-parser for the "list-project" command # ---------------------------------------------------------------------------- @@ -531,13 +550,13 @@ def HandleListProject(self, args): except KeyError as ex: raise ConfigurationException("Solution ID '{0}' is not registered in PoC.".format(args.SolutionID)) from ex - self._LogNormal("Registered projects for solution '{0}':".format(solution.ID)) + self.LogNormal("Registered projects for solution '{0}':".format(solution.ID)) if solution.Projects: for project in solution.Projects: - self._LogNormal(" {id: <10}{name}".format(id=project.ID, name=project.Name)) + self.LogNormal(" {id: <10}{name}".format(id=project.ID, name=project.Name)) else: - self._LogNormal(" {RED}No registered projects found.{NOCOLOR}".format(**Init.Foreground)) - + self.LogNormal(" {RED}No registered projects found.{NOCOLOR}".format(**Init.Foreground)) + # ---------------------------------------------------------------------------- # create the sub-parser for the "remove-project" command # ---------------------------------------------------------------------------- @@ -547,7 +566,7 @@ def HandleListProject(self, args): # def HandleRemoveProject(self, args): # self.PrintHeadline() # self.__PrepareForConfiguration() - + # ---------------------------------------------------------------------------- # create the sub-parser for the "add-ipcore" command # ---------------------------------------------------------------------------- @@ -556,7 +575,7 @@ def HandleListProject(self, args): # def HandleAddIPCore(self, args): # self.PrintHeadline() # self.__PrepareForConfiguration() - + # ---------------------------------------------------------------------------- # create the sub-parser for the "list-ipcore" command # ---------------------------------------------------------------------------- @@ -568,10 +587,10 @@ def HandleListProject(self, args): # # ipcore = Solution(self) # - # self._LogNormal("Registered ipcores in PoC:") + # self.LogNormal("Registered ipcores in PoC:") # for ipcoreName in ipcore.GetIPCoreNames(): # print(" {0}".format(ipcoreName)) - + # ---------------------------------------------------------------------------- # create the sub-parser for the "remove-ipcore" command # ---------------------------------------------------------------------------- @@ -590,7 +609,7 @@ def HandleListProject(self, args): # def HandleAddTestbench(self, args): # self.PrintHeadline() # self.__PrepareForConfiguration() - + # ---------------------------------------------------------------------------- # create the sub-parser for the "remove-testbench" command # ---------------------------------------------------------------------------- @@ -610,10 +629,13 @@ def HandleListProject(self, args): def HandleQueryConfiguration(self, args): self.__PrepareForConfiguration() query = Query(self) - result = query.QueryConfiguration(args.Query) - print(result, end="") - Exit.exit() - + try: + result = query.QueryConfiguration(args.Query) + print(result, end="") + Exit.exit() + except ConfigurationException as ex: + print(str(ex), end="") + Exit.exit(1) # ============================================================================ # Simulation commands @@ -630,36 +652,36 @@ def HandleQueryConfiguration(self, args): # self.Directories["XilinxPrimitiveSource"] = Path(self.PoCConfig['INSTALL.Xilinx.Vivado']['InstallationDirectory']) / "data/vhdl/src" def _ExtractBoard(self, BoardName, DeviceName, force=False): - if (BoardName is not None): return Board(self, BoardName) + if (BoardName is not None): return Board(self, BoardName) elif (DeviceName is not None): return Board(self, "Custom", DeviceName) - elif (force is True): raise CommonException("Either a board name or a device name is required.") - else: return self.__SimulationDefaultBoard + elif (force is True): raise CommonException("Either a board name or a device name is required.") + else: return self.__SimulationDefaultBoard def _ExtractFQNs(self, fqns, defaultLibrary="PoC", defaultType=EntityTypes.Testbench): - if (len(fqns) == 0): raise CommonException("No FQN given.") + if (len(fqns) == 0): raise CommonException("No FQN given.") return [FQN(self, fqn, defaultLibrary=defaultLibrary, defaultType=defaultType) for fqn in fqns] def _ExtractVHDLVersion(self, vhdlVersion, defaultVersion=None): if (defaultVersion is None): defaultVersion = self.__SimulationDefaultVHDLVersion - if (vhdlVersion is None): return defaultVersion - else: return VHDLVersion.parse(vhdlVersion) + if (vhdlVersion is None): return defaultVersion + else: return VHDLVersion.Parse(vhdlVersion) # TODO: move to Configuration class in ToolChains.Xilinx.Vivado def _CheckVivadoEnvironment(self): # check if Vivado is configure - if (len(self.PoCConfig.options("INSTALL.Xilinx.Vivado")) == 0): raise NotConfiguredException("Xilinx Vivado is not configured on this system.") + if (len(self.PoCConfig.options("INSTALL.Xilinx.Vivado")) == 0): raise NotConfiguredException("Xilinx Vivado is not configured on this system.") if (environ.get('XILINX_VIVADO') is None): raise EnvironmentException("Xilinx Vivado environment is not loaded in this shell environment.") # TODO: move to Configuration class in ToolChains.Xilinx.ISE def _CheckISEEnvironment(self): # check if ISE is configure if (len(self.PoCConfig.options("INSTALL.Xilinx.ISE")) == 0): raise NotConfiguredException("Xilinx ISE is not configured on this system.") - if (environ.get('XILINX') is None): raise EnvironmentException("Xilinx ISE environment is not loaded in this shell environment.") + if (environ.get('XILINX') is None): raise EnvironmentException("Xilinx ISE environment is not loaded in this shell environment.") # ---------------------------------------------------------------------------- # create the sub-parser for the "list-testbench" command # ---------------------------------------------------------------------------- - @CommandGroupAttribute("Simulation commands") + @CommandGroupAttribute("Simulation commands") # mccabe:disable=MC0001 @CommandAttribute("list-testbench", help="List all testbenches") @PoCEntityAttribute() @ArgumentAttribute("--kind", metavar="", dest="TestbenchKind", help="Testbench kind: VHDL | COCOTB") @@ -683,9 +705,9 @@ def HandleListTestbenches(self, args): solutionDefaultsFile = solutionRootPath / ".PoC" / "solution.defaults.ini" print(" sln files: {0!s} {1!s}".format(solutionConfigFile, solutionDefaultsFile)) - self._LogVerbose("Reading solution file...") - self._LogDebug(" {0!s}".format(solutionConfigFile)) - self._LogDebug(" {0!s}".format(solutionDefaultsFile)) + self.LogVerbose("Reading solution file...") + self.LogDebug(" {0!s}".format(solutionConfigFile)) + self.LogDebug(" {0!s}".format(solutionDefaultsFile)) if not solutionConfigFile.exists(): raise NotConfiguredException("Solution's {0} configuration file '{1!s}' does not exist.".format(solutionName, solutionConfigFile)) \ from FileNotFoundError(str(solutionConfigFile)) @@ -726,7 +748,7 @@ def HandleListTestbenches(self, args): fqnList = self._ExtractFQNs(args.FQN, defaultLibrary) for fqn in fqnList: - self._LogNormal("") + self.LogNormal("") entity = fqn.Entity if (isinstance(entity, WildCard)): for testbench in entity.GetTestbenches(tbFilter): @@ -736,7 +758,7 @@ def HandleListTestbenches(self, args): print(str(testbench)) Exit.exit() - + # ---------------------------------------------------------------------------- # create the sub-parser for the "asim" command @@ -756,11 +778,11 @@ def HandleActiveHDLSimulation(self, args): vhdlVersion = self._ExtractVHDLVersion(args.VHDLVersion) # create a GHDLSimulator instance and prepare it - simulator = ActiveHDLSimulator(self, args.GUIMode) + simulator = ActiveHDLSimulator(self, self.DryRun, args.GUIMode) allPassed = simulator.RunAll(fqnList, board=board, vhdlVersion=vhdlVersion) # , vhdlGenerics=None) Exit.exit(0 if allPassed else 1) - + # ---------------------------------------------------------------------------- # create the sub-parser for the "ghdl" command @@ -783,7 +805,7 @@ def HandleGHDLSimulation(self, args): board = self._ExtractBoard(args.BoardName, args.DeviceName) vhdlVersion = self._ExtractVHDLVersion(args.VHDLVersion) - simulator = GHDLSimulator(self, args.GUIMode) + simulator = GHDLSimulator(self, self.DryRun, args.GUIMode) allPassed = simulator.RunAll(fqnList, board=board, vhdlVersion=vhdlVersion, guiMode=args.GUIMode) #, vhdlGenerics=None) Exit.exit(0 if allPassed else 1) @@ -801,11 +823,11 @@ def HandleISESimulation(self, args): self.PrintHeadline() self.__PrepareForSimulation() self._CheckISEEnvironment() - + fqnList = self._ExtractFQNs(args.FQN) board = self._ExtractBoard(args.BoardName, args.DeviceName) - simulator = ISESimulator(self, args.GUIMode) + simulator = ISESimulator(self, self.DryRun, args.GUIMode) allPassed = simulator.RunAll(fqnList, board=board, vhdlVersion=VHDLVersion.VHDL93) #, vhdlGenerics=None) Exit.exit(0 if allPassed else 1) @@ -828,11 +850,11 @@ def HandleQuestaSimulation(self, args): board = self._ExtractBoard(args.BoardName, args.DeviceName) vhdlVersion = self._ExtractVHDLVersion(args.VHDLVersion) - simulator = QuestaSimulator(self, args.GUIMode) + simulator = QuestaSimulator(self, self.DryRun, args.GUIMode) allPassed = simulator.RunAll(fqnList, board=board, vhdlVersion=vhdlVersion) # , vhdlGenerics=None) Exit.exit(0 if allPassed else 1) - + # ---------------------------------------------------------------------------- # create the sub-parser for the "xsim" command @@ -848,13 +870,13 @@ def HandleVivadoSimulation(self, args): self.__PrepareForSimulation() self._CheckVivadoEnvironment() - + fqnList = self._ExtractFQNs(args.FQN) board = self._ExtractBoard(args.BoardName, args.DeviceName) # FIXME: VHDL-2008 is broken in Vivado 2016.1 -> use VHDL-93 by default vhdlVersion = self._ExtractVHDLVersion(args.VHDLVersion, defaultVersion=VHDLVersion.VHDL93) - simulator = VivadoSimulator(self, args.GUIMode) + simulator = VivadoSimulator(self, self.DryRun, args.GUIMode) allPassed = simulator.RunAll(fqnList, board=board, vhdlVersion=vhdlVersion) # , vhdlGenerics=None) Exit.exit(0 if allPassed else 1) @@ -874,14 +896,15 @@ def HandleCocotbSimulation(self, args): # check if QuestaSim is configured if (len(self.PoCConfig.options("INSTALL.Mentor.QuestaSim")) == 0): - raise NotConfiguredException("Mentor QuestaSim is not configured on this system.") + if (len(self.PoCConfig.options("INSTALL.Altera.ModelSim")) == 0): + raise NotConfiguredException("Neither Mentor QuestaSim nor Altera ModelSim is not configured on this system.") fqnList = self._ExtractFQNs(args.FQN) board = self._ExtractBoard(args.BoardName, args.DeviceName) # create a CocotbSimulator instance and prepare it - simulator = CocotbSimulator(self, args.GUIMode) - allPassed = simulator.RunAll(fqnList, board=board, vhdlVersion=VHDLVersion.VHDL08) + simulator = CocotbSimulator(self, self.DryRun, args.GUIMode) + allPassed = simulator.RunAll(fqnList, board=board, vhdlVersion=VHDLVersion.VHDL2008) Exit.exit(0 if allPassed else 1) @@ -923,6 +946,27 @@ def HandleListNetlist(self, args): Exit.exit() + # ---------------------------------------------------------------------------- + # create the sub-parser for the "ise" command + # ---------------------------------------------------------------------------- + @CommandGroupAttribute("Synthesis commands") + @CommandAttribute("ise", help="Generate any IP core for the Xilinx ISE tool chain") + @PoCEntityAttribute() + @BoardDeviceAttributeGroup() + @NoCleanUpAttribute() + def HandleISECompilation(self, args): + self.PrintHeadline() + self.__PrepareForSynthesis() + self._CheckISEEnvironment() + + fqnList = self._ExtractFQNs(args.FQN, defaultType=EntityTypes.NetList) + board = self._ExtractBoard(args.BoardName, args.DeviceName, force=True) + + compiler = ISECompiler(self, self.DryRun, args.NoCleanUp) + compiler.RunAll(fqnList, board) + + Exit.exit() + # ---------------------------------------------------------------------------- # create the sub-parser for the "coregen" command # ---------------------------------------------------------------------------- @@ -935,7 +979,7 @@ def HandleCoreGeneratorCompilation(self, args): self.PrintHeadline() self.__PrepareForSynthesis() self._CheckISEEnvironment() - + fqnList = self._ExtractFQNs(args.FQN, defaultType=EntityTypes.NetList) board = self._ExtractBoard(args.BoardName, args.DeviceName, force=True) @@ -965,6 +1009,27 @@ def HandleXstCompilation(self, args): Exit.exit() + # ---------------------------------------------------------------------------- + # create the sub-parser for the "xci" command + # ---------------------------------------------------------------------------- + @CommandGroupAttribute("Synthesis commands") + @CommandAttribute("xci", help="Generate an IP core from Xilinx Vivado IP Catalog") + @PoCEntityAttribute() + @BoardDeviceAttributeGroup() + @NoCleanUpAttribute() + def HandleIpCatalogCompilation(self, args): + self.PrintHeadline() + self.__PrepareForSynthesis() + self._CheckISEEnvironment() + + fqnList = self._ExtractFQNs(args.FQN, defaultType=EntityTypes.NetList) + board = self._ExtractBoard(args.BoardName, args.DeviceName, force=True) + + compiler = XCICompiler(self, self.DryRun, args.NoCleanUp) + compiler.RunAll(fqnList, board) + + Exit.exit() + # ---------------------------------------------------------------------------- # create the sub-parser for the "vivado" command # ---------------------------------------------------------------------------- @@ -1036,11 +1101,11 @@ def HandleLSECompilation(self, args): # main program -def main(): - dryRun = "-D" in sys_argv - debug = "-d" in sys_argv - verbose = "-v" in sys_argv - quiet = "-q" in sys_argv +def main(): # mccabe:disable=MC0001 + dryRun = "--dryrun" in sys_argv + debug = "-d" in sys_argv + verbose = "-v" in sys_argv + quiet = "-q" in sys_argv # configure Exit class Exit.quiet = quiet @@ -1086,10 +1151,10 @@ def main(): except EnvironmentException as ex: Exit.printEnvironmentException(ex) except NotConfiguredException as ex: Exit.printNotConfiguredException(ex) - except PlatformNotSupportedException as ex: Exit.printPlatformNotSupportedException(ex) - except ExceptionBase as ex: Exit.printExceptionbase(ex) - except NotImplementedError as ex: Exit.printNotImplementedError(ex) - # except Exception as ex: Exit.printException(ex) + except PlatformNotSupportedException as ex: Exit.printPlatformNotSupportedException(ex) + except ExceptionBase as ex: Exit.printExceptionbase(ex) + except NotImplementedError as ex: Exit.printNotImplementedError(ex) + except Exception as ex: Exit.printException(ex) # entry point if __name__ == "__main__": diff --git a/py/PoC/Config.py b/py/PoC/Config.py index ee1b93ea..0b429c83 100644 --- a/py/PoC/Config.py +++ b/py/PoC/Config.py @@ -1,13 +1,13 @@ # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2; replace-tabs off; indent-width 2; -# +# # ============================================================================== # Authors: Patrick Lehmann # Martin Zabel -# +# # Python Class: TODO -# +# # Description: # ------------------------------------ # TODO: @@ -16,13 +16,13 @@ # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany # Chair for VLSI-Design, Diagnostics and Architecture -# +# # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at -# +# # http://www.apache.org/licenses/LICENSE-2.0 -# +# # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -43,7 +43,6 @@ from enum import Enum, unique from re import compile as RegExpCompile -from lib.Functions import Init from Base.Configuration import ConfigurationException @@ -57,16 +56,16 @@ def __repr__(self): @unique class Vendors(BaseEnum): - Unknown = 0 - Generic = 1 + Unknown = 0 + Generic = 1 Altera = 2 - Lattice = 3 - MicroSemi = 4 + Lattice = 3 + MicroSemi = 4 Xilinx = 5 def __str__(self): return self.name - + def __repr__(self): return str(self).lower() @@ -86,10 +85,10 @@ class GenericFamilies(Families): class XilinxFamilies(Families): # Xilinx families Spartan = "s" - Artix = "a" - Kintex = "k" - Virtex = "v" - Zynq = "z" + Artix = "a" + Kintex = "k" + Virtex = "v" + Zynq = "z" class AlteraFamilies(Families): @@ -160,7 +159,7 @@ class Devices(BaseEnum): # Xilinx.Zynq devices Zynq7000 = 350 - + class SubTypes(BaseEnum): Unknown = None Generic = 1 @@ -196,30 +195,32 @@ class SubTypes(BaseEnum): def Groups(self): return self.value - + @unique class Packages(BaseEnum): Unknown = 0 Generic = 1 - + TQG = 10 - - CPG = 20 - CSG = 21 + + CLG = 20 + CPG = 21 + CSG = 22 CABGA = 25 - - FF = 30 - FFG = 31 - FTG = 32 + + FBG = 30 + FF = 31 + FFG = 32 FGG = 33 FLG = 34 FT = 35 - + FTG = 36 + RB = 40 RBG = 41 - RS = 42 - RF = 43 + RF = 42 + RS = 43 E = 50 Q = 51 @@ -231,35 +232,35 @@ class Packages(BaseEnum): class Device: def __init__(self, deviceString): # Device members - self.__vendor = Vendors.Unknown - self.__family = GenericFamilies.Unknown - self.__device = Devices.Unknown - self.__generation = 0 - self.__subtype = SubTypes.Unknown - self.__number = 0 - self.__speedGrade = 0 - self.__package = Packages.Unknown - self.__pinCount = 0 + self.__vendor = Vendors.Unknown + self.__family = GenericFamilies.Unknown + self.__device = Devices.Unknown + self.__generation = 0 + self.__subtype = SubTypes.Unknown + self.__number = 0 + self.__speedGrade = 0 + self.__package = Packages.Unknown + self.__pinCount = 0 self.__deviceString = deviceString - + if (not isinstance(deviceString, str)): raise ValueError("Parameter 'deviceString' is not of type str.") if ((deviceString is None) or (deviceString == "")): raise ValueError("Parameter 'deviceString' is empty.") - + # vendor = GENERIC # ========================================================================== - if (deviceString[0:2].lower() == "ge"): self._DecodeGeneric() # ge - Generic FPGA device - elif (deviceString[0:2].lower() == "xc"): self._DecodeXilinx(deviceString) # xc - Xilinx Commercial - elif (deviceString[0:2].lower() == "ep"): self._DecodeAltera(deviceString) # ep - + if (deviceString[0:2].lower() == "ge"): self._DecodeGeneric() # ge - Generic FPGA device + elif (deviceString[0:2].lower() == "xc"): self._DecodeXilinx(deviceString) # xc - Xilinx devices (XC = Xilinx Commercial) + elif (deviceString[0:2].lower() == "ep"): self._DecodeAltera(deviceString) # ep - Altera devices elif (deviceString[0:3].lower() == "ice"): self._DecodeLatticeICE(deviceString) # ice - Lattice iCE series elif (deviceString[0:3].lower() == "lcm"): self._DecodeLatticeLCM(deviceString) # lcm - Lattice MachXO series elif (deviceString[0:3].lower() == "lfe"): self._DecodeLatticeLFE(deviceString) # lfe - Lattice ECP series - else: raise ConfigurationException("Unknown manufacturer code in device string '{0}'".format(deviceString)) + else: raise ConfigurationException("Unknown manufacturer code in device string '{0}'".format(deviceString)) def _DecodeGeneric(self): - self.__vendor = Vendors.Generic - self.__family = GenericFamilies.Generic + self.__vendor = Vendors.Generic + self.__family = GenericFamilies.Generic self.__subtype = SubTypes.Generic self.__package = Packages.Generic @@ -287,17 +288,18 @@ def _DecodeAltera(self, deviceString): if (subtype != ""): d = {"g": "gx", "x": "sx", "t": "gt"} # re-name for Stratix 10 and Arria 10 if subtype in d: subtype = d[subtype] - self.__subtype = SubTypes[subtype.upper()] + try: self.__subtype = SubTypes[subtype.upper()] + except KeyError as ex: raise ConfigurationException("Unknown subtype '{0}'.".format(subtype)) from ex else: self.__subtype = SubTypes.NoSubType else: raise ConfigurationException("RegExp mismatch.") - def _DecodeLatticeICE(self, deviceString): + def _DecodeLatticeICE(self, deviceString): # pylint:disable=unused-argument self.__vendor = Vendors.Lattice - def _DecodeLatticeLCM(self, deviceString): + def _DecodeLatticeLCM(self, deviceString): # pylint:disable=unused-argument self.__vendor = Vendors.Lattice def _DecodeLatticeLFE(self, deviceString): @@ -307,11 +309,11 @@ def _DecodeLatticeLFE(self, deviceString): if (self.__generation == 3): self._DecodeLatticeECP3(deviceString) elif (self.__generation == 5): self._DecodeLatticeECP5(deviceString) - else: raise ConfigurationException("Unknown Lattice ECP generation.") + else: raise ConfigurationException("Unknown Lattice ECP generation.") def _DecodeLatticeECP3(self, deviceString): - self.__subtype = SubTypes.NoSubType - self.__number = int(deviceString[5:8]) + self.__subtype = SubTypes.NoSubType + self.__number = int(deviceString[5:8]) def _DecodeLatticeECP5(self, deviceString): self.__device = Devices.ECP5 @@ -343,7 +345,7 @@ def _DecodeXilinx(self, deviceString): else: raise ConfigurationException("Unknown Xilinx device family.") - deviceRegExpStr = r"(?P[a-z]{0,2})" # device subtype - part 1 + deviceRegExpStr = r"(?P[a-z]{0,2})" # device subtype - part 1 deviceRegExpStr += r"(?P\d{1,4})" # device number deviceRegExpStr += r"(?P[t]{0,1})" # device subtype - part 2 deviceRegExpStr += r"(?P[-1-5]{2})" # speed grade @@ -356,34 +358,36 @@ def _DecodeXilinx(self, deviceString): subtype = deviceRegExpMatch.group('st1') + deviceRegExpMatch.group('st2') package = deviceRegExpMatch.group('pack') - if (subtype != ""): self.__subtype = SubTypes[subtype.upper()] - else: self.__subtype = SubTypes.NoSubType - - self.__number = int(deviceRegExpMatch.group('no')) - self.__speedGrade = int(deviceRegExpMatch.group('sg')) - self.__package = Packages[package.upper()] - self.__pinCount = int(deviceRegExpMatch.group('pins')) + if (subtype != ""): + try: self.__subtype = SubTypes[subtype.upper()] + except KeyError as ex: raise ConfigurationException("Unknown subtype '{0}'.".format(subtype)) from ex + else: self.__subtype = SubTypes.NoSubType + self.__number = int(deviceRegExpMatch.group('no')) + self.__speedGrade = int(deviceRegExpMatch.group('sg')) + try: self.__package = Packages[package.upper()] + except KeyError as ex: raise ConfigurationException("Unknown package '{0}'.".format(package)) from ex + self.__pinCount = int(deviceRegExpMatch.group('pins')) else: raise ConfigurationException("RegExp mismatch.") @property - def Vendor(self): return self.__vendor + def Vendor(self): return self.__vendor @property - def Family(self): return self.__family + def Family(self): return self.__family @property - def Device(self): return self.__device + def Device(self): return self.__device @property - def Generation(self): return self.__generation + def Generation(self): return self.__generation @property - def Number(self): return self.__number + def Number(self): return self.__number @property - def SpeedGrade(self): return self.__speedGrade + def SpeedGrade(self): return self.__speedGrade @property - def PinCount(self): return self.__pinCount + def PinCount(self): return self.__pinCount @property def Package(self): return self.__package @property - def Name(self): return self.FullName.upper() + def Name(self): return self.FullName.upper() # @CachedReadOnlyProperty @property @@ -396,12 +400,12 @@ def ShortName(self): number_format = "{num:03d}" else: number_format = "{num}" - return ("XC%i%s%s%s%s" % ( - self.__generation, - self.__family.Token, - subtype[0], - number_format.format(num=self.__number), - subtype[1] + return ("XC{gen}{fam}{st0}{num}{st1}".format( + gen=self.__generation, + fam=self.__family.Token, + st0=subtype[0], + num=number_format.format(num=self.__number), + st1=subtype[1] )).upper() elif (self.__vendor is Vendors.Altera): if self.__generation == 5: return self.__deviceString[2:] @@ -410,7 +414,7 @@ def ShortName(self): return "{0!s}{1!s}{2!s}-{3!s}F".format(self.__family.value, self.__generation, self.__subtype, self.__number) else: raise NotImplementedError("Device.ShortName() not implemented for vendor {0!s}".format(self.__vendor)) - + # @CachedReadOnlyProperty @property def FullName(self): @@ -422,15 +426,43 @@ def FullName(self): number_format = "{num:03d}" else: number_format = "{num}" - return ("XC%i%s%s%s%s%i%s%i" % ( - self.__generation, - self.__family.Token, - subtype[0], - number_format.format(num=self.__number), - subtype[1], - self.__speedGrade, - str(self.__package), - self.__pinCount + return ("XC{gen}{fam}{st0}{num}{st1}{sg}{pack}{pin}".format( + gen=self.__generation, + fam=self.__family.Token, + st0=subtype[0], + num=number_format.format(num=self.__number), + st1=subtype[1], + sg=self.__speedGrade, + pack=str(self.__package), + pin=self.__pinCount + )).upper() + elif (self.__vendor is Vendors.Altera): + return self.__deviceString + elif (self.__vendor is Vendors.Lattice): + return self.__deviceString + else: + raise NotImplementedError("Device.FullName() not implemented for vendor {0!s}".format(self.__vendor)) + + # @CachedReadOnlyProperty + @property + def FullName2(self): + if (self.__vendor is Vendors.Generic): + return "GENERIC" + elif (self.__vendor is Vendors.Xilinx): + subtype = self.__subtype.Groups + if (self.__family is XilinxFamilies.Zynq): + number_format = "{num:03d}" + else: + number_format = "{num}" + return ("XC{gen}{fam}{st0}{num}{st1}{pack}{pin}{sg}".format( + gen=self.__generation, + fam=self.__family.Token, + st0=subtype[0], + num=number_format.format(num=self.__number), + st1=subtype[1], + pack=str(self.__package), + pin=self.__pinCount, + sg=self.__speedGrade )).upper() elif (self.__vendor is Vendors.Altera): return self.__deviceString @@ -446,7 +478,7 @@ def FamilyName(self): return str(self.__family) else: return str(self.__family) + str(self.__generation) - + # @CachedReadOnlyProperty @property def Series(self): @@ -462,22 +494,22 @@ def Series(self): return "{0!s}-{1}".format(self.__family, self.__generation) elif self.__vendor is Vendors.Lattice: return "{0!s}{1!s}".format(self.__device, self.__subtype) - + def GetVariables(self): result = { - "DeviceShortName" : self.ShortName, - "DeviceFullName" : self.FullName, - "DeviceVendor" : str(self.Vendor), - "DeviceFamily" : str(self.Family), - "DeviceGeneration" : self.Generation, - "DeviceSeries" : self.Series, - "DeviceNumber" : self.Number, - "DeviceSpeedGrade" : self.SpeedGrade, - "DevicePackage" : self.Package, - "DevicePinCount" : self.PinCount + "DeviceShortName": self.ShortName, + "DeviceFullName": self.FullName, + "DeviceVendor": str(self.Vendor), + "DeviceFamily": str(self.Family), + "DeviceGeneration": self.Generation, + "DeviceSeries": self.Series, + "DeviceNumber": self.Number, + "DeviceSpeedGrade": self.SpeedGrade, + "DevicePackage": self.Package, + "DevicePinCount": self.PinCount } return result - + def __str__(self): return self.FullName @@ -519,15 +551,15 @@ def __init__(self, host, boardName=None, device=None): def Name(self): return self.__boardName @property def Device(self): return self.__device - + def GetVariables(self): result = { "BoardName" : self.__boardName } return result - + def __str__(self): return self.__boardName - + def __repr__(self): return str(self).lower() diff --git a/py/PoC/Entity.py b/py/PoC/Entity.py index 628be8c9..6ce64d56 100644 --- a/py/PoC/Entity.py +++ b/py/PoC/Entity.py @@ -1,29 +1,29 @@ # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2; replace-tabs off; indent-width 2; -# +# # ============================================================================== # Authors: Patrick Lehmann -# +# # Python Class: TODO -# +# # Description: # ------------------------------------ # TODO: -# - -# - +# - +# - # # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany # Chair for VLSI-Design, Diagnostics and Architecture -# +# # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at -# +# # http://www.apache.org/licenses/LICENSE-2.0 -# +# # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -102,18 +102,18 @@ class NamespaceRoot: __POCRoot_SectionName = "PoC" def __init__(self, host): - self._host = host + self._host = host - self.__libraries = OrderedDict() + self.__libraries = OrderedDict() self.__libraries[self.__POCRoot_Name.lower()] = (Library(host, self.__POCRoot_Name, self.__POCRoot_SectionName, self)) @property - def Libraries(self): return [lib for lib in self.__libraries.values()] + def Libraries(self): return [lib for lib in self.__libraries.values()] @property - def LibraryNames(self): return [libName for libName in self.__libraries.keys()] + def LibraryNames(self): return [libName for libName in self.__libraries.keys()] - def GetLibraries(self): return self.__libraries.values() - def GetLibraryNames(self): return self.__libraries.keys() + def GetLibraries(self): return self.__libraries.values() + def GetLibraryNames(self): return self.__libraries.keys() def __contains__(self, item): return item.lower() in self.__libraries @@ -143,8 +143,7 @@ def Parse(cls, value): for key,member in cls.__members__.items(): if (key == value): return member - else: - raise ValueError("'{0!s}' is not a valid {1}".format(value, cls.__name__)) + raise ValueError("'{0!s}' is not a valid {1}".format(value, cls.__name__)) class PathElement: @@ -269,6 +268,7 @@ def pprint(self, indent=0): buffer += ns.pprint(indent + 1) return buffer + class Library(Namespace): @property def Level(self): @@ -293,7 +293,7 @@ def GetCocoTestbenches(self): return self.GetTestbenches(TestbenchKind.CocoTest def GetNetlists(self, kind=NetlistKind.All): for entity in self.GetEntities(): - for nl in entity.GetNetlists(): + for nl in entity.GetNetlists(kind): if (nl.Kind in kind): yield nl @@ -344,6 +344,7 @@ def GetEntities(self): class IPCore(PathElement): def __init__(self, host, name, configSectionName, parent): + self._dependencies = [] # Testbenches self._vhdltb = [] # OrderedDict() self._cocotb = [] # OrderedDict() @@ -356,6 +357,9 @@ def __init__(self, host, name, configSectionName, parent): super().__init__(host, name, configSectionName, parent) + @property + def Dependencies(self): return self._dependencies + @property def VHDLTestbench(self): if (len(self._vhdltb) == 0): @@ -408,7 +412,7 @@ def VivadoNetlist(self): raise ConfigurationException("No Vivado netlist configured for '{0!s}'.".format(self)) return self._vivadoNetlist[0] - def GetNetlists(self, kind=NetlistKind.All): + def GetNetlists(self, kind=NetlistKind.All): # mccabe:disable=MC0001 if (NetlistKind.LatticeNetlist in kind): for nl in self._latticeNetlist: if nl.IsVisible: @@ -425,7 +429,6 @@ def GetNetlists(self, kind=NetlistKind.All): for nl in self._coreGenNetlist: if nl.IsVisible: yield nl - yield nl if (NetlistKind.VivadoNetlist in kind): for nl in self._vivadoNetlist: if nl.IsVisible: @@ -434,6 +437,10 @@ def GetNetlists(self, kind=NetlistKind.All): def _Load(self): super()._Load() section = self.ConfigSection + # load dependencies (as names) + self._dependencies = section['Dependencies'].split() + + # load testbenches and netlists for optionName in section: kind = section[optionName].lower() if (kind == "vhdltestbench"): @@ -452,7 +459,7 @@ def _Load(self): self._latticeNetlist.append(nl) # self._xstNetlist[optionName] = nl elif (kind == "quartusnetlist"): - sectionName = self._configSectionName.replace("IP", "QII") + "." + optionName + sectionName = self._configSectionName.replace("IP", "QMAP") + "." + optionName nl = QuartusNetlist(host=self._host, name=optionName, configSectionName=sectionName, parent=self) self._quartusNetlist.append(nl) # self._xstNetlist[optionName] = nl @@ -504,22 +511,25 @@ class Testbench(LazyPathElement): def __init__(self, host, name, configSectionName, parent): self._kind = TestbenchKind.Unknown self._moduleName = "" - self._filesFile = None + self._filesFile = None self._result = None super().__init__(host, name, configSectionName, parent) @property @LazyLoadTrigger - def ModuleName(self): return self._moduleName + def ModuleName(self): return self._moduleName @property @LazyLoadTrigger def FilesFile(self): return self._filesFile @property - def Result(self): return self._result + def Result(self): return self._result @Result.setter def Result(self, value): self._result = value + # def __setattr__(self, key, value): + # super().__setattr__(key, value) + def _LazyLoadable_Load(self): super()._LazyLoadable_Load() self._moduleName = self.ConfigSection["TestbenchModule"] @@ -577,26 +587,25 @@ def pprint(self, indent): class Netlist(LazyPathElement): def __init__(self, host, name, configSectionName, parent): - self._kind = NetlistKind.Unknown - self._moduleName = "" - self._rulesFile = None + self._kind = NetlistKind.Unknown + self._moduleName = "" + self._rulesFile = None super().__init__(host, name, configSectionName, parent) @property @LazyLoadTrigger - def ModuleName(self): return self._moduleName + def ModuleName(self): return self._moduleName @property @LazyLoadTrigger - def RulesFile(self): return self._rulesFile + def RulesFile(self): return self._rulesFile def _LazyLoadable_Load(self): super()._LazyLoadable_Load() - self._moduleName = self.ConfigSection["TopLevel"] - value = self.ConfigSection["RulesFile"] - if (value != ""): - self._rulesFile = Path(value) - else: - self._rulesFile = None + + self._moduleName = self.ConfigSection["TopLevel"] + self._dependencies = self.ConfigSection['Dependencies'].split() + value = self.ConfigSection["RulesFile"] + self._rulesFile = Path(value) if (value != "") else None class XstNetlist(Netlist): @@ -667,10 +676,10 @@ def __init__(self, host, name, configSectionName, parent): @property @LazyLoadTrigger - def FilesFile(self): return self._filesFile + def FilesFile(self): return self._filesFile @property - def QsfFile(self): return self._qsfFile + def QsfFile(self): return self._qsfFile @QsfFile.setter def QsfFile(self, value): if isinstance(value, str): @@ -728,18 +737,18 @@ def pprint(self, indent): class CoreGeneratorNetlist(Netlist): def __init__(self, host, name, configSectionName, parent): - self._xcoFile = None + self._xcoFile = None super().__init__(host, name, configSectionName, parent) - self._kind = NetlistKind.CoreGeneratorNetlist + self._kind = NetlistKind.CoreGeneratorNetlist def __str__(self): return super().__str__() + " (Core Generator netlist)" @property - def FilesFile(self): return None + def FilesFile(self): return None @property - def XcoFile(self): return self._xcoFile + def XcoFile(self): return self._xcoFile def _LazyLoadable_Load(self): super()._LazyLoadable_Load() @@ -754,17 +763,17 @@ def pprint(self, indent): class VivadoNetlist(Netlist): def __init__(self, host, name, configSectionName, parent): - self._filesFile = None - self._tclFile = None + self._filesFile = None + self._tclFile = None super().__init__(host, name, configSectionName, parent) self._kind = NetlistKind.VivadoNetlist @property @LazyLoadTrigger - def FilesFile(self): return self._filesFile + def FilesFile(self): return self._filesFile @property - def TclFile(self): return self._tclFile + def TclFile(self): return self._tclFile @TclFile.setter def TclFile(self, value): if isinstance(value, str): @@ -773,7 +782,7 @@ def TclFile(self, value): def _LazyLoadable_Load(self): super()._LazyLoadable_Load() - self._filesFile = Path(self.ConfigSection["FilesFile"]) + self._filesFile = Path(self.ConfigSection["FilesFile"]) def __str__(self): return super().__str__() + " (Vivado netlist)" @@ -832,10 +841,10 @@ def __init__(self, host, fqn, defaultLibrary="PoC", defaultType=EntityTypes.Sour def Root(self): return self.__host.Root - + @property def Entity(self): return self.__parts[-1] def __str__(self): - return ".".join([p.Name for p in self.__parts]) + return str(self.Entity) diff --git a/py/PoC/Query.py b/py/PoC/Query.py index 3d5db9ef..0a2f009b 100644 --- a/py/PoC/Query.py +++ b/py/PoC/Query.py @@ -41,7 +41,7 @@ from pathlib import Path from Base.Exceptions import NotConfiguredException, PlatformNotSupportedException -from Base.Configuration import ConfigurationException +from Base.Configuration import ConfigurationException class Query: @@ -68,8 +68,11 @@ def QueryConfiguration(self, query): parts = query.split(":") if (len(parts) == 2): sectionName = parts[0] - optionName = parts[1] - result = self.PoCConfig[sectionName][optionName] + optionName = parts[1] + try: + result = self.PoCConfig[sectionName][optionName] + except KeyError as ex: + raise ConfigurationException("Requested setting '{0}:{1}' not found.".format(sectionName, optionName)) from ex else: raise ConfigurationException("Syntax error in query string '{0}'".format(query)) @@ -93,19 +96,26 @@ def _GetModelSimBinaryDirectory(self): raise NotConfiguredException("ERROR: ModelSim is not configured on this system.") def _GetXilinxISESettingsFile(self): - iseInstallationDirectoryPath = Path(self.PoCConfig['INSTALL.Xilinx.ISE']['InstallationDirectory']) - if (self.Platform == "Windows"): - return iseInstallationDirectoryPath / "settings64.bat" - elif (self.Platform == "Linux"): - return iseInstallationDirectoryPath / "settings64.sh" + if (len(self.PoCConfig.options('INSTALL.Xilinx.ISE')) != 0): + iseInstallationDirectoryPath = Path(self.PoCConfig['INSTALL.Xilinx.ISE']['InstallationDirectory']) + if (self.Platform == "Windows"): + return iseInstallationDirectoryPath / "settings64.bat" + elif (self.Platform == "Linux"): + return iseInstallationDirectoryPath / "settings64.sh" + else: + raise PlatformNotSupportedException(self.Platform) else: - raise PlatformNotSupportedException(self.Platform) + raise NotConfiguredException("ERROR: Xilinx ISE is not configured on this system.") def _GetXilinxVivadoSettingsFile(self): - iseInstallationDirectoryPath = Path(self.PoCConfig['INSTALL.Xilinx.Vivado']['InstallationDirectory']) - if (self.Platform == "Windows"): - return iseInstallationDirectoryPath / "settings64.bat" - elif (self.Platform == "Linux"): - return iseInstallationDirectoryPath / "settings64.sh" + if (len(self.PoCConfig.options('INSTALL.Xilinx.Vivado')) != 0): + iseInstallationDirectoryPath = Path(self.PoCConfig['INSTALL.Xilinx.Vivado']['InstallationDirectory']) + if (self.Platform == "Windows"): + return iseInstallationDirectoryPath / "settings64.bat" + elif (self.Platform == "Linux"): + return iseInstallationDirectoryPath / "settings64.sh" + else: + raise PlatformNotSupportedException(self.Platform) else: - raise PlatformNotSupportedException(self.Platform) + raise NotConfiguredException("ERROR: Xilinx ISE is not configured on this system.") + diff --git a/py/PoC/Solution.py b/py/PoC/Solution.py index b477c0ed..c05c0f26 100644 --- a/py/PoC/Solution.py +++ b/py/PoC/Solution.py @@ -5,7 +5,7 @@ # ============================================================================== # Authors: Patrick Lehmann # -# Python Class: TODO +# Python Class: TODO # # Description: # ------------------------------------ @@ -171,7 +171,10 @@ def CreateFiles(self): solutionConfigPath = self._path / ".poc" if (not self._path.is_absolute()): solutionConfigPath = self._host.Directories.Root / solutionConfigPath - solutionConfigPath.mkdir(parents=True) + try: + solutionConfigPath.mkdir(parents=True) + except OSError as ex: + raise ConfigurationException("Error while creating '{0!s}'.".format(solutionConfigPath)) from ex solutionConfigFile = solutionConfigPath / self.__SOLUTION_CONFIG_FILE__ with solutionConfigFile.open('w') as fileHandle: @@ -299,25 +302,23 @@ def __init__(self, file, project = None, fileSet = None): super().__init__(file, project=project, fileSet=fileSet) FilesParserMixIn.__init__(self) - self._variables = None + self._variables = None - # self.__classInclude - self._classFileListFile = FileListFile - self._classVHDLSourceFile = VHDLSourceFile + self._classFileListFile = FileListFile + self._classVHDLSourceFile = VHDLSourceFile self._classVerilogSourceFile = VerilogSourceFile - self._classCocotbSourceFile = CocotbSourceFile + self._classCocotbSourceFile = CocotbSourceFile - def Parse(self): - # print("FileListFile.Parse:") - if (self._fileSet is None): raise CommonException("File '{0!s}' is not associated to a fileset.".format(self._file)) - if (self._project is None): raise CommonException("File '{0!s}' is not associated to a project.".format(self._file)) - if (self._project.RootDirectory is None): raise CommonException("No RootDirectory configured for this project.") + def Parse(self, host): + if (self._fileSet is None): raise CommonException("File '{0!s}' is not associated to a fileset.".format(self._file)) + if (self._project is None): raise CommonException("File '{0!s}' is not associated to a project.".format(self._file)) + if (self._project.RootDirectory is None): raise CommonException("No RootDirectory configured for this project.") # prepare FilesParserMixIn environment self._rootDirectory = self.Project.RootDirectory - self._variables = self.Project.GetVariables() + self._variables = self.Project.GetVariables() self._Parse() - self._Resolve() + self._Resolve(host) def CopyFilesToFileSet(self): for file in self._files: @@ -353,4 +354,3 @@ def Parse(self): def __str__(self): return "FileList file: '{0!s}".format(self._file) - diff --git a/py/PoC/TestCase.py b/py/PoC/TestCase.py index b10e36db..b3413edd 100644 --- a/py/PoC/TestCase.py +++ b/py/PoC/TestCase.py @@ -38,13 +38,13 @@ Exit.printThisIsNoExecutableFile("The PoC-Library - Python Module PoC.Query") -from collections import OrderedDict -from datetime import datetime -from enum import Enum, unique +from collections import OrderedDict +from datetime import datetime +from enum import Enum, unique @unique -class Status(Enum): +class SimulationStatus(Enum): Unknown = 0 SystemError = 1 InternalError = 2 @@ -55,8 +55,17 @@ class Status(Enum): SimulationNoAsserts = 15 SimulationSuccess = 20 +@unique +class CompileStatus(Enum): + Unknown = 0 + SystemError = 1 + InternalError = 2 + CompileError = 6 + CompileFailed = 10 + CompileSuccess = 20 + -class TestElement: +class ElementBase: def __init__(self, name, parent): self._name = name self._parent = parent @@ -69,74 +78,118 @@ def Parent(self): return self._parent def __str__(self): return "{0!s}.{1}".format(self._parent, self._name) -class TestGroup(TestElement): + +class GroupBase(ElementBase): def __init__(self, name, parent): super().__init__(name, parent) - self._parent = None - self._testGroups = OrderedDict() - self._testCases = OrderedDict() + self._groups = OrderedDict() + self._tests = OrderedDict() def __getitem__(self, item): - try: - return self._testCases[item] - except KeyError: - return self._testGroups[item] - - def __setitem__(self, key, value): - if isinstance(value, TestGroup): - self._testGroups[key] = value - elif isinstance(value, TestCase): - self._testCases[key] = value - else: - raise ValueError("Parameter 'value' is not of type TestGroup or TestCase") + try: return self._tests[item] + except KeyError: return self._groups[item] def __len__(self): - return sum([len(group) for group in self._testGroups.values()]) + len(self._testCases) + return sum([len(group) for group in self._groups.values()]) + len(self._tests) @property - def TestGroups(self): return self._testGroups + def Groups(self): return self._groups @property - def TestCases(self): return self._testCases + def Count(self): return len(self) + + +class TestGroup(GroupBase): + def __setitem__(self, key, value): + if isinstance(value, TestGroup): self._groups[key] = value + elif isinstance(value, TestCase): self._tests[key] = value + else: raise ValueError("Parameter 'value' is not of type TestGroup or TestCase") @property - def Count(self): - return len(self) + def TestCases(self): return self._tests @property def PassedCount(self): - return sum([tg.PassedCount for tg in self._testGroups.values()]) \ - + sum([1 for tc in self._testCases.values() if tc.Status is Status.SimulationSuccess]) + return sum([tg.PassedCount for tg in self._groups.values()]) \ + + sum([1 for tc in self._tests.values() if tc.Status is SimulationStatus.SimulationSuccess]) @property def NoAssertsCount(self): - return sum([tg.NoAssertsCount for tg in self._testGroups.values()]) \ - + sum([1 for tc in self._testCases.values() if tc.Status is Status.SimulationNoAsserts]) + return sum([tg.NoAssertsCount for tg in self._groups.values()]) \ + + sum([1 for tc in self._tests.values() if tc.Status is SimulationStatus.SimulationNoAsserts]) @property def FailedCount(self): - return sum([tg.FailedCount for tg in self._testGroups.values()]) \ - + sum([1 for tc in self._testCases.values() if tc.Status is Status.SimulationFailed]) + return sum([tg.FailedCount for tg in self._groups.values()]) \ + + sum([1 for tc in self._tests.values() if tc.Status is SimulationStatus.SimulationFailed]) @property def ErrorCount(self): - return sum([tg.ErrorCount for tg in self._testGroups.values()]) \ - + sum([1 for tc in self._testCases.values() if tc.Status - in (Status.SystemError, Status.AnalyzeError, Status.ElaborationError, Status.SimulationError)]) + errors = (SimulationStatus.SystemError, SimulationStatus.InternalError, SimulationStatus.AnalyzeError, SimulationStatus.ElaborationError, SimulationStatus.SimulationError) + return sum([tg.ErrorCount for tg in self._groups.values()]) \ + + sum([1 for tc in self._tests.values() if tc.Status in errors]) -class TestSuite(TestGroup): - def __init__(self): - super().__init__("PoC", None) +class SynthesisGroup(GroupBase): + def __setitem__(self, key, value): + if isinstance(value, SynthesisGroup): self._groups[key] = value + elif isinstance(value, Synthesis): self._tests[key] = value + else: raise ValueError("Parameter 'value' is not of type SynthesisGroup or Synthesis") + + @property + def Synthesises(self): return self._tests + + @property + def SuccessCount(self): + return sum([tg.SuccessCount for tg in self._groups.values()]) \ + + sum([1 for tc in self._tests.values() if tc.Status is CompileStatus.CompileSuccess]) + + @property + def FailedCount(self): + return sum([tg.FailedCount for tg in self._groups.values()]) \ + + sum([1 for tc in self._tests.values() if tc.Status is CompileStatus.CompileFailed]) + + @property + def ErrorCount(self): + errors = (CompileStatus.SystemError, CompileStatus.InternalError, CompileStatus.CompileError) + return sum([tg.ErrorCount for tg in self._groups.values()]) \ + + sum([1 for tc in self._tests.values() if tc.Status in errors]) + - self._startedAt = datetime.now() - self._endedAt = None - self._initRuntime = None - self._overallRuntime = None +class SuiteMixIn: + def __init__(self): + self._startedAt = datetime.now() + self._endedAt = None + self._initRuntime = None + self._overallRuntime = None def __str__(self): return self._name + def StartTimer(self): + now = datetime.now() + self.__initRuntime = now - self._startedAt + self._startedAt = now + + def StopTimer(self): + self._endedAt = datetime.now() + self._overallRuntime = self._endedAt - self._startedAt + + @property + def StartTime(self): return self._startedAt + @property + def EndTime(self): return self._endedAt + @property + def InitializationTime(self): return self._initRuntime.microseconds + @property + def OverallRunTime(self): return self._overallRuntime.seconds + + +class TestSuite(TestGroup, SuiteMixIn): + def __init__(self): + super().__init__("PoC", None) + SuiteMixIn.__init__(self) + @property def IsAllPassed(self): return (self.Count == self.PassedCount + self.NoAssertsCount) @@ -155,37 +208,44 @@ def AddTestCase(self, testCase): testCaseName = testbenchPath[-2].Name cur[testCaseName] = testCase - def StartTimer(self): - now = datetime.now() - self.__initRuntime = now - self._startedAt - self._startedAt = now - def StopTimer(self): - self._endedAt = datetime.now() - self._overallRuntime = self._endedAt - self._startedAt +class SynthesisSuite(SynthesisGroup, SuiteMixIn): + def __init__(self): + super().__init__("PoC", None) + SuiteMixIn.__init__(self) @property - def StartTime(self): return self._startedAt - @property - def EndTime(self): return self._endedAt - @property - def InitializationTime(self): return self._initRuntime.microseconds - @property - def OverallRunTime(self): return self._overallRuntime.seconds + def IsAllSuccess(self): + return (self.Count == self.SuccessCount) + def AddSynthesis(self, synthesis): + cur = self + netlistPath = synthesis.Netlist.Path + for item in netlistPath[:-2]: + try: + synthGroup = cur[item.Name] + except KeyError: + synthGroup = SynthesisGroup(item.Name, cur) + cur[item.Name] = synthGroup + cur = synthGroup + + synthesisName = netlistPath[-2].Name + cur[synthesisName] = synthesis -class TestCase(TestElement): - def __init__(self, testbench): - super().__init__(testbench.Parent.Name, None) - self._testbench = testbench - self._testGroup = None - self._status = Status.Unknown - self._warnings = [] - self._errors = [] - - self._startedAt = None - self._endedAt = None - self._overallRuntime = None + +class TestBase(ElementBase): + def __init__(self, test): + super().__init__(test.Parent.Name, None) + + self._test = test + + self._status = None + self._warnings = [] + self._errors = [] + + self._startedAt = None + self._endedAt = None + self._overallRuntime = None @property def Parent(self): return self._parent @@ -193,38 +253,56 @@ def Parent(self): return self._parent def Parent(self, value): self._parent = value @property - def Testbench(self): return self._testbench - - @property - def TestGroup(self): return self._testGroup + def TestGroup(self): return self._group @TestGroup.setter - def TestGroup(self, value): self._testGroup = value + def TestGroup(self, value): self._group = value @property def Status(self): return self._status @Status.setter def Status(self, value): self._status = value - def UpdateStatus(self, testbenchResult): - if (testbenchResult is testbenchResult.NotRun): - self._status = Status.Unknown - elif (testbenchResult is testbenchResult.Error): - self._status = Status.SimulationError - elif (testbenchResult is testbenchResult.Failed): - self._status = Status.SimulationFailed - elif (testbenchResult is testbenchResult.NoAsserts): - self._status = Status.SimulationNoAsserts - elif (testbenchResult is testbenchResult.Passed): - self._status = Status.SimulationSuccess - else: - raise IndentationError("Wuhu") - def StartTimer(self): - self._startedAt = datetime.now() + self._startedAt = datetime.now() def StopTimer(self): - self._endedAt = datetime.now() - self._overallRuntime = self._endedAt - self._startedAt + self._endedAt = datetime.now() + self._overallRuntime = self._endedAt - self._startedAt + + @property + def OverallRunTime(self): return self._overallRuntime.seconds + + +class TestCase(TestBase): + def __init__(self, testbench): + super().__init__(testbench) + + self._status = SimulationStatus.Unknown @property - def OverallRunTime(self): return self._overallRuntime.seconds + def Testbench(self): return self._test + + + def UpdateStatus(self, testResult): + if (testResult is testResult.NotRun): self._status = SimulationStatus.Unknown + elif (testResult is testResult.Error): self._status = SimulationStatus.SimulationError + elif (testResult is testResult.Failed): self._status = SimulationStatus.SimulationFailed + elif (testResult is testResult.NoAsserts): self._status = SimulationStatus.SimulationNoAsserts + elif (testResult is testResult.Passed): self._status = SimulationStatus.SimulationSuccess + else: raise IndentationError("Wuhu1") + + +class Synthesis(TestBase): + def __init__(self, synthesis): + super().__init__(synthesis) + + self._status = CompileStatus.Unknown + + @property + def Netlist(self): return self._test + + def UpdateStatus(self, synthResult): + if (synthResult is synthResult.NotRun): self._status = CompileStatus.Unknown + elif (synthResult is synthResult.Error): self._status = CompileStatus.CompileError + elif (synthResult is synthResult.Success): self._status = CompileStatus.CompileSuccess + else: raise IndentationError("Wuhu2") diff --git a/py/PoC/__init__.py b/py/PoC/__init__.py index ee05e3f6..78c2cfdc 100644 --- a/py/PoC/__init__.py +++ b/py/PoC/__init__.py @@ -1,28 +1,28 @@ # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2; replace-tabs off; indent-width 2; -# +# # ============================================================================== # Authors: Patrick Lehmann -# +# # Python Sub Module: Saves The PoC-Library configuration as python source code. -# +# # Description: # ------------------------------------ # TODO: -# +# # # License: # ============================================================================== # Copyright 2007-2015 Technische Universitaet Dresden - Germany # Chair for VLSI-Design, Diagnostics and Architecture -# +# # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at -# +# # http://www.apache.org/licenses/LICENSE-2.0 -# +# # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. diff --git a/py/Processor/__init__.py b/py/Processor/__init__.py index 1b54e767..32a31622 100644 --- a/py/Processor/__init__.py +++ b/py/Processor/__init__.py @@ -1,28 +1,28 @@ # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2; replace-tabs off; indent-width 2; -# +# # ============================================================================== # Authors: Patrick Lehmann -# +# # Python Sub Module: Saves The PoC-Library configuration as python source code. -# +# # Description: # ------------------------------------ # TODO: -# +# # # License: # ============================================================================== # Copyright 2007-2015 Technische Universitaet Dresden - Germany # Chair for VLSI-Design, Diagnostics and Architecture -# +# # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at -# +# # http://www.apache.org/licenses/LICENSE-2.0 -# +# # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. diff --git a/py/RULES.md b/py/RULES.md deleted file mode 100644 index 43d6bffa..00000000 --- a/py/RULES.md +++ /dev/null @@ -1,86 +0,0 @@ - -# `*.rules` Files - -If the pre- or post-processing rules (copying, patching, deleting) for IP cores -are to long or to many, then it's possible to out-source these rules into a -separate `*.rules` file. A rules file supports 2 main sections: `PreProcessRules` -and `PostProcessRules`. Line comments start with `#`. - -### Main Sections - -Rules files support two main sections: - - - `PreProcessRules .. End PreProcessRules` - The listed rules in this section are processed before the IP core generation. - It's possible to copy additional source files into the working directory or to - patch source files before usage. - - Allowed rules: - - - `Copy ...` - - `File ...` - - - `PostProcessRules .. End PostProcessRules` - These rules are processed after the successful IP core generation. Additional - to the rules from the `PreProcessRules`, it's possible to delete generated files. - (Output directory clean-up.) - - Allowed rules: - - - `Copy ...` - - `File ...` - - `Delete ...` - -### Rules - -There are three possible rules: - - - `Copy " To ""` - This rule copies a source file to a destination file. The destination file name - can differ from source file (rename file while copying). Non existent parent - directories in the path to the destination file, are created before copying. - - `File "" .. End File` - This rule allows several sub rules to be applied to a single file: - - - `Replace "" With "" [Options ]` - This file-base sub-rule applies a regular expression replacement to a file. - The first parameter `` is a Python Regular Expression, which - is used to find a match in the file. The second parameter `` is - the corresponding replacement pattern. Both strings have to escape `\` and `"` - characters by an additional `\`-character. No other character has to be escaped. - - It's possible to pass one to three optional options to the Python `re` module: - - - `Multiline` - - `DotAll` - - `CaseInsensitive` - - - `Delete ""` - This rule deletes a file. - -### Using String Interpolation - -Each string (file name, pattern) can include `${[:]}` variables. -These variables are looked up in the ini-file based database and interpolated according -to that rules. A variable can contain a single option name (search in the current section) -or a section name plus option name, delimited by a `:`-sign. Variables can be nested. The -interpolation starts at the section, which referenced the rules files. - -*Note:* It's possible to create a new option in the netlist's section (in the ini-file) and -use it in the rules file like a local variable. This is useful for long concatenated paths. - -*Note:* Look into the *.files file help for more details on string interpolation. - -### Execution order - -The listed rules are executed in order of appearance in the rules files. Here is the execution -order in relation to the IP core generation: - - 1. Pre-process rules - 1. Copy rules - 2. Replace rules - 2. *Generate IP core* - 3. Pre-process rules - 1. Copy rules - 2. Replace rules - 2. Delete rules diff --git a/py/Simulator/ActiveHDLSimulator.py b/py/Simulator/ActiveHDLSimulator.py index 47d6da29..e0e6c706 100644 --- a/py/Simulator/ActiveHDLSimulator.py +++ b/py/Simulator/ActiveHDLSimulator.py @@ -1,13 +1,13 @@ # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2; replace-tabs off; indent-width 2; -# +# # ============================================================================== # Authors: Patrick Lehmann # Martin Zabel -# +# # Python Class: TODO -# +# # Description: # ------------------------------------ # TODO: @@ -16,13 +16,13 @@ # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany # Chair for VLSI-Design, Diagnostics and Architecture -# +# # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at -# +# # http://www.apache.org/licenses/LICENSE-2.0 -# +# # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -43,7 +43,7 @@ from pathlib import Path from Base.Exceptions import NotConfiguredException -from Base.Project import FileTypes, VHDLVersion, ToolChain, Tool +from Base.Project import FileTypes, ToolChain, Tool from Base.Simulator import SimulatorException, Simulator as BaseSimulator, VHDL_TESTBENCH_LIBRARY_NAME, SkipableSimulatorException from ToolChains.Aldec.ActiveHDL import ActiveHDL, ActiveHDLException @@ -52,28 +52,24 @@ class Simulator(BaseSimulator): _TOOL_CHAIN = ToolChain.Aldec_ActiveHDL _TOOL = Tool.Aldec_aSim - def __init__(self, host, guiMode): - super().__init__(host) - - self._guiMode = guiMode + def __init__(self, host, dryRun, guiMode): + super().__init__(host, dryRun) - self._entity = None - self._testbenchFQN = None - self._vhdlVersion = None + self._guiMode = guiMode + self._vhdlVersion = None self._vhdlGenerics = None + self._toolChain = None - self._toolChain = None - - activeHDLFilesDirectoryName = host.PoCConfig['CONFIG.DirectoryNames']['ActiveHDLFiles'] + activeHDLFilesDirectoryName = host.PoCConfig['CONFIG.DirectoryNames']['ActiveHDLFiles'] self.Directories.Working = host.Directories.Temp / activeHDLFilesDirectoryName self.Directories.PreCompiled = host.Directories.PreCompiled / activeHDLFilesDirectoryName - + self._PrepareSimulationEnvironment() self._PrepareSimulator() def _PrepareSimulator(self): # create the Active-HDL executable factory - self._LogVerbose("Preparing Active-HDL simulator.") + self.LogVerbose("Preparing Active-HDL simulator.") for sectionName in ['INSTALL.Aldec.ActiveHDL', 'INSTALL.Lattice.ActiveHDL']: if (len(self.Host.PoCConfig.options(sectionName)) != 0): break @@ -84,7 +80,7 @@ def _PrepareSimulator(self): asimSection = self.Host.PoCConfig[sectionName] binaryPath = Path(asimSection['BinaryDirectory']) version = asimSection['Version'] - self._toolChain = ActiveHDL(self.Host.Platform, binaryPath, version, logger=self.Logger) + self._toolChain = ActiveHDL(self.Host.Platform, self.DryRun, binaryPath, version, logger=self.Logger) def _RunAnalysis(self, _): # create a ActiveHDLVHDLCompiler instance @@ -101,10 +97,7 @@ def _RunAnalysis(self, _): # create a ActiveHDLVHDLCompiler instance acom = self._toolChain.GetVHDLCompiler() - if (self._vhdlVersion == VHDLVersion.VHDL87): acom.Parameters[acom.SwitchVHDLVersion] = "87" - elif (self._vhdlVersion == VHDLVersion.VHDL93): acom.Parameters[acom.SwitchVHDLVersion] = "93" - elif (self._vhdlVersion == VHDLVersion.VHDL02): acom.Parameters[acom.SwitchVHDLVersion] = "2002" - elif (self._vhdlVersion == VHDLVersion.VHDL08): acom.Parameters[acom.SwitchVHDLVersion] = "2008" + acom.Parameters[acom.SwitchVHDLVersion] = repr(self._vhdlVersion) # run acom compile for each VHDL file for file in self._pocProject.Files(fileType=FileTypes.VHDLSourceFile): @@ -124,7 +117,7 @@ def _RunSimulation(self, testbench): return self._RunSimulationWithGUI(testbench) # tclBatchFilePath = self.Host.Directories.Root / self.Host.PoCConfig[testbench.ConfigSectionName]['aSimBatchScript'] - + # create a ActiveHDLSimulator instance aSim = self._toolChain.GetSimulator() aSim.Parameters[aSim.SwitchBatchCommand] = "asim -lib {0} {1}; run -all; bye".format(VHDL_TESTBENCH_LIBRARY_NAME, testbench.ModuleName) @@ -154,10 +147,10 @@ def _RunSimulationWithGUI(self, testbench): # aSim.Title = testbench.ModuleName # # if (tclWaveFilePath.exists()): - # self._LogDebug("Found waveform script: '{0!s}'".format(tclWaveFilePath)) + # self.LogDebug("Found waveform script: '{0!s}'".format(tclWaveFilePath)) # aSim.BatchCommand = "do {0!s}; do {1!s}".format(tclWaveFilePath, tclGUIFilePath) # else: - # self._LogDebug("Didn't find waveform script: '{0!s}'. Loading default commands.".format(tclWaveFilePath)) + # self.LogDebug("Didn't find waveform script: '{0!s}'. Loading default commands.".format(tclWaveFilePath)) # aSim.BatchCommand = "add wave *; do {0!s}".format(tclGUIFilePath) # # aSim.TopLevel = "{0}.{1}".format(VHDL_TESTBENCH_LIBRARY_NAME, testbench.ModuleName) diff --git a/py/Simulator/CocotbSimulator.py b/py/Simulator/CocotbSimulator.py index acdb9611..692598d9 100644 --- a/py/Simulator/CocotbSimulator.py +++ b/py/Simulator/CocotbSimulator.py @@ -1,30 +1,30 @@ # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2; replace-tabs off; indent-width 2; -# +# # ============================================================================== # Authors: Patrick Lehmann # Martin Zabel -# +# # Python Class: TODO -# +# # Description: # ------------------------------------ # TODO: -# - -# - +# - +# - # # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany # Chair for VLSI-Design, Diagnostics and Architecture -# +# # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at -# +# # http://www.apache.org/licenses/LICENSE-2.0 -# +# # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -59,15 +59,12 @@ class Simulator(BaseSimulator): _TOOL = Tool.Cocotb_QuestaSim _COCOTB_SIMBUILD_DIRECTORY = "sim_build" - def __init__(self, host, guiMode): - super().__init__(host) + def __init__(self, host, dryRun, guiMode): + super().__init__(host, dryRun) - self._guiMode = guiMode + self._guiMode = guiMode - self._entity = None - self._testbenchFQN = None - - configSection = host.PoCConfig['CONFIG.DirectoryNames'] + configSection = host.PoCConfig['CONFIG.DirectoryNames'] self.Directories.Working = host.Directories.Temp / configSection['CocotbFiles'] self.Directories.PreCompiled = host.Directories.PreCompiled / configSection['QuestaSimFiles'] @@ -76,7 +73,7 @@ def __init__(self, host, guiMode): def _PrepareSimulator(self): # create the Cocotb executable factory - self._LogVerbose("Preparing Cocotb simulator.") + self.LogVerbose("Preparing Cocotb simulator.") def RunAll(self, fqnList, *args, **kwargs): self._testSuite.StartTimer() @@ -90,7 +87,7 @@ def RunAll(self, fqnList, *args, **kwargs): testbench = entity.CocoTestbench self.TryRun(testbench, *args, **kwargs) except KeyboardInterrupt: - self._LogError("Received a keyboard interrupt.") + self.LogError("Received a keyboard interrupt.") finally: self._testSuite.StopTimer() @@ -98,12 +95,14 @@ def RunAll(self, fqnList, *args, **kwargs): return self._testSuite.IsAllPassed - def _RunSimulation(self, testbench): + def _RunSimulation(self, testbench): # mccabe:disable=MC0001 # select modelsim.ini from precompiled precompiledModelsimIniPath = self.Directories.PreCompiled device_vendor = self._pocProject.Board.Device.Vendor if device_vendor is Vendors.Altera: precompiledModelsimIniPath /= self.Host.PoCConfig['CONFIG.DirectoryNames']['AlteraSpecificFiles'] + elif device_vendor is Vendors.Lattice: + precompiledModelsimIniPath /= self.Host.PoCConfig['CONFIG.DirectoryNames']['LatticeSpecificFiles'] elif device_vendor is Vendors.Xilinx: precompiledModelsimIniPath /= self.Host.PoCConfig['CONFIG.DirectoryNames']['XilinxSpecificFiles'] @@ -115,13 +114,21 @@ def _RunSimulation(self, testbench): simBuildPath = self.Directories.Working / self._COCOTB_SIMBUILD_DIRECTORY # create temporary directory for Cocotb if not existent if (not (simBuildPath).exists()): - self._LogVerbose("Creating build directory for simulator files.") - self._LogDebug("Build directory: {0!s}".format(simBuildPath)) - simBuildPath.mkdir(parents=True) + self.LogVerbose("Creating build directory for simulator files.") + self.LogDebug("Build directory: {0!s}".format(simBuildPath)) + try: + simBuildPath.mkdir(parents=True) + except OSError as ex: + raise SimulatorException("Error while creating '{0!s}'.".format(simBuildPath)) from ex # write local modelsim.ini modelsimIniPath = simBuildPath / "modelsim.ini" - if modelsimIniPath.exists(): modelsimIniPath.unlink() + if modelsimIniPath.exists(): + try: + modelsimIniPath.unlink() + except OSError as ex: + raise SimulatorException("Error while deleting '{0!s}'.".format(modelsimIniPath)) from ex + with modelsimIniPath.open('w') as fileHandle: fileContent = dedent("""\ [Library] @@ -130,7 +137,7 @@ def _RunSimulation(self, testbench): fileHandle.write(fileContent) # - self._LogNormal("Running simulation...") + self.LogNormal("Running simulation...") cocotbTemplateFilePath = self.Host.Directories.Root / \ self.Host.PoCConfig[testbench.ConfigSectionName]['CocotbMakefile'] # depends on testbench topLevel = testbench.TopLevel @@ -145,21 +152,21 @@ def _RunSimulation(self, testbench): vhdlSources += str(file.Path) + " " # copy Cocotb (Python) files to temp directory - self._LogVerbose("Copying Cocotb (Python) files into temporary directory.") + self.LogVerbose("Copying Cocotb (Python) files into temporary directory.") cocotbTempDir = str(self.Directories.Working) for file in self._pocProject.Files(fileType=FileTypes.CocotbSourceFile): if (not file.Path.exists()): raise SimulatorException("Cannot copy '{0!s}' to Cocotb temp directory.".format(file.Path)) \ from FileNotFoundError(str(file.Path)) - self._LogDebug("copy {0!s} {1}".format(file.Path, cocotbTempDir)) + self.LogDebug("copy {0!s} {1}".format(file.Path, cocotbTempDir)) try: shutil.copy(str(file.Path), cocotbTempDir) except OSError as ex: raise SimulatorException("Error while copying '{0!s}'.".format(file.Path)) from ex # read/write Makefile template - self._LogVerbose("Generating Makefile...") - self._LogDebug("Reading Cocotb Makefile template file from '{0!s}'".format(cocotbTemplateFilePath)) + self.LogVerbose("Generating Makefile...") + self.LogDebug("Reading Cocotb Makefile template file from '{0!s}'".format(cocotbTemplateFilePath)) with cocotbTemplateFilePath.open('r') as fileHandle: cocotbMakefileContent = fileHandle.read() @@ -168,11 +175,11 @@ def _RunSimulation(self, testbench): TopLevel=topLevel, CocotbModule=cocotbModule) cocotbMakefilePath = self.Directories.Working / "Makefile" - self._LogDebug("Writing Cocotb Makefile to '{0!s}'".format(cocotbMakefilePath)) + self.LogDebug("Writing Cocotb Makefile to '{0!s}'".format(cocotbMakefilePath)) with cocotbMakefilePath.open('w') as fileHandle: fileHandle.write(cocotbMakefileContent) # execute make - make = Make(self.Host.Platform, logger=self.Host.Logger) + make = Make(self.Host.Platform, self.DryRun, logger=self.Logger) if self._guiMode: make.Parameters[Make.SwitchGui] = 1 testbench.Result = make.RunCocotb() diff --git a/py/Simulator/GHDLSimulator.py b/py/Simulator/GHDLSimulator.py index f2a5513b..173fe967 100644 --- a/py/Simulator/GHDLSimulator.py +++ b/py/Simulator/GHDLSimulator.py @@ -1,30 +1,30 @@ # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2; replace-tabs off; indent-width 2; -# +# # ============================================================================== # Authors: Patrick Lehmann # Martin Zabel -# +# # Python Class: TODO -# +# # Description: # ------------------------------------ # TODO: -# - -# - +# - +# - # # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany # Chair for VLSI-Design, Diagnostics and Architecture -# +# # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at -# +# # http://www.apache.org/licenses/LICENSE-2.0 -# +# # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -59,16 +59,12 @@ class Simulator(BaseSimulator): class __Directories__(BaseSimulator.__Directories__): GTKWBinary = None - def __init__(self, host, guiMode): - super().__init__(host) - - self._guiMode = guiMode + def __init__(self, host, dryRun, guiMode): + super().__init__(host, dryRun) - self._entity = None - self._testbenchFQN = None + self._guiMode = guiMode self._vhdlGenerics = None - - self._toolChain = None + self._toolChain = None ghdlFilesDirectoryName = host.PoCConfig['CONFIG.DirectoryNames']['GHDLFiles'] self.Directories.Working = host.Directories.Temp / ghdlFilesDirectoryName @@ -87,46 +83,34 @@ def __init__(self, host, guiMode): def _PrepareSimulator(self): # create the GHDL executable factory - self._LogVerbose("Preparing GHDL simulator.") - ghdlSection = self.Host.PoCConfig['INSTALL.GHDL'] - binaryPath = Path(ghdlSection['BinaryDirectory']) - version = ghdlSection['Version'] - backend = ghdlSection['Backend'] - self._toolChain = GHDL(self.Host.Platform, binaryPath, version, backend, logger=self.Logger) + self.LogVerbose("Preparing GHDL simulator.") + ghdlSection = self.Host.PoCConfig['INSTALL.GHDL'] + binaryPath = Path(ghdlSection['BinaryDirectory']) + version = ghdlSection['Version'] + backend = ghdlSection['Backend'] + self._toolChain = GHDL(self.Host.Platform, self.DryRun, binaryPath, version, backend, logger=self.Logger) def _RunAnalysis(self, testbench): # create a GHDLAnalyzer instance ghdl = self._toolChain.GetGHDLAnalyze() - ghdl.Parameters[ghdl.FlagVerbose] = (self.Logger.LogLevel is Severity.Debug) + ghdl.Parameters[ghdl.FlagVerbose] = (self.Logger.LogLevel is Severity.Debug) ghdl.Parameters[ghdl.FlagExplicit] = True ghdl.Parameters[ghdl.FlagRelaxedRules] = True - ghdl.Parameters[ghdl.FlagWarnBinding] = True - ghdl.Parameters[ghdl.FlagNoVitalChecks] = True - ghdl.Parameters[ghdl.FlagMultiByteComments] = True + ghdl.Parameters[ghdl.FlagWarnBinding] = True + ghdl.Parameters[ghdl.FlagNoVitalChecks] = True + ghdl.Parameters[ghdl.FlagMultiByteComments] = True ghdl.Parameters[ghdl.FlagSynBinding] = True - ghdl.Parameters[ghdl.FlagPSL] = True - - if (self._vhdlVersion == VHDLVersion.VHDL87): - ghdl.Parameters[ghdl.SwitchVHDLVersion] = "87" - ghdl.Parameters[ghdl.SwitchIEEEFlavor] = "synopsys" - elif (self._vhdlVersion == VHDLVersion.VHDL93): - ghdl.Parameters[ghdl.SwitchVHDLVersion] = "93c" - ghdl.Parameters[ghdl.SwitchIEEEFlavor] = "synopsys" - elif (self._vhdlVersion == VHDLVersion.VHDL02): - ghdl.Parameters[ghdl.SwitchVHDLVersion] = "02" - elif (self._vhdlVersion == VHDLVersion.VHDL08): - ghdl.Parameters[ghdl.SwitchVHDLVersion] = "08" - else: raise SimulatorException("VHDL version is not supported.") + ghdl.Parameters[ghdl.FlagPSL] = True + + self._SetVHDLVersionAndIEEEFlavor(ghdl) + self._SetExternalLibraryReferences(ghdl) - # add external library references - ghdl.Parameters[ghdl.ArgListLibraryReferences] = [str(extLibrary.Path) for extLibrary in self._pocProject.ExternalVHDLLibraries] - # run GHDL analysis for each VHDL file for file in self._pocProject.Files(fileType=FileTypes.VHDLSourceFile): if (not file.Path.exists()): raise SkipableSimulatorException("Cannot analyse '{0!s}'.".format(file.Path)) from FileNotFoundError(str(file.Path)) - ghdl.Parameters[ghdl.SwitchVHDLLibrary] = file.LibraryName - ghdl.Parameters[ghdl.ArgSourceFile] = file.Path + ghdl.Parameters[ghdl.SwitchVHDLLibrary] = file.LibraryName + ghdl.Parameters[ghdl.ArgSourceFile] = file.Path try: ghdl.Analyze() except GHDLReanalyzeException as ex: @@ -136,6 +120,23 @@ def _RunAnalysis(self, testbench): if ghdl.HasErrors: raise SkipableSimulatorException("Error while analysing '{0!s}'.".format(file.Path)) + def _SetVHDLVersionAndIEEEFlavor(self, ghdl): + ghdl.Parameters[ghdl.SwitchIEEEFlavor] = "synopsys" + + if (self._vhdlVersion is VHDLVersion.VHDL93): + ghdl.Parameters[ghdl.SwitchVHDLVersion] = "93c" + else: + ghdl.Parameters[ghdl.SwitchVHDLVersion] = repr(self._vhdlVersion)[-2:] + + def _SetExternalLibraryReferences(self, ghdl): + # add external library references + externalLibraryReferences = [] + for extLibrary in self._pocProject.ExternalVHDLLibraries: + path = str(extLibrary.Path) + if (path not in externalLibraryReferences): + externalLibraryReferences.append(path) + ghdl.Parameters[ghdl.ArgListLibraryReferences] = externalLibraryReferences + # running elaboration # ========================================================================== def _RunElaboration(self, testbench): @@ -144,26 +145,14 @@ def _RunElaboration(self, testbench): # create a GHDLElaborate instance ghdl = self._toolChain.GetGHDLElaborate() - ghdl.Parameters[ghdl.FlagVerbose] = (self.Logger.LogLevel is Severity.Debug) - ghdl.Parameters[ghdl.SwitchVHDLLibrary] = VHDL_TESTBENCH_LIBRARY_NAME - ghdl.Parameters[ghdl.ArgTopLevel] = testbench.ModuleName + ghdl.Parameters[ghdl.FlagVerbose] = (self.Logger.LogLevel is Severity.Debug) + ghdl.Parameters[ghdl.SwitchVHDLLibrary] = VHDL_TESTBENCH_LIBRARY_NAME + ghdl.Parameters[ghdl.ArgTopLevel] = testbench.ModuleName ghdl.Parameters[ghdl.FlagExplicit] = True - # add external library references - ghdl.Parameters[ghdl.ArgListLibraryReferences] = [str(extLibrary.Path) for extLibrary in self._pocProject.ExternalVHDLLibraries] - - if (self._vhdlVersion == VHDLVersion.VHDL87): - ghdl.Parameters[ghdl.SwitchVHDLVersion] = "87" - ghdl.Parameters[ghdl.SwitchIEEEFlavor] = "synopsys" - elif (self._vhdlVersion == VHDLVersion.VHDL93): - ghdl.Parameters[ghdl.SwitchVHDLVersion] = "93c" - ghdl.Parameters[ghdl.SwitchIEEEFlavor] = "synopsys" - elif (self._vhdlVersion == VHDLVersion.VHDL02): - ghdl.Parameters[ghdl.SwitchVHDLVersion] = "02" - elif (self._vhdlVersion == VHDLVersion.VHDL08): - ghdl.Parameters[ghdl.SwitchVHDLVersion] = "08" - else: raise SimulatorException("VHDL version is not supported.") - + self._SetVHDLVersionAndIEEEFlavor(ghdl) + self._SetExternalLibraryReferences(ghdl) + try: ghdl.Elaborate() except GHDLException as ex: @@ -185,84 +174,70 @@ def _RunSimulation(self, testbench): ghdl.Parameters[ghdl.SwitchVHDLLibrary] = VHDL_TESTBENCH_LIBRARY_NAME ghdl.Parameters[ghdl.ArgTopLevel] = testbench.ModuleName - if (self._vhdlVersion == VHDLVersion.VHDL87): - ghdl.Parameters[ghdl.SwitchVHDLVersion] = "87" - ghdl.Parameters[ghdl.SwitchIEEEFlavor] = "synopsys" - elif (self._vhdlVersion == VHDLVersion.VHDL93): - ghdl.Parameters[ghdl.SwitchVHDLVersion] = "93c" - ghdl.Parameters[ghdl.SwitchIEEEFlavor] = "synopsys" - elif (self._vhdlVersion == VHDLVersion.VHDL02): - ghdl.Parameters[ghdl.SwitchVHDLVersion] = "02" - elif (self._vhdlVersion == VHDLVersion.VHDL08): - ghdl.Parameters[ghdl.SwitchVHDLVersion] = "08" - else: raise SimulatorException("VHDL version is not supported.") - - # add external library references - ghdl.Parameters[ghdl.ArgListLibraryReferences] = [str(extLibrary.Path) for extLibrary in self._pocProject.ExternalVHDLLibraries] + self._SetVHDLVersionAndIEEEFlavor(ghdl) + self._SetExternalLibraryReferences(ghdl) # configure RUNOPTS ghdl.RunOptions[ghdl.SwitchIEEEAsserts] = "disable-at-0" # enable, disable, disable-at-0 # set dump format to save simulation results to *.vcd file if (self._guiMode): - waveformFileFormat = self.Host.PoCConfig[testbench.ConfigSectionName]['ghdlWaveformFileFormat'] - if (waveformFileFormat == "vcd"): + configSection = self.Host.PoCConfig[testbench.ConfigSectionName] + testbench.WaveformOptionFile = Path(configSection['ghdlWaveformOptionFile']) + testbench.WaveformFileFormat = configSection['ghdlWaveformFileFormat'] + + if (testbench.WaveformFileFormat == "vcd"): waveformFilePath = self.Directories.Working / (testbench.ModuleName + ".vcd") - ghdl.RunOptions[ghdl.SwitchVCDWaveform] = waveformFilePath - elif (waveformFileFormat == "vcdgz"): + ghdl.RunOptions[ghdl.SwitchVCDWaveform] = waveformFilePath + elif (testbench.WaveformFileFormat == "vcdgz"): waveformFilePath = self.Directories.Working / (testbench.ModuleName + ".vcd.gz") - ghdl.RunOptions[ghdl.SwitchVCDGZWaveform] = waveformFilePath - elif (waveformFileFormat == "fst"): + ghdl.RunOptions[ghdl.SwitchVCDGZWaveform] = waveformFilePath + elif (testbench.WaveformFileFormat == "fst"): waveformFilePath = self.Directories.Working / (testbench.ModuleName + ".fst") - ghdl.RunOptions[ghdl.SwitchFSTWaveform] = waveformFilePath - elif (waveformFileFormat == "ghw"): + ghdl.RunOptions[ghdl.SwitchFSTWaveform] = waveformFilePath + elif (testbench.WaveformFileFormat == "ghw"): waveformFilePath = self.Directories.Working / (testbench.ModuleName + ".ghw") - ghdl.RunOptions[ghdl.SwitchGHDLWaveform] = waveformFilePath - else: raise SimulatorException("Unknown waveform file format for GHDL.") - + ghdl.RunOptions[ghdl.SwitchGHDLWaveform] = waveformFilePath + else: raise SimulatorException("Unknown waveform file format for GHDL.") + + testbench.WaveformFile = waveformFilePath + if testbench.WaveformOptionFile.exists(): + ghdl.RunOptions[ghdl.SwitchWaveformSelect] = testbench.WaveformOptionFile + testbench.Result = ghdl.Run() def _RunView(self, testbench): - # FIXME: get waveform database filename from testbench object - waveformFileFormat = self.Host.PoCConfig[testbench.ConfigSectionName]['ghdlWaveformFileFormat'] - if (waveformFileFormat == "vcd"): - waveformFilePath = self.Directories.Working / (testbench.ModuleName + ".vcd") - elif (waveformFileFormat == "vcdgz"): - waveformFilePath = self.Directories.Working / (testbench.ModuleName + ".vcd.gz") - elif (waveformFileFormat == "fst"): - waveformFilePath = self.Directories.Working / (testbench.ModuleName + ".fst") - elif (waveformFileFormat == "ghw"): - waveformFilePath = self.Directories.Working / (testbench.ModuleName + ".ghw") - else: raise SimulatorException("Unknown waveform file format for GHDL.") - - if (not waveformFilePath.exists()): - raise SkipableSimulatorException("Waveform file '{0!s}' not found.".format(waveformFilePath)) \ - from FileNotFoundError(str(waveformFilePath)) - + if (not testbench.WaveformFile.exists()): + raise SkipableSimulatorException("Waveform file '{0!s}' not found.".format(testbench.WaveformFile)) \ + from FileNotFoundError(str(testbench.WaveformFile)) + gtkwBinaryPath = self.Directories.GTKWBinary gtkwVersion = self.Host.PoCConfig['INSTALL.GTKWave']['Version'] - gtkw = GTKWave(self.Host.Platform, gtkwBinaryPath, gtkwVersion) - gtkw.Parameters[gtkw.SwitchDumpFile] = str(waveformFilePath) + gtkw = GTKWave(self.Host.Platform, self.DryRun, gtkwBinaryPath, gtkwVersion, logger=self.Logger) + gtkw.Parameters[gtkw.SwitchDumpFile] = str(testbench.WaveformFile) # if GTKWave savefile exists, load it's settings - gtkwSaveFilePath = self.Host.Directories.Root / self.Host.PoCConfig[testbench.ConfigSectionName]['gtkwSaveFile'] + configSection = self.Host.PoCConfig[testbench.ConfigSectionName] + gtkwSaveFilePath = self.Host.Directories.Root / configSection['gtkwSaveFile'] if gtkwSaveFilePath.exists(): - self._LogDebug("Found waveform save file: '{0!s}'".format(gtkwSaveFilePath)) + self.LogDebug("Found waveform save file: '{0!s}'".format(gtkwSaveFilePath)) gtkw.Parameters[gtkw.SwitchSaveFile] = str(gtkwSaveFilePath) else: - self._LogDebug("Didn't find waveform save file: '{0!s}'".format(gtkwSaveFilePath)) - + self.LogDebug("Didn't find waveform save file: '{0!s}'".format(gtkwSaveFilePath)) + # run GTKWave GUI gtkw.View() - + # clean-up *.gtkw files if gtkwSaveFilePath.exists(): - self._LogNormal(" Cleaning up GTKWave save file...") - removeKeys = ("[dumpfile]", "[savefile]") - buffer = "" + self.LogVerbose("Cleaning up GTKWave save file...") + removeKeys = ("[dumpfile]", "[savefile]") + buffer = "" with gtkwSaveFilePath.open('r') as gtkwHandle: + # search for these keys in the first 10 header lines for lineNumber,line in enumerate(gtkwHandle): - if (not line.startswith(removeKeys)): buffer += line - if (lineNumber > 10): break + if (not line.startswith(removeKeys)): buffer += line + if (lineNumber > 10): break + # copy remaining lines without processing for line in gtkwHandle: buffer += line with gtkwSaveFilePath.open('w') as gtkwHandle: diff --git a/py/Simulator/ISESimulator.py b/py/Simulator/ISESimulator.py index 68f8d46d..b23cb037 100644 --- a/py/Simulator/ISESimulator.py +++ b/py/Simulator/ISESimulator.py @@ -1,30 +1,30 @@ # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2; replace-tabs off; indent-width 2; -# +# # ============================================================================== # Authors: Patrick Lehmann # Martin Zabel -# +# # Python Class: TODO -# +# # Description: # ------------------------------------ # TODO: -# - -# - +# - +# - # # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany # Chair for VLSI-Design, Diagnostics and Architecture -# +# # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at -# +# # http://www.apache.org/licenses/LICENSE-2.0 -# +# # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -54,47 +54,43 @@ class Simulator(BaseSimulator, XilinxProjectExportMixIn): _TOOL_CHAIN = ToolChain.Xilinx_ISE _TOOL = Tool.Xilinx_iSim - def __init__(self, host, guiMode): - super().__init__(host) + def __init__(self, host, dryRun, guiMode): + super().__init__(host, dryRun) XilinxProjectExportMixIn.__init__(self) - self._guiMode = guiMode - - self._entity = None - self._testbenchFQN = None + self._guiMode = guiMode self._vhdlGenerics = None + self._toolChain = None - self._ise = None - - iseFilesDirectoryName = host.PoCConfig['CONFIG.DirectoryNames']['ISESimulatorFiles'] - self.Directories.Working = host.Directories.Temp / iseFilesDirectoryName - self.Directories.PreCompiled = host.Directories.PreCompiled / iseFilesDirectoryName + iseFilesDirectoryName = host.PoCConfig['CONFIG.DirectoryNames']['ISESimulatorFiles'] + self.Directories.Working = host.Directories.Temp / iseFilesDirectoryName + self.Directories.PreCompiled = host.Directories.PreCompiled / iseFilesDirectoryName self._PrepareSimulationEnvironment() self._PrepareSimulator() def _PrepareSimulator(self): # create the Xilinx ISE executable factory - self._LogVerbose("Preparing ISE simulator.") - iseSection = self.Host.PoCConfig['INSTALL.Xilinx.ISE'] - version = iseSection['Version'] - binaryPath = Path(iseSection['BinaryDirectory']) - self._ise = ISE(self.Host.Platform, binaryPath, version, logger=self.Logger) + self.LogVerbose("Preparing ISE simulator.") + iseSection = self.Host.PoCConfig['INSTALL.Xilinx.ISE'] + version = iseSection['Version'] + binaryPath = Path(iseSection['BinaryDirectory']) + self._toolChain = ISE(self.Host.Platform, self.DryRun, binaryPath, version, logger=self.Logger) def _RunElaboration(self, testbench): - exeFilePath = self.Directories.Working / (testbench.ModuleName + ".exe") + exeFilePath = self.Directories.Working / (testbench.ModuleName + ".exe") prjFilePath = self.Directories.Working / (testbench.ModuleName + ".prj") self._WriteXilinxProjectFile(prjFilePath, "iSim") # create a ISELinker instance - fuse = self._ise.GetFuse() - fuse.Parameters[fuse.FlagIncremental] = True + fuse = self._toolChain.GetFuse() + fuse.Parameters[fuse.FlagIncremental] = True fuse.Parameters[fuse.SwitchTimeResolution] = "1fs" fuse.Parameters[fuse.SwitchMultiThreading] = "4" fuse.Parameters[fuse.FlagRangeCheck] = True - fuse.Parameters[fuse.SwitchProjectFile] = str(prjFilePath) + fuse.Parameters[fuse.SwitchProjectFile] = str(prjFilePath) fuse.Parameters[fuse.SwitchOutputFile] = str(exeFilePath) - fuse.Parameters[fuse.ArgTopLevel] = "{0}.{1}".format(VHDL_TESTBENCH_LIBRARY_NAME, testbench.ModuleName) + fuse.Parameters[fuse.ArgTopLevel] = "{0}.{1}".format(VHDL_TESTBENCH_LIBRARY_NAME, testbench.ModuleName) try: fuse.Link() @@ -104,27 +100,27 @@ def _RunElaboration(self, testbench): raise SkipableSimulatorException("Error while analysing '{0!s}'.".format(prjFilePath)) def _RunSimulation(self, testbench): - iSimLogFilePath = self.Directories.Working / (testbench.ModuleName + ".iSim.log") - exeFilePath = self.Directories.Working / (testbench.ModuleName + ".exe") + iSimLogFilePath = self.Directories.Working / (testbench.ModuleName + ".iSim.log") + exeFilePath = self.Directories.Working / (testbench.ModuleName + ".exe") tclBatchFilePath = self.Host.Directories.Root / self.Host.PoCConfig[testbench.ConfigSectionName]['iSimBatchScript'] tclGUIFilePath = self.Host.Directories.Root / self.Host.PoCConfig[testbench.ConfigSectionName]['iSimGUIScript'] wcfgFilePath = self.Host.Directories.Root / self.Host.PoCConfig[testbench.ConfigSectionName]['iSimWaveformConfigFile'] # create a ISESimulator instance - iSim = ISESimulator(exeFilePath, logger=self.Logger) - iSim.Parameters[iSim.SwitchLogFile] = str(iSimLogFilePath) + iSim = ISESimulator(self._host.Platform, self._host.DryRun, exeFilePath, logger=self.Logger) + iSim.Parameters[iSim.SwitchLogFile] = str(iSimLogFilePath) if (not self._guiMode): iSim.Parameters[iSim.SwitchTclBatchFile] = str(tclBatchFilePath) else: iSim.Parameters[iSim.SwitchTclBatchFile] = str(tclGUIFilePath) - iSim.Parameters[iSim.FlagGuiMode] = True + iSim.Parameters[iSim.FlagGuiMode] = True # if iSim save file exists, load it's settings if wcfgFilePath.exists(): - self._LogDebug("Found waveform config file: '{0!s}'".format(wcfgFilePath)) + self.LogDebug("Found waveform config file: '{0!s}'".format(wcfgFilePath)) iSim.Parameters[iSim.SwitchWaveformFile] = str(wcfgFilePath) else: - self._LogDebug("Didn't find waveform config file: '{0!s}'".format(wcfgFilePath)) + self.LogDebug("Didn't find waveform config file: '{0!s}'".format(wcfgFilePath)) testbench.Result = iSim.Simulate() diff --git a/py/Simulator/QuestaSimulator.py b/py/Simulator/QuestaSimulator.py index e153fa2e..177490fa 100644 --- a/py/Simulator/QuestaSimulator.py +++ b/py/Simulator/QuestaSimulator.py @@ -1,13 +1,13 @@ # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2; replace-tabs off; indent-width 2; -# +# # ============================================================================== # Authors: Patrick Lehmann # Martin Zabel -# +# # Python Class: TODO -# +# # Description: # ------------------------------------ # TODO: @@ -16,13 +16,13 @@ # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany # Chair for VLSI-Design, Diagnostics and Architecture -# +# # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at -# +# # http://www.apache.org/licenses/LICENSE-2.0 -# +# # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -43,29 +43,25 @@ from pathlib import Path from Base.Exceptions import NotConfiguredException -from Base.Project import FileTypes, VHDLVersion, ToolChain, Tool +from Base.Project import FileTypes, ToolChain, Tool from Base.Simulator import SimulatorException, Simulator as BaseSimulator, VHDL_TESTBENCH_LIBRARY_NAME, SkipableSimulatorException from PoC.Config import Vendors -from ToolChains.Mentor.QuestaSim import QuestaSim, QuestaException +from ToolChains.Mentor.QuestaSim import QuestaSim, QuestaSimException class Simulator(BaseSimulator): _TOOL_CHAIN = ToolChain.Mentor_QuestaSim _TOOL = Tool.Mentor_vSim - def __init__(self, host, guiMode): - super().__init__(host) - - self._guiMode = guiMode + def __init__(self, host, dryRun, guiMode): + super().__init__(host, dryRun) - self._entity = None - self._testbenchFQN = None - self._vhdlVersion = None + self._guiMode = guiMode + self._vhdlVersion = None self._vhdlGenerics = None + self._toolChain = None - self._questa = None - - vSimSimulatorFiles = host.PoCConfig['CONFIG.DirectoryNames']['QuestaSimFiles'] + vSimSimulatorFiles = host.PoCConfig['CONFIG.DirectoryNames']['QuestaSimFiles'] self.Directories.Working = host.Directories.Temp / vSimSimulatorFiles self.Directories.PreCompiled = host.Directories.PreCompiled / vSimSimulatorFiles @@ -74,7 +70,7 @@ def __init__(self, host, guiMode): def _PrepareSimulator(self): # create the QuestaSim executable factory - self._LogVerbose("Preparing Mentor simulator.") + self.LogVerbose("Preparing Mentor simulator.") for sectionName in ['INSTALL.Mentor.QuestaSim', 'INSTALL.Altera.ModelSim']: if (len(self.Host.PoCConfig.options(sectionName)) != 0): break @@ -85,7 +81,7 @@ def _PrepareSimulator(self): questaSection = self.Host.PoCConfig[sectionName] binaryPath = Path(questaSection['BinaryDirectory']) version = questaSection['Version'] - self._questa = QuestaSim(self.Host.Platform, binaryPath, version, logger=self.Logger) + self._toolChain = QuestaSim(self.Host.Platform, self.DryRun, binaryPath, version, logger=self.Logger) def Run(self, testbench, board, vhdlVersion, vhdlGenerics=None, guiMode=False): # TODO: refactor into a ModelSim module, shared by QuestaSim and Cocotb (-> MixIn class)? @@ -93,6 +89,8 @@ def Run(self, testbench, board, vhdlVersion, vhdlGenerics=None, guiMode=False): self._modelsimIniPath = self.Directories.PreCompiled if board.Device.Vendor is Vendors.Altera: self._modelsimIniPath /= self.Host.PoCConfig['CONFIG.DirectoryNames']['AlteraSpecificFiles'] + elif board.Device.Vendor is Vendors.Lattice: + self._modelsimIniPath /= self.Host.PoCConfig['CONFIG.DirectoryNames']['LatticeSpecificFiles'] elif board.Device.Vendor is Vendors.Xilinx: self._modelsimIniPath /= self.Host.PoCConfig['CONFIG.DirectoryNames']['XilinxSpecificFiles'] @@ -105,52 +103,50 @@ def Run(self, testbench, board, vhdlVersion, vhdlGenerics=None, guiMode=False): def _RunAnalysis(self, _): # create a QuestaVHDLCompiler instance - vlib = self._questa.GetVHDLLibraryTool() + vlib = self._toolChain.GetVHDLLibraryTool() for lib in self._pocProject.VHDLLibraries: vlib.Parameters[vlib.SwitchLibraryName] = lib.Name vlib.CreateLibrary() # create a QuestaVHDLCompiler instance - vcom = self._questa.GetVHDLCompiler() - vcom.Parameters[vcom.FlagQuietMode] = True + vcom = self._toolChain.GetVHDLCompiler() + vcom.Parameters[vcom.FlagQuietMode] = True vcom.Parameters[vcom.FlagExplicit] = True vcom.Parameters[vcom.FlagRangeCheck] = True vcom.Parameters[vcom.SwitchModelSimIniFile] = self._modelsimIniPath.as_posix() - - if (self._vhdlVersion == VHDLVersion.VHDL87): vcom.Parameters[vcom.SwitchVHDLVersion] = "87" - elif (self._vhdlVersion == VHDLVersion.VHDL93): vcom.Parameters[vcom.SwitchVHDLVersion] = "93" - elif (self._vhdlVersion == VHDLVersion.VHDL02): vcom.Parameters[vcom.SwitchVHDLVersion] = "2002" - elif (self._vhdlVersion == VHDLVersion.VHDL08): vcom.Parameters[vcom.SwitchVHDLVersion] = "2008" - else: raise SimulatorException("VHDL version is not supported.") + vcom.Parameters[vcom.SwitchVHDLVersion] = repr(self._vhdlVersion) # run vcom compile for each VHDL file for file in self._pocProject.Files(fileType=FileTypes.VHDLSourceFile): - if (not file.Path.exists()): raise SimulatorException("Cannot analyse '{0!s}'.".format(file.Path)) from FileNotFoundError(str(file.Path)) + if (not file.Path.exists()): raise SimulatorException("Cannot analyse '{0!s}'.".format(file.Path)) from FileNotFoundError(str(file.Path)) vcomLogFile = self.Directories.Working / (file.Path.stem + ".vcom.log") - vcom.Parameters[vcom.SwitchVHDLLibrary] = file.LibraryName + vcom.Parameters[vcom.SwitchVHDLLibrary] = file.LibraryName vcom.Parameters[vcom.ArgLogFile] = vcomLogFile - vcom.Parameters[vcom.ArgSourceFile] = file.Path + vcom.Parameters[vcom.ArgSourceFile] = file.Path try: vcom.Compile() - except QuestaException as ex: + except QuestaSimException as ex: raise SimulatorException("Error while compiling '{0!s}'.".format(file.Path)) from ex if vcom.HasErrors: raise SkipableSimulatorException("Error while compiling '{0!s}'.".format(file.Path)) # delete empty log files if (vcomLogFile.stat().st_size == 0): - vcomLogFile.unlink() + try: + vcomLogFile.unlink() + except OSError as ex: + raise SimulatorException("Error while deleting '{0!s}'.".format(vcomLogFile)) from ex def _RunSimulation(self, testbench): if self._guiMode: return self._RunSimulationWithGUI(testbench) tclBatchFilePath = self.Host.Directories.Root / self.Host.PoCConfig[testbench.ConfigSectionName]['vSimBatchScript'] - + # create a QuestaSimulator instance - vsim = self._questa.GetSimulator() + vsim = self._toolChain.GetSimulator() vsim.Parameters[vsim.SwitchModelSimIniFile] = self._modelsimIniPath.as_posix() # vsim.Parameters[vsim.FlagOptimization] = True # FIXME: vsim.Parameters[vsim.FlagReportAsError] = "3473" @@ -165,7 +161,7 @@ def _RunSimulationWithGUI(self, testbench): tclWaveFilePath = self.Host.Directories.Root / self.Host.PoCConfig[testbench.ConfigSectionName]['vSimWaveScript'] # create a QuestaSimulator instance - vsim = self._questa.GetSimulator() + vsim = self._toolChain.GetSimulator() vsim.Parameters[vsim.SwitchModelSimIniFile] = self._modelsimIniPath.as_posix() # vsim.Parameters[vsim.FlagOptimization] = True # FIXME: vsim.Parameters[vsim.FlagReportAsError] = "3473" @@ -175,10 +171,10 @@ def _RunSimulationWithGUI(self, testbench): # vsim.Parameters[vsim.SwitchTitle] = testbenchName if (tclWaveFilePath.exists()): - self._LogDebug("Found waveform script: '{0!s}'".format(tclWaveFilePath)) + self.LogDebug("Found waveform script: '{0!s}'".format(tclWaveFilePath)) vsim.Parameters[vsim.SwitchBatchCommand] = "do {0}; do {1}".format(tclWaveFilePath.as_posix(), tclGUIFilePath.as_posix()) else: - self._LogDebug("Didn't find waveform script: '{0!s}'. Loading default commands.".format(tclWaveFilePath)) + self.LogDebug("Didn't find waveform script: '{0!s}'. Loading default commands.".format(tclWaveFilePath)) vsim.Parameters[vsim.SwitchBatchCommand] = "add wave *; do {0}".format(tclGUIFilePath.as_posix()) testbench.Result = vsim.Simulate() diff --git a/py/Simulator/VivadoSimulator.py b/py/Simulator/VivadoSimulator.py index b780985f..e7f3bb7e 100644 --- a/py/Simulator/VivadoSimulator.py +++ b/py/Simulator/VivadoSimulator.py @@ -1,30 +1,30 @@ # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2; replace-tabs off; indent-width 2; -# +# # ============================================================================== # Authors: Patrick Lehmann # Martin Zabel -# +# # Python Class: TODO -# +# # Description: # ------------------------------------ # TODO: -# - -# - +# - +# - # # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany # Chair for VLSI-Design, Diagnostics and Architecture -# +# # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at -# +# # http://www.apache.org/licenses/LICENSE-2.0 -# +# # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -55,33 +55,29 @@ class Simulator(BaseSimulator, XilinxProjectExportMixIn): _TOOL_CHAIN = ToolChain.Xilinx_Vivado _TOOL = Tool.Xilinx_xSim - def __init__(self, host, guiMode): - super().__init__(host) + def __init__(self, host, dryRun, guiMode): + super().__init__(host, dryRun) XilinxProjectExportMixIn.__init__(self) - self._guiMode = guiMode - - self._entity = None - self._testbenchFQN = None - self._vhdlVersion = None + self._guiMode = guiMode + self._vhdlVersion = None self._vhdlGenerics = None + self._toolChain = None - self._vivado = None - - vivadoFilesDirectoryName = host.PoCConfig['CONFIG.DirectoryNames']['VivadoSimulatorFiles'] - self.Directories.Working = host.Directories.Temp / vivadoFilesDirectoryName - self.Directories.PreCompiled = host.Directories.PreCompiled / vivadoFilesDirectoryName + vivadoFilesDirectoryName = host.PoCConfig['CONFIG.DirectoryNames']['VivadoSimulatorFiles'] + self.Directories.Working = host.Directories.Temp / vivadoFilesDirectoryName + self.Directories.PreCompiled = host.Directories.PreCompiled / vivadoFilesDirectoryName self._PrepareSimulationEnvironment() self._PrepareSimulator() def _PrepareSimulator(self): # create the Vivado executable factory - self._LogVerbose("Preparing Vivado simulator.") + self.LogVerbose("Preparing Vivado simulator.") vivadoSection = self.Host.PoCConfig['INSTALL.Xilinx.Vivado'] version = vivadoSection['Version'] binaryPath = Path(vivadoSection['BinaryDirectory']) - self._vivado = Vivado(self.Host.Platform, binaryPath, version, logger=self.Logger) + self._toolChain = Vivado(self.Host.Platform, self.DryRun, binaryPath, version, logger=self.Logger) def _RunElaboration(self, testbench): xelabLogFilePath = self.Directories.Working / (testbench.ModuleName + ".xelab.log") @@ -89,7 +85,7 @@ def _RunElaboration(self, testbench): self._WriteXilinxProjectFile(prjFilePath, "xSim", self._vhdlVersion) # create a VivadoLinker instance - xelab = self._vivado.GetElaborator() + xelab = self._toolChain.GetElaborator() xelab.Parameters[xelab.SwitchTimeResolution] = "1fs" # set minimum time precision to 1 fs xelab.Parameters[xelab.SwitchMultiThreading] = "off" if self.Logger.LogLevel is Severity.Debug else "auto" # disable multithreading support in debug mode xelab.Parameters[xelab.FlagRangeCheck] = True @@ -117,7 +113,7 @@ def _RunSimulation(self, testbench): wcfgFilePath = self.Host.Directories.Root / self.Host.PoCConfig[testbench.ConfigSectionName]['xSimWaveformConfigFile'] # create a VivadoSimulator instance - xSim = self._vivado.GetSimulator() + xSim = self._toolChain.GetSimulator() xSim.Parameters[xSim.SwitchLogFile] = str(xSimLogFilePath) if (not self._guiMode): @@ -128,10 +124,10 @@ def _RunSimulation(self, testbench): # if xSim save file exists, load it's settings if wcfgFilePath.exists(): - self._LogDebug("Found waveform config file: '{0!s}'".format(wcfgFilePath)) + self.LogDebug("Found waveform config file: '{0!s}'".format(wcfgFilePath)) xSim.Parameters[xSim.SwitchWaveformFile] = str(wcfgFilePath) else: - self._LogDebug("Didn't find waveform config file: '{0!s}'".format(wcfgFilePath)) + self.LogDebug("Didn't find waveform config file: '{0!s}'".format(wcfgFilePath)) xSim.Parameters[xSim.SwitchSnapshot] = testbench.ModuleName testbench.Result = xSim.Simulate() diff --git a/py/Simulator/__init__.py b/py/Simulator/__init__.py index 6053946c..1b1d35e3 100644 --- a/py/Simulator/__init__.py +++ b/py/Simulator/__init__.py @@ -1,28 +1,28 @@ # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2; replace-tabs off; indent-width 2; -# +# # ============================================================================== # Authors: Patrick Lehmann -# +# # Python Sub Module: TODO: -# +# # Description: # ------------------------------------ # TODO: -# +# # # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany # Chair for VLSI-Design, Diagnostics and Architecture -# +# # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at -# +# # http://www.apache.org/licenses/LICENSE-2.0 -# +# # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. diff --git a/py/ToolChains/Aldec/ActiveHDL.py b/py/ToolChains/Aldec/ActiveHDL.py index 9f7da7d4..e0091afe 100644 --- a/py/ToolChains/Aldec/ActiveHDL.py +++ b/py/ToolChains/Aldec/ActiveHDL.py @@ -46,13 +46,13 @@ from lib.Functions import CallByRefParam from Base.Exceptions import PlatformNotSupportedException -from Base.Logging import LogEntry, Severity -from Base.Simulator import SimulationResult, PoCSimulationResultFilter +from Base.Logging import LogEntry, Severity +from Base.Simulator import SimulationResult, PoCSimulationResultFilter from Base.Executable import Executable from Base.Executable import ExecutableArgument, PathArgument, StringArgument from Base.Executable import LongFlagArgument, ShortValuedFlagArgument, ShortTupleArgument, CommandLineArgumentList -from Base.Configuration import Configuration as BaseConfiguration, ConfigurationException -from ToolChains.Aldec.Aldec import AldecException +from Base.Configuration import Configuration as BaseConfiguration, ConfigurationException +from ToolChains.Aldec.Aldec import AldecException class ActiveHDLException(AldecException): @@ -111,34 +111,37 @@ def __CheckActiveHDLVersion(self, binPath, version): if str(version) not in output: raise ConfigurationException("Active-HDL version mismatch. Expected version {0}.".format(version)) + class ActiveHDLMixIn: - def __init__(self, platform, binaryDirectoryPath, version, logger=None): + def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): self._platform = platform - self._binaryDirectoryPath = binaryDirectoryPath - self._version = version - self._logger = logger + self._dryrun = dryrun + self._binaryDirectoryPath = binaryDirectoryPath + self._version = version + self._Logger = logger + class ActiveHDL(ActiveHDLMixIn): - def __init__(self, platform, binaryDirectoryPath, version, logger=None): - ActiveHDLMixIn.__init__(self, platform, binaryDirectoryPath, version, logger) + def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): + ActiveHDLMixIn.__init__(self, platform, dryrun, binaryDirectoryPath, version, logger) def GetVHDLLibraryTool(self): - return ActiveHDLVHDLLibraryTool(self._platform, self._binaryDirectoryPath, self._version, logger=self._logger) + return ActiveHDLVHDLLibraryTool(self._platform, self._dryrun, self._binaryDirectoryPath, self._version, logger=self._Logger) def GetVHDLCompiler(self): - return VHDLCompiler(self._platform, self._binaryDirectoryPath, self._version, logger=self._logger) + return VHDLCompiler(self._platform, self._dryrun, self._binaryDirectoryPath, self._version, logger=self._Logger) def GetSimulator(self): - return StandaloneSimulator(self._platform, self._binaryDirectoryPath, self._version, logger=self._logger) + return StandaloneSimulator(self._platform, self._dryrun, self._binaryDirectoryPath, self._version, logger=self._Logger) class VHDLCompiler(Executable, ActiveHDLMixIn): - def __init__(self, platform, binaryDirectoryPath, version, logger=None): - ActiveHDLMixIn.__init__(self, platform, binaryDirectoryPath, version, logger=logger) + def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): + ActiveHDLMixIn.__init__(self, platform, dryrun, binaryDirectoryPath, version, logger=logger) if (self._platform == "Windows"): executablePath = binaryDirectoryPath / "vcom.exe" # elif (self._platform == "Linux"): executablePath = binaryDirectoryPath / "vcom" else: raise PlatformNotSupportedException(self._platform) - super().__init__(platform, executablePath, logger=logger) + super().__init__(platform, dryrun, executablePath, logger=logger) self._hasOutput = False self._hasWarnings = False @@ -191,7 +194,11 @@ class ArgSourceFile(metaclass=PathArgument): def Compile(self): parameterList = self.Parameters.ToArgumentList() - self._LogVerbose("command: {0}".format(" ".join(parameterList))) + self.LogVerbose("command: {0}".format(" ".join(parameterList))) + + if (self._dryrun): + self.LogDryRun("Start process: {0}".format(" ".join(parameterList))) + return try: self.StartProcess(parameterList) @@ -207,31 +214,31 @@ def Compile(self): self._hasOutput = True - self._LogNormal(" acom messages for '{0}'".format(self.Parameters[self.ArgSourceFile])) - self._LogNormal(" " + ("-" * 76)) + self.LogNormal(" acom messages for '{0}'".format(self.Parameters[self.ArgSourceFile])) + self.LogNormal(" " + ("-" * (78 - self.Logger.BaseIndent*2))) while True: self._hasWarnings |= (line.Severity is Severity.Warning) self._hasErrors |= (line.Severity is Severity.Error) - line.IndentBy(2) - self._Log(line) + line.IndentBy(self.Logger.BaseIndent + 1) + self.Log(line) line = next(iterator) except StopIteration: pass finally: if self._hasOutput: - self._LogNormal(" " + ("-" * 76)) + self.LogNormal(" " + ("-" * (78 - self.Logger.BaseIndent*2))) class StandaloneSimulator(Executable, ActiveHDLMixIn): - def __init__(self, platform, binaryDirectoryPath, version, logger=None): - ActiveHDLMixIn.__init__(self, platform, binaryDirectoryPath, version, logger=logger) + def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): + ActiveHDLMixIn.__init__(self, platform, dryrun, binaryDirectoryPath, version, logger=logger) if (self._platform == "Windows"): executablePath = binaryDirectoryPath / "vsimsa.exe" # elif (self._platform == "Linux"): executablePath = binaryDirectoryPath / "vsimsa" else: raise PlatformNotSupportedException(self._platform) - super().__init__(platform, executablePath, logger=logger) + super().__init__(platform, dryrun, executablePath, logger=logger) self._hasOutput = False self._hasWarnings = False @@ -261,8 +268,8 @@ class SwitchBatchCommand(metaclass=ShortTupleArgument): def Simulate(self): parameterList = self.Parameters.ToArgumentList() - self._LogVerbose("command: {0}".format(" ".join(parameterList))) - self._LogDebug("tcl commands: {0}".format(self.Parameters[self.SwitchBatchCommand])) + self.LogVerbose("command: {0}".format(" ".join(parameterList))) + self.LogDebug("tcl commands: {0}".format(self.Parameters[self.SwitchBatchCommand])) try: self.StartProcess(parameterList) @@ -278,33 +285,33 @@ def Simulate(self): line = next(iterator) self._hasOutput = True - self._LogNormal(" vsimsa messages for '{0}.{1}'".format("?????", "?????")) - self._LogNormal(" " + ("-" * 76)) + self.LogNormal(" vsimsa messages for '{0}.{1}'".format("?????", "?????")) + self.LogNormal(" " + ("-" * (78 - self.Logger.BaseIndent*2))) while True: self._hasWarnings |= (line.Severity is Severity.Warning) self._hasErrors |= (line.Severity is Severity.Error) - line.IndentBy(2) - self._Log(line) + line.IndentBy(self.Logger.BaseIndent + 1) + self.Log(line) line = next(iterator) except StopIteration: pass finally: if self._hasOutput: - self._LogNormal(" " + ("-" * 76)) + self.LogNormal(" " + ("-" * (78 - self.Logger.BaseIndent*2))) return simulationResult.value class Simulator(Executable, ActiveHDLMixIn): - def __init__(self, platform, binaryDirectoryPath, version, logger=None): - ActiveHDLMixIn.__init__(self, platform, binaryDirectoryPath, version, logger=logger) + def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): + ActiveHDLMixIn.__init__(self, platform, dryrun, binaryDirectoryPath, version, logger=logger) if (self._platform == "Windows"): executablePath = binaryDirectoryPath / "vsimsa.exe" # elif (self._platform == "Linux"): executablePath = binaryDirectoryPath / "vsimsa" else: raise PlatformNotSupportedException(self._platform) - super().__init__(platform, executablePath, logger=logger) + super().__init__(platform, dryrun, executablePath, logger=logger) self.Parameters[self.Executable] = executablePath @@ -349,8 +356,8 @@ class SwitchBatchCommand(metaclass=ShortTupleArgument): def Simulate(self): parameterList = self.Parameters.ToArgumentList() - self._LogVerbose("command: {0}".format(" ".join(parameterList))) - self._LogDebug("tcl commands: {0}".format(self.Parameters[self.SwitchBatchCommand])) + self.LogVerbose("command: {0}".format(" ".join(parameterList))) + self.LogDebug("tcl commands: {0}".format(self.Parameters[self.SwitchBatchCommand])) _indent = " " print(_indent + "vsimsa messages for '{0}.{1}'".format("??????", "??????")) # self.VHDLLibrary, topLevel)) @@ -365,12 +372,12 @@ def Simulate(self): class ActiveHDLVHDLLibraryTool(Executable, ActiveHDLMixIn): - def __init__(self, platform, binaryDirectoryPath, version, logger=None): - ActiveHDLMixIn.__init__(self, platform, binaryDirectoryPath, version, logger=logger) + def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): + ActiveHDLMixIn.__init__(self, platform, dryrun, binaryDirectoryPath, version, logger=logger) if (self._platform == "Windows"): executablePath = binaryDirectoryPath / "vlib.exe" # elif (self._platform == "Linux"): executablePath = binaryDirectoryPath / "vlib" else: raise PlatformNotSupportedException(self._platform) - super().__init__(platform, executablePath, logger=logger) + super().__init__(platform, dryrun, executablePath, logger=logger) self._hasOutput = False self._hasWarnings = False @@ -404,7 +411,7 @@ class SwitchLibraryName(metaclass=StringArgument): def CreateLibrary(self): parameterList = self.Parameters.ToArgumentList() - self._LogVerbose("command: {0}".format(" ".join(parameterList))) + self.LogVerbose("command: {0}".format(" ".join(parameterList))) try: self.StartProcess(parameterList) @@ -419,22 +426,22 @@ def CreateLibrary(self): line = next(iterator) self._hasOutput = True - self._LogNormal(" alib messages for '{0}'".format(self.Parameters[self.SwitchLibraryName])) - self._LogNormal(" " + ("-" * 76)) + self.LogNormal(" alib messages for '{0}'".format(self.Parameters[self.SwitchLibraryName])) + self.LogNormal(" " + ("-" * (78 - self.Logger.BaseIndent*2))) while True: self._hasWarnings |= (line.Severity is Severity.Warning) self._hasErrors |= (line.Severity is Severity.Error) - line.IndentBy(2) - self._Log(line) + line.IndentBy(self.Logger.BaseIndent + 1) + self.Log(line) line = next(iterator) except StopIteration: pass finally: if self._hasOutput: - self._LogNormal(" " + ("-" * 76)) + self.LogNormal(" " + ("-" * (78 - self.Logger.BaseIndent*2))) # # assemble acom command as list of parameters @@ -454,7 +461,7 @@ def CreateLibrary(self): # ] -def VHDLCompilerFilter(gen): +def VHDLCompilerFilter(gen): # mccabe:disable=MC0001 for line in gen: if line.startswith("Aldec, Inc. VHDL Compiler"): yield LogEntry(line, Severity.Debug) diff --git a/py/ToolChains/Aldec/Aldec.py b/py/ToolChains/Aldec/Aldec.py index 4f265f19..a3ef1822 100644 --- a/py/ToolChains/Aldec/Aldec.py +++ b/py/ToolChains/Aldec/Aldec.py @@ -69,4 +69,4 @@ class Configuration(BaseConfiguration): def _GetDefaultInstallationDirectory(self): path = self._TestDefaultInstallPath({"Windows": "Aldec", "Linux": "Aldec"}) if path is None: return super()._GetDefaultInstallationDirectory() - return str(path) + return path.as_posix() diff --git a/py/ToolChains/Altera/Altera.py b/py/ToolChains/Altera/Altera.py index 0416fe7b..ffcea33a 100644 --- a/py/ToolChains/Altera/Altera.py +++ b/py/ToolChains/Altera/Altera.py @@ -73,4 +73,4 @@ def _GetDefaultInstallationDirectory(self): path = self._TestDefaultInstallPath({"Windows": "Altera", "Linux": "Altera"}) if path is None: return super()._GetDefaultInstallationDirectory() - return str(path) + return path.as_posix() diff --git a/py/ToolChains/Altera/ModelSim.py b/py/ToolChains/Altera/ModelSim.py index e4955040..e3b1c9f6 100644 --- a/py/ToolChains/Altera/ModelSim.py +++ b/py/ToolChains/Altera/ModelSim.py @@ -7,7 +7,7 @@ # Martin Zabel # Thomas B. Preusser # -# Python Class: Altera ModelSim specific classes +# Python Class: Altera ModelSim specific classes # # Description: # ------------------------------------ @@ -85,12 +85,12 @@ def ConfigureForAll(self): else: self._ConfigureInstallationDirectory() binPath = self._ConfigureBinaryDirectory() - self.__GetQuestaSimVersion(binPath) + self.__GetModelSimVersion(binPath) except ConfigurationException: self.ClearSection() raise - def __GetQuestaSimVersion(self, binPath): + def __GetModelSimVersion(self, binPath): if (self._host.Platform == "Windows"): vsimPath = binPath / "vsim.exe" else: diff --git a/py/ToolChains/Altera/Quartus.py b/py/ToolChains/Altera/Quartus.py index a150f870..e4114e13 100644 --- a/py/ToolChains/Altera/Quartus.py +++ b/py/ToolChains/Altera/Quartus.py @@ -111,32 +111,33 @@ def __CheckQuartusVersion(self, binPath, version): class QuartusMixIn: - def __init__(self, platform, binaryDirectoryPath, version, logger=None): + def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): self._platform = platform - self._binaryDirectoryPath = binaryDirectoryPath - self._version = version - self._logger = logger + self._dryrun = dryrun + self._binaryDirectoryPath = binaryDirectoryPath + self._version = version + self._Logger = logger class Quartus(QuartusMixIn): - def __init__(self, platform, binaryDirectoryPath, version, logger=None): - QuartusMixIn.__init__(self, platform, binaryDirectoryPath, version, logger) + def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): + QuartusMixIn.__init__(self, platform, dryrun, binaryDirectoryPath, version, logger) def GetMap(self): - return Map(self._platform, self._binaryDirectoryPath, self._version, logger=self._logger) + return Map(self._platform, self._dryrun, self._binaryDirectoryPath, self._version, logger=self._Logger) def GetTclShell(self): - return TclShell(self._platform, self._binaryDirectoryPath, self._version, logger=self._logger) + return TclShell(self._platform, self._dryrun, self._binaryDirectoryPath, self._version, logger=self._Logger) class Map(Executable, QuartusMixIn): - def __init__(self, platform, binaryDirectoryPath, version, logger=None): - QuartusMixIn.__init__(self, platform, binaryDirectoryPath, version, logger) + def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): + QuartusMixIn.__init__(self, platform, dryrun, binaryDirectoryPath, version, logger) if (platform == "Windows") : executablePath = binaryDirectoryPath / "quartus_map.exe" elif (platform == "Linux") : executablePath = binaryDirectoryPath / "quartus_map" else : raise PlatformNotSupportedException(platform) - Executable.__init__(self, platform, executablePath, logger=logger) + Executable.__init__(self, platform, dryrun, executablePath, logger=logger) self.Parameters[self.Executable] = executablePath @@ -174,7 +175,11 @@ class SwitchDevicePart(metaclass=LongValuedFlagArgument) : def Compile(self) : parameterList = self.Parameters.ToArgumentList() - self._LogVerbose("command: {0}".format(" ".join(parameterList))) + self.LogVerbose("command: {0}".format(" ".join(parameterList))) + + if (self._dryrun): + self.LogDryRun("Start process: {0}".format(" ".join(parameterList))) + return try: self.StartProcess(parameterList) @@ -189,31 +194,31 @@ def Compile(self) : line = next(iterator) self._hasOutput = True - self._LogNormal(" quartus_map messages for '{0}'".format(self.Parameters[self.SwitchArgumentFile])) - self._LogNormal(" " + ("-" * 76)) + self.LogNormal(" quartus_map messages for '{0}'".format(self.Parameters[self.SwitchArgumentFile])) + self.LogNormal(" " + ("-" * (78 - self.Logger.BaseIndent*2))) while True: self._hasWarnings |= (line.Severity is Severity.Warning) self._hasErrors |= (line.Severity is Severity.Error) - line.IndentBy(2) - self._Log(line) + line.IndentBy(self.Logger.BaseIndent + 1) + self.Log(line) line = next(iterator) except StopIteration: pass finally: if self._hasOutput: - self._LogNormal(" " + ("-" * 76)) + self.LogNormal(" " + ("-" * (78 - self.Logger.BaseIndent*2))) class TclShell(Executable, QuartusMixIn): - def __init__(self, platform, binaryDirectoryPath, version, logger=None): - QuartusMixIn.__init__(self, platform, binaryDirectoryPath, version, logger) + def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): + QuartusMixIn.__init__(self, platform, dryrun, binaryDirectoryPath, version, logger) if (platform == "Windows") : executablePath = binaryDirectoryPath / "quartus_sh.exe" elif (platform == "Linux") : executablePath = binaryDirectoryPath / "quartus_sh" else : raise PlatformNotSupportedException(platform) - Executable.__init__(self, platform, executablePath, logger=logger) + super().__init__(platform, dryrun, executablePath, logger=logger) self.Parameters[self.Executable] = executablePath @@ -253,15 +258,54 @@ def MapFilter(gen): else: yield LogEntry(line, Severity.Normal) + +class QuartusSession: + def __init__(self, host): + self.TclShell = host.Toolchain.GetTclShell() + self.TclShell.Parameters[self.TclShell.SwitchShell] = True + self.TclShell.StartProcess() + self.TclShell.SendBoundary() + self.TclShell.ReadUntilBoundary() + + def exit(self): + self.TclShell.Send("exit") + self.TclShell.ReadUntilBoundary() + + class QuartusProject(BaseProject): def __init__(self, host, name, projectFile=None): super().__init__(name) self._host = host - self._projectFile = projectFile + self._projectFile = projectFile + + def Create(self, session=None): + if (session is None): + tclShell = self._host.Toolchain.GetTclShell() + tclShell.Parameters[tclShell.SwitchShell] = True + tclShell.StartProcess() + tclShell.SendBoundary() + tclShell.ReadUntilBoundary() + else: + tclShell = session.TclShell - def Save(self): - pass + tclShell.Send("project_create {0}".format(self._name)) + tclShell.SendBoundary() + tclShell.ReadUntilBoundary() + + if (session is None): + tclShell.Send("project_close") + tclShell.SendBoundary() + tclShell.ReadUntilBoundary() + + tclShell.Send("exit") + tclShell.ReadUntilBoundary() + + def Save(self, session): + tclShell = session.TclShell + tclShell.Send("export_assignments") + tclShell.SendBoundary() + tclShell.ReadUntilBoundary() def Read(self): tclShell = self._host.Toolchain.GetSynthesizer() @@ -276,21 +320,32 @@ def Read(self): tclShell.Send("exit") tclShell.ReadUntilBoundary() - def Open(self): - pass + def Open(self, session): + tclShell = session.TclShell - def Close(self): - pass + tclShell.Send("project_open {0}".format(self._name)) + tclShell.SendBoundary() + tclShell.ReadUntilBoundary() + + def Close(self, session): + tclShell = session.TclShell + tclShell.Send("project_close") + tclShell.SendBoundary() + tclShell.ReadUntilBoundary() -class QuartusSettingsFile(SettingsFile): + tclShell.Send("exit") + tclShell.ReadUntilBoundary() + + +class QuartusSettings(SettingsFile): def __init__(self, name, settingsFile=None): super().__init__(name) - self._projectFile = settingsFile - - self._sourceFiles = [] - self._globalAssignments = OrderedDict() + self._projectFile = settingsFile + self._sourceFiles = [] + self._globalAssignments = OrderedDict() + self._parameters = {} @property def File(self): @@ -305,6 +360,10 @@ def File(self, value): def GlobalAssignments(self): return self._globalAssignments + @property + def Parameters(self): + return self._parameters + def CopySourceFilesFromProject(self, project): for file in project.Files(fileType=FileTypes.VHDLSourceFile): self._sourceFiles.append(file) @@ -316,6 +375,10 @@ def Write(self): for key,value in self._globalAssignments.items(): buffer += "set_global_assignment -name {key} {value!s}\n".format(key=key, value=value) + buffer += "\n" + for key,value in self._parameters.items(): + buffer += "set_parameter -name {key} {value}\n".format(key=key, value=value) + buffer += "\n" for file in self._sourceFiles: if (not file.Path.exists()): diff --git a/py/ToolChains/GHDL.py b/py/ToolChains/GHDL.py index 3cef0a2c..1af50cc1 100644 --- a/py/ToolChains/GHDL.py +++ b/py/ToolChains/GHDL.py @@ -7,7 +7,7 @@ # Martin Zabel # Thomas B. Preusser # -# Python Class: GHDL specific classes +# Python Class: GHDL specific classes # # Description: # ------------------------------------ @@ -43,17 +43,17 @@ from pathlib import Path -from re import compile as RegExpCompile +from re import compile as re_compile from subprocess import check_output, CalledProcessError -from Base.Configuration import Configuration as BaseConfiguration, ConfigurationException +from Base.Configuration import Configuration as BaseConfiguration, ConfigurationException from Base.Exceptions import PlatformNotSupportedException -from Base.Executable import Executable +from Base.Executable import Executable, LongValuedFlagArgument from Base.Executable import ExecutableArgument, PathArgument, StringArgument, ValuedFlagListArgument -from Base.Executable import ShortFlagArgument, LongFlagArgument, ShortValuedFlagArgument, CommandLineArgumentList -from Base.Logging import LogEntry, Severity -from Base.Simulator import PoCSimulationResultFilter, SimulationResult -from Base.ToolChain import ToolChainException +from Base.Executable import ShortFlagArgument, LongFlagArgument, CommandLineArgumentList +from Base.Logging import LogEntry, Severity +from Base.Simulator import PoCSimulationResultFilter, SimulationResult +from Base.ToolChain import ToolChainException from lib.Functions import CallByRefParam @@ -75,22 +75,25 @@ class Configuration(BaseConfiguration): "Version": "0.34dev", "InstallationDirectory": "C:/Tools/GHDL/0.34dev", "BinaryDirectory": "${InstallationDirectory}/bin", + "ScriptDirectory": "${InstallationDirectory}/lib/vendors", "Backend": "mcode" } }, "Linux": { _section: { "Version": "0.34dev", - "InstallationDirectory": "/usr/bin", - "BinaryDirectory": "${InstallationDirectory}", + "InstallationDirectory": "/usr/local", + "BinaryDirectory": "${InstallationDirectory}/bin", + "ScriptDirectory": "${InstallationDirectory}/lib/ghdl/vendors", "Backend": "llvm" } }, "Darwin": { _section: { "Version": "0.34dev", - "InstallationDirectory": None, - "BinaryDirectory": "${InstallationDirectory}", + "InstallationDirectory": "/usr/local", + "BinaryDirectory": "${InstallationDirectory}/bin", + "ScriptDirectory": "${InstallationDirectory}/lib/ghdl/vendors", "Backend": "llvm" } } @@ -111,13 +114,28 @@ def ConfigureForAll(self): def _GetDefaultInstallationDirectory(self): if (self._host.Platform in ["Linux", "Darwin"]): try: - name = check_output(["which", "ghdl"], universal_newlines=True) - if name != "": return str(Path(name[:-1]).parent) + name = check_output(["which", "ghdl"], universal_newlines=True).strip() + if name != "": return Path(name).parent.as_posix() except CalledProcessError: pass # `which` returns non-zero exit code if GHDL is not in PATH return super()._GetDefaultInstallationDirectory() + def _ConfigureBinaryDirectory(self): + """Updates section with value from _template and returns directory as Path object.""" + self._ConfigureScriptDirectory() + return super()._ConfigureBinaryDirectory() + + def _ConfigureScriptDirectory(self): + """Updates section with value from _template and returns directory as Path object.""" + unresolved = self._template[self._host.Platform][self._section]['ScriptDirectory'] + self._host.PoCConfig[self._section]['ScriptDirectory'] = unresolved # create entry + scriptPath = Path(self._host.PoCConfig[self._section]['ScriptDirectory']) # resolve entry + + if (not scriptPath.exists()): + raise ConfigurationException("{0!s} script directory '{1!s}' does not exist.".format(self, scriptPath)) \ + from NotADirectoryError(str(scriptPath)) + def __WriteGHDLSection(self, binPath): if (self._host.Platform == "Windows"): ghdlPath = binPath / "ghdl.exe" @@ -133,9 +151,9 @@ def __WriteGHDLSection(self, binPath): version = None backend = None versionRegExpStr = r"^GHDL (.+?) " - versionRegExp = RegExpCompile(versionRegExpStr) - backendRegExpStr = r" (\w+) code generator" - backendRegExp = RegExpCompile(backendRegExpStr) + versionRegExp = re_compile(versionRegExpStr) + backendRegExpStr = r"(?i).*(mcode|gcc|llvm).* code generator" + backendRegExp = re_compile(backendRegExpStr) for line in output.split('\n'): if version is None: match = versionRegExp.match(line) @@ -145,19 +163,22 @@ def __WriteGHDLSection(self, binPath): if backend is None: match = backendRegExp.match(line) if match is not None: - backend = match.group(1) + backend = match.group(1).lower() + + if ((version is None) or (backend is None)): + raise ConfigurationException("Version number or back-end name not found in '{0!s} -v' output.".format(ghdlPath)) self._host.PoCConfig[self._section]['Version'] = version self._host.PoCConfig[self._section]['Backend'] = backend class GHDL(Executable): - def __init__(self, platform, binaryDirectoryPath, version, backend, logger=None): - if (platform == "Windows"): executablePath = binaryDirectoryPath/ "ghdl.exe" - elif (platform == "Linux"): executablePath = binaryDirectoryPath/ "ghdl" - elif (platform == "Darwin"): executablePath = binaryDirectoryPath/ "ghdl" - else: raise PlatformNotSupportedException(platform) - super().__init__(platform, executablePath, logger=logger) + def __init__(self, platform, dryrun, binaryDirectoryPath, version, backend, logger=None): + if (platform == "Windows"): executablePath = binaryDirectoryPath / "ghdl.exe" + elif (platform == "Linux"): executablePath = binaryDirectoryPath / "ghdl" + elif (platform == "Darwin"): executablePath = binaryDirectoryPath / "ghdl" + else: raise PlatformNotSupportedException(platform) + super().__init__(platform, dryrun, executablePath, logger=logger) self.Executable = executablePath #self.Parameters[self.Executable] = executablePath @@ -165,9 +186,9 @@ def __init__(self, platform, binaryDirectoryPath, version, backend, logger=None) if (platform == "Windows"): if (backend not in ["mcode"]): raise GHDLException("GHDL for Windows does not support backend '{0}'.".format(backend)) elif (platform == "Linux"): - if (backend not in ["gcc", "llvm", "mcode"]): raise GHDLException("GHDL for Linux does not support backend '{0}'.".format(backend)) + if (backend not in ["gcc", "llvm", "mcode"]): raise GHDLException("GHDL for Linux does not support backend '{0}'.".format(backend)) elif (platform == "Darwin"): - if (backend not in ["gcc", "llvm", "mcode"]): raise GHDLException("GHDL for OS X does not support backend '{0}'.".format(backend)) + if (backend not in ["gcc", "llvm", "mcode"]): raise GHDLException("GHDL for OS X does not support backend '{0}'.".format(backend)) self._binaryDirectoryPath = binaryDirectoryPath self._backend = backend @@ -233,21 +254,18 @@ class FlagSynBinding(metaclass=LongFlagArgument): class FlagPSL(metaclass=ShortFlagArgument): _name = "fpsl" - class SwitchIEEEFlavor(metaclass=ShortValuedFlagArgument): - _pattern = "--{0}={1}" - _name = "ieee" + class SwitchIEEEFlavor(metaclass=LongValuedFlagArgument): + _name = "ieee" - class SwitchVHDLVersion(metaclass=ShortValuedFlagArgument): - _pattern = "--{0}={1}" - _name = "std" + class SwitchVHDLVersion(metaclass=LongValuedFlagArgument): + _name = "std" - class SwitchVHDLLibrary(metaclass=ShortValuedFlagArgument): - _pattern = "--{0}={1}" - _name = "work" + class SwitchVHDLLibrary(metaclass=LongValuedFlagArgument): + _name = "work" class ArgListLibraryReferences(metaclass=ValuedFlagListArgument): _pattern = "-{0}{1}" - _name = "P" + _name = "P" class ArgSourceFile(metaclass=PathArgument): pass @@ -276,36 +294,35 @@ class ArgTopLevel(metaclass=StringArgument): ArgTopLevel ) - class SwitchIEEEAsserts(metaclass=ShortValuedFlagArgument): - _pattern = "--{0}={1}" - _name = "ieee-asserts" + class SwitchIEEEAsserts(metaclass=LongValuedFlagArgument): + _name = "ieee-asserts" - class SwitchVCDWaveform(metaclass=ShortValuedFlagArgument): - _pattern = "--{0}={1}" - _name = "vcd" + class SwitchVCDWaveform(metaclass=LongValuedFlagArgument): + _name = "vcd" - class SwitchVCDGZWaveform(metaclass=ShortValuedFlagArgument): - _pattern = "--{0}={1}" - _name = "vcdgz" + class SwitchVCDGZWaveform(metaclass=LongValuedFlagArgument): + _name = "vcdgz" - class SwitchFastWaveform(metaclass=ShortValuedFlagArgument): - _pattern = "--{0}={1}" - _name = "fst" + class SwitchFastWaveform(metaclass=LongValuedFlagArgument): + _name = "fst" - class SwitchGHDLWaveform(metaclass=ShortValuedFlagArgument): - _pattern = "--{0}={1}" - _name = "wave" + class SwitchGHDLWaveform(metaclass=LongValuedFlagArgument): + _name = "wave" + + class SwitchWaveformSelect(metaclass=LongValuedFlagArgument): + _name = "wave-opt-file" # requires GHDL update RunOptions = CommandLineArgumentList( SwitchIEEEAsserts, SwitchVCDWaveform, SwitchVCDGZWaveform, SwitchFastWaveform, - SwitchGHDLWaveform + SwitchGHDLWaveform, + SwitchWaveformSelect ) def GetGHDLAnalyze(self): - ghdl = GHDLAnalyze(self._platform, self._binaryDirectoryPath, self._version, self._backend, logger=self.Logger) + ghdl = GHDLAnalyze(self._platform, self._dryrun, self._binaryDirectoryPath, self._version, self._backend, logger=self._Logger) for param in ghdl.Parameters: if (param is not ghdl.Executable): ghdl.Parameters[param] = None @@ -313,7 +330,7 @@ def GetGHDLAnalyze(self): return ghdl def GetGHDLElaborate(self): - ghdl = GHDLElaborate(self._platform, self._binaryDirectoryPath, self._version, self._backend, logger=self.Logger) + ghdl = GHDLElaborate(self._platform, self._dryrun, self._binaryDirectoryPath, self._version, self._backend, logger=self._Logger) for param in ghdl.Parameters: if (param is not ghdl.Executable): ghdl.Parameters[param] = None @@ -321,7 +338,7 @@ def GetGHDLElaborate(self): return ghdl def GetGHDLRun(self): - ghdl = GHDLRun(self._platform, self._binaryDirectoryPath, self._version, self._backend, logger=self.Logger) + ghdl = GHDLRun(self._platform, self._dryrun, self._binaryDirectoryPath, self._version, self._backend, logger=self._Logger) for param in ghdl.Parameters: if (param is not ghdl.Executable): ghdl.Parameters[param] = None @@ -330,13 +347,17 @@ def GetGHDLRun(self): class GHDLAnalyze(GHDL): - def __init__(self, platform, binaryDirectoryPath, version, backend, logger=None): - super().__init__(platform, binaryDirectoryPath, version, backend, logger=logger) + def __init__(self, platform, dryrun, binaryDirectoryPath, version, backend, logger=None): + super().__init__(platform, dryrun, binaryDirectoryPath, version, backend, logger=logger) def Analyze(self): parameterList = self.Parameters.ToArgumentList() parameterList.insert(0, self.Executable) - self._LogVerbose("command: {0}".format(" ".join(parameterList))) + self.LogVerbose("command: {0}".format(" ".join(parameterList))) + + if (self._dryrun): + self.LogDryRun("Start process: {0}".format(" ".join(parameterList))) + return try: self.StartProcess(parameterList) @@ -351,31 +372,35 @@ def Analyze(self): line = next(iterator) self._hasOutput = True - self._LogNormal(" ghdl analyze messages for '{0}'".format(self.Parameters[self.ArgSourceFile])) - self._LogNormal(" " + ("-" * 76)) + self.LogNormal(" ghdl analyze messages for '{0}'".format(self.Parameters[self.ArgSourceFile])) + self.LogNormal(" " + ("-" * (78 - self.Logger.BaseIndent*2))) while True: self._hasWarnings |= (line.Severity is Severity.Warning) self._hasErrors |= (line.Severity is Severity.Error) - line.IndentBy(2) - self._Log(line) + line.IndentBy(self.Logger.BaseIndent + 1) + self.Log(line) line = next(iterator) except StopIteration: pass finally: if self._hasOutput: - self._LogNormal(" " + ("-" * 76)) + self.LogNormal(" " + ("-" * (78 - self.Logger.BaseIndent*2))) class GHDLElaborate(GHDL): - def __init__(self, platform, binaryDirectoryPath, version, backend, logger=None): - super().__init__(platform, binaryDirectoryPath, version, backend, logger=logger) + def __init__(self, platform, dryrun, binaryDirectoryPath, version, backend, logger=None): + super().__init__(platform, dryrun, binaryDirectoryPath, version, backend, logger=logger) def Elaborate(self): parameterList = self.Parameters.ToArgumentList() parameterList.insert(0, self.Executable) - self._LogVerbose("command: {0}".format(" ".join(parameterList))) + self.LogVerbose("command: {0}".format(" ".join(parameterList))) + + if (self._dryrun): + self.LogDryRun("Start process: {0}".format(" ".join(parameterList))) + return try: self.StartProcess(parameterList) @@ -389,38 +414,41 @@ def Elaborate(self): iterator = iter(GHDLElaborateFilter(self.GetReader())) line = next(iterator) - line.IndentBy(2) + line.IndentBy(self.Logger.BaseIndent + 1) self._hasOutput = True vhdlLibraryName = self.Parameters[self.SwitchVHDLLibrary] topLevel = self.Parameters[self.ArgTopLevel] - self._LogNormal(" ghdl elaborate messages for '{0}.{1}'".format(vhdlLibraryName, topLevel)) - self._LogNormal(" " + ("-" * 76)) - self._Log(line) + self.LogNormal(" ghdl elaborate messages for '{0}.{1}'".format(vhdlLibraryName, topLevel)) + self.LogNormal(" " + ("-" * (78 - self.Logger.BaseIndent*2))) + self.Log(line) while True: self._hasWarnings |= (line.Severity is Severity.Warning) self._hasErrors |= (line.Severity is Severity.Error) line = next(iterator) - line.IndentBy(2) - self._Log(line) + line.IndentBy(self.Logger.BaseIndent + 1) + self.Log(line) except StopIteration: pass finally: if self._hasOutput: - self._LogNormal(" " + ("-" * 76)) + self.LogNormal(" " + ("-" * (78 - self.Logger.BaseIndent*2))) class GHDLRun(GHDL): - def __init__(self, platform, binaryDirectoryPath, version, backend, logger=None): - super().__init__(platform, binaryDirectoryPath, version, backend, logger=logger) + def __init__(self, platform, dryrun, binaryDirectoryPath, version, backend, logger=None): + super().__init__(platform, dryrun, binaryDirectoryPath, version, backend, logger=logger) def Run(self): parameterList = self.Parameters.ToArgumentList() parameterList += self.RunOptions.ToArgumentList() parameterList.insert(0, self.Executable) + self.LogVerbose("command: {0}".format(" ".join(parameterList))) - self._LogVerbose("command: {0}".format(" ".join(parameterList))) + if (self._dryrun): + self.LogDryRun("Start process: {0}".format(" ".join(parameterList))) + return try: self.StartProcess(parameterList) @@ -435,38 +463,41 @@ def Run(self): iterator = iter(PoCSimulationResultFilter(GHDLRunFilter(self.GetReader()), simulationResult)) line = next(iterator) - line.IndentBy(2) + line.IndentBy(self.Logger.BaseIndent + 1) self._hasOutput = True vhdlLibraryName = self.Parameters[self.SwitchVHDLLibrary] topLevel = self.Parameters[self.ArgTopLevel] - self._LogNormal(" ghdl run messages for '{0}.{1}'".format(vhdlLibraryName, topLevel)) - self._LogNormal(" " + ("-" * 76)) - self._Log(line) + self.LogNormal(" ghdl run messages for '{0}.{1}'".format(vhdlLibraryName, topLevel)) + self.LogNormal(" " + ("-" * 76)) + self.Log(line) while True: self._hasWarnings |= (line.Severity is Severity.Warning) self._hasErrors |= (line.Severity is Severity.Error) line = next(iterator) - line.IndentBy(2) - self._Log(line) + line.IndentBy(self.Logger.BaseIndent + 1) + self.Log(line) except StopIteration: pass finally: if self._hasOutput: - self._LogNormal(" " + ("-" * 76)) + self.LogNormal(" " + ("-" * 76)) return simulationResult.value def GHDLAnalyzeFilter(gen): filterPattern = r".+?:\d+:\d+:(?Pwarning:)? (?P.*)" # :::[warning:] - filterRegExp = RegExpCompile(filterPattern) + filterRegExp = re_compile(filterPattern) for line in gen: filterMatch = filterRegExp.match(line) - if (filterMatch is not None): + if ("ghdl: compilation error" in line): + yield LogEntry(line, Severity.Error) + continue + elif (filterMatch is not None): if (filterMatch.group('warning') is not None): yield LogEntry(line, Severity.Warning) continue @@ -491,7 +522,7 @@ def GHDLRunFilter(gen): # (*) -> unknown -> Severity.Error filterPattern = r".+?:\d+:\d+:((?P@\w+:\((?:report|assertion) )?(?P\w+)(?(report)\)):)? (?P.*)" - filterRegExp = RegExpCompile(filterPattern) + filterRegExp = re_compile(filterPattern) lineno = 0 for line in gen: diff --git a/py/ToolChains/GNU.py b/py/ToolChains/GNU.py index 19e7cd69..8aa66d33 100644 --- a/py/ToolChains/GNU.py +++ b/py/ToolChains/GNU.py @@ -38,13 +38,11 @@ pass else: from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("PoC Library - Python Module ToolChains.GNU") # load dependencies import re -from Base.Configuration import Configuration as BaseConfiguration from Base.Exceptions import PlatformNotSupportedException from Base.Executable import Executable, ExecutableArgument, CommandLineArgumentList, ValuedFlagArgument from Base.Logging import LogEntry, Severity @@ -57,20 +55,11 @@ class GNUException(ToolChainException): pass -class Configuration(BaseConfiguration): - _vendor = "GNU" - _toolName = "GNU Make" - _section = None - - def CheckDependency(self): - return False - - class Make(Executable): - def __init__(self, platform, logger=None): + def __init__(self, platform, dryrun, logger=None): if (platform == "Linux"): executablePath = "/usr/bin/make" - else: raise PlatformNotSupportedException(self._platform) - super().__init__(platform, executablePath, logger=logger) + else: raise PlatformNotSupportedException(platform) + super().__init__(platform, dryrun, executablePath, logger=logger) self.Parameters[self.Executable] = executablePath @@ -91,7 +80,11 @@ class SwitchGui(metaclass=ValuedFlagArgument): def RunCocotb(self): parameterList = self.Parameters.ToArgumentList() - self._LogVerbose("command: {0}".format(" ".join(parameterList))) + self.LogVerbose("command: {0}".format(" ".join(parameterList))) + + if (self._dryrun): + self.LogDryRun("Start process: {0}".format(" ".join(parameterList))) + return try: self.StartProcess(parameterList) @@ -106,25 +99,25 @@ def RunCocotb(self): iterator = iter(CocotbSimulationResultFilter(GNUMakeQuestaSimFilter(self.GetReader()), simulationResult)) line = next(iterator) - line.IndentBy(2) + line.IndentBy(self.Logger.BaseIndent + 1) self._hasOutput = True - self._LogNormal(" Make messages") - self._LogNormal(" " + ("-" * 76)) - self._Log(line) + self.LogNormal(" Make messages") + self.LogNormal(" " + ("-" * (78 - self.Logger.BaseIndent*2))) + self.Log(line) while True: self._hasWarnings |= (line.Severity is Severity.Warning) self._hasErrors |= (line.Severity is Severity.Error) line = next(iterator) - line.IndentBy(2) - self._Log(line) + line.IndentBy(self.Logger.BaseIndent + 1) + self.Log(line) except StopIteration: pass finally: if self._hasOutput: - self._LogNormal(" " + ("-" * 76)) + self.LogNormal(" " + ("-" * (78 - self.Logger.BaseIndent*2))) return simulationResult.value @@ -164,4 +157,4 @@ def CocotbSimulationResultFilter(gen, simulationResult): line.Indent) continue - yield line \ No newline at end of file + yield line diff --git a/py/ToolChains/GTKWave.py b/py/ToolChains/GTKWave.py index 049c32f3..21deeeb8 100644 --- a/py/ToolChains/GTKWave.py +++ b/py/ToolChains/GTKWave.py @@ -104,8 +104,8 @@ def ConfigureForAll(self): def _GetDefaultInstallationDirectory(self): if (self._host.Platform in ["Linux", "Darwin"]): try: - name = check_output(["which", "gtkwave"], universal_newlines=True) - if name != "": return str(Path(name[:-1]).parent) + name = check_output(["which", "gtkwave"], universal_newlines=True).strip() + if name != "": return Path(name).parent.as_posix() except CalledProcessError: pass # `which` returns non-zero exit code if executable is not in PATH @@ -137,21 +137,21 @@ def __WriteGtkWaveSection(self, binPath): class GTKWave(Executable): - def __init__(self, platform, binaryDirectoryPath, version, logger=None): - if (platform == "Windows"): executablePath = binaryDirectoryPath/ "gtkwave.exe" - elif (platform == "Linux"): executablePath = binaryDirectoryPath/ "gtkwave" + def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): + if (platform == "Windows"): executablePath = binaryDirectoryPath/ "gtkwave.exe" + elif (platform == "Linux"): executablePath = binaryDirectoryPath/ "gtkwave" elif (platform == "Darwin"): executablePath = binaryDirectoryPath/ "gtkwave" else: raise PlatformNotSupportedException(self._platform) - super().__init__(platform, executablePath, logger=logger) + super().__init__(platform, dryrun, executablePath, logger=logger) self.Parameters[self.Executable] = executablePath - self._binaryDirectoryPath = binaryDirectoryPath - self._version = version + self._binaryDirectoryPath = binaryDirectoryPath + self._version = version - self._hasOutput = False + self._hasOutput = False self._hasWarnings = False - self._hasErrors = False + self._hasErrors = False @property def BinaryDirectoryPath(self): @@ -178,7 +178,11 @@ class SwitchSaveFile(metaclass=LongValuedFlagArgument): def View(self): parameterList = self.Parameters.ToArgumentList() - self._LogVerbose("command: {0}".format(" ".join(parameterList))) + self.LogVerbose("command: {0}".format(" ".join(parameterList))) + + if (self._dryrun): + self.LogDryRun("Start process: {0}".format(" ".join(parameterList))) + return try: self.StartProcess(parameterList) @@ -192,25 +196,25 @@ def View(self): iterator = iter(GTKWaveFilter(self.GetReader())) line = next(iterator) - line.IndentBy(2) + line.IndentBy(self.Logger.BaseIndent + 1) self._hasOutput = True - self._LogNormal(" GTKWave messages for '{0}'".format(self.Parameters[self.SwitchDumpFile])) - self._LogNormal(" " + ("-" * 76)) - self._Log(line) + self.LogNormal(" GTKWave messages for '{0}'".format(self.Parameters[self.SwitchDumpFile])) + self.LogNormal(" " + ("-" * (78 - self.Logger.BaseIndent*2))) + self.Log(line) while True: self._hasWarnings |= (line.Severity is Severity.Warning) self._hasErrors |= (line.Severity is Severity.Error) line = next(iterator) - line.IndentBy(2) - self._Log(line) + line.IndentBy(self.Logger.BaseIndent + 1) + self.Log(line) except StopIteration: pass finally: if self._hasOutput: - self._LogNormal(" " + ("-" * 76)) + self.LogNormal(" " + ("-" * (78 - self.Logger.BaseIndent*2))) def GTKWaveFilter(gen): for line in gen: diff --git a/py/ToolChains/Git.py b/py/ToolChains/Git.py new file mode 100644 index 00000000..07e14b72 --- /dev/null +++ b/py/ToolChains/Git.py @@ -0,0 +1,494 @@ +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# +# ============================================================================== +# Authors: Patrick Lehmann +# Martin Zabel +# Thomas B. Preusser +# +# Python Class: Git specific classes +# +# Description: +# ------------------------------------ +# TODO: +# - +# - +# +# License: +# ============================================================================== +# Copyright 2007-2016 Technische Universitaet Dresden - Germany +# Chair for VLSI-Design, Diagnostics and Architecture +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================== +# +# entry point +if __name__ != "__main__": + # place library initialization code here + pass +else: + from lib.Functions import Exit + Exit.printThisIsNoExecutableFile("PoC Library - Python Module ToolChains.PoC") + + +from pathlib import Path +from re import compile as re_compile +from subprocess import check_output, CalledProcessError +from os import environ +from shutil import copy as shutil_copy + +from Base.Exceptions import PlatformNotSupportedException, CommonException +from Base.Configuration import Configuration as BaseConfiguration, ConfigurationException, SkipConfigurationException +from Base.Executable import Executable, ExecutableArgument, CommandLineArgumentList, CommandArgument, LongFlagArgument, ValuedFlagArgument, StringArgument +from Base.ToolChain import ToolChainException + + +class GitException(ToolChainException): + pass + + +class Configuration(BaseConfiguration): + _vendor = "Git SCM" + _toolName = "Git" + _section = "INSTALL.Git" + _template = { + "Windows": { + _section: { + "Version": "2.8.2", + "InstallationDirectory": "C:/Program Files/Git", + "BinaryDirectory": "${InstallationDirectory}/cmd" + } + }, + "Linux": { + _section: { + "Version": "2.8.1", + "InstallationDirectory": "/usr/bin", + "BinaryDirectory": "${InstallationDirectory}" + } + } + } + + def __init__(self, host): + super().__init__(host) + + self._git = None + + def ConfigureForAll(self): + try: + self._ConfigureInstallationDirectory() + binPath = self._ConfigureBinaryDirectory() + self.__WriteGitSection(binPath) + except ConfigurationException: + self.ClearSection() + raise + + if (len(self._host.PoCConfig['INSTALL.Git']) == 0): + self._host.LogNormal(" Skipping Git setup. Not Git installation found.") + return + + try: + binaryDirectoryPath = binPath + self._git = Git(self._host.Platform, self._host.DryRun, binaryDirectoryPath, logger=self._host.Logger) + except Exception as ex: + self._host.LogWarning(str(ex)) + + if (not self.__IsUnderGitControl()): + self._host.LogNormal("Skipping Git setup. This directory is not under Git control.") + return + + if (not self._AskDoInstall("Install Git mechanisms for PoC developers?")): + self.__UninstallGitFilters() + self.__UninstallGitHooks() + return + + if (self._AskInstalled("Install Git filters?")): + self.__InstallGitFilters() + if (self._AskInstalled("Install Git hooks?")): + self.__InstallGitHooks() + + def _GetDefaultInstallationDirectory(self): + if (self._host.Platform == "Windows"): + # TODO: extract to base class -> provide a SearchInPath method + envPath = environ.get('PATH') + for pathItem in envPath.split(";"): + binaryDirectoryPath = Path(pathItem) + gitPath = binaryDirectoryPath / "git.exe" + if gitPath.exists(): + return binaryDirectoryPath.parent.as_posix() + raise GitException("No Git installation found.") + elif (self._host.Platform in ["Linux", "Darwin"]): + try: + name = check_output(["which", "git"], universal_newlines=True).strip() + if name != "": + return Path(name).parent.as_posix() + except CalledProcessError: + pass # `which` returns non-zero exit code if GHDL is not in PATH + + return super()._GetDefaultInstallationDirectory() + + def _AskDoInstall(self, question): + isInstalled = input(" " + question + " [y/N/p]: ") + isInstalled = isInstalled if isInstalled != "" else "N" + if (isInstalled in ['p', 'P']): + raise SkipConfigurationException() + elif (isInstalled in ['n', 'N']): + return False + elif (isInstalled in ['y', 'Y']): + return True + else: + raise ConfigurationException("Unsupported choice '{0}'".format(isInstalled)) + + def __WriteGitSection(self, binPath): + if (self._host.Platform == "Windows"): + gitPath = binPath / "git.exe" + else: + gitPath = binPath / "git" + + if not gitPath.exists(): + raise ConfigurationException("Executable '{0!s}' not found.".format(gitPath)) from FileNotFoundError(str(gitPath)) + + # get version and backend + output = check_output([str(gitPath), "--version"], universal_newlines=True) + version = None + versionRegExpStr = r"^git version (\d\.\d\.\d+).*" + versionRegExp = re_compile(versionRegExpStr) + for line in output.split('\n'): + if version is None: + match = versionRegExp.match(line) + if match is not None: + version = match.group(1) + + if (version is None): + raise ConfigurationException("Version number not found in '{0!s} --version' output.".format(gitPath)) + + self._host.PoCConfig[self._section]['Version'] = version + + def __IsUnderGitControl(self): + try: + gitRevParse = self._git.GetGitRevParse() + gitRevParse.RevParseParameters[gitRevParse.SwitchInsideWorkingTree] = True + output = gitRevParse.Execute() + return (output == "true") + except CommonException: + return False + + def __UninstallGitFilters(self): + self._host.LogNormal(" Uninstalling Git filters...") + + for fileFormat in [None, "rest", "vhdl"]: + filterName = "filter.normalize" + if (fileFormat is not None): + filterName += "_" + fileFormat + + try: + git = self._git.GetGitConfig() + git.ConfigParameters[git.SwitchRemoveSection] = True + git.ConfigParameters[git.ValueFilterParameters] = filterName + git.Execute() + except CommonException: + self._host.LogWarning(" Error while removing section {0}.".format(filterName)) + + def __InstallGitFilters(self): + self._host.LogNormal(" Installing Git filters...") + + normalizeScript = "tools/git/filters/normalize.pl" + pocInstallationPath = Path(self._host.PoCConfig['INSTALL.PoC']['InstallationDirectory']) + normalizeScriptPath = pocInstallationPath / normalizeScript + + if (not normalizeScriptPath.exists()): + raise ConfigurationException("Normalize script '{0!s}' not found.".format(normalizeScriptPath)) from FileNotFoundError(str(normalizeScriptPath)) + + try: + commonCleanParameters = normalizeScript + " clean" + commonSmudgeParameters = normalizeScript + " smudge" + + for fileFormat in [None, "rest", "vhdl"]: + filterName = "normalize" + cleanParameters = commonCleanParameters + smudgeParameters = commonSmudgeParameters + + if (fileFormat is not None): + filterName += "_" + fileFormat + cleanParameters += " " + fileFormat + smudgeParameters += " " + fileFormat + + git = self._git.GetGitConfig() + git.ConfigParameters[git.ValueFilterClean] = filterName + git.ConfigParameters[git.ValueFilterParameters] = cleanParameters + git.Execute() + + git = self._git.GetGitConfig() + git.ConfigParameters[git.ValueFilterSmudge] = filterName + git.ConfigParameters[git.ValueFilterParameters] = smudgeParameters + git.Execute() + except CommonException: + return False + + def __UninstallGitHooks(self): + self._host.LogNormal(" Uninstalling Git hooks...") + pocInstallationPath = Path(self._host.PoCConfig['INSTALL.PoC']['InstallationDirectory']) + hookRunnerPath = pocInstallationPath / "tools/git/hooks/run-hook.sh" + + gitDirectoryPath = self.__GetGitDirectory() + gitHookDirectoryPath = gitDirectoryPath / "hooks" + + for hookName in ["pre-commit"]: + gitHookPath = gitHookDirectoryPath / hookName + if gitHookPath.exists(): + if (gitHookPath.is_symlink() and (gitHookPath.resolve() == hookRunnerPath)): + self._host.LogNormal(" '{0}' hook is configured for PoC. Deleting.".format(hookName)) + try: + gitHookPath.unlink() + except OSError as ex: + raise ConfigurationException("Cannot remove '{0!s}'.".format(gitHookPath)) from ex + else: + # TODO: check if file was copied -> Hash compare? + self._host.LogWarning(" '{0}' hook is in use by another script. Skipping.".format(hookName)) + + def __InstallGitHooks(self): + self._host.LogNormal(" Installing Git hooks...") + pocInstallationPath = Path(self._host.PoCConfig['INSTALL.PoC']['InstallationDirectory']) + hookRunnerPath = pocInstallationPath / "tools/git/hooks/run-hook.sh" + + if (not hookRunnerPath.exists()): + raise ConfigurationException("Runner script '{0!s}' not found.".format(hookRunnerPath)) from FileNotFoundError(str(hookRunnerPath)) + + gitDirectoryPath = self.__GetGitDirectory() + gitHookDirectoryPath = gitDirectoryPath / "hooks" + + for hookName in ["pre-commit"]: + gitHookPath = gitHookDirectoryPath / hookName + if gitHookPath.exists(): + if (gitHookPath.is_symlink() and (gitHookPath.resolve() == hookRunnerPath)): + self._host.LogNormal(" '{0}' hook is already configured for PoC.".format(hookName)) + else: + self._host.LogWarning(" '{0}' hook is already in use by another script.".format(hookName)) + else: + self._host.LogNormal(" Setting '{0}' hook for PoC...".format(hookName)) + self._host.LogDebug("symlink '{0!s}' -> '{1!s}'.".format(gitHookPath, hookRunnerPath)) + try: + gitHookPath.symlink_to(hookRunnerPath) + except OSError as ex: + # if symlink fails, do a copy as backup solution + if getattr(ex, 'winerror', None) == 1314: + self._host.LogDebug("copy '{0!s}' to '{1!s}'.".format(hookRunnerPath, gitHookPath)) + try: + shutil_copy(str(hookRunnerPath), str(gitHookPath)) + except OSError as ex2: + raise ConfigurationException() from ex2 + + def __GetGitDirectory(self): + try: + gitRevParse = self._git.GetGitRevParse() + gitRevParse.RevParseParameters[gitRevParse.SwitchGitDir] = True + gitDirectory = gitRevParse.Execute() + gitDirectoryPath = Path(gitDirectory) + except CommonException as ex: + raise ConfigurationException() from ex + + # WORKAROUND: GIT REV-PARSE + # if the Git repository isn't a Git submodule AND the current working + # directory is the Git top-level directory, then 'rev-parse' returns a + # relative path, otherwise the path is already absolute. + if (not gitDirectoryPath.is_absolute()): + pocInstallationPath = Path(self._host.PoCConfig['INSTALL.PoC']['InstallationDirectory']) + gitDirectoryPath = pocInstallationPath / gitDirectoryPath + + return gitDirectoryPath + + +class GitMixIn: + def __init__(self, platform, dryrun, binaryDirectoryPath, logger=None): + self._platform = platform + self._dryrun = dryrun + self._binaryDirectoryPath = binaryDirectoryPath + # self._version = version + self._Logger = logger + + +class Git(GitMixIn): + def GetGitRevParse(self): + git = GitRevParse(self._platform, self._dryrun, self._binaryDirectoryPath, logger=self._Logger) + git.Clear() + git.RevParseParameters[GitRevParse.Command] = True + + return git + + def GetGitConfig(self): + git = GitConfig(self._platform, self._dryrun, self._binaryDirectoryPath, logger=self._Logger) + git.Clear() + git.ConfigParameters[GitConfig.Command] = True + + return git + + +class GitSCM(Executable, GitMixIn): + def __init__(self, platform, dryrun, binaryDirectoryPath, logger=None): + GitMixIn.__init__(self, platform, dryrun, binaryDirectoryPath, logger=logger) + + if (platform == "Windows"): executablePath = binaryDirectoryPath / "git.exe" + elif (platform == "Linux"): executablePath = binaryDirectoryPath / "git" + elif (platform == "Darwin"): executablePath = binaryDirectoryPath / "git" + else: raise PlatformNotSupportedException(platform) + super().__init__(platform, dryrun, executablePath, logger=logger) + + self.Parameters[self.Executable] = executablePath + + def Clear(self): + for param in self.Parameters: + if (param is not self.Executable): + self.Parameters[param] = None + + class Executable(metaclass=ExecutableArgument): + pass + + class Switch_Version(metaclass=LongFlagArgument): + _name = "version" + + Parameters = CommandLineArgumentList( + Executable, + Switch_Version + ) + + +class GitRevParse(GitSCM): + def Clear(self): + super().Clear() + for param in self.RevParseParameters: + # if isinstance(param, ExecutableArgument): + # print("{0}".format(param.Value)) + # elif isinstance(param, NamedCommandLineArgument): + # print("{0}".format(param.Name)) + if (param is not self.Command): + # print(" clearing: {0} = {1} to None".format(param.Name, param.Value)) + self.RevParseParameters[param] = None + + class Command(metaclass=CommandArgument): + _name = "rev-parse" + + class SwitchInsideWorkingTree(metaclass=LongFlagArgument): + _name = "is-inside-work-tree" + + class SwitchShowTopLevel(metaclass=LongFlagArgument): + _name = "show-toplevel" + + class SwitchGitDir(metaclass=LongFlagArgument): + _name = "git-dir" + + RevParseParameters = CommandLineArgumentList( + Command, + SwitchInsideWorkingTree, + SwitchShowTopLevel, + SwitchGitDir + ) + + def Execute(self): + parameterList = self.Parameters.ToArgumentList() + parameterList += self.RevParseParameters.ToArgumentList() + self.LogVerbose("command: {0}".format(" ".join(parameterList))) + + if (self._dryrun): + self.LogDryRun("Start process: {0}".format(" ".join(parameterList))) + return + + try: + self.StartProcess(parameterList) + except Exception as ex: + raise GitException("Failed to launch Git.") from ex + + # FIXME: Replace GetReader with a shorter call to e.g. GetLine and/or GetLines + output = "" + for line in self.GetReader(): + output += line + + return output + +class GitConfig(GitSCM): + def Clear(self): + super().Clear() + for param in self.ConfigParameters: + # if isinstance(param, ExecutableArgument): + # print("{0}".format(param.Value)) + # elif isinstance(param, NamedCommandLineArgument): + # print("{0}".format(param.Name)) + if (param is not self.Command): + # print(" clearing: {0} = {1} to None".format(param.Name, param.Value)) + self.ConfigParameters[param] = None + + class Command(metaclass=CommandArgument): + _name = "config" + + class SwitchUnset(metaclass=LongFlagArgument): + _name = "unset" + + class SwitchRemoveSection(metaclass=LongFlagArgument): + _name = "remove-section" + + class ValueFilterClean(metaclass=ValuedFlagArgument): + _name = "clean" + _pattern = "filter.{1}.{0}" + + class ValueFilterSmudge(metaclass=ValuedFlagArgument): + _name = "smudge" + _pattern = "filter.{1}.{0}" + + class ValueFilterParameters(metaclass=StringArgument): + pass + + ConfigParameters = CommandLineArgumentList( + Command, + SwitchUnset, + SwitchRemoveSection, + ValueFilterClean, + ValueFilterSmudge, + ValueFilterParameters + ) + + def Execute(self): + parameterList = self.Parameters.ToArgumentList() + parameterList += self.ConfigParameters.ToArgumentList() + self.LogVerbose("command: {0}".format(" ".join(parameterList))) + + if (self._dryrun): + self.LogDryRun("Start process: {0}".format(" ".join(parameterList))) + return + + try: + self.StartProcess(parameterList) + except Exception as ex: + raise GitException("Failed to launch Git.") from ex + + # FIXME: Replace GetReader with a shorter call to e.g. GetLine and/or GetLines + output = "" + for line in self.GetReader(): + output += line + + return output + + # LOCAL = git rev-parse @ + # PS G:\git\PoC> git rev-parse "@" + # 9c05494ef52c276dabec69dbf734a22f65939305 + + # REMOTE = git rev-parse @{u} + # PS G:\git\PoC> git rev-parse "@{u}" + # 0ff166a40010c1b85a5ab655eea0148474f680c6 + + # MERGEBASE = git merge-base @ @{u} + # PS G:\git\PoC> git merge-base "@" "@{u}" + # 0ff166a40010c1b85a5ab655eea0148474f680c6 + + # if (local == remote): return "Up-to-date" + # elif (local == base): return "Need to pull" + # elif (remote == base): return "Need to push" + # else: return "divergent" diff --git a/py/ToolChains/Lattice/Diamond.py b/py/ToolChains/Lattice/Diamond.py index 97f0e9b9..0e8e8b6e 100644 --- a/py/ToolChains/Lattice/Diamond.py +++ b/py/ToolChains/Lattice/Diamond.py @@ -50,7 +50,7 @@ from Base.Exceptions import PlatformNotSupportedException from Base.Executable import Executable, CommandLineArgumentList, ExecutableArgument, ShortTupleArgument from Base.Logging import Severity, LogEntry -from Base.Project import File, FileTypes +from Base.Project import File, FileTypes, VHDLVersion from ToolChains.Lattice.Lattice import LatticeException @@ -136,33 +136,32 @@ def _ConfigureBinaryDirectory(self): class DiamondMixIn: - def __init__(self, platform, binaryDirectoryPath, version, logger=None): - self._platform = platform + def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): + self._platform = platform + self._dryrun = dryrun self._binaryDirectoryPath = binaryDirectoryPath - self._version = version - self._logger = logger + self._version = version + self._Logger = logger class Diamond(DiamondMixIn): - def __init__(self, platform, binaryDirectoryPath, version, logger=None): - DiamondMixIn.__init__(self, platform, binaryDirectoryPath, version, logger) + def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): + DiamondMixIn.__init__(self, platform, dryrun, binaryDirectoryPath, version, logger) def GetSynthesizer(self): - return Synth(self._platform, self._binaryDirectoryPath, self._version, logger=self._logger) + return Synth(self._platform, self._dryrun, self._binaryDirectoryPath, self._version, logger=self._Logger) + class Synth(Executable, DiamondMixIn): - def __init__(self, platform, binaryDirectoryPath, version, logger=None): - DiamondMixIn.__init__(self, platform, binaryDirectoryPath, version, logger) + def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): + DiamondMixIn.__init__(self, platform, dryrun, binaryDirectoryPath, version, logger) - if (platform == "Windows"): executablePath = binaryDirectoryPath / "pnwrap.exe" + if (platform == "Windows"): executablePath = binaryDirectoryPath / "synthesis.exe" elif (platform == "Linux"): executablePath = binaryDirectoryPath / "synthesis" else: raise PlatformNotSupportedException(platform) - Executable.__init__(self, platform, executablePath, logger=logger) + super().__init__(platform, dryrun, executablePath, logger=logger) self.Parameters[self.Executable] = executablePath - if (platform == "Windows"): - bin2dir = (binaryDirectoryPath / "../../ispfpga/bin/nt64").resolve() - self.Parameters[self.SwitchExecutable] = bin2dir / "synthesis.exe" self._hasOutput = False self._hasWarnings = False @@ -176,17 +175,12 @@ def HasErrors(self): return self._hasErrors class Executable(metaclass=ExecutableArgument): pass - class SwitchExecutable(metaclass=ShortTupleArgument): - _name = "exec" - _value = None - class SwitchProjectFile(metaclass=ShortTupleArgument): _name = "f" _value = None Parameters = CommandLineArgumentList( Executable, - SwitchExecutable, SwitchProjectFile ) @@ -201,7 +195,11 @@ def GetLogFileReader(self, logFile): def Compile(self, logFile): parameterList = self.Parameters.ToArgumentList() - self._LogVerbose("command: {0}".format(" ".join(parameterList))) + self.LogVerbose("command: {0}".format(" ".join(parameterList))) + + if (self._dryrun): + self.LogDryRun("Start process: {0}".format(" ".join(parameterList))) + return try: self.StartProcess(parameterList) @@ -212,28 +210,26 @@ def Compile(self, logFile): self._hasWarnings = False self._hasErrors = False try: - if (self._platform == "Linux"): reader = self.GetReader() # parse stdout directly - else: reader = self.GetLogFileReader(logFile) - iterator = iter(CompilerFilter(reader)) + iterator = iter(CompilerFilter(self.GetReader())) line = next(iterator) self._hasOutput = True - self._LogNormal(" LSE messages for '{0}'".format(self.Parameters[self.SwitchProjectFile])) - self._LogNormal(" " + ("-" * 76)) + self.LogNormal(" LSE messages for '{0}'".format(self.Parameters[self.SwitchProjectFile])) + self.LogNormal(" " + ("-" * (78 - self.Logger.BaseIndent*2))) while True: self._hasWarnings |= (line.Severity is Severity.Warning) self._hasErrors |= (line.Severity is Severity.Error) - line.IndentBy(2) - self._Log(line) + line.IndentBy(self.Logger.BaseIndent + 1) + self.Log(line) line = next(iterator) except StopIteration: pass finally: if self._hasOutput: - self._LogNormal(" " + ("-" * 76)) + self.LogNormal(" " + ("-" * (78 - self.Logger.BaseIndent*2))) def MapFilter(gen): @@ -250,7 +246,9 @@ def __init__(self, file): self._speedGrade = None self._package = None self._topLevel = None - self._logfile = None + self.Logfile = None + self._vhdlVersion = VHDLVersion.Any + self._hdlParams = {} @property def Architecture(self): @@ -289,10 +287,21 @@ def TopLevel(self, value): @property def LogFile(self): - return self._logfile + return self.Logfile @LogFile.setter def LogFile(self, value): - self._logfile = value + self.Logfile = value + + @property + def VHDLVersion(self): + return self._vhdlVersion + @VHDLVersion.setter + def VHDLVersion(self, value): + self._vhdlVersion = value + + @property + def HDLParams(self): + return self._hdlParams def Write(self, project): if (self._file is None): raise DiamondException("No file path for SynthesisArgumentFile provided.") @@ -308,8 +317,12 @@ def Write(self, project): buffer += "-t {0}\n".format(self._package) if (self._topLevel is None): raise DiamondException("Argument 'TopLevel' (-top) is not set.") buffer += "-top {0}\n".format(self._topLevel) - if (self._logfile is not None): - buffer += "-logfile {0}\n".format(self._logfile) + if (self._vhdlVersion is VHDLVersion.VHDL2008): + buffer += "-vh2008\n" + if (self.Logfile is not None): + buffer += "-logfile {0}\n".format(self.Logfile) + for keyValuePair in self._hdlParams.items(): + buffer += "-hdl_param {0} {1}\n".format(*keyValuePair) for file in project.Files(fileType=FileTypes.VHDLSourceFile): buffer += "-lib {library}\n-vhd {file}\n".format(file=file.Path.as_posix(), library=file.LibraryName) diff --git a/py/ToolChains/Lattice/Lattice.py b/py/ToolChains/Lattice/Lattice.py index db8d43a6..480b9c1b 100644 --- a/py/ToolChains/Lattice/Lattice.py +++ b/py/ToolChains/Lattice/Lattice.py @@ -70,7 +70,7 @@ class Configuration(BaseConfiguration): def _GetDefaultInstallationDirectory(self): path = self._TestDefaultInstallPath({"Windows": "Lattice", "Linux": "lattice"}) if path is None: return super()._GetDefaultInstallationDirectory() - return str(path) + return path.as_posix() class LatticeDesignConstraintFile(ConstraintFile): diff --git a/py/ToolChains/Mentor/Mentor.py b/py/ToolChains/Mentor/Mentor.py index 400d7fc4..3f59bf07 100644 --- a/py/ToolChains/Mentor/Mentor.py +++ b/py/ToolChains/Mentor/Mentor.py @@ -6,7 +6,7 @@ # Authors: Patrick Lehmann # Martin Zabel # -# Python Class: Mentor specific classes +# Python Class: Mentor specific classes # # Description: # ------------------------------------ @@ -69,92 +69,4 @@ class Configuration(BaseConfiguration): def _GetDefaultInstallationDirectory(self): path = self._TestDefaultInstallPath({"Windows": "Mentor", "Linux": "Mentor"}) if path is None: return super()._GetDefaultInstallationDirectory() - return str(path) - - - # - # - # def manualConfigureForWindows(self) : - # # Ask for installed Mentor Graphic tools - # isMentor = input('Is a Mentor Graphics tool installed on your system? [Y/n/p]: ') - # isMentor = isMentor if isMentor != "" else "Y" - # if (isMentor in ['p', 'P']) : - # pass - # elif (isMentor in ['n', 'N']) : - # self.pocConfig['Mentor'] = OrderedDict() - # elif (isMentor in ['y', 'Y']) : - # mentorDirectory = input('Mentor Graphics installation directory [C:\Mentor]: ') - # print() - # - # mentorDirectory = mentorDirectory if mentorDirectory != "" else "C:\Altera" - # QuartusVersion = QuartusVersion if QuartusVersion != "" else "15.0" - # - # mentorDirectoryPath = Path(mentorDirectory) - # - # if not mentorDirectoryPath.exists() : raise BaseException( - # "Mentor Graphics installation directory '%s' does not exist." % mentorDirectory) - # - # self.pocConfig['Mentor']['InstallationDirectory'] = mentorDirectoryPath.as_posix() - # - # # Ask for installed Mentor QuestaSIM - # isQuestaSim = input('Is Mentor QuestaSIM installed on your system? [Y/n/p]: ') - # isQuestaSim = isQuestaSim if isQuestaSim != "" else "Y" - # if (isQuestaSim in ['p', 'P']) : - # pass - # elif (isQuestaSim in ['n', 'N']) : - # self.pocConfig['Mentor.QuestaSIM'] = OrderedDict() - # elif (isQuestaSim in ['y', 'Y']) : - # QuestaSimDirectory = input( - # 'QuestaSIM installation directory [{0}\QuestaSim64\\10.2c]: '.format(str(mentorDirectory))) - # QuestaSimVersion = input('QuestaSIM version number [10.4c]: ') - # print() - # - # QuestaSimDirectory = QuestaSimDirectory if QuestaSimDirectory != "" else str( - # mentorDirectory) + "\QuestaSim64\\10.4c" - # QuestaSimVersion = QuestaSimVersion if QuestaSimVersion != "" else "10.4c" - # - # QuestaSimDirectoryPath = Path(QuestaSimDirectory) - # QuestaSimExecutablePath = QuestaSimDirectoryPath / "win64" / "vsim.exe" - # - # if not QuestaSimDirectoryPath.exists() : raise ConfigurationException( - # "QuestaSIM installation directory '%s' does not exist." % QuestaSimDirectory) - # if not QuestaSimExecutablePath.exists() : raise ConfigurationException("QuestaSIM is not installed.") - # - # self.pocConfig['Mentor']['InstallationDirectory'] = MentorDirectoryPath.as_posix() - # - # self.pocConfig['Mentor.QuestaSIM']['Version'] = QuestaSimVersion - # self.pocConfig['Mentor.QuestaSIM']['InstallationDirectory'] = QuestaSimDirectoryPath.as_posix() - # self.pocConfig['Mentor.QuestaSIM']['BinaryDirectory'] = '${InstallationDirectory}/win64' - # else : - # raise ConfigurationException("unknown option") - # else : - # raise ConfigurationException("unknown option") - # - # def manualConfigureForLinux(self) : - # # Ask for installed Mentor QuestaSIM - # isQuestaSim = input('Is mentor QuestaSIM installed on your system? [Y/n/p]: ') - # isQuestaSim = isQuestaSim if isQuestaSim != "" else "Y" - # if (isQuestaSim in ['p', 'P']) : - # pass - # elif (isQuestaSim in ['n', 'N']) : - # self.pocConfig['Mentor.QuestaSIM'] = OrderedDict() - # elif (isQuestaSim in ['y', 'Y']) : - # QuestaSimDirectory = input('QuestaSIM installation directory [/opt/QuestaSim/10.2c]: ') - # QuestaSimVersion = input('QuestaSIM version number [10.2c]: ') - # print() - # - # QuestaSimDirectory = QuestaSimDirectory if QuestaSimDirectory != "" else "/opt/QuestaSim/10.2c" - # QuestaSimVersion = QuestaSimVersion if QuestaSimVersion != "" else "10.2c" - # - # QuestaSimDirectoryPath = Path(QuestaSimDirectory) - # QuestaSimExecutablePath = QuestaSimDirectoryPath / "bin" / "vsim" - # - # if not QuestaSimDirectoryPath.exists() : raise ConfigurationException( - # "QuestaSIM installation directory '%s' does not exist." % QuestaSimDirectory) - # if not QuestaSimExecutablePath.exists() : raise ConfigurationException("QuestaSIM is not installed.") - # - # self.pocConfig['Mentor.QuestaSIM']['Version'] = QuestaSimVersion - # self.pocConfig['Mentor.QuestaSIM']['InstallationDirectory'] = QuestaSimDirectoryPath.as_posix() - # self.pocConfig['Mentor.QuestaSIM']['BinaryDirectory'] = '${InstallationDirectory}/bin' - # else : - # raise ConfigurationException("unknown option") + return path.as_posix() diff --git a/py/ToolChains/Mentor/QuestaSim.py b/py/ToolChains/Mentor/QuestaSim.py index 4a23a7ab..9786324a 100644 --- a/py/ToolChains/Mentor/QuestaSim.py +++ b/py/ToolChains/Mentor/QuestaSim.py @@ -41,20 +41,20 @@ Exit.printThisIsNoExecutableFile("PoC Library - Python Module ToolChains.Mentor.QuestaSim") -from subprocess import check_output -from textwrap import dedent +from subprocess import check_output +from textwrap import dedent from lib.Functions import CallByRefParam from Base.Exceptions import PlatformNotSupportedException -from Base.Logging import LogEntry, Severity +from Base.Logging import LogEntry, Severity from Base.Configuration import Configuration as BaseConfiguration, ConfigurationException -from Base.Simulator import SimulationResult, PoCSimulationResultFilter +from Base.Simulator import SimulationResult, PoCSimulationResultFilter from Base.Executable import Executable from Base.Executable import ExecutableArgument, ShortFlagArgument, ShortTupleArgument, PathArgument, StringArgument, CommandLineArgumentList -from ToolChains.Mentor.Mentor import MentorException +from ToolChains.Mentor.Mentor import MentorException -class QuestaException(MentorException): +class QuestaSimException(MentorException): pass @@ -118,44 +118,51 @@ def RunPostConfigurationTasks(self): vsimPath = self._host.Directories.Root / precompiledDirectory / vSimSimulatorFiles modelsimIniPath = vsimPath / "modelsim.ini" if not modelsimIniPath.exists(): - if not vsimPath.exists(): vsimPath.mkdir(parents=True) + if not vsimPath.exists(): + try: + vsimPath.mkdir(parents=True) + except OSError as ex: + raise ConfigurationException("Error while creating '{0!s}'.".format(vsimPath)) from ex + with modelsimIniPath.open('w') as fileHandle: fileContent = dedent("""\ [Library] others = $MODEL_TECH/../modelsim.ini - osvvm = osvvm """) fileHandle.write(fileContent) + class QuestaSimMixIn: - def __init__(self, platform, binaryDirectoryPath, version, logger=None): + def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): self._platform = platform - self._binaryDirectoryPath = binaryDirectoryPath - self._version = version - self._logger = logger + self._dryrun = dryrun + self._binaryDirectoryPath = binaryDirectoryPath + self._version = version + self._Logger = logger + class QuestaSim(QuestaSimMixIn): - def __init__(self, platform, binaryDirectoryPath, version, logger=None): - QuestaSimMixIn.__init__(self, platform, binaryDirectoryPath, version, logger) + def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): + QuestaSimMixIn.__init__(self, platform, dryrun, binaryDirectoryPath, version, logger) def GetVHDLCompiler(self): - return QuestaVHDLCompiler(self._platform, self._binaryDirectoryPath, self._version, logger=self._logger) + return QuestaVHDLCompiler(self._platform, self._dryrun, self._binaryDirectoryPath, self._version, logger=self._Logger) def GetSimulator(self): - return QuestaSimulator(self._platform, self._binaryDirectoryPath, self._version, logger=self._logger) + return QuestaSimulator(self._platform, self._dryrun, self._binaryDirectoryPath, self._version, logger=self._Logger) def GetVHDLLibraryTool(self): - return QuestaVHDLLibraryTool(self._platform, self._binaryDirectoryPath, self._version, logger=self._logger) + return QuestaVHDLLibraryTool(self._platform, self._dryrun, self._binaryDirectoryPath, self._version, logger=self._Logger) class QuestaVHDLCompiler(Executable, QuestaSimMixIn): - def __init__(self, platform, binaryDirectoryPath, version, logger=None): - QuestaSimMixIn.__init__(self, platform, binaryDirectoryPath, version, logger) + def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): + QuestaSimMixIn.__init__(self, platform, dryrun, binaryDirectoryPath, version, logger) if (self._platform == "Windows"): executablePath = binaryDirectoryPath / "vcom.exe" elif (self._platform == "Linux"): executablePath = binaryDirectoryPath / "vcom" else: raise PlatformNotSupportedException(self._platform) - super().__init__(platform, executablePath, logger=logger) + super().__init__(platform, dryrun, executablePath, logger=logger) self.Parameters[self.Executable] = executablePath @@ -224,12 +231,16 @@ class ArgSourceFile(metaclass=PathArgument): def Compile(self): parameterList = self.Parameters.ToArgumentList() - self._LogVerbose("command: {0}".format(" ".join(parameterList))) + self.LogVerbose("command: {0}".format(" ".join(parameterList))) + + if (self._dryrun): + self.LogDryRun("Start process: {0}".format(" ".join(parameterList))) + return try: self.StartProcess(parameterList) except Exception as ex: - raise QuestaException("Failed to launch vcom run.") from ex + raise QuestaSimException("Failed to launch vcom run.") from ex self._hasOutput = False self._hasWarnings = False @@ -238,34 +249,34 @@ def Compile(self): iterator = iter(QuestaVComFilter(self.GetReader())) line = next(iterator) - line.IndentBy(2) + line.IndentBy(self.Logger.BaseIndent + 1) self._hasOutput = True - self._LogNormal(" vcom messages for '{0}'".format(self.Parameters[self.ArgSourceFile])) - self._LogNormal(" " + ("-" * 76)) - self._Log(line) + self.LogNormal(" vcom messages for '{0}'".format(self.Parameters[self.ArgSourceFile])) + self.LogNormal(" " + ("-" * (78 - self.Logger.BaseIndent*2))) + self.Log(line) while True: self._hasWarnings |= (line.Severity is Severity.Warning) self._hasErrors |= (line.Severity is Severity.Error) line = next(iterator) - line.IndentBy(2) - self._Log(line) + line.IndentBy(self.Logger.BaseIndent + 1) + self.Log(line) except StopIteration: pass finally: if self._hasOutput: - self._LogNormal(" " + ("-" * 76)) + self.LogNormal(" " + ("-" * (78 - self.Logger.BaseIndent*2))) class QuestaSimulator(Executable, QuestaSimMixIn): - def __init__(self, platform, binaryDirectoryPath, version, logger=None): - QuestaSimMixIn.__init__(self, platform, binaryDirectoryPath, version, logger) + def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): + QuestaSimMixIn.__init__(self, platform, dryrun, binaryDirectoryPath, version, logger) if (self._platform == "Windows"): executablePath = binaryDirectoryPath / "vsim.exe" elif (self._platform == "Linux"): executablePath = binaryDirectoryPath / "vsim" else: raise PlatformNotSupportedException(self._platform) - super().__init__(platform, executablePath, logger=logger) + super().__init__(platform, dryrun, executablePath, logger=logger) self.Parameters[self.Executable] = executablePath @@ -354,12 +365,12 @@ class SwitchTopLevel(metaclass=StringArgument): def Simulate(self): parameterList = self.Parameters.ToArgumentList() - self._LogVerbose("command: {0}".format(" ".join(parameterList))) + self.LogVerbose("command: {0}".format(" ".join(parameterList))) try: self.StartProcess(parameterList) except Exception as ex: - raise QuestaException("Failed to launch vsim run.") from ex + raise QuestaSimException("Failed to launch vsim run.") from ex self._hasOutput = False self._hasWarnings = False @@ -369,36 +380,36 @@ def Simulate(self): iterator = iter(PoCSimulationResultFilter(QuestaVSimFilter(self.GetReader()), simulationResult)) line = next(iterator) - line.IndentBy(2) + line.IndentBy(self.Logger.BaseIndent + 1) self._hasOutput = True - self._LogNormal(" vsim messages for '{0}'".format(self.Parameters[self.SwitchTopLevel])) - self._LogNormal(" " + ("-" * 76)) - self._Log(line) + self.LogNormal(" vsim messages for '{0}'".format(self.Parameters[self.SwitchTopLevel])) + self.LogNormal(" " + ("-" * (78 - self.Logger.BaseIndent*2))) + self.Log(line) while True: self._hasWarnings |= (line.Severity is Severity.Warning) self._hasErrors |= (line.Severity is Severity.Error) line = next(iterator) - line.IndentBy(2) - self._Log(line) + line.IndentBy(self.Logger.BaseIndent + 1) + self.Log(line) except StopIteration: pass finally: if self._hasOutput: - self._LogNormal(" " + ("-" * 76)) + self.LogNormal(" " + ("-" * (78 - self.Logger.BaseIndent*2))) return simulationResult.value class QuestaVHDLLibraryTool(Executable, QuestaSimMixIn): - def __init__(self, platform, binaryDirectoryPath, version, logger=None): - QuestaSimMixIn.__init__(self, platform, binaryDirectoryPath, version, logger) + def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): + QuestaSimMixIn.__init__(self, platform, dryrun, binaryDirectoryPath, version, logger) if (self._platform == "Windows"): executablePath = binaryDirectoryPath / "vlib.exe" elif (self._platform == "Linux"): executablePath = binaryDirectoryPath / "vlib" else: raise PlatformNotSupportedException(self._platform) - super().__init__(platform, executablePath, logger=logger) + super().__init__(platform, dryrun, executablePath, logger=logger) self.Parameters[self.Executable] = executablePath @@ -424,12 +435,12 @@ class SwitchLibraryName(metaclass=StringArgument): pass def CreateLibrary(self): parameterList = self.Parameters.ToArgumentList() - self._LogVerbose("command: {0}".format(" ".join(parameterList))) + self.LogVerbose("command: {0}".format(" ".join(parameterList))) try: self.StartProcess(parameterList) except Exception as ex: - raise QuestaException("Failed to launch vlib run.") from ex + raise QuestaSimException("Failed to launch vlib run.") from ex self._hasOutput = False self._hasWarnings = False @@ -438,25 +449,25 @@ def CreateLibrary(self): iterator = iter(QuestaVLibFilter(self.GetReader())) line = next(iterator) - line.IndentBy(2) + line.IndentBy(self.Logger.BaseIndent + 1) self._hasOutput = True - self._LogNormal(" vlib messages for '{0}'".format(self.Parameters[self.SwitchLibraryName])) - self._LogNormal(" " + ("-" * 76)) - self._Log(line) + self.LogNormal(" vlib messages for '{0}'".format(self.Parameters[self.SwitchLibraryName])) + self.LogNormal(" " + ("-" * (78 - self.Logger.BaseIndent*2))) + self.Log(line) while True: self._hasWarnings |= (line.Severity is Severity.Warning) self._hasErrors |= (line.Severity is Severity.Error) line = next(iterator) - line.IndentBy(2) - self._Log(line) + line.IndentBy(self.Logger.BaseIndent + 1) + self.Log(line) except StopIteration: pass finally: if self._hasOutput: - self._LogNormal(" " + ("-" * 76)) + self.LogNormal(" " + ("-" * (78 - self.Logger.BaseIndent*2))) def QuestaVComFilter(gen): diff --git a/py/ToolChains/Mentor/__init__.py b/py/ToolChains/Mentor/__init__.py index e7bdd2cf..df2e8cb8 100644 --- a/py/ToolChains/Mentor/__init__.py +++ b/py/ToolChains/Mentor/__init__.py @@ -3,7 +3,7 @@ # kate: tab-width 2; replace-tabs off; indent-width 2; # # ============================================================================== -# Authors: Patrick Lehmann +# Authors: Patrick Lehmann # # Python Sub Module: TODO: # diff --git a/py/ToolChains/PoC.py b/py/ToolChains/PoC.py index 14c29e18..5ccc2a96 100644 --- a/py/ToolChains/PoC.py +++ b/py/ToolChains/PoC.py @@ -5,6 +5,7 @@ # ============================================================================== # Authors: Patrick Lehmann # Martin Zabel +# Thomas B. Preusser # # Python Class: PoC specific classes # @@ -43,7 +44,7 @@ from os import environ from pathlib import Path -from subprocess import check_output, CalledProcessError +from subprocess import check_output, check_call, CalledProcessError from Base.Configuration import Configuration as BaseConfiguration @@ -54,7 +55,7 @@ class Configuration(BaseConfiguration): _template = { "ALL": { "INSTALL.PoC": { - "Version": "0.0.0", + "Version": "1.0.0", "InstallationDirectory": None }, "SOLUTION.Solutions": {} @@ -63,39 +64,39 @@ class Configuration(BaseConfiguration): def ConfigureForAll(self): try: - latestTagHash = check_output(["git", "rev-list", "--tags", "--max-count=1"], universal_newlines=True) - latestTagName = check_output(["git", "describe", "--tags", latestTagHash[:-1]], universal_newlines=True) - latestTagName = latestTagName[:-1] - self._host._LogNormal(" PoC version: {0} (found in git)".format(latestTagName)) + latestTagHash = check_output(["git", "rev-list", "--tags", "--max-count=1"], universal_newlines=True).strip() + latestTagName = check_output(["git", "describe", "--tags", latestTagHash], universal_newlines=True).strip() + latestTagName = latestTagName + self._host.LogNormal(" PoC version: {0} (found in git)".format(latestTagName)) self._host.PoCConfig['INSTALL.PoC']['Version'] = latestTagName except CalledProcessError: print("WARNING: Can't get version information from latest git tag.") pocVersion = self._template['ALL']['INSTALL.PoC']['Version'] - self._host._LogNormal(" PoC version: {0} (found in default configuration)".format(pocVersion)) + self._host.LogNormal(" PoC version: {0} (found in default configuration)".format(pocVersion)) self._host.PoCConfig['INSTALL.PoC']['Version'] = pocVersion pocInstallationDirectory = Path(environ.get('PoCRootDirectory')) - self._host._LogNormal(" Installation directory: {0!s} (found in environment variable)".format(pocInstallationDirectory)) + self._host.LogNormal(" Installation directory: {0!s} (found in environment variable)".format(pocInstallationDirectory)) self._host.PoCConfig['INSTALL.PoC']['InstallationDirectory'] = pocInstallationDirectory.as_posix() def __CheckForGit(self): try: - check_output(["git", "--version"], universal_newlines=True) + check_call(["git", "--version"]) return True except OSError: return False def __IsUnderGitControl(self): try: - response = check_output(["git", "rev-parse", "--is-inside-work-tree"], universal_newlines=True) - return (response[:-1] == "true") + response = check_output(["git", "rev-parse", "--is-inside-work-tree"], universal_newlines=True).strip() + return (response == "true") except OSError: return False def __GetCurrentBranchName(self): try: - response = check_output(["git", "rev-parse", "--abbrev-ref", "HEAD"], universal_newlines=True) - return response[:-1] + response = check_output(["git", "rev-parse", "--abbrev-ref", "HEAD"], universal_newlines=True).strip() + return response except OSError: return False diff --git a/py/ToolChains/Synopsys/Synopsys.py b/py/ToolChains/Synopsys/Synopsys.py index d848a0a9..a95863b2 100644 --- a/py/ToolChains/Synopsys/Synopsys.py +++ b/py/ToolChains/Synopsys/Synopsys.py @@ -71,7 +71,7 @@ def _GetDefaultInstallationDirectory(self): # if (synopsys is not None): # return Path(synopsys).parent.parent - return str(self._TestDefaultInstallPath({"Windows": "Synopsys", "Linux": "Synopsys"})) + return self._TestDefaultInstallPath({"Windows": "Synopsys", "Linux": "Synopsys"}).as_posix() class SynopsysDesignConstraintFile(ConstraintFile): diff --git a/py/ToolChains/Xilinx/ISE.py b/py/ToolChains/Xilinx/ISE.py index b830849b..dbf107b9 100644 --- a/py/ToolChains/Xilinx/ISE.py +++ b/py/ToolChains/Xilinx/ISE.py @@ -59,9 +59,9 @@ class ISEException(XilinxException): class Configuration(BaseConfiguration): - _vendor = "Xilinx" - _toolName = "Xilinx ISE" - _section = "INSTALL.Xilinx.ISE" + _vendor = "Xilinx" + _toolName = "Xilinx ISE" + _section = "INSTALL.Xilinx.ISE" _template = { "Windows": { _section: { @@ -112,62 +112,39 @@ def __CheckISEVersion(self, binPath): class ISEMixIn: - def __init__(self, platform, binaryDirectoryPath, version, logger=None): + def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): self._platform = platform - self._binaryDirectoryPath = binaryDirectoryPath - self._version = version - self._logger = logger + self._dryrun = dryrun + self._binaryDirectoryPath = binaryDirectoryPath + self._version = version + self._Logger = logger class ISE(ISEMixIn): - def __init__(self, platform, binaryDirectoryPath, version, logger=None): - ISEMixIn.__init__(self, platform, binaryDirectoryPath, version, logger) - + def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): + ISEMixIn.__init__(self, platform, dryrun, binaryDirectoryPath, version, logger) + def GetVHDLCompiler(self): raise NotImplementedError("ISE.GetVHDLCompiler") - # return ISEVHDLCompiler(self._platform, self._binaryDirectoryPath, self._version, logger=self.__logger) + # return ISEVHDLCompiler(self._platform, self._dryrun, self._binaryDirectoryPath, self._version, logger=self._Logger) def GetFuse(self): - return Fuse(self._platform, self._binaryDirectoryPath, self._version, logger=self._logger) + return Fuse(self._platform, self._dryrun, self._binaryDirectoryPath, self._version, logger=self._Logger) def GetXst(self): - return Xst(self._platform, self._binaryDirectoryPath, self._version, logger=self._logger) + return Xst(self._platform, self._dryrun, self._binaryDirectoryPath, self._version, logger=self._Logger) def GetCoreGenerator(self): - return CoreGenerator(self._platform, self._binaryDirectoryPath, self._version, logger=self._logger) + return CoreGenerator(self._platform, self._dryrun, self._binaryDirectoryPath, self._version, logger=self._Logger) -# class ISEVHDLCompiler(Executable, ISESimulatorExecutable): -# def __init__(self, platform, binaryDirectoryPath, version, defaultParameters=[], logger=None): -# ISESimulatorExecutable.__init__(self, platform, binaryDirectoryPath, version, logger=logger) -# -# if (self._platform == "Windows"): executablePath = binaryDirectoryPath / "vhcomp.exe" -# elif (self._platform == "Linux"): executablePath = binaryDirectoryPath / "vhcomp" -# else: raise PlatformNotSupportedException(self._platform) -# super().__init__(platform, executablePath, defaultParameters, logger=logger) -# -# def Compile(self, vhdlFile): -# parameterList = self.Parameters.ToArgumentList() -# -# self._LogVerbose("command: {0}".format(" ".join(parameterList))) -# - # _indent = " " - # print(_indent + "vhcomp messages for '{0}.{1}'".format("??????")) # self.VHDLLibrary, topLevel)) - # print(_indent + "-" * 80) - # try: - # self.StartProcess(parameterList) - # for line in self.GetReader(): - # print(_indent + line) - # except Exception as ex: - # raise ex # SimulatorException() from ex - # print(_indent + "-" * 80) class Fuse(Executable, ISEMixIn): - def __init__(self, platform, binaryDirectoryPath, version, logger=None): - ISEMixIn.__init__(self, platform, binaryDirectoryPath, version, logger=logger) + def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): + ISEMixIn.__init__(self, platform, dryrun, binaryDirectoryPath, version, logger=logger) if (platform == "Windows"): executablePath = binaryDirectoryPath / "fuse.exe" elif (platform == "Linux"): executablePath = binaryDirectoryPath / "fuse" - else: raise PlatformNotSupportedException(self._platform) - super().__init__(platform, executablePath, logger=logger) + else: raise PlatformNotSupportedException(self._platform) + super().__init__(platform, dryrun, executablePath, logger=logger) self.Parameters[self.Executable] = executablePath @@ -220,48 +197,52 @@ class ArgTopLevel(metaclass=StringArgument): pass def Link(self): parameterList = self.Parameters.ToArgumentList() - self._LogVerbose("command: {0}".format(" ".join(parameterList))) + self.LogVerbose("command: {0}".format(" ".join(parameterList))) + + if (self._dryrun): + self.LogDryRun("Start process: {0}".format(" ".join(parameterList))) + return try: self.StartProcess(parameterList) except Exception as ex: raise ISEException("Failed to launch fuse.") from ex - self._hasOutput = False + self._hasOutput = False self._hasWarnings = False - self._hasErrors = False + self._hasErrors = False try: iterator = iter(FuseFilter(self.GetReader())) line = next(iterator) self._hasOutput = True - self._LogNormal(" fuse messages for '{0}'".format(self.Parameters[self.SwitchProjectFile])) - self._LogNormal(" " + ("-" * 76)) + self.LogNormal(" fuse messages for '{0}'".format(self.Parameters[self.SwitchProjectFile])) + self.LogNormal(" " + ("-" * (78 - self.Logger.BaseIndent*2))) while True: self._hasWarnings |= (line.Severity is Severity.Warning) self._hasErrors |= (line.Severity is Severity.Error) - line.IndentBy(2) - self._Log(line) + line.IndentBy(self.Logger.BaseIndent + 1) + self.Log(line) line = next(iterator) except StopIteration: pass finally: if self._hasOutput: - self._LogNormal(" " + ("-" * 76)) + self.LogNormal(" " + ("-" * (78 - self.Logger.BaseIndent*2))) class ISESimulator(Executable): - def __init__(self, executablePath, logger=None): - super().__init__("", executablePath, logger=logger) + def __init__(self, platform, dryrun, executablePath, logger=None): + super().__init__(platform, dryrun, executablePath, logger=logger) self.Parameters[self.Executable] = executablePath - self._hasOutput = False + self._hasOutput = False self._hasWarnings = False - self._hasErrors = False + self._hasErrors = False @property def HasWarnings(self): @@ -295,55 +276,59 @@ class SwitchWaveformFile(metaclass=ShortTupleArgument): def Simulate(self): parameterList = self.Parameters.ToArgumentList() - self._LogVerbose("command: {0}".format(" ".join(parameterList))) + self.LogVerbose("command: {0}".format(" ".join(parameterList))) + + if (self._dryrun): + self.LogDryRun("Start process: {0}".format(" ".join(parameterList))) + return try: self.StartProcess(parameterList) except Exception as ex: raise ISEException("Failed to launch isim.") from ex - self._hasOutput = False + self._hasOutput = False self._hasWarnings = False - self._hasErrors = False + self._hasErrors = False simulationResult = CallByRefParam(SimulationResult.Error) try: iterator = iter(PoCSimulationResultFilter(SimulatorFilter(self.GetReader()), simulationResult)) line = next(iterator) self._hasOutput = True - self._LogNormal(" isim messages for '{0}'".format(self.Parameters[self.Executable])) - self._LogNormal(" " + ("-" * 76)) + self.LogNormal(" isim messages for '{0}'".format(self.Parameters[self.Executable])) + self.LogNormal(" " + ("-" * (78 - self.Logger.BaseIndent*2))) while True: self._hasWarnings |= (line.Severity is Severity.Warning) self._hasErrors |= (line.Severity is Severity.Error) - line.IndentBy(2) - self._Log(line) + line.IndentBy(self.Logger.BaseIndent + 1) + self.Log(line) line = next(iterator) except StopIteration: pass finally: if self._hasOutput: - self._LogNormal(" " + ("-" * 76)) + self.LogNormal(" " + ("-" * (78 - self.Logger.BaseIndent*2))) return simulationResult.value class Xst(Executable, ISEMixIn): - def __init__(self, platform, binaryDirectoryPath, version, logger=None): - ISEMixIn.__init__(self, platform, binaryDirectoryPath, version, logger=logger) + def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): + ISEMixIn.__init__(self, platform, dryrun, binaryDirectoryPath, version, logger=logger) if (platform == "Windows"): executablePath = binaryDirectoryPath / "xst.exe" elif (platform == "Linux"): executablePath = binaryDirectoryPath / "xst" else: raise PlatformNotSupportedException(platform) - Executable.__init__(self, platform, executablePath, logger=logger) + Executable.__init__(self, platform, dryrun, executablePath, logger=logger) self.Parameters[self.Executable] = executablePath - self._hasOutput = False + self._hasOutput = False self._hasWarnings = False - self._hasErrors = False + self._hasErrors = False @property def HasWarnings(self): @@ -374,52 +359,56 @@ class SwitchReportFile(metaclass=ShortTupleArgument): def Compile(self): parameterList = self.Parameters.ToArgumentList() - self._LogVerbose("command: {0}".format(" ".join(parameterList))) + self.LogVerbose("command: {0}".format(" ".join(parameterList))) + + if (self._dryrun): + self.LogDryRun("Start process: {0}".format(" ".join(parameterList))) + return try: self.StartProcess(parameterList) except Exception as ex: raise ISEException("Failed to launch xst.") from ex - self._hasOutput = False + self._hasOutput = False self._hasWarnings = False - self._hasErrors = False + self._hasErrors = False try: iterator = iter(XstFilter(self.GetReader())) line = next(iterator) self._hasOutput = True - self._LogNormal(" xst messages for '{0}'".format(self.Parameters[self.SwitchXstFile])) - self._LogNormal(" " + ("-" * 76)) + self.LogNormal(" xst messages for '{0}'".format(self.Parameters[self.SwitchXstFile])) + self.LogNormal(" " + ("-" * (78 - self.Logger.BaseIndent*2))) while True: self._hasWarnings |= (line.Severity is Severity.Warning) self._hasErrors |= (line.Severity is Severity.Error) - line.IndentBy(2) - self._Log(line) + line.IndentBy(self.Logger.BaseIndent + 1) + self.Log(line) line = next(iterator) except StopIteration: pass finally: if self._hasOutput: - self._LogNormal(" " + ("-" * 76)) + self.LogNormal(" " + ("-" * (78 - self.Logger.BaseIndent*2))) class CoreGenerator(Executable, ISEMixIn): - def __init__(self, platform, binaryDirectoryPath, version, logger=None): - ISEMixIn.__init__(self, platform, binaryDirectoryPath, version, logger=logger) + def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): + ISEMixIn.__init__(self, platform, dryrun, binaryDirectoryPath, version, logger=logger) if (platform == "Windows"): executablePath = binaryDirectoryPath / "coregen.exe" elif (platform == "Linux"): executablePath = binaryDirectoryPath / "coregen" else: raise PlatformNotSupportedException(platform) - Executable.__init__(self, platform, executablePath, logger=logger) + super().__init__(platform, dryrun, executablePath, logger=logger) self.Parameters[self.Executable] = executablePath - self._hasOutput = False + self._hasOutput = False self._hasWarnings = False - self._hasErrors = False + self._hasErrors = False @property def HasWarnings(self): @@ -449,37 +438,41 @@ class SwitchBatchFile(metaclass=ShortTupleArgument): def Generate(self): parameterList = self.Parameters.ToArgumentList() - self._LogVerbose("command: {0}".format(" ".join(parameterList))) + self.LogVerbose("command: {0}".format(" ".join(parameterList))) + + if (self._dryrun): + self.LogDryRun("Start process: {0}".format(" ".join(parameterList))) + return try: self.StartProcess(parameterList) except Exception as ex: raise ISEException("Failed to launch corgen.") from ex - self._hasOutput = False + self._hasOutput = False self._hasWarnings = False - self._hasErrors = False + self._hasErrors = False try: iterator = iter(CoreGeneratorFilter(self.GetReader())) line = next(iterator) self._hasOutput = True - self._LogNormal(" coregen messages for '{0}'".format(self.Parameters[self.SwitchProjectFile])) - self._LogNormal(" " + ("-" * 76)) + self.LogNormal(" coregen messages for '{0}'".format(self.Parameters[self.SwitchProjectFile])) + self.LogNormal(" " + ("-" * (78 - self.Logger.BaseIndent*2))) while True: - self._hasWarnings |= (line.Severity is Severity.Warning) - self._hasErrors |= (line.Severity is Severity.Error) + self._hasWarnings |= (line.Severity is Severity.Warning) + self._hasErrors |= (line.Severity is Severity.Error) - line.IndentBy(2) - self._Log(line) + line.IndentBy(self.Logger.BaseIndent + 1) + self.Log(line) line = next(iterator) except StopIteration: pass finally: if self._hasOutput: - self._LogNormal(" " + ("-" * 76)) + self.LogNormal(" " + ("-" * (78 - self.Logger.BaseIndent*2))) def VhCompFilter(gen): diff --git a/py/ToolChains/Xilinx/Vivado.py b/py/ToolChains/Xilinx/Vivado.py index a3b1d1d2..9714bb2b 100644 --- a/py/ToolChains/Xilinx/Vivado.py +++ b/py/ToolChains/Xilinx/Vivado.py @@ -65,14 +65,14 @@ class Configuration(BaseConfiguration): _template = { "Windows": { _section: { - "Version": "2016.1", + "Version": "2016.2", "InstallationDirectory": "${INSTALL.Xilinx:InstallationDirectory}/Vivado/${Version}", "BinaryDirectory": "${InstallationDirectory}/bin" } }, "Linux": { _section: { - "Version": "2016.1", + "Version": "2016.2", "InstallationDirectory": "${INSTALL.Xilinx:InstallationDirectory}/Vivado/${Version}", "BinaryDirectory": "${InstallationDirectory}/bin" } @@ -111,34 +111,35 @@ def __CheckVivadoVersion(self, binPath, version): class VivadoMixIn: - def __init__(self, platform, binaryDirectoryPath, version, logger=None): + def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): self._platform = platform - self._binaryDirectoryPath = binaryDirectoryPath - self._version = version - self._logger = logger + self._dryrun = dryrun + self._binaryDirectoryPath = binaryDirectoryPath + self._version = version + self._Logger = logger class Vivado(VivadoMixIn): - def __init__(self, platform, binaryDirectoryPath, version, logger=None): - VivadoMixIn.__init__(self, platform, binaryDirectoryPath, version, logger) + def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): + VivadoMixIn.__init__(self, platform, dryrun, binaryDirectoryPath, version, logger) def GetElaborator(self): - return XElab(self._platform, self._binaryDirectoryPath, self._version, logger=self._logger) + return XElab(self._platform, self._dryrun, self._binaryDirectoryPath, self._version, logger=self._Logger) def GetSimulator(self): - return XSim(self._platform, self._binaryDirectoryPath, self._version, logger=self._logger) + return XSim(self._platform, self._dryrun, self._binaryDirectoryPath, self._version, logger=self._Logger) def GetSynthesizer(self): - return Synth(self._platform, self._binaryDirectoryPath, self._version, logger=self._logger) + return Synth(self._platform, self._dryrun, self._binaryDirectoryPath, self._version, logger=self._Logger) class XElab(Executable, VivadoMixIn): - def __init__(self, platform, binaryDirectoryPath, version, logger=None): - VivadoMixIn.__init__(self, platform, binaryDirectoryPath, version, logger) + def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): + VivadoMixIn.__init__(self, platform, dryrun, binaryDirectoryPath, version, logger) if (self._platform == "Windows"): executablePath = binaryDirectoryPath / "xelab.bat" elif (self._platform == "Linux"): executablePath = binaryDirectoryPath / "xelab" else: raise PlatformNotSupportedException(self._platform) - super().__init__(platform, executablePath, logger=logger) + super().__init__(platform, dryrun, executablePath, logger=logger) self.Parameters[self.Executable] = executablePath @@ -218,7 +219,11 @@ class ArgTopLevel(metaclass=StringArgument): def Link(self): parameterList = self.Parameters.ToArgumentList() - self._LogVerbose("command: {0}".format(" ".join(parameterList))) + self.LogVerbose("command: {0}".format(" ".join(parameterList))) + + if (self._dryrun): + self.LogDryRun("Start process: {0}".format(" ".join(parameterList))) + return try: self.StartProcess(parameterList) @@ -233,15 +238,15 @@ def Link(self): line = next(iterator) self._hasOutput = True - self._LogNormal(" xelab messages for '{0}'".format(self.Parameters[self.SwitchProjectFile])) - self._LogNormal(" " + ("-" * 76)) + self.LogNormal(" xelab messages for '{0}'".format(self.Parameters[self.SwitchProjectFile])) + self.LogNormal(" " + ("-" * (78 - self.Logger.BaseIndent*2))) while True: self._hasWarnings |= (line.Severity is Severity.Warning) self._hasErrors |= (line.Severity is Severity.Error) - line.IndentBy(2) - self._Log(line) + line.IndentBy(self.Logger.BaseIndent + 1) + self.Log(line) line = next(iterator) except StopIteration: @@ -252,16 +257,16 @@ def Link(self): # raise GHDLException("Error while executing GHDL.") from ex finally: if self._hasOutput: - self._LogNormal(" " + ("-" * 76)) + self.LogNormal(" " + ("-" * (78 - self.Logger.BaseIndent*2))) class XSim(Executable, VivadoMixIn): - def __init__(self, platform, binaryDirectoryPath, version, logger=None): - VivadoMixIn.__init__(self, platform, binaryDirectoryPath, version, logger) + def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): + VivadoMixIn.__init__(self, platform, dryrun, binaryDirectoryPath, version, logger) if (self._platform == "Windows"): executablePath = binaryDirectoryPath / "xsim.bat" elif (self._platform == "Linux"): executablePath = binaryDirectoryPath / "xsim" else: raise PlatformNotSupportedException(self._platform) - super().__init__(platform, executablePath, logger=logger) + super().__init__(platform, dryrun, executablePath, logger=logger) self.Parameters[self.Executable] = executablePath @@ -310,7 +315,11 @@ class SwitchSnapshot(metaclass=StringArgument): def Simulate(self): parameterList = self.Parameters.ToArgumentList() - self._LogVerbose("command: {0}".format(" ".join(parameterList))) + self.LogVerbose("command: {0}".format(" ".join(parameterList))) + + if (self._dryrun): + self.LogDryRun("Start process: {0}".format(" ".join(parameterList))) + return try: self.StartProcess(parameterList) @@ -326,33 +335,33 @@ def Simulate(self): line = next(iterator) self._hasOutput = True - self._LogNormal(" xsim messages for '{0}'".format(self.Parameters[self.SwitchSnapshot])) - self._LogNormal(" " + ("-" * 76)) + self.LogNormal(" xsim messages for '{0}'".format(self.Parameters[self.SwitchSnapshot])) + self.LogNormal(" " + ("-" * (78 - self.Logger.BaseIndent*2))) while True: self._hasWarnings |= (line.Severity is Severity.Warning) self._hasErrors |= (line.Severity is Severity.Error) - line.IndentBy(2) - self._Log(line) + line.IndentBy(self.Logger.BaseIndent + 1) + self.Log(line) line = next(iterator) except StopIteration: pass finally: if self._hasOutput: - self._LogNormal(" " + ("-" * 76)) + self.LogNormal(" " + ("-" * (78 - self.Logger.BaseIndent*2))) return simulationResult.value class Synth(Executable, VivadoMixIn): - def __init__(self, platform, binaryDirectoryPath, version, logger=None): - VivadoMixIn.__init__(self, platform, binaryDirectoryPath, version, logger) + def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): + VivadoMixIn.__init__(self, platform, dryrun, binaryDirectoryPath, version, logger) if (self._platform == "Windows"): executablePath = binaryDirectoryPath / "vivado.bat" elif (self._platform == "Linux"): executablePath = binaryDirectoryPath / "vivado" else: raise PlatformNotSupportedException(self._platform) - super().__init__(platform, executablePath, logger=logger) + super().__init__(platform, dryrun, executablePath, logger=logger) self.Parameters[self.Executable] = executablePath @@ -393,7 +402,11 @@ class SwitchMode(metaclass=ShortTupleArgument): def Compile(self): parameterList = self.Parameters.ToArgumentList() - self._LogVerbose("command: {0}".format(" ".join(parameterList))) + self.LogVerbose("command: {0}".format(" ".join(parameterList))) + + if (self._dryrun): + self.LogDryRun("Start process: {0}".format(" ".join(parameterList))) + return try: self.StartProcess(parameterList) @@ -408,26 +421,26 @@ def Compile(self): line = next(iterator) self._hasOutput = True - self._LogNormal(" vivado messages for '{0}'".format(self.Parameters[self.SwitchSourceFile])) - self._LogNormal(" " + ("-" * 76)) + self.LogNormal(" vivado messages for '{0}'".format(self.Parameters[self.SwitchSourceFile])) + self.LogNormal(" " + ("-" * (78 - self.Logger.BaseIndent*2))) while True: self._hasWarnings |= (line.Severity is Severity.Warning) self._hasErrors |= (line.Severity is Severity.Error) - line.IndentBy(2) - self._Log(line) + line.IndentBy(self.Logger.BaseIndent + 1) + self.Log(line) line = next(iterator) except StopIteration: pass finally: if self._hasOutput: - self._LogNormal(" " + ("-" * 76)) + self.LogNormal(" " + ("-" * (78 - self.Logger.BaseIndent*2))) -def ElaborationFilter(gen): +def ElaborationFilter(gen): # mccabe:disable=MC0001 for line in gen: if line.startswith("Vivado Simulator "): continue diff --git a/py/ToolChains/Xilinx/Xilinx.py b/py/ToolChains/Xilinx/Xilinx.py index bfa45ffc..7a7edfa3 100644 --- a/py/ToolChains/Xilinx/Xilinx.py +++ b/py/ToolChains/Xilinx/Xilinx.py @@ -41,12 +41,12 @@ Exit.printThisIsNoExecutableFile("The PoC-Library - Python Module ToolChains.Xilinx.Xilinx") -from os import environ +from os import environ from pathlib import Path -from Base.Configuration import Configuration as BaseConfiguration -from Base.Project import FileTypes, VHDLVersion -from Base.ToolChain import ToolChainException +from Base.Configuration import Configuration as BaseConfiguration +from Base.Project import FileTypes, VHDLVersion +from Base.ToolChain import ToolChainException class XilinxException(ToolChainException): @@ -72,15 +72,15 @@ class Configuration(BaseConfiguration): def _GetDefaultInstallationDirectory(self): xilinx = environ.get("XILINX") if (xilinx is not None): - return str(Path(xilinx).parent.parent.parent) + return Path(xilinx).parent.parent.parent.as_posix() xilinx = environ.get("XILINX_VIVADO") if (xilinx is not None): - return str(Path(xilinx).parent.parent) + return Path(xilinx).parent.parent.as_posix() path = self._TestDefaultInstallPath({"Windows": "Xilinx", "Linux": "Xilinx"}) if path is None: return super()._GetDefaultInstallationDirectory() - return str(path) + return path.as_posix() class XilinxProjectExportMixIn: @@ -93,7 +93,7 @@ def _GenerateXilinxProjectFileContent(self, tool, vhdlVersion=VHDLVersion.VHDL93 if (not file.Path.exists()): raise XilinxException("Cannot add '{0!s}' to {1} project file.".format(file.Path, tool)) from FileNotFoundError(str(file.Path)) if file.FileType is FileTypes.VHDLSourceFile: # create one VHDL line for each VHDL file - if (vhdlVersion == VHDLVersion.VHDL2008): projectFileContent += "vhdl2008 {0} \"{1!s}\"\n".format(file.LibraryName, file.Path) + if (vhdlVersion is VHDLVersion.VHDL2008): projectFileContent += "vhdl2008 {0} \"{1!s}\"\n".format(file.LibraryName, file.Path) else: projectFileContent += "vhdl {0} \"{1!s}\"\n".format(file.LibraryName, file.Path) else: # verilog projectFileContent += "verilog work \"{0!s}\"\n".format(file.Path) @@ -102,6 +102,6 @@ def _GenerateXilinxProjectFileContent(self, tool, vhdlVersion=VHDLVersion.VHDL93 def _WriteXilinxProjectFile(self, projectFilePath, tool, vhdlVersion=VHDLVersion.VHDL93): projectFileContent = self._GenerateXilinxProjectFileContent(tool, vhdlVersion) - self._LogDebug("Writing {0} project file to '{1!s}'".format(tool, projectFilePath)) #self._LogDebug only available via late binding + self.LogDebug("Writing {0} project file to '{1!s}'".format(tool, projectFilePath)) #self.LogDebug only available via late binding with projectFilePath.open('w') as prjFileHandle: prjFileHandle.write(projectFileContent) diff --git a/py/ToolChains/__init__.py b/py/ToolChains/__init__.py index ec42bf61..2d8e78a8 100644 --- a/py/ToolChains/__init__.py +++ b/py/ToolChains/__init__.py @@ -40,30 +40,32 @@ Exit.printThisIsNoExecutableFile("The PoC-Library - Repository Service Tool") -from .PoC import Configuration as PoC_Configuration -from .Aldec.Aldec import Configuration as Aldec_Configuration -from .Aldec.ActiveHDL import Configuration as ActiveHDL_Configuration -from .Altera.Altera import Configuration as Altera_Configuration -from .Altera.Quartus import Configuration as Quartus_Configuration -from .Altera.ModelSim import Configuration as AlteraModelSim_Configuration -from .GHDL import Configuration as GHDL_Configuration -from .GTKWave import Configuration as GTKW_Configuration -from .Lattice.Lattice import Configuration as Lattice_Configuration -from .Lattice.Diamond import Configuration as Diamond_Configuration -from .Lattice.ActiveHDL import Configuration as LatticeActiveHDL_Configuration -# from .Lattice.Symplify import Configuration as LatticeSymplify_Configuration -from .Mentor.Mentor import Configuration as Mentor_Configuration -from .Mentor.QuestaSim import Configuration as Questa_Configuration -# from .Mentor.PrecisionRTL import Configuration as PrecisionRTL_Configuration -# from .Synopsys.Synopsys import Configuration as Synopsys_Configuration -# from .Synopsys.Symplify import Configuration as Symplify_Configuration -from .Xilinx.Xilinx import Configuration as Xilinx_Configuration -from .Xilinx.ISE import Configuration as ISE_Configuration -from .Xilinx.Vivado import Configuration as Vivado_Configuration +from .PoC import Configuration as PoC_Configuration +from .Git import Configuration as Git_Configuration +from .Aldec.Aldec import Configuration as Aldec_Configuration +from .Aldec.ActiveHDL import Configuration as ActiveHDL_Configuration +from .Altera.Altera import Configuration as Altera_Configuration +from .Altera.Quartus import Configuration as Quartus_Configuration +from .Altera.ModelSim import Configuration as AlteraModelSim_Configuration +from .GHDL import Configuration as GHDL_Configuration +from .GTKWave import Configuration as GTKW_Configuration +from .Lattice.Lattice import Configuration as Lattice_Configuration +from .Lattice.Diamond import Configuration as Diamond_Configuration +from .Lattice.ActiveHDL import Configuration as LatticeActiveHDL_Configuration +# from .Lattice.Symplify import Configuration as LatticeSymplify_Configuration +from .Mentor.Mentor import Configuration as Mentor_Configuration +from .Mentor.QuestaSim import Configuration as Questa_Configuration +# from .Mentor.PrecisionRTL import Configuration as PrecisionRTL_Configuration +# from .Synopsys.Synopsys import Configuration as Synopsys_Configuration +# from .Synopsys.Symplify import Configuration as Symplify_Configuration +from .Xilinx.Xilinx import Configuration as Xilinx_Configuration +from .Xilinx.ISE import Configuration as ISE_Configuration +from .Xilinx.Vivado import Configuration as Vivado_Configuration Configurations = [ PoC_Configuration, + Git_Configuration, # Aldec products Aldec_Configuration, ActiveHDL_Configuration, diff --git a/py/Wrapper.ps1 b/py/Wrapper.ps1 deleted file mode 100644 index 8d647d37..00000000 --- a/py/Wrapper.ps1 +++ /dev/null @@ -1,266 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# -# ============================================================================== -# Authors: Patrick Lehmann -# -# PowerShell Script: Wrapper Script to execute a given Python script -# -# Description: -# ------------------------------------ -# This is a bash script (callable) which: -# - checks for a minimum installed Python version -# - loads vendor environments before executing the Python programs -# -# License: -# ============================================================================== -# Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# ============================================================================== - -# script settings -$PoC_ExitCode = 0 -$PoC_PythonScriptDir = "py" -$PoC_HookDirectory = "tools\Hooks" - -$PoC_WorkingDir = Get-Location - -# set default values -$PyWrapper_Debug = $false -$PyWrapper_LoadEnv = @{ - "Aldec" = @{ - "PreHookFile" = "Aldec.pre.ps1"; - "PostHookFile" = "Aldec.post.ps1"; - "Tools" = @{ - "ActiveHDL" = @{"Load" = $false; "Commands" = @("asim"); "PreHookFile" = "Aldec.ActiveHDL.pre.ps1"; "PostHookFile" = "Aldec.ActiveHDL.post.ps1"}; - "RevieraPRO" = @{"Load" = $false; "Commands" = @("rpro"); "PreHookFile" = "Aldec.RevieraPRO.pre.ps1"; "PostHookFile" = "Aldec.RevieraPRO.post.ps1"} - }}; - "Altera" = @{ - "PreHookFile" = "Altera.pre.ps1"; - "PostHookFile" = "Altera.post.ps1"; - "Tools" = @{ - "Quartus" = @{"Load" = $false; "Commands" = @("quartus"); "PreHookFile" = "Altera.Quartus.pre.ps1"; "PostHookFile" = "Altera.Quartus.post.ps1"} - # "ModelSim" = @{"Load" = $false; "Commands" = @("vsim"); "PreHookFile" = "Altera.ModelSim.pre.ps1"} - }}; - "GHDL_GTKWave" = @{ - "PreHookFile" = ""; - "PostHookFile" = ""; - "Tools" = @{ - "GHDL" = @{"Load" = $false; "Commands" = @("ghdl"); "PreHookFile" = "GHDL.pre.ps1"; "PostHookFile" = "GHDL.post.ps1"}; - "GTKWave" = @{"Load" = $false; "Commands" = @("ghdl"); "PreHookFile" = "GTKWave.pre.ps1"; "PostHookFile" = "GTKWave.post.ps1"} - }}; - "Lattice" = @{ - "PreHookFile" = "Lattice.pre.ps1"; - "PostHookFile" = "Lattice.post.ps1"; - "Tools" = @{ - "Diamond" = @{"Load" = $false; "Commands" = @("lse"); "PreHookFile" = "Lattice.Diamond.pre.ps1"; "PostHookFile" = "Lattice.Diamond.post.ps1"}; - "ActiveHDL" = @{"Load" = $false; "Commands" = @("asim"); "PreHookFile" = "Lattice.ActiveHDL.pre.ps1"; "PostHookFile" = "Lattice.ActiveHDL.post.ps1"} - }}; - "Mentor" = @{ - "PreHookFile" = "Mentor.pre.ps1"; - "PostHookFile" = "Mentor.post.ps1"; - "Tools" = @{ - "PrecisionRTL" = @{"Load" = $false; "Commands" = @("prtl"); "PreHookFile" = "Mentor.PrecisionRTL.pre.ps1"; "PostHookFile" = "Mentor.PrecisionRTL.post.ps1"}; - "QuestaSim" = @{"Load" = $false; "Commands" = @("vsim", "qsim"); "PreHookFile" = "Mentor.QuestaSim.pre.ps1"; "PostHookFile" = "Mentor.QuestaSim.post.ps1"} - }}; - "Xilinx" = @{ - "PreHookFile" = "Xilinx.pre.ps1"; - "PostHookFile" = "Xilinx.post.ps1"; - "Tools" = @{ - "ISE" = @{"Load" = $false; "Commands" = @("isim", "xst", "coregen"); "PreHookFile" = "Xilinx.ISE.pre.ps1"; "PostHookFile" = "Xilinx.ISE.post.ps1"}; - "Vivado" = @{"Load" = $false; "Commands" = @("xsim", "synth"); "PreHookFile" = "Xilinx.Vivado.pre.ps1"; "PostHookFile" = "Xilinx.Vivado.post.ps1"} - }} -} - -# search parameters for specific options like '-D' to enable batch script debug mode -# TODO: restrict to first n=2? parameters -foreach ($param in $PyWrapper_Parameters) -{ if ($param -cmatch "^-\w*D\w*") - { $PyWrapper_Debug = $true - continue - } - $breakIt = $false - foreach ($VendorName in $PyWrapper_LoadEnv.Keys) - { foreach ($ToolName in $PyWrapper_LoadEnv[$VendorName]["Tools"].Keys) - { foreach ($Command in $PyWrapper_LoadEnv[$VendorName]["Tools"][$ToolName]["Commands"]) - { if ($param -ceq $Command) - { $PyWrapper_LoadEnv[$VendorName]["Tools"][$ToolName]["Load"] = $true - $breakIt = $true - break - } - } - if ($breakIt) { break } - } - if ($breakIt) { break } - } -} - -# publish PoC directories as environment variables -$env:PoCRootDirectory = $PoC_RootDir_AbsPath -$env:PoCWorkingDirectory = $PoC_WorkingDir - -if ($PyWrapper_Debug -eq $true ) { - Write-Host "This is the PoC Library script wrapper operating in debug mode." -ForegroundColor Yellow - Write-Host "" - Write-Host "Directories:" -ForegroundColor Yellow - Write-Host " Script root: $PyWrapper_ScriptDir" -ForegroundColor Yellow - Write-Host " PoC root: $PoC_RootDir_AbsPath" -ForegroundColor Yellow - Write-Host " working: $PoC_WorkingDir" -ForegroundColor Yellow - Write-Host "Script:" -ForegroundColor Yellow - Write-Host " Filename: $PyWrapper_Script" -ForegroundColor Yellow - Write-Host " Solution: $PyWrapper_Solution" -ForegroundColor Yellow - Write-Host " Parameters: $PyWrapper_Parameters" -ForegroundColor Yellow - Write-Host "Load Environment:" -ForegroundColor Yellow - Write-Host " Xilinx ISE: $(PyWrapper_LoadEnv["Xilinx"]["Tools"]["ISE"]["Load"])" -ForegroundColor Yellow - Write-Host " Xilinx VIVADO: $(PyWrapper_LoadEnv["Xilinx"]["Tools"]["Vivado"]["Load"])" -ForegroundColor Yellow - Write-Host "" -} - -# find suitable python version or abort execution -$Python_VersionTest = 'py.exe -3 -c "import sys; sys.exit(not (0x03050000 < sys.hexversion < 0x04000000))"' -Invoke-Expression $Python_VersionTest | Out-Null -if ($LastExitCode -eq 0) { - $Python_Interpreter = "py.exe" - $Python_Parameters = (, "-3") - if ($PyWrapper_Debug -eq $true) { Write-Host "PythonInterpreter: '$Python_Interpreter $Python_Parameters'" -ForegroundColor Yellow } -} else { - Write-Host "ERROR: No suitable Python interpreter found." -ForegroundColor Red - Write-Host "The script requires Python $PyWrapper_MinVersion." -ForegroundColor Yellow - $PoC_ExitCode = 1 -} - -# execute vendor and tool pre-hook files if present -foreach ($VendorName in $PyWrapper_LoadEnv.Keys) -{ foreach ($ToolName in $PyWrapper_LoadEnv[$VendorName]["Tools"].Keys) - { if ($PyWrapper_LoadEnv[$VendorName]["Tools"][$ToolName]["Load"]) - { # if exists, source the vendor pre-hook file - $VendorPreHookFile = $PoC_RootDir_AbsPath + "\" + $PoC_HookDirectory + "\" + $PyWrapper_LoadEnv[$VendorName]["PreHookFile"] - if (Test-Path $VendorPreHookFile -PathType Leaf) - { . ($VendorPreHookFile) } - # if exists, source the tool pre-hook file - $ToolPreHookFile = $PoC_RootDir_AbsPath + "\" + $PoC_HookDirectory + "\" + $PyWrapper_LoadEnv[$VendorName]["Tools"][$ToolName]["PreHookFile"] - if (Test-Path $ToolPreHookFile -PathType Leaf) - { . ($ToolPreHookFile) } - } - } -} - - -if (($PoC_ExitCode -eq 0) -and $PyWrapper_LoadEnv["Xilinx"]["Tools"]["ISE"]["Load"]) { - # load Xilinx ISE environment if not loaded before - if (-not (Test-Path env:XILINX)) { - $PoC_Command = "$Python_Interpreter $Python_Parameters $PoC_RootDir_AbsPath\$PoC_PythonScriptDir\PoC.py query Xilinx.ISE:SettingsFile" - if ($PyWrapper_Debug -eq $true) { Write-Host "Getting ISE settings file: command='$PoC_Command'" -ForegroundColor Yellow } - - # execute python script to receive ISE settings filename - $PoC_ISE_SettingsFile = Invoke-Expression $PoC_Command - if ($LastExitCode -eq 0) { - if ($PyWrapper_Debug -eq $true) { Write-Host "ISE settings file: '$PoC_ISE_SettingsFile'" -ForegroundColor Yellow } - if ($PoC_ISE_SettingsFile -eq "") { - Write-Host "ERROR: No Xilinx ISE installation found." -ForegroundColor Red - Write-Host "Run 'poc.ps1 --configure' to configure your Xilinx ISE installation." -ForegroundColor Red - $PoC_ExitCode = 1 - } elseif (-not (Test-Path $PoC_ISE_SettingsFile -PathType Leaf)) { - Write-Host "ERROR: Xilinx ISE is configured in PoC, but settings file '$PoC_ISE_SettingsFile' does not exist." -ForegroundColor Red - Write-Host "Run 'poc.ps1 --configure' to configure your Xilinx ISE installation." -ForegroundColor Red - $PoC_ExitCode = 1 - } elseif (($PoC_ISE_SettingsFile -like "*.bat") -or ($PoC_ISE_SettingsFile -like "*.cmd")) { - Write-Host "Loading Xilinx ISE environment '$PoC_ISE_SettingsFile'" -ForegroundColor Yellow - Import-Module PSCX - Invoke-BatchFile -path $PoC_ISE_SettingsFile - } else { - Write-Host "ERROR: Xilinx ISE is configured in PoC, but settings file format is not supported." -ForegroundColor Red - $PoC_ExitCode = 1 - } - } else { - Write-Host "ERROR: ExitCode for '$PoC_Command' was not zero. Aborting script execution" -ForegroundColor Red - Write-Host $PoC_ISE_SettingsFile -ForegroundColor Red - $PoC_ExitCode = 1 - } - } -} - -if (($PoC_ExitCode -eq 0) -and $PyWrapper_LoadEnv["Xilinx"]["Tools"]["Vivado"]["Load"]) { - # load Xilinx Vivado environment if not loaded before - if (-not (Test-Path env:XILINX_VIVADO)) { - $PoC_Command = "$Python_Interpreter $Python_Parameters $PoC_RootDir_AbsPath\$PoC_PythonScriptDir\PoC.py query Xilinx.Vivado:SettingsFile" - if ($PyWrapper_Debug -eq $true) { Write-Host "Getting Vivado settings file: command='$PoC_Command'" -ForegroundColor Yellow } - - # execute python script to receive Vivado settings filename - $PoC_Vivado_SettingsFile = Invoke-Expression $PoC_Command - if ($LastExitCode -eq 0) { - if ($PyWrapper_Debug -eq $true) { Write-Host "Vivado settings file: '$PoC_Vivado_SettingsFile'" -ForegroundColor Yellow } - if ($PoC_Vivado_SettingsFile -eq "") { - Write-Host "ERROR: No Xilinx Vivado installation found." -ForegroundColor Red - Write-Host "Run 'poc.ps1 --configure' to configure your Xilinx Vivado installation." -ForegroundColor Red - $PoC_ExitCode = 1 - } elseif (-not (Test-Path $PoC_Vivado_SettingsFile -PathType Leaf)) { - Write-Host "ERROR: Xilinx Vivado is configured in PoC, but settings file '$PoC_Vivado_SettingsFile' does not exist." -ForegroundColor Red - Write-Host "Run 'poc.ps1 --configure' to configure your Xilinx Vivado installation." -ForegroundColor Red - $PoC_ExitCode = 1 - } elseif (($PoC_Vivado_SettingsFile -like "*.bat") -or ($PoC_Vivado_SettingsFile -like "*.cmd")) { - Write-Host "Loading Xilinx Vivado environment '$PoC_Vivado_SettingsFile'" -ForegroundColor Yellow - Import-Module PSCX - Invoke-BatchFile -path $PoC_Vivado_SettingsFile - } else { - Write-Host "ERROR: Xilinx Vivado is configured in PoC, but settings file format is not supported." -ForegroundColor Red - $PoC_ExitCode = 1 - } - } else { - Write-Host "ERROR: ExitCode for '$PoC_Command' was not zero. Aborting script execution" -ForegroundColor Red - $PoC_ExitCode = 1 - } - } -} - -# execute script with appropriate Python interpreter and all given parameters -if ($PoC_ExitCode -eq 0) { - $Python_Script = "$PoC_RootDir_AbsPath\$PoC_PythonScriptDir\$PyWrapper_Script" - if ($PyWrapper_Solution -eq "") { - $Python_ScriptParameters = $PyWrapper_Parameters - } else { - $Python_ScriptParameters = "--sln=$PyWrapper_Solution " + $PyWrapper_Parameters - } - # execute script with appropriate Python interpreter and all given parameters - if ($PyWrapper_Debug -eq $true) { - Write-Host "launching: '$Python_Interpreter $Python_Parameters $Python_Script $Python_ScriptParameters'" -ForegroundColor Yellow - Write-Host "------------------------------------------------------------" -ForegroundColor Yellow - } - - # launching Python script - Invoke-Expression "$Python_Interpreter $Python_Parameters $Python_Script $Python_ScriptParameters" - $PoC_ExitCode = $LastExitCode -} - -# execute vendor and tool post-hook files if present -foreach ($VendorName in $PyWrapper_LoadEnv.Keys) -{ foreach ($ToolName in $PyWrapper_LoadEnv[$VendorName]["Tools"].Keys) - { if ($PyWrapper_LoadEnv[$VendorName]["Tools"][$ToolName]["Load"]) - { # if exists, source the vendor pre-hook file - $VendorPostHookFile = $PoC_RootDir_AbsPath + "\" + $PoC_HookDirectory + "\" + $PyWrapper_LoadEnv[$VendorName]["PostHookFile"] - if (Test-Path $VendorPostHookFile -PathType Leaf) - { . ($VendorPostHookFile) } - # if exists, source the tool pre-hook file - $ToolPostHookFile = $PoC_RootDir_AbsPath + "\" + $PoC_HookDirectory + "\" + $PyWrapper_LoadEnv[$VendorName]["Tools"][$ToolName]["PostHookFile"] - if (Test-Path $ToolPostHookFile -PathType Leaf) - { . ($ToolPostHookFile) } - } - } -} - -# clean up environment variables -$env:PoCRootDirectory = $null -$env:PoCWorkingDirectory = $null diff --git a/py/Wrapper/Hooks/README.md b/py/Wrapper/Hooks/README.md new file mode 100644 index 00000000..ad713991 --- /dev/null +++ b/py/Wrapper/Hooks/README.md @@ -0,0 +1,75 @@ +# PoC Hook Files + +This folder contains "hook files", which are sourced: + - before (`PreHookFile`) and + - after (`PostHostFile`) + +a PoC command gets executed with `poc.sh` or `poc.ps1`. A common use case is the preparation +of special vendor or tool chain environments. E.g. many EDA tools are using FlexLM +as a license manager, which needs the environments variable `LM_LICENSE_FILE` to be +set. A `PreHookFile` can be used to load/export such an environment variable. + + +## Hook Files + +The PoC's wrapper script parses the command line argument list for a known command. If such +a command is found, a pre- and post load event is triggered for a vendor hook file and a +tool hook file. + + +#### Example Mentor QuestaSim on Linux: + +The PoC infrastructure is called with this command line: + +```Bash +./poc.sh -v vsim PoC.arith.prng +``` + +The `vsim` command is recognized and the following events are scheduled: + + 1. `source ./Mentor.pre.sh` + 2. `source ./Mentor.QuestaSim.pre.sh` + 3. Execute `./py/PoC.py -v vsim PoC.arith.prng` + 4. `source ./Mentor.QuestaSim.post.sh` + 5. `source ./Mentor.post.sh` + +If a hook files doesn't exist, it's skipped. + + +#### Example Mentor QuestaSim on Windows: + +The PoC infrastructure is called with this command line: + +```PowerShell +.\poc.ps1 -v vsim PoC.arith.prng +``` + +The `vsim` command is recognized and the following events are scheduled: + + 1. `. .\Mentor.pre.ps1` + 2. `. .\Mentor.QuestaSim.pre.ps1` + 3. Execute `.\py\PoC.py -v vsim PoC.arith.prng` + 4. `. .\Mentor.QuestaSim.post.ps1` + 5. `. .\Mentor.post.ps1` + +If a hook files doesn't exist, it's skipped. + +## FlexLM + +Many EDA tools require an environment variable called `LM_LICENSE_FILE`. +If no other tool settings are required, a common `FlexLM.sh` can be +generated. This file is used as a symlink target for each tool specific +hook file. + +**Content of the `FlexLM.sh` script:** + +```Bash +export LM_LICENSE_FILE=1234@flexlm.company.com +``` + +**Create symlinks:** + +```Bash +ln -s FlexLM.sh Altera.Quartus.pre.sh +ln -s FlexLM.sh Mentor.QuestaSim.pre.sh +``` diff --git a/py/Wrapper/Lattice.Diamond.psm1 b/py/Wrapper/Lattice.Diamond.psm1 new file mode 100644 index 00000000..90d8dfd1 --- /dev/null +++ b/py/Wrapper/Lattice.Diamond.psm1 @@ -0,0 +1,77 @@ +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# +# ============================================================================== +# Authors: Patrick Lehmann +# +# PowerShell Module: +# +# Description: +# ------------------------------------ +# TODO: +# - +# +# License: +# ============================================================================== +# Copyright 2007-2016 Technische Universitaet Dresden - Germany +# Chair for VLSI-Design, Diagnostics and Architecture +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================== +# +function Open-Environment +{ $Debug = $true #$false + + # load Lattice Diamond environment if not loaded before + if (-not (Test-Path env:FOUNDRY)) + { $Diamond_InstallationDirectory = PoCQuery "INSTALL.Lattice.Diamond:InstallationDirectory" + if ($LastExitCode -ne 0) + { Write-Host "[ERROR]: ExitCode for '$PoC_Command' was not zero. Aborting execution." -ForegroundColor Red + Write-Host " $Diamond_InstallationDirectory" -ForegroundColor Red + return 1 + } + elseif ($Diamond_InstallationDirectory -eq "") + { Write-Host "[ERROR]: No Lattice Diamond installation found." -ForegroundColor Red + Write-Host "Run 'poc.ps1 configure' to configure your Lattice Diamond installation." -ForegroundColor Red + return 1 + } + elseif (-not (Test-Path $Diamond_InstallationDirectory)) + { Write-Host "[ERROR]: Lattice Diamond is configured in PoC, but installation directory '$Diamond_InstallationDirectory' does not exist." -ForegroundColor Red + Write-Host "Run 'poc.ps1 configure' to configure your Lattice Diamond installation." -ForegroundColor Red + return 1 + } + + Write-Host "Loading Lattice Diamond environment..." -ForegroundColor Yellow + $env:LSC_INI_PATH = "" + $env:LSC_DIAMOND = "true" + $env:FOUNDRY = "$Diamond_InstallationDirectory\ispFPGA" + $env:TCL_LIBRARY = "$Diamond_InstallationDirectory\tcltk\lib\tcl8.5" + return 0 + } + elseif (-not (Test-Path $env:FOUNDRY)) + { Write-Host "[ERROR]: Environment variable FOUNDRY is set, but the path does not exist." -ForegroundColor Red + Write-Host (" FOUNDRY=" + $env:FOUNDRY) -ForegroundColor Red + $env:FOUNDRY = $null + return Load-Environment + } +} + +function Close-Environment +{ Write-Host "Unloading Lattice Diamond environment..." -ForegroundColor Yellow + $env:LSC_INI_PATH = $null + $env:LSC_DIAMOND = $null + $env:FOUNDRY = $null + $env:TCL_LIBRARY = $null + return 0 +} diff --git a/py/Wrapper/Lattice.Diamond.sh b/py/Wrapper/Lattice.Diamond.sh new file mode 100644 index 00000000..10cf450c --- /dev/null +++ b/py/Wrapper/Lattice.Diamond.sh @@ -0,0 +1,81 @@ +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# +# ============================================================================== +# Authors: Patrick Lehmann +# +# BashModule: +# +# Description: +# ------------------------------------ +# TODO: +# - +# +# License: +# ============================================================================== +# Copyright 2007-2016 Technische Universitaet Dresden - Germany +# Chair for VLSI-Design, Diagnostics and Architecture +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================== + +OpenEnvironment() { + Debug=0 + Py_Interpreter=$1 + # Py_Parameters=$2 + PoC_Query=$2 + + # if $LSC_DIAMOND environment variable is not set + if [ -z "$LSC_DIAMOND" ]; then + Query="INSTALL.Lattice.Diamond:BinaryDirectory" + PoC_Command="$Py_Interpreter $PoC_Query query $Query" + test $Debug -eq 1 && echo -e "${YELLOW}Inquire Lattice Diamond binary directory: command='$PoC_Command'${NOCOLOR}" + Diamond_BinDir=$($PoC_Command) + if [ $? -ne 0 ]; then + echo 1>&2 -e "${RED}ERROR: ExitCode for '$PoC_Command' was not zero. Aborting script execution.${NOCOLOR}" + echo 1>&2 -e "${RED}$Diamond_BinDir${NOCOLOR}" + return 1 + fi + test $Debug -eq 1 && echo 1>&2 -e "${YELLOW}Lattice Diamond binary directory: '$Diamond_BinDir'${NOCOLOR}" + if [ -z "$Diamond_BinDir" ]; then + echo 1>&2 -e "${RED}No Lattice Diamond installation found.${NOCOLOR}" + echo 1>&2 -e "${RED}Run 'PoC.py configure' to configure your Lattice Diamond installation.${NOCOLOR}" + return 1 + fi + # QUESTION: move into PoC.py query like ISESettingsFile ? + Diamond_SettingsFile=$Diamond_BinDir/diamond_env + if [ ! -f "$Diamond_SettingsFile" ]; then + echo 1>&2 -e "${RED}Lattice Diamond settings file not found.${NOCOLOR}" + echo 1>&2 -e "${RED}Run 'PoC.py configure' to configure your Lattice Diamond installation.${NOCOLOR}" + return 1 + fi + + echo -e "${YELLOW}Loading Lattice Diamond environment '$Diamond_SettingsFile'...${NOCOLOR}" + PyWrapper_RescueArgs=$@ + set -- + bindir=$Diamond_BinDir #variable required by diamond_env + source $Diamond_SettingsFile + unset bindir + set -- $PyWrapper_RescueArgs + + return 0 + fi +} + +CloseEnvironment() { + # echo 1>&2 -e "${YELLOW}Unloading Lattice Diamond environment...${NOCOLOR}" + return 0 +} + + diff --git a/py/Wrapper/Sphinx.psm1 b/py/Wrapper/Sphinx.psm1 new file mode 100644 index 00000000..3e3a1ab0 --- /dev/null +++ b/py/Wrapper/Sphinx.psm1 @@ -0,0 +1,53 @@ +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# +# ============================================================================== +# Authors: Patrick Lehmann +# +# PowerShell Module: +# +# Description: +# ------------------------------------ +# TODO: +# - +# +# License: +# ============================================================================== +# Copyright 2007-2016 Technische Universitaet Dresden - Germany +# Chair for VLSI-Design, Diagnostics and Architecture +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================== +# +function Open-Environment +{ $Debug = $false + + $DocumentationDirectory = "docs" + $BuildDirectory = "_build" + $Builder = "html" + $SphinxBinary = "sphinx-build.exe" + + Write-Host "Executing Sphinx ..." + #& $SphinxBinary "-b $Builder -d .\$DocumentationDirectory\$BuildDirectory\doctrees .\$DocumentationDirectory .\$DocumentationDirectory\$BuildDirectory\$Builder" + sphinx-build.exe -b $Builder -d ".\$DocumentationDirectory\$BuildDirectory\doctrees" ".\$DocumentationDirectory" ".\$DocumentationDirectory\$BuildDirectory\$Builder" + + return 1 +} + +function Close-Environment +{ return 0 +} + +Export-ModuleMember -Function 'Open-Environment' +Export-ModuleMember -Function 'Close-Environment' diff --git a/py/Wrapper/Sphinx.sh b/py/Wrapper/Sphinx.sh new file mode 100644 index 00000000..2d8680e8 --- /dev/null +++ b/py/Wrapper/Sphinx.sh @@ -0,0 +1,56 @@ +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# +# ============================================================================== +# Authors: Patrick Lehmann +# +# BashModule: +# +# Description: +# ------------------------------------ +# TODO: +# - +# +# License: +# ============================================================================== +# Copyright 2007-2016 Technische Universitaet Dresden - Germany +# Chair for VLSI-Design, Diagnostics and Architecture +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================== + +OpenEnvironment() { + Debug=0 + Py_Interpreter=$1 + # Py_Parameters=$2 + PoC_Query=$2 + + DocumentationDirectory="docs" + BuildDirectory="_build" + Builder="html" + SphinxBinary="sphinx-build" + + echo 1>&2 -e "${YELLOW}Executing Sphinx ...${NOCOLOR}" + $SphinxBinary -b $Builder -d "./$DocumentationDirectory/$BuildDirectory/doctrees" "./$DocumentationDirectory" "./$DocumentationDirectory/$BuildDirectory/$Builder" + + return 1 +} + + +CloseEnvironment() { + # echo 1>&2 -e "${YELLOW}Unloading Xilinx ISE environment...${NOCOLOR}" + return 0 +} + + diff --git a/py/Wrapper/Xilinx.ISE.psm1 b/py/Wrapper/Xilinx.ISE.psm1 new file mode 100644 index 00000000..e9a26675 --- /dev/null +++ b/py/Wrapper/Xilinx.ISE.psm1 @@ -0,0 +1,131 @@ +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# +# ============================================================================== +# Authors: Patrick Lehmann +# +# PowerShell Module: +# +# Description: +# ------------------------------------ +# TODO: +# - +# +# License: +# ============================================================================== +# Copyright 2007-2016 Technische Universitaet Dresden - Germany +# Chair for VLSI-Design, Diagnostics and Architecture +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================== +# +$VHDLStandard = "93" + +function Open-Environment +{ $Debug = $false + + # load Xilinx ISE environment if not loaded before + if (-not (Test-Path env:XILINX)) + { $ISE_SettingsFile = PoCQuery "Xilinx.ISE:SettingsFile" + if ($LastExitCode -ne 0) + { Write-Host "[ERROR]: ExitCode for '$PoC_Command' was not zero. Aborting execution." -ForegroundColor Red + Write-Host " $ISE_SettingsFile" -ForegroundColor Red + return 1 + } + elseif ($ISE_SettingsFile -eq "") + { Write-Host "ERROR: No Xilinx ISE installation found." -ForegroundColor Red + Write-Host "Run 'poc.ps1 configure' to configure your Xilinx ISE installation." -ForegroundColor Red + return 1 + } + elseif (-not (Test-Path $ISE_SettingsFile -PathType Leaf)) + { Write-Host "[ERROR]: Xilinx ISE is configured in PoC, but settings file '$ISE_SettingsFile' does not exist." -ForegroundColor Red + Write-Host "Run 'poc.ps1 configure' to configure your Xilinx ISE installation." -ForegroundColor Red + return 1 + } + elseif (-not (($ISE_SettingsFile -like "*.bat") -or ($ISE_SettingsFile -like "*.cmd"))) + { Write-Host "[ERROR]: Xilinx ISE is configured in PoC, but settings file format is not supported." -ForegroundColor Red + return 1 + } + + Write-Host "Loading Xilinx ISE environment '$ISE_SettingsFile'" -ForegroundColor Yellow + if (-not (Get-Module -ListAvailable PSCX)) + { Write-Host "[ERROR]: PowerShell Community Extensions (PSCX) is not installed." -ForegroundColor Red + return 1 + } + Import-Module PSCX + + Push-EnvironmentBlock -Description "Before loading Xilinx ISE." + + Invoke-BatchFile -path $ISE_SettingsFile + return 0 + } + elseif (-not (Test-Path $env:XILINX)) + { Write-Host "[ERROR]: Environment variable XILINX is set, but the path does not exist." -ForegroundColor Red + Write-Host (" XILINX=" + $env:XILINX) -ForegroundColor Red + $env:XILINX = $null + return (Load-Environment) + } +} + +function Close-Environment +{ Write-Host "Unloading Xilinx ISE environment..." -ForegroundColor Yellow + + Pop-EnvironmentBlock + + $env:XILINX = $null + $env:XILINX_EDK = $null + $env:XILINX_PLANAHEAD = $null + $env:XILINX_DSP = $null + return 0 +} + +function Register-Environment +{ Write-Host "ISE: register environment" + + if (Test-Path Alias:tb) + { Write-Host "[WARNING] Alias 'tb' is already in use. Use the CmdLet 'Start-Testbench instead.'" -ForegroundColor Yellow } + else + { Set-Alias -Name tb -Value Start-Testbench -Description "Start a testbench in ISE." -Scope Global } +} + +function Unregister-Environment +{ Write-Host "ISE: unregister environment" + + if (Test-Path Alias:tb) { Remove-Item Alias:tb } +} + +function Start-Testbench +{ + + Write-Host "ISE: Start a testbench only in VHDL'93" +} + +function Set-VHDLStandard +{ + [CmdletBinding()] + param( + [String] $std + ) + Write-Host "ISE: Set-VHDLStandard not supported" -ForegroundColor Red +} + + +Export-ModuleMember -Function 'Open-Environment' +Export-ModuleMember -Function 'Close-Environment' + +Export-ModuleMember -Function 'Register-Environment' +Export-ModuleMember -Function 'Unregister-Environment' +Export-ModuleMember -Function 'Start-Testbench' +Export-ModuleMember -Function 'Set-VHDLStandard' + diff --git a/py/Wrapper/Xilinx.ISE.sh b/py/Wrapper/Xilinx.ISE.sh new file mode 100644 index 00000000..bc718e32 --- /dev/null +++ b/py/Wrapper/Xilinx.ISE.sh @@ -0,0 +1,77 @@ +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# +# ============================================================================== +# Authors: Patrick Lehmann +# +# BashModule: +# +# Description: +# ------------------------------------ +# TODO: +# - +# +# License: +# ============================================================================== +# Copyright 2007-2016 Technische Universitaet Dresden - Germany +# Chair for VLSI-Design, Diagnostics and Architecture +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================== + +OpenEnvironment() { + Debug=0 + Py_Interpreter=$1 + # Py_Parameters=$2 + PoC_Query=$2 + + # if $XILINX environment variable is not set + if [ -z "$XILINX" ]; then + Query="Xilinx.ISE:SettingsFile" + PoC_Command="$Py_Interpreter $PoC_Query query $Query" + test $Debug -eq 1 && echo 1>&2 -e "${YELLOW}Inquire ISE settings file: command='$PoC_Command'${NOCOLOR}" + ISE_SettingsFile=$($PoC_Command) + if [ $? -ne 0 ]; then + echo 1>&2 -e "${RED}ERROR: ExitCode for '$PoC_Command' was not zero. Aborting script execution.${NOCOLOR}" + echo 1>&2 -e "${RED}$ISE_SettingsFile${NOCOLOR}" + return 1 + fi + test $Debug -eq 1 && echo 1>&2 -e "${YELLOW}ISE settings file: '$ISE_SettingsFile'${NOCOLOR}" + if [ -z "$ISE_SettingsFile" ]; then + echo 1>&2 -e "${RED}No Xilinx ISE installation found.${NOCOLOR}" + echo 1>&2 -e "${RED}Run 'PoC.py configure' to configure your Xilinx ISE installation.${NOCOLOR}" + return 1 + fi + if [ ! -f "$ISE_SettingsFile" ]; then + echo 1>&2 -e "${RED}Xilinx ISE settings file not found.${NOCOLOR}" + echo 1>&2 -e "${RED}Run 'PoC.py configure' to configure your Xilinx ISE installation.${NOCOLOR}" + return 1 + fi + + echo 1>&2 -e "${YELLOW}Loading Xilinx ISE environment '$ISE_SettingsFile'...${NOCOLOR}" + PyWrapper_RescueArgs=$@ + set -- + source "$ISE_SettingsFile" + set -- $PyWrapper_RescueArgs + + return 0 + fi +} + +CloseEnvironment() { + # echo 1>&2 -e "${YELLOW}Unloading Xilinx ISE environment...${NOCOLOR}" + return 0 +} + + diff --git a/py/Wrapper/Xilinx.Vivado.psm1 b/py/Wrapper/Xilinx.Vivado.psm1 new file mode 100644 index 00000000..993d16a6 --- /dev/null +++ b/py/Wrapper/Xilinx.Vivado.psm1 @@ -0,0 +1,89 @@ +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# +# ============================================================================== +# Authors: Patrick Lehmann +# +# PowerShell Module: +# +# Description: +# ------------------------------------ +# TODO: +# - +# +# License: +# ============================================================================== +# Copyright 2007-2016 Technische Universitaet Dresden - Germany +# Chair for VLSI-Design, Diagnostics and Architecture +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================== +# +function Open-Environment +{ $Debug = $false + + # load Xilinx Vivado environment if not loaded before + if (-not (Test-Path env:XILINX_VIVADO)) + { $Vivado_SettingsFile = PoCQuery "Xilinx.Vivado:SettingsFile" + if ($LastExitCode -ne 0) + { Write-Host "[ERROR]: ExitCode for '$PoC_Command' was not zero. Aborting execution." -ForegroundColor Red + Write-Host " $Vivado_SettingsFile" -ForegroundColor Red + return 1 + } + elseif ($Vivado_SettingsFile -eq "") + { Write-Host "[ERROR]: No Xilinx Vivado installation found." -ForegroundColor Red + Write-Host "Run 'poc.ps1 configure' to configure your Xilinx Vivado installation." -ForegroundColor Red + return 1 + } + elseif (-not (Test-Path $Vivado_SettingsFile -PathType Leaf)) + { Write-Host "[ERROR]: Xilinx Vivado is configured in PoC, but settings file '$Vivado_SettingsFile' does not exist." -ForegroundColor Red + Write-Host "Run 'poc.ps1 configure' to configure your Xilinx Vivado installation." -ForegroundColor Red + return 1 + } + elseif (-not (($Vivado_SettingsFile -like "*.bat") -or ($Vivado_SettingsFile -like "*.cmd"))) + { Write-Host "[ERROR]: Xilinx Vivado is configured in PoC, but settings file format is not supported." -ForegroundColor Red + return 1 + } + + Write-Host "Loading Xilinx Vivado environment '$Vivado_SettingsFile'" -ForegroundColor Yellow + if (-not (Get-Module -ListAvailable PSCX)) + { Write-Host "[ERROR]: PowerShell Community Extensions (PSCX) is not installed." -ForegroundColor Red + return 1 + } + Import-Module PSCX + + Push-EnvironmentBlock -Description "Before loading Xilinx Vivado." + + Invoke-BatchFile -path $Vivado_SettingsFile + return 0 + } + elseif (-not (Test-Path $env:XILINX_VIVADO)) + { Write-Host "[ERROR]: Environment variable XILINX_VIVADO is set, but the path does not exist." -ForegroundColor Red + Write-Host (" XILINX_VIVADO=" + $env:XILINX_VIVADO) -ForegroundColor Red + $env:XILINX_VIVADO = $null + return Load-Environment + } +} + +function Close-Environment +{ Write-Host "Unloading Xilinx Vivado environment..." -ForegroundColor Yellow + + Pop-EnvironmentBlock + + $env:XILINX_VIVADO = $null + return 0 +} + +Export-ModuleMember -Function 'Open-Environment' +Export-ModuleMember -Function 'Close-Environment' diff --git a/py/Wrapper/Xilinx.Vivado.sh b/py/Wrapper/Xilinx.Vivado.sh new file mode 100644 index 00000000..cc5c0457 --- /dev/null +++ b/py/Wrapper/Xilinx.Vivado.sh @@ -0,0 +1,77 @@ +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# +# ============================================================================== +# Authors: Patrick Lehmann +# +# BashModule: +# +# Description: +# ------------------------------------ +# TODO: +# - +# +# License: +# ============================================================================== +# Copyright 2007-2016 Technische Universitaet Dresden - Germany +# Chair for VLSI-Design, Diagnostics and Architecture +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================== + +OpenEnvironment() { + Debug=0 + Py_Interpreter=$1 + # Py_Parameters=$2 + PoC_Query=$2 + + # if $XILINX_VIVADO environment variable is not set + if [ -z "$XILINX_VIVADO" ]; then + Query="Xilinx.Vivado:SettingsFile" + PoC_Command="$Py_Interpreter $PoC_Query query $Query" + test $Debug -eq 1 && echo 1>&2 -e "${YELLOW}Inquire Vivado settings file: command='$PoC_Command'${NOCOLOR}" + Vivado_SettingsFile=$($PoC_Command) + if [ $? -ne 0 ]; then + echo 1>&2 -e "${RED}ERROR: ExitCode for '$PoC_Command' was not zero. Aborting script execution.${NOCOLOR}" + echo 1>&2 -e "${RED}$Vivado_SettingsFile${NOCOLOR}" + return 1 + fi + test $Debug -eq 1 && echo 1>&2 -e "${YELLOW}Vivado settings file: '$Vivado_SettingsFile'${NOCOLOR}" + if [ -z "$Vivado_SettingsFile" ]; then + echo 1>&2 -e "${RED}No Xilinx Vivado installation found.${NOCOLOR}" + echo 1>&2 -e "${RED}Run 'PoC.py configure' to configure your Xilinx Vivado installation.${NOCOLOR}" + return 1 + fi + if [ ! -f "$Vivado_SettingsFile" ]; then + echo 1>&2 -e "${RED}Xilinx Vivado settings file not found.${NOCOLOR}" + echo 1>&2 -e "${RED}Run 'PoC.py configure' to configure your Xilinx Vivado installation.${NOCOLOR}" + return 1 + fi + + echo 1>&2 -e "${YELLOW}Loading Xilinx Vivado environment '$Vivado_SettingsFile'...${NOCOLOR}" + PyWrapper_RescueArgs=$@ + set -- + source "$Vivado_SettingsFile" + set -- $PyWrapper_RescueArgs + + return 0 + fi +} + +CloseEnvironment() { + # echo 1>&2 -e "${YELLOW}Unloading Xilinx Vivado environment...${NOCOLOR}" + return 0 +} + + diff --git a/py/Wrapper/wrapper.sh b/py/Wrapper/wrapper.sh new file mode 100644 index 00000000..d5e14d90 --- /dev/null +++ b/py/Wrapper/wrapper.sh @@ -0,0 +1,349 @@ +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# +# ============================================================================== +# Authors: Patrick Lehmann +# Thomas B. Preusser +# Martin Zabel +# +# Bash Script: Wrapper Script to execute a given Python script +# +# Description: +# ------------------------------------ +# This is a bash script (callable) which: +# - checks for a minimum installed Python version +# - loads vendor environments before executing the Python programs +# +# License: +# ============================================================================== +# Copyright 2007-2016 Technische Universitaet Dresden - Germany +# Chair for VLSI-Design, Diagnostics and Architecture +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================== + +# script settings +PoC_ExitCode=0 +PoC_WorkingDir=$(pwd) +PoC_PythonScriptDir="py" +PoC_FrontEnd="$PoC_RootDir/$PoC_PythonScriptDir/PoC.py" +PoC_WrapperDirectory="$PoC_PythonScriptDir/Wrapper" +PoC_HookDirectory="$PoC_WrapperDirectory/Hooks" + +# define color escape codes +RED='\e[0;31m' # Red +YELLOW='\e[1;33m' # Yellow +NOCOLOR='\e[0m' # No Color + +# set default values +PyWrapper_Debug=0 + +# Aldec tools +declare -A Env_Aldec=( + ["PreHookFile"]="Aldec.pre.sh" + ["PostHookFile"]="Aldec.post.sh" + ["Tools"]="ActiveHDL RevieraPRO" +) +declare -A Env_Aldec_ActiveHDL=( + ["Load"]=0 + ["Commands"]="asim" + ["BashModule"]="Aldec.ActiveHDL.sh" + ["PreHookFile"]="Aldec.ActiveHDL.pre.sh" + ["PostHookFile"]="Aldec.ActiveHDL.post.sh" +) +declare -A Env_Aldec_RevieraPRO=( + ["Load"]=0 + ["Commands"]="rpro" + ["BashModule"]="Aldec.RevieraPRO.sh" + ["PreHookFile"]="Aldec.RevieraPRO.pre.sh" + ["PostHookFile"]="Aldec.RevieraPRO.post.sh" +) +# Altera tools +declare -A Env_Altera=( + ["PreHookFile"]="Altera.pre.sh" + ["PostHookFile"]="Altera.post.sh" + ["Tools"]="Quartus" +) +declare -A Env_Altera_Quartus=( + ["Load"]=0 + ["Commands"]="quartus" + ["BashModule"]="Altera.Quartus.sh" + ["PreHookFile"]="Altera.Quartus.pre.sh" + ["PostHookFile"]="Altera.Quartus.post.sh" +) +# GHDL + GTKWave +declare -A Env_GHDL=( + ["PreHookFile"]="" + ["PostHookFile"]="" + ["Tools"]="GHDL GTKWave" +) +declare -A Env_GHDL_GHDL=( + ["Load"]=0 + ["Commands"]="ghdl" + ["BashModule"]="GHDL.sh" + ["PreHookFile"]="GHDL.pre.sh" + ["PostHookFile"]="GHDL.post.sh" +) +declare -A Env_GHDL_GTKWave=( + ["Load"]=0 + ["Commands"]="ghdl" + ["BashModule"]="GTKWave.sh" + ["PreHookFile"]="GTKWave.pre.sh" + ["PostHookFile"]="GTKWave.post.sh" +) +# Lattice tools +declare -A Env_Lattice=( + ["PreHookFile"]="Lattice.pre.sh" + ["PostHookFile"]="Lattice.post.sh" + ["Tools"]="Diamond ActiveHDL" +) +declare -A Env_Lattice_Diamond=( + ["Load"]=0 + ["Commands"]="lse" + ["BashModule"]="Lattice.Diamond.sh" + ["PreHookFile"]="Lattice.Diamond.pre.sh" + ["PostHookFile"]="Lattice.Diamond.post.sh" +) +declare -A Env_Lattice_ActiveHDL=( + ["Load"]=0 + ["Commands"]="asim" + ["BashModule"]="Lattice.ActiveHDL.sh" + ["PreHookFile"]="Lattice.ActiveHDL.pre.sh" + ["PostHookFile"]="Lattice.ActiveHDL.post.sh" +) +# Mentor Graphics tools +declare -A Env_Mentor=( + ["PreHookFile"]="Mentor.pre.sh" + ["PostHookFile"]="Mentor.post.sh" + ["Tools"]="PrecisionRTL QuestaSim" +) +declare -A Env_Mentor_PrecisionRTL=( + ["Load"]=0 + ["Commands"]="prtl" + ["BashModule"]="Mentor.PrecisionRTL.sh" + ["PreHookFile"]="Mentor.PrecisionRTL.pre.sh" + ["PostHookFile"]="Mentor.PrecisionRTL.post.sh" +) +declare -A Env_Mentor_QuestaSim=( + ["Load"]=0 + ["Commands"]="vsim" + ["BashModule"]="Mentor.QuestaSim.sh" + ["PreHookFile"]="Mentor.QuestaSim.pre.sh" + ["PostHookFile"]="Mentor.QuestaSim.post.sh" +) +# Sphinx documentation system +declare -A Env_Sphinx=( + ["PreHookFile"]="" + ["PostHookFile"]="" + ["Tools"]="Sphinx" +) +declare -A Env_Sphinx_Sphinx=( + ["Load"]=0 + ["Commands"]="docs" + ["BashModule"]="Sphinx.sh" + ["PreHookFile"]="Sphinx.pre.sh" + ["PostHookFile"]="Sphinx.post.sh" +) +# Xilinx tools +declare -A Env_Xilinx=( + ["PreHookFile"]="Xilinx.pre.sh" + ["PostHookFile"]="Xilinx.post.sh" + ["Tools"]="ISE Vivado" +) +declare -A Env_Xilinx_ISE=( + ["Load"]=0 + ["Commands"]="isim xst coregen ise" + ["BashModule"]="Xilinx.ISE.sh" + ["PreHookFile"]="Xilinx.ISE.pre.sh" + ["PostHookFile"]="Xilinx.ISE.post.sh" +) +declare -A Env_Xilinx_Vivado=( + ["Load"]=0 + ["Commands"]="xsim vivado" + ["BashModule"]="Xilinx.Vivado.sh" + ["PreHookFile"]="Xilinx.Vivado.pre.sh" + ["PostHookFile"]="Xilinx.Vivado.post.sh" +) + + +# Cocotb +declare -A Env_Cocotb=( + ["PreHookFile"]="Cocotb.pre.sh" + ["PostHookFile"]="Cocotb.post.sh" + ["Tools"]="QuestaSim" +) +declare -A Env_Cocotb_QuestaSim=( + ["Load"]=0 + ["Commands"]="cocotb" + ["BashModule"]="Cocotb.QuestaSim.sh" + ["PreHookFile"]="Cocotb.QuestaSim.pre.sh" + ["PostHookFile"]="Cocotb.QuestaSim.post.sh" +) + + +# List all vendors +Env_Vendors="Aldec Altera GHDL Lattice Mentor Sphinx Xilinx Cocotb" + +# search script parameters for known commands +BreakIt=0 +for param in $PyWrapper_Parameters; do + if [ "$param" = "-D" ]; then + PyWrapper_Debug=1 + continue + fi + # compare registered commands from all vendor tools + for VendorName in $Env_Vendors; do + declare -n VendorIndex="Env_$VendorName" + for ToolName in ${VendorIndex["Tools"]}; do + declare -n ToolIndex="Env_${VendorName}_${ToolName}" + for Command in ${ToolIndex["Commands"]}; do + if [ "$param" = "$Command" ]; then + ToolIndex["Load"]=1 + BreakIt=1 + break + fi + done # Commands + done # ToolNames + done # VendorNames + # break is a known command was detected + if [ $BreakIt -eq 1 ]; then break; fi +done # Parameters + + +# publish PoC directories as environment variables +export PoCRootDirectory=$PoC_RootDir +export PoCWorkingDirectory=$PoC_WorkingDir + +if [ $PyWrapper_Debug -eq 1 ]; then + echo -e "${YELLOW}This is the PoC Library script wrapper operating in debug mode.${NOCOLOR}" + echo + echo -e "${YELLOW}Directories:${NOCOLOR}" + echo -e "${YELLOW} PoC root: $PoC_RootDir${NOCOLOR}" + echo -e "${YELLOW} working: $PoC_WorkingDir${NOCOLOR}" + echo -e "${YELLOW}Script:${NOCOLOR}" + echo -e "${YELLOW} Filename: $PyWrapper_Script${NOCOLOR}" + echo -e "${YELLOW} Solution: $PyWrapper_Solution${NOCOLOR}" + echo -e "${YELLOW} Parameters: $PyWrapper_Parameters${NOCOLOR}" + echo -e "${YELLOW}Load Environment: ${NOCOLOR}" + echo -e "${YELLOW} Lattice Diamond: ${Env_Lattice_Diamond["Load"]}${NOCOLOR}" + echo -e "${YELLOW} Xilinx ISE: ${Env_Xilinx_ISE["Load"]}${NOCOLOR}" + echo -e "${YELLOW} Xilinx VIVADO: ${Env_Xilinx_Vivado["Load"]}${NOCOLOR}" + echo +fi + +# find suitable python version or abort execution +Python_VersionTest='import sys; sys.exit(not (0x03050000 < sys.hexversion < 0x04000000))' +python -c "$Python_VersionTest" 2>/dev/null +if [ $? -eq 0 ]; then + Python_Interpreter=$(which python 2>/dev/null) + test $PyWrapper_Debug -eq 1 && echo -e "${YELLOW}PythonInterpreter: use standard interpreter: '$Python_Interpreter'${NOCOLOR}" +else + # standard python interpreter is not suitable, try to find a suitable version manually + for pyVersion in 3.9 3.8 3.7 3.6 3.5; do + Python_Interpreter=$(which python$pyVersion 2>/dev/null) + # if ExitCode = 0 => version found + if [ $? -eq 0 ]; then + # redo version test + $Python_Interpreter -c "$Python_VersionTest" 2>/dev/null + if [ $? -eq 0 ]; then break; fi + fi + done + test $PyWrapper_Debug -eq 1 && echo -e "${YELLOW}PythonInterpreter: use this interpreter: '$Python_Interpreter'${NOCOLOR}" +fi +# if no interpreter was found => exit +if [ -z "$Python_Interpreter" ]; then + echo 1>&2 -e "${RED}No suitable Python interpreter found.${NOCOLOR}" + echo 1>&2 -e "${RED}The script requires Python >= $PyWrapper_MinVersion${NOCOLOR}" + PoC_ExitCode=1 +fi + + +# execute vendor and tool pre-hook files if present +for VendorName in $Env_Vendors; do + declare -n VendorIndex="Env_$VendorName" + for ToolName in ${VendorIndex["Tools"]}; do + declare -n ToolIndex="Env_${VendorName}_${ToolName}" + if [ ${ToolIndex["Load"]} -eq 1 ]; then + # if exists, source the vendor pre-hook file + VendorPreHookFile=$PoC_RootDir/$PoC_HookDirectory/${VendorIndex["PreHookFile"]} + test -f $VendorPreHookFile && source $VendorPreHookFile + + # if exists, source the tool pre-hook file + ToolPreHookFile=$PoC_RootDir/$PoC_HookDirectory/${ToolIndex["PreHookFile"]} + test -f $ToolPreHookFile && source $ToolPreHookFile + + # if exists, source the BashModule file + ModuleFile=$PoC_RootDir/$PoC_WrapperDirectory/${ToolIndex["BashModule"]} + if [ -f $ModuleFile ]; then + source $ModuleFile + OpenEnvironment $Python_Interpreter $PoC_FrontEnd + PoC_ExitCode=$? + fi + + break 2 + fi + done # ToolNames +done # VendorNames + + +# execute script with appropriate python interpreter and all given parameters +if [ $PoC_ExitCode -eq 0 ]; then + Python_Script="$PoC_RootDir/$PoC_PythonScriptDir/$PyWrapper_Script" + + if [ -z $PyWrapper_Solution ]; then + Python_ScriptParameters=$PyWrapper_Parameters + else + Python_ScriptParameters="--sln=$PyWrapper_Solution $PyWrapper_Parameters" + fi + + if [ $PyWrapper_Debug -eq 1 ]; then + echo -e "${YELLOW}Launching: '$Python_Interpreter $Python_Script $Python_ScriptParameters'${NOCOLOR}" + echo -e "${YELLOW}------------------------------------------------------------${NOCOLOR}" + fi + + # launching python script + set -f + "$Python_Interpreter" $Python_Script $Python_ScriptParameters + PoC_ExitCode=$? +fi + +# execute vendor and tool post-hook files if present +for VendorName in $Env_Vendors; do + declare -n VendorIndex="Env_$VendorName" + for ToolName in ${VendorIndex["Tools"]}; do + declare -n ToolIndex="Env_${VendorName}_${ToolName}" + if [ ${ToolIndex["Load"]} -eq 1 ]; then + # if exists, source the tool Post-hook file + ToolPostHookFile=$PoC_RootDir/$PoC_HookDirectory/${ToolIndex["PostHookFile"]} + test -f $ToolPostHookFile && source $ToolPostHookFile + + # if exists, source the vendor post-hook file + VendorPostHookFile=$PoC_RootDir/$PoC_HookDirectory/${VendorIndex["PostHookFile"]} + test -f $VendorPostHookFile && source $VendorPostHookFile + + # if exists, source the BashModule file + ModuleFile=$PoC_RootDir/$PoC_WrapperDirectory/${ToolIndex["BashModule"]} + if [ -f $ModuleFile ]; then + # source $ModuleFile + CloseEnvironment $Python_Interpreter $PoC_FrontEnd + PoC_ExitCode=$? + fi + break 2 + fi + done # ToolNames +done # VendorNames + +# clean up environment variables +unset PoCRootDirectory +unset PoCWorkingDirectory diff --git a/py/__init__.py b/py/__init__.py index 1b54e767..32a31622 100644 --- a/py/__init__.py +++ b/py/__init__.py @@ -1,28 +1,28 @@ # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2; replace-tabs off; indent-width 2; -# +# # ============================================================================== # Authors: Patrick Lehmann -# +# # Python Sub Module: Saves The PoC-Library configuration as python source code. -# +# # Description: # ------------------------------------ # TODO: -# +# # # License: # ============================================================================== # Copyright 2007-2015 Technische Universitaet Dresden - Germany # Chair for VLSI-Design, Diagnostics and Architecture -# +# # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at -# +# # http://www.apache.org/licenses/LICENSE-2.0 -# +# # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. diff --git a/py/config.boards.ini b/py/config.boards.ini index 38a12af4..ea331074 100644 --- a/py/config.boards.ini +++ b/py/config.boards.ini @@ -1,11 +1,11 @@ -# EMACS settings: -*- tab-width: 2indent-tabs-mode: t -*- +# EMACS settings: -*- tab-width: 2indent-tabs-mode: t -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2replace-tabs offindent-width 2; # # ============================================================================== -# Authors: Patrick Lehmann +# Authors: Patrick Lehmann # -# Supported boards: This file stores all supported boards and it's settings. +# Supported boards: This file stores all supported boards and it's settings. # # Description: # ------------------------------------ @@ -29,235 +29,239 @@ # ============================================================================== # [BOARDS] -GENERIC = BOARD.GENERIC +GENERIC = BOARD.GENERIC # virtual boards per vendor -Altera = BOARD.DE4 -Lattice = BOARD.ECP5Versa -Xilinx = BOARD.KC705 +Altera = BOARD.DE4 +Lattice = BOARD.ECP5Versa +Xilinx = BOARD.KC705 # Altera boards -DE0 = BOARD.DE0 -DE4 = BOARD.DE4 -DE5 = BOARD.DE5 -S2GXAV = BOARD.S2GXAV +DE0 = BOARD.DE0 +DE4 = BOARD.DE4 +DE5 = BOARD.DE5 +S2GXAV = BOARD.S2GXAV # Lattice boards -ECP5Versa = BOARD.ECP5Versa +ECP5Versa = BOARD.ECP5Versa # Xilinx boards -S3SK = BOARD.S3SK200 -S3SK200 = BOARD.S3SK200 -S3SK500 = BOARD.S3SK500 -S3SK1000 = BOARD.S3SK1000 -S3SK1600 = BOARD.S3SK1600 -ML505 = BOARD.ML505 -ML506 = BOARD.ML505 -ML507 = BOARD.ML507 -Atlys = BOARD.Atlys -ML605 = BOARD.ML605 -KC705 = BOARD.KC705 -VC707 = BOARD.VC707 -VC709 = BOARD.VC709 -ZC706 = BOARD.ZC706 -ZEDBOARD = BOARD.ZEDBOARD +S3SK = BOARD.S3SK200 +S3SK200 = BOARD.S3SK200 +S3SK500 = BOARD.S3SK500 +S3SK1000 = BOARD.S3SK1000 +S3SK1600 = BOARD.S3SK1600 +ML505 = BOARD.ML505 +ML506 = BOARD.ML505 +ML507 = BOARD.ML507 +Atlys = BOARD.Atlys +ML605 = BOARD.ML605 +AC701 = BOARD.AC701 +KC705 = BOARD.KC705 +VC707 = BOARD.VC707 +VC709 = BOARD.VC709 +ZC706 = BOARD.ZC706 +ZedBoard = BOARD.ZedBoard [BOARD.GENERIC] -FPGA = GENERIC +FPGA = GENERIC [BOARD.DE0] -FPGA = EP3C16F484C6 +FPGA = EP3C16F484C6 [BOARD.S2GXAV] -FPGA = EP2SGX90FF1508C3 +FPGA = EP2SGX90FF1508C3 [BOARD.DE4] -FPGA = EP4SGX230KF40C2 +FPGA = EP4SGX230KF40C2 [BOARD.DE5] -FPGA = EP5SGXEA7N2F45C2 +FPGA = EP5SGXEA7N2F45C2 [BOARD.ECP5Versa] -FPGA = LFE5UM-45F-6BG381C +FPGA = LFE5UM-45F-6BG381C [BOARD.S3SK200] -FPGA = XC3S200FT256 +FPGA = XC3S200FT256 [BOARD.S3SK500] -FPGA = XC3S500FT256 +FPGA = XC3S500FT256 [BOARD.S3SK1000] -FPGA = XC3S1000FT256 +FPGA = XC3S1000FT256 [BOARD.S3SK1600] -FPGA = XC3S1600FT256 +FPGA = XC3S1600FT256 [BOARD.ML505] -FPGA = XC5VLX50T-1FF1136 -UCF = XilinxISEConstraints +FPGA = XC5VLX50T-1FF1136 +UCF = XilinxISEConstraints [CONST.ML505.UCF] -Default.ucf = ${ConstraintDir}/Default.ucf -Clock.SMA = ${ConstraintDir}/Clock.SMA.ucf -Clock.SystemClock = ${ConstraintDir}/Clock.SystemClock.ucf -Clock.UserClock = ${ConstraintDir}/Clock.UserClock.ucf -GPIO.Button.Cursor = ${ConstraintDir}/GPIO.Button.Cursor.ucf -GPIO.Button.Special = ${ConstraintDir}/GPIO.Button.Special.ucf -GPIO.Switch = ${ConstraintDir}/GPIO.Switch.ucf -GPIO.LED = ${ConstraintDir}/GPIO.LED.ucf -GPIO.LED.Cursor = ${ConstraintDir}/GPIO.LED.Cursor.ucf -GPIO.LED.Error = ${ConstraintDir}/GPIO.LED.Error.ucf -GPIO.Rotary = ${ConstraintDir}/GPIO.Rotary.ucf -UART = ${ConstraintDir}/UART.ucf -Bus.LCDisplay = ${ConstraintDir}/Bus.LCDisplay.ucf -Bus.PS2.Keyboard = ${ConstraintDir}/Bus.PS2.Keyboard.ucf -Bus.PS2.Mouse = ${ConstraintDir}/Bus.PS2.Mouse.ucf -Bus.IIC.Main = ${ConstraintDir}/Bus.IIC.Main.ucf -Bus.IIC.Monitor = ${ConstraintDir}/Bus.IIC.Monitor.ucf -EthernetPHY = ${ConstraintDir}/EthernetPHY.ucf -EthernetPHY.GMII = ${ConstraintDir}/EthernetPHY.GMII.ucf -EthernetPHY.RGMII = ${ConstraintDir}/EthernetPHY.RGMII.ucf -EthernetPHY.SGMII = ${ConstraintDir}/EthernetPHY.SGMII.ucf -Monitor.DVI.Output = ${ConstraintDir}/Monitor.DVI.Output.ucf -PCIe = ${ConstraintDir}/PCIe.ucf -Transceiver.SFP = ${ConstraintDir}/Transceiver.SFP.ucf -Transceiver.SMA = ${ConstraintDir}/Transceiver.SMA.ucf -Transceiver.SMA_RefClock = ${ConstraintDir}/Transceiver.SMA_RefClock.ucf +Default.ucf = ${ConstraintDir}/Default.ucf +Clock.SMA = ${ConstraintDir}/Clock.SMA.ucf +Clock.SystemClock = ${ConstraintDir}/Clock.SystemClock.ucf +Clock.UserClock = ${ConstraintDir}/Clock.UserClock.ucf +GPIO.Button.Cursor = ${ConstraintDir}/GPIO.Button.Cursor.ucf +GPIO.Button.Special = ${ConstraintDir}/GPIO.Button.Special.ucf +GPIO.Switch = ${ConstraintDir}/GPIO.Switch.ucf +GPIO.LED = ${ConstraintDir}/GPIO.LED.ucf +GPIO.LED.Cursor = ${ConstraintDir}/GPIO.LED.Cursor.ucf +GPIO.LED.Error = ${ConstraintDir}/GPIO.LED.Error.ucf +GPIO.Rotary = ${ConstraintDir}/GPIO.Rotary.ucf +UART = ${ConstraintDir}/UART.ucf +Bus.LCDisplay = ${ConstraintDir}/Bus.LCDisplay.ucf +Bus.PS2.Keyboard = ${ConstraintDir}/Bus.PS2.Keyboard.ucf +Bus.PS2.Mouse = ${ConstraintDir}/Bus.PS2.Mouse.ucf +Bus.IIC.Main = ${ConstraintDir}/Bus.IIC.Main.ucf +Bus.IIC.Monitor = ${ConstraintDir}/Bus.IIC.Monitor.ucf +EthernetPHY = ${ConstraintDir}/EthernetPHY.ucf +EthernetPHY.GMII = ${ConstraintDir}/EthernetPHY.GMII.ucf +EthernetPHY.RGMII = ${ConstraintDir}/EthernetPHY.RGMII.ucf +EthernetPHY.SGMII = ${ConstraintDir}/EthernetPHY.SGMII.ucf +Monitor.DVI.Output = ${ConstraintDir}/Monitor.DVI.Output.ucf +PCIe = ${ConstraintDir}/PCIe.ucf +Transceiver.SFP = ${ConstraintDir}/Transceiver.SFP.ucf +Transceiver.SMA = ${ConstraintDir}/Transceiver.SMA.ucf +Transceiver.SMA_RefClock = ${ConstraintDir}/Transceiver.SMA_RefClock.ucf [BOARD.ML506] -FPGA = XC5VSX50T-1FFG1136 +FPGA = XC5VSX50T-1FFG1136 [BOARD.ML507] -FPGA = XC5VFX70T-1FFG1136 +FPGA = XC5VFX70T-1FFG1136 [BOARD.XUPV5] -FPGA = XC5VLX110T-1FF1136 +FPGA = XC5VLX110T-1FF1136 [BOARD.Atlys] -FPGA = XC6SLX45-3CSG324 +FPGA = XC6SLX45-3CSG324 [BOARD.ML605] -FPGA = XC6VLX240T-1FF1156 -UCF = XilinxISEConstraints +FPGA = XC6VLX240T-1FF1156 +UCF = XilinxISEConstraints [CONST.ML605.UCF] -Default.ucf = ${ConstraintDir}/Default.ucf -Clock.SystemClock = ${ConstraintDir}/Clock.SystemClock.ucf -Clock.UserClock = ${ConstraintDir}/Clock.UserClock.ucf -GPIO.Button.Cursor = ${ConstraintDir}/GPIO.Button.Cursor.ucf -GPIO.Button.Special = ${ConstraintDir}/GPIO.Button.Special.ucf -GPIO.Switch = ${ConstraintDir}/GPIO.Switch.ucf -GPIO.LED = ${ConstraintDir}/GPIO.LED.ucf -GPIO.LED.Cursor = ${ConstraintDir}/GPIO.LED.Cursor.ucf -GPIO.Rotary = ${ConstraintDir}/GPIO.Rotary.ucf -USB_UART = ${ConstraintDir}/USB_UART.ucf -Bus.LCDisplay = ${ConstraintDir}/Bus.LCDisplay.ucf -Bus.IIC = ${ConstraintDir}/Bus.IIC.ucf -Bus.PMBus = ${ConstraintDir}/Bus.PMBus.ucf -EthernetPHY = ${ConstraintDir}/EthernetPHY.ucf -EthernetPHY.GMII = ${ConstraintDir}/EthernetPHY.GMII.ucf -EthernetPHY.RGMII = ${ConstraintDir}/EthernetPHY.RGMII.ucf -EthernetPHY.SGMII = ${ConstraintDir}/EthernetPHY.SGMII.ucf -Monitor.DVI.Output = ${ConstraintDir}/Monitor.DVI.Output.ucf -PCIe = ${ConstraintDir}/PCIe.ucf -Transceiver.SFP = ${ConstraintDir}/Transceiver.SFP.ucf -Transceiver.SMA = ${ConstraintDir}/Transceiver.SMA.ucf -Transceiver.SMA_RefClock = ${ConstraintDir}/Transceiver.SMA_RefClock.ucf +Default.ucf = ${ConstraintDir}/Default.ucf +Clock.SystemClock = ${ConstraintDir}/Clock.SystemClock.ucf +Clock.UserClock = ${ConstraintDir}/Clock.UserClock.ucf +GPIO.Button.Cursor = ${ConstraintDir}/GPIO.Button.Cursor.ucf +GPIO.Button.Special = ${ConstraintDir}/GPIO.Button.Special.ucf +GPIO.Switch = ${ConstraintDir}/GPIO.Switch.ucf +GPIO.LED = ${ConstraintDir}/GPIO.LED.ucf +GPIO.LED.Cursor = ${ConstraintDir}/GPIO.LED.Cursor.ucf +GPIO.Rotary = ${ConstraintDir}/GPIO.Rotary.ucf +USB_UART = ${ConstraintDir}/USB_UART.ucf +Bus.LCDisplay = ${ConstraintDir}/Bus.LCDisplay.ucf +Bus.IIC = ${ConstraintDir}/Bus.IIC.ucf +Bus.PMBus = ${ConstraintDir}/Bus.PMBus.ucf +EthernetPHY = ${ConstraintDir}/EthernetPHY.ucf +EthernetPHY.GMII = ${ConstraintDir}/EthernetPHY.GMII.ucf +EthernetPHY.RGMII = ${ConstraintDir}/EthernetPHY.RGMII.ucf +EthernetPHY.SGMII = ${ConstraintDir}/EthernetPHY.SGMII.ucf +Monitor.DVI.Output = ${ConstraintDir}/Monitor.DVI.Output.ucf +PCIe = ${ConstraintDir}/PCIe.ucf +Transceiver.SFP = ${ConstraintDir}/Transceiver.SFP.ucf +Transceiver.SMA = ${ConstraintDir}/Transceiver.SMA.ucf +Transceiver.SMA_RefClock = ${ConstraintDir}/Transceiver.SMA_RefClock.ucf + +[BOARD.AC701] +FPGA = XC7A200T-2FBG676 [BOARD.KC705] -FPGA = XC7K325T-2FFG900 -UCF = XilinxISEConstraints -XDC = XilinxvivadoConstraints +FPGA = XC7K325T-2FFG900 +UCF = XilinxISEConstraints +XDC = XilinxvivadoConstraints [CONST.KC705.UCF] -Default = ${ConstraintDir}/Default.ucf -Clock.SystemClock = ${ConstraintDir}/Clock.SystemClock.ucf -Clock.ProgUserClock = ${ConstraintDir}/Clock.ProgUserClock.ucf -Clock.SMAClock = ${ConstraintDir}/Clock.SMAClock.ucf -Clock.Si5324 = ${ConstraintDir}/Clock.Si5324.ucf -Bus.LCDisplay = ${ConstraintDir}/Bus.LCDisplay.ucf -Bus.IIC = ${ConstraintDir}/Bus.IIC.ucf -Bus.PMBus = ${ConstraintDir}/Bus.PMBus.ucf -EthernetPHY = ${ConstraintDir}/EthernetPHY.ucf -EthernetPHY.GMII = ${ConstraintDir}/EthernetPHY.GMII.ucf -EthernetPHY.RGMII = ${ConstraintDir}/EthernetPHY.RGMII.ucf -EthernetPHY.SGMII = ${ConstraintDir}/EthernetPHY.SGMII.ucf -GPIO.Button.Cursor = ${ConstraintDir}/GPIO.Button.Cursor.ucf -GPIO.Button.Special = ${ConstraintDir}/GPIO.Button.Special.ucf -GPIO.Switch = ${ConstraintDir}/GPIO.Switch.ucf -GPIO.LED = ${ConstraintDir}/GPIO.LED.ucf -GPIO.Rotary = ${ConstraintDir}/GPIO.Rotary.ucf -GPIO.SMA = ${ConstraintDir}/GPIO.SMA.ucf -FanControl = ${ConstraintDir}/FanControl.ucf -PCIe = ${ConstraintDir}/PCIe.ucf -Transceiver.SFP = ${ConstraintDir}/Transceiver.SFP.ucf -Transceiver.SMA = ${ConstraintDir}/Transceiver.SMA.ucf -Transceiver.SMA_RefClock = ${ConstraintDir}/Transceiver.SMA_RefClock.ucf -USB_UART = ${ConstraintDir}/USB_UART.ucf +Default = ${ConstraintDir}/Default.ucf +Clock.SystemClock = ${ConstraintDir}/Clock.SystemClock.ucf +Clock.ProgUserClock = ${ConstraintDir}/Clock.ProgUserClock.ucf +Clock.SMAClock = ${ConstraintDir}/Clock.SMAClock.ucf +Clock.Si5324 = ${ConstraintDir}/Clock.Si5324.ucf +Bus.LCDisplay = ${ConstraintDir}/Bus.LCDisplay.ucf +Bus.IIC = ${ConstraintDir}/Bus.IIC.ucf +Bus.PMBus = ${ConstraintDir}/Bus.PMBus.ucf +EthernetPHY = ${ConstraintDir}/EthernetPHY.ucf +EthernetPHY.GMII = ${ConstraintDir}/EthernetPHY.GMII.ucf +EthernetPHY.RGMII = ${ConstraintDir}/EthernetPHY.RGMII.ucf +EthernetPHY.SGMII = ${ConstraintDir}/EthernetPHY.SGMII.ucf +GPIO.Button.Cursor = ${ConstraintDir}/GPIO.Button.Cursor.ucf +GPIO.Button.Special = ${ConstraintDir}/GPIO.Button.Special.ucf +GPIO.Switch = ${ConstraintDir}/GPIO.Switch.ucf +GPIO.LED = ${ConstraintDir}/GPIO.LED.ucf +GPIO.Rotary = ${ConstraintDir}/GPIO.Rotary.ucf +GPIO.SMA = ${ConstraintDir}/GPIO.SMA.ucf +FanControl = ${ConstraintDir}/FanControl.ucf +PCIe = ${ConstraintDir}/PCIe.ucf +Transceiver.SFP = ${ConstraintDir}/Transceiver.SFP.ucf +Transceiver.SMA = ${ConstraintDir}/Transceiver.SMA.ucf +Transceiver.SMA_RefClock = ${ConstraintDir}/Transceiver.SMA_RefClock.ucf +USB_UART = ${ConstraintDir}/USB_UART.ucf [CONST.KC705.XDC] -Bus.IIC = ${ConstraintDir}/Bus.IIC.xdc -Clock.ProgUserClock = ${ConstraintDir}/Clock.ProgUserClock.xdc -Clock.SystemClock = ${ConstraintDir}/Clock.SystemClock.xdc -FanControl = ${ConstraintDir}/FanControl.xdc -GPIO.Button.Cursor = ${ConstraintDir}/GPIO.Button.Cursor.xdc -GPIO.Button.Special = ${ConstraintDir}/GPIO.Button.Special.xdc -GPIO.LED = ${ConstraintDir}/GPIO.LED.xdc -GPIO.Rotary = ${ConstraintDir}/GPIO.Rotary.xdc -GPIO.Switch = ${ConstraintDir}/GPIO.Switch.xdc -Transceiver.SFP = ${ConstraintDir}/Transceiver.SFP.xdc -USB_UART = ${ConstraintDir}/USB_UART.xdc +Bus.IIC = ${ConstraintDir}/Bus.IIC.xdc +Clock.ProgUserClock = ${ConstraintDir}/Clock.ProgUserClock.xdc +Clock.SystemClock = ${ConstraintDir}/Clock.SystemClock.xdc +FanControl = ${ConstraintDir}/FanControl.xdc +GPIO.Button.Cursor = ${ConstraintDir}/GPIO.Button.Cursor.xdc +GPIO.Button.Special = ${ConstraintDir}/GPIO.Button.Special.xdc +GPIO.LED = ${ConstraintDir}/GPIO.LED.xdc +GPIO.Rotary = ${ConstraintDir}/GPIO.Rotary.xdc +GPIO.Switch = ${ConstraintDir}/GPIO.Switch.xdc +Transceiver.SFP = ${ConstraintDir}/Transceiver.SFP.xdc +USB_UART = ${ConstraintDir}/USB_UART.xdc [BOARD.VC707] -FPGA = XC7VX485T-2FFG1761 -UCF = XilinxISEConstraints -XDC = XilinxvivadoConstraints +FPGA = XC7VX485T-2FFG1761 +UCF = XilinxISEConstraints +XDC = XilinxvivadoConstraints [CONST.VC707.UCF] -Default = ${ConstraintDir}/Default.ucf -Clock.SystemClock = ${ConstraintDir}/Clock.SystemClock.ucf -Clock.ProgUserClock = ${ConstraintDir}/Clock.ProgUserClock.ucf -Clock.SMAClock = ${ConstraintDir}/Clock.SMAClock.ucf -Clock.Si5324 = ${ConstraintDir}/Clock.Si5324.ucf -Bus.LCDisplay = ${ConstraintDir}/Bus.LCDisplay.ucf -Bus.IIC = ${ConstraintDir}/Bus.IIC.ucf -Bus.PMBus = ${ConstraintDir}/Bus.PMBus.ucf -EthernetPHY = ${ConstraintDir}/EthernetPHY.ucf -EthernetPHY.GMII = ${ConstraintDir}/EthernetPHY.GMII.ucf -EthernetPHY.RGMII = ${ConstraintDir}/EthernetPHY.RGMII.ucf -EthernetPHY.SGMII = ${ConstraintDir}/EthernetPHY.SGMII.ucf -GPIO.Button.Cursor = ${ConstraintDir}/GPIO.Button.Cursor.ucf -GPIO.Button.Special = ${ConstraintDir}/GPIO.Button.Special.ucf -GPIO.Switch = ${ConstraintDir}/GPIO.Switch.ucf -GPIO.LED = ${ConstraintDir}/GPIO.LED.ucf -GPIO.Rotary = ${ConstraintDir}/GPIO.Rotary.ucf -GPIO.SMA = ${ConstraintDir}/GPIO.SMA.ucf -FanControl = ${ConstraintDir}/FanControl.ucf -PCIe = ${ConstraintDir}/PCIe.ucf -Transceiver.SFP = ${ConstraintDir}/Transceiver.SFP.ucf -Transceiver.SMA = ${ConstraintDir}/Transceiver.SMA.ucf -Transceiver.SMA_RefClock = ${ConstraintDir}/Transceiver.SMA_RefClock.ucf -USB_UART = ${ConstraintDir}/USB_UART.ucf +Default = ${ConstraintDir}/Default.ucf +Clock.SystemClock = ${ConstraintDir}/Clock.SystemClock.ucf +Clock.ProgUserClock = ${ConstraintDir}/Clock.ProgUserClock.ucf +Clock.SMAClock = ${ConstraintDir}/Clock.SMAClock.ucf +Clock.Si5324 = ${ConstraintDir}/Clock.Si5324.ucf +Bus.LCDisplay = ${ConstraintDir}/Bus.LCDisplay.ucf +Bus.IIC = ${ConstraintDir}/Bus.IIC.ucf +Bus.PMBus = ${ConstraintDir}/Bus.PMBus.ucf +EthernetPHY = ${ConstraintDir}/EthernetPHY.ucf +EthernetPHY.GMII = ${ConstraintDir}/EthernetPHY.GMII.ucf +EthernetPHY.RGMII = ${ConstraintDir}/EthernetPHY.RGMII.ucf +EthernetPHY.SGMII = ${ConstraintDir}/EthernetPHY.SGMII.ucf +GPIO.Button.Cursor = ${ConstraintDir}/GPIO.Button.Cursor.ucf +GPIO.Button.Special = ${ConstraintDir}/GPIO.Button.Special.ucf +GPIO.Switch = ${ConstraintDir}/GPIO.Switch.ucf +GPIO.LED = ${ConstraintDir}/GPIO.LED.ucf +GPIO.Rotary = ${ConstraintDir}/GPIO.Rotary.ucf +GPIO.SMA = ${ConstraintDir}/GPIO.SMA.ucf +FanControl = ${ConstraintDir}/FanControl.ucf +PCIe = ${ConstraintDir}/PCIe.ucf +Transceiver.SFP = ${ConstraintDir}/Transceiver.SFP.ucf +Transceiver.SMA = ${ConstraintDir}/Transceiver.SMA.ucf +Transceiver.SMA_RefClock = ${ConstraintDir}/Transceiver.SMA_RefClock.ucf +USB_UART = ${ConstraintDir}/USB_UART.ucf [CONST.VC707.XDC] -Bus.IIC = ${ConstraintDir}/Bus.IIC.xdc -Clock.ProgUserClock = ${ConstraintDir}/Clock.ProgUserClock.xdc -Clock.SystemClock = ${ConstraintDir}/Clock.SystemClock.xdc -FanControl = ${ConstraintDir}/FanControl.xdc -GPIO.Button.Cursor = ${ConstraintDir}/GPIO.Button.Cursor.xdc -GPIO.Button.Special = ${ConstraintDir}/GPIO.Button.Special.xdc -GPIO.LED = ${ConstraintDir}/GPIO.LED.xdc -GPIO.Rotary = ${ConstraintDir}/GPIO.Rotary.xdc -GPIO.Switch = ${ConstraintDir}/GPIO.Switch.xdc -Transceiver.SFP = ${ConstraintDir}/Transceiver.SFP.xdc -USB_UART = ${ConstraintDir}/USB_UART.xdc +Bus.IIC = ${ConstraintDir}/Bus.IIC.xdc +Clock.ProgUserClock = ${ConstraintDir}/Clock.ProgUserClock.xdc +Clock.SystemClock = ${ConstraintDir}/Clock.SystemClock.xdc +FanControl = ${ConstraintDir}/FanControl.xdc +GPIO.Button.Cursor = ${ConstraintDir}/GPIO.Button.Cursor.xdc +GPIO.Button.Special = ${ConstraintDir}/GPIO.Button.Special.xdc +GPIO.LED = ${ConstraintDir}/GPIO.LED.xdc +GPIO.Rotary = ${ConstraintDir}/GPIO.Rotary.xdc +GPIO.Switch = ${ConstraintDir}/GPIO.Switch.xdc +Transceiver.SFP = ${ConstraintDir}/Transceiver.SFP.xdc +USB_UART = ${ConstraintDir}/USB_UART.xdc [BOARD.VC709] -FPGA = XC7VX690T-2FFG1761C +FPGA = XC7VX690T-2FFG1761C [BOARD.ZC706] -FPGA = XC7Z045-2FFG900 +FPGA = XC7Z045-2FFG900 -[BOARD.ZEDBOARD] -FPGA = XC7Z020-1CLG484 +[BOARD.ZedBoard] +FPGA = XC7Z020-1CLG484 diff --git a/py/config.defaults.ini b/py/config.defaults.ini index 3ea5a9ce..818f38ed 100644 --- a/py/config.defaults.ini +++ b/py/config.defaults.ini @@ -1,16 +1,16 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2; replace-tabs off; indent-width 2; # # ============================================================================== -# Authors: Patrick Lehmann +# Authors: Patrick Lehmann # -# Config file: Global configuration file +# Config file: Global configuration file # # Description: # ------------------------------------ -# This file defines: -# - default option values for sections +# This file defines: +# - default option values for sections # # License: # ============================================================================== @@ -31,295 +31,346 @@ # ============================================================================== # [CONFIG.DirectoryNames] -HDLSourceFiles = src -TestbenchFiles = tb -NetlistFiles = netlist -ConstraintFiles = ucf -SimulatorFiles = sim -TemporaryFiles = temp -PrecompiledFiles = ${TemporaryFiles}/precompiled +HDLSourceFiles = src +TestbenchFiles = tb +NetlistFiles = netlist +ConstraintFiles = ucf +SimulatorFiles = sim +TemporaryFiles = temp +PrecompiledFiles = ${TemporaryFiles}/precompiled # Aldec files -ActiveHDLFiles = activehdl -RivieraPROFiles = rivierapro +ActiveHDLFiles = activehdl +RivieraPROFiles = rivierapro # Altera files -AlteraSpecificFiles = altera -QuartusSynthesisFiles = quartus +AlteraSpecificFiles = altera +QuartusSynthesisFiles = quartus # Cocotb files -CocotbFiles = cocotb +CocotbFiles = cocotb # GHDL/GTKWave files -GHDLFiles = ghdl -#GTKWaveFiles = gtkw +GHDLFiles = ghdl +# GTKWaveFiles = gtkw # Lattice files -LatticeSpecificFiles = lattice -LatticeSynthesisFiles = lse +LatticeSpecificFiles = lattice +LatticeSynthesisFiles = lse # Mentor files -ModelSimFiles = vsim -QuestaSimFiles = vsim +ModelSimFiles = vsim +QuestaSimFiles = vsim # Synopsys files # Xilinx files -XilinxSpecificFiles = xilinx -ISESynthesisFiles = xst -ISECoreGeneratorFiles = coregen -ISESimulatorFiles = isim -VivadoSimulatorFiles = xsim -VivadoSynthesisFiles = vivado +XilinxSpecificFiles = xilinx +ISESynthesisFiles = xst +ISECoreGeneratorFiles = coregen +ISESimulatorFiles = isim +VivadoSimulatorFiles = xsim +VivadoSynthesisFiles = vivado +VivadoIPCatalogFiles = xci + [BOARD.DEFAULT] -Name = %{Name} -ConstraintDir = ${%{ParentWithRoot}:Name} +Name = %{Name} +ConstraintDir = ${%{ParentWithRoot}:Name} + [PoC.DEFAULT] -Visibility = Public -Name = %{Name} -DirectoryName = ${Name} -Prefix = ${%{ParentWithRoot}:Name} +Visibility = Public +Name = %{Name} +DirectoryName = ${Name} +Prefix = ${%{ParentWithRoot}:Name} # build directories recursively from parent + directory name of the sub-namespace -RelDir = ${%{ParentWithRoot}:RelDir}/${DirectoryName} -SrcDir = ${%{ParentWithRoot}:SrcDir}/${DirectoryName} -TBDir = ${%{ParentWithRoot}:TBDir}/${DirectoryName} -SimDir = ${%{ParentWithRoot}:SimDir}/${DirectoryName} -NLDir = ${%{ParentWithRoot}:NLDir}/${DirectoryName} -XSTDir = ${%{ParentWithRoot}:XSTDir}/${DirectoryName} -QIIDir = ${%{ParentWithRoot}:QIIDir}/${DirectoryName} +RelDir = ${%{ParentWithRoot}:RelDir}/${DirectoryName} +SrcDir = ${%{ParentWithRoot}:SrcDir}/${DirectoryName} +TBDir = ${%{ParentWithRoot}:TBDir}/${DirectoryName} +SimDir = ${%{ParentWithRoot}:SimDir}/${DirectoryName} +NLDir = ${%{ParentWithRoot}:NLDir}/${DirectoryName} +XSTDir = ${%{ParentWithRoot}:XSTDir}/${DirectoryName} +QMAPDir = ${%{ParentWithRoot}:QMAPDir}/${DirectoryName} + [IP.DEFAULT] -Visibility = Public -Name = %{Name} -EntityPrefix = ${PoC.%{Parent}:Name} -FilesFile = ${SrcDir}/${EntityPrefix}_${Name}.files +Visibility = Public +Name = %{Name} +EntityPrefix = ${PoC.%{Parent}:Name} +FilesFile = ${SrcDir}/${EntityPrefix}_${Name}.files # inherit directories from IP core section -RelDir = ${PoC.%{Parent}:RelDir} -SrcDir = ${PoC.%{Parent}:SrcDir} -TBDir = ${PoC.%{Parent}:TBDir} -SimDir = ${PoC.%{Parent}:SimDir} -NLDir = ${PoC.%{Parent}:NLDir} -XSTDir = ${PoC.%{Parent}:XSTDir} -QIIDir = ${PoC.%{Parent}:QIIDir} +RelDir = ${PoC.%{Parent}:RelDir} +SrcDir = ${PoC.%{Parent}:SrcDir} +TBDir = ${PoC.%{Parent}:TBDir} +SimDir = ${PoC.%{Parent}:SimDir} +NLDir = ${PoC.%{Parent}:NLDir} +XSTDir = ${PoC.%{Parent}:XSTDir} +QMAPDir = ${PoC.%{Parent}:QMAPDir} +Dependencies = +# VHDL Generics or Verilog Parameters, Example: key1=value1; key2=value2 +HDLParameters = + [TB.DEFAULT] -Visibility = Public -TBName = ${PoC.%{GrantParent}:Name}_${IP.%{Parent}:Name} -TestbenchModule = ${TBName}_tb -FilesFile = ${TBDir}/${TestbenchModule}.files +Visibility = Public +TBName = ${PoC.%{GrantParent}:Name}_${IP.%{Parent}:Name} +TestbenchModule = ${TBName}_tb +FilesFile = ${TBDir}/${TestbenchModule}.files # inherit directories from IP core section -SrcDir = ${IP.%{Parent}:SrcDir} -TBDir = ${IP.%{Parent}:TBDir} -SimDir = ${IP.%{Parent}:SimDir} +SrcDir = ${IP.%{Parent}:SrcDir} +TBDir = ${IP.%{Parent}:TBDir} +SimDir = ${IP.%{Parent}:SimDir} # vendor specific simulator files # Aldec -aSimBatchScript = ${PoC:SimDir}/aSim.batch.tcl -aSimGUIScript = ${PoC:SimDir}/aSim.gui.tcl -aSimWaveScript = ${SimDir}/${TestbenchModule}.awc +aSimBatchScript = ${PoC:SimDir}/aSim.batch.tcl +aSimGUIScript = ${PoC:SimDir}/aSim.gui.tcl +aSimWaveScript = ${SimDir}/${TestbenchModule}.awc # GHDL / GTKWave -ghdlWaveformFileFormat = ghw -gtkwSaveFile = ${SimDir}/${TestbenchModule}.gtkw +ghdlWaveformOptionFile = ${SimDir}/${TestbenchModule}.ghdl +ghdlWaveformFileFormat = ghw +gtkwSaveFile = ${SimDir}/${TestbenchModule}.gtkw # ModelSim / QuestaSim -vSimBatchScript = ${PoC:SimDir}/vSim.batch.tcl -vSimGUIScript = ${PoC:SimDir}/vSim.gui.tcl -vSimWaveScript = ${SimDir}/${TestbenchModule}.wdo +vSimBatchScript = ${PoC:SimDir}/vSim.batch.tcl +vSimGUIScript = ${PoC:SimDir}/vSim.gui.tcl +vSimWaveScript = ${SimDir}/${TestbenchModule}.wdo # Xilinx ISE -iSimBatchScript = ${PoC:SimDir}/iSim.batch.tcl -iSimGUIScript = ${PoC:SimDir}/iSim.gui.tcl -iSimWaveformConfigFile = ${SimDir}/${TestbenchModule}.wcfg +iSimBatchScript = ${PoC:SimDir}/iSim.batch.tcl +iSimGUIScript = ${PoC:SimDir}/iSim.gui.tcl +iSimWaveformConfigFile = ${SimDir}/${TestbenchModule}.wcfg # Xilinx Vivado -xSimBatchScript = ${PoC:SimDir}/xSim.batch.tcl -xSimGUIScript = ${PoC:SimDir}/xSim.gui.tcl -xSimWaveformConfigFile = ${SimDir}/${TestbenchModule}.wcfg +xSimBatchScript = ${PoC:SimDir}/xSim.batch.tcl +xSimGUIScript = ${PoC:SimDir}/xSim.gui.tcl +xSimWaveformConfigFile = ${SimDir}/${TestbenchModule}.wcfg + [COCOTB.DEFAULT] -Visibility = Public -TBName = ${PoC.%{GrantParent}:Name}_${IP.%{Parent}:Name} -TopLevel = ${TBName} -TestbenchModule = ${TBName}_cocotb -FilesFile = ${TBDir}/${TBName}_tb.files -CocotbMakefile = ${PoC:SimDir}/Cocotb.Makefile +Visibility = Public +TBName = ${PoC.%{GrantParent}:Name}_${IP.%{Parent}:Name} +TopLevel = ${TBName} +TestbenchModule = ${TBName}_cocotb +FilesFile = ${TBDir}/${TBName}_tb.files +CocotbMakefile = ${PoC:SimDir}/Cocotb.Makefile # inherit directories from IP core section -SrcDir = ${IP.%{Parent}:SrcDir} -TBDir = ${IP.%{Parent}:TBDir} -SimDir = ${IP.%{Parent}:SimDir} +SrcDir = ${IP.%{Parent}:SrcDir} +TBDir = ${IP.%{Parent}:TBDir} +SimDir = ${IP.%{Parent}:SimDir} + [CG.DEFAULT] -Visibility = Public -TopLevel = ${PoC.%{GrantParent}:Name}_${IP.%{Parent}:Name} -CoreGeneratorFile = ${SrcDir}/${TopLevel}.xco -RulesFile = +Visibility = Public +TopLevel = ${PoC.%{GrantParent}:Name}_${IP.%{Parent}:Name} +CoreGeneratorFile = ${SrcDir}/${TopLevel}.xco +RulesFile = +Dependencies = # inherit directories from IP core section -RelDir = ${IP.%{Parent}:RelDir} -SrcDir = ${IP.%{Parent}:SrcDir} -NLDir = ${IP.%{Parent}:NLDir} +RelDir = ${IP.%{Parent}:RelDir} +SrcDir = ${IP.%{Parent}:SrcDir} +NLDir = ${IP.%{Parent}:NLDir} # empty task lists -PreCopyRules = -PreReplaceRules = -PostCopyRules = -PostReplaceRules = -PostDeleteRules = +PreCopyRules = +PreReplaceRules = +PostCopyRules = +PostReplaceRules = +PostDeleteRules = # Use these predefined options to override a value # ------------------------------------------------------------------------------ -DefaultRulesFile = ${SrcDir}/${IP.%{Parent}:EntityPrefix}_${IP.%{Parent}:Name}.rules -DefaultPostCopyNGC = ${SPECIAL:OutputDir}/${TopLevel}.ngc -> ${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/${TopLevel}.ngc -DefaultPostCopyVHDL = ${SPECIAL:OutputDir}/${TopLevel}.vhd -> ${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/${TopLevel}.vhdl -DefaultPostCopyNCF = ${SPECIAL:OutputDir}/${TopLevel}.ncf -> ${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/${TopLevel}.ncf +DefaultRulesFile = ${SrcDir}/${IP.%{Parent}:EntityPrefix}_${IP.%{Parent}:Name}.rules +DefaultPostCopyNGC = ${SPECIAL:OutputDir}/${TopLevel}.ngc -> ${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/${TopLevel}.ngc +DefaultPostCopyVHDL = ${SPECIAL:OutputDir}/${TopLevel}.vhd -> ${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/${TopLevel}.vhdl +DefaultPostCopyNCF = ${SPECIAL:OutputDir}/${TopLevel}.ncf -> ${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/${TopLevel}.ncf + [LSE.DEFAULT] -Visibility = Public -TopLevel = ${PoC.%{GrantParent}:Name}_${IP.%{Parent}:Name} -FilesFile = ${SrcDir}/${IP.%{Parent}:EntityPrefix}_${IP.%{Parent}:Name}.files -RulesFile = +Visibility = Public +TopLevel = ${PoC.%{GrantParent}:Name}_${IP.%{Parent}:Name} +FilesFile = ${SrcDir}/${IP.%{Parent}:EntityPrefix}_${IP.%{Parent}:Name}.files +RulesFile = +Dependencies = # inherit directories from IP core section -RelDir = ${IP.%{Parent}:RelDir} -SrcDir = ${IP.%{Parent}:SrcDir} -NLDir = ${IP.%{Parent}:NLDir} +RelDir = ${IP.%{Parent}:RelDir} +SrcDir = ${IP.%{Parent}:SrcDir} +NLDir = ${IP.%{Parent}:NLDir} # if no rules file is given, check these rules -PreCopyRules = -PreReplaceRules = -PostCopyRules = -PostReplaceRules = -PostDeleteRules = - -[QII.DEFAULT] -Visibility = Public -TopLevel = ${PoC.%{GrantParent}:Name}_${IP.%{Parent}:Name} -FilesFile = ${SrcDir}/${IP.%{Parent}:EntityPrefix}_${IP.%{Parent}:Name}.files -RulesFile = +PreCopyRules = +PreReplaceRules = +PostCopyRules = +PostReplaceRules = +PostDeleteRules = +# HDLParameter inheritance, see also IP.DEFAULT +HDLParameters = ${IP.%{Parent}:HDLParameters} + +[QMAP.DEFAULT] +Visibility = Public +TopLevel = ${PoC.%{GrantParent}:Name}_${IP.%{Parent}:Name} +FilesFile = ${SrcDir}/${IP.%{Parent}:EntityPrefix}_${IP.%{Parent}:Name}.files +RulesFile = +Dependencies = # inherit directories from IP core section -RelDir = ${IP.%{Parent}:RelDir} -SrcDir = ${IP.%{Parent}:SrcDir} -NLDir = ${IP.%{Parent}:NLDir} -QIIDir = ${IP.%{Parent}:QIIDir} +RelDir = ${IP.%{Parent}:RelDir} +SrcDir = ${IP.%{Parent}:SrcDir} +NLDir = ${IP.%{Parent}:NLDir} +QMAPDir = ${IP.%{Parent}:QMAPDir} # if no rules file is given, check these rules -PreCopyRules = -PreReplaceRules = -PostCopyRules = -PostReplaceRules = -PostDeleteRules = +PreCopyRules = +PreReplaceRules = +PostCopyRules = +PostReplaceRules = +PostDeleteRules = +# HDLParameter inheritance, see also IP.DEFAULT +HDLParameters = ${IP.%{Parent}:HDLParameters} + [XST.DEFAULT] -Visibility = Public -TopLevel = ${PoC.%{GrantParent}:Name}_${IP.%{Parent}:Name} +Visibility = Public +TopLevel = ${PoC.%{GrantParent}:Name}_${IP.%{Parent}:Name} # QUESTION: where to store these files? in src or xst dir? -# FilesFile = ${IP.%{Parent}:FilesFile} -FilesFile = ${SrcDir}/${IP.%{Parent}:EntityPrefix}_${IP.%{Parent}:Name}.files -RulesFile = -Dependencies = +# FilesFile = ${IP.%{Parent}:FilesFile} +FilesFile = ${SrcDir}/${IP.%{Parent}:EntityPrefix}_${IP.%{Parent}:Name}.files +RulesFile = +Dependencies = # Note: If a *.rules file should be used, then set its value to ${DefaultRulesFile} # inherit directories from IP core section -RelDir = ${IP.%{Parent}:RelDir} -SrcDir = ${IP.%{Parent}:SrcDir} -NLDir = ${IP.%{Parent}:NLDir} -XSTDir = ${IP.%{Parent}:XSTDir} +RelDir = ${IP.%{Parent}:RelDir} +SrcDir = ${IP.%{Parent}:SrcDir} +NLDir = ${IP.%{Parent}:NLDir} +XSTDir = ${IP.%{Parent}:XSTDir} # if no rules file is given, check these rules -PreCopyRules = -PreReplaceRules = -PostCopyRules = ${SPECIAL:OutputDir}/${TopLevel}.ngc -> ${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/${TopLevel}.ngc -PostReplaceRules = -PostDeleteRules = +PreCopyRules = +PreReplaceRules = +PostCopyRules = ${SPECIAL:OutputDir}/${TopLevel}.ngc -> ${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/${TopLevel}.ngc +PostReplaceRules = +PostDeleteRules = # Use these predefined options to override a value # ------------------------------------------------------------------------------ -DefaultRulesFile = ${XSTDir}/${IP.%{Parent}:EntityPrefix}_${IP.%{Parent}:Name}.rules -DefaultPostCopyNGC = ${SPECIAL:OutputDir}/${TopLevel}.ngc -> ${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/${TopLevel}.ngc -# DefaultPostCopyVHDL = ${SPECIAL:OutputDir}/${TopLevel}.vhd -> ${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/${TopLevel}.vhdl -# DefaultPostCopyNCF = ${SPECIAL:OutputDir}/${TopLevel}.ncf -> ${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/${TopLevel}.ncf -XSTNoConstraintsFile = ${PoC:XSTDir}/empty.xcf +DefaultRulesFile = ${XSTDir}/${IP.%{Parent}:EntityPrefix}_${IP.%{Parent}:Name}.rules +DefaultPostCopyNGC = ${SPECIAL:OutputDir}/${TopLevel}.ngc -> ${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/${TopLevel}.ngc +# DefaultPostCopyVHDL = ${SPECIAL:OutputDir}/${TopLevel}.vhd -> ${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/${TopLevel}.vhdl +# DefaultPostCopyNCF = ${SPECIAL:OutputDir}/${TopLevel}.ncf -> ${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/${TopLevel}.ncf +XSTNoConstraintsFile = ${PoC:XSTDir}/empty.xcf # Xilinx XST specific files -XSTConstraintsFile = ${XSTNoConstraintsFile} -XSTOptionsFile = ${PoC:XSTDir}/${SPECIAL:DeviceSeries}.xst -XSTFilterFile = ${PoC:XSTDir}/default.filter -# overrideable XST options -XSTOption.UseNewParser = YES -XSTOption.InputFormat = mixed -XSTOption.OutputFormat = NGC -XSTOption.OptimizationMode = Speed -XSTOption.OptimizationLevel = 2 -XSTOption.PowerReduction = NO -XSTOption.IgnoreSynthesisConstraintsFile = NO -XSTOption.KeepHierarchy = Soft -XSTOption.NetListHierarchy = As_Optimized -XSTOption.GenerateRTLView = NO -XSTOption.Globaloptimization = AllClockNets -XSTOption.ReadCores = YES -XSTOption.WriteTimingConstraints = NO -XSTOption.CrossClockAnalysis = YES -XSTOption.HierarchySeparator = / -XSTOption.BusDelimiter = <> -XSTOption.Case = Maintain -XSTOption.SliceUtilizationRatio = 100 -XSTOption.BRAMUtilizationRatio = 100 -XSTOption.DSPUtilizationRatio = 100 -XSTOption.LUTCombining = Auto -XSTOption.ReduceControlSets = Auto -XSTOption.Verilog2001 = YES -XSTOption.FSMExtract = YES -XSTOption.FSMEncoding = Auto -XSTOption.FSMSafeImplementation = NO -XSTOption.FSMStyle = LUT -XSTOption.RAMExtract = YES -XSTOption.RAMStyle = Auto -XSTOption.ROMExtract = YES -XSTOption.ROMStyle = Auto -XSTOption.MUXExtract = YES -XSTOption.MUXStyle = Auto -XSTOption.DecoderExtract = YES -XSTOption.PriorityExtract = YES -XSTOption.ShRegExtract = YES -XSTOption.ShiftExtract = YES -XSTOption.XorCollapse = YES -XSTOption.AutoBRAMPacking = NO -XSTOption.ResourceSharing = YES -XSTOption.ASyncToSync = NO -XSTOption.UseDSP48 = Auto -XSTOption.IOBuf = NO -XSTOption.MaxFanOut = 100000 -XSTOption.BufG = 32 -XSTOption.RegisterDuplication = YES -XSTOption.RegisterBalancing = NO -XSTOption.SlicePacking = YES -XSTOption.OptimizePrimitives = NO -XSTOption.UseClockEnable = Auto -XSTOption.UseSyncSet = Auto -XSTOption.UseSyncReset = Auto -XSTOption.PackIORegistersIntoIOBs = Auto -XSTOption.EquivalentRegisterRemoval = YES -XSTOption.SliceUtilizationRatioMaxMargin = 5 +XSTConstraintsFile = ${XSTNoConstraintsFile} +XSTOptionsFile = ${PoC:XSTDir}/${SPECIAL:DeviceSeries}.xst +XSTFilterFile = ${PoC:XSTDir}/default.filter +# HDLParameter inheritance, see also IP.DEFAULT +HDLParameters = ${IP.%{Parent}:HDLParameters} +# Overrideable XST options +XSTOption.UseNewParser = YES +XSTOption.InputFormat = mixed +XSTOption.OutputFormat = NGC +XSTOption.OptimizationMode = Speed +XSTOption.OptimizationLevel = 2 +XSTOption.PowerReduction = NO +XSTOption.IgnoreSynthesisConstraintsFile = NO +XSTOption.KeepHierarchy = Soft +XSTOption.NetListHierarchy = As_Optimized +XSTOption.GenerateRTLView = NO +XSTOption.Globaloptimization = AllClockNets +XSTOption.ReadCores = YES +XSTOption.WriteTimingConstraints = NO +XSTOption.CrossClockAnalysis = YES +XSTOption.HierarchySeparator = / +XSTOption.BusDelimiter = <> +XSTOption.Case = Maintain +XSTOption.SliceUtilizationRatio = 100 +XSTOption.BRAMUtilizationRatio = 100 +XSTOption.DSPUtilizationRatio = 100 +XSTOption.LUTCombining = Auto +XSTOption.ReduceControlSets = Auto +XSTOption.Verilog2001 = YES +XSTOption.FSMExtract = YES +XSTOption.FSMEncoding = Auto +XSTOption.FSMSafeImplementation = NO +XSTOption.FSMStyle = LUT +XSTOption.RAMExtract = YES +XSTOption.RAMStyle = Auto +XSTOption.ROMExtract = YES +XSTOption.ROMStyle = Auto +XSTOption.MUXExtract = YES +XSTOption.MUXStyle = Auto +XSTOption.DecoderExtract = YES +XSTOption.PriorityExtract = YES +XSTOption.ShRegExtract = YES +XSTOption.ShiftExtract = YES +XSTOption.XorCollapse = YES +XSTOption.AutoBRAMPacking = NO +XSTOption.ResourceSharing = YES +XSTOption.ASyncToSync = NO +XSTOption.UseDSP48 = Auto +XSTOption.IOBuf = NO +XSTOption.MaxFanOut = 100000 +XSTOption.BufG = 32 +XSTOption.RegisterDuplication = YES +XSTOption.RegisterBalancing = NO +XSTOption.SlicePacking = YES +XSTOption.OptimizePrimitives = NO +XSTOption.UseClockEnable = Auto +XSTOption.UseSyncSet = Auto +XSTOption.UseSyncReset = Auto +XSTOption.PackIORegistersIntoIOBs = Auto +XSTOption.EquivalentRegisterRemoval = YES +XSTOption.SliceUtilizationRatioMaxMargin = 5 + [VIVADO.DEFAULT] -Visibility = Public -TopLevel = ${PoC.%{GrantParent}:Name}_${IP.%{Parent}:Name} +Visibility = Public +TopLevel = ${PoC.%{GrantParent}:Name}_${IP.%{Parent}:Name} # QUESTION: where to store these files? in src or xst dir? -# FilesFile = ${IP.%{Parent}:FilesFile} -FilesFile = ${SrcDir}/${IP.%{Parent}:EntityPrefix}_${IP.%{Parent}:Name}.files +# FilesFile = ${IP.%{Parent}:FilesFile} +FilesFile = ${SrcDir}/${IP.%{Parent}:EntityPrefix}_${IP.%{Parent}:Name}.files RulesFile = Dependencies = # Note: If a *.rules file should be used, then set its value to ${DefaultRulesFile} # inherit directories from IP core section -RelDir = ${IP.%{Parent}:RelDir} -SrcDir = ${IP.%{Parent}:SrcDir} -NLDir = ${IP.%{Parent}:NLDir} +RelDir = ${IP.%{Parent}:RelDir} +SrcDir = ${IP.%{Parent}:SrcDir} +NLDir = ${IP.%{Parent}:NLDir} # if no rules file is given, check these rules PreCopyRules = PreReplaceRules = -PostCopyRules = ${SPECIAL:OutputDir}/${TopLevel}.dcp -> ${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/${TopLevel}.dcp +PostCopyRules = ${SPECIAL:OutputDir}/${TopLevel}.dcp -> ${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/${TopLevel}.dcp PostReplaceRules = PostDeleteRules = # Use these predefined options to override a value # ------------------------------------------------------------------------------ -DefaultRulesFile = ${XSTDir}/${IP.%{Parent}:EntityPrefix}_${IP.%{Parent}:Name}.rules -DefaultPostCopyDCP = ${SPECIAL:OutputDir}/${TopLevel}.dcp -> ${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/${TopLevel}.dcp -# DefaultPostCopyVHDL = ${SPECIAL:OutputDir}/${TopLevel}.vhd -> ${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/${TopLevel}.vhdl -# DefaultPostCopyNCF = ${SPECIAL:OutputDir}/${TopLevel}.ncf -> ${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/${TopLevel}.ncf +DefaultRulesFile = ${XSTDir}/${IP.%{Parent}:EntityPrefix}_${IP.%{Parent}:Name}.rules +DefaultPostCopyDCP = ${SPECIAL:OutputDir}/${TopLevel}.dcp -> ${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/${TopLevel}.dcp +# DefaultPostCopyVHDL = ${SPECIAL:OutputDir}/${TopLevel}.vhd -> ${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/${TopLevel}.vhdl +# DefaultPostCopyNCF = ${SPECIAL:OutputDir}/${TopLevel}.ncf -> ${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/${TopLevel}.ncf +# HDLParameter inheritance, see also IP.DEFAULT +HDLParameters = ${IP.%{Parent}:HDLParameters} +SimHDLParameters = ${IP.%{Parent}:SimHDLParameters} +SynthHDLParameters = ${IP.%{Parent}:SynthHDLParameters} + +[XCI.DEFAULT] +Visibility = Public +TopLevel = ${PoC.%{GrantParent}:Name}_${IP.%{Parent}:Name} +IPCatalogFile = ${SrcDir}/${TopLevel}.xci +RulesFile = +Dependencies = +# inherit directories from IP core section +RelDir = ${IP.%{Parent}:RelDir} +SrcDir = ${IP.%{Parent}:SrcDir} +NLDir = ${IP.%{Parent}:NLDir} + +# empty task lists +PreCopyRules = +PreReplaceRules = +PostCopyRules = +PostReplaceRules = +PostDeleteRules = +# Use these predefined options to override a value +# ------------------------------------------------------------------------------ +DefaultRulesFile = ${SrcDir}/${IP.%{Parent}:EntityPrefix}_${IP.%{Parent}:Name}.rules +DefaultPostCopyDCP = ${SPECIAL:OutputDir}/${TopLevel}.ngc -> ${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/${TopLevel}.dcp +DefaultPostCopyVHDL = ${SPECIAL:OutputDir}/${TopLevel}.vhd -> ${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/${TopLevel}.vhdl +DefaultPostCopyXDC = ${SPECIAL:OutputDir}/${TopLevel}.ncf -> ${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/${TopLevel}.xdc -[SPECIAL] -Device = ERROR -DeviceSeries = ERROR -OutputDir = ERROR +[SPECIAL] +Device = ERROR +DeviceSeries = ERROR +OutputDir = ERROR diff --git a/py/config.entity.ini b/py/config.entity.ini index b350185f..4e08e0c7 100644 --- a/py/config.entity.ini +++ b/py/config.entity.ini @@ -1,18 +1,18 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2; replace-tabs off; indent-width 2; # # ============================================================================== -# Authors: Patrick Lehmann +# Authors: Patrick Lehmann # -# Config file: Global configuration file +# Config file: Global configuration file # # Description: # ------------------------------------ -# This file defines: -# - common directory names -# - directory names for sub namespaces -# - prefixes for namespaces +# This file defines: +# - common directory names +# - directory names for sub namespaces +# - prefixes for namespaces # # License: # ============================================================================== @@ -38,13 +38,13 @@ # PoC.arith # ============================================================================== [IP.arith.addw] -Description = Adder for wide inputs -tb = VHDLTestbench +Description = Adder for wide inputs +tb = VHDLTestbench [TB.arith.addw.tb] [IP.arith.carrychain_inc] -# tb = VHDLTestbench +# tb = VHDLTestbench # [TB.arith.carrychain_inc.tb] @@ -52,10 +52,10 @@ tb = VHDLTestbench [IP.arith.counter_bcd] -tb = VHDLTestbench +tb = VHDLTestbench +HDLParameters = DIGITS=9 [TB.arith.counter_bcd.tb] [XST.arith.counter_bcd.nl] -XSTOption.Generics = DIGITS=9 [IP.arith.counter_gray] @@ -65,17 +65,17 @@ XSTOption.Generics = DIGITS=9 [IP.arith.convert_bin2bcd] -tb = VHDLTestbench +tb = VHDLTestbench [TB.arith.convert_bin2bcd.tb] [IP.arith.div] -tb = VHDLTestbench +tb = VHDLTestbench [TB.arith.div.tb] [IP.arith.firstone] -tb = VHDLTestbench +tb = VHDLTestbench [TB.arith.firstone.tb] @@ -83,41 +83,42 @@ tb = VHDLTestbench [IP.arith.prefix_and] -tb = VHDLTestbench +tb = VHDLTestbench [TB.arith.prefix_and.tb] [IP.arith.prefix_or] -tb = VHDLTestbench +tb = VHDLTestbench [TB.arith.prefix_or.tb] [IP.arith.prng] -Description = Pseudo Random Number Generator (PRNG) -tb = VHDLTestbench -nl1 = QuartusNetlist -nl2 = XSTNetlist -nl3 = LSENetlist -nl4 = VivadoNetlist +Description = Pseudo Random Number Generator (PRNG) +tb = VHDLTestbench +nl1 = QuartusNetlist +nl2 = XSTNetlist +nl3 = LSENetlist +nl4 = VivadoNetlist +HDLParameters = BITS=8 [TB.arith.prng.tb] -[QII.arith.prng.nl1] +[QMAP.arith.prng.nl1] [XST.arith.prng.nl2] -XSTOption.Generics = BITS=8 [LSE.arith.prng.nl3] [VIVADO.arith.prng.nl4] + [IP.arith.same] [IP.arith.scaler] -tb = VHDLTestbench +tb = VHDLTestbench [TB.arith.scaler.tb] [IP.arith.shifter_barrel] -nl = XSTNetlist +nl = XSTNetlist +HDLParameters = BITS=32 [XST.arith.shifter_barrel.nl] -XSTOption.Generics = BITS=32 [IP.arith.sqrt] @@ -125,7 +126,7 @@ XSTOption.Generics = BITS=32 # PoC.bus # ============================================================================== [IP.bus.Arbiter] -# tb = VHDLTestbench +# tb = VHDLTestbench # [TB.bus.Arbiter.tb] # PoC.bus.stream @@ -163,25 +164,27 @@ XSTOption.Generics = BITS=32 # PoC.cache # ============================================================================== [IP.cache.par] -cocotb = CocoTestbench -nl1 = XSTNetlist -nl2 = QuartusNetlist -nl3 = LSENetlist +cocotb = CocoTestbench +nl1 = XSTNetlist +nl2 = QuartusNetlist +nl3 = LSENetlist +nl4 = VivadoNetlist [COCOTB.cache.par.cocotb] [XST.cache.par.nl1] -[QII.cache.par.nl2] +[QMAP.cache.par.nl2] [LSE.cache.par.nl3] +[VIVADO.cache.par.nl4] [IP.cache.replacement_policy] -# tb = VHDLTestbench +# tb = VHDLTestbench # [TB.cache.replacement_policy.tb] [IP.cache.tagunit_par] -# tb = VHDLTestbench +# tb = VHDLTestbench # [TB.cache.tagunit_par.tb] [IP.cache.tagunit_seq] -# tb = VHDLTestbench +# tb = VHDLTestbench # [TB.cache.tagunit_seq.tb] # PoC.comm @@ -194,58 +197,65 @@ nl3 = LSENetlist # PoC.common # ============================================================================== [IP.common.config] -tb = VHDLTestbench +tb = VHDLTestbench [TB.common.config.tb] +TBName = ${IP.%{Parent}:Name} [IP.common.strings] -tb = VHDLTestbench +tb = VHDLTestbench [TB.common.strings.tb] +TBName = ${IP.%{Parent}:Name} + +[IP.common.physical] +tb = VHDLTestbench +[TB.common.physical.tb] +TBName = ${IP.%{Parent}:Name} # PoC.dstruct # ============================================================================== [IP.dstruct.deque] -tb = VHDLTestbench +tb = VHDLTestbench [TB.dstruct.deque.tb] [IP.dstruct.stack] -tb = VHDLTestbench +tb = VHDLTestbench [TB.dstruct.stack.tb] # PoC.fifo # ============================================================================== [IP.fifo.cc_got] -tb = VHDLTestbench +tb = VHDLTestbench [TB.fifo.cc_got.tb] [IP.fifo.cc_got_tempgot] -tb = VHDLTestbench +tb = VHDLTestbench [TB.fifo.cc_got_tempgot.tb] -Visibility = Private +Visibility = Private [IP.fifo.cc_got_tempput] -tb = VHDLTestbench +tb = VHDLTestbench [TB.fifo.cc_got_tempput.tb] [IP.fifo.dc_got] [IP.fifo.ic_got] -tb = VHDLTestbench +tb = VHDLTestbench [TB.fifo.ic_got.tb] [IP.fifo.ic_assembly] -tb = VHDLTestbench +tb = VHDLTestbench [TB.fifo.ic_assembly.tb] [IP.fifo.glue] -# tb = VHDLTestbench +# tb = VHDLTestbench # [TB.fifo.glue.tb] # PoC.io # ============================================================================== [IP.io.Debounce] -tb = VHDLTestbench +tb = VHDLTestbench [TB.io.Debounce.tb] [IP.io.7SegmentMux_BCD] @@ -255,9 +265,9 @@ tb = VHDLTestbench [IP.io.FanControl] -nl = XSTNetlist +nl = XSTNetlist +HDLParameters = CLOCK_FREQ=100MHz; ADD_INPUT_SYNCHRONIZERS=TRUE; ENABLE_TACHO=FALSE [XST.io.FanControl.nl] -XSTOption.Generics = CLOCK_FREQ=100MHz ADD_INPUT_SYNCHRONIZERS=TRUE ENABLE_TACHO=FALSE [IP.io.FrequencyCounter] @@ -273,19 +283,19 @@ XSTOption.Generics = CLOCK_FREQ=100MHz ADD_INPUT_SYNCHRONIZERS=TRUE ENABLE_TACHO # PoC.io.ddrio # ------------------------------------------------------------------------------ [IP.io.ddrio.in] -tb = VHDLTestbench +tb = VHDLTestbench [TB.io.ddrio.in.tb] [IP.io.ddrio.inout] -tb = VHDLTestbench -nl = XSTNetlist +tb = VHDLTestbench +nl = XSTNetlist +HDLParameters = BITS=2 [TB.io.ddrio.inout.tb] [XST.io.ddrio.inout.nl] -XSTConstraintsFile = ${XSTDir}/ddrio_inout.xcf -XSTOption.Generics = BITS=2 +XSTConstraintsFile = ${XSTDir}/ddrio_inout.xcf [IP.io.ddrio.out] -tb = VHDLTestbench +tb = VHDLTestbench [TB.io.ddrio.out.tb] # PoC.io.device @@ -294,16 +304,16 @@ tb = VHDLTestbench # PoC.io.iic # ------------------------------------------------------------------------------ [IP.io.iic.BusController] -Visibility = Private +Visibility = Private [IP.io.iic.Controller] -Visibility = Private -tb = VHDLTestbench +Visibility = Private +tb = VHDLTestbench [TB.io.iic.Controller.tb] [IP.io.iic.Switch_PCA9548A] -Visibility = Private +Visibility = Private # PoC.io.jtag # ------------------------------------------------------------------------------ @@ -319,12 +329,12 @@ Visibility = Private [IP.io.lcd.LCDSynchronizer] [IP.io.lcd.ChipScopeVIO] -cg = CoreGenNetlist +cg = CoreGenNetlist [CG.io.lcd.ChipScopeVIO.cg] -PostCopy.Rule = ${DefaultPostCopyNGC} - ${DefaultPostCopyVHDL} - ${DefaultPostCopyNCF} - +PostCopyRules = ${DefaultPostCopyNGC} + ${DefaultPostCopyVHDL} + ${DefaultPostCopyNCF} + # PoC.io.mdio # ------------------------------------------------------------------------------ @@ -343,7 +353,7 @@ PostCopy.Rule = ${DefaultPostCopyNGC} # PoC.io.pio # ------------------------------------------------------------------------------ [IP.io.pio.fifo] -tb = VHDLTestbench +tb = VHDLTestbench [TB.io.pio.fifo.tb] # PoC.io.pmod @@ -359,22 +369,33 @@ tb = VHDLTestbench # PoC.io.uart # ------------------------------------------------------------------------------ [IP.io.uart.rx] -tb = VHDLTestbench +tb = VHDLTestbench [TB.io.uart.rx.tb] [IP.io.uart.tx] - [IP.io.uart.fifo] -nl = XSTNetlist -[XST.io.uart.fifo.nl] -XSTOption.Generics = CLOCK_FREQ=100MHz BAUDRATE=115200Bd +nl1 = QuartusNetlist +nl2 = XSTNetlist +nl3 = VivadoNetlist +nl4 = LSENetlist +HDLParameters = CLOCK_FREQ=100MHz; BAUDRATE=115200Bd +[QMAP.io.uart.fifo.nl1] +[XST.io.uart.fifo.nl2] +[VIVADO.io.uart.fifo.nl3] +[LSE.io.uart.fifo.nl4] [IP.io.uart.ft245] # PoC.mem # ============================================================================== +# PoC.mem.ddr3 +# ------------------------------------------------------------------------------ +[IP.mem.ddr3.mem2mig_adapter_Series7] +#tb = VHDLTestbench +#[TB.mem.lut.mem2mig_adapter_Series7.tb] + # PoC.mem.is61lv # ------------------------------------------------------------------------------ @@ -384,34 +405,64 @@ XSTOption.Generics = CLOCK_FREQ=100MHz BAUDRATE=115200Bd # PoC.mem.lut # ------------------------------------------------------------------------------ [IP.mem.lut.Sine] -tb = VHDLTestbench +tb = VHDLTestbench [TB.mem.lut.Sine.tb] # PoC.mem.ocram # ------------------------------------------------------------------------------ [IP.mem.ocram.esdp] -nl = XSTNetlist -[XST.mem.ocram.esdp.nl] -XSTOption.Generics = a_bits=8 d_bits=16 +tb = VHDLTestbench +nl1 = LSENetlist +nl2 = QuartusNetlist +nl3 = XSTNetlist +nl4 = VivadoNetlist +HDLParameters = A_BITS=12; D_BITS=16 +[TB.mem.ocram.esdp.tb] +[LSE.mem.ocram.esdp.nl1] +[QMAP.mem.ocram.esdp.nl2] +[XST.mem.ocram.esdp.nl3] +[VIVADO.mem.ocram.esdp.nl4] [IP.mem.ocram.sdp] -tb = VHDLTestbench -nl = XSTNetlist +tb = VHDLTestbench +nl1 = LSENetlist +nl2 = QuartusNetlist +nl3 = XSTNetlist +nl4 = VivadoNetlist +HDLParameters = A_BITS=12; D_BITS=16 [TB.mem.ocram.sdp.tb] -[XST.mem.ocram.sdp.nl] -XSTOption.Generics = a_bits=8 d_bits=16 +[LSE.mem.ocram.sdp.nl1] +[QMAP.mem.ocram.sdp.nl2] +[XST.mem.ocram.sdp.nl3] +[VIVADO.mem.ocram.sdp.nl4] [IP.mem.ocram.sp] -nl = XSTNetlist -[XST.mem.ocram.sp.nl] -XSTOption.Generics = a_bits=8 d_bits=16 +tb = VHDLTestbench +nl1 = LSENetlist +nl2 = QuartusNetlist +nl3 = XSTNetlist +nl4 = VivadoNetlist +HDLParameters = A_BITS=12; D_BITS=16 +[TB.mem.ocram.sp.tb] +[LSE.mem.ocram.sp.nl1] +[QMAP.mem.ocram.sp.nl2] +[XST.mem.ocram.sp.nl3] +[VIVADO.mem.ocram.sp.nl4] [IP.mem.ocram.tdp] -nl = XSTNetlist -[XST.mem.ocram.tdp.nl] -XSTOption.Generics = a_bits=8 d_bits=16 +tb = VHDLTestbench +nl1 = LSENetlist +nl2 = QuartusNetlist +nl3 = XSTNetlist +nl4 = VivadoNetlist +HDLParameters = A_BITS=12; D_BITS=16 +[TB.mem.ocram.tdp.tb] +[LSE.mem.ocram.tdp.nl1] +[QMAP.mem.ocram.tdp.nl2] +[XST.mem.ocram.tdp.nl3] +[VIVADO.mem.ocram.tdp.nl4] # PoC.mem.ocrom @@ -463,81 +514,90 @@ XSTOption.Generics = a_bits=8 d_bits=16 # PoC.misc.gearbox # ------------------------------------------------------------------------------ [IP.misc.gearbox.down_cc] -tb = VHDLTestbench -nl = XSTNetlist +tb = VHDLTestbench +nl = XSTNetlist +HDLParameters = INPUT_BITS=32; OUTPUT_BITS=8; ADD_INPUT_REGISTERS=TRUE; ADD_OUTPUT_REGISTERS=TRUE [TB.misc.gearbox.down_cc.tb] [XST.misc.gearbox.down_cc.nl] -XSTConstraintsFile = ${XSTNoConstraintsFile} -XSTOption.Generics = INPUT_BITS=32 OUTPUT_BITS=8 ADD_INPUT_REGISTERS=TRUE ADD_OUTPUT_REGISTERS=TRUE +XSTConstraintsFile = ${XSTNoConstraintsFile} [IP.misc.gearbox.down_dc] -tb = VHDLTestbench -nl = XSTNetlist +tb = VHDLTestbench +nl = XSTNetlist +HDLParameters = INPUT_BITS=32; OUTPUT_BITS=8; ADD_INPUT_REGISTERS=TRUE; ADD_OUTPUT_REGISTERS=TRUE [TB.misc.gearbox.down_dc.tb] [XST.misc.gearbox.down_dc.nl] -XSTConstraintsFile = ${XSTNoConstraintsFile} -XSTOption.Generics = INPUT_BITS=32 OUTPUT_BITS=8 ADD_INPUT_REGISTERS=TRUE ADD_OUTPUT_REGISTERS=TRUE +XSTConstraintsFile = ${XSTNoConstraintsFile} [IP.misc.gearbox.up_cc] -tb = VHDLTestbench -nl = XSTNetlist +tb = VHDLTestbench +nl = XSTNetlist +HDLParameters = INPUT_BITS=8; OUTPUT_BITS=32; ADD_INPUT_REGISTERS=TRUE [TB.misc.gearbox.up_cc.tb] [XST.misc.gearbox.up_cc.nl] -XSTConstraintsFile = ${XSTNoConstraintsFile} -XSTOption.Generics = INPUT_BITS=8 OUTPUT_BITS=32 ADD_INPUT_REGISTERS=TRUE +XSTConstraintsFile = ${XSTNoConstraintsFile} [IP.misc.gearbox.up_dc] -tb = VHDLTestbench -nl = XSTNetlist +tb = VHDLTestbench +nl = XSTNetlist +HDLParameters = INPUT_BITS=8; OUTPUT_BITS=32; ADD_INPUT_REGISTERS=TRUE [TB.misc.gearbox.up_dc.tb] [XST.misc.gearbox.up_dc.nl] -XSTConstraintsFile = ${XSTNoConstraintsFile} -XSTOption.Generics = INPUT_BITS=8 OUTPUT_BITS=32 ADD_INPUT_REGISTERS=TRUE +XSTConstraintsFile = ${XSTNoConstraintsFile} # PoC.misc.stat # ------------------------------------------------------------------------------ [IP.misc.stat.Average] -tb = VHDLTestbench +tb = VHDLTestbench [TB.misc.stat.Average.tb] [IP.misc.stat.Histogram] -tb = VHDLTestbench +tb = VHDLTestbench [TB.misc.stat.Histogram.tb] [IP.misc.stat.Minimum] -tb = VHDLTestbench +tb = VHDLTestbench [TB.misc.stat.Minimum.tb] [IP.misc.stat.Maximum] -tb = VHDLTestbench +tb = VHDLTestbench [TB.misc.stat.Maximum.tb] # PoC.misc.sync # ------------------------------------------------------------------------------ [IP.misc.sync.Bits] -tb = VHDLTestbench -nl1 = QuartusNetlist -[QII.misc.sync.Bits.nl1] - +tb = VHDLTestbench +nl1 = QuartusNetlist +nl2 = XSTNetlist +nl3 = VivadoNetlist +nl4 = LSENetlist [TB.misc.sync.Bits.tb] +[QMAP.misc.sync.Bits.nl1] +[XST.misc.sync.Bits.nl2] +[VIVADO.misc.sync.Bits.nl3] +[LSE.misc.sync.Bits.nl4] [IP.misc.sync.Reset] -tb = VHDLTestbench +tb = VHDLTestbench [TB.misc.sync.Reset.tb] +[IP.misc.sync.Pulse] +# tb = VHDLTestbench +[TB.misc.sync.Pulse.tb] + [IP.misc.sync.Strobe] -tb = VHDLTestbench +tb = VHDLTestbench [TB.misc.sync.Strobe.tb] [IP.misc.sync.Vector] -tb = VHDLTestbench +tb = VHDLTestbench [TB.misc.sync.Vector.tb] [IP.misc.sync.Command] -tb = VHDLTestbench +tb = VHDLTestbench [TB.misc.sync.Command.tb] # PoC.net @@ -583,26 +643,26 @@ tb = VHDLTestbench [IP.net.eth.GEMAC_TX] [IP.net.eth.GMII_SGMII_PCS_Virtex5] -cg = CoreGenNetlist +cg = CoreGenNetlist [XST.net.eth.GMII_SGMII_PCS_Virtex5.nl] -CoreGeneratorFile = ${SrcDir}/Xilinx/Virtex5/${TopLevel}.xco -PostCopyRule = ${DefaultPostCopyNGC} - ${DefaultPostCopyVHDL} +CoreGeneratorFile = ${SrcDir}/Xilinx/Virtex5/${TopLevel}.xco +PostCopyRules = ${DefaultPostCopyNGC} + ${DefaultPostCopyVHDL} [IP.net.eth.GMII_SGMII_PCS_Virtex6] -cg = CoreGenNetlist +cg = CoreGenNetlist [XST.net.eth.GMII_SGMII_PCS_Virtex6.nl] -CoreGeneratorFile = ${SrcDir}/Xilinx/Virtex6/${TopLevel}.xco -PostCopyRule = ${DefaultPostCopyNGC} - ${DefaultPostCopyVHDL} +CoreGeneratorFile = ${SrcDir}/Xilinx/Virtex6/${TopLevel}.xco +PostCopyRules = ${DefaultPostCopyNGC} + ${DefaultPostCopyVHDL} [IP.net.eth.GMII_SGMII_PCS_Series7] -cg = CoreGenNetlist +cg = CoreGenNetlist [XST.net.eth.GMII_SGMII_PCS_Series7.nl] -CoreGeneratorFile = ${SrcDir}/Xilinx/Series7/${TopLevel}.xco -PostCopyRule = ${DefaultPostCopyNGC} - ${DefaultPostCopyVHDL} +CoreGeneratorFile = ${SrcDir}/Xilinx/Series7/${TopLevel}.xco +PostCopyRules = ${DefaultPostCopyNGC} + ${DefaultPostCopyVHDL} [IP.net.eth.PHYController] @@ -616,16 +676,16 @@ PostCopyRule = ${DefaultPostCopyNGC} # PoC.net.eth10g # ------------------------------------------------------------------------------ [IP.net.eth10g.PCS_PMA_Series7] -nl = CoreGenNetlist +nl = CoreGenNetlist [XST.net.eth10g.PCS_PMA_Series7.nl] -CoreGeneratorFile = ${SrcDir}/Xilinx/Series7/${TopLevel}.xco -PostCopyRule = ${DefaultPostCopyNGC} - ${DefaultPostCopyVHDL} - ${SPECIAL:OutputDir}/${TopLevel}/example_design/${TopLevel}_block.vhd -> ${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/${TopLevel}_block.vhdl - ${SPECIAL:OutputDir}/${TopLevel}/example_design/gtx/${TopLevel}_gtwizard_10gbaser.vhd -> ${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/${TopLevel}_gtwizard_10gbaser.vhdl - ${SPECIAL:OutputDir}/${TopLevel}/example_design/gtx/${TopLevel}_gtwizard_10gbaser_gt.vhd -> ${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/${TopLevel}_gtwizard_10gbaser_gt.vhdl -PostReplaceRule = ${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/${TopLevel}.vhdl :: "-- synthesis translate_off\n" -> "" - ${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/${TopLevel}.vhdl :: "end eth10g_PCS_PMA_Series7;\n" -> "end eth10g_PCS_PMA_Series7;\n\n-- synthesis translate_off" +CoreGeneratorFile = ${SrcDir}/Xilinx/Series7/${TopLevel}.xco +PostCopyRules = ${DefaultPostCopyNGC} + ${DefaultPostCopyVHDL} + ${SPECIAL:OutputDir}/${TopLevel}/example_design/${TopLevel}_block.vhd -> ${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/${TopLevel}_block.vhdl + ${SPECIAL:OutputDir}/${TopLevel}/example_design/gtx/${TopLevel}_gtwizard_10gbaser.vhd -> ${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/${TopLevel}_gtwizard_10gbaser.vhdl + ${SPECIAL:OutputDir}/${TopLevel}/example_design/gtx/${TopLevel}_gtwizard_10gbaser_gt.vhd -> ${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/${TopLevel}_gtwizard_10gbaser_gt.vhdl +PostReplaceRules = ${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/${TopLevel}.vhdl :: "-- synthesis translate_off\n" -> "" + ${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/${TopLevel}.vhdl :: "end eth10g_PCS_PMA_Series7;\n" -> "end eth10g_PCS_PMA_Series7;\n\n-- synthesis translate_off" # PoC.net.icmpv4 # ------------------------------------------------------------------------------ @@ -740,148 +800,85 @@ PostReplaceRule = ${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/${TopLevel}.vhdl :: [IP.net.udp.Wrapper] -# PoC.sata -# ============================================================================== -[IP.sata.TransceiverLayer] -tb = VHDLTestbench -[TB.sata.TransceiverLayer.tb] - -[IP.sata.PhysicalLayer] - - -[IP.sata.LinkLayer] - - -[IP.sata.TransportLayer] - - -[IP.sata.StreamingLayer] - - -[IP.sata.StreamingStack] -nl = XSTNetlist -[XST.sata.StreamingStack.nl] -XSTConstraintsFile = ${XSTNoConstraintsFile} -XSTOption.Generics = DEBUG=FALSE ENABLE_CHIPSCOPE=FALSE ENABLE_DEBUGPORT=FALSE REFCLOCK_FREQ=150MHz INITIAL_SATA_GENERATION=2 ALLOW_SPEED_NEGOTIATION=FALSE LOGICAL_BLOCK_SIZE=8KiB - -[IP.sata.TransceiverMonitor_ILA] -cg = CoreGenNetlist -[CG.sata.TransceiverMonitor_ILA.cg] -CoreGeneratorFile = ${SrcDir}/${TopLevel}.xco -PostCopyRule = ${DefaultPostCopyNGC} - ${DefaultPostCopyVHDL} - ${DefaultPostCopyNCF} - -[IP.sata.TransceiverLayer_ILA]] -cg = CoreGenNetlist -[CG.sata.TransceiverLayer_ILA.cg] -CoreGeneratorFile = ${SrcDir}/chipscope/${TopLevel}.xco -PostCopyRule = ${DefaultPostCopyNGC} - ${DefaultPostCopyVHDL} - ${DefaultPostCopyNCF} - -[IP.sata.PhysicalLayer_ILA]] -cg = CoreGenNetlist -[CG.sata.PhysicalLayer_ILA.cg] -CoreGeneratorFile = ${SrcDir}/chipscope/${TopLevel}.xco -PostCopyRule = ${DefaultPostCopyNGC} - ${DefaultPostCopyVHDL} - ${DefaultPostCopyNCF} - -[IP.sata.LinkLayer_ILA]] -cg = CoreGenNetlist -[CG.sata.LinkLayer_ILA.cg] -CoreGeneratorFile = ${SrcDir}/chipscope/${TopLevel}.xco -PostCopyRule = ${DefaultPostCopyNGC} - ${DefaultPostCopyVHDL} - ${DefaultPostCopyNCF} - -[IP.sata.TransportLayer_ILA]] -cg = CoreGenNetlist -[CG.sata.TransportLayer_ILA.cg] -CoreGeneratorFile = ${SrcDir}/chipscope/${TopLevel}.xco -PostCopyRule = ${DefaultPostCopyNGC} - ${DefaultPostCopyVHDL} - ${DefaultPostCopyNCF} - -[IP.sata.StreamingLayer_ILA]] -cg = CoreGenNetlist -[CG.sata.StreamingLayer_ILA.cg] -CoreGeneratorFile = ${SrcDir}/chipscope/${TopLevel}.xco -PostCopyRule = ${DefaultPostCopyNGC} - ${DefaultPostCopyVHDL} - ${DefaultPostCopyNCF} - # PoC.sim # ============================================================================== [IP.sim.ClockGenerator] -tb = VHDLTestbench +tb = VHDLTestbench [TB.sim.ClockGenerator.tb] [IP.sim.Waveform] -tb = VHDLTestbench +tb = VHDLTestbench [TB.sim.Waveform.tb] # PoC.sort # ============================================================================== [IP.sort.ExpireList] -tb = VHDLTestbench +tb = VHDLTestbench [TB.sort.ExpireList.tb] [IP.sort.InsertSort] -tb = VHDLTestbench +tb = VHDLTestbench [TB.sort.InsertSort.tb] [IP.sort.LeastFrequentlyUsed] -tb = VHDLTestbench +tb = VHDLTestbench [TB.sort.LeastFrequentlyUsed.tb] [IP.sort.lru_cache] -tb = VHDLTestbench -cocotb = CocoTestbench +tb = VHDLTestbench +cocotb = CocoTestbench [TB.sort.lru_cache.tb] [COCOTB.sort.lru_cache.cocotb] [IP.sort.lru_list] -# tb = VHDLTestbench -cocotb = CocoTestbench +# tb = VHDLTestbench +cocotb = CocoTestbench # [TB.sort.lru_list.tb] [COCOTB.sort.lru_list.cocotb] # PoC.sort.sortnet # ------------------------------------------------------------------------------ [IP.sort.sortnet.BitonicSort] -tb = VHDLTestbench -nl1 = LSENetlist -nl2 = QuartusNetlist -nl3 = XSTNetlist +tb = VHDLTestbench +nl1 = LSENetlist +nl2 = QuartusNetlist +nl3 = XSTNetlist +nl4 = VivadoNetlist +HDLParameters = INPUTS=32; KEY_BITS=32; DATA_BITS=64; PIPELINE_STAGE_AFTER=2 [TB.sort.sortnet.BitonicSort.tb] [LSE.sort.sortnet.BitonicSort.nl1] -[QII.sort.sortnet.BitonicSort.nl2] +# VHDLGenerics = INPUTS=32; KEY_BITS=33; DATA_BITS=65; PIPELINE_STAGE_AFTER=2 +[QMAP.sort.sortnet.BitonicSort.nl2] [XST.sort.sortnet.BitonicSort.nl3] -XSTOption.Generics = INPUTS=32 KEY_BITS=32 DATA_BITS=32 PIPELINE_STAGE_AFTER=2 +[VIVADO.sort.sortnet.BitonicSort.nl4] + [IP.sort.sortnet.OddEvenMergeSort] -tb = VHDLTestbench -nl1 = LSENetlist -nl2 = QuartusNetlist -nl3 = XSTNetlist +tb = VHDLTestbench +nl1 = LSENetlist +nl2 = QuartusNetlist +nl3 = XSTNetlist +nl4 = VivadoNetlist +HDLParameters = INPUTS=32; KEY_BITS=32; DATA_BITS=64; PIPELINE_STAGE_AFTER=2 [TB.sort.sortnet.OddEvenMergeSort.tb] [LSE.sort.sortnet.OddEvenMergeSort.nl1] -[QII.sort.sortnet.OddEvenMergeSort.nl2] +[QMAP.sort.sortnet.OddEvenMergeSort.nl2] [XST.sort.sortnet.OddEvenMergeSort.nl3] +[VIVADO.sort.sortnet.OddEvenMergeSort.nl4] [IP.sort.sortnet.OddEvenSort] -tb = VHDLTestbench -nl1 = LSENetlist -nl2 = QuartusNetlist -nl3 = XSTNetlist +tb = VHDLTestbench +nl1 = LSENetlist +nl2 = QuartusNetlist +nl3 = XSTNetlist +nl4 = VivadoNetlist +HDLParameters = INPUTS=32; KEY_BITS=32; DATA_BITS=64; PIPELINE_STAGE_AFTER=2 [TB.sort.sortnet.OddEvenSort.tb] [LSE.sort.sortnet.OddEvenSort.nl1] -[QII.sort.sortnet.OddEvenSort.nl2] +[QMAP.sort.sortnet.OddEvenSort.nl2] [XST.sort.sortnet.OddEvenSort.nl3] -XSTOption.Generics = INPUTS=64 KEY_BITS=32 DATA_BITS=32 PIPELINE_STAGE_AFTER=3 ADD_OUTPUT_REGISTERS=TRUE +[VIVADO.sort.sortnet.OddEvenSort.nl4] [IP.sort.sortnet.MergeSort_Streamed] @@ -891,11 +888,11 @@ XSTOption.Generics = INPUTS=64 KEY_BITS=32 DATA_BITS=32 PIPELINE_STAGE_AFTER=3 A [IP.sort.sortnet.Stream_Adapter] -tb = VHDLTestbench +tb = VHDLTestbench [TB.sort.sortnet.Stream_Adapter.tb] [IP.sort.sortnet.Stream_Adapter2] -tb = VHDLTestbench +tb = VHDLTestbench [TB.sort.sortnet.Stream_Adapter2.tb] # PoC.xil @@ -904,175 +901,175 @@ tb = VHDLTestbench [IP.xil.ChipScopeICON] -Dependencies = CG.xil.ChipScopeICON_1.cg - CG.xil.ChipScopeICON_2.cg - CG.xil.ChipScopeICON_3.cg - CG.xil.ChipScopeICON_4.cg - CG.xil.ChipScopeICON_5.cg - CG.xil.ChipScopeICON_6.cg - CG.xil.ChipScopeICON_7.cg - CG.xil.ChipScopeICON_8.cg - CG.xil.ChipScopeICON_9.cg - CG.xil.ChipScopeICON_10.cg - CG.xil.ChipScopeICON_11.cg - CG.xil.ChipScopeICON_12.cg - CG.xil.ChipScopeICON_13.cg - CG.xil.ChipScopeICON_14.cg - CG.xil.ChipScopeICON_15.cg +Dependencies = CG:PoC.xil.ChipScopeICON_1 + CG:PoC.xil.ChipScopeICON_2 + CG:PoC.xil.ChipScopeICON_3 + CG:PoC.xil.ChipScopeICON_4 + CG:PoC.xil.ChipScopeICON_5 + CG:PoC.xil.ChipScopeICON_6 + CG:PoC.xil.ChipScopeICON_7 + CG:PoC.xil.ChipScopeICON_8 + CG:PoC.xil.ChipScopeICON_9 + CG:PoC.xil.ChipScopeICON_10 + CG:PoC.xil.ChipScopeICON_11 + CG:PoC.xil.ChipScopeICON_12 + CG:PoC.xil.ChipScopeICON_13 + CG:PoC.xil.ChipScopeICON_14 + CG:PoC.xil.ChipScopeICON_15 [IP.xil.ChipScopeICON_1] -cg = CoreGenNetlist +cg = CoreGenNetlist [CG.xil.ChipScopeICON_1.cg] -CoreGeneratorFile = ${SrcDir}/${TopLevel}.xco -PostCopyRule = ${DefaultPostCopyNGC} - ${DefaultPostCopyVHDL} - ${DefaultPostCopyNCF} +CoreGeneratorFile = ${SrcDir}/${TopLevel}.xco +PostCopyRules = ${DefaultPostCopyNGC} + ${DefaultPostCopyVHDL} + ${DefaultPostCopyNCF} [IP.xil.ChipScopeICON_2] -cg = CoreGenNetlist +cg = CoreGenNetlist [CG.xil.ChipScopeICON_2.cg] -CoreGeneratorFile = ${SrcDir}/${TopLevel}.xco -PostCopyRule = ${DefaultPostCopyNGC} - ${DefaultPostCopyVHDL} - ${DefaultPostCopyNCF} +CoreGeneratorFile = ${SrcDir}/${TopLevel}.xco +PostCopyRules = ${DefaultPostCopyNGC} + ${DefaultPostCopyVHDL} + ${DefaultPostCopyNCF} [IP.xil.ChipScopeICON_3] -cg = CoreGenNetlist +cg = CoreGenNetlist [CG.xil.ChipScopeICON_3.cg] -CoreGeneratorFile = ${SrcDir}/${TopLevel}.xco -PostCopyRule = ${DefaultPostCopyNGC} - ${DefaultPostCopyVHDL} - ${DefaultPostCopyNCF} +CoreGeneratorFile = ${SrcDir}/${TopLevel}.xco +PostCopyRules = ${DefaultPostCopyNGC} + ${DefaultPostCopyVHDL} + ${DefaultPostCopyNCF} [IP.xil.ChipScopeICON_4] -cg = CoreGenNetlist +cg = CoreGenNetlist [CG.xil.ChipScopeICON_4.cg] -CoreGeneratorFile = ${SrcDir}/${TopLevel}.xco -PostCopyRule = ${DefaultPostCopyNGC} - ${DefaultPostCopyVHDL} - ${DefaultPostCopyNCF} +CoreGeneratorFile = ${SrcDir}/${TopLevel}.xco +PostCopyRules = ${DefaultPostCopyNGC} + ${DefaultPostCopyVHDL} + ${DefaultPostCopyNCF} [IP.xil.ChipScopeICON_5] -cg = CoreGenNetlist +cg = CoreGenNetlist [CG.xil.ChipScopeICON_5.cg] -CoreGeneratorFile = ${SrcDir}/${TopLevel}.xco -PostCopyRule = ${DefaultPostCopyNGC} - ${DefaultPostCopyVHDL} - ${DefaultPostCopyNCF} +CoreGeneratorFile = ${SrcDir}/${TopLevel}.xco +PostCopyRules = ${DefaultPostCopyNGC} + ${DefaultPostCopyVHDL} + ${DefaultPostCopyNCF} [IP.xil.ChipScopeICON_6] -cg = CoreGenNetlist +cg = CoreGenNetlist [CG.xil.ChipScopeICON_6.cg] -CoreGeneratorFile = ${SrcDir}/${TopLevel}.xco -PostCopyRule = ${DefaultPostCopyNGC} - ${DefaultPostCopyVHDL} - ${DefaultPostCopyNCF} +CoreGeneratorFile = ${SrcDir}/${TopLevel}.xco +PostCopyRules = ${DefaultPostCopyNGC} + ${DefaultPostCopyVHDL} + ${DefaultPostCopyNCF} [IP.xil.ChipScopeICON_7] -cg = CoreGenNetlist +cg = CoreGenNetlist [CG.xil.ChipScopeICON_7.cg] -CoreGeneratorFile = ${SrcDir}/${TopLevel}.xco -PostCopyRule = ${DefaultPostCopyNGC} - ${DefaultPostCopyVHDL} - ${DefaultPostCopyNCF} +CoreGeneratorFile = ${SrcDir}/${TopLevel}.xco +PostCopyRules = ${DefaultPostCopyNGC} + ${DefaultPostCopyVHDL} + ${DefaultPostCopyNCF} [IP.xil.ChipScopeICON_8] -cg = CoreGenNetlist +cg = CoreGenNetlist [CG.xil.ChipScopeICON_8.cg] -CoreGeneratorFile = ${SrcDir}/${TopLevel}.xco -PostCopyRule = ${DefaultPostCopyNGC} - ${DefaultPostCopyVHDL} - ${DefaultPostCopyNCF} +CoreGeneratorFile = ${SrcDir}/${TopLevel}.xco +PostCopyRules = ${DefaultPostCopyNGC} + ${DefaultPostCopyVHDL} + ${DefaultPostCopyNCF} [IP.xil.ChipScopeICON_9] -cg = CoreGenNetlist +cg = CoreGenNetlist [CG.xil.ChipScopeICON_9.cg] -CoreGeneratorFile = ${SrcDir}/${TopLevel}.xco -PostCopyRule = ${DefaultPostCopyNGC} - ${DefaultPostCopyVHDL} - ${DefaultPostCopyNCF} +CoreGeneratorFile = ${SrcDir}/${TopLevel}.xco +PostCopyRules = ${DefaultPostCopyNGC} + ${DefaultPostCopyVHDL} + ${DefaultPostCopyNCF} [IP.xil.ChipScopeICON_10] -cg = CoreGenNetlist +cg = CoreGenNetlist [CG.xil.ChipScopeICON_10.cg] -CoreGeneratorFile = ${SrcDir}/${TopLevel}.xco -PostCopyRule = ${DefaultPostCopyNGC} - ${DefaultPostCopyVHDL} - ${DefaultPostCopyNCF} +CoreGeneratorFile = ${SrcDir}/${TopLevel}.xco +PostCopyRules = ${DefaultPostCopyNGC} + ${DefaultPostCopyVHDL} + ${DefaultPostCopyNCF} [IP.xil.ChipScopeICON_11] -cg = CoreGenNetlist +cg = CoreGenNetlist [CG.xil.ChipScopeICON_11.cg] -CoreGeneratorFile = ${SrcDir}/${TopLevel}.xco -PostCopyRule = ${DefaultPostCopyNGC} - ${DefaultPostCopyVHDL} - ${DefaultPostCopyNCF} +CoreGeneratorFile = ${SrcDir}/${TopLevel}.xco +PostCopyRules = ${DefaultPostCopyNGC} + ${DefaultPostCopyVHDL} + ${DefaultPostCopyNCF} [IP.xil.ChipScopeICON_12] -cg = CoreGenNetlist +cg = CoreGenNetlist [CG.xil.ChipScopeICON_12.cg] -CoreGeneratorFile = ${SrcDir}/${TopLevel}.xco -PostCopyRule = ${DefaultPostCopyNGC} - ${DefaultPostCopyVHDL} - ${DefaultPostCopyNCF} +CoreGeneratorFile = ${SrcDir}/${TopLevel}.xco +PostCopyRules = ${DefaultPostCopyNGC} + ${DefaultPostCopyVHDL} + ${DefaultPostCopyNCF} [IP.xil.ChipScopeICON_13] -cg = CoreGenNetlist +cg = CoreGenNetlist [CG.xil.ChipScopeICON_13.cg] -CoreGeneratorFile = ${SrcDir}/${TopLevel}.xco -PostCopyRule = ${DefaultPostCopyNGC} - ${DefaultPostCopyVHDL} - ${DefaultPostCopyNCF} +CoreGeneratorFile = ${SrcDir}/${TopLevel}.xco +PostCopyRules = ${DefaultPostCopyNGC} + ${DefaultPostCopyVHDL} + ${DefaultPostCopyNCF} [IP.xil.ChipScopeICON_14] -cg = CoreGenNetlist +cg = CoreGenNetlist [CG.xil.ChipScopeICON_14.cg] -CoreGeneratorFile = ${SrcDir}/${TopLevel}.xco -PostCopyRule = ${DefaultPostCopyNGC} - ${DefaultPostCopyVHDL} - ${DefaultPostCopyNCF} +CoreGeneratorFile = ${SrcDir}/${TopLevel}.xco +PostCopyRules = ${DefaultPostCopyNGC} + ${DefaultPostCopyVHDL} + ${DefaultPostCopyNCF} [IP.xil.ChipScopeICON_15] -cg = CoreGenNetlist +cg = CoreGenNetlist [CG.xil.ChipScopeICON_15.cg] -CoreGeneratorFile = ${SrcDir}/${TopLevel}.xco -PostCopyRule = ${DefaultPostCopyNGC} - ${DefaultPostCopyVHDL} - ${DefaultPostCopyNCF} +CoreGeneratorFile = ${SrcDir}/${TopLevel}.xco +PostCopyRules = ${DefaultPostCopyNGC} + ${DefaultPostCopyVHDL} + ${DefaultPostCopyNCF} [IP.xil.ChipScopeILA_8x4k] -cg = CoreGenNetlist +cg = CoreGenNetlist [CG.xil.ChipScopeILA_8x4k.cg] -CoreGeneratorFile = ${SrcDir}/${TopLevel}.xco -PostCopyRule = ${DefaultPostCopyNGC} - ${DefaultPostCopyVHDL} - ${DefaultPostCopyNCF} +CoreGeneratorFile = ${SrcDir}/${TopLevel}.xco +PostCopyRules = ${DefaultPostCopyNGC} + ${DefaultPostCopyVHDL} + ${DefaultPostCopyNCF} [IP.xil.ChipScopeILA_8x32k] -cg = CoreGenNetlist +cg = CoreGenNetlist [CG.xil.ChipScopeILA_8x32k.cg] -CoreGeneratorFile = ${SrcDir}/${TopLevel}.xco -PostCopyRule = ${DefaultPostCopyNGC} - ${DefaultPostCopyVHDL} - ${DefaultPostCopyNCF} +CoreGeneratorFile = ${SrcDir}/${TopLevel}.xco +PostCopyRules = ${DefaultPostCopyNGC} + ${DefaultPostCopyVHDL} + ${DefaultPostCopyNCF} [IP.xil.ChipScopeILA_16x4k] -cg = CoreGenNetlist +cg = CoreGenNetlist [CG.xil.ChipScopeILA_16x4k.cg] -CoreGeneratorFile = ${SrcDir}/${TopLevel}.xco -PostCopyRule = ${DefaultPostCopyNGC} - ${DefaultPostCopyVHDL} - ${DefaultPostCopyNCF} +CoreGeneratorFile = ${SrcDir}/${TopLevel}.xco +PostCopyRules = ${DefaultPostCopyNGC} + ${DefaultPostCopyVHDL} + ${DefaultPostCopyNCF} [IP.xil.ChipScopeILA_32x4k] -cg = CoreGenNetlist +cg = CoreGenNetlist [CG.xil.ChipScopeILA_32x4k.cg] -CoreGeneratorFile = ${SrcDir}/${TopLevel}.xco -PostCopyRule = ${DefaultPostCopyNGC} - ${DefaultPostCopyVHDL} - ${DefaultPostCopyNCF} +CoreGeneratorFile = ${SrcDir}/${TopLevel}.xco +PostCopyRules = ${DefaultPostCopyNGC} + ${DefaultPostCopyVHDL} + ${DefaultPostCopyNCF} [IP.xil.ChipScopeILA_64x4k] -cg = CoreGenNetlist +cg = CoreGenNetlist [CG.xil.ChipScopeILA_64x4k.cg] -CoreGeneratorFile = ${SrcDir}/${TopLevel}.xco -PostCopyRule = ${DefaultPostCopyNGC} - ${DefaultPostCopyVHDL} - ${DefaultPostCopyNCF} +CoreGeneratorFile = ${SrcDir}/${TopLevel}.xco +PostCopyRules = ${DefaultPostCopyNGC} + ${DefaultPostCopyVHDL} + ${DefaultPostCopyNCF} [IP.xil.ChipScopeVIO_8x8] -cg = CoreGenNetlist +cg = CoreGenNetlist [CG.xil.ChipScopeVIO_8x8.cg] -CoreGeneratorFile = ${SrcDir}/${TopLevel}.xco -PostCopyRule = ${DefaultPostCopyNGC} - ${DefaultPostCopyVHDL} - ${DefaultPostCopyNCF} +CoreGeneratorFile = ${SrcDir}/${TopLevel}.xco +PostCopyRules = ${DefaultPostCopyNGC} + ${DefaultPostCopyVHDL} + ${DefaultPostCopyNCF} [IP.xil.Reconfigurator] @@ -1082,40 +1079,39 @@ PostCopyRule = ${DefaultPostCopyNGC} # PoC.xil.mig # ------------------------------------------------------------------------------ [IP.xil.mig.Atlys_1x128] -nl = XSTNetlist -cg = CoreGenNetlist +nl = XSTNetlist +cg = CoreGenNetlist # step 1: coregen [CG.xil.mig.Atlys_1x128.cg] -CoreGeneratorFile = ${SrcDir}/${TopLevel}.xco -RulesFile = ${DefaultRulesFile} +CoreGeneratorFile = ${SrcDir}/${TopLevel}.xco +RulesFile = ${DefaultRulesFile} # step 2: generate netlist [XST.xil.mig.Atlys_1x128.nl] -Dependencies = CG.xil.mig.Atlys_1x128.cg +Dependencies = CG.xil.mig.Atlys_1x128.cg # use .files file from "xst" directory -FilesFile = ${XSTDir}/${IP.%{Parent}:EntityPrefix}_${IP.%{Parent}:Name}.files -RulesFile = ${DefaultRulesFile} -XSTConstraintsFile = ${XSTDir}/${TopLevel}.xcf +FilesFile = ${XSTDir}/${IP.%{Parent}:EntityPrefix}_${IP.%{Parent}:Name}.files +RulesFile = ${DefaultRulesFile} +XSTConstraintsFile = ${XSTDir}/${TopLevel}.xcf # example for different clock and no clock buffer -#XSTOption.Generics = C3_CLKOUT2_DIVIDE=8 C3_INPUT_CLK_TYPE="NONE" +#HDLParameters = C3_CLKOUT2_DIVIDE=8; C3_INPUT_CLK_TYPE="NONE" [IP.xil.mig.KC705_MT8JTF12864HZ_1G6] -nl = XSTNetlist -cg = CoreGenNetlist +nl = XSTNetlist +cg = CoreGenNetlist # step 1: coregen [CG.xil.mig.KC705_MT8JTF12864HZ_1G6.cg] -CoreGeneratorFile = ${SrcDir}/${TopLevel}.xco -RulesFile = ${DefaultRulesFile} -tempDir = ${SPECIAL:OutputDir}/${TopLevel} -dstDir = ${PoC:NLDir}/${SPECIAL:Device}/${RelDir} +CoreGeneratorFile = ${SrcDir}/${TopLevel}.xco +RulesFile = ${DefaultRulesFile} +tempDir = ${SPECIAL:OutputDir}/${TopLevel} +dstDir = ${PoC:NLDir}/${SPECIAL:Device}/${RelDir} # step 2: generate netlist [XST.xil.mig.KC705_MT8JTF12864HZ_1G6.nl] -Dependencies = CG.xil.mig.KC705_MT8JTF12864HZ_1G6.cg +Dependencies = CG.xil.mig.KC705_MT8JTF12864HZ_1G6.cg # use .files file from "xst" directory -FilesFile = ${XSTDir}/${IP.%{Parent}:EntityPrefix}_${IP.%{Parent}:Name}.files -RulesFile = ${DefaultRulesFile} -XSTConstraintsFile = ${XSTDir}/${TopLevel}.xcf -netlistDir = ${PoC:NLDir}/${SPECIAL:Device}/${RelDir} +FilesFile = ${XSTDir}/${IP.%{Parent}:EntityPrefix}_${IP.%{Parent}:Name}.files +RulesFile = ${DefaultRulesFile} +XSTConstraintsFile = ${XSTDir}/${TopLevel}.xcf +netlistDir = ${PoC:NLDir}/${SPECIAL:Device}/${RelDir} # set TEMP_MON_CONTROL="EXTERNAL" if the temperature is supplied by an external XADC instance -XSTOption.Generics = TEMP_MON_CONTROL="INTERNAL" - +HDLParameters = TEMP_MON_CONTROL="INTERNAL" diff --git a/py/config.structure.ini b/py/config.structure.ini index 7b1a58ca..efedd020 100644 --- a/py/config.structure.ini +++ b/py/config.structure.ini @@ -1,18 +1,18 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2; replace-tabs off; indent-width 2; # # ============================================================================== -# Authors: Patrick Lehmann +# Authors: Patrick Lehmann # -# Config file: Global configuration file +# Config file: Global configuration file # # Description: # ------------------------------------ -# This file defines: -# - common directory names -# - directory names for sub namespaces -# - prefixes for namespaces +# This file defines: +# - common directory names +# - directory names for sub namespaces +# - prefixes for namespaces # # License: # ============================================================================== @@ -33,359 +33,367 @@ # ============================================================================== # [PoC] -Name = -DirectoryName = -# Path = -Prefix = -EntityPrefix = -RelDir = -SrcDir = ${INSTALL.PoC:InstallationDirectory}/${CONFIG.DirectoryNames:HDLSourceFiles} -TBDir = ${INSTALL.PoC:InstallationDirectory}/${CONFIG.DirectoryNames:TestbenchFiles} -SimDir = ${INSTALL.PoC:InstallationDirectory}/${CONFIG.DirectoryNames:SimulatorFiles} -NLDir = ${INSTALL.PoC:InstallationDirectory}/${CONFIG.DirectoryNames:NetlistFiles} -XSTDir = ${INSTALL.PoC:InstallationDirectory}/${CONFIG.DirectoryNames:ISESynthesisFiles} -QIIDir = ${INSTALL.PoC:InstallationDirectory}/${CONFIG.DirectoryNames:QuartusSynthesisFiles} -alt = Namespace -arith = Namespace -bus = Namespace -cache = Namespace -comm = Namespace -common = Namespace -dstruct = Namespace -fifo = Namespace -io = Namespace -lib = Namespace -mem = Namespace -misc = Namespace -net = Namespace -sata = Namespace -sim = Namespace -sort = Namespace -xil = Namespace +Name = +DirectoryName = +# Path = +Prefix = +EntityPrefix = +RelDir = +SrcDir = ${INSTALL.PoC:InstallationDirectory}/${CONFIG.DirectoryNames:HDLSourceFiles} +TBDir = ${INSTALL.PoC:InstallationDirectory}/${CONFIG.DirectoryNames:TestbenchFiles} +SimDir = ${INSTALL.PoC:InstallationDirectory}/${CONFIG.DirectoryNames:SimulatorFiles} +NLDir = ${INSTALL.PoC:InstallationDirectory}/${CONFIG.DirectoryNames:NetlistFiles} +XSTDir = ${INSTALL.PoC:InstallationDirectory}/${CONFIG.DirectoryNames:ISESynthesisFiles} +QMAPDir = ${INSTALL.PoC:InstallationDirectory}/${CONFIG.DirectoryNames:QuartusSynthesisFiles} +alt = Namespace +arith = Namespace +bus = Namespace +cache = Namespace +comm = Namespace +common = Namespace +dstruct = Namespace +fifo = Namespace +io = Namespace +lib = Namespace +mem = Namespace +misc = Namespace +net = Namespace +sim = Namespace +sort = Namespace +xil = Namespace [PoC.alt] [PoC.arith] -addw = Entity -carrychain_inc = Entity -convert_bin2bcd = Entity -counter_bcd = Entity -counter_free = Entity -counter_gray = Entity -counter_ring = Entity -div = Entity -firstone = Entity -muls_wide = Entity -prefix_and = Entity -prefix_or = Entity -prng = Entity -same = Entity -scaler = Entity -shifter_barrel = Entity -sqrt = Entity +addw = Entity +carrychain_inc = Entity +convert_bin2bcd = Entity +counter_bcd = Entity +counter_free = Entity +counter_gray = Entity +counter_ring = Entity +div = Entity +firstone = Entity +muls_wide = Entity +prefix_and = Entity +prefix_or = Entity +prng = Entity +same = Entity +scaler = Entity +shifter_barrel = Entity +sqrt = Entity [PoC.bus] -stream = Namespace -wb = Namespace -Arbiter = Entity +stream = Namespace +wb = Namespace +Arbiter = Entity [PoC.bus.stream] -Buffer = Entity -DeMux = Entity -FrameGenerator = Entity -Mirror = Entity -Mux = Entity -Sink = Entity -Source = Entity +Buffer = Entity +DeMux = Entity +FrameGenerator = Entity +Mirror = Entity +Mux = Entity +Sink = Entity +Source = Entity [PoC.bus.wb] -fifo_adapter = Entity -ocram_adapter = Entity -uart_wrapper = Entity +fifo_adapter = Entity +ocram_adapter = Entity +uart_wrapper = Entity [PoC.cache] -par = Entity -replacement_policy = Entity -tagunit_par = Entity -tagunit_seq = Entity +par = Entity +replacement_policy = Entity +tagunit_par = Entity +tagunit_seq = Entity [PoC.comm] -crc = Entity -scamble = Entity +crc = Entity +scamble = Entity [PoC.common] +config = Entity +strings = Entity +physical = Entity [PoC.dstruct] -deque = Entity -stack = Entity +deque = Entity +stack = Entity [PoC.fifo] -cc_got = Entity -cc_got_tempgot = Entity -cc_got_tempput = Entity -ic_assembly = Entity -ic_got = Entity -glue = Entity +cc_got = Entity +cc_got_tempgot = Entity +cc_got_tempput = Entity +ic_assembly = Entity +ic_got = Entity +glue = Entity [PoC.io] -ddrio = Namespace -device = Namespace -iic = Namespace -jtag = Namespace -lcd = Namespace -mdio = Namespace -ow = Namespace -pio = Namespace -pmod = Namespace -uart = Namespace -Debounce = Entity -7SegmentMux_BCD = Entity -7SegmentMux_HEX = Entity -FanControl = Entity -FrequencyCounter = Entity -GlitchFilter = Entity -PulseWidthModulation = Entity -TimingCounter = Entity +ddrio = Namespace +device = Namespace +iic = Namespace +jtag = Namespace +lcd = Namespace +mdio = Namespace +ow = Namespace +pio = Namespace +pmod = Namespace +uart = Namespace +Debounce = Entity +7SegmentMux_BCD = Entity +7SegmentMux_HEX = Entity +FanControl = Entity +FrequencyCounter = Entity +GlitchFilter = Entity +PulseWidthModulation = Entity +TimingCounter = Entity [PoC.io.ddrio] -in = Entity -inout = Entity -out = Entity +in = Entity +inout = Entity +out = Entity [PoC.io.device] -# DS1820Controller = Entity +# DS1820Controller = Entity [PoC.io.iic] -BusController = Entity -Controller = Entity -Switch_PCA9548A = Entity +BusController = Entity +Controller = Entity +Switch_PCA9548A = Entity [PoC.io.jtag] [PoC.io.lcd] -dotmatrix = Entity -LCDBuffer = Entity -LCDSynchronizer = Entity +dotmatrix = Entity +LCDBuffer = Entity +LCDSynchronizer = Entity [PoC.io.mdio] -IIC_Adapter = Entity -Controller = Entity +IIC_Adapter = Entity +Controller = Entity [PoC.io.ow] -BusController = Entity -Controller = Entity +BusController = Entity +Controller = Entity [PoC.io.pio] [PoC.io.pmod] -KYPD = Entity -SSD = Entity -USBUART = Entity +KYPD = Entity +SSD = Entity +USBUART = Entity [PoC.io.uart] -rx = Entity -tx = Entity -fifo = Entity -ft245 = Entity +rx = Entity +tx = Entity +fifo = Entity +ft245 = Entity [PoC.lib] [PoC.mem] -is61lv = Namespace -is61nlp = Namespace -lut = Namespace -ocram = Namespace -ocrom = Namespace -sdram = Namespace +ddr3 = Namespace +is61lv = Namespace +is61nlp = Namespace +lut = Namespace +ocram = Namespace +ocrom = Namespace +sdram = Namespace + +[PoC.mem.ddr3] +mem2mig_adapter_Series7 = Entity [PoC.mem.is61lv] [PoC.mem.is61nlp] [PoC.mem.lut] -Sine = Entity +Sine = Entity [PoC.mem.ocram] -esdp = Entity -sdp = Entity -sp = Entity -tdp = Entity +esdp = Entity +sdp = Entity +sp = Entity +tdp = Entity [PoC.mem.ocrom] -sp = Entity -dp = Entity +sp = Entity +dp = Entity [PoC.mem.sdram] -ctrl_s3esk = Entity -ctrl_de0 = Entity +ctrl_s3esk = Entity +ctrl_de0 = Entity [PoC.misc] -filter = Namespace -gearbox = Namespace -stat = Namespace -sync = Namespace -Delay = Entity -FrequencyMeasurement = Entity -PulseTrain = Entity -Sequencer = Entity -StrobeGenerator = Entity -StrobeLimiter = Entity -WorkAligner = Entity +filter = Namespace +gearbox = Namespace +stat = Namespace +sync = Namespace +Delay = Entity +FrequencyMeasurement = Entity +PulseTrain = Entity +Sequencer = Entity +StrobeGenerator = Entity +StrobeLimiter = Entity +WorkAligner = Entity [PoC.misc.filter] -and = Entity -mean = Entity -or = Entity +and = Entity +mean = Entity +or = Entity [PoC.misc.gearbox] -down_cc = Entity -down_dc = Entity -up_cc = Entity -up_dc = Entity +down_cc = Entity +down_dc = Entity +up_cc = Entity +up_dc = Entity [PoC.misc.stat] -Average = Entity -Histogram = Entity -Minimum = Entity -Maximum = Entity +Average = Entity +Histogram = Entity +Minimum = Entity +Maximum = Entity [PoC.misc.sync] -Bits = Entity -Reset = Entity -Strobe = Entity -Vector = Entity -Command = Entity +Bits = Entity +Pulse = Entity +Reset = Entity +Strobe = Entity +Vector = Entity +Command = Entity [PoC.net] -arp = Namespace -eth = Namespace -eth10g = Namespace -icmpv4 = Namespace -icmpv6 = Namespace -ipv4 = Namespace -ipv6 = Namespace -mac = Namespace -ndp = Namespace -stack = Namespace -udp = Namespace -FrameChecksum = Entity -FrameLoopback = Entity +arp = Namespace +eth = Namespace +eth10g = Namespace +icmpv4 = Namespace +icmpv6 = Namespace +ipv4 = Namespace +ipv6 = Namespace +mac = Namespace +ndp = Namespace +stack = Namespace +udp = Namespace +FrameChecksum = Entity +FrameLoopback = Entity [PoC.net.arp] -BroadCast_Receiver = Entity -BroadCast_Requester = Entity -Cache = Entity -IPPool = Entity -Tester = Entity -UniCast_Receiver = Entity -UniCast_Responder = Entity -Wrapper = Entity +BroadCast_Receiver = Entity +BroadCast_Requester = Entity +Cache = Entity +IPPool = Entity +Tester = Entity +UniCast_Receiver = Entity +UniCast_Responder = Entity +Wrapper = Entity [PoC.net.eth] -GEMAC_GMII = Entity -GEMAC_RX = Entity -GEMAC_TX = Entity -PHYController = Entity -PHYController_Marvell_88E1111 = Entity -Wrapper = Entity +GEMAC_GMII = Entity +GEMAC_RX = Entity +GEMAC_TX = Entity +PHYController = Entity +PHYController_Marvell_88E1111 = Entity +Wrapper = Entity [PoC.net.eth10g] [PoC.net.icmpv4] -RX = Entity -TX = Entity -Wrapper = Entity +RX = Entity +TX = Entity +Wrapper = Entity [PoC.net.icmpv6] -RX = Entity -TX = Entity -Wrapper = Entity +TX = Entity +RX = Entity +Wrapper = Entity [PoC.net.ipv4] -FrameLoopback = Entity -RX = Entity -TX = Entity -Wrapper = Entity +FrameLoopback = Entity +RX = Entity +TX = Entity +Wrapper = Entity [PoC.net.ipv6] -FrameLoopback = Entity -RX = Entity -TX = Entity -Wrapper = Entity +FrameLoopback = Entity +RX = Entity +TX = Entity +Wrapper = Entity [PoC.net.mac] -FrameLoopback = Entity -RX_DestMAC_Switch = Entity -RX_SrcMAC_Filter = Entity -RX_Type_Switch = Entity -TX_DestMAC_Prepender = Entity -TX_SrcMAC_Prepender = Entity -TX_Type_Prepender = Entity -Wrapper = Entity +FrameLoopback = Entity +RX_DestMAC_Switch = Entity +RX_SrcMAC_Filter = Entity +RX_Type_Switch = Entity +TX_DestMAC_Prepender = Entity +TX_SrcMAC_Prepender = Entity +TX_Type_Prepender = Entity +Wrapper = Entity [PoC.net.ndp] -DestinationCache = Entity -FSMQuery = Entity -NeighborCache = Entity -Wrapper = Entity +DestinationCache = Entity +FSMQuery = Entity +NeighborCache = Entity +Wrapper = Entity [PoC.net.stack] -MAC = Entity -IPv4 = Entity -IPv6 = Entity -UDPv4 = Entity -UDPv6 = Entity +MAC = Entity +IPv4 = Entity +IPv6 = Entity +UDPv4 = Entity +UDPv6 = Entity [PoC.net.udp] -FrameLoopback = Entity -RX = Entity -TX = Entity -Wrapper = Entity - - -[PoC.sata] -Visibility = Private -TransceiverLayer = Entity -PhysicalLayer = Entity -LinkLayer = Entity -TransportLayer = Entity -StreamingLayer = Entity -StreamingStack = Entity -TransceiverLayer_ILA = Entity -PhysicalLayer_ILA = Entity -LinkLayer_ILA = Entity -TransportLayer_ILA = Entity -StreamingLayer_ILA = Entity +FrameLoopback = Entity +RX = Entity +TX = Entity +Wrapper = Entity + [PoC.sim] [PoC.sort] -sortnet = Namespace -lru_cache = Entity -lru_list = Entity +sortnet = Namespace +lru_cache = Entity +lru_list = Entity [PoC.sort.sortnet] -BitonicSort = Entity -OddEvenSort = Entity -OddEvenMergeSort = Entity -MergeSort_Streamed = Entity -Stream_Adapter = Entity -Stream_Adapter2 = Entity -Transform = Entity +BitonicSort = Entity +OddEvenSort = Entity +OddEvenMergeSort = Entity +MergeSort_Streamed = Entity +Stream_Adapter = Entity +Stream_Adapter2 = Entity +Transform = Entity [PoC.xil] -mig = Namespace -BSCAN = Entity -ChipScopeICON = Entity -ChipScopeILA_8x4k = Entity -ChipScopeILA_8x32k = Entity -ChipScopeILA_16x4k = Entity -ChipScopeILA_32x4k = Entity -ChipScopeILA_64x4k = Entity -ChipScopeVIO_8x8 = Entity -Reconfigurator = Entity -SystemMonitor = Entity +mig = Namespace +BSCAN = Entity +ChipScopeICON = Entity +ChipScopeICON_1 = Entity +ChipScopeICON_2 = Entity +ChipScopeICON_3 = Entity +ChipScopeICON_4 = Entity +ChipScopeICON_5 = Entity +ChipScopeICON_6 = Entity +ChipScopeICON_7 = Entity +ChipScopeICON_8 = Entity +ChipScopeICON_9 = Entity +ChipScopeICON_10 = Entity +ChipScopeICON_11 = Entity +ChipScopeICON_12 = Entity +ChipScopeICON_13 = Entity +ChipScopeICON_14 = Entity +ChipScopeICON_15 = Entity +ChipScopeILA_8x4k = Entity +ChipScopeILA_8x32k = Entity +ChipScopeILA_16x4k = Entity +ChipScopeILA_32x4k = Entity +ChipScopeILA_64x4k = Entity +ChipScopeVIO_8x8 = Entity +Reconfigurator = Entity +SystemMonitor = Entity [PoC.xil.mig] -Atlys_1x128 = Entity -KC705_MT8JTF12864HZ_1G6 = Entity +Atlys_1x128 = Entity +KC705_MT8JTF12864HZ_1G6 = Entity diff --git a/py/lib/ArgParseAttributes.py b/py/lib/ArgParseAttributes.py index dffdd5d5..b883df47 100644 --- a/py/lib/ArgParseAttributes.py +++ b/py/lib/ArgParseAttributes.py @@ -1,18 +1,18 @@ # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2; replace-tabs off; indent-width 2; -# +# # ============================================================================= -# _ _ _ _ _ _ -# _ __ _ _ / \ | |_| |_ _ __(_) |__ _ _| |_ ___ +# _ _ _ _ _ _ +# _ __ _ _ / \ | |_| |_ _ __(_) |__ _ _| |_ ___ # | '_ \| | | | / _ \| __| __| '__| | '_ \| | | | __/ _ \ # | |_) | |_| |/ ___ \ |_| |_| | | | |_) | |_| | || __/ # | .__/ \__, /_/ \_\__|\__|_| |_|_.__/ \__,_|\__\___| -# |_| |___/ -# +# |_| |___/ +# # ============================================================================= # Authors: Patrick Lehmann -# +# # Python package: ArgParse pyAttribute attributes # # Description: @@ -22,13 +22,13 @@ # License: # ============================================================================ # Copyright 2007-2016 Patrick Lehmann - Dresden, Germany -# +# # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at -# +# # http://www.apache.org/licenses/LICENSE-2.0 -# +# # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -41,26 +41,26 @@ class CommandGroupAttribute(Attribute): __groupName = "" - + def __init__(self, groupName): super().__init__() self.__groupName = groupName - + @property def GroupName(self): return self.__groupName class DefaultAttribute(Attribute): __handler = None - + def __call__(self, func): self.__handler = func return super().__call__(func) - + @property def Handler(self): return self.__handler - + class CommandAttribute(Attribute): __command = "" __handler = None @@ -70,23 +70,23 @@ def __init__(self, command, **kwargs): super().__init__() self.__command = command self.__kwargs = kwargs - + def __call__(self, func): self.__handler = func return super().__call__(func) - + @property def Command(self): return self.__command - + @property def Handler(self): return self.__handler - + @property def KWArgs(self): return self.__kwargs - + class ArgumentAttribute(Attribute): __args = None __kwargs = None @@ -95,15 +95,15 @@ def __init__(self, *args, **kwargs): super().__init__() self.__args = args self.__kwargs = kwargs - + @property def Args(self): return self.__args - + @property def KWArgs(self): return self.__kwargs - + class SwitchArgumentAttribute(ArgumentAttribute): def __init__(self, *args, **kwargs): kwargs['action'] = "store_const" @@ -116,7 +116,7 @@ class CommonArgumentAttribute(ArgumentAttribute): class CommonSwitchArgumentAttribute(SwitchArgumentAttribute): pass - + class ArgParseMixin(AttributeHelperMixin): __mainParser = None __subParser = None @@ -124,49 +124,49 @@ class ArgParseMixin(AttributeHelperMixin): def __init__(self, **kwargs): super().__init__() - + # create a commandline argument parser import argparse self.__mainParser = argparse.ArgumentParser(**kwargs) self.__subParser = self.__mainParser.add_subparsers(help='sub-command help') - + for _,func in CommonArgumentAttribute.GetMethods(self): for comAttribute in CommonArgumentAttribute.GetAttributes(func): self.__mainParser.add_argument(*(comAttribute.Args), **(comAttribute.KWArgs)) - + for _,func in CommonSwitchArgumentAttribute.GetMethods(self): for comAttribute in CommonSwitchArgumentAttribute.GetAttributes(func): self.__mainParser.add_argument(*(comAttribute.Args), **(comAttribute.KWArgs)) - + for _,func in self.GetMethods(): defAttributes = DefaultAttribute.GetAttributes(func) if (len(defAttributes) != 0): defAttribute = defAttributes[0] self.__mainParser.set_defaults(func=defAttribute.Handler) continue - + cmdAttributes = CommandAttribute.GetAttributes(func) if (len(cmdAttributes) != 0): cmdAttribute = cmdAttributes[0] subParser = self.__subParser.add_parser(cmdAttribute.Command, **(cmdAttribute.KWArgs)) subParser.set_defaults(func=cmdAttribute.Handler) - + for argAttribute in ArgumentAttribute.GetAttributes(func): subParser.add_argument(*(argAttribute.Args), **(argAttribute.KWArgs)) self.__subParsers[cmdAttribute.Command] = subParser continue - + def Run(self): # parse command line options and process splitted arguments in callback functions args = self.__mainParser.parse_args() # because func is a function (unbound to an object), it MUST be called with self as a first parameter args.func(self, args) - + @property def MainParser(self): return self.__mainParser - + @property def SubParsers(self): return self.__subParsers diff --git a/py/lib/CodeDOM.py b/py/lib/CodeDOM.py new file mode 100644 index 00000000..4aa3acce --- /dev/null +++ b/py/lib/CodeDOM.py @@ -0,0 +1,632 @@ +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# +# ============================================================================== +# Authors: Patrick Lehmann +# Martin Zabel +# +# Python Module: TODO +# +# Description: +# ------------------------------------ +# TODO: +# +# License: +# ============================================================================== +# Copyright 2007-2016 Patrick Lehmann - Dresden, Germany +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================== +# +from lib.Functions import Init +from lib.Parser import MismatchingParserResult, MatchingParserResult, EmptyChoiseParserResult, GreedyMatchingParserResult +from lib.Parser import SpaceToken, CharacterToken, StringToken, NumberToken, Tokenizer + +DEBUG = False#True + +# ============================================================================== +# Base classes +# ============================================================================== +class CodeDOMMeta(type): + def parse(mcls): + result = mcls() + return result + + def GetChoiceParser(self, choices): + if DEBUG: print("init ChoiceParser") + parsers = [] + for choice in choices: + parser = choice.GetParser() + parser.send(None) + tup = (choice, parser) + parsers.append(tup) + + removeList = [] + while True: + token = yield + for parser in parsers: + try: + parser[1].send(token) + except MismatchingParserResult: + removeList.append(parser) + except MatchingParserResult as ex: + if DEBUG: print("ChoiceParser: found a matching choice") + raise ex + + for parser in removeList: + if DEBUG: print("deactivating parser for {0}".format(parser[0].__name__)) + parsers.remove(parser) + removeList.clear() + + if (len(parsers) == 0): + break + + if DEBUG: print("ChoiceParser: list of choices is empty -> no match found") + raise EmptyChoiseParserResult("ChoiceParser: ") + + def GetRepeatParser(self, callback, generator): + if DEBUG: print("init RepeatParser") + parser = generator() + parser.send(None) + + while True: + token = yield + try: + parser.send(token) + except EmptyChoiseParserResult: + break + except MismatchingParserResult: + break + except MatchingParserResult as ex: + if DEBUG: print("RepeatParser: found a statement") + callback(ex.value) + + parser = generator() + parser.send(None) + + if DEBUG: print("RepeatParser: repeat end") + raise MatchingParserResult() + + +class CodeDOMObject(metaclass=CodeDOMMeta): + def __init__(self): + super().__init__() + + @classmethod + def Parse(cls, string, printChar): + parser = cls.GetParser() + parser.send(None) + + try: + for token in Tokenizer.GetWordTokenizer(string): + if printChar: print("{BLUE}{token!s}{NOCOLOR}".format(token=token, **Init.Foreground)) + parser.send(token) + + # XXX: print("send empty token") + parser.send(None) + except MatchingParserResult as ex: + return ex.value + except MismatchingParserResult as ex: + print("ERROR: {0}".format(ex.value)) + + # print("close root parser") + # parser.close() + +# ============================================================================== +# Expressions +# ============================================================================== +class Expression(CodeDOMObject): + pass + +class UnaryExpression(Expression): + def __init__(self, child): + super().__init__() + self._child = child + + @property + def Child(self): + return self._child + +class NotExpression(UnaryExpression): + def __init__(self, child): + super().__init__(child) + + __PARSER_EXPRESSIONS__ = None + + @classmethod + def GetParser(cls): + if DEBUG: print("init NotExpressionParser") + child = None + + # match for "!" + token = yield + # if (not isinstance(token, StringToken)): raise MismatchingParserResult() + # if (token.Value != "not"): raise MismatchingParserResult() + if (not isinstance(token, CharacterToken)): raise MismatchingParserResult() + if (token.Value != "!"): raise MismatchingParserResult() + # match for optional whitespace + token = yield + if isinstance(token, SpaceToken): token = yield + + # match for sub expression + # ========================================================================== + parser = cls.__PARSER_EXPRESSIONS__.GetParser() + parser.send(None) + try: + while True: + parser.send(token) + token = yield + except MatchingParserResult as ex: + child = ex.value + + # construct result + result = cls(child) + if DEBUG: print("NotExpressionParser: matched {0}".format(result)) + raise MatchingParserResult(result) + + def __str__(self): + return "not {0}".format(self._child.__str__()) + +class BinaryExpression(Expression): + def __init__(self, leftChild, rightChild): + super().__init__() + self._leftChild = leftChild + self._rightChild = rightChild + + @property + def LeftChild(self): + return self._leftChild + + @property + def RightChild(self): + return self._rightChild + + __PARSER_NAME__ = None + __PARSER_LHS_EXPRESSIONS__ = None + __PARSER_RHS_EXPRESSIONS__ = None + __PARSER_OPERATOR__ = None + + @classmethod + def GetParser(cls): + if DEBUG: print("init " + cls.__PARSER_NAME__) + leftChild = None + rightChild = None + + # match for opening ( + token = yield + if (not isinstance(token, CharacterToken)): raise MismatchingParserResult() + if (token.Value != "("): raise MismatchingParserResult() + # match for optional whitespace + token = yield + if isinstance(token, SpaceToken): token = yield + + # match for sub expression + # ========================================================================== + parser = cls.__PARSER_LHS_EXPRESSIONS__.GetParser() + parser.send(None) + try: + while True: + parser.send(token) + token = yield + except GreedyMatchingParserResult as ex: + leftChild = ex.value + except MatchingParserResult as ex: + leftChild = ex.value + token = yield + + # match for optional whitespace + if isinstance(token, SpaceToken): token = yield + # match for operator keyword or sign(s) + if isinstance(cls.__PARSER_OPERATOR__, str): + if (not isinstance(token, StringToken)): raise MismatchingParserResult() + if (token.Value != cls.__PARSER_OPERATOR__): raise MismatchingParserResult() + token = yield + if (not isinstance(token, SpaceToken)): raise MismatchingParserResult() + token = yield + elif isinstance(cls.__PARSER_OPERATOR__, tuple): + for sign in cls.__PARSER_OPERATOR__: + if (not isinstance(token, CharacterToken)): raise MismatchingParserResult() + if (token.Value != sign): raise MismatchingParserResult() + token = yield + # match for optional whitespace + if isinstance(token, SpaceToken): token = yield + elif isinstance(cls.__PARSER_OPERATOR__, list): + for kw in cls.__PARSER_OPERATOR__[:-1]: + if (not isinstance(token, StringToken)): raise MismatchingParserResult() + if (token.Value != kw): raise MismatchingParserResult() + token = yield + if (not isinstance(token, SpaceToken)): raise MismatchingParserResult() + token = yield + kw = cls.__PARSER_OPERATOR__[-1] + if (not isinstance(token, StringToken)): raise MismatchingParserResult() + if (token.Value != kw): raise MismatchingParserResult() + token = yield + if (not isinstance(token, SpaceToken)): raise MismatchingParserResult() + token = yield + + # match for sub expression + # ========================================================================== + parser = cls.__PARSER_RHS_EXPRESSIONS__.GetParser() + parser.send(None) + try: + while True: + parser.send(token) + token = yield + except GreedyMatchingParserResult as ex: + rightChild = ex.value + except MatchingParserResult as ex: + rightChild = ex.value + token = yield + + # match for optional whitespace + if isinstance(token, SpaceToken): token = yield + # match for closing ) + if (not isinstance(token, CharacterToken)): raise MismatchingParserResult() + if (token.Value != ")"): raise MismatchingParserResult() + + # construct result + result = cls(leftChild, rightChild) + if DEBUG: print(cls.__PARSER_NAME__ + ": matched {0}".format(result)) + raise MatchingParserResult(result) + + def __str__(self): + if isinstance(self.__PARSER_OPERATOR__, tuple): op = "".join(self.__PARSER_OPERATOR__) + elif isinstance(self.__PARSER_OPERATOR__, list): op = " ".join(self.__PARSER_OPERATOR__) + else: op = self.__PARSER_OPERATOR__ + + return "({left!s} {op} {right!s})".format(left=self._leftChild, op=op, right=self._rightChild) + +class LogicalExpression(BinaryExpression): + pass + +class CompareExpression(LogicalExpression): + pass + +class EqualExpression(CompareExpression): + __PARSER_NAME__ = "EqualExpressionParser" + __PARSER_OPERATOR__ = ("=",) + + +class UnequalExpression(CompareExpression): + __PARSER_NAME__ = "UnequalExpressionParser" + __PARSER_OPERATOR__ = ("!", "=") + + +class LessThanExpression(CompareExpression): + __PARSER_NAME__ = "LessThanExpressionParser" + __PARSER_OPERATOR__ = ("<",) + + +class LessThanEqualExpression(CompareExpression): + __PARSER_NAME__ = "LessThanEqualExpressionParser" + __PARSER_OPERATOR__ = ("<", "=") + + +class GreaterThanExpression(CompareExpression): + __PARSER_NAME__ = "GreaterThanExpressionParser" + __PARSER_OPERATOR__ = (">",) + + +class GreaterThanEqualExpression(CompareExpression): + __PARSER_NAME__ = "GreaterThanEqualExpressionParser" + __PARSER_OPERATOR__ = (">", "=") + + +class AndExpression(LogicalExpression): + __PARSER_NAME__ = "AndExpressionParser" + __PARSER_OPERATOR__ = "and" + + +class OrExpression(LogicalExpression): + __PARSER_NAME__ = "OrExpressionParser" + __PARSER_OPERATOR__ = "or" + + +class XorExpression(LogicalExpression): + __PARSER_NAME__ = "XorExpressionParser" + __PARSER_OPERATOR__ = "xor" + + +class InExpression(LogicalExpression): + __PARSER_NAME__ = "InExpressionParser" + __PARSER_OPERATOR__ = "in" + + +class NotInExpression(LogicalExpression): + __PARSER_NAME__ = "NotInExpressionParser" + __PARSER_OPERATOR__ = ["not", "in"] + + +class Function(Expression): + pass + + +class ListElement(Expression): + def __init__(self): + super().__init__() + + __PARSER_LIST_ELEMENT_EXPRESSIONS__ = None + + @classmethod + def GetParser(cls): + if DEBUG: print("init ListElementParser") + + # match for EXISTS keyword + token = yield + if (not isinstance(token, CharacterToken)): raise MismatchingParserResult() + if (token.Value != ","): raise MismatchingParserResult() + # match for optional whitespace + token = yield + if isinstance(token, SpaceToken): token = yield + + parser = cls.__PARSER_LIST_ELEMENT_EXPRESSIONS__.GetParser() + parser.send(None) + + while True: + parser.send(token) + token = yield + +# ============================================================================== +# Literals +# ============================================================================== +class Literal(Expression): + pass + +class StringLiteral(Literal): + def __init__(self, value): + super().__init__() + self._value = value + + @property + def Value(self): + return self._value + + @classmethod + def GetParser(cls): + if DEBUG: print("init StringLiteralParser") + + # match for opening " + token = yield + if (not isinstance(token, CharacterToken)): raise MismatchingParserResult() + if (token.Value != "\""): raise MismatchingParserResult() + # match for string: value + value = "" + wasEscapeSign = False + while True: + token = yield + if isinstance(token, CharacterToken): + if (token.Value == "\""): + if (wasEscapeSign is True): + wasEscapeSign = False + value += "\"" + continue + else: + break + elif (token.Value == "\\"): + if (wasEscapeSign is True): + wasEscapeSign = False + value += "\\" + continue + else: + wasEscapeSign = True + continue + value += token.Value + + # construct result + result = cls(value) + if DEBUG: print("StringLiteralParser: matched {0}".format(result)) + raise MatchingParserResult(result) + + def __str__(self): + return "\"{0}\"".format(self._value) + +class IntegerLiteral(Literal): + def __init__(self, value): + super().__init__() + self._value = value + + @property + def Value(self): + return self._value + + @classmethod + def GetParser(cls): + if DEBUG: print("init IntegerLiteralParser") + + # match for opening " + token = yield + if (not isinstance(token, NumberToken)): raise MismatchingParserResult() + value = int(token.Value) + + # construct result + result = cls(value) + if DEBUG: print("IntegerLiteralParser: matched {0}".format(result)) + raise MatchingParserResult(result) + + def __str__(self): + return str(self._value) + + +class Identifier(Expression): + def __init__(self, name): + super().__init__() + self._name = name + + @property + def Name(self): + return self._name + + @classmethod + def GetParser(cls): + if DEBUG: print("init IdentifierParser") + + name = "" + while True: + token = yield + if isinstance(token, StringToken): + name += token.Value + elif isinstance(token, NumberToken): + if (name != ""): + name += token.Value + else: + raise MismatchingParserResult("IdentifierParser: Expected identifier name. Got a number.") + elif (isinstance(token, CharacterToken) and (token.Value == "_")): + name += token.Value + elif (name == ""): + raise MismatchingParserResult("IdentifierParser: Expected identifier name.") + else: + break + + # construct result + result = cls(name) + if DEBUG: print("IdentifierParser: matched {0}".format(result)) + raise GreedyMatchingParserResult(result) + + def __str__(self): + return self._name + +# ============================================================================== +# Statements +# ============================================================================== +class Statement(CodeDOMObject): + def __init__(self, commentText=""): + super().__init__() + self._commentText = commentText + + @property + def CommentText(self): return self._commentText + @CommentText.setter + def CommentText(self, value): self._commentText = value + + +class BlockStatement(Statement): + def __init__(self, commentText=""): + super().__init__(commentText) + self._statements = [] + + def AddStatement(self, stmt): + self._statements.append(stmt) + + @property + def Statements(self): + return self._statements + + def __str__(self, indent=0): + _indent = " " * indent + buffer = _indent + "BlockStatement" + for stmt in self._statements: + buffer += "\n{0}".format(stmt.__str__(indent + 1)) + return buffer + + +class ConditionalBlockStatement(BlockStatement): + def __init__(self, expression, commentText=""): + super().__init__(commentText) + self._expression = expression + + @property + def Expression(self): + return self._expression + + def __str__(self, indent=0): + _indent = " " * indent + buffer = _indent + "ConditionalBlockStatement " + self._expression.__str__() + for stmt in self._statements: + buffer += "\n{0}".format(stmt.__str__(indent + 1)) + return buffer + +# ============================================================================== +# Empty and comment lines +# ============================================================================== +class EmptyLine(CodeDOMObject): + def __init__(self): + super().__init__() + + @classmethod + def GetParser(cls): + # match for optional whitespace + token = yield + if isinstance(token, SpaceToken): token = yield + + # match for delimiter sign: \n + if (not isinstance(token, CharacterToken)): raise MismatchingParserResult() + if (token.Value.lower() != "\n"): raise MismatchingParserResult() + + # construct result + result = cls() + raise MatchingParserResult(result) + + def __str__(self, indent=0): + return " " * indent + "" + + +class CommentLine(CodeDOMObject): + def __init__(self, commentText): + super().__init__() + self._commentText = commentText + + @property + def Text(self): + return self._commentText + + @classmethod + def GetParser(cls): + # match for optional whitespace + token = yield + if isinstance(token, SpaceToken): token = yield + + # match for sign: # + if (not isinstance(token, CharacterToken)): raise MismatchingParserResult() + if (token.Value.lower() != "#"): raise MismatchingParserResult() + + # match for any until line end + commentText = "" + while True: + token = yield + if isinstance(token, CharacterToken): + if (token.Value == "\n"): break + commentText += token.Value + + # construct result + result = cls(commentText) + raise MatchingParserResult(result) + + def __str__(self, indent=0): + return "{0}#{1}".format(" " * indent, self._commentText) + +# ============================================================================== +# Forward declarations +# ============================================================================== +class BlockedStatement(CodeDOMObject): + _allowedStatements = [] + + @classmethod + def AddChoice(cls, value): + cls._allowedStatements.append(value) + + @classmethod + def GetParser(cls): + return cls.GetChoiceParser(cls._allowedStatements) + + +class ExpressionChoice(CodeDOMObject): + _allowedExpressions = [] + + @classmethod + def AddChoice(cls, value): + cls._allowedExpressions.append(value) + + @classmethod + def GetParser(cls): + return cls.GetChoiceParser(cls._allowedExpressions) diff --git a/py/lib/Decorators.py b/py/lib/Decorators.py index f0b25b4b..559263e1 100644 --- a/py/lib/Decorators.py +++ b/py/lib/Decorators.py @@ -29,16 +29,16 @@ class CachedReadOnlyProperty: def __init__(self, func): self.func = func self.__cache = None - + def __call__(self, *args): if self.__cache is None: result = self.func(*args) self.__cache = result return self.__cache - + def __repr__(self): return self.func.__doc__ - + def __get__(self, obj, _): functools.partial(self.__call__, obj) diff --git a/py/lib/Functions.py b/py/lib/Functions.py index 09a0fdce..eeee5536 100644 --- a/py/lib/Functions.py +++ b/py/lib/Functions.py @@ -1,12 +1,13 @@ # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2; replace-tabs off; indent-width 2; -# +# # ============================================================================== # Authors: Patrick Lehmann -# +# Thomas B. Preusser +# # Python functions: Auxillary functions to exit a program and report an error message. -# +# # Description: # ------------------------------------ # TODO: @@ -64,6 +65,8 @@ class Init: def init(cls): from colorama import init init() + from colorama import Back as Background + print(Background.BLACK, end="") from colorama import Fore as Foreground Foreground = { @@ -78,6 +81,7 @@ def init(cls): "DARK_CYAN": Foreground.CYAN, "GRAY": Foreground.WHITE, "DARK_GRAY": Foreground.LIGHTBLACK_EX, + "WHITE": Foreground.LIGHTWHITE_EX, "NOCOLOR": Foreground.RESET, "HEADLINE": Foreground.LIGHTMAGENTA_EX, @@ -85,7 +89,6 @@ def init(cls): "WARNING": Foreground.LIGHTYELLOW_EX } - class Exit: @classmethod def exit(cls, returnCode=0): diff --git a/py/lib/Parser.py b/py/lib/Parser.py index 1ac6044b..813cf3c3 100644 --- a/py/lib/Parser.py +++ b/py/lib/Parser.py @@ -1,12 +1,12 @@ # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2; replace-tabs off; indent-width 2; -# +# # ============================================================================== # Authors: Patrick Lehmann -# +# # Python Module: TODO -# +# # Description: # ------------------------------------ # TODO: @@ -14,13 +14,13 @@ # License: # ============================================================================== # Copyright 2007-2016 Patrick Lehmann - Dresden, Germany -# +# # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at -# +# # http://www.apache.org/licenses/LICENSE-2.0 -# +# # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -28,1471 +28,251 @@ # limitations under the License. # ============================================================================== # +from enum import Enum -DEBUG = False#True -DEBUG2 = False#True - -from enum import Enum -from colorama import Fore -from pathlib import Path class ParserException(Exception): pass -class MismatchingParserResult(StopIteration): pass -class EmptyChoiseParserResult(MismatchingParserResult): pass +class MismatchingParserResult(StopIteration): pass +class EmptyChoiseParserResult(MismatchingParserResult): pass class MatchingParserResult(StopIteration): pass +class GreedyMatchingParserResult(MatchingParserResult): pass + class SourceCodePosition: def __init__(self, row, column, absolute): - self._row = row - self._column = column - self._absolute = absolute - - @property - def Row(self): - return self._row - - @Row.setter - def Row(self, value): - self._row = value - - @property - def Column(self): - return self._column - - @Column.setter - def Column(self, value): - self._column = value - - @property - def Absolute(self): - return self._absolute - - @Absolute.setter - def Absolute(self, value): - self._absolute = value + self.Row = row + self.Column = column + self.Absolute = absolute + + def __str__(self): + return "(line: {0}, col: {1})".format(self.Row, self.Column) + class Token: - def __init__(self, previousToken, value, start, end=None): - self._previousToken = previousToken - self._value = value - self._start = start - self._end = end + def __init__(self, previousToken, start, end=None): + previousToken.NextToken = self + self._previousToken = previousToken + self.NextToken = None + self.Start = start + self.End = end def __len__(self): - return self._end.Absolute - self._start.Absolute + 1 + return self.End.Absolute - self.Start.Absolute + 1 @property def PreviousToken(self): return self._previousToken - - @property - def Value(self): - return self._value - - @property - def Start(self): - return self._start - - @property - def End(self): - return self._end - + @PreviousToken.setter + def PreviousToken(self, value): + self._previousToken = value + value.NextToken = self + + # @property + # def NextToken(self): + # return self._nextToken + # @NextToken.setter + # def NextToken(self, value): + # self._nextToken = value + @property def Length(self): return len(self) -class CharacterToken(Token): + def __str__(self): + return repr(self) + " at " + str(self.Start) + +class SuperToken(Token): + def __init__(self, startToken, endToken=None): + super().__init__(startToken.PreviousToken, startToken.Start, endToken.End if endToken else None) + self.StartToken = startToken + self.EndToken = endToken + + def __iter__(self): + token = self.StartToken + while (token is not self.EndToken): + yield token + token = token.NextToken + yield self.EndToken + +class ValuedToken(Token): + def __init__(self, previousToken, value, start, end=None): + super().__init__(previousToken, start, end) + self.Value = value + + +class StartOfDocumentToken(ValuedToken): + def __init__(self): + self._previousToken = None + self._nextToken = None + self.Value = None + self.Start = SourceCodePosition(1, 1, 1) + self.End = None + + def __len__(self): + return 0 + + def __str__(self): + return "" + + +class CharacterToken(ValuedToken): def __init__(self, previousToken, value, start): if (len(value) != 1): raise ValueError() super().__init__(previousToken, value, start=start, end=start) def __len__(self): return 1 - - def __repr(self): - if (self._value == "\r"): - return "".format(self._start.Absolute, self._start.Row, self._start.Column) - elif (self._value == "\n"): - return "".format(self._start.Absolute, self._start.Row, self._start.Column) - elif (self._value == "\t"): - return "".format(self._start.Absolute, self._start.Row, self._start.Column) - elif (self._value == " "): - return "".format(self._start.Absolute, self._start.Row, self._start.Column) - else: - return "".format(self._value, self._start.Absolute, self._start.Row, self._start.Column) - + + __CHARACTER_TRANSLATION__ = { + "\r": "CR", + "\n": "NL", + "\t": "TAB", + " ": "SPACE" + } + def __str__(self): - if (self._value == "\r"): - return "CR" - elif (self._value == "\n"): - return "NL" - elif (self._value == "\t"): - return "TAB" - elif (self._value == " "): - return "SPACE" + return "".format( + char=self.__repr__(), pos=self.Start.Absolute, line=self.Start.Row, col=self.Start.Column) + + def __repr__(self): + if (self.Value in self.__CHARACTER_TRANSLATION__): + return self.__CHARACTER_TRANSLATION__[self.Value] else: - return self._value + return self.Value + -class SpaceToken(Token): +class SpaceToken(ValuedToken): def __str__(self): - return "".format(self._value) + return "".format( + value=self.Value, pos=self.Start.Absolute, line=self.Start.Row, col=self.Start.Column) -class DelimiterToken(Token): +class DelimiterToken(ValuedToken): def __str__(self): - return "".format(self._value) + return "".format( + value=self.Value, pos=self.Start.Absolute, line=self.Start.Row, col=self.Start.Column) -class NumberToken(Token): +class NumberToken(ValuedToken): def __str__(self): - return "".format(self._value) + return "".format( + value=self.Value, pos=self.Start.Absolute, line=self.Start.Row, col=self.Start.Column) -class StringToken(Token): +class StringToken(ValuedToken): def __str__(self): - return "".format(self._value) + return "".format( + value=self.Value, pos=self.Start.Absolute, line=self.Start.Row, col=self.Start.Column) class Tokenizer: class TokenKind(Enum): SpaceChars = 0 AlphaChars = 1 - NumberChars = 2 + NumberChars = 2 DelimiterChars = 3 OtherChars = 4 @classmethod def GetCharacterTokenizer(cls, iterable): previousToken = None - absolute = 0 - column = 0 - row = 1 + absolute = 0 + column = 0 + row = 1 for char in iterable: - absolute += 1 - column += 1 + absolute += 1 + column += 1 previousToken = CharacterToken(previousToken, char, SourceCodePosition(row, column, absolute)) yield previousToken if (char == "\n"): column = 0 row += 1 - + + __ALPHA_CHARS__ = "abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ" + __NUMBER_CHARS__ = "0123456789" + __SPACE_CHARS__ = " \t" + @classmethod - def GetWordTokenizer(cls, iterable): - previousToken = None - tokenKind = cls.TokenKind.OtherChars - start = SourceCodePosition(1, 1, 1) - end = start - buffer = "" - absolute = 0 - column = 0 - row = 1 + def GetWordTokenizer(cls, iterable, alphaCharacters=__ALPHA_CHARS__, numberCharacters=__NUMBER_CHARS__, whiteSpaceCharacters=__SPACE_CHARS__): + previousToken = StartOfDocumentToken() + tokenKind = cls.TokenKind.OtherChars + start = SourceCodePosition(1, 1, 1) + buffer = "" + absolute = 0 + column = 0 + row = 1 + + yield previousToken + for char in iterable: - absolute += 1 - column += 1 - + absolute += 1 + column += 1 + if (tokenKind is cls.TokenKind.SpaceChars): - if ((char == " ") or (char == "\t")): + if (char in whiteSpaceCharacters): buffer += char else: - previousToken = SpaceToken(previousToken, buffer, start, end) + previousToken = SpaceToken(previousToken, buffer, start, SourceCodePosition(row, column, absolute)) yield previousToken - - if (char in "abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ"): - buffer = char + + start = SourceCodePosition(row, column, absolute) + buffer = char + if (char in alphaCharacters): tokenKind = cls.TokenKind.AlphaChars - elif (char in "0123456789"): - buffer = char + elif (char in numberCharacters): tokenKind = cls.TokenKind.NumberChars else: tokenKind = cls.TokenKind.OtherChars - previousToken = CharacterToken(previousToken, char, SourceCodePosition(row, column, absolute)) + previousToken = CharacterToken(previousToken, char, start) yield previousToken elif (tokenKind is cls.TokenKind.AlphaChars): - if (char in "abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ"): + if (char in alphaCharacters): buffer += char else: - previousToken = StringToken(previousToken, buffer, start, end) + previousToken = StringToken(previousToken, buffer, start, SourceCodePosition(row, column, absolute)) yield previousToken - + + start = SourceCodePosition(row, column, absolute) + buffer = char if (char in " \t"): - buffer = char tokenKind = cls.TokenKind.SpaceChars - elif (char in "0123456789"): - buffer = char + elif (char in numberCharacters): tokenKind = cls.TokenKind.NumberChars else: tokenKind = cls.TokenKind.OtherChars - previousToken = CharacterToken(previousToken, char, SourceCodePosition(row, column, absolute)) + previousToken = CharacterToken(previousToken, char, start) yield previousToken elif (tokenKind is cls.TokenKind.NumberChars): - if (char in "0123456789"): + if (char in numberCharacters): buffer += char else: - previousToken = NumberToken(previousToken, buffer, start, end) + previousToken = NumberToken(previousToken, buffer, start,SourceCodePosition(row, column, absolute)) yield previousToken - + + start = SourceCodePosition(row, column, absolute) + buffer = char if (char in " \t"): - buffer = char tokenKind = cls.TokenKind.SpaceChars - elif (char in "abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ"): - buffer = char + elif (char in alphaCharacters): tokenKind = cls.TokenKind.AlphaChars else: tokenKind = cls.TokenKind.OtherChars - previousToken = CharacterToken(previousToken, char, SourceCodePosition(row, column, absolute)) + previousToken = CharacterToken(previousToken, char, start) yield previousToken elif (tokenKind is cls.TokenKind.OtherChars): + start = SourceCodePosition(row, column, absolute) + buffer = char if (char in " \t"): - buffer = char - tokenKind = cls.TokenKind.SpaceChars - elif (char in "abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ"): - buffer = char - tokenKind = cls.TokenKind.AlphaChars - elif (char in "0123456789"): - buffer = char - tokenKind = cls.TokenKind.NumberChars + tokenKind = cls.TokenKind.SpaceChars + elif (char in alphaCharacters): + tokenKind = cls.TokenKind.AlphaChars + elif (char in numberCharacters): + tokenKind = cls.TokenKind.NumberChars else: - previousToken = CharacterToken(previousToken, char, SourceCodePosition(row, column, absolute)) + previousToken = CharacterToken(previousToken, char, start) yield previousToken else: raise ParserException("Unknown state.") - - end.Row = row - end.Column = column - end.Absolute = absolute - + if (char == "\n"): column = 0 row += 1 # end for - -class CodeDOMMeta(type): - def parse(mcls): - result = mcls() - return result - - def GetChoiceParser(self, choices): - if DEBUG: print("init ChoiceParser") - parsers = [] - for choice in choices: - # print("create parser for {0}".format(choice.__name__)) - parser = choice.GetParser() - parser.send(None) - tup = (choice, parser) - parsers.append(tup) - - removeList = [] - while True: - token = yield - for parser in parsers: - try: - parser[1].send(token) - except MismatchingParserResult as ex: - removeList.append(parser) - except MatchingParserResult as ex: - if DEBUG: print("ChoiceParser: found a matching choice") - raise ex - - for parser in removeList: - if DEBUG: print("deactivating parser for {0}".format(parser[0].__name__)) - parsers.remove(parser) - removeList.clear() - - if (len(parsers) == 0): - break - - if DEBUG: print("ChoiceParser: list of choices is empty -> no match found") - raise EmptyChoiseParserResult("ChoiceParser: ") - - def GetRepeatParser(self, callback, generator): - if DEBUG: print("init RepeatParser") - parser = generator() - parser.send(None) - - while True: - token = yield - try: - parser.send(token) - except MismatchingParserResult as ex: - break - except MatchingParserResult as ex: - if DEBUG: print("RepeatParser: found a statement") - callback(ex.value) - - parser = generator() - parser.send(None) - - if DEBUG: print("RepeatParser: repeat end") - raise MatchingParserResult() - -class CodeDOMObject(metaclass=CodeDOMMeta): - def __init__(self): - super().__init__() - # self._name = None - - # @property - # def Name(self): - # if (self._name is not None): - # return self._name - # else: - # return self.__class__.__name__ - - # @Name.setter - # def Name(self, value): - # self._name = value - - @classmethod - def parse(cls, string, printChar): - parser = cls.GetParser() - parser.send(None) - - try: - for token in Tokenizer.GetWordTokenizer(string): - if printChar: print(Fore.LIGHTBLUE_EX + str(token) + Fore.RESET) - parser.send(token) - - # XXX: print("send empty token") - parser.send(None) - except MatchingParserResult as ex: - return ex.value - except MismatchingParserResult as ex: - print("ERROR: {0}".format(ex.value)) - - # print("close root parser") - # parser.close() - -class Expressions(CodeDOMObject): - _allowedExpressions = [] - - @classmethod - def AddChoice(cls, value): - cls._allowedExpressions.append(value) - - @classmethod - def GetParser(cls): - if DEBUG: print("return ExpressionsParser") - return cls.GetChoiceParser(cls._allowedExpressions) - # parser.send(None) - - # try: - # while True: - # token = yield - # parser.send(token) - # except MatchingParserResult as ex: - # if DEBUG: print("ExpressionsParser: matched {0}".format(ex.__class__.__name__)) - # raise ex - - def __str__(self, indent=0): - _indent = " " * indent - buffer = _indent + "........." - for stmt in self._statements: - buffer += "\n{0}".format(stmt.__str__(indent + 1)) - return buffer - -class Expression(CodeDOMObject): - pass - -class Identifier(Expression): - def __init__(self, name): - super().__init__() - self._name = name - - @property - def Name(self): - return self._name - - @classmethod - def GetParser(cls): - if DEBUG: print("init IdentifierParser") - - # match for identifier name - token = yield - if DEBUG2: print("IdentifierParser: token={0} expected name".format(token)) - if (not isinstance(token, StringToken)): raise MismatchingParserResult() - name = token.Value - - # construct result - result = cls(name) - if DEBUG: print("IdentifierParser: matched {0}".format(result)) - raise MatchingParserResult(result) - - def __str__(self): - return self._name - -class Literal(Expression): - pass - -class StringLiteral(Literal): - def __init__(self, value): - super().__init__() - self._value = value - - @property - def Value(self): - return self._value - - @classmethod - def GetParser(cls): - if DEBUG: print("init StringLiteralParser") - - # match for opening " - token = yield - if DEBUG2: print("StringLiteralParser: token={0} expected '\"'".format(token)) - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult() - if (token.Value != "\""): raise MismatchingParserResult() - - # match for string value - value = "" - while True: - token = yield - if isinstance(token, CharacterToken): - if (token.Value == "\""): - break - value += token.Value - - # construct result - result = cls(value) - if DEBUG: print("StringLiteralParser: matched {0}".format(result)) - raise MatchingParserResult(result) - - def __str__(self): - return "\"{0}\"".format(self._value) - -class IntegerLiteral(Literal): - def __init__(self, value): - super().__init__() - self._value = value - - @property - def Value(self): - return self._value - - @classmethod - def GetParser(cls): - if DEBUG: print("init IntegerLiteralParser") - - # match for opening " - token = yield - if DEBUG2: print("IntegerLiteralParser: token={0} expected number".format(token)) - if (not isinstance(token, NumberToken)): raise MismatchingParserResult() - value = int(token.Value) - - # construct result - result = cls(value) - if DEBUG: print("IntegerLiteralParser: matched {0}".format(result)) - raise MatchingParserResult(result) - - def __str__(self): - return str(self._value) - -class Function(Expression): - pass - -class ExistsFunction(Function): - def __init__(self, directoryname): - super().__init__() - self._path = Path(directoryname) - - @property - def Path(self): - return self._path - - @classmethod - def GetParser(cls): - if DEBUG: print("init ExistsFunctionParser") - - # match for EXISTS keyword - token = yield - if DEBUG2: print("ExistsFunctionParser: token={0} expected '('".format(token)) - # if (not isinstance(token, StringToken)): raise MismatchingParserResult() - # if (token.Value != "exists"): raise MismatchingParserResult() - - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult() - if (token.Value != "?"): raise MismatchingParserResult() - - # match for opening ( - token = yield - if DEBUG2: print("ExistsFunctionParser: token={0} expected '('".format(token)) - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult() - if (token.Value != "("): raise MismatchingParserResult() - # match for optional whitespace - token = yield - if DEBUG2: print("ExistsFunctionParser: token={0}".format(token)) - if isinstance(token, SpaceToken): token = yield - # match for delimiter sign: " - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("ExistsFunctionParser: Expected double quote sign before VHDL fileName.") - if (token.Value.lower() != "\""): raise MismatchingParserResult("ExistsFunctionParser: Expected double quote sign before VHDL fileName.") - # match for string: path - path = "" - while True: - token = yield - if isinstance(token, CharacterToken): - if (token.Value == "\""): - break - path += token.Value - # match for optional whitespace - token = yield - if DEBUG2: print("ExistsFunctionParser: token={0}".format(token)) - if isinstance(token, SpaceToken): token = yield - # match for delimiter sign: \n - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("ExistsFunctionParser: Expected end of line or comment") - if (token.Value != ")"): raise MismatchingParserResult("ExistsFunctionParser: Expected end of line or comment") - - # construct result - result = cls(path) - if DEBUG: print("ExistsFunctionParser: matched {0}".format(result)) - raise MatchingParserResult(result) - - def __str__(self): - return "exists(\"{0!s}\")".format(self._path) - -class ListElement(Expression): - def __init__(self): - super().__init__() - - @classmethod - def GetParser(cls): - if DEBUG: print("init ListElementParser") - - # match for EXISTS keyword - token = yield - if DEBUG2: print("ListElementParser: token={0} expected '('".format(token)) - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult() - if (token.Value != ","): raise MismatchingParserResult() - # match for optional whitespace - token = yield - if DEBUG2: print("ListElementParser: token={0}".format(token)) - if isinstance(token, SpaceToken): token = yield - - parser = Expressions.GetParser() - parser.send(None) - - while True: - parser.send(token) - token = yield - -class ListConstructorExpression(Expression): - def __init__(self): - super().__init__() - self._list = [] - - @property - def List(self): - return self._list - - def AddElement(self, element): - if DEBUG2: print("ListConstructorExpression: adding element {0}".format(element)) - self._list.append(element) - - @classmethod - def GetParser(cls): - if DEBUG: print("init ListConstructorExpressionParser") - - # match for sign "[" - token = yield - if DEBUG2: print("ListConstructorExpressionParser: token={0} expected '('".format(token)) - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult() - if (token.Value != "["): raise MismatchingParserResult() - # match for optional whitespace - token = yield - if DEBUG2: print("ListConstructorExpressionParser: token={0}".format(token)) - if isinstance(token, SpaceToken): token = yield - - result = cls() - parser = Expressions.GetParser() - parser.send(None) - - try: - while True: - parser.send(token) - token = yield - except MatchingParserResult as ex: - result.AddElement(ex.value) - - parser = cls.GetRepeatParser(result.AddElement, ListElement.GetParser) - parser.send(None) - - try: - while True: - token = yield - parser.send(token) - except MatchingParserResult as ex: - pass - - # match for optional whitespace - # token = yield - if DEBUG2: print("ListConstructorExpressionParser: token={0}".format(token)) - if isinstance(token, SpaceToken): token = yield - # match for delimiter sign: \n - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult("ListConstructorExpressionParser: Expected end of line or comment") - if (token.Value != "]"): raise MismatchingParserResult("ListConstructorExpressionParser: Expected end of line or comment") - - # construct result - if DEBUG: print("ListConstructorExpressionParser: matched {0}".format(result)) - raise MatchingParserResult(result) - - def __str__(self): - buffer = "[{0}".format(self._list[0]) - for item in self._list[1:]: - buffer += ", {0}".format(item) - buffer += "]" - return buffer - -class UnaryExpression(Expression): - def __init__(self, child): - super().__init__() - self._child = child - - @property - def Child(self): - return self._child - -class NotExpression(UnaryExpression): - def __init__(self, child): - super().__init__(child) - - @classmethod - def GetParser(cls): - if DEBUG: print("init NotExpressionParser") - - # match for "!" - token = yield - if DEBUG2: print("NotExpressionParser: token={0} expected '('".format(token)) - # if (not isinstance(token, StringToken)): raise MismatchingParserResult() - # if (token.Value != "not"): raise MismatchingParserResult() - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult() - if (token.Value != "!"): raise MismatchingParserResult() - - # match for optional whitespace - token = yield - if DEBUG2: print("NotExpressionParser: token={0}".format(token)) - if isinstance(token, SpaceToken): token = yield - - # match for sub expression - # ========================================================================== - parser = Expressions.GetParser() - parser.send(None) - try: - while True: - parser.send(token) - token = yield - except MatchingParserResult as ex: - if DEBUG2: print("NotExpressionParser: matched {0} got {1}".format(ex.__class__.__name__, ex.value)) - child = ex.value - - # construct result - result = cls(child) - if DEBUG: print("NotExpressionParser: matched {0}".format(result)) - raise MatchingParserResult(result) - - def __str__(self): - return "not {0}".format(self._child.__str__()) - -class BinaryExpression(Expression): - def __init__(self, leftChild, rightChild): - super().__init__() - self._leftChild = leftChild - self._rightChild = rightChild - - @property - def LeftChild(self): - return self._leftChild - - @property - def RightChild(self): - return self._rightChild - - def __str__(self): - return "({0} ?? {1})".format(self._leftChild.__str__(), self._rightChild.__str__()) - -class LogicalExpression(BinaryExpression): - pass - -class CompareExpression(BinaryExpression): - pass - -class EqualExpression(CompareExpression): - @classmethod - def GetParser(cls): - if DEBUG: print("init EqualExpressionParser") - - # match for opening ( - token = yield - if DEBUG2: print("EqualExpressionParser: token={0} expected '('".format(token)) - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult() - if (token.Value != "("): raise MismatchingParserResult() - - # match for optional whitespace - token = yield - if DEBUG2: print("EqualExpressionParser: token={0}".format(token)) - if isinstance(token, SpaceToken): - token = yield - if DEBUG2: print("EqualExpressionParser: token={0}".format(token)) - - # match for sub expression - # ========================================================================== - parser = Expressions.GetParser() - parser.send(None) - try: - while True: - parser.send(token) - token = yield - except MatchingParserResult as ex: - if DEBUG2: print("EqualExpressionParser: matched {0} got {1}".format(ex.__class__.__name__, ex.value)) - leftChild = ex.value - - # match for optional whitespace - token = yield - if DEBUG2: print("EqualExpressionParser: token={0}".format(token)) - if isinstance(token, SpaceToken): - token = yield - if DEBUG2: print("EqualExpressionParser: token={0}".format(token)) - - # match for equal sign = - if DEBUG2: print("EqualExpressionParser: token={0} expected '='".format(token)) - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult() - if (token.Value != "="): raise MismatchingParserResult() - - # match for optional whitespace - token = yield - if DEBUG2: print("EqualExpressionParser: token={0}".format(token)) - if isinstance(token, SpaceToken): - token = yield - if DEBUG2: print("EqualExpressionParser: token={0}".format(token)) - - # match for sub expression - # ========================================================================== - parser = Expressions.GetParser() - parser.send(None) - try: - while True: - parser.send(token) - token = yield - except MatchingParserResult as ex: - if DEBUG2: print("EqualExpressionParser: matched {0} got {1}".format(ex.__class__.__name__, ex.value)) - rightChild = ex.value - - # match for optional whitespace - token = yield - if DEBUG2: print("EqualExpressionParser: token={0}".format(token)) - if isinstance(token, SpaceToken): - token = yield - if DEBUG2: print("EqualExpressionParser: token={0}".format(token)) - - # match for closing ) - if DEBUG2: print("EqualExpressionParser: token={0} expected ')'".format(token)) - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult() - if (token.Value != ")"): raise MismatchingParserResult() - - # construct result - result = cls(leftChild, rightChild) - if DEBUG: print("EqualExpressionParser: matched {0}".format(result)) - raise MatchingParserResult(result) - - def __str__(self): - return "({0} = {1})".format(self._leftChild.__str__(), self._rightChild.__str__()) - -class UnequalExpression(CompareExpression): - @classmethod - def GetParser(cls): - if DEBUG: print("init UnequalExpressionParser") - - # match for opening ( - token = yield - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult() - if (token.Value != "("): raise MismatchingParserResult() - # match for optional whitespace - token = yield - if isinstance(token, SpaceToken): token = yield - - # match for sub expression - # ========================================================================== - parser = Expressions.GetParser() - parser.send(None) - try: - while True: - parser.send(token) - token = yield - except MatchingParserResult as ex: - if DEBUG2: print("UnequalExpressionParser: matched {0} got {1}".format(ex.__class__.__name__, ex.value)) - leftChild = ex.value - - # match for optional whitespace - token = yield - if isinstance(token, SpaceToken): token = yield - # match for equal sign ! - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult() - if (token.Value != "!"): raise MismatchingParserResult() - # match for equal sign = - token = yield - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult() - if (token.Value != "="): raise MismatchingParserResult() - # match for optional whitespace - token = yield - if isinstance(token, SpaceToken): token = yield - - # match for sub expression - # ========================================================================== - parser = Expressions.GetParser() - parser.send(None) - try: - while True: - parser.send(token) - token = yield - except MatchingParserResult as ex: - if DEBUG2: print("UnequalExpressionParser: matched {0} got {1}".format(ex.__class__.__name__, ex.value)) - rightChild = ex.value - - # match for optional whitespace - token = yield - if isinstance(token, SpaceToken): token = yield - # match for closing ) - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult() - if (token.Value != ")"): raise MismatchingParserResult() - - # construct result - result = cls(leftChild, rightChild) - if DEBUG: print("UnequalExpressionParser: matched {0}".format(result)) - raise MatchingParserResult(result) - - def __str__(self): - return "({0} != {1})".format(self._leftChild.__str__(), self._rightChild.__str__()) - -class LessThanExpression(CompareExpression): - @classmethod - def GetParser(cls): - if DEBUG: print("init LessThanExpressionParser") - - # match for opening ( - token = yield - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult() - if (token.Value != "("): raise MismatchingParserResult() - # match for optional whitespace - token = yield - if isinstance(token, SpaceToken): token = yield - - # match for sub expression - # ========================================================================== - parser = Expressions.GetParser() - parser.send(None) - try: - while True: - parser.send(token) - token = yield - except MatchingParserResult as ex: - if DEBUG2: print("LessThanExpressionParser: matched {0} got {1}".format(ex.__class__.__name__, ex.value)) - leftChild = ex.value - - # match for optional whitespace - token = yield - if isinstance(token, SpaceToken): token = yield - # match for equal sign < - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult() - if (token.Value != "<"): raise MismatchingParserResult() - # match for optional whitespace - token = yield - if isinstance(token, SpaceToken): token = yield - - # match for sub expression - # ========================================================================== - parser = Expressions.GetParser() - parser.send(None) - try: - while True: - parser.send(token) - token = yield - except MatchingParserResult as ex: - if DEBUG2: print("LessThanExpressionParser: matched {0} got {1}".format(ex.__class__.__name__, ex.value)) - rightChild = ex.value - - # match for optional whitespace - token = yield - if isinstance(token, SpaceToken): token = yield - # match for closing ) - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult() - if (token.Value != ")"): raise MismatchingParserResult() - - # construct result - result = cls(leftChild, rightChild) - if DEBUG: print("LessThanExpressionParser: matched {0}".format(result)) - raise MatchingParserResult(result) - - def __str__(self): - return "({0} < {1})".format(self._leftChild.__str__(), self._rightChild.__str__()) - -class LessThanEqualExpression(CompareExpression): - @classmethod - def GetParser(cls): - if DEBUG: print("init LessThanEqualExpression") - - # match for opening ( - token = yield - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult() - if (token.Value != "("): raise MismatchingParserResult() - # match for optional whitespace - token = yield - if isinstance(token, SpaceToken): token = yield - - # match for sub expression - # ========================================================================== - parser = Expressions.GetParser() - parser.send(None) - try: - while True: - parser.send(token) - token = yield - except MatchingParserResult as ex: - if DEBUG2: print("LessThanEqualExpression: matched {0} got {1}".format(ex.__class__.__name__, ex.value)) - leftChild = ex.value - - # match for optional whitespace - token = yield - if isinstance(token, SpaceToken): token = yield - # match for equal sign < - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult() - if (token.Value != "<"): raise MismatchingParserResult() - # match for equal sign = - token = yield - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult() - if (token.Value != "="): raise MismatchingParserResult() - # match for optional whitespace - token = yield - if isinstance(token, SpaceToken): token = yield - - # match for sub expression - # ========================================================================== - parser = Expressions.GetParser() - parser.send(None) - try: - while True: - parser.send(token) - token = yield - except MatchingParserResult as ex: - if DEBUG2: print("LessThanEqualExpression: matched {0} got {1}".format(ex.__class__.__name__, ex.value)) - rightChild = ex.value - - # match for optional whitespace - token = yield - if isinstance(token, SpaceToken): token = yield - # match for closing ) - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult() - if (token.Value != ")"): raise MismatchingParserResult() - - # construct result - result = cls(leftChild, rightChild) - if DEBUG: print("LessThanEqualExpression: matched {0}".format(result)) - raise MatchingParserResult(result) - - def __str__(self): - return "({0} <= {1})".format(self._leftChild.__str__(), self._rightChild.__str__()) - -class GreaterThanExpression(CompareExpression): - @classmethod - def GetParser(cls): - if DEBUG: print("init GreaterThanExpression") - - # match for opening ( - token = yield - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult() - if (token.Value != "("): raise MismatchingParserResult() - # match for optional whitespace - token = yield - if isinstance(token, SpaceToken): token = yield - - # match for sub expression - # ========================================================================== - parser = Expressions.GetParser() - parser.send(None) - try: - while True: - parser.send(token) - token = yield - except MatchingParserResult as ex: - if DEBUG2: print("GreaterThanExpression: matched {0} got {1}".format(ex.__class__.__name__, ex.value)) - leftChild = ex.value - - # match for optional whitespace - token = yield - if isinstance(token, SpaceToken): token = yield - # match for equal sign > - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult() - if (token.Value != ">"): raise MismatchingParserResult() - # match for optional whitespace - token = yield - if isinstance(token, SpaceToken): token = yield - - # match for sub expression - # ========================================================================== - parser = Expressions.GetParser() - parser.send(None) - try: - while True: - parser.send(token) - token = yield - except MatchingParserResult as ex: - if DEBUG2: print("GreaterThanExpression: matched {0} got {1}".format(ex.__class__.__name__, ex.value)) - rightChild = ex.value - - # match for optional whitespace - token = yield - if isinstance(token, SpaceToken): token = yield - # match for closing ) - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult() - if (token.Value != ")"): raise MismatchingParserResult() - - # construct result - result = cls(leftChild, rightChild) - if DEBUG: print("GreaterThanExpression: matched {0}".format(result)) - raise MatchingParserResult(result) - - def __str__(self): - return "({0} != {1})".format(self._leftChild.__str__(), self._rightChild.__str__()) - -class GreaterThanEqualExpression(CompareExpression): - @classmethod - def GetParser(cls): - if DEBUG: print("init GreaterThanEqualExpression") - - # match for opening ( - token = yield - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult() - if (token.Value != "("): raise MismatchingParserResult() - # match for optional whitespace - token = yield - if isinstance(token, SpaceToken): token = yield - - # match for sub expression - # ========================================================================== - parser = Expressions.GetParser() - parser.send(None) - try: - while True: - parser.send(token) - token = yield - except MatchingParserResult as ex: - if DEBUG2: print("GreaterThanEqualExpression: matched {0} got {1}".format(ex.__class__.__name__, ex.value)) - leftChild = ex.value - - # match for optional whitespace - token = yield - if isinstance(token, SpaceToken): token = yield - # match for equal sign > - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult() - if (token.Value != ">"): raise MismatchingParserResult() - # match for equal sign = - token = yield - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult() - if (token.Value != "="): raise MismatchingParserResult() - # match for optional whitespace - token = yield - if isinstance(token, SpaceToken): token = yield - - # match for sub expression - # ========================================================================== - parser = Expressions.GetParser() - parser.send(None) - try: - while True: - parser.send(token) - token = yield - except MatchingParserResult as ex: - if DEBUG2: print("GreaterThanEqualExpression: matched {0} got {1}".format(ex.__class__.__name__, ex.value)) - rightChild = ex.value - - # match for optional whitespace - token = yield - if isinstance(token, SpaceToken): token = yield - # match for closing ) - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult() - if (token.Value != ")"): raise MismatchingParserResult() - - # construct result - result = cls(leftChild, rightChild) - if DEBUG: print("GreaterThanEqualExpression: matched {0}".format(result)) - raise MatchingParserResult(result) - - def __str__(self): - return "({0} >= {1})".format(self._leftChild.__str__(), self._rightChild.__str__()) - -class AndExpression(LogicalExpression): - @classmethod - def GetParser(cls): - if DEBUG: print("init AndExpressionParser") - - # match for opening ( - token = yield - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult() - if (token.Value != "("): raise MismatchingParserResult() - # match for optional whitespace - token = yield - if isinstance(token, SpaceToken): token = yield - - # match for sub expression - # ========================================================================== - parser = Expressions.GetParser() - parser.send(None) - try: - while True: - parser.send(token) - token = yield - except MatchingParserResult as ex: - if DEBUG2: print("AndExpressionParser: matched {0} got {1}".format(ex.__class__.__name__, ex.value)) - leftChild = ex.value - - # match for whitespace - token = yield - if (not isinstance(token, SpaceToken)): raise MismatchingParserResult() - # match for AND keyword - token = yield - if (not isinstance(token, StringToken)): raise MismatchingParserResult() - if (token.Value.lower() != "and"): raise MismatchingParserResult() - # match for whitespace - token = yield - if (not isinstance(token, SpaceToken)): raise MismatchingParserResult() - - # match for sub expression - # ========================================================================== - parser = Expressions.GetParser() - parser.send(None) - try: - while True: - token = yield - parser.send(token) - except MatchingParserResult as ex: - if DEBUG2: print("AndExpressionParser: matched {0} got {1}".format(ex.__class__.__name__, ex.value)) - rightChild = ex.value - - # match for optional whitespace - token = yield - if isinstance(token, SpaceToken): token = yield - # match for closing ) - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult() - if (token.Value != ")"): raise MismatchingParserResult() - - # construct result - result = cls(leftChild, rightChild) - if DEBUG: print("AndExpressionParser: matched {0}".format(result)) - raise MatchingParserResult(result) - - def __str__(self): - return "({0} and {1})".format(self._leftChild.__str__(), self._rightChild.__str__()) - -class OrExpression(LogicalExpression): - @classmethod - def GetParser(cls): - if DEBUG: print("init OrExpressionParser") - - # match for opening ( - token = yield - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult() - if (token.Value != "("): raise MismatchingParserResult() - # match for optional whitespace - token = yield - if isinstance(token, SpaceToken): token = yield - - # match for sub expression - # ========================================================================== - parser = Expressions.GetParser() - parser.send(None) - try: - while True: - parser.send(token) - token = yield - except MatchingParserResult as ex: - if DEBUG2: print("OrExpressionParser: matched {0} got {1}".format(ex.__class__.__name__, ex.value)) - leftChild = ex.value - - # match for whitespace - token = yield - if (not isinstance(token, SpaceToken)): raise MismatchingParserResult() - # match for OR keyword - token = yield - if (not isinstance(token, StringToken)): raise MismatchingParserResult() - if (token.Value.lower() != "or"): raise MismatchingParserResult() - # match for whitespace - token = yield - if (not isinstance(token, SpaceToken)): raise MismatchingParserResult() - - # match for sub expression - # ========================================================================== - parser = Expressions.GetParser() - parser.send(None) - try: - while True: - token = yield - parser.send(token) - except MatchingParserResult as ex: - if DEBUG2: print("OrExpressionParser: matched {0} got {1}".format(ex.__class__.__name__, ex.value)) - rightChild = ex.value - - # match for optional whitespace - token = yield - if isinstance(token, SpaceToken): token = yield - # match for closing ) - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult() - if (token.Value != ")"): raise MismatchingParserResult() - - # construct result - result = cls(leftChild, rightChild) - if DEBUG: print("OrExpressionParser: matched {0}".format(result)) - raise MatchingParserResult(result) - - def __str__(self): - return "({0} or {1})".format(self._leftChild.__str__(), self._rightChild.__str__()) - -class XorExpression(LogicalExpression): - @classmethod - def GetParser(cls): - if DEBUG: print("init XorExpressionParser") - - # match for opening ( - token = yield - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult() - if (token.Value != "("): raise MismatchingParserResult() - # match for optional whitespace - token = yield - if isinstance(token, SpaceToken): token = yield - - # match for sub expression - # ========================================================================== - parser = Expressions.GetParser() - parser.send(None) - try: - while True: - parser.send(token) - token = yield - except MatchingParserResult as ex: - if DEBUG2: print("XorExpression: matched {0} got {1}".format(ex.__class__.__name__, ex.value)) - leftChild = ex.value - - # match for whitespace - token = yield - if (not isinstance(token, SpaceToken)): raise MismatchingParserResult() - # match for XOR keyword - token = yield - if (not isinstance(token, StringToken)): raise MismatchingParserResult() - if (token.Value.lower() != "xor"): raise MismatchingParserResult() - # match for whitespace - token = yield - if (not isinstance(token, SpaceToken)): raise MismatchingParserResult() - - # match for sub expression - # ========================================================================== - parser = Expressions.GetParser() - parser.send(None) - try: - while True: - token = yield - parser.send(token) - except MatchingParserResult as ex: - if DEBUG2: print("XorExpression: matched {0} got {1}".format(ex.__class__.__name__, ex.value)) - rightChild = ex.value - - # match for optional whitespace - token = yield - if isinstance(token, SpaceToken): token = yield - # match for closing ) - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult() - if (token.Value != ")"): raise MismatchingParserResult() - - # construct result - result = cls(leftChild, rightChild) - if DEBUG: print("XorExpressionParser: matched {0}".format(result)) - raise MatchingParserResult(result) - - def __str__(self): - return "({0} xor {1})".format(self._leftChild.__str__(), self._rightChild.__str__()) - -class InExpression(LogicalExpression): - @classmethod - def GetParser(cls): - if DEBUG: print("init InExpressionParser") - - # match for opening ( - token = yield - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult() - if (token.Value != "("): raise MismatchingParserResult() - # match for optional whitespace - token = yield - if isinstance(token, SpaceToken): token = yield - - # match for sub expression - # ========================================================================== - parser = Expressions.GetParser() - parser.send(None) - try: - while True: - parser.send(token) - token = yield - except MatchingParserResult as ex: - if DEBUG2: print("InExpressionParser: matched {0} got {1}".format(ex.__class__.__name__, ex.value)) - leftChild = ex.value - - # match for whitespace - token = yield - if (not isinstance(token, SpaceToken)): raise MismatchingParserResult() - # match for IN keyword - token = yield - if (not isinstance(token, StringToken)): raise MismatchingParserResult() - if (token.Value.lower() != "in"): raise MismatchingParserResult() - # match for whitespace - token = yield - if (not isinstance(token, SpaceToken)): raise MismatchingParserResult() - - # match for sub expression - # ========================================================================== - parser = ListConstructorExpression.GetParser() - parser.send(None) - try: - while True: - token = yield - parser.send(token) - except MatchingParserResult as ex: - if DEBUG2: print("InExpressionParser: matched {0} got {1}".format(ex.__class__.__name__, ex.value)) - rightChild = ex.value - - # match for optional whitespace - token = yield - if isinstance(token, SpaceToken): token = yield - # match for closing ) - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult() - if (token.Value != ")"): raise MismatchingParserResult() - - # construct result - result = cls(leftChild, rightChild) - if DEBUG: print("InExpressionParser: matched {0}".format(result)) - raise MatchingParserResult(result) - - def __str__(self): - return "({0} in {1})".format(self._leftChild.__str__(), self._rightChild.__str__()) - -class NotInExpression(LogicalExpression): - @classmethod - def GetParser(cls): - if DEBUG: print("init NotInExpressionParser") - - # match for opening ( - token = yield - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult() - if (token.Value != "("): raise MismatchingParserResult() - # match for optional whitespace - token = yield - if isinstance(token, SpaceToken): token = yield - - # match for sub expression - # ========================================================================== - parser = Expressions.GetParser() - parser.send(None) - try: - while True: - parser.send(token) - token = yield - except MatchingParserResult as ex: - if DEBUG2: print("NotInExpressionParser: matched {0} got {1}".format(ex.__class__.__name__, ex.value)) - leftChild = ex.value - - # match for whitespace - token = yield - if (not isinstance(token, SpaceToken)): raise MismatchingParserResult() - # match for NOT keyword - token = yield - if (not isinstance(token, StringToken)): raise MismatchingParserResult() - if (token.Value.lower() != "not"): raise MismatchingParserResult() - # match for whitespace - token = yield - if (not isinstance(token, SpaceToken)): raise MismatchingParserResult() - # match for IN keyword - token = yield - if (not isinstance(token, StringToken)): raise MismatchingParserResult() - if (token.Value.lower() != "in"): raise MismatchingParserResult() - # match for whitespace - token = yield - if (not isinstance(token, SpaceToken)): raise MismatchingParserResult() - - # match for sub expression - # ========================================================================== - parser = ListConstructorExpression.GetParser() - parser.send(None) - try: - while True: - token = yield - parser.send(token) - except MatchingParserResult as ex: - if DEBUG2: print("NotInExpressionParser: matched {0} got {1}".format(ex.__class__.__name__, ex.value)) - rightChild = ex.value - - # match for optional whitespace - token = yield - if isinstance(token, SpaceToken): token = yield - # match for closing ) - if (not isinstance(token, CharacterToken)): raise MismatchingParserResult() - if (token.Value != ")"): raise MismatchingParserResult() - - # construct result - result = cls(leftChild, rightChild) - if DEBUG: print("NotInExpressionParser: matched {0}".format(result)) - raise MatchingParserResult(result) - - def __str__(self): - return "({0} not in {1})".format(self._leftChild.__str__(), self._rightChild.__str__()) - -Expressions.AddChoice(Identifier) -Expressions.AddChoice(StringLiteral) -Expressions.AddChoice(IntegerLiteral) -Expressions.AddChoice(NotExpression) -Expressions.AddChoice(ExistsFunction) -Expressions.AddChoice(AndExpression) -Expressions.AddChoice(OrExpression) -Expressions.AddChoice(XorExpression) -Expressions.AddChoice(EqualExpression) -Expressions.AddChoice(UnequalExpression) -Expressions.AddChoice(LessThanExpression) -Expressions.AddChoice(LessThanEqualExpression) -Expressions.AddChoice(GreaterThanExpression) -Expressions.AddChoice(GreaterThanEqualExpression) -Expressions.AddChoice(InExpression) -Expressions.AddChoice(NotInExpression) - -class Statement(CodeDOMObject): - def __init__(self, commentText=""): - super().__init__() - self._commentText = commentText - - @property - def CommentText(self): return self._commentText - @CommentText.setter - def CommentText(self, value): self._commentText = value - - -class BlockStatement(Statement): - def __init__(self, commentText=""): - super().__init__(commentText) - self._statements = [] - - def AddStatement(self, stmt): - self._statements.append(stmt) - - @property - def Statements(self): - return self._statements - - def __str__(self, indent=0): - _indent = " " * indent - buffer = _indent + "BlockStatement" - for stmt in self._statements: - buffer += "\n{0}".format(stmt.__str__(indent + 1)) - return buffer - -class ConditionalBlockStatement(BlockStatement): - def __init__(self, expression, commentText=""): - super().__init__(commentText) - self._expression = expression - - @property - def Expression(self): - return self._expression - - def __str__(self, indent=0): - _indent = " " * indent - buffer = _indent + "ConditionalBlockStatement " + self._expression.__str__() - for stmt in self._statements: - buffer += "\n{0}".format(stmt.__str__(indent + 1)) - return buffer diff --git a/py/lib/__init__.py b/py/lib/__init__.py index 1b54e767..32a31622 100644 --- a/py/lib/__init__.py +++ b/py/lib/__init__.py @@ -1,28 +1,28 @@ # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2; replace-tabs off; indent-width 2; -# +# # ============================================================================== # Authors: Patrick Lehmann -# +# # Python Sub Module: Saves The PoC-Library configuration as python source code. -# +# # Description: # ------------------------------------ # TODO: -# +# # # License: # ============================================================================== # Copyright 2007-2015 Technische Universitaet Dresden - Germany # Chair for VLSI-Design, Diagnostics and Architecture -# +# # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at -# +# # http://www.apache.org/licenses/LICENSE-2.0 -# +# # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. diff --git a/py/lib/pyAttribute.py b/py/lib/pyAttribute.py index 936d7cc8..b315dd8f 100644 --- a/py/lib/pyAttribute.py +++ b/py/lib/pyAttribute.py @@ -1,18 +1,18 @@ # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2; replace-tabs off; indent-width 2; -# +# # ============================================================================= -# _ _ _ _ _ _ -# _ __ _ _ / \ | |_| |_ _ __(_) |__ _ _| |_ ___ +# _ _ _ _ _ _ +# _ __ _ _ / \ | |_| |_ _ __(_) |__ _ _| |_ ___ # | '_ \| | | | / _ \| __| __| '__| | '_ \| | | | __/ _ \ # | |_) | |_| |/ ___ \ |_| |_| | | | |_) | |_| | || __/ # | .__/ \__, /_/ \_\__|\__|_| |_|_.__/ \__,_|\__\___| -# |_| |___/ -# +# |_| |___/ +# # ============================================================================= # Authors: Patrick Lehmann -# +# # Python package: pyAttribute base classes # # Description: @@ -22,13 +22,13 @@ # License: # ============================================================================ # Copyright 2007-2016 Patrick Lehmann - Dresden, Germany -# +# # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at -# +# # http://www.apache.org/licenses/LICENSE-2.0 -# +# # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -39,7 +39,7 @@ class Attribute: __AttributesMemberName__ = "__pyattr__" _debug = False - + def __call__(self, func): self._AppendAttribute(func, self) return func @@ -51,7 +51,7 @@ def _AppendAttribute(func, attribute): func.__dict__[Attribute.__AttributesMemberName__].append(attribute) else: func.__setattr__(Attribute.__AttributesMemberName__, [attribute]) - + def __str__(self): return self.__name__ @@ -67,7 +67,7 @@ def GetMethods(cls, cl): if isinstance(attribute, cls): methods[funcname] = func return methods.items() - + @classmethod def GetAttributes(cls, method): if (Attribute.__AttributesMemberName__ in method.__dict__): @@ -91,7 +91,7 @@ def HasAttribute(self, method): return (isinstance(attributeList, list) and (len(attributeList) != 0)) else: return False - + def GetAttributes(self, method): if (Attribute.__AttributesMemberName__ in method.__dict__): attributeList = method.__dict__[Attribute.__AttributesMemberName__] diff --git a/py/lib/pyAttribute/ArgParseAttributes.py b/py/lib/pyAttribute/ArgParseAttributes.py new file mode 100644 index 00000000..a161f2d7 --- /dev/null +++ b/py/lib/pyAttribute/ArgParseAttributes.py @@ -0,0 +1,179 @@ +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# +# ============================================================================= +# _ _ _ _ _ _ +# _ __ _ _ / \ | |_| |_ _ __(_) |__ _ _| |_ ___ +# | '_ \| | | | / _ \| __| __| '__| | '_ \| | | | __/ _ \ +# | |_) | |_| |/ ___ \ |_| |_| | | | |_) | |_| | || __/ +# | .__/ \__, /_/ \_\__|\__|_| |_|_.__/ \__,_|\__\___| +# |_| |___/ +# +# ============================================================================= +# Authors: Patrick Lehmann +# +# Python module: pyAttributes for ArgParse +# +# Description: +# ------------------------------------ +# TODO +# +# License: +# ============================================================================ +# Copyright 2007-2016 Patrick Lehmann - Dresden, Germany +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================ +# +from . import Attribute, AttributeHelperMixin + + +class CommandGroupAttribute(Attribute): + __groupName = "" + + def __init__(self, groupName): + super().__init__() + self.__groupName = groupName + + @property + def GroupName(self): + return self.__groupName + + +class DefaultAttribute(Attribute): + __handler = None + + def __call__(self, func): + self.__handler = func + return super().__call__(func) + + @property + def Handler(self): + return self.__handler + + +class CommandAttribute(Attribute): + __command = "" + __handler = None + __kwargs = None + + def __init__(self, command, **kwargs): + super().__init__() + self.__command = command + self.__kwargs = kwargs + + def __call__(self, func): + self.__handler = func + return super().__call__(func) + + @property + def Command(self): + return self.__command + + @property + def Handler(self): + return self.__handler + + @property + def KWArgs(self): + return self.__kwargs + + +class ArgumentAttribute(Attribute): + __args = None + __kwargs = None + + def __init__(self, *args, **kwargs): + super().__init__() + self.__args = args + self.__kwargs = kwargs + + @property + def Args(self): + return self.__args + + @property + def KWArgs(self): + return self.__kwargs + + +class SwitchArgumentAttribute(ArgumentAttribute): + def __init__(self, *args, **kwargs): + kwargs['action'] = "store_const" + kwargs['const'] = True + kwargs['default'] = False + super().__init__(*args, **kwargs) + + +class CommonArgumentAttribute(ArgumentAttribute): + pass + + +class CommonSwitchArgumentAttribute(SwitchArgumentAttribute): + pass + + +class ArgParseMixin(AttributeHelperMixin): + __mainParser = None + __subParser = None + __subParsers = {} + + def __init__(self, **kwargs): + super().__init__() + + # create a commandline argument parser + import argparse + self.__mainParser = argparse.ArgumentParser(**kwargs) + self.__subParser = self.__mainParser.add_subparsers(help='sub-command help') + + for _, func in CommonArgumentAttribute.GetMethods(self): + for comAttribute in CommonArgumentAttribute.GetAttributes(func): + self.__mainParser.add_argument(*(comAttribute.Args), **(comAttribute.KWArgs)) + + for _, func in CommonSwitchArgumentAttribute.GetMethods(self): + for comAttribute in CommonSwitchArgumentAttribute.GetAttributes(func): + self.__mainParser.add_argument(*(comAttribute.Args), **(comAttribute.KWArgs)) + + for _, func in self.GetMethods(): + defAttributes = DefaultAttribute.GetAttributes(func) + if (len(defAttributes) != 0): + defAttribute = defAttributes[0] + self.__mainParser.set_defaults(func=defAttribute.Handler) + continue + + cmdAttributes = CommandAttribute.GetAttributes(func) + if (len(cmdAttributes) != 0): + cmdAttribute = cmdAttributes[0] + subParser = self.__subParser.add_parser(cmdAttribute.Command, **(cmdAttribute.KWArgs)) + subParser.set_defaults(func=cmdAttribute.Handler) + + for argAttribute in ArgumentAttribute.GetAttributes(func): + subParser.add_argument(*(argAttribute.Args), **(argAttribute.KWArgs)) + + self.__subParsers[cmdAttribute.Command] = subParser + continue + + def Run(self): + # parse command line options and process splitted arguments in callback functions + args = self.__mainParser.parse_args() + # because func is a function (unbound to an object), it MUST be called with self as a first parameter + args.func(self, args) + + @property + def MainParser(self): + return self.__mainParser + + @property + def SubParsers(self): + return self.__subParsers diff --git a/py/lib/pyAttribute/__init__.py b/py/lib/pyAttribute/__init__.py new file mode 100644 index 00000000..aceb75cf --- /dev/null +++ b/py/lib/pyAttribute/__init__.py @@ -0,0 +1,100 @@ +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# +# ============================================================================= +# _ _ _ _ _ _ +# _ __ _ _ / \ | |_| |_ _ __(_) |__ _ _| |_ ___ +# | '_ \| | | | / _ \| __| __| '__| | '_ \| | | | __/ _ \ +# | |_) | |_| |/ ___ \ |_| |_| | | | |_) | |_| | || __/ +# | .__/ \__, /_/ \_\__|\__|_| |_|_.__/ \__,_|\__\___| +# |_| |___/ +# +# ============================================================================= +# Authors: Patrick Lehmann +# +# Python package: pyAttribute Implementation +# +# Description: +# ------------------------------------ +# TODO +# +# License: +# ============================================================================ +# Copyright 2007-2016 Patrick Lehmann - Dresden, Germany +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================ +# +class Attribute: + __AttributesMemberName__ = "__pyattr__" + _debug = False + + def __call__(self, func): + self._AppendAttribute(func, self) + return func + + @staticmethod + def _AppendAttribute(func, attribute): + # inherit attributes and append myself or create a new attributes list + if (Attribute.__AttributesMemberName__ in func.__dict__): + func.__dict__[Attribute.__AttributesMemberName__].append(attribute) + else: + func.__setattr__(Attribute.__AttributesMemberName__, [attribute]) + + def __str__(self): + return self.__name__ + + @classmethod + def GetMethods(cls, cl): + methods = {} + for funcname, func in cl.__class__.__dict__.items(): + if hasattr(func, '__dict__'): + if (Attribute.__AttributesMemberName__ in func.__dict__): + attributes = func.__dict__[Attribute.__AttributesMemberName__] + if isinstance(attributes, list): + for attribute in attributes: + if isinstance(attribute, cls): + methods[funcname] = func + return methods.items() + + @classmethod + def GetAttributes(cls, method): + if (Attribute.__AttributesMemberName__ in method.__dict__): + attributes = method.__dict__[Attribute.__AttributesMemberName__] + if isinstance(attributes, list): + return [attribute for attribute in attributes if isinstance(attribute, cls)] + return list() + + +class AttributeHelperMixin: + def GetMethods(self): + return { + funcname: func + for funcname, func in self.__class__.__dict__.items() + if hasattr(func, '__dict__') + }.items() + + def HasAttribute(self, method): + if (Attribute.__AttributesMemberName__ in method.__dict__): + attributeList = method.__dict__[Attribute.__AttributesMemberName__] + return (isinstance(attributeList, list) and (len(attributeList) != 0)) + else: + return False + + def GetAttributes(self, method): + if (Attribute.__AttributesMemberName__ in method.__dict__): + attributeList = method.__dict__[Attribute.__AttributesMemberName__] + if isinstance(attributeList, list): + return attributeList + return list() diff --git a/py/wrapper.sh b/py/wrapper.sh deleted file mode 100644 index d25ab416..00000000 --- a/py/wrapper.sh +++ /dev/null @@ -1,236 +0,0 @@ -#! /bin/bash -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# -# ============================================================================== -# Authors: Patrick Lehmann -# Thomas B. Preusser -# Martin Zabel -# -# Bash Script: Wrapper Script to execute a given Python script -# -# Description: -# ------------------------------------ -# This is a bash script (callable) which: -# - checks for a minimum installed Python version -# - loads vendor environments before executing the Python programs -# -# License: -# ============================================================================== -# Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# ============================================================================== - -# script settings -PoC_ExitCode=0 -PoC_PythonScriptDir=py - -# define color escape codes -RED='\e[0;31m' # Red -YELLOW='\e[1;33m' # Yellow -NOCOLOR='\e[0m' # No Color - -PoC_WorkingDir=$(pwd) - -# set default values -PyWrapper_Debug=0 -PyWrapper_LoadEnv_Aldec_ActiveHDL=0 -# PyWrapper_LoadEnv_Aldec_RevieraPRO=0 -# PyWrapper_LoadEnv_Altera_Quartus=0 -# PyWrapper_LoadEnv_Altera_ModelSim=0 -PyWrapper_LoadEnv_GHDL_GTKWave=0 -PyWrapper_LoadEnv_Lattice_Diamond=0 -# PyWrapper_LoadEnv_Lattice_ActiveHDL=0 -PyWrapper_LoadEnv_Mentor_QuestaSim=0 -PyWrapper_LoadEnv_Xilinx_ISE=0 -PyWrapper_LoadEnv_Xilinx_Vivado=0 - -# search for special parameters -# TODO: restrict to first n=2? parameters -for param in $PyWrapper_Parameters; do - if [ "$param" = "-D" ]; then PyWrapper_Debug=1; fi - if [ "$param" = "asim" ]; then PyWrapper_LoadEnv_Aldec_ActiveHDL=1; fi - if [ "$param" = "ghdl" ]; then PyWrapper_LoadEnv_GHDL_GTKWave=1; fi - if [ "$param" = "isim" ]; then PyWrapper_LoadEnv_Xilinx_ISE=1; fi - if [ "$param" = "xsim" ]; then PyWrapper_LoadEnv_Xilinx_Vivado=1; fi - if [ "$param" = "vsim" ]; then PyWrapper_LoadEnv_Mentor_QuestaSim=1; fi - - if [ "$param" = "coregen" ]; then PyWrapper_LoadEnv_Xilinx_ISE=1; fi - if [ "$param" = "xst" ]; then PyWrapper_LoadEnv_Xilinx_ISE=1; fi - if [ "$param" = "vivado" ]; then PyWrapper_LoadEnv_Xilinx_Vivado=1; fi - - if [ "$param" = "lse" ]; then PyWrapper_LoadEnv_Lattice_Diamond=1; fi -done - -# publish PoC directories as environment variables -export PoCRootDirectory=$PoC_RootDir_AbsPath -export PoCWorkingDirectory=$PoC_WorkingDir - -if [ $PyWrapper_Debug -eq 1 ]; then - echo -e "${YELLOW}This is the PoC Library script wrapper operating in debug mode.${NOCOLOR}" - echo - echo -e "${YELLOW}Directories:${NOCOLOR}" - echo -e "${YELLOW} Script root: $PyWrapper_ScriptDir${NOCOLOR}" - echo -e "${YELLOW} PoC root: $PoC_RootDir_AbsPath${NOCOLOR}" - echo -e "${YELLOW} working: $PoC_WorkingDir${NOCOLOR}" - echo -e "${YELLOW}Script:${NOCOLOR}" - echo -e "${YELLOW} Filename: $PyWrapper_Script${NOCOLOR}" - echo -e "${YELLOW} Solution: $PyWrapper_Solution${NOCOLOR}" - echo -e "${YELLOW} Parameters: $PyWrapper_Parameters${NOCOLOR}" - echo -e "${YELLOW}Load Environment:${NOCOLOR}" - echo -e "${YELLOW} Xilinx ISE: $PyWrapper_LoadEnv_Xilinx_ISE${NOCOLOR}" - echo -e "${YELLOW} Xilinx VIVADO: $PyWrapper_LoadEnv_Xilinx_Vivado${NOCOLOR}" - echo -fi - -# find suitable python version or abort execution -Python_VersionTest='import sys; sys.exit(not (0x03050000 < sys.hexversion < 0x04000000))' -python -c "$Python_VersionTest" 2>/dev/null -if [ $? -eq 0 ]; then - Python_Interpreter=$(which python 2>/dev/null) - if [ $PyWrapper_Debug -eq 1 ]; then echo -e "${YELLOW}PythonInterpreter: use standard interpreter: '$Python_Interpreter'${NOCOLOR}"; fi -else - # standard python interpreter is not suitable, try to find a suitable version manually - for pyVersion in 3.9 3.8 3.7 3.6 3.5; do - Python_Interpreter=$(which python$pyVersion 2>/dev/null) - # if ExitCode = 0 => version found - if [ $? -eq 0 ]; then - # redo version test - $Python_Interpreter -c "$Python_VersionTest" 2>/dev/null - if [ $? -eq 0 ]; then break; fi - fi - done - if [ $PyWrapper_Debug -eq 1 ]; then echo -e "${YELLOW}PythonInterpreter: use this interpreter: '$Python_Interpreter'${NOCOLOR}"; fi -fi -# if no interpreter was found => exit -if [ -z "$Python_Interpreter" ]; then - echo 1>&2 -e "${RED}No suitable Python interpreter found.${NOCOLOR}" - echo 1>&2 -e "${RED}The script requires Python >= $PyWrapper_MinVersion${NOCOLOR}" - PoC_ExitCode=1 -fi - -# load Xilinx ISE environment -if [ $PoC_ExitCode -eq 0 ]; then - if [ $PyWrapper_LoadEnv_Xilinx_ISE -eq 1 ]; then - # if $XILINX environment variable is not set - if [ -z "$XILINX" ]; then - command="$Python_Interpreter $PoC_RootDir_AbsPath/$PoC_PythonScriptDir/PoC.py query Xilinx.ISE:SettingsFile" - if [ $PyWrapper_Debug -eq 1 ]; then echo -e "${YELLOW}getting ISE settings file: command='$command'${NOCOLOR}"; fi - PoC_ISE_SettingsFile=$($command) - if [ $? -eq 0 ]; then - if [ $PyWrapper_Debug -eq 1 ]; then echo -e "${YELLOW}ISE settings file: '$PoC_ISE_SettingsFile'${NOCOLOR}"; fi - if [ -z "$PoC_ISE_SettingsFile" ]; then - echo 1>&2 -e "${RED}No Xilinx ISE installation found.${NOCOLOR}" - echo 1>&2 -e "${RED}Run 'PoC.py --configure' to configure your Xilinx ISE installation.${NOCOLOR}" - PoC_ExitCode=1 - fi - echo -e "${YELLOW}Loading Xilinx ISE environment '$PoC_ISE_SettingsFile'${NOCOLOR}" - PyWrapper_RescueArgs=$@ - set -- - source "$PoC_ISE_SettingsFile" - set -- $PyWrapper_RescueArgs - else - echo 1>&2 -e "${RED}ERROR: ExitCode for '$command' was not zero. Aborting script execution.${NOCOLOR}" - echo 1>&2 -e "${RED}$PoC_Vivado_SettingsFile${NOCOLOR}" - PoC_ExitCode=1 - fi - fi - fi -fi - -# load Xilinx Vivado environment -if [ $PoC_ExitCode -eq 0 ]; then - if [ $PyWrapper_LoadEnv_Xilinx_Vivado -eq 1 ]; then - # if $XILINX_VIVADO environment variable is not set - if [ -z "$XILINX_VIVADO" ]; then - command="$Python_Interpreter $PoC_RootDir_AbsPath/$PoC_PythonScriptDir/PoC.py query Xilinx.Vivado:SettingsFile" - if [ $PyWrapper_Debug -eq 1 ]; then echo -e "${YELLOW}getting Vivado settings file: command='$command'${NOCOLOR}"; fi - PoC_Vivado_SettingsFile=$($command) - if [ $? -eq 0 ]; then - if [ $PyWrapper_Debug -eq 1 ]; then echo -e "${YELLOW}Vivado settings file: '$PoC_Vivado_SettingsFile'${NOCOLOR}"; fi - if [ -z "$PoC_Vivado_SettingsFile" ]; then - echo 1>&2 -e "${RED}No Xilinx Vivado installation found.${NOCOLOR}" - echo 1>&2 -e "${RED}Run 'PoC.py --configure' to configure your Xilinx Vivado installation.${NOCOLOR}" - PoC_ExitCode=1 - fi - echo -e "${YELLOW}Loading Xilinx Vivado environment '$PoC_Vivado_SettingsFile'${NOCOLOR}" - PyWrapper_RescueArgs=$@ - set -- - source "$PoC_Vivado_SettingsFile" - set -- $PyWrapper_RescueArgs - else - echo 1>&2 -e "${RED}ERROR: ExitCode for '$command' was not zero. Aborting script execution.${NOCOLOR}" - echo 1>&2 -e "${RED}$PoC_Vivado_SettingsFile${NOCOLOR}" - PoC_ExitCode=1 - fi - fi - fi -fi - -# load Lattice Diamond environment -if [ $PoC_ExitCode -eq 0 ]; then - if [ $PyWrapper_LoadEnv_Lattice_Diamond -eq 1 ]; then - # if $XILINX_VIVADO environment variable is not set - if [ -z "$LSC_DIAMOND" ]; then - command="$Python_Interpreter $PoC_RootDir_AbsPath/$PoC_PythonScriptDir/PoC.py query INSTALL.Lattice.Diamond:BinaryDirectory" - if [ $PyWrapper_Debug -eq 1 ]; then echo -e "${YELLOW}getting Lattice Diamond binary directory: command='$command'${NOCOLOR}"; fi - PoC_Diamond_BinDir=$($command) - if [ $? -eq 0 ]; then - if [ $PyWrapper_Debug -eq 1 ]; then echo -e "${YELLOW}Lattice Diamond binary directory: '$PoC_Diamond_BinDir'${NOCOLOR}"; fi - if [ -z "$PoC_Diamond_BinDir" ]; then - echo 1>&2 -e "${RED}No Lattice Diamond installation found.${NOCOLOR}" - echo 1>&2 -e "${RED}Run 'PoC.py --configure' to configure your Lattice Diamond installation.${NOCOLOR}" - PoC_ExitCode=1 - fi - echo -e "${YELLOW}Loading Lattice Diamond environment '$PoC_Diamond_BinDir/diamond_env'${NOCOLOR}" - PyWrapper_RescueArgs=$@ - set -- - bindir=$PoC_Diamond_BinDir #variable required by diamond_env - source $bindir/diamond_env - unset bindir - set -- $PyWrapper_RescueArgs - else - echo 1>&2 -e "${RED}ERROR: ExitCode for '$command' was not zero. Aborting script execution.${NOCOLOR}" - PoC_ExitCode=1 - fi - fi - fi -fi - -# execute script with appropriate python interpreter and all given parameters -if [ $PoC_ExitCode -eq 0 ]; then - Python_Script="$PoC_RootDir_AbsPath/$PoC_PythonScriptDir/$PyWrapper_Script" - - if [ -z $PyWrapper_Solution ]; then - Python_ScriptParameters=$PyWrapper_Parameters - else - Python_ScriptParameters="--sln=$PyWrapper_Solution $PyWrapper_Parameters" - fi - - if [ $PyWrapper_Debug -eq 1 ]; then - echo -e "${YELLOW}launching: '$Python_Interpreter $Python_Script $Python_ScriptParameters'${NOCOLOR}" - echo -e "${YELLOW}------------------------------------------------------------${NOCOLOR}" - fi - - # launching python script - set -f - $Python_Interpreter $Python_Script $Python_ScriptParameters - PoC_ExitCode=$? -fi - -# clean up environment variables -unset PoCRootDirectory -unset PoCWorkingDirectory diff --git a/readthedocs.yml b/readthedocs.yml new file mode 100644 index 00000000..e8d6ad67 --- /dev/null +++ b/readthedocs.yml @@ -0,0 +1,5 @@ +formats: + - pdf +requirements_file: requirements.txt +python: + version: 3 diff --git a/requirements.txt b/requirements.txt index a5141e87..c24614e1 100644 --- a/requirements.txt +++ b/requirements.txt @@ -1,2 +1,2 @@ colorama==0.3.7 -py-flags==1.0.1 +py-flags==1.1.0 diff --git a/sim/arith/arith_addw_tb.gtkw b/sim/arith/arith_addw_tb.gtkw index 1700fff7..3927e3d5 100644 --- a/sim/arith/arith_addw_tb.gtkw +++ b/sim/arith/arith_addw_tb.gtkw @@ -2,10 +2,8 @@ [*] GTKWave Analyzer v3.3.69 (w)1999-2016 BSI [*] Tue Feb 09 01:50:32 2016 [*] -[dumpfile] "H:\Austausch\PoC\temp\ghdl\arith_addw_tb.ghw" [dumpfile_mtime] "Tue Feb 09 01:47:51 2016" [dumpfile_size] 108986677 -[savefile] "H:\Austausch\PoC\sim\arith\arith_addw_tb.gtkw" [timestart] 0 [size] 1680 997 [pos] -217 -217 diff --git a/sim/arith/arith_convert_bin2bcd_tb.ghdl b/sim/arith/arith_convert_bin2bcd_tb.ghdl new file mode 100644 index 00000000..7bdf6ad9 --- /dev/null +++ b/sim/arith/arith_convert_bin2bcd_tb.ghdl @@ -0,0 +1,46 @@ +$ version 1.1 + +# Signals in packages : + +# Signals in entities : +/arith_convert_bin2bcd_tb/clock +/arith_convert_bin2bcd_tb/reset +/arith_convert_bin2bcd_tb/start +/arith_convert_bin2bcd_tb/conv1_binary +/arith_convert_bin2bcd_tb/conv1_bcddigits +/arith_convert_bin2bcd_tb/conv1_sign +/arith_convert_bin2bcd_tb/conv2_binary +/arith_convert_bin2bcd_tb/conv2_bcddigits +/arith_convert_bin2bcd_tb/conv2_sign +/arith_convert_bin2bcd_tb/conv1/clock +/arith_convert_bin2bcd_tb/conv1/reset +/arith_convert_bin2bcd_tb/conv1/start +/arith_convert_bin2bcd_tb/conv1/busy +/arith_convert_bin2bcd_tb/conv1/binary +/arith_convert_bin2bcd_tb/conv1/issigned +/arith_convert_bin2bcd_tb/conv1/bcddigits +/arith_convert_bin2bcd_tb/conv1/sign +/arith_convert_bin2bcd_tb/conv1/digit_shift_rst +/arith_convert_bin2bcd_tb/conv1/digit_shift_en +/arith_convert_bin2bcd_tb/conv1/digit_shift_in +/arith_convert_bin2bcd_tb/conv1/binary_en +/arith_convert_bin2bcd_tb/conv1/binary_rl +/arith_convert_bin2bcd_tb/conv1/binary_d +/arith_convert_bin2bcd_tb/conv1/sign_d +/arith_convert_bin2bcd_tb/conv1/delayshifter +/arith_convert_bin2bcd_tb/conv2/clock +/arith_convert_bin2bcd_tb/conv2/reset +/arith_convert_bin2bcd_tb/conv2/start +/arith_convert_bin2bcd_tb/conv2/busy +/arith_convert_bin2bcd_tb/conv2/binary +/arith_convert_bin2bcd_tb/conv2/issigned +/arith_convert_bin2bcd_tb/conv2/bcddigits +/arith_convert_bin2bcd_tb/conv2/sign +/arith_convert_bin2bcd_tb/conv2/digit_shift_rst +/arith_convert_bin2bcd_tb/conv2/digit_shift_en +/arith_convert_bin2bcd_tb/conv2/digit_shift_in +/arith_convert_bin2bcd_tb/conv2/binary_en +/arith_convert_bin2bcd_tb/conv2/binary_rl +/arith_convert_bin2bcd_tb/conv2/binary_d +/arith_convert_bin2bcd_tb/conv2/sign_d +/arith_convert_bin2bcd_tb/conv2/delayshifter diff --git a/sim/arith/arith_prefix_and_tb.ghdl b/sim/arith/arith_prefix_and_tb.ghdl new file mode 100644 index 00000000..cd25c992 --- /dev/null +++ b/sim/arith/arith_prefix_and_tb.ghdl @@ -0,0 +1,8 @@ +$ version 1.1 + +# Signals in packages : + +# Signals in entities : +/arith_prefix_and_tb/clock +/arith_prefix_and_tb/x +/arith_prefix_and_tb/y diff --git a/sim/arith/arith_prefix_or_tb.ghdl b/sim/arith/arith_prefix_or_tb.ghdl new file mode 100644 index 00000000..fd6d5148 --- /dev/null +++ b/sim/arith/arith_prefix_or_tb.ghdl @@ -0,0 +1,8 @@ +$ version 1.1 + +# Signals in packages : + +# Signals in entities : +/arith_prefix_or_tb/clock +/arith_prefix_or_tb/x +/arith_prefix_or_tb/y diff --git a/sim/arith/arith_prng_tb.ghdl b/sim/arith/arith_prng_tb.ghdl new file mode 100644 index 00000000..4b40cab3 --- /dev/null +++ b/sim/arith/arith_prng_tb.ghdl @@ -0,0 +1,3 @@ +$ version 1.1 + +/arith_prng_tb/* diff --git a/sim/dstruct/dstruct_deque_tb.ghdl b/sim/dstruct/dstruct_deque_tb.ghdl new file mode 100644 index 00000000..92768581 --- /dev/null +++ b/sim/dstruct/dstruct_deque_tb.ghdl @@ -0,0 +1,48 @@ +$ version 1.1 + +# Signals in packages : + +# Signals in entities : +/dstruct_deque_tb/clk +/dstruct_deque_tb/rst +/dstruct_deque_tb/dina +/dstruct_deque_tb/puta +/dstruct_deque_tb/gota +/dstruct_deque_tb/douta +/dstruct_deque_tb/fulla +/dstruct_deque_tb/valida +/dstruct_deque_tb/dinb +/dstruct_deque_tb/putb +/dstruct_deque_tb/gotb +/dstruct_deque_tb/doutb +/dstruct_deque_tb/validb +/dstruct_deque_tb/fullb +/dstruct_deque_tb/dut/clk +/dstruct_deque_tb/dut/rst +/dstruct_deque_tb/dut/dina +/dstruct_deque_tb/dut/puta +/dstruct_deque_tb/dut/gota +/dstruct_deque_tb/dut/douta +/dstruct_deque_tb/dut/valida +/dstruct_deque_tb/dut/fulla +/dstruct_deque_tb/dut/dinb +/dstruct_deque_tb/dut/putb +/dstruct_deque_tb/dut/gotb +/dstruct_deque_tb/dut/doutb +/dstruct_deque_tb/dut/validb +/dstruct_deque_tb/dut/fullb +/dstruct_deque_tb/dut/combined +/dstruct_deque_tb/dut/ctrl +/dstruct_deque_tb/dut/sub +/dstruct_deque_tb/dut/last_operation +/dstruct_deque_tb/dut/last_op_ctrl +/dstruct_deque_tb/dut/delayed_valid +/dstruct_deque_tb/dut/delay +/dstruct_deque_tb/dut/stackpointera +/dstruct_deque_tb/dut/wea +/dstruct_deque_tb/dut/stackpointerb +/dstruct_deque_tb/dut/web +/dstruct_deque_tb/dut/ctrla +/dstruct_deque_tb/dut/ctrlb +/dstruct_deque_tb/dut/adra +/dstruct_deque_tb/dut/adrb diff --git a/sim/dstruct/dstruct_stack_tb.ghdl b/sim/dstruct/dstruct_stack_tb.ghdl new file mode 100644 index 00000000..db6d4968 --- /dev/null +++ b/sim/dstruct/dstruct_stack_tb.ghdl @@ -0,0 +1,32 @@ +$ version 1.1 + +# Signals in packages : + +# Signals in entities : +/dstruct_stack_tb/clk +/dstruct_stack_tb/rst +/dstruct_stack_tb/din +/dstruct_stack_tb/put +/dstruct_stack_tb/got +/dstruct_stack_tb/dout +/dstruct_stack_tb/full +/dstruct_stack_tb/valid +/dstruct_stack_tb/empty +/dstruct_stack_tb/dut/clk +/dstruct_stack_tb/dut/rst +/dstruct_stack_tb/dut/din +/dstruct_stack_tb/dut/put +/dstruct_stack_tb/dut/full +/dstruct_stack_tb/dut/got +/dstruct_stack_tb/dut/dout +/dstruct_stack_tb/dut/valid +/dstruct_stack_tb/dut/stackpointer +/dstruct_stack_tb/dut/we +/dstruct_stack_tb/dut/adr +/dstruct_stack_tb/dut/s_adr +/dstruct_stack_tb/dut/s_dout +/dstruct_stack_tb/dut/s_valid +/dstruct_stack_tb/dut/s_din +/dstruct_stack_tb/dut/ctrl +/dstruct_stack_tb/dut/current_state +/dstruct_stack_tb/dut/next_state diff --git a/sim/io/uart/uart_rx_tb.ghdl b/sim/io/uart/uart_rx_tb.ghdl new file mode 100644 index 00000000..b4a3e2c9 --- /dev/null +++ b/sim/io/uart/uart_rx_tb.ghdl @@ -0,0 +1,20 @@ +$ version 1.1 + +# Signals in packages : + +# Signals in entities : +/uart_rx_tb/clock +/uart_rx_tb/reset +/uart_rx_tb/bitclock +/uart_rx_tb/bitclock_x8 +/uart_rx_tb/uart_rx +/uart_rx_tb/rx_strobe +/uart_rx_tb/rx_data +/uart_rx_tb/rx/rst +/uart_rx_tb/rx/rx +/uart_rx_tb/rx/do +/uart_rx_tb/rx/stb +/uart_rx_tb/rx/rxs +/uart_rx_tb/rx/buf +/uart_rx_tb/rx/cnt +/uart_rx_tb/rx/vld diff --git a/sim/io/uart/uart_rx_tb.gtkw b/sim/io/uart/uart_rx_tb.gtkw index 17b4a03a..f6b482d9 100644 --- a/sim/io/uart/uart_rx_tb.gtkw +++ b/sim/io/uart/uart_rx_tb.gtkw @@ -2,10 +2,8 @@ [*] GTKWave Analyzer v3.3.61 (w)1999-2014 BSI [*] Tue Feb 09 01:06:25 2016 [*] -[dumpfile] "H:\Austausch\PoC\temp\ghdl\uart_rx_tb.ghw" [dumpfile_mtime] "Tue Feb 09 01:03:30 2016" [dumpfile_size] 54807 -[savefile] "H:\Austausch\PoC\sim\io\uart\uart_rx_tb.gtkw" [timestart] 0 [size] 1680 997 [pos] -35 -35 diff --git a/sim/mem/lut/lut_Sine_tb.ghdl b/sim/mem/lut/lut_Sine_tb.ghdl new file mode 100644 index 00000000..fd4d12d1 --- /dev/null +++ b/sim/mem/lut/lut_Sine_tb.ghdl @@ -0,0 +1,24 @@ +$ version 1.1 + +# Signals in packages : + +# Signals in entities : +/lut_sine_tb/clock +/lut_sine_tb/sim_stop +/lut_sine_tb/lut_in +/lut_sine_tb/lut_q1_in +/lut_sine_tb/lut_q1_out +/lut_sine_tb/lut_q2_in +/lut_sine_tb/lut_q2_out +/lut_sine_tb/lut_q3_in +/lut_sine_tb/lut_q3_out +/lut_sine_tb/lut_q4_in +/lut_sine_tb/lut_q4_out +/lut_sine_tb/lutq1/input +/lut_sine_tb/lutq1/output +/lut_sine_tb/lutq2/input +/lut_sine_tb/lutq2/output +/lut_sine_tb/lutq3/input +/lut_sine_tb/lutq3/output +/lut_sine_tb/lutq4/input +/lut_sine_tb/lutq4/output diff --git a/sim/mem/lut/lut_Sine_tb.gtkw b/sim/mem/lut/lut_Sine_tb.gtkw index 79ebc77a..776f6eec 100644 --- a/sim/mem/lut/lut_Sine_tb.gtkw +++ b/sim/mem/lut/lut_Sine_tb.gtkw @@ -2,10 +2,8 @@ [*] GTKWave Analyzer v3.3.61 (w)1999-2014 BSI [*] Mon Feb 08 22:21:35 2016 [*] -[dumpfile] "H:\Austausch\PoC\temp\ghdl\lut_Sine_tb.ghw" [dumpfile_mtime] "Mon Feb 08 22:17:35 2016" [dumpfile_size] 77559 -[savefile] "H:\Austausch\PoC\sim\mem\lut\lut_Sine_tb.gtkw" [timestart] 0 [size] 1676 996 [pos] -1 -1 diff --git a/sim/mem/ocram/ocram_sdp_tb.ghdl b/sim/mem/ocram/ocram_sdp_tb.ghdl new file mode 100644 index 00000000..72ec2d18 --- /dev/null +++ b/sim/mem/ocram/ocram_sdp_tb.ghdl @@ -0,0 +1,13 @@ +$ version 1.1 + +# Signals in packages : + +# Signals in entities : +/ocram_sdp_tb/rce +/ocram_sdp_tb/wce +/ocram_sdp_tb/we +/ocram_sdp_tb/ra +/ocram_sdp_tb/wa +/ocram_sdp_tb/d +/ocram_sdp_tb/q +/ocram_sdp_tb/clk diff --git a/sim/mem/ocram/ocram_sdp_tb.gtkw b/sim/mem/ocram/ocram_sdp_tb.gtkw index 8a2e10d5..8dbdf8bb 100644 --- a/sim/mem/ocram/ocram_sdp_tb.gtkw +++ b/sim/mem/ocram/ocram_sdp_tb.gtkw @@ -2,10 +2,8 @@ [*] GTKWave Analyzer v3.3.61 (w)1999-2014 BSI [*] Mon Feb 08 22:46:43 2016 [*] -[dumpfile] "H:\Austausch\PoC\temp\ghdl\ocram_sdp_tb.ghw" [dumpfile_mtime] "Mon Feb 08 22:45:30 2016" [dumpfile_size] 116720 -[savefile] "H:\Austausch\PoC\sim\mem\ocram\ocram_sdp_tb.gtkw" [timestart] 0 [size] 1680 997 [pos] -217 -217 diff --git a/sim/misc/gearbox/gearbox_down_cc_tb.ghdl b/sim/misc/gearbox/gearbox_down_cc_tb.ghdl new file mode 100644 index 00000000..79086233 --- /dev/null +++ b/sim/misc/gearbox/gearbox_down_cc_tb.ghdl @@ -0,0 +1,237 @@ +$ version 1.1 + +# Signals in packages : + +# Signals in entities : +/gearbox_down_cc_tb/clock +/gearbox_down_cc_tb//syncin +/gearbox_down_cc_tb//validin +/gearbox_down_cc_tb//datain +/gearbox_down_cc_tb//syncout +/gearbox_down_cc_tb//validout +/gearbox_down_cc_tb//dataout +/gearbox_down_cc_tb//firstout +/gearbox_down_cc_tb//lastout +/gearbox_down_cc_tb//gear/clock +/gearbox_down_cc_tb//gear/in_sync +/gearbox_down_cc_tb//gear/in_valid +/gearbox_down_cc_tb//gear/in_next +/gearbox_down_cc_tb//gear/in_data +/gearbox_down_cc_tb//gear/in_meta +/gearbox_down_cc_tb//gear/out_sync +/gearbox_down_cc_tb//gear/out_valid +/gearbox_down_cc_tb//gear/out_data +/gearbox_down_cc_tb//gear/out_meta +/gearbox_down_cc_tb//gear/out_first +/gearbox_down_cc_tb//gear/out_last +/gearbox_down_cc_tb//gear/in_sync_d +/gearbox_down_cc_tb//gear/in_data_d +/gearbox_down_cc_tb//gear/in_meta_d +/gearbox_down_cc_tb//gear/in_valid_d +/gearbox_down_cc_tb//gear/muxselect_rst +/gearbox_down_cc_tb//gear/muxselect_en +/gearbox_down_cc_tb//gear/muxselect_us +/gearbox_down_cc_tb//gear/muxselect_ov +/gearbox_down_cc_tb//gear/nxt +/gearbox_down_cc_tb//gear/autoincrement +/gearbox_down_cc_tb//gear/gearboxinput +/gearbox_down_cc_tb//gear/gearboxbuffer_en +/gearbox_down_cc_tb//gear/gearboxbuffer +/gearbox_down_cc_tb//gear/gearboxoutput +/gearbox_down_cc_tb//gear/syncout +/gearbox_down_cc_tb//gear/validout +/gearbox_down_cc_tb//gear/dataout +/gearbox_down_cc_tb//gear/metaout +/gearbox_down_cc_tb//gear/firstout +/gearbox_down_cc_tb//gear/lastout +/gearbox_down_cc_tb//gear/out_sync_d +/gearbox_down_cc_tb//gear/out_valid_d +/gearbox_down_cc_tb//gear/out_data_d +/gearbox_down_cc_tb//gear/out_meta_d +/gearbox_down_cc_tb//gear/out_first_d +/gearbox_down_cc_tb//gear/out_last_d +/gearbox_down_cc_tb//gear//muxinput +/gearbox_down_cc_tb//syncin +/gearbox_down_cc_tb//validin +/gearbox_down_cc_tb//datain +/gearbox_down_cc_tb//syncout +/gearbox_down_cc_tb//validout +/gearbox_down_cc_tb//dataout +/gearbox_down_cc_tb//firstout +/gearbox_down_cc_tb//lastout +/gearbox_down_cc_tb//gear/clock +/gearbox_down_cc_tb//gear/in_sync +/gearbox_down_cc_tb//gear/in_valid +/gearbox_down_cc_tb//gear/in_next +/gearbox_down_cc_tb//gear/in_data +/gearbox_down_cc_tb//gear/in_meta +/gearbox_down_cc_tb//gear/out_sync +/gearbox_down_cc_tb//gear/out_valid +/gearbox_down_cc_tb//gear/out_data +/gearbox_down_cc_tb//gear/out_meta +/gearbox_down_cc_tb//gear/out_first +/gearbox_down_cc_tb//gear/out_last +/gearbox_down_cc_tb//gear/in_sync_d +/gearbox_down_cc_tb//gear/in_data_d +/gearbox_down_cc_tb//gear/in_meta_d +/gearbox_down_cc_tb//gear/in_valid_d +/gearbox_down_cc_tb//gear/muxselect_rst +/gearbox_down_cc_tb//gear/muxselect_en +/gearbox_down_cc_tb//gear/muxselect_us +/gearbox_down_cc_tb//gear/muxselect_ov +/gearbox_down_cc_tb//gear/nxt +/gearbox_down_cc_tb//gear/autoincrement +/gearbox_down_cc_tb//gear/gearboxinput +/gearbox_down_cc_tb//gear/gearboxbuffer_en +/gearbox_down_cc_tb//gear/gearboxbuffer +/gearbox_down_cc_tb//gear/gearboxoutput +/gearbox_down_cc_tb//gear/syncout +/gearbox_down_cc_tb//gear/validout +/gearbox_down_cc_tb//gear/dataout +/gearbox_down_cc_tb//gear/metaout +/gearbox_down_cc_tb//gear/firstout +/gearbox_down_cc_tb//gear/lastout +/gearbox_down_cc_tb//gear/out_sync_d +/gearbox_down_cc_tb//gear/out_valid_d +/gearbox_down_cc_tb//gear/out_data_d +/gearbox_down_cc_tb//gear/out_meta_d +/gearbox_down_cc_tb//gear/out_first_d +/gearbox_down_cc_tb//gear/out_last_d +/gearbox_down_cc_tb//syncin +/gearbox_down_cc_tb//validin +/gearbox_down_cc_tb//datain +/gearbox_down_cc_tb//syncout +/gearbox_down_cc_tb//validout +/gearbox_down_cc_tb//dataout +/gearbox_down_cc_tb//firstout +/gearbox_down_cc_tb//lastout +/gearbox_down_cc_tb//gear/clock +/gearbox_down_cc_tb//gear/in_sync +/gearbox_down_cc_tb//gear/in_valid +/gearbox_down_cc_tb//gear/in_next +/gearbox_down_cc_tb//gear/in_data +/gearbox_down_cc_tb//gear/in_meta +/gearbox_down_cc_tb//gear/out_sync +/gearbox_down_cc_tb//gear/out_valid +/gearbox_down_cc_tb//gear/out_data +/gearbox_down_cc_tb//gear/out_meta +/gearbox_down_cc_tb//gear/out_first +/gearbox_down_cc_tb//gear/out_last +/gearbox_down_cc_tb//gear/in_sync_d +/gearbox_down_cc_tb//gear/in_data_d +/gearbox_down_cc_tb//gear/in_meta_d +/gearbox_down_cc_tb//gear/in_valid_d +/gearbox_down_cc_tb//gear/muxselect_rst +/gearbox_down_cc_tb//gear/muxselect_en +/gearbox_down_cc_tb//gear/muxselect_us +/gearbox_down_cc_tb//gear/muxselect_ov +/gearbox_down_cc_tb//gear/nxt +/gearbox_down_cc_tb//gear/autoincrement +/gearbox_down_cc_tb//gear/gearboxinput +/gearbox_down_cc_tb//gear/gearboxbuffer_en +/gearbox_down_cc_tb//gear/gearboxbuffer +/gearbox_down_cc_tb//gear/gearboxoutput +/gearbox_down_cc_tb//gear/syncout +/gearbox_down_cc_tb//gear/validout +/gearbox_down_cc_tb//gear/dataout +/gearbox_down_cc_tb//gear/metaout +/gearbox_down_cc_tb//gear/firstout +/gearbox_down_cc_tb//gear/lastout +/gearbox_down_cc_tb//gear/out_sync_d +/gearbox_down_cc_tb//gear/out_valid_d +/gearbox_down_cc_tb//gear/out_data_d +/gearbox_down_cc_tb//gear/out_meta_d +/gearbox_down_cc_tb//gear/out_first_d +/gearbox_down_cc_tb//gear/out_last_d +/gearbox_down_cc_tb//syncin +/gearbox_down_cc_tb//validin +/gearbox_down_cc_tb//datain +/gearbox_down_cc_tb//syncout +/gearbox_down_cc_tb//validout +/gearbox_down_cc_tb//dataout +/gearbox_down_cc_tb//firstout +/gearbox_down_cc_tb//lastout +/gearbox_down_cc_tb//gear/clock +/gearbox_down_cc_tb//gear/in_sync +/gearbox_down_cc_tb//gear/in_valid +/gearbox_down_cc_tb//gear/in_next +/gearbox_down_cc_tb//gear/in_data +/gearbox_down_cc_tb//gear/in_meta +/gearbox_down_cc_tb//gear/out_sync +/gearbox_down_cc_tb//gear/out_valid +/gearbox_down_cc_tb//gear/out_data +/gearbox_down_cc_tb//gear/out_meta +/gearbox_down_cc_tb//gear/out_first +/gearbox_down_cc_tb//gear/out_last +/gearbox_down_cc_tb//gear/in_sync_d +/gearbox_down_cc_tb//gear/in_data_d +/gearbox_down_cc_tb//gear/in_meta_d +/gearbox_down_cc_tb//gear/in_valid_d +/gearbox_down_cc_tb//gear/muxselect_rst +/gearbox_down_cc_tb//gear/muxselect_en +/gearbox_down_cc_tb//gear/muxselect_us +/gearbox_down_cc_tb//gear/muxselect_ov +/gearbox_down_cc_tb//gear/nxt +/gearbox_down_cc_tb//gear/autoincrement +/gearbox_down_cc_tb//gear/gearboxinput +/gearbox_down_cc_tb//gear/gearboxbuffer_en +/gearbox_down_cc_tb//gear/gearboxbuffer +/gearbox_down_cc_tb//gear/gearboxoutput +/gearbox_down_cc_tb//gear/syncout +/gearbox_down_cc_tb//gear/validout +/gearbox_down_cc_tb//gear/dataout +/gearbox_down_cc_tb//gear/metaout +/gearbox_down_cc_tb//gear/firstout +/gearbox_down_cc_tb//gear/lastout +/gearbox_down_cc_tb//gear/out_sync_d +/gearbox_down_cc_tb//gear/out_valid_d +/gearbox_down_cc_tb//gear/out_data_d +/gearbox_down_cc_tb//gear/out_meta_d +/gearbox_down_cc_tb//gear/out_first_d +/gearbox_down_cc_tb//gear/out_last_d +/gearbox_down_cc_tb//syncin +/gearbox_down_cc_tb//validin +/gearbox_down_cc_tb//datain +/gearbox_down_cc_tb//syncout +/gearbox_down_cc_tb//validout +/gearbox_down_cc_tb//dataout +/gearbox_down_cc_tb//firstout +/gearbox_down_cc_tb//lastout +/gearbox_down_cc_tb//gear/clock +/gearbox_down_cc_tb//gear/in_sync +/gearbox_down_cc_tb//gear/in_valid +/gearbox_down_cc_tb//gear/in_next +/gearbox_down_cc_tb//gear/in_data +/gearbox_down_cc_tb//gear/in_meta +/gearbox_down_cc_tb//gear/out_sync +/gearbox_down_cc_tb//gear/out_valid +/gearbox_down_cc_tb//gear/out_data +/gearbox_down_cc_tb//gear/out_meta +/gearbox_down_cc_tb//gear/out_first +/gearbox_down_cc_tb//gear/out_last +/gearbox_down_cc_tb//gear/in_sync_d +/gearbox_down_cc_tb//gear/in_data_d +/gearbox_down_cc_tb//gear/in_meta_d +/gearbox_down_cc_tb//gear/in_valid_d +/gearbox_down_cc_tb//gear/muxselect_rst +/gearbox_down_cc_tb//gear/muxselect_en +/gearbox_down_cc_tb//gear/muxselect_us +/gearbox_down_cc_tb//gear/muxselect_ov +/gearbox_down_cc_tb//gear/nxt +/gearbox_down_cc_tb//gear/autoincrement +/gearbox_down_cc_tb//gear/gearboxinput +/gearbox_down_cc_tb//gear/gearboxbuffer_en +/gearbox_down_cc_tb//gear/gearboxbuffer +/gearbox_down_cc_tb//gear/gearboxoutput +/gearbox_down_cc_tb//gear/syncout +/gearbox_down_cc_tb//gear/validout +/gearbox_down_cc_tb//gear/dataout +/gearbox_down_cc_tb//gear/metaout +/gearbox_down_cc_tb//gear/firstout +/gearbox_down_cc_tb//gear/lastout +/gearbox_down_cc_tb//gear/out_sync_d +/gearbox_down_cc_tb//gear/out_valid_d +/gearbox_down_cc_tb//gear/out_data_d +/gearbox_down_cc_tb//gear/out_meta_d +/gearbox_down_cc_tb//gear/out_first_d +/gearbox_down_cc_tb//gear/out_last_d diff --git a/sim/misc/gearbox/gearbox_down_cc_tb.gtkw b/sim/misc/gearbox/gearbox_down_cc_tb.gtkw index 233a8152..84c2129e 100644 --- a/sim/misc/gearbox/gearbox_down_cc_tb.gtkw +++ b/sim/misc/gearbox/gearbox_down_cc_tb.gtkw @@ -2,10 +2,8 @@ [*] GTKWave Analyzer v3.3.61 (w)1999-2014 BSI [*] Mon Feb 08 01:00:49 2016 [*] -[dumpfile] "H:\Austausch\PoC\temp\ghdl\gearbox_down_cc_tb.ghw" [dumpfile_mtime] "Mon Feb 08 01:00:05 2016" [dumpfile_size] 430817 -[savefile] "H:\Austausch\PoC\sim\misc\gearbox\gearbox_down_cc_tb.gtkw" [timestart] 0 [size] 1676 996 [pos] -1 -1 diff --git a/sim/misc/gearbox/gearbox_down_dc_tb.ghdl b/sim/misc/gearbox/gearbox_down_dc_tb.ghdl new file mode 100644 index 00000000..20e3ea25 --- /dev/null +++ b/sim/misc/gearbox/gearbox_down_dc_tb.ghdl @@ -0,0 +1,41 @@ +$ version 1.1 + +# Signals in packages : + +# Signals in entities : +/gearbox_down_dc_tb//clock1 +/gearbox_down_dc_tb//clock2 +/gearbox_down_dc_tb//datain +/gearbox_down_dc_tb//dataout +/gearbox_down_dc_tb//gear/clock1 +/gearbox_down_dc_tb//gear/clock2 +/gearbox_down_dc_tb//gear/in_data +/gearbox_down_dc_tb//gear/out_data +/gearbox_down_dc_tb//gear/wordboundary +/gearbox_down_dc_tb//gear/wordboundary_d +/gearbox_down_dc_tb//gear/align +/gearbox_down_dc_tb//gear/data_d +/gearbox_down_dc_tb//gear/datain +/gearbox_down_dc_tb//gear/dataout_d +/gearbox_down_dc_tb//gear/muxinput +/gearbox_down_dc_tb//gear/muxoutput +/gearbox_down_dc_tb//gear/muxcounter_us +/gearbox_down_dc_tb//gear/muxselect_us +/gearbox_down_dc_tb//clock1 +/gearbox_down_dc_tb//clock2 +/gearbox_down_dc_tb//datain +/gearbox_down_dc_tb//dataout +/gearbox_down_dc_tb//gear/clock1 +/gearbox_down_dc_tb//gear/clock2 +/gearbox_down_dc_tb//gear/in_data +/gearbox_down_dc_tb//gear/out_data +/gearbox_down_dc_tb//gear/wordboundary +/gearbox_down_dc_tb//gear/wordboundary_d +/gearbox_down_dc_tb//gear/align +/gearbox_down_dc_tb//gear/data_d +/gearbox_down_dc_tb//gear/datain +/gearbox_down_dc_tb//gear/dataout_d +/gearbox_down_dc_tb//gear/muxinput +/gearbox_down_dc_tb//gear/muxoutput +/gearbox_down_dc_tb//gear/muxcounter_us +/gearbox_down_dc_tb//gear/muxselect_us diff --git a/sim/misc/gearbox/gearbox_down_dc_tb.gtkw b/sim/misc/gearbox/gearbox_down_dc_tb.gtkw index e71b1221..5543e96c 100644 --- a/sim/misc/gearbox/gearbox_down_dc_tb.gtkw +++ b/sim/misc/gearbox/gearbox_down_dc_tb.gtkw @@ -2,10 +2,8 @@ [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI [*] Thu Jan 21 23:46:58 2016 [*] -[dumpfile] "D:\git\PoC\temp\ghdl\gearbox_down_dc_tb.ghw" [dumpfile_mtime] "Thu Jan 21 23:45:45 2016" [dumpfile_size] 21756 -[savefile] "D:\git\PoC\sim\misc\gearbox\gearbox_down_dc_tb.gtkw" [timestart] 0 [size] 1920 996 [pos] -1 -1 diff --git a/sim/misc/gearbox/gearbox_up_cc_tb.ghdl b/sim/misc/gearbox/gearbox_up_cc_tb.ghdl new file mode 100644 index 00000000..2f148ab0 --- /dev/null +++ b/sim/misc/gearbox/gearbox_up_cc_tb.ghdl @@ -0,0 +1,246 @@ +$ version 1.1 + +# Signals in packages : + +# Signals in entities : +/gearbox_up_cc_tb/clock +/gearbox_up_cc_tb//syncin +/gearbox_up_cc_tb//validin +/gearbox_up_cc_tb//datain +/gearbox_up_cc_tb//syncout +/gearbox_up_cc_tb//validout +/gearbox_up_cc_tb//dataout +/gearbox_up_cc_tb//firstout +/gearbox_up_cc_tb//lastout +/gearbox_up_cc_tb//gear/clock +/gearbox_up_cc_tb//gear/in_sync +/gearbox_up_cc_tb//gear/in_valid +/gearbox_up_cc_tb//gear/in_data +/gearbox_up_cc_tb//gear/in_meta +/gearbox_up_cc_tb//gear/out_sync +/gearbox_up_cc_tb//gear/out_valid +/gearbox_up_cc_tb//gear/out_data +/gearbox_up_cc_tb//gear/out_meta +/gearbox_up_cc_tb//gear/out_first +/gearbox_up_cc_tb//gear/out_last +/gearbox_up_cc_tb//gear/in_sync_d +/gearbox_up_cc_tb//gear/in_data_d +/gearbox_up_cc_tb//gear/in_meta_d +/gearbox_up_cc_tb//gear/in_valid_d +/gearbox_up_cc_tb//gear/stageselect_rst +/gearbox_up_cc_tb//gear/stageselect_en +/gearbox_up_cc_tb//gear/stageselect_us +/gearbox_up_cc_tb//gear/stageselect_ov +/gearbox_up_cc_tb//gear/muxselect_rst +/gearbox_up_cc_tb//gear/muxselect_en +/gearbox_up_cc_tb//gear/muxselect_us +/gearbox_up_cc_tb//gear/muxselect_ov +/gearbox_up_cc_tb//gear/gearboxinput +/gearbox_up_cc_tb//gear/gearboxbuffer_en +/gearbox_up_cc_tb//gear/gearboxbuffer +/gearbox_up_cc_tb//gear/metabuffer +/gearbox_up_cc_tb//gear/gearboxoutput +/gearbox_up_cc_tb//gear/syncout +/gearbox_up_cc_tb//gear/validout +/gearbox_up_cc_tb//gear/dataout +/gearbox_up_cc_tb//gear/metaout +/gearbox_up_cc_tb//gear/firstout +/gearbox_up_cc_tb//gear/lastout +/gearbox_up_cc_tb//gear/out_sync_d +/gearbox_up_cc_tb//gear/out_valid_d +/gearbox_up_cc_tb//gear/out_data_d +/gearbox_up_cc_tb//gear/out_meta_d +/gearbox_up_cc_tb//gear/out_first_d +/gearbox_up_cc_tb//gear/out_last_d +/gearbox_up_cc_tb//syncin +/gearbox_up_cc_tb//validin +/gearbox_up_cc_tb//datain +/gearbox_up_cc_tb//syncout +/gearbox_up_cc_tb//validout +/gearbox_up_cc_tb//dataout +/gearbox_up_cc_tb//firstout +/gearbox_up_cc_tb//lastout +/gearbox_up_cc_tb//gear/clock +/gearbox_up_cc_tb//gear/in_sync +/gearbox_up_cc_tb//gear/in_valid +/gearbox_up_cc_tb//gear/in_data +/gearbox_up_cc_tb//gear/in_meta +/gearbox_up_cc_tb//gear/out_sync +/gearbox_up_cc_tb//gear/out_valid +/gearbox_up_cc_tb//gear/out_data +/gearbox_up_cc_tb//gear/out_meta +/gearbox_up_cc_tb//gear/out_first +/gearbox_up_cc_tb//gear/out_last +/gearbox_up_cc_tb//gear/in_sync_d +/gearbox_up_cc_tb//gear/in_data_d +/gearbox_up_cc_tb//gear/in_meta_d +/gearbox_up_cc_tb//gear/in_valid_d +/gearbox_up_cc_tb//gear/stageselect_rst +/gearbox_up_cc_tb//gear/stageselect_en +/gearbox_up_cc_tb//gear/stageselect_us +/gearbox_up_cc_tb//gear/stageselect_ov +/gearbox_up_cc_tb//gear/muxselect_rst +/gearbox_up_cc_tb//gear/muxselect_en +/gearbox_up_cc_tb//gear/muxselect_us +/gearbox_up_cc_tb//gear/muxselect_ov +/gearbox_up_cc_tb//gear/gearboxinput +/gearbox_up_cc_tb//gear/gearboxbuffer_en +/gearbox_up_cc_tb//gear/gearboxbuffer +/gearbox_up_cc_tb//gear/metabuffer +/gearbox_up_cc_tb//gear/gearboxoutput +/gearbox_up_cc_tb//gear/syncout +/gearbox_up_cc_tb//gear/validout +/gearbox_up_cc_tb//gear/dataout +/gearbox_up_cc_tb//gear/metaout +/gearbox_up_cc_tb//gear/firstout +/gearbox_up_cc_tb//gear/lastout +/gearbox_up_cc_tb//gear/out_sync_d +/gearbox_up_cc_tb//gear/out_valid_d +/gearbox_up_cc_tb//gear/out_data_d +/gearbox_up_cc_tb//gear/out_meta_d +/gearbox_up_cc_tb//gear/out_first_d +/gearbox_up_cc_tb//gear/out_last_d +/gearbox_up_cc_tb//syncin +/gearbox_up_cc_tb//validin +/gearbox_up_cc_tb//datain +/gearbox_up_cc_tb//syncout +/gearbox_up_cc_tb//validout +/gearbox_up_cc_tb//dataout +/gearbox_up_cc_tb//firstout +/gearbox_up_cc_tb//lastout +/gearbox_up_cc_tb//gear/clock +/gearbox_up_cc_tb//gear/in_sync +/gearbox_up_cc_tb//gear/in_valid +/gearbox_up_cc_tb//gear/in_data +/gearbox_up_cc_tb//gear/in_meta +/gearbox_up_cc_tb//gear/out_sync +/gearbox_up_cc_tb//gear/out_valid +/gearbox_up_cc_tb//gear/out_data +/gearbox_up_cc_tb//gear/out_meta +/gearbox_up_cc_tb//gear/out_first +/gearbox_up_cc_tb//gear/out_last +/gearbox_up_cc_tb//gear/in_sync_d +/gearbox_up_cc_tb//gear/in_data_d +/gearbox_up_cc_tb//gear/in_meta_d +/gearbox_up_cc_tb//gear/in_valid_d +/gearbox_up_cc_tb//gear/stageselect_rst +/gearbox_up_cc_tb//gear/stageselect_en +/gearbox_up_cc_tb//gear/stageselect_us +/gearbox_up_cc_tb//gear/stageselect_ov +/gearbox_up_cc_tb//gear/muxselect_rst +/gearbox_up_cc_tb//gear/muxselect_en +/gearbox_up_cc_tb//gear/muxselect_us +/gearbox_up_cc_tb//gear/muxselect_ov +/gearbox_up_cc_tb//gear/gearboxinput +/gearbox_up_cc_tb//gear/gearboxbuffer_en +/gearbox_up_cc_tb//gear/gearboxbuffer +/gearbox_up_cc_tb//gear/metabuffer +/gearbox_up_cc_tb//gear/gearboxoutput +/gearbox_up_cc_tb//gear/syncout +/gearbox_up_cc_tb//gear/validout +/gearbox_up_cc_tb//gear/dataout +/gearbox_up_cc_tb//gear/metaout +/gearbox_up_cc_tb//gear/firstout +/gearbox_up_cc_tb//gear/lastout +/gearbox_up_cc_tb//gear/out_sync_d +/gearbox_up_cc_tb//gear/out_valid_d +/gearbox_up_cc_tb//gear/out_data_d +/gearbox_up_cc_tb//gear/out_meta_d +/gearbox_up_cc_tb//gear/out_first_d +/gearbox_up_cc_tb//gear/out_last_d +/gearbox_up_cc_tb//syncin +/gearbox_up_cc_tb//validin +/gearbox_up_cc_tb//datain +/gearbox_up_cc_tb//syncout +/gearbox_up_cc_tb//validout +/gearbox_up_cc_tb//dataout +/gearbox_up_cc_tb//firstout +/gearbox_up_cc_tb//lastout +/gearbox_up_cc_tb//gear/clock +/gearbox_up_cc_tb//gear/in_sync +/gearbox_up_cc_tb//gear/in_valid +/gearbox_up_cc_tb//gear/in_data +/gearbox_up_cc_tb//gear/in_meta +/gearbox_up_cc_tb//gear/out_sync +/gearbox_up_cc_tb//gear/out_valid +/gearbox_up_cc_tb//gear/out_data +/gearbox_up_cc_tb//gear/out_meta +/gearbox_up_cc_tb//gear/out_first +/gearbox_up_cc_tb//gear/out_last +/gearbox_up_cc_tb//gear/in_sync_d +/gearbox_up_cc_tb//gear/in_data_d +/gearbox_up_cc_tb//gear/in_meta_d +/gearbox_up_cc_tb//gear/in_valid_d +/gearbox_up_cc_tb//gear/stageselect_rst +/gearbox_up_cc_tb//gear/stageselect_en +/gearbox_up_cc_tb//gear/stageselect_us +/gearbox_up_cc_tb//gear/stageselect_ov +/gearbox_up_cc_tb//gear/muxselect_rst +/gearbox_up_cc_tb//gear/muxselect_en +/gearbox_up_cc_tb//gear/muxselect_us +/gearbox_up_cc_tb//gear/muxselect_ov +/gearbox_up_cc_tb//gear/gearboxinput +/gearbox_up_cc_tb//gear/gearboxbuffer_en +/gearbox_up_cc_tb//gear/gearboxbuffer +/gearbox_up_cc_tb//gear/metabuffer +/gearbox_up_cc_tb//gear/gearboxoutput +/gearbox_up_cc_tb//gear/syncout +/gearbox_up_cc_tb//gear/validout +/gearbox_up_cc_tb//gear/dataout +/gearbox_up_cc_tb//gear/metaout +/gearbox_up_cc_tb//gear/firstout +/gearbox_up_cc_tb//gear/lastout +/gearbox_up_cc_tb//gear/out_sync_d +/gearbox_up_cc_tb//gear/out_valid_d +/gearbox_up_cc_tb//gear/out_data_d +/gearbox_up_cc_tb//gear/out_meta_d +/gearbox_up_cc_tb//gear/out_first_d +/gearbox_up_cc_tb//gear/out_last_d +/gearbox_up_cc_tb//syncin +/gearbox_up_cc_tb//validin +/gearbox_up_cc_tb//datain +/gearbox_up_cc_tb//syncout +/gearbox_up_cc_tb//validout +/gearbox_up_cc_tb//dataout +/gearbox_up_cc_tb//firstout +/gearbox_up_cc_tb//lastout +/gearbox_up_cc_tb//gear/clock +/gearbox_up_cc_tb//gear/in_sync +/gearbox_up_cc_tb//gear/in_valid +/gearbox_up_cc_tb//gear/in_data +/gearbox_up_cc_tb//gear/in_meta +/gearbox_up_cc_tb//gear/out_sync +/gearbox_up_cc_tb//gear/out_valid +/gearbox_up_cc_tb//gear/out_data +/gearbox_up_cc_tb//gear/out_meta +/gearbox_up_cc_tb//gear/out_first +/gearbox_up_cc_tb//gear/out_last +/gearbox_up_cc_tb//gear/in_sync_d +/gearbox_up_cc_tb//gear/in_data_d +/gearbox_up_cc_tb//gear/in_meta_d +/gearbox_up_cc_tb//gear/in_valid_d +/gearbox_up_cc_tb//gear/stageselect_rst +/gearbox_up_cc_tb//gear/stageselect_en +/gearbox_up_cc_tb//gear/stageselect_us +/gearbox_up_cc_tb//gear/stageselect_ov +/gearbox_up_cc_tb//gear/muxselect_rst +/gearbox_up_cc_tb//gear/muxselect_en +/gearbox_up_cc_tb//gear/muxselect_us +/gearbox_up_cc_tb//gear/muxselect_ov +/gearbox_up_cc_tb//gear/gearboxinput +/gearbox_up_cc_tb//gear/gearboxbuffer_en +/gearbox_up_cc_tb//gear/gearboxbuffer +/gearbox_up_cc_tb//gear/metabuffer +/gearbox_up_cc_tb//gear/gearboxoutput +/gearbox_up_cc_tb//gear/syncout +/gearbox_up_cc_tb//gear/validout +/gearbox_up_cc_tb//gear/dataout +/gearbox_up_cc_tb//gear/metaout +/gearbox_up_cc_tb//gear/firstout +/gearbox_up_cc_tb//gear/lastout +/gearbox_up_cc_tb//gear/out_sync_d +/gearbox_up_cc_tb//gear/out_valid_d +/gearbox_up_cc_tb//gear/out_data_d +/gearbox_up_cc_tb//gear/out_meta_d +/gearbox_up_cc_tb//gear/out_first_d +/gearbox_up_cc_tb//gear/out_last_d diff --git a/sim/misc/gearbox/gearbox_up_cc_tb.gtkw b/sim/misc/gearbox/gearbox_up_cc_tb.gtkw index e705d847..c4a429a2 100644 --- a/sim/misc/gearbox/gearbox_up_cc_tb.gtkw +++ b/sim/misc/gearbox/gearbox_up_cc_tb.gtkw @@ -2,10 +2,8 @@ [*] GTKWave Analyzer v3.3.61 (w)1999-2014 BSI [*] Mon Feb 08 01:01:09 2016 [*] -[dumpfile] "H:\Austausch\PoC\temp\ghdl\gearbox_up_cc_tb.ghw" [dumpfile_mtime] "Mon Feb 08 00:54:13 2016" [dumpfile_size] 255233 -[savefile] "H:\Austausch\PoC\sim\misc\gearbox\gearbox_up_cc_tb.gtkw" [timestart] 0 [size] 1676 996 [pos] -1 -1 diff --git a/sim/misc/gearbox/gearbox_up_dc_tb.ghdl b/sim/misc/gearbox/gearbox_up_dc_tb.ghdl new file mode 100644 index 00000000..cc34b119 --- /dev/null +++ b/sim/misc/gearbox/gearbox_up_dc_tb.ghdl @@ -0,0 +1,53 @@ +$ version 1.1 + +# Signals in packages : + +# Signals in entities : +/gearbox_up_dc_tb//clock1 +/gearbox_up_dc_tb//clock2 +/gearbox_up_dc_tb//align +/gearbox_up_dc_tb//datain +/gearbox_up_dc_tb//dataout +/gearbox_up_dc_tb//valid +/gearbox_up_dc_tb//gear/clock1 +/gearbox_up_dc_tb//gear/clock2 +/gearbox_up_dc_tb//gear/in_align +/gearbox_up_dc_tb//gear/in_data +/gearbox_up_dc_tb//gear/out_data +/gearbox_up_dc_tb//gear/out_valid +/gearbox_up_dc_tb//gear/counter_us +/gearbox_up_dc_tb//gear/select_us +/gearbox_up_dc_tb//gear/in_data_d +/gearbox_up_dc_tb//gear/in_align_d +/gearbox_up_dc_tb//gear/data_d +/gearbox_up_dc_tb//gear/collected +/gearbox_up_dc_tb//gear/collected_swapped +/gearbox_up_dc_tb//gear/collected_en +/gearbox_up_dc_tb//gear/collected_d +/gearbox_up_dc_tb//gear/dataout_d +/gearbox_up_dc_tb//gear/valid_r +/gearbox_up_dc_tb//gear/valid_d +/gearbox_up_dc_tb//clock1 +/gearbox_up_dc_tb//clock2 +/gearbox_up_dc_tb//align +/gearbox_up_dc_tb//datain +/gearbox_up_dc_tb//dataout +/gearbox_up_dc_tb//valid +/gearbox_up_dc_tb//gear/clock1 +/gearbox_up_dc_tb//gear/clock2 +/gearbox_up_dc_tb//gear/in_align +/gearbox_up_dc_tb//gear/in_data +/gearbox_up_dc_tb//gear/out_data +/gearbox_up_dc_tb//gear/out_valid +/gearbox_up_dc_tb//gear/counter_us +/gearbox_up_dc_tb//gear/select_us +/gearbox_up_dc_tb//gear/in_data_d +/gearbox_up_dc_tb//gear/in_align_d +/gearbox_up_dc_tb//gear/data_d +/gearbox_up_dc_tb//gear/collected +/gearbox_up_dc_tb//gear/collected_swapped +/gearbox_up_dc_tb//gear/collected_en +/gearbox_up_dc_tb//gear/collected_d +/gearbox_up_dc_tb//gear/dataout_d +/gearbox_up_dc_tb//gear/valid_r +/gearbox_up_dc_tb//gear/valid_d diff --git a/sim/misc/gearbox/gearbox_up_dc_tb.gtkw b/sim/misc/gearbox/gearbox_up_dc_tb.gtkw index ef751c9c..2bad64bf 100644 --- a/sim/misc/gearbox/gearbox_up_dc_tb.gtkw +++ b/sim/misc/gearbox/gearbox_up_dc_tb.gtkw @@ -2,10 +2,8 @@ [*] GTKWave Analyzer v3.3.61 (w)1999-2014 BSI [*] Mon Feb 08 01:07:41 2016 [*] -[dumpfile] "H:\Austausch\PoC\temp\ghdl\gearbox_up_dc_tb.ghw" [dumpfile_mtime] "Mon Feb 08 01:05:18 2016" [dumpfile_size] 143749 -[savefile] "H:\Austausch\PoC\sim\misc\gearbox\gearbox_up_dc_tb.gtkw" [timestart] 0 [size] 1676 996 [pos] -1 -1 diff --git a/sim/misc/stat/stat_Maximum_tb.ghdl b/sim/misc/stat/stat_Maximum_tb.ghdl new file mode 100644 index 00000000..4bbdf0d9 --- /dev/null +++ b/sim/misc/stat/stat_Maximum_tb.ghdl @@ -0,0 +1,28 @@ +$ version 1.1 + +# Signals in packages : + +# Signals in entities : +/stat_maximum_tb/clock +/stat_maximum_tb/reset +/stat_maximum_tb/enable +/stat_maximum_tb/datain +/stat_maximum_tb/valids +/stat_maximum_tb/maximums +/stat_maximum_tb/counts +/stat_maximum_tb/maximums_slvv +/stat_maximum_tb/counts_slvv +/stat_maximum_tb/uut/clock +/stat_maximum_tb/uut/reset +/stat_maximum_tb/uut/enable +/stat_maximum_tb/uut/datain +/stat_maximum_tb/uut/valids +/stat_maximum_tb/uut/maximums +/stat_maximum_tb/uut/counts +/stat_maximum_tb/uut/datain_us +/stat_maximum_tb/uut/taghit +/stat_maximum_tb/uut/maximumhit +/stat_maximum_tb/uut/tagmemory +/stat_maximum_tb/uut/countermemory +/stat_maximum_tb/uut/maximumindex +/stat_maximum_tb/uut/validmemory diff --git a/sim/misc/stat/stat_Minimum_tb.ghdl b/sim/misc/stat/stat_Minimum_tb.ghdl new file mode 100644 index 00000000..ad298842 --- /dev/null +++ b/sim/misc/stat/stat_Minimum_tb.ghdl @@ -0,0 +1,28 @@ +$ version 1.1 + +# Signals in packages : + +# Signals in entities : +/stat_minimum_tb/clock +/stat_minimum_tb/reset +/stat_minimum_tb/enable +/stat_minimum_tb/datain +/stat_minimum_tb/valids +/stat_minimum_tb/minimums +/stat_minimum_tb/counts +/stat_minimum_tb/minimums_slvv +/stat_minimum_tb/counts_slvv +/stat_minimum_tb/uut/clock +/stat_minimum_tb/uut/reset +/stat_minimum_tb/uut/enable +/stat_minimum_tb/uut/datain +/stat_minimum_tb/uut/valids +/stat_minimum_tb/uut/minimums +/stat_minimum_tb/uut/counts +/stat_minimum_tb/uut/datain_us +/stat_minimum_tb/uut/taghit +/stat_minimum_tb/uut/minimumhit +/stat_minimum_tb/uut/tagmemory +/stat_minimum_tb/uut/countermemory +/stat_minimum_tb/uut/minimumindex +/stat_minimum_tb/uut/validmemory diff --git a/sim/misc/sync/sync_Bits_tb.ghdl b/sim/misc/sync/sync_Bits_tb.ghdl new file mode 100644 index 00000000..74480e8a --- /dev/null +++ b/sim/misc/sync/sync_Bits_tb.ghdl @@ -0,0 +1,9 @@ +$ version 1.1 + +# Signals in packages : + +# Signals in entities : +/sync_bits_tb/clock1 +/sync_bits_tb/clock2 +/sync_bits_tb/sync_in +/sync_bits_tb/sync_out diff --git a/sim/misc/sync/sync_Command_tb.ghdl b/sim/misc/sync/sync_Command_tb.ghdl new file mode 100644 index 00000000..8710ed19 --- /dev/null +++ b/sim/misc/sync/sync_Command_tb.ghdl @@ -0,0 +1,11 @@ +$ version 1.1 + +# Signals in packages : + +# Signals in entities : +/sync_command_tb/clock1 +/sync_command_tb/clock2 +/sync_command_tb/sync_in +/sync_command_tb/sync_out +/sync_command_tb/sync_busy +/sync_command_tb/sync_changed diff --git a/sim/misc/sync/sync_Command_tb.gtkw b/sim/misc/sync/sync_Command_tb.gtkw index 234d15e3..d0bc9fb3 100644 --- a/sim/misc/sync/sync_Command_tb.gtkw +++ b/sim/misc/sync/sync_Command_tb.gtkw @@ -2,10 +2,8 @@ [*] GTKWave Analyzer v3.3.61 (w)1999-2014 BSI [*] Mon Feb 08 14:49:54 2016 [*] -[dumpfile] "H:\Austausch\PoC\temp\ghdl\sync_Command_tb.ghw" [dumpfile_mtime] "Mon Feb 08 14:49:00 2016" [dumpfile_size] 3330 -[savefile] "H:\Austausch\PoC\sim\misc\sync\sync_Command_tb.gtkw" [timestart] 0 [size] 1680 997 [pos] -243 -243 diff --git a/sim/misc/sync/sync_Reset_tb.ghdl b/sim/misc/sync/sync_Reset_tb.ghdl new file mode 100644 index 00000000..6f5ab50b --- /dev/null +++ b/sim/misc/sync/sync_Reset_tb.ghdl @@ -0,0 +1,9 @@ +$ version 1.1 + +# Signals in packages : + +# Signals in entities : +/sync_reset_tb/clock1 +/sync_reset_tb/clock2 +/sync_reset_tb/sync_in +/sync_reset_tb/sync_out diff --git a/sim/misc/sync/sync_Reset_tb.gtkw b/sim/misc/sync/sync_Reset_tb.gtkw index eb975afb..4e3fd835 100644 --- a/sim/misc/sync/sync_Reset_tb.gtkw +++ b/sim/misc/sync/sync_Reset_tb.gtkw @@ -2,10 +2,8 @@ [*] GTKWave Analyzer v3.3.61 (w)1999-2014 BSI [*] Mon Feb 08 14:40:50 2016 [*] -[dumpfile] "H:\Austausch\PoC\temp\ghdl\sync_Reset_tb.ghw" [dumpfile_mtime] "Mon Feb 08 14:39:23 2016" [dumpfile_size] 2407 -[savefile] "H:\Austausch\PoC\sim\misc\sync\sync_Reset_tb.gtkw" [timestart] 0 [size] 1680 997 [pos] -61 -61 diff --git a/sim/misc/sync/sync_Strobe_tb.ghdl b/sim/misc/sync/sync_Strobe_tb.ghdl new file mode 100644 index 00000000..c6d81db4 --- /dev/null +++ b/sim/misc/sync/sync_Strobe_tb.ghdl @@ -0,0 +1,10 @@ +$ version 1.1 + +# Signals in packages : + +# Signals in entities : +/sync_strobe_tb/clock1 +/sync_strobe_tb/clock2 +/sync_strobe_tb/sync_in +/sync_strobe_tb/sync_out +/sync_strobe_tb/sync_busy diff --git a/sim/misc/sync/sync_Strobe_tb.gtkw b/sim/misc/sync/sync_Strobe_tb.gtkw index b87a3599..2bc3bbf5 100644 --- a/sim/misc/sync/sync_Strobe_tb.gtkw +++ b/sim/misc/sync/sync_Strobe_tb.gtkw @@ -2,10 +2,8 @@ [*] GTKWave Analyzer v3.3.61 (w)1999-2014 BSI [*] Mon Feb 08 14:37:35 2016 [*] -[dumpfile] "H:\Austausch\PoC\temp\ghdl\sync_Strobe_tb.ghw" [dumpfile_mtime] "Mon Feb 08 14:35:10 2016" [dumpfile_size] 3230 -[savefile] "H:\Austausch\PoC\sim\misc\sync\sync_Strobe_tb.gtkw" [timestart] 0 [size] 1680 997 [pos] -35 -35 diff --git a/sim/misc/sync/sync_Vector_tb.ghdl b/sim/misc/sync/sync_Vector_tb.ghdl new file mode 100644 index 00000000..31d75e8b --- /dev/null +++ b/sim/misc/sync/sync_Vector_tb.ghdl @@ -0,0 +1,11 @@ +$ version 1.1 + +# Signals in packages : + +# Signals in entities : +/sync_vector_tb/clock1 +/sync_vector_tb/clock2 +/sync_vector_tb/sync_in +/sync_vector_tb/sync_out +/sync_vector_tb/sync_busy +/sync_vector_tb/sync_changed diff --git a/sim/misc/sync/sync_Vector_tb.gtkw b/sim/misc/sync/sync_Vector_tb.gtkw index 8520b755..2679805e 100644 --- a/sim/misc/sync/sync_Vector_tb.gtkw +++ b/sim/misc/sync/sync_Vector_tb.gtkw @@ -2,10 +2,8 @@ [*] GTKWave Analyzer v3.3.61 (w)1999-2014 BSI [*] Mon Feb 08 14:48:43 2016 [*] -[dumpfile] "H:\Austausch\PoC\temp\ghdl\sync_Vector_tb.ghw" [dumpfile_mtime] "Mon Feb 08 14:47:38 2016" [dumpfile_size] 3320 -[savefile] "H:\Austausch\PoC\sim\misc\sync\sync_Vector_tb.gtkw" [timestart] 0 [size] 1680 997 [pos] -217 -217 diff --git a/sim/sort/sortnet/sortnet_BitonicSort_tb.ghdl b/sim/sort/sortnet/sortnet_BitonicSort_tb.ghdl new file mode 100644 index 00000000..6fa2d7ff --- /dev/null +++ b/sim/sort/sortnet/sortnet_BitonicSort_tb.ghdl @@ -0,0 +1,35 @@ +$ version 1.1 + +# Signals in packages : + +# Signals in entities : +/sortnet_bitonicsort_tb/clock +/sortnet_bitonicsort_tb/generator_valid +/sortnet_bitonicsort_tb/generator_iskey +/sortnet_bitonicsort_tb/generator_data +/sortnet_bitonicsort_tb/generator_meta +/sortnet_bitonicsort_tb/sort_valid +/sortnet_bitonicsort_tb/sort_iskey +/sortnet_bitonicsort_tb/sort_data +/sortnet_bitonicsort_tb/sort_meta +/sortnet_bitonicsort_tb/datainputmatrix +/sortnet_bitonicsort_tb/dataoutputmatrix +/sortnet_bitonicsort_tb/sort/clock +/sortnet_bitonicsort_tb/sort/reset +/sortnet_bitonicsort_tb/sort/inverse +/sortnet_bitonicsort_tb/sort/in_valid +/sortnet_bitonicsort_tb/sort/in_iskey +/sortnet_bitonicsort_tb/sort/in_data +/sortnet_bitonicsort_tb/sort/in_meta +/sortnet_bitonicsort_tb/sort/out_valid +/sortnet_bitonicsort_tb/sort/out_iskey +/sortnet_bitonicsort_tb/sort/out_data +/sortnet_bitonicsort_tb/sort/out_meta +/sortnet_bitonicsort_tb/sort/in_valid_d +/sortnet_bitonicsort_tb/sort/in_iskey_d +/sortnet_bitonicsort_tb/sort/in_data_d +/sortnet_bitonicsort_tb/sort/in_meta_d +/sortnet_bitonicsort_tb/sort/metavector +/sortnet_bitonicsort_tb/sort/datamatrix +/sortnet_bitonicsort_tb/sort/metaoutputs_d +/sortnet_bitonicsort_tb/sort/dataoutputs_d diff --git a/sim/sort/sortnet/sortnet_OddEvenMergeSort_tb.ghdl b/sim/sort/sortnet/sortnet_OddEvenMergeSort_tb.ghdl new file mode 100644 index 00000000..ceea4277 --- /dev/null +++ b/sim/sort/sortnet/sortnet_OddEvenMergeSort_tb.ghdl @@ -0,0 +1,35 @@ +$ version 1.1 + +# Signals in packages : + +# Signals in entities : +/sortnet_oddevenmergesort_tb/clock +/sortnet_oddevenmergesort_tb/generator_valid +/sortnet_oddevenmergesort_tb/generator_iskey +/sortnet_oddevenmergesort_tb/generator_data +/sortnet_oddevenmergesort_tb/generator_meta +/sortnet_oddevenmergesort_tb/sort_valid +/sortnet_oddevenmergesort_tb/sort_iskey +/sortnet_oddevenmergesort_tb/sort_data +/sortnet_oddevenmergesort_tb/sort_meta +/sortnet_oddevenmergesort_tb/datainputmatrix +/sortnet_oddevenmergesort_tb/dataoutputmatrix +/sortnet_oddevenmergesort_tb/sort/clock +/sortnet_oddevenmergesort_tb/sort/reset +/sortnet_oddevenmergesort_tb/sort/inverse +/sortnet_oddevenmergesort_tb/sort/in_valid +/sortnet_oddevenmergesort_tb/sort/in_iskey +/sortnet_oddevenmergesort_tb/sort/in_data +/sortnet_oddevenmergesort_tb/sort/in_meta +/sortnet_oddevenmergesort_tb/sort/out_valid +/sortnet_oddevenmergesort_tb/sort/out_iskey +/sortnet_oddevenmergesort_tb/sort/out_data +/sortnet_oddevenmergesort_tb/sort/out_meta +/sortnet_oddevenmergesort_tb/sort/in_valid_d +/sortnet_oddevenmergesort_tb/sort/in_iskey_d +/sortnet_oddevenmergesort_tb/sort/in_data_d +/sortnet_oddevenmergesort_tb/sort/in_meta_d +/sortnet_oddevenmergesort_tb/sort/metavector +/sortnet_oddevenmergesort_tb/sort/datamatrix +/sortnet_oddevenmergesort_tb/sort/metaoutputs_d +/sortnet_oddevenmergesort_tb/sort/dataoutputs_d diff --git a/sim/sort/sortnet/sortnet_OddEvenMergeSort_tb.gtkw b/sim/sort/sortnet/sortnet_OddEvenMergeSort_tb.gtkw index 967927e6..75e96f7d 100644 --- a/sim/sort/sortnet/sortnet_OddEvenMergeSort_tb.gtkw +++ b/sim/sort/sortnet/sortnet_OddEvenMergeSort_tb.gtkw @@ -2,10 +2,8 @@ [*] GTKWave Analyzer v3.3.69 (w)1999-2016 BSI [*] Sun Mar 20 17:06:18 2016 [*] -[dumpfile] "G:\git\PoC\temp\ghdl\sortnet_OddEvenMergeSort_tb.ghw" [dumpfile_mtime] "Sun Mar 20 17:05:58 2016" [dumpfile_size] 582043 -[savefile] "G:\git\PoC\sim\sort\sortnet\sortnet_OddEvenMergeSort_tb.gtkw" [timestart] 0 [size] 1676 997 [pos] -1 -1 diff --git a/sim/sort/sortnet/sortnet_OddEvenSort_tb.ghdl b/sim/sort/sortnet/sortnet_OddEvenSort_tb.ghdl new file mode 100644 index 00000000..111832cb --- /dev/null +++ b/sim/sort/sortnet/sortnet_OddEvenSort_tb.ghdl @@ -0,0 +1,35 @@ +$ version 1.1 + +# Signals in packages : + +# Signals in entities : +/sortnet_oddevensort_tb/clock +/sortnet_oddevensort_tb/generator_valid +/sortnet_oddevensort_tb/generator_iskey +/sortnet_oddevensort_tb/generator_data +/sortnet_oddevensort_tb/generator_meta +/sortnet_oddevensort_tb/sort_valid +/sortnet_oddevensort_tb/sort_iskey +/sortnet_oddevensort_tb/sort_data +/sortnet_oddevensort_tb/sort_meta +/sortnet_oddevensort_tb/datainputmatrix +/sortnet_oddevensort_tb/dataoutputmatrix +/sortnet_oddevensort_tb/sort/clock +/sortnet_oddevensort_tb/sort/reset +/sortnet_oddevensort_tb/sort/inverse +/sortnet_oddevensort_tb/sort/in_valid +/sortnet_oddevensort_tb/sort/in_iskey +/sortnet_oddevensort_tb/sort/in_data +/sortnet_oddevensort_tb/sort/in_meta +/sortnet_oddevensort_tb/sort/out_valid +/sortnet_oddevensort_tb/sort/out_iskey +/sortnet_oddevensort_tb/sort/out_data +/sortnet_oddevensort_tb/sort/out_meta +/sortnet_oddevensort_tb/sort/in_valid_d +/sortnet_oddevensort_tb/sort/in_iskey_d +/sortnet_oddevensort_tb/sort/in_data_d +/sortnet_oddevensort_tb/sort/in_meta_d +/sortnet_oddevensort_tb/sort/metavector +/sortnet_oddevensort_tb/sort/datamatrix +/sortnet_oddevensort_tb/sort/metaoutputs_d +/sortnet_oddevensort_tb/sort/dataoutputs_d diff --git a/sim/sort/sortnet/sortnet_OddEvenSort_tb.gtkw b/sim/sort/sortnet/sortnet_OddEvenSort_tb.gtkw index 6cfa9c17..6695eba5 100644 --- a/sim/sort/sortnet/sortnet_OddEvenSort_tb.gtkw +++ b/sim/sort/sortnet/sortnet_OddEvenSort_tb.gtkw @@ -2,10 +2,8 @@ [*] GTKWave Analyzer v3.3.69 (w)1999-2016 BSI [*] Sun Mar 20 17:00:26 2016 [*] -[dumpfile] "G:\git\PoC\temp\ghdl\sortnet_OddEvenSort_tb.ghw" [dumpfile_mtime] "Sun Mar 20 16:55:34 2016" [dumpfile_size] 1236808 -[savefile] "G:\git\PoC\sim\sort\sortnet\sortnet_OddEvenSort_tb.gtkw" [timestart] 0 [size] 1680 997 [pos] -1 -1 diff --git a/sim/sort/sortnet/sortnet_Stream_Adapter2_tb.ghdl b/sim/sort/sortnet/sortnet_Stream_Adapter2_tb.ghdl new file mode 100644 index 00000000..0558917a --- /dev/null +++ b/sim/sort/sortnet/sortnet_Stream_Adapter2_tb.ghdl @@ -0,0 +1,168 @@ +$ version 1.1 + +# Signals in packages : + +# Signals in entities : +/sortnet_stream_adapter2_tb/clock +/sortnet_stream_adapter2_tb/generator_valid +/sortnet_stream_adapter2_tb/generator_data +/sortnet_stream_adapter2_tb/generator_sof +/sortnet_stream_adapter2_tb/generator_iskey +/sortnet_stream_adapter2_tb/generator_eof +/sortnet_stream_adapter2_tb/generator_meta +/sortnet_stream_adapter2_tb/sort_out_valid +/sortnet_stream_adapter2_tb/sort_out_data +/sortnet_stream_adapter2_tb/sort_out_iskey +/sortnet_stream_adapter2_tb/tester_ack +/sortnet_stream_adapter2_tb/sort/clock +/sortnet_stream_adapter2_tb/sort/reset +/sortnet_stream_adapter2_tb/sort/inverse +/sortnet_stream_adapter2_tb/sort/in_valid +/sortnet_stream_adapter2_tb/sort/in_data +/sortnet_stream_adapter2_tb/sort/in_meta +/sortnet_stream_adapter2_tb/sort/in_sof +/sortnet_stream_adapter2_tb/sort/in_iskey +/sortnet_stream_adapter2_tb/sort/in_eof +/sortnet_stream_adapter2_tb/sort/in_ack +/sortnet_stream_adapter2_tb/sort/out_valid +/sortnet_stream_adapter2_tb/sort/out_data +/sortnet_stream_adapter2_tb/sort/out_meta +/sortnet_stream_adapter2_tb/sort/out_sof +/sortnet_stream_adapter2_tb/sort/out_iskey +/sortnet_stream_adapter2_tb/sort/out_eof +/sortnet_stream_adapter2_tb/sort/out_ack +/sortnet_stream_adapter2_tb/sort/synchronized_r +/sortnet_stream_adapter2_tb/sort/syncin +/sortnet_stream_adapter2_tb/sort/metain +/sortnet_stream_adapter2_tb/sort/gearup_sync +/sortnet_stream_adapter2_tb/sort/gearup_valid +/sortnet_stream_adapter2_tb/sort/gearup_data +/sortnet_stream_adapter2_tb/sort/gearup_meta +/sortnet_stream_adapter2_tb/sort/gearup_first +/sortnet_stream_adapter2_tb/sort/gearup_last +/sortnet_stream_adapter2_tb/sort/sort_valid +/sortnet_stream_adapter2_tb/sort/sort_iskey +/sortnet_stream_adapter2_tb/sort/sort_data +/sortnet_stream_adapter2_tb/sort/sort_meta +/sortnet_stream_adapter2_tb/sort/transform_valid +/sortnet_stream_adapter2_tb/sort/transform_data +/sortnet_stream_adapter2_tb/sort/transform_meta +/sortnet_stream_adapter2_tb/sort/transform_sof +/sortnet_stream_adapter2_tb/sort/transform_eof +/sortnet_stream_adapter2_tb/sort/merge_sync +/sortnet_stream_adapter2_tb/sort/merge_valid +/sortnet_stream_adapter2_tb/sort/merge_data +/sortnet_stream_adapter2_tb/sort/merge_meta +/sortnet_stream_adapter2_tb/sort/merge_sof +/sortnet_stream_adapter2_tb/sort/merge_eof +/sortnet_stream_adapter2_tb/sort/merge_ack +/sortnet_stream_adapter2_tb/sort/geardown_nxt +/sortnet_stream_adapter2_tb/sort/geardown_meta +/sortnet_stream_adapter2_tb/sort/geardown_first +/sortnet_stream_adapter2_tb/sort/geardown_last +/sortnet_stream_adapter2_tb/sort/gearup/clock +/sortnet_stream_adapter2_tb/sort/gearup/in_sync +/sortnet_stream_adapter2_tb/sort/gearup/in_valid +/sortnet_stream_adapter2_tb/sort/gearup/in_data +/sortnet_stream_adapter2_tb/sort/gearup/in_meta +/sortnet_stream_adapter2_tb/sort/gearup/out_sync +/sortnet_stream_adapter2_tb/sort/gearup/out_valid +/sortnet_stream_adapter2_tb/sort/gearup/out_data +/sortnet_stream_adapter2_tb/sort/gearup/out_meta +/sortnet_stream_adapter2_tb/sort/gearup/out_first +/sortnet_stream_adapter2_tb/sort/gearup/out_last +/sortnet_stream_adapter2_tb/sort/gearup/in_sync_d +/sortnet_stream_adapter2_tb/sort/gearup/in_data_d +/sortnet_stream_adapter2_tb/sort/gearup/in_meta_d +/sortnet_stream_adapter2_tb/sort/gearup/in_valid_d +/sortnet_stream_adapter2_tb/sort/gearup/stageselect_rst +/sortnet_stream_adapter2_tb/sort/gearup/stageselect_en +/sortnet_stream_adapter2_tb/sort/gearup/stageselect_us +/sortnet_stream_adapter2_tb/sort/gearup/stageselect_ov +/sortnet_stream_adapter2_tb/sort/gearup/muxselect_rst +/sortnet_stream_adapter2_tb/sort/gearup/muxselect_en +/sortnet_stream_adapter2_tb/sort/gearup/muxselect_us +/sortnet_stream_adapter2_tb/sort/gearup/muxselect_ov +/sortnet_stream_adapter2_tb/sort/gearup/gearboxinput +/sortnet_stream_adapter2_tb/sort/gearup/gearboxbuffer_en +/sortnet_stream_adapter2_tb/sort/gearup/gearboxbuffer +/sortnet_stream_adapter2_tb/sort/gearup/metabuffer +/sortnet_stream_adapter2_tb/sort/gearup/gearboxoutput +/sortnet_stream_adapter2_tb/sort/gearup/syncout +/sortnet_stream_adapter2_tb/sort/gearup/validout +/sortnet_stream_adapter2_tb/sort/gearup/dataout +/sortnet_stream_adapter2_tb/sort/gearup/metaout +/sortnet_stream_adapter2_tb/sort/gearup/firstout +/sortnet_stream_adapter2_tb/sort/gearup/lastout +/sortnet_stream_adapter2_tb/sort/gearup/out_sync_d +/sortnet_stream_adapter2_tb/sort/gearup/out_valid_d +/sortnet_stream_adapter2_tb/sort/gearup/out_data_d +/sortnet_stream_adapter2_tb/sort/gearup/out_meta_d +/sortnet_stream_adapter2_tb/sort/gearup/out_first_d +/sortnet_stream_adapter2_tb/sort/gearup/out_last_d +/sortnet_stream_adapter2_tb/sort/blktransform/datainputmatrix +/sortnet_stream_adapter2_tb/sort/blktransform/dataoutputmatrix +/sortnet_stream_adapter2_tb/sort/blktransform/transform/clock +/sortnet_stream_adapter2_tb/sort/blktransform/transform/reset +/sortnet_stream_adapter2_tb/sort/blktransform/transform/in_valid +/sortnet_stream_adapter2_tb/sort/blktransform/transform/in_data +/sortnet_stream_adapter2_tb/sort/blktransform/transform/in_sof +/sortnet_stream_adapter2_tb/sort/blktransform/transform/in_eof +/sortnet_stream_adapter2_tb/sort/blktransform/transform/out_valid +/sortnet_stream_adapter2_tb/sort/blktransform/transform/out_data +/sortnet_stream_adapter2_tb/sort/blktransform/transform/out_sof +/sortnet_stream_adapter2_tb/sort/blktransform/transform/out_eof +/sortnet_stream_adapter2_tb/sort/blktransform/transform/datain +/sortnet_stream_adapter2_tb/sort/blktransform/transform/columnwriter_rst +/sortnet_stream_adapter2_tb/sort/blktransform/transform/columnwriter_us +/sortnet_stream_adapter2_tb/sort/blktransform/transform/columnwriter_ov +/sortnet_stream_adapter2_tb/sort/blktransform/transform/inputbuffer +/sortnet_stream_adapter2_tb/sort/blktransform/transform/rowreader_en_r +/sortnet_stream_adapter2_tb/sort/blktransform/transform/rowreader_rst +/sortnet_stream_adapter2_tb/sort/blktransform/transform/rowreader_en +/sortnet_stream_adapter2_tb/sort/blktransform/transform/rowreader_us +/sortnet_stream_adapter2_tb/sort/blktransform/transform/rowreader_ov +/sortnet_stream_adapter2_tb/sort/blkmergesort/mergesortmatrix_valid +/sortnet_stream_adapter2_tb/sort/blkmergesort/mergesortmatrix_data +/sortnet_stream_adapter2_tb/sort/blkmergesort/mergesortmatrix_sof +/sortnet_stream_adapter2_tb/sort/blkmergesort/mergesortmatrix_eof +/sortnet_stream_adapter2_tb/sort/blkmergesort/mergesortmatrix_ack +/sortnet_stream_adapter2_tb/sort/geardown/clock +/sortnet_stream_adapter2_tb/sort/geardown/in_sync +/sortnet_stream_adapter2_tb/sort/geardown/in_valid +/sortnet_stream_adapter2_tb/sort/geardown/in_next +/sortnet_stream_adapter2_tb/sort/geardown/in_data +/sortnet_stream_adapter2_tb/sort/geardown/in_meta +/sortnet_stream_adapter2_tb/sort/geardown/out_sync +/sortnet_stream_adapter2_tb/sort/geardown/out_valid +/sortnet_stream_adapter2_tb/sort/geardown/out_data +/sortnet_stream_adapter2_tb/sort/geardown/out_meta +/sortnet_stream_adapter2_tb/sort/geardown/out_first +/sortnet_stream_adapter2_tb/sort/geardown/out_last +/sortnet_stream_adapter2_tb/sort/geardown/in_sync_d +/sortnet_stream_adapter2_tb/sort/geardown/in_data_d +/sortnet_stream_adapter2_tb/sort/geardown/in_meta_d +/sortnet_stream_adapter2_tb/sort/geardown/in_valid_d +/sortnet_stream_adapter2_tb/sort/geardown/muxselect_rst +/sortnet_stream_adapter2_tb/sort/geardown/muxselect_en +/sortnet_stream_adapter2_tb/sort/geardown/muxselect_us +/sortnet_stream_adapter2_tb/sort/geardown/muxselect_ov +/sortnet_stream_adapter2_tb/sort/geardown/nxt +/sortnet_stream_adapter2_tb/sort/geardown/autoincrement +/sortnet_stream_adapter2_tb/sort/geardown/gearboxinput +/sortnet_stream_adapter2_tb/sort/geardown/gearboxbuffer_en +/sortnet_stream_adapter2_tb/sort/geardown/gearboxbuffer +/sortnet_stream_adapter2_tb/sort/geardown/gearboxoutput +/sortnet_stream_adapter2_tb/sort/geardown/syncout +/sortnet_stream_adapter2_tb/sort/geardown/validout +/sortnet_stream_adapter2_tb/sort/geardown/dataout +/sortnet_stream_adapter2_tb/sort/geardown/metaout +/sortnet_stream_adapter2_tb/sort/geardown/firstout +/sortnet_stream_adapter2_tb/sort/geardown/lastout +/sortnet_stream_adapter2_tb/sort/geardown/out_sync_d +/sortnet_stream_adapter2_tb/sort/geardown/out_valid_d +/sortnet_stream_adapter2_tb/sort/geardown/out_data_d +/sortnet_stream_adapter2_tb/sort/geardown/out_meta_d +/sortnet_stream_adapter2_tb/sort/geardown/out_first_d +/sortnet_stream_adapter2_tb/sort/geardown/out_last_d +/sortnet_stream_adapter2_tb/sort/geardown//muxinput diff --git a/sim/sort/sortnet/sortnet_Stream_Adapter2_tb.gtkw b/sim/sort/sortnet/sortnet_Stream_Adapter2_tb.gtkw index b1e04b12..1226e93b 100644 --- a/sim/sort/sortnet/sortnet_Stream_Adapter2_tb.gtkw +++ b/sim/sort/sortnet/sortnet_Stream_Adapter2_tb.gtkw @@ -2,10 +2,8 @@ [*] GTKWave Analyzer v3.3.61 (w)1999-2014 BSI [*] Mon Jan 04 05:24:27 2016 [*] -[dumpfile] "H:\Austausch\PoC\temp\ghdl\sortnet_Stream_Adapter2_tb.ghw" [dumpfile_mtime] "Mon Jan 04 05:20:23 2016" [dumpfile_size] 238301 -[savefile] "H:\Austausch\PoC\sim\sort\sortnet\sortnet_Stream_Adapter2_tb.gtkw" [timestart] 0 [size] 1676 997 [pos] -1 -1 diff --git a/sim/sort/sortnet/sortnet_Stream_Adapter_tb.ghdl b/sim/sort/sortnet/sortnet_Stream_Adapter_tb.ghdl new file mode 100644 index 00000000..09bd9dce --- /dev/null +++ b/sim/sort/sortnet/sortnet_Stream_Adapter_tb.ghdl @@ -0,0 +1,115 @@ +$ version 1.1 + +# Signals in packages : + +# Signals in entities : +/sortnet_stream_adapter_tb/clock +/sortnet_stream_adapter_tb/generator_valid +/sortnet_stream_adapter_tb/generator_data +/sortnet_stream_adapter_tb/generator_iskey +/sortnet_stream_adapter_tb/generator_tag +/sortnet_stream_adapter_tb/sort_out_valid +/sortnet_stream_adapter_tb/sort_out_data +/sortnet_stream_adapter_tb/sort_out_iskey +/sortnet_stream_adapter_tb/tester_ack +/sortnet_stream_adapter_tb/stopsimulation +/sortnet_stream_adapter_tb/sort/clock +/sortnet_stream_adapter_tb/sort/reset +/sortnet_stream_adapter_tb/sort/in_valid +/sortnet_stream_adapter_tb/sort/in_iskey +/sortnet_stream_adapter_tb/sort/in_data +/sortnet_stream_adapter_tb/sort/in_meta +/sortnet_stream_adapter_tb/sort/in_ack +/sortnet_stream_adapter_tb/sort/out_valid +/sortnet_stream_adapter_tb/sort/out_iskey +/sortnet_stream_adapter_tb/sort/out_data +/sortnet_stream_adapter_tb/sort/out_meta +/sortnet_stream_adapter_tb/sort/out_ack +/sortnet_stream_adapter_tb/sort/metain +/sortnet_stream_adapter_tb/sort/gearup_valid +/sortnet_stream_adapter_tb/sort/gearup_data +/sortnet_stream_adapter_tb/sort/gearup_meta +/sortnet_stream_adapter_tb/sort/sort_valid +/sortnet_stream_adapter_tb/sort/sort_iskey +/sortnet_stream_adapter_tb/sort/sort_data +/sortnet_stream_adapter_tb/sort/sort_meta +/sortnet_stream_adapter_tb/sort/geardown_nxt +/sortnet_stream_adapter_tb/sort/gearup/clock +/sortnet_stream_adapter_tb/sort/gearup/in_sync +/sortnet_stream_adapter_tb/sort/gearup/in_valid +/sortnet_stream_adapter_tb/sort/gearup/in_data +/sortnet_stream_adapter_tb/sort/gearup/in_meta +/sortnet_stream_adapter_tb/sort/gearup/out_sync +/sortnet_stream_adapter_tb/sort/gearup/out_valid +/sortnet_stream_adapter_tb/sort/gearup/out_data +/sortnet_stream_adapter_tb/sort/gearup/out_meta +/sortnet_stream_adapter_tb/sort/gearup/out_first +/sortnet_stream_adapter_tb/sort/gearup/out_last +/sortnet_stream_adapter_tb/sort/gearup/in_sync_d +/sortnet_stream_adapter_tb/sort/gearup/in_data_d +/sortnet_stream_adapter_tb/sort/gearup/in_meta_d +/sortnet_stream_adapter_tb/sort/gearup/in_valid_d +/sortnet_stream_adapter_tb/sort/gearup/stageselect_rst +/sortnet_stream_adapter_tb/sort/gearup/stageselect_en +/sortnet_stream_adapter_tb/sort/gearup/stageselect_us +/sortnet_stream_adapter_tb/sort/gearup/stageselect_ov +/sortnet_stream_adapter_tb/sort/gearup/muxselect_rst +/sortnet_stream_adapter_tb/sort/gearup/muxselect_en +/sortnet_stream_adapter_tb/sort/gearup/muxselect_us +/sortnet_stream_adapter_tb/sort/gearup/muxselect_ov +/sortnet_stream_adapter_tb/sort/gearup/gearboxinput +/sortnet_stream_adapter_tb/sort/gearup/gearboxbuffer_en +/sortnet_stream_adapter_tb/sort/gearup/gearboxbuffer +/sortnet_stream_adapter_tb/sort/gearup/metabuffer +/sortnet_stream_adapter_tb/sort/gearup/gearboxoutput +/sortnet_stream_adapter_tb/sort/gearup/syncout +/sortnet_stream_adapter_tb/sort/gearup/validout +/sortnet_stream_adapter_tb/sort/gearup/dataout +/sortnet_stream_adapter_tb/sort/gearup/metaout +/sortnet_stream_adapter_tb/sort/gearup/firstout +/sortnet_stream_adapter_tb/sort/gearup/lastout +/sortnet_stream_adapter_tb/sort/gearup/out_sync_d +/sortnet_stream_adapter_tb/sort/gearup/out_valid_d +/sortnet_stream_adapter_tb/sort/gearup/out_data_d +/sortnet_stream_adapter_tb/sort/gearup/out_meta_d +/sortnet_stream_adapter_tb/sort/gearup/out_first_d +/sortnet_stream_adapter_tb/sort/gearup/out_last_d +/sortnet_stream_adapter_tb/sort/geardown/clock +/sortnet_stream_adapter_tb/sort/geardown/in_sync +/sortnet_stream_adapter_tb/sort/geardown/in_valid +/sortnet_stream_adapter_tb/sort/geardown/in_next +/sortnet_stream_adapter_tb/sort/geardown/in_data +/sortnet_stream_adapter_tb/sort/geardown/in_meta +/sortnet_stream_adapter_tb/sort/geardown/out_sync +/sortnet_stream_adapter_tb/sort/geardown/out_valid +/sortnet_stream_adapter_tb/sort/geardown/out_data +/sortnet_stream_adapter_tb/sort/geardown/out_meta +/sortnet_stream_adapter_tb/sort/geardown/out_first +/sortnet_stream_adapter_tb/sort/geardown/out_last +/sortnet_stream_adapter_tb/sort/geardown/in_sync_d +/sortnet_stream_adapter_tb/sort/geardown/in_data_d +/sortnet_stream_adapter_tb/sort/geardown/in_meta_d +/sortnet_stream_adapter_tb/sort/geardown/in_valid_d +/sortnet_stream_adapter_tb/sort/geardown/muxselect_rst +/sortnet_stream_adapter_tb/sort/geardown/muxselect_en +/sortnet_stream_adapter_tb/sort/geardown/muxselect_us +/sortnet_stream_adapter_tb/sort/geardown/muxselect_ov +/sortnet_stream_adapter_tb/sort/geardown/nxt +/sortnet_stream_adapter_tb/sort/geardown/autoincrement +/sortnet_stream_adapter_tb/sort/geardown/gearboxinput +/sortnet_stream_adapter_tb/sort/geardown/gearboxbuffer_en +/sortnet_stream_adapter_tb/sort/geardown/gearboxbuffer +/sortnet_stream_adapter_tb/sort/geardown/gearboxoutput +/sortnet_stream_adapter_tb/sort/geardown/syncout +/sortnet_stream_adapter_tb/sort/geardown/validout +/sortnet_stream_adapter_tb/sort/geardown/dataout +/sortnet_stream_adapter_tb/sort/geardown/metaout +/sortnet_stream_adapter_tb/sort/geardown/firstout +/sortnet_stream_adapter_tb/sort/geardown/lastout +/sortnet_stream_adapter_tb/sort/geardown/out_sync_d +/sortnet_stream_adapter_tb/sort/geardown/out_valid_d +/sortnet_stream_adapter_tb/sort/geardown/out_data_d +/sortnet_stream_adapter_tb/sort/geardown/out_meta_d +/sortnet_stream_adapter_tb/sort/geardown/out_first_d +/sortnet_stream_adapter_tb/sort/geardown/out_last_d +/sortnet_stream_adapter_tb/sort/geardown//muxinput diff --git a/sim/sort/sortnet/sortnet_Stream_Adapter_tb.gtkw b/sim/sort/sortnet/sortnet_Stream_Adapter_tb.gtkw index ec250657..a54fe064 100644 --- a/sim/sort/sortnet/sortnet_Stream_Adapter_tb.gtkw +++ b/sim/sort/sortnet/sortnet_Stream_Adapter_tb.gtkw @@ -2,10 +2,8 @@ [*] GTKWave Analyzer v3.3.69 (w)1999-2016 BSI [*] Sun Mar 20 17:07:11 2016 [*] -[dumpfile] "G:\git\PoC\temp\ghdl\sortnet_Stream_Adapter_tb.ghw" [dumpfile_mtime] "Sun Mar 20 17:06:47 2016" [dumpfile_size] 89113 -[savefile] "G:\git\PoC\sim\sort\sortnet\sortnet_Stream_Adapter_tb.gtkw" [timestart] 0 [size] 1676 997 [pos] -1 -1 diff --git a/src/arith/arith.pkg.vhdl b/src/arith/arith.pkg.vhdl index 15941eae..8d05380e 100644 --- a/src/arith/arith.pkg.vhdl +++ b/src/arith/arith.pkg.vhdl @@ -1,7 +1,6 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Thomas B. Preusser -- Martin Zabel @@ -11,7 +10,7 @@ -- associated to the PoC.arith namespace -- -- Description: --- ------------------------------------ +-- ------------------------------------- -- For detailed documentation see below. -- -- License: @@ -185,12 +184,12 @@ package arith is component arith_carrychain_inc_xilinx is generic ( - BITS : POSITIVE + BITS : positive ); port ( - X : in STD_LOGIC_VECTOR(BITS - 1 downto 0); - CIn : in STD_LOGIC := '1'; - Y : out STD_LOGIC_VECTOR(BITS - 1 downto 0) + X : in std_logic_vector(BITS - 1 downto 0); + CIn : in std_logic := '1'; + Y : out std_logic_vector(BITS - 1 downto 0) ); end component; diff --git a/src/arith/arith_addw.vhdl b/src/arith/arith_addw.vhdl index 8ed25b04..ca5aedf4 100644 --- a/src/arith/arith_addw.vhdl +++ b/src/arith/arith_addw.vhdl @@ -1,14 +1,13 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Thomas B. Preusser -- -- Entity: arith_addw -- -- Description: --- ------------------------------------ +-- ------------------------------------- -- Implements wide addition providing several options all based -- on an adaptation of a carry-select approach. -- diff --git a/src/arith/arith_carrychain_inc.vhdl b/src/arith/arith_carrychain_inc.vhdl index 2c7f56db..b60a2fe3 100644 --- a/src/arith/arith_carrychain_inc.vhdl +++ b/src/arith/arith_carrychain_inc.vhdl @@ -1,20 +1,19 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: Carry-chain abstraction for increment by one operations +-- Entity: Carry-chain abstraction for increment by one operations -- -- Description: --- ------------------------------------ +-- ------------------------------------- -- This is a generic carry-chain abstraction for increment by one operations. -- -- Y <= X + (0...0) & Cin -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -29,7 +28,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.std_logic_1164.all; @@ -43,28 +42,29 @@ use PoC.arith.all; entity arith_carrychain_inc is generic ( - BITS : POSITIVE + BITS : positive ); port ( - X : in STD_LOGIC_VECTOR(BITS - 1 downto 0); - CIn : in STD_LOGIC := '1'; - Y : out STD_LOGIC_VECTOR(BITS - 1 downto 0) + X : in std_logic_vector(BITS - 1 downto 0); + CIn : in std_logic := '1'; + Y : out std_logic_vector(BITS - 1 downto 0) ); end entity; architecture rtl of arith_carrychain_inc is -- Force Carry-chain use for pointer increments on Xilinx architectures - constant XILINX_FORCE_CARRYCHAIN : BOOLEAN := (not SIMULATION) and (VENDOR = VENDOR_XILINX) and (BITS > 4); + constant XILINX_FORCE_CARRYCHAIN : boolean := (not SIMULATION) and (VENDOR = VENDOR_XILINX) and (BITS > 4); begin - genGeneric : if (XILINX_FORCE_CARRYCHAIN = FALSE) generate - signal Zero : UNSIGNED(BITS - 1 downto 1) := (others => '0'); + genGeneric : if not XILINX_FORCE_CARRYCHAIN generate + signal Cin_vec : unsigned(0 downto 0); begin - Y <= std_logic_vector(unsigned(X) + (Zero & CIn)); + Cin_vec(0) <= Cin; -- WORKAROUND: for GHDL + Y <= std_logic_vector(unsigned(X) + Cin_vec); end generate; - genXilinx : if (XILINX_FORCE_CARRYCHAIN = TRUE) generate + genXilinx : if XILINX_FORCE_CARRYCHAIN generate inc : arith_carrychain_inc_xilinx generic map ( BITS => BITS diff --git a/src/arith/arith_cca.files b/src/arith/arith_cca.files new file mode 100644 index 00000000..02bbc19f --- /dev/null +++ b/src/arith/arith_cca.files @@ -0,0 +1,17 @@ +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# ============================================================================== +# Note: all files are relative to PoC root directory +# +# Load external vendor libraries +if (DeviceVendor = "Xilinx") then + include "lib/Xilinx.files" # Xilinx primitives +end if + +# Common PoC packages for configuration, synthesis and simulation +include "src/common/common.files" # load common packages + +# PoC.arith +vhdl PoC "src/arith/arith.pkg.vhdl" # PoC.arith package +vhdl PoC "src/arith/arith_cca.vhdl" # Top-Level diff --git a/src/arith/arith_cca.vhdl b/src/arith/arith_cca.vhdl new file mode 100644 index 00000000..0665ab48 --- /dev/null +++ b/src/arith/arith_cca.vhdl @@ -0,0 +1,190 @@ +-- =================================================================================== +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- +-- ============================================================================= +-- Description: Carry-Compact Adder for Xilinx Virtex-5 architectures and newer. +-- +-- A carry-compact adder (CCA) utilizes the fast carry chain of contemporary +-- FPGA devices to implement a fast and even compacted binary word addition. +-- For wide operands, it accounts for the delay encountered even on this fast +-- signal path and uses the associated time to perform a significantly +-- shorter but effective LUT-based parallel computation that reduces the +-- length of the internal ripple-carry adder without affecting the critical +-- path length. +-- The compaction performed by the CCA is performed hierarchical on +-- potentially multiple levels. The number of levels may be restricted by the +-- optional generic parameter X. A linear compaction on a single level may +-- be of special interest as it typically does not increase the LUT demand +-- in comparison to a standard RCA implementation. +-- The parameter L is architecture-dependent and estimates the delay of a LUT +-- stage in terms of carry-chain hops. It is a tuning parameter. Values +-- around 20 are a good starting point. +-- +-- For a detailed description see: http://dx.doi.org/10.1109/ARITH.2011.22 +-- +-- Preusser, T.B.; Zabel, M.; Spallek, R.G.: +-- "Accelerating Computations on FPGA Carry Chains by Operand Compaction", +-- 20th IEEE Symposium on Computer Arithmetic (ARITH), 2011. +-- +-- Author: Thomas B. Preusser +-- ================================================================================ +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- =================================================================================== + +library IEEE; +use IEEE.std_logic_1164.all; + +entity arith_cca is + generic( + N : positive; -- bit width + L : natural; -- CC length equivalent per LUT stage + X : natural := 0 -- max expansion depth; default: zero (0) - unlimited + ); + port( + a : in std_logic_vector(N-1 downto 0); + b : in std_logic_vector(N-1 downto 0); + c : in std_logic := '0'; + s : out std_logic_vector(N-1 downto 0) + ); +end arith_cca; + + +library IEEE; +use IEEE.numeric_std.all; + +architecture rtl of arith_cca is + + type tLevel is record + base : natural; + core : integer; + done : natural; + end record tLevel; + type tLevels is array(natural range<>) of tLevel; + + function compact return tLevels is + variable res : tLevels(0 to 31); + variable base, core, done : integer; + begin + base := 0; + core := (N-L)/2; + done := N-2*core; + for i in res'range loop + res(i) := (base, core, done); + if core <= 0 then + for j in 0 to i loop + report integer'image(j)&": ("&integer'image(res(j).base)&", "&integer'image(res(j).core)&", "&integer'image(res(j).done)&")" severity note; + end loop; -- j + return res(0 to i); + end if; + base := base + 2*core; + done := done + (core-2*(core/2)+L); + core := core/2 - L; + if i+1 = X and core > 0 then + done := done + 2*core; + core := 0; + end if; + end loop; + end function compact; + constant LEVELS : tLevels := compact; + constant CCA : boolean := LEVELS'length > 1; + +begin + genRCA: if not CCA generate + assert false + report "Using standard RCA for small "&integer'image(N)&"-bit adder." + severity note; + s <= std_logic_vector(unsigned(a)+unsigned(b)+(0 to 0 => c)); + end generate; + + genCCA: if CCA generate + constant WI : positive := LEVELS(LEVELS'high).base; + constant WC : positive := LEVELS(LEVELS'high).done + LEVELS'high*L + 2*LEVELS(LEVELS'high).core; + + signal ai, bi, si : std_logic_vector(WI-1 downto 0); + signal ac, bc, sc : unsigned(WC-1 downto 0); + begin + + -- Feed operands into compaction tree except for a prefix of L bits + -- to hide expansion delay of lower-order bits + blkFeed: block is + constant DONE : natural := LEVELS(0).done; + begin + -- alias most-significant prefix of ports and compacted operation + genPre: if DONE > 0 generate + ac(WC-1 downto WC-DONE) <= unsigned(a(N-1 downto N-DONE)); + bc(WC-1 downto WC-DONE) <= unsigned(b(N-1 downto N-DONE)); + s(N-1 downto N-DONE) <= std_logic_vector(sc(WC-1 downto WC-DONE)); + end generate genPre; + + -- copy compaction region + ai(N-DONE-1 downto 0) <= a(N-DONE-1 downto 0); + bi(N-DONE-1 downto 0) <= b(N-DONE-1 downto 0); + s(N-DONE-1 downto 0) <= si(N-DONE-1 downto 0); + end block blkFeed; + + -- Build the compaction tree + genCompact: for i in 1 to LEVELS'high generate + constant PAIRS : positive := LEVELS(i-1).core; + + constant BASE : natural := LEVELS(i).base; + constant CORE : integer := LEVELS(i).core; + constant DONE : natural := LEVELS(i).done; + + begin + genPairs: for j in 0 to PAIRS-1 generate + signal b1, b0, a1, a0 : std_logic; + signal ss : std_logic; + begin + -- Compaction ------ + + -- Simplify Names + b1 <= bi(BASE-2*(PAIRS-j)+1); + b0 <= bi(BASE-2*(PAIRS-j)+0); + a1 <= ai(BASE-2*(PAIRS-j)+1); + a0 <= ai(BASE-2*(PAIRS-j)+0); + + genLast: if CORE <= 0 or j < L or L+2*CORE <= j generate + signal aa, bb : std_logic; + begin + aa <= (b1 and a1) or (b1 and a0) or (a1 and a0); + bb <= (b1 and a1) or (b1 and b0) or (a1 and b0); + + genSuf: if CORE <= 0 or j < L generate + ac((i-1)*L+j) <= aa; + bc((i-1)*L+j) <= bb; + ss <= sc((i-1)*L+j); + end generate genSuf; + genPre: if CORE > 0 and L+2*CORE <= j generate + ac(j-L-2*CORE+(WC-DONE)) <= aa; + bc(j-L-2*CORE+(WC-DONE)) <= bb; + ss <= sc(j-L-2*CORE+(WC-DONE)); + end generate genPre; + end generate genLast; + + genCore: if CORE > 0 and L <= j and j < L+2*CORE generate + ss <= si(BASE-L+j); + ai(BASE-L+j) <= (b1 and a1) or ((b1 xor a1) and a0); + bi(BASE-L+j) <= (b1 and a1) or ((b1 xor a1) and b0); + end generate genCore; + + -- Expansion ------ + si(BASE-2*(PAIRS-j)+0) <= (b0 xor a0) xor (ss xor ((b1 xor a1) and (b0 xor a0))); + si(BASE-2*(PAIRS-j)+1) <= (b1 xor a1) xor ((b0 and a0) or ((b0 xor a0) and (ss xor ((b1 xor a1) and (b0 xor a0))))); + end generate genPairs; + end generate genCompact; + sc <= ac + bc + (0 to 0 => c); + end generate genCCA; + +end rtl; diff --git a/src/arith/arith_convert_bin2bcd.vhdl b/src/arith/arith_convert_bin2bcd.vhdl index 206a7fea..861573b5 100644 --- a/src/arith/arith_convert_bin2bcd.vhdl +++ b/src/arith/arith_convert_bin2bcd.vhdl @@ -1,15 +1,14 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Patrick Lehmann -- -- Entity: Converter binary numbers to BCD encoded numbers. -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: -- ============================================================================= @@ -30,8 +29,8 @@ -- ============================================================================= library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; library PoC; use PoC.utils.all; @@ -40,48 +39,48 @@ use PoC.components.all; entity arith_convert_bin2bcd is generic ( - BITS : POSITIVE := 8; - DIGITS : POSITIVE := 3; - RADIX : POSITIVE := 2 + BITS : positive := 8; + DIGITS : positive := 3; + RADIX : positive := 2 ); port ( - Clock : in STD_LOGIC; - Reset : in STD_LOGIC; + Clock : in std_logic; + Reset : in std_logic; - Start : in STD_LOGIC; - Busy : out STD_LOGIC; + Start : in std_logic; + Busy : out std_logic; - Binary : in STD_LOGIC_VECTOR(BITS - 1 downto 0); - IsSigned : in STD_LOGIC := '0'; + Binary : in std_logic_vector(BITS - 1 downto 0); + IsSigned : in std_logic := '0'; BCDDigits : out T_BCD_VECTOR(DIGITS - 1 downto 0); - Sign : out STD_LOGIC + Sign : out std_logic ); -end; +end entity; architecture rtl of arith_convert_bin2bcd is - constant RADIX_BITS : POSITIVE := log2ceil(RADIX); - constant BINARY_SHIFTS : POSITIVE := div_ceil(BITS, RADIX_BITS); - constant BINARY_BITS : POSITIVE := BINARY_SHIFTS * RADIX_BITS; + constant RADIX_BITS : positive := log2ceil(RADIX); + constant BINARY_SHIFTS : positive := div_ceil(BITS, RADIX_BITS); + constant BINARY_BITS : positive := BINARY_SHIFTS * RADIX_BITS; - subtype T_CARRY is UNSIGNED(RADIX_BITS - 1 downto 0); - type T_CARRY_VECTOR is array(NATURAL range <>) of T_CARRY; + subtype T_CARRY is unsigned(RADIX_BITS - 1 downto 0); + type T_CARRY_VECTOR is array(natural range <>) of T_CARRY; - signal Digit_Shift_rst : STD_LOGIC; - signal Digit_Shift_en : STD_LOGIC; + signal Digit_Shift_rst : std_logic; + signal Digit_Shift_en : std_logic; signal Digit_Shift_in : T_CARRY_VECTOR(DIGITS downto 0); - signal Binary_en : STD_LOGIC; - signal Binary_rl : STD_LOGIC; - signal Binary_d : STD_LOGIC_VECTOR(BINARY_BITS - 1 downto 0) := (others => '0'); + signal Binary_en : std_logic; + signal Binary_rl : std_logic; + signal Binary_d : std_logic_vector(BINARY_BITS - 1 downto 0) := (others => '0'); - signal Sign_d : STD_LOGIC := '0'; - signal DelayShifter : STD_LOGIC_VECTOR(BINARY_SHIFTS downto 0) := '1' & (BINARY_SHIFTS - 1 downto 0 => '0'); + signal Sign_d : std_logic := '0'; + signal DelayShifter : std_logic_vector(BINARY_SHIFTS downto 0) := '1' & (BINARY_SHIFTS - 1 downto 0 => '0'); - function nextBCD(Value : UNSIGNED(4 downto 0)) return UNSIGNED is - constant Temp : UNSIGNED(4 downto 0) := Value - 10; + function nextBCD(Value : unsigned(4 downto 0)) return unsigned is + constant Temp : unsigned(4 downto 0) := Value - 10; begin - if (Value > 9) then + if Value > 9 then return '1' & Temp(3 downto 0); else return Value; @@ -104,7 +103,7 @@ begin elsif (Binary_en = '1') then Binary_d(Binary_d'high downto Binary'high) <= (others => '0'); if ((IsSigned and Binary(Binary'high)) = '1') then - Binary_d(Binary'high downto 0) <= inc(not(Binary)); + Binary_d(Binary'high downto 0) <= std_logic_vector(-signed(Binary)); Sign_d <= '1'; else Binary_d(Binary'high downto 0) <= Binary; @@ -123,11 +122,11 @@ begin -- generate DIGITS many systolic elements genDigits : for i in 0 to DIGITS - 1 generate - signal Digit_nxt : UNSIGNED(3 + RADIX_BITS downto 0); - signal Digit_d : UNSIGNED(3 downto 0) := (others => '0'); + signal Digit_nxt : unsigned(3 + RADIX_BITS downto 0); + signal Digit_d : unsigned(3 downto 0) := (others => '0'); begin process(Digit_d, Digit_Shift_in) - variable Temp : UNSIGNED(4 downto 0); + variable Temp : unsigned(4 downto 0); begin Temp := '0' & Digit_d; for j in RADIX_BITS - 1 downto 0 loop @@ -142,7 +141,7 @@ begin begin if rising_edge(Clock) then if (Digit_Shift_rst = '1') then - Digit_d <= "0000"; + Digit_d <= "0000"; elsif (Digit_Shift_en = '1') then Digit_d <= Digit_nxt(Digit_d'range); end if; diff --git a/src/arith/arith_counter_bcd.vhdl b/src/arith/arith_counter_bcd.vhdl index 02b57fab..928aa965 100644 --- a/src/arith/arith_counter_bcd.vhdl +++ b/src/arith/arith_counter_bcd.vhdl @@ -1,29 +1,29 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Martin Zabel -- Thomas B. Preusser -- --- Module: BCD counter. +-- Entity: BCD counter. -- -- Description: --- ------------------------------------ --- Counter with output in binary coded decimal (BCD). --- The number of BCD digits is configurable. +-- ------------------------------------- +-- Counter with output in binary coded decimal (BCD). The number of BCD digits +-- is configurable by ``DIGITS``. +-- +-- All control signals (reset ``rst``, increment ``inc``) are high-active and +-- synchronous to clock ``clk``. The output ``val`` is the current counter +-- state. Groups of 4 bit represent one BCD digit. The lowest significant digit +-- is specified by ``val(3 downto 0)``. -- --- All control signals (reset 'rst', increment 'inc') are high-active and --- synchronous to clock 'clk'. --- The output 'val' is the current counter state. Groups of 4 bit represent one --- BCD digit. The lowest significant digit is specified by val(3 downto 0). +-- .. TODO:: -- --- TODO: --- - implement a 'dec' input for decrementing --- - implement a 'load' input to load a value +-- * implement a ``dec`` input for decrementing +-- * implement a ``load`` input to load a value -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -38,7 +38,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.std_logic_1164.all; @@ -76,7 +76,7 @@ begin p(i) <= cnt_r(3) and cnt_r(0); -- Local Overflow at digit 9 process(clk) begin - if(rising_edge(clk)) then + if rising_edge(clk) then if rst = '1' then cnt_r <= (others => '0'); elsif (inc and c(i)) = '1' then -- short critical path for 'inc' diff --git a/src/arith/arith_counter_free.vhdl b/src/arith/arith_counter_free.vhdl index ce13596d..f4f8e6f5 100644 --- a/src/arith/arith_counter_free.vhdl +++ b/src/arith/arith_counter_free.vhdl @@ -1,25 +1,24 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- =========================================================================== --- Module: Poc.arith_counter_free --- +-- ============================================================================= -- Authors: Thomas B. Preusser -- +-- Entity: Poc.arith_counter_free +-- -- Description: --- ------------ --- Implements a free-running counter that generates a strobe signal --- every DIVIDER-th cycle the increment input was asserted. --- There is deliberately no output or specification of the counter --- value so as to allow an implementation to optimize as much as --- possible. --- The implementation guarantees a strobe output directly from a --- register. It is asserted exactly for one clock after DIVIDER cycles --- of an asserted increment input have been observed. +-- ------------------------------------- +-- Implements a free-running counter that generates a strobe signal every +-- DIVIDER-th cycle the increment input was asserted. There is deliberately no +-- output or specification of the counter value so as to allow an implementation +-- to optimize as much as possible. +-- +-- The implementation guarantees a strobe output directly from a register. It is +-- asserted exactly for one clock after DIVIDER cycles of an asserted increment +-- input have been observed. -- -- License: --- =========================================================================== +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -34,7 +33,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- =========================================================================== +-- ============================================================================= library IEEE; use IEEE.std_logic_1164.all; @@ -51,7 +50,7 @@ entity arith_counter_free is inc : in std_logic; stb : out std_logic -- End-of-Period Strobe ); -end arith_counter_free; +end entity arith_counter_free; library IEEE; diff --git a/src/arith/arith_counter_gray.vhdl b/src/arith/arith_counter_gray.vhdl index f7c76c12..904d166e 100644 --- a/src/arith/arith_counter_gray.vhdl +++ b/src/arith/arith_counter_gray.vhdl @@ -1,20 +1,19 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ --- Module: Gray-Code counter. --- +-- ============================================================================= -- Authors: Thomas B. Preusser -- Martin Zabel -- Steffen Koehler -- +-- Entity: Gray-Code counter. +-- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2014 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -29,7 +28,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library ieee; use ieee.std_logic_1164.all; @@ -49,7 +48,7 @@ entity arith_counter_gray is val : out std_logic_vector(BITS-1 downto 0); -- Value output cry : out std_logic -- Carry output ); -end arith_counter_gray; +end entity arith_counter_gray; architecture rtl of arith_counter_gray is @@ -149,7 +148,7 @@ begin par_nxt <= s(0) xor dec; end process; - cry <= ((gray_cnt_r(BITS-1) xor dec) and (gray_cnt_nxt(BITS-1) xnor dec)); + cry <= (gray_cnt_r(BITS-1) xor dec) and (gray_cnt_nxt(BITS-1) xnor dec); end generate g2; end rtl; diff --git a/src/arith/arith_counter_ring.vhdl b/src/arith/arith_counter_ring.vhdl index 6fd21031..a19955d4 100644 --- a/src/arith/arith_counter_ring.vhdl +++ b/src/arith/arith_counter_ring.vhdl @@ -1,19 +1,21 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ --- Module: TODO --- +-- ============================================================================= -- Authors: Patrick Lehmann -- +-- Entity: Ring counter/Johnson Counter +-- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- This module implements an up/down ring-counter with loadable initial value +-- (``seed``) on reset. The counter can be configured to a Johnson counter by +-- enabling ``INVERT_FEEDBACK``. The number of counter bits is configurable with +-- ``BITS``. -- -- License: --- ============================================================================ --- Copyright 2007-2014 Technische Universitaet Dresden - Germany +-- ============================================================================= +-- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); @@ -27,51 +29,49 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; +library IEEE; +use IEEE.STD_LOGIC_1164.all; -LIBRARY PoC; -USE PoC.utils.ALL; +library PoC; +use PoC.utils.all; -ENTITY arith_counter_ring IS - GENERIC ( - BITS : POSITIVE; - INVERT_FEEDBACK : BOOLEAN := FALSE -- FALSE -> ring counter; TRUE -> johnson counter +entity arith_counter_ring is + generic ( + BITS : positive; + INVERT_FEEDBACK : boolean := FALSE -- FALSE -> ring counter; TRUE -> johnson counter ); - PORT ( - Clock : IN STD_LOGIC; -- Clock - Reset : IN STD_LOGIC; -- Reset - seed : IN STD_LOGIC_VECTOR(BITS - 1 DOWNTO 0) := (OTHERS => '0'); -- initial counter vector / load value - inc : IN STD_LOGIC := '0'; -- increment counter - dec : IN STD_LOGIC := '0'; -- decrement counter - value : OUT STD_LOGIC_VECTOR(BITS - 1 DOWNTO 0) -- counter value + port ( + Clock : in std_logic; -- Clock + Reset : in std_logic; -- Reset + seed : in std_logic_vector(BITS - 1 downto 0) := (others => '0'); -- initial counter vector / load value + inc : in std_logic := '0'; -- increment counter + dec : in std_logic := '0'; -- decrement counter + value : out std_logic_vector(BITS - 1 downto 0) -- counter value ); -END; +end entity; -ARCHITECTURE rtl OF arith_counter_ring IS - CONSTANT INVERT : STD_LOGIC := to_sl(INVERT_FEEDBACK); +architecture rtl of arith_counter_ring is + constant invert : std_logic := to_sl(INVERT_FEEDBACK); - SIGNAL counter : STD_LOGIC_VECTOR(BITS - 1 DOWNTO 0) := (OTHERS => '0'); + signal Counter : std_logic_vector(BITS - 1 downto 0) := (others => '0'); -BEGIN - PROCESS(Clock) - BEGIN - IF rising_edge(Clock) THEN - IF (Reset = '1') THEN - counter <= seed; - ELSE - IF (inc = '1') THEN - counter <= counter(counter'high - 1 DOWNTO 0) & (counter(counter'high) XOR INVERT); - ELSIF (dec = '1') THEN - counter <= (counter(0) XOR INVERT) & counter(counter'high DOWNTO 1); - END IF; - END IF; - END IF; - END PROCESS; +begin + process(Clock) + begin + if rising_edge(Clock) then + if (Reset = '1') then + Counter <= seed; + elsif (inc = '1') then + Counter <= Counter(Counter'high - 1 downto 0) & (Counter(Counter'high) xor invert); + elsif (dec = '1') then + Counter <= (Counter(0) xor invert) & Counter(Counter'high downto 1); + end if; + end if; + end process; - value <= counter; -END; + value <= Counter; +end architecture; diff --git a/src/arith/arith_div.vhdl b/src/arith/arith_div.vhdl index 11996928..c2252374 100644 --- a/src/arith/arith_div.vhdl +++ b/src/arith/arith_div.vhdl @@ -1,19 +1,20 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Thomas B. Preusser -- --- Module: Multi-cycle Non-Performing Restoring Divider +-- Entity: Multi-cycle Non-Performing Restoring Divider -- -- Description: --- ------------------------------------ --- Implementation of a Non-Performing restoring divider with a configurable radix. --- The multi-cycle division is controlled by 'start' / 'rdy'. A new division is --- started by asserting 'start'. The result Q = A/D is available when 'rdy' --- returns to '1'. A division by zero is identified by output Z. The Q and R --- outputs are undefined in this case. +-- ------------------------------------- +-- Implementation of a Non-Performing restoring divider with a configurable radix. +-- The multi-cycle division is controlled by 'start' / 'rdy'. A new division is +-- started by asserting 'start'. The result Q = A/D is available when 'rdy' +-- returns to '1'. A division by zero is identified by output Z. The Q and R +-- outputs are undefined in this case. +-- +-- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universität Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture @@ -57,7 +58,7 @@ entity arith_div is R : out std_logic_vector(D_BITS-1 downto 0); -- Remainder Z : out std_logic -- Division by Zero ); -end arith_div; +end entity arith_div; library IEEE; diff --git a/src/arith/arith_firstone.vhdl b/src/arith/arith_firstone.vhdl index 98d1543d..3d0cb990 100644 --- a/src/arith/arith_firstone.vhdl +++ b/src/arith/arith_firstone.vhdl @@ -1,26 +1,30 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; +-- ============================================================================= +-- Authors: Thomas B. Preusser +-- +-- Entity: TODO -- --- =========================================================================== -- Description: --- Computes from an input word, a word of the same size that has, at most, --- one bit set. The output contains a set bit at the position of the --- rightmost set bit of the input if and only if such a set bit exists in the --- input. --- A typical use case for this computation would be an arbitration over --- requests with a fixed and strictly ordered priority. The terminology of --- the interface assumes this use case and provides some useful extras: +-- ------------------------------------- +-- Computes from an input word, a word of the same size that has, at most, +-- one bit set. The output contains a set bit at the position of the rightmost +-- set bit of the input if and only if such a set bit exists in the input. +-- +-- A typical use case for this computation would be an arbitration over +-- requests with a fixed and strictly ordered priority. The terminology of +-- the interface assumes this use case and provides some useful extras: -- --- - Set tin <= '0' (no input token) to disallow grants altogether. --- - Read tout (unused token) to see whether or any grant was issued. --- - Read bin to obtain the binary index of the rightmost detected one bit. --- The index starts at zero (0) in the rightmost bit position. +-- * Set tin <= '0' (no input token) to disallow grants altogether. +-- * Read tout (unused token) to see whether or any grant was issued. +-- * Read bin to obtain the binary index of the rightmost detected one bit. +-- The index starts at zero (0) in the rightmost bit position. -- --- This implementation uses carry chains for wider implementations. +-- This implementation uses carry chains for wider implementations. -- --- Authors: Thomas B. Preusser --- =========================================================================== +-- License: +-- ============================================================================= -- Copyright 2007-2015 Technische Universität Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -35,7 +39,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- =========================================================================== +-- ============================================================================= library IEEE; use IEEE.std_logic_1164.all; @@ -54,7 +58,7 @@ entity arith_firstone is tout : out std_logic; -- Inactive: Unused Token bin : out std_logic_vector(log2ceil(N)-1 downto 0) -- Binary Grant Index ); -end arith_firstone; +end entity arith_firstone; library IEEE; diff --git a/src/arith/arith_prefix_and.vhdl b/src/arith/arith_prefix_and.vhdl index 21e93621..ac665127 100644 --- a/src/arith/arith_prefix_and.vhdl +++ b/src/arith/arith_prefix_and.vhdl @@ -1,7 +1,6 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Thomas B. Preusser -- Patrick Lehmann @@ -9,11 +8,12 @@ -- Entity: Prefix AND computation -- -- Description: --- ------------------------------------ --- Prefix AND computation: --- y(i) <= '1' when x(i downto 0) = (i downto 0 => '1') else '0' --- This implementation uses carry chains for wider implementations. +-- ------------------------------------- +-- Prefix AND computation: +-- ``y(i) <= '1' when x(i downto 0) = (i downto 0 => '1') else '0';`` +-- This implementation uses carry chains for wider implementations. -- +-- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universität Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture @@ -70,7 +70,7 @@ begin y(1) <= p(1); end generate gen1; end generate; - genXilinx : if (VENDOR = VENDOR_XILINX) generate + genXilinx : if VENDOR = VENDOR_XILINX generate prefix : arith_prefix_and_xilinx generic map ( N => N diff --git a/src/arith/arith_prefix_or.vhdl b/src/arith/arith_prefix_or.vhdl index 4f8fefda..8e60f3db 100644 --- a/src/arith/arith_prefix_or.vhdl +++ b/src/arith/arith_prefix_or.vhdl @@ -1,7 +1,6 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Thomas B. Preusser -- Patrick Lehmann @@ -9,11 +8,12 @@ -- Entity: Prefix OR computation -- -- Description: --- ------------------------------------ --- Prefix OR computation: --- y(i) <= '0' when x(i downto 0) = (i downto 0 => '0') else '1'; --- This implementation uses carry chains for wider implementations. +-- ------------------------------------- +-- Prefix OR computation: +-- ``y(i) <= '0' when x(i downto 0) = (i downto 0 => '0') else '1';`` +-- This implementation uses carry chains for wider implementations. -- +-- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universität Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture @@ -54,7 +54,7 @@ end entity; architecture rtl of arith_prefix_or is begin -- Generic Carry Chain through Addition - genGeneric: if (VENDOR /= VENDOR_XILINX) generate + genGeneric: if VENDOR /= VENDOR_XILINX generate y(0) <= x(0); gen1: if N > 1 generate signal p : unsigned(N-1 downto 1); @@ -70,7 +70,7 @@ begin y(1) <= p(1); end generate gen1; end generate; - genXilinx : if (VENDOR = VENDOR_XILINX) generate + genXilinx : if VENDOR = VENDOR_XILINX generate prefix : arith_prefix_or_xilinx generic map ( N => N diff --git a/src/arith/arith_prng.vhdl b/src/arith/arith_prng.vhdl index 59b1e29c..63bc2074 100644 --- a/src/arith/arith_prng.vhdl +++ b/src/arith/arith_prng.vhdl @@ -1,20 +1,24 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- =================================================================================== +-- ============================================================================= -- Authors: Martin Zabel -- Patrick Lehmann -- --- Module: Pseudo-Random Number Generator (PRNG). +-- Entity: Pseudo-Random Number Generator (PRNG). -- -- Description: --- ------------------------------------ --- The number sequence includes the value all-zeros, but not all-ones. --- Synchronized Reset is used. +-- ------------------------------------- +-- This module implementes a Pseudo-Random Number Generator (PRNG) with +-- configurable bit count (``BITS``). This module uses an internal list of FPGA +-- optimized polynomials from 3 to 168 bits. The polynomials have at most 5 tap +-- positions, so that long shift registers can be inferred instead of single +-- flip-flops. +-- +-- The generated number sequence includes the value all-zeros, but not all-ones. -- -- License: --- =================================================================================== +-- ============================================================================= -- Copyright 2007-2014 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -29,7 +33,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- =================================================================================== +-- ============================================================================= library ieee; use ieee.std_logic_1164.all; @@ -54,7 +58,7 @@ end entity; architecture rtl of arith_prng is - subtype T_TAPPOSITION is T_NATVEC(0 TO 4); + subtype T_TAPPOSITION is T_NATVEC(0 to 4); type T_TAPPOSITION_VECTOR is array (natural range <>) of T_TAPPOSITION; -- Tap positions are taken from Xilinx Application Note 052 (XAPP052) @@ -245,7 +249,7 @@ begin begin temp := val_r(val_r'left); for i in 0 to 4 loop - if (C_TAPPOSITIONS(i) > 0) then + if C_TAPPOSITIONS(i) > 0 then temp := temp xnor val_r(C_TAPPOSITIONS(i)); end if; end loop; diff --git a/src/arith/arith_same.vhdl b/src/arith/arith_same.vhdl index f0554476..37ce7eb4 100644 --- a/src/arith/arith_same.vhdl +++ b/src/arith/arith_same.vhdl @@ -1,24 +1,24 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================================================================================================ +-- ============================================================================= -- Authors: Thomas B. Preusser -- --- Module: This module detects whether all bit positions of a --- std_logic_vector have the same value. +-- Entity: This module detects whether all bit positions of a std_logic_vector have the same value. +-- -- Description: --- ------------------------------------ --- This circuit may, for instance, be used to detect the first sign change --- and, thus, the range of a two's complement number. +-- ------------------------------------- +-- This circuit may, for instance, be used to detect the first sign change +-- and, thus, the range of a two's complement number. -- --- These components may be chained by using the output of the predecessor as --- guard input. This chaining allows to have intermediate results available --- while still ensuring the use of a fast carry chain on supporting FPGA --- architectures. When chaining, make sure to overlap both vector slices by one --- bit position as to avoid an undetected sign change between the slices. +-- These components may be chained by using the output of the predecessor as +-- guard input. This chaining allows to have intermediate results available +-- while still ensuring the use of a fast carry chain on supporting FPGA +-- architectures. When chaining, make sure to overlap both vector slices by one +-- bit position as to avoid an undetected sign change between the slices. -- --- ============================================================================================================================================================ +-- License: +-- ============================================================================= -- Copyright 2007-2015 Technische Universität Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -33,7 +33,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================================================================================================ +-- ============================================================================= library IEEE; use IEEE.std_logic_1164.all; diff --git a/src/arith/arith_scaler.vhdl b/src/arith/arith_scaler.vhdl index 7dcd4ab2..b2c99c2a 100644 --- a/src/arith/arith_scaler.vhdl +++ b/src/arith/arith_scaler.vhdl @@ -1,16 +1,32 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; +-- ============================================================================= +-- Authors: Thomas B. Preusser -- --- =========================================================================== --- Description: A flexible scaler for fixed-point values. --- The scaler is implemented for a set of multiplier and --- divider values. Each individual scaling operation can --- arbitrarily select one value from each these sets. +-- Entity: A flexible scaler for fixed-point values. -- --- Authors: Thomas B. Preusser --- =========================================================================== --- Copyright 2007-2014 Technische Universitaet Dresden - Germany +-- Description: +-- ------------------------------------- +-- A flexible scaler for fixed-point values. The scaler is implemented for a set +-- of multiplier and divider values. Each individual scaling operation can +-- arbitrarily select one value from each these sets. +-- +-- The computation calculates: ``unsigned(arg) * MULS(msel) / DIVS(dsel)`` +-- rounded to the nearest (tie upwards) fixed-point result of the same precision +-- as ``arg``. +-- +-- The computation is started by asserting ``start`` to high for one cycle. If a +-- computation is running, it will be restarted. The completion of a calculation +-- is signaled via ``done``. ``done`` is high when no computation is in progress. +-- The result of the last scaling operation is stable and can be read from +-- ``res``. The weight of the LSB of ``res`` is the same as the LSB of ``arg``. +-- Make sure to tap a sufficient number of result bits in accordance to the +-- highest scaling ratio to be used in order to avoid a truncation overflow. +-- +-- License: +-- ============================================================================= +-- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); @@ -24,7 +40,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- =========================================================================== +-- ============================================================================= library IEEE; use IEEE.std_logic_1164.all; @@ -35,42 +51,22 @@ use poc.utils.all; entity arith_scaler is generic ( - -- The set of multipliers to choose from in scaling operations. - MULS : T_POSVEC := (0 => 1); - -- The set of divisors to choose from in scaling operations. - DIVS : T_POSVEC := (0 => 1) + MULS : T_POSVEC := (0 => 1); -- The set of multipliers to choose from in scaling operations. + DIVS : T_POSVEC := (0 => 1) -- The set of divisors to choose from in scaling operations. ); port ( - --------------------------------------------------------------------------- - -- System Control clk : in std_logic; rst : in std_logic; - --------------------------------------------------------------------------- - -- Start of Computation - -- Strobe 'start'. If a computation is running, it will be canceled. - -- The initiated computation calculates: - -- - -- unsigned(arg)*MULS(msel)/DIVS(dsel) - -- - -- rounded to the nearest (tie upwards) fixed-point result of the same - -- precision as 'arg'. - start : in std_logic; - arg : in std_logic_vector; + start : in std_logic; -- Start of Computation + arg : in std_logic_vector; -- Fixed-point value to be scaled msel : in std_logic_vector(log2ceil(MULS'length)-1 downto 0) := (others => '0'); dsel : in std_logic_vector(log2ceil(DIVS'length)-1 downto 0) := (others => '0'); - --------------------------------------------------------------------------- - -- Completion - -- 'done' is '1' when no computation is in progress. The result of the - -- last scaling operation is stable and can be read from 'res'. The weight - -- of the LSB of 'res' is the same as the LSB of 'arg'. Make sure to tap - -- a sufficient number of result bits in accordance to the highest scaling - -- ratio to be used in order to avoid a truncation overflow. - done : out std_logic; - res : out std_logic_vector + done : out std_logic; -- Completion + res : out std_logic_vector -- Result ); -end arith_scaler; +end entity arith_scaler; library IEEE; diff --git a/src/arith/arith_shifter_barrel.vhdl b/src/arith/arith_shifter_barrel.vhdl index 0df057bc..36418e88 100644 --- a/src/arith/arith_shifter_barrel.vhdl +++ b/src/arith/arith_shifter_barrel.vhdl @@ -1,23 +1,23 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: Universal Barrel-Shifter +-- Entity: Universal Barrel-Shifter -- -- Description: --- ------------------------------------ --- This Barrel-Shifter supports: --- - shifting and rotating --- - right and left operations --- - arithmetic and logic mode (only valid for shift operations) --- This is equivalent to the CPU instructions: SLL, SLA, SRL, SRA, RL, RR +-- ------------------------------------- +-- This Barrel-Shifter supports: +-- +-- * shifting and rotating +-- * right and left operations +-- * arithmetic and logic mode (only valid for shift operations) -- +-- This is equivalent to the CPU instructions: SLL, SLA, SRL, SRA, RL, RR -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -32,7 +32,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -44,24 +44,24 @@ use PoC.utils.all; entity arith_shifter_barrel is generic ( - BITS : POSITIVE := 32 + BITS : positive := 32 ); port ( - Input : in STD_LOGIC_VECTOR(BITS - 1 downto 0); - ShiftAmount : in STD_LOGIC_VECTOR(log2ceilnz(BITS) - 1 downto 0); - ShiftRotate : in STD_LOGIC; - LeftRight : in STD_LOGIC; - ArithmeticLogic : in STD_LOGIC; - Output : out STD_LOGIC_VECTOR(BITS - 1 downto 0) + Input : in std_logic_vector(BITS - 1 downto 0); + ShiftAmount : in std_logic_vector(log2ceilnz(BITS) - 1 downto 0); + ShiftRotate : in std_logic; + LeftRight : in std_logic; + ArithmeticLogic : in std_logic; + Output : out std_logic_vector(BITS - 1 downto 0) ); -end; +end entity; architecture rtl of arith_shifter_barrel is - constant STAGES : POSITIVE := log2ceilnz(BITS); + constant STAGES : positive := log2ceilnz(BITS); - subtype T_INTERMEDIATE_RESULT is STD_LOGIC_VECTOR(BITS - 1 downto 0); - type T_INTERMEDIATE_VECTOR is array (NATURAL range <>) of T_INTERMEDIATE_RESULT; + subtype T_INTERMEDIATE_RESULT is std_logic_vector(BITS - 1 downto 0); + type T_INTERMEDIATE_VECTOR is array (natural range <>) of T_INTERMEDIATE_RESULT; signal IntermediateResults : T_INTERMEDIATE_VECTOR(STAGES downto 0); @@ -70,7 +70,7 @@ begin Output <= IntermediateResults(STAGES); genStage : for i in 0 to STAGES - 1 generate - process(IntermediateResults(i), ShiftRotate, LeftRight, ArithmeticLogic) + process(IntermediateResults(i), ShiftRotate, LeftRight, ArithmeticLogic, ShiftAmount) begin if (ShiftAmount(i) = '0') then IntermediateResults(i + 1) <= IntermediateResults(i); -- NOP @@ -95,4 +95,4 @@ begin end if; end process; end generate; -end; \ No newline at end of file +end; diff --git a/src/arith/arith_sqrt.vhdl b/src/arith/arith_sqrt.vhdl index 4fce5425..77731924 100644 --- a/src/arith/arith_sqrt.vhdl +++ b/src/arith/arith_sqrt.vhdl @@ -1,14 +1,21 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; +-- ============================================================================= +-- Authors: Thomas B. Preußer -- --- ============================================================================================================================================================ --- Description: Iterative Square Root Extractor. --- Its computation requires (N+1)/2 steps for an argument bit width of N. +-- Entity: Iterative Square Root Extractor. -- --- Authors: Thomas B. Preußer --- ============================================================================================================================================================ --- Copyright 2007-2014 Technische Universität Dresden - Germany, Chair for VLSI-Design, Diagnostics and Architecture +-- Description: +-- ------------------------------------- +-- Iterative Square Root Extractor. +-- +-- Its computation requires (N+1)/2 steps for an argument bit width of N. +-- +-- License: +-- ============================================================================= +-- Copyright 2007-2014 Technische Universität Dresden - Germany, +-- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. @@ -21,7 +28,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================================================================================================ +-- ============================================================================= library IEEE; use IEEE.std_logic_1164.all; @@ -45,7 +52,7 @@ entity arith_sqrt is sqrt : out std_logic_vector((N-1)/2 downto 0); -- Result rdy : out std_logic -- Ready / Done ); -end arith_sqrt; +end entity arith_sqrt; architecture rtl of arith_sqrt is diff --git a/src/arith/xilinx/arith_addw_xilinx.vhdl b/src/arith/xilinx/arith_addw_xilinx.vhdl index 2a133d92..b1900767 100644 --- a/src/arith/xilinx/arith_addw_xilinx.vhdl +++ b/src/arith/xilinx/arith_addw_xilinx.vhdl @@ -1,14 +1,13 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Thomas B. Preusser -- -- Entity: arith_addw_xilinx -- -- Description: --- ------------------------------------ +-- ------------------------------------- -- Implements wide addition providing several options all based -- on an adaptation of a carry-select approach. -- diff --git a/src/arith/xilinx/arith_carrychain_inc_xilinx.vhdl b/src/arith/xilinx/arith_carrychain_inc_xilinx.vhdl index 2bd06a11..fb5ea857 100644 --- a/src/arith/xilinx/arith_carrychain_inc_xilinx.vhdl +++ b/src/arith/xilinx/arith_carrychain_inc_xilinx.vhdl @@ -1,21 +1,20 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: Carry-chain abstraction for increment by one operations +-- Entity: Carry-chain abstraction for increment by one operations -- -- Description: --- ------------------------------------ +-- ------------------------------------- -- This is a Xilinx specific carry-chain abstraction for increment by one -- operations. -- -- Y <= X + (0...0) & Cin -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -30,7 +29,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.std_logic_1164.all; @@ -41,19 +40,19 @@ use Unisim.VComponents.all; entity arith_carrychain_inc_xilinx is generic ( - BITS : POSITIVE + BITS : positive ); port ( - X : in STD_LOGIC_VECTOR(BITS - 1 downto 0); - CIn : in STD_LOGIC := '1'; - Y : out STD_LOGIC_VECTOR(BITS - 1 downto 0) + X : in std_logic_vector(BITS - 1 downto 0); + CIn : in std_logic := '1'; + Y : out std_logic_vector(BITS - 1 downto 0) ); end entity; architecture rtl of arith_carrychain_inc_xilinx is - signal ci : STD_LOGIC_VECTOR(BITS downto 0); - signal co : STD_LOGIC_VECTOR(BITS downto 0); + signal ci : std_logic_vector(BITS downto 0); + signal co : std_logic_vector(BITS downto 0); begin ci(0) <= CIn; diff --git a/src/arith/xilinx/arith_cca_xilinx.vhdl b/src/arith/xilinx/arith_cca_xilinx.vhdl new file mode 100644 index 00000000..4eded071 --- /dev/null +++ b/src/arith/xilinx/arith_cca_xilinx.vhdl @@ -0,0 +1,231 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- +-- ============================================================================= +-- Description: Carry-Compact Adder for Xilinx Virtex-5 architectures and newer. +-- +-- A carry-compact adder (CCA) utilizes the fast carry chain of contemporary +-- FPGA devices to implement a fast and even compacted binary word addition. +-- For wide operands, it accounts for the delay encountered even on this fast +-- signal path and uses the associated time to perform a significantly +-- shorter but effective LUT-based parallel computation that reduces the +-- length of the internal ripple-carry adder without affecting the critical +-- path length. +-- The compaction performed by the CCA is performed hierarchical on +-- potentially multiple levels. The number of levels may be restricted by the +-- optional generic parameter X. A linear compaction on a single level may +-- be of special interest as it typically does not increase the LUT demand +-- in comparison to a standard RCA implementation. +-- The parameter L is architecture-dependent and estimates the delay of a LUT +-- stage in terms of carry-chain hops. It is a tuning parameter. Values +-- around 20 are a good starting point. +-- +-- For a detailed description see: http://dx.doi.org/10.1109/ARITH.2011.22 +-- +-- Preusser, T.B.; Zabel, M.; Spallek, R.G.: +-- "Accelerating Computations on FPGA Carry Chains by Operand Compaction", +-- 20th IEEE Symposium on Computer Arithmetic (ARITH), 2011. +-- +-- Author: Thomas B. Preusser +-- ================================================================================ +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- =================================================================================== + +library IEEE; +use IEEE.std_logic_1164.all; + +entity arith_cca is + generic( + N : positive; -- bit width + L : natural; -- CC length equivalent per LUT stage + X : natural := 0 -- max expansion depth; default: zero (0) - unlimited + ); + port( + a : in std_logic_vector(N-1 downto 0); + b : in std_logic_vector(N-1 downto 0); + c : in std_logic := '0'; + s : out std_logic_vector(N-1 downto 0) + ); +end arith_cca; + + +library IEEE; +use IEEE.numeric_std.all; + +architecture rtl of arith_cca is + + type tLevel is record + base : natural; + core : integer; + done : natural; + end record tLevel; + type tLevels is array(natural range<>) of tLevel; + + function compact return tLevels is + variable res : tLevels(0 to 31); + variable base, core, done : integer; + begin + base := 0; + core := (N-L)/2; + done := N-2*core; + for i in res'range loop + res(i) := (base, core, done); + if core <= 0 then + for j in 0 to i loop + report integer'image(j)&": ("&integer'image(res(j).base)&", "&integer'image(res(j).core)&", "&integer'image(res(j).done)&")" severity note; + end loop; -- j + return res(0 to i); + end if; + base := base + 2*core; + done := done + (core-2*(core/2)+L); + core := core/2 - L; + if i+1 = X and core > 0 then + done := done + 2*core; + core := 0; + end if; + end loop; + end function compact; + constant LEVELS : tLevels := compact; + constant CCA : boolean := LEVELS'length > 1; + +begin + genRCA: if not CCA generate + assert false + report "Using standard RCA for small "&integer'image(N)&"-bit adder." + severity note; + s <= std_logic_vector(unsigned(a)+unsigned(b)+(0 to 0 => c)); + end generate; + + genCCA: if CCA generate + constant WI : positive := LEVELS(LEVELS'high).base; + constant WC : positive := LEVELS(LEVELS'high).done + LEVELS'high*L + 2*LEVELS(LEVELS'high).core; + + signal ai, bi, si : std_logic_vector(WI-1 downto 0); + signal ac, bc, sc : unsigned(WC-1 downto 0); + begin + + -- Feed operands into compaction tree except for a prefix of L bits + -- to hide expansion delay of lower-order bits + blkFeed: block is + constant DONE : natural := LEVELS(0).done; + begin + -- alias most-significant prefix of ports and compacted operation + genPre: if DONE > 0 generate + ac(WC-1 downto WC-DONE) <= unsigned(a(N-1 downto N-DONE)); + bc(WC-1 downto WC-DONE) <= unsigned(b(N-1 downto N-DONE)); + s(N-1 downto N-DONE) <= std_logic_vector(sc(WC-1 downto WC-DONE)); + end generate genPre; + + -- copy compaction region + ai(N-DONE-1 downto 0) <= a(N-DONE-1 downto 0); + bi(N-DONE-1 downto 0) <= b(N-DONE-1 downto 0); + s(N-DONE-1 downto 0) <= si(N-DONE-1 downto 0); + end block blkFeed; + + -- Build the compaction tree + genCompact: for i in 1 to LEVELS'high generate + constant PAIRS : positive := LEVELS(i-1).core; + + constant BASE : natural := LEVELS(i).base; + constant CORE : integer := LEVELS(i).core; + constant DONE : natural := LEVELS(i).done; + + component LUT6_2 is + generic( + INIT : bit_vector := X"0000000000000000" + ); + port( + O5 : out std_ulogic; + O6 : out std_ulogic; + I0 : in std_ulogic; + I1 : in std_ulogic; + I2 : in std_ulogic; + I3 : in std_ulogic; + I4 : in std_ulogic; + I5 : in std_ulogic + ); + end component LUT6_2; + + begin + genPairs: for j in 0 to PAIRS-1 generate + signal b1, b0, a1, a0 : std_logic; + signal ss : std_logic; + begin + -- Compaction ------ + + -- Simplify Names + b1 <= bi(BASE-2*(PAIRS-j)+1); + b0 <= bi(BASE-2*(PAIRS-j)+0); + a1 <= ai(BASE-2*(PAIRS-j)+1); + a0 <= ai(BASE-2*(PAIRS-j)+0); + + genLast: if CORE <= 0 or j < L or L+2*CORE <= j generate + signal aa, bb : std_logic; + begin + aa <= (b1 and a1) or (b1 and a0) or (a1 and a0); + bb <= (b1 and a1) or (b1 and b0) or (a1 and b0); + + genSuf: if CORE <= 0 or j < L generate + ac((i-1)*L+j) <= aa; + bc((i-1)*L+j) <= bb; + ss <= sc((i-1)*L+j); + end generate genSuf; + genPre: if CORE > 0 and L+2*CORE <= j generate + ac(j-L-2*CORE+(WC-DONE)) <= aa; + bc(j-L-2*CORE+(WC-DONE)) <= bb; + ss <= sc(j-L-2*CORE+(WC-DONE)); + end generate genPre; + end generate genLast; + + genCore: if CORE > 0 and L <= j and j < L+2*CORE generate + ss <= si(BASE-L+j); + + compact: LUT6_2 + generic map( + INIT => X"FCC0FCC0FAA0FAA0" + ) + port map( + O6 => bi(BASE-L+j), + O5 => ai(BASE-L+j), + I5 => '1', + I4 => '-', + I3 => b1, + I2 => a1, + I1 => b0, + I0 => a0 + ); + end generate genCore; + + -- Expansion ------ + expand: LUT6_2 + generic map( + INIT => X"E77E81189FF96006" + ) + port map( + O6 => si(BASE-2*(PAIRS-j)+1), + O5 => si(BASE-2*(PAIRS-j)+0), + I5 => '1', + I4 => ss, + I3 => b1, + I2 => a1, + I1 => b0, + I0 => a0 + ); + + end generate genPairs; + end generate genCompact; + sc <= ac + bc + (0 to 0 => c); + end generate genCCA; + +end rtl; diff --git a/src/arith/xilinx/arith_inc_ovcy_xilinx.vhdl b/src/arith/xilinx/arith_inc_ovcy_xilinx.vhdl index d54af7d3..f299993c 100644 --- a/src/arith/xilinx/arith_inc_ovcy_xilinx.vhdl +++ b/src/arith/xilinx/arith_inc_ovcy_xilinx.vhdl @@ -1,16 +1,15 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================================================================================================ +-- ============================================================================= -- Authors: Thomas B. Preusser -- --- Module: TODO +-- Entity: TODO -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- --- ============================================================================================================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universität Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -25,7 +24,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================================================================================================ +-- ============================================================================= library IEEE; use IEEE.std_logic_1164.all; @@ -46,7 +45,7 @@ entity arith_inc_ovcy_xilinx is end entity; -architecture rtl of inc_ovcy_xilinx is +architecture rtl of arith_inc_ovcy_xilinx is signal c : std_logic_vector(N downto 0); -- Carry Chain Links begin -- rtl diff --git a/src/arith/xilinx/arith_prefix_and_xilinx.vhdl b/src/arith/xilinx/arith_prefix_and_xilinx.vhdl index ab73b50e..d423b880 100644 --- a/src/arith/xilinx/arith_prefix_and_xilinx.vhdl +++ b/src/arith/xilinx/arith_prefix_and_xilinx.vhdl @@ -1,7 +1,6 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Thomas B. Preusser -- Patrick Lehmann @@ -9,7 +8,7 @@ -- Entity: Prefix AND computation -- -- Description: --- ------------------------------------ +-- ------------------------------------- -- Prefix AND computation: -- y(i) <= '1' when x(i downto 0) = (i downto 0 => '1') else '0' -- This implementation uses carry chains for wider implementations. diff --git a/src/arith/xilinx/arith_prefix_or_xilinx.vhdl b/src/arith/xilinx/arith_prefix_or_xilinx.vhdl index cbee72cd..8c172a12 100644 --- a/src/arith/xilinx/arith_prefix_or_xilinx.vhdl +++ b/src/arith/xilinx/arith_prefix_or_xilinx.vhdl @@ -1,7 +1,6 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Thomas B. Preusser -- Patrick Lehmann @@ -9,7 +8,7 @@ -- Entity: Prefix OR computation -- -- Description: --- ------------------------------------ +-- ------------------------------------- -- Prefix OR computation: -- y(i) <= '0' when x(i downto 0) = (i downto 0 => '0') else '1'; -- This implementation uses carry chains for wider implementations. diff --git a/src/bus/bus_Arbiter.vhdl b/src/bus/bus_Arbiter.vhdl index da86e2d7..a965b2fe 100644 --- a/src/bus/bus_Arbiter.vhdl +++ b/src/bus/bus_Arbiter.vhdl @@ -1,20 +1,20 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: Generic arbiter +-- Entity: Generic arbiter -- -- Description: --- ------------------------------------ --- This module implements a generic arbiter. It currently support the --- following arbitration strategies: --- - Round Robin (RR) +-- ------------------------------------- +-- This module implements a generic arbiter. It currently supports the +-- following arbitration strategies: +-- +-- * Round Robin (RR) -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -29,7 +29,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -41,47 +41,47 @@ use PoC.utils.all; entity bus_Arbiter is generic ( - STRATEGY : STRING := "RR"; -- RR, LOT - PORTS : POSITIVE := 1; + STRATEGY : string := "RR"; -- RR, LOT + PORTS : positive := 1; WEIGHTS : T_INTVEC := (0 => 1); - OUTPUT_REG : BOOLEAN := TRUE + OUTPUT_REG : boolean := TRUE ); port ( - Clock : in STD_LOGIC; - Reset : in STD_LOGIC; + Clock : in std_logic; + Reset : in std_logic; - Arbitrate : in STD_LOGIC; - Request_Vector : in STD_LOGIC_VECTOR(PORTS - 1 downto 0); + Arbitrate : in std_logic; + Request_Vector : in std_logic_vector(PORTS - 1 downto 0); - Arbitrated : out STD_LOGIC; - Grant_Vector : out STD_LOGIC_VECTOR(PORTS - 1 downto 0); - Grant_Index : out STD_LOGIC_VECTOR(log2ceilnz(PORTS) - 1 downto 0) + Arbitrated : out std_logic; + Grant_Vector : out std_logic_vector(PORTS - 1 downto 0); + Grant_Index : out std_logic_vector(log2ceilnz(PORTS) - 1 downto 0) ); -end; +end entity; architecture rtl of bus_Arbiter is - attribute KEEP : BOOLEAN; - attribute FSM_ENCODING : STRING; + attribute KEEP : boolean; + attribute FSM_ENCODING : string; begin -- Assert STRATEGY for known strings -- ========================================================================================================================================================== - assert ((STRATEGY = "RR") OR (STRATEGY = "LOT")) + assert ((STRATEGY = "RR") or (STRATEGY = "LOT")) report "Unknown arbiter strategy." severity FAILURE; -- Round Robin Arbiter -- ========================================================================================================================================================== - genRR : if (STRATEGY = "RR") generate - signal RequestLeft : UNSIGNED(PORTS - 1 downto 0); - signal SelectLeft : UNSIGNED(PORTS - 1 downto 0); - signal SelectRight : UNSIGNED(PORTS - 1 downto 0); + genRR : if STRATEGY = "RR" generate + signal RequestLeft : unsigned(PORTS - 1 downto 0); + signal SelectLeft : unsigned(PORTS - 1 downto 0); + signal SelectRight : unsigned(PORTS - 1 downto 0); - signal ChannelPointer_en : STD_LOGIC; - signal ChannelPointer : STD_LOGIC_VECTOR(PORTS - 1 downto 0); - signal ChannelPointer_d : STD_LOGIC_VECTOR(PORTS - 1 downto 0) := to_slv(1, PORTS); - signal ChannelPointer_nxt : STD_LOGIC_VECTOR(PORTS - 1 downto 0); + signal ChannelPointer_en : std_logic; + signal ChannelPointer : std_logic_vector(PORTS - 1 downto 0); + signal ChannelPointer_d : std_logic_vector(PORTS - 1 downto 0) := to_slv(1, PORTS); + signal ChannelPointer_nxt : std_logic_vector(PORTS - 1 downto 0); begin @@ -93,7 +93,7 @@ begin ChannelPointer_nxt <= std_logic_vector(ite((RequestLeft = (RequestLeft'range => '0')), SelectRight, SelectLeft)); -- generate ChannelPointer register and unregistered outputs - genREG0 : if (OUTPUT_REG = FALSE) generate + genREG0 : if not OUTPUT_REG generate process(Clock) begin if rising_edge(Clock) then @@ -111,15 +111,15 @@ begin end generate; -- generate ChannelPointer register and registered outputs - genREG1 : if (OUTPUT_REG = TRUE) generate - signal ChannelPointer_bin_d : STD_LOGIC_VECTOR(log2ceilnz(PORTS) - 1 downto 0) := to_slv(0, log2ceilnz(PORTS) - 1); + genREG1 : if OUTPUT_REG generate + signal ChannelPointer_bin_d : std_logic_vector(log2ceilnz(PORTS) - 1 downto 0) := (others => '0'); begin process(Clock) begin if rising_edge(Clock) then if (Reset = '1') then ChannelPointer_d <= to_slv(1, PORTS); - ChannelPointer_bin_d <= to_slv(0, log2ceilnz(PORTS) - 1); + ChannelPointer_bin_d <= (others => '0'); elsif (ChannelPointer_en = '1') then ChannelPointer_d <= ChannelPointer_nxt; ChannelPointer_bin_d <= std_logic_vector(onehot2bin(ChannelPointer_nxt)); diff --git a/src/bus/stream/stream.pkg.vhdl b/src/bus/stream/stream.pkg.vhdl index 30ce08e8..dbe7a86a 100644 --- a/src/bus/stream/stream.pkg.vhdl +++ b/src/bus/stream/stream.pkg.vhdl @@ -1,19 +1,18 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- -- Package: VHDL package for component declarations, types and functions -- associated to the PoC.bus.stream namespace -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -28,7 +27,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -43,65 +42,65 @@ use PoC.strings.all; package stream is -- single dataword for TestRAM type T_SIM_STREAM_WORD_8 is record - Valid : STD_LOGIC; + Valid : std_logic; Data : T_SLV_8; - SOF : STD_LOGIC; - EOF : STD_LOGIC; - Ready : STD_LOGIC; - EOFG : BOOLEAN; + SOF : std_logic; + EOF : std_logic; + Ready : std_logic; + EOFG : boolean; end record; type T_SIM_STREAM_WORD_32 is record - Valid : STD_LOGIC; + Valid : std_logic; Data : T_SLV_32; - SOF : STD_LOGIC; - EOF : STD_LOGIC; - Ready : STD_LOGIC; - EOFG : BOOLEAN; + SOF : std_logic; + EOF : std_logic; + Ready : std_logic; + EOFG : boolean; end record; -- define array indices - constant C_SIM_STREAM_MAX_PATTERN_COUNT : POSITIVE := 128;-- * 1024; -- max data size per testcase - constant C_SIM_STREAM_MAX_FRAMEGROUP_COUNT : POSITIVE := 8; + constant C_SIM_STREAM_MAX_PATTERN_COUNT : positive := 128;-- * 1024; -- max data size per testcase + constant C_SIM_STREAM_MAX_FRAMEGROUP_COUNT : positive := 8; - constant C_SIM_STREAM_WORD_INDEX_BW : POSITIVE := log2ceilnz(C_SIM_STREAM_MAX_PATTERN_COUNT); - constant C_SIM_STREAM_FRAMEGROUP_INDEX_BW : POSITIVE := log2ceilnz(C_SIM_STREAM_MAX_FRAMEGROUP_COUNT); + constant C_SIM_STREAM_WORD_INDEX_BW : positive := log2ceilnz(C_SIM_STREAM_MAX_PATTERN_COUNT); + constant C_SIM_STREAM_FRAMEGROUP_INDEX_BW : positive := log2ceilnz(C_SIM_STREAM_MAX_FRAMEGROUP_COUNT); - subtype T_SIM_STREAM_WORD_INDEX is INTEGER range 0 to C_SIM_STREAM_MAX_PATTERN_COUNT - 1; - subtype T_SIM_STREAM_FRAMEGROUP_INDEX is INTEGER range 0 to C_SIM_STREAM_MAX_FRAMEGROUP_COUNT - 1; + subtype T_SIM_STREAM_WORD_INDEX is integer range 0 to C_SIM_STREAM_MAX_PATTERN_COUNT - 1; + subtype T_SIM_STREAM_FRAMEGROUP_INDEX is integer range 0 to C_SIM_STREAM_MAX_FRAMEGROUP_COUNT - 1; subtype T_SIM_DELAY is T_UINT_16; - type T_SIM_DELAY_VECTOR is array (NATURAL range <>) of T_SIM_DELAY; + type T_SIM_DELAY_VECTOR is array (natural range <>) of T_SIM_DELAY; -- define array of datawords - type T_SIM_STREAM_WORD_VECTOR_8 is array (NATURAL range <>) of T_SIM_STREAM_WORD_8; - type T_SIM_STREAM_WORD_VECTOR_32 is array (NATURAL range <>) of T_SIM_STREAM_WORD_32; + type T_SIM_STREAM_WORD_VECTOR_8 is array (natural range <>) of T_SIM_STREAM_WORD_8; + type T_SIM_STREAM_WORD_VECTOR_32 is array (natural range <>) of T_SIM_STREAM_WORD_32; -- define link layer directions type T_SIM_STREAM_DIRECTION is (Send, RECEIVE); -- define framegroup information type T_SIM_STREAM_FRAMEGROUP_8 is record - Active : BOOLEAN; - Name : STRING(1 to 64); - PrePause : NATURAL; - PostPause : NATURAL; + Active : boolean; + Name : string(1 to 64); + PrePause : natural; + PostPause : natural; DataCount : T_SIM_STREAM_WORD_INDEX; Data : T_SIM_STREAM_WORD_VECTOR_8(0 to C_SIM_STREAM_MAX_PATTERN_COUNT - 1); end record; type T_SIM_STREAM_FRAMEGROUP_32 is record - Active : BOOLEAN; - Name : STRING(1 to 64); - PrePause : NATURAL; - PostPause : NATURAL; + Active : boolean; + Name : string(1 to 64); + PrePause : natural; + PostPause : natural; DataCount : T_SIM_STREAM_WORD_INDEX; Data : T_SIM_STREAM_WORD_VECTOR_32(T_SIM_STREAM_WORD_INDEX); end record; -- define array of framegroups - type T_SIM_STREAM_FRAMEGROUP_VECTOR_8 is array (NATURAL range <>) of T_SIM_STREAM_FRAMEGROUP_8; - type T_SIM_STREAM_FRAMEGROUP_VECTOR_32 is array (NATURAL range <>) of T_SIM_STREAM_FRAMEGROUP_32; + type T_SIM_STREAM_FRAMEGROUP_VECTOR_8 is array (natural range <>) of T_SIM_STREAM_FRAMEGROUP_8; + type T_SIM_STREAM_FRAMEGROUP_VECTOR_32 is array (natural range <>) of T_SIM_STREAM_FRAMEGROUP_32; -- define constants (stored in RAMB36's parity-bits) constant C_SIM_STREAM_WORD_8_EMPTY : T_SIM_STREAM_WORD_8 := (Valid => '0', Data => (others => 'U'), SOF => '0', EOF => '0', Ready => '0', EOFG => FALSE); @@ -130,8 +129,8 @@ package stream is Data => (others => C_SIM_STREAM_WORD_32_EMPTY) ); - function CountPatterns(Data : T_SIM_STREAM_WORD_VECTOR_8) return NATURAL; - function CountPatterns(Data : T_SIM_STREAM_WORD_VECTOR_32) return NATURAL; + function CountPatterns(Data : T_SIM_STREAM_WORD_VECTOR_8) return natural; + function CountPatterns(Data : T_SIM_STREAM_WORD_VECTOR_32) return natural; function dat(slv : T_SLV_8) return T_SIM_STREAM_WORD_8; function dat(slvv : T_SLVV_8) return T_SIM_STREAM_WORD_VECTOR_8; @@ -152,18 +151,18 @@ package stream is function eofg(stmwv : T_SIM_STREAM_WORD_VECTOR_8) return T_SIM_STREAM_WORD_VECTOR_8; function eofg(stmw : T_SIM_STREAM_WORD_32) return T_SIM_STREAM_WORD_32; - function to_string(stmw : T_SIM_STREAM_WORD_8) return STRING; - function to_string(stmw : T_SIM_STREAM_WORD_32) return STRING; + function to_string(stmw : T_SIM_STREAM_WORD_8) return string; + function to_string(stmw : T_SIM_STREAM_WORD_32) return string; -- checksum functions -- ================================================================ - function sim_CRC8(words : T_SIM_STREAM_WORD_VECTOR_8) return STD_LOGIC_VECTOR; + function sim_CRC8(words : T_SIM_STREAM_WORD_VECTOR_8) return std_logic_vector; -- function sim_CRC16(words : T_SIM_STREAM_WORD_VECTOR_8) return STD_LOGIC_VECTOR; end; package body stream is -function CountPatterns(Data : T_SIM_STREAM_WORD_VECTOR_8) return NATURAL is +function CountPatterns(Data : T_SIM_STREAM_WORD_VECTOR_8) return natural is begin for i in 0 to Data'length - 1 loop if (Data(i).EOFG = TRUE) then @@ -174,7 +173,7 @@ function CountPatterns(Data : T_SIM_STREAM_WORD_VECTOR_8) return NATURAL is return 0; end; - function CountPatterns(Data : T_SIM_STREAM_WORD_VECTOR_32) return NATURAL is + function CountPatterns(Data : T_SIM_STREAM_WORD_VECTOR_32) return natural is begin for i in 0 to Data'length - 1 loop if (Data(i).EOFG = TRUE) then @@ -359,8 +358,8 @@ function CountPatterns(Data : T_SIM_STREAM_WORD_VECTOR_8) return NATURAL is return result; end; - function to_flag1_string(stmw : T_SIM_STREAM_WORD_8) return STRING is - variable flag : STD_LOGIC_VECTOR(2 downto 0) := to_sl(stmw.EOFG) & stmw.EOF & stmw.SOF; + function to_flag1_string(stmw : T_SIM_STREAM_WORD_8) return string is + variable flag : std_logic_vector(2 downto 0) := to_sl(stmw.EOFG) & stmw.EOF & stmw.SOF; begin case flag is when "000" => return ""; @@ -375,8 +374,8 @@ function CountPatterns(Data : T_SIM_STREAM_WORD_VECTOR_8) return NATURAL is end case; end function; - function to_flag1_string(stmw : T_SIM_STREAM_WORD_32) return STRING is - variable flag : STD_LOGIC_VECTOR(2 downto 0) := to_sl(stmw.EOFG) & stmw.EOF & stmw.SOF; + function to_flag1_string(stmw : T_SIM_STREAM_WORD_32) return string is + variable flag : std_logic_vector(2 downto 0) := to_sl(stmw.EOFG) & stmw.EOF & stmw.SOF; begin case flag is when "000" => return ""; @@ -391,8 +390,8 @@ function CountPatterns(Data : T_SIM_STREAM_WORD_VECTOR_8) return NATURAL is end case; end function; - function to_flag2_string(stmw : T_SIM_STREAM_WORD_8) return STRING is - variable flag : STD_LOGIC_VECTOR(1 downto 0) := stmw.Ready & stmw.Valid; + function to_flag2_string(stmw : T_SIM_STREAM_WORD_8) return string is + variable flag : std_logic_vector(1 downto 0) := stmw.Ready & stmw.Valid; begin case flag is when "00" => return " "; @@ -405,8 +404,8 @@ function CountPatterns(Data : T_SIM_STREAM_WORD_VECTOR_8) return NATURAL is end case; end function; - function to_flag2_string(stmw : T_SIM_STREAM_WORD_32) return STRING is - variable flag : STD_LOGIC_VECTOR(1 downto 0) := stmw.Ready & stmw.Valid; + function to_flag2_string(stmw : T_SIM_STREAM_WORD_32) return string is + variable flag : std_logic_vector(1 downto 0) := stmw.Ready & stmw.Valid; begin case flag is when "00" => return " "; @@ -419,12 +418,12 @@ function CountPatterns(Data : T_SIM_STREAM_WORD_VECTOR_8) return NATURAL is end case; end function; - function to_string(stmw : T_SIM_STREAM_WORD_8) return STRING is + function to_string(stmw : T_SIM_STREAM_WORD_8) return string is begin return to_flag2_string(stmw) & " 0x" & to_string(stmw.Data, 'h') & " " & to_flag1_string(stmw); end function; - function to_string(stmw : T_SIM_STREAM_WORD_32) return STRING is + function to_string(stmw : T_SIM_STREAM_WORD_32) return string is begin return to_flag2_string(stmw) & " 0x" & to_string(stmw.Data, 'h') & " " & to_flag1_string(stmw); end function; @@ -437,14 +436,14 @@ function CountPatterns(Data : T_SIM_STREAM_WORD_VECTOR_8) return NATURAL is -- return to_stdlogicvector(to_bitvector(slv)); -- end; - function sim_CRC8(words : T_SIM_STREAM_WORD_VECTOR_8) return STD_LOGIC_VECTOR is + function sim_CRC8(words : T_SIM_STREAM_WORD_VECTOR_8) return std_logic_vector is constant CRC8_INIT : T_SLV_8 := x"FF"; constant CRC8_POLYNOMIAL : T_SLV_8 := x"31"; -- 0x131 variable CRC8_Value : T_SLV_8 := CRC8_INIT; -- variable Pattern : T_DATAFifO_PATTERN; - variable Word : UNSIGNED(T_SLV_8'range); + variable Word : unsigned(T_SLV_8'range); begin report "Computing CRC8 for Words " & to_string(words'low) & " to " & to_string(words'high) severity NOTE; @@ -452,7 +451,7 @@ function CountPatterns(Data : T_SIM_STREAM_WORD_VECTOR_8) return NATURAL is if (words(i).Valid = '1') then Word := to_01(unsigned(words(i).Data)); --- ASSERT (J > 9) report str_merge(" Word: 0x", hstr(Word), " CRC16_Value: 0x", hstr(CRC16_Value)) severity NOTE; +-- assert (J > 9) report str_merge(" Word: 0x", hstr(Word), " CRC16_Value: 0x", hstr(CRC16_Value)) severity NOTE; for j in Word'range loop CRC8_Value := (CRC8_Value(CRC8_Value'high - 1 downto 0) & '0') xor (CRC8_POLYNOMIAL and (CRC8_POLYNOMIAL'range => (Word(j) xor CRC8_Value(CRC8_Value'high)))); @@ -483,15 +482,15 @@ function CountPatterns(Data : T_SIM_STREAM_WORD_VECTOR_8) return NATURAL is -- ---- report Frames(i).Name severity NOTE; -- --- FOR J IN 1 to Frames(i).Count - 1 loop +-- for j in 1 to Frames(i).Count - 1 loop -- Pattern := Frames(i).DataFifOPatterns(J); -- -- if (Pattern.Valid = '1') then -- Word := to_01(Pattern.Data); -- ----- ASSERT (J > 9) report str_merge(" Word: 0x", hstr(Word), " CRC16_Value: 0x", hstr(CRC16_Value)) severity NOTE; +---- assert (J > 9) report str_merge(" Word: 0x", hstr(Word), " CRC16_Value: 0x", hstr(CRC16_Value)) severity NOTE; -- --- FOR K IN Word'range loop +-- for k in Word'range loop -- CRC16_Value := (CRC16_Value(CRC16_Value'high - 1 downto 0) & '0') XOR (CRC16_POLYNOMIAL AND (CRC16_POLYNOMIAL'range => (Word(K) XOR CRC16_Value(CRC16_Value'high)))); -- end loop; -- end if; diff --git a/src/bus/stream/stream_Buffer.vhdl b/src/bus/stream/stream_Buffer.vhdl index 7dd6dd97..e854a1c9 100644 --- a/src/bus/stream/stream_Buffer.vhdl +++ b/src/bus/stream/stream_Buffer.vhdl @@ -1,20 +1,20 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: A generic buffer module for the PoC.Stream protocol. +-- Entity: A generic buffer module for the PoC.Stream protocol. -- -- Description: --- ------------------------------------ --- This module implements a generic buffer (FIFO) for the PoC.Stream protocol. --- It is generic in DATA_BITS and in META_BITS as well as in FIFO depths for --- data and meta information. +-- ------------------------------------- +-- This module implements a generic buffer (FIFO) for the +-- :doc:`PoC.Stream ` protocol. It is generic in +-- ``DATA_BITS`` and in ``META_BITS`` as well as in FIFO depths for data and +-- meta information. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -29,7 +29,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -43,41 +43,41 @@ use PoC.vectors.all; entity stream_Buffer is generic ( - FRAMES : POSITIVE := 2; - DATA_BITS : POSITIVE := 8; - DATA_FIFO_DEPTH : POSITIVE := 8; - META_BITS : T_POSVEC := (0 => 8); - META_FIFO_DEPTH : T_POSVEC := (0 => 16) + FRAMES : positive := 2; + DATA_BITS : positive := 8; + DATA_FIFO_DEPTH : positive := 8; + META_BITS : T_POSVEC := (0 => 8); + META_FIFO_DEPTH : T_POSVEC := (0 => 16) ); port ( - Clock : in STD_LOGIC; - Reset : in STD_LOGIC; + Clock : in std_logic; + Reset : in std_logic; -- IN Port - In_Valid : in STD_LOGIC; - In_Data : in STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0); - In_SOF : in STD_LOGIC; - In_EOF : in STD_LOGIC; - In_Ack : out STD_LOGIC; - In_Meta_rst : out STD_LOGIC; - In_Meta_nxt : out STD_LOGIC_VECTOR(META_BITS'length - 1 downto 0); - In_Meta_Data : in STD_LOGIC_VECTOR(isum(META_BITS) - 1 downto 0); + In_Valid : in std_logic; + In_Data : in std_logic_vector(DATA_BITS - 1 downto 0); + In_SOF : in std_logic; + In_EOF : in std_logic; + In_Ack : out std_logic; + In_Meta_rst : out std_logic; + In_Meta_nxt : out std_logic_vector(META_BITS'length - 1 downto 0); + In_Meta_Data : in std_logic_vector(isum(META_BITS) - 1 downto 0); -- OUT Port - Out_Valid : out STD_LOGIC; - Out_Data : out STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0); - Out_SOF : out STD_LOGIC; - Out_EOF : out STD_LOGIC; - Out_Ack : in STD_LOGIC; - Out_Meta_rst : in STD_LOGIC; - Out_Meta_nxt : in STD_LOGIC_VECTOR(META_BITS'length - 1 downto 0); - Out_Meta_Data : out STD_LOGIC_VECTOR(isum(META_BITS) - 1 downto 0) + Out_Valid : out std_logic; + Out_Data : out std_logic_vector(DATA_BITS - 1 downto 0); + Out_SOF : out std_logic; + Out_EOF : out std_logic; + Out_Ack : in std_logic; + Out_Meta_rst : in std_logic; + Out_Meta_nxt : in std_logic_vector(META_BITS'length - 1 downto 0); + Out_Meta_Data : out std_logic_vector(isum(META_BITS) - 1 downto 0) ); end entity; architecture rtl of stream_Buffer is - attribute FSM_ENCODING : STRING; + attribute FSM_ENCODING : string; - constant META_STREAMS : POSITIVE := META_BITS'length; + constant META_STREAMS : positive := META_BITS'length; type T_WRITER_STATE is (ST_IDLE, ST_FRAME); type T_READER_STATE is (ST_IDLE, ST_FRAME); @@ -87,18 +87,18 @@ architecture rtl of stream_Buffer is signal Reader_State : T_READER_STATE := ST_IDLE; signal Reader_NextState : T_READER_STATE; - constant EOF_BIT : NATURAL := DATA_BITS; + constant EOF_BIT : natural := DATA_BITS; - signal DataFIFO_put : STD_LOGIC; - signal DataFIFO_DataIn : STD_LOGIC_VECTOR(DATA_BITS downto 0); - signal DataFIFO_Full : STD_LOGIC; + signal DataFIFO_put : std_logic; + signal DataFIFO_DataIn : std_logic_vector(DATA_BITS downto 0); + signal DataFIFO_Full : std_logic; - signal DataFIFO_got : STD_LOGIC; - signal DataFIFO_DataOut : STD_LOGIC_VECTOR(DataFIFO_DataIn'range); - signal DataFIFO_Valid : STD_LOGIC; + signal DataFIFO_got : std_logic; + signal DataFIFO_DataOut : std_logic_vector(DataFIFO_DataIn'range); + signal DataFIFO_Valid : std_logic; - signal FrameCommit : STD_LOGIC; - signal Meta_rst : STD_LOGIC_VECTOR(META_BITS'length - 1 downto 0); + signal FrameCommit : std_logic; + signal Meta_rst : std_logic_vector(META_BITS'length - 1 downto 0); begin assert (META_BITS'length = META_FIFO_DEPTH'length) report "META_BITS'length /= META_FIFO_DEPTH'length" severity FAILURE; @@ -130,19 +130,19 @@ begin case Writer_State is when ST_IDLE => - In_Ack <= NOT DataFIFO_Full; + In_Ack <= not DataFIFO_Full; DataFIFO_put <= In_Valid; - if ((In_Valid AND In_SOF AND NOT In_EOF) = '1') then + if ((In_Valid and In_SOF and not In_EOF) = '1') then Writer_NextState <= ST_FRAME; end if; when ST_FRAME => - In_Ack <= NOT DataFIFO_Full; + In_Ack <= not DataFIFO_Full; DataFIFO_put <= In_Valid; - if ((In_Valid AND In_EOF AND NOT DataFIFO_Full) = '1') then + if ((In_Valid and In_EOF and not DataFIFO_Full) = '1') then Writer_NextState <= ST_IDLE; end if; @@ -169,7 +169,7 @@ begin Out_SOF <= '1'; DataFIFO_got <= Out_Ack; - if ((DataFIFO_Valid AND NOT DataFIFO_DataOut(EOF_BIT) AND Out_Ack) = '1') then + if ((DataFIFO_Valid and not DataFIFO_DataOut(EOF_BIT) and Out_Ack) = '1') then Reader_NextState <= ST_FRAME; end if; @@ -177,7 +177,7 @@ begin Out_Valid <= DataFIFO_Valid; DataFIFO_got <= Out_Ack; - if ((DataFIFO_Valid AND DataFIFO_DataOut(EOF_BIT) AND Out_Ack) = '1') then + if ((DataFIFO_Valid and DataFIFO_DataOut(EOF_BIT) and Out_Ack) = '1') then Reader_NextState <= ST_IDLE; end if; @@ -212,16 +212,16 @@ begin fstate_rd => open ); - FrameCommit <= DataFIFO_Valid AND DataFIFO_DataOut(EOF_BIT) AND Out_Ack; + FrameCommit <= DataFIFO_Valid and DataFIFO_DataOut(EOF_BIT) and Out_Ack; In_Meta_rst <= slv_and(Meta_rst); genMeta : for i in 0 to META_BITS'length - 1 generate begin - genReg : if (META_FIFO_DEPTH(i) = 1) generate - signal MetaReg_DataIn : STD_LOGIC_VECTOR(META_BITS(i) - 1 downto 0); - signal MetaReg_d : STD_LOGIC_VECTOR(META_BITS(i) - 1 downto 0) := (others => '0'); - signal MetaReg_DataOut : STD_LOGIC_VECTOR(META_BITS(i) - 1 downto 0); + genReg : if META_FIFO_DEPTH(i) = 1 generate + signal MetaReg_DataIn : std_logic_vector(META_BITS(i) - 1 downto 0); + signal MetaReg_d : std_logic_vector(META_BITS(i) - 1 downto 0) := (others => '0'); + signal MetaReg_DataOut : std_logic_vector(META_BITS(i) - 1 downto 0); begin MetaReg_DataIn <= In_Meta_Data(high(META_BITS, i) downto low(META_BITS, i)); @@ -230,7 +230,7 @@ begin if rising_edge(Clock) then if (Reset = '1') then MetaReg_d <= (others => '0'); - elsif ((In_Valid AND In_SOF) = '1') then + elsif ((In_Valid and In_SOF) = '1') then MetaReg_d <= MetaReg_DataIn; end if; end if; @@ -239,36 +239,36 @@ begin MetaReg_DataOut <= MetaReg_d; Out_Meta_Data(high(META_BITS, i) downto low(META_BITS, i)) <= MetaReg_DataOut; end generate; -- META_FIFO_DEPTH(i) = 1 - genFIFO : if (META_FIFO_DEPTH(i) > 1) generate - signal MetaFIFO_put : STD_LOGIC; - signal MetaFIFO_DataIn : STD_LOGIC_VECTOR(META_BITS(i) - 1 downto 0); - signal MetaFIFO_Full : STD_LOGIC; + genFIFO : if META_FIFO_DEPTH(i) > 1 generate + signal MetaFIFO_put : std_logic; + signal MetaFIFO_DataIn : std_logic_vector(META_BITS(i) - 1 downto 0); + signal MetaFIFO_Full : std_logic; - signal MetaFIFO_Commit : STD_LOGIC; - signal MetaFIFO_Rollback : STD_LOGIC; + signal MetaFIFO_Commit : std_logic; + signal MetaFIFO_Rollback : std_logic; - signal MetaFIFO_got : STD_LOGIC; - signal MetaFIFO_DataOut : STD_LOGIC_VECTOR(MetaFIFO_DataIn'range); - signal MetaFIFO_Valid : STD_LOGIC; + signal MetaFIFO_got : std_logic; + signal MetaFIFO_DataOut : std_logic_vector(MetaFIFO_DataIn'range); + signal MetaFIFO_Valid : std_logic; - signal Writer_CounterControl : STD_LOGIC := '0'; - signal Writer_Counter_en : STD_LOGIC; - signal Writer_Counter_us : UNSIGNED(log2ceilnz(META_FIFO_DEPTH(i)) - 1 downto 0) := (others => '0'); + signal Writer_CounterControl : std_logic := '0'; + signal Writer_Counter_en : std_logic; + signal Writer_Counter_us : unsigned(log2ceilnz(META_FIFO_DEPTH(i)) - 1 downto 0) := (others => '0'); begin process(Clock) begin if rising_edge(Clock) then if (Reset = '1') then Writer_CounterControl <= '0'; - elsif ((In_Valid AND In_SOF) = '1') then + elsif ((In_Valid and In_SOF) = '1') then Writer_CounterControl <= '1'; - elsif (Writer_Counter_us = (META_FIFO_DEPTH(i) - 1)) then + elsif Writer_Counter_us = (META_FIFO_DEPTH(i) - 1) then Writer_CounterControl <= '0'; end if; end if; end process; - Writer_Counter_en <= (In_Valid AND In_SOF) OR Writer_CounterControl; + Writer_Counter_en <= (In_Valid and In_SOF) or Writer_CounterControl; process(Clock) begin @@ -281,7 +281,7 @@ begin end if; end process; - Meta_rst(i) <= NOT Writer_Counter_en; + Meta_rst(i) <= not Writer_Counter_en; In_Meta_nxt(i) <= Writer_Counter_en; MetaFIFO_put <= Writer_Counter_en; diff --git a/src/bus/stream/stream_DeMux.vhdl b/src/bus/stream/stream_DeMux.vhdl index 25c1c572..e9c904c3 100644 --- a/src/bus/stream/stream_DeMux.vhdl +++ b/src/bus/stream/stream_DeMux.vhdl @@ -1,20 +1,17 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: A generic buffer module for the PoC.Stream protocol. +-- Entity: A generic buffer module for the PoC.Stream protocol. -- -- Description: --- ------------------------------------ --- This module implements a generic buffer (FIFO) for the PoC.Stream protocol. --- It is generic in DATA_BITS and in META_BITS as well as in FIFO depths for --- data and meta information. +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -29,7 +26,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -43,60 +40,60 @@ use PoC.vectors.all; entity stream_DeMux is generic ( - PORTS : POSITIVE := 2; - DATA_BITS : POSITIVE := 8; - META_BITS : NATURAL := 8; - META_REV_BITS : NATURAL := 2 + PORTS : positive := 2; + DATA_BITS : positive := 8; + META_BITS : natural := 8; + META_REV_BITS : natural := 2 ); port ( - Clock : in STD_LOGIC; - Reset : in STD_LOGIC; + Clock : in std_logic; + Reset : in std_logic; -- Control interface - DeMuxControl : in STD_LOGIC_VECTOR(PORTS - 1 downto 0); + DeMuxControl : in std_logic_vector(PORTS - 1 downto 0); -- IN Port - In_Valid : in STD_LOGIC; - In_Data : in STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0); - In_Meta : in STD_LOGIC_VECTOR(META_BITS - 1 downto 0); - In_Meta_rev : out STD_LOGIC_VECTOR(META_REV_BITS - 1 downto 0); - In_SOF : in STD_LOGIC; - In_EOF : in STD_LOGIC; - In_Ack : out STD_LOGIC; + In_Valid : in std_logic; + In_Data : in std_logic_vector(DATA_BITS - 1 downto 0); + In_Meta : in std_logic_vector(META_BITS - 1 downto 0); + In_Meta_rev : out std_logic_vector(META_REV_BITS - 1 downto 0); + In_SOF : in std_logic; + In_EOF : in std_logic; + In_Ack : out std_logic; -- OUT Ports - Out_Valid : out STD_LOGIC_VECTOR(PORTS - 1 downto 0); - Out_Data : out T_SLM(PORTS - 1 downto 0, DATA_BITS - 1 downto 0); - Out_Meta : out T_SLM(PORTS - 1 downto 0, META_BITS - 1 downto 0); - Out_Meta_rev : in T_SLM(PORTS - 1 downto 0, META_REV_BITS - 1 downto 0); - Out_SOF : out STD_LOGIC_VECTOR(PORTS - 1 downto 0); - Out_EOF : out STD_LOGIC_VECTOR(PORTS - 1 downto 0); - Out_Ack : in STD_LOGIC_VECTOR(PORTS - 1 downto 0) + Out_Valid : out std_logic_vector(PORTS - 1 downto 0); + Out_Data : out T_SLM(PORTS - 1 downto 0, DATA_BITS - 1 downto 0); + Out_Meta : out T_SLM(PORTS - 1 downto 0, META_BITS - 1 downto 0); + Out_Meta_rev : in T_SLM(PORTS - 1 downto 0, META_REV_BITS - 1 downto 0); + Out_SOF : out std_logic_vector(PORTS - 1 downto 0); + Out_EOF : out std_logic_vector(PORTS - 1 downto 0); + Out_Ack : in std_logic_vector(PORTS - 1 downto 0) ); -end; +end entity; architecture rtl of stream_DeMux is - attribute KEEP : BOOLEAN; - attribute FSM_ENCODING : STRING; + attribute KEEP : boolean; + attribute FSM_ENCODING : string; - subtype T_CHANNEL_INDEX is NATURAL range 0 to PORTS - 1; + subtype T_CHANNEL_INDEX is natural range 0 to PORTS - 1; type T_STATE is (ST_IDLE, ST_DATAFLOW, ST_DISCARD_FRAME); signal State : T_STATE := ST_IDLE; signal NextState : T_STATE; - signal Is_SOF : STD_LOGIC; - signal Is_EOF : STD_LOGIC; + signal Is_SOF : std_logic; + signal Is_EOF : std_logic; - signal In_Ack_i : STD_LOGIC; - signal Out_Valid_i : STD_LOGIC; - signal DiscardFrame : STD_LOGIC; + signal In_Ack_i : std_logic; + signal Out_Valid_i : std_logic; + signal DiscardFrame : std_logic; - signal ChannelPointer_rst : STD_LOGIC; - signal ChannelPointer_en : STD_LOGIC; - signal ChannelPointer : STD_LOGIC_VECTOR(PORTS - 1 downto 0); - signal ChannelPointer_d : STD_LOGIC_VECTOR(PORTS - 1 downto 0) := (others => '0'); + signal ChannelPointer_rst : std_logic; + signal ChannelPointer_en : std_logic; + signal ChannelPointer : std_logic_vector(PORTS - 1 downto 0); + signal ChannelPointer_d : std_logic_vector(PORTS - 1 downto 0) := (others => '0'); - signal ChannelPointer_bin : UNSIGNED(log2ceilnz(PORTS) - 1 downto 0); + signal ChannelPointer_bin : unsigned(log2ceilnz(PORTS) - 1 downto 0); signal idx : T_CHANNEL_INDEX; signal Out_Data_i : T_SLM(PORTS - 1 downto 0, DATA_BITS - 1 downto 0) := (others => (others => 'Z')); -- necessary default assignment 'Z' to get correct simulation results (iSIM, vSIM, ghdl/gtkwave) diff --git a/src/bus/stream/stream_FrameGenerator.vhdl b/src/bus/stream/stream_FrameGenerator.vhdl index b11bd742..76a8e802 100644 --- a/src/bus/stream/stream_FrameGenerator.vhdl +++ b/src/bus/stream/stream_FrameGenerator.vhdl @@ -1,20 +1,17 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: A generic buffer module for the PoC.Stream protocol. +-- Entity: A generic buffer module for the PoC.Stream protocol. -- -- Description: --- ------------------------------------ --- This module implements a generic buffer (FIFO) for the PoC.Stream protocol. --- It is generic in DATA_BITS and in META_BITS as well as in FIFO depths for --- data and meta information. +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -29,7 +26,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -42,32 +39,29 @@ use PoC.vectors.all; entity stream_FrameGenerator is generic ( - DATA_BITS : POSITIVE := 8; - WORD_BITS : POSITIVE := 16; - APPEND : T_FRAMEGEN_APPEND := FRAMEGEN_APP_NONE; - FRAMEGROUPS : T_FRAMEGEN_FRAMEGROUP_VECTOR_8 := (0 => C_FRAMEGEN_FRAMEGROUP_EMPTY) + DATA_BITS : positive := 8; + WORD_BITS : positive := 16; + APPEND : T_FRAMEGEN_APPEND := FRAMEGEN_APP_NONE; + FRAMEGROUPS : T_FRAMEGEN_FRAMEGROUP_VECTOR_8 := (0 => C_FRAMEGEN_FRAMEGROUP_EMPTY) ); port ( - Clock : in STD_LOGIC; - Reset : in STD_LOGIC; - + Clock : in std_logic; + Reset : in std_logic; -- CSE interface - Command : in T_FRAMEGEN_COMMAND; - Status : out T_FRAMEGEN_STATUS; - + Command : in T_FRAMEGEN_COMMAND; + Status : out T_FRAMEGEN_STATUS; -- Control interface - Pause : in T_SLV_16; - FrameGroupIndex : in T_SLV_8; - FrameIndex : in T_SLV_8; - Sequences : in T_SLV_16; - FrameLength : in T_SLV_16; - + Pause : in T_SLV_16; + FrameGroupIndex : in T_SLV_8; + FrameIndex : in T_SLV_8; + Sequences : in T_SLV_16; + FrameLength : in T_SLV_16; -- OUT Port - Out_Valid : out STD_LOGIC; - Out_Data : out STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0); - Out_SOF : out STD_LOGIC; - Out_EOF : out STD_LOGIC; - Out_Ack : in STD_LOGIC + Out_Valid : out std_logic; + Out_Data : out std_logic_vector(DATA_BITS - 1 downto 0); + Out_SOF : out std_logic; + Out_EOF : out std_logic; + Out_Ack : in std_logic ); end entity; @@ -83,20 +77,20 @@ architecture rtl of stream_FrameGenerator is signal State : T_STATE := ST_IDLE; signal NextState : T_STATE; - signal FrameLengthCounter_rst : STD_LOGIC; - signal FrameLengthCounter_en : STD_LOGIC; - signal FrameLengthCounter_us : UNSIGNED(15 downto 0) := (others => '0'); + signal FrameLengthCounter_rst : std_logic; + signal FrameLengthCounter_en : std_logic; + signal FrameLengthCounter_us : unsigned(15 downto 0) := (others => '0'); - signal SequencesCounter_rst : STD_LOGIC; - signal SequencesCounter_en : STD_LOGIC; - signal SequencesCounter_us : UNSIGNED(15 downto 0) := (others => '0'); - signal ContentCounter_rst : STD_LOGIC; - signal ContentCounter_en : STD_LOGIC; - signal ContentCounter_us : UNSIGNED(WORD_BITS - 1 downto 0) := (others => '0'); + signal SequencesCounter_rst : std_logic; + signal SequencesCounter_en : std_logic; + signal SequencesCounter_us : unsigned(15 downto 0) := (others => '0'); + signal ContentCounter_rst : std_logic; + signal ContentCounter_en : std_logic; + signal ContentCounter_us : unsigned(WORD_BITS - 1 downto 0) := (others => '0'); - signal PRNG_rst : STD_LOGIC; - signal PRNG_got : STD_LOGIC; - signal PRNG_Data : STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0); + signal PRNG_rst : std_logic; + signal PRNG_got : std_logic; + signal PRNG_Data : std_logic_vector(DATA_BITS - 1 downto 0); begin process(Clock) @@ -146,7 +140,7 @@ begin case Command is when FRAMEGEN_CMD_NONE => - NULL; + null; when FRAMEGEN_CMD_SEQUENCE => NextState <= ST_SEQUENCE_SOF; @@ -189,7 +183,7 @@ begin FrameLengthCounter_en <= '1'; ContentCounter_en <= '1'; - if (FrameLengthCounter_us = (unsigned(FrameLength) - 2)) then + if FrameLengthCounter_us = (unsigned(FrameLength) - 2) then NextState <= ST_SEQUENCE_EOF; end if; end if; @@ -205,7 +199,7 @@ begin SequencesCounter_en <= '1'; -- if (Pause = (Pause'range => '0')) then - if (SequencesCounter_us = (unsigned(Sequences) - 1)) then + if SequencesCounter_us = (unsigned(Sequences) - 1) then Status <= FRAMEGEN_STATUS_COMPLETE; NextState <= ST_IDLE; else @@ -235,7 +229,7 @@ begin FrameLengthCounter_en <= '1'; PRNG_got <= '1'; - if (FrameLengthCounter_us = (unsigned(FrameLength) - 2)) then + if FrameLengthCounter_us = (unsigned(FrameLength) - 2) then NextState <= ST_RANDOM_EOF; end if; end if; diff --git a/src/bus/stream/stream_Mirror.vhdl b/src/bus/stream/stream_Mirror.vhdl index 0334dadf..c0190fb7 100644 --- a/src/bus/stream/stream_Mirror.vhdl +++ b/src/bus/stream/stream_Mirror.vhdl @@ -1,20 +1,17 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: A generic buffer module for the PoC.Stream protocol. +-- Entity: A generic buffer module for the PoC.Stream protocol. -- -- Description: --- ------------------------------------ --- This module implements a generic buffer (FIFO) for the PoC.Stream protocol. --- It is generic in DATA_BITS and in META_BITS as well as in FIFO depths for --- data and meta information. +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -29,7 +26,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -43,54 +40,54 @@ use PoC.vectors.all; entity stream_Mirror is generic ( - portS : POSITIVE := 2; - DATA_BITS : POSITIVE := 8; - META_BITS : T_POSVEC := (0 => 8); - META_LENGTH : T_POSVEC := (0 => 16) + PORTS : positive := 2; + DATA_BITS : positive := 8; + META_BITS : T_POSVEC := (0 => 8); + META_LENGTH : T_POSVEC := (0 => 16) ); port ( - Clock : in STD_LOGIC; - Reset : in STD_LOGIC; - - In_Valid : in STD_LOGIC; - In_Data : in STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0); - In_SOF : in STD_LOGIC; - In_EOF : in STD_LOGIC; - In_Ack : out STD_LOGIC; - In_Meta_rst : out STD_LOGIC; - In_Meta_nxt : out STD_LOGIC_VECTOR(META_BITS'length - 1 downto 0); - In_Meta_Data : in STD_LOGIC_VECTOR(isum(META_BITS) - 1 downto 0); - - Out_Valid : out STD_LOGIC_VECTOR(portS - 1 downto 0); - Out_Data : out T_SLM(portS - 1 downto 0, DATA_BITS - 1 downto 0); - Out_SOF : out STD_LOGIC_VECTOR(portS - 1 downto 0); - Out_EOF : out STD_LOGIC_VECTOR(portS - 1 downto 0); - Out_Ack : in STD_LOGIC_VECTOR(portS - 1 downto 0); - Out_Meta_rst : in STD_LOGIC_VECTOR(portS - 1 downto 0); - Out_Meta_nxt : in T_SLM(portS - 1 downto 0, META_BITS'length - 1 downto 0); - Out_Meta_Data : out T_SLM(portS - 1 downto 0, isum(META_BITS) - 1 downto 0) + Clock : in std_logic; + Reset : in std_logic; + -- IN Port + In_Valid : in std_logic; + In_Data : in std_logic_vector(DATA_BITS - 1 downto 0); + In_SOF : in std_logic; + In_EOF : in std_logic; + In_Ack : out std_logic; + In_Meta_rst : out std_logic; + In_Meta_nxt : out std_logic_vector(META_BITS'length - 1 downto 0); + In_Meta_Data : in std_logic_vector(isum(META_BITS) - 1 downto 0); + -- OUT Port + Out_Valid : out std_logic_vector(PORTS - 1 downto 0); + Out_Data : out T_SLM(PORTS - 1 downto 0, DATA_BITS - 1 downto 0); + Out_SOF : out std_logic_vector(PORTS - 1 downto 0); + Out_EOF : out std_logic_vector(PORTS - 1 downto 0); + Out_Ack : in std_logic_vector(PORTS - 1 downto 0); + Out_Meta_rst : in std_logic_vector(PORTS - 1 downto 0); + Out_Meta_nxt : in T_SLM(PORTS - 1 downto 0, META_BITS'length - 1 downto 0); + Out_Meta_Data : out T_SLM(PORTS - 1 downto 0, isum(META_BITS) - 1 downto 0) ); end entity; architecture rtl of stream_Mirror is - attribute KEEP : BOOLEAN; - attribute FSM_ENCODING : STRING; + attribute KEEP : boolean; + attribute FSM_ENCODING : string; - signal FIFOGlue_put : STD_LOGIC; - signal FIFOGlue_DataIn : STD_LOGIC_VECTOR(DATA_BITS + 1 downto 0); - signal FIFOGlue_Full : STD_LOGIC; - signal FIFOGlue_Valid : STD_LOGIC; - signal FIFOGlue_DataOut : STD_LOGIC_VECTOR(DATA_BITS + 1 downto 0); - signal FIFOGlue_got : STD_LOGIC; + signal FIFOGlue_put : std_logic; + signal FIFOGlue_DataIn : std_logic_vector(DATA_BITS + 1 downto 0); + signal FIFOGlue_Full : std_logic; + signal FIFOGlue_Valid : std_logic; + signal FIFOGlue_DataOut : std_logic_vector(DATA_BITS + 1 downto 0); + signal FIFOGlue_got : std_logic; - signal Ack_i : STD_LOGIC; - signal Mask_r : STD_LOGIC_VECTOR(portS - 1 downto 0) := (others => '1'); + signal Ack_i : std_logic; + signal Mask_r : std_logic_vector(PORTS - 1 downto 0) := (others => '1'); - signal MetaOut_rst : STD_LOGIC_VECTOR(portS - 1 downto 0); + signal MetaOut_rst : std_logic_vector(PORTS - 1 downto 0); - signal Out_Data_i : T_SLM(portS - 1 downto 0, DATA_BITS - 1 downto 0) := (others => (others => 'Z')); - signal Out_Meta_Data_i : T_SLM(portS - 1 downto 0, isum(META_BITS) - 1 downto 0) := (others => (others => 'Z')); + signal Out_Data_i : T_SLM(PORTS - 1 downto 0, DATA_BITS - 1 downto 0) := (others => (others => 'Z')); + signal Out_Meta_Data_i : T_SLM(PORTS - 1 downto 0, isum(META_BITS) - 1 downto 0) := (others => (others => 'Z')); begin -- Data path @@ -122,17 +119,17 @@ begin got => FIFOGlue_got -- Data Consumed ); - genPorts : for i in 0 to portS - 1 generate + genPorts : for i in 0 to PORTS - 1 generate assign_row(Out_Data_i, FIFOGlue_DataOut(DATA_BITS - 1 downto 0), i); end generate; Ack_i <= slv_and(Out_Ack) or slv_and(not Mask_r or Out_Ack); - FIFOGlue_got <= Ack_i ; + FIFOGlue_got <= Ack_i; - Out_Valid <= (portS - 1 downto 0 => FIFOGlue_Valid) and Mask_r; + Out_Valid <= (PORTS - 1 downto 0 => FIFOGlue_Valid) and Mask_r; Out_Data <= Out_Data_i; - Out_SOF <= (portS - 1 downto 0 => FIFOGlue_DataOut(DATA_BITS + 0)); - Out_EOF <= (portS - 1 downto 0 => FIFOGlue_DataOut(DATA_BITS + 1)); + Out_SOF <= (PORTS - 1 downto 0 => FIFOGlue_DataOut(DATA_BITS + 0)); + Out_EOF <= (PORTS - 1 downto 0 => FIFOGlue_DataOut(DATA_BITS + 1)); process(Clock) begin @@ -150,12 +147,12 @@ begin In_Meta_rst <= slv_and(MetaOut_rst); genMeta : for i in 0 to META_BITS'length - 1 generate - subtype T_METAMEMORY is STD_LOGIC_VECTOR(META_BITS(i) - 1 downto 0); - type T_METAMEMORY_VECTOR is array(NATURAL range <>) of T_METAMEMORY; + subtype T_METAMEMORY is std_logic_vector(META_BITS(i) - 1 downto 0); + type T_METAMEMORY_VECTOR is array(natural range <>) of T_METAMEMORY; begin - genReg : if (META_LENGTH(i) = 1) generate - signal MetaMemory_en : STD_LOGIC; + genReg : if META_LENGTH(i) = 1 generate + signal MetaMemory_en : std_logic; signal MetaMemory : T_METAMEMORY; begin MetaMemory_en <= In_Valid and In_SOF; @@ -169,19 +166,19 @@ begin end if; end process; - genReader : FOR J IN 0 to portS - 1 generate + genReader : for j in 0 to PORTS - 1 generate assign_row(Out_Meta_Data_i, MetaMemory, J, high(META_BITS, i), low(META_BITS, i)); end generate; end generate; - genMem : if (META_LENGTH(i) > 1) generate - signal MetaMemory_en : STD_LOGIC; + genMem : if META_LENGTH(i) > 1 generate + signal MetaMemory_en : std_logic; signal MetaMemory : T_METAMEMORY_VECTOR(META_LENGTH(i) - 1 downto 0); - signal Writer_CounterControl : STD_LOGIC := '0'; + signal Writer_CounterControl : std_logic := '0'; - signal Writer_en : STD_LOGIC; - signal Writer_rst : STD_LOGIC; - signal Writer_us : UNSIGNED(log2ceilnz(META_LENGTH(i)) - 1 downto 0) := (others => '0'); + signal Writer_en : std_logic; + signal Writer_rst : std_logic; + signal Writer_us : unsigned(log2ceilnz(META_LENGTH(i)) - 1 downto 0) := (others => '0'); begin -- MetaMemory Write Pointer Control process(Clock) @@ -192,7 +189,7 @@ begin else if ((In_Valid and In_SOF) = '1') then Writer_CounterControl <= '1'; - elsif (Writer_us = (META_LENGTH(i) - 1)) then + elsif Writer_us = (META_LENGTH(i) - 1) then Writer_CounterControl <= '0'; end if; end if; @@ -203,7 +200,7 @@ begin In_Meta_nxt(i) <= Writer_en; MetaMemory_en <= Writer_en; - MetaOut_rst(i) <= NOT Writer_en; + MetaOut_rst(i) <= not Writer_en; -- MetaMemory - Write Pointer process(Clock) @@ -227,12 +224,12 @@ begin end if; end process; - genReader : for j in 0 to portS - 1 generate + genReader : for j in 0 to PORTS - 1 generate signal Row : T_METAMEMORY; - signal Reader_en : STD_LOGIC; - signal Reader_rst : STD_LOGIC; - signal Reader_us : UNSIGNED(log2ceilnz(META_LENGTH(i)) - 1 downto 0) := (others => '0'); + signal Reader_en : std_logic; + signal Reader_rst : std_logic; + signal Reader_us : unsigned(log2ceilnz(META_LENGTH(i)) - 1 downto 0) := (others => '0'); begin Reader_rst <= Out_Meta_rst(j) or (In_Valid and In_SOF); Reader_en <= Out_Meta_nxt(j, i); diff --git a/src/bus/stream/stream_Mux.vhdl b/src/bus/stream/stream_Mux.vhdl index 59cb5cda..9fdbda4b 100644 --- a/src/bus/stream/stream_Mux.vhdl +++ b/src/bus/stream/stream_Mux.vhdl @@ -1,20 +1,17 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: A generic buffer module for the PoC.Stream protocol. +-- Entity: A generic buffer module for the PoC.Stream protocol. -- -- Description: --- ------------------------------------ --- This module implements a generic buffer (FIFO) for the PoC.Stream protocol. --- It is generic in DATA_BITS and in META_BITS as well as in FIFO depths for --- data and meta information. +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -29,7 +26,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -43,65 +40,65 @@ use PoC.vectors.all; entity stream_Mux is generic ( - PORTS : POSITIVE := 2; - DATA_BITS : POSITIVE := 8; - META_BITS : NATURAL := 8; - META_REV_BITS : NATURAL := 2--; --- WEIGHTS : T_INTVEC := (1, 1) + PORTS : positive := 2; + DATA_BITS : positive := 8; + META_BITS : natural := 8; + META_REV_BITS : natural := 2--; +-- WEIGHTS : T_INTVEC := (1, 1) ); port ( - Clock : in STD_LOGIC; - Reset : in STD_LOGIC; + Clock : in std_logic; + Reset : in std_logic; -- IN Ports - In_Valid : in STD_LOGIC_VECTOR(PORTS - 1 downto 0); - In_Data : in T_SLM(PORTS - 1 downto 0, DATA_BITS - 1 downto 0); - In_Meta : in T_SLM(PORTS - 1 downto 0, META_BITS - 1 downto 0); - In_Meta_rev : out T_SLM(PORTS - 1 downto 0, META_REV_BITS - 1 downto 0); - In_SOF : in STD_LOGIC_VECTOR(PORTS - 1 downto 0); - In_EOF : in STD_LOGIC_VECTOR(PORTS - 1 downto 0); - In_Ack : out STD_LOGIC_VECTOR(PORTS - 1 downto 0); + In_Valid : in std_logic_vector(PORTS - 1 downto 0); + In_Data : in T_SLM(PORTS - 1 downto 0, DATA_BITS - 1 downto 0); + In_Meta : in T_SLM(PORTS - 1 downto 0, META_BITS - 1 downto 0); + In_Meta_rev : out T_SLM(PORTS - 1 downto 0, META_REV_BITS - 1 downto 0); + In_SOF : in std_logic_vector(PORTS - 1 downto 0); + In_EOF : in std_logic_vector(PORTS - 1 downto 0); + In_Ack : out std_logic_vector(PORTS - 1 downto 0); -- OUT Port - Out_Valid : out STD_LOGIC; - Out_Data : out STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0); - Out_Meta : out STD_LOGIC_VECTOR(META_BITS - 1 downto 0); - Out_Meta_rev : in STD_LOGIC_VECTOR(META_REV_BITS - 1 downto 0); - Out_SOF : out STD_LOGIC; - Out_EOF : out STD_LOGIC; - Out_Ack : in STD_LOGIC + Out_Valid : out std_logic; + Out_Data : out std_logic_vector(DATA_BITS - 1 downto 0); + Out_Meta : out std_logic_vector(META_BITS - 1 downto 0); + Out_Meta_rev : in std_logic_vector(META_REV_BITS - 1 downto 0); + Out_SOF : out std_logic; + Out_EOF : out std_logic; + Out_Ack : in std_logic ); end entity; architecture rtl of stream_Mux is - attribute KEEP : BOOLEAN; - attribute FSM_ENCODING : STRING; + attribute KEEP : boolean; + attribute FSM_ENCODING : string; - subtype T_CHANNEL_INDEX is NATURAL range 0 to PORTS - 1; + subtype T_CHANNEL_INDEX is natural range 0 to PORTS - 1; type T_STATE is (ST_IDLE, ST_DATAFLOW); signal State : T_STATE := ST_IDLE; signal NextState : T_STATE; - signal FSM_Dataflow_en : STD_LOGIC; + signal FSM_Dataflow_en : std_logic; - signal RequestVector : STD_LOGIC_VECTOR(PORTS - 1 downto 0); - signal RequestWithSelf : STD_LOGIC; - signal RequestWithoutSelf : STD_LOGIC; + signal RequestVector : std_logic_vector(PORTS - 1 downto 0); + signal RequestWithSelf : std_logic; + signal RequestWithoutSelf : std_logic; - signal RequestLeft : UNSIGNED(PORTS - 1 downto 0); - signal SelectLeft : UNSIGNED(PORTS - 1 downto 0); - signal SelectRight : UNSIGNED(PORTS - 1 downto 0); + signal RequestLeft : unsigned(PORTS - 1 downto 0); + signal SelectLeft : unsigned(PORTS - 1 downto 0); + signal SelectRight : unsigned(PORTS - 1 downto 0); - signal ChannelPointer_en : STD_LOGIC; - signal ChannelPointer : STD_LOGIC_VECTOR(PORTS - 1 downto 0); - signal ChannelPointer_d : STD_LOGIC_VECTOR(PORTS - 1 downto 0) := to_slv(2 ** (PORTS - 1), PORTS); - signal ChannelPointer_nxt : STD_LOGIC_VECTOR(PORTS - 1 downto 0); - signal ChannelPointer_bin : UNSIGNED(log2ceilnz(PORTS) - 1 downto 0); + signal ChannelPointer_en : std_logic; + signal ChannelPointer : std_logic_vector(PORTS - 1 downto 0); + signal ChannelPointer_d : std_logic_vector(PORTS - 1 downto 0) := to_slv(2 ** (PORTS - 1), PORTS); + signal ChannelPointer_nxt : std_logic_vector(PORTS - 1 downto 0); + signal ChannelPointer_bin : unsigned(log2ceilnz(PORTS) - 1 downto 0); signal idx : T_CHANNEL_INDEX; - signal Out_EOF_i : STD_LOGIC; + signal Out_EOF_i : std_logic; begin RequestVector <= In_Valid and In_SOF; @@ -178,14 +175,14 @@ begin In_Ack <= (In_Ack 'range => (Out_Ack and FSM_Dataflow_en)) and ChannelPointer; - genMetaReverse_0 : if (META_REV_BITS = 0) generate + genMetaReverse_0 : if META_REV_BITS = 0 generate In_Meta_rev <= (others => (others => '0')); end generate; - genMetaReverse_1 : if (META_REV_BITS > 0) generate + genMetaReverse_1 : if META_REV_BITS > 0 generate signal Temp_Meta_rev : T_SLM(PORTS - 1 downto 0, META_REV_BITS - 1 downto 0) := (others => (others => 'Z')); begin genAssign : for i in 0 to PORTS - 1 generate - signal row : STD_LOGIC_VECTOR(META_REV_BITS - 1 downto 0); + signal row : std_logic_vector(META_REV_BITS - 1 downto 0); begin row <= Out_Meta_rev and (row'range => ChannelPointer(i)); assign_row(Temp_Meta_rev, row, i); diff --git a/src/bus/stream/stream_Source.vhdl b/src/bus/stream/stream_Source.vhdl index f40a1248..92bd855b 100644 --- a/src/bus/stream/stream_Source.vhdl +++ b/src/bus/stream/stream_Source.vhdl @@ -1,20 +1,17 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: A generic buffer module for the PoC.Stream protocol. +-- Entity: A generic buffer module for the PoC.Stream protocol. -- -- Description: --- ------------------------------------ --- This module implements a generic buffer (FIFO) for the PoC.Stream protocol. --- It is generic in DATA_BITS and in META_BITS as well as in FIFO depths for --- data and meta information. +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -29,7 +26,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -44,38 +41,38 @@ use PoC.stream.all; entity stream_Source is generic ( - TESTCASES : T_SIM_STREAM_FRAMEGROUP_VECTOR_8 + TESTCASES : T_SIM_STREAM_FRAMEGROUP_VECTOR_8 ); port ( - Clock : in STD_LOGIC; - Reset : in STD_LOGIC; + Clock : in std_logic; + Reset : in std_logic; -- Control interface - Enable : in STD_LOGIC; + Enable : in std_logic; -- OUT Port - Out_Valid : out STD_LOGIC; - Out_Data : out T_SLV_8; - Out_SOF : out STD_LOGIC; - Out_EOF : out STD_LOGIC; - Out_Ack : in STD_LOGIC + Out_Valid : out std_logic; + Out_Data : out T_SLV_8; + Out_SOF : out std_logic; + Out_EOF : out std_logic; + Out_Ack : in std_logic ); end entity; architecture rtl of stream_Source is - constant MAX_CYCLES : NATURAL := 10 * 1000; - constant MAX_ERRORS : NATURAL := 50; + constant MAX_CYCLES : natural := 10 * 1000; + constant MAX_ERRORS : natural := 50; -- dummy signals for iSIM - signal FrameGroupNumber_us : UNSIGNED(log2ceilnz(TESTCASES'length) - 1 downto 0) := (others => '0'); + signal FrameGroupNumber_us : unsigned(log2ceilnz(TESTCASES'length) - 1 downto 0) := (others => '0'); begin process - variable Cycles : NATURAL := 0; - variable Errors : NATURAL := 0; + variable Cycles : natural := 0; + variable Errors : natural := 0; - variable FrameGroupNumber : NATURAL := 0; + variable FrameGroupNumber : natural := 0; - variable WordIndex : NATURAL := 0; + variable WordIndex : natural := 0; variable CurFG : T_SIM_STREAM_FRAMEGROUP_8; begin @@ -109,15 +106,15 @@ begin -- PrePause for i in 1 to CurFG.PrePause loop wait until rising_edge(Clock); - end LOOP; + end loop; WordIndex := 0; -- infinite loop loop -- check for to many simulation cycles - assert (Cycles < MAX_CYCLES) report "MAX_CYCLES reached: framegroup=" & INTEGER'image(to_integer(FrameGroupNumber_us)) severity FAILURE; --- ASSERT (Errors < MAX_ERRORS) report "MAX_ERRORS reached" severity FAILURE; + assert (Cycles < MAX_CYCLES) report "MAX_CYCLES reached: framegroup=" & integer'image(to_integer(FrameGroupNumber_us)) severity FAILURE; +-- assert (Errors < MAX_ERRORS) report "MAX_ERRORS reached" severity FAILURE; Cycles := Cycles + 1; wait until rising_edge(Clock); @@ -133,9 +130,9 @@ begin WordIndex := WordIndex + 1; end if; - -- check if framegroup end is reached => exit LOOP - assert FALSE report "WordIndex=" & INTEGER'image(WordIndex) severity WARNING; - exit when ((WordIndex /= 0) AND (CurFG.Data(WordIndex - 1).EOFG = TRUE)); + -- check if framegroup end is reached => exit loop + assert FALSE report "WordIndex=" & integer'image(WordIndex) severity WARNING; + exit when ((WordIndex /= 0) and (CurFG.Data(WordIndex - 1).EOFG = TRUE)); end loop; -- PostPause diff --git a/src/cache/cache.pkg.vhdl b/src/cache/cache.pkg.vhdl index 973efb7b..24729cb4 100644 --- a/src/cache/cache.pkg.vhdl +++ b/src/cache/cache.pkg.vhdl @@ -1,18 +1,17 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- -- Package: Cache functions and types -- -- Description: --- ------------------------------------ +-- ------------------------------------- -- For detailed documentation see below. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -27,7 +26,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.std_logic_1164.all; @@ -40,14 +39,14 @@ package cache is -- cache-lookup Result type T_CACHE_RESULT is (CACHE_RESULT_NONE, CACHE_RESULT_HIT, CACHE_RESULT_MISS); - function to_Cache_Result(CacheHit : STD_LOGIC; CacheMiss : STD_LOGIC) return T_CACHE_RESULT; + function to_Cache_Result(CacheHit : std_logic; CacheMiss : std_logic) return T_CACHE_RESULT; end package; package body cache is - function to_cache_Result(CacheHit : STD_LOGIC; CacheMiss : STD_LOGIC) return T_CACHE_RESULT is + function to_cache_Result(CacheHit : std_logic; CacheMiss : std_logic) return T_CACHE_RESULT is begin if (CacheMiss = '1') then return CACHE_RESULT_MISS; diff --git a/src/cache/cache_par.vhdl b/src/cache/cache_par.vhdl index 368a2ded..e38470d0 100644 --- a/src/cache/cache_par.vhdl +++ b/src/cache/cache_par.vhdl @@ -1,48 +1,53 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- Martin Zabel -- --- Module: Cache with parallel tag-unit and data memory. +-- Entity: Cache with parallel tag-unit and data memory. -- -- Description: --- ------------------------------------ +-- ------------------------------------- -- All inputs are synchronous to the rising-edge of the clock `clock`. -- --- Command truth table: +-- **Command truth table:** -- --- Request | ReadWrite | Invalidate | Replace | Command --- --------+-----------+-------------+---------+-------------------------------- --- 0 | 0 | 0 | 0 | None --- 1 | 0 | 0 | 0 | Read cache line --- 1 | 1 | 0 | 0 | Update cache line --- 1 | 0 | 1 | 0 | Read cache line and discard it --- 1 | 1 | 1 | 0 | Write cache line and discard it --- 0 | - | 0 | 1 | Replace cache line. --- --------+-----------+-------------+------------------------------------------ +-- +---------+-----------+-------------+---------+---------------------------------+ +-- | Request | ReadWrite | Invalidate | Replace | Command | +-- +=========+===========+=============+=========+=================================+ +-- | 0 | 0 | 0 | 0 | None | +-- +---------+-----------+-------------+---------+---------------------------------+ +-- | 1 | 0 | 0 | 0 | Read cache line | +-- +---------+-----------+-------------+---------+---------------------------------+ +-- | 1 | 1 | 0 | 0 | Update cache line | +-- +---------+-----------+-------------+---------+---------------------------------+ +-- | 1 | 0 | 1 | 0 | Read cache line and discard it | +-- +---------+-----------+-------------+---------+---------------------------------+ +-- | 1 | 1 | 1 | 0 | Write cache line and discard it | +-- +---------+-----------+-------------+---------+---------------------------------+ +-- | 0 | | 0 | 1 | Replace cache line. | +-- +---------+-----------+-------------+---------+---------------------------------+ -- --- All commands use `Address` to lookup (request) or replace a cache line. --- `Address` and `OldAddress` do not include the word/byte select part. +-- All commands use ``Address`` to lookup (request) or replace a cache line. +-- ``Address`` and ``OldAddress`` do not include the word/byte select part. -- Each command is completed within one clock cycle, but outputs are delayed as -- described below. -- --- Upon requests, the outputs `CacheMiss` and `CacheHit` indicate (high-active) --- whether the `Address` is stored within the cache, or not. Both outputs have a +-- Upon requests, the outputs ``CacheMiss`` and ``CacheHit`` indicate (high-active) +-- whether the ``Address`` is stored within the cache, or not. Both outputs have a -- latency of one clock cycle. -- --- Upon writing a cache line, the new content is given by `CacheLineIn`. --- Upon reading a cache line, the current content is outputed on `CacheLineOut` +-- Upon writing a cache line, the new content is given by ``CacheLineIn``. +-- Upon reading a cache line, the current content is outputed on ``CacheLineOut`` -- with a latency of one clock cycle. -- --- Upon replacing a cache line, the new content is given by `CacheLineIn`. The --- old content is outputed on `CacheLineOut` and the old tag on `OldAddress`, +-- Upon replacing a cache line, the new content is given by ``CacheLineIn``. The +-- old content is outputed on ``CacheLineOut`` and the old tag on ``OldAddress``, -- both with a latency of one clock cycle. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -57,15 +62,15 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; -use IEEE.STD_LOGIC_1164.all; -use IEEE.NUMERIC_STD.all; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; library PoC; -use PoC.utils.all; -use PoC.vectors.all; +use PoC.utils.all; +use PoC.vectors.all; entity cache_par is @@ -92,7 +97,7 @@ entity cache_par is CacheMiss : out std_logic := '0'; OldAddress : out std_logic_vector(ADDRESS_BITS - 1 downto 0) ); -end; +end entity; architecture rtl of cache_par is diff --git a/src/cache/cache_replacement_policy.vhdl b/src/cache/cache_replacement_policy.vhdl index bce8c54a..6db18718 100644 --- a/src/cache/cache_replacement_policy.vhdl +++ b/src/cache/cache_replacement_policy.vhdl @@ -1,48 +1,60 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- Martin Zabel -- --- Module: Wrap different cache replacement policies. +-- Entity: Wrap different cache replacement policies. -- -- Description: --- ------------------------------------ --- --- Policies | supported --- -----------------------------------#-------------------- --- RR round robin | not yet --- RAND random | not yet --- CLOCK clock algorithm | not yet --- LRU least recently used | YES --- LFU least frequently used | not yet --- -----------------------------------#-------------------- --- --- Command thruth table: --- --- TagAccess | ReadWrite | Invalidate | Replace | Command --- ----------+-----------+-------------+---------+-------------------------------- --- 0 | - | - | 0 | None --- 1 | 0 | 0 | 0 | TagHit and reading a cache line --- 1 | 1 | 0 | 0 | TagHit and writing a cache line --- 1 | 0 | 1 | 0 | TagHit and invalidate a cache line (while reading) --- 1 | 1 | 1 | 0 | TagHit and invalidate a cache line (while writing) --- 0 | - | 0 | 1 | Replace cache line --- ----------+-----------+-------------+------------------------------------------ +-- ------------------------------------- +-- +-- **Supported policies:** +-- +-- +----------+-----------------------+-----------+ +-- | Abbr. | Policies | supported | +-- +==========+=======================+===========+ +-- | RR | round robin | not yet | +-- +----------+-----------------------+-----------+ +-- | RAND | random | not yet | +-- +----------+-----------------------+-----------+ +-- | CLOCK | clock algorithm | not yet | +-- +----------+-----------------------+-----------+ +-- | LRU | least recently used | YES | +-- +----------+-----------------------+-----------+ +-- | LFU | least frequently used | not yet | +-- +----------+-----------------------+-----------+ +-- +-- **Command thruth table:** +-- +-- +-----------+-----------+-------------+---------+-----------------------------------------------------+ +-- | TagAccess | ReadWrite | Invalidate | Replace | Command | +-- +===========+===========+=============+=========+=====================================================+ +-- | 0 | | | 0 | None | +-- +-----------+-----------+-------------+---------+-----------------------------------------------------+ +-- | 1 | 0 | 0 | 0 | TagHit and reading a cache line | +-- +-----------+-----------+-------------+---------+-----------------------------------------------------+ +-- | 1 | 1 | 0 | 0 | TagHit and writing a cache line | +-- +-----------+-----------+-------------+---------+-----------------------------------------------------+ +-- | 1 | 0 | 1 | 0 | TagHit and invalidate a cache line (while reading) | +-- +-----------+-----------+-------------+---------+-----------------------------------------------------+ +-- | 1 | 1 | 1 | 0 | TagHit and invalidate a cache line (while writing) | +-- +-----------+-----------+-------------+---------+-----------------------------------------------------+ +-- | 0 | | 0 | 1 | Replace cache line | +-- +-----------+-----------+-------------+---------+-----------------------------------------------------+ -- -- In a set-associative cache, each cache-set has its own instance of this component. -- --- The input `HitWay` specifies the accessed way in a fully-associative or +-- The input ``HitWay`` specifies the accessed way in a fully-associative or -- set-associative cache. -- --- The output `ReplaceWay` identifies the way which will be replaced as next by +-- The output ``ReplaceWay`` identifies the way which will be replaced as next by -- a replace command. In a set-associative cache, this is the way in a specific -- cache set (see above). -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -57,7 +69,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -89,7 +101,7 @@ entity cache_replacement_policy is Invalidate : in std_logic; HitWay : in std_logic_vector(log2ceilnz(CACHE_WAYS) - 1 downto 0) ); -end; +end entity; architecture rtl of cache_replacement_policy is @@ -108,7 +120,7 @@ begin -- =========================================================================== -- policy: RR - round robin -- =========================================================================== - genRR : if (str_equal(REPLACEMENT_POLICY, "RR") = true) generate + genRR : if str_equal(REPLACEMENT_POLICY, "RR") generate constant VALID_BIT : natural := 0; subtype T_OPTION_LINE is std_logic_vector(0 downto 0); @@ -125,46 +137,46 @@ begin -- ValidHit <= OptionMemory(to_integer(unsigned(HitWay)))(VALID_BIT); -- IsValid <= ValidHit; -- --- PROCESS(Clock) --- BEGIN --- IF rising_edge(Clock) THEN --- IF (Reset = '1') THEN --- FOR I IN 0 TO CACHE_WAYS - 1 LOOP +-- process(Clock) +-- begin +-- if rising_edge(Clock) then +-- if (Reset = '1') then +-- for i in 0 to CACHE_WAYS - 1 loop -- OptionMemory(I)(VALID_BIT) <= '0'; --- END LOOP; --- ELSE --- IF (Insert = '1') THEN +-- end loop; +-- else +-- if (Insert = '1') then -- OptionMemory(to_integer(Pointer_us))(VALID_BIT) <= '1'; --- END IF; +-- end if; -- --- IF (Invalidate = '1') THEN +-- if (Invalidate = '1') then -- OptionMemory(to_integer(unsigned(HitWay)))(VALID_BIT) <= '0'; --- END IF; --- END IF; --- END IF; --- END PROCESS; +-- end if; +-- end if; +-- end if; +-- end process; -- -- Replace <= Insert; -- ReplaceWay <= std_logic_vector(Pointer_us); -- --- PROCESS(Clock) --- BEGIN --- IF rising_edge(Clock) THEN --- IF (Reset = '1') THEN --- Pointer_us <= (OTHERS => '0'); --- ELSE --- IF (Insert = '1') THEN +-- process(Clock) +-- begin +-- if rising_edge(Clock) then +-- if (Reset = '1') then +-- Pointer_us <= (others => '0'); +-- else +-- if (Insert = '1') then -- Pointer_us <= Pointer_us + 1; --- END IF; --- END IF; --- END IF; --- END PROCESS; +-- end if; +-- end if; +-- end if; +-- end process; end generate; -- =========================================================================== -- policy: LRU - least recently used -- =========================================================================== - genLRU : if (str_equal(REPLACEMENT_POLICY, "LRU") = true) generate + genLRU : if str_equal(REPLACEMENT_POLICY, "LRU") generate signal LRU_Insert : std_logic; signal LRU_Invalidate : std_logic; signal KeyIn : std_logic_vector(log2ceilnz(CACHE_WAYS) - 1 downto 0); diff --git a/src/cache/cache_tagunit_par.vhdl b/src/cache/cache_tagunit_par.vhdl index 41164f0f..05cf42a9 100644 --- a/src/cache/cache_tagunit_par.vhdl +++ b/src/cache/cache_tagunit_par.vhdl @@ -1,48 +1,53 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- Martin Zabel -- --- Module: Tag-unit with fully-parallel compare of tag. +-- Entity: Tag-unit with fully-parallel compare of tag. -- -- Description: --- ------------------------------------ --- All inputs are synchronous to the rising-edge of the clock `clock`. +-- ------------------------------------- +-- All inputs are synchronous to the rising-edge of the clock ``clock``. -- --- Command truth table: +-- **Command thruth table:** -- --- Request | ReadWrite | Invalidate | Replace | Command --- --------+-----------+-------------+---------+-------------------------------- --- 0 | 0 | 0 | 0 | None --- 1 | 0 | 0 | 0 | Read cache line --- 1 | 1 | 0 | 0 | Update cache line --- 1 | 0 | 1 | 0 | Read cache line and discard it --- 1 | 1 | 1 | 0 | Write cache line and discard it --- 0 | - | 0 | 1 | Replace cache line. --- --------+-----------+-------------+------------------------------------------ +-- +---------+-----------+-------------+---------+----------------------------------+ +-- | Request | ReadWrite | Invalidate | Replace | Command | +-- +=========+===========+=============+=========+==================================+ +-- | 0 | 0 | 0 | 0 | None | +-- +---------+-----------+-------------+---------+----------------------------------+ +-- | 1 | 0 | 0 | 0 | Read cache line | +-- +---------+-----------+-------------+---------+----------------------------------+ +-- | 1 | 1 | 0 | 0 | Update cache line | +-- +---------+-----------+-------------+---------+----------------------------------+ +-- | 1 | 0 | 1 | 0 | Read cache line and discard it | +-- +---------+-----------+-------------+---------+----------------------------------+ +-- | 1 | 1 | 1 | 0 | Write cache line and discard it | +-- +---------+-----------+-------------+---------+----------------------------------+ +-- | 0 | | 0 | 1 | Replace cache line. | +-- +---------+-----------+-------------+---------+----------------------------------+ -- --- All commands use `Address` to lookup (request) or replace a cache line. +-- All commands use ``Address`` to lookup (request) or replace a cache line. -- Each command is completed within one clock cycle. -- --- Upon requests, the outputs `CacheMiss` and `CacheHit` indicate (high-active) --- immediately (combinational) whether the `Address` is stored within the cache, or not. +-- Upon requests, the outputs ``CacheMiss`` and ``CacheHit`` indicate (high-active) +-- immediately (combinational) whether the ``Address`` is stored within the cache, or not. -- But, the cache-line usage is updated at the rising-edge of the clock. --- If hit, `LineIndex` specifies the cache line where to find the content. +-- If hit, ``LineIndex`` specifies the cache line where to find the content. -- --- The output `ReplaceLineIndex` indicates which cache line will be replaced as --- next by a replace command. The output `OldAddress` specifies the old tag stored at this --- index. The replace command will store the `NewAddress` and update the cache-line +-- The output ``ReplaceLineIndex`` indicates which cache line will be replaced as +-- next by a replace command. The output ``OldAddress`` specifies the old tag stored at this +-- index. The replace command will store the ``NewAddress`` and update the cache-line -- usage at the rising-edge of the clock. -- --- For a direct-mapped cache, the number of CACHE_LINES must be a power of 2. --- For a set-associative cache, the expression (CACHE_LINES / ASSOCIATIVITY) +-- For a direct-mapped cache, the number of ``CACHE_LINES`` must be a power of 2. +-- For a set-associative cache, the expression ``CACHE_LINES / ASSOCIATIVITY`` -- must be a power of 2. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -57,15 +62,15 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; -use IEEE.STD_LOGIC_1164.all; -use IEEE.NUMERIC_STD.all; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; library PoC; -use PoC.utils.all; -use PoC.vectors.all; +use PoC.utils.all; +use PoC.vectors.all; entity cache_tagunit_par is generic ( @@ -91,7 +96,7 @@ entity cache_tagunit_par is TagHit : out std_logic; TagMiss : out std_logic ); -end; +end entity; architecture rtl of cache_tagunit_par is attribute KEEP : boolean; @@ -102,7 +107,7 @@ begin -- =========================================================================== -- Full-Associative Cache -- =========================================================================== - genFA : if (CACHE_LINES = ASSOCIATIVITY) generate + genFA : if CACHE_LINES = ASSOCIATIVITY generate constant TAG_BITS : positive := ADDRESS_BITS; constant WAY_BITS : positive := log2ceilnz(ASSOCIATIVITY); @@ -158,7 +163,7 @@ begin -- hit/miss calculation TagHit_i <= slv_or(TagHits) and Request; - TagMiss_i <= not (slv_or(TagHits)) and Request; + TagMiss_i <= not slv_or(TagHits) and Request; -- outputs LineIndex <= std_logic_vector(HitWay); @@ -192,7 +197,7 @@ begin -- =========================================================================== -- Direct-Mapped Cache -- =========================================================================== - genDM : if (ASSOCIATIVITY = 1) generate + genDM : if ASSOCIATIVITY = 1 generate -- Addresses are splitted into a tag part and an index part. constant INDEX_BITS : positive := log2ceilnz(CACHE_LINES); constant TAG_BITS : positive := ADDRESS_BITS - INDEX_BITS; @@ -249,7 +254,7 @@ begin -- hit/miss calculation TagHit_i <= DM_TagHit and Request; - TagMiss_i <= not (DM_TagHit) and Request; + TagMiss_i <= not DM_TagHit and Request; -- outputs LineIndex <= std_logic_vector(Address_Index); @@ -263,7 +268,7 @@ begin -- =========================================================================== -- Set-Assoziative Cache -- =========================================================================== - genSA : if ((ASSOCIATIVITY > 1) and (SETS > 1)) generate + genSA : if (ASSOCIATIVITY > 1) and (SETS > 1) generate -- Addresses are splitted into a tag part and an index part. constant CACHE_SETS : positive := CACHE_LINES / ASSOCIATIVITY; constant INDEX_BITS : positive := log2ceilnz(CACHE_SETS); @@ -351,7 +356,7 @@ begin -- Global hit / miss calculation and output ---------------------------------------------------------------------------- TagHit_i <= slv_or(TagHits) and Request; - TagMiss_i <= not (slv_or(TagHits)) and Request; + TagMiss_i <= not slv_or(TagHits) and Request; LineIndex <= std_logic_vector(HitWay) & std_logic_vector(Address_Index); TagHit <= TagHit_i; diff --git a/src/cache/cache_tagunit_seq.vhdl b/src/cache/cache_tagunit_seq.vhdl index d9e4db4d..2241aa10 100644 --- a/src/cache/cache_tagunit_seq.vhdl +++ b/src/cache/cache_tagunit_seq.vhdl @@ -1,18 +1,17 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: Tag-unit with sequential compare of tag. +-- Entity: Tag-unit with sequential compare of tag. -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2014 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -27,15 +26,15 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; -use IEEE.STD_LOGIC_1164.all; -use IEEE.NUMERIC_STD.all; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; library PoC; -use PoC.utils.all; -use PoC.vectors.all; +use PoC.utils.all; +use PoC.vectors.all; entity cache_tagunit_seq is generic ( @@ -71,7 +70,7 @@ entity cache_tagunit_seq is Request_TagHit : out std_logic; Request_TagMiss : out std_logic ); -end; +end entity; architecture rtl of cache_tagunit_seq is @@ -83,7 +82,7 @@ begin -- ========================================================================================================================================================== -- Full-Assoziative Cache -- ========================================================================================================================================================== - genFA : if (CACHE_LINES = ASSOCIATIVITY) generate + genFA : if CACHE_LINES = ASSOCIATIVITY generate constant FA_CACHE_LINES : positive := ASSOCIATIVITY; constant FA_TAG_BITS : positive := TAG_BITS; constant FA_CHUNKS : positive := div_ceil(FA_TAG_BITS, CHUNK_BITS); @@ -114,7 +113,7 @@ begin constant tag_line : std_logic_vector(slm'high(2) downto slm'low(2)) := get_row(slm, row); variable result : T_TAG_LINE(FA_CHUNKS - 1 downto 0); begin --- REPORT "tagline @row " & INTEGER'image(row) & " = " & to_string(tag_line, 'h') SEVERITY NOTE; +-- report "tagline @row " & INTEGER'image(row) & " = " & to_string(tag_line, 'h') severity NOTE; for I in result'range loop result(I) := tag_line((I * CHUNK_BITS) + CHUNK_BITS - 1 downto (I * CHUNK_BITS)); end loop; @@ -129,10 +128,10 @@ begin signal RequestComplete : std_logic; signal NewTagSeqCounter_rst : std_logic; --- SIGNAL NewTagSeqCounter_en : STD_LOGIC; +-- signal NewTagSeqCounter_en : STD_LOGIC; signal NewTagSeqCounter_us : unsigned(FA_CHUNK_INDEX_BITS - 1 downto 0) := (others => '0'); signal TagSeqCounter_rst : std_logic; --- SIGNAL TagSeqCounter_en : STD_LOGIC; +-- signal TagSeqCounter_en : STD_LOGIC; signal TagSeqCounter_us : unsigned(FA_CHUNK_INDEX_BITS - 1 downto 0) := (others => '0'); signal TagMemory_we : std_logic; @@ -207,7 +206,7 @@ begin -- NewTagSeqCounter_en <= '1'; TagMemory_we <= '1'; - if (NewTagSeqCounter_us = ite((TAG_BYTE_ORDER = LITTLE_ENDIAN), (FA_CHUNKS - 1), 0)) then + if NewTagSeqCounter_us = ite((TAG_BYTE_ORDER = LITTLE_ENDIAN), (FA_CHUNKS - 1), 0) then Replaced <= '1'; Replace_NextState <= ST_IDLE; @@ -261,7 +260,7 @@ begin Request_NextState <= ST_IDLE; else - if (TagSeqCounter_us = ite((TAG_BYTE_ORDER = LITTLE_ENDIAN), (FA_CHUNKS - 1), 0)) then + if TagSeqCounter_us = ite((TAG_BYTE_ORDER = LITTLE_ENDIAN), (FA_CHUNKS - 1), 0) then RequestComplete <= '1'; Request_NextState <= ST_READ; @@ -297,13 +296,13 @@ begin if rising_edge(Clock) then -- NewTagSeqCounter if ((Reset or NewTagSeqCounter_rst) = '1') then - if (TAG_BYTE_ORDER = LITTLE_ENDIAN) then + if TAG_BYTE_ORDER = LITTLE_ENDIAN then NewTagSeqCounter_us <= to_unsigned(0, NewTagSeqCounter_us'length); else NewTagSeqCounter_us <= to_unsigned((FA_CHUNKS - 1), NewTagSeqCounter_us'length); end if; else - if (TAG_BYTE_ORDER = LITTLE_ENDIAN) then + if TAG_BYTE_ORDER = LITTLE_ENDIAN then NewTagSeqCounter_us <= NewTagSeqCounter_us + 1; else NewTagSeqCounter_us <= NewTagSeqCounter_us - 1; @@ -312,13 +311,13 @@ begin -- TagSeqCounter if ((Reset or TagSeqCounter_rst) = '1') then - if (TAG_BYTE_ORDER = LITTLE_ENDIAN) then + if TAG_BYTE_ORDER = LITTLE_ENDIAN then TagSeqCounter_us <= to_unsigned(0, TagSeqCounter_us'length); else TagSeqCounter_us <= to_unsigned((FA_CHUNKS - 1), TagSeqCounter_us'length); end if; else - if (TAG_BYTE_ORDER = LITTLE_ENDIAN) then + if TAG_BYTE_ORDER = LITTLE_ENDIAN then TagSeqCounter_us <= TagSeqCounter_us + 1; else TagSeqCounter_us <= TagSeqCounter_us - 1; @@ -332,9 +331,9 @@ begin constant C_TAGMEMORY : T_TAG_LINE(FA_CHUNKS - 1 downto 0) := to_tagmemory(FA_INITIAL_TAGS_RESIZED, I); signal TagMemory : T_TAG_LINE(FA_CHUNKS - 1 downto 0) := C_TAGMEMORY; begin --- genASS : FOR J IN 0 TO FA_CHUNKS - 1 GENERATE --- ASSERT FALSE REPORT "line=" & INTEGER'image(I) & " chunk=" & INTEGER'image(J) & " tag=" & to_string(C_TAGMEMORY(J), 'h') SEVERITY NOTE; --- END GENERATE; +-- genASS : for j in 0 to FA_CHUNKS - 1 generate +-- assert FALSE report "line=" & INTEGER'image(I) & " chunk=" & INTEGER'image(J) & " tag=" & to_string(C_TAGMEMORY(J), 'h') severity NOTE; +-- end generate; process(Clock) begin @@ -406,7 +405,6 @@ begin TagIndex <= MemoryIndex_i when rising_edge(Clock); -- replacement policy --- Policy : ENTITY L_Global.cache_replacement_policy Policy : entity PoC.cache_replacement_policy generic map ( REPLACEMENT_POLICY => REPLACEMENT_POLICY, @@ -428,7 +426,7 @@ begin -- ========================================================================================================================================================== -- Direct-Mapped Cache -- ========================================================================================================================================================== - genDM : if (ASSOCIATIVITY = 1) generate + genDM : if ASSOCIATIVITY = 1 generate constant FA_CACHE_LINES : positive := CACHE_LINES; constant FA_TAG_BITS : positive := TAG_BITS; constant FA_MEMORY_INDEX_BITS : positive := log2ceilnz(FA_CACHE_LINES); @@ -445,9 +443,9 @@ begin signal TagMiss_i : std_logic; begin -- -- generate comparators --- genVectors : FOR I IN 0 TO FA_CACHE_LINES - 1 GENERATE +-- genVectors : for i in 0 to FA_CACHE_LINES - 1 generate -- TagHits(I) <= to_sl(TagMemory(I) = FA_Tag); --- END GENERATE; +-- end generate; -- -- -- convert hit-vector to binary index (cache line address) -- FA_MemoryIndex_us <= onehot2bin(TagHits); @@ -456,15 +454,15 @@ begin -- -- Memories -- FA_ReplaceIndex_us <= FA_MemoryIndex_us; -- --- PROCESS(Clock) --- BEGIN --- IF rising_edge(Clock) THEN --- IF (Replace = '1') THEN +-- process(Clock) +-- begin +-- if rising_edge(Clock) then +-- if (Replace = '1') then -- TagMemory(to_integer(FA_ReplaceIndex_us)) <= NewTag; -- ValidMemory(to_integer(FA_ReplaceIndex_us)) <= '1'; --- END IF; --- END IF; --- END PROCESS; +-- end if; +-- end if; +-- end process; -- -- -- access valid-vector -- ValidHit <= ValidMemory(to_integer(FA_MemoryIndex_us)); @@ -478,14 +476,14 @@ begin -- TagHit <= TagHit_i; -- TagMiss <= TagMiss_i; -- --- genPolicy : FOR I IN 0 TO SETS - 1 GENERATE --- policy : ENTITY PoC.cache_replacement_policy --- GENERIC MAP ( +-- genPolicy : for i in 0 to SETS - 1 generate +-- policy : entity PoC.cache_replacement_policy +-- generic map ( -- REPLACEMENT_POLICY => REPLACEMENT_POLICY, -- CACHE_LINES => ASSOCIATIVITY, --- INITIAL_VALIDS => INITIAL_VALIDS(I * ASSOCIATIVITY + ASSOCIATIVITY - 1 DOWNTO I * ASSOCIATIVITY) +-- INITIAL_VALIDS => INITIAL_VALIDS(I * ASSOCIATIVITY + ASSOCIATIVITY - 1 downto I * ASSOCIATIVITY) -- ) --- PORT MAP ( +-- port map ( -- Clock => Clock, -- Reset => Reset, -- @@ -497,12 +495,12 @@ begin -- Invalidate => Invalidate(I), -- Index => Policy_Index(I) -- ); --- END GENERATE; +-- end generate; end generate; -- ========================================================================================================================================================== -- Set-Assoziative Cache -- ========================================================================================================================================================== - genSA : if ((ASSOCIATIVITY > 1) and (SETS > 1)) generate + genSA : if (ASSOCIATIVITY > 1) and (SETS > 1) generate constant FA_CACHE_LINES : positive := CACHE_LINES; constant SETINDEX_BITS : natural := log2ceil(SETS); constant FA_TAG_BITS : positive := TAG_BITS; @@ -520,9 +518,9 @@ begin signal TagMiss_i : std_logic; begin -- -- generate comparators --- genVectors : FOR I IN 0 TO FA_CACHE_LINES - 1 GENERATE +-- genVectors : for i in 0 to FA_CACHE_LINES - 1 generate -- TagHits(I) <= to_sl(TagMemory(I) = FA_Tag); --- END GENERATE; +-- end generate; -- -- -- convert hit-vector to binary index (cache line address) -- FA_MemoryIndex_us <= onehot2bin(TagHits); @@ -531,15 +529,15 @@ begin -- -- Memories -- FA_ReplaceIndex_us <= FA_MemoryIndex_us; -- --- PROCESS(Clock) --- BEGIN --- IF rising_edge(Clock) THEN --- IF (Replace = '1') THEN +-- process(Clock) +-- begin +-- if rising_edge(Clock) then +-- if (Replace = '1') then -- TagMemory(to_integer(FA_ReplaceIndex_us)) <= NewTag; -- ValidMemory(to_integer(FA_ReplaceIndex_us)) <= '1'; --- END IF; --- END IF; --- END PROCESS; +-- end if; +-- end if; +-- end process; -- -- -- access valid-vector -- ValidHit <= ValidMemory(to_integer(FA_MemoryIndex_us)); @@ -553,14 +551,14 @@ begin -- TagHit <= TagHit_i; -- TagMiss <= TagMiss_i; -- --- genPolicy : FOR I IN 0 TO SETS - 1 GENERATE --- policy : ENTITY PoC.cache_replacement_policy --- GENERIC MAP ( +-- genPolicy : for i in 0 to SETS - 1 generate +-- policy : entity PoC.cache_replacement_policy +-- generic map ( -- REPLACEMENT_POLICY => REPLACEMENT_POLICY, -- CACHE_LINES => ASSOCIATIVITY, --- INITIAL_VALIDS => INITIAL_VALIDS(I * ASSOCIATIVITY + ASSOCIATIVITY - 1 DOWNTO I * ASSOCIATIVITY) +-- INITIAL_VALIDS => INITIAL_VALIDS(I * ASSOCIATIVITY + ASSOCIATIVITY - 1 downto I * ASSOCIATIVITY) -- ) --- PORT MAP ( +-- port map ( -- Clock => Clock, -- Reset => Reset, -- @@ -572,6 +570,6 @@ begin -- Invalidate => Invalidate(I), -- Index => Policy_Index(I) -- ); --- END GENERATE; +-- end generate; end generate; end architecture; diff --git a/src/comm/comm.pkg.vhdl b/src/comm/comm.pkg.vhdl index 5eaed89c..a64df347 100644 --- a/src/comm/comm.pkg.vhdl +++ b/src/comm/comm.pkg.vhdl @@ -1,19 +1,18 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Thomas B. Preusser -- --- Module: VHDL package for component declarations, types and +-- Entity: VHDL package for component declarations, types and -- functions associated to the PoC.comm namespace -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -28,7 +27,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.std_logic_1164.all; diff --git a/src/comm/comm_crc.vhdl b/src/comm/comm_crc.vhdl index ffc23ed5..0fe5fe8b 100644 --- a/src/comm/comm_crc.vhdl +++ b/src/comm/comm_crc.vhdl @@ -1,22 +1,21 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Thomas B. Preusser -- Patrick Lehmann -- --- Module: Computes the Cyclic Redundancy Check (CRC) +-- Entity: Computes the Cyclic Redundancy Check (CRC) -- -- Description: --- ------------------------------------ --- Computes the Cyclic Redundancy Check (CRC) for a data packet as remainder --- of the polynomial division of the message by the given generator --- polynomial (GEN). +-- ------------------------------------- +-- Computes the Cyclic Redundancy Check (CRC) for a data packet as remainder +-- of the polynomial division of the message by the given generator +-- polynomial (GEN). -- --- The computation is unrolled so as to process an arbitrary number of --- message bits per step. The generated CRC is independent from the chosen --- processing width. +-- The computation is unrolled so as to process an arbitrary number of +-- message bits per step. The generated CRC is independent from the chosen +-- processing width. -- -- License: -- ============================================================================= @@ -62,7 +61,7 @@ entity comm_crc is rmd : out std_logic_vector(abs(mssb_idx(GEN)-GEN'right)-1 downto 0); -- Remainder zero : out std_logic -- Remainder is Zero ); -end comm_crc; +end entity comm_crc; architecture rtl of comm_crc is @@ -124,4 +123,4 @@ begin rmd <= lfso; zero <= '1' when lfso = (lfso'range => '0') else '0'; -end rtl; +end architecture; diff --git a/src/comm/comm_scramble.vhdl b/src/comm/comm_scramble.vhdl index ca1a965d..cfc2f4be 100644 --- a/src/comm/comm_scramble.vhdl +++ b/src/comm/comm_scramble.vhdl @@ -1,17 +1,16 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Thomas B. Preusser -- --- Module: Computes XOR masks for stream scrambling from an LFSR generator. +-- Entity: Computes XOR masks for stream scrambling from an LFSR generator. -- -- Description: --- ------------------------------------ --- The LFSR computation is unrolled to generate an arbitrary number of mask --- bits in parallel. The mask are output in little endian. The generated bit --- sequence is independent from the chosen output width. +-- ------------------------------------- +-- The LFSR computation is unrolled to generate an arbitrary number of mask +-- bits in parallel. The mask are output in little endian. The generated bit +-- sequence is independent from the chosen output width. -- -- License: -- ============================================================================= @@ -38,18 +37,18 @@ use IEEE.std_logic_1164.all; entity comm_scramble is generic ( GEN : bit_vector; -- Generator Polynomial (little endian) - BITS : positive -- Width of Mask Bits to be computed in parallel + BITS : positive -- Width of Mask Bits to be computed in parallel in each step ); port ( clk : in std_logic; -- Clock - set : in std_logic; -- Set LFSR to provided Value - din : in std_logic_vector(GEN'length-2 downto 0); + set : in std_logic; -- Set LFSR to value provided on din + din : in std_logic_vector(GEN'length-2 downto 0) := (others => '0'); step : in std_logic; -- Compute a Mask Output - mask : out std_logic_vector(BITS-1 downto 0) := (others => '0') + mask : out std_logic_vector(BITS-1 downto 0) ); -end comm_scramble; +end entity comm_scramble; architecture rtl of comm_scramble is @@ -97,4 +96,4 @@ begin end if; end process; -end rtl; +end architecture; diff --git a/src/common/common.files b/src/common/common.files index 8eb3f623..a49fce70 100644 --- a/src/common/common.files +++ b/src/common/common.files @@ -17,11 +17,13 @@ vhdl poc "src/common/physical.vhdl" # PoC physical types package vhdl poc "src/common/components.vhdl" # PoC components if (ToolChain not in ["Altera_QuartusII", "Lattice_Diamond"]) then - if (VHDL < 2002) then + if (VHDLVersion < 2002) then vhdl poc "src/common/fileio.v93.vhdl" # - elseif (VHDL >= 2002) then + elseif (VHDLVersion <= 2008) then vhdl poc "src/common/protected.v08.vhdl" # PoC protected type implementations vhdl poc "src/common/fileio.v08.vhdl" # + else + report "VHDL version not supported." end if end if diff --git a/src/common/common.vhdl b/src/common/common.vhdl index 8182647e..543dc865 100644 --- a/src/common/common.vhdl +++ b/src/common/common.vhdl @@ -1,18 +1,17 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- -- Context: Provides all packages from /src/common. -- -- Description: --- ------------------------------------ +-- ------------------------------------- -- This package provides all common packages as a single context. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -27,7 +26,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= context Common is library PoC ; diff --git a/src/common/components.vhdl b/src/common/components.vhdl index 5febe160..8fff218a 100644 --- a/src/common/components.vhdl +++ b/src/common/components.vhdl @@ -1,14 +1,13 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- -- Package: Common primitives described as a function -- -- Description: --- ------------------------------------ +-- ------------------------------------- -- This packages describes common primitives like flip flops and multiplexers -- as a function to use them as one-liners. -- @@ -18,7 +17,7 @@ -- this value MUST be set via signal declaration! -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -33,7 +32,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -45,69 +44,58 @@ use PoC.utils.all; package components is -- implement an optional register stage - function registered(signal Clock : STD_LOGIC; constant IsRegistered : BOOLEAN) return BOOLEAN; + function registered(signal Clock : std_logic; constant IsRegistered : boolean) return boolean; -- FlipFlop functions -- =========================================================================== -- RS-FlipFlops - function ffrs(q : STD_LOGIC; rst : STD_LOGIC := '0'; set : STD_LOGIC := '0') return STD_LOGIC; -- RS-FlipFlop with dominant rst - function ffsr(q : STD_LOGIC; rst : STD_LOGIC := '0'; set : STD_LOGIC := '0') return STD_LOGIC; -- RS-FlipFlop with dominant set + function ffrs(q : std_logic; rst : std_logic := '0'; set : std_logic := '0') return std_logic; -- RS-FlipFlop with dominant rst + function ffsr(q : std_logic; rst : std_logic := '0'; set : std_logic := '0') return std_logic; -- RS-FlipFlop with dominant set -- D-FlipFlops (Delay) - function ffdre(q : STD_LOGIC; d : STD_LOGIC; rst : STD_LOGIC := '0'; en : STD_LOGIC := '1'; constant INIT : STD_LOGIC := '0') return STD_LOGIC; -- D-FlipFlop with reset and enable - function ffdre(q : STD_LOGIC_VECTOR; d : STD_LOGIC_VECTOR; rst : STD_LOGIC := '0'; en : STD_LOGIC := '1'; constant INIT : STD_LOGIC_VECTOR := (7 downto 0 => '0')) return STD_LOGIC_VECTOR; -- D-FlipFlop with reset and enable - function ffdse(q : STD_LOGIC; d : STD_LOGIC; set : STD_LOGIC := '0'; en : STD_LOGIC := '1') return STD_LOGIC; -- D-FlipFlop with set and enable + function ffdre(q : std_logic; d : std_logic; rst : std_logic := '0'; en : std_logic := '1'; constant INIT : std_logic := '0') return std_logic; -- D-FlipFlop with reset and enable + function ffdre(q : std_logic_vector; d : std_logic_vector; rst : std_logic := '0'; en : std_logic := '1'; constant INIT : std_logic_vector := (7 downto 0 => '0')) return std_logic_vector; -- D-FlipFlop with reset and enable + function ffdse(q : std_logic; d : std_logic; set : std_logic := '0'; en : std_logic := '1') return std_logic; -- D-FlipFlop with set and enable -- T-FlipFlops (Toggle) - function fftre(q : STD_LOGIC; t : STD_LOGIC; rst : STD_LOGIC := '0'; en : STD_LOGIC := '1'; constant INIT : STD_LOGIC := '0') return STD_LOGIC; -- T-FlipFlop with reset and enable - function fftse(q : STD_LOGIC; t : STD_LOGIC; set : STD_LOGIC := '0'; en : STD_LOGIC := '1') return STD_LOGIC; -- T-FlipFlop with set and enable - - -- adder - function inc(value : STD_LOGIC_VECTOR; constant increment : NATURAL := 1) return STD_LOGIC_VECTOR; - function inc(value : UNSIGNED; constant increment : NATURAL := 1) return UNSIGNED; - function inc(value : SIGNED; constant increment : NATURAL := 1) return SIGNED; - function dec(value : STD_LOGIC_VECTOR; constant decrement : NATURAL := 1) return STD_LOGIC_VECTOR; - function dec(value : UNSIGNED; constant decrement : NATURAL := 1) return UNSIGNED; - function dec(value : SIGNED; constant decrement : NATURAL := 1) return SIGNED; - - -- negate - function neg(value : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; -- calculate 2's complement + function fftre(q : std_logic; t : std_logic; rst : std_logic := '0'; en : std_logic := '1'; constant INIT : std_logic := '0') return std_logic; -- T-FlipFlop with reset and enable + function fftse(q : std_logic; t : std_logic; set : std_logic := '0'; en : std_logic := '1') return std_logic; -- T-FlipFlop with set and enable -- counter - function upcounter_next(cnt : UNSIGNED; rst : STD_LOGIC := '0'; en : STD_LOGIC := '1'; constant INIT : NATURAL := 0) return UNSIGNED; - function upcounter_equal(cnt : UNSIGNED; value : NATURAL) return STD_LOGIC; - function downcounter_next(cnt : SIGNED; rst : STD_LOGIC := '0'; en : STD_LOGIC := '1'; constant INIT : INTEGER := 0) return SIGNED; - function downcounter_equal(cnt : SIGNED; value : INTEGER) return STD_LOGIC; - function downcounter_neg(cnt : SIGNED) return STD_LOGIC; + function upcounter_next(cnt : unsigned; rst : std_logic := '0'; en : std_logic := '1'; constant INIT : natural := 0) return unsigned; + function upcounter_equal(cnt : unsigned; value : natural) return std_logic; + function downcounter_next(cnt : signed; rst : std_logic := '0'; en : std_logic := '1'; constant INIT : integer := 0) return signed; + function downcounter_equal(cnt : signed; value : integer) return std_logic; + function downcounter_neg(cnt : signed) return std_logic; -- shiftregisters - function shreg_left(q : STD_LOGIC_VECTOR; i : STD_LOGIC; en : STD_LOGIC := '1') return STD_LOGIC_VECTOR; - function shreg_right(q : STD_LOGIC_VECTOR; i : STD_LOGIC; en : STD_LOGIC := '1') return STD_LOGIC_VECTOR; + function shreg_left(q : std_logic_vector; i : std_logic; en : std_logic := '1') return std_logic_vector; + function shreg_right(q : std_logic_vector; i : std_logic; en : std_logic := '1') return std_logic_vector; -- rotate registers - function rreg_left(q : STD_LOGIC_VECTOR; en : STD_LOGIC := '1') return STD_LOGIC_VECTOR; - function rreg_right(q : STD_LOGIC_VECTOR; en : STD_LOGIC := '1') return STD_LOGIC_VECTOR; + function rreg_left(q : std_logic_vector; en : std_logic := '1') return std_logic_vector; + function rreg_right(q : std_logic_vector; en : std_logic := '1') return std_logic_vector; -- compare - function comp(value1 : STD_LOGIC_VECTOR; value2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; - function comp(value1 : UNSIGNED; value2 : UNSIGNED) return UNSIGNED; - function comp(value1 : SIGNED; value2 : SIGNED) return SIGNED; - function comp_allzero(value : STD_LOGIC_VECTOR) return STD_LOGIC; - function comp_allzero(value : UNSIGNED) return STD_LOGIC; - function comp_allzero(value : SIGNED) return STD_LOGIC; - function comp_allone(value : STD_LOGIC_VECTOR) return STD_LOGIC; - function comp_allone(value : UNSIGNED) return STD_LOGIC; - function comp_allone(value : SIGNED) return STD_LOGIC; + function comp(value1 : std_logic_vector; value2 : std_logic_vector) return std_logic_vector; + function comp(value1 : unsigned; value2 : unsigned) return unsigned; + function comp(value1 : signed; value2 : signed) return signed; + function comp_allzero(value : std_logic_vector) return std_logic; + function comp_allzero(value : unsigned) return std_logic; + function comp_allzero(value : signed) return std_logic; + function comp_allone(value : std_logic_vector) return std_logic; + function comp_allone(value : unsigned) return std_logic; + function comp_allone(value : signed) return std_logic; -- multiplexing - function mux(sel : STD_LOGIC; sl0 : STD_LOGIC; sl1 : STD_LOGIC) return STD_LOGIC; - function mux(sel : STD_LOGIC; slv0 : STD_LOGIC_VECTOR; slv1 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; - function mux(sel : STD_LOGIC; us0 : UNSIGNED; us1 : UNSIGNED) return UNSIGNED; - function mux(sel : STD_LOGIC; s0 : SIGNED; s1 : SIGNED) return SIGNED; + function mux(sel : std_logic; sl0 : std_logic; sl1 : std_logic) return std_logic; + function mux(sel : std_logic; slv0 : std_logic_vector; slv1 : std_logic_vector) return std_logic_vector; + function mux(sel : std_logic; us0 : unsigned; us1 : unsigned) return unsigned; + function mux(sel : std_logic; s0 : signed; s1 : signed) return signed; end package; package body components is -- implement an optional register stage -- =========================================================================== - function registered(signal Clock : STD_LOGIC; constant IsRegistered : BOOLEAN) return BOOLEAN is + function registered(signal Clock : std_logic; constant IsRegistered : boolean) return boolean is begin return ite(IsRegistered, rising_edge(Clock), TRUE); end function; @@ -115,9 +103,9 @@ package body components is -- FlipFlops -- =========================================================================== -- D-flipflop with reset and enable - function ffdre(q : STD_LOGIC; d : STD_LOGIC; rst : STD_LOGIC := '0'; en : STD_LOGIC := '1'; constant INIT : STD_LOGIC := '0') return STD_LOGIC is + function ffdre(q : std_logic; d : std_logic; rst : std_logic := '0'; en : std_logic := '1'; constant INIT : std_logic := '0') return std_logic is begin - if (SIMULATION = FALSE) then + if not SIMULATION then if (INIT = '0') then return ((d and en) or (q and not en)) and not rst; elsif (INIT = '1') then @@ -132,9 +120,9 @@ package body components is end if; end function; - function ffdre(q : STD_LOGIC_VECTOR; d : STD_LOGIC_VECTOR; rst : STD_LOGIC := '0'; en : STD_LOGIC := '1'; constant INIT : STD_LOGIC_VECTOR := (7 downto 0 => '0')) return STD_LOGIC_VECTOR is - constant INIT_I : STD_LOGIC_VECTOR(q'range) := resize(INIT, q'length); - variable Result : STD_LOGIC_VECTOR(q'range); + function ffdre(q : std_logic_vector; d : std_logic_vector; rst : std_logic := '0'; en : std_logic := '1'; constant INIT : std_logic_vector := (7 downto 0 => '0')) return std_logic_vector is + constant INIT_I : std_logic_vector(q'range) := resize(INIT, q'length); + variable Result : std_logic_vector(q'range); begin for i in q'range loop Result(i) := ffdre(q => q(i), d => d(i), rst => rst, en => en, INIT => INIT_I(i)); @@ -143,15 +131,15 @@ package body components is end function; -- D-flipflop with set and enable - function ffdse(q : STD_LOGIC; d : STD_LOGIC; set : STD_LOGIC := '0'; en : STD_LOGIC := '1') return STD_LOGIC is + function ffdse(q : std_logic; d : std_logic; set : std_logic := '0'; en : std_logic := '1') return std_logic is begin return ffdre(q => q, d => d, rst => set, en => en, INIT => '1'); end function; -- T-flipflop with reset and enable - function fftre(q : STD_LOGIC; t : STD_LOGIC; rst : STD_LOGIC := '0'; en : STD_LOGIC := '1'; constant INIT : STD_LOGIC := '0') return STD_LOGIC is + function fftre(q : std_logic; t : std_logic; rst : std_logic := '0'; en : std_logic := '1'; constant INIT : std_logic := '0') return std_logic is begin - if (SIMULATION = FALSE) then + if not SIMULATION then if (INIT = '0') then return ((not q and (t and en)) or (q and not (t and en))) and not rst; elsif (INIT = '1') then @@ -167,67 +155,28 @@ package body components is end function; -- T-flipflop with set and enable - function fftse(q : STD_LOGIC; t : STD_LOGIC; set : STD_LOGIC := '0'; en : STD_LOGIC := '1') return STD_LOGIC is + function fftse(q : std_logic; t : std_logic; set : std_logic := '0'; en : std_logic := '1') return std_logic is begin return fftre(q => q, t => t, rst => set, en => en, INIT => '1'); end function; -- RS-flipflop with dominant rst - function ffrs(q : STD_LOGIC; rst : STD_LOGIC := '0'; set : STD_LOGIC := '0') return STD_LOGIC is + function ffrs(q : std_logic; rst : std_logic := '0'; set : std_logic := '0') return std_logic is begin return (q or set) and not rst; end function; -- RS-flipflop with dominant set - function ffsr(q : STD_LOGIC; rst : STD_LOGIC := '0'; set : STD_LOGIC := '0') return STD_LOGIC is + function ffsr(q : std_logic; rst : std_logic := '0'; set : std_logic := '0') return std_logic is begin return (q and not rst) or set; end function; - -- Adder - -- =========================================================================== - function inc(value : STD_LOGIC_VECTOR; constant increment : NATURAL := 1) return STD_LOGIC_VECTOR is - begin - report "Incrementing a STD_LOGIC_VECTOR - implicit conversion to UNSIGNED" severity WARNING; - return std_logic_vector(inc(unsigned(value), increment)); - end function; - - function inc(value : UNSIGNED; constant increment : NATURAL := 1) return UNSIGNED is - begin - return value + increment; - end function; - - function inc(value : SIGNED; constant increment : NATURAL := 1) return SIGNED is - begin - return value + increment; - end function; - - function dec(value : STD_LOGIC_VECTOR; constant decrement : NATURAL := 1) return STD_LOGIC_VECTOR is - begin - report "Decrementing a STD_LOGIC_VECTOR - implicit conversion to UNSIGNED" severity WARNING; - return std_logic_vector(dec(unsigned(value), decrement)); - end function; - - function dec(value : UNSIGNED; constant decrement : NATURAL := 1) return UNSIGNED is - begin - return value - decrement; - end function; - - function dec(value : SIGNED; constant decrement : NATURAL := 1) return SIGNED is - begin - return value - decrement; - end function; - - -- negate - function neg(value : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is - begin - return std_logic_vector(inc(unsigned(not value))); -- 2's complement - end function; -- Counters -- =========================================================================== -- up-counter - function upcounter_next(cnt : UNSIGNED; rst : STD_LOGIC := '0'; en : STD_LOGIC := '1'; constant INIT : NATURAL := 0) return UNSIGNED is + function upcounter_next(cnt : unsigned; rst : std_logic := '0'; en : std_logic := '1'; constant INIT : natural := 0) return unsigned is begin if (rst = '1') then return to_unsigned(INIT, cnt'length); @@ -238,14 +187,14 @@ package body components is end if; end function; - function upcounter_equal(cnt : UNSIGNED; value : NATURAL) return STD_LOGIC is + function upcounter_equal(cnt : unsigned; value : natural) return std_logic is begin -- optimized comparison for only up counting values return to_sl((cnt and to_unsigned(value, cnt'length)) = value); end function; -- down-counter - function downcounter_next(cnt : SIGNED; rst : STD_LOGIC := '0'; en : STD_LOGIC := '1'; constant INIT : INTEGER := 0) return SIGNED is + function downcounter_next(cnt : signed; rst : std_logic := '0'; en : std_logic := '1'; constant INIT : integer := 0) return signed is begin if (rst = '1') then return to_signed(INIT, cnt'length); @@ -256,35 +205,35 @@ package body components is end if; end function; - function downcounter_equal(cnt : SIGNED; value : INTEGER) return STD_LOGIC is + function downcounter_equal(cnt : signed; value : integer) return std_logic is begin -- optimized comparison for only down counting values return to_sl((cnt nor to_signed(value, cnt'length)) /= value); end function; - function downcounter_neg(cnt : SIGNED) return STD_LOGIC is + function downcounter_neg(cnt : signed) return std_logic is begin return cnt(cnt'high); end function; -- Shift/Rotate Registers -- =========================================================================== - function shreg_left(q : STD_LOGIC_VECTOR; i : std_logic; en : STD_LOGIC := '1') return STD_LOGIC_VECTOR is + function shreg_left(q : std_logic_vector; i : std_logic; en : std_logic := '1') return std_logic_vector is begin return mux(en, q, q(q'left - 1 downto q'right) & i); end function; - function shreg_right(q : STD_LOGIC_VECTOR; i : std_logic; en : STD_LOGIC := '1') return STD_LOGIC_VECTOR is + function shreg_right(q : std_logic_vector; i : std_logic; en : std_logic := '1') return std_logic_vector is begin return mux(en, q, i & q(q'left downto q'right - 1)); end function; - function rreg_left(q : STD_LOGIC_VECTOR; en : STD_LOGIC := '1') return STD_LOGIC_VECTOR is + function rreg_left(q : std_logic_vector; en : std_logic := '1') return std_logic_vector is begin return mux(en, q, q(q'left - 1 downto q'right) & q(q'left)); end function; - function rreg_right(q : STD_LOGIC_VECTOR; en : STD_LOGIC := '1') return STD_LOGIC_VECTOR is + function rreg_right(q : std_logic_vector; en : std_logic := '1') return std_logic_vector is begin return mux(en, q, q(q'right) & q(q'left downto q'right - 1)); end function; @@ -295,82 +244,82 @@ package body components is -- 1- => value1 < value2 (difference is negative) -- 00 => value1 = value2 (difference is zero) -- -1 => value1 > value2 (difference is positive) - function comp(value1 : STD_LOGIC_VECTOR; value2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is + function comp(value1 : std_logic_vector; value2 : std_logic_vector) return std_logic_vector is begin report "Comparing two STD_LOGIC_VECTORs - implicit conversion to UNSIGNED" severity WARNING; return std_logic_vector(comp(unsigned(value1), unsigned(value2))); end function; - function comp(value1 : UNSIGNED; value2 : UNSIGNED) return UNSIGNED is + function comp(value1 : unsigned; value2 : unsigned) return unsigned is begin - if (value1 < value2) then + if value1 < value2 then return "10"; - elsif (value1 = value2) then + elsif value1 = value2 then return "00"; else return "01"; end if; end function; - function comp(value1 : SIGNED; value2 : SIGNED) return SIGNED is + function comp(value1 : signed; value2 : signed) return signed is begin - if (value1 < value2) then + if value1 < value2 then return "10"; - elsif (value1 = value2) then + elsif value1 = value2 then return "00"; else return "01"; end if; end function; - function comp_allzero(value : STD_LOGIC_VECTOR) return STD_LOGIC is + function comp_allzero(value : std_logic_vector) return std_logic is begin return comp_allzero(unsigned(value)); end function; - function comp_allzero(value : UNSIGNED) return STD_LOGIC is + function comp_allzero(value : unsigned) return std_logic is begin return to_sl(value = (value'range => '0')); end function; - function comp_allzero(value : SIGNED) return STD_LOGIC is + function comp_allzero(value : signed) return std_logic is begin return to_sl(value = (value'range => '0')); end function; - function comp_allone(value : STD_LOGIC_VECTOR) return STD_LOGIC is + function comp_allone(value : std_logic_vector) return std_logic is begin return comp_allone(unsigned(value)); end function; - function comp_allone(value : UNSIGNED) return STD_LOGIC is + function comp_allone(value : unsigned) return std_logic is begin return to_sl(value = (value'range => '1')); end function; - function comp_allone(value : SIGNED) return STD_LOGIC is + function comp_allone(value : signed) return std_logic is begin return to_sl(value = (value'range => '1')); end function; -- multiplexers - function mux(sel : STD_LOGIC; sl0 : STD_LOGIC; sl1 : STD_LOGIC) return STD_LOGIC is + function mux(sel : std_logic; sl0 : std_logic; sl1 : std_logic) return std_logic is begin return (sl0 and not sel) or (sl1 and sel); end function; - function mux(sel : STD_LOGIC; slv0 : STD_LOGIC_VECTOR; slv1 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is + function mux(sel : std_logic; slv0 : std_logic_vector; slv1 : std_logic_vector) return std_logic_vector is begin return (slv0 and not (slv0'range => sel)) or (slv1 and (slv1'range => sel)); end function; - function mux(sel : STD_LOGIC; us0 : UNSIGNED; us1 : UNSIGNED) return UNSIGNED is + function mux(sel : std_logic; us0 : unsigned; us1 : unsigned) return unsigned is begin return (us0 and not (us0'range => sel)) or (us1 and (us1'range => sel)); end function; - function mux(sel : STD_LOGIC; s0 : SIGNED; s1 : SIGNED) return SIGNED is + function mux(sel : std_logic; s0 : signed; s1 : signed) return signed is begin return (s0 and not (s0'range => sel)) or (s1 and (s1'range => sel)); end function; diff --git a/src/common/config.vhdl b/src/common/config.vhdl index 219cfa3c..8d84f7d3 100644 --- a/src/common/config.vhdl +++ b/src/common/config.vhdl @@ -1,8 +1,7 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Thomas B. Preusser -- Martin Zabel -- Patrick Lehmann @@ -10,12 +9,12 @@ -- Package: Global configuration settings. -- -- Description: --- ------------------------------------ +-- ------------------------------------- -- This file evaluates the settings declared in the project specific package my_config. -- See also template file my_config.vhdl.template. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -30,7 +29,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.std_logic_1164.all; @@ -42,13 +41,13 @@ use PoC.utils.all; package config_private is -- TODO: -- =========================================================================== - subtype T_BOARD_STRING is STRING(1 to 16); - subtype T_BOARD_CONFIG_STRING is STRING(1 to 64); - subtype T_DEVICE_STRING is STRING(1 to 32); + subtype T_BOARD_STRING is string(1 to 16); + subtype T_BOARD_CONFIG_STRING is string(1 to 64); + subtype T_DEVICE_STRING is string(1 to 32); -- Data structures to describe UART / RS232 type T_BOARD_UART_DESC is record - IsDTE : BOOLEAN; -- Data terminal Equipment (e.g. PC, Printer) + IsDTE : boolean; -- Data terminal Equipment (e.g. PC, Printer) FlowControl : T_BOARD_CONFIG_STRING; -- (NONE, SW, HW_CTS_RTS, HW_RTR_RTS) BaudRate : T_BOARD_CONFIG_STRING; -- e.g. "115.2 kBd" BaudRate_Max : T_BOARD_CONFIG_STRING; @@ -59,13 +58,13 @@ package config_private is IPStyle : T_BOARD_CONFIG_STRING; RS_DataInterface : T_BOARD_CONFIG_STRING; PHY_Device : T_BOARD_CONFIG_STRING; - PHY_DeviceAddress : STD_LOGIC_VECTOR(7 downto 0); + PHY_DeviceAddress : std_logic_vector(7 downto 0); PHY_DataInterface : T_BOARD_CONFIG_STRING; PHY_ManagementInterface : T_BOARD_CONFIG_STRING; end record; - subtype T_BOARD_ETHERNET_DESC_INDEX is NATURAL range 0 to 7; - type T_BOARD_ETHERNET_DESC_VECTOR is array(NATURAL range <>) of T_BOARD_ETHERNET_DESC; + subtype T_BOARD_ETHERNET_DESC_INDEX is natural range 0 to 7; + type T_BOARD_ETHERNET_DESC_VECTOR is array(natural range <>) of T_BOARD_ETHERNET_DESC; -- Data structures to describe a board layout type T_BOARD_INFO is record @@ -78,29 +77,29 @@ package config_private is type T_BOARD_INFO_VECTOR is array (natural range <>) of T_BOARD_INFO; - constant C_POC_NUL : CHARACTER; + constant C_POC_NUL : character; constant C_BOARD_STRING_EMPTY : T_BOARD_STRING; constant C_BOARD_CONFIG_STRING_EMPTY : T_BOARD_CONFIG_STRING; constant C_DEVICE_STRING_EMPTY : T_DEVICE_STRING; - CONSTANT C_BOARD_INFO_LIST : T_BOARD_INFO_VECTOR; + constant C_BOARD_INFO_LIST : T_BOARD_INFO_VECTOR; function conf(str : string) return T_BOARD_CONFIG_STRING; end package; package body config_private is - constant C_POC_NUL : CHARACTER := '~'; + constant C_POC_NUL : character := '~'; constant C_BOARD_STRING_EMPTY : T_BOARD_STRING := (others => C_POC_NUL); constant C_BOARD_CONFIG_STRING_EMPTY : T_BOARD_CONFIG_STRING := (others => C_POC_NUL); constant C_DEVICE_STRING_EMPTY : T_DEVICE_STRING := (others => C_POC_NUL); function conf(str : string) return T_BOARD_CONFIG_STRING is - constant ConstNUL : STRING(1 to 1) := (others => C_POC_NUL); - variable Result : STRING(1 to T_BOARD_CONFIG_STRING'length); + constant ConstNUL : string(1 to 1) := (others => C_POC_NUL); + variable Result : string(1 to T_BOARD_CONFIG_STRING'length); begin Result := (others => C_POC_NUL); if (str'length > 0) then - Result(1 to imin(T_BOARD_CONFIG_STRING'length, imax(1, str'length))) := ite((str'length > 0), str(1 to imin(T_BOARD_CONFIG_STRING'length, str'length)), ConstNUL); + Result(1 to bound(T_BOARD_CONFIG_STRING'length, 1, str'length)) := ite((str'length > 0), str(1 to imin(T_BOARD_CONFIG_STRING'length, str'length)), ConstNUL); end if; return Result; end function; @@ -115,7 +114,7 @@ package body config_private is ); -- predefined UART descriptions - function brd_CreateUART(IsDTE : BOOLEAN; FlowControl : STRING; BaudRate : STRING; BaudRate_Max : STRING := "") return T_BOARD_UART_DESC is + function brd_CreateUART(IsDTE : boolean; FlowControl : string; BaudRate : string; BaudRate_Max : string := "") return T_BOARD_UART_DESC is variable Result : T_BOARD_UART_DESC; begin Result.IsDTE := IsDTE; @@ -133,7 +132,7 @@ package body config_private is constant C_BOARD_UART_DCE_460800_NONE : T_BOARD_UART_DESC := brd_CreateUART(FALSE, "NONE", "460.8 kBd"); constant C_BOARD_UART_DTE_921600_NONE : T_BOARD_UART_DESC := brd_CreateUART(FALSE, "NONE", "921.6 kBd"); - function brd_CreateEthernet(IPStyle : STRING; RS_DataInt : STRING; PHY_Device : STRING; PHY_DevAddress : STD_LOGIC_VECTOR(7 downto 0); PHY_DataInt : STRING; PHY_MgntInt : STRING) return T_BOARD_ETHERNET_DESC is + function brd_CreateEthernet(IPStyle : string; RS_DataInt : string; PHY_Device : string; PHY_DevAddress : std_logic_vector(7 downto 0); PHY_DataInt : string; PHY_MgntInt : string) return T_BOARD_ETHERNET_DESC is variable Result : T_BOARD_ETHERNET_DESC; begin Result.IPStyle := conf(IPStyle); @@ -155,7 +154,7 @@ package body config_private is -- Board Descriptions -- =========================================================================== - CONSTANT C_BOARD_INFO_LIST : T_BOARD_INFO_VECTOR := ( + constant C_BOARD_INFO_LIST : T_BOARD_INFO_VECTOR := ( ( BoardName => conf("GENERIC"), FPGADevice => conf("GENERIC"), -- GENERIC @@ -244,10 +243,24 @@ package body config_private is EthernetCount => 1 ),( BoardName => conf("ZC706"), - FPGADevice => conf("XC7Z045-2FFG900"), -- XC7K325T-2FFG900C + FPGADevice => conf("XC7Z045-2FFG900"), -- XC7Z045-2FFG900C UART => C_BOARD_UART_DTE_921600_NONE, Ethernet => C_BOARD_ETH_NONE, EthernetCount => 0 + ),( + BoardName => conf("ZedBoard"), + FPGADevice => conf("XC7Z020-1CLG484"), -- XC7Z020-1CLG484 + UART => C_BOARD_UART_DTE_921600_NONE, + Ethernet => C_BOARD_ETH_NONE, + EthernetCount => 0 + ),( + BoardName => conf("AC701"), + FPGADevice => conf("XC7A200T-2FBG676C"), -- XC7A200T-2FBG676C + UART => C_BOARD_UART_DTE_921600_NONE, + Ethernet => ( + 0 => C_BOARD_ETH_SOFT_GMII_88E1111, + others => C_BOARD_ETH_EMPTY), + EthernetCount => 1 ),( BoardName => conf("KC705"), FPGADevice => conf("XC7K325T-2FFG900C"), -- XC7K325T-2FFG900C @@ -310,12 +323,6 @@ package body config_private is UART => C_BOARD_UART_DTE_921600_NONE, Ethernet => C_BOARD_ETH_NONE, EthernetCount => 0 - ),( - BoardName => conf("ZEDBOARD"), - FPGADevice => conf("XC7Z020-1CLG484"), -- XC7Z020-1CLG484 - UART => C_BOARD_UART_EMPTY, - Ethernet => C_BOARD_ETH_NONE, - EthernetCount => 0 ), -- Custom Board (MUST BE LAST ONE) -- ========================================================================= @@ -344,6 +351,7 @@ use PoC.utils.all; package config is constant PROJECT_DIR : string := MY_PROJECT_DIR; constant OPERATING_SYSTEM : string := MY_OPERATING_SYSTEM; + constant POC_VERBOSE : boolean := MY_VERBOSE; -- List of known FPGA / Chip vendors -- --------------------------------------------------------------------------- @@ -418,7 +426,7 @@ package config is DEVICE_ZYNQ7, DEVICE_ZYNQ_ULTRA_PLUS, -- Xilinx.Zynq DEVICE_ARTIX7, -- Xilinx.Artix DEVICE_KINTEX7, DEVICE_KINTEX_ULTRA, DEVICE_KINTEX_ULTRA_PLUS, -- Xilinx.Kintex - DEVICE_VIRTEX5, DEVICE_VIRTEX6, DEVICE_VIRTEX7, -- Xilinx.Virtex + DEVICE_VIRTEX4, DEVICE_VIRTEX5, DEVICE_VIRTEX6, DEVICE_VIRTEX7, -- Xilinx.Virtex DEVICE_VIRTEX_ULTRA, DEVICE_VIRTEX_ULTRA_PLUS -- ); @@ -473,23 +481,23 @@ package config is Vendor : T_VENDOR; Device : T_DEVICE; DevFamily : T_DEVICE_FAMILY; - DevGeneration : NATURAL; - DevNumber : NATURAL; + DevGeneration : natural; + DevNumber : natural; DevSubType : T_DEVICE_SUBTYPE; DevSeries : T_DEVICE_SERIES; TransceiverType : T_TRANSCEIVER; - LUT_FanIn : POSITIVE; + LUT_FanIn : positive; end record; -- Functions extracting board and PCB properties from "MY_BOARD" -- which is declared in package "my_config". -- =========================================================================== - function BOARD(BoardConfig : string := C_BOARD_STRING_EMPTY) return NATURAL; - function BOARD_INFO(BoardConfig : STRING := C_BOARD_STRING_EMPTY) return T_BOARD_INFO; - function BOARD_NAME(BoardConfig : STRING := C_BOARD_STRING_EMPTY) return STRING; - function BOARD_DEVICE(BoardConfig : STRING := C_BOARD_STRING_EMPTY) return STRING; - function BOARD_UART_BAUDRATE(BoardConfig : STRING := C_BOARD_STRING_EMPTY) return STRING; + function BOARD(BoardConfig : string := C_BOARD_STRING_EMPTY) return natural; + function BOARD_INFO(BoardConfig : string := C_BOARD_STRING_EMPTY) return T_BOARD_INFO; + function BOARD_NAME(BoardConfig : string := C_BOARD_STRING_EMPTY) return string; + function BOARD_DEVICE(BoardConfig : string := C_BOARD_STRING_EMPTY) return string; + function BOARD_UART_BAUDRATE(BoardConfig : string := C_BOARD_STRING_EMPTY) return string; -- Functions extracting device and architecture properties from "MY_DEVICE" -- which is declared in package "my_config". @@ -500,62 +508,67 @@ package config is function DEVICE_FAMILY(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_FAMILY; function DEVICE_SUBTYPE(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_SUBTYPE; function DEVICE_SERIES(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_SERIES; - function DEVICE_GENERATION(DeviceString : string := C_DEVICE_STRING_EMPTY) return NATURAL; - function DEVICE_NUMBER(DeviceString : string := C_DEVICE_STRING_EMPTY) return NATURAL; + function DEVICE_GENERATION(DeviceString : string := C_DEVICE_STRING_EMPTY) return natural; + function DEVICE_NUMBER(DeviceString : string := C_DEVICE_STRING_EMPTY) return natural; function TRANSCEIVER_TYPE(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_TRANSCEIVER; - function LUT_FANIN(DeviceString : string := C_DEVICE_STRING_EMPTY) return POSITIVE; + function LUT_FANIN(DeviceString : string := C_DEVICE_STRING_EMPTY) return positive; function DEVICE_INFO(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_INFO; + -- Convert T_DEVICE to string representation as required by "altera_mf" library + -- =========================================================================== + function getAlteraDeviceName (device : T_DEVICE) return string; + -- force FSM to predefined encoding in debug mode - function getFSMEncoding_gray(debug : BOOLEAN) return STRING; + -- =========================================================================== + function getFSMEncoding_gray(debug : boolean) return string; end package; package body config is -- inlined function from PoC.utils, to break dependency -- =========================================================================== - function ite(cond : BOOLEAN; value1 : STRING; value2 : STRING) return STRING is begin + function ite(cond : boolean; value1 : string; value2 : string) return string is begin if cond then return value1; else return value2; end if; end function; -- chr_is* function - function chr_isDigit(chr : CHARACTER) return boolean is + function chr_isDigit(chr : character) return boolean is begin - return ((CHARACTER'pos('0') <= CHARACTER'pos(chr)) and (CHARACTER'pos(chr) <= CHARACTER'pos('9'))); + return ((character'pos('0') <= CHARACTER'pos(chr)) and (character'pos(chr) <= CHARACTER'pos('9'))); end function; function chr_isAlpha(chr : character) return boolean is begin - return (((CHARACTER'pos('a') <= CHARACTER'pos(chr)) and (CHARACTER'pos(chr) <= CHARACTER'pos('z'))) or - ((CHARACTER'pos('A') <= CHARACTER'pos(chr)) and (CHARACTER'pos(chr) <= CHARACTER'pos('Z')))); + return (((character'pos('a') <= CHARACTER'pos(chr)) and (character'pos(chr) <= CHARACTER'pos('z'))) or + ((character'pos('A') <= CHARACTER'pos(chr)) and (character'pos(chr) <= CHARACTER'pos('Z')))); end function; - function str_length(str : STRING) return NATURAL is + function str_length(str : string) return natural is begin for i in str'range loop - if (str(i) = C_POC_NUL) then + if str(i) = C_POC_NUL then return i - str'low; end if; end loop; return str'length; end function; - function str_trim(str : STRING) return STRING is + function str_trim(str : string) return string is begin for i in str'range loop - if (str(i) = C_POC_NUL) then + if str(i) = C_POC_NUL then return str(str'low to i-1); end if; end loop; return str; end function; - function str_imatch(str1 : STRING; str2 : STRING) return BOOLEAN is - constant len : NATURAL := imin(str1'length, str2'length); - variable chr1 : CHARACTER; - variable chr2 : CHARACTER; + function str_imatch(str1 : string; str2 : string) return boolean is + constant len : natural := imin(str1'length, str2'length); + variable chr1 : character; + variable chr2 : character; begin -- if both strings are empty if ((str1'length = 0 ) and (str2'length = 0)) then return TRUE; end if; @@ -563,17 +576,17 @@ package body config is for i in 0 to len-1 loop chr1 := str1(str1'low + i); chr2 := str2(str2'low + i); - if (CHARACTER'pos('A') <= CHARACTER'pos(chr1)) and (CHARACTER'pos(chr1) <= CHARACTER'pos('Z')) then - chr1 := CHARACTER'val(CHARACTER'pos(chr1) - CHARACTER'pos('A') + CHARACTER'pos('a')); + if (character'pos('A') <= CHARACTER'pos(chr1)) and (character'pos(chr1) <= CHARACTER'pos('Z')) then + chr1 := character'val(CHARACTER'pos(chr1) - character'pos('A') + CHARACTER'pos('a')); end if; - if (CHARACTER'pos('A') <= CHARACTER'pos(chr2)) and (CHARACTER'pos(chr2) <= CHARACTER'pos('Z')) then - chr2 := CHARACTER'val(CHARACTER'pos(chr2) - CHARACTER'pos('A') + CHARACTER'pos('a')); + if (character'pos('A') <= CHARACTER'pos(chr2)) and (character'pos(chr2) <= CHARACTER'pos('Z')) then + chr2 := character'val(CHARACTER'pos(chr2) - character'pos('A') + CHARACTER'pos('a')); end if; - if (chr1 /= chr2) then + if chr1 /= chr2 then return FALSE; - elsif ((chr1 = C_POC_NUL) xor (chr2 = C_POC_NUL)) then + elsif (chr1 = C_POC_NUL) xor (chr2 = C_POC_NUL) then return FALSE; - elsif ((chr1 = C_POC_NUL) and (chr2 = C_POC_NUL)) then + elsif (chr1 = C_POC_NUL) and (chr2 = C_POC_NUL) then return TRUE; end if; end loop; @@ -587,7 +600,7 @@ package body config is end if; end function; - function str_find(str : STRING; pattern : STRING; start : NATURAL := 0) return BOOLEAN is + function str_find(str : string; pattern : string; start : natural := 0) return boolean is begin for i in imax(str'low, start) to (str'high - pattern'length + 1) loop exit when (str(i) = C_POC_NUL); @@ -601,34 +614,34 @@ package body config is -- private functions required by board description -- ModelSim requires that this functions is defined before it is used below. -- =========================================================================== - function getLocalDeviceString(DeviceString : STRING) return STRING is - constant ConstNUL : STRING(1 to 1) := (others => C_POC_NUL); - constant MY_DEVICE_STR : STRING := BOARD_DEVICE; - variable Result : STRING(1 to T_DEVICE_STRING'length); + function getLocalDeviceString(DeviceString : string) return string is + constant ConstNUL : string(1 to 1) := (others => C_POC_NUL); + constant MY_DEVICE_STR : string := BOARD_DEVICE; + variable Result : string(1 to T_DEVICE_STRING'length); begin Result := (others => C_POC_NUL); -- report DeviceString for debugging - if (POC_VERBOSE = TRUE) then + if POC_VERBOSE then report "getLocalDeviceString: DeviceString='" & str_trim(DeviceString) & "' MY_DEVICE='" & str_trim(MY_DEVICE) & "' MY_DEVICE_STR='" & str_trim(MY_DEVICE_STR) & "'" severity NOTE; end if; -- if DeviceString is populated - if ((str_length(DeviceString) /= 0) and (str_imatch(DeviceString, "None") = FALSE)) then - Result(1 to imin(T_DEVICE_STRING'length, imax(1, DeviceString'length))) := ite((DeviceString'length > 0), DeviceString(1 to imin(T_DEVICE_STRING'length, DeviceString'length)), ConstNUL); + if (str_length(DeviceString) /= 0) and not str_imatch(DeviceString, "None") then + Result(1 to bound(T_DEVICE_STRING'length, 1, DeviceString'length)) := ite((DeviceString'length > 0), DeviceString(1 to imin(T_DEVICE_STRING'length, DeviceString'length)), ConstNUL); -- if MY_DEVICE is set, prefer it - elsif ((str_length(MY_DEVICE) /= 0) and (str_imatch(MY_DEVICE, "None") = FALSE)) then - Result(1 to imin(T_DEVICE_STRING'length, imax(1, MY_DEVICE'length))) := ite((MY_DEVICE'length > 0), MY_DEVICE(1 to imin(T_DEVICE_STRING'length, MY_DEVICE'length)), ConstNUL); + elsif (str_length(MY_DEVICE) /= 0) and not str_imatch(MY_DEVICE, "None") then + Result(1 to bound(T_DEVICE_STRING'length, 1, MY_DEVICE'length)) := ite((MY_DEVICE'length > 0), MY_DEVICE(1 to imin(T_DEVICE_STRING'length, MY_DEVICE'length)), ConstNUL); -- otherwise use MY_BOARD else - Result(1 to imin(T_DEVICE_STRING'length, imax(1, MY_DEVICE_STR'length))) := ite((MY_DEVICE_STR'length > 0), MY_DEVICE_STR(1 to imin(T_DEVICE_STRING'length, MY_DEVICE_STR'length)), ConstNUL); + Result(1 to bound(T_DEVICE_STRING'length, 1, MY_DEVICE_STR'length)) := ite((MY_DEVICE_STR'length > 0), MY_DEVICE_STR(1 to imin(T_DEVICE_STRING'length, MY_DEVICE_STR'length)), ConstNUL); end if; return Result; end function; - function extractFirstNumber(str : STRING) return NATURAL is + function extractFirstNumber(str : string) return natural is variable low : integer; variable high : integer; - variable Result : NATURAL; - variable Digit : INTEGER; + variable Result : natural; + variable Digit : integer; begin low := -1; high := -1; @@ -639,7 +652,7 @@ package body config is end if; end loop; -- abort if no digit can be found - if (low = -1) then return 0; end if; + if low = -1 then return 0; end if; for i in (low + 1) to str'high loop if chr_isAlpha(str(i)) then @@ -648,12 +661,12 @@ package body config is end if; end loop; - if (high = -1) then return 0; end if; + if high = -1 then return 0; end if; -- return INTEGER'value(str(low to high)); -- 'value(...) is not supported by Vivado Synth 2014.1 -- convert substring to a number for i in low to high loop - if (chr_isDigit(str(i)) = FALSE) then + if not chr_isDigit(str(i)) then return 0; end if; Result := (Result * 10) + (character'pos(str(i)) - character'pos('0')); @@ -664,11 +677,11 @@ package body config is -- Public functions -- =========================================================================== -- TODO: comment - function BOARD(BoardConfig : string := C_BOARD_STRING_EMPTY) return NATURAL is + function BOARD(BoardConfig : string := C_BOARD_STRING_EMPTY) return natural is constant MY_BRD : T_BOARD_CONFIG_STRING := ite((BoardConfig /= C_BOARD_STRING_EMPTY), conf(BoardConfig), conf(MY_BOARD)); - constant BOARD_NAME : STRING := str_trim(MY_BRD); + constant BOARD_NAME : string := str_trim(MY_BRD); begin - if (POC_VERBOSE = TRUE) then report "PoC configuration: Used board is '" & BOARD_NAME & "'" severity NOTE; end if; + if POC_VERBOSE then report "PoC configuration: Used board is '" & BOARD_NAME & "'" severity NOTE; end if; for i in C_BOARD_INFO_LIST'range loop if str_imatch(BOARD_NAME, C_BOARD_INFO_LIST(i).BoardName) then return i; @@ -679,28 +692,28 @@ package body config is return C_BOARD_INFO_LIST'high; end function; - function BOARD_INFO(BoardConfig : STRING := C_BOARD_STRING_EMPTY) return T_BOARD_INFO is - constant BRD : NATURAL := BOARD(BoardConfig); + function BOARD_INFO(BoardConfig : string := C_BOARD_STRING_EMPTY) return T_BOARD_INFO is + constant BRD : natural := BOARD(BoardConfig); begin return C_BOARD_INFO_LIST(BRD); end function; -- TODO: comment - function BOARD_NAME(BoardConfig : STRING := C_BOARD_STRING_EMPTY) return STRING is - constant BRD : NATURAL := BOARD(BoardConfig); + function BOARD_NAME(BoardConfig : string := C_BOARD_STRING_EMPTY) return string is + constant BRD : natural := BOARD(BoardConfig); begin return str_trim(C_BOARD_INFO_LIST(BRD).BoardName); end function; -- TODO: comment - function BOARD_DEVICE(BoardConfig : STRING := C_BOARD_STRING_EMPTY) return STRING is - constant BRD : NATURAL := BOARD(BoardConfig); + function BOARD_DEVICE(BoardConfig : string := C_BOARD_STRING_EMPTY) return string is + constant BRD : natural := BOARD(BoardConfig); begin return str_trim(C_BOARD_INFO_LIST(BRD).FPGADevice); end function; - function BOARD_UART_BAUDRATE(BoardConfig : STRING := C_BOARD_STRING_EMPTY) return STRING is - constant BRD : NATURAL := BOARD(BoardConfig); + function BOARD_UART_BAUDRATE(BoardConfig : string := C_BOARD_STRING_EMPTY) return string is + constant BRD : natural := BOARD(BoardConfig); begin return str_trim(C_BOARD_INFO_LIST(BRD).UART.BaudRate); end function; @@ -790,6 +803,7 @@ package body config is when "KU" => return DEVICE_KINTEX_ULTRA; when "3S" => return DEVICE_SPARTAN3; when "6S" => return DEVICE_SPARTAN6; + when "4V" => return DEVICE_VIRTEX4; when "5V" => return DEVICE_VIRTEX5; when "6V" => return DEVICE_VIRTEX6; when "7V" => return DEVICE_VIRTEX7; @@ -863,10 +877,10 @@ package body config is end case; end function; - function DEVICE_GENERATION(DeviceString : string := C_DEVICE_STRING_EMPTY) return NATURAL is + function DEVICE_GENERATION(DeviceString : string := C_DEVICE_STRING_EMPTY) return natural is constant SERIES : T_DEVICE_SERIES := DEVICE_SERIES(DeviceString); begin - if (SERIES = DEVICE_SERIES_7_SERIES) then + if SERIES = DEVICE_SERIES_7_SERIES then return 7; else return 0; @@ -915,14 +929,14 @@ package body config is DEVICE_CYCLONE5 => return DEVICE_SUBTYPE_NONE; when DEVICE_STRATIX2 => - if chr_isDigit(DEV_SUB_STR(1)) then return DEVICE_SUBTYPE_NONE; - elsif (DEV_SUB_STR = "GX") then return DEVICE_SUBTYPE_GX; + if chr_isDigit(DEV_SUB_STR(1)) then return DEVICE_SUBTYPE_NONE; + elsif DEV_SUB_STR = "GX" then return DEVICE_SUBTYPE_GX; else report "Unknown Stratix II subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure; end if; when DEVICE_STRATIX4 => if (DEV_SUB_STR(1) = 'E') then return DEVICE_SUBTYPE_E; - elsif (DEV_SUB_STR = "GX") then return DEVICE_SUBTYPE_GX; + elsif DEV_SUB_STR = "GX" then return DEVICE_SUBTYPE_GX; -- elsif (DEV_SUB_STR = "GT") then return DEVICE_SUBTYPE_GT; else report "Unknown Stratix IV subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure; end if; @@ -934,7 +948,7 @@ package body config is when DEVICE_ECP5 => if (DEV_SUB_STR(1) = 'U') then return DEVICE_SUBTYPE_U; - elsif (DEV_SUB_STR = "UM") then return DEVICE_SUBTYPE_UM; + elsif DEV_SUB_STR = "UM" then return DEVICE_SUBTYPE_UM; else report "Unknown Lattice ECP5 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure; end if; @@ -943,36 +957,39 @@ package body config is return DEVICE_SUBTYPE_NONE; when DEVICE_SPARTAN6 => - if ((DEV_SUB_STR = "LX") and (not str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LX; - elsif ((DEV_SUB_STR = "LX") and ( str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LXT; + if ((DEV_SUB_STR = "LX") and (not str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LX; + elsif ((DEV_SUB_STR = "LX") and ( str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LXT; else report "Unknown Virtex-5 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure; end if; + when DEVICE_VIRTEX4 => + report "Unkown Virtex 4" severity failure; + when DEVICE_VIRTEX5 => - if ((DEV_SUB_STR = "LX") and (not str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LX; - elsif ((DEV_SUB_STR = "LX") and ( str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LXT; - elsif ((DEV_SUB_STR = "SX") and ( str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_SXT; - elsif ((DEV_SUB_STR = "TX") and ( str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_TXT; - elsif ((DEV_SUB_STR = "FX") and ( str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_FXT; + if ((DEV_SUB_STR = "LX") and (not str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LX; + elsif ((DEV_SUB_STR = "LX") and ( str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LXT; + elsif ((DEV_SUB_STR = "SX") and ( str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_SXT; + elsif ((DEV_SUB_STR = "TX") and ( str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_TXT; + elsif ((DEV_SUB_STR = "FX") and ( str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_FXT; else report "Unknown Virtex-5 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure; end if; when DEVICE_VIRTEX6 => - if ((DEV_SUB_STR = "LX") and (not str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LX; - elsif ((DEV_SUB_STR = "LX") and ( str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LXT; - elsif ((DEV_SUB_STR = "SX") and ( str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_SXT; - elsif ((DEV_SUB_STR = "CX") and ( str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_CXT; - elsif ((DEV_SUB_STR = "HX") and ( str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_HXT; + if ((DEV_SUB_STR = "LX") and (not str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LX; + elsif ((DEV_SUB_STR = "LX") and ( str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LXT; + elsif ((DEV_SUB_STR = "SX") and ( str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_SXT; + elsif ((DEV_SUB_STR = "CX") and ( str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_CXT; + elsif ((DEV_SUB_STR = "HX") and ( str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_HXT; else report "Unknown Virtex-6 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure; end if; when DEVICE_ARTIX7 => - if ( ( str_find(MY_DEV(5 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_T; + if ( ( str_find(MY_DEV(5 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_T; else report "Unknown Artix-7 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure; end if; when DEVICE_KINTEX7 => - if ( ( str_find(MY_DEV(5 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_T; + if ( ( str_find(MY_DEV(5 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_T; else report "Unknown Kintex-7 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure; end if; @@ -980,9 +997,9 @@ package body config is when DEVICE_KINTEX_ULTRA_PLUS => return DEVICE_SUBTYPE_NONE; when DEVICE_VIRTEX7 => - if ( ( str_find(MY_DEV(5 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_T; - elsif ((DEV_SUB_STR(1) = 'X') and ( str_find(MY_DEV(6 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_XT; - elsif ((DEV_SUB_STR(1) = 'H') and ( str_find(MY_DEV(6 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_HT; + if ( ( str_find(MY_DEV(5 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_T; + elsif ((DEV_SUB_STR(1) = 'X') and ( str_find(MY_DEV(6 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_XT; + elsif ((DEV_SUB_STR(1) = 'H') and ( str_find(MY_DEV(6 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_HT; else report "Unknown Virtex-7 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure; end if; @@ -1018,7 +1035,7 @@ package body config is when DEVICE_SPARTAN3 => return 4; when DEVICE_SPARTAN6 => return 6; - when DEVICE_VIRTEX5 | DEVICE_VIRTEX6 => return 6; + when DEVICE_VIRTEX4 | DEVICE_VIRTEX5 | DEVICE_VIRTEX6 => return 6; when others => report "LUT fan-in is unknown for the given device." severity failure; -- return statement is explicitly missing otherwise XST won't stop @@ -1050,6 +1067,9 @@ package body config is when others => report "Unknown Spartan-6 subtype: " & T_DEVICE_SUBTYPE'image(DEV_SUB) severity failure; end case; + when DEVICE_VIRTEX4 => + report "Unknown Virtex-4" severity failure; + when DEVICE_VIRTEX5 => case DEV_SUB is when DEVICE_SUBTYPE_LX => return TRANSCEIVER_NONE; @@ -1075,7 +1095,7 @@ package body config is case DEV_SUB is when DEVICE_SUBTYPE_T => return TRANSCEIVER_GTXE2; when DEVICE_SUBTYPE_XT => - if (DEV_NUM = 485) then return TRANSCEIVER_GTXE2; + if DEV_NUM = 485 then return TRANSCEIVER_GTXE2; else return TRANSCEIVER_GTHE2; end if; when DEVICE_SUBTYPE_HT => return TRANSCEIVER_GTHE2; @@ -1110,10 +1130,36 @@ package body config is return Result; end function; + + -- Convert T_DEVICE to string representation as required by "altera_mf" library + function getAlteraDeviceName (device : T_DEVICE) return string is + begin + case device is + when DEVICE_ARRIA1 => return "Arria"; + when DEVICE_ARRIA2 => return "Arria II"; + when DEVICE_ARRIA5 => return "Arria V"; + when DEVICE_ARRIA10 => return "Arria 10"; + when DEVICE_CYCLONE1 => return "Cyclone"; + when DEVICE_CYCLONE2 => return "Cyclone II"; + when DEVICE_CYCLONE3 => return "Cyclone III"; + when DEVICE_CYCLONE4 => return "Cyclone IV"; + when DEVICE_CYCLONE5 => return "Cyclone V"; + when DEVICE_STRATIX1 => return "Stratix"; + when DEVICE_STRATIX2 => return "Stratix II"; + when DEVICE_STRATIX3 => return "Stratix III"; + when DEVICE_STRATIX4 => return "Stratix IV"; + when DEVICE_STRATIX5 => return "Stratix V"; + when DEVICE_STRATIX10 => return "Stratix 10"; + when others => + report "Unknown Altera device." severity failure; + -- return statement is explicitly missing otherwise XST won't stop + end case; + end function; + -- force FSM to predefined encoding in debug mode - function getFSMEncoding_gray(debug : BOOLEAN) return STRING is + function getFSMEncoding_gray(debug : boolean) return string is begin - if (debug = true) then + if debug then return "gray"; else case VENDOR is diff --git a/src/common/debug.vhdl b/src/common/debug.vhdl index 7bf772f4..0a852a93 100644 --- a/src/common/debug.vhdl +++ b/src/common/debug.vhdl @@ -1,8 +1,7 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Thomas B. Preusser -- Martin Zabel -- Patrick Lehmann @@ -10,12 +9,12 @@ -- Package: Debug helper functions. -- -- Description: --- ------------------------------------ +-- ------------------------------------- -- This file declares a debug helper function to export enum encodings as a -- ChipScope readable token file (*.tok). -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -30,7 +29,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= use STD.TextIO.all; @@ -39,13 +38,13 @@ use PoC.strings.all; package debug is - impure function dbg_ExportEncoding(Name : STRING; encodings : string; tokenFileName : STRING) return BOOLEAN; + impure function dbg_ExportEncoding(Name : string; encodings : string; tokenFileName : string) return boolean; end package; package body debug is - impure function dbg_ExportEncoding(Name : STRING; encodings : string; tokenFileName : STRING) return BOOLEAN is + impure function dbg_ExportEncoding(Name : string; encodings : string; tokenFileName : string) return boolean is file tokenFile : TEXT open WRITE_MODE is tokenFileName; variable cnt, base : integer; @@ -55,14 +54,14 @@ package body debug is report "dbg_ExportEncoding: '" & encodings & "'" severity note; -- write file header - write(l, STRING'("# Encoding file for '" & Name & "'")); writeline(tokenFile, l); - write(l, STRING'("#")); writeline(tokenFile, l); - write(l, STRING'("# ChipScope Token File Version")); writeline(tokenFile, l); - write(l, STRING'("@FILE_VERSION=1.0.0")); writeline(tokenFile, l); - write(l, STRING'("#")); writeline(tokenFile, l); - write(l, STRING'("# Default token value")); writeline(tokenFile, l); - write(l, STRING'("@DEFAULT_TOKEN=")); writeline(tokenFile, l); - write(l, STRING'("#")); writeline(tokenFile, l); + write(l, string'("# Encoding file for '" & Name & "'")); writeline(tokenFile, l); + write(l, string'("#")); writeline(tokenFile, l); + write(l, string'("# ChipScope Token File Version")); writeline(tokenFile, l); + write(l, string'("@FILE_VERSION=1.0.0")); writeline(tokenFile, l); + write(l, string'("#")); writeline(tokenFile, l); + write(l, string'("# Default token value")); writeline(tokenFile, l); + write(l, string'("@DEFAULT_TOKEN=")); writeline(tokenFile, l); + write(l, string'("#")); writeline(tokenFile, l); -- write state entires cnt := 0; diff --git a/src/common/fileio.v08.vhdl b/src/common/fileio.v08.vhdl index 43e3dc22..75e7de2e 100644 --- a/src/common/fileio.v08.vhdl +++ b/src/common/fileio.v08.vhdl @@ -1,18 +1,17 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- -- Package: File I/O-related Functions. -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -42,46 +41,46 @@ package FileIO is subtype T_LOGFILE_OPEN_KIND is FILE_OPEN_KIND range WRITE_MODE to APPEND_MODE; -- Constant declarations - constant C_LINEBREAK : STRING; + constant C_LINEBREAK : string; -- =========================================================================== type T_LOGFILE is protected - procedure OpenFile(FileName : STRING; OpenKind : T_LOGFILE_OPEN_KIND := WRITE_MODE); - impure function OpenFile(FileName : STRING; OpenKind : T_LOGFILE_OPEN_KIND := WRITE_MODE) return FILE_OPEN_STATUS; - procedure OpenFile(Status : out FILE_OPEN_STATUS; FileName : STRING; OpenKind : T_LOGFILE_OPEN_KIND := WRITE_MODE); - impure function IsOpen return BOOLEAN; + procedure OpenFile(FileName : string; OpenKind : T_LOGFILE_OPEN_KIND := WRITE_MODE); + impure function OpenFile(FileName : string; OpenKind : T_LOGFILE_OPEN_KIND := WRITE_MODE) return FILE_OPEN_STATUS; + procedure OpenFile(Status : out FILE_OPEN_STATUS; FileName : string; OpenKind : T_LOGFILE_OPEN_KIND := WRITE_MODE); + impure function IsOpen return boolean; procedure CloseFile; - procedure Print(str : STRING); - procedure PrintLine(str : STRING := ""); + procedure Print(str : string); + procedure PrintLine(str : string := ""); procedure Flush; -- procedure WriteLine(LineBuffer : inout LINE); end protected; -- =========================================================================== type T_FILE is protected - procedure OpenFile(FileName : STRING; OpenKind : FILE_OPEN_KIND := WRITE_MODE); - impure function OpenFile(FileName : STRING; OpenKind : FILE_OPEN_KIND := WRITE_MODE) return FILE_OPEN_STATUS; - procedure OpenFile(Status : out FILE_OPEN_STATUS; FileName : STRING; OpenKind : FILE_OPEN_KIND := WRITE_MODE); - impure function IsOpen return BOOLEAN; + procedure OpenFile(FileName : string; OpenKind : FILE_OPEN_KIND := WRITE_MODE); + impure function OpenFile(FileName : string; OpenKind : FILE_OPEN_KIND := WRITE_MODE) return FILE_OPEN_STATUS; + procedure OpenFile(Status : out FILE_OPEN_STATUS; FileName : string; OpenKind : FILE_OPEN_KIND := WRITE_MODE); + impure function IsOpen return boolean; procedure CloseFile; - procedure Print(str : STRING); - procedure PrintLine(str : STRING := ""); + procedure Print(str : string); + procedure PrintLine(str : string := ""); procedure Flush; -- procedure WriteLine(LineBuffer : inout LINE); end protected; type T_STDOUT is protected - procedure Print(str : STRING); - procedure PrintLine(str : STRING := ""); + procedure Print(str : string); + procedure PrintLine(str : string := ""); procedure Flush; end protected; end package; package body FileIO is - constant C_LINEBREAK : STRING := ite(str_equal(MY_OPERATING_SYSTEM, "WINDOWS"), (CR & LF), (1 => LF)); + constant C_LINEBREAK : string := ite(str_equal(MY_OPERATING_SYSTEM, "WINDOWS"), (CR & LF), (1 => LF)); -- =========================================================================== file Global_LogFile : TEXT; @@ -93,28 +92,28 @@ package body FileIO is -- =========================================================================== type T_LOGFILE is protected body variable LineBuffer : LINE; - variable Local_IsOpen : BOOLEAN; - variable Local_FileName : STRING(1 to 256); + variable Local_IsOpen : boolean; + variable Local_FileName : string(1 to 256); - procedure OpenFile(FileName : STRING; OpenKind : T_LOGFILE_OPEN_KIND := WRITE_MODE) is + procedure OpenFile(FileName : string; OpenKind : T_LOGFILE_OPEN_KIND := WRITE_MODE) is variable Status : FILE_OPEN_STATUS; begin OpenFile(Status, FileName, OpenKind); end procedure; - impure function OpenFile(FileName : STRING; OpenKind : T_LOGFILE_OPEN_KIND := WRITE_MODE) return FILE_OPEN_STATUS is + impure function OpenFile(FileName : string; OpenKind : T_LOGFILE_OPEN_KIND := WRITE_MODE) return FILE_OPEN_STATUS is variable Status : FILE_OPEN_STATUS; begin OpenFile(Status, FileName, OpenKind); return Status; end function; - procedure OpenFile(Status : out FILE_OPEN_STATUS; FileName : STRING; OpenKind : T_LOGFILE_OPEN_KIND := WRITE_MODE) is + procedure OpenFile(Status : out FILE_OPEN_STATUS; FileName : string; OpenKind : T_LOGFILE_OPEN_KIND := WRITE_MODE) is variable Status_i : FILE_OPEN_STATUS; begin - if (Local_IsOpen = FALSE) then + if not Local_IsOpen then file_open(Status_i, Global_LogFile, FileName, OpenKind); - Local_IsOpen := (Status_i = OPEN_OK); + Local_IsOpen := Status_i = OPEN_OK; Local_FileName := resize(FileName, Local_FileName'length); Status := Status_i; else @@ -122,14 +121,14 @@ package body FileIO is end if; end procedure; - impure function IsOpen return BOOLEAN is + impure function IsOpen return boolean is begin return Local_IsOpen; end function; procedure CloseFile is begin - if (Local_IsOpen = TRUE) then + if Local_IsOpen then file_close(Global_LogFile); Local_IsOpen := FALSE; end if; @@ -137,7 +136,7 @@ package body FileIO is procedure WriteLine(LineBuffer : inout LINE) is begin - if (Local_IsOpen = FALSE) then + if not Local_IsOpen then writeline(OUTPUT, LineBuffer); -- elsif (LogFile_IsMirrored.Get = TRUE) then -- tee(Global_LogFile, LineBuffer); @@ -146,12 +145,12 @@ package body FileIO is end if ; end procedure; - procedure Print(str : STRING) is + procedure Print(str : string) is begin write(LineBuffer, str); end procedure; - procedure PrintLine(str : STRING := "") is + procedure PrintLine(str : string := "") is begin write(LineBuffer, str); WriteLine(LineBuffer); @@ -166,33 +165,33 @@ package body FileIO is type T_FILE is protected body file LocalFile : TEXT; variable LineBuffer : LINE; - variable Local_IsOpen : BOOLEAN; - variable Local_FileName : STRING(1 to 256); + variable Local_IsOpen : boolean; + variable Local_FileName : string(1 to 256); - procedure OpenFile(FileName : STRING; OpenKind : FILE_OPEN_KIND := WRITE_MODE) is + procedure OpenFile(FileName : string; OpenKind : FILE_OPEN_KIND := WRITE_MODE) is variable Status : FILE_OPEN_STATUS; begin OpenFile(Status, FileName, OpenKind); end procedure; - impure function OpenFile(FileName : STRING; OpenKind : FILE_OPEN_KIND := WRITE_MODE) return FILE_OPEN_STATUS is + impure function OpenFile(FileName : string; OpenKind : FILE_OPEN_KIND := WRITE_MODE) return FILE_OPEN_STATUS is variable Status : FILE_OPEN_STATUS; begin OpenFile(Status, FileName, OpenKind); return Status; end function; - impure function IsOpen return BOOLEAN is + impure function IsOpen return boolean is begin return Local_IsOpen; end function; - procedure OpenFile(Status : out FILE_OPEN_STATUS; FileName : STRING; OpenKind : FILE_OPEN_KIND := WRITE_MODE) is + procedure OpenFile(Status : out FILE_OPEN_STATUS; FileName : string; OpenKind : FILE_OPEN_KIND := WRITE_MODE) is variable Status_i : FILE_OPEN_STATUS; begin - if (Local_IsOpen = FALSE) then + if not Local_IsOpen then file_open(Status_i, LocalFile, FileName, OpenKind); - Local_IsOpen := (Status_i = OPEN_OK); + Local_IsOpen := Status_i = OPEN_OK; Local_FileName := resize(FileName, Local_FileName'length); Status := Status_i; else @@ -202,7 +201,7 @@ package body FileIO is procedure CloseFile is begin - if (Local_IsOpen = TRUE) then + if Local_IsOpen then file_close(LocalFile); Local_IsOpen := FALSE; end if; @@ -210,19 +209,19 @@ package body FileIO is procedure WriteLine(LineBuffer : inout LINE) is begin - if (Local_IsOpen = FALSE) then + if not Local_IsOpen then report "File is not open." severity ERROR; else writeline(LocalFile, LineBuffer); end if ; end procedure; - procedure Print(str : STRING) is + procedure Print(str : string) is begin write(LineBuffer, str); end procedure; - procedure PrintLine(str : STRING := "") is + procedure PrintLine(str : string := "") is begin write(LineBuffer, str); WriteLine(LineBuffer); @@ -237,12 +236,12 @@ package body FileIO is type T_STDOUT is protected body variable LineBuffer : LINE; - procedure Print(str : STRING) is + procedure Print(str : string) is begin write(LineBuffer, str); end procedure; - procedure PrintLine(str : STRING := "") is + procedure PrintLine(str : string := "") is begin write(LineBuffer, str); writeline(OUTPUT, LineBuffer); diff --git a/src/common/fileio.v93.vhdl b/src/common/fileio.v93.vhdl index c5923def..b9adab8c 100644 --- a/src/common/fileio.v93.vhdl +++ b/src/common/fileio.v93.vhdl @@ -1,15 +1,14 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- Thomas B. Preusser -- -- Package: File I/O-related Functions. -- -- Description: --- ------------------------------------ +-- ------------------------------------- -- Exploring the options for providing a more convenient API than std.textio. -- Not yet recommended for adoption as it depends on the VHDL generation and -- still is under discussion. @@ -21,7 +20,7 @@ -- - move C_LINEBREAK to my_config to keep platform dependency out? -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -48,63 +47,63 @@ use PoC.utils.all; package FileIO is -- Constant declarations - constant C_LINEBREAK : STRING; + constant C_LINEBREAK : string; -- Log file -- =========================================================================== subtype T_LOGFILE_OPEN_KIND is FILE_OPEN_KIND range WRITE_MODE to APPEND_MODE; - procedure LogFile_Open(FileName : STRING; OpenKind : T_LOGFILE_OPEN_KIND := WRITE_MODE); - procedure LogFile_Open(Status : out FILE_OPEN_STATUS; FileName : STRING; OpenKind : T_LOGFILE_OPEN_KIND := WRITE_MODE); - impure function LogFile_IsOpen return BOOLEAN; - procedure LogFile_Print(str : STRING); - procedure LogFile_PrintLine(str : STRING := ""); + procedure LogFile_Open(FileName : string; OpenKind : T_LOGFILE_OPEN_KIND := WRITE_MODE); + procedure LogFile_Open(Status : out FILE_OPEN_STATUS; FileName : string; OpenKind : T_LOGFILE_OPEN_KIND := WRITE_MODE); + impure function LogFile_IsOpen return boolean; + procedure LogFile_Print(str : string); + procedure LogFile_PrintLine(str : string := ""); procedure LogFile_Flush; procedure LogFile_Close; -- StdOut -- =========================================================================== - procedure StdOut_Print(str : STRING); - procedure StdOut_PrintLine(str : STRING := ""); + procedure StdOut_Print(str : string); + procedure StdOut_PrintLine(str : string := ""); procedure StdOut_Flush; end package; package body FileIO is - constant C_LINEBREAK : STRING := ite(str_equal(MY_OPERATING_SYSTEM, "WINDOWS"), (CR & LF), (1 => LF)); + constant C_LINEBREAK : string := ite(str_equal(MY_OPERATING_SYSTEM, "WINDOWS"), (CR & LF), (1 => LF)); -- =========================================================================== file LogFile_FileHandle : TEXT; - shared variable LogFile_State_IsOpen : BOOLEAN := FALSE; + shared variable LogFile_State_IsOpen : boolean := FALSE; shared variable LogFile_LineBuffer : LINE; - procedure LogFile_Open(FileName : STRING; OpenKind : T_LOGFILE_OPEN_KIND := WRITE_MODE) is + procedure LogFile_Open(FileName : string; OpenKind : T_LOGFILE_OPEN_KIND := WRITE_MODE) is variable OpenStatus : FILE_OPEN_STATUS; begin LogFile_Open(OpenStatus, FileName, OpenKind); end procedure; - procedure LogFile_Open(Status : out FILE_OPEN_STATUS; FileName : STRING; OpenKind : T_LOGFILE_OPEN_KIND := WRITE_MODE) is + procedure LogFile_Open(Status : out FILE_OPEN_STATUS; FileName : string; OpenKind : T_LOGFILE_OPEN_KIND := WRITE_MODE) is variable OpenStatus : FILE_OPEN_STATUS; begin file_open(OpenStatus, LogFile_FileHandle, FileName, OpenKind); - LogFile_State_IsOpen := (OpenStatus = OPEN_OK); + LogFile_State_IsOpen := OpenStatus = OPEN_OK; Status := OpenStatus; end procedure; - impure function LogFile_IsOpen return BOOLEAN is + impure function LogFile_IsOpen return boolean is begin return LogFile_State_IsOpen; end function; - procedure LogFile_Print(str : STRING) is + procedure LogFile_Print(str : string) is begin write(LogFile_LineBuffer, str); end procedure; - procedure LogFile_PrintLine(str : STRING := "") is + procedure LogFile_PrintLine(str : string := "") is begin write(LogFile_LineBuffer, str); writeline(LogFile_FileHandle, LogFile_LineBuffer); @@ -117,7 +116,7 @@ package body FileIO is procedure LogFile_Close is begin - if (LogFile_State_IsOpen = TRUE) then + if LogFile_State_IsOpen then file_close(LogFile_FileHandle); LogFile_State_IsOpen := FALSE; end if; @@ -126,12 +125,12 @@ package body FileIO is -- =========================================================================== shared variable StdOut_LineBuffer : line; - procedure StdOut_Print(str : STRING) is + procedure StdOut_Print(str : string) is begin write(StdOut_LineBuffer, str); end procedure; - procedure StdOut_PrintLine(str : STRING := "") is + procedure StdOut_PrintLine(str : string := "") is begin write(StdOut_LineBuffer, str); writeline(OUTPUT, StdOut_LineBuffer); diff --git a/src/common/math.vhdl b/src/common/math.vhdl index b7be4382..3cfc0ba4 100644 --- a/src/common/math.vhdl +++ b/src/common/math.vhdl @@ -1,18 +1,17 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- -- Package: Math extension package. -- -- Description: --- ------------------------------------ +-- ------------------------------------- -- This package provides additional math functions. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -27,7 +26,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.std_logic_1164.all; @@ -39,41 +38,41 @@ use PoC.utils.all; package math is -- figurate numbers - function squareNumber(N : POSITIVE) return POSITIVE; - function cubicNumber(N : POSITIVE) return POSITIVE; - function triangularNumber(N : NATURAL) return NATURAL; + function squareNumber(N : natural) return natural; + function cubicNumber(N : natural) return natural; + function triangularNumber(N : natural) return natural; -- coefficients -- binomial coefficient (N choose K) - function binomialCoefficient(N : POSITIVE; K : POSITIVE) return POSITIVE; + function binomialCoefficient(N : positive; K : positive) return positive; -- greatest common divisor (gcd) - function greatestCommonDivisor(N1 : POSITIVE; N2 : POSITIVE) return POSITIVE; + function greatestCommonDivisor(N1 : positive; N2 : positive) return positive; -- least common multiple (lcm) - function leastCommonMultiple(N1 : POSITIVE; N2 : POSITIVE) return POSITIVE; + function leastCommonMultiple(N1 : positive; N2 : positive) return positive; end package; package body math is -- figurate numbers - function squareNumber(N : POSITIVE) return POSITIVE is + function squareNumber(N : natural) return natural is begin return N*N; end function; - function cubicNumber(N : POSITIVE) return POSITIVE is + function cubicNumber(N : natural) return natural is begin return N*N*N; end function; - function triangularNumber(N : NATURAL) return NATURAL is - variable T : NATURAL; + function triangularNumber(N : natural) return natural is + variable T : natural; begin return (N * (N + 1) / 2); end function; -- coefficients - function binomialCoefficient(N : POSITIVE; K : POSITIVE) return POSITIVE is - variable Result : POSITIVE; + function binomialCoefficient(N : positive; K : positive) return positive is + variable Result : positive; begin Result := 1; for i in 1 to K loop @@ -83,10 +82,10 @@ package body math is end function; -- greatest common divisor (gcd) - function greatestCommonDivisor(N1 : POSITIVE; N2 : POSITIVE) return POSITIVE is - variable M1 : POSITIVE; - variable M2 : NATURAL; - variable Remainer : NATURAL; + function greatestCommonDivisor(N1 : positive; N2 : positive) return positive is + variable M1 : positive; + variable M2 : natural; + variable Remainer : natural; begin M1 := imax(N1, N2); M2 := imin(N1, N2); @@ -99,8 +98,8 @@ package body math is end function; -- least common multiple (lcm) - function leastCommonMultiple(N1 : POSITIVE; N2 : POSITIVE) return POSITIVE is + function leastCommonMultiple(N1 : positive; N2 : positive) return positive is begin return ((N1 * N2) / greatestCommonDivisor(N1, N2)); end function; -end package body; \ No newline at end of file +end package body; diff --git a/src/common/physical.vhdl b/src/common/physical.vhdl index 7f97b8f7..e0214446 100644 --- a/src/common/physical.vhdl +++ b/src/common/physical.vhdl @@ -1,16 +1,16 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- Martin Zabel +-- Thomas B. Preusser -- -- Package: This VHDL package declares new physical types and their -- conversion functions. -- -- Description: --- ------------------------------------ +-- ------------------------------------- -- For detailed documentation see below. -- -- NAMING CONVENTION: @@ -33,7 +33,7 @@ -- -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -48,7 +48,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.math_real.all; @@ -66,22 +66,22 @@ package physical is -- Vivado maps 1 us to 1 fs, 1 ms to 1 ps and so on (factor 10e9). -- Thus, define a new type based to be used for PoC functions. subtype T_TIME is real range real'low to real'high; - - type FREQ is range 0 to INTEGER'high units + + type FREQ is range 0 to integer'high units Hz; kHz = 1000 Hz; MHz = 1000 kHz; -- GHz = 1000 MHz; -- suffix not supported because Vivado maps 1 GHz to 1 Hz end units; - type BAUD is range 0 to INTEGER'high units + type BAUD is range 0 to integer'high units Bd; kBd = 1000 Bd; MBd = 1000 kBd; -- GBd = 1000 MBd; -- suffix not supported because Vivado maps 1 GBd to 1 Bd end units; - type MEMORY is range 0 to INTEGER'high units + type MEMORY is range 0 to integer'high units Byte; KiB = 1024 Byte; MiB = 1024 KiB; @@ -89,26 +89,35 @@ package physical is end units; -- vector data types - type T_TIMEVEC is array(NATURAL range <>) of T_TIME; - type T_FREQVEC is array(NATURAL range <>) of FREQ; - type T_BAUDVEC is array(NATURAL range <>) of BAUD; - type T_MEMVEC is array(NATURAL range <>) of MEMORY; + type T_TIMEVEC is array(natural range <>) of T_TIME; + type T_FREQVEC is array(natural range <>) of FREQ; + type T_BAUDVEC is array(natural range <>) of BAUD; + type T_MEMVEC is array(natural range <>) of MEMORY; -- if true: TimingToCycles reports difference between expected and actual result - constant C_PHYSICAL_REPORT_TIMING_DEVIATION : BOOLEAN := TRUE; + constant C_PHYSICAL_REPORT_TIMING_DEVIATION : boolean := TRUE; -- conversion functions - function to_time(f : FREQ) return TIME; -- can be used by testbenches without restrictions + function to_time(f : FREQ) return time; -- can be used by testbenches without restrictions function to_time(f : FREQ) return T_TIME; function to_freq(p : T_TIME) return FREQ; function to_freq(br : BAUD) return FREQ; - function to_baud(str : STRING) return BAUD; + function to_baud(str : string) return BAUD; + + -- inter-type arithmetic + function div(a : time; b : time) return real; + function div(a : FREQ; b : FREQ) return real; + + function "/"(x : real; t : time) return FREQ; + function "/"(x : real; f : FREQ) return time; + function "*"(t : time; f : FREQ) return real; + function "*"(f : FREQ; t : time) return real; -- if-then-else -- function ite(cond : BOOLEAN; value1 : T_TIME; value2 : T_TIME) return T_TIME; -- include package PoC.utils instead. - function ite(cond : BOOLEAN; value1 : FREQ; value2 : FREQ) return FREQ; - function ite(cond : BOOLEAN; value1 : BAUD; value2 : BAUD) return BAUD; - function ite(cond : BOOLEAN; value1 : MEMORY; value2 : MEMORY) return MEMORY; + function ite(cond : boolean; value1 : FREQ; value2 : FREQ) return FREQ; + function ite(cond : boolean; value1 : BAUD; value2 : BAUD) return BAUD; + function ite(cond : boolean; value1 : MEMORY; value2 : MEMORY) return MEMORY; -- min/ max for 2 arguments function tmin(arg1 : T_TIME; arg2 : T_TIME) return T_TIME; -- Calculates: min(arg1, arg2) for times @@ -138,12 +147,12 @@ package physical is function msum(vec : T_MEMVEC) return MEMORY; -- Calculates: sum(vec) for a memory vector -- convert standard types (NATURAL, REAL) to time (T_TIME) - function fs2Time(t_fs : INTEGER) return T_TIME; - function ps2Time(t_ps : INTEGER) return T_TIME; - function ns2Time(t_ns : INTEGER) return T_TIME; - function us2Time(t_us : INTEGER) return T_TIME; - function ms2Time(t_ms : INTEGER) return T_TIME; - function sec2Time(t_sec : INTEGER) return T_TIME; + function fs2Time(t_fs : integer) return T_TIME; + function ps2Time(t_ps : integer) return T_TIME; + function ns2Time(t_ns : integer) return T_TIME; + function us2Time(t_us : integer) return T_TIME; + function ms2Time(t_ms : integer) return T_TIME; + function sec2Time(t_sec : integer) return T_TIME; function fs2Time(t_fs : REAL) return T_TIME; function ps2Time(t_ps : REAL) return T_TIME; @@ -153,10 +162,10 @@ package physical is function sec2Time(t_sec : REAL) return T_TIME; -- convert standard types (NATURAL, REAL) to period (T_TIME) - function Hz2Time(f_Hz : NATURAL) return T_TIME; - function kHz2Time(f_kHz : NATURAL) return T_TIME; - function MHz2Time(f_MHz : NATURAL) return T_TIME; - function GHz2Time(f_GHz : NATURAL) return T_TIME; + function Hz2Time(f_Hz : natural) return T_TIME; + function kHz2Time(f_kHz : natural) return T_TIME; + function MHz2Time(f_MHz : natural) return T_TIME; + function GHz2Time(f_GHz : natural) return T_TIME; function Hz2Time(f_Hz : REAL) return T_TIME; function kHz2Time(f_kHz : REAL) return T_TIME; @@ -164,10 +173,10 @@ package physical is function GHz2Time(f_GHz : REAL) return T_TIME; -- convert standard types (NATURAL, REAL) to frequency (FREQ) - function Hz2Freq(f_Hz : NATURAL) return FREQ; - function kHz2Freq(f_kHz : NATURAL) return FREQ; - function MHz2Freq(f_MHz : NATURAL) return FREQ; - function GHz2Freq(f_GHz : NATURAL) return FREQ; + function Hz2Freq(f_Hz : natural) return FREQ; + function kHz2Freq(f_kHz : natural) return FREQ; + function MHz2Freq(f_MHz : natural) return FREQ; + function GHz2Freq(f_GHz : natural) return FREQ; function Hz2Freq(f_Hz : REAL) return FREQ; function kHz2Freq(f_kHz : REAL) return FREQ; @@ -175,38 +184,52 @@ package physical is function GHz2Freq(f_GHz : REAL) return FREQ; -- convert physical types to standard type (REAL) - function to_real(t : TIME; scale : TIME) return REAL; + function to_real(t : time; scale : time) return REAL; function to_real(t : T_TIME; scale : T_TIME) return REAL; function to_real(f : FREQ; scale : FREQ) return REAL; function to_real(br : BAUD; scale : BAUD) return REAL; function to_real(mem : MEMORY; scale : MEMORY) return REAL; -- convert physical types to standard type (INTEGER) - function to_int(t : T_TIME; scale : T_TIME; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER; - function to_int(f : FREQ; scale : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER; - function to_int(br : BAUD; scale : BAUD; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER; - function to_int(mem : MEMORY; scale : MEMORY; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return INTEGER; + function to_int(t : T_TIME; scale : T_TIME; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return integer; + function to_int(f : FREQ; scale : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return integer; + function to_int(br : BAUD; scale : BAUD; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return integer; + function to_int(mem : MEMORY; scale : MEMORY; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return integer; -- calculate needed counter cycles to achieve a given 1. timing/delay and 2. frequency/period - function TimingToCycles(Timing : T_TIME; Clock_Period : T_TIME; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return NATURAL; - function TimingToCycles(Timing : T_TIME; Clock_Frequency : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return NATURAL; + function TimingToCycles(Timing : T_TIME; Clock_Period : T_TIME; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return natural; + function TimingToCycles(Timing : T_TIME; Clock_Frequency : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return natural; - function CyclesToDelay(Cycles : NATURAL; Clock_Period : T_TIME) return T_TIME; - function CyclesToDelay(Cycles : NATURAL; Clock_Frequency : FREQ) return T_TIME; + function CyclesToDelay(Cycles : natural; Clock_Period : T_TIME) return T_TIME; + function CyclesToDelay(Cycles : natural; Clock_Frequency : FREQ) return T_TIME; -- convert and format physical types to STRING - function to_string(t : TIME; precision : NATURAL) return STRING; - function to_string(t : T_TIME; precision : NATURAL) return STRING; - function to_string(f : FREQ; precision : NATURAL) return STRING; - function to_string(br : BAUD; precision : NATURAL) return STRING; - function to_string(mem : MEMORY; precision : NATURAL) return STRING; + function to_string(t : time; precision : natural) return string; + function to_string(t : T_TIME; precision : natural) return string; + function to_string(f : FREQ; precision : natural) return string; + function to_string(br : BAUD; precision : natural) return string; + function to_string(mem : MEMORY; precision : natural) return string; end package; package body physical is - -- iSim 14.7 does not support fs in simulation (fs values are converted to 0 ps) - function MinimalTimeResolutionInSimulation return TIME is + -- WORKAROUND: for simulators with a "Minimal Time Resolution" > 1 fs + -- Version: all + -- Vendors: all + -- Issue: + -- Some simulators use a lower minimal time resolution (MTR) than the VHDL + -- standard (LRM) defines (1 fs). Usually, the MTR is set to 1 ps or 1 ns. + -- Most simulators allow the user to specify a higher MTR -> check the + -- simulator documentation. + -- Solution: + -- The currently set MTR can be calculated in VHDL. Using the correct MTR + -- can prevent cleared intermediate values and division by zero errors. + -- Examples: + -- Mentor Graphics QuestaSim/ModelSim (vSim): default MTR = ? ?? + -- Xilinx ISE Simulator (iSim): default MTR = 1 ps + -- Xilinx Vivado Simulator (xSim): default MTR = 1 ps + function MinimalTimeResolutionInSimulation return time is begin if (1 fs > 0 sec) then return 1 fs; elsif (1 ps > 0 sec) then return 1 ps; @@ -219,12 +242,19 @@ package body physical is -- real division for physical types -- =========================================================================== - function div(a : TIME; b : TIME) return REAL is - constant MTRIS : TIME := MinimalTimeResolutionInSimulation; + function div(a : time; b : time) return REAL is + constant MTRIS : time := MinimalTimeResolutionInSimulation; variable a_real : real; variable b_real : real; begin - -- Quartus-II work-around + -- WORKAROUND: for Altera Quartus + -- Version: all + -- Issue: + -- Results of TIME arithmetic must be in 32-bit integer range, because + -- the internally used 64-bit integer for type TIME can not be + -- represented in VHDL. + -- Solution: + -- Pre- and post-scale all values to stay in the integer range. if a < 1 us then a_real := real(a / MTRIS); elsif a < 1 ms then @@ -247,7 +277,7 @@ package body physical is return a_real / b_real; end function; - + function div(a : T_TIME; b : T_TIME) return REAL is begin return a / b; @@ -270,11 +300,11 @@ package body physical is -- conversion functions -- =========================================================================== - function to_time(f : FREQ) return TIME is -- can be used by testbenches without restrictions - variable res : TIME; + function to_time(f : FREQ) return time is -- can be used by testbenches without restrictions + variable res : time; begin res := div(1000 MHz, f) * 1 ns; - if (POC_VERBOSE = TRUE) then + if POC_VERBOSE then report "to_time: f= " & to_string(f, 3) & " return " & to_string(res, 3) severity note; end if; return res; @@ -306,7 +336,7 @@ package body physical is if (p >= 500.0e-12) then res := integer(1.0 / p) * 1 Hz; else report "to_freq: input period exceeds output frequency scale." severity failure; end if; - if (POC_VERBOSE = TRUE) then + if POC_VERBOSE then report "to_freq: p= " & to_string(p, 3) & " return " & to_string(res, 3) severity note; end if; return res; @@ -316,18 +346,18 @@ package body physical is variable res : FREQ; begin res := (br / 1 Bd) * 1 Hz; - if (POC_VERBOSE = TRUE) then + if POC_VERBOSE then report "to_freq: br= " & to_string(br, 3) & " return " & to_string(res, 3) severity note; end if; return res; end function; - function to_baud(str : STRING) return BAUD is - variable pos : INTEGER; - variable int : NATURAL; - variable base : POSITIVE; - variable frac : NATURAL; - variable digits : NATURAL; + function to_baud(str : string) return BAUD is + variable pos : integer; + variable int : natural; + variable base : positive; + variable frac : natural; + variable digits : natural; begin pos := str'low; int := 0; @@ -335,7 +365,7 @@ package body physical is digits := 0; -- read integer part for i in pos to str'high loop - if (chr_isDigit(str(i)) = TRUE) then int := int * 10 + to_digit_dec(str(i)); + if chr_isDigit(str(i)) then int := int * 10 + to_digit_dec(str(i)); elsif (str(i) = '.') then pos := -i; exit; elsif (str(i) = ' ') then pos := i; exit; else pos := 0; exit; @@ -345,32 +375,32 @@ package body physical is if ((pos < 0) and (-pos < str'high)) then for i in -pos+1 to str'high loop if ((frac = 0) and (str(i) = '0')) then next; - elsif (chr_isDigit(str(i)) = TRUE) then frac := frac * 10 + to_digit_dec(str(i)); + elsif chr_isDigit(str(i)) then frac := frac * 10 + to_digit_dec(str(i)); elsif (str(i) = ' ') then digits := i + pos - 1; pos := i; exit; else pos := 0; exit; end if; end loop; end if; -- abort if format is unknown - if (pos = 0) then report "to_baud: Unknown format" severity FAILURE; end if; + if pos = 0 then report "to_baud: Unknown format" severity FAILURE; end if; -- parse unit pos := pos + 1; if ((pos + 1 = str'high) and (str(pos to pos + 1) = "Bd")) then return int * 1 Bd; elsif (pos + 2 = str'high) then if (str(pos to pos + 2) = "kBd") then - if (frac = 0) then return (int * 1 kBd); + if frac = 0 then return (int * 1 kBd); elsif (digits <= 3) then return (int * 1 kBd) + (frac * 10**(3 - digits) * 1 Bd); else return (int * 1 kBd) + (frac / 10**(digits - 3) * 100 Bd); end if; elsif (str(pos to pos + 2) = "MBd") then - if (frac = 0) then return (int * 1 kBd); + if frac = 0 then return (int * 1 kBd); elsif (digits <= 3) then return (int * 1 MBd) + (frac * 10**(3 - digits) * 1 kBd); elsif (digits <= 6) then return (int * 1 MBd) + (frac * 10**(6 - digits) * 1 Bd); else return (int * 1 MBd) + (frac / 10**(digits - 6) * 100000 Bd); end if; elsif (str(pos to pos + 2) = "GBd") then - if (frac = 0) then return (int * 1 kBd); + if frac = 0 then return (int * 1 kBd); elsif (digits <= 3) then return (int * 1000 MBd) + (frac * 10**(3 - digits) * 1 MBd); elsif (digits <= 6) then return (int * 1000 MBd) + (frac * 10**(6 - digits) * 1 kBd); elsif (digits <= 9) then return (int * 1000 MBd) + (frac * 10**(9 - digits) * 1 Bd); @@ -384,6 +414,25 @@ package body physical is end if; end function; + -- inter-type arithmetic + -- =========================================================================== + function "/"(x : real; t : time) return FREQ is + begin + return x*div(1 ms, t) * 1 kHz; + end function; + function "/"(x : real; f : FREQ) return time is + begin + return x*div(1 kHz, f) * 1 ms; + end function; + function "*"(t : time; f : FREQ) return real is + begin + return div(t, 1.0/f); + end function; + function "*"(f : FREQ; t : time) return real is + begin + return div(f, 1.0/t); + end function; + -- if-then-else -- =========================================================================== -- include package PoC.utils instead. @@ -396,7 +445,7 @@ package body physical is -- end if; --end function; - function ite(cond : BOOLEAN; value1 : FREQ; value2 : FREQ) return FREQ is + function ite(cond : boolean; value1 : FREQ; value2 : FREQ) return FREQ is begin if cond then return value1; @@ -405,7 +454,7 @@ package body physical is end if; end function; - function ite(cond : BOOLEAN; value1 : BAUD; value2 : BAUD) return BAUD is + function ite(cond : boolean; value1 : BAUD; value2 : BAUD) return BAUD is begin if cond then return value1; @@ -414,7 +463,7 @@ package body physical is end if; end function; - function ite(cond : BOOLEAN; value1 : MEMORY; value2 : MEMORY) return MEMORY is + function ite(cond : boolean; value1 : MEMORY; value2 : MEMORY) return MEMORY is begin if cond then return value1; @@ -428,56 +477,56 @@ package body physical is -- Calculates: min(arg1, arg2) for times function tmin(arg1 : T_TIME; arg2 : T_TIME) return T_TIME is begin - if (arg1 < arg2) then return arg1; end if; + if arg1 < arg2 then return arg1; end if; return arg2; end function; -- Calculates: min(arg1, arg2) for frequencies function fmin(arg1 : FREQ; arg2 : FREQ) return FREQ is begin - if (arg1 < arg2) then return arg1; end if; + if arg1 < arg2 then return arg1; end if; return arg2; end function; -- Calculates: min(arg1, arg2) for symbols per second function bmin(arg1 : BAUD; arg2 : BAUD) return BAUD is begin - if (arg1 < arg2) then return arg1; end if; + if arg1 < arg2 then return arg1; end if; return arg2; end function; -- Calculates: min(arg1, arg2) for memory function mmin(arg1 : MEMORY; arg2 : MEMORY) return MEMORY is begin - if (arg1 < arg2) then return arg1; end if; + if arg1 < arg2 then return arg1; end if; return arg2; end function; -- Calculates: max(arg1, arg2) for times function tmax(arg1 : T_TIME; arg2 : T_TIME) return T_TIME is begin - if (arg1 > arg2) then return arg1; end if; + if arg1 > arg2 then return arg1; end if; return arg2; end function; -- Calculates: max(arg1, arg2) for frequencies function fmax(arg1 : FREQ; arg2 : FREQ) return FREQ is begin - if (arg1 > arg2) then return arg1; end if; + if arg1 > arg2 then return arg1; end if; return arg2; end function; -- Calculates: max(arg1, arg2) for symbols per second function bmax(arg1 : BAUD; arg2 : BAUD) return BAUD is begin - if (arg1 > arg2) then return arg1; end if; + if arg1 > arg2 then return arg1; end if; return arg2; end function; -- Calculates: max(arg1, arg2) for memory function mmax(arg1 : MEMORY; arg2 : MEMORY) return MEMORY is begin - if (arg1 > arg2) then return arg1; end if; + if arg1 > arg2 then return arg1; end if; return arg2; end function; @@ -488,7 +537,7 @@ package body physical is variable res : T_TIME := T_TIME'high; begin for i in vec'range loop - if (vec(i) < res) then + if vec(i) < res then res := vec(i); end if; end loop; @@ -536,7 +585,7 @@ package body physical is variable res : T_TIME := T_TIME'low; begin for i in vec'range loop - if (vec(i) > res) then + if vec(i) > res then res := vec(i); end if; end loop; @@ -621,32 +670,32 @@ package body physical is -- convert standard types (NATURAL, REAL) to time (T_TIME) -- =========================================================================== - function fs2Time(t_fs : INTEGER) return T_TIME is + function fs2Time(t_fs : integer) return T_TIME is begin return real(t_fs) * 1.0e-15; end function; - function ps2Time(t_ps : INTEGER) return T_TIME is + function ps2Time(t_ps : integer) return T_TIME is begin return real(t_ps) * 1.0e-12; end function; - function ns2Time(t_ns : INTEGER) return T_TIME is + function ns2Time(t_ns : integer) return T_TIME is begin return real(t_ns) * 1.0e-9; end function; - function us2Time(t_us : INTEGER) return T_TIME is + function us2Time(t_us : integer) return T_TIME is begin return real(t_us) * 1.0e-6; end function; - function ms2Time(t_ms : INTEGER) return T_TIME is + function ms2Time(t_ms : integer) return T_TIME is begin return real(t_ms) * 1.0e-3; end function; - function sec2Time(t_sec : INTEGER) return T_TIME is + function sec2Time(t_sec : integer) return T_TIME is begin return real(t_sec); end function; @@ -683,23 +732,23 @@ package body physical is -- convert standard types (NATURAL, REAL) to period (T_TIME) -- =========================================================================== - function Hz2Time(f_Hz : NATURAL) return T_TIME is + function Hz2Time(f_Hz : natural) return T_TIME is begin return to_time(Hz2Freq(f_Hz)); end function; - function kHz2Time(f_kHz : NATURAL) return T_TIME is + function kHz2Time(f_kHz : natural) return T_TIME is begin return to_time(kHz2Freq(f_kHz)); end function; - function MHz2Time(f_MHz : NATURAL) return T_TIME + function MHz2Time(f_MHz : natural) return T_TIME is begin return to_time(MHz2Freq(f_MHz)); end function; - function GHz2Time(f_GHz : NATURAL) return T_TIME is + function GHz2Time(f_GHz : natural) return T_TIME is begin return to_time(GHz2Freq(f_GHz)); end function; @@ -726,22 +775,22 @@ package body physical is -- convert standard types (NATURAL, REAL) to frequency (FREQ) -- =========================================================================== - function Hz2Freq(f_Hz : NATURAL) return FREQ is + function Hz2Freq(f_Hz : natural) return FREQ is begin return f_Hz * 1 Hz; end function; - function kHz2Freq(f_kHz : NATURAL) return FREQ is + function kHz2Freq(f_kHz : natural) return FREQ is begin return f_kHz * 1 kHz; end function; - function MHz2Freq(f_MHz : NATURAL) return FREQ is + function MHz2Freq(f_MHz : natural) return FREQ is begin return f_MHz * 1 MHz; end function; - function GHz2Freq(f_GHz : NATURAL) return FREQ is + function GHz2Freq(f_GHz : natural) return FREQ is begin return f_GHz * 1000 MHz; end function; @@ -769,7 +818,7 @@ package body physical is -- convert physical types to standard type (REAL) -- =========================================================================== - function to_real(t : TIME; scale : TIME) return REAL is + function to_real(t : time; scale : time) return REAL is begin if (scale = 1 fs) then return div(t, 1 fs); elsif (scale = 1 ps) then return div(t, 1 ps); @@ -824,7 +873,7 @@ package body physical is -- convert physical types to standard type (INTEGER) -- =========================================================================== - function to_int(t : T_TIME; scale : T_TIME; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER is + function to_int(t : T_TIME; scale : T_TIME; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return integer is begin case RoundingStyle is when ROUND_UP => return integer(ceil(to_real(t, scale))); @@ -835,7 +884,7 @@ package body physical is report "to_int: unsupported RoundingStyle: " & T_ROUNDING_STYLE'image(RoundingStyle) severity failure; end; - function to_int(f : FREQ; scale : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER is + function to_int(f : FREQ; scale : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return integer is begin case RoundingStyle is when ROUND_UP => return integer(ceil(to_real(f, scale))); @@ -846,7 +895,7 @@ package body physical is report "to_int: unsupported RoundingStyle: " & T_ROUNDING_STYLE'image(RoundingStyle) severity failure; end; - function to_int(br : BAUD; scale : BAUD; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER is + function to_int(br : BAUD; scale : BAUD; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return integer is begin case RoundingStyle is when ROUND_UP => return integer(ceil(to_real(br, scale))); @@ -857,7 +906,7 @@ package body physical is report "to_int: unsupported RoundingStyle: " & T_ROUNDING_STYLE'image(RoundingStyle) severity failure; end; - function to_int(mem : MEMORY; scale : MEMORY; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return INTEGER is + function to_int(mem : MEMORY; scale : MEMORY; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return integer is begin case RoundingStyle is when ROUND_UP => return integer(ceil(to_real(mem, scale))); @@ -870,12 +919,12 @@ package body physical is -- calculate needed counter cycles to achieve a given 1. timing/delay and 2. frequency/period -- =========================================================================== - -- @param Timing A given timing or delay, which should be achived + -- @param Timing A given timing or delay, which should be achieved -- @param Clock_Period The period of the circuits clock - -- @RoundingStyle Default = round to nearest; other choises: ROUND_UP, ROUND_DOWN - function TimingToCycles(Timing : T_TIME; Clock_Period : T_TIME; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return NATURAL is + -- @RoundingStyle Default = ROUND_UP; other choises: ROUND_UP, ROUND_DOWN, ROUND_TO_NEAREST + function TimingToCycles(Timing : T_TIME; Clock_Period : T_TIME; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return natural is variable res_real : REAL; - variable res_nat : NATURAL; + variable res_nat : natural; variable res_time : T_TIME; variable res_dev : REAL; begin @@ -895,21 +944,21 @@ package body physical is res_time := CyclesToDelay(res_nat, Clock_Period); res_dev := (div(res_time, Timing) - 1.0) * 100.0; - if (POC_VERBOSE = TRUE) then - report "TimingToCycles: " & CR & - " Timing: " & to_string(Timing, 3) & CR & - " Clock_Period: " & to_string(Clock_Period, 3) & CR & - " RoundingStyle: " & str_substr(T_ROUNDING_STYLE'image(RoundingStyle), 7) & CR & - " res_real = " & str_format(res_real, 3) & CR & - " => " & INTEGER'image(res_nat) + if POC_VERBOSE then + report "TimingToCycles: " & LF & + " Timing: " & to_string(Timing, 3) & LF & + " Clock_Period: " & to_string(Clock_Period, 3) & LF & + " RoundingStyle: " & str_substr(T_ROUNDING_STYLE'image(RoundingStyle), 7) & LF & + " res_real = " & str_format(res_real, 3) & LF & + " => " & integer'image(res_nat) severity note; end if; - if (C_PHYSICAL_REPORT_TIMING_DEVIATION = TRUE) then - report "TimingToCycles (timing deviation report): " & CR & - " timing to achieve: " & to_string(Timing, 3) & CR & - " calculated cycles: " & INTEGER'image(res_nat) & " cy" & CR & - " resulting timing: " & to_string(res_time, 3) & CR & + if C_PHYSICAL_REPORT_TIMING_DEVIATION then + report "TimingToCycles (timing deviation report): " & LF & + " timing to achieve: " & to_string(Timing, 3) & LF & + " calculated cycles: " & integer'image(res_nat) & " cy" & LF & + " resulting timing: " & to_string(res_time, 3) & LF & " deviation: " & to_string(res_time - Timing, 3) & " (" & str_format(res_dev, 2) & "%)" severity note; end if; @@ -917,25 +966,25 @@ package body physical is return res_nat; end; - function TimingToCycles(Timing : T_TIME; Clock_Frequency : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return NATURAL is + function TimingToCycles(Timing : T_TIME; Clock_Frequency : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return natural is begin return TimingToCycles(Timing, to_time(Clock_Frequency), RoundingStyle); end function; - function CyclesToDelay(Cycles : NATURAL; Clock_Period : T_TIME) return T_TIME is + function CyclesToDelay(Cycles : natural; Clock_Period : T_TIME) return T_TIME is begin return Clock_Period * real(Cycles); end function; - function CyclesToDelay(Cycles : NATURAL; Clock_Frequency : FREQ) return T_TIME is + function CyclesToDelay(Cycles : natural; Clock_Frequency : FREQ) return T_TIME is begin return CyclesToDelay(Cycles, to_time(Clock_Frequency)); end function; -- convert and format physical types to STRING - function to_string(t : TIME; precision : NATURAL) return STRING is - variable tt : TIME; - variable unit : STRING(1 to 3) := (others => C_POC_NUL); + function to_string(t : time; precision : natural) return string is + variable tt : time; + variable unit : string(1 to 3) := (others => C_POC_NUL); variable value : REAL; begin tt := abs t; @@ -962,11 +1011,11 @@ package body physical is return ite(t >= 0 fs, str_format(value, precision) & " " & str_trim(unit), '-' & str_format(value, precision) & " " & str_trim(unit)); end function; - - function to_string(t : T_TIME; precision : NATURAL) return STRING is + + function to_string(t : T_TIME; precision : natural) return string is variable tt : T_TIME; - variable unit : STRING(1 to 3) := (others => C_POC_NUL); - variable value : REAL; + variable unit : string(1 to 3) := (others => C_POC_NUL); + variable value : real; begin tt := abs t; if (tt < 1.0e-12) then @@ -993,8 +1042,8 @@ package body physical is '-' & str_format(value, precision) & " " & str_trim(unit)); end function; - function to_string(f : FREQ; precision : NATURAL) return STRING is - variable unit : STRING(1 to 3) := (others => C_POC_NUL); + function to_string(f : FREQ; precision : natural) return string is + variable unit : string(1 to 3) := (others => C_POC_NUL); variable value : REAL; begin if (f < 1 kHz) then @@ -1014,8 +1063,8 @@ package body physical is return str_format(value, precision) & " " & str_trim(unit); end function; - function to_string(br : BAUD; precision : NATURAL) return STRING is - variable unit : STRING(1 to 3) := (others => C_POC_NUL); + function to_string(br : BAUD; precision : natural) return string is + variable unit : string(1 to 3) := (others => C_POC_NUL); variable value : REAL; begin if (br < 1 kBd) then @@ -1035,8 +1084,8 @@ package body physical is return str_format(value, precision) & " " & str_trim(unit); end function; - function to_string(mem : MEMORY; precision : NATURAL) return STRING is - variable unit : STRING(1 to 3) := (others => C_POC_NUL); + function to_string(mem : MEMORY; precision : natural) return string is + variable unit : string(1 to 3) := (others => C_POC_NUL); variable value : REAL; begin if (mem < 1 KiB) then diff --git a/src/common/protected.v08.vhdl b/src/common/protected.v08.vhdl index b4176dd1..edc86a65 100644 --- a/src/common/protected.v08.vhdl +++ b/src/common/protected.v08.vhdl @@ -1,18 +1,17 @@ -- EMACS settings: -*- tab-width: 2;indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2;replace-tabs off;indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- -- Package: Protected type implementations. -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -42,9 +41,9 @@ package ProtectedTypes is -- =========================================================================== type P_BOOLEAN is protected procedure Clear; - procedure Set(Value : BOOLEAN := TRUE); - impure function Get return BOOLEAN; - impure function Toggle return BOOLEAN; + procedure Set(Value : boolean := TRUE); + impure function Get return boolean; + impure function Toggle return boolean; end protected; -- protected INTEGER implementation @@ -52,12 +51,12 @@ package ProtectedTypes is -- TODO: Mult, Div, Pow, Mod, Rem type P_INTEGER is protected procedure Clear; - procedure Set(Value : INTEGER); - impure function Get return INTEGER; - procedure Add(Value : INTEGER); - impure function Add(Value : INTEGER) return INTEGER; - procedure Sub(Value : INTEGER); - impure function Sub(Value : INTEGER) return INTEGER; + procedure Set(Value : integer); + impure function Get return integer; + procedure Add(Value : integer); + impure function Add(Value : integer) return integer; + procedure Sub(Value : integer); + impure function Sub(Value : integer) return integer; end protected; -- protected NATURAL implementation @@ -65,12 +64,12 @@ package ProtectedTypes is -- TODO: Mult, Div, Pow, Mod, Rem type P_NATURAL is protected procedure Clear; - procedure Set(Value : NATURAL); - impure function Get return NATURAL; - procedure Add(Value : NATURAL); - impure function Add(Value : NATURAL) return NATURAL; - procedure Sub(Value : NATURAL); - impure function Sub(Value : NATURAL) return NATURAL; + procedure Set(Value : natural); + impure function Get return natural; + procedure Add(Value : natural); + impure function Add(Value : natural) return natural; + procedure Sub(Value : natural); + impure function Sub(Value : natural) return natural; end protected; -- protected POSITIVE implementation @@ -78,12 +77,12 @@ package ProtectedTypes is -- TODO: Mult, Div, Pow, Mod, Rem type P_POSITIVE is protected procedure Clear; - procedure Set(Value : POSITIVE); - impure function Get return POSITIVE; - procedure Add(Value : POSITIVE); - impure function Add(Value : POSITIVE) return POSITIVE; - procedure Sub(Value : POSITIVE); - impure function Sub(Value : POSITIVE) return POSITIVE; + procedure Set(Value : positive); + impure function Get return positive; + procedure Add(Value : positive); + impure function Add(Value : positive) return positive; + procedure Sub(Value : positive); + impure function Sub(Value : positive) return positive; end protected; -- protected REAL implementation @@ -105,24 +104,24 @@ package body ProtectedTypes is -- protected BOOLEAN implementation -- =========================================================================== type P_BOOLEAN is protected body - variable InnerValue : BOOLEAN := FALSE; + variable InnerValue : boolean := FALSE; procedure Clear is begin InnerValue := FALSE; end procedure; - procedure Set(Value : BOOLEAN := TRUE) is + procedure Set(Value : boolean := TRUE) is begin InnerValue := Value; end procedure; - impure function Get return BOOLEAN is + impure function Get return boolean is begin return InnerValue; end function; - impure function Toggle return BOOLEAN is + impure function Toggle return boolean is begin InnerValue := not InnerValue; return InnerValue; @@ -132,40 +131,40 @@ package body ProtectedTypes is -- protected INTEGER implementation -- =========================================================================== type P_INTEGER is protected body - variable InnerValue : INTEGER := 0; + variable InnerValue : integer := 0; procedure Clear is begin InnerValue := 0; end procedure; - procedure Set(Value : INTEGER) is + procedure Set(Value : integer) is begin InnerValue := Value; end procedure; - impure function Get return INTEGER is + impure function Get return integer is begin return InnerValue; end function; - procedure Add(Value : INTEGER) is + procedure Add(Value : integer) is begin InnerValue := InnerValue + Value; end procedure; - impure function Add(Value : INTEGER) return INTEGER is + impure function Add(Value : integer) return integer is begin Add(Value); return InnerValue; end function; - procedure Sub(Value : INTEGER) is + procedure Sub(Value : integer) is begin InnerValue := InnerValue - Value; end procedure; - impure function Sub(Value : INTEGER) return INTEGER is + impure function Sub(Value : integer) return integer is begin Sub(Value); return InnerValue; @@ -175,40 +174,40 @@ package body ProtectedTypes is -- protected NATURAL implementation -- =========================================================================== type P_NATURAL is protected body - variable InnerValue : NATURAL := 0; + variable InnerValue : natural := 0; procedure Clear is begin InnerValue := 0; end procedure; - procedure Set(Value : NATURAL) is + procedure Set(Value : natural) is begin InnerValue := Value; end procedure; - impure function Get return NATURAL is + impure function Get return natural is begin return InnerValue; end function; - procedure Add(Value : NATURAL) is + procedure Add(Value : natural) is begin InnerValue := InnerValue + Value; end procedure; - impure function Add(Value : NATURAL) return NATURAL is + impure function Add(Value : natural) return natural is begin Add(Value); return InnerValue; end function; - procedure Sub(Value : NATURAL) is + procedure Sub(Value : natural) is begin InnerValue := InnerValue - Value; end procedure; - impure function Sub(Value : NATURAL) return NATURAL is + impure function Sub(Value : natural) return natural is begin Sub(Value); return InnerValue; @@ -218,40 +217,40 @@ package body ProtectedTypes is -- protected POSITIVE implementation -- =========================================================================== type P_POSITIVE is protected body - variable InnerValue : POSITIVE := 1; + variable InnerValue : positive := 1; procedure Clear is begin InnerValue := 1; end procedure; - procedure Set(Value : POSITIVE) is + procedure Set(Value : positive) is begin InnerValue := Value; end procedure; - impure function Get return POSITIVE is + impure function Get return positive is begin return InnerValue; end function; - procedure Add(Value : POSITIVE) is + procedure Add(Value : positive) is begin InnerValue := InnerValue + Value; end procedure; - impure function Add(Value : POSITIVE) return POSITIVE is + impure function Add(Value : positive) return positive is begin Add(Value); return InnerValue; end function; - procedure Sub(Value : POSITIVE) is + procedure Sub(Value : positive) is begin InnerValue := InnerValue - Value; end procedure; - impure function Sub(Value : POSITIVE) return POSITIVE is + impure function Sub(Value : positive) return positive is begin Sub(Value); return InnerValue; diff --git a/src/common/strings.vhdl b/src/common/strings.vhdl index a5a2a1df..d7f7ad42 100644 --- a/src/common/strings.vhdl +++ b/src/common/strings.vhdl @@ -1,8 +1,7 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Thomas B. Preusser -- Martin Zabel -- Patrick Lehmann @@ -10,11 +9,11 @@ -- Package: String related functions and types -- -- Description: --- ------------------------------------ +-- ------------------------------------- -- For detailed documentation see below. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -55,23 +54,23 @@ package strings is -- Solution: -- PoC uses backtick "`" as a fill and termination symbol, if a Quartus-II -- synthesis environment is detected. - constant C_POC_NUL : CHARACTER := ite((SYNTHESIS_TOOL /= SYNTHESIS_TOOL_ALTERA_QUARTUS2), NUL, '`'); + constant C_POC_NUL : character := ite((SYNTHESIS_TOOL /= SYNTHESIS_TOOL_ALTERA_QUARTUS2), NUL, '`'); -- Type declarations -- =========================================================================== - subtype T_RAWCHAR is STD_LOGIC_VECTOR(7 downto 0); - type T_RAWSTRING is array (NATURAL range <>) of T_RAWCHAR; + subtype T_RAWCHAR is std_logic_vector(7 downto 0); + type T_RAWSTRING is array (natural range <>) of T_RAWCHAR; -- testing area: -- =========================================================================== - function to_IPStyle(str : STRING) return T_IPSTYLE; + function to_IPStyle(str : string) return T_IPSTYLE; -- to_char - function to_char(Value : STD_LOGIC) return CHARACTER; - function to_char(rawchar : T_RAWCHAR) return CHARACTER; + function to_char(Value : std_logic) return character; + function to_char(rawchar : T_RAWCHAR) return character; - function to_HexChar(Value : NATURAL) return CHARACTER; - function to_HexChar(Value : UNSIGNED) return CHARACTER; + function to_HexChar(Value : natural) return character; + function to_HexChar(Value : unsigned) return character; -- chr_is* function function chr_isDigit(chr : character) return boolean; @@ -85,36 +84,36 @@ package strings is function chr_isAlpha(chr : character) return boolean; -- raw_format_* functions - function raw_format_bool_bin(Value : BOOLEAN) return STRING; - function raw_format_bool_chr(Value : BOOLEAN) return STRING; - function raw_format_bool_str(Value : BOOLEAN) return STRING; - function raw_format_slv_bin(slv : STD_LOGIC_VECTOR) return STRING; - function raw_format_slv_oct(slv : STD_LOGIC_VECTOR) return STRING; - function raw_format_slv_dec(slv : STD_LOGIC_VECTOR) return STRING; - function raw_format_slv_hex(slv : STD_LOGIC_VECTOR) return STRING; - function raw_format_nat_bin(Value : NATURAL) return STRING; - function raw_format_nat_oct(Value : NATURAL) return STRING; - function raw_format_nat_dec(Value : NATURAL) return STRING; - function raw_format_nat_hex(Value : NATURAL) return STRING; + function raw_format_bool_bin(Value : boolean) return string; + function raw_format_bool_chr(Value : boolean) return string; + function raw_format_bool_str(Value : boolean) return string; + function raw_format_slv_bin(slv : std_logic_vector) return string; + function raw_format_slv_oct(slv : std_logic_vector) return string; + function raw_format_slv_dec(slv : std_logic_vector) return string; + function raw_format_slv_hex(slv : std_logic_vector) return string; + function raw_format_nat_bin(Value : natural) return string; + function raw_format_nat_oct(Value : natural) return string; + function raw_format_nat_dec(Value : natural) return string; + function raw_format_nat_hex(Value : natural) return string; -- str_format_* functions - function str_format(Value : REAL; precision : NATURAL := 3) return STRING; + function str_format(Value : REAL; precision : natural := 3) return string; -- to_string - function to_string(Value : BOOLEAN) return STRING; - function to_string(Value : INTEGER; base : POSITIVE := 10) return STRING; - function to_string(slv : STD_LOGIC_VECTOR; format : CHARACTER; Length : NATURAL := 0; fill : CHARACTER := '0') return STRING; - function to_string(rawstring : T_RAWSTRING) return STRING; - function to_string(Value : T_BCD_VECTOR) return STRING; + function to_string(Value : boolean) return string; + function to_string(Value : integer; base : positive := 10) return string; + function to_string(slv : std_logic_vector; format : character; Length : natural := 0; fill : character := '0') return string; + function to_string(rawstring : T_RAWSTRING) return string; + function to_string(Value : T_BCD_VECTOR) return string; -- to_slv - function to_slv(rawstring : T_RAWSTRING) return STD_LOGIC_VECTOR; + function to_slv(rawstring : T_RAWSTRING) return std_logic_vector; -- digit subtypes incl. error Value (-1) - subtype T_DIGIT_BIN is INTEGER range -1 to 1; - subtype T_DIGIT_OCT is INTEGER range -1 to 7; - subtype T_DIGIT_DEC is INTEGER range -1 to 9; - subtype T_DIGIT_HEX is INTEGER range -1 to 15; + subtype T_DIGIT_BIN is integer range -1 to 1; + subtype T_DIGIT_OCT is integer range -1 to 7; + subtype T_DIGIT_DEC is integer range -1 to 9; + subtype T_DIGIT_HEX is integer range -1 to 15; -- to_digit* function to_digit_bin(chr : character) return T_DIGIT_BIN; @@ -124,18 +123,18 @@ package strings is function to_digit(chr : character; base : character := 'd') return integer; -- to_natural* - function to_natural_bin(str : STRING) return INTEGER; - function to_natural_oct(str : STRING) return INTEGER; - function to_natural_dec(str : STRING) return INTEGER; - function to_natural_hex(str : STRING) return INTEGER; - function to_natural(str : STRING; base : CHARACTER := 'd') return INTEGER; + function to_natural_bin(str : string) return integer; + function to_natural_oct(str : string) return integer; + function to_natural_dec(str : string) return integer; + function to_natural_hex(str : string) return integer; + function to_natural(str : string; base : character := 'd') return integer; -- to_raw* function to_RawChar(char : character) return T_RAWCHAR; function to_RawString(str : string) return T_RAWSTRING; -- resize - function resize(str : STRING; size : POSITIVE; FillChar : CHARACTER := C_POC_NUL) return STRING; + function resize(str : string; size : positive; FillChar : character := C_POC_NUL) return string; -- function resize(rawstr : T_RAWSTRING; size : POSITIVE; FillChar : T_RAWCHAR := x"00") return T_RAWSTRING; -- Character functions @@ -143,34 +142,34 @@ package strings is function chr_toUpper(chr : character) return character; -- String functions - function str_length(str : STRING) return NATURAL; - function str_equal(str1 : STRING; str2 : STRING) return BOOLEAN; - function str_match(str1 : STRING; str2 : STRING) return BOOLEAN; - function str_imatch(str1 : STRING; str2 : STRING) return BOOLEAN; - function str_pos(str : STRING; chr : CHARACTER; start : NATURAL := 0) return INTEGER; - function str_pos(str : STRING; pattern : STRING; start : NATURAL := 0) return INTEGER; - function str_ipos(str : STRING; chr : CHARACTER; start : NATURAL := 0) return INTEGER; - function str_ipos(str : STRING; pattern : STRING; start : NATURAL := 0) return INTEGER; - function str_find(str : STRING; chr : CHARACTER) return BOOLEAN; - function str_find(str : STRING; pattern : STRING) return BOOLEAN; - function str_ifind(str : STRING; chr : CHARACTER) return BOOLEAN; - function str_ifind(str : STRING; pattern : STRING) return BOOLEAN; - function str_replace(str : STRING; pattern : STRING; replace : STRING) return STRING; - function str_substr(str : STRING; start : INTEGER := 0; Length : INTEGER := 0) return STRING; - function str_ltrim(str : STRING; char : CHARACTER := ' ') return STRING; - function str_rtrim(str : STRING; char : CHARACTER := ' ') return STRING; - function str_trim(str : STRING) return STRING; - function str_calign(str : STRING; Length : NATURAL; FillChar : CHARACTER := ' ') return STRING; - function str_lalign(str : STRING; Length : NATURAL; FillChar : CHARACTER := ' ') return STRING; - function str_ralign(str : STRING; Length : NATURAL; FillChar : CHARACTER := ' ') return STRING; - function str_toLower(str : STRING) return STRING; - function str_toUpper(str : STRING) return STRING; + function str_length(str : string) return natural; + function str_equal(str1 : string; str2 : string) return boolean; + function str_match(str1 : string; str2 : string) return boolean; + function str_imatch(str1 : string; str2 : string) return boolean; + function str_pos(str : string; chr : character; start : natural := 0) return integer; + function str_pos(str : string; pattern : string; start : natural := 0) return integer; + function str_ipos(str : string; chr : character; start : natural := 0) return integer; + function str_ipos(str : string; pattern : string; start : natural := 0) return integer; + function str_find(str : string; chr : character) return boolean; + function str_find(str : string; pattern : string) return boolean; + function str_ifind(str : string; chr : character) return boolean; + function str_ifind(str : string; pattern : string) return boolean; + function str_replace(str : string; pattern : string; replace : string) return string; + function str_substr(str : string; start : integer := 0; Length : integer := 0) return string; + function str_ltrim(str : string; char : character := ' ') return string; + function str_rtrim(str : string; char : character := ' ') return string; + function str_trim(str : string) return string; + function str_calign(str : string; Length : natural; FillChar : character := ' ') return string; + function str_lalign(str : string; Length : natural; FillChar : character := ' ') return string; + function str_ralign(str : string; Length : natural; FillChar : character := ' ') return string; + function str_toLower(str : string) return string; + function str_toUpper(str : string) return string; end package; package body strings is -- - function to_IPStyle(str : STRING) return T_IPSTYLE is + function to_IPStyle(str : string) return T_IPSTYLE is begin for i in T_IPSTYLE'pos(T_IPSTYLE'low) to T_IPSTYLE'pos(T_IPSTYLE'high) loop if str_imatch(str, T_IPSTYLE'image(T_IPSTYLE'val(i))) then @@ -183,9 +182,9 @@ package body strings is -- to_char -- =========================================================================== - function to_char(Value : STD_LOGIC) return CHARACTER is + function to_char(Value : std_logic) return character is begin - case Value IS + case Value is when 'U' => return 'U'; when 'X' => return 'X'; when '0' => return '0'; @@ -199,20 +198,19 @@ package body strings is end case; end function; - function to_char(rawchar : T_RAWCHAR) return CHARACTER is + function to_char(rawchar : T_RAWCHAR) return character is begin - return CHARACTER'val(to_integer(unsigned(rawchar))); + return character'val(to_integer(unsigned(rawchar))); end function; -- - function to_HexChar(Value : NATURAL) return CHARACTER is - constant HEX : STRING := "0123456789ABCDEF"; + function to_HexChar(Value : natural) return character is + constant HEX : string := "0123456789ABCDEF"; begin return ite(Value < 16, HEX(Value+1), 'X'); end function; - function to_HexChar(Value : UNSIGNED) return CHARACTER is - constant HEX : STRING := "0123456789ABCDEF"; + function to_HexChar(Value : unsigned) return character is begin return to_HexChar(to_integer(Value)); end function; @@ -265,25 +263,25 @@ package body strings is -- raw_format_* functions -- =========================================================================== - function raw_format_bool_bin(Value : BOOLEAN) return STRING is + function raw_format_bool_bin(Value : boolean) return string is begin return ite(Value, "1", "0"); end function; - function raw_format_bool_chr(Value : BOOLEAN) return STRING is + function raw_format_bool_chr(Value : boolean) return string is begin return ite(Value, "T", "F"); end function; - function raw_format_bool_str(Value : BOOLEAN) return STRING is + function raw_format_bool_str(Value : boolean) return string is begin return str_toUpper(boolean'image(Value)); end function; - function raw_format_slv_bin(slv : STD_LOGIC_VECTOR) return STRING is - variable Value : STD_LOGIC_VECTOR(slv'length - 1 downto 0); - variable Result : STRING(1 to slv'length); - variable j : NATURAL; + function raw_format_slv_bin(slv : std_logic_vector) return string is + variable Value : std_logic_vector(slv'length - 1 downto 0); + variable Result : string(1 to slv'length); + variable j : natural; begin -- convert input slv to a downto ranged vector and normalize range to slv'low = 0 Value := movez(ite(slv'ascending, descend(slv), slv)); @@ -296,11 +294,11 @@ package body strings is return Result; end function; - function raw_format_slv_oct(slv : STD_LOGIC_VECTOR) return STRING is - variable Value : STD_LOGIC_VECTOR(slv'length - 1 downto 0); - variable Digit : STD_LOGIC_VECTOR(2 downto 0); - variable Result : STRING(1 to div_ceil(slv'length, 3)); - variable j : NATURAL; + function raw_format_slv_oct(slv : std_logic_vector) return string is + variable Value : std_logic_vector(slv'length - 1 downto 0); + variable Digit : std_logic_vector(2 downto 0); + variable Result : string(1 to div_ceil(slv'length, 3)); + variable j : natural; begin -- convert input slv to a downto ranged vector; normalize range to slv'low = 0 and resize it to a multiple of 3 Value := resize(movez(ite(slv'ascending, descend(slv), slv)), (Result'length * 3)); @@ -315,17 +313,17 @@ package body strings is return Result; end function; - function raw_format_slv_dec(slv : STD_LOGIC_VECTOR) return STRING is - variable Value : STD_LOGIC_VECTOR(slv'length - 1 downto 0); - variable Result : STRING(1 to div_ceil(slv'length, 3)); + function raw_format_slv_dec(slv : std_logic_vector) return string is + variable Value : std_logic_vector(slv'length - 1 downto 0); + variable Result : string(1 to div_ceil(slv'length, 3)); - subtype TT_BCD is INTEGER range 0 to 31; + subtype TT_BCD is integer range 0 to 31; type TT_BCD_VECTOR is array(natural range <>) of TT_BCD; variable Temp : TT_BCD_VECTOR(div_ceil(slv'length, 3) - 1 downto 0); variable Carry : T_UINT_8; - variable Pos : NATURAL; + variable Pos : natural; begin Temp := (others => 0); Pos := 0; @@ -351,11 +349,11 @@ package body strings is return Result(imin(Pos, Result'high) to Result'high); end function; - function raw_format_slv_hex(slv : STD_LOGIC_VECTOR) return STRING is - variable Value : STD_LOGIC_VECTOR(4*div_ceil(slv'length, 4) - 1 downto 0); - variable Digit : STD_LOGIC_VECTOR(3 downto 0); - variable Result : STRING(1 to div_ceil(slv'length, 4)); - variable j : NATURAL; + function raw_format_slv_hex(slv : std_logic_vector) return string is + variable Value : std_logic_vector(4*div_ceil(slv'length, 4) - 1 downto 0); + variable Digit : std_logic_vector(3 downto 0); + variable Result : string(1 to div_ceil(slv'length, 4)); + variable j : natural; begin Value := resize(slv, Value'length); j := 0; @@ -367,38 +365,38 @@ package body strings is return Result; end function; - function raw_format_nat_bin(Value : NATURAL) return STRING is + function raw_format_nat_bin(Value : natural) return string is begin return raw_format_slv_bin(to_slv(Value, log2ceilnz(Value+1))); end function; - function raw_format_nat_oct(Value : NATURAL) return STRING is + function raw_format_nat_oct(Value : natural) return string is begin return raw_format_slv_oct(to_slv(Value, log2ceilnz(Value+1))); end function; - function raw_format_nat_dec(Value : NATURAL) return STRING is + function raw_format_nat_dec(Value : natural) return string is begin - return INTEGER'image(Value); + return integer'image(Value); end function; - function raw_format_nat_hex(Value : NATURAL) return STRING is + function raw_format_nat_hex(Value : natural) return string is begin return raw_format_slv_hex(to_slv(Value, log2ceilnz(Value+1))); end function; -- str_format_* functions -- =========================================================================== - function str_format(Value : REAL; precision : NATURAL := 3) return STRING is + function str_format(Value : REAL; precision : natural := 3) return string is constant s : REAL := sign(Value); constant val : REAL := Value * s; - constant int : INTEGER := integer(floor(val)); - constant frac : INTEGER := integer(round((val - real(int)) * 10.0**precision)); + constant int : integer := integer(floor(val)); + constant frac : integer := integer(round((val - real(int)) * 10.0**precision)); constant overflow : boolean := frac >= 10**precision; - constant int2 : INTEGER := ite(overflow, int+1, int); - constant frac2 : INTEGER := ite(overflow, frac-10**precision, frac); - constant frac_str : STRING := INTEGER'image(frac2); - constant res : STRING := INTEGER'image(int2) & "." & (2 to (precision - frac_str'length + 1) => '0') & frac_str; + constant int2 : integer := ite(overflow, int+1, int); + constant frac2 : integer := ite(overflow, frac-10**precision, frac); + constant frac_str : string := integer'image(frac2); + constant res : string := integer'image(int2) & "." & (2 to (precision - frac_str'length + 1) => '0') & frac_str; begin return ite ((s < 0.0), "-" & res, res); end function; @@ -411,23 +409,23 @@ package body strings is end function; -- convert an integer Value to a STRING using an arbitrary base - function to_string(Value : INTEGER; base : POSITIVE := 10) return STRING is - constant absValue : NATURAL := abs(Value); - constant len : POSITIVE := log10ceilnz(absValue); - variable power : POSITIVE; - variable Result : STRING(1 TO len); + function to_string(Value : integer; base : positive := 10) return string is + constant absValue : natural := abs Value; + constant len : positive := log10ceilnz(absValue); + variable power : positive; + variable Result : string(1 to len); begin power := 1; - if (base = 10) then - return INTEGER'image(Value); + if base = 10 then + return integer'image(Value); else for i in len downto 1 loop Result(i) := to_HexChar(absValue / power mod base); power := power * base; end loop; - if (Value < 0) then + if Value < 0 then return '-' & Result; else return Result; @@ -436,17 +434,17 @@ package body strings is end function; -- QUESTION: rename to slv_format(..) ? - function to_string(slv : STD_LOGIC_VECTOR; format : CHARACTER; Length : NATURAL := 0; fill : CHARACTER := '0') return STRING is - constant int : INTEGER := ite((slv'length <= 31), to_integer(unsigned(resize(slv, 31))), 0); - constant str : STRING := INTEGER'image(int); - constant bin_len : POSITIVE := slv'length; - constant dec_len : POSITIVE := str'length;--log10ceilnz(int); - constant hex_len : POSITIVE := ite(((bin_len mod 4) = 0), (bin_len / 4), (bin_len / 4) + 1); - constant len : NATURAL := ite((format = 'b'), bin_len, + function to_string(slv : std_logic_vector; format : character; Length : natural := 0; fill : character := '0') return string is + constant int : integer := ite((slv'length <= 31), to_integer(unsigned(resize(slv, 31))), 0); + constant str : string := integer'image(int); + constant bin_len : positive := slv'length; + constant dec_len : positive := str'length;--log10ceilnz(int); + constant hex_len : positive := ite(((bin_len mod 4) = 0), (bin_len / 4), (bin_len / 4) + 1); + constant len : natural := ite((format = 'b'), bin_len, ite((format = 'd'), dec_len, ite((format = 'h'), hex_len, 0))); - variable j : NATURAL; - variable Result : STRING(1 to ite((Length = 0), len, imax(len, Length))); + variable j : natural; + variable Result : string(1 to ite((Length = 0), len, imax(len, Length))); begin j := 0; Result := (others => fill); @@ -476,8 +474,8 @@ package body strings is return Result; end function; - function to_string(rawstring : T_RAWSTRING) return STRING is - variable Result : STRING(1 to rawstring'length); + function to_string(rawstring : T_RAWSTRING) return string is + variable Result : string(1 to rawstring'length); begin for i in rawstring'low to rawstring'high loop Result(i - rawstring'low + 1) := to_char(rawstring(i)); @@ -485,8 +483,8 @@ package body strings is return Result; end function; - function to_string(Value : T_BCD_VECTOR) return STRING is - variable Result : STRING(1 to Value'length); + function to_string(Value : T_BCD_VECTOR) return string is + variable Result : string(1 to Value'length); begin for i in Value'range loop Result(Result'high - (i - Value'low)) := to_HexChar(unsigned(Value(i))); @@ -496,8 +494,8 @@ package body strings is -- to_slv -- =========================================================================== - function to_slv(rawstring : T_RAWSTRING) return STD_LOGIC_VECTOR is - variable Result : STD_LOGIC_VECTOR((rawstring'length * 8) - 1 downto 0); + function to_slv(rawstring : T_RAWSTRING) return std_logic_vector is + variable Result : std_logic_vector((rawstring'length * 8) - 1 downto 0); begin for i in rawstring'range loop Result(((i - rawstring'low) * 8) + 7 downto (i - rawstring'low) * 8) := rawstring(i); @@ -508,7 +506,7 @@ package body strings is -- to_digit* -- =========================================================================== -- convert a binary digit given as CHARACTER to a digit returned as NATURAL; return -1 on error - function to_digit_bin(chr : CHARACTER) return T_DIGIT_BIN is + function to_digit_bin(chr : character) return T_DIGIT_BIN is begin case chr is when '0' => return 0; @@ -518,35 +516,35 @@ package body strings is end function; -- convert an octal digit given as CHARACTER to a digit returned as NATURAL; return -1 on error - function to_digit_oct(chr : CHARACTER) return T_DIGIT_OCT is - variable dec : INTEGER; + function to_digit_oct(chr : character) return T_DIGIT_OCT is + variable dec : integer; begin dec := to_digit_dec(chr); return ite((dec < 8), dec, -1); end function; -- convert a adecimal digit given as CHARACTER to a digit returned as NATURAL; return -1 on error - function to_digit_dec(chr : CHARACTER) return T_DIGIT_DEC is + function to_digit_dec(chr : character) return T_DIGIT_DEC is begin if chr_isDigit(chr) then - return CHARACTER'pos(chr) - CHARACTER'pos('0'); + return character'pos(chr) - CHARACTER'pos('0'); else return -1; end if; end function; -- convert a hexadecimal digit given as CHARACTER to a digit returned as NATURAL; return -1 on error - function to_digit_hex(chr : CHARACTER) return T_DIGIT_HEX is + function to_digit_hex(chr : character) return T_DIGIT_HEX is begin - if chr_isDigit(chr) then return CHARACTER'pos(chr) - CHARACTER'pos('0'); - elsif chr_isLowerHexDigit(chr) then return CHARACTER'pos(chr) - CHARACTER'pos('a') + 10; - elsif chr_isUpperHexDigit(chr) then return CHARACTER'pos(chr) - CHARACTER'pos('A') + 10; + if chr_isDigit(chr) then return character'pos(chr) - CHARACTER'pos('0'); + elsif chr_isLowerHexDigit(chr) then return character'pos(chr) - CHARACTER'pos('a') + 10; + elsif chr_isUpperHexDigit(chr) then return character'pos(chr) - CHARACTER'pos('A') + 10; else return -1; end if; end function; -- convert a digit given as CHARACTER to a digit returned as NATURAL; return -1 on error - function to_digit(chr : CHARACTER; base : CHARACTER := 'd') return integer is + function to_digit(chr : character; base : character := 'd') return integer is begin case base is when 'b' => return to_digit_bin(chr); @@ -560,13 +558,13 @@ package body strings is -- to_natural* -- =========================================================================== -- convert a binary number given as STRING to a NATURAL; return -1 on error - function to_natural_bin(str : STRING) return INTEGER is - variable Result : NATURAL; - variable Digit : INTEGER; + function to_natural_bin(str : string) return integer is + variable Result : natural; + variable Digit : integer; begin for i in str'range loop Digit := to_digit_bin(str(i)); - if (Digit /= -1) then + if Digit /= -1 then Result := Result * 2 + Digit; else return -1; @@ -576,13 +574,13 @@ package body strings is end function; -- convert an octal number given as STRING to a NATURAL; return -1 on error - function to_natural_oct(str : STRING) return INTEGER is - variable Result : NATURAL; - variable Digit : INTEGER; + function to_natural_oct(str : string) return integer is + variable Result : natural; + variable Digit : integer; begin for i in str'range loop Digit := to_digit_oct(str(i)); - if (Digit /= -1) then + if Digit /= -1 then Result := Result * 8 + Digit; else return -1; @@ -592,9 +590,9 @@ package body strings is end function; -- convert a decimal number given as STRING to a NATURAL; return -1 on error - function to_natural_dec(str : STRING) return INTEGER is - variable Result : NATURAL; - variable Digit : INTEGER; + function to_natural_dec(str : string) return integer is + variable Result : natural; + variable Digit : integer; begin -- WORKAROUND: Xilinx Vivado Synth -- Version: 2014.1 @@ -604,7 +602,7 @@ package body strings is -- implement a manual conversion using shift and multiply for i in str'range loop Digit := to_digit_dec(str(i)); - if (Digit /= -1) then + if Digit /= -1 then Result := Result * 10 + Digit; else return -1; @@ -614,13 +612,13 @@ package body strings is end function; -- convert a hexadecimal number given as STRING to a NATURAL; return -1 on error - function to_natural_hex(str : STRING) return INTEGER is - variable Result : NATURAL; - variable Digit : INTEGER; + function to_natural_hex(str : string) return integer is + variable Result : natural; + variable Digit : integer; begin for i in str'range loop Digit := to_digit_hex(str(i)); - if (Digit /= -1) then + if Digit /= -1 then Result := Result * 16 + Digit; else return -1; @@ -630,7 +628,7 @@ package body strings is end function; -- convert a number given as STRING to a NATURAL; return -1 on error - function to_natural(str : STRING; base : CHARACTER := 'd') return INTEGER is + function to_natural(str : string; base : character := 'd') return integer is begin case base is when 'b' => return to_natural_bin(str); @@ -644,13 +642,13 @@ package body strings is -- to_raw* -- =========================================================================== -- convert a CHARACTER to a RAWCHAR - function to_RawChar(char : CHARACTER) return T_RAWCHAR is + function to_RawChar(char : character) return T_RAWCHAR is begin - return std_logic_vector(to_unsigned(CHARACTER'pos(char), T_RAWCHAR'length)); + return std_logic_vector(to_unsigned(character'pos(char), T_RAWCHAR'length)); end function; -- convert a STRING to a RAWSTRING - function to_RawString(str : STRING) return T_RAWSTRING is + function to_RawString(str : string) return T_RAWSTRING is variable Result : T_RAWSTRING(0 to str'length - 1); begin for i in str'low to str'high loop @@ -661,16 +659,16 @@ package body strings is -- resize -- =========================================================================== - function resize(str : STRING; Size : POSITIVE; FillChar : CHARACTER := C_POC_NUL) return STRING is - constant ConstNUL : STRING(1 to 1) := (others => C_POC_NUL); - variable Result : STRING(1 to Size); + function resize(str : string; Size : positive; FillChar : character := C_POC_NUL) return string is + constant ConstNUL : string(1 to 1) := (others => C_POC_NUL); + variable Result : string(1 to Size); begin Result := (others => FillChar); if (str'length > 0) then -- WORKAROUND: for Altera Quartus-II -- Version: 15.0 - -- Issue: array bounds are check regardless of the hierachy and control flow - Result(1 to imin(Size, imax(1, str'length))) := ite((str'length > 0), str(1 to imin(Size, str'length)), ConstNUL); + -- Issue: array bounds are check regardless of the hierarchy and control flow + Result(1 to bound(Size, 1, str'length)) := ite((str'length > 0), str(1 to imin(Size, str'length)), ConstNUL); end if; return Result; end function; @@ -720,10 +718,10 @@ package body strings is -- String functions -- =========================================================================== -- count the length of a POC_NUL terminated STRING - function str_length(str : STRING) return NATURAL is + function str_length(str : string) return natural is begin for i in str'range loop - if (str(i) = C_POC_NUL) then + if str(i) = C_POC_NUL then return i - str'low; end if; end loop; @@ -731,9 +729,9 @@ package body strings is end function; -- compare two STRINGs for equality - -- pre-check the string lengthes to suppress warnings for unqual sized string comparisions. + -- pre-check the string lengthes to suppress warnings for unqual sized string comparisons. -- QUESTION: overload "=" operator? - function str_equal(str1 : STRING; str2 : STRING) return BOOLEAN is + function str_equal(str1 : string; str2 : string) return boolean is begin if str1'length /= str2'length then return FALSE; @@ -743,8 +741,8 @@ package body strings is end function; -- compare two POC_NUL terminated STRINGs - function str_match(str1 : STRING; str2 : STRING) return BOOLEAN is - constant len : NATURAL := imin(str1'length, str2'length); + function str_match(str1 : string; str2 : string) return boolean is + constant len : natural := imin(str1'length, str2'length); begin -- if both strings are empty if ((str1'length = 0 ) and (str2'length = 0)) then return TRUE; end if; @@ -765,17 +763,17 @@ package body strings is end function; -- compare two POC_NUL terminated STRINGs; case insentitve - function str_imatch(str1 : STRING; str2 : STRING) return BOOLEAN is + function str_imatch(str1 : string; str2 : string) return boolean is begin return str_match(str_toLower(str1), str_toLower(str2)); end function; -- search for chr in a STRING and return the position; return -1 on error - function str_pos(str : STRING; chr : CHARACTER; start : NATURAL := 0) return INTEGER is + function str_pos(str : string; chr : character; start : natural := 0) return integer is begin for i in imax(str'low, start) to str'high loop exit when (str(i) = C_POC_NUL); - if (str(i) = chr) then + if str(i) = chr then return i; end if; end loop; @@ -784,7 +782,7 @@ package body strings is -- search for pattern in a STRING and return the position; return -1 on error -- QUESTION: implement KMP algorithm? - function str_pos(str : STRING; pattern : STRING; start : NATURAL := 0) return INTEGER is + function str_pos(str : string; pattern : string; start : natural := 0) return integer is begin for i in imax(str'low, start) to (str'high - pattern'length + 1) loop exit when (str(i) = C_POC_NUL); @@ -796,13 +794,13 @@ package body strings is end function; -- search for chr in a STRING and return the position; case insentitve; return -1 on error - function str_ipos(str : STRING; chr : CHARACTER; start : NATURAL := 0) return INTEGER is + function str_ipos(str : string; chr : character; start : natural := 0) return integer is begin return str_pos(str_toLower(str), chr_toLower(chr)); end function; -- search for pattern in a STRING and return the position; case insentitve; return -1 on error - function str_ipos(str : STRING; pattern : STRING; start : NATURAL := 0) return INTEGER is + function str_ipos(str : string; pattern : string; start : natural := 0) return integer is begin return str_pos(str_toLower(str), str_toLower(pattern)); end function; @@ -840,36 +838,36 @@ package body strings is -- end function; -- check if chr exists in STRING str - function str_find(str : STRING; chr : CHARACTER) return boolean is + function str_find(str : string; chr : character) return boolean is begin return (str_pos(str, chr) > 0); end function; -- check if pattern exists in STRING str - function str_find(str : STRING; pattern : STRING) return boolean is + function str_find(str : string; pattern : string) return boolean is begin return (str_pos(str, pattern) > 0); end function; -- check if chr exists in STRING str; case insentitve - function str_ifind(str : STRING; chr : CHARACTER) return boolean is + function str_ifind(str : string; chr : character) return boolean is begin return (str_ipos(str, chr) > 0); end function; -- check if pattern exists in STRING str; case insentitve - function str_ifind(str : STRING; pattern : STRING) return boolean is + function str_ifind(str : string; pattern : string) return boolean is begin return (str_ipos(str, pattern) > 0); end function; -- replace a pattern in a STRING str by the STRING replace - function str_replace(str : STRING; pattern : STRING; replace : STRING) return STRING is - variable pos : INTEGER; + function str_replace(str : string; pattern : string; replace : string) return string is + variable pos : integer; begin pos := str_pos(str, pattern); - if (pos > 0) then - if (pos = 1) then + if pos > 0 then + if pos = 1 then return replace & str(pattern'length + 1 to str'length); elsif (pos = str'length - pattern'length + 1) then return str(1 to str'length - pattern'length) & replace; @@ -891,21 +889,21 @@ package body strings is -- str_substr("Hello World.", 7, 0) => "World." - copy from pos 7 to end of string -- str_substr("Hello World.", 7, 5) => "World" - copy from pos 7 for 5 characters -- str_substr("Hello World.", 0, -7) => "Hello World." - copy all until character 8 from right boundary - function str_substr(str : STRING; start : INTEGER := 0; Length : INTEGER := 0) return STRING is + function str_substr(str : string; start : integer := 0; Length : integer := 0) return string is variable StartOfString : positive; variable EndOfString : positive; begin - if (start < 0) then -- start is negative -> start substring at right string boundary + if start < 0 then -- start is negative -> start substring at right string boundary StartOfString := str'high + start + 1; - elsif (start = 0) then -- start is zero -> start substring at left string boundary + elsif start = 0 then -- start is zero -> start substring at left string boundary StartOfString := str'low; else -- start is positive -> start substring at left string boundary + offset StartOfString := start; end if; - if (Length < 0) then -- Length is negative -> end substring at length'th character before right string boundary + if Length < 0 then -- Length is negative -> end substring at length'th character before right string boundary EndOfString := str'high + Length; - elsif (Length = 0) then -- Length is zero -> end substring at right string boundary + elsif Length = 0 then -- Length is zero -> end substring at right string boundary EndOfString := str'high; else -- Length is positive -> end substring at StartOfString + Length EndOfString := StartOfString + Length - 1; @@ -918,10 +916,10 @@ package body strings is end function; -- left-trim the STRING str - function str_ltrim(str : STRING; char : CHARACTER := ' ') return STRING is + function str_ltrim(str : string; char : character := ' ') return string is begin for i in str'range loop - if (str(i) /= char) then + if str(i) /= char then return str(i to str'high); end if; end loop; @@ -929,10 +927,10 @@ package body strings is end function; -- right-trim the STRING str - function str_rtrim(str : STRING; char : CHARACTER := ' ') return STRING is + function str_rtrim(str : string; char : character := ' ') return string is begin for i in str'reverse_range loop - if (str(i) /= char) then + if str(i) /= char then return str(str'low to i); end if; end loop; @@ -940,15 +938,15 @@ package body strings is end function; -- remove POC_NUL string termination characters - function str_trim(str : STRING) return STRING is + function str_trim(str : string) return string is begin return str(str'low to str'low + str_length(str) - 1); end function; -- center-align a STRING str in a FillChar filled STRING of length Length - function str_calign(str : STRING; Length : NATURAL; FillChar : CHARACTER := ' ') return STRING is - constant Start : POSITIVE := (Length - str'length) / 2; - variable Result : STRING(1 to Length); + function str_calign(str : string; Length : natural; FillChar : character := ' ') return string is + constant Start : positive := (Length - str'length) / 2; + variable Result : string(1 to Length); begin Result := (others => FillChar); Result(Start to (Start + str'length)) := str; @@ -956,8 +954,8 @@ package body strings is end function; -- left-align a STRING str in a FillChar filled STRING of length Length - function str_lalign(str : STRING; Length : NATURAL; FillChar : CHARACTER := ' ') return STRING is - variable Result : STRING(1 to Length); + function str_lalign(str : string; Length : natural; FillChar : character := ' ') return string is + variable Result : string(1 to Length); begin Result := (others => FillChar); Result(1 to str'length) := str; @@ -965,8 +963,8 @@ package body strings is end function; -- right-align a STRING str in a FillChar filled STRING of length Length - function str_ralign(str : STRING; Length : NATURAL; FillChar : CHARACTER := ' ') return STRING is - variable Result : STRING(1 to Length); + function str_ralign(str : string; Length : natural; FillChar : character := ' ') return string is + variable Result : string(1 to Length); begin Result := (others => FillChar); Result((Length - str'length + 1) to Length) := str; @@ -974,8 +972,8 @@ package body strings is end function; -- convert an upper case STRING into a lower case STRING - function str_toLower(str : STRING) return STRING is - variable Result : STRING(str'range); + function str_toLower(str : string) return string is + variable Result : string(str'range); begin for i in str'range loop Result(i) := chr_toLower(str(i)); @@ -984,8 +982,8 @@ package body strings is end function; -- convert a lower case STRING into an upper case STRING - function str_toUpper(str : STRING) return STRING is - variable Result : STRING(str'range); + function str_toUpper(str : string) return string is + variable Result : string(str'range); begin for i in str'range loop Result(i) := chr_toUpper(str(i)); diff --git a/src/common/utils.vhdl b/src/common/utils.vhdl index 5ae6fb75..e6a4d3e7 100644 --- a/src/common/utils.vhdl +++ b/src/common/utils.vhdl @@ -1,20 +1,20 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ --- Package: Common functions and types --- +-- ============================================================================= -- Authors: Thomas B. Preusser -- Martin Zabel -- Patrick Lehmann +-- Paul Genssler +-- +-- Package: Common functions and types -- -- Description: --- ------------------------------------ +-- ------------------------------------- -- For detailed documentation see below. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -29,43 +29,35 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; - -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use IEEE.math_real.all; - -library PoC; -use PoC.my_config.all; - +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use IEEE.math_real.all; package utils is - -- PoC settings - -- ========================================================================== - constant POC_VERBOSE : BOOLEAN := MY_VERBOSE; -- Environment -- ========================================================================== -- Distinguishes simulation from synthesis - constant SIMULATION : BOOLEAN; -- deferred constant declaration + constant SIMULATION : boolean; -- deferred constant declaration -- Type declarations -- ========================================================================== --+ Vectors of primitive standard types +++++++++++++++++++++++++++++++++++++ - type T_BOOLVEC is array(NATURAL range <>) of BOOLEAN; - type T_INTVEC is array(NATURAL range <>) of INTEGER; - type T_NATVEC is array(NATURAL range <>) of NATURAL; - type T_POSVEC is array(NATURAL range <>) of POSITIVE; - type T_REALVEC is array(NATURAL range <>) of REAL; + type T_BOOLVEC is array(natural range <>) of boolean; + type T_INTVEC is array(natural range <>) of integer; + type T_NATVEC is array(natural range <>) of natural; + type T_POSVEC is array(natural range <>) of positive; + type T_REALVEC is array(natural range <>) of REAL; --+ Integer subranges sometimes useful for speeding up simulation ++++++++++ - subtype T_INT_8 is INTEGER range -128 to 127; - subtype T_INT_16 is INTEGER range -32768 to 32767; - subtype T_UINT_8 is INTEGER range 0 to 255; - subtype T_UINT_16 is INTEGER range 0 to 65535; + subtype T_INT_8 is integer range -128 to 127; + subtype T_INT_16 is integer range -32768 to 32767; + subtype T_UINT_8 is integer range 0 to 255; + subtype T_UINT_16 is integer range 0 to 65535; --+ Enums ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- Intellectual Property (IP) type @@ -84,7 +76,7 @@ package utils is -- QUESTION: extract to an own BCD package? -- => overloaded operators for +/-/=/... and conversion functions type T_BCD is array(3 downto 0) of std_logic; - type T_BCD_VECTOR is array(NATURAL range <>) of T_BCD; + type T_BCD_VECTOR is array(natural range <>) of T_BCD; constant C_BCD_MINUS : T_BCD := "1010"; constant C_BCD_OFF : T_BCD := "1011"; @@ -94,15 +86,15 @@ package utils is --+ Division ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- Calculates: ceil(a / b) - function div_ceil(a : NATURAL; b : POSITIVE) return NATURAL; + function div_ceil(a : natural; b : positive) return natural; --+ Power +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- is input a power of 2? - function is_pow2(int : NATURAL) return BOOLEAN; + function is_pow2(int : natural) return boolean; -- round to next power of 2 - function ceil_pow2(int : NATURAL) return POSITIVE; + function ceil_pow2(int : natural) return positive; -- round to previous power of 2 - function floor_pow2(int : NATURAL) return NATURAL; + function floor_pow2(int : natural) return natural; --+ Logarithm ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- Calculates: ceil(ld(arg)) @@ -110,45 +102,45 @@ package utils is -- Calculates: max(1, ceil(ld(arg))) function log2ceilnz(arg : positive) return positive; -- Calculates: ceil(lg(arg)) - function log10ceil(arg : POSITIVE) return NATURAL; + function log10ceil(arg : positive) return natural; -- Calculates: max(1, ceil(lg(arg))) - function log10ceilnz(arg : POSITIVE) return POSITIVE; + function log10ceilnz(arg : positive) return positive; --+ if-then-else (ite) +++++++++++++++++++++++++++++++++++++++++++++++++++++ - function ite(cond : BOOLEAN; value1 : BOOLEAN; value2 : BOOLEAN) return BOOLEAN; - function ite(cond : BOOLEAN; value1 : INTEGER; value2 : INTEGER) return INTEGER; - function ite(cond : BOOLEAN; value1 : REAL; value2 : REAL) return REAL; - function ite(cond : BOOLEAN; value1 : STD_LOGIC; value2 : STD_LOGIC) return STD_LOGIC; - function ite(cond : BOOLEAN; value1 : STD_LOGIC_VECTOR; value2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; - function ite(cond : BOOLEAN; value1 : BIT_VECTOR; value2 : BIT_VECTOR) return BIT_VECTOR; - function ite(cond : BOOLEAN; value1 : UNSIGNED; value2 : UNSIGNED) return UNSIGNED; - function ite(cond : BOOLEAN; value1 : CHARACTER; value2 : CHARACTER) return CHARACTER; - function ite(cond : BOOLEAN; value1 : STRING; value2 : STRING) return STRING; + function ite(cond : boolean; value1 : boolean; value2 : boolean) return boolean; + function ite(cond : boolean; value1 : integer; value2 : integer) return integer; + function ite(cond : boolean; value1 : REAL; value2 : REAL) return REAL; + function ite(cond : boolean; value1 : std_logic; value2 : std_logic) return std_logic; + function ite(cond : boolean; value1 : std_logic_vector; value2 : std_logic_vector) return std_logic_vector; + function ite(cond : boolean; value1 : bit_vector; value2 : bit_vector) return bit_vector; + function ite(cond : boolean; value1 : unsigned; value2 : unsigned) return unsigned; + function ite(cond : boolean; value1 : character; value2 : character) return character; + function ite(cond : boolean; value1 : string; value2 : string) return string; -- conditional increment / decrement - function inc(cond : BOOLEAN; value : INTEGER; increment : INTEGER := 1) return INTEGER; - function dec(cond : BOOLEAN; value : INTEGER; decrement : INTEGER := 1) return INTEGER; + function inc_if(cond : boolean; value : integer; increment : integer := 1) return integer; + function dec_if(cond : boolean; value : integer; decrement : integer := 1) return integer; --+ Max / Min / Sum ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ function imin(arg1 : integer; arg2 : integer) return integer; -- Calculates: min(arg1, arg2) for integers alias rmin is IEEE.math_real.realmin[real, real return real]; -- function rmin(arg1 : real; arg2 : real) return real; -- Calculates: min(arg1, arg2) for reals - function imin(vec : T_INTVEC) return INTEGER; -- Calculates: min(vec) for a integer vector - function imin(vec : T_NATVEC) return NATURAL; -- Calculates: min(vec) for a natural vector - function imin(vec : T_POSVEC) return POSITIVE; -- Calculates: min(vec) for a positive vector + function imin(vec : T_INTVEC) return integer; -- Calculates: min(vec) for a integer vector + function imin(vec : T_NATVEC) return natural; -- Calculates: min(vec) for a natural vector + function imin(vec : T_POSVEC) return positive; -- Calculates: min(vec) for a positive vector function rmin(vec : T_REALVEC) return real; -- Calculates: min(vec) of real vector function imax(arg1 : integer; arg2 : integer) return integer; -- Calculates: max(arg1, arg2) for integers alias rmax is IEEE.math_real.realmax[real, real return real]; -- function rmax(arg1 : real; arg2 : real) return real; -- Calculates: max(arg1, arg2) for reals - function imax(vec : T_INTVEC) return INTEGER; -- Calculates: max(vec) for a integer vector - function imax(vec : T_NATVEC) return NATURAL; -- Calculates: max(vec) for a natural vector - function imax(vec : T_POSVEC) return POSITIVE; -- Calculates: max(vec) for a positive vector + function imax(vec : T_INTVEC) return integer; -- Calculates: max(vec) for a integer vector + function imax(vec : T_NATVEC) return natural; -- Calculates: max(vec) for a natural vector + function imax(vec : T_POSVEC) return positive; -- Calculates: max(vec) for a positive vector function rmax(vec : T_REALVEC) return real; -- Calculates: max(vec) of real vector - function isum(vec : T_NATVEC) return NATURAL; -- Calculates: sum(vec) for a natural vector + function isum(vec : T_NATVEC) return natural; -- Calculates: sum(vec) for a natural vector function isum(vec : T_POSVEC) return natural; -- Calculates: sum(vec) for a positive vector function isum(vec : T_INTVEC) return integer; -- Calculates: sum(vec) of integer vector function rsum(vec : T_REALVEC) return real; -- Calculates: sum(vec) of real vector @@ -156,37 +148,38 @@ package utils is --+ Conversions ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- to integer: to_int - function to_int(bool : BOOLEAN; zero : INTEGER := 0; one : INTEGER := 1) return INTEGER; - function to_int(sl : STD_LOGIC; zero : INTEGER := 0; one : INTEGER := 1) return INTEGER; + function to_int(bool : boolean; zero : integer := 0; one : integer := 1) return integer; + function to_int(sl : std_logic; zero : integer := 0; one : integer := 1) return integer; -- to std_logic: to_sl - function to_sl(Value : BOOLEAN) return STD_LOGIC; - function to_sl(Value : CHARACTER) return STD_LOGIC; + function to_sl(Value : boolean) return std_logic; + function to_sl(Value : character) return std_logic; -- to std_logic_vector: to_slv - function to_slv(Value : NATURAL; Size : POSITIVE) return STD_LOGIC_VECTOR; -- short for std_logic_vector(to_unsigned(Value, Size)) + function to_slv(Value : natural; Size : positive) return std_logic_vector; -- short for std_logic_vector(to_unsigned(Value, Size)) - function to_BCD(Digit : INTEGER) return T_BCD; - function to_BCD(Digit : CHARACTER) return T_BCD; - function to_BCD(Digit : UNSIGNED) return T_BCD; - function to_BCD(Digit : STD_LOGIC_VECTOR) return T_BCD; - function to_BCD_Vector(Value : INTEGER; Size : NATURAL := 0; Fill : T_BCD := x"0") return T_BCD_VECTOR; - function to_BCD_Vector(Value : STRING; Size : NATURAL := 0; Fill : T_BCD := x"0") return T_BCD_VECTOR; + function to_BCD(Digit : integer) return T_BCD; + function to_BCD(Digit : character) return T_BCD; + function to_BCD(Digit : unsigned) return T_BCD; + function to_BCD(Digit : std_logic_vector) return T_BCD; + function to_BCD_Vector(Value : integer; Size : natural := 0; Fill : T_BCD := x"0") return T_BCD_VECTOR; + function to_BCD_Vector(Value : string; Size : natural := 0; Fill : T_BCD := x"0") return T_BCD_VECTOR; -- TODO: comment - function to_index(slv : UNSIGNED; max : NATURAL := 0) return INTEGER; - function to_index(slv : STD_LOGIC_VECTOR; max : NATURAL := 0) return INTEGER; + function bound(index : integer; lowerBound : integer; upperBound : integer) return integer; + function to_index(slv : unsigned; max : natural := 0) return integer; + function to_index(slv : std_logic_vector; max : natural := 0) return integer; -- is_* - function is_sl(c : CHARACTER) return BOOLEAN; + function is_sl(c : character) return boolean; --+ Basic Vector Utilities +++++++++++++++++++++++++++++++++++++++++++++++++ -- Aggregate functions - function slv_or (vec : STD_LOGIC_VECTOR) return STD_LOGIC; - function slv_nor (vec : STD_LOGIC_VECTOR) return STD_LOGIC; - function slv_and (vec : STD_LOGIC_VECTOR) return STD_LOGIC; - function slv_nand(vec : STD_LOGIC_VECTOR) return STD_LOGIC; + function slv_or (vec : std_logic_vector) return std_logic; + function slv_nor (vec : std_logic_vector) return std_logic; + function slv_and (vec : std_logic_vector) return std_logic; + function slv_nand(vec : std_logic_vector) return std_logic; function slv_xor (vec : std_logic_vector) return std_logic; -- NO slv_xnor! This operation would not be well-defined as -- not xor(vec) /= vec_{n-1} xnor ... xnor vec_1 xnor vec_0 iff n is odd. @@ -200,8 +193,8 @@ package utils is function reverse(vec : unsigned) return unsigned; -- scale a value into a range [Minimum, Maximum] - function scale(Value : INTEGER; Minimum : INTEGER; Maximum : INTEGER; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER; - function scale(Value : REAL; Minimum : INTEGER; Maximum : INTEGER; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER; + function scale(Value : integer; Minimum : integer; Maximum : integer; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return integer; + function scale(Value : REAL; Minimum : integer; Maximum : integer; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return integer; function scale(Value : REAL; Minimum : REAL; Maximum : REAL) return REAL; -- Resizes the vector to the specified length. The adjustment is make on @@ -251,11 +244,14 @@ package utils is function mssb_idx(arg : bit_vector) return integer; -- Swap sub vectors in vector (endian reversal) - function swap(slv : STD_LOGIC_VECTOR; Size : POSITIVE) return STD_LOGIC_VECTOR; + function swap(slv : std_logic_vector; Size : positive) return std_logic_vector; + + -- Swap the bits in a chunk + function bit_swap(slv : std_logic_vector; Chunksize : positive) return std_logic_vector; -- generate bit masks - function genmask_high(Bits : NATURAL; MaskLength : POSITIVE) return STD_LOGIC_VECTOR; - function genmask_low(Bits : NATURAL; MaskLength : POSITIVE) return STD_LOGIC_VECTOR; + function genmask_high(Bits : natural; MaskLength : positive) return std_logic_vector; + function genmask_low(Bits : natural; MaskLength : positive) return std_logic_vector; function genmask_alternate(len : positive; lsb : std_logic := '0') return std_logic_vector; --+ Encodings ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ @@ -302,12 +298,12 @@ package body utils is end function; -- deferred constant assignment - constant SIMULATION : BOOLEAN := is_simulation; + constant SIMULATION : boolean := is_simulation; -- Divisions: div_* -- =========================================================================== -- integer division; always round-up - function div_ceil(a : NATURAL; b : POSITIVE) return NATURAL is -- calculates: ceil(a / b) + function div_ceil(a : natural; b : positive) return natural is -- calculates: ceil(a / b) begin return (a + (b - 1)) / b; end function; @@ -315,20 +311,20 @@ package body utils is -- Power functions: *_pow2 -- ========================================================================== -- return TRUE, if input is a power of 2 - function is_pow2(int : NATURAL) return BOOLEAN is + function is_pow2(int : natural) return boolean is begin return ceil_pow2(int) = int; end function; -- round to next power of 2 - function ceil_pow2(int : NATURAL) return POSITIVE is + function ceil_pow2(int : natural) return positive is begin return 2 ** log2ceil(int); end function; -- round to previous power of 2 - function floor_pow2(int : NATURAL) return NATURAL is - variable temp : UNSIGNED(30 downto 0); + function floor_pow2(int : natural) return natural is + variable temp : unsigned(30 downto 0); begin temp := to_unsigned(int, 31); for i in temp'range loop @@ -385,7 +381,7 @@ package body utils is -- if-then-else (ite) -- ========================================================================== - function ite(cond : BOOLEAN; value1 : BOOLEAN; value2 : BOOLEAN) return BOOLEAN is + function ite(cond : boolean; value1 : boolean; value2 : boolean) return boolean is begin if cond then return value1; @@ -394,7 +390,7 @@ package body utils is end if; end function; - function ite(cond : BOOLEAN; value1 : INTEGER; value2 : INTEGER) return INTEGER is + function ite(cond : boolean; value1 : integer; value2 : integer) return integer is begin if cond then return value1; @@ -403,7 +399,7 @@ package body utils is end if; end function; - function ite(cond : BOOLEAN; value1 : REAL; value2 : REAL) return REAL is + function ite(cond : boolean; value1 : REAL; value2 : REAL) return REAL is begin if cond then return value1; @@ -412,7 +408,7 @@ package body utils is end if; end function; - function ite(cond : BOOLEAN; value1 : STD_LOGIC; value2 : STD_LOGIC) return STD_LOGIC is + function ite(cond : boolean; value1 : std_logic; value2 : std_logic) return std_logic is begin if cond then return value1; @@ -421,7 +417,7 @@ package body utils is end if; end function; - function ite(cond : BOOLEAN; value1 : STD_LOGIC_VECTOR; value2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is + function ite(cond : boolean; value1 : std_logic_vector; value2 : std_logic_vector) return std_logic_vector is begin if cond then return value1; @@ -430,7 +426,7 @@ package body utils is end if; end function; - function ite(cond : BOOLEAN; value1 : BIT_VECTOR; value2 : BIT_VECTOR) return BIT_VECTOR is + function ite(cond : boolean; value1 : bit_vector; value2 : bit_vector) return bit_vector is begin if cond then return value1; @@ -439,7 +435,7 @@ package body utils is end if; end function; - function ite(cond : BOOLEAN; value1 : UNSIGNED; value2 : UNSIGNED) return UNSIGNED is + function ite(cond : boolean; value1 : unsigned; value2 : unsigned) return unsigned is begin if cond then return value1; @@ -448,7 +444,7 @@ package body utils is end if; end function; - function ite(cond : BOOLEAN; value1 : CHARACTER; value2 : CHARACTER) return CHARACTER is + function ite(cond : boolean; value1 : character; value2 : character) return character is begin if cond then return value1; @@ -457,7 +453,7 @@ package body utils is end if; end function; - function ite(cond : BOOLEAN; value1 : STRING; value2 : STRING) return STRING is + function ite(cond : boolean; value1 : string; value2 : string) return string is begin if cond then return value1; @@ -469,7 +465,7 @@ package body utils is -- conditional increment / decrement -- =========================================================================== -- return the by increment incremented Value if cond is true else passthrough Value - function inc(cond : BOOLEAN; Value : INTEGER; increment : INTEGER := 1) return INTEGER is + function inc_if(cond : boolean; Value : integer; increment : integer := 1) return integer is begin if cond then return Value + increment; @@ -479,7 +475,7 @@ package body utils is end function; -- return the by decrement decremented Value if cond is true else passthrough Value - function dec(cond : BOOLEAN; Value : INTEGER; decrement : INTEGER := 1) return INTEGER is + function dec_if(cond : boolean; Value : integer; decrement : integer := 1) return integer is begin if cond then return Value - decrement; @@ -502,36 +498,36 @@ package body utils is -- return arg2; -- end function; - function imin(vec : T_INTVEC) return INTEGER is - variable Result : INTEGER; + function imin(vec : T_INTVEC) return integer is + variable Result : integer; begin - Result := INTEGER'high; + Result := integer'high; for i in vec'range loop - if (vec(i) < Result) then + if vec(i) < Result then Result := vec(i); end if; end loop; return Result; end function; - function imin(vec : T_NATVEC) return NATURAL is - variable Result : NATURAL; + function imin(vec : T_NATVEC) return natural is + variable Result : natural; begin - Result := NATURAL'high; + Result := natural'high; for i in vec'range loop - if (vec(i) < Result) then + if vec(i) < Result then Result := vec(i); end if; end loop; return Result; end function; - function imin(vec : T_POSVEC) return POSITIVE is - variable Result : POSITIVE; + function imin(vec : T_POSVEC) return positive is + variable Result : positive; begin - Result := POSITIVE'high; + Result := positive'high; for i in vec'range loop - if (vec(i) < Result) then + if vec(i) < Result then Result := vec(i); end if; end loop; @@ -562,36 +558,36 @@ package body utils is -- return arg2; -- end function; - function imax(vec : T_INTVEC) return INTEGER is - variable Result : INTEGER; + function imax(vec : T_INTVEC) return integer is + variable Result : integer; begin - Result := INTEGER'low; + Result := integer'low; for i in vec'range loop - if (vec(i) > Result) then + if vec(i) > Result then Result := vec(i); end if; end loop; return Result; end function; - function imax(vec : T_NATVEC) return NATURAL is - variable Result : NATURAL; + function imax(vec : T_NATVEC) return natural is + variable Result : natural; begin - Result := NATURAL'low; + Result := natural'low; for i in vec'range loop - if (vec(i) > Result) then + if vec(i) > Result then Result := vec(i); end if; end loop; return Result; end function; - function imax(vec : T_POSVEC) return POSITIVE is - variable Result : POSITIVE; + function imax(vec : T_POSVEC) return positive is + variable Result : positive; begin - Result := POSITIVE'low; + Result := positive'low; for i in vec'range loop - if (vec(i) > Result) then + if vec(i) > Result then Result := vec(i); end if; end loop; @@ -610,8 +606,8 @@ package body utils is return Result; end function; - function isum(vec : T_INTVEC) return INTEGER is - variable Result : INTEGER; + function isum(vec : T_INTVEC) return integer is + variable Result : integer; begin Result := 0; for i in vec'range loop @@ -620,8 +616,8 @@ package body utils is return Result; end function; - function isum(vec : T_NATVEC) return NATURAL is - variable Result : NATURAL; + function isum(vec : T_NATVEC) return natural is + variable Result : natural; begin Result := 0; for i in vec'range loop @@ -652,8 +648,8 @@ package body utils is -- Vector aggregate functions: slv_* -- ========================================================================== - function slv_or(vec : STD_LOGIC_VECTOR) return STD_LOGIC is - variable Result : STD_LOGIC; + function slv_or(vec : std_logic_vector) return std_logic is + variable Result : std_logic; begin Result := '0'; for i in vec'range loop @@ -662,13 +658,13 @@ package body utils is return Result; end function; - function slv_nor(vec : STD_LOGIC_VECTOR) return STD_LOGIC is + function slv_nor(vec : std_logic_vector) return std_logic is begin return not slv_or(vec); end function; - function slv_and(vec : STD_LOGIC_VECTOR) return STD_LOGIC is - variable Result : STD_LOGIC; + function slv_and(vec : std_logic_vector) return std_logic is + variable Result : std_logic; begin Result := '1'; for i in vec'range loop @@ -677,7 +673,7 @@ package body utils is return Result; end function; - function slv_nand(vec : STD_LOGIC_VECTOR) return STD_LOGIC is + function slv_nand(vec : std_logic_vector) return std_logic is begin return not slv_and(vec); end function; @@ -696,12 +692,12 @@ package body utils is -- Type conversion -- =========================================================================== -- Convert to integer: to_int - function to_int(bool : BOOLEAN; zero : INTEGER := 0; one : INTEGER := 1) return INTEGER is + function to_int(bool : boolean; zero : integer := 0; one : integer := 1) return integer is begin return ite(bool, one, zero); end function; - function to_int(sl : STD_LOGIC; zero : INTEGER := 0; one : INTEGER := 1) return INTEGER is + function to_int(sl : std_logic; zero : integer := 0; one : integer := 1) return integer is begin if (sl = '1') then return one; @@ -711,12 +707,12 @@ package body utils is -- Convert to bit: to_sl -- =========================================================================== - function to_sl(Value : BOOLEAN) return STD_LOGIC is + function to_sl(Value : boolean) return std_logic is begin return ite(Value, '1', '0'); end function; - function to_sl(Value : CHARACTER) return STD_LOGIC is + function to_sl(Value : character) return std_logic is begin case Value is when 'U' => return 'U'; @@ -727,7 +723,7 @@ package body utils is when 'L' => return 'L'; when 'H' => return 'H'; when '-' => return '-'; - when OTHERS => return 'X'; + when others => return 'X'; end case; end function; @@ -735,7 +731,7 @@ package body utils is -- =========================================================================== -- short for std_logic_vector(to_unsigned(Value, Size)) -- the return value is guaranteed to have the range (Size-1 downto 0) - function to_slv(Value : NATURAL; Size : POSITIVE) return STD_LOGIC_VECTOR is + function to_slv(Value : natural; Size : positive) return std_logic_vector is constant res : std_logic_vector(Size-1 downto 0) := std_logic_vector(to_unsigned(Value, Size)); begin return res; @@ -743,32 +739,32 @@ package body utils is -- Convert to T_BCD or T_BCD_VECTOR: to_BCD* -- =========================================================================== - function to_BCD(Digit : INTEGER) return T_BCD is + function to_BCD(Digit : integer) return T_BCD is begin return T_BCD(to_unsigned(Digit, T_BCD'length)); end function; - function to_BCD(Digit : CHARACTER) return T_BCD is + function to_BCD(Digit : character) return T_BCD is begin - return T_BCD(to_unsigned((CHARACTER'pos(Digit) - CHARACTER'pos('0')), T_BCD'length)); + return T_BCD(to_unsigned((character'pos(Digit) - CHARACTER'pos('0')), T_BCD'length)); end function; - function to_BCD(Digit : UNSIGNED) return T_BCD is + function to_BCD(Digit : unsigned) return T_BCD is begin return T_BCD(Digit); end function; - function to_BCD(Digit : STD_LOGIC_VECTOR) return T_BCD is + function to_BCD(Digit : std_logic_vector) return T_BCD is begin return T_BCD(Digit); end function; - function to_BCD_Vector(Value : INTEGER; Size : NATURAL := 0; Fill : T_BCD := x"0") return T_BCD_VECTOR is + function to_BCD_Vector(Value : integer; Size : natural := 0; Fill : T_BCD := x"0") return T_BCD_VECTOR is begin - return to_BCD_Vector(INTEGER'image(Value), Size, Fill); + return to_BCD_Vector(integer'image(Value), Size, Fill); end function; - function to_BCD_Vector(Value : STRING; Size : NATURAL := 0; Fill : T_BCD := x"0") return T_BCD_VECTOR is + function to_BCD_Vector(Value : string; Size : natural := 0; Fill : T_BCD := x"0") return T_BCD_VECTOR is variable Result : T_BCD_VECTOR(Size - 1 downto 0); begin Result := (others => Fill); @@ -779,7 +775,18 @@ package body utils is end function; -- bound array indices for simulation, to prevent out of range errors - function to_index(slv : UNSIGNED; max : NATURAL := 0) return INTEGER is + function bound(index : integer; lowerBound : integer; upperBound : integer) return integer is + begin + if index < lowerBound then + return lowerBound; + elsif upperBound < index then + return upperBound; + else + return index; + end if; + end function; + + function to_index(slv : unsigned; max : natural := 0) return integer is variable res : integer; begin if (slv'length = 0) then return 0; end if; @@ -792,18 +799,18 @@ package body utils is end function; -- bound array indices for simulation, to prevent out of range errors - function to_index(slv : STD_LOGIC_VECTOR; max : NATURAL := 0) return INTEGER is + function to_index(slv : std_logic_vector; max : natural := 0) return integer is begin return to_index(unsigned(slv), max); end function; -- is_* -- =========================================================================== - function is_sl(c : CHARACTER) return BOOLEAN is + function is_sl(c : character) return boolean is begin case c is when 'U'|'X'|'0'|'1'|'Z'|'W'|'L'|'H'|'-' => return true; - when OTHERS => return false; + when others => return false; end case; end function; @@ -833,41 +840,59 @@ package body utils is -- Swap sub vectors in vector -- ========================================================================== - function swap(slv : STD_LOGIC_VECTOR; Size : POSITIVE) return STD_LOGIC_VECTOR IS - CONSTANT SegmentCount : NATURAL := slv'length / Size; - variable FromH : NATURAL; - variable FromL : NATURAL; - variable ToH : NATURAL; - variable ToL : NATURAL; - variable Result : STD_LOGIC_VECTOR(slv'length - 1 DOWNTO 0); - begin - for i in 0 TO SegmentCount - 1 loop + function swap(slv : std_logic_vector; Size : positive) return std_logic_vector is + constant SegmentCount : natural := slv'length / Size; + variable FromH : natural; + variable FromL : natural; + variable ToH : natural; + variable ToL : natural; + variable Result : std_logic_vector(slv'length - 1 downto 0); + begin + for i in 0 to SegmentCount - 1 loop FromH := ((i + 1) * Size) - 1; FromL := i * Size; ToH := ((SegmentCount - i) * Size) - 1; ToL := (SegmentCount - i - 1) * Size; - Result(ToH DOWNTO ToL) := slv(FromH DOWNTO FromL); + Result(ToH downto ToL) := slv(FromH downto FromL); end loop; return Result; end function; + + -- Swap the bits in a chunk + -- ========================================================================== + function bit_swap(slv : std_logic_vector; Chunksize : positive) return std_logic_vector is + constant SegmentCount : natural := slv'length / Chunksize; + variable FromH : natural; + variable FromL : natural; + variable Result : std_logic_vector(slv'length - 1 downto 0); + begin + for i in 0 to SegmentCount - 1 loop + FromH := ((i + 1) * Chunksize) - 1; + FromL := i * Chunksize; + Result(FromH downto FromL) := reverse(slv(FromH downto FromL)); + end loop; + return Result; + end function; + + -- generate bit masks -- ========================================================================== - function genmask_high(Bits : NATURAL; MaskLength : POSITIVE) return STD_LOGIC_VECTOR IS + function genmask_high(Bits : natural; MaskLength : positive) return std_logic_vector is begin - if (Bits = 0) then - return (MaskLength - 1 DOWNTO 0 => '0'); + if Bits = 0 then + return (MaskLength - 1 downto 0 => '0'); else - return (MaskLength - 1 DOWNTO MaskLength - Bits + 1 => '1') & (MaskLength - Bits DOWNTO 0 => '0'); + return (MaskLength - 1 downto MaskLength - Bits + 1 => '1') & (MaskLength - Bits downto 0 => '0'); end if; end function; - function genmask_low(Bits : NATURAL; MaskLength : POSITIVE) return STD_LOGIC_VECTOR is + function genmask_low(Bits : natural; MaskLength : positive) return std_logic_vector is begin - if (Bits = 0) then - return (MaskLength - 1 DOWNTO 0 => '0'); + if Bits = 0 then + return (MaskLength - 1 downto 0 => '0'); else - return (MaskLength - 1 DOWNTO Bits => '0') & (Bits - 1 DOWNTO 0 => '1'); + return (MaskLength - 1 downto Bits => '0') & (Bits - 1 downto 0 => '1'); end if; end function; @@ -999,16 +1024,16 @@ package body utils is end function; -- scale a value into a given range - function scale(Value : INTEGER; Minimum : INTEGER; Maximum : INTEGER; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER is + function scale(Value : integer; Minimum : integer; Maximum : integer; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return integer is begin return scale(real(Value), Minimum, Maximum, RoundingStyle); end function; - function scale(Value : REAL; Minimum : INTEGER; Maximum : INTEGER; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER is + function scale(Value : REAL; Minimum : integer; Maximum : integer; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return integer is variable Result : REAL; begin - if (Maximum < Minimum) then - return INTEGER'low; + if Maximum < Minimum then + return integer'low; else Result := real(Value) * ((real(Maximum) + 0.5) - (real(Minimum) - 0.5)) + (real(Minimum) - 0.5); case RoundingStyle is @@ -1024,7 +1049,7 @@ package body utils is function scale(Value : REAL; Minimum : REAL; Maximum : REAL) return REAL is begin - if (Maximum < Minimum) then + if Maximum < Minimum then return REAL'low; else return Value * (Maximum - Minimum) + Minimum; diff --git a/src/common/vectors.vhdl b/src/common/vectors.vhdl index 13ac1c29..21a40b04 100644 --- a/src/common/vectors.vhdl +++ b/src/common/vectors.vhdl @@ -1,8 +1,7 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Thomas B. Preusser -- Martin Zabel -- Patrick Lehmann @@ -10,11 +9,11 @@ -- Package: Common functions and types -- -- Description: --- ------------------------------------ +-- ------------------------------------- -- For detailed documentation see below. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -29,7 +28,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.std_logic_1164.all; @@ -45,104 +44,113 @@ package vectors is -- Type declarations -- ========================================================================== -- STD_LOGIC_VECTORs - subtype T_SLV_2 is STD_LOGIC_VECTOR(1 downto 0); - subtype T_SLV_3 is STD_LOGIC_VECTOR(2 downto 0); - subtype T_SLV_4 is STD_LOGIC_VECTOR(3 downto 0); - subtype T_SLV_8 is STD_LOGIC_VECTOR(7 downto 0); - subtype T_SLV_12 is STD_LOGIC_VECTOR(11 downto 0); - subtype T_SLV_16 is STD_LOGIC_VECTOR(15 downto 0); - subtype T_SLV_24 is STD_LOGIC_VECTOR(23 downto 0); - subtype T_SLV_32 is STD_LOGIC_VECTOR(31 downto 0); - subtype T_SLV_48 is STD_LOGIC_VECTOR(47 downto 0); - subtype T_SLV_64 is STD_LOGIC_VECTOR(63 downto 0); - subtype T_SLV_96 is STD_LOGIC_VECTOR(95 downto 0); - subtype T_SLV_128 is STD_LOGIC_VECTOR(127 downto 0); - subtype T_SLV_256 is STD_LOGIC_VECTOR(255 downto 0); - subtype T_SLV_512 is STD_LOGIC_VECTOR(511 downto 0); + subtype T_SLV_2 is std_logic_vector(1 downto 0); + subtype T_SLV_3 is std_logic_vector(2 downto 0); + subtype T_SLV_4 is std_logic_vector(3 downto 0); + subtype T_SLV_8 is std_logic_vector(7 downto 0); + subtype T_SLV_12 is std_logic_vector(11 downto 0); + subtype T_SLV_16 is std_logic_vector(15 downto 0); + subtype T_SLV_24 is std_logic_vector(23 downto 0); + subtype T_SLV_32 is std_logic_vector(31 downto 0); + subtype T_SLV_48 is std_logic_vector(47 downto 0); + subtype T_SLV_64 is std_logic_vector(63 downto 0); + subtype T_SLV_96 is std_logic_vector(95 downto 0); + subtype T_SLV_128 is std_logic_vector(127 downto 0); + subtype T_SLV_256 is std_logic_vector(255 downto 0); + subtype T_SLV_512 is std_logic_vector(511 downto 0); -- STD_LOGIC_VECTOR_VECTORs -- type T_SLVV is array(NATURAL range <>) of STD_LOGIC_VECTOR; -- VHDL 2008 syntax - not yet supported by Xilinx - type T_SLVV_2 is array(NATURAL range <>) of T_SLV_2; - type T_SLVV_3 is array(NATURAL range <>) of T_SLV_3; - type T_SLVV_4 is array(NATURAL range <>) of T_SLV_4; - type T_SLVV_8 is array(NATURAL range <>) of T_SLV_8; - type T_SLVV_12 is array(NATURAL range <>) of T_SLV_12; - type T_SLVV_16 is array(NATURAL range <>) of T_SLV_16; - type T_SLVV_24 is array(NATURAL range <>) of T_SLV_24; - type T_SLVV_32 is array(NATURAL range <>) of T_SLV_32; - type T_SLVV_48 is array(NATURAL range <>) of T_SLV_48; - type T_SLVV_64 is array(NATURAL range <>) of T_SLV_64; - type T_SLVV_128 is array(NATURAL range <>) of T_SLV_128; - type T_SLVV_256 is array(NATURAL range <>) of T_SLV_256; - type T_SLVV_512 is array(NATURAL range <>) of T_SLV_512; + type T_SLVV_2 is array(natural range <>) of T_SLV_2; + type T_SLVV_3 is array(natural range <>) of T_SLV_3; + type T_SLVV_4 is array(natural range <>) of T_SLV_4; + type T_SLVV_8 is array(natural range <>) of T_SLV_8; + type T_SLVV_12 is array(natural range <>) of T_SLV_12; + type T_SLVV_16 is array(natural range <>) of T_SLV_16; + type T_SLVV_24 is array(natural range <>) of T_SLV_24; + type T_SLVV_32 is array(natural range <>) of T_SLV_32; + type T_SLVV_48 is array(natural range <>) of T_SLV_48; + type T_SLVV_64 is array(natural range <>) of T_SLV_64; + type T_SLVV_128 is array(natural range <>) of T_SLV_128; + type T_SLVV_256 is array(natural range <>) of T_SLV_256; + type T_SLVV_512 is array(natural range <>) of T_SLV_512; -- STD_LOGIC_MATRIXs - type T_SLM is array(NATURAL range <>, NATURAL range <>) of STD_LOGIC; + type T_SLM is array(natural range <>, natural range <>) of std_logic; -- ATTENTION: -- 1. you MUST initialize your matrix signal with 'Z' to get correct simulation results (iSIM, vSIM, ghdl/gtkwave) - -- Example: signal myMatrix : T_SLM(3 downto 0, 7 downto 0) := (others => (others => 'Z')); + -- Example: signal myMatrix : T_SLM(3 downto 0, 7 downto 0) := (others => (others => 'Z')); -- 2. Xilinx iSIM bug: DON'T use myMatrix'range(n) for n >= 2 - -- myMatrix'range(2) returns always myMatrix'range(1); see work-around notes below + -- myMatrix'range(2) returns always myMatrix'range(1); see work-around notes below -- -- USAGE NOTES: - -- dimmension 1 => rows - e.g. Words - -- dimmension 2 => columns - e.g. Bits/Bytes in a word + -- dimension 1 => rows - e.g. Words + -- dimension 2 => columns - e.g. Bits/Bytes in a word -- -- WORKAROUND: for Xilinx ISE/iSim - -- Version: 14.2 - -- Issue: myMatrix'range(n) for n >= 2 returns always myMatrix'range(1) + -- Version: 14.2 + -- Issue: myMatrix'range(n) for n >= 2 returns always myMatrix'range(1) -- ========================================================================== -- Function declarations -- ========================================================================== -- slicing boundary calulations - function low (lenvec : T_POSVEC; index : NATURAL) return NATURAL; - function high(lenvec : T_POSVEC; index : NATURAL) return NATURAL; + function low (lenvec : T_POSVEC; index : natural) return natural; + function high(lenvec : T_POSVEC; index : natural) return natural; -- Assign procedures: assign_* - procedure assign_row(signal slm : out T_SLM; slv : STD_LOGIC_VECTOR; constant RowIndex : NATURAL); -- assign vector to complete row - procedure assign_row(signal slm : out T_SLM; slv : STD_LOGIC_VECTOR; constant RowIndex : NATURAL; Position : NATURAL); -- assign short vector to row starting at position - procedure assign_row(signal slm : out T_SLM; slv : STD_LOGIC_VECTOR; constant RowIndex : NATURAL; High : NATURAL; Low : NATURAL); -- assign short vector to row in range high:low - procedure assign_col(signal slm : out T_SLM; slv : STD_LOGIC_VECTOR; constant ColIndex : NATURAL); -- assign vector to complete column + procedure assign_row(signal slm : out T_SLM; slv : std_logic_vector; constant RowIndex : natural); -- assign vector to complete row + procedure assign_row(signal slm : out T_SLM; slv : std_logic_vector; constant RowIndex : natural; Position : natural); -- assign short vector to row starting at position + procedure assign_row(signal slm : out T_SLM; slv : std_logic_vector; constant RowIndex : natural; High : natural; Low : natural); -- assign short vector to row in range high:low + procedure assign_col(signal slm : out T_SLM; slv : std_logic_vector; constant ColIndex : natural); -- assign vector to complete column -- ATTENTION: see T_SLM definition for further details and work-arounds -- Matrix to matrix conversion: slm_slice* - function slm_slice(slm : T_SLM; RowIndex : NATURAL; ColIndex : NATURAL; Height : NATURAL; Width : NATURAL) return T_SLM; -- get submatrix in boundingbox RowIndex,ColIndex,Height,Width - function slm_slice_rows(slm : T_SLM; High : NATURAL; Low : NATURAL) return T_SLM; -- get submatrix / all rows in RowIndex range high:low - function slm_slice_cols(slm : T_SLM; High : NATURAL; Low : NATURAL) return T_SLM; -- get submatrix / all columns in ColIndex range high:low + function slm_slice(slm : T_SLM; RowIndex : natural; ColIndex : natural; Height : natural; Width : natural) return T_SLM; -- get submatrix in boundingbox RowIndex,ColIndex,Height,Width + function slm_slice_rows(slm : T_SLM; High : natural; Low : natural) return T_SLM; -- get submatrix / all rows in RowIndex range high:low + function slm_slice_cols(slm : T_SLM; High : natural; Low : natural) return T_SLM; -- get submatrix / all columns in ColIndex range high:low + + -- Boolean Operators + function "not" (a : t_slm) return t_slm; + function "and" (a, b : t_slm) return t_slm; + function "or" (a, b : t_slm) return t_slm; + function "xor" (a, b : t_slm) return t_slm; + function "nand"(a, b : t_slm) return t_slm; + function "nor" (a, b : t_slm) return t_slm; + function "xnor"(a, b : t_slm) return t_slm; -- Matrix concatenation: slm_merge_* function slm_merge_rows(slm1 : T_SLM; slm2 : T_SLM) return T_SLM; function slm_merge_cols(slm1 : T_SLM; slm2 : T_SLM) return T_SLM; -- Matrix to vector conversion: get_* - function get_col(slm : T_SLM; ColIndex : NATURAL) return STD_LOGIC_VECTOR; -- get a matrix column - function get_row(slm : T_SLM; RowIndex : NATURAL) return STD_LOGIC_VECTOR; -- get a matrix row - function get_row(slm : T_SLM; RowIndex : NATURAL; Length : POSITIVE) return STD_LOGIC_VECTOR; -- get a matrix row of defined length [length - 1 downto 0] - function get_row(slm : T_SLM; RowIndex : NATURAL; High : NATURAL; Low : NATURAL) return STD_LOGIC_VECTOR; -- get a sub vector of a matrix row at high:low + function get_col(slm : T_SLM; ColIndex : natural) return std_logic_vector; -- get a matrix column + function get_row(slm : T_SLM; RowIndex : natural) return std_logic_vector; -- get a matrix row + function get_row(slm : T_SLM; RowIndex : natural; Length : positive) return std_logic_vector; -- get a matrix row of defined length [length - 1 downto 0] + function get_row(slm : T_SLM; RowIndex : natural; High : natural; Low : natural) return std_logic_vector; -- get a sub vector of a matrix row at high:low -- Convert to vector: to_slv - function to_slv(slvv : T_SLVV_2) return STD_LOGIC_VECTOR; -- convert vector-vector to flatten vector - function to_slv(slvv : T_SLVV_4) return STD_LOGIC_VECTOR; -- ... - function to_slv(slvv : T_SLVV_8) return STD_LOGIC_VECTOR; -- ... - function to_slv(slvv : T_SLVV_12) return STD_LOGIC_VECTOR; -- ... - function to_slv(slvv : T_SLVV_16) return STD_LOGIC_VECTOR; -- ... - function to_slv(slvv : T_SLVV_24) return STD_LOGIC_VECTOR; -- ... - function to_slv(slvv : T_SLVV_32) return STD_LOGIC_VECTOR; -- ... - function to_slv(slvv : T_SLVV_64) return STD_LOGIC_VECTOR; -- ... - function to_slv(slvv : T_SLVV_128) return STD_LOGIC_VECTOR; -- ... - function to_slv(slm : T_SLM) return STD_LOGIC_VECTOR; -- convert matrix to flatten vector + function to_slv(slvv : T_SLVV_2) return std_logic_vector; -- convert vector-vector to flatten vector + function to_slv(slvv : T_SLVV_4) return std_logic_vector; -- ... + function to_slv(slvv : T_SLVV_8) return std_logic_vector; -- ... + function to_slv(slvv : T_SLVV_12) return std_logic_vector; -- ... + function to_slv(slvv : T_SLVV_16) return std_logic_vector; -- ... + function to_slv(slvv : T_SLVV_24) return std_logic_vector; -- ... + function to_slv(slvv : T_SLVV_32) return std_logic_vector; -- ... + function to_slv(slvv : T_SLVV_64) return std_logic_vector; -- ... + function to_slv(slvv : T_SLVV_128) return std_logic_vector; -- ... + function to_slv(slm : T_SLM) return std_logic_vector; -- convert matrix to flatten vector -- Convert flat vector to avector-vector: to_slvv_* - function to_slvv_4(slv : STD_LOGIC_VECTOR) return T_SLVV_4; -- - function to_slvv_8(slv : STD_LOGIC_VECTOR) return T_SLVV_8; -- - function to_slvv_12(slv : STD_LOGIC_VECTOR) return T_SLVV_12; -- - function to_slvv_16(slv : STD_LOGIC_VECTOR) return T_SLVV_16; -- - function to_slvv_32(slv : STD_LOGIC_VECTOR) return T_SLVV_32; -- - function to_slvv_64(slv : STD_LOGIC_VECTOR) return T_SLVV_64; -- - function to_slvv_128(slv : STD_LOGIC_VECTOR) return T_SLVV_128; -- - function to_slvv_256(slv : STD_LOGIC_VECTOR) return T_SLVV_256; -- - function to_slvv_512(slv : STD_LOGIC_VECTOR) return T_SLVV_512; -- + function to_slvv_4(slv : std_logic_vector) return T_SLVV_4; -- + function to_slvv_8(slv : std_logic_vector) return T_SLVV_8; -- + function to_slvv_12(slv : std_logic_vector) return T_SLVV_12; -- + function to_slvv_16(slv : std_logic_vector) return T_SLVV_16; -- + function to_slvv_32(slv : std_logic_vector) return T_SLVV_32; -- + function to_slvv_64(slv : std_logic_vector) return T_SLVV_64; -- + function to_slvv_128(slv : std_logic_vector) return T_SLVV_128; -- + function to_slvv_256(slv : std_logic_vector) return T_SLVV_256; -- + function to_slvv_512(slv : std_logic_vector) return T_SLVV_512; -- -- Convert matrix to avector-vector: to_slvv_* function to_slvv_4(slm : T_SLM) return T_SLVV_4; -- @@ -156,7 +164,7 @@ package vectors is function to_slvv_512(slm : T_SLM) return T_SLVV_512; -- -- Convert vector-vector to matrix: to_slm - function to_slm(slv : STD_LOGIC_VECTOR; ROWS : POSITIVE; COLS : POSITIVE) return T_SLM; -- create matrix from vector + function to_slm(slv : std_logic_vector; ROWS : positive; COLS : positive) return T_SLM; -- create matrix from vector function to_slm(slvv : T_SLVV_4) return T_SLM; -- create matrix from vector-vector function to_slm(slvv : T_SLVV_8) return T_SLM; -- create matrix from vector-vector function to_slm(slvv : T_SLVV_12) return T_SLM; -- create matrix from vector-vector @@ -183,19 +191,19 @@ package vectors is function rev(slvv : T_SLVV_512) return T_SLVV_512; -- TODO: - function resize(slm : T_SLM; size : POSITIVE) return T_SLM; + function resize(slm : T_SLM; size : positive) return T_SLM; -- to_string - function to_string(slvv : T_SLVV_8; sep : CHARACTER := ':') return STRING; - function to_string(slm : T_SLM; groups : POSITIVE := 4; format : CHARACTER := 'b') return STRING; + function to_string(slvv : T_SLVV_8; sep : character := ':') return string; + function to_string(slm : T_SLM; groups : positive := 4; format : character := 'b') return string; end package vectors; package body vectors is -- slicing boundary calulations -- ========================================================================== - function low(lenvec : T_POSVEC; index : NATURAL) return NATURAL is - variable pos : NATURAL := 0; + function low(lenvec : T_POSVEC; index : natural) return natural is + variable pos : natural := 0; begin for i in lenvec'low to index - 1 loop pos := pos + lenvec(i); @@ -203,8 +211,8 @@ package body vectors is return pos; end function; - function high(lenvec : T_POSVEC; index : NATURAL) return NATURAL is - variable pos : NATURAL := 0; + function high(lenvec : T_POSVEC; index : natural) return natural is + variable pos : natural := 0; begin for i in lenvec'low to index loop pos := pos + lenvec(i); @@ -214,8 +222,8 @@ package body vectors is -- Assign procedures: assign_* -- ========================================================================== - procedure assign_row(signal slm : out T_SLM; slv : STD_LOGIC_VECTOR; constant RowIndex : NATURAL) is - variable temp : STD_LOGIC_VECTOR(slm'high(2) downto slm'low(2)); -- WORKAROUND: Xilinx iSIM work-around, because 'range(2) evaluates to 'range(1); see work-around notes at T_SLM type declaration + procedure assign_row(signal slm : out T_SLM; slv : std_logic_vector; constant RowIndex : natural) is + variable temp : std_logic_vector(slm'high(2) downto slm'low(2)); -- WORKAROUND: Xilinx iSIM work-around, because 'range(2) evaluates to 'range(1); see work-around notes at T_SLM type declaration begin temp := slv; for i in temp'range loop @@ -223,8 +231,8 @@ package body vectors is end loop; end procedure; - procedure assign_row(signal slm : out T_SLM; slv : STD_LOGIC_VECTOR; constant RowIndex : NATURAL; Position : NATURAL) is - variable temp : STD_LOGIC_VECTOR(Position + slv'length - 1 downto Position); + procedure assign_row(signal slm : out T_SLM; slv : std_logic_vector; constant RowIndex : natural; Position : natural) is + variable temp : std_logic_vector(Position + slv'length - 1 downto Position); begin temp := slv; for i in temp'range loop @@ -232,8 +240,8 @@ package body vectors is end loop; end procedure; - procedure assign_row(signal slm : out T_SLM; slv : STD_LOGIC_VECTOR; constant RowIndex : NATURAL; High : NATURAL; Low : NATURAL) is - variable temp : STD_LOGIC_VECTOR(High downto Low); + procedure assign_row(signal slm : out T_SLM; slv : std_logic_vector; constant RowIndex : natural; High : natural; Low : natural) is + variable temp : std_logic_vector(High downto Low); begin temp := slv; for i in temp'range loop @@ -241,8 +249,8 @@ package body vectors is end loop; end procedure; - procedure assign_col(signal slm : out T_SLM; slv : STD_LOGIC_VECTOR; constant ColIndex : NATURAL) is - variable temp : STD_LOGIC_VECTOR(slm'range(1)); + procedure assign_col(signal slm : out T_SLM; slv : std_logic_vector; constant ColIndex : natural) is + variable temp : std_logic_vector(slm'range(1)); begin temp := slv; for i in temp'range loop @@ -252,7 +260,7 @@ package body vectors is -- Matrix to matrix conversion: slm_slice* -- ========================================================================== - function slm_slice(slm : T_SLM; RowIndex : NATURAL; ColIndex : NATURAL; Height : NATURAL; Width : NATURAL) return T_SLM is + function slm_slice(slm : T_SLM; RowIndex : natural; ColIndex : natural; Height : natural; Width : natural) return T_SLM is variable Result : T_SLM(Height - 1 downto 0, Width - 1 downto 0) := (others => (others => '0')); begin for i in 0 to Height - 1 loop @@ -263,7 +271,7 @@ package body vectors is return Result; end function; - function slm_slice_rows(slm : T_SLM; High : NATURAL; Low : NATURAL) return T_SLM is + function slm_slice_rows(slm : T_SLM; High : natural; Low : natural) return T_SLM is variable Result : T_SLM(High - Low downto 0, slm'length(2) - 1 downto 0) := (others => (others => '0')); begin for i in 0 to High - Low loop @@ -274,7 +282,7 @@ package body vectors is return Result; end function; - function slm_slice_cols(slm : T_SLM; High : NATURAL; Low : NATURAL) return T_SLM is + function slm_slice_cols(slm : T_SLM; High : natural; Low : natural) return T_SLM is variable Result : T_SLM(slm'length(1) - 1 downto 0, High - Low downto 0) := (others => (others => '0')); begin for i in 0 to slm'length(1) - 1 loop @@ -285,10 +293,73 @@ package body vectors is return Result; end function; + -- Boolean Operators + function "not"(a : t_slm) return t_slm is + variable res : t_slm(a'range(1), a'range(2)); + begin + for i in res'range(1) loop + for j in res'range(2) loop + res(i, j) := not a(i, j); + end loop; + end loop; + return res; + end function; + + function "and"(a, b : t_slm) return t_slm is + variable bb, res : t_slm(a'range(1), a'range(2)); + begin + bb := b; + for i in res'range(1) loop + for j in res'range(2) loop + res(i, j) := a(i, j) and bb(i, j); + end loop; + end loop; + return res; + end function; + + function "or"(a, b : t_slm) return t_slm is + variable bb, res : t_slm(a'range(1), a'range(2)); + begin + bb := b; + for i in res'range(1) loop + for j in res'range(2) loop + res(i, j) := a(i, j) or bb(i, j); + end loop; + end loop; + return res; + end function; + + function "xor"(a, b : t_slm) return t_slm is + variable bb, res : t_slm(a'range(1), a'range(2)); + begin + bb := b; + for i in res'range(1) loop + for j in res'range(2) loop + res(i, j) := a(i, j) xor bb(i, j); + end loop; + end loop; + return res; + end function; + + function "nand"(a, b : t_slm) return t_slm is + begin + return not(a and b); + end function; + + function "nor"(a, b : t_slm) return t_slm is + begin + return not(a or b); + end function; + + function "xnor"(a, b : t_slm) return t_slm is + begin + return not(a xor b); + end function; + -- Matrix concatenation: slm_merge_* function slm_merge_rows(slm1 : T_SLM; slm2 : T_SLM) return T_SLM is - constant ROWS : POSITIVE := slm1'length(1) + slm2'length(1); - constant COLUMNS : POSITIVE := slm1'length(2); + constant ROWS : positive := slm1'length(1) + slm2'length(1); + constant COLUMNS : positive := slm1'length(2); variable slm : T_SLM(ROWS - 1 downto 0, COLUMNS - 1 downto 0); begin for i in slm1'range(1) loop @@ -305,8 +376,8 @@ package body vectors is end function; function slm_merge_cols(slm1 : T_SLM; slm2 : T_SLM) return T_SLM is - constant ROWS : POSITIVE := slm1'length(1); - constant COLUMNS : POSITIVE := slm1'length(2) + slm2'length(2); + constant ROWS : positive := slm1'length(1); + constant COLUMNS : positive := slm1'length(2) + slm2'length(2); variable slm : T_SLM(ROWS - 1 downto 0, COLUMNS - 1 downto 0); begin for i in slm1'range(1) loop @@ -324,8 +395,8 @@ package body vectors is -- Matrix to vector conversion: get_* -- ========================================================================== -- get a matrix column - function get_col(slm : T_SLM; ColIndex : NATURAL) return STD_LOGIC_VECTOR is - variable slv : STD_LOGIC_VECTOR(slm'range(1)); + function get_col(slm : T_SLM; ColIndex : natural) return std_logic_vector is + variable slv : std_logic_vector(slm'range(1)); begin for i in slm'range(1) loop slv(i) := slm(i, ColIndex); @@ -334,8 +405,8 @@ package body vectors is end function; -- get a matrix row - function get_row(slm : T_SLM; RowIndex : NATURAL) return STD_LOGIC_VECTOR is - variable slv : STD_LOGIC_VECTOR(slm'high(2) downto slm'low(2)); -- WORKAROUND: Xilinx iSIM work-around, because 'range(2) evaluates to 'range(1); see work-around notes at T_SLM type declaration + function get_row(slm : T_SLM; RowIndex : natural) return std_logic_vector is + variable slv : std_logic_vector(slm'high(2) downto slm'low(2)); -- WORKAROUND: Xilinx iSIM work-around, because 'range(2) evaluates to 'range(1); see work-around notes at T_SLM type declaration begin for i in slv'range loop slv(i) := slm(RowIndex, i); @@ -344,14 +415,14 @@ package body vectors is end function; -- get a matrix row of defined length [length - 1 downto 0] - function get_row(slm : T_SLM; RowIndex : NATURAL; Length : POSITIVE) return STD_LOGIC_VECTOR is + function get_row(slm : T_SLM; RowIndex : natural; Length : positive) return std_logic_vector is begin return get_row(slm, RowIndex, (Length - 1), 0); end function; -- get a sub vector of a matrix row at high:low - function get_row(slm : T_SLM; RowIndex : NATURAL; High : NATURAL; Low : NATURAL) return STD_LOGIC_VECTOR is - variable slv : STD_LOGIC_VECTOR(High downto Low); + function get_row(slm : T_SLM; RowIndex : natural; High : natural; Low : natural) return std_logic_vector is + variable slv : std_logic_vector(High downto Low); begin for i in slv'range loop slv(i) := slm(RowIndex, i); @@ -362,8 +433,8 @@ package body vectors is -- Convert to vector: to_slv -- ========================================================================== -- convert vector-vector to flatten vector - function to_slv(slvv : T_SLVV_2) return STD_LOGIC_VECTOR is - variable slv : STD_LOGIC_VECTOR((slvv'length * 2) - 1 downto 0); + function to_slv(slvv : T_SLVV_2) return std_logic_vector is + variable slv : std_logic_vector((slvv'length * 2) - 1 downto 0); begin for i in slvv'range loop slv((i * 2) + 1 downto (i * 2)) := slvv(i); @@ -371,8 +442,8 @@ package body vectors is return slv; end function; - function to_slv(slvv : T_SLVV_4) return STD_LOGIC_VECTOR is - variable slv : STD_LOGIC_VECTOR((slvv'length * 4) - 1 downto 0); + function to_slv(slvv : T_SLVV_4) return std_logic_vector is + variable slv : std_logic_vector((slvv'length * 4) - 1 downto 0); begin for i in slvv'range loop slv((i * 4) + 3 downto (i * 4)) := slvv(i); @@ -380,8 +451,8 @@ package body vectors is return slv; end function; - function to_slv(slvv : T_SLVV_8) return STD_LOGIC_VECTOR is - variable slv : STD_LOGIC_VECTOR((slvv'length * 8) - 1 downto 0); + function to_slv(slvv : T_SLVV_8) return std_logic_vector is + variable slv : std_logic_vector((slvv'length * 8) - 1 downto 0); begin for i in slvv'range loop slv((i * 8) + 7 downto (i * 8)) := slvv(i); @@ -389,8 +460,8 @@ package body vectors is return slv; end function; - function to_slv(slvv : T_SLVV_12) return STD_LOGIC_VECTOR is - variable slv : STD_LOGIC_VECTOR((slvv'length * 12) - 1 downto 0); + function to_slv(slvv : T_SLVV_12) return std_logic_vector is + variable slv : std_logic_vector((slvv'length * 12) - 1 downto 0); begin for i in slvv'range loop slv((i * 12) + 11 downto (i * 12)) := slvv(i); @@ -398,8 +469,8 @@ package body vectors is return slv; end function; - function to_slv(slvv : T_SLVV_16) return STD_LOGIC_VECTOR is - variable slv : STD_LOGIC_VECTOR((slvv'length * 16) - 1 downto 0); + function to_slv(slvv : T_SLVV_16) return std_logic_vector is + variable slv : std_logic_vector((slvv'length * 16) - 1 downto 0); begin for i in slvv'range loop slv((i * 16) + 15 downto (i * 16)) := slvv(i); @@ -407,8 +478,8 @@ package body vectors is return slv; end function; - function to_slv(slvv : T_SLVV_24) return STD_LOGIC_VECTOR is - variable slv : STD_LOGIC_VECTOR((slvv'length * 24) - 1 downto 0); + function to_slv(slvv : T_SLVV_24) return std_logic_vector is + variable slv : std_logic_vector((slvv'length * 24) - 1 downto 0); begin for i in slvv'range loop slv((i * 24) + 23 downto (i * 24)) := slvv(i); @@ -416,8 +487,8 @@ package body vectors is return slv; end function; - function to_slv(slvv : T_SLVV_32) return STD_LOGIC_VECTOR is - variable slv : STD_LOGIC_VECTOR((slvv'length * 32) - 1 downto 0); + function to_slv(slvv : T_SLVV_32) return std_logic_vector is + variable slv : std_logic_vector((slvv'length * 32) - 1 downto 0); begin for i in slvv'range loop slv((i * 32) + 31 downto (i * 32)) := slvv(i); @@ -425,8 +496,8 @@ package body vectors is return slv; end function; - function to_slv(slvv : T_SLVV_64) return STD_LOGIC_VECTOR is - variable slv : STD_LOGIC_VECTOR((slvv'length * 64) - 1 downto 0); + function to_slv(slvv : T_SLVV_64) return std_logic_vector is + variable slv : std_logic_vector((slvv'length * 64) - 1 downto 0); begin for i in slvv'range loop slv((i * 64) + 63 downto (i * 64)) := slvv(i); @@ -434,8 +505,8 @@ package body vectors is return slv; end function; - function to_slv(slvv : T_SLVV_128) return STD_LOGIC_VECTOR is - variable slv : STD_LOGIC_VECTOR((slvv'length * 128) - 1 downto 0); + function to_slv(slvv : T_SLVV_128) return std_logic_vector is + variable slv : std_logic_vector((slvv'length * 128) - 1 downto 0); begin for i in slvv'range loop slv((i * 128) + 127 downto (i * 128)) := slvv(i); @@ -444,8 +515,8 @@ package body vectors is end function; -- convert matrix to flatten vector - function to_slv(slm : T_SLM) return STD_LOGIC_VECTOR is - variable slv : STD_LOGIC_VECTOR((slm'length(1) * slm'length(2)) - 1 downto 0); + function to_slv(slm : T_SLM) return std_logic_vector is + variable slv : std_logic_vector((slm'length(1) * slm'length(2)) - 1 downto 0); begin for i in slm'range(1) loop for j in slm'high(2) downto slm'low(2) loop -- WORKAROUND: Xilinx iSIM work-around, because 'range(2) evaluates to 'range(1); see work-around notes at T_SLM type declaration @@ -459,7 +530,7 @@ package body vectors is -- Convert flat vector to a vector-vector: to_slvv_* -- ========================================================================== -- create vector-vector from vector (4 bit) - function to_slvv_4(slv : STD_LOGIC_VECTOR) return T_SLVV_4 is + function to_slvv_4(slv : std_logic_vector) return T_SLVV_4 is variable Result : T_SLVV_4((slv'length / 4) - 1 downto 0); begin if ((slv'length mod 4) /= 0) then report "to_slvv_4: width mismatch - slv'length is no multiple of 4 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if; @@ -471,7 +542,7 @@ package body vectors is end function; -- create vector-vector from vector (8 bit) - function to_slvv_8(slv : STD_LOGIC_VECTOR) return T_SLVV_8 is + function to_slvv_8(slv : std_logic_vector) return T_SLVV_8 is variable Result : T_SLVV_8((slv'length / 8) - 1 downto 0); begin if ((slv'length mod 8) /= 0) then report "to_slvv_8: width mismatch - slv'length is no multiple of 8 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if; @@ -483,7 +554,7 @@ package body vectors is end function; -- create vector-vector from vector (12 bit) - function to_slvv_12(slv : STD_LOGIC_VECTOR) return T_SLVV_12 is + function to_slvv_12(slv : std_logic_vector) return T_SLVV_12 is variable Result : T_SLVV_12((slv'length / 12) - 1 downto 0); begin if ((slv'length mod 12) /= 0) then report "to_slvv_12: width mismatch - slv'length is no multiple of 12 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if; @@ -495,7 +566,7 @@ package body vectors is end function; -- create vector-vector from vector (16 bit) - function to_slvv_16(slv : STD_LOGIC_VECTOR) return T_SLVV_16 is + function to_slvv_16(slv : std_logic_vector) return T_SLVV_16 is variable Result : T_SLVV_16((slv'length / 16) - 1 downto 0); begin if ((slv'length mod 16) /= 0) then report "to_slvv_16: width mismatch - slv'length is no multiple of 16 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if; @@ -507,7 +578,7 @@ package body vectors is end function; -- create vector-vector from vector (32 bit) - function to_slvv_32(slv : STD_LOGIC_VECTOR) return T_SLVV_32 is + function to_slvv_32(slv : std_logic_vector) return T_SLVV_32 is variable Result : T_SLVV_32((slv'length / 32) - 1 downto 0); begin if ((slv'length mod 32) /= 0) then report "to_slvv_32: width mismatch - slv'length is no multiple of 32 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if; @@ -519,7 +590,7 @@ package body vectors is end function; -- create vector-vector from vector (64 bit) - function to_slvv_64(slv : STD_LOGIC_VECTOR) return T_SLVV_64 is + function to_slvv_64(slv : std_logic_vector) return T_SLVV_64 is variable Result : T_SLVV_64((slv'length / 64) - 1 downto 0); begin if ((slv'length mod 64) /= 0) then report "to_slvv_64: width mismatch - slv'length is no multiple of 64 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if; @@ -531,7 +602,7 @@ package body vectors is end function; -- create vector-vector from vector (128 bit) - function to_slvv_128(slv : STD_LOGIC_VECTOR) return T_SLVV_128 is + function to_slvv_128(slv : std_logic_vector) return T_SLVV_128 is variable Result : T_SLVV_128((slv'length / 128) - 1 downto 0); begin if ((slv'length mod 128) /= 0) then report "to_slvv_128: width mismatch - slv'length is no multiple of 128 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if; @@ -543,7 +614,7 @@ package body vectors is end function; -- create vector-vector from vector (256 bit) - function to_slvv_256(slv : STD_LOGIC_VECTOR) return T_SLVV_256 is + function to_slvv_256(slv : std_logic_vector) return T_SLVV_256 is variable Result : T_SLVV_256((slv'length / 256) - 1 downto 0); begin if ((slv'length mod 256) /= 0) then report "to_slvv_256: width mismatch - slv'length is no multiple of 256 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if; @@ -555,7 +626,7 @@ package body vectors is end function; -- create vector-vector from vector (512 bit) - function to_slvv_512(slv : STD_LOGIC_VECTOR) return T_SLVV_512 is + function to_slvv_512(slv : std_logic_vector) return T_SLVV_512 is variable Result : T_SLVV_512((slv'length / 512) - 1 downto 0); begin if ((slv'length mod 512) /= 0) then report "to_slvv_512: width mismatch - slv'length is no multiple of 512 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if; @@ -572,7 +643,7 @@ package body vectors is function to_slvv_4(slm : T_SLM) return T_SLVV_4 is variable Result : T_SLVV_4(slm'range(1)); begin - if (slm'length(2) /= 4) then report "to_slvv_4: type mismatch - slm'length(2)=" & INTEGER'image(slm'length(2)) severity FAILURE; end if; + if (slm'length(2) /= 4) then report "to_slvv_4: type mismatch - slm'length(2)=" & integer'image(slm'length(2)) severity FAILURE; end if; for i in slm'range(1) loop Result(i) := get_row(slm, i); @@ -584,7 +655,7 @@ package body vectors is function to_slvv_8(slm : T_SLM) return T_SLVV_8 is variable Result : T_SLVV_8(slm'range(1)); begin - if (slm'length(2) /= 8) then report "to_slvv_8: type mismatch - slm'length(2)=" & INTEGER'image(slm'length(2)) severity FAILURE; end if; + if (slm'length(2) /= 8) then report "to_slvv_8: type mismatch - slm'length(2)=" & integer'image(slm'length(2)) severity FAILURE; end if; for i in slm'range(1) loop Result(i) := get_row(slm, i); @@ -596,7 +667,7 @@ package body vectors is function to_slvv_12(slm : T_SLM) return T_SLVV_12 is variable Result : T_SLVV_12(slm'range(1)); begin - if (slm'length(2) /= 12) then report "to_slvv_12: type mismatch - slm'length(2)=" & INTEGER'image(slm'length(2)) severity FAILURE; end if; + if (slm'length(2) /= 12) then report "to_slvv_12: type mismatch - slm'length(2)=" & integer'image(slm'length(2)) severity FAILURE; end if; for i in slm'range(1) loop Result(i) := get_row(slm, i); @@ -608,7 +679,7 @@ package body vectors is function to_slvv_16(slm : T_SLM) return T_SLVV_16 is variable Result : T_SLVV_16(slm'range(1)); begin - if (slm'length(2) /= 16) then report "to_slvv_16: type mismatch - slm'length(2)=" & INTEGER'image(slm'length(2)) severity FAILURE; end if; + if (slm'length(2) /= 16) then report "to_slvv_16: type mismatch - slm'length(2)=" & integer'image(slm'length(2)) severity FAILURE; end if; for i in slm'range(1) loop Result(i) := get_row(slm, i); @@ -620,7 +691,7 @@ package body vectors is function to_slvv_32(slm : T_SLM) return T_SLVV_32 is variable Result : T_SLVV_32(slm'range(1)); begin - if (slm'length(2) /= 32) then report "to_slvv_32: type mismatch - slm'length(2)=" & INTEGER'image(slm'length(2)) severity FAILURE; end if; + if (slm'length(2) /= 32) then report "to_slvv_32: type mismatch - slm'length(2)=" & integer'image(slm'length(2)) severity FAILURE; end if; for i in slm'range(1) loop Result(i) := get_row(slm, i); @@ -632,7 +703,7 @@ package body vectors is function to_slvv_64(slm : T_SLM) return T_SLVV_64 is variable Result : T_SLVV_64(slm'range(1)); begin - if (slm'length(2) /= 64) then report "to_slvv_64: type mismatch - slm'length(2)=" & INTEGER'image(slm'length(2)) severity FAILURE; end if; + if (slm'length(2) /= 64) then report "to_slvv_64: type mismatch - slm'length(2)=" & integer'image(slm'length(2)) severity FAILURE; end if; for i in slm'range(1) loop Result(i) := get_row(slm, i); @@ -644,7 +715,7 @@ package body vectors is function to_slvv_128(slm : T_SLM) return T_SLVV_128 is variable Result : T_SLVV_128(slm'range(1)); begin - if (slm'length(2) /= 128) then report "to_slvv_128: type mismatch - slm'length(2)=" & INTEGER'image(slm'length(2)) severity FAILURE; end if; + if (slm'length(2) /= 128) then report "to_slvv_128: type mismatch - slm'length(2)=" & integer'image(slm'length(2)) severity FAILURE; end if; for i in slm'range(1) loop Result(i) := get_row(slm, i); @@ -656,7 +727,7 @@ package body vectors is function to_slvv_256(slm : T_SLM) return T_SLVV_256 is variable Result : T_SLVV_256(slm'range); begin - if (slm'length(2) /= 256) then report "to_slvv_256: type mismatch - slm'length(2)=" & INTEGER'image(slm'length(2)) severity FAILURE; end if; + if (slm'length(2) /= 256) then report "to_slvv_256: type mismatch - slm'length(2)=" & integer'image(slm'length(2)) severity FAILURE; end if; for i in slm'range loop Result(i) := get_row(slm, i); @@ -668,7 +739,7 @@ package body vectors is function to_slvv_512(slm : T_SLM) return T_SLVV_512 is variable Result : T_SLVV_512(slm'range(1)); begin - if (slm'length(2) /= 512) then report "to_slvv_512: type mismatch - slm'length(2)=" & INTEGER'image(slm'length(2)) severity FAILURE; end if; + if (slm'length(2) /= 512) then report "to_slvv_512: type mismatch - slm'length(2)=" & integer'image(slm'length(2)) severity FAILURE; end if; for i in slm'range(1) loop Result(i) := get_row(slm, i); @@ -679,7 +750,7 @@ package body vectors is -- Convert vector-vector to matrix: to_slm -- ========================================================================== -- create matrix from vector - function to_slm(slv : STD_LOGIC_VECTOR; ROWS : POSITIVE; COLS : POSITIVE) return T_SLM is + function to_slm(slv : std_logic_vector; ROWS : positive; COLS : positive) return T_SLM is variable slm : T_SLM(ROWS - 1 downto 0, COLS - 1 downto 0); begin for i in 0 to ROWS - 1 loop @@ -705,7 +776,7 @@ package body vectors is function to_slm(slvv : T_SLVV_8) return T_SLM is -- variable test : STD_LOGIC_VECTOR(T_SLV_8'range); -- variable slm : T_SLM(slvv'range, test'range); -- BUG: iSIM 14.5 cascaded 'range accesses let iSIM break down --- variable slm : T_SLM(slvv'range, T_SLV_8'range); -- BUG: iSIM 14.5 allocates 9 bits in dimmension 2 +-- variable slm : T_SLM(slvv'range, T_SLV_8'range); -- BUG: iSIM 14.5 allocates 9 bits in dimension 2 variable slm : T_SLM(slvv'range, 7 downto 0); -- WORKAROUND: use constant range begin -- report "slvv: slvv.length=" & INTEGER'image(slvv'length) & " slm.dim0.length=" & INTEGER'image(slm'length(1)) & " slm.dim1.length=" & INTEGER'image(slm'length(2)) severity NOTE; @@ -903,7 +974,7 @@ package body vectors is -- Resizes the vector to the specified length. Input vectors larger than the specified size are truncated from the left side. Smaller input -- vectors are extended on the left by the provided fill value (default: '0'). Use the resize functions of the numeric_std package for -- value-preserving resizes of the signed and unsigned data types. - function resize(slm : T_SLM; size : POSITIVE) return T_SLM is + function resize(slm : T_SLM; size : positive) return T_SLM is variable Result : T_SLM(size - 1 downto 0, slm'high(2) downto slm'low(2)) := (others => (others => '0')); -- WORKAROUND: Xilinx iSIM work-around, because 'range(2) evaluates to 'range(1); see work-around notes at T_SLM type declaration begin for i in slm'range(1) loop @@ -914,10 +985,10 @@ package body vectors is return Result; end function; - function to_string(slvv : T_SLVV_8; sep : CHARACTER := ':') return STRING is - constant hex_len : POSITIVE := ite((sep = C_POC_NUL), (slvv'length * 2), (slvv'length * 3) - 1); - variable Result : STRING(1 to hex_len) := (others => sep); - variable pos : POSITIVE := 1; + function to_string(slvv : T_SLVV_8; sep : character := ':') return string is + constant hex_len : positive := ite((sep = C_POC_NUL), (slvv'length * 2), (slvv'length * 3) - 1); + variable Result : string(1 to hex_len) := (others => sep); + variable pos : positive := 1; begin for i in slvv'range loop Result(pos to pos + 1) := to_string(slvv(i), 'h'); @@ -926,11 +997,11 @@ package body vectors is return Result; end function; - function to_string_bin(slm : T_SLM; groups : POSITIVE := 4; format : CHARACTER := 'h') return STRING is - variable PerLineOverheader : POSITIVE := div_ceil(slm'length(2), groups); - variable Result : STRING(1 to (slm'length(1) * (slm'length(2) + PerLineOverheader)) + 10); - variable Writer : POSITIVE; - variable GroupCounter : NATURAL; + function to_string_bin(slm : T_SLM; groups : positive := 4; format : character := 'h') return string is + variable PerLineOverheader : positive := div_ceil(slm'length(2), groups); + variable Result : string(1 to (slm'length(1) * (slm'length(2) + PerLineOverheader)) + 10); + variable Writer : positive; + variable GroupCounter : natural; begin Result := (others => C_POC_NUL); Result(1) := LF; @@ -941,7 +1012,7 @@ package body vectors is Result(Writer) := to_char(slm(i, j)); Writer := Writer + 1; GroupCounter := GroupCounter + 1; - if (GroupCounter = groups) then + if GroupCounter = groups then Result(Writer) := ' '; Writer := Writer + 1; GroupCounter := 0; @@ -953,7 +1024,7 @@ package body vectors is return str_trim(Result); end function; - function to_string(slm : T_SLM; groups : POSITIVE := 4; format : CHARACTER := 'b') return STRING is + function to_string(slm : T_SLM; groups : positive := 4; format : character := 'b') return string is begin if (format = 'b') then return to_string_bin(slm, groups); diff --git a/src/dstruct/dstruct.pkg.vhdl b/src/dstruct/dstruct.pkg.vhdl index 6e9b036e..1a5f41f2 100644 --- a/src/dstruct/dstruct.pkg.vhdl +++ b/src/dstruct/dstruct.pkg.vhdl @@ -1,7 +1,7 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- =========================================================================== +-- ============================================================================= -- Authors: Jens Voss -- -- Package: dstruct diff --git a/src/dstruct/dstruct_deque.vhdl b/src/dstruct/dstruct_deque.vhdl index 40012caf..879c11f5 100644 --- a/src/dstruct/dstruct_deque.vhdl +++ b/src/dstruct/dstruct_deque.vhdl @@ -1,20 +1,19 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- ============================================================================ +-- ============================================================================= -- Authors: Jens Voss -- --- Entity: dstruct_deque +-- Entity: Double-ended queue -- -- Description: --- ------------ --- Implements a deque, i.e. a double-ended queue. This datastructures --- allows two acting entities to queue data elements for the consumption --- by the other while still being able to unqueue untaken ones in --- LIFO fashion. +-- ------------------------------------- +-- Implements a deque (double-ended queue). This data structure allows two +-- acting entities to queue data elements for the consumption by the other while +-- still being able to unqueue untaken ones in LIFO fashion. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -29,10 +28,11 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; -use IEEE.std_logic_1164.all; +use IEEE.std_logic_1164.all; + entity dstruct_deque is generic ( @@ -59,7 +59,7 @@ entity dstruct_deque is validB : out std_logic; fullB : out std_logic ); -end dstruct_deque; +end entity dstruct_deque; library IEEE; @@ -95,7 +95,7 @@ architecture rtl of dstruct_deque is -- Stackpointer -- A - signal stackpointerA : unsigned (A_BITS-1 downto 0) := shift_right(to_unsigned(MIN_DEPTH-1,A_BITS),1) ; + signal stackpointerA : unsigned (A_BITS-1 downto 0) := shift_right(to_unsigned(MIN_DEPTH-1,A_BITS),1); -- signal reA : std_logic := '0'; signal weA : std_logic := '0'; -- B @@ -165,7 +165,7 @@ begin -- reB <= '1'; adrB <= stackpointerB - 2; last_op_ctrl <= UNSET; - if (ctrl = "01") then + if ctrl = "01" then if(last_operation = '0') then --> deque is empty! -- B couldn't read a valid value => don't update SP! @@ -173,7 +173,7 @@ begin adrB <= stackpointerB - 1; last_op_ctrl <= UNSET; end if; - elsif (ctrl = "10") then + elsif ctrl = "10" then --> only one element left -- side B saw empty signal -- so B couldn't read a valid value @@ -186,7 +186,7 @@ begin weB <= '1'; adrB <= stackpointerB; last_op_ctrl <= SET; - if (ctrl = "01") then + if ctrl = "01" then if(last_operation = '1') then --> deque is full! -- B cant write => don't update SP! @@ -198,7 +198,7 @@ begin --> delay validA signal for one clk cycle delay <= '1'; end if; - elsif (ctrl = "00") then + elsif ctrl = "00" then --> only one spot left -- B isn't allowed to write -- B sees full signal atm @@ -213,7 +213,7 @@ begin adrB <= stackpointerB - 1; weB <= '1'; last_op_ctrl <= SET; - if (ctrl = "01") then + if ctrl = "01" then if (last_operation = '1') then --> deque is full! -- B read a valid value but new value cant be pushed! @@ -231,14 +231,14 @@ begin last_op_ctrl <= SET; delay <= '1'; end if; - elsif (ctrl = "10") then + elsif ctrl = "10" then --> only one element left -- B couldn't read it, but can write new value ctrlB <= PUSH; weB <= '1'; adrB <= stackpointerB; last_op_ctrl <= SET; - elsif (ctrl = "00") then + elsif ctrl = "00" then -- only one spot left -- B read a valid value but cant write new value ctrlB <= POP; @@ -269,7 +269,7 @@ begin -- reA <= '1'; adrA <= stackpointerA + 2; last_op_ctrl <= UNSET; - if (ctrl = "01") then + if ctrl = "01" then if (last_operation = '1') then --> deque is full -- A and B read a valid value! @@ -282,7 +282,7 @@ begin adrA <= stackpointerA + 1; adrB <= stackpointerB - 1; end if; - elsif (ctrl = "10") then + elsif ctrl = "10" then -- A and B both tried to read last value! -- but only A was allowed to read value so only update stackpointerA ctrlA <= POP; @@ -298,7 +298,7 @@ begin weB <= '1'; adrB <= stackpointerB; last_op_ctrl <= SET; - if (ctrl = "01") then + if ctrl = "01" then if(last_operation = '1') then --> deque is full! -- A read a valid value, but B cant push! @@ -315,12 +315,12 @@ begin last_op_ctrl <= SET; delay <= '1'; end if; - elsif (ctrl = "10") then + elsif ctrl = "10" then --> only one element in deque --> A read valid value and B can write new value --> But validA has to be delayed! delay <= '1'; - elsif (ctrl = "00") then + elsif ctrl = "00" then --> only one spot left -- A read valid value, but B isn't allowed to write last value ctrlB <= IDLE; @@ -338,7 +338,7 @@ begin adrA <= stackpointerA + 2; -- reA <= '1'; last_op_ctrl <= SET; - if (ctrl = "01") then + if ctrl = "01" then if last_operation = '1' then --> deque is full! -- A and B read a valid value, but B cant push! @@ -358,7 +358,7 @@ begin last_op_ctrl <= SET; delay <= '1'; end if; - elsif (ctrl = "00") then + elsif ctrl = "00" then --> only one spot left -- A and B read valid values, but B isn't allowed to write new value -- B sees full signal atm @@ -366,7 +366,7 @@ begin weB <= '0'; adrB <= stackpointerB - 2; last_op_ctrl <= UNSET; - elsif (ctrl = "10") then + elsif ctrl = "10" then --> only one element in deque -- only A read a valid value, but B can write a new value --> validA has to be delayed! @@ -383,7 +383,7 @@ begin weA <= '1'; adrA <= stackpointerA; last_op_ctrl <= SET; - if (ctrl = "01") then + if ctrl = "01" then if (last_operation = '1') then --> deque is full -- A cant write! @@ -402,7 +402,7 @@ begin adrA <= stackpointerA; adrB <= stackpointerB - 2; last_op_ctrl <= SET; - if (ctrl = "01") then + if ctrl = "01" then if (last_operation = '1') then --> deque is full! -- A cant write, but B read a valid value! @@ -417,7 +417,7 @@ begin adrB <= stackpointerB - 1; last_op_ctrl <= SET; end if; - elsif (ctrl = "10") then + elsif ctrl = "10" then --> only one element left -- A can write new value, but B couldn't read a valid value -- B sees empty signal atm @@ -435,7 +435,7 @@ begin weB <= '1'; adrB <= stackpointerB; last_op_ctrl <= SET; - if (ctrl = "01") then + if ctrl = "01" then if (last_operation = '1') then --> deque is full! -- A and B cant write! @@ -451,7 +451,7 @@ begin --> A and B can write! last_op_ctrl <= SET; end if; - elsif (ctrl = "00") then + elsif ctrl = "00" then --> only one spot left. -- only A is allowed to write -- B got full signal @@ -469,7 +469,7 @@ begin weB <= '1'; adrB <= stackpointerB - 1; last_op_ctrl <= SET; - if (ctrl = "01") then + if ctrl = "01" then if (last_operation = '1') then --> deque is full! -- A and B cant write, but B read a valid value! @@ -487,14 +487,14 @@ begin adrB <= stackpointerB; last_op_ctrl <= SET; end if; - elsif (ctrl = "00") then + elsif ctrl = "00" then --> only one spot left -- only A can write last value -- B only read a valid value ctrlB <= POP; weB <= '0'; adrB <= stackpointerB - 2; - elsif (ctrl = "10") then + elsif ctrl = "10" then --> only one element left --> B couldn't read value but A and B are allowed to write new values ctrlB <= PUSH; @@ -509,7 +509,7 @@ begin weA <= '1'; adrA <= stackpointerA + 1; last_op_ctrl <= SET; - if (ctrl = "01") then + if ctrl = "01" then if (last_operation = '1') then --> deque is full! -- A cant write, but read a valid value! @@ -536,7 +536,7 @@ begin -- reB <= '1'; adrB <= stackpointerB - 2; last_op_ctrl <= SET; - if (ctrl = "01") then + if ctrl = "01" then if (last_operation = '1') then --> deque is full! -- A cant write new values, but A and B could read a valid value @@ -554,7 +554,7 @@ begin adrA <= stackpointerA; last_op_ctrl <= SET; end if; - elsif (ctrl = "10") then + elsif ctrl = "10" then --> only one element in deque -- only A read valid value and can write a new value adrB <= stackpointerB - 1; @@ -574,7 +574,7 @@ begin weB <= '1'; adrB <= stackpointerB; last_op_ctrl <= SET; - if (ctrl = "01") then + if ctrl = "01" then if (last_operation = '1') then --> deque is full! -- A and B cant write, but A could read valid value @@ -593,7 +593,7 @@ begin adrA <= stackpointerA; last_op_ctrl <= SET; end if; - elsif (ctrl = "00") then + elsif ctrl = "00" then --> only one spot left -- B cant write new value ctrlB <= IDLE; @@ -612,7 +612,7 @@ begin -- reB <= '1'; adrB <= stackpointerB - 1; last_op_ctrl <= SET; - if (ctrl = "01") then + if ctrl = "01" then if last_operation = '1' then --> deque is full -- A and B could read valid values but cant write new values @@ -632,14 +632,14 @@ begin adrB <= stackpointerB; last_op_ctrl <= SET; end if; - elsif (ctrl = "10") then + elsif ctrl = "10" then --> only one element left -- only A read last value, A replaces the last element -- B just writes new value -- B sees empty signal atm ctrlB <= PUSH; adrB <= stackpointerB; - elsif (ctrl = "00") then + elsif ctrl = "00" then --> only one spot left -- B read a valid value, but isn't allowed to write -- B sees full signal atm @@ -656,7 +656,7 @@ begin process(clk) begin - if (rising_edge(clk)) then + if rising_edge(clk) then if (rst = '1') then last_operation <= '0'; else @@ -677,7 +677,7 @@ begin --stackpointerA operations process(clk) begin - if (rising_edge(clk)) then + if rising_edge(clk) then if (rst = '1') then stackpointerA <= shift_right(to_unsigned(MIN_DEPTH-1,A_BITS),1); else @@ -698,7 +698,7 @@ begin -- stackpointerB operations process(clk) begin - if (rising_edge(clk)) then + if rising_edge(clk) then if (rst = '1') then stackpointerB <= shift_right(to_unsigned(MIN_DEPTH-1,A_BITS),1) + 1; else @@ -719,7 +719,7 @@ begin -- delayed_valid register process(clk) begin - if (rising_edge(clk)) then + if rising_edge(clk) then if(rst = '1') then delayed_valid <= '0'; else diff --git a/src/dstruct/dstruct_stack.vhdl b/src/dstruct/dstruct_stack.vhdl index 78faa7d6..e714a6d8 100644 --- a/src/dstruct/dstruct_stack.vhdl +++ b/src/dstruct/dstruct_stack.vhdl @@ -1,17 +1,17 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- ============================================================================ +-- ============================================================================= -- Authors: Jens Voss -- --- Entity: dstruct_stack +-- Entity: Stack (LIFO) -- -- Description: --- ------------ --- Implements a stack, i.e. a LIFO storage abstraction. +-- ------------------------------------- +-- Implements a stack, a LIFO storage abstraction. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -26,10 +26,11 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; -use IEEE.std_logic_1164.all; +use IEEE.std_logic_1164.all; + entity dstruct_stack is generic ( @@ -50,7 +51,7 @@ entity dstruct_stack is dout : out std_logic_vector(D_BITS-1 downto 0); valid : out std_logic ); -end dstruct_stack; +end entity dstruct_stack; library IEEE; @@ -102,7 +103,7 @@ begin process(clk) begin - if(rising_edge(clk)) then + if rising_edge(clk) then if(rst = '1') then current_state <= SEMPTY; else @@ -146,7 +147,7 @@ begin ctrl <= PUSH; s_adr <= stackpointer; we <= '1'; - if (stackpointer = (MIN_DEPTH - 1)) then + if stackpointer = (MIN_DEPTH - 1) then next_state <= SFULL; end if; elsif (got = '1' and put = '1') then @@ -178,7 +179,7 @@ begin process(clk) begin - if (rising_edge(clk)) then + if rising_edge(clk) then case( ctrl ) is when IDLE => stackpointer <= stackpointer; diff --git a/src/fifo/fifo.pkg.vhdl b/src/fifo/fifo.pkg.vhdl index 740f2d5c..22106658 100644 --- a/src/fifo/fifo.pkg.vhdl +++ b/src/fifo/fifo.pkg.vhdl @@ -1,7 +1,6 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Thomas B. Preusser -- Steffen Koehler @@ -12,7 +11,7 @@ -- associated to the PoC.fifo namespace -- -- Description: --- ------------------------------------ +-- ------------------------------------- -- For detailed documentation see below. -- -- License: diff --git a/src/fifo/fifo_cc_got.vhdl b/src/fifo/fifo_cc_got.vhdl index f0b4f5a4..48168c3f 100644 --- a/src/fifo/fifo_cc_got.vhdl +++ b/src/fifo/fifo_cc_got.vhdl @@ -1,48 +1,74 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Thomas B. Preusser -- Steffen Koehler -- Martin Zabel -- Patrick Lehmann -- --- Module: FIFO, Common Clock (cc), Pipelined Interface +-- Entity: FIFO, Common Clock (cc), Pipelined Interface -- -- Description: --- ------------------------------------ --- The specified depth (MIN_DEPTH) is rounded up to the next suitable value. +-- ------------------------------------- +-- This module implements a regular FIFO with common clock (cc), pipelined +-- interface. Common clock means read and write port use the same clock. The +-- FIFO size can be configured in word width (``D_BITS``) and minimum word count +-- ``MIN_DEPTH``. The specified depth is rounded up to the next suitable value. +-- +-- ``DATA_REG`` (=true) is a hint, that distributed memory or registers should +-- be used as data storage. The actual memory type depends on the device +-- architecture. See implementation for details. +-- +-- ``*STATE_*_BITS`` defines the granularity of the fill state indicator +-- ``*state_*``. If a fill state is not of interest, set ``*STATE_*_BITS = 0``. +-- ``fstate_rd`` is associated with the read clock domain and outputs the +-- guaranteed number of words available in the FIFO. ``estate_wr`` is associated +-- with the write clock domain and outputs the number of words that is +-- guaranteed to be accepted by the FIFO without a capacity overflow. Note that +-- both these indicators cannot replace the ``full`` or ``valid`` outputs as +-- they may be implemented as giving pessimistic bounds that are minimally off +-- the true fill state. +-- +-- ``fstate_rd`` and ``estate_wr`` are combinatorial outputs and include an address +-- comparator (subtractor) in their path. -- --- DATA_REG (=true) is a hint, that distributed memory or registers should be --- used as data storage. The actual memory type depends on the device --- architecture. See implementation for details. +-- .. rubric:: Examples: -- --- *STATE_*_BITS defines the granularity of the fill state indicator --- '*state_*'. 'fstate_rd' is associated with the read clock domain and outputs --- the guaranteed number of words available in the FIFO. 'estate_wr' is --- associated with the write clock domain and outputs the number of words that --- is guaranteed to be accepted by the FIFO without a capacity overflow. Note --- that both these indicators cannot replace the 'full' or 'valid' outputs as --- they may be implemented as giving pessimistic bounds that are minimally off --- the true fill state. +-- * FSTATE_RD_BITS = 1: -- --- If a fill state is not of interest, set *STATE_*_BITS = 0. +-- +-----------+----------------------+ +-- | fstate_rd | filled (at least) | +-- +===========+======================+ +-- | 0 | 0/2 full | +-- +-----------+----------------------+ +-- | 1 | 1/2 full (half full) | +-- +-----------+----------------------+ -- --- 'fstate_rd' and 'estate_wr' are combinatorial outputs and include an address --- comparator (subtractor) in their path. +-- * FSTATE_RD_BITS = 2: -- --- Examples: --- - FSTATE_RD_BITS = 1: fstate_rd == 0 => 0/2 full --- fstate_rd == 1 => 1/2 full (half full) +-- +-----------+----------------------+ +-- | fstate_rd | filled (at least) | +-- +===========+======================+ +-- | 0 | 0/4 full | +-- +-----------+----------------------+ +-- | 1 | 1/4 full | +-- +-----------+----------------------+ +-- | 2 | 2/4 full (half full) | +-- +-----------+----------------------+ +-- | 3 | 3/4 full | +-- +-----------+----------------------+ -- --- - FSTATE_RD_BITS = 2: fstate_rd == 0 => 0/4 full --- fstate_rd == 1 => 1/4 full --- fstate_rd == 2 => 2/4 full --- fstate_rd == 3 => 3/4 full +-- SeeAlso: +-- :doc:`PoC.fifo.dc_got ` +-- For a FIFO with dependent clocks. +-- :doc:`PoC.fifo.ic_got ` +-- For a FIFO with independent clocks (cross-clock FIFO). +-- :doc:`PoC.fifo.glue ` +-- For a minimal FIFO / pipeline decoupling. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -57,7 +83,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.std_logic_1164.all; @@ -95,7 +121,7 @@ entity fifo_cc_got is valid : out std_logic; fstate_rd : out std_logic_vector(imax(0, FSTATE_RD_BITS-1) downto 0) ); -end fifo_cc_got; +end entity fifo_cc_got; architecture rtl of fifo_cc_got is @@ -132,10 +158,10 @@ begin ----------------------------------------------------------------------------- -- Pointer Logic blkPointer : block - signal IP0_slv : STD_LOGIC_VECTOR(IP0'range); - signal IP1_slv : STD_LOGIC_VECTOR(IP0'range); - signal OP0_slv : STD_LOGIC_VECTOR(IP0'range); - signal OP1_slv : STD_LOGIC_VECTOR(IP0'range); + signal IP0_slv : std_logic_vector(IP0'range); + signal IP1_slv : std_logic_vector(IP0'range); + signal OP0_slv : std_logic_vector(IP0'range); + signal OP1_slv : std_logic_vector(IP0'range); begin IP0_slv <= std_logic_vector(IP0); OP0_slv <= std_logic_vector(OP0); @@ -375,7 +401,7 @@ begin begin if rising_edge(clk) then --synthesis translate_off - if SIMULATION AND (rst = '1') then + if SIMULATION and (rst = '1') then regfile <= (others => (others => '-')); else --synthesis translate_on diff --git a/src/fifo/fifo_cc_got_tempgot.vhdl b/src/fifo/fifo_cc_got_tempgot.vhdl index eb0246c3..998a1555 100644 --- a/src/fifo/fifo_cc_got_tempgot.vhdl +++ b/src/fifo/fifo_cc_got_tempgot.vhdl @@ -1,59 +1,58 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================================================================================================ --- Module: FIFO, common clock (cc), pipelined interface, --- reads only become effective after explicit commit --- +-- ============================================================================= -- Authors: Thomas B. Preusser -- Steffen Koehler -- Martin Zabel -- Patrick Lehmann -- +-- Entity: FIFO, common clock (cc), pipelined interface, reads only become effective after explicit commit +-- -- Description: --- ------------------------------------ --- The specified depth (MIN_DEPTH) is rounded up to the next suitable value. +-- ------------------------------------- +-- The specified depth (``MIN_DEPTH``) is rounded up to the next suitable value. -- --- As uncommitted reads occupy FIFO space that is not yet available for --- writing, an instance of this FIFO can, indeed, report 'full' and 'not vld' --- at the same time. While a 'commit' would eventually make space available for --- writing ('not ful'), a 'rollback' would re-iterate data for reading --- ('vld'). +-- As uncommitted reads occupy FIFO space that is not yet available for +-- writing, an instance of this FIFO can, indeed, report ``full`` and ``not vld`` +-- at the same time. While a ``commit`` would eventually make space available for +-- writing (``not ful``), a ``rollback`` would re-iterate data for reading +-- (``vld``). -- --- 'commit' and 'rollback' are inclusive and apply to all reads ('got') since --- the previous 'commit' or 'rollback' up to and including a potentially --- simultaneous read. +-- ``commit`` and ``rollback`` are inclusive and apply to all reads (``got``) since +-- the previous ``commit`` or ``rollback`` up to and including a potentially +-- simultaneous read. -- --- The FIFO state upon a simultaneous assertion of 'commit' and 'rollback' is --- *undefined*! +-- The FIFO state upon a simultaneous assertion of ``commit`` and ``rollback`` is +-- *undefined*! -- --- *STATE_*_BITS defines the granularity of the fill state indicator --- '*state_*'. 'fstate_rd' is associated with the read clock domain and outputs --- the guaranteed number of words available in the FIFO. 'estate_wr' is --- associated with the write clock domain and outputs the number of words that --- is guaranteed to be accepted by the FIFO without a capacity overflow. Note --- that both these indicators cannot replace the 'full' or 'valid' outputs as --- they may be implemented as giving pessimistic bounds that are minimally off --- the true fill state. +-- ``*STATE_*_BITS`` defines the granularity of the fill state indicator +-- ``*state_*``. ``fstate_rd`` is associated with the read clock domain and outputs +-- the guaranteed number of words available in the FIFO. ``estate_wr`` is +-- associated with the write clock domain and outputs the number of words that +-- is guaranteed to be accepted by the FIFO without a capacity overflow. Note +-- that both these indicators cannot replace the ``full`` or ``valid`` outputs as +-- they may be implemented as giving pessimistic bounds that are minimally off +-- the true fill state. -- --- If a fill state is not of interest, set *STATE_*_BITS = 0. +-- If a fill state is not of interest, set ``*STATE_*_BITS = 0``. -- --- 'fstate_rd' and 'estate_wr' are combinatorial outputs and include an address --- comparator (subtractor) in their path. +-- ``fstate_rd`` and ``estate_wr`` are combinatorial outputs and include an address +-- comparator (subtractor) in their path. -- --- Examples: --- - FSTATE_RD_BITS = 1: fstate_rd == 0 => 0/2 full --- fstate_rd == 1 => 1/2 full (half full) +-- Examples: +-- - FSTATE_RD_BITS = 1: fstate_rd == 0 => 0/2 full +-- fstate_rd == 1 => 1/2 full (half full) -- --- - FSTATE_RD_BITS = 2: fstate_rd == 0 => 0/4 full --- fstate_rd == 1 => 1/4 full --- fstate_rd == 2 => 2/4 full --- fstate_rd == 3 => 3/4 full +-- - FSTATE_RD_BITS = 2: fstate_rd == 0 => 0/4 full +-- fstate_rd == 1 => 1/4 full +-- fstate_rd == 2 => 2/4 full +-- fstate_rd == 3 => 3/4 full -- -- License: --- ============================================================================================================================================================ --- Copyright 2007-2014 Technische Universitaet Dresden - Germany, Chair for VLSI-Design, Diagnostics and Architecture +-- ============================================================================= +-- Copyright 2007-2014 Technische Universitaet Dresden - Germany, +-- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. @@ -66,7 +65,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================================================================================================ +-- ============================================================================= library IEEE; use IEEE.std_logic_1164.all; @@ -107,7 +106,7 @@ entity fifo_cc_got_tempgot is commit : in std_logic; rollback : in std_logic ); -end fifo_cc_got_tempgot; +end entity fifo_cc_got_tempgot; architecture rtl of fifo_cc_got_tempgot is @@ -129,7 +128,7 @@ architecture rtl of fifo_cc_got_tempgot is signal IP1 : unsigned(A_BITS-1 downto 0); signal OP1 : unsigned(A_BITS-1 downto 0); - -- Commited Read Pointer (Commit Marker) + -- Committed Read Pointer (Commit Marker) signal OPm : unsigned(A_BITS-1 downto 0) := (others => '0'); ----------------------------------------------------------------------------- @@ -152,10 +151,10 @@ begin ----------------------------------------------------------------------------- -- Pointer Logic blkPointer : block - signal IP0_slv : STD_LOGIC_VECTOR(IP0'range); - signal IP1_slv : STD_LOGIC_VECTOR(IP0'range); - signal OP0_slv : STD_LOGIC_VECTOR(IP0'range); - signal OP1_slv : STD_LOGIC_VECTOR(IP0'range); + signal IP0_slv : std_logic_vector(IP0'range); + signal IP1_slv : std_logic_vector(IP0'range); + signal OP0_slv : std_logic_vector(IP0'range); + signal OP1_slv : std_logic_vector(IP0'range); begin IP0_slv <= std_logic_vector(IP0); OP0_slv <= std_logic_vector(OP0); @@ -398,7 +397,7 @@ begin begin if rising_edge(clk) then --synthesis translate_off - if SIMULATION AND (rst = '1') then + if SIMULATION and (rst = '1') then regfile <= (others => (others => '-')); else --synthesis translate_on @@ -419,4 +418,4 @@ begin end generate genSmall; -end rtl; +end architecture; diff --git a/src/fifo/fifo_cc_got_tempput.vhdl b/src/fifo/fifo_cc_got_tempput.vhdl index c91886a7..169c7837 100644 --- a/src/fifo/fifo_cc_got_tempput.vhdl +++ b/src/fifo/fifo_cc_got_tempput.vhdl @@ -1,59 +1,58 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================================================================================================ --- Module: FIFO, common clock (cc), pipelined interface, --- writes only become effective after explicit commit --- +-- ============================================================================= -- Authors: Thomas B. Preusser -- Steffen Koehler -- Martin Zabel -- Patrick Lehmann -- +-- Entity: FIFO, common clock (cc), pipelined interface, writes only become effective after explicit commit +-- -- Description: --- ------------------------------------ --- The specified depth (MIN_DEPTH) is rounded up to the next suitable value. +-- ------------------------------------- +-- The specified depth (``MIN_DEPTH``) is rounded up to the next suitable value. -- --- As uncommitted writes populate FIFO space that is not yet available for --- reading, an instance of this FIFO can, indeed, report 'full' and 'not vld' --- at the same time. While a 'commit' would eventually make data available for --- reading ('vld'), a 'rollback' would free the space for subsequent writing --- ('not ful'). +-- As uncommitted writes populate FIFO space that is not yet available for +-- reading, an instance of this FIFO can, indeed, report ``full`` and ``not vld`` +-- at the same time. While a ``commit`` would eventually make data available for +-- reading (``vld``), a ``rollback`` would free the space for subsequent writing +-- (``not ful``). -- --- 'commit' and 'rollback' are inclusive and apply to all writes ('put') since --- the previous 'commit' or 'rollback' up to and including a potentially --- simultaneous write. +-- ``commit`` and ``rollback`` are inclusive and apply to all writes (``put``) since +-- the previous 'commit' or 'rollback' up to and including a potentially +-- simultaneous write. -- --- The FIFO state upon a simultaneous assertion of 'commit' and 'rollback' is --- *undefined*! +-- The FIFO state upon a simultaneous assertion of ``commit`` and ``rollback`` is +-- *undefined*. -- --- *STATE_*_BITS defines the granularity of the fill state indicator --- '*state_*'. 'fstate_rd' is associated with the read clock domain and outputs --- the guaranteed number of words available in the FIFO. 'estate_wr' is --- associated with the write clock domain and outputs the number of words that --- is guaranteed to be accepted by the FIFO without a capacity overflow. Note --- that both these indicators cannot replace the 'full' or 'valid' outputs as --- they may be implemented as giving pessimistic bounds that are minimally off --- the true fill state. +-- ``*STATE_*_BITS`` defines the granularity of the fill state indicator +-- ``*state_*``. ``fstate_rd`` is associated with the read clock domain and outputs +-- the guaranteed number of words available in the FIFO. ``estate_wr`` is +-- associated with the write clock domain and outputs the number of words that +-- is guaranteed to be accepted by the FIFO without a capacity overflow. Note +-- that both these indicators cannot replace the ``full`` or ``valid`` outputs as +-- they may be implemented as giving pessimistic bounds that are minimally off +-- the true fill state. -- --- If a fill state is not of interest, set *STATE_*_BITS = 0. +-- If a fill state is not of interest, set ``*STATE_*_BITS = 0``. -- --- 'fstate_rd' and 'estate_wr' are combinatorial outputs and include an address --- comparator (subtractor) in their path. +-- ``fstate_rd`` and ``estate_wr`` are combinatorial outputs and include an address +-- comparator (subtractor) in their path. -- --- Examples: --- - FSTATE_RD_BITS = 1: fstate_rd == 0 => 0/2 full --- fstate_rd == 1 => 1/2 full (half full) +-- Examples: +-- - FSTATE_RD_BITS = 1: fstate_rd == 0 => 0/2 full +-- fstate_rd == 1 => 1/2 full (half full) -- --- - FSTATE_RD_BITS = 2: fstate_rd == 0 => 0/4 full --- fstate_rd == 1 => 1/4 full --- fstate_rd == 2 => 2/4 full --- fstate_rd == 3 => 3/4 full +-- - FSTATE_RD_BITS = 2: fstate_rd == 0 => 0/4 full +-- fstate_rd == 1 => 1/4 full +-- fstate_rd == 2 => 2/4 full +-- fstate_rd == 3 => 3/4 full -- -- License: --- ============================================================================================================================================================ --- Copyright 2007-2014 Technische Universitaet Dresden - Germany, Chair for VLSI-Design, Diagnostics and Architecture +-- ============================================================================= +-- Copyright 2007-2014 Technische Universitaet Dresden - Germany, +-- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. @@ -66,7 +65,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================================================================================================ +-- ============================================================================= library IEEE; use IEEE.std_logic_1164.all; @@ -74,7 +73,7 @@ use IEEE.numeric_std.all; library poc; use poc.config.all; -USE poc.utils.all; +use poc.utils.all; use poc.ocram.ocram_sdp; @@ -107,7 +106,7 @@ entity fifo_cc_got_tempput is valid : out std_logic; fstate_rd : out std_logic_vector(imax(0, FSTATE_RD_BITS-1) downto 0) ); -end fifo_cc_got_tempput; +end entity fifo_cc_got_tempput; architecture rtl of fifo_cc_got_tempput is @@ -129,7 +128,7 @@ architecture rtl of fifo_cc_got_tempput is signal IP1 : unsigned(A_BITS-1 downto 0); signal OP1 : unsigned(A_BITS-1 downto 0); - -- Commited Write Pointer (Commit Marker) + -- Committed Write Pointer (Commit Marker) signal IPm : unsigned(A_BITS-1 downto 0) := (others => '0'); ----------------------------------------------------------------------------- @@ -152,10 +151,10 @@ begin ----------------------------------------------------------------------------- -- Pointer Logic blkPointer : block - signal IP0_slv : STD_LOGIC_VECTOR(IP0'range); - signal IP1_slv : STD_LOGIC_VECTOR(IP0'range); - signal OP0_slv : STD_LOGIC_VECTOR(IP0'range); - signal OP1_slv : STD_LOGIC_VECTOR(IP0'range); + signal IP0_slv : std_logic_vector(IP0'range); + signal IP1_slv : std_logic_vector(IP0'range); + signal OP0_slv : std_logic_vector(IP0'range); + signal OP1_slv : std_logic_vector(IP0'range); begin IP0_slv <= std_logic_vector(IP0); OP0_slv <= std_logic_vector(OP0); @@ -398,7 +397,7 @@ begin begin if rising_edge(clk) then --synthesis translate_off - if SIMULATION AND (rst = '1') then + if SIMULATION and (rst = '1') then regfile <= (others => (others => '-')); else --synthesis translate_on @@ -419,4 +418,4 @@ begin end generate genSmall; -end rtl; +end architecture; diff --git a/src/fifo/fifo_glue.vhdl b/src/fifo/fifo_glue.vhdl index 4057bb4c..19cfe72a 100644 --- a/src/fifo/fifo_glue.vhdl +++ b/src/fifo/fifo_glue.vhdl @@ -1,21 +1,19 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- =========================================================================== --- Module: minimal FIFO, common clock (cc), --- pipelined interface, first-word-fall-through mode --- +-- ============================================================================= -- Authors: Thomas B. Preusser -- +-- Entity: Minimal FIFO, common clock (cc), pipelined interface, first-word-fall-through mode +-- -- Description: --- ------------------------------------ --- Its primary use is the decoupling of enable domains in a processing --- pipeline. Data storage is limited to two words only so as to allow both --- the 'ful' and the 'vld' indicators to be driven by registers. +-- ------------------------------------- +-- Its primary use is the decoupling of enable domains in a processing +-- pipeline. Data storage is limited to two words only so as to allow both +-- the ``ful`` and the ``vld`` indicators to be driven by registers. -- -- License: --- =========================================================================== +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -30,7 +28,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- =========================================================================== +-- ============================================================================= library IEEE; use IEEE.std_logic_1164.all; @@ -54,7 +52,7 @@ entity fifo_glue is do : out std_logic_vector(D_BITS-1 downto 0); -- Data Output got : in std_logic -- Data Consumed ); -end fifo_glue; +end entity fifo_glue; architecture rtl of fifo_glue is @@ -111,4 +109,4 @@ begin vld <= Avail; do <= B; -end rtl; +end architecture; diff --git a/src/fifo/fifo_ic_assembly.vhdl b/src/fifo/fifo_ic_assembly.vhdl index 9c9e8242..c81ff3ab 100644 --- a/src/fifo/fifo_ic_assembly.vhdl +++ b/src/fifo/fifo_ic_assembly.vhdl @@ -1,29 +1,28 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- =========================================================================== +-- ============================================================================= -- Authors: Thomas B. Preusser -- --- Module: address-based FIFO stream assembly, independent clocks (ic) +-- Entity: Address-based FIFO stream assembly, independent clocks (ic) -- -- Description: --- ------------ --- This module assembles a FIFO stream from data blocks that may arrive --- slightly out of order. The arriving data is ordered according to their --- address. The streamed output starts with the data word written to --- address zero (0) and may proceed all the way to just before the first yet --- missing data. The association of data with addresses is used on the input --- side for the sole purpose of reconstructing the correct order of the data. --- It is assumed to wrap so as to allow an infinite input sequence. Addresses --- are not actively exposed to the purely stream-based FIFO output. +-- ------------------------------------- +-- This module assembles a FIFO stream from data blocks that may arrive +-- slightly out of order. The arriving data is ordered according to their +-- address. The streamed output starts with the data word written to +-- address zero (0) and may proceed all the way to just before the first yet +-- missing data. The association of data with addresses is used on the input +-- side for the sole purpose of reconstructing the correct order of the data. +-- It is assumed to wrap so as to allow an infinite input sequence. Addresses +-- are not actively exposed to the purely stream-based FIFO output. -- --- The implemented functionality enables the reconstruction of streams that --- are tunnelled across address-based transports that are allowed to reorder --- the transmission of data blocks. This applies to many DMA implementations. +-- The implemented functionality enables the reconstruction of streams that +-- are tunnelled across address-based transports that are allowed to reorder +-- the transmission of data blocks. This applies to many DMA implementations. -- -- License: --- =========================================================================== +-- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -38,7 +37,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- =========================================================================== +-- ============================================================================= library IEEE; use IEEE.std_logic_1164.all; @@ -76,7 +75,7 @@ entity fifo_ic_assembly is vld : out std_logic; got : in std_logic ); -end fifo_ic_assembly; +end entity fifo_ic_assembly; library IEEE; diff --git a/src/fifo/fifo_ic_got.vhdl b/src/fifo/fifo_ic_got.vhdl index 7abf3c75..3e21ea18 100644 --- a/src/fifo/fifo_ic_got.vhdl +++ b/src/fifo/fifo_ic_got.vhdl @@ -1,55 +1,54 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- =========================================================================== --- Module: FIFO, independent clocks (ic), first-word-fall-through mode --- +-- ============================================================================= -- Authors: Thomas B. Preusser -- Steffen Koehler -- Martin Zabel -- +-- Entity: FIFO, independent clocks (ic), first-word-fall-through mode +-- -- Description: --- ------------------------------------ --- Independent clocks meens that read and write clock are unrelated. +-- ------------------------------------- +-- Independent clocks meens that read and write clock are unrelated. -- --- This implementation uses dedicated block RAM for storing data. +-- This implementation uses dedicated block RAM for storing data. -- --- First-word-fall-through (FWFT) mode is implemented, so data can be read out --- as soon as 'valid' goes high. After the data has been captured, then the --- signal 'got' must be asserted. +-- First-word-fall-through (FWFT) mode is implemented, so data can be read out +-- as soon as ``valid`` goes high. After the data has been captured, then the +-- signal ``got`` must be asserted. -- --- Synchronous reset is used. Both resets may overlap. +-- Synchronous reset is used. Both resets may overlap. -- --- DATA_REG (=true) is a hint, that distributed memory or registers should be --- used as data storage. The actual memory type depends on the device --- architecture. See implementation for details. +-- ``DATA_REG`` (=true) is a hint, that distributed memory or registers should be +-- used as data storage. The actual memory type depends on the device +-- architecture. See implementation for details. -- --- *STATE_*_BITS defines the granularity of the fill state indicator --- '*state_*'. 'fstate_rd' is associated with the read clock domain and outputs --- the guaranteed number of words available in the FIFO. 'estate_wr' is --- associated with the write clock domain and outputs the number of words that --- is guaranteed to be accepted by the FIFO without a capacity overflow. Note --- that both these indicators cannot replace the 'full' or 'valid' outputs as --- they may be implemented as giving pessimistic bounds that are minimally off --- the true fill state. +-- ``*STATE_*_BITS`` defines the granularity of the fill state indicator +-- ``*state_*``. ``fstate_rd`` is associated with the read clock domain and outputs +-- the guaranteed number of words available in the FIFO. ``estate_wr`` is +-- associated with the write clock domain and outputs the number of words that +-- is guaranteed to be accepted by the FIFO without a capacity overflow. Note +-- that both these indicators cannot replace the ``full`` or ``valid`` outputs as +-- they may be implemented as giving pessimistic bounds that are minimally off +-- the true fill state. -- --- If a fill state is not of interest, set *STATE_*_BITS = 0. +-- If a fill state is not of interest, set *STATE_*_BITS = 0. -- --- 'fstate_rd' and 'estate_wr' are combinatorial outputs and include an address --- comparator (subtractor) in their path. +-- ``fstate_rd`` and ``estate_wr`` are combinatorial outputs and include an address +-- comparator (subtractor) in their path. -- --- Examples: --- - FSTATE_RD_BITS = 1: fstate_rd == 0 => 0/2 full --- fstate_rd == 1 => 1/2 full (half full) +-- Examples: +-- - FSTATE_RD_BITS = 1: fstate_rd == 0 => 0/2 full +-- fstate_rd == 1 => 1/2 full (half full) -- --- - FSTATE_RD_BITS = 2: fstate_rd == 0 => 0/4 full --- fstate_rd == 1 => 1/4 full --- fstate_rd == 2 => 2/4 full --- fstate_rd == 3 => 3/4 full +-- - FSTATE_RD_BITS = 2: fstate_rd == 0 => 0/4 full +-- fstate_rd == 1 => 1/4 full +-- fstate_rd == 2 => 2/4 full +-- fstate_rd == 3 => 3/4 full -- -- License: --- =========================================================================== +-- ============================================================================= -- Copyright 2007-2014 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -64,14 +63,14 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================================================================================================ +-- ============================================================================= library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library poc; -USE PoC.utils.ALL; +use PoC.utils.all; use poc.ocram.all; -- "all" required by Quartus RTL simulation @@ -101,7 +100,7 @@ entity fifo_ic_got is dout : out std_logic_vector(D_BITS-1 downto 0); fstate_rd : out std_logic_vector(imax(FSTATE_RD_BITS-1, 0) downto 0) ); -end fifo_ic_got; +end entity fifo_ic_got; architecture rtl of fifo_ic_got is @@ -355,7 +354,7 @@ begin begin if rising_edge(clk_wr) then --synthesis translate_off - if SIMULATION AND (rst_wr = '1') then + if SIMULATION and (rst_wr = '1') then regfile <= (others => (others => '-')); else --synthesis translate_on diff --git a/src/fifo/fifo_shift.vhdl b/src/fifo/fifo_shift.vhdl index d1995a53..09bba2c2 100644 --- a/src/fifo/fifo_shift.vhdl +++ b/src/fifo/fifo_shift.vhdl @@ -1,26 +1,23 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; +-- ============================================================================= +-- Authors: Thomas B. Preusser -- --- ============================================================================ --- Entity: fifo_shift --- --- Module: FIFO, common clock, pipelined interface --- --- Authors: Thomas B. Preusser +-- Entity: FIFO, common clock, pipelined interface -- -- Description: --- ------------------------------------ --- This FIFO implementation is based on an internal shift register. This is --- especially useful for smaller FIFO sizes, which can be implemented in LUT --- storage on some devices (e.g. Xilinx' SRLs). Only a single read pointer is --- maintained, which determines the number of valid entries within the --- underlying shift register. --- The specified depth (MIN_DEPTH) is rounded up to the next suitable value. +-- ------------------------------------- +-- This FIFO implementation is based on an internal shift register. This is +-- especially useful for smaller FIFO sizes, which can be implemented in LUT +-- storage on some devices (e.g. Xilinx' SRLs). Only a single read pointer is +-- maintained, which determines the number of valid entries within the +-- underlying shift register. -- +-- The specified depth (``MIN_DEPTH``) is rounded up to the next suitable value. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2014 Technische Universitaet Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -35,7 +32,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.std_logic_1164.all; @@ -64,7 +61,7 @@ entity fifo_shift is dout : out std_logic_vector(D_BITS-1 downto 0); -- Output Data vld : out std_logic -- Data Valid ); -end fifo_shift; +end entity fifo_shift; library IEEE; use IEEE.numeric_std.all; diff --git a/src/io/ddrio/ddrio.pkg.vhdl b/src/io/ddrio/ddrio.pkg.vhdl index 5306756d..22b24cb9 100644 --- a/src/io/ddrio/ddrio.pkg.vhdl +++ b/src/io/ddrio/ddrio.pkg.vhdl @@ -1,8 +1,7 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Martin Zabel -- Patrick Lehmann -- @@ -10,11 +9,11 @@ -- functions associated to the PoC.io.ddrio namespace -- -- Description: --- ------------------------------------ +-- ------------------------------------- -- For detailed documentation see below. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -29,55 +28,55 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; -use IEEE.std_logic_1164.ALL; +use IEEE.std_logic_1164.all; package ddrio is component ddrio_in is generic ( - BITS : POSITIVE; - INIT_VALUE : BIT_VECTOR := x"FFFFFFFF" + BITS : positive; + INIT_VALUE : bit_vector := x"FFFFFFFF" ); port ( - Clock : in STD_LOGIC; - ClockEnable : in STD_LOGIC; - DataIn_high : out STD_LOGIC_VECTOR(BITS - 1 downto 0); - DataIn_low : out STD_LOGIC_VECTOR(BITS - 1 downto 0); - Pad : in STD_LOGIC_VECTOR(BITS - 1 downto 0)); + Clock : in std_logic; + ClockEnable : in std_logic; + DataIn_high : out std_logic_vector(BITS - 1 downto 0); + DataIn_low : out std_logic_vector(BITS - 1 downto 0); + Pad : in std_logic_vector(BITS - 1 downto 0)); end component; component ddrio_inout is generic ( - BITS : POSITIVE); + BITS : positive); port ( - ClockOut : in STD_LOGIC; - ClockOutEnable : in STD_LOGIC; - OutputEnable : in STD_LOGIC; - DataOut_high : in STD_LOGIC_VECTOR(BITS - 1 downto 0); - DataOut_low : in STD_LOGIC_VECTOR(BITS - 1 downto 0); - ClockIn : in STD_LOGIC; - ClockInEnable : in STD_LOGIC; - DataIn_high : out STD_LOGIC_VECTOR(BITS - 1 downto 0); - DataIn_low : out STD_LOGIC_VECTOR(BITS - 1 downto 0); - Pad : inout STD_LOGIC_VECTOR(BITS - 1 downto 0)); + ClockOut : in std_logic; + ClockOutEnable : in std_logic; + OutputEnable : in std_logic; + DataOut_high : in std_logic_vector(BITS - 1 downto 0); + DataOut_low : in std_logic_vector(BITS - 1 downto 0); + ClockIn : in std_logic; + ClockInEnable : in std_logic; + DataIn_high : out std_logic_vector(BITS - 1 downto 0); + DataIn_low : out std_logic_vector(BITS - 1 downto 0); + Pad : inout std_logic_vector(BITS - 1 downto 0)); end component; component ddrio_out is generic ( - NO_OUTPUT_ENABLE : BOOLEAN := false; - BITS : POSITIVE; - INIT_VALUE : BIT_VECTOR := x"FFFFFFFF" + NO_OUTPUT_ENABLE : boolean := false; + BITS : positive; + INIT_VALUE : bit_vector := x"FFFFFFFF" ); port ( - Clock : in STD_LOGIC; - ClockEnable : in STD_LOGIC; - OutputEnable : in STD_LOGIC; - DataOut_high : in STD_LOGIC_VECTOR(BITS - 1 downto 0); - DataOut_low : in STD_LOGIC_VECTOR(BITS - 1 downto 0); - Pad : out STD_LOGIC_VECTOR(BITS - 1 downto 0) + Clock : in std_logic; + ClockEnable : in std_logic; + OutputEnable : in std_logic; + DataOut_high : in std_logic_vector(BITS - 1 downto 0); + DataOut_low : in std_logic_vector(BITS - 1 downto 0); + Pad : out std_logic_vector(BITS - 1 downto 0) ); end component; @@ -85,91 +84,91 @@ package ddrio is component ddrio_in_altera is generic ( - BITS : POSITIVE; - INIT_VALUE : BIT_VECTOR := x"FFFFFFFF" + BITS : positive; + INIT_VALUE : bit_vector := x"FFFFFFFF" ); port ( - Clock : in STD_LOGIC; - ClockEnable : in STD_LOGIC; - DataIn_high : out STD_LOGIC_VECTOR(BITS - 1 downto 0); - DataIn_low : out STD_LOGIC_VECTOR(BITS - 1 downto 0); - Pad : in STD_LOGIC_VECTOR(BITS - 1 downto 0)); + Clock : in std_logic; + ClockEnable : in std_logic; + DataIn_high : out std_logic_vector(BITS - 1 downto 0); + DataIn_low : out std_logic_vector(BITS - 1 downto 0); + Pad : in std_logic_vector(BITS - 1 downto 0)); end component; component ddrio_in_xilinx is generic ( - BITS : POSITIVE; - INIT_VALUE : BIT_VECTOR := x"FFFFFFFF" + BITS : positive; + INIT_VALUE : bit_vector := x"FFFFFFFF" ); port ( - Clock : in STD_LOGIC; - ClockEnable : in STD_LOGIC; - DataIn_high : out STD_LOGIC_VECTOR(BITS - 1 downto 0); - DataIn_low : out STD_LOGIC_VECTOR(BITS - 1 downto 0); - Pad : in STD_LOGIC_VECTOR(BITS - 1 downto 0)); + Clock : in std_logic; + ClockEnable : in std_logic; + DataIn_high : out std_logic_vector(BITS - 1 downto 0); + DataIn_low : out std_logic_vector(BITS - 1 downto 0); + Pad : in std_logic_vector(BITS - 1 downto 0)); end component; component ddrio_inout_altera is generic ( - BITS : POSITIVE); + BITS : positive); port ( - ClockOut : in STD_LOGIC; - ClockOutEnable : in STD_LOGIC; - OutputEnable : in STD_LOGIC; - DataOut_high : in STD_LOGIC_VECTOR(BITS - 1 downto 0); - DataOut_low : in STD_LOGIC_VECTOR(BITS - 1 downto 0); - ClockIn : in STD_LOGIC; - ClockInEnable : in STD_LOGIC; - DataIn_high : out STD_LOGIC_VECTOR(BITS - 1 downto 0); - DataIn_low : out STD_LOGIC_VECTOR(BITS - 1 downto 0); - Pad : inout STD_LOGIC_VECTOR(BITS - 1 downto 0)); + ClockOut : in std_logic; + ClockOutEnable : in std_logic; + OutputEnable : in std_logic; + DataOut_high : in std_logic_vector(BITS - 1 downto 0); + DataOut_low : in std_logic_vector(BITS - 1 downto 0); + ClockIn : in std_logic; + ClockInEnable : in std_logic; + DataIn_high : out std_logic_vector(BITS - 1 downto 0); + DataIn_low : out std_logic_vector(BITS - 1 downto 0); + Pad : inout std_logic_vector(BITS - 1 downto 0)); end component; component ddrio_inout_xilinx is generic ( - BITS : POSITIVE); + BITS : positive); port ( - ClockOut : in STD_LOGIC; - ClockOutEnable : in STD_LOGIC; - OutputEnable : in STD_LOGIC; - DataOut_high : in STD_LOGIC_VECTOR(BITS - 1 downto 0); - DataOut_low : in STD_LOGIC_VECTOR(BITS - 1 downto 0); - ClockIn : in STD_LOGIC; - ClockInEnable : in STD_LOGIC; - DataIn_high : out STD_LOGIC_VECTOR(BITS - 1 downto 0); - DataIn_low : out STD_LOGIC_VECTOR(BITS - 1 downto 0); - Pad : inout STD_LOGIC_VECTOR(BITS - 1 downto 0)); + ClockOut : in std_logic; + ClockOutEnable : in std_logic; + OutputEnable : in std_logic; + DataOut_high : in std_logic_vector(BITS - 1 downto 0); + DataOut_low : in std_logic_vector(BITS - 1 downto 0); + ClockIn : in std_logic; + ClockInEnable : in std_logic; + DataIn_high : out std_logic_vector(BITS - 1 downto 0); + DataIn_low : out std_logic_vector(BITS - 1 downto 0); + Pad : inout std_logic_vector(BITS - 1 downto 0)); end component; component ddrio_out_altera is generic ( - NO_OUTPUT_ENABLE : BOOLEAN := false; - BITS : POSITIVE; - INIT_VALUE : BIT_VECTOR := x"FFFFFFFF" + NO_OUTPUT_ENABLE : boolean := false; + BITS : positive; + INIT_VALUE : bit_vector := x"FFFFFFFF" ); port ( - Clock : in STD_LOGIC; - ClockEnable : in STD_LOGIC; - OutputEnable : in STD_LOGIC; - DataOut_high : in STD_LOGIC_VECTOR(BITS - 1 downto 0); - DataOut_low : in STD_LOGIC_VECTOR(BITS - 1 downto 0); - Pad : out STD_LOGIC_VECTOR(BITS - 1 downto 0) + Clock : in std_logic; + ClockEnable : in std_logic; + OutputEnable : in std_logic; + DataOut_high : in std_logic_vector(BITS - 1 downto 0); + DataOut_low : in std_logic_vector(BITS - 1 downto 0); + Pad : out std_logic_vector(BITS - 1 downto 0) ); end component; component ddrio_out_xilinx is generic ( - NO_OUTPUT_ENABLE : BOOLEAN := false; - BITS : POSITIVE; - INIT_VALUE : BIT_VECTOR := x"FFFFFFFF" + NO_OUTPUT_ENABLE : boolean := false; + BITS : positive; + INIT_VALUE : bit_vector := x"FFFFFFFF" ); port ( - Clock : in STD_LOGIC; - ClockEnable : in STD_LOGIC; - OutputEnable : in STD_LOGIC; - DataOut_high : in STD_LOGIC_VECTOR(BITS - 1 downto 0); - DataOut_low : in STD_LOGIC_VECTOR(BITS - 1 downto 0); - Pad : out STD_LOGIC_VECTOR(BITS - 1 downto 0) + Clock : in std_logic; + ClockEnable : in std_logic; + OutputEnable : in std_logic; + DataOut_high : in std_logic_vector(BITS - 1 downto 0); + DataOut_low : in std_logic_vector(BITS - 1 downto 0); + Pad : out std_logic_vector(BITS - 1 downto 0) ); end component; diff --git a/src/io/ddrio/ddrio_in.vhdl b/src/io/ddrio/ddrio_in.vhdl index cf11d3d0..63bafdc0 100644 --- a/src/io/ddrio/ddrio_in.vhdl +++ b/src/io/ddrio/ddrio_in.vhdl @@ -1,38 +1,40 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Martin Zabel -- Patrick Lehmann -- --- Module: Chip-Specific DDR Input Registers +-- Entity: Chip-Specific DDR Input Registers -- -- Description: --- ------------------------------------ --- Instantiates chip-specific DDR input registers. +-- ------------------------------------- +-- Instantiates chip-specific :abbr:`DDR (Double Data Rate)` input registers. +-- +-- Both data ``DataIn_high/low`` are synchronously outputted to the on-chip logic +-- with the rising edge of ``Clock``. ``DataIn_high`` is the value at the ``Pad`` +-- sampled with the same rising edge. ``DataIn_low`` is the value sampled with +-- the falling edge directly before this rising edge. Thus sampling starts with +-- the falling edge of the clock as depicted in the following waveform. +-- +-- .. code-block:: none -- --- Both data "DataIn_high/low" are synchronously outputted to the on-chip logic --- with the rising edge of "Clock". "DataIn_high" is the value at the "Pad" --- sampled with the same rising edge. "DataIn_low" is the value sampled with --- the falling edge directly before this rising edge. Thus sampling starts with --- the falling edge of the clock as depicted in the following waveform. --- __ ____ ____ __ --- Clock |____| |____| |____| --- Pad < 0 >< 1 >< 2 >< 3 >< 4 >< 5 > --- DataIn_low ... >< 0 >< 2 >< --- DataIn_high ... >< 1 >< 3 >< +-- __ ____ ____ __ +-- Clock |____| |____| |____| +-- Pad < 0 >< 1 >< 2 >< 3 >< 4 >< 5 > +-- DataIn_low ... >< 0 >< 2 >< +-- DataIn_high ... >< 1 >< 3 >< -- --- < i > is the value of the i-th data bit on the line. +-- < i > is the value of the i-th data bit on the line. -- --- After power-up, the output ports "DataIn_high" and "DataIn_low" both equal --- INIT_VALUE. +-- After power-up, the output ports ``DataIn_high`` and ``DataIn_low`` both equal +-- INIT_VALUE. -- --- "Pad" must be connected to a PAD because FPGAs only have these registers in --- IOBs. +-- ``Pad`` must be connected to a PAD because FPGAs only have these registers in +-- IOBs. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -47,7 +49,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; @@ -61,15 +63,15 @@ use PoC.ddrio.all; entity ddrio_in is generic ( - BITS : POSITIVE; - INIT_VALUE : BIT_VECTOR := x"FFFFFFFF" + BITS : positive; + INIT_VALUE : bit_vector := x"FFFFFFFF" ); port ( - Clock : in STD_LOGIC; - ClockEnable : in STD_LOGIC; - DataIn_high : out STD_LOGIC_VECTOR(BITS - 1 downto 0); - DataIn_low : out STD_LOGIC_VECTOR(BITS - 1 downto 0); - Pad : in STD_LOGIC_VECTOR(BITS - 1 downto 0) + Clock : in std_logic; + ClockEnable : in std_logic; + DataIn_high : out std_logic_vector(BITS - 1 downto 0); + DataIn_low : out std_logic_vector(BITS - 1 downto 0); + Pad : in std_logic_vector(BITS - 1 downto 0) ); end entity; @@ -81,7 +83,7 @@ begin report "PoC.io.ddrio.in is not implemented for given DEVICE." severity FAILURE; - genXilinx : if (VENDOR = VENDOR_XILINX) generate + genXilinx : if VENDOR = VENDOR_XILINX generate i : ddrio_in_xilinx generic map ( BITS => BITS, @@ -96,7 +98,7 @@ begin ); end generate; - genAltera : if (VENDOR = VENDOR_ALTERA) generate + genAltera : if VENDOR = VENDOR_ALTERA generate i : ddrio_in_altera generic map ( BITS => BITS, @@ -111,10 +113,10 @@ begin ); end generate; - genGeneric : if ((SIMULATION = TRUE) and (VENDOR = VENDOR_GENERIC)) generate - signal Pad_d_fe : STD_LOGIC_VECTOR(BITS - 1 downto 0) := to_stdlogicvector(INIT_VALUE); - signal DataIn_high_d : STD_LOGIC_VECTOR(BITS - 1 downto 0) := to_stdlogicvector(INIT_VALUE); - signal DataIn_low_d : STD_LOGIC_VECTOR(BITS - 1 downto 0) := to_stdlogicvector(INIT_VALUE); + genGeneric : if SIMULATION and (VENDOR = VENDOR_GENERIC) generate + signal Pad_d_fe : std_logic_vector(BITS - 1 downto 0) := to_stdlogicvector(INIT_VALUE); + signal DataIn_high_d : std_logic_vector(BITS - 1 downto 0) := to_stdlogicvector(INIT_VALUE); + signal DataIn_low_d : std_logic_vector(BITS - 1 downto 0) := to_stdlogicvector(INIT_VALUE); begin Pad_d_fe <= Pad when falling_edge(Clock) and (ClockEnable = '1'); DataIn_high_d <= Pad when rising_edge(Clock) and (ClockEnable = '1'); diff --git a/src/io/ddrio/ddrio_in_altera.vhdl b/src/io/ddrio/ddrio_in_altera.vhdl index 1973580c..74a29328 100644 --- a/src/io/ddrio/ddrio_in_altera.vhdl +++ b/src/io/ddrio/ddrio_in_altera.vhdl @@ -1,19 +1,18 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Martin Zabel -- Patrick Lehmann -- --- Module: Instantiates Chip-Specific DDR Input Registers for Altera FPGAs. +-- Entity: Instantiates Chip-Specific DDR Input Registers for Altera FPGAs. -- -- Description: --- ------------------------------------ +-- ------------------------------------- -- See PoC.io.ddrio.in for interface description. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -28,10 +27,10 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; -use IEEE.std_logic_1164.ALL; +use IEEE.std_logic_1164.all; library Altera_mf; use Altera_mf.Altera_MF_Components.all; @@ -41,15 +40,15 @@ use poc.utils.all; entity ddrio_in_altera is generic ( - BITS : POSITIVE; - INIT_VALUE : BIT_VECTOR := x"FFFFFFFF" + BITS : positive; + INIT_VALUE : bit_vector := x"FFFFFFFF" ); port ( - Clock : in STD_LOGIC; - ClockEnable : in STD_LOGIC; - DataIn_high : out STD_LOGIC_VECTOR(BITS - 1 downto 0); - DataIn_low : out STD_LOGIC_VECTOR(BITS - 1 downto 0); - Pad : in STD_LOGIC_VECTOR(BITS - 1 downto 0) + Clock : in std_logic; + ClockEnable : in std_logic; + DataIn_high : out std_logic_vector(BITS - 1 downto 0); + DataIn_low : out std_logic_vector(BITS - 1 downto 0); + Pad : in std_logic_vector(BITS - 1 downto 0) ); end entity; diff --git a/src/io/ddrio/ddrio_in_xilinx.vhdl b/src/io/ddrio/ddrio_in_xilinx.vhdl index 1e3e3a16..f3292e11 100644 --- a/src/io/ddrio/ddrio_in_xilinx.vhdl +++ b/src/io/ddrio/ddrio_in_xilinx.vhdl @@ -1,19 +1,18 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Martin Zabel -- Patrick Lehmann -- --- Module: Instantiates Chip-Specific DDR Input Registers for Xilinx FPGAs. +-- Entity: Instantiates Chip-Specific DDR Input Registers for Xilinx FPGAs. -- -- Description: --- ------------------------------------ +-- ------------------------------------- -- See PoC.io.ddrio.in for interface description. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -28,10 +27,10 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; -use IEEE.std_logic_1164.ALL; +use IEEE.std_logic_1164.all; library UniSim; use UniSim.vComponents.all; @@ -39,15 +38,15 @@ use UniSim.vComponents.all; entity ddrio_in_xilinx is generic ( - BITS : POSITIVE; - INIT_VALUE : BIT_VECTOR := x"FFFFFFFF" + BITS : positive; + INIT_VALUE : bit_vector := x"FFFFFFFF" ); port ( - Clock : in STD_LOGIC; - ClockEnable : in STD_LOGIC; - DataIn_high : out STD_LOGIC_VECTOR(BITS - 1 downto 0); - DataIn_low : out STD_LOGIC_VECTOR(BITS - 1 downto 0); - Pad : in STD_LOGIC_VECTOR(BITS - 1 downto 0) + Clock : in std_logic; + ClockEnable : in std_logic; + DataIn_high : out std_logic_vector(BITS - 1 downto 0); + DataIn_low : out std_logic_vector(BITS - 1 downto 0); + Pad : in std_logic_vector(BITS - 1 downto 0) ); end entity; diff --git a/src/io/ddrio/ddrio_inout.vhdl b/src/io/ddrio/ddrio_inout.vhdl index 6167ff2c..b8a11b2f 100644 --- a/src/io/ddrio/ddrio_inout.vhdl +++ b/src/io/ddrio/ddrio_inout.vhdl @@ -1,43 +1,46 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Martin Zabel -- Patrick Lehmann -- --- Module: Chip-Specific DDR Input and Output Registers +-- Entity: Chip-Specific DDR Input and Output Registers -- -- Description: --- ------------------------------------ --- Instantiates chip-specific DDR input and output registers. +-- ------------------------------------- +-- Instantiates chip-specific :abbr:`DDR (Double Data Rate)` input and output +-- registers. +-- +-- Both data ``DataOut_high/low`` as well as ``OutputEnable`` are sampled with +-- the ``rising_edge(Clock)`` from the on-chip logic. ``DataOut_high`` is brought +-- out with this rising edge. ``DataOut_low`` is brought out with the falling +-- edge. +-- +-- ``OutputEnable`` (Tri-State) is high-active. It is automatically inverted if +-- necessary. Output is disabled after power-up. -- --- Both data "DataOut_high/low" as well as "OutputEnable" are sampled with --- the rising_edge(Clock) from the on-chip logic. "DataOut_high" is brought --- out with this rising edge. "DataOut_low" is brought out with the falling --- edge. +-- Both data ``DataIn_high/low`` are synchronously outputted to the on-chip logic +-- with the rising edge of ``Clock``. ``DataIn_high`` is the value at the ``Pad`` +-- sampled with the same rising edge. ``DataIn_low`` is the value sampled with +-- the falling edge directly before this rising edge. Thus sampling starts with +-- the falling edge of the clock as depicted in the following waveform. -- --- "OutputEnable" (Tri-State) is high-active. It is automatically inverted if --- necessary. Output is disabled after power-up. +-- .. code-block:: none -- --- Both data "DataIn_high/low" are synchronously outputted to the on-chip logic --- with the rising edge of "Clock". "DataIn_high" is the value at the "Pad" --- sampled with the same rising edge. "DataIn_low" is the value sampled with --- the falling edge directly before this rising edge. Thus sampling starts with --- the falling edge of the clock as depicted in the following waveform. --- __ ____ ____ __ --- Clock |____| |____| |____| --- Pad < 0 >< 1 >< 2 >< 3 >< 4 >< 5 > --- DataIn_low ... >< 0 >< 2 >< --- DataIn_high ... >< 1 >< 3 >< +-- __ ____ ____ __ +-- Clock |____| |____| |____| +-- Pad < 0 >< 1 >< 2 >< 3 >< 4 >< 5 > +-- DataIn_low ... >< 0 >< 2 >< +-- DataIn_high ... >< 1 >< 3 >< -- --- < i > is the value of the i-th data bit on the line. +-- < i > is the value of the i-th data bit on the line. -- --- "Pad" must be connected to a PAD because FPGAs only have these registers in --- IOBs. +-- ``Pad`` must be connected to a PAD because FPGAs only have these registers in +-- IOBs. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -52,7 +55,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; @@ -66,21 +69,21 @@ use PoC.ddrio.all; entity ddrio_inout is generic ( - BITS : POSITIVE + BITS : positive ); port ( - ClockOut : in STD_LOGIC; - ClockOutEnable : in STD_LOGIC; - OutputEnable : in STD_LOGIC; - DataOut_high : in STD_LOGIC_VECTOR(BITS - 1 downto 0); - DataOut_low : in STD_LOGIC_VECTOR(BITS - 1 downto 0); - - ClockIn : in STD_LOGIC; - ClockInEnable : in STD_LOGIC; - DataIn_high : out STD_LOGIC_VECTOR(BITS - 1 downto 0); - DataIn_low : out STD_LOGIC_VECTOR(BITS - 1 downto 0); - - Pad : inout STD_LOGIC_VECTOR(BITS - 1 downto 0) + ClockOut : in std_logic; + ClockOutEnable : in std_logic; + OutputEnable : in std_logic; + DataOut_high : in std_logic_vector(BITS - 1 downto 0); + DataOut_low : in std_logic_vector(BITS - 1 downto 0); + + ClockIn : in std_logic; + ClockInEnable : in std_logic; + DataIn_high : out std_logic_vector(BITS - 1 downto 0); + DataIn_low : out std_logic_vector(BITS - 1 downto 0); + + Pad : inout std_logic_vector(BITS - 1 downto 0) ); end entity; @@ -92,7 +95,7 @@ begin report "PoC.io.ddrio.inout is not implemented for given DEVICE." severity FAILURE; - genXilinx : if (VENDOR = VENDOR_XILINX) generate + genXilinx : if VENDOR = VENDOR_XILINX generate inst : ddrio_inout_xilinx generic map ( BITS => BITS @@ -111,7 +114,7 @@ begin ); end generate; - genAltera : if (VENDOR = VENDOR_ALTERA) generate + genAltera : if VENDOR = VENDOR_ALTERA generate inst : ddrio_inout_altera generic map ( BITS => BITS @@ -130,22 +133,22 @@ begin ); end generate; - genGeneric : if ((SIMULATION = TRUE) and (VENDOR = VENDOR_GENERIC)) generate - signal DataOut_high_d : STD_LOGIC_VECTOR(BITS - 1 downto 0); - signal DataOut_low_d : STD_LOGIC_VECTOR(BITS - 1 downto 0); - signal OutputEnable_d : STD_LOGIC; - signal Pad_o : STD_LOGIC_VECTOR(BITS - 1 downto 0); + genGeneric : if SIMULATION and (VENDOR = VENDOR_GENERIC) generate + signal DataOut_high_d : std_logic_vector(BITS - 1 downto 0); + signal DataOut_low_d : std_logic_vector(BITS - 1 downto 0); + signal OutputEnable_d : std_logic; + signal Pad_o : std_logic_vector(BITS - 1 downto 0); - signal Pad_d_fe : STD_LOGIC_VECTOR(BITS - 1 downto 0); - signal DataIn_high_d : STD_LOGIC_VECTOR(BITS - 1 downto 0); - signal DataIn_low_d : STD_LOGIC_VECTOR(BITS - 1 downto 0); + signal Pad_d_fe : std_logic_vector(BITS - 1 downto 0); + signal DataIn_high_d : std_logic_vector(BITS - 1 downto 0); + signal DataIn_low_d : std_logic_vector(BITS - 1 downto 0); begin DataOut_high_d <= DataOut_high when rising_edge(ClockOut) and (ClockOutEnable = '1'); DataOut_low_d <= DataOut_low when rising_edge(ClockOut) and (ClockOutEnable = '1'); OutputEnable_d <= OutputEnable when rising_edge(ClockOut) and (ClockOutEnable = '1'); - process(ClockOut, OutputEnable, DataOut_high_d, DataOut_low_d) - type T_MUX is array(BIT) of STD_LOGIC_VECTOR(BITS - 1 downto 0); + process(ClockOut, OutputEnable_d, DataOut_high_d, DataOut_low_d) + type T_MUX is array(bit) of std_logic_vector(BITS - 1 downto 0); variable MuxInput : T_MUX; begin MuxInput('1') := DataOut_high_d; diff --git a/src/io/ddrio/ddrio_inout_altera.vhdl b/src/io/ddrio/ddrio_inout_altera.vhdl index cbf6e154..94c8300d 100644 --- a/src/io/ddrio/ddrio_inout_altera.vhdl +++ b/src/io/ddrio/ddrio_inout_altera.vhdl @@ -1,19 +1,18 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Martin Zabel -- Patrick Lehmann -- --- Module: Instantiates Chip-Specific DDR Input/Output Registers for Xilinx FPGAs. +-- Entity: Instantiates Chip-Specific DDR Input/Output Registers for Xilinx FPGAs. -- -- Description: --- ------------------------------------ +-- ------------------------------------- -- See PoC.io.ddrio.inout for interface description. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -28,11 +27,11 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; -use IEEE.std_logic_1164.ALL; +use IEEE.std_logic_1164.all; library Altera_mf; use Altera_mf.Altera_MF_Components.all; @@ -40,21 +39,21 @@ use Altera_mf.Altera_MF_Components.all; entity ddrio_inout_altera is generic ( - BITS : POSITIVE + BITS : positive ); port ( - ClockOut : in STD_LOGIC; - ClockOutEnable : in STD_LOGIC; - OutputEnable : in STD_LOGIC; - DataOut_high : in STD_LOGIC_VECTOR(BITS - 1 downto 0); - DataOut_low : in STD_LOGIC_VECTOR(BITS - 1 downto 0); + ClockOut : in std_logic; + ClockOutEnable : in std_logic; + OutputEnable : in std_logic; + DataOut_high : in std_logic_vector(BITS - 1 downto 0); + DataOut_low : in std_logic_vector(BITS - 1 downto 0); - ClockIn : in STD_LOGIC; - ClockInEnable : in STD_LOGIC; - DataIn_high : out STD_LOGIC_VECTOR(BITS - 1 downto 0); - DataIn_low : out STD_LOGIC_VECTOR(BITS - 1 downto 0); + ClockIn : in std_logic; + ClockInEnable : in std_logic; + DataIn_high : out std_logic_vector(BITS - 1 downto 0); + DataIn_low : out std_logic_vector(BITS - 1 downto 0); - Pad : inout STD_LOGIC_VECTOR(BITS - 1 downto 0) + Pad : inout std_logic_vector(BITS - 1 downto 0) ); end entity; diff --git a/src/io/ddrio/ddrio_inout_xilinx.vhdl b/src/io/ddrio/ddrio_inout_xilinx.vhdl index b05735c6..37052639 100644 --- a/src/io/ddrio/ddrio_inout_xilinx.vhdl +++ b/src/io/ddrio/ddrio_inout_xilinx.vhdl @@ -1,19 +1,18 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Martin Zabel -- Patrick Lehmann -- --- Module: Instantiates Chip-Specific DDR Input/Output Registers for Xilinx FPGAs. +-- Entity: Instantiates Chip-Specific DDR Input/Output Registers for Xilinx FPGAs. -- -- Description: --- ------------------------------------ +-- ------------------------------------- -- See PoC.io.ddrio.inout for interface description. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -28,11 +27,11 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; -use IEEE.std_logic_1164.ALL; +use IEEE.std_logic_1164.all; library UniSim; use UniSim.vComponents.all; @@ -40,21 +39,21 @@ use UniSim.vComponents.all; entity ddrio_inout_xilinx is generic ( - BITS : POSITIVE + BITS : positive ); port ( - ClockOut : in STD_LOGIC; - ClockOutEnable : in STD_LOGIC; - OutputEnable : in STD_LOGIC; - DataOut_high : in STD_LOGIC_VECTOR(BITS - 1 downto 0); - DataOut_low : in STD_LOGIC_VECTOR(BITS - 1 downto 0); + ClockOut : in std_logic; + ClockOutEnable : in std_logic; + OutputEnable : in std_logic; + DataOut_high : in std_logic_vector(BITS - 1 downto 0); + DataOut_low : in std_logic_vector(BITS - 1 downto 0); - ClockIn : in STD_LOGIC; - ClockInEnable : in STD_LOGIC; - DataIn_high : out STD_LOGIC_VECTOR(BITS - 1 downto 0); - DataIn_low : out STD_LOGIC_VECTOR(BITS - 1 downto 0); + ClockIn : in std_logic; + ClockInEnable : in std_logic; + DataIn_high : out std_logic_vector(BITS - 1 downto 0); + DataIn_low : out std_logic_vector(BITS - 1 downto 0); - Pad : inout STD_LOGIC_VECTOR(BITS - 1 downto 0) + Pad : inout std_logic_vector(BITS - 1 downto 0) ); end entity; diff --git a/src/io/ddrio/ddrio_out.vhdl b/src/io/ddrio/ddrio_out.vhdl index ac4eeac4..2131087c 100644 --- a/src/io/ddrio/ddrio_out.vhdl +++ b/src/io/ddrio/ddrio_out.vhdl @@ -1,34 +1,33 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Martin Zabel -- Patrick Lehmann -- --- Module: Chip-Specific DDR Output Registers +-- Entity: Chip-Specific DDR Output Registers -- -- Description: --- ------------------------------------ --- Instantiates chip-specific DDR output registers. +-- ------------------------------------- +-- Instantiates chip-specific :abbr:`DDR (Double Data Rate)` output registers. -- --- Both data "DataOut_high/low" as well as "OutputEnable" are sampled with --- the rising_edge(Clock) from the on-chip logic. "DataOut_high" is brought --- out with this rising edge. "DataOut_low" is brought out with the falling --- edge. +-- Both data ``DataOut_high/low`` as well as ``OutputEnable`` are sampled with +-- the ``rising_edge(Clock)`` from the on-chip logic. ``DataOut_high`` is brought +-- out with this rising edge. ``DataOut_low`` is brought out with the falling +-- edge. -- --- "OutputEnable" (Tri-State) is high-active. It is automatically inverted if --- necessary. If an output enable is not required, you may save some logic by --- setting NO_OUTPUT_ENABLE = true. +-- ``OutputEnable`` (Tri-State) is high-active. It is automatically inverted if +-- necessary. If an output enable is not required, you may save some logic by +-- setting ``NO_OUTPUT_ENABLE = true``. -- --- If NO_OUTPUT_ENABLE = false then output is disabled after power-up. --- If NO_OUTPUT_ENABLE = true then output after power-up equals INIT_VALUE. +-- If ``NO_OUTPUT_ENABLE = false`` then output is disabled after power-up. +-- If ``NO_OUTPUT_ENABLE = true`` then output after power-up equals ``INIT_VALUE``. -- --- "Pad" must be connected to a PAD because FPGAs only have these registers in --- IOBs. +-- ``Pad`` must be connected to a PAD because FPGAs only have these registers in +-- IOBs. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -43,7 +42,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; @@ -57,17 +56,17 @@ use PoC.ddrio.all; entity ddrio_out is generic ( - NO_OUTPUT_ENABLE : BOOLEAN := false; - BITS : POSITIVE; - INIT_VALUE : BIT_VECTOR := x"FFFFFFFF" + NO_OUTPUT_ENABLE : boolean := false; + BITS : positive; + INIT_VALUE : bit_vector := x"FFFFFFFF" ); port ( - Clock : in STD_LOGIC; - ClockEnable : in STD_LOGIC := '1'; - OutputEnable : in STD_LOGIC := '1'; - DataOut_high : in STD_LOGIC_VECTOR(BITS - 1 downto 0); - DataOut_low : in STD_LOGIC_VECTOR(BITS - 1 downto 0); - Pad : out STD_LOGIC_VECTOR(BITS - 1 downto 0) + Clock : in std_logic; + ClockEnable : in std_logic := '1'; + OutputEnable : in std_logic := '1'; + DataOut_high : in std_logic_vector(BITS - 1 downto 0); + DataOut_low : in std_logic_vector(BITS - 1 downto 0); + Pad : out std_logic_vector(BITS - 1 downto 0) ); end entity; @@ -79,7 +78,7 @@ begin report "PoC.io.ddrio.out is not implemented for given DEVICE." severity FAILURE; - genXilinx : if (VENDOR = VENDOR_XILINX) generate + genXilinx : if VENDOR = VENDOR_XILINX generate i : ddrio_out_xilinx generic map ( NO_OUTPUT_ENABLE => NO_OUTPUT_ENABLE, @@ -96,7 +95,7 @@ begin ); end generate; - genAltera : if (VENDOR = VENDOR_ALTERA) generate + genAltera : if VENDOR = VENDOR_ALTERA generate i : ddrio_out_altera generic map ( NO_OUTPUT_ENABLE => NO_OUTPUT_ENABLE, @@ -113,18 +112,18 @@ begin ); end generate; - genGeneric : if ((SIMULATION = TRUE) and (VENDOR = VENDOR_GENERIC)) generate - signal DataOut_high_d : STD_LOGIC_VECTOR(BITS - 1 downto 0) := to_stdlogicvector(INIT_VALUE); - signal DataOut_low_d : STD_LOGIC_VECTOR(BITS - 1 downto 0) := to_stdlogicvector(INIT_VALUE); - signal OutputEnable_d : STD_LOGIC; - signal Pad_o : STD_LOGIC_VECTOR(BITS - 1 downto 0) := to_stdlogicvector(INIT_VALUE); + genGeneric : if SIMULATION and (VENDOR = VENDOR_GENERIC) generate + signal DataOut_high_d : std_logic_vector(BITS - 1 downto 0) := to_stdlogicvector(INIT_VALUE); + signal DataOut_low_d : std_logic_vector(BITS - 1 downto 0) := to_stdlogicvector(INIT_VALUE); + signal OutputEnable_d : std_logic; + signal Pad_o : std_logic_vector(BITS - 1 downto 0) := to_stdlogicvector(INIT_VALUE); begin DataOut_high_d <= DataOut_high when rising_edge(Clock) and (ClockEnable = '1'); DataOut_low_d <= DataOut_low when rising_edge(Clock) and (ClockEnable = '1'); OutputEnable_d <= OutputEnable when rising_edge(Clock) and (ClockEnable = '1'); - process(Clock, OutputEnable, DataOut_high_d, DataOut_low_d) - type T_MUX is array(BIT) of STD_LOGIC_VECTOR(BITS - 1 downto 0); + process(Clock, OutputEnable_d, DataOut_high_d, DataOut_low_d) + type T_MUX is array(bit) of std_logic_vector(BITS - 1 downto 0); variable MuxInput : T_MUX; begin MuxInput('1') := DataOut_high_d; diff --git a/src/io/ddrio/ddrio_out_altera.vhdl b/src/io/ddrio/ddrio_out_altera.vhdl index d1ed508d..814fb955 100644 --- a/src/io/ddrio/ddrio_out_altera.vhdl +++ b/src/io/ddrio/ddrio_out_altera.vhdl @@ -1,19 +1,18 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Martin Zabel -- Patrick Lehmann -- --- Module: Instantiates Chip-Specific DDR Output Registers for Altera FPGAs. +-- Entity: Instantiates Chip-Specific DDR Output Registers for Altera FPGAs. -- -- Description: --- ------------------------------------ +-- ------------------------------------- -- See PoC.io.ddrio.out for interface description. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -28,10 +27,10 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; -use IEEE.std_logic_1164.ALL; +use IEEE.std_logic_1164.all; library Altera_mf; use Altera_mf.Altera_MF_Components.all; @@ -41,17 +40,17 @@ use poc.utils.all; entity ddrio_out_altera is generic ( - NO_OUTPUT_ENABLE : BOOLEAN := false; - BITS : POSITIVE; - INIT_VALUE : BIT_VECTOR := x"FFFFFFFF" + NO_OUTPUT_ENABLE : boolean := false; + BITS : positive; + INIT_VALUE : bit_vector := x"FFFFFFFF" ); port ( - Clock : in STD_LOGIC; - ClockEnable : in STD_LOGIC; - OutputEnable : in STD_LOGIC; - DataOut_high : in STD_LOGIC_VECTOR(BITS - 1 downto 0); - DataOut_low : in STD_LOGIC_VECTOR(BITS - 1 downto 0); - Pad : out STD_LOGIC_VECTOR(BITS - 1 downto 0) + Clock : in std_logic; + ClockEnable : in std_logic; + OutputEnable : in std_logic; + DataOut_high : in std_logic_vector(BITS - 1 downto 0); + DataOut_low : in std_logic_vector(BITS - 1 downto 0); + Pad : out std_logic_vector(BITS - 1 downto 0) ); end entity; diff --git a/src/io/ddrio/ddrio_out_xilinx.vhdl b/src/io/ddrio/ddrio_out_xilinx.vhdl index e8e8525d..3b0b5c69 100644 --- a/src/io/ddrio/ddrio_out_xilinx.vhdl +++ b/src/io/ddrio/ddrio_out_xilinx.vhdl @@ -1,19 +1,18 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Martin Zabel -- Patrick Lehmann -- --- Module: Instantiates Chip-Specific DDR Output Registers for Xilinx FPGAs. +-- Entity: Instantiates Chip-Specific DDR Output Registers for Xilinx FPGAs. -- -- Description: --- ------------------------------------ +-- ------------------------------------- -- See PoC.io.ddrio.out for interface description. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -28,11 +27,11 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; -use IEEE.std_logic_1164.ALL; +use IEEE.std_logic_1164.all; library UniSim; use UniSim.vComponents.all; @@ -40,17 +39,17 @@ use UniSim.vComponents.all; entity ddrio_out_xilinx is generic ( - NO_OUTPUT_ENABLE : BOOLEAN := false; - BITS : POSITIVE; - INIT_VALUE : BIT_VECTOR := x"FFFFFFFF" + NO_OUTPUT_ENABLE : boolean := false; + BITS : positive; + INIT_VALUE : bit_vector := x"FFFFFFFF" ); port ( - Clock : in STD_LOGIC; - ClockEnable : in STD_LOGIC; - OutputEnable : in STD_LOGIC; - DataOut_high : in STD_LOGIC_VECTOR(BITS - 1 downto 0); - DataOut_low : in STD_LOGIC_VECTOR(BITS - 1 downto 0); - Pad : out STD_LOGIC_VECTOR(BITS - 1 downto 0) + Clock : in std_logic; + ClockEnable : in std_logic; + OutputEnable : in std_logic; + DataOut_high : in std_logic_vector(BITS - 1 downto 0); + DataOut_low : in std_logic_vector(BITS - 1 downto 0); + Pad : out std_logic_vector(BITS - 1 downto 0) ); end entity; diff --git a/src/io/io.pkg.vhdl b/src/io/io.pkg.vhdl index 702e5651..457646af 100644 --- a/src/io/io.pkg.vhdl +++ b/src/io/io.pkg.vhdl @@ -1,19 +1,18 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- -- Package: VHDL package for component declarations, types and -- functions associated to the PoC.io namespace -- -- Description: --- ------------------------------------ +-- ------------------------------------- -- For detailed documentation see below. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -28,7 +27,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -43,18 +42,18 @@ package io is -- not yet supported by Xilinx ISE Simulator - the subsignal I (with reverse direction) is always 'U' -- so use this record only in pure synthesis environments type T_IO_TRISTATE is record - I : STD_LOGIC; -- input / from device to FPGA - O : STD_LOGIC; -- output / from FPGA to device - T : STD_LOGIC; -- output disable / tristate enable + I : std_logic; -- input / from device to FPGA + O : std_logic; -- output / from FPGA to device + T : std_logic; -- output disable / tristate enable end record; type T_IO_LVDS is record - P : STD_LOGIC; - N : STD_LOGIC; + P : std_logic; + N : std_logic; end record; - type T_IO_TRISTATE_VECTOR is array(NATURAL range <>) of T_IO_TRISTATE; - type T_IO_LVDS_VECTOR is array(NATURAL range <>) of T_IO_LVDS; + type T_IO_TRISTATE_VECTOR is array(natural range <>) of T_IO_TRISTATE; + type T_IO_LVDS_VECTOR is array(natural range <>) of T_IO_LVDS; type T_IO_DATARATE is (IO_DATARATE_SDR, IO_DATARATE_DDR, IO_DATARATE_QDR); @@ -66,7 +65,7 @@ package io is IO_7SEGMENT_CHAR_H, IO_7SEGMENT_CHAR_O, IO_7SEGMENT_CHAR_U, IO_7SEGMENT_CHAR_MINUS ); - type T_IO_7SEGMENT_CHAR_ENCODING is array(T_IO_7SEGMENT_CHAR) of STD_LOGIC_VECTOR(6 downto 0); + type T_IO_7SEGMENT_CHAR_ENCODING is array(T_IO_7SEGMENT_CHAR) of std_logic_vector(6 downto 0); --constant C_IO_7SEGMENT_CHAR_ENCODING : T_IO_7SEGMENT_CHAR_ENCODING := ( --IO_7SEGMENT_CHAR_0 @@ -91,8 +90,8 @@ package io is --IO_7SEGMENT_CHAR_MINUS --); - function io_7SegmentDisplayEncoding(hex : STD_LOGIC_VECTOR(3 downto 0); dot : STD_LOGIC := '0'; WITH_DOT : BOOLEAN := FALSE) return STD_LOGIC_VECTOR; - function io_7SegmentDisplayEncoding(digit : T_BCD; dot : STD_LOGIC := '0'; WITH_DOT : BOOLEAN := FALSE) return STD_LOGIC_VECTOR; + function io_7SegmentDisplayEncoding(hex : std_logic_vector(3 downto 0); dot : std_logic := '0'; WITH_DOT : boolean := FALSE) return std_logic_vector; + function io_7SegmentDisplayEncoding(digit : T_BCD; dot : std_logic := '0'; WITH_DOT : boolean := FALSE) return std_logic_vector; -- MDIOController @@ -146,13 +145,13 @@ package io is CLOCK_FREQ_MHZ : real ); port ( - Clock : in STD_LOGIC; - Reset : in STD_LOGIC; + Clock : in std_logic; + Reset : in std_logic; - Fan_PWM : out STD_LOGIC; - Fan_Tacho : in STD_LOGIC; + Fan_PWM : out std_logic; + Fan_Tacho : in std_logic; - TachoFrequency : out STD_LOGIC_VECTOR(15 downto 0) + TachoFrequency : out std_logic_vector(15 downto 0) ); end component; @@ -160,9 +159,9 @@ end package; package body io is - function io_7SegmentDisplayEncoding(hex : STD_LOGIC_VECTOR(3 downto 0); dot : STD_LOGIC := '0'; WITH_DOT : BOOLEAN := FALSE) return STD_LOGIC_VECTOR is - constant DOT_INDEX : POSITIVE := ite(WITH_DOT, 7, 6); - variable Result : STD_LOGIC_VECTOR(ite(WITH_DOT, 7, 6) downto 0); + function io_7SegmentDisplayEncoding(hex : std_logic_vector(3 downto 0); dot : std_logic := '0'; WITH_DOT : boolean := FALSE) return std_logic_vector is + constant DOT_INDEX : positive := ite(WITH_DOT, 7, 6); + variable Result : std_logic_vector(ite(WITH_DOT, 7, 6) downto 0); begin Result(DOT_INDEX) := dot; case hex is -- segments: GFEDCBA -- Segment Pos. @@ -187,7 +186,7 @@ package body io is return Result; end function; - function io_7SegmentDisplayEncoding(digit : T_BCD; dot : STD_LOGIC := '0'; WITH_DOT : BOOLEAN := FALSE) return STD_LOGIC_VECTOR is + function io_7SegmentDisplayEncoding(digit : T_BCD; dot : std_logic := '0'; WITH_DOT : boolean := FALSE) return std_logic_vector is begin return io_7SegmentDisplayEncoding(std_logic_vector(digit), dot, WITH_DOT); end function; diff --git a/src/io/io_7SegmentMux_BCD.vhdl b/src/io/io_7SegmentMux_BCD.vhdl index e608d40f..828fcb9a 100644 --- a/src/io/io_7SegmentMux_BCD.vhdl +++ b/src/io/io_7SegmentMux_BCD.vhdl @@ -1,21 +1,20 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: time multiplexed 7 Segment Display Controller for BCD chars +-- Entity: time multiplexed 7 Segment Display Controller for BCD chars -- -- Description: --- ------------------------------------ --- This module is a 7 segment display controller that uses time multiplexing --- to control a common anode for each digit in the display. The shown characters --- are BCD encoded. A dot per digit is optional. A minus sign for negative --- numbers is supported. +-- ------------------------------------- +-- This module is a 7 segment display controller that uses time multiplexing +-- to control a common anode for each digit in the display. The shown characters +-- are BCD encoded. A dot per digit is optional. A minus sign for negative +-- numbers is supported. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -30,7 +29,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -47,24 +46,24 @@ entity io_7SegmentMux_BCD is generic ( CLOCK_FREQ : FREQ := 100 MHz; REFRESH_RATE : FREQ := 1 kHz; - DIGITS : POSITIVE := 4 + DIGITS : positive := 4 ); port ( - Clock : in STD_LOGIC; + Clock : in std_logic; BCDDigits : in T_BCD_VECTOR(DIGITS - 1 downto 0); - BCDDots : in STD_LOGIC_VECTOR(DIGITS - 1 downto 0); + BCDDots : in std_logic_vector(DIGITS - 1 downto 0); - SegmentControl : out STD_LOGIC_VECTOR(7 downto 0); - DigitControl : out STD_LOGIC_VECTOR(DIGITS - 1 downto 0) + SegmentControl : out std_logic_vector(7 downto 0); + DigitControl : out std_logic_vector(DIGITS - 1 downto 0) ); -end; +end entity; architecture rtl of io_7SegmentMux_BCD is - signal DigitCounter_rst : STD_LOGIC; - signal DigitCounter_en : STD_LOGIC; - signal DigitCounter_us : UNSIGNED(log2ceilnz(DIGITS) - 1 downto 0) := (others => '0'); + signal DigitCounter_rst : std_logic; + signal DigitCounter_en : std_logic; + signal DigitCounter_us : unsigned(log2ceilnz(DIGITS) - 1 downto 0) := (others => '0'); begin Strobe : entity PoC.misc_StrobeGenerator @@ -84,14 +83,14 @@ begin process(BCDDigits, BCDDots, DigitCounter_us) variable BCDDigit : T_BCD; - variable BCDDot : STD_LOGIC; + variable BCDDot : std_logic; begin BCDDigit := BCDDigits(to_index(DigitCounter_us, BCDDigits'length)); BCDDot := BCDDots(to_index(DigitCounter_us, BCDDigits'length)); - if (BCDDigit < C_BCD_MINUS) then + if BCDDigit < C_BCD_MINUS then SegmentControl <= io_7SegmentDisplayEncoding(BCDDigit, BCDDot, WITH_DOT => TRUE); - elsif (BCDDigit = C_BCD_MINUS) then + elsif BCDDigit = C_BCD_MINUS then SegmentControl <= BCDDot & "1000000"; else SegmentControl <= "00000000"; diff --git a/src/io/io_7SegmentMux_HEX.vhdl b/src/io/io_7SegmentMux_HEX.vhdl index a774ec87..54248335 100644 --- a/src/io/io_7SegmentMux_HEX.vhdl +++ b/src/io/io_7SegmentMux_HEX.vhdl @@ -1,20 +1,19 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: time multiplexed 7 Segment Display Controller for HEX chars +-- Entity: time multiplexed 7 Segment Display Controller for HEX chars -- -- Description: --- ------------------------------------ --- This module is a 7 segment display controller that uses time multiplexing --- to control a common anode for each digit in the display. The shown characters --- are HEX encoded. A dot per digit is optional. +-- ------------------------------------- +-- This module is a 7 segment display controller that uses time multiplexing +-- to control a common anode for each digit in the display. The shown characters +-- are HEX encoded. A dot per digit is optional. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -29,7 +28,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -47,24 +46,24 @@ entity io_7SegmentMux_HEX is generic ( CLOCK_FREQ : FREQ := 100 MHz; REFRESH_RATE : FREQ := 1 kHz; - DIGITS : POSITIVE := 4 + DIGITS : positive := 4 ); port ( - Clock : in STD_LOGIC; + Clock : in std_logic; HexDigits : in T_SLVV_4(DIGITS - 1 downto 0); - HexDots : in STD_LOGIC_VECTOR(DIGITS - 1 downto 0); + HexDots : in std_logic_vector(DIGITS - 1 downto 0); - SegmentControl : out STD_LOGIC_VECTOR(7 downto 0); - DigitControl : out STD_LOGIC_VECTOR(DIGITS - 1 downto 0) + SegmentControl : out std_logic_vector(7 downto 0); + DigitControl : out std_logic_vector(DIGITS - 1 downto 0) ); -end; +end entity; architecture rtl of io_7SegmentMux_HEX is - signal DigitCounter_rst : STD_LOGIC; - signal DigitCounter_en : STD_LOGIC; - signal DigitCounter_us : UNSIGNED(log2ceilnz(DIGITS) - 1 downto 0) := (others => '0'); + signal DigitCounter_rst : std_logic; + signal DigitCounter_en : std_logic; + signal DigitCounter_us : unsigned(log2ceilnz(DIGITS) - 1 downto 0) := (others => '0'); begin Strobe : entity PoC.misc_StrobeGenerator @@ -84,7 +83,7 @@ begin process(HexDigits, HexDots, DigitCounter_us) variable HexDigit : T_SLV_4; - variable HexDot : STD_LOGIC; + variable HexDot : std_logic; begin HexDigit := HexDigits(to_index(DigitCounter_us, HexDigits'length)); HexDot := HexDots(to_index(DigitCounter_us, HexDigits'length)); diff --git a/src/io/io_Debounce.vhdl b/src/io/io_Debounce.vhdl index 605e3c51..c458bd43 100644 --- a/src/io/io_Debounce.vhdl +++ b/src/io/io_Debounce.vhdl @@ -1,30 +1,29 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- Thomas B. Preusser -- --- Module: Debounce module for BITS many bouncing input pins. +-- Entity: Debounce module for BITS many bouncing input pins. -- -- Description: --- ------------------------------------ --- This module debounces several input pins preventing input changes --- following a previous one within the configured BOUNCE_TIME to pass. --- Internally, the forwarded state is locked for, at least, this BOUNCE_TIME. --- As the backing timer is restarted on every input fluctuation, the next --- passing input update must have seen a stabilized input. +-- ------------------------------------- +-- This module debounces several input pins preventing input changes +-- following a previous one within the configured ``BOUNCE_TIME`` to pass. +-- Internally, the forwarded state is locked for, at least, this ``BOUNCE_TIME``. +-- As the backing timer is restarted on every input fluctuation, the next +-- passing input update must have seen a stabilized input. -- --- The parameter COMMON_LOCK uses a single internal timer for all processed --- inputs. Thus, all inputs must stabilize before any one may pass changed. --- This option is usually fully acceptable for user inputs such as push buttons. +-- The parameter ``COMMON_LOCK`` uses a single internal timer for all processed +-- inputs. Thus, all inputs must stabilize before any one may pass changed. +-- This option is usually fully acceptable for user inputs such as push buttons. -- --- The parameter ADD_INPUT_SYNCHRONIZERS triggers the optional instantiation --- of a two-FF input synchronizer on each input bit. +-- The parameter ``ADD_INPUT_SYNCHRONIZERS`` triggers the optional instantiation +-- of a two-FF input synchronizer on each input bit. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -39,7 +38,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -55,7 +54,7 @@ entity io_Debounce is CLOCK_FREQ : FREQ; BOUNCE_TIME : t_time; BITS : positive := 1; - INIT : STD_LOGIC_VECTOR := x"00000000"; -- initial state of Output + INIT : std_logic_vector := x"00000000"; -- initial state of Output ADD_INPUT_SYNCHRONIZERS : boolean := true; COMMON_LOCK : boolean := false ); @@ -65,7 +64,7 @@ entity io_Debounce is Input : in std_logic_vector(BITS-1 downto 0); Output : out std_logic_vector(BITS-1 downto 0) := resize(descend(INIT), BITS) ); -end; +end entity; architecture rtl of io_Debounce is diff --git a/src/io/io_FanControl.vhdl b/src/io/io_FanControl.vhdl index 688b0dca..68599f36 100644 --- a/src/io/io_FanControl.vhdl +++ b/src/io/io_FanControl.vhdl @@ -1,14 +1,15 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: Generic Fan Controller +-- Entity: Generic Fan Controller -- -- Description: --- ------------------------------------ +-- ------------------------------------- +-- .. code-block:: none +-- -- This module generates a PWM signal for a 3-pin (transistor controlled) or -- 4-pin fan header. The FPGAs temperature is read from device specific system -- monitors (normal, user temperature, over temperature). @@ -29,7 +30,7 @@ -- -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -44,7 +45,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -62,48 +63,48 @@ use PoC.xil.all; entity io_FanControl is generic ( CLOCK_FREQ : FREQ; - ADD_INPUT_SYNCHRONIZERS : BOOLEAN := TRUE; - ENABLE_TACHO : BOOLEAN := FALSE + ADD_INPUT_SYNCHRONIZERS : boolean := TRUE; + ENABLE_TACHO : boolean := FALSE ); port ( -- Global Control - Clock : in STD_LOGIC; - Reset : in STD_LOGIC; + Clock : in std_logic; + Reset : in std_logic; -- Fan Control derived from internal System Health Monitor - Fan_PWM : out STD_LOGIC; + Fan_PWM : out std_logic; -- Decoding of Speed Sensor (Requires ENABLE_TACHO) Fan_Tacho : in std_logic := 'X'; TachoFrequency : out std_logic_vector(15 downto 0) ); -end; +end entity; architecture rtl of io_FanControl is constant TIME_STARTUP : T_TIME := 500.0e-3; -- StartUp time - constant PWM_RESOLUTION : POSITIVE := 4; -- 4 Bit resolution => 0 to 15 steps + constant PWM_RESOLUTION : positive := 4; -- 4 Bit resolution => 0 to 15 steps constant PWM_FREQ : FREQ := 10 Hz; -- - constant TACHO_RESOLUTION : POSITIVE := 8; + constant TACHO_RESOLUTION : positive := 8; - signal PWM_PWMIn : STD_LOGIC_VECTOR(PWM_RESOLUTION - 1 downto 0); - signal PWM_PWMOut : STD_LOGIC := '0'; + signal PWM_PWMIn : std_logic_vector(PWM_RESOLUTION - 1 downto 0); + signal PWM_PWMOut : std_logic := '0'; begin -- System Monitor and temperature to PWM ratio calculation for Virtex6 -- ========================================================================================================================================================== - genXilinx : if (VENDOR = VENDOR_XILINX) generate - signal OverTemperature_async : STD_LOGIC; - signal OverTemperature_sync : STD_LOGIC; + genXilinx : if VENDOR = VENDOR_XILINX generate + signal OverTemperature_async : std_logic; + signal OverTemperature_sync : std_logic; - signal UserTemperature_async : STD_LOGIC; - signal UserTemperature_sync : STD_LOGIC; + signal UserTemperature_async : std_logic; + signal UserTemperature_sync : std_logic; - signal TC_Timeout : STD_LOGIC; - signal StartUp : STD_LOGIC; + signal TC_Timeout : std_logic; + signal StartUp : std_logic; begin - genML605 : if (str_imatch(BOARD_NAME, "ML605") = TRUE) generate + genML605 : if str_imatch(BOARD_NAME, "ML605") generate SystemMonitor : xil_SystemMonitor_Virtex6 port map ( Reset => Reset, -- Reset signal for the System Monitor control logic @@ -115,7 +116,7 @@ begin VN => '0' ); end generate; - genSeries7Board : if ((str_imatch(BOARD_NAME, "KC705") or str_imatch(BOARD_NAME, "VC707")) = TRUE) generate + genSeries7Board : if str_imatch(BOARD_NAME, "KC705") or str_imatch(BOARD_NAME, "VC707") generate SystemMonitor : xil_SystemMonitor_Series7 port map ( Reset => Reset, -- Reset signal for the System Monitor control logic @@ -158,25 +159,25 @@ begin process(StartUp, UserTemperature_sync, OverTemperature_sync) begin - if (StartUp = '1') then PWM_PWMIn <= to_slv(2**(PWM_RESOLUTION) - 1, PWM_RESOLUTION); -- 100%; start up - elsif (OverTemperature_sync = '1') then PWM_PWMIn <= to_slv(2**(PWM_RESOLUTION) - 1, PWM_RESOLUTION); -- 100% + if (StartUp = '1') then PWM_PWMIn <= to_slv(2**PWM_RESOLUTION - 1, PWM_RESOLUTION); -- 100%; start up + elsif (OverTemperature_sync = '1') then PWM_PWMIn <= to_slv(2**PWM_RESOLUTION - 1, PWM_RESOLUTION); -- 100% elsif (UserTemperature_sync = '1') then PWM_PWMIn <= to_slv(2**(PWM_RESOLUTION - 1), PWM_RESOLUTION); -- 50% else PWM_PWMIn <= to_slv(4, PWM_RESOLUTION); -- 13% end if; end process; end generate; - genAltera : if (VENDOR = VENDOR_ALTERA) generate + genAltera : if VENDOR = VENDOR_ALTERA generate -- signal OverTemperature_async : STD_LOGIC; - signal OverTemperature_sync : STD_LOGIC; + signal OverTemperature_sync : std_logic; -- signal UserTemperature_async : STD_LOGIC; - signal UserTemperature_sync : STD_LOGIC; + signal UserTemperature_sync : std_logic; - signal TC_Timeout : STD_LOGIC; - signal StartUp : STD_LOGIC; + signal TC_Timeout : std_logic; + signal StartUp : std_logic; begin - genDE4 : if (str_imatch(BOARD_NAME, "DE4") = TRUE) generate + genDE4 : if str_imatch(BOARD_NAME, "DE4") generate OverTemperature_sync <= '0'; UserTemperature_sync <= '1'; end generate; @@ -199,8 +200,8 @@ begin process(StartUp, UserTemperature_sync, OverTemperature_sync) begin - if (StartUp = '1') then PWM_PWMIn <= to_slv(2**(PWM_RESOLUTION) - 1, PWM_RESOLUTION); -- 100%; start up - elsif (OverTemperature_sync = '1') then PWM_PWMIn <= to_slv(2**(PWM_RESOLUTION) - 1, PWM_RESOLUTION); -- 100% + if (StartUp = '1') then PWM_PWMIn <= to_slv(2**PWM_RESOLUTION - 1, PWM_RESOLUTION); -- 100%; start up + elsif (OverTemperature_sync = '1') then PWM_PWMIn <= to_slv(2**PWM_RESOLUTION - 1, PWM_RESOLUTION); -- 100% elsif (UserTemperature_sync = '1') then PWM_PWMIn <= to_slv(2**(PWM_RESOLUTION - 1), PWM_RESOLUTION); -- 50% else PWM_PWMIn <= to_slv(4, PWM_RESOLUTION); -- 13% end if; @@ -227,18 +228,18 @@ begin -- tacho signal interpretation -> convert to RPM -- ========================================================================================================================================================== - genNoTacho : if (ENABLE_TACHO = FALSE) generate + genNoTacho : if not ENABLE_TACHO generate TachoFrequency <= (TachoFrequency'range => 'X'); end generate; - genTacho : if (ENABLE_TACHO = TRUE) generate - signal Tacho_sync : STD_LOGIC; - signal Tacho_Freq : STD_LOGIC_VECTOR(TACHO_RESOLUTION - 1 downto 0); + genTacho : if ENABLE_TACHO generate + signal Tacho_sync : std_logic; + signal Tacho_Freq : std_logic_vector(TACHO_RESOLUTION - 1 downto 0); begin -- Input Synchronization - genNoSync : if (ADD_INPUT_SYNCHRONIZERS = FALSE) generate + genNoSync : if not ADD_INPUT_SYNCHRONIZERS generate Tacho_sync <= Fan_Tacho; end generate; - genSync : if (ADD_INPUT_SYNCHRONIZERS = TRUE) generate + genSync : if ADD_INPUT_SYNCHRONIZERS generate sync_i : entity PoC.sync_Bits port map ( Clock => Clock, -- Clock to be synchronized to diff --git a/src/io/io_FrequencyCounter.vhdl b/src/io/io_FrequencyCounter.vhdl index 8a33a9ad..51f412eb 100644 --- a/src/io/io_FrequencyCounter.vhdl +++ b/src/io/io_FrequencyCounter.vhdl @@ -1,18 +1,17 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: TODO +-- Entity: TODO -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2014 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -27,7 +26,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -42,32 +41,32 @@ entity io_FrequencyCounter is generic ( CLOCK_FREQ : FREQ := 100 MHz; TIMEBASE : T_TIME := 1.0; - RESOLUTION : POSITIVE := 8 + RESOLUTION : positive := 8 ); port ( - Clock : in STD_LOGIC; - Reset : in STD_LOGIC; - FreqIn : in STD_LOGIC; - FreqOut : out STD_LOGIC_VECTOR(RESOLUTION - 1 downto 0) + Clock : in std_logic; + Reset : in std_logic; + FreqIn : in std_logic; + FreqOut : out std_logic_vector(RESOLUTION - 1 downto 0) ); -end; +end entity; architecture rtl of io_FrequencyCounter is - constant TIMEBASECOUNTER_MAX : POSITIVE := TimingToCycles(TIMEBASE, CLOCK_FREQ); - constant TIMEBASECOUNTER_BITS : POSITIVE := log2ceilnz(TIMEBASECOUNTER_MAX); - constant REQUENCYCOUNTER_MAX : POSITIVE := 2**RESOLUTION; - constant FREQUENCYCOUNTER_BITS : POSITIVE := RESOLUTION; + constant TIMEBASECOUNTER_MAX : positive := TimingToCycles(TIMEBASE, CLOCK_FREQ); + constant TIMEBASECOUNTER_BITS : positive := log2ceilnz(TIMEBASECOUNTER_MAX); + constant REQUENCYCOUNTER_MAX : positive := 2**RESOLUTION; + constant FREQUENCYCOUNTER_BITS : positive := RESOLUTION; - signal TimeBaseCounter_us : UNSIGNED(TIMEBASECOUNTER_BITS - 1 downto 0) := (others => '0'); - signal TimeBaseCounter_ov : STD_LOGIC; - signal FrequencyCounter_us : UNSIGNED(FREQUENCYCOUNTER_BITS downto 0) := (others => '0'); - signal FrequencyCounter_ov : STD_LOGIC; + signal TimeBaseCounter_us : unsigned(TIMEBASECOUNTER_BITS - 1 downto 0) := (others => '0'); + signal TimeBaseCounter_ov : std_logic; + signal FrequencyCounter_us : unsigned(FREQUENCYCOUNTER_BITS downto 0) := (others => '0'); + signal FrequencyCounter_ov : std_logic; - signal FreqIn_d : STD_LOGIC := '0'; - signal FreqIn_re : STD_LOGIC; + signal FreqIn_d : std_logic := '0'; + signal FreqIn_re : std_logic; - signal FreqOut_d : STD_LOGIC_VECTOR(RESOLUTION - 1 downto 0) := (others => '0'); + signal FreqOut_d : std_logic_vector(RESOLUTION - 1 downto 0) := (others => '0'); begin FreqIn_d <= FreqIn when rising_edge(Clock); diff --git a/src/io/io_GlitchFilter.vhdl b/src/io/io_GlitchFilter.vhdl index a6187a89..75a92e8b 100644 --- a/src/io/io_GlitchFilter.vhdl +++ b/src/io/io_GlitchFilter.vhdl @@ -1,19 +1,18 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: Glitch Filter +-- Entity: Glitch Filter -- -- Description: --- ------------------------------------ --- This module filters glitches on a wire. The high and low spike suppression --- cycle counts can be configured. +-- ------------------------------------- +-- This module filters glitches on a wire. The high and low spike suppression +-- cycle counts can be configured. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -28,7 +27,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -41,21 +40,21 @@ use PoC.utils.all; entity io_GlitchFilter is generic ( - HIGH_SPIKE_SUPPRESSION_CYCLES : NATURAL := 5; - LOW_SPIKE_SUPPRESSION_CYCLES : NATURAL := 5 + HIGH_SPIKE_SUPPRESSION_CYCLES : natural := 5; + LOW_SPIKE_SUPPRESSION_CYCLES : natural := 5 ); port ( - Clock : in STD_LOGIC; - Input : in STD_LOGIC; - Output : out STD_LOGIC + Clock : in std_logic; + Input : in std_logic; + Output : out std_logic ); end entity; architecture rtl of io_GlitchFilter is -- Timing table ID - constant TTID_HIGH_SPIKE : NATURAL := 0; - constant TTID_LOW_SPIKE : NATURAL := 1; + constant TTID_HIGH_SPIKE : natural := 0; + constant TTID_LOW_SPIKE : natural := 1; -- Timing table constant TIMING_TABLE : T_NATVEC := ( @@ -63,19 +62,19 @@ architecture rtl of io_GlitchFilter is TTID_LOW_SPIKE => LOW_SPIKE_SUPPRESSION_CYCLES ); - signal State : STD_LOGIC := '0'; - signal NextState : STD_LOGIC; + signal State : std_logic := '0'; + signal NextState : std_logic; - signal TC_en : STD_LOGIC; - signal TC_Load : STD_LOGIC; - signal TC_Slot : NATURAL; - signal TC_Timeout : STD_LOGIC; + signal TC_en : std_logic; + signal TC_Load : std_logic; + signal TC_Slot : natural; + signal TC_Timeout : std_logic; begin assert FALSE report "GlitchFilter: " & - "HighSpikeSuppressionCycles=" & INTEGER'image(TIMING_TABLE(TTID_HIGH_SPIKE)) & " " & - "LowSpikeSuppressionCycles=" & INTEGER'image(TIMING_TABLE(TTID_LOW_SPIKE)) & " " + "HighSpikeSuppressionCycles=" & integer'image(TIMING_TABLE(TTID_HIGH_SPIKE)) & " " & + "LowSpikeSuppressionCycles=" & integer'image(TIMING_TABLE(TTID_LOW_SPIKE)) & " " severity NOTE; process(Clock) diff --git a/src/io/io_KeyPadScanner.vhdl b/src/io/io_KeyPadScanner.vhdl index d3032326..3725c5fb 100644 --- a/src/io/io_KeyPadScanner.vhdl +++ b/src/io/io_KeyPadScanner.vhdl @@ -1,22 +1,21 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: Keypad button matrix scanner +-- Entity: Keypad button matrix scanner -- -- Description: --- ------------------------------------ --- This module drives a one-hot encoded column vector to read back a rows --- vector. By scanning column-by-column it's possible to extract the current --- button state of the whole keypad. The scanner uses high-active logic. The --- keypad size and scan frequency can be configured. The outputed signal --- matrix is not debounced. +-- ------------------------------------- +-- This module drives a one-hot encoded column vector to read back a rows +-- vector. By scanning column-by-column it's possible to extract the current +-- button state of the whole keypad. The scanner uses high-active logic. The +-- keypad size and scan frequency can be configured. The outputed signal +-- matrix is not debounced. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -31,7 +30,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -48,18 +47,18 @@ entity io_KeyPadScanner is generic ( CLOCK_FREQ : FREQ := 100 MHz; SCAN_FREQ : FREQ := 1 kHz; - ROWS : POSITIVE := 4; - COLUMNS : POSITIVE := 4; - ADD_INPUT_SYNCHRONIZERS : BOOLEAN := TRUE + ROWS : positive := 4; + COLUMNS : positive := 4; + ADD_INPUT_SYNCHRONIZERS : boolean := TRUE ); port ( - Clock : in STD_LOGIC; - Reset : in STD_LOGIC; + Clock : in std_logic; + Reset : in std_logic; -- Matrix interface KeyPadMatrix : out T_SLM(COLUMNS - 1 downto 0, ROWS - 1 downto 0); -- KeyPad interface - ColumnVector : out STD_LOGIC_VECTOR(COLUMNS - 1 downto 0); - RowVector : in STD_LOGIC_VECTOR(ROWS - 1 downto 0) + ColumnVector : out std_logic_vector(COLUMNS - 1 downto 0); + RowVector : in std_logic_vector(ROWS - 1 downto 0) ); end entity; @@ -67,16 +66,16 @@ end entity; architecture rtl of io_KeyPadScanner is constant SHIFT_FREQ : FREQ := SCAN_FREQ * COLUMNS; - constant COLUMNTIMER_MAX : POSITIVE := TimingToCycles(to_time(SHIFT_FREQ), CLOCK_FREQ) - 1; - constant COLUMNTIMER_BITS : POSITIVE := log2ceilnz(COLUMNTIMER_MAX) + 1; + constant COLUMNTIMER_MAX : positive := TimingToCycles(to_time(SHIFT_FREQ), CLOCK_FREQ) - 1; + constant COLUMNTIMER_BITS : positive := log2ceilnz(COLUMNTIMER_MAX) + 1; - signal ColumnTimer_rst : STD_LOGIC; - signal ColumnTimer_s : SIGNED(COLUMNTIMER_BITS - 1 downto 0) := to_signed(COLUMNTIMER_MAX, COLUMNTIMER_BITS); + signal ColumnTimer_rst : std_logic; + signal ColumnTimer_s : signed(COLUMNTIMER_BITS - 1 downto 0) := to_signed(COLUMNTIMER_MAX, COLUMNTIMER_BITS); - signal ColumnSelect_en : STD_LOGIC; - signal ColumnSelect_d : STD_LOGIC_VECTOR(COLUMNS - 1 downto 0) := (0 => '1', others => '0'); + signal ColumnSelect_en : std_logic; + signal ColumnSelect_d : std_logic_vector(COLUMNS - 1 downto 0) := (0 => '1', others => '0'); - signal Rows_sync : STD_LOGIC_VECTOR(ROWS - 1 downto 0); + signal Rows_sync : std_logic_vector(ROWS - 1 downto 0); signal KeyPadMatrix_r : T_SLM(COLUMNS - 1 downto 0, ROWS - 1 downto 0) := (others => (others => '0')); begin -- generate a < 100 kHz shift enable to 'clock' the ColumnSelect shift register @@ -89,7 +88,7 @@ begin ColumnVector <= ColumnSelect_d; -- synchronize input signals - genSync : if (ADD_INPUT_SYNCHRONIZERS = TRUE) generate + genSync : if ADD_INPUT_SYNCHRONIZERS generate sync : entity PoC.sync_Bits generic map ( BITS => ROWS @@ -100,7 +99,7 @@ begin Output => Rows_sync ); end generate; - genNoSync : if (ADD_INPUT_SYNCHRONIZERS = FALSE) generate + genNoSync : if not ADD_INPUT_SYNCHRONIZERS generate Rows_sync <= RowVector; end generate; diff --git a/src/io/io_PulseWidthModulation.vhdl b/src/io/io_PulseWidthModulation.vhdl index b8d2f289..dcbcc3e3 100644 --- a/src/io/io_PulseWidthModulation.vhdl +++ b/src/io/io_PulseWidthModulation.vhdl @@ -1,19 +1,18 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: Pulse Width Modulated (PWM) signal generator +-- Entity: Pulse Width Modulated (PWM) signal generator -- -- Description: --- ------------------------------------ --- This module generates a pulse width modulated signal, that can be configured --- in frequency (PWM_FREQ) and modulation granularity (PWM_RESOLUTION). +-- ------------------------------------- +-- This module generates a pulse width modulated signal, that can be configured +-- in frequency (``PWM_FREQ``) and modulation granularity (``PWM_RESOLUTION``). -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -28,7 +27,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -43,27 +42,27 @@ entity io_PulseWidthModulation is generic ( CLOCK_FREQ : FREQ := 100 MHz; PWM_FREQ : FREQ := 1 kHz; - PWM_RESOLUTION : POSITIVE := 8 + PWM_RESOLUTION : positive := 8 ); port ( - Clock : in STD_LOGIC; - Reset : in STD_LOGIC; - PWMIn : in STD_LOGIC_VECTOR(PWM_RESOLUTION - 1 downto 0); - PWMOut : out STD_LOGIC + Clock : in std_logic; + Reset : in std_logic; + PWMIn : in std_logic_vector(PWM_RESOLUTION - 1 downto 0); + PWMOut : out std_logic ); -end; +end entity; architecture rtl of io_PulseWidthModulation is - constant PWM_STEPS : POSITIVE := 2**PWM_RESOLUTION; + constant PWM_STEPS : positive := 2**PWM_RESOLUTION; constant PWM_STEP_FREQ : FREQ := PWM_FREQ * (PWM_STEPS - 1); - constant PWM_FREQUENCYCOUNTER_MAX : POSITIVE := (CLOCK_FREQ+PWM_STEP_FREQ-1 Hz) / PWM_STEP_FREQ; -- division with round-up - constant PWM_FREQUENCYCOUNTER_BITS : POSITIVE := log2ceilnz(PWM_FREQUENCYCOUNTER_MAX); + constant PWM_FREQUENCYCOUNTER_MAX : positive := (CLOCK_FREQ+PWM_STEP_FREQ-1 Hz) / PWM_STEP_FREQ; -- division with round-up + constant PWM_FREQUENCYCOUNTER_BITS : positive := log2ceilnz(PWM_FREQUENCYCOUNTER_MAX); - signal PWM_FrequencyCounter_us : UNSIGNED(PWM_FREQUENCYCOUNTER_BITS downto 0) := (others => '0'); - signal PWM_FrequencyCounter_ov : STD_LOGIC; - signal PWM_PulseCounter_us : UNSIGNED(PWM_RESOLUTION - 1 downto 0) := (others => '0'); - signal PWM_PulseCounter_ov : STD_LOGIC; + signal PWM_FrequencyCounter_us : unsigned(PWM_FREQUENCYCOUNTER_BITS downto 0) := (others => '0'); + signal PWM_FrequencyCounter_ov : std_logic; + signal PWM_PulseCounter_us : unsigned(PWM_RESOLUTION - 1 downto 0) := (others => '0'); + signal PWM_PulseCounter_ov : std_logic; begin -- PWM frequency counter diff --git a/src/io/io_TimingCounter.vhdl b/src/io/io_TimingCounter.vhdl index 67e148f5..bda4aaba 100644 --- a/src/io/io_TimingCounter.vhdl +++ b/src/io/io_TimingCounter.vhdl @@ -1,21 +1,20 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: optimized down-counter to control timings for low speed signals +-- Entity: optimized down-counter to control timings for low speed signals -- -- Description: --- ------------------------------------ --- This down-counter can be configured with a TIMING_TABLE (a ROM), from which --- the initial counter value is loaded. The table index can be selected by --- 'Slot'. 'Timeout' is a registered output. Up to 16 values fit into one ROM --- consisting of 'log2ceilnz(imax(TIMING_TABLE)) + 1' 6-input LUTs. +-- ------------------------------------- +-- This down-counter can be configured with a ``TIMING_TABLE`` (a ROM), from which +-- the initial counter value is loaded. The table index can be selected by +-- ``Slot``. ``Timeout`` is a registered output. Up to 16 values fit into one ROM +-- consisting of ``log2ceilnz(imax(TIMING_TABLE)) + 1`` 6-input LUTs. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -30,7 +29,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -46,13 +45,13 @@ entity io_TimingCounter is TIMING_TABLE : T_NATVEC -- timing table ); port ( - Clock : in STD_LOGIC; -- clock - Enable : in STD_LOGIC; -- enable counter - Load : in STD_LOGIC; -- load Timing Value from TIMING_TABLE selected by slot - Slot : in NATURAL range 0 to (TIMING_TABLE'length - 1); -- - Timeout : out STD_LOGIC -- timing reached + Clock : in std_logic; -- clock + Enable : in std_logic; -- enable counter + Load : in std_logic; -- load Timing Value from TIMING_TABLE selected by slot + Slot : in natural range 0 to (TIMING_TABLE'length - 1); -- + Timeout : out std_logic -- timing reached ); -end; +end entity; architecture rtl of io_TimingCounter is @@ -62,16 +61,16 @@ architecture rtl of io_TimingCounter is assert (not MY_VERBOSE) report "TIMING_TABLE (transformed):" severity NOTE; for i in vec'range loop Result(i) := vec(i) - 1; - assert (not MY_VERBOSE) report " " & INTEGER'image(i) & " - " & INTEGER'image(Result(i)) severity NOTE; + assert (not MY_VERBOSE) report " " & integer'image(i) & " - " & INTEGER'image(Result(i)) severity NOTE; end loop; return Result; end; constant TIMING_TABLE2 : T_INTVEC := transform(TIMING_TABLE); - constant TIMING_MAX : NATURAL := imax(TIMING_TABLE2); - constant COUNTER_BITS : NATURAL := log2ceilnz(TIMING_MAX + 1); + constant TIMING_MAX : natural := imax(TIMING_TABLE2); + constant COUNTER_BITS : natural := log2ceilnz(TIMING_MAX + 1); - signal Counter_s : SIGNED(COUNTER_BITS downto 0) := to_signed(TIMING_TABLE2(0), COUNTER_BITS + 1); + signal Counter_s : signed(COUNTER_BITS downto 0) := to_signed(TIMING_TABLE2(0), COUNTER_BITS + 1); begin process(Clock) diff --git a/src/io/pmod/pmod.pkg.vhdl b/src/io/pmod/pmod.pkg.vhdl index 2f76e657..d2d7c786 100644 --- a/src/io/pmod/pmod.pkg.vhdl +++ b/src/io/pmod/pmod.pkg.vhdl @@ -1,19 +1,18 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- -- Package: VHDL package for component declarations, types and -- functions associated to the PoC.io.pmod namespace -- -- Description: --- ------------------------------------ +-- ------------------------------------- -- For detailed documentation see below. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -28,7 +27,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -39,33 +38,33 @@ library PoC; package pmod is type T_PMOD_KYPD_KEYPAD is record - Key0 : STD_LOGIC; - Key1 : STD_LOGIC; - Key2 : STD_LOGIC; - Key3 : STD_LOGIC; - Key4 : STD_LOGIC; - Key5 : STD_LOGIC; - Key6 : STD_LOGIC; - Key7 : STD_LOGIC; - Key8 : STD_LOGIC; - Key9 : STD_LOGIC; - KeyA : STD_LOGIC; - KeyB : STD_LOGIC; - KeyC : STD_LOGIC; - KeyD : STD_LOGIC; - KeyE : STD_LOGIC; - KeyF : STD_LOGIC; + Key0 : std_logic; + Key1 : std_logic; + Key2 : std_logic; + Key3 : std_logic; + Key4 : std_logic; + Key5 : std_logic; + Key6 : std_logic; + Key7 : std_logic; + Key8 : std_logic; + Key9 : std_logic; + KeyA : std_logic; + KeyB : std_logic; + KeyC : std_logic; + KeyD : std_logic; + KeyE : std_logic; + KeyF : std_logic; end record; type T_PMOD_SSD_PINS is record - AnodeA : STD_LOGIC; - AnodeB : STD_LOGIC; - AnodeC : STD_LOGIC; - AnodeD : STD_LOGIC; - AnodeE : STD_LOGIC; - AnodeF : STD_LOGIC; - AnodeG : STD_LOGIC; - Cathode : STD_LOGIC; + AnodeA : std_logic; + AnodeB : std_logic; + AnodeC : std_logic; + AnodeD : std_logic; + AnodeE : std_logic; + AnodeF : std_logic; + AnodeG : std_logic; + Cathode : std_logic; end record; end package; diff --git a/src/io/pmod/pmod_KYPD.vhdl b/src/io/pmod/pmod_KYPD.vhdl index 06e9ec6e..da222e08 100644 --- a/src/io/pmod/pmod_KYPD.vhdl +++ b/src/io/pmod/pmod_KYPD.vhdl @@ -1,23 +1,22 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: Digilent Peripherial Module: 4x4 Keypad (Pmod_KYPD) +-- Entity: Digilent Peripherial Module: 4x4 Keypad (Pmod_KYPD) -- -- Description: --- ------------------------------------ --- This module drives a 4-bit one-cold encoded column vector to read back a --- 4-bit rows vector. By scanning column-by-column it's possible to extract --- the current button state of the whole keypad. This wrapper converts the --- high-active signals from io_KeyPadScanner to low-active signals for the --- pmod. An additional debounce circuit filters the button signals. The scan --- frequency and bounce time can be configured. +-- ------------------------------------- +-- This module drives a 4-bit one-cold encoded column vector to read back a +-- 4-bit rows vector. By scanning column-by-column it's possible to extract +-- the current button state of the whole keypad. This wrapper converts the +-- high-active signals from :doc:`PoC.io.KeypadScanner <../io_KeyPadScanner>` +-- to low-active signals for the pmod. An additional debounce circuit filters +-- the button signals. The scan frequency and bounce time can be configured. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -32,7 +31,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -51,24 +50,24 @@ entity pmod_KYPD is BOUNCE_TIME : T_TIME := 10.0e-3 ); port ( - Clock : in STD_LOGIC; - Reset : in STD_LOGIC; + Clock : in std_logic; + Reset : in std_logic; -- Matrix interface Keys : out T_PMOD_KYPD_KEYPAD; -- KeyPad interface - Columns_n : out STD_LOGIC_VECTOR(3 downto 0); - Rows_n : in STD_LOGIC_VECTOR(3 downto 0) + Columns_n : out std_logic_vector(3 downto 0); + Rows_n : in std_logic_vector(3 downto 0) ); end entity; architecture rtl of pmod_KYPD is - signal ColumnVector : STD_LOGIC_VECTOR(3 downto 0); - signal RowVector : STD_LOGIC_VECTOR(3 downto 0); + signal ColumnVector : std_logic_vector(3 downto 0); + signal RowVector : std_logic_vector(3 downto 0); signal KeyPadMatrix : T_SLM(3 downto 0, 3 downto 0); - signal KeyPadMatrix_slv : STD_LOGIC_VECTOR(15 downto 0); - signal KeyPadVector : STD_LOGIC_VECTOR(15 downto 0); + signal KeyPadMatrix_slv : std_logic_vector(15 downto 0); + signal KeyPadVector : std_logic_vector(15 downto 0); signal KeyPad : T_SLM(3 downto 0, 3 downto 0); begin diff --git a/src/io/pmod/pmod_SSD.vhdl b/src/io/pmod/pmod_SSD.vhdl index 85a81417..8476986b 100644 --- a/src/io/pmod/pmod_SSD.vhdl +++ b/src/io/pmod/pmod_SSD.vhdl @@ -1,17 +1,18 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: Digilent Peritherial Module: Pmod_SSD +-- Entity: Digilent Peritherial Module: Pmod_SSD -- -- Description: --- ------------------------------------ --- This module drives a dual-digit 7-segment display (Pmod_SSD). The module --- expects two binary encoded 4-bit 'Digit' signals and drives a 2x6 bit --- Pmod connector (7 anode bits, 1 cathode bit). +-- ------------------------------------- +-- This module drives a dual-digit 7-segment display (Pmod_SSD). The module +-- expects two binary encoded 4-bit ``Digit`` signals and drives a 2x6 bit +-- Pmod connector (7 anode bits, 1 cathode bit). +-- +-- -- code-block:. none -- -- Segment Pos./ Index -- AAA | 000 @@ -23,7 +24,7 @@ -- DDD DOT | 333 7 -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -38,7 +39,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -58,10 +59,10 @@ entity pmod_SSD is REFRESH_RATE : FREQ := 1 kHz ); port ( - Clock : in STD_LOGIC; + Clock : in std_logic; - Digit0 : in STD_LOGIC_VECTOR(3 downto 0); - Digit1 : in STD_LOGIC_VECTOR(3 downto 0); + Digit0 : in std_logic_vector(3 downto 0); + Digit1 : in std_logic_vector(3 downto 0); SSD : out T_PMOD_SSD_PINS ); @@ -69,17 +70,17 @@ end entity; architecture rtl of pmod_SSD is - constant REFRESHTIMER_MAX : POSITIVE := TimingToCycles(to_time(REFRESH_RATE), CLOCK_FREQ) - 1; - constant REFRESHTIMER_BITS : POSITIVE := log2ceilnz(REFRESHTIMER_MAX) + 1; + constant REFRESHTIMER_MAX : positive := TimingToCycles(to_time(REFRESH_RATE), CLOCK_FREQ) - 1; + constant REFRESHTIMER_BITS : positive := log2ceilnz(REFRESHTIMER_MAX) + 1; - signal RefreshTimer_rst : STD_LOGIC; - signal RefreshTimer_s : SIGNED(REFRESHTIMER_BITS - 1 downto 0) := to_signed(REFRESHTIMER_MAX, REFRESHTIMER_BITS); + signal RefreshTimer_rst : std_logic; + signal RefreshTimer_s : signed(REFRESHTIMER_BITS - 1 downto 0) := to_signed(REFRESHTIMER_MAX, REFRESHTIMER_BITS); - signal CathodeSelect_en : STD_LOGIC; - signal CathodeSelect_r : STD_LOGIC := '0'; + signal CathodeSelect_en : std_logic; + signal CathodeSelect_r : std_logic := '0'; - signal Digit : STD_LOGIC_VECTOR(3 downto 0); - signal Segments : STD_LOGIC_VECTOR(6 downto 0); + signal Digit : std_logic_vector(3 downto 0); + signal Segments : std_logic_vector(6 downto 0); begin -- generate a < 1 kHz enable to toggle the CathodeSelect register RefreshTimer_s <= downcounter_next(cnt => RefreshTimer_s, rst => RefreshTimer_rst, INIT => REFRESHTIMER_MAX) when rising_edge(Clock); diff --git a/src/io/pmod/pmod_USBUART.vhdl b/src/io/pmod/pmod_USBUART.vhdl index eceb6489..c306ed40 100644 --- a/src/io/pmod/pmod_USBUART.vhdl +++ b/src/io/pmod/pmod_USBUART.vhdl @@ -1,20 +1,20 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: Digilent Peripherial Module: USB-UART (Pmod_USBUART) +-- Entity: Digilent Peripherial Module: USB-UART (Pmod_USBUART) -- -- Description: --- ------------------------------------ --- This module abstracts a FTDI FT232R USB-UART bridge. The FT232R supports --- up to 3 MBaud. A synchronous FIFO interface (32x words) is provided. --- Hardware flow control (RTS_CTS) is enabled. +-- ------------------------------------- +-- This module abstracts a FTDI FT232R USB-UART bridge by instantiating a +-- :doc:`PoC.io.uart.fifo <../uart/uart_fifo>`. The FT232R supports up to +-- 3 MBaud. A synchronous FIFO interface with a 32 words buffer is provided. +-- Hardware flow control (RTS_CTS) is enabled. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -29,7 +29,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -46,21 +46,21 @@ entity pmod_USBUART is BAUDRATE : BAUD := 115200 Bd ); port ( - Clock : in STD_LOGIC; - Reset : in STD_LOGIC; + Clock : in std_logic; + Reset : in std_logic; - TX_put : in STD_LOGIC; - TX_Data : in STD_LOGIC_VECTOR(7 downto 0); - TX_Full : out STD_LOGIC; + TX_put : in std_logic; + TX_Data : in std_logic_vector(7 downto 0); + TX_Full : out std_logic; - RX_Valid : out STD_LOGIC; - RX_Data : out STD_LOGIC_VECTOR(7 downto 0); - RX_got : in STD_LOGIC; + RX_Valid : out std_logic; + RX_Data : out std_logic_vector(7 downto 0); + RX_got : in std_logic; - UART_TX : out STD_LOGIC; - UART_RX : in STD_LOGIC; - UART_RTS : out STD_LOGIC; - UART_CTS : in STD_LOGIC + UART_TX : out std_logic; + UART_RX : in std_logic; + UART_RTS : out std_logic; + UART_CTS : in std_logic ); end entity; diff --git a/src/io/uart/uart.pkg.vhdl b/src/io/uart/uart.pkg.vhdl index 5b660867..33d9a34c 100644 --- a/src/io/uart/uart.pkg.vhdl +++ b/src/io/uart/uart.pkg.vhdl @@ -1,16 +1,15 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- =========================================================================== --- Package: UART (RS232) Components for PoC.io.uart --- +-- ============================================================================= -- Authors: Martin Zabel -- Thomas B. Preusser -- Patrick Lehmann -- +-- Package: UART (RS232) Components for PoC.io.uart +-- -- License: --- =========================================================================== +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -25,7 +24,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- =========================================================================== +-- ============================================================================= library IEEE; use IEEE.std_logic_1164.all; @@ -52,7 +51,7 @@ package uart is 25 => 460800 Bd, 26 => 500000 Bd, 27 => 576000 Bd, 28 => 921600 Bd ); - function io_UART_IsTypicalBaudRate(br : BAUD) return BOOLEAN; + function io_UART_IsTypicalBaudRate(br : BAUD) return boolean; -- Bit Clock Generator: 8 Ticks per Bit component uart_bclk @@ -133,15 +132,15 @@ package uart is Reset : in std_logic; -- FIFO interface - TX_put : in STD_LOGIC; - TX_Data : in STD_LOGIC_VECTOR(7 downto 0); - TX_Full : out STD_LOGIC; - TX_EmptyState : out STD_LOGIC_VECTOR(TX_ESTATE_BITS - 1 downto 0); - - RX_Valid : out STD_LOGIC; - RX_Data : out STD_LOGIC_VECTOR(7 downto 0); - RX_got : in STD_LOGIC; - RX_FullState : out STD_LOGIC_VECTOR(RX_FSTATE_BITS - 1 downto 0); + TX_put : in std_logic; + TX_Data : in std_logic_vector(7 downto 0); + TX_Full : out std_logic; + TX_EmptyState : out std_logic_vector(TX_ESTATE_BITS - 1 downto 0); + + RX_Valid : out std_logic; + RX_Data : out std_logic_vector(7 downto 0); + RX_got : in std_logic; + RX_FullState : out std_logic_vector(RX_FSTATE_BITS - 1 downto 0); RX_Overflow : out std_logic; -- External Pins @@ -183,7 +182,7 @@ end package; package body uart is - function io_UART_IsTypicalBaudRate(br : BAUD) return BOOLEAN is + function io_UART_IsTypicalBaudRate(br : BAUD) return boolean is begin for i in C_IO_UART_TYPICAL_BAUDRATES'range loop next when (br /= C_IO_UART_TYPICAL_BAUDRATES(i)); diff --git a/src/io/uart/uart_bclk.vhdl b/src/io/uart/uart_bclk.vhdl index d4ab2230..6eccb804 100644 --- a/src/io/uart/uart_bclk.vhdl +++ b/src/io/uart/uart_bclk.vhdl @@ -1,25 +1,24 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Martin Zabel -- Patrick Lehmann -- --- Module: UART bit clock / baud rate generator +-- Entity: UART bit clock / baud rate generator -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- --- old comments: --- UART BAUD rate generator --- bclk_r = bit clock is rising --- bclk_x8_r = bit clock times 8 is rising +-- old comments: +-- :abbr:`UART (Universal Asynchronous Receiver Transmitter)` BAUD rate generator +-- bclk_r = bit clock is rising +-- bclk_x8_r = bit clock times 8 is rising -- -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2008-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -34,7 +33,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.std_logic_1164.all; @@ -63,10 +62,10 @@ end entity; architecture rtl of uart_bclk is - constant UART_OVERSAMPLING_RATE : POSITIVE := 8; + constant UART_OVERSAMPLING_RATE : positive := 8; constant TIME_UNIT_INTERVAL : T_TIME := 1.0 / (to_real(BAUDRATE, 1 Bd) * real(UART_OVERSAMPLING_RATE)); - constant BAUDRATE_COUNTER_MAX : POSITIVE := TimingToCycles(TIME_UNIT_INTERVAL, CLOCK_FREQ); - constant BAUDRATE_COUNTER_BITS : POSITIVE := log2ceilnz(BAUDRATE_COUNTER_MAX + 1); + constant BAUDRATE_COUNTER_MAX : positive := TimingToCycles(TIME_UNIT_INTERVAL, CLOCK_FREQ); + constant BAUDRATE_COUNTER_BITS : positive := log2ceilnz(BAUDRATE_COUNTER_MAX + 1); -- registers signal x8_cnt : unsigned(BAUDRATE_COUNTER_BITS - 1 downto 0) := (others => '0'); @@ -76,15 +75,15 @@ architecture rtl of uart_bclk is signal x8_cnt_done : std_logic; signal x1_cnt_done : std_logic; - signal bclk_r : STD_LOGIC := '0'; - signal bclk_x8_r : STD_LOGIC := '0'; + signal bclk_r : std_logic := '0'; + signal bclk_x8_r : std_logic := '0'; begin assert FALSE -- LF works in QuartusII report "uart_bclk:" & LF & " CLOCK_FREQ=" & to_string(CLOCK_FREQ, 3) & LF & " BAUDRATE=" & to_string(BAUDRATE, 3) & LF & - " COUNTER_MAX=" & INTEGER'image(BAUDRATE_COUNTER_MAX) & LF & - " COUNTER_BITS=" & INTEGER'image(BAUDRATE_COUNTER_BITS) + " COUNTER_MAX=" & integer'image(BAUDRATE_COUNTER_MAX) & LF & + " COUNTER_BITS=" & integer'image(BAUDRATE_COUNTER_BITS) severity NOTE; assert io_UART_IsTypicalBaudRate(BAUDRATE) diff --git a/src/io/uart/uart_fifo.files b/src/io/uart/uart_fifo.files index 902ac35d..21d637ad 100644 --- a/src/io/uart/uart_fifo.files +++ b/src/io/uart/uart_fifo.files @@ -7,8 +7,8 @@ # Common PoC packages for configuration, synthesis and simulation include "src/common/common.files" # load common packages -# PoC.misc.sync -include "src/misc/sync/sync_Bits.files" # +include "src/misc/sync/sync_Bits.files" # PoC.misc.sync +include "src/fifo/fifo_cc_got.files" # PoC.fifo.cc_got # PoC.io.uart vhdl poc "src/io/uart/uart.pkg.vhdl" # UART Package diff --git a/src/io/uart/uart_fifo.vhdl b/src/io/uart/uart_fifo.vhdl index 7141894e..48bb44c2 100644 --- a/src/io/uart/uart_fifo.vhdl +++ b/src/io/uart/uart_fifo.vhdl @@ -1,27 +1,26 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Martin Zabel -- Patrick Lehmann -- --- Module: UART Wrapper with Embedded FIFOs and Optional Flow Control +-- Entity: UART Wrapper with Embedded FIFOs and Optional Flow Control -- -- Description: --- ------------------------------------ --- Small FIFOs are included in this module, if larger or asynchronous --- transmit / receive FIFOs are required, then they must be connected --- externally. +-- ------------------------------------- +-- Small :abbr:`FIFO (first-in, first-out)` s are included in this module, if +-- larger or asynchronous transmit / receive FIFOs are required, then they must +-- be connected externally. -- --- old comments: --- UART BAUD rate generator --- bclk = bit clock is rising --- bclk_x8 = bit clock times 8 is rising +-- old comments: +-- :abbr:`UART (Universal Asynchronous Receiver Transmitter)` BAUD rate generator +-- bclk = bit clock is rising +-- bclk_x8 = bit clock times 8 is rising -- -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2008-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -36,7 +35,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; @@ -55,7 +54,7 @@ entity uart_fifo is -- Communication Parameters CLOCK_FREQ : FREQ; BAUDRATE : BAUD; - ADD_INPUT_SYNCHRONIZERS : BOOLEAN := TRUE; + ADD_INPUT_SYNCHRONIZERS : boolean := TRUE; -- Buffer Dimensioning TX_MIN_DEPTH : positive := 16; @@ -75,47 +74,47 @@ entity uart_fifo is Reset : in std_logic; -- FIFO interface - TX_put : in STD_LOGIC; - TX_Data : in STD_LOGIC_VECTOR(7 downto 0); - TX_Full : out STD_LOGIC; - TX_EmptyState : out STD_LOGIC_VECTOR(imax(0, TX_ESTATE_BITS-1) downto 0); - - RX_Valid : out STD_LOGIC; - RX_Data : out STD_LOGIC_VECTOR(7 downto 0); - RX_got : in STD_LOGIC; - RX_FullState : out STD_LOGIC_VECTOR(imax(0, RX_FSTATE_BITS-1) downto 0); + TX_put : in std_logic; + TX_Data : in std_logic_vector(7 downto 0); + TX_Full : out std_logic; + TX_EmptyState : out std_logic_vector(imax(0, TX_ESTATE_BITS-1) downto 0); + + RX_Valid : out std_logic; + RX_Data : out std_logic_vector(7 downto 0); + RX_got : in std_logic; + RX_FullState : out std_logic_vector(imax(0, RX_FSTATE_BITS-1) downto 0); RX_Overflow : out std_logic; -- External pins UART_TX : out std_logic; UART_RX : in std_logic; - UART_RTS : out STD_LOGIC; - UART_CTS : in STD_LOGIC + UART_RTS : out std_logic; + UART_CTS : in std_logic ); end entity; architecture rtl of uart_fifo is - signal FC_TX_Strobe : STD_LOGIC; + signal FC_TX_Strobe : std_logic; signal FC_TX_Data : T_SLV_8; - signal FC_TX_got : STD_LOGIC; - signal FC_RX_put : STD_LOGIC; + signal FC_TX_got : std_logic; + signal FC_RX_put : std_logic; signal FC_RX_Data : T_SLV_8; - signal TXFIFO_Valid : STD_LOGIC; + signal TXFIFO_Valid : std_logic; signal TXFIFO_Data : T_SLV_8; - signal RXFIFO_Full : STD_LOGIC; + signal RXFIFO_Full : std_logic; - signal TXUART_Full : STD_LOGIC; - signal RXUART_Strobe : STD_LOGIC; + signal TXUART_Full : std_logic; + signal RXUART_Strobe : std_logic; signal RXUART_Data : T_SLV_8; - signal BitClock : STD_LOGIC; - signal BitClock_x8 : STD_LOGIC; + signal BitClock : std_logic; + signal BitClock_x8 : std_logic; - signal UART_RX_sync : STD_LOGIC; + signal UART_RX_sync : std_logic; begin assert FALSE report "uart_fifo: BAUDRATE=: " & to_string(BAUDRATE, 3) severity NOTE; @@ -171,7 +170,7 @@ begin fstate_rd => RX_FullState ); - genNOFC : if (FLOWCONTROL = UART_FLOWCONTROL_NONE) generate + genNOFC : if FLOWCONTROL = UART_FLOWCONTROL_NONE generate signal Overflow_r : std_logic := '0'; begin @@ -189,7 +188,7 @@ begin -- =========================================================================== -- Software Flow Control -- =========================================================================== - genSWFC : if (FLOWCONTROL = UART_FLOWCONTROL_XON_XOFF) generate + genSWFC : if FLOWCONTROL = UART_FLOWCONTROL_XON_XOFF generate constant XON : std_logic_vector(7 downto 0) := x"11"; -- ^Q constant XOFF : std_logic_vector(7 downto 0) := x"13"; -- ^S @@ -257,7 +256,7 @@ begin -- =========================================================================== -- Hardware Flow Control -- =========================================================================== - genHWFC1 : if (FLOWCONTROL = UART_FLOWCONTROL_RTS_CTS) generate + genHWFC1 : if FLOWCONTROL = UART_FLOWCONTROL_RTS_CTS generate begin @@ -265,7 +264,7 @@ begin -- =========================================================================== -- Hardware Flow Control -- =========================================================================== - genHWFC2 : if (FLOWCONTROL = UART_FLOWCONTROL_RTR_CTS) generate + genHWFC2 : if FLOWCONTROL = UART_FLOWCONTROL_RTR_CTS generate begin @@ -274,10 +273,10 @@ begin -- =========================================================================== -- BitClock, Transmitter, Receiver -- =========================================================================== - genNoSync : if (ADD_INPUT_SYNCHRONIZERS = FALSE) generate + genNoSync : if not ADD_INPUT_SYNCHRONIZERS generate UART_RX_sync <= UART_RX; end generate; - genSync : if (ADD_INPUT_SYNCHRONIZERS = TRUE) generate + genSync : if ADD_INPUT_SYNCHRONIZERS generate sync_i : entity PoC.sync_Bits port map ( Clock => Clock, -- Clock to be synchronized to diff --git a/src/io/uart/uart_ft245.vhdl b/src/io/uart/uart_ft245.vhdl index eabc1d5e..ff8ef8c4 100644 --- a/src/io/uart/uart_ft245.vhdl +++ b/src/io/uart/uart_ft245.vhdl @@ -1,16 +1,19 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- =========================================================================== --- +-- ============================================================================= -- Authors: Peter Reichel -- Jan Schirok -- Steffen Koehler -- --- Module: UART controller for FTDI FT245M UART-over-USB converter. +-- Entity: UART controller for FTDI FT245M UART-over-USB converter. +-- +-- Description: +-- ------------ +-- .. TODO:: No documentation available. -- -- License: --- =========================================================================== +-- ============================================================================= -- Copyright 2008-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -25,7 +28,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- =========================================================================== +-- ============================================================================= library IEEE; diff --git a/src/io/uart/uart_rx.vhdl b/src/io/uart/uart_rx.vhdl index 25c391ef..51d4ff36 100644 --- a/src/io/uart/uart_rx.vhdl +++ b/src/io/uart/uart_rx.vhdl @@ -1,18 +1,18 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- =========================================================================== +-- ============================================================================= -- Authors: Thomas B. Preusser -- --- Module: uart_rx +-- Entity: Universal Asynchronous Receiver Transmitter (UART) - Receiver -- -- Description: --- ------------ --- UART (RS232) Receiver: 1 Start + 8 Data + 1 Stop +-- ------------------------------------- +-- :abbr:`UART (Universal Asynchronous Receiver Transmitter)` Receiver: +-- 1 Start + 8 Data + 1 Stop -- -- License: --- =========================================================================== +-- ============================================================================= -- Copyright 2008-2016 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -27,7 +27,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- =========================================================================== +-- ============================================================================= library IEEE; use IEEE.std_logic_1164.all; diff --git a/src/io/uart/uart_tx.vhdl b/src/io/uart/uart_tx.vhdl index 4be317a0..1e2a9633 100644 --- a/src/io/uart/uart_tx.vhdl +++ b/src/io/uart/uart_tx.vhdl @@ -1,17 +1,18 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; +-- ============================================================================= +-- Authors: Thomas B. Preusser -- --- =========================================================================== --- Module: +-- Entity: Universal Asynchronous Receiver Transmitter (UART) - Transmitter -- --- Authors: Thomas B. Preusser --- --- Description: UART (RS232) Transmitter: 1 Start + 8 Data + 1 Stop --- ------------ +-- Description: +-- ------------------------------------- +-- :abbr:`UART (Universal Asynchronous Receiver Transmitter)` Transmitter: +-- 1 Start + 8 Data + 1 Stop -- -- License: --- =========================================================================== +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -26,7 +27,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- =========================================================================== +-- ============================================================================= library IEEE; use IEEE.std_logic_1164.all; diff --git a/src/mem/lut/lut_Sine.vhdl b/src/mem/lut/lut_Sine.vhdl index 7b6b1be8..7af50ea5 100644 --- a/src/mem/lut/lut_Sine.vhdl +++ b/src/mem/lut/lut_Sine.vhdl @@ -1,18 +1,17 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: TODO +-- Entity: TODO -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -27,7 +26,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.std_logic_1164.all; @@ -41,29 +40,29 @@ use PoC.strings.all; entity lut_Sine is generic ( - REG_OUTPUT : BOOLEAN := TRUE; - MAX_AMPLITUDE : POSITIVE := 255; - POINTS : POSITIVE := 4096; + REG_OUTPUT : boolean := TRUE; + MAX_AMPLITUDE : positive := 255; + POINTS : positive := 4096; OFFSET_DEG : REAL := 0.0; - QUARTERS : POSITIVE := 4 + QUARTERS : positive := 4 ); port ( - Clock : in STD_LOGIC; - Input : in STD_LOGIC_VECTOR(log2ceilnz(POINTS) - 1 downto 0); - Output : out STD_LOGIC_VECTOR(log2ceilnz(MAX_AMPLITUDE + ((QUARTERS - 1) / 2)) downto 0) + Clock : in std_logic; + Input : in std_logic_vector(log2ceilnz(POINTS) - 1 downto 0); + Output : out std_logic_vector(log2ceilnz(MAX_AMPLITUDE + ((QUARTERS - 1) / 2)) downto 0) ); end entity; architecture rtl of lut_Sine is - signal Output_nxt : STD_LOGIC_VECTOR(Output'range); + signal Output_nxt : std_logic_vector(Output'range); begin -- =========================================================================== -- 1 Qudrant LUT -- =========================================================================== - genQ1 : if (QUARTERS = 1) generate - subtype T_RESULT is NATURAL range 0 to MAX_AMPLITUDE; - type T_LUT is array (NATURAL range <>) of T_RESULT; + genQ1 : if QUARTERS = 1 generate + subtype T_RESULT is natural range 0 to MAX_AMPLITUDE; + type T_LUT is array (natural range <>) of T_RESULT; function generateLUT return T_LUT is variable Result : T_LUT(0 to POINTS - 1) := (others => 0); @@ -88,9 +87,9 @@ begin -- =========================================================================== -- 2 Qudrant LUT -- =========================================================================== - genQ12 : if (QUARTERS = 2) generate - subtype T_RESULT is NATURAL range 0 to MAX_AMPLITUDE; - type T_LUT is array (NATURAL range <>) of T_RESULT; + genQ12 : if QUARTERS = 2 generate + subtype T_RESULT is natural range 0 to MAX_AMPLITUDE; + type T_LUT is array (natural range <>) of T_RESULT; function generateLUT return T_LUT is variable Result : T_LUT(0 to POINTS - 1) := (others => 0); @@ -115,15 +114,15 @@ begin -- =========================================================================== -- 3 Qudrant LUT -> ERROR -- =========================================================================== - genQ13 : if (QUARTERS = 3) generate + genQ13 : if QUARTERS = 3 generate assert false report "QUARTERS=3 is not supported." severity FAILURE; end generate; -- =========================================================================== -- 4 Qudrant LUT -- =========================================================================== - genQ14 : if (QUARTERS = 4) generate - subtype T_RESULT is INTEGER range -MAX_AMPLITUDE to MAX_AMPLITUDE; - type T_LUT is array (NATURAL range <>) of T_RESULT; + genQ14 : if QUARTERS = 4 generate + subtype T_RESULT is integer range -MAX_AMPLITUDE to MAX_AMPLITUDE; + type T_LUT is array (natural range <>) of T_RESULT; function generateLUT return T_LUT is variable Result : T_LUT(0 to POINTS - 1) := (others => 0); @@ -151,15 +150,15 @@ begin -- =========================================================================== -- No output registers -- =========================================================================== - genNoReg : if (REG_OUTPUT = FALSE) generate + genNoReg : if not REG_OUTPUT generate begin Output <= Output_nxt; end generate; -- =========================================================================== -- Output registers -- =========================================================================== - genReg : if (REG_OUTPUT = TRUE) generate - signal Output_d : STD_LOGIC_VECTOR(Output'range) := (others => '0'); + genReg : if REG_OUTPUT generate + signal Output_d : std_logic_vector(Output'range) := (others => '0'); begin Output_d <= Output_nxt when rising_edge(Clock); diff --git a/src/mem/mem.pkg.vhdl b/src/mem/mem.pkg.vhdl index 489f5410..54a329fd 100644 --- a/src/mem/mem.pkg.vhdl +++ b/src/mem/mem.pkg.vhdl @@ -1,8 +1,7 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Martin Zabel -- Patrick Lehmann -- @@ -10,13 +9,13 @@ -- associated to the PoC.mem.ocram namespace -- -- Description: --- ------------------------------------ +-- ------------------------------------- -- On-Chip RAMs (Random-Access-Memory/Read-Write-Memory - RWM) for FPGAs. -- -- A detailed documentation is included in each module. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2008-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -31,7 +30,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library STD; use STD.TextIO.all; @@ -60,12 +59,12 @@ package mem is MEM_CONTENT_HEX ); - function mem_FileExtension(Filename : STRING) return STRING; + function mem_FileExtension(Filename : string) return string; impure function mem_ReadMemoryFile( FileName : string; - MemoryLines : POSITIVE; - BitsPerMemoryLine : POSITIVE; + MemoryLines : positive; + BitsPerMemoryLine : positive; FORMAT : T_MEM_FILEFORMAT; CONTENT : T_MEM_CONTENT := MEM_CONTENT_HEX ) return T_SLM; @@ -73,7 +72,7 @@ end package; package body mem is - function mem_FileExtension(FileName : STRING) return STRING is + function mem_FileExtension(FileName : string) return string is begin for i in FileName'high downto FileName'low loop if (FileName(i) = '.') then @@ -83,24 +82,24 @@ package body mem is return ""; end function; - procedure ReadHex(L : inout LINE; Value : out STD_LOGIC_VECTOR; Good : out BOOLEAN) is - variable ok : BOOLEAN; - variable Char : CHARACTER; + procedure ReadHex(L : inout LINE; Value : out std_logic_vector; Good : out boolean) is + variable ok : boolean; + variable Char : character; variable Digit : T_DIGIT_HEX; - constant DigitCount : POSITIVE := div_ceil(Value'length, 4); - variable slv : STD_LOGIC_VECTOR((DigitCount * 4) - 1 downto 0); - variable Swapped : STD_LOGIC_VECTOR((DigitCount * 4) - 1 downto 0); + constant DigitCount : positive := div_ceil(Value'length, 4); + variable slv : std_logic_vector((DigitCount * 4) - 1 downto 0); + variable Swapped : std_logic_vector((DigitCount * 4) - 1 downto 0); begin Good := TRUE; for i in 0 to DigitCount - 1 loop read(L, Char, ok); - if (ok = FALSE) then + if not ok then Swapped := swap(slv, 4); Value := Swapped(Value'length - 1 downto 0); return; end if; Digit := to_digit_hex(Char); - if (Digit = -1) then + if Digit = -1 then Good := FALSE; return; end if; @@ -113,20 +112,20 @@ package body mem is -- Reads a memory file and returns a 2D std_logic matrix impure function mem_ReadMemoryFile( FileName : string; - MemoryLines : POSITIVE; - BitsPerMemoryLine : POSITIVE; + MemoryLines : positive; + BitsPerMemoryLine : positive; FORMAT : T_MEM_FILEFORMAT; CONTENT : T_MEM_CONTENT := MEM_CONTENT_HEX ) return T_SLM is file FileHandle : TEXT open READ_MODE is FileName; variable CurrentLine : LINE; - variable Good : BOOLEAN; - variable TempWord : STD_LOGIC_VECTOR((div_ceil(BitsPerMemoryLine, 4) * 4) - 1 downto 0); + variable Good : boolean; + variable TempWord : std_logic_vector((div_ceil(BitsPerMemoryLine, 4) * 4) - 1 downto 0); variable Result : T_SLM(MemoryLines - 1 downto 0, BitsPerMemoryLine - 1 downto 0); begin Result := (others => (others => ite(SIMULATION, 'U', '0'))); - if (FORMAT = MEM_FILEFORMAT_XILINX_MEM) then + if FORMAT = MEM_FILEFORMAT_XILINX_MEM then -- discard the first line of a mem file readline(FileHandle, CurrentLine); end if; @@ -137,7 +136,7 @@ package body mem is readline(FileHandle, CurrentLine); -- report CurrentLine.all severity NOTE; ReadHex(CurrentLine, TempWord, Good); - if (Good = FALSE) then + if not Good then report "Error while reading memory file '" & FileName & "'." severity FAILURE; return Result; end if; diff --git a/src/mem/ocram/altera/ocram_esdp_altera.vhdl b/src/mem/ocram/altera/ocram_esdp_altera.vhdl deleted file mode 100644 index f5d22d0d..00000000 --- a/src/mem/ocram/altera/ocram_esdp_altera.vhdl +++ /dev/null @@ -1,171 +0,0 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ --- Authors: Martin Zabel --- Patrick Lehmann --- --- Module: Instantiate enhanced simple dual-port memory on Altera --- FPGAs. --- --- Description: --- ------------------------------------ --- Quartus synthesis does not infer this RAM type correctly. --- Instead, altsyncram is instantiated directly. --- --- For further documentation see module "ocram_esdp" --- (src/mem/ocram/ocram_esdp.vhdl). --- --- License: --- ============================================================================ --- Copyright 2008-2015 Technische Universitaet Dresden - Germany --- Chair for VLSI-Design, Diagnostics and Architecture --- --- Licensed under the Apache License, Version 2.0 (the "License"); --- you may not use this file except in compliance with the License. --- You may obtain a copy of the License at --- --- http://www.apache.org/licenses/LICENSE-2.0 --- --- Unless required by applicable law or agreed to in writing, software --- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --- See the License for the specific language governing permissions and --- limitations under the License. --- ============================================================================ - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -library altera_mf; -use altera_mf.all; - -library PoC; -use PoC.utils.all; -use PoC.strings.all; - - -entity ocram_esdp_altera is - generic ( - A_BITS : positive; - D_BITS : positive; - FILENAME : STRING := "" - ); - port ( - clk1 : in std_logic; - clk2 : in std_logic; - ce1 : in std_logic; - ce2 : in std_logic; - we1 : in std_logic; - a1 : in unsigned(A_BITS-1 downto 0); - a2 : in unsigned(A_BITS-1 downto 0); - d1 : in std_logic_vector(D_BITS-1 downto 0); - q1 : out std_logic_vector(D_BITS-1 downto 0); - q2 : out std_logic_vector(D_BITS-1 downto 0) - ); -end ocram_esdp_altera; - - -architecture rtl of ocram_esdp_altera is - component altsyncram - generic ( - address_aclr_a : STRING; - address_aclr_b : STRING; - address_reg_b : STRING; - indata_aclr_a : STRING; - indata_aclr_b : STRING; - indata_reg_b : STRING; - init_file : STRING; - intended_device_family : STRING; - lpm_type : STRING; - numwords_a : NATURAL; - numwords_b : NATURAL; - operation_mode : STRING; - outdata_aclr_a : STRING; - outdata_aclr_b : STRING; - outdata_reg_a : STRING; - outdata_reg_b : STRING; - power_up_uninitialized : STRING; - widthad_a : NATURAL; - widthad_b : NATURAL; - width_a : NATURAL; - width_b : NATURAL; - width_byteena_a : NATURAL; - width_byteena_b : NATURAL; - wrcontrol_aclr_a : STRING; - wrcontrol_aclr_b : STRING; - wrcontrol_wraddress_reg_b : STRING - ); - port ( - clocken0 : in STD_LOGIC; - clocken1 : in STD_LOGIC; - wren_a : in STD_LOGIC; - clock0 : in STD_LOGIC; - wren_b : in STD_LOGIC; - clock1 : in STD_LOGIC; - address_a : in STD_LOGIC_VECTOR (widthad_a-1 downto 0); - address_b : in STD_LOGIC_VECTOR (widthad_b-1 downto 0); - q_a : out STD_LOGIC_VECTOR (width_a-1 downto 0); - q_b : out STD_LOGIC_VECTOR (width_b-1 downto 0); - data_a : in STD_LOGIC_VECTOR (width_a-1 downto 0); - data_b : in STD_LOGIC_VECTOR (width_b-1 downto 0) - ); - end component; - - constant DEPTH : positive := 2**A_BITS; - constant INIT_FILE : STRING := ite((str_length(FILENAME) = 0), "UNUSED", FILENAME); - - signal a1_sl : std_logic_vector(A_BITS-1 downto 0); - signal a2_sl : std_logic_vector(A_BITS-1 downto 0); - -begin - - a1_sl <= std_logic_vector(a1); - a2_sl <= std_logic_vector(a2); - - mem : altsyncram - generic map ( - address_aclr_a => "NONE", - address_aclr_b => "NONE", - address_reg_b => "CLOCK1", - indata_aclr_a => "NONE", - indata_aclr_b => "NONE", - indata_reg_b => "CLOCK1", - init_file => INIT_FILE, - intended_device_family => "Stratix", - lpm_type => "altsyncram", - numwords_a => DEPTH, - numwords_b => DEPTH, - operation_mode => "BIDIR_DUAL_PORT", - outdata_aclr_a => "NONE", - outdata_aclr_b => "NONE", - outdata_reg_a => "UNREGISTERED", - outdata_reg_b => "UNREGISTERED", - power_up_uninitialized => "FALSE", - widthad_a => A_BITS, - widthad_b => A_BITS, - width_a => D_BITS, - width_b => D_BITS, - width_byteena_a => 1, - width_byteena_b => 1, - wrcontrol_aclr_a => "NONE", - wrcontrol_aclr_b => "NONE", - wrcontrol_wraddress_reg_b => "CLOCK1" - ) - port map ( - clock0 => clk1, - clock1 => clk2, - clocken0 => ce1, - clocken1 => ce2, - wren_a => we1, - wren_b => '0', - address_a => a1_sl, - address_b => a2_sl, - data_a => d1, - data_b => (others => '0'), - q_a => q1, - q_b => q2 - ); -end rtl; diff --git a/src/mem/ocram/altera/ocram_sp_altera.vhdl b/src/mem/ocram/altera/ocram_sp_altera.vhdl index 648aab5b..5d66f7f1 100644 --- a/src/mem/ocram/altera/ocram_sp_altera.vhdl +++ b/src/mem/ocram/altera/ocram_sp_altera.vhdl @@ -1,15 +1,14 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Martin Zabel -- Patrick Lehmann -- --- Module: Instantiate single-port memory on Altera FPGAs. +-- Entity: Instantiate single-port memory on Altera FPGAs. -- -- Description: --- ------------------------------------ +-- ------------------------------------- -- Quartus synthesis does not infer this RAM type correctly. -- Instead, altsyncram is instantiated directly. -- @@ -17,7 +16,7 @@ -- (src/mem/ocram/ocram_sp.vhdl). -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2008-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -32,7 +31,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.std_logic_1164.all; @@ -42,6 +41,7 @@ library altera_mf; use altera_mf.all; library PoC; +use PoC.config.all; use PoC.utils.all; use PoC.strings.all; @@ -50,7 +50,7 @@ entity ocram_sp_altera is generic ( A_BITS : positive; D_BITS : positive; - FILENAME : STRING := "" + FILENAME : string := "" ); port ( clk : in std_logic; @@ -66,34 +66,34 @@ end entity; architecture rtl of ocram_sp_altera is component altsyncram generic ( - address_aclr_a : STRING; - indata_aclr_a : STRING; - init_file : STRING; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - numwords_a : NATURAL; - operation_mode : STRING; - outdata_aclr_a : STRING; - outdata_reg_a : STRING; - power_up_uninitialized : STRING; - widthad_a : NATURAL; - width_a : NATURAL; - width_byteena_a : NATURAL; - wrcontrol_aclr_a : STRING + address_aclr_a : string; + indata_aclr_a : string; + init_file : string; + intended_device_family : string; + lpm_hint : string; + lpm_type : string; + numwords_a : natural; + operation_mode : string; + outdata_aclr_a : string; + outdata_reg_a : string; + power_up_uninitialized : string; + widthad_a : natural; + width_a : natural; + width_byteena_a : natural; + wrcontrol_aclr_a : string ); port ( - clocken0 : in STD_LOGIC; - wren_a : in STD_LOGIC; - clock0 : in STD_LOGIC; - address_a : in STD_LOGIC_VECTOR(widthad_a-1 downto 0); - q_a : out STD_LOGIC_VECTOR(width_a-1 downto 0); - data_a : in STD_LOGIC_VECTOR(width_a-1 downto 0) + clocken0 : in std_logic; + wren_a : in std_logic; + clock0 : in std_logic; + address_a : in std_logic_vector(widthad_a-1 downto 0); + q_a : out std_logic_vector(width_a-1 downto 0); + data_a : in std_logic_vector(width_a-1 downto 0) ); end component; constant DEPTH : positive := 2**A_BITS; - constant INIT_FILE : STRING := ite((str_length(FILENAME) = 0), "UNUSED", FILENAME); + constant INIT_FILE : string := ite((str_length(FILENAME) = 0), "UNUSED", FILENAME); signal a_sl : std_logic_vector(A_BITS-1 downto 0); @@ -105,7 +105,7 @@ begin address_aclr_a => "NONE", indata_aclr_a => "NONE", init_file => INIT_FILE, - intended_device_family => "Stratix", + intended_device_family => getAlteraDeviceName(DEVICE), lpm_hint => "ENABLE_RUNTIME_MOD = NO", lpm_type => "altsyncram", numwords_a => DEPTH, diff --git a/src/mem/ocram/altera/ocram_tdp_altera.vhdl b/src/mem/ocram/altera/ocram_tdp_altera.vhdl index 45add818..c9cb2532 100644 --- a/src/mem/ocram/altera/ocram_tdp_altera.vhdl +++ b/src/mem/ocram/altera/ocram_tdp_altera.vhdl @@ -1,15 +1,14 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Martin Zabel -- Patrick Lehmann -- --- Module: Instantiate true dual-port memory on Altera FPGAs. +-- Entity: Instantiate true dual-port memory on Altera FPGAs. -- -- Description: --- ------------------------------------ +-- ------------------------------------- -- Quartus synthesis does not infer this RAM type correctly. -- Instead, altsyncram is instantiated directly. -- @@ -17,7 +16,7 @@ -- (src/mem/ocram/ocram_tdp.vhdl). -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2008-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -32,7 +31,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.std_logic_1164.all; @@ -42,6 +41,7 @@ library altera_mf; use altera_mf.all; library PoC; +use PoC.config.all; use PoC.utils.all; use PoC.strings.all; @@ -50,7 +50,7 @@ entity ocram_tdp_altera is generic ( A_BITS : positive; D_BITS : positive; - FILENAME : STRING := "" + FILENAME : string := "" ); port ( clk1 : in std_logic; @@ -72,50 +72,50 @@ end ocram_tdp_altera; architecture rtl of ocram_tdp_altera is component altsyncram generic ( - address_aclr_a : STRING; - address_aclr_b : STRING; - address_reg_b : STRING; - indata_aclr_a : STRING; - indata_aclr_b : STRING; - indata_reg_b : STRING; - init_file : STRING; - intended_device_family : STRING; - lpm_type : STRING; - numwords_a : NATURAL; - numwords_b : NATURAL; - operation_mode : STRING; - outdata_aclr_a : STRING; - outdata_aclr_b : STRING; - outdata_reg_a : STRING; - outdata_reg_b : STRING; - power_up_uninitialized : STRING; - widthad_a : NATURAL; - widthad_b : NATURAL; - width_a : NATURAL; - width_b : NATURAL; - width_byteena_a : NATURAL; - width_byteena_b : NATURAL; - wrcontrol_aclr_a : STRING; - wrcontrol_aclr_b : STRING; - wrcontrol_wraddress_reg_b : STRING); + address_aclr_a : string; + address_aclr_b : string; + address_reg_b : string; + indata_aclr_a : string; + indata_aclr_b : string; + indata_reg_b : string; + init_file : string; + intended_device_family : string; + lpm_type : string; + numwords_a : natural; + numwords_b : natural; + operation_mode : string; + outdata_aclr_a : string; + outdata_aclr_b : string; + outdata_reg_a : string; + outdata_reg_b : string; + power_up_uninitialized : string; + widthad_a : natural; + widthad_b : natural; + width_a : natural; + width_b : natural; + width_byteena_a : natural; + width_byteena_b : natural; + wrcontrol_aclr_a : string; + wrcontrol_aclr_b : string; + wrcontrol_wraddress_reg_b : string); port ( - clocken0 : IN STD_LOGIC; - clocken1 : IN STD_LOGIC; - wren_a : IN STD_LOGIC; - clock0 : IN STD_LOGIC; - wren_b : IN STD_LOGIC; - clock1 : IN STD_LOGIC; - address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - address_b : IN STD_LOGIC_VECTOR (widthad_b-1 DOWNTO 0); - q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); - q_b : OUT STD_LOGIC_VECTOR (width_b-1 DOWNTO 0); - data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); - data_b : IN STD_LOGIC_VECTOR (width_b-1 DOWNTO 0) + clocken0 : in std_logic; + clocken1 : in std_logic; + wren_a : in std_logic; + clock0 : in std_logic; + wren_b : in std_logic; + clock1 : in std_logic; + address_a : in std_logic_vector (widthad_a-1 downto 0); + address_b : in std_logic_vector (widthad_b-1 downto 0); + q_a : out std_logic_vector (width_a-1 downto 0); + q_b : out std_logic_vector (width_b-1 downto 0); + data_a : in std_logic_vector (width_a-1 downto 0); + data_b : in std_logic_vector (width_b-1 downto 0) ); end component; constant DEPTH : positive := 2**A_BITS; - constant INIT_FILE : STRING := ite((str_length(FILENAME) = 0), "UNUSED", FILENAME); + constant INIT_FILE : string := ite((str_length(FILENAME) = 0), "UNUSED", FILENAME); signal a1_sl : std_logic_vector(A_BITS-1 downto 0); signal a2_sl : std_logic_vector(A_BITS-1 downto 0); @@ -134,7 +134,7 @@ begin indata_aclr_b => "NONE", indata_reg_b => "CLOCK1", init_file => INIT_FILE, - intended_device_family => "Stratix", + intended_device_family => getAlteraDeviceName(DEVICE), lpm_type => "altsyncram", numwords_a => DEPTH, numwords_b => DEPTH, diff --git a/src/mem/ocram/ocram.pkg.vhdl b/src/mem/ocram/ocram.pkg.vhdl index ee7ff2bd..11776b08 100644 --- a/src/mem/ocram/ocram.pkg.vhdl +++ b/src/mem/ocram/ocram.pkg.vhdl @@ -1,8 +1,7 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Martin Zabel -- Patrick Lehmann -- @@ -10,13 +9,13 @@ -- associated to the PoC.mem.ocram namespace -- -- Description: --- ------------------------------------ +-- ------------------------------------- -- On-Chip RAMs (Random-Access-Memory/Read-Write-Memory - RWM) for FPGAs. -- -- A detailed documentation is included in each module. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2008-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -31,7 +30,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.std_logic_1164.all; @@ -44,7 +43,7 @@ package ocram is generic ( A_BITS : positive; D_BITS : positive; - FILENAME : STRING := "" + FILENAME : string := "" ); port ( clk : in std_logic; @@ -60,7 +59,7 @@ package ocram is generic ( A_BITS : positive; D_BITS : positive; - FILENAME : STRING := "" + FILENAME : string := "" ); port ( rclk : in std_logic; @@ -79,7 +78,7 @@ package ocram is generic ( A_BITS : positive; D_BITS : positive; - FILENAME : STRING := "" + FILENAME : string := "" ); port ( clk1 : in std_logic; @@ -99,7 +98,7 @@ package ocram is generic ( A_BITS : positive; D_BITS : positive; - FILENAME : STRING := "" + FILENAME : string := "" ); port ( clk1 : in std_logic; diff --git a/src/mem/ocram/ocram_esdp.files b/src/mem/ocram/ocram_esdp.files index 336ae854..fbfb3a57 100644 --- a/src/mem/ocram/ocram_esdp.files +++ b/src/mem/ocram/ocram_esdp.files @@ -13,6 +13,8 @@ vhdl poc "src/mem/mem.pkg.vhdl" # Memory package # PoC.mem.ocram vhdl poc "src/mem/ocram/ocram.pkg.vhdl" # On-Chip-RAM if (DeviceVendor = "Altera") then - vhdl poc "src/mem/ocram/altera/ocram_esdp_altera.vhdl" # Altera specific extended simple dual-port RAM + include "lib/Altera.files" + vhdl poc "src/mem/ocram/altera/ocram_tdp_altera.vhdl" # Altera specific extended simple dual-port RAM end if +vhdl poc "src/mem/ocram/ocram_tdp.vhdl" # True dual-port RAM vhdl poc "src/mem/ocram/ocram_esdp.vhdl" # Extended simple dual-port RAM diff --git a/src/mem/ocram/ocram_esdp.vhdl b/src/mem/ocram/ocram_esdp.vhdl index 70a5780b..3f80baf2 100644 --- a/src/mem/ocram/ocram_esdp.vhdl +++ b/src/mem/ocram/ocram_esdp.vhdl @@ -1,50 +1,72 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Martin Zabel -- Patrick Lehmann -- --- Module: Enhanced simple dual-port memory. +-- Entity: Enhanced simple dual-port memory. -- -- Description: --- ------------------------------------ +-- ------------------------------------- -- Inferring / instantiating enhanced simple dual-port memory, with: -- -- * dual clock, clock enable, -- * 1 read/write port (1st port) plus 1 read port (2nd port). -- +-- .. NOTE:: +-- This component is **deprecated**. +-- Please use :doc:`PoC.mem.ocram.tdp ` for new designs. +-- This component has been provided because older FPGA compilers where not +-- able to infer true dual-port memory from an RTL description. +-- +-- Command truth table for port 1: +-- +-- === === ================ +-- ce1 we1 Command +-- === === ================ +-- 0 X No operation +-- 1 0 Read from memory +-- 1 1 Write to memory +-- === === ================ +-- +-- Command truth table for port 2: +-- +-- === ================ +-- ce2 Command +-- === ================ +-- 0 No operation +-- 1 Read from memory +-- === ================ +-- +-- Both reading and writing are synchronous to the rising-edge of the clock. +-- Thus, when reading, the memory data will be outputted after the +-- clock edge, i.e, in the following clock cycle. +-- -- The generalized behavior across Altera and Xilinx FPGAs since -- Stratix/Cyclone and Spartan-3/Virtex-5, respectively, is as follows: -- --- * Same-Port Read-During Write: --- At rising edge of "clk1", data "d1" written to port 1 (ce1 and we1 = '1') --- is directly passed to the output "q1". This is also known as write-first --- mode or read-through write behavior. --- --- * Mixed-Port Read-During Write: --- Here, the Altera M512/M4K TriMatrix memory (as found e.g. in Stratix --- and Stratix II FPGAs) defines the minimum time after which the written data --- at port 1 can be read-out at port 2 again. As stated in the Stratix --- Handbook, Volume 2, page 2-13, data is actually written with the falling --- (instead of the rising) edge of the clock into the memory array. The write --- itself takes the write-cycle time which is less or equal to the minimum --- clock-period time. After this, the data can be read-out at the other port. --- Consequently, data "d1" written at the rising-edge of "clk1" at address --- "a1" can be read-out at the 2nd port from the same address with the --- 2nd rising-edge of "clk2" following the falling-edge of "clk1". --- If the rising-edge of "clk2" coincides with the falling-edge of "clk1" --- (e.g. same clock signal), then it is counted as the 1st rising-edge of --- "clk2" in this timing. --- --- WARNING: The simulated behavior on RT-level is not correct. --- --- TODO: add timing diagram --- TODO: implement correct behavior for RT-level simulation +-- Same-Port Read-During-Write +-- When writing data through port 1, the read output of the same port +-- (``q1``) will output the new data (``d1``, in the following clock cycle) +-- which is aka. "write-first behavior". This behavior also applies to Altera +-- M20K memory blocks as described in the Altera: "Stratix 5 Device Handbook" +-- (S5-5V1). The documentation in the Altera: "Embedded Memory User Guide" +-- (UG-01068) is wrong. +-- +-- Mixed-Port Read-During-Write +-- When reading at the write address, the read value will be unknown which is +-- aka. "don't care behavior". This applies to all reads (at the same +-- address) which are issued during the write-cycle time, which starts at the +-- rising-edge of the write clock (``clk1``) and (in the worst case) extends +-- until the next rising-edge of the write clock. +-- +-- .. WARNING:: +-- The simulated behavior on RT-level is too optimistic. When reading +-- at the write address always the new data will be returned. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2008-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -59,7 +81,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library STD; use STD.TextIO.all; @@ -78,21 +100,21 @@ use PoC.mem.all; entity ocram_esdp is generic ( - A_BITS : positive; - D_BITS : positive; - FILENAME : STRING := "" + A_BITS : positive; -- number of address bits + D_BITS : positive; -- number of data bits + FILENAME : string := "" -- file-name for RAM initialization ); port ( - clk1 : in std_logic; - clk2 : in std_logic; - ce1 : in std_logic; - ce2 : in std_logic; - we1 : in std_logic; - a1 : in unsigned(A_BITS-1 downto 0); - a2 : in unsigned(A_BITS-1 downto 0); - d1 : in std_logic_vector(D_BITS-1 downto 0); - q1 : out std_logic_vector(D_BITS-1 downto 0); - q2 : out std_logic_vector(D_BITS-1 downto 0) + clk1 : in std_logic; -- clock for 1st port + clk2 : in std_logic; -- clock for 2nd port + ce1 : in std_logic; -- clock-enable for 1st port + ce2 : in std_logic; -- clock-enable for 2nd port + we1 : in std_logic; -- write-enable for 1st port + a1 : in unsigned(A_BITS-1 downto 0); -- address for 1st port + a2 : in unsigned(A_BITS-1 downto 0); -- address for 2nd port + d1 : in std_logic_vector(D_BITS-1 downto 0); -- write-data for 1st port + q1 : out std_logic_vector(D_BITS-1 downto 0); -- read-data from 1st port + q2 : out std_logic_vector(D_BITS-1 downto 0) -- read-data from 2nd port ); end entity; @@ -101,75 +123,38 @@ architecture rtl of ocram_esdp is constant DEPTH : positive := 2**A_BITS; begin - gInfer : if ((VENDOR = VENDOR_GENERIC) or (VENDOR = VENDOR_LATTICE) or (VENDOR = VENDOR_XILINX)) generate - -- RAM can be inferred correctly - -- XST Advanced HDL Synthesis generates extended simple dual-port - -- memory as expected. - -- RAM can be inferred correctly only for newer FPGAs! - subtype word_t is std_logic_vector(D_BITS - 1 downto 0); - type ram_t is array(0 to DEPTH - 1) of word_t; - - -- Compute the initialization of a RAM array, if specified, from the passed file. - impure function ocram_InitMemory(FilePath : string) return ram_t is - variable Memory : T_SLM(DEPTH - 1 downto 0, word_t'range); - variable res : ram_t; - begin - if (str_length(FilePath) = 0) then - -- shortcut required by Vivado - return (others => (others => ite(SIMULATION, 'U', '0'))); - elsif (mem_FileExtension(FilePath) = "mem") then - Memory := mem_ReadMemoryFile(FilePath, DEPTH, word_t'length, MEM_FILEFORMAT_XILINX_MEM, MEM_CONTENT_HEX); - else - Memory := mem_ReadMemoryFile(FilePath, DEPTH, word_t'length, MEM_FILEFORMAT_INTEL_HEX, MEM_CONTENT_HEX); - end if; + gInfer : if (VENDOR = VENDOR_GENERIC) or (VENDOR = VENDOR_LATTICE) or (VENDOR = VENDOR_XILINX) generate - for i in Memory'range(1) loop - for j in word_t'range loop - res(i)(j) := Memory(i, j); - end loop; - end loop; - return res; - end function; - - signal ram : ram_t := ocram_InitMemory(FILENAME); - signal a1_reg : unsigned(A_BITS-1 downto 0); - signal a2_reg : unsigned(A_BITS-1 downto 0); - - begin - process (clk1) - begin - if rising_edge(clk1) then - if ce1 = '1' then - if we1 = '1' then - ram(to_integer(a1)) <= d1; - end if; - - a1_reg <= a1; - end if; - end if; - end process; - - q1 <= ram(to_integer(a1_reg)); -- gets new data - - process (clk2) - begin -- process - if rising_edge(clk2) then - if ce2 = '1' then - a2_reg <= a2; - end if; - end if; - end process; - - -- read data is unknown, when reading at write address - q2 <= ram(to_integer(a2_reg)); + -- For Xilinx ISE, Xilinx Vivado and Lattice LSE we can reuse the ocram_tdp. + -- + -- **Attention**: This encapsulation is mandatory for Xilinx Vivado, + -- otherwise Vivado synthesizes a lot of LUT-RAM instead of Block-RAM. + ram_tdp: entity poc.ocram_tdp + generic map ( + A_BITS => A_BITS, + D_BITS => D_BITS, + FILENAME => FILENAME) + port map ( + clk1 => clk1, + clk2 => clk2, + ce1 => ce1, + ce2 => ce2, + we1 => we1, + we2 => '0', + a1 => a1, + a2 => a2, + d1 => d1, + d2 => (others => '0'), + q1 => q1, + q2 => q2); end generate gInfer; gAltera: if VENDOR = VENDOR_ALTERA generate - component ocram_esdp_altera + component ocram_tdp_altera generic ( A_BITS : positive; D_BITS : positive; - FILENAME : STRING := "" + FILENAME : string := "" ); port ( clk1 : in std_logic; @@ -177,9 +162,11 @@ begin ce1 : in std_logic; ce2 : in std_logic; we1 : in std_logic; + we2 : in std_logic; a1 : in unsigned(A_BITS-1 downto 0); a2 : in unsigned(A_BITS-1 downto 0); d1 : in std_logic_vector(D_BITS-1 downto 0); + d2 : in std_logic_vector(D_BITS-1 downto 0); q1 : out std_logic_vector(D_BITS-1 downto 0); q2 : out std_logic_vector(D_BITS-1 downto 0) ); @@ -188,7 +175,7 @@ begin -- Direct instantiation of altsyncram (including component -- declaration above) is not sufficient for ModelSim. -- That requires also usage of altera_mf library. - i: ocram_esdp_altera + ram_tdp: ocram_tdp_altera generic map ( A_BITS => A_BITS, D_BITS => D_BITS, @@ -200,9 +187,11 @@ begin ce1 => ce1, ce2 => ce2, we1 => we1, + we2 => '0', a1 => a1, a2 => a2, d1 => d1, + d2 => (others => '0'), q1 => q1, q2 => q2 ); diff --git a/src/mem/ocram/ocram_sdp.vhdl b/src/mem/ocram/ocram_sdp.vhdl index 7e74f7ea..f06913a2 100644 --- a/src/mem/ocram/ocram_sdp.vhdl +++ b/src/mem/ocram/ocram_sdp.vhdl @@ -1,44 +1,39 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Martin Zabel -- Thomas B. Preusser -- Patrick Lehmann -- --- Module: Simple dual-port memory. +-- Entity: Simple dual-port memory. -- -- Description: --- ------------------------------------ +-- ------------------------------------- -- Inferring / instantiating simple dual-port memory, with: --- * dual clock, clock enable, --- * 1 read port plus 1 write port. +-- +-- * dual clock, clock enable, +-- * 1 read port plus 1 write port. -- -- The generalized behavior across Altera and Xilinx FPGAs since -- Stratix/Cyclone and Spartan-3/Virtex-5, respectively, is as follows: -- --- The Altera M512/M4K TriMatrix memory (as found e.g. in Stratix and --- Stratix II FPGAs) defines the minimum time after which the written data at --- the write port can be read-out at read port again. As stated in the Stratix --- Handbook, Volume 2, page 2-13, data is actually written with the falling --- (instead of the rising) edge of the clock into the memory array. The write --- itself takes the write-cycle time which is less or equal to the minimum --- clock-period time. After this, the data can be read-out at the other port. --- Consequently, data "d" written at the rising-edge of "wclk" at address --- "wa" can be read-out at the read port from the same address with the --- 2nd rising-edge of "rclk" following the falling-edge of "wclk". --- If the rising-edge of "rclk" coincides with the falling-edge of "wclk" --- (e.g. same clock signal), then it is counted as the 1st rising-edge of --- "rclk" in this timing. +-- Mixed-Port Read-During-Write +-- When reading at the write address, the read value will be unknown which is +-- aka. "don't care behavior". This applies to all reads (at the same +-- address) which are issued during the write-cycle time, which starts at the +-- rising-edge of the write clock and (in the worst case) extends until the +-- next rising-edge of the write clock. -- --- WARNING: The simulated behavior on RT-level is not correct. +-- .. WARNING:: +-- The simulated behavior on RT-level is too optimistic. The +-- mixed-port read-during-write behavior is only valid if the read and write +-- clock are in phase. Otherwise, simulation will always show known data. -- --- TODO: add timing diagram --- TODO: implement correct behavior for RT-level simulation +-- .. TODO:: Implement correct behavior for RT-level simulation. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2008-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -53,7 +48,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.std_logic_1164.all; @@ -69,9 +64,9 @@ use PoC.mem.all; entity ocram_sdp is generic ( - A_BITS : positive; - D_BITS : positive; - FILENAME : STRING := "" + A_BITS : positive; -- number of address bits + D_BITS : positive; -- number of data bits + FILENAME : string := "" -- file-name for RAM initialization ); port ( rclk : in std_logic; -- read clock @@ -92,7 +87,7 @@ architecture rtl of ocram_sdp is begin - gInfer : if ((VENDOR = VENDOR_ALTERA) or (VENDOR = VENDOR_GENERIC) or (VENDOR = VENDOR_LATTICE) or (VENDOR = VENDOR_XILINX)) generate + gInfer : if (VENDOR = VENDOR_ALTERA) or (VENDOR = VENDOR_GENERIC) or (VENDOR = VENDOR_LATTICE) or (VENDOR = VENDOR_XILINX) generate -- RAM can be inferred correctly -- Xilinx notes: -- WRITE_MODE is set to WRITE_FIRST, but this also means that read data @@ -114,10 +109,10 @@ begin variable Memory : T_SLM(DEPTH - 1 downto 0, word_t'range); variable res : ram_t; begin - if (str_length(FilePath) = 0) then + if str_length(FilePath) = 0 then -- shortcut required by Vivado return (others => (others => ite(SIMULATION, 'U', '0'))); - elsif (mem_FileExtension(FilePath) = "mem") then + elsif mem_FileExtension(FilePath) = "mem" then Memory := mem_ReadMemoryFile(FilePath, DEPTH, word_t'length, MEM_FILEFORMAT_XILINX_MEM, MEM_CONTENT_HEX); else Memory := mem_ReadMemoryFile(FilePath, DEPTH, word_t'length, MEM_FILEFORMAT_INTEL_HEX, MEM_CONTENT_HEX); diff --git a/src/mem/ocram/ocram_sp.files b/src/mem/ocram/ocram_sp.files index 1d510bdd..d7cd9dc1 100644 --- a/src/mem/ocram/ocram_sp.files +++ b/src/mem/ocram/ocram_sp.files @@ -13,6 +13,7 @@ vhdl poc "src/mem/mem.pkg.vhdl" # Memory package # PoC.mem.ocram vhdl poc "src/mem/ocram/ocram.pkg.vhdl" # On-Chip-RAM if (DeviceVendor = "Altera") then + include "lib/Altera.files" vhdl poc "src/mem/ocram/altera/ocram_sp_altera.vhdl" # Altera specific single-port RAM end if vhdl poc "src/mem/ocram/ocram_sp.vhdl" # Single-port RAM diff --git a/src/mem/ocram/ocram_sp.vhdl b/src/mem/ocram/ocram_sp.vhdl index ba77b7bd..fecbd731 100644 --- a/src/mem/ocram/ocram_sp.vhdl +++ b/src/mem/ocram/ocram_sp.vhdl @@ -1,26 +1,41 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Martin Zabel -- Patrick Lehmann -- --- Module: Single-port memory. +-- Entity: Single-port memory. -- -- Description: --- ------------------------------------ --- Inferring / instantiating single-port RAM +-- ------------------------------------- +-- Inferring / instantiating single port memory, with: +-- +-- * single clock, clock enable, +-- * 1 read/write port. +-- +-- Command Truth Table: +-- +-- == == ================ +-- ce we Command +-- == == ================ +-- 0 X No operation +-- 1 0 Read from memory +-- 1 1 Write to memory +-- == == ================ -- --- - single clock, clock enable --- - 1 read/write port +-- Both reading and writing are synchronous to the rising-edge of the clock. +-- Thus, when reading, the memory data will be outputted after the +-- clock edge, i.e, in the following clock cycle. -- --- Written data is passed through the memory and output again as read-data 'q'. --- This is the normal behaviour of a single-port RAM and also known as --- write-first mode or read-through-write behaviour. +-- When writing data, the read output will output the new data (in the +-- following clock cycle) which is aka. "write-first behavior". This behavior +-- also applies to Altera M20K memory blocks as described in the Altera: +-- "Stratix 5 Device Handbook" (S5-5V1). The documentation in the Altera: +-- "Embedded Memory User Guide" (UG-01068) is wrong. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2008-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -35,7 +50,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; @@ -52,17 +67,17 @@ use PoC.mem.all; entity ocram_sp is generic ( - A_BITS : positive; - D_BITS : positive; - FILENAME : STRING := "" + A_BITS : positive; -- number of address bits + D_BITS : positive; -- number of data bits + FILENAME : string := "" -- file-name for RAM initialization ); port ( - clk : in std_logic; - ce : in std_logic; - we : in std_logic; - a : in unsigned(A_BITS-1 downto 0); - d : in std_logic_vector(D_BITS-1 downto 0); - q : out std_logic_vector(D_BITS-1 downto 0) + clk : in std_logic; -- clock + ce : in std_logic; -- clock enable + we : in std_logic; -- write enable + a : in unsigned(A_BITS-1 downto 0); -- address + d : in std_logic_vector(D_BITS-1 downto 0); -- write data + q : out std_logic_vector(D_BITS-1 downto 0) -- read output ); end entity; @@ -72,7 +87,7 @@ architecture rtl of ocram_sp is begin - gInfer : if ((VENDOR = VENDOR_GENERIC) or (VENDOR = VENDOR_LATTICE) or (VENDOR = VENDOR_XILINX)) generate + gInfer : if (VENDOR = VENDOR_GENERIC) or (VENDOR = VENDOR_LATTICE) or (VENDOR = VENDOR_XILINX) generate -- RAM can be inferred correctly -- XST Advanced HDL Synthesis generates single-port memory as expected. subtype word_t is std_logic_vector(D_BITS - 1 downto 0); @@ -83,10 +98,10 @@ begin variable Memory : T_SLM(DEPTH - 1 downto 0, word_t'range); variable res : ram_t; begin - if (str_length(FilePath) = 0) then + if str_length(FilePath) = 0 then -- shortcut required by Vivado return (others => (others => ite(SIMULATION, 'U', '0'))); - elsif (mem_FileExtension(FilePath) = "mem") then + elsif mem_FileExtension(FilePath) = "mem" then Memory := mem_ReadMemoryFile(FilePath, DEPTH, word_t'length, MEM_FILEFORMAT_XILINX_MEM, MEM_CONTENT_HEX); else Memory := mem_ReadMemoryFile(FilePath, DEPTH, word_t'length, MEM_FILEFORMAT_INTEL_HEX, MEM_CONTENT_HEX); @@ -117,7 +132,8 @@ begin end if; end process; - q <= ram(to_integer(a_reg)); -- gets new data + q <= (others => 'X') when SIMULATION and is_x(std_logic_vector(a_reg)) else + ram(to_integer(a_reg)); -- gets new data end generate gInfer; gAltera: if VENDOR = VENDOR_ALTERA generate @@ -125,7 +141,7 @@ begin generic ( A_BITS : positive; D_BITS : positive; - FILENAME : STRING := "" + FILENAME : string := "" ); port ( clk : in std_logic; diff --git a/src/mem/ocram/ocram_tdp.files b/src/mem/ocram/ocram_tdp.files index c265f98a..f94e2625 100644 --- a/src/mem/ocram/ocram_tdp.files +++ b/src/mem/ocram/ocram_tdp.files @@ -13,6 +13,7 @@ vhdl poc "src/mem/mem.pkg.vhdl" # Memory package # PoC.mem.ocram vhdl poc "src/mem/ocram/ocram.pkg.vhdl" # On-Chip-RAM if (DeviceVendor = "Altera") then + include "lib/Altera.files" vhdl poc "src/mem/ocram/altera/ocram_tdp_altera.vhdl" # Altera specific true dual-port RAM end if vhdl poc "src/mem/ocram/ocram_tdp.vhdl" # True dual-port RAM diff --git a/src/mem/ocram/ocram_tdp.vhdl b/src/mem/ocram/ocram_tdp.vhdl index 52245165..517157a1 100644 --- a/src/mem/ocram/ocram_tdp.vhdl +++ b/src/mem/ocram/ocram_tdp.vhdl @@ -1,51 +1,57 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Martin Zabel -- Patrick Lehmann -- --- Module: True dual-port memory. +-- Entity: True dual-port memory. -- -- Description: --- ------------------------------------ +-- ------------------------------------- -- Inferring / instantiating true dual-port memory, with: -- -- * dual clock, clock enable, -- * 2 read/write ports. -- +-- Command truth table for port 1, same applies to port 2: +-- +-- === === ================ +-- ce1 we1 Command +-- === === ================ +-- 0 X No operation +-- 1 0 Read from memory +-- 1 1 Write to memory +-- === === ================ +-- -- The generalized behavior across Altera and Xilinx FPGAs since -- Stratix/Cyclone and Spartan-3/Virtex-5, respectively, is as follows: -- --- * Same-Port Read-During Write: --- At rising edge of "clk1", data "d1" written to port 1 (ce1 and we1 = '1') --- is directly passed to the output "q1". This is also known as write-first --- mode or read-through write behavior. Same applies for port 2 (d2 -> q2). +-- Same-Port Read-During-Write +-- When writing data through port 1, the read output of the same port +-- (``q1``) will output the new data (``d1``, in the following clock cycle) +-- which is aka. "write-first behavior". This behavior also applies to Altera +-- M20K memory blocks as described in the Altera: "Stratix 5 Device Handbook" +-- (S5-5V1). The documentation in the Altera: "Embedded Memory User Guide" +-- (UG-01068) is wrong. +-- +-- Same applies to port 2. -- --- * Mixed-Port Read-During Write: --- Here, the Altera M512/M4K TriMatrix memory (as found e.g. in Stratix --- and Stratix II FPGAs) defines the minimum time after which the written data --- at one port can be read-out at the other again. As stated in the Stratix --- Handbook, Volume 2, page 2-13, data is actually written with the falling --- (instead of the rising) edge of the clock into the memory array. The write --- itself takes the write-cycle time which is less or equal to the minimum --- clock-period time. After this, the data can be read-out at the other port. --- Consequently, data "d1" written at the rising-edge of "clk1" at address --- "a1" can be read-out at the 2nd port from the same address with the --- 2nd rising-edge of "clk2" following the falling-edge of "clk1". --- If the rising-edge of "clk2" coincides with the falling-edge of "clk1" --- (e.g. same clock signal), then it is counted as the 1st rising-edge of --- "clk2" in this timing. Same applies analogous to data written at port 2 --- and read-out at port 1. +-- Mixed-Port Read-During-Write +-- When reading at the write address, the read value will be unknown which is +-- aka. "don't care behavior". This applies to all reads (at the same +-- address) which are issued during the write-cycle time, which starts at the +-- rising-edge of the write clock and (in the worst case) extends +-- until the next rising-edge of that write clock. -- --- WARNING: The simulated behavior on RT-level is not correct. +-- .. WARNING:: +-- The simulated behavior on RT-level is too optimistic. When reading +-- at the write address always the new data will be returned. -- --- TODO: add timing diagram --- TODO: implement correct behavior for RT-level simulation +-- .. TODO:: Implement correct behavior for RT-level simulation. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2008-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -60,7 +66,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; @@ -77,23 +83,23 @@ use PoC.mem.all; entity ocram_tdp is generic ( - A_BITS : positive; - D_BITS : positive; - FILENAME : STRING := "" + A_BITS : positive; -- number of address bits + D_BITS : positive; -- number of data bits + FILENAME : string := "" -- file-name for RAM initialization ); port ( - clk1 : in std_logic; - clk2 : in std_logic; - ce1 : in std_logic; - ce2 : in std_logic; - we1 : in std_logic; - we2 : in std_logic; - a1 : in unsigned(A_BITS-1 downto 0); - a2 : in unsigned(A_BITS-1 downto 0); - d1 : in std_logic_vector(D_BITS-1 downto 0); - d2 : in std_logic_vector(D_BITS-1 downto 0); - q1 : out std_logic_vector(D_BITS-1 downto 0); - q2 : out std_logic_vector(D_BITS-1 downto 0) + clk1 : in std_logic; -- clock for 1st port + clk2 : in std_logic; -- clock for 2nd port + ce1 : in std_logic; -- clock-enable for 1st port + ce2 : in std_logic; -- clock-enable for 2nd port + we1 : in std_logic; -- write-enable for 1st port + we2 : in std_logic; -- write-enable for 2nd port + a1 : in unsigned(A_BITS-1 downto 0); -- address for 1st port + a2 : in unsigned(A_BITS-1 downto 0); -- address for 2nd port + d1 : in std_logic_vector(D_BITS-1 downto 0); -- write-data for 1st port + d2 : in std_logic_vector(D_BITS-1 downto 0); -- write-data for 2nd port + q1 : out std_logic_vector(D_BITS-1 downto 0); -- read-data from 1st port + q2 : out std_logic_vector(D_BITS-1 downto 0) -- read-data from 2nd port ); end entity; @@ -102,7 +108,7 @@ architecture rtl of ocram_tdp is constant DEPTH : positive := 2**A_BITS; begin - gInfer : if ((VENDOR = VENDOR_GENERIC) or (VENDOR = VENDOR_LATTICE) or (VENDOR = VENDOR_XILINX)) generate + gInfer : if (VENDOR = VENDOR_GENERIC) or (VENDOR = VENDOR_LATTICE) or (VENDOR = VENDOR_XILINX) generate -- RAM can be inferred correctly only if '-use_new_parser yes' is enabled in XST options subtype word_t is std_logic_vector(D_BITS - 1 downto 0); type ram_t is array(0 to DEPTH - 1) of word_t; @@ -112,10 +118,10 @@ begin variable Memory : T_SLM(DEPTH - 1 downto 0, word_t'range); variable res : ram_t; begin - if (str_length(FilePath) = 0) then + if str_length(FilePath) = 0 then -- shortcut required by Vivado return (others => (others => ite(SIMULATION, 'U', '0'))); - elsif (mem_FileExtension(FilePath) = "mem") then + elsif mem_FileExtension(FilePath) = "mem" then Memory := mem_ReadMemoryFile(FilePath, DEPTH, word_t'length, MEM_FILEFORMAT_XILINX_MEM, MEM_CONTENT_HEX); else Memory := mem_ReadMemoryFile(FilePath, DEPTH, word_t'length, MEM_FILEFORMAT_INTEL_HEX, MEM_CONTENT_HEX); @@ -158,8 +164,10 @@ begin end if; end process; - q1 <= ram(to_integer(a1_reg)); -- returns new data - q2 <= ram(to_integer(a2_reg)); -- returns new data + q1 <= (others => 'X') when SIMULATION and is_x(std_logic_vector(a1_reg)) else + ram(to_integer(a1_reg)); -- returns new data + q2 <= (others => 'X') when SIMULATION and is_x(std_logic_vector(a2_reg)) else + ram(to_integer(a2_reg)); -- returns new data end generate gInfer; gAltera: if VENDOR = VENDOR_ALTERA generate @@ -167,7 +175,7 @@ begin generic ( A_BITS : positive; D_BITS : positive; - FILENAME : STRING := "" + FILENAME : string := "" ); port ( clk1 : in std_logic; @@ -189,7 +197,7 @@ begin -- declaration above) is not sufficient for ModelSim. -- That requires also usage of altera_mf library. - i: ocram_tdp_altera + ram_tdp: ocram_tdp_altera generic map ( A_BITS => A_BITS, D_BITS => D_BITS, diff --git a/src/mem/ocrom/ocrom.pkg.vhdl b/src/mem/ocrom/ocrom.pkg.vhdl index 428046da..63cacbf9 100644 --- a/src/mem/ocrom/ocrom.pkg.vhdl +++ b/src/mem/ocrom/ocrom.pkg.vhdl @@ -1,8 +1,7 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Martin Zabel -- Patrick Lehmann -- @@ -10,13 +9,13 @@ -- associated to the PoC.mem.ocram namespace -- -- Description: --- ------------------------------------ +-- ------------------------------------- -- On-Chip ROMs (Read-Only-Memory) for FPGAs. -- -- A detailed documentation is included in each module. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2008-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -31,7 +30,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.std_logic_1164.all; @@ -44,7 +43,7 @@ package ocrom is generic ( A_BITS : positive; D_BITS : positive; - FILENAME : STRING := "" + FILENAME : string := "" ); port ( clk : in std_logic; @@ -59,7 +58,7 @@ package ocrom is generic ( A_BITS : positive; D_BITS : positive; - FILENAME : STRING := "" + FILENAME : string := "" ); port ( clk1 : in std_logic; diff --git a/src/mem/ocrom/ocrom_dp.vhdl b/src/mem/ocrom/ocrom_dp.vhdl index 9be6356f..e0779a9b 100644 --- a/src/mem/ocrom/ocrom_dp.vhdl +++ b/src/mem/ocrom/ocrom_dp.vhdl @@ -1,15 +1,14 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Martin Zabel -- Patrick Lehmann -- --- Module: True dual-port memory. +-- Entity: True dual-port memory. -- -- Description: --- ------------------------------------ +-- ------------------------------------- -- Inferring / instantiating dual-port read-only memory, with: -- -- * dual clock, clock enable, @@ -24,7 +23,7 @@ -- TODO: implement correct behavior for RT-level simulation -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2008-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -39,7 +38,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library STD; @@ -62,7 +61,7 @@ entity ocrom_dp is generic ( A_BITS : positive; D_BITS : positive; - FILENAME : STRING := "" + FILENAME : string := "" ); port ( clk1 : in std_logic; @@ -83,7 +82,7 @@ architecture rtl of ocrom_dp is begin assert (str_length(FILENAME) /= 0) report "Do you really want to generate a block of zeros?" severity FAILURE; - gInfer: if ((VENDOR = VENDOR_GENERIC) or (VENDOR = VENDOR_XILINX)) generate + gInfer: if (VENDOR = VENDOR_GENERIC) or (VENDOR = VENDOR_XILINX) generate -- RAM can be inferred correctly only for newer FPGAs! subtype word_t is std_logic_vector(D_BITS - 1 downto 0); type rom_t is array(0 to DEPTH - 1) of word_t; @@ -93,10 +92,10 @@ begin variable Memory : T_SLM(DEPTH - 1 downto 0, word_t'range); variable res : rom_t; begin - if (str_length(FilePath) = 0) then + if str_length(FilePath) = 0 then -- shortcut required by Vivado (assert above is ignored) return (others => (others => ite(SIMULATION, 'U', '0'))); - elsif (mem_FileExtension(FilePath) = "mem") then + elsif mem_FileExtension(FilePath) = "mem" then Memory := mem_ReadMemoryFile(FilePath, DEPTH, word_t'length, MEM_FILEFORMAT_XILINX_MEM, MEM_CONTENT_HEX); else Memory := mem_ReadMemoryFile(FilePath, DEPTH, word_t'length, MEM_FILEFORMAT_INTEL_HEX, MEM_CONTENT_HEX); @@ -137,12 +136,12 @@ begin q2 <= rom(to_integer(a2_reg)); -- returns new data end generate gInfer; - gAltera: if (VENDOR = VENDOR_ALTERA) generate + gAltera: if VENDOR = VENDOR_ALTERA generate component ocram_tdp_altera generic ( A_BITS : positive; D_BITS : positive; - FILENAME : STRING := "" + FILENAME : string := "" ); port ( clk1 : in std_logic; diff --git a/src/mem/ocrom/ocrom_sp.vhdl b/src/mem/ocrom/ocrom_sp.vhdl index 22f2aeb8..90fc6cbb 100644 --- a/src/mem/ocrom/ocrom_sp.vhdl +++ b/src/mem/ocrom/ocrom_sp.vhdl @@ -1,15 +1,14 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Martin Zabel -- Patrick Lehmann -- --- Module: Single-port memory. +-- Entity: Single-port memory. -- -- Description: --- ------------------------------------ +-- ------------------------------------- -- Inferring / instantiating single-port read-only memory -- -- - single clock, clock enable @@ -17,7 +16,7 @@ -- -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2008-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -32,7 +31,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library STD; @@ -55,7 +54,7 @@ entity ocrom_sp is generic ( A_BITS : positive; D_BITS : positive; - FILENAME : STRING := "" + FILENAME : string := "" ); port ( clk : in std_logic; @@ -72,7 +71,7 @@ architecture rtl of ocrom_sp is begin assert (str_length(FILENAME) /= 0) report "Do you really want to generate a block of zeros?" severity FAILURE; - gInfer: if ((VENDOR = VENDOR_GENERIC) or (VENDOR = VENDOR_XILINX)) generate + gInfer: if (VENDOR = VENDOR_GENERIC) or (VENDOR = VENDOR_XILINX) generate -- RAM can be inferred correctly -- XST Advanced HDL Synthesis generates single-port memory as expected. subtype word_t is std_logic_vector(D_BITS - 1 downto 0); @@ -83,10 +82,10 @@ begin variable Memory : T_SLM(DEPTH - 1 downto 0, word_t'range); variable res : rom_t; begin - if (str_length(FilePath) = 0) then + if str_length(FilePath) = 0 then -- shortcut required by Vivado (assert above is ignored) return (others => (others => ite(SIMULATION, 'U', '0'))); - elsif (mem_FileExtension(FilePath) = "mem") then + elsif mem_FileExtension(FilePath) = "mem" then Memory := mem_ReadMemoryFile(FilePath, DEPTH, word_t'length, MEM_FILEFORMAT_XILINX_MEM, MEM_CONTENT_HEX); else Memory := mem_ReadMemoryFile(FilePath, DEPTH, word_t'length, MEM_FILEFORMAT_INTEL_HEX, MEM_CONTENT_HEX); @@ -120,7 +119,7 @@ begin generic ( A_BITS : positive; D_BITS : positive; - FILENAME : STRING := "" + FILENAME : string := "" ); port ( clk : in std_logic; diff --git a/src/mem/sdram/sdram_ctrl_de0.vhdl b/src/mem/sdram/sdram_ctrl_de0.vhdl index 402afe61..42c2adde 100644 --- a/src/mem/sdram/sdram_ctrl_de0.vhdl +++ b/src/mem/sdram/sdram_ctrl_de0.vhdl @@ -1,14 +1,13 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Martin Zabel -- --- Module: Controller for ISSI SDR-SDRAM for Altera DE0 Board +-- Entity: Controller for ISSI SDR-SDRAM for Altera DE0 Board -- -- Description: --- ------------------------------------ +-- ------------------------------------- -- Complete controller for ISSI SDR-SDRAM for Altera DE0 Board. -- SDRAM Device: IS42S16400F -- @@ -31,7 +30,7 @@ -- Synchronous resets are used. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -46,7 +45,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= ------------------------------------------------------------------------------- -- Naming Conventions: diff --git a/src/mem/sdram/sdram_ctrl_fsm.vhdl b/src/mem/sdram/sdram_ctrl_fsm.vhdl index b6205ad0..1fa749f1 100644 --- a/src/mem/sdram/sdram_ctrl_fsm.vhdl +++ b/src/mem/sdram/sdram_ctrl_fsm.vhdl @@ -1,14 +1,13 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Martin Zabel -- --- Module: Generic controller for SDRAM memory. +-- Entity: Generic controller for SDRAM memory. -- -- Description: --- ------------------------------------ +-- ------------------------------------- -- This file contains the FSM as well as parts of the datapath. -- The board specific physical layer is defined in another file -- sdram_ctrl_phy_*.vhdl @@ -74,7 +73,7 @@ -- The write data must directly connected to the physical layer. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -89,7 +88,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= ------------------------------------------------------------------------------- -- Naming Conventions: diff --git a/src/mem/sdram/sdram_ctrl_phy_de0.vhdl b/src/mem/sdram/sdram_ctrl_phy_de0.vhdl index 37158b5a..50608c78 100644 --- a/src/mem/sdram/sdram_ctrl_phy_de0.vhdl +++ b/src/mem/sdram/sdram_ctrl_phy_de0.vhdl @@ -1,14 +1,13 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Martin Zabel -- --- Module: Physical layer of SDRAM-Controller for Altera DE0 Board +-- Entity: Physical layer of SDRAM-Controller for Altera DE0 Board -- -- Description: --- ------------------------------------ +-- ------------------------------------- -- Physical layer used by module 'sdram_ctrl_de0' -- -- Instantiates input and output buffer components and adjusts timing for @@ -34,7 +33,7 @@ -- Synchronous resets are used. Reset must be hold for at least two cycles. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -49,7 +48,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= ------------------------------------------------------------------------------- -- Naming Conventions: @@ -72,7 +71,7 @@ ------------------------------------------------------------------------------- library ieee; -use ieee.std_logic_1164.ALL; +use ieee.std_logic_1164.all; library altera_mf; use altera_mf.altera_mf_components.all; diff --git a/src/mem/sdram/sdram_ctrl_phy_s3esk.vhdl b/src/mem/sdram/sdram_ctrl_phy_s3esk.vhdl index f11deacb..a6555e8d 100644 --- a/src/mem/sdram/sdram_ctrl_phy_s3esk.vhdl +++ b/src/mem/sdram/sdram_ctrl_phy_s3esk.vhdl @@ -1,14 +1,13 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Martin Zabel -- --- Module: Physical layer of SDRAM-Controller for Spartan-3E Starter Kit +-- Entity: Physical layer of SDRAM-Controller for Spartan-3E Starter Kit -- -- Description: --- ------------------------------------ +-- ------------------------------------- -- Physical layer used by module 'sdram_ctrl_s3esk' -- -- Instantiates input and output buffer components and adjusts timing for @@ -59,7 +58,7 @@ -- Synchronous resets are used. Reset must be hold for at least two cycles. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -74,7 +73,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= ------------------------------------------------------------------------------- -- Naming Conventions: @@ -97,7 +96,7 @@ ------------------------------------------------------------------------------- library ieee; -use ieee.std_logic_1164.ALL; +use ieee.std_logic_1164.all; library unisim; use unisim.VComponents.all; diff --git a/src/mem/sdram/sdram_ctrl_s3esk.vhdl b/src/mem/sdram/sdram_ctrl_s3esk.vhdl index 846e5ae8..a898f2f9 100644 --- a/src/mem/sdram/sdram_ctrl_s3esk.vhdl +++ b/src/mem/sdram/sdram_ctrl_s3esk.vhdl @@ -1,14 +1,13 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Martin Zabel -- --- Module: Controller for Micron DDR-SDRAM on Spartan-3E Starter Kit Board. +-- Entity: Controller for Micron DDR-SDRAM on Spartan-3E Starter Kit Board. -- -- Description: --- ------------------------------------ +-- ------------------------------------- -- Controller for Micron DDR-SDRAM on Spartan-3E Starter Kit Board. -- SDRAM Device: MT46V32M16-6T -- @@ -30,7 +29,7 @@ -- Synchronous resets are used. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -45,7 +44,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= ------------------------------------------------------------------------------- -- Naming Conventions: diff --git a/src/misc/filter/filter_and.vhdl b/src/misc/filter/filter_and.vhdl index ff81e867..50198d9a 100644 --- a/src/misc/filter/filter_and.vhdl +++ b/src/misc/filter/filter_and.vhdl @@ -1,15 +1,14 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= --- Package: TODO --- -- Authors: Patrick Lehmann -- +-- Entity: TODO +-- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: -- ============================================================================= @@ -37,33 +36,33 @@ use PoC.utils.all; entity filter_and is generic ( - TAPS : POSITIVE := 4; -- - INIT : STD_LOGIC := '0'; -- - ADD_OUTPUT_REG : BOOLEAN := FALSE -- + TAPS : positive := 4; -- + INIT : std_logic := '0'; -- + ADD_OUTPUT_REG : boolean := FALSE -- ); port ( - Clock : in STD_LOGIC; -- clock - DataIn : in STD_LOGIC; -- data to filter - DataOut : out STD_LOGIC -- filtered signal + Clock : in std_logic; -- clock + DataIn : in std_logic; -- data to filter + DataOut : out std_logic -- filtered signal ); -end; +end entity; architecture rtl of filter_and is - signal Delays : STD_LOGIC_VECTOR(TAPS - 1 downto 0) := (others => INIT); - signal FilterOut : STD_LOGIC; + signal Delays : std_logic_vector(TAPS - 1 downto 0) := (others => INIT); + signal FilterOut : std_logic; begin Delays <= Delays(Delays'high - 1 downto 0) & DataIn when rising_edge(Clock); FilterOut <= slv_and(Delays); - genOutReg0 : if (ADD_OUTPUT_REG = FALSE) generate + genOutReg0 : if not ADD_OUTPUT_REG generate DataOut <= FilterOut; end generate; - genOutReg1 : if (ADD_OUTPUT_REG = TRUE) generate - signal FilterOut_d : STD_LOGIC := INIT; + genOutReg1 : if ADD_OUTPUT_REG generate + signal FilterOut_d : std_logic := INIT; begin FilterOut_d <= FilterOut when rising_edge(Clock); DataOut <= FilterOut_d; end generate; -end; \ No newline at end of file +end; diff --git a/src/misc/filter/filter_mean.vhdl b/src/misc/filter/filter_mean.vhdl index 442a5b58..bb9e09c9 100644 --- a/src/misc/filter/filter_mean.vhdl +++ b/src/misc/filter/filter_mean.vhdl @@ -1,15 +1,14 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= --- Package: TODO --- -- Authors: Patrick Lehmann -- +-- Entity: TODO +-- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: -- ============================================================================= @@ -37,21 +36,21 @@ use PoC.utils.all; entity filter_mean is generic ( - TAPS : POSITIVE := 4; -- - INIT : STD_LOGIC := '1'; -- - ADD_OUTPUT_REG : BOOLEAN := FALSE -- + TAPS : positive := 4; -- + INIT : std_logic := '1'; -- + ADD_OUTPUT_REG : boolean := FALSE -- ); port ( - Clock : in STD_LOGIC; -- clock - DataIn : in STD_LOGIC; -- data to filter - DataOut : out STD_LOGIC -- filtered signal + Clock : in std_logic; -- clock + DataIn : in std_logic; -- data to filter + DataOut : out std_logic -- filtered signal ); -end; +end entity; architecture rtl of filter_mean is - signal Delays : STD_LOGIC_VECTOR(TAPS - 1 downto 0) := (others => INIT); - signal FilterOut : STD_LOGIC; + signal Delays : std_logic_vector(TAPS - 1 downto 0) := (others => INIT); + signal FilterOut : std_logic; begin Delays <= Delays(Delays'high - 1 downto 0) & DataIn when rising_edge(Clock); @@ -70,13 +69,13 @@ begin FilterOut <= to_sl(popcnt > (Delays'length - popcnt)); end process; - genOutReg0 : if (ADD_OUTPUT_REG = FALSE) generate + genOutReg0 : if not ADD_OUTPUT_REG generate DataOut <= FilterOut; end generate; - genOutReg1 : if (ADD_OUTPUT_REG = TRUE) generate - signal FilterOut_d : STD_LOGIC := INIT; + genOutReg1 : if ADD_OUTPUT_REG generate + signal FilterOut_d : std_logic := INIT; begin FilterOut_d <= FilterOut when rising_edge(Clock); DataOut <= FilterOut_d; end generate; -end; \ No newline at end of file +end; diff --git a/src/misc/filter/filter_or.vhdl b/src/misc/filter/filter_or.vhdl index 074110d5..1107ee7d 100644 --- a/src/misc/filter/filter_or.vhdl +++ b/src/misc/filter/filter_or.vhdl @@ -1,15 +1,14 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= --- Package: TODO --- -- Authors: Patrick Lehmann -- +-- Entity: TODO +-- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: -- ============================================================================= @@ -37,33 +36,33 @@ use PoC.utils.all; entity filter_or is generic ( - TAPS : POSITIVE := 4; -- - INIT : STD_LOGIC := '1'; -- - ADD_OUTPUT_REG : BOOLEAN := FALSE -- + TAPS : positive := 4; -- + INIT : std_logic := '1'; -- + ADD_OUTPUT_REG : boolean := FALSE -- ); port ( - Clock : in STD_LOGIC; -- clock - DataIn : in STD_LOGIC; -- data to filter - DataOut : out STD_LOGIC -- filtered signal + Clock : in std_logic; -- clock + DataIn : in std_logic; -- data to filter + DataOut : out std_logic -- filtered signal ); -end; +end entity; architecture rtl of filter_or is - signal Delays : STD_LOGIC_VECTOR(TAPS - 1 downto 0) := (others => INIT); - signal FilterOut : STD_LOGIC; + signal Delays : std_logic_vector(TAPS - 1 downto 0) := (others => INIT); + signal FilterOut : std_logic; begin Delays <= Delays(Delays'high - 1 downto 0) & DataIn when rising_edge(Clock); FilterOut <= slv_or(Delays); - genOutReg0 : if (ADD_OUTPUT_REG = FALSE) generate + genOutReg0 : if not ADD_OUTPUT_REG generate DataOut <= FilterOut; end generate; - genOutReg1 : if (ADD_OUTPUT_REG = TRUE) generate - signal FilterOut_d : STD_LOGIC := INIT; + genOutReg1 : if ADD_OUTPUT_REG generate + signal FilterOut_d : std_logic := INIT; begin FilterOut_d <= FilterOut when rising_edge(Clock); DataOut <= FilterOut_d; end generate; -end; \ No newline at end of file +end; diff --git a/src/misc/gearbox/gearbox_down_cc.vhdl b/src/misc/gearbox/gearbox_down_cc.vhdl index ed297f6b..f7025ae2 100644 --- a/src/misc/gearbox/gearbox_down_cc.vhdl +++ b/src/misc/gearbox/gearbox_down_cc.vhdl @@ -1,14 +1,13 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: A downscaling gearbox module with a common clock (cc) interface. +-- Entity: A downscaling gearbox module with a common clock (cc) interface. -- -- Description: --- ------------------------------------ +-- ------------------------------------- -- This module provides a downscaling gearbox with a common clock (cc) -- interface. It perfoems a 'word' to 'byte' splitting. The default order is -- LITTLE_ENDIAN (starting at byte(0)). Input "In_Data" and output "Out_Data" @@ -16,7 +15,7 @@ -- can be added by enabling (ADD_***PUT_REGISTERS = TRUE). -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -31,7 +30,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.std_logic_1164.all; @@ -46,67 +45,67 @@ use PoC.components.all; entity gearbox_down_cc is generic ( - INPUT_BITS : POSITIVE := 32; - OUTPUT_BITS : POSITIVE := 24; - META_BITS : NATURAL := 0; - ADD_INPUT_REGISTERS : BOOLEAN := FALSE; - ADD_OUTPUT_REGISTERS : BOOLEAN := FALSE + INPUT_BITS : positive := 32; + OUTPUT_BITS : positive := 24; + META_BITS : natural := 0; + ADD_INPUT_REGISTERS : boolean := FALSE; + ADD_OUTPUT_REGISTERS : boolean := FALSE ); port ( - Clock : in STD_LOGIC; - - In_Sync : in STD_LOGIC; - In_Valid : in STD_LOGIC; - In_Next : out STD_LOGIC; - In_Data : in STD_LOGIC_VECTOR(INPUT_BITS - 1 downto 0); - In_Meta : in STD_LOGIC_VECTOR(META_BITS - 1 downto 0); - - Out_Sync : out STD_LOGIC; - Out_Valid : out STD_LOGIC; - Out_Data : out STD_LOGIC_VECTOR(OUTPUT_BITS - 1 downto 0); - Out_Meta : out STD_LOGIC_VECTOR(META_BITS - 1 downto 0); - Out_First : out STD_LOGIC; - Out_Last : out STD_LOGIC + Clock : in std_logic; + + In_Sync : in std_logic; + In_Valid : in std_logic; + In_Next : out std_logic; + In_Data : in std_logic_vector(INPUT_BITS - 1 downto 0); + In_Meta : in std_logic_vector(META_BITS - 1 downto 0); + + Out_Sync : out std_logic; + Out_Valid : out std_logic; + Out_Data : out std_logic_vector(OUTPUT_BITS - 1 downto 0); + Out_Meta : out std_logic_vector(META_BITS - 1 downto 0); + Out_First : out std_logic; + Out_Last : out std_logic ); end entity; architecture rtl of gearbox_down_cc is - constant C_VERBOSE : BOOLEAN := FALSE; --POC_VERBOSE; + constant C_VERBOSE : boolean := FALSE; --POC_VERBOSE; - constant BITS_PER_CHUNK : POSITIVE := greatestCommonDivisor(INPUT_BITS, OUTPUT_BITS); - constant INPUT_CHUNKS : POSITIVE := INPUT_BITS / BITS_PER_CHUNK; - constant OUTPUT_CHUNKS : POSITIVE := OUTPUT_BITS / BITS_PER_CHUNK; + constant BITS_PER_CHUNK : positive := greatestCommonDivisor(INPUT_BITS, OUTPUT_BITS); + constant INPUT_CHUNKS : positive := INPUT_BITS / BITS_PER_CHUNK; + constant OUTPUT_CHUNKS : positive := OUTPUT_BITS / BITS_PER_CHUNK; - subtype T_CHUNK is STD_LOGIC_VECTOR(BITS_PER_CHUNK - 1 downto 0); - type T_CHUNK_VECTOR is array(NATURAL range <>) of T_CHUNK; + subtype T_CHUNK is std_logic_vector(BITS_PER_CHUNK - 1 downto 0); + type T_CHUNK_VECTOR is array(natural range <>) of T_CHUNK; - subtype T_MUX_INDEX is INTEGER range 0 to INPUT_CHUNKS - 1; + subtype T_MUX_INDEX is integer range 0 to INPUT_CHUNKS - 1; type T_MUX_INPUT is record Index : T_MUX_INDEX; - UseBuffer : BOOLEAN; + UseBuffer : boolean; end record; - type T_MUX_INPUT_LIST is array(NATURAL range <>) of T_MUX_INPUT; + type T_MUX_INPUT_LIST is array(natural range <>) of T_MUX_INPUT; type T_MUX_INPUT_STRUCT is record List : T_MUX_INPUT_LIST(0 to OUTPUT_CHUNKS - 1); - Reg_en : STD_LOGIC; - Nxt : STD_LOGIC; - First : STD_LOGIC; - Last : STD_LOGIC; + Reg_en : std_logic; + Nxt : std_logic; + First : std_logic; + Last : std_logic; end record; - type T_MUX_DESCRIPTIONS is array(NATURAL range <>) of T_MUX_INPUT_STRUCT; + type T_MUX_DESCRIPTIONS is array(natural range <>) of T_MUX_INPUT_STRUCT; function genMuxDescription return T_MUX_DESCRIPTIONS is variable DESC : T_MUX_DESCRIPTIONS(0 to INPUT_CHUNKS - 1); - variable UseBuffer : BOOLEAN; + variable UseBuffer : boolean; variable k : T_MUX_INDEX; begin - if (C_VERBOSE = TRUE) then report "genMuxDescription: IC=" & INTEGER'image(INPUT_CHUNKS) severity NOTE; end if; + if C_VERBOSE then report "genMuxDescription: IC=" & integer'image(INPUT_CHUNKS) severity NOTE; end if; k := INPUT_CHUNKS - 1; for i in 0 to INPUT_CHUNKS - 1 loop - if (C_VERBOSE = TRUE) then report " i: " & INTEGER'image(i) & " List:" severity NOTE; end if; + if C_VERBOSE then report " i: " & integer'image(i) & " List:" severity NOTE; end if; UseBuffer := TRUE; for j in 0 to OUTPUT_CHUNKS - 1 loop k := (k + 1) mod INPUT_CHUNKS; @@ -114,14 +113,14 @@ architecture rtl of gearbox_down_cc is DESC(i).List(j).Index := k; DESC(i).List(j).UseBuffer := UseBuffer; - if (C_VERBOSE = TRUE) then report " j= " & INTEGER'image(j) & " k=" & INTEGER'image(DESC(i).List(j).Index) severity NOTE; end if; + if C_VERBOSE then report " j= " & integer'image(j) & " k=" & INTEGER'image(DESC(i).List(j).Index) severity NOTE; end if; end loop; DESC(i).Reg_en := to_sl(not UseBuffer); DESC(i).Nxt := to_sl(k + OUTPUT_CHUNKS >= INPUT_CHUNKS); DESC(i).First := to_sl(i = 0); DESC(i).Last := to_sl(i = INPUT_CHUNKS - 1); - if (C_VERBOSE = TRUE) then report " en=" & STD_LOGIC'image(DESC(i).Reg_en) & " nxt=" & STD_LOGIC'image(DESC(i).Nxt) severity NOTE; end if; + if C_VERBOSE then report " en=" & std_logic'image(DESC(i).Reg_en) & " nxt=" & STD_LOGIC'image(DESC(i).Nxt) severity NOTE; end if; end loop; return DESC; end function; @@ -129,8 +128,8 @@ architecture rtl of gearbox_down_cc is constant MUX_INPUT_TRANSLATION : T_MUX_DESCRIPTIONS := genMuxDescription; -- create vector-vector from vector (4 bit) - function to_chunkv(slv : STD_LOGIC_VECTOR) return T_CHUNK_VECTOR is - constant CHUNKS : POSITIVE := slv'length / BITS_PER_CHUNK; + function to_chunkv(slv : std_logic_vector) return T_CHUNK_VECTOR is + constant CHUNKS : positive := slv'length / BITS_PER_CHUNK; variable Result : T_CHUNK_VECTOR(CHUNKS - 1 downto 0); begin if ((slv'length mod BITS_PER_CHUNK) /= 0) then report "to_chunkv: width mismatch - slv'length is no multiple of BITS_PER_CHUNK (slv'length=" & INTEGER'image(slv'length) & "; BITS_PER_CHUNK=" & INTEGER'image(BITS_PER_CHUNK) & ")" severity FAILURE; end if; @@ -142,8 +141,8 @@ architecture rtl of gearbox_down_cc is end function; -- convert vector-vector to flatten vector - function to_slv(slvv : T_CHUNK_VECTOR) return STD_LOGIC_VECTOR is - variable slv : STD_LOGIC_VECTOR((slvv'length * BITS_PER_CHUNK) - 1 downto 0); + function to_slv(slvv : T_CHUNK_VECTOR) return std_logic_vector is + variable slv : std_logic_vector((slvv'length * BITS_PER_CHUNK) - 1 downto 0); begin for i in slvv'range loop slv(((i + 1) * BITS_PER_CHUNK) - 1 downto (i * BITS_PER_CHUNK)) := slvv(i); @@ -151,46 +150,46 @@ architecture rtl of gearbox_down_cc is return slv; end function; - signal In_Sync_d : STD_LOGIC := '0'; - signal In_Data_d : STD_LOGIC_VECTOR(INPUT_BITS - 1 downto 0) := (others => '0'); - signal In_Meta_d : STD_LOGIC_VECTOR(META_BITS - 1 downto 0) := (others => '0'); - signal In_Valid_d : STD_LOGIC := '0'; + signal In_Sync_d : std_logic := '0'; + signal In_Data_d : std_logic_vector(INPUT_BITS - 1 downto 0) := (others => '0'); + signal In_Meta_d : std_logic_vector(META_BITS - 1 downto 0) := (others => '0'); + signal In_Valid_d : std_logic := '0'; - signal MuxSelect_rst : STD_LOGIC; - signal MuxSelect_en : STD_LOGIC; - signal MuxSelect_us : UNSIGNED(log2ceilnz(INPUT_CHUNKS) - 1 downto 0) := (others => '0'); - signal MuxSelect_ov : STD_LOGIC; + signal MuxSelect_rst : std_logic; + signal MuxSelect_en : std_logic; + signal MuxSelect_us : unsigned(log2ceilnz(INPUT_CHUNKS) - 1 downto 0) := (others => '0'); + signal MuxSelect_ov : std_logic; - signal Nxt : STD_LOGIC; - signal AutoIncrement : STD_LOGIC; + signal Nxt : std_logic; + signal AutoIncrement : std_logic; signal GearBoxInput : T_CHUNK_VECTOR(INPUT_CHUNKS - 1 downto 0); - signal GearBoxBuffer_en : STD_LOGIC; + signal GearBoxBuffer_en : std_logic; signal GearBoxBuffer : T_CHUNK_VECTOR(INPUT_CHUNKS - 1 downto 1) := (others => (others => '0')); signal GearBoxOutput : T_CHUNK_VECTOR(OUTPUT_CHUNKS - 1 downto 0); - signal SyncOut : STD_LOGIC; - signal ValidOut : STD_LOGIC; - signal DataOut : STD_LOGIC_VECTOR(OUTPUT_BITS - 1 downto 0); - signal MetaOut : STD_LOGIC_VECTOR(META_BITS - 1 downto 0); - signal FirstOut : STD_LOGIC; - signal LastOut : STD_LOGIC; + signal SyncOut : std_logic; + signal ValidOut : std_logic; + signal DataOut : std_logic_vector(OUTPUT_BITS - 1 downto 0); + signal MetaOut : std_logic_vector(META_BITS - 1 downto 0); + signal FirstOut : std_logic; + signal LastOut : std_logic; - signal Out_Sync_d : STD_LOGIC := '0'; - signal Out_Valid_d : STD_LOGIC := '0'; - signal Out_Data_d : STD_LOGIC_VECTOR(OUTPUT_BITS - 1 downto 0) := (others => '0'); - signal Out_Meta_d : STD_LOGIC_VECTOR(META_BITS - 1 downto 0) := (others => '0'); - signal Out_First_d : STD_LOGIC := '0'; - signal Out_Last_d : STD_LOGIC := '0'; + signal Out_Sync_d : std_logic := '0'; + signal Out_Valid_d : std_logic := '0'; + signal Out_Data_d : std_logic_vector(OUTPUT_BITS - 1 downto 0) := (others => '0'); + signal Out_Meta_d : std_logic_vector(META_BITS - 1 downto 0) := (others => '0'); + signal Out_First_d : std_logic := '0'; + signal Out_Last_d : std_logic := '0'; begin assert (not C_VERBOSE) - report "gearbox_down_cc:" & CR & - " INPUT_BITS=" & INTEGER'image(INPUT_BITS) & - " OUTPUT_BITS=" & INTEGER'image(OUTPUT_BITS) & - " INPUT_CHUNKS=" & INTEGER'image(INPUT_CHUNKS) & - " OUTPUT_CHUNKS=" & INTEGER'image(OUTPUT_CHUNKS) & - " BITS_PER_CHUNK=" & INTEGER'image(BITS_PER_CHUNK) + report "gearbox_down_cc:" & LF & + " INPUT_BITS=" & integer'image(INPUT_BITS) & + " OUTPUT_BITS=" & integer'image(OUTPUT_BITS) & + " INPUT_CHUNKS=" & integer'image(INPUT_CHUNKS) & + " OUTPUT_CHUNKS=" & integer'image(OUTPUT_CHUNKS) & + " BITS_PER_CHUNK=" & integer'image(BITS_PER_CHUNK) severity NOTE; assert (INPUT_BITS > OUTPUT_BITS) report "OUTPUT_BITS must be less than INPUT_BITS, otherwise it's no down-sizing gearbox." severity FAILURE; @@ -227,11 +226,11 @@ begin begin genMuxInputs : for i in 0 to INPUT_CHUNKS - 1 generate assert (not C_VERBOSE) - report "i= " & INTEGER'image(i) & " " & - "j= " & INTEGER'image(j) & " " & - "-> idx= " & INTEGER'image(MUX_INPUT_TRANSLATION(i).List(j).Index) & " " & - "-> useBuffer= " & BOOLEAN'image(MUX_INPUT_TRANSLATION(i).List(j).UseBuffer) & " " & - "-> Nxt= " & STD_LOGIC'image(MUX_INPUT_TRANSLATION(i).Nxt) + report "i= " & integer'image(i) & " " & + "j= " & integer'image(j) & " " & + "-> idx= " & integer'image(MUX_INPUT_TRANSLATION(i).List(j).Index) & " " & + "-> useBuffer= " & boolean'image(MUX_INPUT_TRANSLATION(i).List(j).UseBuffer) & " " & + "-> Nxt= " & std_logic'image(MUX_INPUT_TRANSLATION(i).Nxt) severity NOTE; connectToInput : if (MUX_INPUT_TRANSLATION(i).List(j).UseBuffer = FALSE) generate diff --git a/src/misc/gearbox/gearbox_down_dc.vhdl b/src/misc/gearbox/gearbox_down_dc.vhdl index 5ea7cbe3..eff98181 100644 --- a/src/misc/gearbox/gearbox_down_dc.vhdl +++ b/src/misc/gearbox/gearbox_down_dc.vhdl @@ -1,14 +1,13 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: A downscaling gearbox module with a dependent clock (dc) interface. +-- Entity: A downscaling gearbox module with a dependent clock (dc) interface. -- -- Description: --- ------------------------------------ +-- ------------------------------------- -- This module provides a downscaling gearbox with a dependent clock (dc) -- interface. It perfoems a 'word' to 'byte' splitting. The default order is -- LITTLE_ENDIAN (starting at byte(0)). Input "In_Data" is of clock domain @@ -21,7 +20,7 @@ -- - Clock1 and Clock2 MUST be phase aligned (related) to each other. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -36,7 +35,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; @@ -50,38 +49,38 @@ use PoC.components.all; entity gearbox_down_dc is generic ( - INPUT_BITS : POSITIVE := 32; -- input bits ('words') - OUTPUT_BITS : POSITIVE := 8; -- output bits ('byte') + INPUT_BITS : positive := 32; -- input bits ('words') + OUTPUT_BITS : positive := 8; -- output bits ('byte') OUTPUT_ORDER : T_BIT_ORDER := LSB_FIRST; -- LSB_FIRST: start at byte(0), MSB_FIRST: start at byte(n-1) - ADD_INPUT_REGISTERS : BOOLEAN := FALSE; -- add input register @Clock1 - ADD_OUTPUT_REGISTERS : BOOLEAN := FALSE -- add output register @Clock2 + ADD_INPUT_REGISTERS : boolean := FALSE; -- add input register @Clock1 + ADD_OUTPUT_REGISTERS : boolean := FALSE -- add output register @Clock2 ); port ( - Clock1 : in STD_LOGIC; -- input clock domain - Clock2 : in STD_LOGIC; -- output clock domain - In_Data : in STD_LOGIC_VECTOR(INPUT_BITS - 1 downto 0); -- input word - Out_Data : out STD_LOGIC_VECTOR(OUTPUT_BITS - 1 downto 0) -- output word + Clock1 : in std_logic; -- input clock domain + Clock2 : in std_logic; -- output clock domain + In_Data : in std_logic_vector(INPUT_BITS - 1 downto 0); -- input word + Out_Data : out std_logic_vector(OUTPUT_BITS - 1 downto 0) -- output word ); end entity; -architecture rtl OF gearbox_down_dc is +architecture rtl of gearbox_down_dc is constant BIT_RATIO : REAL := real(INPUT_BITS) / real(OUTPUT_BITS); - constant COUNTER_BITS : POSITIVE := log2ceil(integer(BIT_RATIO)); + constant COUNTER_BITS : positive := log2ceil(integer(BIT_RATIO)); - TYPE T_MUX_INPUT IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(OUTPUT_BITS - 1 downto 0); + type T_MUX_INPUT is array (natural range <>) of std_logic_vector(OUTPUT_BITS - 1 downto 0); - signal WordBoundary : STD_LOGIC := '0'; - signal WordBoundary_d : STD_LOGIC := '0'; - signal Align : STD_LOGIC; + signal WordBoundary : std_logic := '0'; + signal WordBoundary_d : std_logic := '0'; + signal Align : std_logic; - signal Data_d : STD_LOGIC_VECTOR(INPUT_BITS - 1 downto 0) := (others => '0'); - signal DataIn : STD_LOGIC_VECTOR(INPUT_BITS - 1 downto 0); - signal DataOut_d : STD_LOGIC_VECTOR(OUTPUT_BITS - 1 downto 0) := (others => '0'); + signal Data_d : std_logic_vector(INPUT_BITS - 1 downto 0) := (others => '0'); + signal DataIn : std_logic_vector(INPUT_BITS - 1 downto 0); + signal DataOut_d : std_logic_vector(OUTPUT_BITS - 1 downto 0) := (others => '0'); signal MuxInput : T_MUX_INPUT(2**COUNTER_BITS - 1 downto 0); - signal MuxOutput : STD_LOGIC_VECTOR(OUTPUT_BITS - 1 downto 0); - signal MuxCounter_us : UNSIGNED(COUNTER_BITS - 1 downto 0) := (others => '0'); - signal MuxSelect_us : UNSIGNED(COUNTER_BITS - 1 downto 0); + signal MuxOutput : std_logic_vector(OUTPUT_BITS - 1 downto 0); + signal MuxCounter_us : unsigned(COUNTER_BITS - 1 downto 0) := (others => '0'); + signal MuxSelect_us : unsigned(COUNTER_BITS - 1 downto 0); begin assert (INPUT_BITS > OUTPUT_BITS) report "OUTPUT_BITS must be less than INPUT_BITS, otherwise it's no down-sizing gearbox." severity FAILURE; diff --git a/src/misc/gearbox/gearbox_up_cc.vhdl b/src/misc/gearbox/gearbox_up_cc.vhdl index 4eff8185..d90f8d82 100644 --- a/src/misc/gearbox/gearbox_up_cc.vhdl +++ b/src/misc/gearbox/gearbox_up_cc.vhdl @@ -1,14 +1,13 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: A upscaling gearbox module with a commonc clock (cc) interface. +-- Entity: A upscaling gearbox module with a commonc clock (cc) interface. -- -- Description: --- ------------------------------------ +-- ------------------------------------- -- This module provides a downscaling gearbox with a common clock (cc) -- interface. It perfoems a 'byte' to 'word' collection. The default order is -- LITTLE_ENDIAN (starting at byte(0)). Input "In_Data" and output "Out_Data" @@ -16,7 +15,7 @@ -- can be added by enabling (ADD_***PUT_REGISTERS = TRUE). -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -31,7 +30,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.std_logic_1164.all; @@ -46,72 +45,72 @@ use PoC.components.all; entity gearbox_up_cc is generic ( - INPUT_BITS : POSITIVE := 24; - OUTPUT_BITS : POSITIVE := 32; - META_BITS : NATURAL := 0; - ADD_INPUT_REGISTERS : BOOLEAN := FALSE; - ADD_OUTPUT_REGISTERS : BOOLEAN := FALSE + INPUT_BITS : positive := 24; + OUTPUT_BITS : positive := 32; + META_BITS : natural := 0; + ADD_INPUT_REGISTERS : boolean := FALSE; + ADD_OUTPUT_REGISTERS : boolean := FALSE ); port ( - Clock : in STD_LOGIC; - - In_Sync : in STD_LOGIC; - In_Valid : in STD_LOGIC; - In_Data : in STD_LOGIC_VECTOR(INPUT_BITS - 1 downto 0); - In_Meta : in STD_LOGIC_VECTOR(META_BITS - 1 downto 0); - - Out_Sync : out STD_LOGIC; - Out_Valid : out STD_LOGIC; - Out_Data : out STD_LOGIC_VECTOR(OUTPUT_BITS - 1 downto 0); - Out_Meta : out STD_LOGIC_VECTOR(META_BITS - 1 downto 0); - Out_First : out STD_LOGIC; - Out_Last : out STD_LOGIC + Clock : in std_logic; + + In_Sync : in std_logic; + In_Valid : in std_logic; + In_Data : in std_logic_vector(INPUT_BITS - 1 downto 0); + In_Meta : in std_logic_vector(META_BITS - 1 downto 0); + + Out_Sync : out std_logic; + Out_Valid : out std_logic; + Out_Data : out std_logic_vector(OUTPUT_BITS - 1 downto 0); + Out_Meta : out std_logic_vector(META_BITS - 1 downto 0); + Out_First : out std_logic; + Out_Last : out std_logic ); end entity; architecture rtl of gearbox_up_cc is - constant C_VERBOSE : BOOLEAN := FALSE; --POC_VERBOSE; + constant C_VERBOSE : boolean := FALSE; --POC_VERBOSE; - constant BITS_PER_CHUNK : POSITIVE := greatestCommonDivisor(INPUT_BITS, OUTPUT_BITS); - constant INPUT_CHUNKS : POSITIVE := INPUT_BITS / BITS_PER_CHUNK; - constant OUTPUT_CHUNKS : POSITIVE := OUTPUT_BITS / BITS_PER_CHUNK; - constant STAGES : POSITIVE := div_ceil(OUTPUT_CHUNKS, INPUT_CHUNKS); + constant BITS_PER_CHUNK : positive := greatestCommonDivisor(INPUT_BITS, OUTPUT_BITS); + constant INPUT_CHUNKS : positive := INPUT_BITS / BITS_PER_CHUNK; + constant OUTPUT_CHUNKS : positive := OUTPUT_BITS / BITS_PER_CHUNK; + constant STAGES : positive := div_ceil(OUTPUT_CHUNKS, INPUT_CHUNKS); - subtype T_CHUNK is STD_LOGIC_VECTOR(BITS_PER_CHUNK - 1 downto 0); - type T_CHUNK_VECTOR is array(NATURAL range <>) of T_CHUNK; - type T_BUFFER_MATRIX is array(NATURAL range <>) of T_CHUNK_VECTOR(INPUT_CHUNKS - 1 downto 0); + subtype T_CHUNK is std_logic_vector(BITS_PER_CHUNK - 1 downto 0); + type T_CHUNK_VECTOR is array(natural range <>) of T_CHUNK; + type T_BUFFER_MATRIX is array(natural range <>) of T_CHUNK_VECTOR(INPUT_CHUNKS - 1 downto 0); - subtype T_STAGE_INDEX is INTEGER range 0 to STAGES; - subtype T_MUX_INDEX is INTEGER range 0 to INPUT_CHUNKS - 1; + subtype T_STAGE_INDEX is integer range 0 to STAGES; + subtype T_MUX_INDEX is integer range 0 to INPUT_CHUNKS - 1; type T_MUX_INPUT is record Index : T_MUX_INDEX; Stage : T_STAGE_INDEX; end record; - type T_MUX_INPUT_LIST is array(NATURAL range <>) of T_MUX_INPUT; - type T_MUX_DESCRIPTIONS is array(NATURAL range <>) of T_MUX_INPUT_LIST(0 to OUTPUT_CHUNKS - 1); + type T_MUX_INPUT_LIST is array(natural range <>) of T_MUX_INPUT; + type T_MUX_DESCRIPTIONS is array(natural range <>) of T_MUX_INPUT_LIST(0 to OUTPUT_CHUNKS - 1); type T_COUNTER_STRUCT is record - First : STD_LOGIC; - Valid : STD_LOGIC; - Last : STD_LOGIC; - Reg_en : STD_LOGIC; + First : std_logic; + Valid : std_logic; + Last : std_logic; + Reg_en : std_logic; Reg_Stage : T_STAGE_INDEX; end record; - type T_COUNTER_DESCRIPTIONS is array(NATURAL range <>) of T_COUNTER_STRUCT; + type T_COUNTER_DESCRIPTIONS is array(natural range <>) of T_COUNTER_STRUCT; function genCounterDescription return T_COUNTER_DESCRIPTIONS is - variable First : STD_LOGIC; + variable First : std_logic; variable DESC : T_COUNTER_DESCRIPTIONS(0 to OUTPUT_CHUNKS - 1); begin First := '1'; - if (C_VERBOSE = TRUE) then + if C_VERBOSE then report "genCounterDescription:" & - " INPUT_CHUNKS=" & INTEGER'image(INPUT_CHUNKS) & - " OUTPUT_CHUNKS=" & INTEGER'image(OUTPUT_CHUNKS) & - " STAGES=" & INTEGER'image(STAGES) + " INPUT_CHUNKS=" & integer'image(INPUT_CHUNKS) & + " OUTPUT_CHUNKS=" & integer'image(OUTPUT_CHUNKS) & + " STAGES=" & integer'image(STAGES) severity NOTE; end if; for i in 0 to STAGES - 1 loop @@ -122,15 +121,15 @@ architecture rtl of gearbox_up_cc is DESC(i).Last := to_sl(i = (OUTPUT_CHUNKS - 1)); First := First and not DESC(i).First; - if (C_VERBOSE = TRUE) then - report " i: " & INTEGER'image(i) & - " en=" & STD_LOGIC'image(DESC(i).Reg_en) & - " stg=" & INTEGER'image(DESC(i).Reg_Stage) & - " vld=" & STD_LOGIC'image(DESC(i).Valid) + if C_VERBOSE then + report " i: " & integer'image(i) & + " en=" & std_logic'image(DESC(i).Reg_en) & + " stg=" & integer'image(DESC(i).Reg_Stage) & + " vld=" & std_logic'image(DESC(i).Valid) severity NOTE; end if; end loop; - if (C_VERBOSE and (STAGES < OUTPUT_CHUNKS)) then report "----------------------------------------" severity NOTE; end if; + if C_VERBOSE and (STAGES < OUTPUT_CHUNKS) then report "----------------------------------------" severity NOTE; end if; for i in STAGES to OUTPUT_CHUNKS - 1 loop DESC(i).Reg_en := to_sl(i /= (OUTPUT_CHUNKS - 1)); DESC(i).Reg_Stage := i mod STAGES; @@ -139,11 +138,11 @@ architecture rtl of gearbox_up_cc is DESC(i).Last := to_sl(i = (OUTPUT_CHUNKS - 1)); First := First and not DESC(i).First; - if (C_VERBOSE = TRUE) then - report " i: " & INTEGER'image(i) & - " en=" & STD_LOGIC'image(DESC(i).Reg_en) & - " stg=" & INTEGER'image(DESC(i).Reg_Stage) & - " vld=" & STD_LOGIC'image(DESC(i).Valid) + if C_VERBOSE then + report " i: " & integer'image(i) & + " en=" & std_logic'image(DESC(i).Reg_en) & + " stg=" & integer'image(DESC(i).Reg_Stage) & + " vld=" & std_logic'image(DESC(i).Valid) severity NOTE; end if; end loop; @@ -155,26 +154,26 @@ architecture rtl of gearbox_up_cc is variable k : T_MUX_INDEX; variable s : T_STAGE_INDEX; begin - if (C_VERBOSE = TRUE) then + if C_VERBOSE then report "genMuxDescription:" & - " INPUT_CHUNKS=" & INTEGER'image(INPUT_CHUNKS) & - " OUTPUT_CHUNKS=" & INTEGER'image(OUTPUT_CHUNKS) & - " STAGES=" & INTEGER'image(STAGES) + " INPUT_CHUNKS=" & integer'image(INPUT_CHUNKS) & + " OUTPUT_CHUNKS=" & integer'image(OUTPUT_CHUNKS) & + " STAGES=" & integer'image(STAGES) severity NOTE; end if; k := INPUT_CHUNKS - 1; for i in 0 to INPUT_CHUNKS - 1 loop s := ite((i = 0), STAGES, 0); - if (C_VERBOSE = TRUE) then report " Mux " & INTEGER'image(i) severity NOTE; end if; + if C_VERBOSE then report " Mux " & integer'image(i) severity NOTE; end if; for j in 0 to OUTPUT_CHUNKS - 1 loop s := ite(((k + 1) = INPUT_CHUNKS), (s + 1) mod (STAGES + 1), s); k := (k + 1) mod INPUT_CHUNKS; DESC(i)(j).Stage := s; DESC(i)(j).Index := k; - if (C_VERBOSE = TRUE) then - report " port: " & INTEGER'image(j) & - " idx=" & INTEGER'image(DESC(i)(j).Stage) & - " stg=" & INTEGER'image(DESC(i)(j).Index) + if C_VERBOSE then + report " port: " & integer'image(j) & + " idx=" & integer'image(DESC(i)(j).Stage) & + " stg=" & integer'image(DESC(i)(j).Index) severity NOTE; end if; end loop; @@ -187,8 +186,8 @@ architecture rtl of gearbox_up_cc is constant MUX_INPUT_TRANSLATION : T_MUX_DESCRIPTIONS := genMuxDescription; -- create vector-vector from vector (4 bit) - function to_chunkv(slv : STD_LOGIC_VECTOR) return T_CHUNK_VECTOR is - constant CHUNKS : POSITIVE := slv'length / BITS_PER_CHUNK; + function to_chunkv(slv : std_logic_vector) return T_CHUNK_VECTOR is + constant CHUNKS : positive := slv'length / BITS_PER_CHUNK; variable Result : T_CHUNK_VECTOR(CHUNKS - 1 downto 0); begin if ((slv'length mod BITS_PER_CHUNK) /= 0) then report "to_chunkv: width mismatch - slv'length is no multiple of BITS_PER_CHUNK (slv'length=" & INTEGER'image(slv'length) & "; BITS_PER_CHUNK=" & INTEGER'image(BITS_PER_CHUNK) & ")" severity FAILURE; end if; @@ -200,8 +199,8 @@ architecture rtl of gearbox_up_cc is end function; -- convert vector-vector to flatten vector - function to_slv(slvv : T_CHUNK_VECTOR) return STD_LOGIC_VECTOR is - variable slv : STD_LOGIC_VECTOR((slvv'length * BITS_PER_CHUNK) - 1 downto 0); + function to_slv(slvv : T_CHUNK_VECTOR) return std_logic_vector is + variable slv : std_logic_vector((slvv'length * BITS_PER_CHUNK) - 1 downto 0); begin for i in slvv'range loop slv(((i + 1) * BITS_PER_CHUNK) - 1 downto (i * BITS_PER_CHUNK)) := slvv(i); @@ -209,49 +208,49 @@ architecture rtl of gearbox_up_cc is return slv; end function; - signal In_Sync_d : STD_LOGIC := '0'; - signal In_Data_d : STD_LOGIC_VECTOR(INPUT_BITS - 1 downto 0) := (others => '0'); - signal In_Meta_d : STD_LOGIC_VECTOR(META_BITS - 1 downto 0) := (others => '0'); - signal In_Valid_d : STD_LOGIC := '0'; + signal In_Sync_d : std_logic := '0'; + signal In_Data_d : std_logic_vector(INPUT_BITS - 1 downto 0) := (others => '0'); + signal In_Meta_d : std_logic_vector(META_BITS - 1 downto 0) := (others => '0'); + signal In_Valid_d : std_logic := '0'; - signal StageSelect_rst : STD_LOGIC; - signal StageSelect_en : STD_LOGIC; - signal StageSelect_us : UNSIGNED(log2ceilnz(OUTPUT_CHUNKS) - 1 downto 0) := (others => '0'); - signal StageSelect_ov : STD_LOGIC; + signal StageSelect_rst : std_logic; + signal StageSelect_en : std_logic; + signal StageSelect_us : unsigned(log2ceilnz(OUTPUT_CHUNKS) - 1 downto 0) := (others => '0'); + signal StageSelect_ov : std_logic; - signal MuxSelect_rst : STD_LOGIC; - signal MuxSelect_en : STD_LOGIC; - signal MuxSelect_us : UNSIGNED(log2ceilnz(INPUT_CHUNKS) - 1 downto 0) := (others => '0'); - signal MuxSelect_ov : STD_LOGIC; + signal MuxSelect_rst : std_logic; + signal MuxSelect_en : std_logic; + signal MuxSelect_us : unsigned(log2ceilnz(INPUT_CHUNKS) - 1 downto 0) := (others => '0'); + signal MuxSelect_ov : std_logic; signal GearBoxInput : T_CHUNK_VECTOR(INPUT_CHUNKS - 1 downto 0); - signal GearBoxBuffer_en : STD_LOGIC; + signal GearBoxBuffer_en : std_logic; signal GearBoxBuffer : T_BUFFER_MATRIX(STAGES - 1 downto 0) := (others => (others => (others => '0'))); - signal MetaBuffer : STD_LOGIC_VECTOR(META_BITS - 1 downto 0) := (others => '0'); + signal MetaBuffer : std_logic_vector(META_BITS - 1 downto 0) := (others => '0'); signal GearBoxOutput : T_CHUNK_VECTOR(OUTPUT_CHUNKS - 1 downto 0); - signal SyncOut : STD_LOGIC; - signal ValidOut : STD_LOGIC; - signal DataOut : STD_LOGIC_VECTOR(OUTPUT_BITS - 1 downto 0); - signal MetaOut : STD_LOGIC_VECTOR(META_BITS - 1 downto 0); - signal FirstOut : STD_LOGIC; - signal LastOut : STD_LOGIC; + signal SyncOut : std_logic; + signal ValidOut : std_logic; + signal DataOut : std_logic_vector(OUTPUT_BITS - 1 downto 0); + signal MetaOut : std_logic_vector(META_BITS - 1 downto 0); + signal FirstOut : std_logic; + signal LastOut : std_logic; - signal Out_Sync_d : STD_LOGIC := '0'; - signal Out_Valid_d : STD_LOGIC := '0'; - signal Out_Data_d : STD_LOGIC_VECTOR(OUTPUT_BITS - 1 downto 0) := (others => '0'); - signal Out_Meta_d : STD_LOGIC_VECTOR(META_BITS - 1 downto 0) := (others => '0'); - signal Out_First_d : STD_LOGIC := '0'; - signal Out_Last_d : STD_LOGIC := '0'; + signal Out_Sync_d : std_logic := '0'; + signal Out_Valid_d : std_logic := '0'; + signal Out_Data_d : std_logic_vector(OUTPUT_BITS - 1 downto 0) := (others => '0'); + signal Out_Meta_d : std_logic_vector(META_BITS - 1 downto 0) := (others => '0'); + signal Out_First_d : std_logic := '0'; + signal Out_Last_d : std_logic := '0'; begin assert (not C_VERBOSE) - report "gearbox_up_cc:" & CR & - " INPUT_BITS=" & INTEGER'image(INPUT_BITS) & - " OUTPUT_BITS=" & INTEGER'image(OUTPUT_BITS) & - " INPUT_CHUNKS=" & INTEGER'image(INPUT_CHUNKS) & - " OUTPUT_CHUNKS=" & INTEGER'image(OUTPUT_CHUNKS) & - " BITS_PER_CHUNK=" & INTEGER'image(BITS_PER_CHUNK) + report "gearbox_up_cc:" & LF & + " INPUT_BITS=" & integer'image(INPUT_BITS) & + " OUTPUT_BITS=" & integer'image(OUTPUT_BITS) & + " INPUT_CHUNKS=" & integer'image(INPUT_CHUNKS) & + " OUTPUT_CHUNKS=" & integer'image(OUTPUT_CHUNKS) & + " BITS_PER_CHUNK=" & integer'image(BITS_PER_CHUNK) severity NOTE; assert (INPUT_BITS < OUTPUT_BITS) report "INPUT_BITS must be less than OUTPUT_BITS, otherwise it's no up-sizing gearbox." severity FAILURE; diff --git a/src/misc/gearbox/gearbox_up_dc.vhdl b/src/misc/gearbox/gearbox_up_dc.vhdl index 75b8b8d9..9345ea59 100644 --- a/src/misc/gearbox/gearbox_up_dc.vhdl +++ b/src/misc/gearbox/gearbox_up_dc.vhdl @@ -1,14 +1,13 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: An upscaling gearbox module with a dependent clock (dc) interface. +-- Entity: An upscaling gearbox module with a dependent clock (dc) interface. -- -- Description: --- ------------------------------------ +-- ------------------------------------- -- This module provides a upscaling gearbox with a dependent clock (dc) -- interface. It perfoems a 'byte' to 'word' collection. The default order is -- LITTLE_ENDIAN (starting at byte(0)). Input "In_Data" is of clock domain @@ -22,7 +21,7 @@ -- - Clock1 and Clock2 MUST be phase aligned (related) to each other. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -37,7 +36,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; @@ -51,37 +50,37 @@ use PoC.components.all; entity gearbox_up_dc is generic ( - INPUT_BITS : POSITIVE := 8; -- input bit width + INPUT_BITS : positive := 8; -- input bit width INPUT_ORDER : T_BIT_ORDER := LSB_FIRST; -- LSB_FIRST: start at byte(0), MSB_FIRST: start at byte(n-1) - OUTPUT_BITS : POSITIVE := 32; -- output bit width - ADD_INPUT_REGISTERS : BOOLEAN := FALSE -- add input register @Clock1 + OUTPUT_BITS : positive := 32; -- output bit width + ADD_INPUT_REGISTERS : boolean := FALSE -- add input register @Clock1 ); port ( - Clock1 : in STD_LOGIC; -- input clock domain - Clock2 : in STD_LOGIC; -- output clock domain - In_Align : in STD_LOGIC; -- align word (one cycle high impulse) - In_Data : in STD_LOGIC_VECTOR(INPUT_BITS - 1 downto 0); -- input word - Out_Data : out STD_LOGIC_VECTOR(OUTPUT_BITS - 1 downto 0); -- output word - Out_Valid : out STD_LOGIC -- output is valid + Clock1 : in std_logic; -- input clock domain + Clock2 : in std_logic; -- output clock domain + In_Align : in std_logic; -- align word (one cycle high impulse) + In_Data : in std_logic_vector(INPUT_BITS - 1 downto 0); -- input word + Out_Data : out std_logic_vector(OUTPUT_BITS - 1 downto 0); -- output word + Out_Valid : out std_logic -- output is valid ); end entity; -architecture rtl OF gearbox_up_dc is +architecture rtl of gearbox_up_dc is constant BIT_RATIO : REAL := real(OUTPUT_BITS) / real(INPUT_BITS); - constant INPUT_CHUNKS : POSITIVE := integer(BIT_RATIO); - constant BITS_PER_CHUNK : POSITIVE := INPUT_BITS; + constant INPUT_CHUNKS : positive := integer(BIT_RATIO); + constant BITS_PER_CHUNK : positive := INPUT_BITS; - constant COUNTER_MAX : POSITIVE := INPUT_CHUNKS - 1; - constant COUNTER_BITS : POSITIVE := log2ceil(COUNTER_MAX + 1); + constant COUNTER_MAX : positive := INPUT_CHUNKS - 1; + constant COUNTER_BITS : positive := log2ceil(COUNTER_MAX + 1); - subtype T_CHUNK is STD_LOGIC_VECTOR(BITS_PER_CHUNK - 1 downto 0); - type T_CHUNK_VECTOR is array(NATURAL range <>) of T_CHUNK; + subtype T_CHUNK is std_logic_vector(BITS_PER_CHUNK - 1 downto 0); + type T_CHUNK_VECTOR is array(natural range <>) of T_CHUNK; -- convert chunk-vector to flatten vector - function to_slv(slvv : T_CHUNK_VECTOR) return STD_LOGIC_VECTOR is - variable slv : STD_LOGIC_VECTOR((slvv'length * BITS_PER_CHUNK) - 1 downto 0); + function to_slv(slvv : T_CHUNK_VECTOR) return std_logic_vector is + variable slv : std_logic_vector((slvv'length * BITS_PER_CHUNK) - 1 downto 0); begin for i in slvv'range loop slv(((i + 1) * BITS_PER_CHUNK) - 1 downto i * BITS_PER_CHUNK) := slvv(i); @@ -89,30 +88,32 @@ architecture rtl OF gearbox_up_dc is return slv; end function; - signal Counter_us : UNSIGNED(COUNTER_BITS - 1 downto 0) := (others => '0'); - signal Select_us : UNSIGNED(COUNTER_BITS - 1 downto 0); + signal Counter_us : unsigned(COUNTER_BITS - 1 downto 0) := (others => '0'); + signal Select_us : unsigned(COUNTER_BITS - 1 downto 0); - signal In_Data_d : STD_LOGIC_VECTOR(INPUT_BITS - 1 downto 0) := (others => '0'); + signal In_Data_d : std_logic_vector(INPUT_BITS - 1 downto 0) := (others => '0'); + signal In_Align_d : std_logic; signal Data_d : T_CHUNK_VECTOR(INPUT_CHUNKS - 2 downto 0) := (others => (others => '0')); - signal Collected : STD_LOGIC_VECTOR(OUTPUT_BITS - 1 downto 0); - signal Collected_swapped : STD_LOGIC_VECTOR(OUTPUT_BITS - 1 downto 0); - signal Collected_en : STD_LOGIC; - signal Collected_d : STD_LOGIC_VECTOR(OUTPUT_BITS - 1 downto 0) := (others => '0'); - signal DataOut_d : STD_LOGIC_VECTOR(OUTPUT_BITS - 1 downto 0) := (others => '0'); - - signal Valid_r : STD_LOGIC := '0'; - signal Valid_d : STD_LOGIC := '0'; + signal Collected : std_logic_vector(OUTPUT_BITS - 1 downto 0); + signal Collected_swapped : std_logic_vector(OUTPUT_BITS - 1 downto 0); + signal Collected_en : std_logic; + signal Collected_d : std_logic_vector(OUTPUT_BITS - 1 downto 0) := (others => '0'); + signal DataOut_d : std_logic_vector(OUTPUT_BITS - 1 downto 0) := (others => '0'); + + signal Valid_r : std_logic := '0'; + signal Valid_d : std_logic := '0'; begin assert (INPUT_BITS < OUTPUT_BITS) report "INPUT_BITS must be less than OUTPUT_BITS, otherwise it's no up-sizing gearbox." severity FAILURE; -- input register @Clock1 - In_Data_d <= In_Data when registered(Clock1, ADD_INPUT_REGISTERS); + In_Align_d <= In_Align when registered(Clock1, ADD_INPUT_REGISTERS); + In_Data_d <= In_Data when registered(Clock1, ADD_INPUT_REGISTERS); -- byte alignment counter @Clock1 process(Clock1) begin if rising_edge(Clock1) then - if (In_Align = '1') then + if (In_Align_d = '1') then Counter_us <= to_unsigned(1, Counter_us'length); Valid_r <= '0'; elsif (upcounter_equal(cnt => Counter_us, value => COUNTER_MAX) = '1') then @@ -124,14 +125,14 @@ begin end if; end process; - Select_us <= mux(In_Align, Counter_us, (Counter_us'range => '0')); + Select_us <= mux(In_Align_d, Counter_us, (Counter_us'range => '0')); -- delay registers @Clock1 process(Clock1) begin if rising_edge(Clock1) then for j in 0 to INPUT_CHUNKS - 2 loop - if (j = to_index(Select_us, COUNTER_MAX)) then -- D-FF enable + if j = to_index(Select_us, COUNTER_MAX) then -- D-FF enable Data_d(j) <= In_Data_d; end if; end loop; diff --git a/src/misc/misc_Delay.vhdl b/src/misc/misc_Delay.vhdl index a01faa2a..64c296d0 100644 --- a/src/misc/misc_Delay.vhdl +++ b/src/misc/misc_Delay.vhdl @@ -1,15 +1,14 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Patrick Lehmann -- --- Package: TODO +-- Entity: TODO -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: -- ============================================================================= @@ -38,23 +37,23 @@ use PoC.vectors.all; entity misc_Delay is generic ( - BITS : POSITIVE; + BITS : positive; TAPS : T_NATVEC -- select one or multiple delay tap points ); port ( - Clock : in STD_LOGIC; -- clock - Reset : in STD_LOGIC := '0'; -- reset; avoid reset to enable SRL16/SRL32 usage - Enable : in STD_LOGIC := '1'; -- enable - DataIn : in STD_LOGIC_VECTOR(BITS - 1 downto 0); -- data to delay + Clock : in std_logic; -- clock + Reset : in std_logic := '0'; -- reset; avoid reset to enable SRL16/SRL32 usage + Enable : in std_logic := '1'; -- enable + DataIn : in std_logic_vector(BITS - 1 downto 0); -- data to delay DataOut : out T_SLM(TAPS'length - 1 downto 0, BITS - 1 downto 0) -- delayed ouputs, tapped at TAPS(i) ); -end; +end entity; architecture rtl of misc_Delay is - constant MAX_DELAY : NATURAL := imax(TAPS); + constant MAX_DELAY : natural := imax(TAPS); - type T_DELAY_VECTOR is array (NATURAL range <>) of STD_LOGIC_VECTOR(BITS - 1 downto 0); + type T_DELAY_VECTOR is array (natural range <>) of std_logic_vector(BITS - 1 downto 0); signal Shifter_nxt : T_DELAY_VECTOR(MAX_DELAY downto 0); signal Shifter_d : T_DELAY_VECTOR(MAX_DELAY - 1 downto 0) := (others => (others => '0')); @@ -79,4 +78,4 @@ begin end generate; DataOut <= DataOut_i; -end; \ No newline at end of file +end; diff --git a/src/misc/misc_FrequencyMeasurement.vhdl b/src/misc/misc_FrequencyMeasurement.vhdl index d3d8a34d..3fdbc3e1 100644 --- a/src/misc/misc_FrequencyMeasurement.vhdl +++ b/src/misc/misc_FrequencyMeasurement.vhdl @@ -1,18 +1,16 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Patrick Lehmann -- --- Package: measures a input frequency relativ to a reference frequency +-- Entity: measures a input frequency relativ to a reference frequency -- -- Description: --- ------------------------------------ --- This module counts 1 second in a reference timer at reference clock. This --- reference time is used to start and stop a timer at input clock. The counter --- value is the measured frequency in Hz. --- +-- ------------------------------------- +-- This module counts 1 second in a reference timer at reference clock. This +-- reference time is used to start and stop a timer at input clock. The counter +-- value is the measured frequency in Hz. -- -- License: -- ============================================================================= @@ -48,38 +46,38 @@ entity misc_FrequencyMeasurement is REFERENCE_CLOCK_FREQ : FREQ := 100 MHz ); port ( - Reference_Clock : in STD_LOGIC; - Input_Clock : in STD_LOGIC; + Reference_Clock : in std_logic; + Input_Clock : in std_logic; - Start : in STD_LOGIC; - Done : out STD_LOGIC; + Start : in std_logic; + Done : out std_logic; Result : out T_SLV_32 ); end entity; architecture rtl of misc_FrequencyMeasurement is - constant TIMEBASE_COUNTER_MAX : POSITIVE := TimingToCycles(ite(SIMULATION, 10.0e-6, 1.0), REFERENCE_CLOCK_FREQ); - constant TIMEBASE_COUNTER_BITS : POSITIVE := log2ceilnz(TIMEBASE_COUNTER_MAX); + constant TIMEBASE_COUNTER_MAX : positive := TimingToCycles(ite(SIMULATION, 10.0e-6, 1.0), REFERENCE_CLOCK_FREQ); + constant TIMEBASE_COUNTER_BITS : positive := log2ceilnz(TIMEBASE_COUNTER_MAX); - signal TimeBase_Counter_rst : STD_LOGIC; - signal TimeBase_Counter_s : SIGNED(TIMEBASE_COUNTER_BITS downto 0) := to_signed(-1, TIMEBASE_COUNTER_BITS + 1); - signal TimeBase_Counter_nxt : SIGNED(TIMEBASE_COUNTER_BITS downto 0); - signal TimeBase_Counter_uf : STD_LOGIC; + signal TimeBase_Counter_rst : std_logic; + signal TimeBase_Counter_s : signed(TIMEBASE_COUNTER_BITS downto 0) := to_signed(-1, TIMEBASE_COUNTER_BITS + 1); + signal TimeBase_Counter_nxt : signed(TIMEBASE_COUNTER_BITS downto 0); + signal TimeBase_Counter_uf : std_logic; - signal Stop : STD_LOGIC; - signal sync_Start : STD_LOGIC; - signal sync_Stop : STD_LOGIC; + signal Stop : std_logic; + signal sync_Start : std_logic; + signal sync_Stop : std_logic; signal sync1_Busy : T_SLV_2; - signal Frequency_Counter_en_r : STD_LOGIC := '0'; - signal Frequency_Counter_us : UNSIGNED(31 downto 0) := (others => '0'); + signal Frequency_Counter_en_r : std_logic := '0'; + signal Frequency_Counter_us : unsigned(31 downto 0) := (others => '0'); - signal CaptureResult : STD_LOGIC; - signal CaptureResult_d : STD_LOGIC := '0'; - signal Result_en : STD_LOGIC; + signal CaptureResult : std_logic; + signal CaptureResult_d : std_logic := '0'; + signal Result_en : std_logic; signal Result_d : T_SLV_32 := (others => '0'); - signal Done_r : STD_LOGIC := '0'; + signal Done_r : std_logic := '0'; begin TimeBase_Counter_rst <= Start; diff --git a/src/misc/misc_bit_lz.vhdl b/src/misc/misc_bit_lz.vhdl index 16165419..c76e6824 100644 --- a/src/misc/misc_bit_lz.vhdl +++ b/src/misc/misc_bit_lz.vhdl @@ -1,8 +1,7 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- =========================================================================== +-- ============================================================================= -- Description: -- -- An LZ77-based bit stream compressor. @@ -41,10 +40,10 @@ -- -- COUNT_BITS <= OFFSET_BITS < 2**COUNT_BITS - COUNT_BITS -- --- =========================================================================== +-- ============================================================================= -- Authors: Thomas B. Preusser -- --- =========================================================================== +-- ============================================================================= -- References: -- -- Original Study @@ -63,7 +62,7 @@ -- arbeitenden LZ77-Woerterbuchansatzes", -- Fehlertolerante und energieeffiziente eingebettete Systeme: -- Methoden und Anwendungen (FEES 2015), Oct, 2015. --- =========================================================================== +-- ============================================================================= library IEEE; use IEEE.std_logic_1164.all; diff --git a/src/misc/stat/stat_Average.vhdl b/src/misc/stat/stat_Average.vhdl index 42b0014b..ef65907b 100644 --- a/src/misc/stat/stat_Average.vhdl +++ b/src/misc/stat/stat_Average.vhdl @@ -1,15 +1,14 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: Computes the overall average value of all data words +-- Entity: Computes the overall average value of all data words -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: -- ============================================================================= @@ -41,40 +40,40 @@ use PoC.arith.all; entity stat_Average is generic ( - DATA_BITS : POSITIVE := 8; - COUNTER_BITS : POSITIVE := 16 + DATA_BITS : positive := 8; + COUNTER_BITS : positive := 16 ); port ( - Clock : in STD_LOGIC; - Reset : in STD_LOGIC; + Clock : in std_logic; + Reset : in std_logic; - Enable : in STD_LOGIC; - DataIn : in STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0); + Enable : in std_logic; + DataIn : in std_logic_vector(DATA_BITS - 1 downto 0); - Count : out STD_LOGIC_VECTOR(COUNTER_BITS - 1 downto 0); - Sum : out STD_LOGIC_VECTOR(COUNTER_BITS - 1 downto 0); - Average : out STD_LOGIC_VECTOR(COUNTER_BITS - 1 downto 0); - Valid : out STD_LOGIC + Count : out std_logic_vector(COUNTER_BITS - 1 downto 0); + Sum : out std_logic_vector(COUNTER_BITS - 1 downto 0); + Average : out std_logic_vector(COUNTER_BITS - 1 downto 0); + Valid : out std_logic ); end entity; architecture rtl of stat_Average is - signal DataIn_us : UNSIGNED(DataIn'range); + signal DataIn_us : unsigned(DataIn'range); - signal Counter_i : STD_LOGIC_VECTOR(COUNTER_BITS - 1 downto 0); - signal Counter_us : UNSIGNED(COUNTER_BITS - 1 downto 0) := (others => '0'); + signal Counter_i : std_logic_vector(COUNTER_BITS - 1 downto 0); + signal Counter_us : unsigned(COUNTER_BITS - 1 downto 0) := (others => '0'); - signal Sum_i : STD_LOGIC_VECTOR(COUNTER_BITS - 1 downto 0); - signal Sum_us : UNSIGNED(COUNTER_BITS - 1 downto 0) := (others => '0'); + signal Sum_i : std_logic_vector(COUNTER_BITS - 1 downto 0); + signal Sum_us : unsigned(COUNTER_BITS - 1 downto 0) := (others => '0'); - signal Quotient : STD_LOGIC_VECTOR(COUNTER_BITS - 1 downto 0); - signal Valid_i : STD_LOGIC; + signal Quotient : std_logic_vector(COUNTER_BITS - 1 downto 0); + signal Valid_i : std_logic; - type T_SUM_VECTOR is array(NATURAL range <>) of STD_LOGIC_VECTOR(COUNTER_BITS - 1 downto 0); - type T_COUNT_VECTOR is array(NATURAL range <>) of STD_LOGIC_VECTOR(COUNTER_BITS - 1 downto 0); + type T_SUM_VECTOR is array(natural range <>) of std_logic_vector(COUNTER_BITS - 1 downto 0); + type T_COUNT_VECTOR is array(natural range <>) of std_logic_vector(COUNTER_BITS - 1 downto 0); - constant DELAY : POSITIVE := COUNTER_BITS - 1; + constant DELAY : positive := COUNTER_BITS - 1; signal Count_d : T_COUNT_VECTOR(DELAY downto 0) := (others => (others => '0')); signal Sum_d : T_SUM_VECTOR(DELAY downto 0) := (others => (others => '0')); diff --git a/src/misc/stat/stat_Histogram.vhdl b/src/misc/stat/stat_Histogram.vhdl index fbc08423..e7a5fbb6 100644 --- a/src/misc/stat/stat_Histogram.vhdl +++ b/src/misc/stat/stat_Histogram.vhdl @@ -1,15 +1,14 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: Creates a histogram of all input data +-- Entity: Creates a histogram of all input data -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: -- ============================================================================= @@ -40,15 +39,15 @@ use PoC.vectors.all; entity stat_Histogram is generic ( - DATA_BITS : POSITIVE := 16; - COUNTER_BITS : POSITIVE := 16 + DATA_BITS : positive := 16; + COUNTER_BITS : positive := 16 ); port ( - Clock : in STD_LOGIC; - Reset : in STD_LOGIC; + Clock : in std_logic; + Reset : in std_logic; - Enable : in STD_LOGIC; - DataIn : in STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0); + Enable : in std_logic; + DataIn : in std_logic_vector(DATA_BITS - 1 downto 0); Histogram : out T_SLM(2**DATA_BITS - 1 downto 0, COUNTER_BITS - 1 downto 0) ); @@ -56,7 +55,7 @@ end entity; architecture rtl of stat_Histogram is - type T_HISTOGRAM_MEMORY is array(NATURAL range <>) of UNSIGNED(COUNTER_BITS downto 0); + type T_HISTOGRAM_MEMORY is array(natural range <>) of unsigned(COUNTER_BITS downto 0); -- create matrix from vector-vector function to_slm(usv : T_HISTOGRAM_MEMORY) return T_SLM is diff --git a/src/misc/stat/stat_Maximum.vhdl b/src/misc/stat/stat_Maximum.vhdl index aa3fd4b7..0fec5823 100644 --- a/src/misc/stat/stat_Maximum.vhdl +++ b/src/misc/stat/stat_Maximum.vhdl @@ -1,15 +1,14 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: Counts the most significant data words +-- Entity: Counts the most significant data words -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: -- ============================================================================= @@ -40,18 +39,18 @@ use PoC.vectors.all; entity stat_Maximum is generic ( - DEPTH : POSITIVE := 8; - DATA_BITS : POSITIVE := 16; - COUNTER_BITS : POSITIVE := 16 + DEPTH : positive := 8; + DATA_BITS : positive := 16; + COUNTER_BITS : positive := 16 ); port ( - Clock : in STD_LOGIC; - Reset : in STD_LOGIC; + Clock : in std_logic; + Reset : in std_logic; - Enable : in STD_LOGIC; - DataIn : in STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0); + Enable : in std_logic; + DataIn : in std_logic_vector(DATA_BITS - 1 downto 0); - Valids : out STD_LOGIC_VECTOR(DEPTH - 1 downto 0); + Valids : out std_logic_vector(DEPTH - 1 downto 0); Maximums : out T_SLM(DEPTH - 1 downto 0, DATA_BITS - 1 downto 0); Counts : out T_SLM(DEPTH - 1 downto 0, COUNTER_BITS - 1 downto 0) ); @@ -59,8 +58,8 @@ end entity; architecture rtl of stat_Maximum is - type T_TAG_MEMORY is array(NATURAL range <>) of UNSIGNED(DATA_BITS - 1 downto 0); - type T_COUNTER_MEMORY is array(NATURAL range <>) of UNSIGNED(COUNTER_BITS - 1 downto 0); + type T_TAG_MEMORY is array(natural range <>) of unsigned(DATA_BITS - 1 downto 0); + type T_COUNTER_MEMORY is array(natural range <>) of unsigned(COUNTER_BITS - 1 downto 0); -- create matrix from vector-vector function to_slm(usv : T_TAG_MEMORY) return T_SLM is @@ -85,14 +84,14 @@ architecture rtl of stat_Maximum is return slm; end function; - signal DataIn_us : UNSIGNED(DataIn'range); + signal DataIn_us : unsigned(DataIn'range); - signal TagHit : STD_LOGIC_VECTOR(DEPTH - 1 downto 0); - signal MaximumHit : STD_LOGIC_VECTOR(DEPTH - 1 downto 0); + signal TagHit : std_logic_vector(DEPTH - 1 downto 0); + signal MaximumHit : std_logic_vector(DEPTH - 1 downto 0); signal TagMemory : T_TAG_MEMORY(DEPTH - 1 downto 0) := (others => (others => '0')); signal CounterMemory : T_COUNTER_MEMORY(DEPTH - 1 downto 0) := (others => (others => '0')); - signal MaximumIndex : STD_LOGIC_VECTOR(DEPTH - 1 downto 0) := '1' & (DEPTH - 2 downto 0 => '0'); --((DEPTH - 1) => '1', others => '0'); -- WORKAROUND: GHDL says not static choice exclude others choice; non-locally static choice for an aggregate is allowed only if only choice - signal ValidMemory : STD_LOGIC_VECTOR(DEPTH - 1 downto 0) := (others => '0'); + signal MaximumIndex : std_logic_vector(DEPTH - 1 downto 0) := '1' & (DEPTH - 2 downto 0 => '0'); --((DEPTH - 1) => '1', others => '0'); -- WORKAROUND: GHDL says not static choice exclude others choice; non-locally static choice for an aggregate is allowed only if only choice + signal ValidMemory : std_logic_vector(DEPTH - 1 downto 0) := (others => '0'); begin DataIn_us <= unsigned(DataIn); @@ -103,7 +102,7 @@ begin end generate; process(Clock) - variable TagHit_idx : NATURAL; + variable TagHit_idx : natural; begin if rising_edge(Clock) then if (Reset = '1') then diff --git a/src/misc/stat/stat_Minimum.vhdl b/src/misc/stat/stat_Minimum.vhdl index 7b01d4c9..5651278c 100644 --- a/src/misc/stat/stat_Minimum.vhdl +++ b/src/misc/stat/stat_Minimum.vhdl @@ -1,15 +1,14 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: Counts the least significant data words +-- Entity: Counts the least significant data words -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: -- ============================================================================= @@ -40,18 +39,18 @@ use PoC.vectors.all; entity stat_Minimum is generic ( - DEPTH : POSITIVE := 8; - DATA_BITS : POSITIVE := 16; - COUNTER_BITS : POSITIVE := 16 + DEPTH : positive := 8; + DATA_BITS : positive := 16; + COUNTER_BITS : positive := 16 ); port ( - Clock : in STD_LOGIC; - Reset : in STD_LOGIC; + Clock : in std_logic; + Reset : in std_logic; - Enable : in STD_LOGIC; - DataIn : in STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0); + Enable : in std_logic; + DataIn : in std_logic_vector(DATA_BITS - 1 downto 0); - Valids : out STD_LOGIC_VECTOR(DEPTH - 1 downto 0); + Valids : out std_logic_vector(DEPTH - 1 downto 0); Minimums : out T_SLM(DEPTH - 1 downto 0, DATA_BITS - 1 downto 0); Counts : out T_SLM(DEPTH - 1 downto 0, COUNTER_BITS - 1 downto 0) ); @@ -59,8 +58,8 @@ end entity; architecture rtl of stat_Minimum is - type T_TAG_MEMORY is array(NATURAL range <>) of UNSIGNED(DATA_BITS - 1 downto 0); - type T_COUNTER_MEMORY is array(NATURAL range <>) of UNSIGNED(COUNTER_BITS - 1 downto 0); + type T_TAG_MEMORY is array(natural range <>) of unsigned(DATA_BITS - 1 downto 0); + type T_COUNTER_MEMORY is array(natural range <>) of unsigned(COUNTER_BITS - 1 downto 0); -- create matrix from vector-vector function to_slm(usv : T_TAG_MEMORY) return T_SLM is @@ -85,14 +84,14 @@ architecture rtl of stat_Minimum is return slm; end function; - signal DataIn_us : UNSIGNED(DataIn'range); + signal DataIn_us : unsigned(DataIn'range); - signal TagHit : STD_LOGIC_VECTOR(DEPTH - 1 downto 0); - signal MinimumHit : STD_LOGIC_VECTOR(DEPTH - 1 downto 0); + signal TagHit : std_logic_vector(DEPTH - 1 downto 0); + signal MinimumHit : std_logic_vector(DEPTH - 1 downto 0); signal TagMemory : T_TAG_MEMORY(DEPTH - 1 downto 0) := (others => (others => '1')); signal CounterMemory : T_COUNTER_MEMORY(DEPTH - 1 downto 0) := (others => (others => '0')); - signal MinimumIndex : STD_LOGIC_VECTOR(DEPTH - 1 downto 0) := '1' & (DEPTH - 2 downto 0 => '0'); --((DEPTH - 1) => '1', others => '0'); -- WORKAROUND: GHDL says not static choice exclude others choice; non-locally static choice for an aggregate is allowed only if only choice - signal ValidMemory : STD_LOGIC_VECTOR(DEPTH - 1 downto 0) := (others => '0'); + signal MinimumIndex : std_logic_vector(DEPTH - 1 downto 0) := '1' & (DEPTH - 2 downto 0 => '0'); --((DEPTH - 1) => '1', others => '0'); -- WORKAROUND: GHDL says not static choice exclude others choice; non-locally static choice for an aggregate is allowed only if only choice + signal ValidMemory : std_logic_vector(DEPTH - 1 downto 0) := (others => '0'); begin DataIn_us <= unsigned(DataIn); @@ -103,7 +102,7 @@ begin end generate; process(Clock) - variable TagHit_idx : NATURAL; + variable TagHit_idx : natural; begin if rising_edge(Clock) then if (Reset = '1') then diff --git a/src/misc/sync/sync.pkg.vhdl b/src/misc/sync/sync.pkg.vhdl index 973ffdae..792021d4 100644 --- a/src/misc/sync/sync.pkg.vhdl +++ b/src/misc/sync/sync.pkg.vhdl @@ -1,19 +1,18 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- -- Package: VHDL package for component declarations, types and -- functions associated to the PoC.misc.sync namespace -- -- Description: --- ------------------------------------ +-- ------------------------------------- -- For detailed documentation see below. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -28,7 +27,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -36,44 +35,44 @@ use IEEE.NUMERIC_STD.all; package sync is - subtype T_MISC_SYNC_DEPTH is INTEGER range 2 to 16; + subtype T_MISC_SYNC_DEPTH is integer range 2 to 16; component sync_Bits is generic ( - BITS : POSITIVE := 1; -- number of bit to be synchronized - INIT : STD_LOGIC_VECTOR := x"00000000"; -- initialitation bits + BITS : positive := 1; -- number of bit to be synchronized + INIT : std_logic_vector := x"00000000"; -- initialitation bits SYNC_DEPTH : T_MISC_SYNC_DEPTH := 2 -- generate SYNC_DEPTH many stages, at least 2 ); port ( - Clock : in STD_LOGIC; -- output clock domain - Input : in STD_LOGIC_VECTOR(BITS - 1 downto 0); -- @async: input bits - Output : out STD_LOGIC_VECTOR(BITS - 1 downto 0) -- @Clock: output bits + Clock : in std_logic; -- output clock domain + Input : in std_logic_vector(BITS - 1 downto 0); -- @async: input bits + Output : out std_logic_vector(BITS - 1 downto 0) -- @Clock: output bits ); end component; component sync_Bits_Altera is generic ( - BITS : POSITIVE := 1; -- number of bit to be synchronized - INIT : STD_LOGIC_VECTOR := x"00000000"; -- initialitation bits + BITS : positive := 1; -- number of bit to be synchronized + INIT : std_logic_vector := x"00000000"; -- initialitation bits SYNC_DEPTH : T_MISC_SYNC_DEPTH := 2 -- generate SYNC_DEPTH many stages, at least 2 ); port ( - Clock : in STD_LOGIC; -- Clock to be synchronized to - Input : in STD_LOGIC_VECTOR(BITS - 1 downto 0); -- Data to be synchronized - Output : out STD_LOGIC_VECTOR(BITS - 1 downto 0) -- synchronised data + Clock : in std_logic; -- Clock to be synchronized to + Input : in std_logic_vector(BITS - 1 downto 0); -- Data to be synchronized + Output : out std_logic_vector(BITS - 1 downto 0) -- synchronised data ); end component; component sync_Bits_Xilinx is generic ( - BITS : POSITIVE := 1; -- number of bit to be synchronized - INIT : STD_LOGIC_VECTOR := x"00000000"; -- initialitation bits + BITS : positive := 1; -- number of bit to be synchronized + INIT : std_logic_vector := x"00000000"; -- initialitation bits SYNC_DEPTH : T_MISC_SYNC_DEPTH := 2 -- generate SYNC_DEPTH many stages, at least 2 ); port ( - Clock : in STD_LOGIC; -- Clock to be synchronized to - Input : in STD_LOGIC_VECTOR(BITS - 1 downto 0); -- Data to be synchronized - Output : out STD_LOGIC_VECTOR(BITS - 1 downto 0) -- synchronised data + Clock : in std_logic; -- Clock to be synchronized to + Input : in std_logic_vector(BITS - 1 downto 0); -- Data to be synchronized + Output : out std_logic_vector(BITS - 1 downto 0) -- synchronised data ); end component; @@ -82,9 +81,9 @@ package sync is SYNC_DEPTH : T_MISC_SYNC_DEPTH := 2 -- generate SYNC_DEPTH many stages, at least 2 ); port ( - Clock : in STD_LOGIC; -- output clock domain - Input : in STD_LOGIC; -- @async: reset input - Output : out STD_LOGIC -- @Clock: reset output + Clock : in std_logic; -- output clock domain + Input : in std_logic; -- @async: reset input + Output : out std_logic -- @Clock: reset output ); end component; @@ -93,9 +92,9 @@ package sync is SYNC_DEPTH : T_MISC_SYNC_DEPTH := 2 -- generate SYNC_DEPTH many stages, at least 2 ); port ( - Clock : in STD_LOGIC; -- output clock domain - Input : in STD_LOGIC; -- @async: reset input - Output : out STD_LOGIC -- @Clock: reset output + Clock : in std_logic; -- output clock domain + Input : in std_logic; -- @async: reset input + Output : out std_logic -- @Clock: reset output ); end component; @@ -104,9 +103,9 @@ package sync is SYNC_DEPTH : T_MISC_SYNC_DEPTH := 2 -- generate SYNC_DEPTH many stages, at least 2 ); port ( - Clock : in STD_LOGIC; -- output clock domain - Input : in STD_LOGIC; -- @async: reset input - Output : out STD_LOGIC -- @Clock: reset output + Clock : in std_logic; -- output clock domain + Input : in std_logic; -- @async: reset input + Output : out std_logic -- @Clock: reset output ); end component; end package; diff --git a/src/misc/sync/sync_Bits.files b/src/misc/sync/sync_Bits.files index b7dd22a4..f45c4761 100644 --- a/src/misc/sync/sync_Bits.files +++ b/src/misc/sync/sync_Bits.files @@ -8,17 +8,17 @@ include "src/common/common.files" # load common packages # PoC.misc.sync -vhdl poc "src/misc/sync/sync.pkg.vhdl" # +vhdl poc "src/misc/sync/sync.pkg.vhdl" if (DeviceVendor = "Altera") then include "lib/Altera.files" # Altera primitives - vhdl poc "src/misc/sync/sync_Bits_Altera.vhdl" # + vhdl poc "src/misc/sync/sync_Bits_Altera.vhdl" elseif (DeviceVendor = "Xilinx") then include "lib/Xilinx.files" # Xilinx primitives - vhdl poc "src/misc/sync/sync_Bits_Xilinx.vhdl" # + vhdl poc "src/misc/sync/sync_Bits_Xilinx.vhdl" if (ToolChain = "Xilinx_ISE") then - ucf "ucf/misc/sync/sync_Bits_Xilinx.ucf" # +# ucf "ucf/misc/sync/sync_Bits_Xilinx.ucf" elseif (ToolChain = "Xilinx_Vivado") then - xdc "ucf/misc/sync/sync_Bits_Xilinx.xdc" # +# xdc "ucf/misc/sync/sync_Bits_Xilinx.xdc" end if end if -vhdl poc "src/misc/sync/sync_Bits.vhdl" # +vhdl poc "src/misc/sync/sync_Bits.vhdl" # Top-Level diff --git a/src/misc/sync/sync_Bits.vhdl b/src/misc/sync/sync_Bits.vhdl index 609b3488..e5668c5a 100644 --- a/src/misc/sync/sync_Bits.vhdl +++ b/src/misc/sync/sync_Bits.vhdl @@ -1,34 +1,42 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= --- Authors: Patrick Lehmann +-- Authors: Patrick Lehmann -- --- Module: Synchronizes a flag signal across clock-domain boundaries +-- Entity: Synchronizes a flag signal across clock-domain boundaries -- -- Description: --- ------------------------------------ --- This module synchronizes multiple flag bits from clock-domain 'Clock1' to --- clock-domain 'Clock'. The clock-domain boundary crossing is done by two --- synchronizer D-FFs. All bits are independent from each other. If a known --- vendor like Altera or Xilinx are recognized, a vendor specific --- implementation is choosen. +-- ------------------------------------- +-- This module synchronizes multiple flag bits into clock-domain ``Clock``. +-- The clock-domain boundary crossing is done by two synchronizer D-FFs. All +-- bits are independent from each other. If a known vendor like Altera or Xilinx +-- are recognized, a vendor specific implementation is chosen. +-- +-- .. ATTENTION:: +-- Use this synchronizer only for long time stable signals (flags). -- --- ATTENTION: --- Use this synchronizer only for long time stable signals (flags). +-- Constraints: +-- General: +-- Please add constraints for meta stability to all '_meta' signals and +-- timing ignore constraints to all '_async' signals. -- --- CONSTRAINTS: --- General: --- Please add constraints for meta stability to all '_meta' signals and --- timing ignore constraints to all '_async' signals. +-- Xilinx: +-- In case of a Xilinx device, this module will instantiate the optimized +-- module PoC.xil.sync.Bits. Please attend to the notes of sync_Bits.vhdl. -- --- Xilinx: --- In case of a Xilinx device, this module will instantiate the optimized --- module PoC.xil.SyncBits. Please attend to the notes of xil_SyncBits.vhdl. +-- Altera sdc file: +-- TODO -- --- Altera sdc file: --- TODO +-- SeeAlso: +-- :doc:`PoC.misc.sync.Reset ` +-- For a special 2 D-FF synchronizer for *reset*-signals. +-- :doc:`PoC.misc.sync.Pulse ` +-- For a special 1+2 D-FF synchronizer for *pulse*-signals. +-- :doc:`PoC.misc.sync.Strobe ` +-- For a synchronizer for *strobe*-signals. +-- :doc:`PoC.misc.sync.Vector ` +-- For a multiple bits capable synchronizer. -- -- License: -- ============================================================================= @@ -59,31 +67,31 @@ use PoC.sync.all; entity sync_Bits is generic ( - BITS : POSITIVE := 1; -- number of bit to be synchronized - INIT : STD_LOGIC_VECTOR := x"00000000"; -- initialitation bits + BITS : positive := 1; -- number of bit to be synchronized + INIT : std_logic_vector := x"00000000"; -- initialitation bits SYNC_DEPTH : T_MISC_SYNC_DEPTH := 2 -- generate SYNC_DEPTH many stages, at least 2 ); port ( - Clock : in STD_LOGIC; -- output clock domain - Input : in STD_LOGIC_VECTOR(BITS - 1 downto 0); -- @async: input bits - Output : out STD_LOGIC_VECTOR(BITS - 1 downto 0) -- @Clock: output bits + Clock : in std_logic; -- output clock domain + Input : in std_logic_vector(BITS - 1 downto 0); -- @async: input bits + Output : out std_logic_vector(BITS - 1 downto 0) -- @Clock: output bits ); end entity; architecture rtl of sync_Bits is - constant INIT_I : STD_LOGIC_VECTOR := resize(descend(INIT), BITS); - + constant INIT_I : std_logic_vector := resize(descend(INIT), BITS); + constant DEV_INFO : T_DEVICE_INFO := DEVICE_INFO; begin - genGeneric : if ((VENDOR /= VENDOR_ALTERA) and (VENDOR /= VENDOR_XILINX)) generate - attribute ASYNC_REG : STRING; - attribute SHREG_EXTRACT : STRING; + genGeneric : if ((DEV_INFO.Vendor /= VENDOR_ALTERA) and (DEV_INFO.Vendor /= VENDOR_XILINX)) generate + attribute ASYNC_REG : string; + attribute SHREG_EXTRACT : string; begin gen : for i in 0 to BITS - 1 generate - signal Data_async : STD_LOGIC; - signal Data_meta : STD_LOGIC := INIT_I(i); - signal Data_sync : STD_LOGIC_VECTOR(SYNC_DEPTH - 1 downto 1) := (others => INIT_I(i)); + signal Data_async : std_logic; + signal Data_meta : std_logic := INIT_I(i); + signal Data_sync : std_logic_vector(SYNC_DEPTH - 1 downto 1) := (others => INIT_I(i)); -- Mark register DataSync_async's input as asynchronous and ignore timings (TIG) attribute ASYNC_REG of Data_meta : signal is "TRUE"; @@ -108,7 +116,7 @@ begin end generate; -- use dedicated and optimized 2 D-FF synchronizer for Altera FPGAs - genAltera : if (VENDOR = VENDOR_ALTERA) generate + genAltera : if (DEV_INFO.Vendor = VENDOR_ALTERA) generate sync : sync_Bits_Altera generic map ( BITS => BITS, @@ -123,7 +131,7 @@ begin end generate; -- use dedicated and optimized 2 D-FF synchronizer for Xilinx FPGAs - genXilinx : if (VENDOR = VENDOR_XILINX) generate + genXilinx : if (DEV_INFO.Vendor = VENDOR_XILINX) generate sync : sync_Bits_Xilinx generic map ( BITS => BITS, diff --git a/src/misc/sync/sync_Bits_Altera.vhdl b/src/misc/sync/sync_Bits_Altera.vhdl index 57492ed7..060aed89 100644 --- a/src/misc/sync/sync_Bits_Altera.vhdl +++ b/src/misc/sync/sync_Bits_Altera.vhdl @@ -1,27 +1,26 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: sync_Bits_Altera +-- Entity: sync_Bits_Altera -- -- Description: --- ------------------------------------ --- This is a multi-bit clock-domain-crossing circuit optimized for Altera FPGAs. --- It generates 2 flip flops per input bit and notifies Quartus II, that these --- flip flops are synchronizer flip flops. If you need a platform independent --- version of this synchronizer, please use 'PoC.misc.sync.sync_Flag', which --- internally instantiates this module if a Altera FPGA is detected. +-- ------------------------------------- +-- This is a multi-bit clock-domain-crossing circuit optimized for Altera FPGAs. +-- It generates 2 flip flops per input bit and notifies Quartus, that these +-- flip flops are synchronizer flip flops. If you need a platform independent +-- version of this synchronizer, please use `PoC.misc.sync.Flag`, which +-- internally instantiates this module if an Altera FPGA is detected. -- --- ATTENTION: --- Use this synchronizer only for long time stable signals (flags). +-- .. ATTENTION: +-- Use this synchronizer only for long time stable signals (flags). -- --- CONSTRAINTS: +-- CONSTRAINTS: -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -36,7 +35,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -47,29 +46,29 @@ use PoC.sync.all; entity sync_Bits_Altera is generic ( - BITS : POSITIVE := 1; -- number of bit to be synchronized - INIT : STD_LOGIC_VECTOR := x"00000000"; -- initialitation bits + BITS : positive := 1; -- number of bit to be synchronized + INIT : std_logic_vector := x"00000000"; -- initialitation bits SYNC_DEPTH : T_MISC_SYNC_DEPTH := 2 -- generate SYNC_DEPTH many stages, at least 2 ); port ( - Clock : in STD_LOGIC; -- Clock to be synchronized to - Input : in STD_LOGIC_VECTOR(BITS - 1 downto 0); -- Data to be synchronized - Output : out STD_LOGIC_VECTOR(BITS - 1 downto 0) -- synchronised data + Clock : in std_logic; -- Clock to be synchronized to + Input : in std_logic_vector(BITS - 1 downto 0); -- Data to be synchronized + Output : out std_logic_vector(BITS - 1 downto 0) -- synchronised data ); end entity; architecture rtl of sync_Bits_Altera is - attribute PRESERVE : BOOLEAN; - attribute ALTERA_ATTRIBUTE : STRING; + attribute PRESERVE : boolean; + attribute ALTERA_ATTRIBUTE : string; -- Apply a SDC constraint to meta stable flip flop attribute ALTERA_ATTRIBUTE of rtl : architecture is "-name SDC_STATEMENT ""set_false_path -to [get_registers {*|sync_Bits_Altera:*|\gen:*:Data_meta}] """; begin gen : for i in 0 to BITS - 1 generate - signal Data_async : STD_LOGIC; - signal Data_meta : STD_LOGIC := INIT(i); - signal Data_sync : STD_LOGIC_VECTOR(SYNC_DEPTH - 1 downto 0) := (others => INIT(i)); + signal Data_async : std_logic; + signal Data_meta : std_logic := INIT(i); + signal Data_sync : std_logic_vector(SYNC_DEPTH - 1 downto 0) := (others => INIT(i)); -- preserve both registers (no optimization, shift register extraction, ...) attribute PRESERVE of Data_meta : signal is TRUE; diff --git a/src/misc/sync/sync_Bits_Xilinx.vhdl b/src/misc/sync/sync_Bits_Xilinx.vhdl index 1d7f10aa..fb5278d7 100644 --- a/src/misc/sync/sync_Bits_Xilinx.vhdl +++ b/src/misc/sync/sync_Bits_Xilinx.vhdl @@ -1,37 +1,47 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: sync_Bits_Xilinx +-- Entity: sync_Bits_Xilinx -- -- Description: --- ------------------------------------ --- This is a multi-bit clock-domain-crossing circuit optimized for Xilinx FPGAs. --- It utilizes two 'FD' instances from UniSim.vComponents. If you need a --- platform independent version of this synchronizer, please use --- 'PoC.misc.sync.sync_Flag', which internally instantiates this module if --- a Xilinx FPGA is detected. +-- ------------------------------------- +-- This is a multi-bit clock-domain-crossing circuit optimized for Xilinx FPGAs. +-- It utilizes two `FD` instances from `UniSim.vComponents`. If you need a +-- platform independent version of this synchronizer, please use +-- `PoC.misc.sync.Flag`, which internally instantiates this module if a Xilinx +-- FPGA is detected. +-- +-- .. ATTENTION: +-- Use this synchronizer only for long time stable signals (flags). +-- +-- CONSTRAINTS: +-- This relative placement of the internal sites are constrained by RLOCs. -- --- ATTENTION: --- Use this synchronizer only for long time stable signals (flags). +-- Xilinx ISE UCF or XCF file: +-- .. code-block:: VHDL -- --- CONSTRAINTS: --- This relative placement of the internal sites is constrained by RLOCs. +-- NET "*_async" TIG; +-- INST "*FF1_METASTABILITY_FFS" TNM = "METASTABILITY_FFS"; +-- TIMESPEC "TS_MetaStability" = FROM FFS TO "METASTABILITY_FFS" TIG; -- --- Xilinx ISE UCF or XCF file: --- NET "*_async" TIG; --- INST "*FF1_METASTABILITY_FFS" TNM = "METASTABILITY_FFS"; --- TIMESPEC "TS_MetaStability" = FROM FFS TO "METASTABILITY_FFS" TIG; +-- Xilinx Vivado xdc file: +-- The XDC file `sync_Bits_Xilinx.xdc` must be directly applied to all +-- instances of sync_Bits_Xilinx. To achieve this, set the property +-- `SCOPED_TO_REF` to `sync_Bits_Xilinx` within the Vivado project. +-- Load the XDC file defining the clocks before that XDC file by using the +-- property `PROCESSING_ORDER`. -- --- Xilinx Vivado xdc file: --- TODO --- TODO +-- .. literalinclude:: ../../../ucf/misc/sync/sync_Bits_Xilinx.xdc +-- :language: xdc +-- :tab-width: 2 +-- :linenos: +-- :lines: 4-8 -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -46,26 +56,26 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; library PoC; -use PoC.utils.ALL; +use PoC.utils.all; use PoC.sync.all; entity sync_Bits_Xilinx is generic ( - BITS : POSITIVE := 1; -- number of bit to be synchronized - INIT : STD_LOGIC_VECTOR := x"00000000"; -- initialitation bits + BITS : positive := 1; -- number of bit to be synchronized + INIT : std_logic_vector := x"00000000"; -- initialitation bits SYNC_DEPTH : T_MISC_SYNC_DEPTH := 2 -- generate SYNC_DEPTH many stages, at least 2 ); port ( - Clock : in STD_LOGIC; -- Clock to be synchronized to - Input : in STD_LOGIC_VECTOR(BITS - 1 downto 0); -- Data to be synchronized - Output : out STD_LOGIC_VECTOR(BITS - 1 downto 0) -- synchronised data + Clock : in std_logic; -- Clock to be synchronized to + Input : in std_logic_vector(BITS - 1 downto 0); -- Data to be synchronized + Output : out std_logic_vector(BITS - 1 downto 0) -- synchronised data ); end entity; @@ -82,19 +92,19 @@ use PoC.sync.all; entity sync_Bit_Xilinx is generic ( - INIT : BIT; -- initialitation bit + INIT : bit; -- initialitation bit SYNC_DEPTH : T_MISC_SYNC_DEPTH := 2 -- generate SYNC_DEPTH many stages, at least 2 ); port ( - Clock : in STD_LOGIC; -- Clock to be synchronized to - Input : in STD_LOGIC; -- Data to be synchronized - Output : out STD_LOGIC -- synchronised data + Clock : in std_logic; -- Clock to be synchronized to + Input : in std_logic; -- Data to be synchronized + Output : out std_logic -- synchronised data ); end entity; architecture rtl of sync_Bits_Xilinx is - constant INIT_I : BIT_VECTOR := to_bitvector(resize(descend(INIT), BITS)); + constant INIT_I : bit_vector := to_bitvector(resize(descend(INIT), BITS)); begin gen : for i in 0 to BITS - 1 generate Sync : entity PoC.sync_Bit_Xilinx @@ -112,13 +122,13 @@ end architecture; architecture rtl of sync_Bit_Xilinx is - attribute ASYNC_REG : STRING; - attribute SHREG_EXTRACT : STRING; - attribute RLOC : STRING; + attribute ASYNC_REG : string; + attribute SHREG_EXTRACT : string; + attribute RLOC : string; - signal Data_async : STD_LOGIC; - signal Data_meta : STD_LOGIC; - signal Data_sync : STD_LOGIC; + signal Data_async : std_logic; + signal Data_meta : std_logic; + signal Data_sync : std_logic; -- Mark register Data_async's input as asynchronous attribute ASYNC_REG of Data_meta : signal is "TRUE"; diff --git a/src/misc/sync/sync_Command.vhdl b/src/misc/sync/sync_Command.vhdl index 6764d857..85516c59 100644 --- a/src/misc/sync/sync_Command.vhdl +++ b/src/misc/sync/sync_Command.vhdl @@ -1,27 +1,25 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= --- Authors: Patrick Lehmann --- Steffen Koehler +-- Authors: Patrick Lehmann +-- Steffen Koehler -- --- Module: Synchronizes a command signal across clock-domain boundaries +-- Entity: Synchronizes a command signal across clock-domain boundaries -- -- Description: --- ------------------------------------ --- This module synchronizes a vector of bits from clock-domain 'Clock1' to --- clock-domain 'Clock2'. The clock-domain boundary crossing is done by a --- change comparator, a T-FF, two synchronizer D-FFs and a reconstructive --- XOR indicating a value change on the input. This changed signal is used --- to capture the input for the new output. A busy flag is additionally --- calculated for the input clock-domain. The output has strobe character --- and is reset to it's INIT value after one clock cycle. +-- ------------------------------------- +-- This module synchronizes a vector of bits from clock-domain ``Clock1`` to +-- clock-domain ``Clock2``. The clock-domain boundary crossing is done by a +-- change comparator, a T-FF, two synchronizer D-FFs and a reconstructive +-- XOR indicating a value change on the input. This changed signal is used +-- to capture the input for the new output. A busy flag is additionally +-- calculated for the input clock-domain. The output has strobe character +-- and is reset to it's ``INIT`` value after one clock cycle. -- --- CONSTRAINTS: --- General: --- This module uses sub modules which need to be constrained. Please --- attend to the notes of the instantiated sub modules. +-- Constraints: +-- This module uses sub modules which need to be constrained. Please +-- attend to the notes of the instantiated sub modules. -- -- License: -- ============================================================================= @@ -49,50 +47,50 @@ library PoC; use PoC.utils.all; -entity sync_Command IS +entity sync_Command is generic ( - BITS : POSITIVE := 8; -- number of bit to be synchronized - INIT : STD_LOGIC_VECTOR := x"00000000" -- + BITS : positive := 8; -- number of bit to be synchronized + INIT : std_logic_vector := x"00000000" -- ); - PORT ( - Clock1 : in STD_LOGIC; -- input clock - Clock2 : in STD_LOGIC; -- output clock - Input : in STD_LOGIC_VECTOR(BITS - 1 downto 0); -- @Clock1: input vector - Output : out STD_LOGIC_VECTOR(BITS - 1 downto 0); -- @Clock2: output vector - Busy : out STD_LOGIC; -- @Clock1: busy bit - Changed : out STD_LOGIC -- @Clock2: changed bit + port ( + Clock1 : in std_logic; -- input clock + Clock2 : in std_logic; -- output clock + Input : in std_logic_vector(BITS - 1 downto 0); -- @Clock1: input vector + Output : out std_logic_vector(BITS - 1 downto 0); -- @Clock2: output vector + Busy : out std_logic; -- @Clock1: busy bit + Changed : out std_logic -- @Clock2: changed bit ); -end; +end entity; -architecture rtl OF sync_Command is - attribute SHREG_EXTRACT : STRING; +architecture rtl of sync_Command is + attribute SHREG_EXTRACT : string; - constant INIT_I : STD_LOGIC_VECTOR := descend(INIT)(BITS - 1 downto 0); + constant INIT_I : std_logic_vector := descend(INIT)(BITS - 1 downto 0); - signal D0 : STD_LOGIC := '0'; - signal D1 : STD_LOGIC_VECTOR(BITS - 1 downto 0) := INIT_I; - signal T2 : STD_LOGIC := '0'; - signal D3 : STD_LOGIC := '0'; - signal D4 : STD_LOGIC := '0'; - signal D5 : STD_LOGIC_VECTOR(BITS - 1 downto 0) := INIT_I; + signal D0 : std_logic := '0'; + signal D1 : std_logic_vector(BITS - 1 downto 0) := INIT_I; + signal T2 : std_logic := '0'; + signal D3 : std_logic := '0'; + signal D4 : std_logic := '0'; + signal D5 : std_logic_vector(BITS - 1 downto 0) := INIT_I; - signal IsCommand_Clk1 : STD_LOGIC; - signal Changed_Clk1 : STD_LOGIC; - signal Changed_Clk2 : STD_LOGIC; - signal Busy_i : STD_LOGIC; + signal IsCommand_Clk1 : std_logic; + signal Changed_Clk1 : std_logic; + signal Changed_Clk2 : std_logic; + signal Busy_i : std_logic; -- Prevent XST from translating two FFs into SRL plus FF - attribute SHREG_EXTRACT of D0 : signal IS "NO"; - attribute SHREG_EXTRACT of T2 : signal IS "NO"; - attribute SHREG_EXTRACT of D3 : signal IS "NO"; - attribute SHREG_EXTRACT of D4 : signal IS "NO"; - attribute SHREG_EXTRACT of D5 : signal IS "NO"; - - signal syncClk1_In : STD_LOGIC; - signal syncClk1_Out : STD_LOGIC; - signal syncClk2_In : STD_LOGIC; - signal syncClk2_Out : STD_LOGIC; + attribute SHREG_EXTRACT of D0 : signal is "NO"; + attribute SHREG_EXTRACT of T2 : signal is "NO"; + attribute SHREG_EXTRACT of D3 : signal is "NO"; + attribute SHREG_EXTRACT of D4 : signal is "NO"; + attribute SHREG_EXTRACT of D5 : signal is "NO"; + + signal syncClk1_In : std_logic; + signal syncClk1_Out : std_logic; + signal syncClk2_In : std_logic; + signal syncClk2_Out : std_logic; begin diff --git a/src/misc/sync/sync_Pulse.files b/src/misc/sync/sync_Pulse.files new file mode 100644 index 00000000..f3876952 --- /dev/null +++ b/src/misc/sync/sync_Pulse.files @@ -0,0 +1,26 @@ +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# ============================================================================== +# Note: all files are relative to PoC root directory +# +# Common PoC packages for configuration, synthesis and simulation +include "src/common/common.files" # load common packages + +# PoC.misc.sync +vhdl poc "src/misc/sync/sync.pkg.vhdl" +if (DeviceVendor = "Altera") then + include "lib/Altera.files" # Altera primitives + vhdl poc "src/misc/sync/sync_Bits_Altera.vhdl" + vhdl poc "src/misc/sync/sync_Pulse_Altera.vhdl" +elseif (DeviceVendor = "Xilinx") then + include "lib/Xilinx.files" # Xilinx primitives + vhdl poc "src/misc/sync/sync_Bits_Xilinx.vhdl" + vhdl poc "src/misc/sync/sync_Pulse_Xilinx.vhdl" + if (ToolChain = "Xilinx_ISE") then +# ucf "ucf/misc/sync/sync_Bits_Xilinx.ucf" + elseif (ToolChain = "Xilinx_Vivado") then +# xdc "ucf/misc/sync/sync_Bits_Xilinx.xdc" + end if +end if +vhdl poc "src/misc/sync/sync_Pulse.vhdl" # Top-Level diff --git a/src/misc/sync/sync_Pulse.vhdl b/src/misc/sync/sync_Pulse.vhdl new file mode 100644 index 00000000..64aff09d --- /dev/null +++ b/src/misc/sync/sync_Pulse.vhdl @@ -0,0 +1,150 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- ============================================================================= +-- Authors: Patrick Lehmann +-- +-- Entity: Synchronizes a very short pulse across clock-domain boundaries +-- +-- Description: +-- ------------------------------------- +-- This module synchronizes multiple pulsed bits into the clock-domain ``Clock``. +-- The clock-domain boundary crossing is done by two synchronizer D-FFs. All bits +-- are independent from each other. If a known vendor like Altera or Xilinx are +-- recognized, a vendor specific implementation is chosen. +-- +-- .. ATTENTION:: +-- Use this synchronizer for very short signals (pulse). +-- +-- Constraints: +-- General: +-- Please add constraints for meta stability to all '_meta' signals and +-- timing ignore constraints to all '_async' signals. +-- +-- Xilinx: +-- In case of a Xilinx device, this module will instantiate the optimized +-- module PoC.xil.sync.Pulse. Please attend to the notes of sync_Bits.vhdl. +-- +-- Altera sdc file: +-- TODO +-- +-- SeeAlso: +-- :doc:`PoC.misc.sync.Bits ` +-- For a common 2 D-FF synchronizer for *flag*-signals. +-- :doc:`PoC.misc.sync.Reset ` +-- For a special 2 D-FF synchronizer for *reset*-signals. +-- :doc:`PoC.misc.sync.Strobe ` +-- For a synchronizer for *strobe*-signals. +-- :doc:`PoC.misc.sync.Vector ` +-- For a multiple bits capable synchronizer. +-- +-- License: +-- ============================================================================= +-- Copyright 2007-2016 Technische Universitaet Dresden - Germany +-- Chair for VLSI-Design, Diagnostics and Architecture +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library PoC; +use PoC.config.all; +use PoC.utils.all; +use PoC.sync.all; + + +entity sync_Pulse is + generic ( + BITS : positive := 1; -- number of bit to be synchronized + SYNC_DEPTH : T_MISC_SYNC_DEPTH := 2 -- generate SYNC_DEPTH many stages, at least 2 + ); + port ( + Clock : in std_logic; -- output clock domain + Input : in std_logic_vector(BITS - 1 downto 0); -- @async: input bits + Output : out std_logic_vector(BITS - 1 downto 0) -- @Clock: output bits + ); +end entity; + + +architecture rtl of sync_Pulse is + constant DEV_INFO : T_DEVICE_INFO := DEVICE_INFO; +begin + genGeneric : if ((DEV_INFO.Vendor /= VENDOR_ALTERA) and (DEV_INFO.Vendor /= VENDOR_XILINX)) generate + attribute ASYNC_REG : string; + attribute SHREG_EXTRACT : string; + begin + gen : for i in 0 to BITS - 1 generate + signal Data_async : std_logic; + signal Data_meta : std_logic := INIT_I(i); + signal Data_sync : std_logic_vector(SYNC_DEPTH - 1 downto 1) := (others => INIT_I(i)); + + -- Mark register DataSync_async's input as asynchronous and ignore timings (TIG) + attribute ASYNC_REG of Data_meta : signal is "TRUE"; + + -- Prevent XST from translating two FFs into SRL plus FF + attribute SHREG_EXTRACT of Data_meta : signal is "NO"; + attribute SHREG_EXTRACT of Data_sync : signal is "NO"; + + begin + process(Input(i), Data_sync(Data_sync'high)) + begin + if ((not Input(i) and Data_sync(Data_sync'high)) = '1') then + Data_async <= '0'; + elsif rising_edge(Input) then + Data_async <= '1'; + end if; + end process; + + process(Clock) + begin + if rising_edge(Clock) then + Data_meta <= Data_async; + Data_sync <= Data_sync(Data_sync'high - 1 downto 1) & Data_meta; + end if; + end process; + + Output(i) <= Data_sync(Data_sync'high); + end generate; + end generate; + + -- use dedicated and optimized 1+2 D-FF synchronizer for Altera FPGAs + genAltera : if (DEV_INFO.Vendor = VENDOR_ALTERA) generate + sync : sync_Pulse_Altera + generic map ( + BITS => BITS, + SYNC_DEPTH => SYNC_DEPTH + ) + port map ( + Clock => Clock, + Input => Input, + Output => Output + ); + end generate; + + -- use dedicated and optimized 1+2 D-FF synchronizer for Xilinx FPGAs + genXilinx : if (DEV_INFO.Vendor = VENDOR_XILINX) generate + sync : sync_Pulse_Xilinx + generic map ( + BITS => BITS, + SYNC_DEPTH => SYNC_DEPTH + ) + port map ( + Clock => Clock, + Input => Input, + Output => Output + ); + end generate; + +end architecture; diff --git a/src/misc/sync/sync_Pulse_Altera.vhdl b/src/misc/sync/sync_Pulse_Altera.vhdl new file mode 100644 index 00000000..82cd9165 --- /dev/null +++ b/src/misc/sync/sync_Pulse_Altera.vhdl @@ -0,0 +1,100 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- ============================================================================= +-- Authors: Patrick Lehmann +-- +-- Entity: sync_Pulse_Altera +-- +-- Description: +-- ------------------------------------- +-- This is a multi-bit clock-domain-crossing circuit optimized for Altera FPGAs. +-- It synchronizes multiple pulsed bits into the clock-domain ``Clock``. +-- The clock-domain boundary crossing is done by two synchronizer D-FFs. All bits +-- are independent from each other. It generates 3 flip flops per input bit and +-- notifies Quartus, that these flip flops are synchronizer flip flops. If you +-- need a platform independent version of this synchronizer, please use +-- `PoC.misc.sync.Pulse`, which internally instantiates this module if an Altera +-- FPGA is detected. +-- +-- .. ATTENTION:: +-- Use this synchronizer for very short signals (pulse). +-- +-- CONSTRAINTS: +-- +-- License: +-- ============================================================================= +-- Copyright 2007-2016 Technische Universitaet Dresden - Germany +-- Chair for VLSI-Design, Diagnostics and Architecture +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library PoC; +use PoC.sync.all; + + +entity sync_Pulse_Altera is + generic ( + BITS : positive := 1; -- number of bit to be synchronized + SYNC_DEPTH : T_MISC_SYNC_DEPTH := 2 -- generate SYNC_DEPTH many stages, at least 2 + ); + port ( + Clock : in std_logic; -- Clock to be synchronized to + Input : in std_logic_vector(BITS - 1 downto 0); -- Data to be synchronized + Output : out std_logic_vector(BITS - 1 downto 0) -- synchronised data + ); +end entity; + + +architecture rtl of sync_Pulse_Altera is + attribute PRESERVE : boolean; + attribute ALTERA_ATTRIBUTE : string; + + -- Apply a SDC constraint to meta stable flip flop + attribute ALTERA_ATTRIBUTE of rtl : architecture is "-name SDC_STATEMENT ""set_false_path -to [get_registers {*|sync_Pulse_Altera:*|\gen:*:Data_meta}] """; +begin + gen : for i in 0 to BITS - 1 generate + signal Data_async : std_logic; + signal Data_meta : std_logic := INIT(i); + signal Data_sync : std_logic_vector(SYNC_DEPTH - 1 downto 0) := (others => INIT(i)); + + -- preserve both registers (no optimization, shift register extraction, ...) + attribute PRESERVE of Data_meta : signal is TRUE; + attribute PRESERVE of Data_sync : signal is TRUE; + -- Notity the synthesizer / timing analysator to identity a synchronizer circuit + attribute ALTERA_ATTRIBUTE of Data_meta : signal is "-name SYNCHRONIZER_IDENTIFICATION ""FORCED IF ASYNCHRONOUS"""; + begin + process(Input(i), Data_sync(Data_sync'high)) + begin + if ((not Input(i) and Data_sync(Data_sync'high)) = '1') then + Data_async <= '0'; + elsif rising_edge(Input) then + Data_async <= '1'; + end if; + end process; + + process(Clock) + begin + if rising_edge(Clock) then + Data_meta <= Data_async; + Data_sync <= Data_sync(Data_sync'high - 1 downto 0) & Data_meta; + end if; + end process; + + Output(i) <= Data_sync(Data_sync'high); + end generate; +end architecture; diff --git a/src/misc/sync/sync_Pulse_Xilinx.vhdl b/src/misc/sync/sync_Pulse_Xilinx.vhdl new file mode 100644 index 00000000..9505e2d9 --- /dev/null +++ b/src/misc/sync/sync_Pulse_Xilinx.vhdl @@ -0,0 +1,119 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- ============================================================================= +-- Authors: Patrick Lehmann +-- +-- Entity: sync_Pulse_Xilinx +-- +-- Description: +-- ------------------------------------- +-- This is a multi-bit clock-domain-crossing circuit optimized for Xilinx FPGAs. +-- It synchronizes multiple pulsed bits into the clock-domain ``Clock``. +-- It utilizes two `FD` instances from `UniSim.vComponents`. All bits are +-- independent from each other. If you need a platform independent version of +-- this synchronizer, please use `PoC.misc.sync.Pulse`, which internally +-- instantiates this module if a Xilinx FPGA is detected. +-- +-- .. ATTENTION:: +-- Use this synchronizer for very short signals (pulse). +-- +-- CONSTRAINTS: +-- This relative placement of the internal sites are constrained by RLOCs. +-- +-- Xilinx ISE UCF or XCF file: +-- .. code-block:: VHDL +-- +-- NET "*_async" TIG; +-- INST "*FF1_METASTABILITY_FFS" TNM = "METASTABILITY_FFS"; +-- TIMESPEC "TS_MetaStability" = FROM FFS TO "METASTABILITY_FFS" TIG; +-- +-- Xilinx Vivado xdc file: +-- The XDC file `sync_Pulse_Xilinx.xdc` must be directly applied to all +-- instances of sync_Pulse_Xilinx. To achieve this, set the property +-- `SCOPED_TO_REF` to `sync_Pulse_Xilinx` within the Vivado project. +-- Load the XDC file defining the clocks before that XDC file by using the +-- property `PROCESSING_ORDER`. +-- +-- .. literalinclude:: ../../../ucf/misc/sync/sync_Pulse_Xilinx.xdc +-- :language: xdc +-- :tab-width: 2 +-- :linenos: +-- :lines: 4-8 +-- +-- License: +-- ============================================================================= +-- Copyright 2007-2016 Technische Universitaet Dresden - Germany +-- Chair for VLSI-Design, Diagnostics and Architecture +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library PoC; +use PoC.utils.all; +use PoC.sync.all; + + +entity sync_Pulse_Xilinx is + generic ( + BITS : positive := 1; -- number of bit to be synchronized + SYNC_DEPTH : T_MISC_SYNC_DEPTH := 2 -- generate SYNC_DEPTH many stages, at least 2 + ); + port ( + Clock : in std_logic; -- Clock to be synchronized to + Input : in std_logic_vector(BITS - 1 downto 0); -- Data to be synchronized + Output : out std_logic_vector(BITS - 1 downto 0) -- synchronised data + ); +end entity; + + +architecture rtl of sync_Pulse_Xilinx is + constant INIT_I : bit_vector := (0 to BITS - 1 => '0'); + + signal Captured_async : std_logic_vector(BITS - 1 downto 0); + signal Input_sync : std_logic_vector(BITS - 1 downto 0); +begin + gen : for i in 0 to BITS - 1 generate + signal Clear : std_logic; + begin + capture : FDCE + generic map ( + INIT => '0' + ) + port map ( + C => Input(i), + CE => '1', + CLR => Clear, + D => '1' + Q => Captured_async(i), + ); + + Clear <= not Input(i) and Input_sync(i); + end generate; + + Sync : entity PoC.sync_Bits_Xilinx + generic map ( + BITS => BITS, + SYNC_DEPTH => SYNC_DEPTH + ) + port map ( + Clock => Clock, + Input => Captured_async(i), + Output => Input_sync(i) + ); + + Output <= Input_sync; +end architecture; diff --git a/src/misc/sync/sync_Reset.vhdl b/src/misc/sync/sync_Reset.vhdl index e3ca83be..d5f7fb1f 100644 --- a/src/misc/sync/sync_Reset.vhdl +++ b/src/misc/sync/sync_Reset.vhdl @@ -1,35 +1,34 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= --- Authors: Patrick Lehmann +-- Authors: Patrick Lehmann -- --- Module: Synchronizes a reset signal across clock-domain boundaries +-- Entity: Synchronizes a reset signal across clock-domain boundaries -- -- Description: --- ------------------------------------ --- This module synchronizes an asynchronous reset signal to the clock --- 'Clock'. The 'Input' can be asserted and de-asserted at any time. --- The 'Output' is asserted asynchronously and de-asserted synchronously --- to the clock. +-- ------------------------------------- +-- This module synchronizes an asynchronous reset signal to the clock +-- ``Clock``. The ``Input`` can be asserted and de-asserted at any time. +-- The ``Output`` is asserted asynchronously and de-asserted synchronously +-- to the clock. -- --- ATTENTION: --- Use this synchronizer only to asynchronously reset your design. --- The 'Output' should be feed by global buffer to the destination FFs, so --- that, it reaches their reset inputs within one clock cycle. +-- .. ATTENTION:: +-- Use this synchronizer only to asynchronously reset your design. +-- The 'Output' should be feed by global buffer to the destination FFs, so +-- that, it reaches their reset inputs within one clock cycle. -- --- CONSTRAINTS: --- General: --- Please add constraints for meta stability to all '_meta' signals and --- timing ignore constraints to all '_async' signals. +-- Constraints: +-- General: +-- Please add constraints for meta stability to all '_meta' signals and +-- timing ignore constraints to all '_async' signals. -- --- Xilinx: --- In case of a Xilinx device, this module will instantiate the optimized --- module xil_SyncReset. Please attend to the notes of xil_SyncReset. +-- Xilinx: +-- In case of a Xilinx device, this module will instantiate the optimized +-- module xil_SyncReset. Please attend to the notes of xil_SyncReset. -- --- Altera sdc file: --- TODO +-- Altera sdc file: +-- TODO -- -- License: -- ============================================================================= @@ -63,22 +62,22 @@ entity sync_Reset is SYNC_DEPTH : T_MISC_SYNC_DEPTH := 2 -- generate SYNC_DEPTH many stages, at least 2 ); port ( - Clock : in STD_LOGIC; -- output clock domain - Input : in STD_LOGIC; -- @async: reset input - Output : out STD_LOGIC -- @Clock: reset output + Clock : in std_logic; -- output clock domain + Input : in std_logic; -- @async: reset input + Output : out std_logic -- @Clock: reset output ); end entity; architecture rtl of sync_Reset is begin - genGeneric : if ((VENDOR /= VENDOR_ALTERA) and (VENDOR /= VENDOR_XILINX)) generate - attribute ASYNC_REG : STRING; - attribute SHREG_EXTRACT : STRING; + genGeneric : if (VENDOR /= VENDOR_ALTERA) and (VENDOR /= VENDOR_XILINX) generate + attribute ASYNC_REG : string; + attribute SHREG_EXTRACT : string; - signal Data_async : STD_LOGIC; - signal Data_meta : STD_LOGIC := '1'; - signal Data_sync : STD_LOGIC_VECTOR(SYNC_DEPTH - 1 downto 0) := (others => '1'); + signal Data_async : std_logic; + signal Data_meta : std_logic := '1'; + signal Data_sync : std_logic_vector(SYNC_DEPTH - 1 downto 0) := (others => '1'); -- Mark registers as asynchronous attribute ASYNC_REG of Data_meta : signal is "TRUE"; @@ -91,7 +90,7 @@ begin begin Data_async <= Input; - process(Clock, Input) + process(Clock, Data_async) begin if (Data_async = '1') then Data_meta <= '1'; @@ -106,7 +105,7 @@ begin end generate; -- use dedicated and optimized 2 D-FF synchronizer for Altera FPGAs - genAltera : if (VENDOR = VENDOR_ALTERA) generate + genAltera : if VENDOR = VENDOR_ALTERA generate sync : sync_Reset_Altera generic map ( SYNC_DEPTH => SYNC_DEPTH @@ -119,7 +118,7 @@ begin end generate; -- use dedicated and optimized 2 D-FF synchronizer for Xilinx FPGAs - genXilinx : if (VENDOR = VENDOR_XILINX) generate + genXilinx : if VENDOR = VENDOR_XILINX generate sync : sync_Reset_Xilinx generic map ( SYNC_DEPTH => SYNC_DEPTH diff --git a/src/misc/sync/sync_Reset_Altera.vhdl b/src/misc/sync/sync_Reset_Altera.vhdl index 873bb46a..ea130fd2 100644 --- a/src/misc/sync/sync_Reset_Altera.vhdl +++ b/src/misc/sync/sync_Reset_Altera.vhdl @@ -1,19 +1,18 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: sync_Reset_Altera +-- Entity: sync_Reset_Altera -- -- Description: --- ------------------------------------ --- This is the Altera specific implementation of the entity --- 'PoC.misc.sync.sync_Reset'. See the description there on how to use this. +-- ------------------------------------- +-- This is the Altera specific implementation of the entity +-- `PoC.misc.sync.Reset`. See the description there on how to use this. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -28,7 +27,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -42,39 +41,39 @@ entity sync_Reset_Altera is SYNC_DEPTH : T_MISC_SYNC_DEPTH := 2 -- generate SYNC_DEPTH many stages, at least 2 ); port ( - Clock : in STD_LOGIC; -- Clock to be synchronized to - Input : in STD_LOGIC; -- Data to be synchronized - Output : out STD_LOGIC -- synchronised data + Clock : in std_logic; -- Clock to be synchronized to + Input : in std_logic; -- Data to be synchronized + Output : out std_logic -- synchronised data ); end entity; architecture rtl of sync_Reset_Altera is - attribute altera_attribute : STRING; - attribute preserve : BOOLEAN; + attribute ALTERA_ATTRIBUTE : string; + attribute preserve : boolean; - signal Data_async : STD_LOGIC; - signal Data_meta : STD_LOGIC := '1'; - signal Data_sync : STD_LOGIC_VECTOR(SYNC_DEPTH - 1 downto 0) := (others => '1'); + signal Data_async : std_logic; + signal Data_meta : std_logic := '1'; + signal Data_sync : std_logic_vector(SYNC_DEPTH - 1 downto 0) := (others => '1'); -- Apply a SDC constraint to meta stable flip flop - --attribute altera_attribute of rtl : architecture is "-name SDC_STATEMENT ""set_false_path -to *|sync_Reset_Altera:*|Data_meta """; + --attribute ALTERA_ATTRIBUTE of rtl : architecture is "-name SDC_STATEMENT ""set_false_path -to *|sync_Reset_Altera:*|Data_meta """; -- Notity the synthesizer / timing analysator to identity a synchronizer circuit - attribute altera_attribute of Data_meta : signal is "-name SYNCHRONIZER_IDENTIFICATION ""FORCED IF ASYNCHRONOUS"""; + attribute ALTERA_ATTRIBUTE of Data_meta : signal is "-name SYNCHRONIZER_IDENTIFICATION ""FORCED IF ASYNCHRONOUS"""; -- preserve both registers (no optimization, shift register extraction, ...) attribute preserve of Data_meta : signal is TRUE; attribute preserve of Data_sync : signal is TRUE; begin Data_async <= '0'; - process(Clock) + process(Clock, Input) begin if (Input = '1') then Data_meta <= '1'; Data_sync <= (others => '1'); elsif rising_edge(Clock) then Data_meta <= Data_async; - Data_sync <= Data_sync8Data_sync'high - 1 downto 0) & Data_meta; + Data_sync <= Data_sync(Data_sync'high - 1 downto 0) & Data_meta; end if; end process; diff --git a/src/misc/sync/sync_Reset_Xilinx.vhdl b/src/misc/sync/sync_Reset_Xilinx.vhdl index 2feb3ef7..4ca69ea8 100644 --- a/src/misc/sync/sync_Reset_Xilinx.vhdl +++ b/src/misc/sync/sync_Reset_Xilinx.vhdl @@ -1,14 +1,13 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: sync_Reset_Xilinx +-- Entity: sync_Reset_Xilinx -- -- Description: --- ------------------------------------ +-- ------------------------------------- -- This is the Xilinx specific implementation of the entity -- 'PoC.misc.sync.sync_Reset'. See the description there on how to use this. -- @@ -25,7 +24,7 @@ -- TODO -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -40,7 +39,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -57,21 +56,21 @@ entity sync_Reset_Xilinx is SYNC_DEPTH : T_MISC_SYNC_DEPTH := 2 -- generate SYNC_DEPTH many stages, at least 2 ); port ( - Clock : in STD_LOGIC; -- Clock to be synchronized to - Input : in STD_LOGIC; -- high active asynchronous reset - Output : out STD_LOGIC -- "Synchronised" reset signal + Clock : in std_logic; -- Clock to be synchronized to + Input : in std_logic; -- high active asynchronous reset + Output : out std_logic -- "Synchronised" reset signal ); end entity; architecture rtl of sync_Reset_Xilinx is - attribute ASYNC_REG : STRING; - attribute SHREG_EXTRACT : STRING; - attribute RLOC : STRING; + attribute ASYNC_REG : string; + attribute SHREG_EXTRACT : string; + attribute RLOC : string; - signal Reset_async : STD_LOGIC; - signal Reset_meta : STD_LOGIC; - signal Reset_sync : STD_LOGIC; + signal Reset_async : std_logic; + signal Reset_meta : std_logic; + signal Reset_sync : std_logic; -- Mark register "Reset_meta" and "Output" as asynchronous attribute ASYNC_REG of Reset_meta : signal is "TRUE"; diff --git a/src/misc/sync/sync_Strobe.vhdl b/src/misc/sync/sync_Strobe.vhdl index 1b1d8290..5a076969 100644 --- a/src/misc/sync/sync_Strobe.vhdl +++ b/src/misc/sync/sync_Strobe.vhdl @@ -1,29 +1,27 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= --- Authors: Patrick Lehmann --- Steffen Koehler +-- Authors: Patrick Lehmann +-- Steffen Koehler -- --- Module: Synchronizes a strobe signal across clock-domain boundaries +-- Entity: Synchronizes a strobe signal across clock-domain boundaries -- -- Description: --- ------------------------------------ --- This module synchronizes multiple high-active bits from clock-domain --- 'Clock1' to clock-domain 'Clock2'. The clock-domain boundary crossing is --- done by a T-FF, two synchronizer D-FFs and a reconstructive XOR. A busy --- flag is additionally calculated and can be used to block new inputs. All --- bits are independent from each other. Multiple consecutive strobes are --- suppressed by a rising edge detection. +-- ------------------------------------- +-- This module synchronizes multiple high-active bits from clock-domain +-- ``Clock1`` to clock-domain ``Clock2``. The clock-domain boundary crossing is +-- done by a T-FF, two synchronizer D-FFs and a reconstructive XOR. A busy +-- flag is additionally calculated and can be used to block new inputs. All +-- bits are independent from each other. Multiple consecutive strobes are +-- suppressed by a rising edge detection. -- --- ATTENTION: --- Use this synchronizer only for one-cycle high-active signals (strobes). +-- .. ATTENTION:: +-- Use this synchronizer only for one-cycle high-active signals (strobes). -- --- CONSTRAINTS: --- General: --- This module uses sub modules which need to be constrained. Please --- attend to the notes of the instantiated sub modules. +-- Constraints: +-- This module uses sub modules which need to be constrained. Please +-- attend to the notes of the instantiated sub modules. -- -- License: -- ============================================================================= @@ -50,44 +48,44 @@ use IEEE.NUMERIC_STD.all; library PoC; -entity sync_Strobe IS +entity sync_Strobe is generic ( - BITS : POSITIVE := 1; -- number of bit to be synchronized - GATED_INPUT_BY_BUSY : BOOLEAN := TRUE -- use gated input (by busy signal) + BITS : positive := 1; -- number of bit to be synchronized + GATED_INPUT_BY_BUSY : boolean := TRUE -- use gated input (by busy signal) ); port ( - Clock1 : in STD_LOGIC; -- input clock domain - Clock2 : in STD_LOGIC; -- output clock domain - Input : in STD_LOGIC_VECTOR(BITS - 1 downto 0); -- @Clock1: input bits - Output : out STD_LOGIC_VECTOR(BITS - 1 downto 0); -- @Clock2: output bits - Busy : out STD_LOGIC_VECTOR(BITS - 1 downto 0) -- @Clock1: busy bits + Clock1 : in std_logic; -- input clock domain + Clock2 : in std_logic; -- output clock domain + Input : in std_logic_vector(BITS - 1 downto 0); -- @Clock1: input bits + Output : out std_logic_vector(BITS - 1 downto 0); -- @Clock2: output bits + Busy : out std_logic_vector(BITS - 1 downto 0) -- @Clock1: busy bits ); -end; +end entity; architecture rtl of sync_Strobe is - attribute SHREG_EXTRACT : STRING; + attribute SHREG_EXTRACT : string; - signal syncClk1_In : STD_LOGIC_VECTOR(BITS - 1 downto 0); - signal syncClk1_Out : STD_LOGIC_VECTOR(BITS - 1 downto 0); - signal syncClk2_In : STD_LOGIC_VECTOR(BITS - 1 downto 0); - signal syncClk2_Out : STD_LOGIC_VECTOR(BITS - 1 downto 0); + signal syncClk1_In : std_logic_vector(BITS - 1 downto 0); + signal syncClk1_Out : std_logic_vector(BITS - 1 downto 0); + signal syncClk2_In : std_logic_vector(BITS - 1 downto 0); + signal syncClk2_Out : std_logic_vector(BITS - 1 downto 0); -BEGIN +begin gen : for i in 0 to BITS - 1 generate - signal D0 : STD_LOGIC := '0'; - signal T1 : STD_LOGIC := '0'; - signal D2 : STD_LOGIC := '0'; + signal D0 : std_logic := '0'; + signal T1 : std_logic := '0'; + signal D2 : std_logic := '0'; - signal Changed_Clk1 : STD_LOGIC; - signal Changed_Clk2 : STD_LOGIC; - signal Busy_i : STD_LOGIC; + signal Changed_Clk1 : std_logic; + signal Changed_Clk2 : std_logic; + signal Busy_i : std_logic; -- Prevent XST from translating two FFs into SRL plus FF - attribute SHREG_EXTRACT OF D0 : signal is "NO"; - attribute SHREG_EXTRACT OF T1 : signal is "NO"; - attribute SHREG_EXTRACT OF D2 : signal is "NO"; + attribute SHREG_EXTRACT of D0 : signal is "NO"; + attribute SHREG_EXTRACT of T1 : signal is "NO"; + attribute SHREG_EXTRACT of D2 : signal is "NO"; begin @@ -98,7 +96,7 @@ BEGIN D0 <= Input(i); -- T-FF to converts a strobe to a flag signal - if (GATED_INPUT_BY_BUSY = TRUE) then + if GATED_INPUT_BY_BUSY then T1 <= (Changed_Clk1 and not Busy_i) xor T1; else T1 <= Changed_Clk1 xor T1; @@ -141,4 +139,4 @@ BEGIN Input => syncClk1_In, -- @async: input bits Output => syncClk1_Out -- @Clock: output bits ); -end; \ No newline at end of file +end; diff --git a/src/misc/sync/sync_Vector.vhdl b/src/misc/sync/sync_Vector.vhdl index 448f827d..122ff1f5 100644 --- a/src/misc/sync/sync_Vector.vhdl +++ b/src/misc/sync/sync_Vector.vhdl @@ -1,26 +1,24 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= --- Authors: Steffen Koehler --- Patrick Lehmann +-- Authors: Steffen Koehler +-- Patrick Lehmann -- --- Module: Synchronizes a signal vector across clock-domain boundaries +-- Entity: Synchronizes a signal vector across clock-domain boundaries -- -- Description: --- ------------------------------------ --- This module synchronizes a vector of bits from clock-domain 'Clock1' to --- clock-domain 'Clock2'. The clock-domain boundary crossing is done by a --- change comparator, a T-FF, two synchronizer D-FFs and a reconstructive --- XOR indicating a value change on the input. This changed signal is used --- to capture the input for the new output. A busy flag is additionally --- calculated for the input clock domain. +-- ------------------------------------- +-- This module synchronizes a vector of bits from clock-domain ``Clock1`` to +-- clock-domain ``Clock2``. The clock-domain boundary crossing is done by a +-- change comparator, a T-FF, two synchronizer D-FFs and a reconstructive +-- XOR indicating a value change on the input. This changed signal is used +-- to capture the input for the new output. A busy flag is additionally +-- calculated for the input clock domain. -- --- CONSTRAINTS: --- General: --- This module uses sub modules which need to be constrainted. Please --- attend to the notes of the instantiated sub modules. +-- Constraints: +-- This module uses sub modules which need to be constrainted. Please +-- attend to the notes of the instantiated sub modules. -- -- License: -- ============================================================================= @@ -48,49 +46,49 @@ library PoC; use PoC.utils.all; -entity sync_Vector IS +entity sync_Vector is generic ( - MASTER_BITS : POSITIVE := 8; -- number of bit to be synchronized - SLAVE_BITS : NATURAL := 0; - INIT : STD_LOGIC_VECTOR := x"00000000" -- + MASTER_BITS : positive := 8; -- number of bit to be synchronized + SLAVE_BITS : natural := 0; + INIT : std_logic_vector := x"00000000" -- ); - PORT ( - Clock1 : in STD_LOGIC; -- input clock - Clock2 : in STD_LOGIC; -- output clock - Input : in STD_LOGIC_VECTOR((MASTER_BITS + SLAVE_BITS) - 1 downto 0); -- @Clock1: input vector - Output : out STD_LOGIC_VECTOR((MASTER_BITS + SLAVE_BITS) - 1 downto 0); -- @Clock2: output vector - Busy : out STD_LOGIC; -- @Clock1: busy bit - Changed : out STD_LOGIC -- @Clock2: changed bit + port ( + Clock1 : in std_logic; -- input clock + Clock2 : in std_logic; -- output clock + Input : in std_logic_vector((MASTER_BITS + SLAVE_BITS) - 1 downto 0); -- @Clock1: input vector + Output : out std_logic_vector((MASTER_BITS + SLAVE_BITS) - 1 downto 0); -- @Clock2: output vector + Busy : out std_logic; -- @Clock1: busy bit + Changed : out std_logic -- @Clock2: changed bit ); -end; +end entity; architecture rtl of sync_Vector is - attribute SHREG_EXTRACT : STRING; + attribute SHREG_EXTRACT : string; - constant INIT_I : STD_LOGIC_VECTOR := descend(INIT)((MASTER_BITS + SLAVE_BITS) - 1 downto 0); + constant INIT_I : std_logic_vector := descend(INIT)((MASTER_BITS + SLAVE_BITS) - 1 downto 0); - signal D0 : STD_LOGIC_VECTOR((MASTER_BITS + SLAVE_BITS) - 1 downto 0) := INIT_I; - signal T1 : STD_LOGIC := '0'; - signal D2 : STD_LOGIC := '0'; - signal D3 : STD_LOGIC := '0'; - signal D4 : STD_LOGIC_VECTOR((MASTER_BITS + SLAVE_BITS) - 1 downto 0) := INIT_I; + signal D0 : std_logic_vector((MASTER_BITS + SLAVE_BITS) - 1 downto 0) := INIT_I; + signal T1 : std_logic := '0'; + signal D2 : std_logic := '0'; + signal D3 : std_logic := '0'; + signal D4 : std_logic_vector((MASTER_BITS + SLAVE_BITS) - 1 downto 0) := INIT_I; - signal Changed_Clk1 : STD_LOGIC; - signal Changed_Clk2 : STD_LOGIC; - signal Busy_i : STD_LOGIC; + signal Changed_Clk1 : std_logic; + signal Changed_Clk2 : std_logic; + signal Busy_i : std_logic; -- Prevent XST from translating two FFs into SRL plus FF - attribute SHREG_EXTRACT of D0 : signal IS "NO"; - attribute SHREG_EXTRACT of T1 : signal IS "NO"; - attribute SHREG_EXTRACT of D2 : signal IS "NO"; - attribute SHREG_EXTRACT of D3 : signal IS "NO"; - attribute SHREG_EXTRACT of D4 : signal IS "NO"; + attribute SHREG_EXTRACT of D0 : signal is "NO"; + attribute SHREG_EXTRACT of T1 : signal is "NO"; + attribute SHREG_EXTRACT of D2 : signal is "NO"; + attribute SHREG_EXTRACT of D3 : signal is "NO"; + attribute SHREG_EXTRACT of D4 : signal is "NO"; - signal syncClk1_In : STD_LOGIC; - signal syncClk1_Out : STD_LOGIC; - signal syncClk2_In : STD_LOGIC; - signal syncClk2_Out : STD_LOGIC; + signal syncClk1_In : std_logic; + signal syncClk1_Out : std_logic; + signal syncClk2_In : std_logic; + signal syncClk2_Out : std_logic; begin @@ -144,4 +142,4 @@ begin Input(0) => syncClk1_In, -- @async: input bits Output(0) => syncClk1_Out -- @Clock: output bits ); -end; \ No newline at end of file +end; diff --git a/src/net/arp/arp_BroadCast_Receiver.vhdl b/src/net/arp/arp_BroadCast_Receiver.vhdl index df5fdaff..ef3ff7ba 100644 --- a/src/net/arp/arp_BroadCast_Receiver.vhdl +++ b/src/net/arp/arp_BroadCast_Receiver.vhdl @@ -1,18 +1,17 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: TODO +-- Entity: TODO -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -27,7 +26,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -42,41 +41,41 @@ use PoC.net.all; entity arp_BroadCast_Receiver is generic ( - ALLOWED_PROTOCOL_IPV4 : BOOLEAN := TRUE; - ALLOWED_PROTOCOL_IPV6 : BOOLEAN := FALSE + ALLOWED_PROTOCOL_IPV4 : boolean := TRUE; + ALLOWED_PROTOCOL_IPV6 : boolean := FALSE ); port ( - Clock : in STD_LOGIC; -- - Reset : in STD_LOGIC; -- + Clock : in std_logic; -- + Reset : in std_logic; -- - RX_Valid : in STD_LOGIC; + RX_Valid : in std_logic; RX_Data : in T_SLV_8; - RX_SOF : in STD_LOGIC; - RX_EOF : in STD_LOGIC; - RX_Ack : out STD_LOGIC; - RX_Meta_rst : out STD_LOGIC; - RX_Meta_SrcMACAddress_nxt : out STD_LOGIC; + RX_SOF : in std_logic; + RX_EOF : in std_logic; + RX_Ack : out std_logic; + RX_Meta_rst : out std_logic; + RX_Meta_SrcMACAddress_nxt : out std_logic; RX_Meta_SrcMACAddress_Data : in T_SLV_8; - RX_Meta_DestMACAddress_nxt : out STD_LOGIC; + RX_Meta_DestMACAddress_nxt : out std_logic; RX_Meta_DestMACAddress_Data : in T_SLV_8; - Clear : in STD_LOGIC; - Error : OUT STD_LOGIC; + Clear : in std_logic; + Error : out std_logic; - RequestReceived : out STD_LOGIC; - Address_rst : in STD_LOGIC; - SenderMACAddress_nxt : in STD_LOGIC; + RequestReceived : out std_logic; + Address_rst : in std_logic; + SenderMACAddress_nxt : in std_logic; SenderMACAddress_Data : out T_SLV_8; - SenderIPAddress_nxt : in STD_LOGIC; + SenderIPAddress_nxt : in std_logic; SenderIPAddress_Data : out T_SLV_8; - TargetIPAddress_nxt : in STD_LOGIC; + TargetIPAddress_nxt : in std_logic; TargetIPAddress_Data : out T_SLV_8 ); end entity; architecture rtl of arp_BroadCast_Receiver is - attribute FSM_ENCODING : STRING; + attribute FSM_ENCODING : string; type T_STATE is ( ST_IDLE, @@ -95,57 +94,57 @@ architecture rtl of arp_BroadCast_Receiver is signal NextState : T_STATE; attribute FSM_ENCODING of State : signal is "gray"; --"speed1"; - signal Is_SOF : STD_LOGIC; - signal Is_EOF : STD_LOGIC; + signal Is_SOF : std_logic; + signal Is_EOF : std_logic; - constant HARDWARE_ADDRESS_LENGTH : POSITIVE := 6; -- MAC -> 6 bytes - constant PROTOCOL_IPV4_ADDRESS_LENGTH : POSITIVE := 4; -- IPv4 -> 4 bytes - constant PROTOCOL_IPV6_ADDRESS_LENGTH : POSITIVE := 16; -- IPv6 -> 16 bytes - constant PROTOCOL_ADDRESS_LENGTH : POSITIVE := ite((ALLOWED_PROTOCOL_IPV6 = FALSE), PROTOCOL_IPV4_ADDRESS_LENGTH, PROTOCOL_IPV6_ADDRESS_LENGTH); -- IPv4 -> 4 bytes; IPv6 -> 16 bytes + constant HARDWARE_ADDRESS_LENGTH : positive := 6; -- MAC -> 6 bytes + constant PROTOCOL_IPV4_ADDRESS_LENGTH : positive := 4; -- IPv4 -> 4 bytes + constant PROTOCOL_IPV6_ADDRESS_LENGTH : positive := 16; -- IPv6 -> 16 bytes + constant PROTOCOL_ADDRESS_LENGTH : positive := ite((ALLOWED_PROTOCOL_IPV6 = FALSE), PROTOCOL_IPV4_ADDRESS_LENGTH, PROTOCOL_IPV6_ADDRESS_LENGTH); -- IPv4 -> 4 bytes; IPv6 -> 16 bytes - subtype T_HARDWARE_ADDRESS_INDEX is NATURAL range 0 to HARDWARE_ADDRESS_LENGTH - 1; - subtype T_PROTOCOL_ADDRESS_INDEX is NATURAL range 0 to PROTOCOL_ADDRESS_LENGTH - 1; + subtype T_HARDWARE_ADDRESS_INDEX is natural range 0 to HARDWARE_ADDRESS_LENGTH - 1; + subtype T_PROTOCOL_ADDRESS_INDEX is natural range 0 to PROTOCOL_ADDRESS_LENGTH - 1; - signal IsIPv4_set : STD_LOGIC; - signal IsIPv4_r : STD_LOGIC := '0'; - signal IsIPv6_set : STD_LOGIC; - signal IsIPv6_r : STD_LOGIC := '0'; + signal IsIPv4_set : std_logic; + signal IsIPv4_r : std_logic := '0'; + signal IsIPv6_set : std_logic; + signal IsIPv6_r : std_logic := '0'; - constant WRITER_COUNTER_BITS : POSITIVE := log2ceilnz(imax(HARDWARE_ADDRESS_LENGTH, PROTOCOL_ADDRESS_LENGTH)); - signal Writer_Counter_rst : STD_LOGIC; - signal Writer_Counter_en : STD_LOGIC; - signal Writer_Counter_us : UNSIGNED(WRITER_COUNTER_BITS - 1 downto 0) := (others => '0'); + constant WRITER_COUNTER_BITS : positive := log2ceilnz(imax(HARDWARE_ADDRESS_LENGTH, PROTOCOL_ADDRESS_LENGTH)); + signal Writer_Counter_rst : std_logic; + signal Writer_Counter_en : std_logic; + signal Writer_Counter_us : unsigned(WRITER_COUNTER_BITS - 1 downto 0) := (others => '0'); - signal Reader_SenderMAC_Counter_rst : STD_LOGIC; - signal Reader_SenderMAC_Counter_en : STD_LOGIC; - signal Reader_SenderMAC_Counter_us : UNSIGNED(log2ceilnz(HARDWARE_ADDRESS_LENGTH) - 1 downto 0) := (others => '0'); + signal Reader_SenderMAC_Counter_rst : std_logic; + signal Reader_SenderMAC_Counter_en : std_logic; + signal Reader_SenderMAC_Counter_us : unsigned(log2ceilnz(HARDWARE_ADDRESS_LENGTH) - 1 downto 0) := (others => '0'); - signal Reader_SenderIP_Counter_rst : STD_LOGIC; - signal Reader_SenderIP_Counter_en : STD_LOGIC; - signal Reader_SenderIP_Counter_us : UNSIGNED(log2ceilnz(PROTOCOL_ADDRESS_LENGTH) - 1 downto 0) := (others => '0'); + signal Reader_SenderIP_Counter_rst : std_logic; + signal Reader_SenderIP_Counter_en : std_logic; + signal Reader_SenderIP_Counter_us : unsigned(log2ceilnz(PROTOCOL_ADDRESS_LENGTH) - 1 downto 0) := (others => '0'); - signal Reader_TargetIP_Counter_rst : STD_LOGIC; - signal Reader_TargetIP_Counter_en : STD_LOGIC; - signal Reader_TargetIP_Counter_us : UNSIGNED(log2ceilnz(PROTOCOL_ADDRESS_LENGTH) - 1 downto 0) := (others => '0'); + signal Reader_TargetIP_Counter_rst : std_logic; + signal Reader_TargetIP_Counter_en : std_logic; + signal Reader_TargetIP_Counter_us : unsigned(log2ceilnz(PROTOCOL_ADDRESS_LENGTH) - 1 downto 0) := (others => '0'); -- signal SenderMACAddress_Data_rst : STD_LOGIC; - signal SenderHardwareAddress_en : STD_LOGIC; - signal SenderHardwareAddress_us : UNSIGNED(log2ceilnz(HARDWARE_ADDRESS_LENGTH) - 1 downto 0); + signal SenderHardwareAddress_en : std_logic; + signal SenderHardwareAddress_us : unsigned(log2ceilnz(HARDWARE_ADDRESS_LENGTH) - 1 downto 0); signal SenderHardwareAddress_d : T_SLVV_8(HARDWARE_ADDRESS_LENGTH - 1 downto 0) := (others => (others => '0')); -- signal SenderIPv4Address_Data_rst : STD_LOGIC; - signal SenderProtocolAddress_en : STD_LOGIC; - signal SenderProtocolAddress_us : UNSIGNED(log2ceilnz(PROTOCOL_ADDRESS_LENGTH) - 1 downto 0); + signal SenderProtocolAddress_en : std_logic; + signal SenderProtocolAddress_us : unsigned(log2ceilnz(PROTOCOL_ADDRESS_LENGTH) - 1 downto 0); signal SenderProtocolAddress_d : T_SLVV_8(PROTOCOL_ADDRESS_LENGTH - 1 downto 0) := (others => (others => '0')); -- signal TargetIPv4Address_Data_rst : STD_LOGIC; - signal TargetProtocolAddress_en : STD_LOGIC; - signal TargetProtocolAddress_us : UNSIGNED(log2ceilnz(PROTOCOL_ADDRESS_LENGTH) - 1 downto 0); + signal TargetProtocolAddress_en : std_logic; + signal TargetProtocolAddress_us : unsigned(log2ceilnz(PROTOCOL_ADDRESS_LENGTH) - 1 downto 0); signal TargetProtocolAddress_d : T_SLVV_8(PROTOCOL_ADDRESS_LENGTH - 1 downto 0) := (others => (others => '0')); begin - assert (ALLOWED_PROTOCOL_IPV4 OR ALLOWED_PROTOCOL_IPV6) report "At least one protocol must be selected: IPv4, IPv6" severity FAILURE; + assert (ALLOWED_PROTOCOL_IPV4 or ALLOWED_PROTOCOL_IPV6) report "At least one protocol must be selected: IPv4, IPv6" severity FAILURE; RX_Meta_rst <= '0'; RX_Meta_SrcMACAddress_nxt <= '0'; @@ -185,17 +184,17 @@ begin Writer_Counter_rst <= '0'; Writer_Counter_en <= '0'; - Reader_SenderMAC_Counter_rst <= Clear OR Address_rst; + Reader_SenderMAC_Counter_rst <= Clear or Address_rst; Reader_SenderMAC_Counter_en <= SenderMACAddress_nxt; SenderHardwareAddress_en <= '0'; SenderHardwareAddress_us <= Writer_Counter_us(SenderHardwareAddress_us'range); - Reader_SenderIP_Counter_rst <= Clear OR Address_rst; + Reader_SenderIP_Counter_rst <= Clear or Address_rst; Reader_SenderIP_Counter_en <= SenderIPAddress_nxt; SenderProtocolAddress_en <= '0'; SenderProtocolAddress_us <= Writer_Counter_us(SenderProtocolAddress_us'range); - Reader_TargetIP_Counter_rst <= Clear OR Address_rst; + Reader_TargetIP_Counter_rst <= Clear or Address_rst; Reader_TargetIP_Counter_en <= TargetIPAddress_nxt; TargetProtocolAddress_en <= '0'; TargetProtocolAddress_us <= Writer_Counter_us(TargetProtocolAddress_us'range); @@ -445,7 +444,7 @@ begin process(Clock) begin if rising_edge(Clock) then - if ((Reset OR Clear) = '1') then + if ((Reset or Clear) = '1') then IsIPv4_r <= '0'; IsIPv6_r <= '0'; else @@ -508,8 +507,8 @@ begin end if; end process; - SenderMACAddress_Data <= SenderHardwareAddress_d(ite((NOT SIMULATION), to_integer(Reader_SenderMAC_Counter_us), imin(to_integer(Reader_SenderMAC_Counter_us), 5))); - SenderIPAddress_Data <= SenderProtocolAddress_d(ite((NOT SIMULATION), to_integer(Reader_SenderIP_Counter_us), imin(to_integer(Reader_SenderIP_Counter_us), 3))); - TargetIPAddress_Data <= TargetProtocolAddress_d(ite((NOT SIMULATION), to_integer(Reader_TargetIP_Counter_us), imin(to_integer(Reader_TargetIP_Counter_us), 3))); + SenderMACAddress_Data <= SenderHardwareAddress_d(ite((not SIMULATION), to_integer(Reader_SenderMAC_Counter_us), imin(to_integer(Reader_SenderMAC_Counter_us), 5))); + SenderIPAddress_Data <= SenderProtocolAddress_d(ite((not SIMULATION), to_integer(Reader_SenderIP_Counter_us), imin(to_integer(Reader_SenderIP_Counter_us), 3))); + TargetIPAddress_Data <= TargetProtocolAddress_d(ite((not SIMULATION), to_integer(Reader_TargetIP_Counter_us), imin(to_integer(Reader_TargetIP_Counter_us), 3))); end architecture; diff --git a/src/net/arp/arp_BroadCast_Requester.vhdl b/src/net/arp/arp_BroadCast_Requester.vhdl index 6f2162a3..8c4093ea 100644 --- a/src/net/arp/arp_BroadCast_Requester.vhdl +++ b/src/net/arp/arp_BroadCast_Requester.vhdl @@ -1,18 +1,17 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: TODO +-- Entity: TODO -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -27,7 +26,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -42,40 +41,40 @@ use PoC.net.all; entity arp_BroadCast_Requester is generic ( - ALLOWED_PROTOCOL_IPV4 : BOOLEAN := TRUE; - ALLOWED_PROTOCOL_IPV6 : BOOLEAN := FALSE + ALLOWED_PROTOCOL_IPV4 : boolean := TRUE; + ALLOWED_PROTOCOL_IPV6 : boolean := FALSE ); port ( - Clock : in STD_LOGIC; -- - Reset : in STD_LOGIC; -- + Clock : in std_logic; -- + Reset : in std_logic; -- - SendRequest : in STD_LOGIC; - Complete : out STD_LOGIC; + SendRequest : in std_logic; + Complete : out std_logic; - Address_rst : out STD_LOGIC; - SenderMACAddress_nxt : out STD_LOGIC; + Address_rst : out std_logic; + SenderMACAddress_nxt : out std_logic; SenderMACAddress_Data : in T_SLV_8; - SenderIPv4Address_nxt : out STD_LOGIC; + SenderIPv4Address_nxt : out std_logic; SenderIPv4Address_Data : in T_SLV_8; - TargetMACAddress_nxt : out STD_LOGIC; + TargetMACAddress_nxt : out std_logic; TargetMACAddress_Data : in T_SLV_8; - TargetIPv4Address_nxt : out STD_LOGIC; + TargetIPv4Address_nxt : out std_logic; TargetIPv4Address_Data : in T_SLV_8; - TX_Valid : out STD_LOGIC; + TX_Valid : out std_logic; TX_Data : out T_SLV_8; - TX_SOF : out STD_LOGIC; - TX_EOF : out STD_LOGIC; - TX_Ack : in STD_LOGIC; - TX_Meta_DestMACAddress_rst : in STD_LOGIC; - TX_Meta_DestMACAddress_nxt : in STD_LOGIC; + TX_SOF : out std_logic; + TX_EOF : out std_logic; + TX_Ack : in std_logic; + TX_Meta_DestMACAddress_rst : in std_logic; + TX_Meta_DestMACAddress_nxt : in std_logic; TX_Meta_DestMACAddress_Data : out T_SLV_8 ); end entity; architecture rtl of arp_BroadCast_Requester is - attribute FSM_ENCODING : STRING; + attribute FSM_ENCODING : string; type T_STATE is ( ST_IDLE, @@ -92,18 +91,18 @@ architecture rtl of arp_BroadCast_Requester is signal NextState : T_STATE; attribute FSM_ENCODING of State : signal is "gray"; - constant HARDWARE_ADDRESS_LENGTH : POSITIVE := 6; -- MAC -> 6 bytes - constant PROTOCOL_IPV4_ADDRESS_LENGTH : POSITIVE := 4; -- IPv4 -> 4 bytes - constant PROTOCOL_IPV6_ADDRESS_LENGTH : POSITIVE := 16; -- IPv6 -> 16 bytes - constant PROTOCOL_ADDRESS_LENGTH : POSITIVE := ite((ALLOWED_PROTOCOL_IPV6 = FALSE), PROTOCOL_IPV4_ADDRESS_LENGTH, PROTOCOL_IPV6_ADDRESS_LENGTH); -- IPv4 -> 4 bytes; IPv6 -> 16 bytes + constant HARDWARE_ADDRESS_LENGTH : positive := 6; -- MAC -> 6 bytes + constant PROTOCOL_IPV4_ADDRESS_LENGTH : positive := 4; -- IPv4 -> 4 bytes + constant PROTOCOL_IPV6_ADDRESS_LENGTH : positive := 16; -- IPv6 -> 16 bytes + constant PROTOCOL_ADDRESS_LENGTH : positive := ite((ALLOWED_PROTOCOL_IPV6 = FALSE), PROTOCOL_IPV4_ADDRESS_LENGTH, PROTOCOL_IPV6_ADDRESS_LENGTH); -- IPv4 -> 4 bytes; IPv6 -> 16 bytes - signal IsIPv4_l : STD_LOGIC := '1'; - signal IsIPv6_l : STD_LOGIC := '0'; + signal IsIPv4_l : std_logic := '1'; + signal IsIPv6_l : std_logic := '0'; - constant READER_COUNTER_BITS : POSITIVE := log2ceilnz(imax(HARDWARE_ADDRESS_LENGTH, PROTOCOL_ADDRESS_LENGTH)); - signal Reader_Counter_rst : STD_LOGIC; - signal Reader_Counter_en : STD_LOGIC; - signal Reader_Counter_us : UNSIGNED(READER_COUNTER_BITS - 1 downto 0) := (others => '0'); + constant READER_COUNTER_BITS : positive := log2ceilnz(imax(HARDWARE_ADDRESS_LENGTH, PROTOCOL_ADDRESS_LENGTH)); + signal Reader_Counter_rst : std_logic; + signal Reader_Counter_en : std_logic; + signal Reader_Counter_us : unsigned(READER_COUNTER_BITS - 1 downto 0) := (others => '0'); begin IsIPv4_l <= '1'; @@ -260,10 +259,10 @@ begin SenderIPv4Address_nxt <= '1'; Reader_Counter_en <= '1'; - if ((IsIPv4_l = '1') AND (Reader_Counter_us = (PROTOCOL_IPV4_ADDRESS_LENGTH - 1))) then + if ((IsIPv4_l = '1') and (Reader_Counter_us = (PROTOCOL_IPV4_ADDRESS_LENGTH - 1))) then Reader_Counter_rst <= '1'; NextState <= ST_SEND_TARGET_MAC; - elsif ((IsIPv6_l = '1') AND (Reader_Counter_us = (PROTOCOL_IPV6_ADDRESS_LENGTH - 1))) then + elsif ((IsIPv6_l = '1') and (Reader_Counter_us = (PROTOCOL_IPV6_ADDRESS_LENGTH - 1))) then Reader_Counter_rst <= '1'; NextState <= ST_SEND_TARGET_MAC; end if; @@ -291,11 +290,11 @@ begin TargetIPv4Address_nxt <= '1'; Reader_Counter_en <= '1'; - if ((IsIPv4_l = '1') AND (Reader_Counter_us = (PROTOCOL_IPV4_ADDRESS_LENGTH - 1))) then + if ((IsIPv4_l = '1') and (Reader_Counter_us = (PROTOCOL_IPV4_ADDRESS_LENGTH - 1))) then TX_EOF <= '1'; Reader_Counter_rst <= '1'; NextState <= ST_COMPLETE; - elsif ((IsIPv6_l = '1') AND (Reader_Counter_us = (PROTOCOL_IPV6_ADDRESS_LENGTH - 1))) then + elsif ((IsIPv6_l = '1') and (Reader_Counter_us = (PROTOCOL_IPV6_ADDRESS_LENGTH - 1))) then TX_EOF <= '1'; Reader_Counter_rst <= '1'; NextState <= ST_COMPLETE; @@ -313,7 +312,7 @@ begin process(Clock) begin if rising_edge(Clock) then - if ((Reset OR Reader_Counter_rst) = '1') then + if ((Reset or Reader_Counter_rst) = '1') then Reader_Counter_us <= (others => '0'); elsif (Reader_Counter_en = '1') then Reader_Counter_us <= Reader_Counter_us + 1; diff --git a/src/net/arp/arp_Cache.vhdl b/src/net/arp/arp_Cache.vhdl index ea02668a..0fcb17f3 100644 --- a/src/net/arp/arp_Cache.vhdl +++ b/src/net/arp/arp_Cache.vhdl @@ -1,18 +1,17 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: TODO +-- Entity: TODO -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -27,7 +26,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -45,47 +44,47 @@ use PoC.net.all; entity arp_Cache is generic ( CLOCK_FREQ : FREQ := 125 MHz; - REPLACEMENT_POLICY : STRING := "LRU"; + REPLACEMENT_POLICY : string := "LRU"; TAG_BYTE_ORDER : T_BYTE_ORDER := BIG_ENDIAN; DATA_BYTE_ORDER : T_BYTE_ORDER := BIG_ENDIAN; INITIAL_CACHE_CONTENT : T_NET_ARP_ARPCACHE_VECTOR ); port ( - Clock : in STD_LOGIC; -- - Reset : in STD_LOGIC; -- + Clock : in std_logic; -- + Reset : in std_logic; -- Command : in T_NET_ARP_ARPCACHE_COMMAND; Status : out T_NET_ARP_ARPCACHE_STATUS; - NewIPv4Address_rst : out STD_LOGIC; - NewIPv4Address_nxt : out STD_LOGIC; + NewIPv4Address_rst : out std_logic; + NewIPv4Address_nxt : out std_logic; NewIPv4Address_Data : in T_SLV_8; - NewMACAddress_rst : out STD_LOGIC; - NewMACAddress_nxt : out STD_LOGIC; + NewMACAddress_rst : out std_logic; + NewMACAddress_nxt : out std_logic; NewMACAddress_Data : in T_SLV_8; - Lookup : in STD_LOGIC; - IPv4Address_rst : out STD_LOGIC; - IPv4Address_nxt : out STD_LOGIC; + Lookup : in std_logic; + IPv4Address_rst : out std_logic; + IPv4Address_nxt : out std_logic; IPv4Address_Data : in T_SLV_8; CacheResult : out T_CACHE_RESULT; - MACAddress_rst : in STD_LOGIC; - MACAddress_nxt : in STD_LOGIC; + MACAddress_rst : in std_logic; + MACAddress_nxt : in std_logic; MACAddress_Data : out T_SLV_8 ); end entity; architecture rtl of arp_Cache is - constant CACHE_LINES : POSITIVE := 8; - constant TAG_BITS : POSITIVE := 32; -- IPv4 address - constant DATA_BITS : POSITIVE := 48; -- MAC address - constant TAGCHUNK_BITS : POSITIVE := 8; - constant DATACHUNK_BITS : POSITIVE := 8; + constant CACHE_LINES : positive := 8; + constant TAG_BITS : positive := 32; -- IPv4 address + constant DATA_BITS : positive := 48; -- MAC address + constant TAGCHUNK_BITS : positive := 8; + constant DATACHUNK_BITS : positive := 8; - constant DATACHUNKS : POSITIVE := div_ceil(DATA_BITS, DATACHUNK_BITS); - constant DATACHUNK_INDEX_BITS : POSITIVE := log2ceilnz(DATACHUNKS); - constant CACHEMEMORY_INDEX_BITS : POSITIVE := log2ceilnz(CACHE_LINES); + constant DATACHUNKS : positive := div_ceil(DATA_BITS, DATACHUNK_BITS); + constant DATACHUNK_INDEX_BITS : positive := log2ceilnz(DATACHUNKS); + constant CACHEMEMORY_INDEX_BITS : positive := log2ceilnz(CACHE_LINES); function to_TagData(CacheContent : T_NET_ARP_ARPCACHE_VECTOR) return T_SLM is -- variable slvv : T_SLVV_32(CACHE_LINES - 1 downto 0) := (others => (others => '0')); @@ -107,7 +106,7 @@ architecture rtl of arp_Cache is end function; function to_CacheMemory(CacheContent : T_NET_ARP_ARPCACHE_VECTOR) return T_SLVV_8 is - constant BYTES_PER_LINE : POSITIVE := 6; + constant BYTES_PER_LINE : positive := 6; constant slvv : T_SLVV_48(CACHE_LINES - 1 downto 0) := to_CacheData_slvv_48(CacheContent); variable result : T_SLVV_8((CACHE_LINES * BYTES_PER_LINE) - 1 downto 0); begin @@ -123,55 +122,55 @@ architecture rtl of arp_Cache is constant INITIAL_DATALINES : T_SLVV_8 := to_CacheMemory(INITIAL_CACHE_CONTENT); - signal ReadWrite : STD_LOGIC; + signal ReadWrite : std_logic; type T_FSMREPLACE_STATE is (ST_IDLE, ST_REPLACE); signal FSMReplace_State : T_FSMREPLACE_STATE := ST_IDLE; signal FSMReplace_NextState : T_FSMREPLACE_STATE; - signal Insert : STD_LOGIC; + signal Insert : std_logic; - signal TU_NewTag_rst : STD_LOGIC; - signal TU_NewTag_nxt : STD_LOGIC; + signal TU_NewTag_rst : std_logic; + signal TU_NewTag_nxt : std_logic; signal NewTag_Data : T_SLV_8; signal NewCacheLine_Data : T_SLV_8; - signal TU_Tag_rst : STD_LOGIC; - signal TU_Tag_nxt : STD_LOGIC; + signal TU_Tag_rst : std_logic; + signal TU_Tag_nxt : std_logic; signal TU_Tag_Data : T_SLV_8; - signal CacheHit : STD_LOGIC; - signal CacheMiss : STD_LOGIC; + signal CacheHit : std_logic; + signal CacheMiss : std_logic; - signal TU_Index : STD_LOGIC_VECTOR(CACHEMEMORY_INDEX_BITS - 1 downto 0); - signal TU_Index_d : STD_LOGIC_VECTOR(CACHEMEMORY_INDEX_BITS - 1 downto 0); + signal TU_Index : std_logic_vector(CACHEMEMORY_INDEX_BITS - 1 downto 0); + signal TU_Index_d : std_logic_vector(CACHEMEMORY_INDEX_BITS - 1 downto 0); -- signal TU_Index_us : UNSIGNED(CACHEMEMORY_INDEX_BITS - 1 downto 0); - signal TU_NewIndex : STD_LOGIC_VECTOR(CACHEMEMORY_INDEX_BITS - 1 downto 0); - signal TU_Replaced : STD_LOGIC; + signal TU_NewIndex : std_logic_vector(CACHEMEMORY_INDEX_BITS - 1 downto 0); + signal TU_Replaced : std_logic; - signal TU_TagHit : STD_LOGIC; - signal TU_TagMiss : STD_LOGIC; + signal TU_TagHit : std_logic; + signal TU_TagMiss : std_logic; constant TICKCOUNTER_RES : T_TIME := 10.0e-3; - constant TICKCOUNTER_MAX : POSITIVE := TimingToCycles(TICKCOUNTER_RES, CLOCK_FREQ); - constant TICKCOUNTER_BITS : POSITIVE := log2ceilnz(TICKCOUNTER_MAX); + constant TICKCOUNTER_MAX : positive := TimingToCycles(TICKCOUNTER_RES, CLOCK_FREQ); + constant TICKCOUNTER_BITS : positive := log2ceilnz(TICKCOUNTER_MAX); - signal TickCounter_s : SIGNED(TICKCOUNTER_BITS downto 0) := to_signed(TICKCOUNTER_MAX, TICKCOUNTER_BITS + 1); - signal Tick : STD_LOGIC; + signal TickCounter_s : signed(TICKCOUNTER_BITS downto 0) := to_signed(TICKCOUNTER_MAX, TICKCOUNTER_BITS + 1); + signal Tick : std_logic; - signal Exp_Expired : STD_LOGIC; - signal Exp_KeyOut : STD_LOGIC_VECTOR(CACHEMEMORY_INDEX_BITS - 1 downto 0); + signal Exp_Expired : std_logic; + signal Exp_KeyOut : std_logic_vector(CACHEMEMORY_INDEX_BITS - 1 downto 0); - signal DataChunkIndex_us : UNSIGNED((CACHEMEMORY_INDEX_BITS + DATACHUNK_INDEX_BITS) - 1 downto 0) := (others => '0'); - signal DataChunkIndex_l_us : UNSIGNED((CACHEMEMORY_INDEX_BITS + DATACHUNK_INDEX_BITS) - 1 downto 0) := (others => '0'); - signal NewDataChunkIndex_en : STD_LOGIC; - signal NewDataChunkIndex_us : UNSIGNED((CACHEMEMORY_INDEX_BITS + DATACHUNK_INDEX_BITS) - 1 downto 0) := (others => '0'); - signal NewDataChunkIndex_max_us : UNSIGNED((CACHEMEMORY_INDEX_BITS + DATACHUNK_INDEX_BITS) - 1 downto 0) := (others => '0'); - signal CacheMemory_we : STD_LOGIC; + signal DataChunkIndex_us : unsigned((CACHEMEMORY_INDEX_BITS + DATACHUNK_INDEX_BITS) - 1 downto 0) := (others => '0'); + signal DataChunkIndex_l_us : unsigned((CACHEMEMORY_INDEX_BITS + DATACHUNK_INDEX_BITS) - 1 downto 0) := (others => '0'); + signal NewDataChunkIndex_en : std_logic; + signal NewDataChunkIndex_us : unsigned((CACHEMEMORY_INDEX_BITS + DATACHUNK_INDEX_BITS) - 1 downto 0) := (others => '0'); + signal NewDataChunkIndex_max_us : unsigned((CACHEMEMORY_INDEX_BITS + DATACHUNK_INDEX_BITS) - 1 downto 0) := (others => '0'); + signal CacheMemory_we : std_logic; signal CacheMemory : T_SLVV_8((CACHE_LINES * T_NET_MAC_ADDRESS'length) - 1 downto 0) := INITIAL_DATALINES; - signal Memory_ReadWrite : STD_LOGIC; + signal Memory_ReadWrite : std_logic; begin process(Clock) @@ -201,11 +200,11 @@ begin Insert <= '0'; - case FSMReplace_State IS + case FSMReplace_State is when ST_IDLE => NewMACAddress_rst <= '1'; - case Command IS + case Command is when NET_ARP_ARPCACHE_CMD_NONE => null; @@ -250,7 +249,7 @@ begin CacheResult <= to_Cache_Result(CacheHit, CacheMiss); -- Cache TagUnit --- TU : entity L_Global.Cache_TagUnit_seq +-- TU : entity PoC.Cache_TagUnit_seq TU : entity PoC.cache_TagUnit_seq generic map ( REPLACEMENT_POLICY => REPLACEMENT_POLICY, @@ -300,7 +299,7 @@ begin Tick <= TickCounter_s(TickCounter_s'high); --- Exp : entity L_Global.list_expire +-- Exp : entity PoC.list_expire Exp : entity PoC.list_expire generic map ( CLOCK_CYCLE_TICKS => 65536, @@ -350,7 +349,7 @@ begin -- DataChunkIndex counter process(Clock, TU_Index) - variable temp : UNSIGNED(DataChunkIndex_us'range); + variable temp : unsigned(DataChunkIndex_us'range); begin if (DATA_BYTE_ORDER = LITTLE_ENDIAN) then temp := resize(unsigned(TU_Index) * 6, DataChunkIndex_us'length); diff --git a/src/net/arp/arp_IPPool.vhdl b/src/net/arp/arp_IPPool.vhdl index 6d898522..a2c98d6c 100644 --- a/src/net/arp/arp_IPPool.vhdl +++ b/src/net/arp/arp_IPPool.vhdl @@ -1,18 +1,17 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: TODO +-- Entity: TODO -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -27,7 +26,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -43,20 +42,20 @@ use PoC.net.all; entity arp_IPPool is generic ( - IPPOOL_SIZE : POSITIVE; + IPPOOL_SIZE : positive; INITIAL_IPV4ADDRESSES : T_NET_IPV4_ADDRESS_VECTOR := (0 to 7 => C_NET_IPV4_ADDRESS_EMPTY) ); port ( - Clock : in STD_LOGIC; -- - Reset : in STD_LOGIC; -- + Clock : in std_logic; -- + Reset : in std_logic; -- -- Command : in T_ETHERNET_ARP_IPPOOL_COMMAND; -- IPv4Address : in T_NET_IPV4_ADDRESS; -- MACAddress : in T_ETHERNET_MAC_ADDRESS; - Lookup : in STD_LOGIC; - IPv4Address_rst : out STD_LOGIC; - IPv4Address_nxt : out STD_LOGIC; + Lookup : in std_logic; + IPv4Address_rst : out std_logic; + IPv4Address_nxt : out std_logic; IPv4Address_Data : in T_SLV_8; PoolResult : out T_CACHE_RESULT @@ -65,13 +64,13 @@ end entity; architecture rtl of arp_IPPool is - constant CACHE_LINES : POSITIVE := imax(IPPOOL_SIZE, INITIAL_IPV4ADDRESSES'length); - constant TAG_BITS : POSITIVE := 32; - constant TAGCHUNK_BITS : POSITIVE := 8; + constant CACHE_LINES : positive := imax(IPPOOL_SIZE, INITIAL_IPV4ADDRESSES'length); + constant TAG_BITS : positive := 32; + constant TAGCHUNK_BITS : positive := 8; -- constant TAGCHUNKS : POSITIVE := div_ceil(TAG_BITS, CHUNK_BITS); -- constant CHUNK_INDEX_BITS : POSITIVE := log2ceilnz(CHUNKS); - constant CACHEMEMORY_INDEX_BITS : POSITIVE := log2ceilnz(CACHE_LINES); + constant CACHEMEMORY_INDEX_BITS : positive := log2ceilnz(CACHE_LINES); function to_TagData(CacheContent : T_NET_IPV4_ADDRESS_VECTOR) return T_SLM is variable slvv : T_SLVV_32(CACHE_LINES - 1 downto 0) := (others => (others => '0')); @@ -84,33 +83,33 @@ architecture rtl of arp_IPPool is constant INITIAL_TAGS : T_SLM := to_TagData(INITIAL_IPV4ADDRESSES); - signal ReadWrite : STD_LOGIC; + signal ReadWrite : std_logic; - signal Insert : STD_LOGIC; - signal TU_NewTag_rst : STD_LOGIC; - signal TU_NewTag_nxt : STD_LOGIC; + signal Insert : std_logic; + signal TU_NewTag_rst : std_logic; + signal TU_NewTag_nxt : std_logic; signal NewTag_Data : T_SLV_8; - signal TU_Tag_rst : STD_LOGIC; - signal TU_Tag_nxt : STD_LOGIC; + signal TU_Tag_rst : std_logic; + signal TU_Tag_nxt : std_logic; signal TU_Tag_Data : T_SLV_8; - signal CacheHit : STD_LOGIC; - signal CacheMiss : STD_LOGIC; + signal CacheHit : std_logic; + signal CacheMiss : std_logic; - signal TU_Index : STD_LOGIC_VECTOR(CACHEMEMORY_INDEX_BITS - 1 downto 0); - signal TU_Index_d : STD_LOGIC_VECTOR(CACHEMEMORY_INDEX_BITS - 1 downto 0); - signal TU_Index_us : UNSIGNED(CACHEMEMORY_INDEX_BITS - 1 downto 0); - signal TU_NewIndex : STD_LOGIC_VECTOR(CACHEMEMORY_INDEX_BITS - 1 downto 0); - signal TU_Replace : STD_LOGIC; + signal TU_Index : std_logic_vector(CACHEMEMORY_INDEX_BITS - 1 downto 0); + signal TU_Index_d : std_logic_vector(CACHEMEMORY_INDEX_BITS - 1 downto 0); + signal TU_Index_us : unsigned(CACHEMEMORY_INDEX_BITS - 1 downto 0); + signal TU_NewIndex : std_logic_vector(CACHEMEMORY_INDEX_BITS - 1 downto 0); + signal TU_Replace : std_logic; - signal TU_TagHit : STD_LOGIC; - signal TU_TagMiss : STD_LOGIC; + signal TU_TagHit : std_logic; + signal TU_TagMiss : std_logic; begin -- process(Command) -- begin -- Insert <= '0'; -- --- case Command IS +-- case Command is -- when NET_NDP_NeighborCache_CMD_NONE => null; -- when NET_NDP_NeighborCache_CMD_ADD => Insert <= '1'; -- @@ -130,7 +129,7 @@ begin PoolResult <= to_Cache_Result(CacheHit, CacheMiss); -- Cache TagUnit --- TU : entity L_Global.Cache_TagUnit_seq +-- TU : entity PoC.Cache_TagUnit_seq TU : entity PoC.cache_TagUnit_seq generic map ( REPLACEMENT_POLICY => "LRU", @@ -168,4 +167,4 @@ begin CacheHit <= TU_TagHit; CacheMiss <= TU_TagMiss; -end architecture; \ No newline at end of file +end architecture; diff --git a/src/net/arp/arp_UniCast_Receiver.vhdl b/src/net/arp/arp_UniCast_Receiver.vhdl index fcb07190..8ec0f2d5 100644 --- a/src/net/arp/arp_UniCast_Receiver.vhdl +++ b/src/net/arp/arp_UniCast_Receiver.vhdl @@ -1,18 +1,17 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: TODO +-- Entity: TODO -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -27,7 +26,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -42,46 +41,46 @@ use PoC.net.all; entity arp_UniCast_Receiver is generic ( - ALLOWED_PROTOCOL_IPV4 : BOOLEAN := TRUE; - ALLOWED_PROTOCOL_IPV6 : BOOLEAN := FALSE + ALLOWED_PROTOCOL_IPV4 : boolean := TRUE; + ALLOWED_PROTOCOL_IPV6 : boolean := FALSE ); port ( - Clock : in STD_LOGIC; -- - Reset : in STD_LOGIC; -- + Clock : in std_logic; -- + Reset : in std_logic; -- - RX_Valid : in STD_LOGIC; + RX_Valid : in std_logic; RX_Data : in T_SLV_8; - RX_SOF : in STD_LOGIC; - RX_EOF : in STD_LOGIC; - RX_Ack : out STD_LOGIC; - RX_Meta_rst : out STD_LOGIC; - RX_Meta_SrcMACAddress_nxt : out STD_LOGIC; + RX_SOF : in std_logic; + RX_EOF : in std_logic; + RX_Ack : out std_logic; + RX_Meta_rst : out std_logic; + RX_Meta_SrcMACAddress_nxt : out std_logic; RX_Meta_SrcMACAddress_Data : in T_SLV_8; - RX_Meta_DestMACAddress_nxt : out STD_LOGIC; + RX_Meta_DestMACAddress_nxt : out std_logic; RX_Meta_DestMACAddress_Data : in T_SLV_8; - Clear : in STD_LOGIC; - Error : OUT STD_LOGIC; + Clear : in std_logic; + Error : out std_logic; - ResponseReceived : out STD_LOGIC; - Address_rst : in STD_LOGIC; - SenderMACAddress_nxt : in STD_LOGIC; + ResponseReceived : out std_logic; + Address_rst : in std_logic; + SenderMACAddress_nxt : in std_logic; SenderMACAddress_Data : out T_SLV_8; - SenderIPAddress_nxt : in STD_LOGIC; + SenderIPAddress_nxt : in std_logic; SenderIPAddress_Data : out T_SLV_8; - TargetIPAddress_nxt : in STD_LOGIC; + TargetIPAddress_nxt : in std_logic; TargetIPAddress_Data : out T_SLV_8; - TargetMACAddress_nxt : in STD_LOGIC; + TargetMACAddress_nxt : in std_logic; TargetMACAddress_Data : out T_SLV_8 ); end entity; architecture rtl of arp_UniCast_Receiver is - attribute FSM_ENCODING : STRING; + attribute FSM_ENCODING : string; - subtype T_MAC_BYTEINDEX is NATURAL range 0 to 5; - subtype T_IP_BYTEINDEX is NATURAL range 0 to 3; + subtype T_MAC_BYTEINDEX is natural range 0 to 5; + subtype T_IP_BYTEINDEX is natural range 0 to 3; type T_STATE is ( ST_IDLE, @@ -100,68 +99,68 @@ architecture rtl of arp_UniCast_Receiver is signal NextState : T_STATE; attribute FSM_ENCODING of State : signal is "gray"; --"speed1"; - signal Is_SOF : STD_LOGIC; - signal Is_EOF : STD_LOGIC; + signal Is_SOF : std_logic; + signal Is_EOF : std_logic; - constant HARDWARE_ADDRESS_LENGTH : POSITIVE := 6; -- MAC -> 6 bytes - constant PROTOCOL_IPV4_ADDRESS_LENGTH : POSITIVE := 4; -- IPv4 -> 4 bytes - constant PROTOCOL_IPV6_ADDRESS_LENGTH : POSITIVE := 16; -- IPv6 -> 16 bytes - constant PROTOCOL_ADDRESS_LENGTH : POSITIVE := ite((ALLOWED_PROTOCOL_IPV6 = FALSE), PROTOCOL_IPV4_ADDRESS_LENGTH, PROTOCOL_IPV6_ADDRESS_LENGTH); -- IPv4 -> 4 bytes; IPv6 -> 16 bytes + constant HARDWARE_ADDRESS_LENGTH : positive := 6; -- MAC -> 6 bytes + constant PROTOCOL_IPV4_ADDRESS_LENGTH : positive := 4; -- IPv4 -> 4 bytes + constant PROTOCOL_IPV6_ADDRESS_LENGTH : positive := 16; -- IPv6 -> 16 bytes + constant PROTOCOL_ADDRESS_LENGTH : positive := ite((ALLOWED_PROTOCOL_IPV6 = FALSE), PROTOCOL_IPV4_ADDRESS_LENGTH, PROTOCOL_IPV6_ADDRESS_LENGTH); -- IPv4 -> 4 bytes; IPv6 -> 16 bytes - subtype T_HARDWARE_ADDRESS_INDEX is NATURAL range 0 to HARDWARE_ADDRESS_LENGTH - 1; - subtype T_PROTOCOL_ADDRESS_INDEX is NATURAL range 0 to PROTOCOL_ADDRESS_LENGTH - 1; + subtype T_HARDWARE_ADDRESS_INDEX is natural range 0 to HARDWARE_ADDRESS_LENGTH - 1; + subtype T_PROTOCOL_ADDRESS_INDEX is natural range 0 to PROTOCOL_ADDRESS_LENGTH - 1; - signal IsIPv4_set : STD_LOGIC; - signal IsIPv4_r : STD_LOGIC := '0'; - signal IsIPv6_set : STD_LOGIC; - signal IsIPv6_r : STD_LOGIC := '0'; + signal IsIPv4_set : std_logic; + signal IsIPv4_r : std_logic := '0'; + signal IsIPv6_set : std_logic; + signal IsIPv6_r : std_logic := '0'; - constant WRITER_COUNTER_BITS : POSITIVE := log2ceilnz(imax(HARDWARE_ADDRESS_LENGTH, PROTOCOL_ADDRESS_LENGTH)); - signal Writer_Counter_rst : STD_LOGIC; - signal Writer_Counter_en : STD_LOGIC; - signal Writer_Counter_us : UNSIGNED(WRITER_COUNTER_BITS - 1 downto 0) := (others => '0'); + constant WRITER_COUNTER_BITS : positive := log2ceilnz(imax(HARDWARE_ADDRESS_LENGTH, PROTOCOL_ADDRESS_LENGTH)); + signal Writer_Counter_rst : std_logic; + signal Writer_Counter_en : std_logic; + signal Writer_Counter_us : unsigned(WRITER_COUNTER_BITS - 1 downto 0) := (others => '0'); - signal Reader_SenderMAC_Counter_rst : STD_LOGIC; - signal Reader_SenderMAC_Counter_en : STD_LOGIC; - signal Reader_SenderMAC_Counter_us : UNSIGNED(log2ceilnz(HARDWARE_ADDRESS_LENGTH) - 1 downto 0) := (others => '0'); + signal Reader_SenderMAC_Counter_rst : std_logic; + signal Reader_SenderMAC_Counter_en : std_logic; + signal Reader_SenderMAC_Counter_us : unsigned(log2ceilnz(HARDWARE_ADDRESS_LENGTH) - 1 downto 0) := (others => '0'); - signal Reader_SenderIP_Counter_rst : STD_LOGIC; - signal Reader_SenderIP_Counter_en : STD_LOGIC; - signal Reader_SenderIP_Counter_us : UNSIGNED(log2ceilnz(PROTOCOL_ADDRESS_LENGTH) - 1 downto 0) := (others => '0'); + signal Reader_SenderIP_Counter_rst : std_logic; + signal Reader_SenderIP_Counter_en : std_logic; + signal Reader_SenderIP_Counter_us : unsigned(log2ceilnz(PROTOCOL_ADDRESS_LENGTH) - 1 downto 0) := (others => '0'); - signal Reader_TargetMAC_Counter_rst : STD_LOGIC; - signal Reader_TargetMAC_Counter_en : STD_LOGIC; - signal Reader_TargetMAC_Counter_us : UNSIGNED(log2ceilnz(HARDWARE_ADDRESS_LENGTH) - 1 downto 0) := (others => '0'); + signal Reader_TargetMAC_Counter_rst : std_logic; + signal Reader_TargetMAC_Counter_en : std_logic; + signal Reader_TargetMAC_Counter_us : unsigned(log2ceilnz(HARDWARE_ADDRESS_LENGTH) - 1 downto 0) := (others => '0'); - signal Reader_TargetIP_Counter_rst : STD_LOGIC; - signal Reader_TargetIP_Counter_en : STD_LOGIC; - signal Reader_TargetIP_Counter_us : UNSIGNED(log2ceilnz(PROTOCOL_ADDRESS_LENGTH) - 1 downto 0) := (others => '0'); + signal Reader_TargetIP_Counter_rst : std_logic; + signal Reader_TargetIP_Counter_en : std_logic; + signal Reader_TargetIP_Counter_us : unsigned(log2ceilnz(PROTOCOL_ADDRESS_LENGTH) - 1 downto 0) := (others => '0'); - signal SenderHardwareAddress_en : STD_LOGIC; - signal SenderHardwareAddress_us : UNSIGNED(log2ceilnz(HARDWARE_ADDRESS_LENGTH) - 1 downto 0); + signal SenderHardwareAddress_en : std_logic; + signal SenderHardwareAddress_us : unsigned(log2ceilnz(HARDWARE_ADDRESS_LENGTH) - 1 downto 0); signal SenderHardwareAddress_d : T_SLVV_8(HARDWARE_ADDRESS_LENGTH - 1 downto 0) := (others => (others => '0')); - signal SenderProtocolAddress_en : STD_LOGIC; - signal SenderProtocolAddress_us : UNSIGNED(log2ceilnz(PROTOCOL_ADDRESS_LENGTH) - 1 downto 0); + signal SenderProtocolAddress_en : std_logic; + signal SenderProtocolAddress_us : unsigned(log2ceilnz(PROTOCOL_ADDRESS_LENGTH) - 1 downto 0); signal SenderProtocolAddress_d : T_SLVV_8(PROTOCOL_ADDRESS_LENGTH - 1 downto 0) := (others => (others => '0')); - signal TargetHardwareAddress_en : STD_LOGIC; - signal TargetHardwareAddress_us : UNSIGNED(log2ceilnz(HARDWARE_ADDRESS_LENGTH) - 1 downto 0); + signal TargetHardwareAddress_en : std_logic; + signal TargetHardwareAddress_us : unsigned(log2ceilnz(HARDWARE_ADDRESS_LENGTH) - 1 downto 0); signal TargetHardwareAddress_d : T_SLVV_8(HARDWARE_ADDRESS_LENGTH - 1 downto 0) := (others => (others => '0')); - signal TargetProtocolAddress_en : STD_LOGIC; - signal TargetProtocolAddress_us : UNSIGNED(log2ceilnz(PROTOCOL_ADDRESS_LENGTH) - 1 downto 0); + signal TargetProtocolAddress_en : std_logic; + signal TargetProtocolAddress_us : unsigned(log2ceilnz(PROTOCOL_ADDRESS_LENGTH) - 1 downto 0); signal TargetProtocolAddress_d : T_SLVV_8(PROTOCOL_ADDRESS_LENGTH - 1 downto 0) := (others => (others => '0')); begin - assert (ALLOWED_PROTOCOL_IPV4 OR ALLOWED_PROTOCOL_IPV6) report "At least one protocol must be selected: IPv4, IPv6" severity FAILURE; + assert (ALLOWED_PROTOCOL_IPV4 or ALLOWED_PROTOCOL_IPV6) report "At least one protocol must be selected: IPv4, IPv6" severity FAILURE; RX_Meta_rst <= '0'; RX_Meta_SrcMACAddress_nxt <= '0'; RX_Meta_DestMACAddress_nxt <= '0'; - Is_SOF <= RX_Valid AND RX_SOF; - Is_EOF <= RX_Valid AND RX_EOF; + Is_SOF <= RX_Valid and RX_SOF; + Is_EOF <= RX_Valid and RX_EOF; process(Clock) begin @@ -193,22 +192,22 @@ begin Writer_Counter_rst <= '0'; Writer_Counter_en <= '0'; - Reader_SenderMAC_Counter_rst <= Clear OR Address_rst; + Reader_SenderMAC_Counter_rst <= Clear or Address_rst; Reader_SenderMAC_Counter_en <= SenderMACAddress_nxt; SenderHardwareAddress_en <= '0'; SenderHardwareAddress_us <= Writer_Counter_us(SenderHardwareAddress_us'range); - Reader_SenderIP_Counter_rst <= Clear OR Address_rst; + Reader_SenderIP_Counter_rst <= Clear or Address_rst; Reader_SenderIP_Counter_en <= SenderIPAddress_nxt; SenderProtocolAddress_en <= '0'; SenderProtocolAddress_us <= Writer_Counter_us(SenderProtocolAddress_us'range); - Reader_TargetMAC_Counter_rst <= Clear OR Address_rst; + Reader_TargetMAC_Counter_rst <= Clear or Address_rst; Reader_TargetMAC_Counter_en <= TargetMACAddress_nxt; TargetHardwareAddress_en <= '0'; TargetHardwareAddress_us <= Writer_Counter_us(TargetHardwareAddress_us'range); - Reader_TargetIP_Counter_rst <= Clear OR Address_rst; + Reader_TargetIP_Counter_rst <= Clear or Address_rst; Reader_TargetIP_Counter_en <= TargetIPAddress_nxt; TargetProtocolAddress_en <= '0'; TargetProtocolAddress_us <= Writer_Counter_us(TargetProtocolAddress_us'range); @@ -249,10 +248,10 @@ begin RX_Ack <= '1'; if (Is_EOF = '0') then - if ((ALLOWED_PROTOCOL_IPV4 = TRUE) AND (RX_Data = x"08")) then + if ((ALLOWED_PROTOCOL_IPV4 = TRUE) and (RX_Data = x"08")) then IsIPv4_set <= '1'; NextState <= ST_RECEIVE_PROTOCOL_TYPE_1; - elsif ((ALLOWED_PROTOCOL_IPV6 = TRUE) AND (RX_Data = x"86")) then + elsif ((ALLOWED_PROTOCOL_IPV6 = TRUE) and (RX_Data = x"86")) then IsIPv6_set <= '1'; NextState <= ST_RECEIVE_PROTOCOL_TYPE_1; else @@ -268,9 +267,9 @@ begin RX_Ack <= '1'; if (Is_EOF = '0') then - if ((IsIPv4_r = '1') AND (RX_Data = x"00")) then + if ((IsIPv4_r = '1') and (RX_Data = x"00")) then NextState <= ST_RECEIVE_HARDWARE_ADDRESS_LENGTH; - elsif ((IsIPv6_r = '1') AND (RX_Data = x"66")) then + elsif ((IsIPv6_r = '1') and (RX_Data = x"66")) then NextState <= ST_RECEIVE_HARDWARE_ADDRESS_LENGTH; else NextState <= ST_DISCARD_FRAME; @@ -300,9 +299,9 @@ begin RX_Ack <= '1'; if (Is_EOF = '0') then - if ((IsIPv4_r = '1') AND (RX_Data = x"04")) then + if ((IsIPv4_r = '1') and (RX_Data = x"04")) then NextState <= ST_RECEIVE_OPERATION_0; - elsif ((IsIPv6_r = '1') AND (RX_Data = x"10")) then + elsif ((IsIPv6_r = '1') and (RX_Data = x"10")) then NextState <= ST_RECEIVE_OPERATION_0; else NextState <= ST_DISCARD_FRAME; @@ -365,10 +364,10 @@ begin SenderProtocolAddress_en <= '1'; if (Is_EOF = '0') then - if ((IsIPv4_r = '1') AND (Writer_Counter_us = (PROTOCOL_IPV4_ADDRESS_LENGTH - 1))) then + if ((IsIPv4_r = '1') and (Writer_Counter_us = (PROTOCOL_IPV4_ADDRESS_LENGTH - 1))) then Writer_Counter_rst <= '1'; NextState <= ST_RECEIVE_TARGET_MAC; - elsif ((IsIPv6_r = '1') AND (Writer_Counter_us = (PROTOCOL_IPV6_ADDRESS_LENGTH - 1))) then + elsif ((IsIPv6_r = '1') and (Writer_Counter_us = (PROTOCOL_IPV6_ADDRESS_LENGTH - 1))) then Writer_Counter_rst <= '1'; NextState <= ST_RECEIVE_TARGET_MAC; end if; @@ -400,18 +399,18 @@ begin TargetProtocolAddress_en <= '1'; if (Is_EOF = '0') then - if ((IsIPv4_r = '1') AND (Writer_Counter_us = (PROTOCOL_IPV4_ADDRESS_LENGTH - 1))) then + if ((IsIPv4_r = '1') and (Writer_Counter_us = (PROTOCOL_IPV4_ADDRESS_LENGTH - 1))) then Writer_Counter_rst <= '1'; NextState <= ST_DISCARD_ETHERNET_PADDING_BYTES; - elsif ((IsIPv6_r = '1') AND (Writer_Counter_us = (PROTOCOL_IPV6_ADDRESS_LENGTH - 1))) then + elsif ((IsIPv6_r = '1') and (Writer_Counter_us = (PROTOCOL_IPV6_ADDRESS_LENGTH - 1))) then Writer_Counter_rst <= '1'; NextState <= ST_DISCARD_ETHERNET_PADDING_BYTES; end if; else - if ((IsIPv4_r = '1') AND (Writer_Counter_us = (PROTOCOL_IPV4_ADDRESS_LENGTH - 1))) then + if ((IsIPv4_r = '1') and (Writer_Counter_us = (PROTOCOL_IPV4_ADDRESS_LENGTH - 1))) then Writer_Counter_rst <= '1'; NextState <= ST_COMPLETE; - elsif ((IsIPv6_r = '1') AND (Writer_Counter_us = (PROTOCOL_IPV6_ADDRESS_LENGTH - 1))) then + elsif ((IsIPv6_r = '1') and (Writer_Counter_us = (PROTOCOL_IPV6_ADDRESS_LENGTH - 1))) then Writer_Counter_rst <= '1'; NextState <= ST_COMPLETE; else @@ -456,7 +455,7 @@ begin process(Clock) begin if rising_edge(Clock) then - if ((Reset OR Clear) = '1') then + if ((Reset or Clear) = '1') then IsIPv4_r <= '0'; IsIPv6_r <= '0'; else diff --git a/src/net/arp/arp_UniCast_Responder.vhdl b/src/net/arp/arp_UniCast_Responder.vhdl index 97976777..4a2202fd 100644 --- a/src/net/arp/arp_UniCast_Responder.vhdl +++ b/src/net/arp/arp_UniCast_Responder.vhdl @@ -1,18 +1,17 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: TODO +-- Entity: TODO -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -27,7 +26,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -42,40 +41,40 @@ use PoC.net.all; entity arp_UniCast_Responder is generic ( - ALLOWED_PROTOCOL_IPV4 : BOOLEAN := TRUE; - ALLOWED_PROTOCOL_IPV6 : BOOLEAN := FALSE + ALLOWED_PROTOCOL_IPV4 : boolean := TRUE; + ALLOWED_PROTOCOL_IPV6 : boolean := FALSE ); port ( - Clock : in STD_LOGIC; -- - Reset : in STD_LOGIC; -- + Clock : in std_logic; -- + Reset : in std_logic; -- - SendResponse : in STD_LOGIC; - Complete : out STD_LOGIC; + SendResponse : in std_logic; + Complete : out std_logic; - Address_rst : out STD_LOGIC; - SenderMACAddress_nxt : out STD_LOGIC; + Address_rst : out std_logic; + SenderMACAddress_nxt : out std_logic; SenderMACAddress_Data : in T_SLV_8; - SenderIPv4Address_nxt : out STD_LOGIC; + SenderIPv4Address_nxt : out std_logic; SenderIPv4Address_Data : in T_SLV_8; - TargetMACAddress_nxt : out STD_LOGIC; + TargetMACAddress_nxt : out std_logic; TargetMACAddress_Data : in T_SLV_8; - TargetIPv4Address_nxt : out STD_LOGIC; + TargetIPv4Address_nxt : out std_logic; TargetIPv4Address_Data : in T_SLV_8; - TX_Valid : out STD_LOGIC; + TX_Valid : out std_logic; TX_Data : out T_SLV_8; - TX_SOF : out STD_LOGIC; - TX_EOF : out STD_LOGIC; - TX_Ack : in STD_LOGIC; - TX_Meta_DestMACAddress_rst : in STD_LOGIC; - TX_Meta_DestMACAddress_nxt : in STD_LOGIC; + TX_SOF : out std_logic; + TX_EOF : out std_logic; + TX_Ack : in std_logic; + TX_Meta_DestMACAddress_rst : in std_logic; + TX_Meta_DestMACAddress_nxt : in std_logic; TX_Meta_DestMACAddress_Data : out T_SLV_8 ); end entity; architecture rtl of arp_UniCast_Responder is - attribute FSM_ENCODING : STRING; + attribute FSM_ENCODING : string; type T_STATE is ( ST_IDLE, @@ -92,18 +91,18 @@ architecture rtl of arp_UniCast_Responder is signal NextState : T_STATE; attribute FSM_ENCODING of State : signal is "gray"; - constant HARDWARE_ADDRESS_LENGTH : POSITIVE := 6; -- MAC -> 6 bytes - constant PROTOCOL_IPV4_ADDRESS_LENGTH : POSITIVE := 4; -- IPv4 -> 4 bytes - constant PROTOCOL_IPV6_ADDRESS_LENGTH : POSITIVE := 16; -- IPv6 -> 16 bytes - constant PROTOCOL_ADDRESS_LENGTH : POSITIVE := ite((ALLOWED_PROTOCOL_IPV6 = FALSE), PROTOCOL_IPV4_ADDRESS_LENGTH, PROTOCOL_IPV6_ADDRESS_LENGTH); -- IPv4 -> 4 bytes; IPv6 -> 16 bytes + constant HARDWARE_ADDRESS_LENGTH : positive := 6; -- MAC -> 6 bytes + constant PROTOCOL_IPV4_ADDRESS_LENGTH : positive := 4; -- IPv4 -> 4 bytes + constant PROTOCOL_IPV6_ADDRESS_LENGTH : positive := 16; -- IPv6 -> 16 bytes + constant PROTOCOL_ADDRESS_LENGTH : positive := ite((ALLOWED_PROTOCOL_IPV6 = FALSE), PROTOCOL_IPV4_ADDRESS_LENGTH, PROTOCOL_IPV6_ADDRESS_LENGTH); -- IPv4 -> 4 bytes; IPv6 -> 16 bytes - signal IsIPv4_l : STD_LOGIC; - signal IsIPv6_l : STD_LOGIC; + signal IsIPv4_l : std_logic; + signal IsIPv6_l : std_logic; - constant READER_COUNTER_BITS : POSITIVE := log2ceilnz(imax(HARDWARE_ADDRESS_LENGTH, PROTOCOL_ADDRESS_LENGTH)); - signal Reader_Counter_rst : STD_LOGIC; - signal Reader_Counter_en : STD_LOGIC; - signal Reader_Counter_us : UNSIGNED(READER_COUNTER_BITS - 1 downto 0) := (others => '0'); + constant READER_COUNTER_BITS : positive := log2ceilnz(imax(HARDWARE_ADDRESS_LENGTH, PROTOCOL_ADDRESS_LENGTH)); + signal Reader_Counter_rst : std_logic; + signal Reader_Counter_en : std_logic; + signal Reader_Counter_us : unsigned(READER_COUNTER_BITS - 1 downto 0) := (others => '0'); begin @@ -261,10 +260,10 @@ begin SenderIPv4Address_nxt <= '1'; Reader_Counter_en <= '1'; - if ((IsIPv4_l = '1') AND (Reader_Counter_us = (PROTOCOL_IPV4_ADDRESS_LENGTH - 1))) then + if ((IsIPv4_l = '1') and (Reader_Counter_us = (PROTOCOL_IPV4_ADDRESS_LENGTH - 1))) then Reader_Counter_rst <= '1'; NextState <= ST_SEND_TARGET_MAC; - elsif ((IsIPv6_l = '1') AND (Reader_Counter_us = (PROTOCOL_IPV6_ADDRESS_LENGTH - 1))) then + elsif ((IsIPv6_l = '1') and (Reader_Counter_us = (PROTOCOL_IPV6_ADDRESS_LENGTH - 1))) then Reader_Counter_rst <= '1'; NextState <= ST_SEND_TARGET_MAC; end if; @@ -292,11 +291,11 @@ begin TargetIPv4Address_nxt <= '1'; Reader_Counter_en <= '1'; - if ((IsIPv4_l = '1') AND (Reader_Counter_us = (PROTOCOL_IPV4_ADDRESS_LENGTH - 1))) then + if ((IsIPv4_l = '1') and (Reader_Counter_us = (PROTOCOL_IPV4_ADDRESS_LENGTH - 1))) then TX_EOF <= '1'; Reader_Counter_rst <= '1'; NextState <= ST_COMPLETE; - elsif ((IsIPv6_l = '1') AND (Reader_Counter_us = (PROTOCOL_IPV6_ADDRESS_LENGTH - 1))) then + elsif ((IsIPv6_l = '1') and (Reader_Counter_us = (PROTOCOL_IPV6_ADDRESS_LENGTH - 1))) then TX_EOF <= '1'; Reader_Counter_rst <= '1'; NextState <= ST_COMPLETE; @@ -313,7 +312,7 @@ begin process(Clock) begin if rising_edge(Clock) then - if ((Reset OR Reader_Counter_rst) = '1') then + if ((Reset or Reader_Counter_rst) = '1') then Reader_Counter_us <= (others => '0'); elsif (Reader_Counter_en = '1') then Reader_Counter_us <= Reader_Counter_us + 1; diff --git a/src/net/arp/arp_Wrapper.vhdl b/src/net/arp/arp_Wrapper.vhdl index e55ca22c..0dda7230 100644 --- a/src/net/arp/arp_Wrapper.vhdl +++ b/src/net/arp/arp_Wrapper.vhdl @@ -1,18 +1,17 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: TODO +-- Entity: TODO -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -27,7 +26,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -51,51 +50,51 @@ entity arp_Wrapper is APR_REQUEST_TIMEOUT : T_TIME := 100.0e-3 ); port ( - Clock : in STD_LOGIC; - Reset : in STD_LOGIC; + Clock : in std_logic; + Reset : in std_logic; - IPPool_Announce : in STD_LOGIC; - IPPool_Announced : out STD_LOGIC; + IPPool_Announce : in std_logic; + IPPool_Announced : out std_logic; - IPCache_Lookup : in STD_LOGIC; - IPCache_IPv4Address_rst : out STD_LOGIC; - IPCache_IPv4Address_nxt : out STD_LOGIC; + IPCache_Lookup : in std_logic; + IPCache_IPv4Address_rst : out std_logic; + IPCache_IPv4Address_nxt : out std_logic; IPCache_IPv4Address_Data : in T_SLV_8; - IPCache_Valid : out STD_LOGIC; - IPCache_MACAddress_rst : in STD_LOGIC; - IPCache_MACAddress_nxt : in STD_LOGIC; + IPCache_Valid : out std_logic; + IPCache_MACAddress_rst : in std_logic; + IPCache_MACAddress_nxt : in std_logic; IPCache_MACAddress_Data : out T_SLV_8; - Eth_UC_TX_Valid : out STD_LOGIC; + Eth_UC_TX_Valid : out std_logic; Eth_UC_TX_Data : out T_SLV_8; - Eth_UC_TX_SOF : out STD_LOGIC; - Eth_UC_TX_EOF : out STD_LOGIC; - Eth_UC_TX_Ack : in STD_LOGIC; - Eth_UC_TX_Meta_rst : in STD_LOGIC; - Eth_UC_TX_Meta_DestMACAddress_nxt : in STD_LOGIC; + Eth_UC_TX_SOF : out std_logic; + Eth_UC_TX_EOF : out std_logic; + Eth_UC_TX_Ack : in std_logic; + Eth_UC_TX_Meta_rst : in std_logic; + Eth_UC_TX_Meta_DestMACAddress_nxt : in std_logic; Eth_UC_TX_Meta_DestMACAddress_Data : out T_SLV_8; - Eth_UC_RX_Valid : in STD_LOGIC; + Eth_UC_RX_Valid : in std_logic; Eth_UC_RX_Data : in T_SLV_8; - Eth_UC_RX_SOF : in STD_LOGIC; - Eth_UC_RX_EOF : in STD_LOGIC; - Eth_UC_RX_Ack : out STD_LOGIC; - Eth_UC_RX_Meta_rst : out STD_LOGIC; - Eth_UC_RX_Meta_SrcMACAddress_nxt : out STD_LOGIC; + Eth_UC_RX_SOF : in std_logic; + Eth_UC_RX_EOF : in std_logic; + Eth_UC_RX_Ack : out std_logic; + Eth_UC_RX_Meta_rst : out std_logic; + Eth_UC_RX_Meta_SrcMACAddress_nxt : out std_logic; Eth_UC_RX_Meta_SrcMACAddress_Data : in T_SLV_8; - Eth_UC_RX_Meta_DestMACAddress_nxt : out STD_LOGIC; + Eth_UC_RX_Meta_DestMACAddress_nxt : out std_logic; Eth_UC_RX_Meta_DestMACAddress_Data : in T_SLV_8; - Eth_BC_RX_Valid : in STD_LOGIC; + Eth_BC_RX_Valid : in std_logic; Eth_BC_RX_Data : in T_SLV_8; - Eth_BC_RX_SOF : in STD_LOGIC; - Eth_BC_RX_EOF : in STD_LOGIC; - Eth_BC_RX_Ack : out STD_LOGIC; - Eth_BC_RX_Meta_rst : out STD_LOGIC; - Eth_BC_RX_Meta_SrcMACAddress_nxt : out STD_LOGIC; + Eth_BC_RX_SOF : in std_logic; + Eth_BC_RX_EOF : in std_logic; + Eth_BC_RX_Ack : out std_logic; + Eth_BC_RX_Meta_rst : out std_logic; + Eth_BC_RX_Meta_SrcMACAddress_nxt : out std_logic; Eth_BC_RX_Meta_SrcMACAddress_Data : in T_SLV_8; - Eth_BC_RX_Meta_DestMACAddress_nxt : out STD_LOGIC; + Eth_BC_RX_Meta_DestMACAddress_nxt : out std_logic; Eth_BC_RX_Meta_DestMACAddress_Data : in T_SLV_8 ); end entity; @@ -105,10 +104,10 @@ architecture rtl of arp_Wrapper is signal ARPCache_Command : T_NET_ARP_ARPCACHE_COMMAND; signal IPPool_Command : T_NET_ARP_IPPOOL_COMMAND; - signal IPPool_Announce_l : STD_LOGIC := '0'; - signal IPPool_Announced_i : STD_LOGIC; + signal IPPool_Announce_l : std_logic := '0'; + signal IPPool_Announced_i : std_logic; - type T_FSMPOOL_STATE IS ( + type T_FSMPOOL_STATE is ( ST_IDLE, ST_IPPOOL_WAIT, ST_SEND_RESPONSE, @@ -119,22 +118,22 @@ architecture rtl of arp_Wrapper is signal FSMPool_State : T_FSMPOOL_STATE := ST_IDLE; signal FSMPool_NextState : T_FSMPOOL_STATE; - signal FSMPool_MACSeq1_SenderMACAddress_rst : STD_LOGIC; - signal FSMPool_MACSeq1_SenderMACAddress_nxt : STD_LOGIC; + signal FSMPool_MACSeq1_SenderMACAddress_rst : std_logic; + signal FSMPool_MACSeq1_SenderMACAddress_nxt : std_logic; - signal FSMPool_BCRcv_Clear : STD_LOGIC; - signal FSMPool_BCRcv_Address_rst : STD_LOGIC; - signal FSMPool_BCRcv_SenderMACAddress_nxt : STD_LOGIC; - signal FSMPool_BCRcv_SenderIPv4Address_nxt : STD_LOGIC; - signal FSMPool_BCRcv_TargetIPv4Address_nxt : STD_LOGIC; + signal FSMPool_BCRcv_Clear : std_logic; + signal FSMPool_BCRcv_Address_rst : std_logic; + signal FSMPool_BCRcv_SenderMACAddress_nxt : std_logic; + signal FSMPool_BCRcv_SenderIPv4Address_nxt : std_logic; + signal FSMPool_BCRcv_TargetIPv4Address_nxt : std_logic; signal FSMPool_Command : T_NET_ARP_IPPOOL_COMMAND; signal FSMPool_NewIPv4Address_Data : T_NET_IPV4_ADDRESS; signal FSMPool_NewMACAddress_Data : T_NET_MAC_ADDRESS; - signal FSMPool_IPPool_Lookup : STD_LOGIC; + signal FSMPool_IPPool_Lookup : std_logic; signal FSMPool_IPPool_IPv4Address_Data : T_SLV_8; - signal FSMPool_UCRsp_SendResponse : STD_LOGIC; + signal FSMPool_UCRsp_SendResponse : std_logic; signal FSMPool_UCRsp_SenderMACAddress_Data : T_SLV_8; signal FSMPool_UCRsp_SenderIPv4Address_Data : T_SLV_8; signal FSMPool_UCRsp_TargetMACAddress_Data : T_SLV_8; @@ -144,39 +143,39 @@ architecture rtl of arp_Wrapper is signal MACSeq1_SenderMACAddress_Data : T_SLV_8; -- broadcast receiver - signal BCRcv_Error : STD_LOGIC; + signal BCRcv_Error : std_logic; - signal BCRcv_RequestReceived : STD_LOGIC; + signal BCRcv_RequestReceived : std_logic; signal BCRcv_SenderMACAddress_Data : T_SLV_8; signal BCRcv_SenderIPv4Address_Data : T_SLV_8; signal BCRcv_TargetIPv4Address_Data : T_SLV_8; -- ippool - signal IPPool_Insert : STD_LOGIC; - signal IPPool_UCRsp_SendResponse : STD_LOGIC; - signal IPPool_IPv4Address_rst : STD_LOGIC; - signal IPPool_IPv4Address_nxt : STD_LOGIC; + signal IPPool_Insert : std_logic; + signal IPPool_UCRsp_SendResponse : std_logic; + signal IPPool_IPv4Address_rst : std_logic; + signal IPPool_IPv4Address_nxt : std_logic; signal IPPool_PoolResult : T_CACHE_RESULT; -- unicast responder - signal UCRsp_Complete : STD_LOGIC; + signal UCRsp_Complete : std_logic; - signal UCRsp_Address_rst : STD_LOGIC; - signal UCRsp_SenderMACAddress_nxt : STD_LOGIC; - signal UCRsp_SenderIPv4Address_nxt : STD_LOGIC; - signal UCRsp_TargetMACAddress_nxt : STD_LOGIC; - signal UCRsp_TargetIPv4Address_nxt : STD_LOGIC; + signal UCRsp_Address_rst : std_logic; + signal UCRsp_SenderMACAddress_nxt : std_logic; + signal UCRsp_SenderIPv4Address_nxt : std_logic; + signal UCRsp_TargetMACAddress_nxt : std_logic; + signal UCRsp_TargetIPv4Address_nxt : std_logic; - signal UCRsp_TX_Valid : STD_LOGIC; + signal UCRsp_TX_Valid : std_logic; signal UCRsp_TX_Data : T_SLV_8; - signal UCRsp_TX_SOF : STD_LOGIC; - signal UCRsp_TX_EOF : STD_LOGIC; - signal UCRsp_TX_Ack : STD_LOGIC; - signal UCRsp_TX_Meta_DestMACAddress_rst : STD_LOGIC; - signal UCRsp_TX_Meta_DestMACAddress_nxt : STD_LOGIC; + signal UCRsp_TX_SOF : std_logic; + signal UCRsp_TX_EOF : std_logic; + signal UCRsp_TX_Ack : std_logic; + signal UCRsp_TX_Meta_DestMACAddress_rst : std_logic; + signal UCRsp_TX_Meta_DestMACAddress_nxt : std_logic; signal UCRsp_TX_Meta_DestMACAddress_Data : T_SLV_8; - type T_FSMCACHE_STATE IS ( + type T_FSMCACHE_STATE is ( ST_IDLE, ST_CACHE, ST_CACHE_WAIT, ST_READ_CACHE, ST_SEND_BROADCAST_REQUEST, ST_SEND_BROADCAST_REQUEST_WAIT, ST_WAIT_FOR_UNICAST_RESPONSE, @@ -191,24 +190,24 @@ architecture rtl of arp_Wrapper is signal FSMCache_ARPCache_NewIPv4Address_Data : T_SLV_8; signal FSMCache_ARPCache_NewMACAddress_Data : T_SLV_8; - signal FSMCache_MACSeq2_SenderMACAddress_rst : STD_LOGIC; - signal FSMCache_MACSeq2_SenderMACAddress_nxt : STD_LOGIC; - signal FSMCache_IPSeq2_SenderIPv4Address_rst : STD_LOGIC; - signal FSMCache_IPSeq2_SenderIPv4Address_nxt : STD_LOGIC; + signal FSMCache_MACSeq2_SenderMACAddress_rst : std_logic; + signal FSMCache_MACSeq2_SenderMACAddress_nxt : std_logic; + signal FSMCache_IPSeq2_SenderIPv4Address_rst : std_logic; + signal FSMCache_IPSeq2_SenderIPv4Address_nxt : std_logic; - signal FSMCache_UCRcv_Clear : STD_LOGIC; - signal FSMCache_UCRcv_Address_rst : STD_LOGIC; - signal FSMCache_UCRcv_SenderMACAddress_nxt : STD_LOGIC; - signal FSMCache_UCRcv_SenderIPv4Address_nxt : STD_LOGIC; - signal FSMCache_UCRcv_TargetMACAddress_nxt : STD_LOGIC; - signal FSMCache_UCRcv_TargetIPv4Address_nxt : STD_LOGIC; + signal FSMCache_UCRcv_Clear : std_logic; + signal FSMCache_UCRcv_Address_rst : std_logic; + signal FSMCache_UCRcv_SenderMACAddress_nxt : std_logic; + signal FSMCache_UCRcv_SenderIPv4Address_nxt : std_logic; + signal FSMCache_UCRcv_TargetMACAddress_nxt : std_logic; + signal FSMCache_UCRcv_TargetIPv4Address_nxt : std_logic; - signal FSMCache_ARPCache_Lookup : STD_LOGIC; + signal FSMCache_ARPCache_Lookup : std_logic; signal FSMCache_ARPCache_IPv4Address_Data : T_SLV_8; - signal FSMCache_ARPCache_MACAddress_rst : STD_LOGIC; - signal FSMCache_ARPCache_MACAddress_nxt : STD_LOGIC; + signal FSMCache_ARPCache_MACAddress_rst : std_logic; + signal FSMCache_ARPCache_MACAddress_nxt : std_logic; - signal FSMCache_BCReq_SendRequest : STD_LOGIC; + signal FSMCache_BCReq_SendRequest : std_logic; signal FSMCache_BCReq_SenderMACAddress_Data : T_SLV_8; signal FSMCache_BCReq_SenderIPv4Address_Data : T_SLV_8; signal FSMCache_BCReq_TargetMACAddress_Data : T_SLV_8; @@ -219,16 +218,16 @@ architecture rtl of arp_Wrapper is signal IPSeq2_SenderIPv4Address_Data : T_SLV_8; -- ARP request timeout counter - constant ARPREQ_TIMEOUTCOUNTER_MAX : POSITIVE := TimingToCycles(APR_REQUEST_TIMEOUT, CLOCK_FREQ); - constant ARPREQ_TIMEOUTCOUNTER_BITS : POSITIVE := log2ceilnz(ARPREQ_TIMEOUTCOUNTER_MAX); + constant ARPREQ_TIMEOUTCOUNTER_MAX : positive := TimingToCycles(APR_REQUEST_TIMEOUT, CLOCK_FREQ); + constant ARPREQ_TIMEOUTCOUNTER_BITS : positive := log2ceilnz(ARPREQ_TIMEOUTCOUNTER_MAX); - signal FSMCache_ARPReq_TimeoutCounter_rst : STD_LOGIC; - signal ARPReq_TimeoutCounter_s : SIGNED(ARPREQ_TIMEOUTCOUNTER_BITS downto 0) := to_signed(ARPREQ_TIMEOUTCOUNTER_MAX, ARPREQ_TIMEOUTCOUNTER_BITS + 1); - signal ARPReq_Timeout : STD_LOGIC; + signal FSMCache_ARPReq_TimeoutCounter_rst : std_logic; + signal ARPReq_TimeoutCounter_s : signed(ARPREQ_TIMEOUTCOUNTER_BITS downto 0) := to_signed(ARPREQ_TIMEOUTCOUNTER_MAX, ARPREQ_TIMEOUTCOUNTER_BITS + 1); + signal ARPReq_Timeout : std_logic; -- unicast receiver - signal UCRcv_Error : STD_LOGIC; - signal UCRcv_ResponseReceived : STD_LOGIC; + signal UCRcv_Error : std_logic; + signal UCRcv_ResponseReceived : std_logic; signal UCRcv_SenderMACAddress_Data : T_SLV_8; signal UCRcv_SenderIPv4Address_Data : T_SLV_8; signal UCRcv_TargetMACAddress_Data : T_SLV_8; @@ -236,42 +235,42 @@ architecture rtl of arp_Wrapper is -- arp cache signal ARPCache_Status : T_NET_ARP_ARPCACHE_STATUS; - signal ARPCache_NewMACAddress_nxt : STD_LOGIC; - signal ARPCache_NewIPv4Address_nxt : STD_LOGIC; + signal ARPCache_NewMACAddress_nxt : std_logic; + signal ARPCache_NewIPv4Address_nxt : std_logic; signal ARPCache_CacheResult : T_CACHE_RESULT; - signal ARPCache_IPv4Address_rst : STD_LOGIC; - signal ARPCache_IPv4Address_nxt : STD_LOGIC; + signal ARPCache_IPv4Address_rst : std_logic; + signal ARPCache_IPv4Address_nxt : std_logic; signal ARPCache_MACAddress_Data : T_SLV_8; -- broadcast requester - signal BCReq_Complete : STD_LOGIC; + signal BCReq_Complete : std_logic; - signal BCReq_Address_rst : STD_LOGIC; - signal BCReq_SenderMACAddress_nxt : STD_LOGIC; - signal BCReq_SenderIPv4Address_nxt : STD_LOGIC; - signal BCReq_TargetMACAddress_nxt : STD_LOGIC; - signal BCReq_TargetIPv4Address_nxt : STD_LOGIC; + signal BCReq_Address_rst : std_logic; + signal BCReq_SenderMACAddress_nxt : std_logic; + signal BCReq_SenderIPv4Address_nxt : std_logic; + signal BCReq_TargetMACAddress_nxt : std_logic; + signal BCReq_TargetIPv4Address_nxt : std_logic; - signal BCReq_TX_Valid : STD_LOGIC; + signal BCReq_TX_Valid : std_logic; signal BCReq_TX_Data : T_SLV_8; - signal BCReq_TX_SOF : STD_LOGIC; - signal BCReq_TX_EOF : STD_LOGIC; - signal BCReq_TX_Ack : STD_LOGIC; - signal BCReq_TX_Meta_DestMACAddress_rst : STD_LOGIC; - signal BCReq_TX_Meta_DestMACAddress_nxt : STD_LOGIC; + signal BCReq_TX_SOF : std_logic; + signal BCReq_TX_EOF : std_logic; + signal BCReq_TX_Ack : std_logic; + signal BCReq_TX_Meta_DestMACAddress_rst : std_logic; + signal BCReq_TX_Meta_DestMACAddress_nxt : std_logic; signal BCReq_TX_Meta_DestMACAddress_Data : T_SLV_8; begin -- latched inputs (high-active) - IPPool_Announce_l <= ((IPPool_Announce OR IPPool_Announce_l) and NOT IPPool_Announced_i) when rising_edge(Clock); + IPPool_Announce_l <= ((IPPool_Announce or IPPool_Announce_l) and not IPPool_Announced_i) when rising_edge(Clock); IPPool_Announced <= IPPool_Announced_i; -- FIXME: assign correct value IPPool_Insert <= '0'; --- ============================================================================================================================================================ +-- ============================================================================= -- Responder Path --- ============================================================================================================================================================ +-- ============================================================================= MACSeq1 : entity PoC.misc_Sequencer generic map ( INPUT_BITS => 48, @@ -336,7 +335,7 @@ begin FSMPool_UCRsp_TargetMACAddress_Data <= BCRcv_SenderMACAddress_Data; FSMPool_UCRsp_TargetIPv4Address_Data <= BCRcv_SenderIPv4Address_Data; - case FSMPool_State IS + case FSMPool_State is when ST_IDLE => if (BCRcv_RequestReceived = '1') then FSMPool_IPPool_Lookup <= '1'; @@ -473,9 +472,9 @@ begin TX_Meta_DestMACAddress_nxt => UCRsp_TX_Meta_DestMACAddress_nxt, TX_Meta_DestMACAddress_Data => UCRsp_TX_Meta_DestMACAddress_Data ); --- ============================================================================================================================================================ +-- ============================================================================= -- ARPCache Path --- ============================================================================================================================================================ +-- ============================================================================= MACSeq2 : entity PoC.misc_Sequencer generic map ( INPUT_BITS => 48, @@ -565,7 +564,7 @@ begin FSMCache_UCRcv_TargetMACAddress_nxt <= '0'; -- default assignment for unsed metadata TargetMACAddress FSMCache_UCRcv_TargetIPv4Address_nxt <= '0'; -- default assignment for unsed metadata TargetIPv4Address - case FSMCache_State IS + case FSMCache_State is when ST_IDLE => IPCache_IPv4Address_rst <= '1'; @@ -777,30 +776,30 @@ begin ); blkStmMux : block - constant LLMUX_PORT_BCREQ : NATURAL := 0; - constant LLMUX_PORT_UCRSP : NATURAL := 1; - constant LLMUX_PORTS : POSITIVE := 2; + constant LLMUX_PORT_BCREQ : natural := 0; + constant LLMUX_PORT_UCRSP : natural := 1; + constant LLMUX_PORTS : positive := 2; - constant META_RST_BIT : NATURAL := 0; - constant META_DEST_NXT_BIT : NATURAL := 1; + constant META_RST_BIT : natural := 0; + constant META_DEST_NXT_BIT : natural := 1; - constant META_BITS : POSITIVE := 8; - constant META_REV_BITS : POSITIVE := 2; + constant META_BITS : positive := 8; + constant META_REV_BITS : positive := 2; signal Temp_Meta : T_SLVV_48(LLMUX_PORTS - 1 downto 0); signal Temp_Meta2 : T_SLV_48; - signal StmMux_In_Valid : STD_LOGIC_VECTOR(LLMUX_PORTS - 1 downto 0); + signal StmMux_In_Valid : std_logic_vector(LLMUX_PORTS - 1 downto 0); signal StmMux_In_Data : T_SLM(LLMUX_PORTS - 1 downto 0, T_SLV_8'range) := (others => (others => 'Z')); -- necessary default assignment 'Z' to get correct simulation results (iSIM, vSIM, ghdl/gtkwave) signal StmMux_In_Meta : T_SLM(LLMUX_PORTS - 1 downto 0, META_BITS - 1 downto 0) := (others => (others => 'Z')); -- necessary default assignment 'Z' to get correct simulation results (iSIM, vSIM, ghdl/gtkwave) signal StmMux_In_Meta_rev : T_SLM(LLMUX_PORTS - 1 downto 0, META_REV_BITS - 1 downto 0) := (others => (others => 'Z')); -- necessary default assignment 'Z' to get correct simulation results (iSIM, vSIM, ghdl/gtkwave) - signal StmMux_In_SOF : STD_LOGIC_VECTOR(LLMUX_PORTS - 1 downto 0); - signal StmMux_In_EOF : STD_LOGIC_VECTOR(LLMUX_PORTS - 1 downto 0); - signal StmMux_In_Ack : STD_LOGIC_VECTOR(LLMUX_PORTS - 1 downto 0); + signal StmMux_In_SOF : std_logic_vector(LLMUX_PORTS - 1 downto 0); + signal StmMux_In_EOF : std_logic_vector(LLMUX_PORTS - 1 downto 0); + signal StmMux_In_Ack : std_logic_vector(LLMUX_PORTS - 1 downto 0); - signal StmMux_Out_Meta : STD_LOGIC_VECTOR(META_BITS - 1 downto 0); - signal StmMux_Out_Meta_rev : STD_LOGIC_VECTOR(META_REV_BITS - 1 downto 0); + signal StmMux_Out_Meta : std_logic_vector(META_BITS - 1 downto 0); + signal StmMux_Out_Meta_rev : std_logic_vector(META_REV_BITS - 1 downto 0); begin diff --git a/src/net/icmpv4/icmpv4_RX.vhdl b/src/net/icmpv4/icmpv4_RX.vhdl index 29056b33..d21a2cef 100644 --- a/src/net/icmpv4/icmpv4_RX.vhdl +++ b/src/net/icmpv4/icmpv4_RX.vhdl @@ -1,18 +1,17 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: TODO +-- Entity: TODO -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -27,7 +26,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -42,55 +41,55 @@ use PoC.net.all; entity icmpv4_RX is generic ( - DEBUG : BOOLEAN := FALSE + DEBUG : boolean := FALSE ); port ( - Clock : in STD_LOGIC; -- - Reset : in STD_LOGIC; -- + Clock : in std_logic; -- + Reset : in std_logic; -- -- CSE interface Command : in T_NET_ICMPV4_RX_COMMAND; Status : out T_NET_ICMPV4_RX_STATUS; Error : out T_NET_ICMPV4_RX_ERROR; -- IN port - In_Valid : in STD_LOGIC; + In_Valid : in std_logic; In_Data : in T_SLV_8; - In_SOF : in STD_LOGIC; - In_EOF : in STD_LOGIC; - In_Ack : out STD_LOGIC; - In_Meta_rst : out STD_LOGIC; - In_Meta_SrcMACAddress_nxt : out STD_LOGIC; + In_SOF : in std_logic; + In_EOF : in std_logic; + In_Ack : out std_logic; + In_Meta_rst : out std_logic; + In_Meta_SrcMACAddress_nxt : out std_logic; In_Meta_SrcMACAddress_Data : in T_SLV_8; - In_Meta_DestMACAddress_nxt : out STD_LOGIC; + In_Meta_DestMACAddress_nxt : out std_logic; In_Meta_DestMACAddress_Data : in T_SLV_8; - In_Meta_SrcIPv4Address_nxt : out STD_LOGIC; + In_Meta_SrcIPv4Address_nxt : out std_logic; In_Meta_SrcIPv4Address_Data : in T_SLV_8; - In_Meta_DestIPv4Address_nxt : out STD_LOGIC; + In_Meta_DestIPv4Address_nxt : out std_logic; In_Meta_DestIPv4Address_Data : in T_SLV_8; In_Meta_Length : in T_SLV_16; -- OUT Port - Out_Meta_rst : in STD_LOGIC; - Out_Meta_SrcMACAddress_nxt : in STD_LOGIC; + Out_Meta_rst : in std_logic; + Out_Meta_SrcMACAddress_nxt : in std_logic; Out_Meta_SrcMACAddress_Data : out T_SLV_8; - Out_Meta_DestMACAddress_nxt : in STD_LOGIC; + Out_Meta_DestMACAddress_nxt : in std_logic; Out_Meta_DestMACAddress_Data : out T_SLV_8; - Out_Meta_SrcIPv4Address_nxt : in STD_LOGIC; + Out_Meta_SrcIPv4Address_nxt : in std_logic; Out_Meta_SrcIPv4Address_Data : out T_SLV_8; - Out_Meta_DestIPv4Address_nxt : in STD_LOGIC; + Out_Meta_DestIPv4Address_nxt : in std_logic; Out_Meta_DestIPv4Address_Data : out T_SLV_8; Out_Meta_Length : out T_SLV_16; Out_Meta_Type : out T_SLV_8; Out_Meta_Code : out T_SLV_8; Out_Meta_Identification : out T_SLV_16; Out_Meta_SequenceNumber : out T_SLV_16; - Out_Meta_Payload_nxt : in STD_LOGIC; - Out_Meta_Payload_last : out STD_LOGIC; + Out_Meta_Payload_nxt : in std_logic; + Out_Meta_Payload_last : out std_logic; Out_Meta_Payload_Data : out T_SLV_8 ); end entity; architecture rtl of icmpv4_RX is - attribute FSM_ENCODING : STRING; + attribute FSM_ENCODING : string; type T_STATE is ( ST_IDLE, @@ -111,17 +110,17 @@ architecture rtl of icmpv4_RX is signal NextState : T_STATE; attribute FSM_ENCODING of State : signal is ite(DEBUG, "gray", ite((VENDOR = VENDOR_XILINX), "auto", "default")); - signal Register_rst : STD_LOGIC; + signal Register_rst : std_logic; -- UDP header fields - signal Type_en : STD_LOGIC; - signal Code_en : STD_LOGIC; - signal Checksum_en0 : STD_LOGIC; - signal Checksum_en1 : STD_LOGIC; - signal Identification_en0 : STD_LOGIC; - signal Identification_en1 : STD_LOGIC; - signal SequenceNumber_en0 : STD_LOGIC; - signal SequenceNumber_en1 : STD_LOGIC; + signal Type_en : std_logic; + signal Code_en : std_logic; + signal Checksum_en0 : std_logic; + signal Checksum_en1 : std_logic; + signal Identification_en0 : std_logic; + signal Identification_en1 : std_logic; + signal SequenceNumber_en0 : std_logic; + signal SequenceNumber_en1 : std_logic; signal Type_d : T_SLV_8 := (others => '0'); signal Code_d : T_SLV_8 := (others => '0'); @@ -129,14 +128,14 @@ architecture rtl of icmpv4_RX is signal Identification_d : T_SLV_16 := (others => '0'); signal SequenceNumber_d : T_SLV_16 := (others => '0'); - signal MetaFIFO_put : STD_LOGIC; - signal MetaFIFO_DataIn : STD_LOGIC_VECTOR(8 downto 0); - signal MetaFIFO_Full : STD_LOGIC; - signal MetaFIFO_Commit : STD_LOGIC; - signal MetaFIFO_Rollback : STD_LOGIC; + signal MetaFIFO_put : std_logic; + signal MetaFIFO_DataIn : std_logic_vector(8 downto 0); + signal MetaFIFO_Full : std_logic; + signal MetaFIFO_Commit : std_logic; + signal MetaFIFO_Rollback : std_logic; -- signal MetaFIFO_Valid : STD_LOGIC; - signal MetaFIFO_DataOut : STD_LOGIC_VECTOR(8 downto 0); - signal MetaFIFO_got : STD_LOGIC; + signal MetaFIFO_DataOut : std_logic_vector(8 downto 0); + signal MetaFIFO_got : std_logic; begin @@ -359,7 +358,7 @@ begin process(Clock) begin if rising_edge(Clock) then - if ((Reset OR Register_rst) = '1') then + if ((Reset or Register_rst) = '1') then Type_d <= (others => '0'); Code_d <= (others => '0'); Checksum_d <= (others => '0'); diff --git a/src/net/icmpv4/icmpv4_TX.vhdl b/src/net/icmpv4/icmpv4_TX.vhdl index 4f8b3c33..968eb7f0 100644 --- a/src/net/icmpv4/icmpv4_TX.vhdl +++ b/src/net/icmpv4/icmpv4_TX.vhdl @@ -1,18 +1,17 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: TODO +-- Entity: TODO -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -27,7 +26,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -42,45 +41,45 @@ use PoC.net.all; entity icmpv4_TX is generic ( - DEBUG : BOOLEAN := FALSE; + DEBUG : boolean := FALSE; SOURCE_IPV4ADDRESS : T_NET_IPV4_ADDRESS := C_NET_IPV4_ADDRESS_EMPTY ); port ( - Clock : in STD_LOGIC; -- - Reset : in STD_LOGIC; -- + Clock : in std_logic; -- + Reset : in std_logic; -- -- CSE interface Command : in T_NET_ICMPV4_TX_COMMAND; Status : out T_NET_ICMPV4_TX_STATUS; Error : out T_NET_ICMPV4_TX_ERROR; -- OUT port - Out_Valid : out STD_LOGIC; + Out_Valid : out std_logic; Out_Data : out T_SLV_8; - Out_SOF : out STD_LOGIC; - Out_EOF : out STD_LOGIC; - Out_Ack : in STD_LOGIC; - Out_Meta_rst : in STD_LOGIC; - Out_Meta_SrcIPv4Address_nxt : in STD_LOGIC; + Out_SOF : out std_logic; + Out_EOF : out std_logic; + Out_Ack : in std_logic; + Out_Meta_rst : in std_logic; + Out_Meta_SrcIPv4Address_nxt : in std_logic; Out_Meta_SrcIPv4Address_Data : out T_SLV_8; - Out_Meta_DestIPv4Address_nxt : in STD_LOGIC; + Out_Meta_DestIPv4Address_nxt : in std_logic; Out_Meta_DestIPv4Address_Data : out T_SLV_8; Out_Meta_Length : out T_SLV_16; -- IN port - In_Meta_rst : out STD_LOGIC; - In_Meta_IPv4Address_nxt : out STD_LOGIC; + In_Meta_rst : out std_logic; + In_Meta_IPv4Address_nxt : out std_logic; In_Meta_IPv4Address_Data : in T_SLV_8; In_Meta_Type : in T_SLV_8; In_Meta_Code : in T_SLV_8; In_Meta_Identification : in T_SLV_16; In_Meta_SequenceNumber : in T_SLV_16; - In_Meta_Payload_nxt : out STD_LOGIC; - In_Meta_Payload_last : in STD_LOGIC; + In_Meta_Payload_nxt : out std_logic; + In_Meta_Payload_last : in std_logic; In_Meta_Payload_Data : in T_SLV_8 ); end entity; architecture rtl of icmpv4_TX is - attribute FSM_ENCODING : STRING; + attribute FSM_ENCODING : string; type T_STATE is ( ST_IDLE, @@ -103,12 +102,12 @@ architecture rtl of icmpv4_TX is signal Checksum : T_SLV_16; - constant PAYLOAD : STD_LOGIC_VECTOR(255 downto 0) := x"00010203" & x"04050607" & x"08090A0B" & x"0C0D0E0F" & x"10111213" & x"14151617" & x"18191A1B" & x"1C1D1E1F"; + constant PAYLOAD : std_logic_vector(255 downto 0) := x"00010203" & x"04050607" & x"08090A0B" & x"0C0D0E0F" & x"10111213" & x"14151617" & x"18191A1B" & x"1C1D1E1F"; constant PAYLOAD_ROM : T_SLVV_8 := to_slvv_8(PAYLOAD); - signal PayloadROM_Reader_nxt : STD_LOGIC; - signal PayloadROM_Reader_ov : STD_LOGIC; - signal PayloadROM_Reader_us : UNSIGNED(log2ceilnz(PAYLOAD_ROM'length) - 1 downto 0) := (others => '0'); + signal PayloadROM_Reader_nxt : std_logic; + signal PayloadROM_Reader_ov : std_logic; + signal PayloadROM_Reader_us : unsigned(log2ceilnz(PAYLOAD_ROM'length) - 1 downto 0) := (others => '0'); signal PayloadROM_Data : T_SLV_8; begin @@ -141,7 +140,7 @@ begin case State is when ST_IDLE => - case Command IS + case Command is when NET_ICMPV4_TX_CMD_NONE => null; diff --git a/src/net/icmpv4/icmpv4_Wrapper.vhdl b/src/net/icmpv4/icmpv4_Wrapper.vhdl index ea891d49..c830fd19 100644 --- a/src/net/icmpv4/icmpv4_Wrapper.vhdl +++ b/src/net/icmpv4/icmpv4_Wrapper.vhdl @@ -1,18 +1,17 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: TODO +-- Entity: TODO -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -27,7 +26,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -42,47 +41,47 @@ use PoC.net.all; entity icmpv4_Wrapper is generic ( - DEBUG : BOOLEAN := FALSE; + DEBUG : boolean := FALSE; SOURCE_IPV4ADDRESS : T_NET_IPV4_ADDRESS := C_NET_IPV4_ADDRESS_EMPTY ); port ( - Clock : in STD_LOGIC; - Reset : in STD_LOGIC; + Clock : in std_logic; + Reset : in std_logic; -- CSE interface Command : in T_NET_ICMPV4_COMMAND; Status : out T_NET_ICMPV4_STATUS; Error : out T_NET_ICMPV4_ERROR; -- Echo-Request destination address - IPv4Address_rst : out STD_LOGIC; - IPv4Address_nxt : out STD_LOGIC; + IPv4Address_rst : out std_logic; + IPv4Address_nxt : out std_logic; IPv4Address_Data : in T_SLV_8; -- to IPv4 layer - IP_TX_Valid : out STD_LOGIC; + IP_TX_Valid : out std_logic; IP_TX_Data : out T_SLV_8; - IP_TX_SOF : out STD_LOGIC; - IP_TX_EOF : out STD_LOGIC; - IP_TX_Ack : in STD_LOGIC; - IP_TX_Meta_rst : in STD_LOGIC; - IP_TX_Meta_SrcIPv4Address_nxt : in STD_LOGIC; + IP_TX_SOF : out std_logic; + IP_TX_EOF : out std_logic; + IP_TX_Ack : in std_logic; + IP_TX_Meta_rst : in std_logic; + IP_TX_Meta_SrcIPv4Address_nxt : in std_logic; IP_TX_Meta_SrcIPv4Address_Data : out T_SLV_8; - IP_TX_Meta_DestIPv4Address_nxt : in STD_LOGIC; + IP_TX_Meta_DestIPv4Address_nxt : in std_logic; IP_TX_Meta_DestIPv4Address_Data : out T_SLV_8; IP_TX_Meta_Length : out T_SLV_16; -- from IPv4 layer - IP_RX_Valid : in STD_LOGIC; + IP_RX_Valid : in std_logic; IP_RX_Data : in T_SLV_8; - IP_RX_SOF : in STD_LOGIC; - IP_RX_EOF : in STD_LOGIC; - IP_RX_Ack : out STD_LOGIC; - IP_RX_Meta_rst : out STD_LOGIC; - IP_RX_Meta_SrcMACAddress_nxt : out STD_LOGIC; + IP_RX_SOF : in std_logic; + IP_RX_EOF : in std_logic; + IP_RX_Ack : out std_logic; + IP_RX_Meta_rst : out std_logic; + IP_RX_Meta_SrcMACAddress_nxt : out std_logic; IP_RX_Meta_SrcMACAddress_Data : in T_SLV_8; - IP_RX_Meta_DestMACAddress_nxt : out STD_LOGIC; + IP_RX_Meta_DestMACAddress_nxt : out std_logic; IP_RX_Meta_DestMACAddress_Data : in T_SLV_8; -- IP_RX_Meta_EthType : in T_SLV_16; - IP_RX_Meta_SrcIPv4Address_nxt : out STD_LOGIC; + IP_RX_Meta_SrcIPv4Address_nxt : out std_logic; IP_RX_Meta_SrcIPv4Address_Data : in T_SLV_8; - IP_RX_Meta_DestIPv4Address_nxt : out STD_LOGIC; + IP_RX_Meta_DestIPv4Address_nxt : out std_logic; IP_RX_Meta_DestIPv4Address_Data : in T_SLV_8; -- IP_RX_Meta_TrafficClass : in T_SLV_8; -- IP_RX_Meta_FlowLabel : in T_SLV_24; @@ -93,7 +92,7 @@ end entity; architecture rtl of icmpv4_Wrapper is - attribute FSM_ENCODING : STRING; + attribute FSM_ENCODING : string; type T_STATE is ( ST_IDLE, @@ -119,40 +118,40 @@ architecture rtl of icmpv4_Wrapper is signal RX_Status : T_NET_ICMPV4_RX_STATUS; signal RX_Error : T_NET_ICMPV4_RX_ERROR; - signal TX_Meta_rst : STD_LOGIC; - signal TX_Meta_IPv4Address_nxt : STD_LOGIC; + signal TX_Meta_rst : std_logic; + signal TX_Meta_IPv4Address_nxt : std_logic; signal FSM_TX_Meta_IPv4Address_Data : T_SLV_8; signal FSM_TX_Meta_Type : T_SLV_8; signal FSM_TX_Meta_Code : T_SLV_8; signal FSM_TX_Meta_Identification : T_SLV_16; signal FSM_TX_Meta_SequenceNumber : T_SLV_16; - signal TX_Meta_Payload_nxt : STD_LOGIC; - signal FSM_TX_Meta_Payload_last : STD_LOGIC; + signal TX_Meta_Payload_nxt : std_logic; + signal FSM_TX_Meta_Payload_last : std_logic; signal FSM_TX_Meta_Payload_Data : T_SLV_8; - signal RX_Meta_rst : STD_LOGIC; - signal FSM_RX_Meta_rst : STD_LOGIC; - signal FSM_RX_Meta_SrcMACAddress_nxt : STD_LOGIC; + signal RX_Meta_rst : std_logic; + signal FSM_RX_Meta_rst : std_logic; + signal FSM_RX_Meta_SrcMACAddress_nxt : std_logic; signal RX_Meta_SrcMACAddress_Data : T_SLV_8; - signal FSM_RX_Meta_DestMACAddress_nxt : STD_LOGIC; + signal FSM_RX_Meta_DestMACAddress_nxt : std_logic; signal RX_Meta_DestMACAddress_Data : T_SLV_8; - signal FSM_RX_Meta_SrcIPv4Address_nxt : STD_LOGIC; + signal FSM_RX_Meta_SrcIPv4Address_nxt : std_logic; signal RX_Meta_SrcIPv4Address_Data : T_SLV_8; - signal FSM_RX_Meta_DestIPv4Address_nxt : STD_LOGIC; + signal FSM_RX_Meta_DestIPv4Address_nxt : std_logic; signal RX_Meta_DestIPv4Address_Data : T_SLV_8; signal RX_Meta_Length : T_SLV_16; signal RX_Meta_Type : T_SLV_8; signal RX_Meta_Code : T_SLV_8; signal RX_Meta_Identification : T_SLV_16; signal RX_Meta_SequenceNumber : T_SLV_16; - signal FSM_RX_Meta_Payload_nxt : STD_LOGIC; - signal RX_Meta_Payload_last : STD_LOGIC; + signal FSM_RX_Meta_Payload_nxt : std_logic; + signal RX_Meta_Payload_last : std_logic; signal RX_Meta_Payload_Data : T_SLV_8; begin --- ============================================================================================================================================================ +-- ============================================================================= -- ICMPv4 FSM --- ============================================================================================================================================================ +-- ============================================================================= process(Clock) begin if rising_edge(Clock) then @@ -191,15 +190,15 @@ begin FSM_RX_Meta_DestIPv4Address_nxt <= '0'; FSM_RX_Meta_Payload_nxt <= '0'; - case FSM_State IS + case FSM_State is when ST_IDLE => - case Command IS + case Command is when NET_ICMPV4_CMD_NONE => null; when NET_ICMPV4_CMD_ECHO_REQUEST => FSM_NextState <= ST_SEND_ECHO_REQUEST; when others => FSM_NextState <= ST_ERROR; end case; - case RX_Status IS + case RX_Status is when NET_ICMPV4_RX_STATUS_IDLE => null; when NET_ICMPV4_RX_STATUS_RECEIVED_ECHO_REQUEST => FSM_NextState <= ST_SEND_ECHO_REPLY; when others => FSM_NextState <= ST_ERROR; @@ -230,7 +229,7 @@ begin FSM_TX_Meta_Identification <= x"C0FE"; FSM_TX_Meta_SequenceNumber <= x"BEAF"; - case TX_Status IS + case TX_Status is when NET_ICMPV4_TX_STATUS_IDLE => null; when NET_ICMPV4_TX_STATUS_SENDING => null; when NET_ICMPV4_TX_STATUS_SEND_COMPLETE => FSM_NextState <= ST_WAIT_FOR_ECHO_REPLY; @@ -239,7 +238,7 @@ begin end case; when ST_WAIT_FOR_ECHO_REPLY => - case RX_Status IS + case RX_Status is when NET_ICMPV4_RX_STATUS_IDLE => null; when NET_ICMPV4_RX_STATUS_RECEIVING => null; when NET_ICMPV4_RX_STATUS_RECEIVED_ECHO_REPLY => FSM_NextState <= ST_EVAL_ECHO_REPLY; @@ -281,7 +280,7 @@ begin FSM_TX_Meta_Identification <= RX_Meta_Identification; FSM_TX_Meta_SequenceNumber <= RX_Meta_SequenceNumber; - case TX_Status IS + case TX_Status is when NET_ICMPV4_TX_STATUS_IDLE => null; when NET_ICMPV4_TX_STATUS_SENDING => null; when NET_ICMPV4_TX_STATUS_SEND_COMPLETE => FSM_NextState <= ST_SEND_ECHO_REPLY_FINISHED; @@ -305,9 +304,9 @@ begin end case; end process; --- ============================================================================================================================================================ +-- ============================================================================= -- TX Path --- ============================================================================================================================================================ +-- ============================================================================= TX : entity PoC.icmpv4_TX generic map ( DEBUG => DEBUG, @@ -345,9 +344,9 @@ begin In_Meta_Payload_Data => FSM_TX_Meta_Payload_Data ); --- ============================================================================================================================================================ +-- ============================================================================= -- RX Path --- ============================================================================================================================================================ +-- ============================================================================= RX : entity PoC.icmpv4_RX generic map ( DEBUG => DEBUG diff --git a/src/net/ipv4/ipv4_FrameLoopback.vhdl b/src/net/ipv4/ipv4_FrameLoopback.vhdl index fc604682..576e358f 100644 --- a/src/net/ipv4/ipv4_FrameLoopback.vhdl +++ b/src/net/ipv4/ipv4_FrameLoopback.vhdl @@ -1,18 +1,17 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: TODO +-- Entity: TODO -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -27,7 +26,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -42,33 +41,33 @@ use PoC.net.all; entity ipv4_FrameLoopback is generic ( - MAX_FRAMES : POSITIVE := 4 + MAX_FRAMES : positive := 4 ); port ( - Clock : in STD_LOGIC; - Reset : in STD_LOGIC; + Clock : in std_logic; + Reset : in std_logic; -- IN port - In_Valid : in STD_LOGIC; + In_Valid : in std_logic; In_Data : in T_SLV_8; - In_SOF : in STD_LOGIC; - In_EOF : in STD_LOGIC; - In_Ack : out STD_LOGIC; - In_Meta_rst : out STD_LOGIC; - In_Meta_SrcIPv4Address_nxt : out STD_LOGIC; + In_SOF : in std_logic; + In_EOF : in std_logic; + In_Ack : out std_logic; + In_Meta_rst : out std_logic; + In_Meta_SrcIPv4Address_nxt : out std_logic; In_Meta_SrcIPv4Address_Data : in T_SLV_8; - In_Meta_DestIPv4Address_nxt : out STD_LOGIC; + In_Meta_DestIPv4Address_nxt : out std_logic; In_Meta_DestIPv4Address_Data : in T_SLV_8; In_Meta_Length : in T_SLV_16; -- OUT port - Out_Valid : out STD_LOGIC; + Out_Valid : out std_logic; Out_Data : out T_SLV_8; - Out_SOF : out STD_LOGIC; - Out_EOF : out STD_LOGIC; - Out_Ack : in STD_LOGIC; - Out_Meta_rst : in STD_LOGIC; - Out_Meta_SrcIPv4Address_nxt : in STD_LOGIC; + Out_SOF : out std_logic; + Out_EOF : out std_logic; + Out_Ack : in std_logic; + Out_Meta_rst : in std_logic; + Out_Meta_SrcIPv4Address_nxt : in std_logic; Out_Meta_SrcIPv4Address_Data : out T_SLV_8; - Out_Meta_DestIPv4Address_nxt : in STD_LOGIC; + Out_Meta_DestIPv4Address_nxt : in std_logic; Out_Meta_DestIPv4Address_Data : out T_SLV_8; Out_Meta_Length : out T_SLV_16 ); @@ -76,9 +75,9 @@ end entity; architecture rtl of ipv4_FrameLoopback is - constant META_STREAMID_SRCADDR : NATURAL := 0; - constant META_STREAMID_DESTADDR : NATURAL := 1; - constant META_STREAMID_LENGTH : NATURAL := 2; + constant META_STREAMID_SRCADDR : natural := 0; + constant META_STREAMID_DESTADDR : natural := 1; + constant META_STREAMID_LENGTH : natural := 2; constant META_BITS : T_POSVEC := ( META_STREAMID_SRCADDR => 8, @@ -92,10 +91,10 @@ architecture rtl of ipv4_FrameLoopback is META_STREAMID_LENGTH => 1 ); - signal StmBuf_MetaIn_nxt : STD_LOGIC_VECTOR(META_BITS'length - 1 downto 0); - signal StmBuf_MetaIn_Data : STD_LOGIC_VECTOR(isum(META_BITS) - 1 downto 0); - signal StmBuf_MetaOut_nxt : STD_LOGIC_VECTOR(META_BITS'length - 1 downto 0); - signal StmBuf_MetaOut_Data : STD_LOGIC_VECTOR(isum(META_BITS) - 1 downto 0); + signal StmBuf_MetaIn_nxt : std_logic_vector(META_BITS'length - 1 downto 0); + signal StmBuf_MetaIn_Data : std_logic_vector(isum(META_BITS) - 1 downto 0); + signal StmBuf_MetaOut_nxt : std_logic_vector(META_BITS'length - 1 downto 0); + signal StmBuf_MetaOut_Data : std_logic_vector(isum(META_BITS) - 1 downto 0); begin StmBuf_MetaIn_Data(high(META_BITS, META_STREAMID_SRCADDR) downto low(META_BITS, META_STREAMID_SRCADDR)) <= In_Meta_SrcIPv4Address_Data; diff --git a/src/net/ipv4/ipv4_RX.vhdl b/src/net/ipv4/ipv4_RX.vhdl index ff65c102..a49c4ea1 100644 --- a/src/net/ipv4/ipv4_RX.vhdl +++ b/src/net/ipv4/ipv4_RX.vhdl @@ -1,18 +1,17 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: TODO +-- Entity: TODO -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -27,7 +26,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -42,40 +41,40 @@ use PoC.net.all; entity ipv4_RX is generic ( - DEBUG : BOOLEAN := FALSE + DEBUG : boolean := FALSE ); port ( - Clock : in STD_LOGIC; -- - Reset : in STD_LOGIC; -- + Clock : in std_logic; -- + Reset : in std_logic; -- -- STATUS port - Error : out STD_LOGIC; + Error : out std_logic; -- IN port - In_Valid : in STD_LOGIC; + In_Valid : in std_logic; In_Data : in T_SLV_8; - In_SOF : in STD_LOGIC; - In_EOF : in STD_LOGIC; - In_Ack : out STD_LOGIC; - In_Meta_rst : out STD_LOGIC; - In_Meta_SrcMACAddress_nxt : out STD_LOGIC; + In_SOF : in std_logic; + In_EOF : in std_logic; + In_Ack : out std_logic; + In_Meta_rst : out std_logic; + In_Meta_SrcMACAddress_nxt : out std_logic; In_Meta_SrcMACAddress_Data : in T_SLV_8; - In_Meta_DestMACAddress_nxt : out STD_LOGIC; + In_Meta_DestMACAddress_nxt : out std_logic; In_Meta_DestMACAddress_Data : in T_SLV_8; In_Meta_EthType : in T_SLV_16; -- OUT port - Out_Valid : out STD_LOGIC; + Out_Valid : out std_logic; Out_Data : out T_SLV_8; - Out_SOF : out STD_LOGIC; - Out_EOF : out STD_LOGIC; - Out_Ack : in STD_LOGIC; - Out_Meta_rst : in STD_LOGIC; - Out_Meta_SrcMACAddress_nxt : in STD_LOGIC; + Out_SOF : out std_logic; + Out_EOF : out std_logic; + Out_Ack : in std_logic; + Out_Meta_rst : in std_logic; + Out_Meta_SrcMACAddress_nxt : in std_logic; Out_Meta_SrcMACAddress_Data : out T_SLV_8; - Out_Meta_DestMACAddress_nxt : in STD_LOGIC; + Out_Meta_DestMACAddress_nxt : in std_logic; Out_Meta_DestMACAddress_Data : out T_SLV_8; Out_Meta_EthType : out T_SLV_16; - Out_Meta_SrcIPv4Address_nxt : in STD_LOGIC; + Out_Meta_SrcIPv4Address_nxt : in std_logic; Out_Meta_SrcIPv4Address_Data : out T_SLV_8; - Out_Meta_DestIPv4Address_nxt : in STD_LOGIC; + Out_Meta_DestIPv4Address_nxt : in std_logic; Out_Meta_DestIPv4Address_Data : out T_SLV_8; Out_Meta_Length : out T_SLV_16; Out_Meta_Protocol : out T_SLV_8 @@ -84,7 +83,7 @@ end entity; architecture rtl of ipv4_RX is - attribute FSM_ENCODING : STRING; + attribute FSM_ENCODING : string; type T_STATE is ( ST_IDLE, @@ -101,45 +100,45 @@ architecture rtl of ipv4_RX is signal State : T_STATE := ST_IDLE; signal NextState : T_STATE; - attribute FSM_ENCODING of State : signal IS ite(DEBUG, "gray", ite((VENDOR = VENDOR_XILINX), "auto", "default")); + attribute FSM_ENCODING of State : signal is ite(DEBUG, "gray", ite((VENDOR = VENDOR_XILINX), "auto", "default")); - signal In_Ack_i : STD_LOGIC; - signal Is_DataFlow : STD_LOGIC; - signal Is_SOF : STD_LOGIC; - signal Is_EOF : STD_LOGIC; + signal In_Ack_i : std_logic; + signal Is_DataFlow : std_logic; + signal Is_SOF : std_logic; + signal Is_EOF : std_logic; - signal Out_Valid_i : STD_LOGIC; - signal Out_SOF_i : STD_LOGIC; - signal Out_EOF_i : STD_LOGIC; + signal Out_Valid_i : std_logic; + signal Out_SOF_i : std_logic; + signal Out_EOF_i : std_logic; - subtype T_IPV4_BYTEINDEX is NATURAL range 0 to 3; + subtype T_IPV4_BYTEINDEX is natural range 0 to 3; signal IP_ByteIndex : T_IPV4_BYTEINDEX; - signal Register_rst : STD_LOGIC; + signal Register_rst : std_logic; -- IPv4 Basic Header - signal HeaderLength_en : STD_LOGIC; - signal TypeOfService_en : STD_LOGIC; - signal TotalLength_en0 : STD_LOGIC; - signal TotalLength_en1 : STD_LOGIC; + signal HeaderLength_en : std_logic; + signal TypeOfService_en : std_logic; + signal TotalLength_en0 : std_logic; + signal TotalLength_en1 : std_logic; -- signal Identification_en0 : STD_LOGIC; -- signal Identification_en1 : STD_LOGIC; - signal Flags_en : STD_LOGIC; + signal Flags_en : std_logic; -- signal FragmentOffset_en0 : STD_LOGIC; -- signal FragmentOffset_en1 : STD_LOGIC; - signal TimeToLive_en : STD_LOGIC; - signal Protocol_en : STD_LOGIC; - signal HeaderChecksum_en0 : STD_LOGIC; - signal HeaderChecksum_en1 : STD_LOGIC; - signal SourceIPv4Address_en : STD_LOGIC; - signal DestIPv4Address_en : STD_LOGIC; + signal TimeToLive_en : std_logic; + signal Protocol_en : std_logic; + signal HeaderChecksum_en0 : std_logic; + signal HeaderChecksum_en1 : std_logic; + signal SourceIPv4Address_en : std_logic; + signal DestIPv4Address_en : std_logic; signal HeaderLength_d : T_SLV_4 := (others => '0'); signal TypeOfService_d : T_SLV_8 := (others => '0'); signal TotalLength_d : T_SLV_16 := (others => '0'); -- signal Identification_d : T_SLV_16 := (others => '0'); - signal Flag_DontFragment_d : STD_LOGIC := '0'; - signal Flag_MoreFragmenta_d : STD_LOGIC := '0'; + signal Flag_DontFragment_d : std_logic := '0'; + signal Flag_MoreFragmenta_d : std_logic := '0'; -- signal FragmentOffset_d : STD_LOGIC_VECTOR(12 downto 0) := (others => '0'); signal TimeToLive_d : T_SLV_8 := (others => '0'); signal Protocol_d : T_SLV_8 := (others => '0'); @@ -147,26 +146,26 @@ architecture rtl of ipv4_RX is signal SourceIPv4Address_d : T_NET_IPV4_ADDRESS := (others => (others => '0')); signal DestIPv4Address_d : T_NET_IPV4_ADDRESS := (others => (others => '0')); - constant IPV4_ADDRESS_LENGTH : POSITIVE := 4; -- IPv4 -> 4 bytes - constant IPV4_ADDRESS_READER_BITS : POSITIVE := log2ceilnz(IPV4_ADDRESS_LENGTH); + constant IPV4_ADDRESS_LENGTH : positive := 4; -- IPv4 -> 4 bytes + constant IPV4_ADDRESS_READER_BITS : positive := log2ceilnz(IPV4_ADDRESS_LENGTH); - signal IPv4SeqCounter_rst : STD_LOGIC; - signal IPv4SeqCounter_en : STD_LOGIC; - signal IPv4SeqCounter_us : UNSIGNED(IPV4_ADDRESS_READER_BITS - 1 downto 0) := to_unsigned(IPV4_ADDRESS_LENGTH - 1, IPV4_ADDRESS_READER_BITS); + signal IPv4SeqCounter_rst : std_logic; + signal IPv4SeqCounter_en : std_logic; + signal IPv4SeqCounter_us : unsigned(IPV4_ADDRESS_READER_BITS - 1 downto 0) := to_unsigned(IPV4_ADDRESS_LENGTH - 1, IPV4_ADDRESS_READER_BITS); - signal SrcIPv4Address_Reader_rst : STD_LOGIC; - signal SrcIPv4Address_Reader_en : STD_LOGIC; - signal SrcIPv4Address_Reader_us : UNSIGNED(IPV4_ADDRESS_READER_BITS - 1 downto 0) := to_unsigned(IPV4_ADDRESS_LENGTH - 1, IPV4_ADDRESS_READER_BITS); - signal DestIPv4Address_Reader_rst : STD_LOGIC; - signal DestIPv4Address_Reader_en : STD_LOGIC; - signal DestIPv4Address_Reader_us : UNSIGNED(IPV4_ADDRESS_READER_BITS - 1 downto 0) := to_unsigned(IPV4_ADDRESS_LENGTH - 1, IPV4_ADDRESS_READER_BITS); + signal SrcIPv4Address_Reader_rst : std_logic; + signal SrcIPv4Address_Reader_en : std_logic; + signal SrcIPv4Address_Reader_us : unsigned(IPV4_ADDRESS_READER_BITS - 1 downto 0) := to_unsigned(IPV4_ADDRESS_LENGTH - 1, IPV4_ADDRESS_READER_BITS); + signal DestIPv4Address_Reader_rst : std_logic; + signal DestIPv4Address_Reader_en : std_logic; + signal DestIPv4Address_Reader_us : unsigned(IPV4_ADDRESS_READER_BITS - 1 downto 0) := to_unsigned(IPV4_ADDRESS_LENGTH - 1, IPV4_ADDRESS_READER_BITS); begin In_Ack <= In_Ack_i; - Is_DataFlow <= In_Valid AND In_Ack_i; - Is_SOF <= In_Valid AND In_SOF; - Is_EOF <= In_Valid AND In_EOF; + Is_DataFlow <= In_Valid and In_Ack_i; + Is_SOF <= In_Valid and In_SOF; + Is_EOF <= In_Valid and In_EOF; process(Clock) begin @@ -438,7 +437,7 @@ begin process(Clock) begin if rising_edge(Clock) then - if ((Reset OR Register_rst) = '1') then + if ((Reset or Register_rst) = '1') then HeaderLength_d <= (others => '0'); TypeOfService_d <= (others => '0'); TotalLength_d <= (others => '0'); @@ -515,7 +514,7 @@ begin process(Clock) begin if rising_edge(Clock) then - if ((Reset OR IPv4SeqCounter_rst) = '1') then + if ((Reset or IPv4SeqCounter_rst) = '1') then IPv4SeqCounter_us <= to_unsigned(IPV4_ADDRESS_LENGTH - 1, IPV4_ADDRESS_READER_BITS); elsif (IPv4SeqCounter_en = '1') then IPv4SeqCounter_us <= IPv4SeqCounter_us - 1; @@ -531,7 +530,7 @@ begin process(Clock) begin if rising_edge(Clock) then - if ((Reset OR SrcIPv4Address_Reader_rst) = '1') then + if ((Reset or SrcIPv4Address_Reader_rst) = '1') then SrcIPv4Address_Reader_us <= to_unsigned(IPV4_ADDRESS_LENGTH - 1, IPV4_ADDRESS_READER_BITS); elsif (SrcIPv4Address_Reader_en = '1') then SrcIPv4Address_Reader_us <= SrcIPv4Address_Reader_us - 1; @@ -542,7 +541,7 @@ begin process(Clock) begin if rising_edge(Clock) then - if ((Reset OR DestIPv4Address_Reader_rst) = '1') then + if ((Reset or DestIPv4Address_Reader_rst) = '1') then DestIPv4Address_Reader_us <= to_unsigned(IPV4_ADDRESS_LENGTH - 1, IPV4_ADDRESS_READER_BITS); elsif (DestIPv4Address_Reader_en = '1') then DestIPv4Address_Reader_us <= DestIPv4Address_Reader_us - 1; diff --git a/src/net/ipv4/ipv4_TX.vhdl b/src/net/ipv4/ipv4_TX.vhdl index c4e57551..328c4c8d 100644 --- a/src/net/ipv4/ipv4_TX.vhdl +++ b/src/net/ipv4/ipv4_TX.vhdl @@ -1,18 +1,17 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: TODO +-- Entity: TODO -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -27,7 +26,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -42,48 +41,48 @@ use PoC.net.all; entity ipv4_TX is generic ( - DEBUG : BOOLEAN := FALSE + DEBUG : boolean := FALSE ); port ( - Clock : in STD_LOGIC; -- - Reset : in STD_LOGIC; -- + Clock : in std_logic; -- + Reset : in std_logic; -- -- IN port - In_Valid : in STD_LOGIC; + In_Valid : in std_logic; In_Data : in T_SLV_8; - In_SOF : in STD_LOGIC; - In_EOF : in STD_LOGIC; - In_Ack : out STD_LOGIC; - In_Meta_rst : out STD_LOGIC; - In_Meta_SrcIPv4Address_nxt : out STD_LOGIC; + In_SOF : in std_logic; + In_EOF : in std_logic; + In_Ack : out std_logic; + In_Meta_rst : out std_logic; + In_Meta_SrcIPv4Address_nxt : out std_logic; In_Meta_SrcIPv4Address_Data : in T_SLV_8; - In_Meta_DestIPv4Address_nxt : out STD_LOGIC; + In_Meta_DestIPv4Address_nxt : out std_logic; In_Meta_DestIPv4Address_Data : in T_SLV_8; In_Meta_Length : in T_SLV_16; In_Meta_Protocol : in T_SLV_8; -- ARP port - ARP_IPCache_Query : out STD_LOGIC; - ARP_IPCache_IPv4Address_rst : in STD_LOGIC; - ARP_IPCache_IPv4Address_nxt : in STD_LOGIC; + ARP_IPCache_Query : out std_logic; + ARP_IPCache_IPv4Address_rst : in std_logic; + ARP_IPCache_IPv4Address_nxt : in std_logic; ARP_IPCache_IPv4Address_Data : out T_SLV_8; - ARP_IPCache_Valid : in STD_LOGIC; - ARP_IPCache_MACAddress_rst : out STD_LOGIC; - ARP_IPCache_MACAddress_nxt : out STD_LOGIC; + ARP_IPCache_Valid : in std_logic; + ARP_IPCache_MACAddress_rst : out std_logic; + ARP_IPCache_MACAddress_nxt : out std_logic; ARP_IPCache_MACAddress_Data : in T_SLV_8; -- OUT port - Out_Valid : out STD_LOGIC; + Out_Valid : out std_logic; Out_Data : out T_SLV_8; - Out_SOF : out STD_LOGIC; - Out_EOF : out STD_LOGIC; - Out_Ack : in STD_LOGIC; - Out_Meta_rst : in STD_LOGIC; - Out_Meta_DestMACAddress_nxt : in STD_LOGIC; + Out_SOF : out std_logic; + Out_EOF : out std_logic; + Out_Ack : in std_logic; + Out_Meta_rst : in std_logic; + Out_Meta_DestMACAddress_nxt : in std_logic; Out_Meta_DestMACAddress_Data : out T_SLV_8 ); end entity; architecture rtl of ipv4_TX is - attribute FSM_ENCODING : STRING; + attribute FSM_ENCODING : string; type T_STATE is ( ST_IDLE, @@ -106,47 +105,47 @@ architecture rtl of ipv4_TX is signal State : T_STATE := ST_IDLE; signal NextState : T_STATE; - attribute FSM_ENCODING of State : signal IS ite(DEBUG, "gray", ite((VENDOR = VENDOR_XILINX), "auto", "default")); + attribute FSM_ENCODING of State : signal is ite(DEBUG, "gray", ite((VENDOR = VENDOR_XILINX), "auto", "default")); - signal In_Ack_i : STD_LOGIC; + signal In_Ack_i : std_logic; - signal UpperLayerPacketLength : STD_LOGIC_VECTOR(15 downto 0); + signal UpperLayerPacketLength : std_logic_vector(15 downto 0); signal InternetHeaderLength : T_SLV_4; signal TypeOfService : T_NET_IPV4_TYPE_OF_SERVICE; signal TotalLength : T_SLV_16; signal Identification : T_SLV_16; - signal Flag_DontFragment : STD_LOGIC; - signal Flag_MoreFragments : STD_LOGIC; - signal FragmentOffset : STD_LOGIC_VECTOR(12 downto 0); + signal Flag_DontFragment : std_logic; + signal Flag_MoreFragments : std_logic; + signal FragmentOffset : std_logic_vector(12 downto 0); signal TimeToLive : T_SLV_8; signal Protocol : T_SLV_8; signal HeaderChecksum : T_SLV_16; - signal IPv4SeqCounter_rst : STD_LOGIC; - signal IPv4SeqCounter_en : STD_LOGIC; - signal IPv4SeqCounter_us : UNSIGNED(1 downto 0) := (others => '0'); - - signal Checksum_rst : STD_LOGIC; - signal Checksum_en : STD_LOGIC; - signal Checksum_Addend0_us : UNSIGNED(T_SLV_8'range); - signal Checksum_Addend1_us : UNSIGNED(T_SLV_8'range); - signal Checksum0_nxt0_us : UNSIGNED(T_SLV_8'high + 1 downto 0); - signal Checksum0_nxt1_us : UNSIGNED(T_SLV_8'high + 1 downto 0); - signal Checksum0_d_us : UNSIGNED(T_SLV_8'high downto 0) := (others => '0'); - signal Checksum0_cy : UNSIGNED(T_SLV_2'range); - signal Checksum1_nxt_us : UNSIGNED(T_SLV_8'range); - signal Checksum1_d_us : UNSIGNED(T_SLV_8'range) := (others => '0'); - signal Checksum0_cy0 : STD_LOGIC; - signal Checksum0_cy0_d : STD_LOGIC := '0'; - signal Checksum0_cy1 : STD_LOGIC; - signal Checksum0_cy1_d : STD_LOGIC := '0'; + signal IPv4SeqCounter_rst : std_logic; + signal IPv4SeqCounter_en : std_logic; + signal IPv4SeqCounter_us : unsigned(1 downto 0) := (others => '0'); + + signal Checksum_rst : std_logic; + signal Checksum_en : std_logic; + signal Checksum_Addend0_us : unsigned(T_SLV_8'range); + signal Checksum_Addend1_us : unsigned(T_SLV_8'range); + signal Checksum0_nxt0_us : unsigned(T_SLV_8'high + 1 downto 0); + signal Checksum0_nxt1_us : unsigned(T_SLV_8'high + 1 downto 0); + signal Checksum0_d_us : unsigned(T_SLV_8'high downto 0) := (others => '0'); + signal Checksum0_cy : unsigned(T_SLV_2'range); + signal Checksum1_nxt_us : unsigned(T_SLV_8'range); + signal Checksum1_d_us : unsigned(T_SLV_8'range) := (others => '0'); + signal Checksum0_cy0 : std_logic; + signal Checksum0_cy0_d : std_logic := '0'; + signal Checksum0_cy1 : std_logic; + signal Checksum0_cy1_d : std_logic := '0'; signal Checksum_i : T_SLV_16; signal Checksum : T_SLV_16; - signal Checksum_mux_rst : STD_LOGIC; - signal Checksum_mux_set : STD_LOGIC; - signal Checksum_mux_r : STD_LOGIC := '0'; + signal Checksum_mux_rst : std_logic; + signal Checksum_mux_set : std_logic; + signal Checksum_mux_r : std_logic := '0'; begin @@ -220,7 +219,7 @@ begin IPv4SeqCounter_rst <= '1'; Checksum_rst <= '1'; - if ((In_Valid AND In_SOF) = '1') then + if ((In_Valid and In_SOF) = '1') then NextState <= ST_ARP_QUERY; end if; @@ -484,7 +483,7 @@ begin Out_EOF <= In_EOF; In_Ack_i <= Out_Ack; - if ((In_EOF AND Out_Ack) = '1') then + if ((In_EOF and Out_Ack) = '1') then In_Meta_rst <= '1'; NextState <= ST_IDLE; end if; @@ -501,7 +500,7 @@ begin process(Clock) begin if rising_edge(Clock) then - if ((Reset OR IPv4SeqCounter_rst) = '1') then + if ((Reset or IPv4SeqCounter_rst) = '1') then IPv4SeqCounter_us <= (others => '0'); elsif (IPv4SeqCounter_en = '1') then IPv4SeqCounter_us <= IPv4SeqCounter_us + 1; @@ -544,7 +543,7 @@ Checksum0_nxt0_us <= ("0" & Checksum1_d_us) process(Clock) begin if rising_edge(Clock) then - if ((Reset OR Checksum_mux_rst) = '1') then + if ((Reset or Checksum_mux_rst) = '1') then Checksum_mux_r <= '0'; elsif (Checksum_mux_set = '1') then Checksum_mux_r <= '1'; diff --git a/src/net/ipv4/ipv4_Wrapper.vhdl b/src/net/ipv4/ipv4_Wrapper.vhdl index 5316628d..23cc65e3 100644 --- a/src/net/ipv4/ipv4_Wrapper.vhdl +++ b/src/net/ipv4/ipv4_Wrapper.vhdl @@ -1,18 +1,17 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: TODO +-- Entity: TODO -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -27,7 +26,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -42,70 +41,70 @@ use PoC.net.all; entity ipv4_Wrapper is generic ( - DEBUG : BOOLEAN := FALSE; + DEBUG : boolean := FALSE; PACKET_TYPES : T_NET_IPV4_PROTOCOL_VECTOR := (0 => x"00") ); port ( - Clock : in STD_LOGIC; - Reset : in STD_LOGIC; + Clock : in std_logic; + Reset : in std_logic; -- to MAC layer - MAC_TX_Valid : out STD_LOGIC; + MAC_TX_Valid : out std_logic; MAC_TX_Data : out T_SLV_8; - MAC_TX_SOF : out STD_LOGIC; - MAC_TX_EOF : out STD_LOGIC; - MAC_TX_Ack : in STD_LOGIC; - MAC_TX_Meta_rst : in STD_LOGIC; - MAC_TX_Meta_DestMACAddress_nxt : in STD_LOGIC; + MAC_TX_SOF : out std_logic; + MAC_TX_EOF : out std_logic; + MAC_TX_Ack : in std_logic; + MAC_TX_Meta_rst : in std_logic; + MAC_TX_Meta_DestMACAddress_nxt : in std_logic; MAC_TX_Meta_DestMACAddress_Data : out T_SLV_8; -- from MAC layer - MAC_RX_Valid : in STD_LOGIC; + MAC_RX_Valid : in std_logic; MAC_RX_Data : in T_SLV_8; - MAC_RX_SOF : in STD_LOGIC; - MAC_RX_EOF : in STD_LOGIC; - MAC_RX_Ack : out STD_LOGIC; - MAC_RX_Meta_rst : out STD_LOGIC; - MAC_RX_Meta_SrcMACAddress_nxt : out STD_LOGIC; + MAC_RX_SOF : in std_logic; + MAC_RX_EOF : in std_logic; + MAC_RX_Ack : out std_logic; + MAC_RX_Meta_rst : out std_logic; + MAC_RX_Meta_SrcMACAddress_nxt : out std_logic; MAC_RX_Meta_SrcMACAddress_Data : in T_SLV_8; - MAC_RX_Meta_DestMACAddress_nxt : out STD_LOGIC; + MAC_RX_Meta_DestMACAddress_nxt : out std_logic; MAC_RX_Meta_DestMACAddress_Data : in T_SLV_8; MAC_RX_Meta_EthType : in T_SLV_16; -- to ARP - ARP_IPCache_Query : out STD_LOGIC; - ARP_IPCache_IPv4Address_rst : in STD_LOGIC; - ARP_IPCache_IPv4Address_nxt : in STD_LOGIC; + ARP_IPCache_Query : out std_logic; + ARP_IPCache_IPv4Address_rst : in std_logic; + ARP_IPCache_IPv4Address_nxt : in std_logic; ARP_IPCache_IPv4Address_Data : out T_SLV_8; -- from ARP - ARP_IPCache_Valid : in STD_LOGIC; - ARP_IPCache_MACAddress_rst : out STD_LOGIC; - ARP_IPCache_MACAddress_nxt : out STD_LOGIC; + ARP_IPCache_Valid : in std_logic; + ARP_IPCache_MACAddress_rst : out std_logic; + ARP_IPCache_MACAddress_nxt : out std_logic; ARP_IPCache_MACAddress_Data : in T_SLV_8; -- from upper layer - TX_Valid : in STD_LOGIC_VECTOR(PACKET_TYPES'length - 1 downto 0); + TX_Valid : in std_logic_vector(PACKET_TYPES'length - 1 downto 0); TX_Data : in T_SLVV_8(PACKET_TYPES'length - 1 downto 0); - TX_SOF : in STD_LOGIC_VECTOR(PACKET_TYPES'length - 1 downto 0); - TX_EOF : in STD_LOGIC_VECTOR(PACKET_TYPES'length - 1 downto 0); - TX_Ack : out STD_LOGIC_VECTOR(PACKET_TYPES'length - 1 downto 0); - TX_Meta_rst : out STD_LOGIC_VECTOR(PACKET_TYPES'length - 1 downto 0); - TX_Meta_SrcIPv4Address_nxt : out STD_LOGIC_VECTOR(PACKET_TYPES'length - 1 downto 0); + TX_SOF : in std_logic_vector(PACKET_TYPES'length - 1 downto 0); + TX_EOF : in std_logic_vector(PACKET_TYPES'length - 1 downto 0); + TX_Ack : out std_logic_vector(PACKET_TYPES'length - 1 downto 0); + TX_Meta_rst : out std_logic_vector(PACKET_TYPES'length - 1 downto 0); + TX_Meta_SrcIPv4Address_nxt : out std_logic_vector(PACKET_TYPES'length - 1 downto 0); TX_Meta_SrcIPv4Address_Data : in T_SLVV_8(PACKET_TYPES'length - 1 downto 0); - TX_Meta_DestIPv4Address_nxt : out STD_LOGIC_VECTOR(PACKET_TYPES'length - 1 downto 0); + TX_Meta_DestIPv4Address_nxt : out std_logic_vector(PACKET_TYPES'length - 1 downto 0); TX_Meta_DestIPv4Address_Data : in T_SLVV_8(PACKET_TYPES'length - 1 downto 0); TX_Meta_Length : in T_SLVV_16(PACKET_TYPES'length - 1 downto 0); -- to upper layer - RX_Valid : out STD_LOGIC_VECTOR(PACKET_TYPES'length - 1 downto 0); + RX_Valid : out std_logic_vector(PACKET_TYPES'length - 1 downto 0); RX_Data : out T_SLVV_8(PACKET_TYPES'length - 1 downto 0); - RX_SOF : out STD_LOGIC_VECTOR(PACKET_TYPES'length - 1 downto 0); - RX_EOF : out STD_LOGIC_VECTOR(PACKET_TYPES'length - 1 downto 0); - RX_Ack : in STD_LOGIC_VECTOR(PACKET_TYPES'length - 1 downto 0); - RX_Meta_rst : in STD_LOGIC_VECTOR(PACKET_TYPES'length - 1 downto 0); - RX_Meta_SrcMACAddress_nxt : in STD_LOGIC_VECTOR(PACKET_TYPES'length - 1 downto 0); + RX_SOF : out std_logic_vector(PACKET_TYPES'length - 1 downto 0); + RX_EOF : out std_logic_vector(PACKET_TYPES'length - 1 downto 0); + RX_Ack : in std_logic_vector(PACKET_TYPES'length - 1 downto 0); + RX_Meta_rst : in std_logic_vector(PACKET_TYPES'length - 1 downto 0); + RX_Meta_SrcMACAddress_nxt : in std_logic_vector(PACKET_TYPES'length - 1 downto 0); RX_Meta_SrcMACAddress_Data : out T_SLVV_8(PACKET_TYPES'length - 1 downto 0); - RX_Meta_DestMACAddress_nxt : in STD_LOGIC_VECTOR(PACKET_TYPES'length - 1 downto 0); + RX_Meta_DestMACAddress_nxt : in std_logic_vector(PACKET_TYPES'length - 1 downto 0); RX_Meta_DestMACAddress_Data : out T_SLVV_8(PACKET_TYPES'length - 1 downto 0); RX_Meta_EthType : out T_SLVV_16(PACKET_TYPES'length - 1 downto 0); - RX_Meta_SrcIPv4Address_nxt : in STD_LOGIC_VECTOR(PACKET_TYPES'length - 1 downto 0); + RX_Meta_SrcIPv4Address_nxt : in std_logic_vector(PACKET_TYPES'length - 1 downto 0); RX_Meta_SrcIPv4Address_Data : out T_SLVV_8(PACKET_TYPES'length - 1 downto 0); - RX_Meta_DestIPv4Address_nxt : in STD_LOGIC_VECTOR(PACKET_TYPES'length - 1 downto 0); + RX_Meta_DestIPv4Address_nxt : in std_logic_vector(PACKET_TYPES'length - 1 downto 0); RX_Meta_DestIPv4Address_Data : out T_SLVV_8(PACKET_TYPES'length - 1 downto 0); RX_Meta_Length : out T_SLVV_16(PACKET_TYPES'length - 1 downto 0); RX_Meta_Protocol : out T_SLVV_8(PACKET_TYPES'length - 1 downto 0) @@ -114,12 +113,12 @@ end entity; architecture rtl of ipv4_Wrapper is - constant IPV4_SWITCH_PORTS : POSITIVE := PACKET_TYPES'length; + constant IPV4_SWITCH_PORTS : positive := PACKET_TYPES'length; - constant TXSTMMUX_META_STREAMID_SRCADR : NATURAL := 0; - constant TXSTMMUX_META_STREAMID_DESTADR : NATURAL := 1; - constant TXSTMMUX_META_STREAMID_LENGTH : NATURAL := 2; - constant TXSTMMUX_META_STREAMID_PROTOCOL : NATURAL := 3; + constant TXSTMMUX_META_STREAMID_SRCADR : natural := 0; + constant TXSTMMUX_META_STREAMID_DESTADR : natural := 1; + constant TXSTMMUX_META_STREAMID_LENGTH : natural := 2; + constant TXSTMMUX_META_STREAMID_PROTOCOL : natural := 3; constant TXSTMMUX_META_BITS : T_POSVEC := ( TXSTMMUX_META_STREAMID_SRCADR => 8, @@ -128,40 +127,40 @@ architecture rtl of ipv4_Wrapper is TXSTMMUX_META_STREAMID_PROTOCOL => 8 ); - constant TXSTMMUX_META_RST_BIT : NATURAL := 0; - constant TXSTMMUX_META_SRC_NXT_BIT : NATURAL := 1; - constant TXSTMMUX_META_DEST_NXT_BIT : NATURAL := 2; + constant TXSTMMUX_META_RST_BIT : natural := 0; + constant TXSTMMUX_META_SRC_NXT_BIT : natural := 1; + constant TXSTMMUX_META_DEST_NXT_BIT : natural := 2; - constant TXSTMMUX_META_REV_BITS : NATURAL := 3; + constant TXSTMMUX_META_REV_BITS : natural := 3; - signal StmMux_In_Valid : STD_LOGIC_VECTOR(IPV4_SWITCH_PORTS - 1 downto 0); + signal StmMux_In_Valid : std_logic_vector(IPV4_SWITCH_PORTS - 1 downto 0); signal StmMux_In_Data : T_SLM(IPV4_SWITCH_PORTS - 1 downto 0, T_SLV_8'range) := (others => (others => 'Z')); -- necessary default assignment 'Z' to get correct simulation results (iSIM, vSIM, ghdl/gtkwave) signal StmMux_In_Meta : T_SLM(IPV4_SWITCH_PORTS - 1 downto 0, isum(TXSTMMUX_META_BITS) - 1 downto 0) := (others => (others => 'Z')); -- necessary default assignment 'Z' to get correct simulation results (iSIM, vSIM, ghdl/gtkwave) signal StmMux_In_Meta_rev : T_SLM(IPV4_SWITCH_PORTS - 1 downto 0, TXSTMMUX_META_REV_BITS - 1 downto 0) := (others => (others => 'Z')); -- necessary default assignment 'Z' to get correct simulation results (iSIM, vSIM, ghdl/gtkwave) - signal StmMux_In_SOF : STD_LOGIC_VECTOR(IPV4_SWITCH_PORTS - 1 downto 0); - signal StmMux_In_EOF : STD_LOGIC_VECTOR(IPV4_SWITCH_PORTS - 1 downto 0); - signal StmMux_In_Ack : STD_LOGIC_VECTOR(IPV4_SWITCH_PORTS - 1 downto 0); + signal StmMux_In_SOF : std_logic_vector(IPV4_SWITCH_PORTS - 1 downto 0); + signal StmMux_In_EOF : std_logic_vector(IPV4_SWITCH_PORTS - 1 downto 0); + signal StmMux_In_Ack : std_logic_vector(IPV4_SWITCH_PORTS - 1 downto 0); - signal TX_StmMux_Valid : STD_LOGIC; + signal TX_StmMux_Valid : std_logic; signal TX_StmMux_Data : T_SLV_8; - signal TX_StmMux_Meta : STD_LOGIC_VECTOR(isum(TXSTMMUX_META_BITS) - 1 downto 0); - signal TX_StmMux_Meta_rev : STD_LOGIC_VECTOR(TXSTMMUX_META_REV_BITS - 1 downto 0); - signal TX_StmMux_SOF : STD_LOGIC; - signal TX_StmMux_EOF : STD_LOGIC; + signal TX_StmMux_Meta : std_logic_vector(isum(TXSTMMUX_META_BITS) - 1 downto 0); + signal TX_StmMux_Meta_rev : std_logic_vector(TXSTMMUX_META_REV_BITS - 1 downto 0); + signal TX_StmMux_SOF : std_logic; + signal TX_StmMux_EOF : std_logic; signal TX_StmMux_SrcIPv4Address_Data : T_SLV_8; signal TX_StmMux_DestIPv4Address_Data : T_SLV_8; signal TX_StmMux_Length : T_SLV_16; signal TX_StmMux_Protocol : T_SLV_8; - signal IPv4_TX_Ack : STD_LOGIC; - signal IPv4_TX_Meta_rst : STD_LOGIC; - signal IPv4_TX_Meta_SrcIPv4Address_nxt : STD_LOGIC; - signal IPv4_TX_Meta_DestIPv4Address_nxt : STD_LOGIC; + signal IPv4_TX_Ack : std_logic; + signal IPv4_TX_Meta_rst : std_logic; + signal IPv4_TX_Meta_SrcIPv4Address_nxt : std_logic; + signal IPv4_TX_Meta_DestIPv4Address_nxt : std_logic; - signal IPv4_RX_Valid : STD_LOGIC; + signal IPv4_RX_Valid : std_logic; signal IPv4_RX_Data : T_SLV_8; - signal IPv4_RX_SOF : STD_LOGIC; - signal IPv4_RX_EOF : STD_LOGIC; + signal IPv4_RX_SOF : std_logic; + signal IPv4_RX_EOF : std_logic; signal IPv4_RX_Meta_SrcMACAddress_Data : T_SLV_8; signal IPv4_RX_Meta_DestMACAddress_Data : T_SLV_8; @@ -171,21 +170,21 @@ architecture rtl of ipv4_Wrapper is signal IPv4_RX_Meta_Length : T_SLV_16; signal IPv4_RX_Meta_Protocol : T_SLV_8; - constant STMDEMUX_META_RST_BIT : NATURAL := 0; - constant STMDEMUX_META_MACSRC_NXT_BIT : NATURAL := 1; - constant STMDEMUX_META_MACDEST_NXT_BIT : NATURAL := 2; - constant STMDEMUX_META_IPV4SRC_NXT_BIT : NATURAL := 3; - constant STMDEMUX_META_IPV4DEST_NXT_BIT : NATURAL := 4; - - constant STMDEMUX_META_STREAMID_SRCMAC : NATURAL := 0; - constant STMDEMUX_META_STREAMID_DESTMAC : NATURAL := 1; - constant STMDEMUX_META_STREAMID_ETHTYPE : NATURAL := 2; - constant STMDEMUX_META_STREAMID_SRCIP : NATURAL := 3; - constant STMDEMUX_META_STREAMID_DESTIP : NATURAL := 4; - constant STMDEMUX_META_STREAMID_LENGTH : NATURAL := 5; - constant STMDEMUX_META_STREAMID_PROTO : NATURAL := 6; - - constant STMDEMUX_DATA_BITS : NATURAL := 8; -- + constant STMDEMUX_META_RST_BIT : natural := 0; + constant STMDEMUX_META_MACSRC_NXT_BIT : natural := 1; + constant STMDEMUX_META_MACDEST_NXT_BIT : natural := 2; + constant STMDEMUX_META_IPV4SRC_NXT_BIT : natural := 3; + constant STMDEMUX_META_IPV4DEST_NXT_BIT : natural := 4; + + constant STMDEMUX_META_STREAMID_SRCMAC : natural := 0; + constant STMDEMUX_META_STREAMID_DESTMAC : natural := 1; + constant STMDEMUX_META_STREAMID_ETHTYPE : natural := 2; + constant STMDEMUX_META_STREAMID_SRCIP : natural := 3; + constant STMDEMUX_META_STREAMID_DESTIP : natural := 4; + constant STMDEMUX_META_STREAMID_LENGTH : natural := 5; + constant STMDEMUX_META_STREAMID_PROTO : natural := 6; + + constant STMDEMUX_DATA_BITS : natural := 8; -- constant STMDEMUX_META_BITS : T_POSVEC := ( STMDEMUX_META_STREAMID_SRCMAC => 8, STMDEMUX_META_STREAMID_DESTMAC => 8, @@ -195,31 +194,31 @@ architecture rtl of ipv4_Wrapper is STMDEMUX_META_STREAMID_LENGTH => 16, STMDEMUX_META_STREAMID_PROTO => 8 ); - constant STMDEMUX_META_REV_BITS : NATURAL := 5; -- sum over all control bits (rst, nxt, nxt, nxt, nxt) + constant STMDEMUX_META_REV_BITS : natural := 5; -- sum over all control bits (rst, nxt, nxt, nxt, nxt) - signal RX_StmDeMux_Ack : STD_LOGIC; - signal RX_StmDeMux_Meta_rst : STD_LOGIC; - signal RX_StmDeMux_Meta_SrcMACAddress_nxt : STD_LOGIC; - signal RX_StmDeMux_Meta_DestMACAddress_nxt : STD_LOGIC; - signal RX_StmDeMux_Meta_SrcIPv4Address_nxt : STD_LOGIC; - signal RX_StmDeMux_Meta_DestIPv4Address_nxt : STD_LOGIC; + signal RX_StmDeMux_Ack : std_logic; + signal RX_StmDeMux_Meta_rst : std_logic; + signal RX_StmDeMux_Meta_SrcMACAddress_nxt : std_logic; + signal RX_StmDeMux_Meta_DestMACAddress_nxt : std_logic; + signal RX_StmDeMux_Meta_SrcIPv4Address_nxt : std_logic; + signal RX_StmDeMux_Meta_DestIPv4Address_nxt : std_logic; - signal RX_StmDeMux_MetaIn : STD_LOGIC_VECTOR(isum(STMDEMUX_META_BITS) - 1 downto 0); - signal RX_StmDeMux_MetaIn_rev : STD_LOGIC_VECTOR(STMDEMUX_META_REV_BITS - 1 downto 0); + signal RX_StmDeMux_MetaIn : std_logic_vector(isum(STMDEMUX_META_BITS) - 1 downto 0); + signal RX_StmDeMux_MetaIn_rev : std_logic_vector(STMDEMUX_META_REV_BITS - 1 downto 0); signal RX_StmDeMux_Data : T_SLM(IPV4_SWITCH_PORTS - 1 downto 0, STMDEMUX_DATA_BITS - 1 downto 0) := (others => (others => 'Z')); -- necessary default assignment 'Z' to get correct simulation results (iSIM, vSIM, ghdl/gtkwave) signal RX_StmDeMux_MetaOut : T_SLM(IPV4_SWITCH_PORTS - 1 downto 0, isum(STMDEMUX_META_BITS) - 1 downto 0) := (others => (others => 'Z')); -- necessary default assignment 'Z' to get correct simulation results (iSIM, vSIM, ghdl/gtkwave) signal RX_StmDeMux_MetaOut_rev : T_SLM(IPV4_SWITCH_PORTS - 1 downto 0, STMDEMUX_META_REV_BITS - 1 downto 0) := (others => (others => 'Z')); -- necessary default assignment 'Z' to get correct simulation results (iSIM, vSIM, ghdl/gtkwave) - signal StmDeMux_Control : STD_LOGIC_VECTOR(IPV4_SWITCH_PORTS - 1 downto 0); + signal StmDeMux_Control : std_logic_vector(IPV4_SWITCH_PORTS - 1 downto 0); begin --- ============================================================================================================================================================ +-- ============================================================================= -- TX Path --- ============================================================================================================================================================ +-- ============================================================================= genTXStmBuf : for i in 0 to IPV4_SWITCH_PORTS - 1 generate - constant TXSTMBUF_META_STREAMID_SRCADR : NATURAL := 0; - constant TXSTMBUF_META_STREAMID_DESTADR : NATURAL := 1; - constant TXSTMBUF_META_STREAMID_LENGTH : NATURAL := 2; + constant TXSTMBUF_META_STREAMID_SRCADR : natural := 0; + constant TXSTMBUF_META_STREAMID_DESTADR : natural := 1; + constant TXSTMBUF_META_STREAMID_LENGTH : natural := 2; constant TXSTMBUF_META_BITS : T_POSVEC := ( TXSTMBUF_META_STREAMID_SRCADR => 8, @@ -235,19 +234,19 @@ begin signal StmBuf_DataOut : T_SLV_8; -- signal Meta_rst : STD_LOGIC; - signal StmBuf_MetaIn_nxt : STD_LOGIC_VECTOR(TXSTMBUF_META_BITS'length - 1 downto 0); - signal StmBuf_MetaIn_Data : STD_LOGIC_VECTOR(isum(TXSTMBUF_META_BITS) - 1 downto 0); + signal StmBuf_MetaIn_nxt : std_logic_vector(TXSTMBUF_META_BITS'length - 1 downto 0); + signal StmBuf_MetaIn_Data : std_logic_vector(isum(TXSTMBUF_META_BITS) - 1 downto 0); - signal StmBuf_Meta_rst : STD_LOGIC; - signal StmBuf_MetaOut_nxt : STD_LOGIC_VECTOR(TXSTMBUF_META_BITS'length - 1 downto 0); - signal StmBuf_MetaOut_Data : STD_LOGIC_VECTOR(isum(TXSTMBUF_META_BITS) - 1 downto 0); + signal StmBuf_Meta_rst : std_logic; + signal StmBuf_MetaOut_nxt : std_logic_vector(TXSTMBUF_META_BITS'length - 1 downto 0); + signal StmBuf_MetaOut_Data : std_logic_vector(isum(TXSTMBUF_META_BITS) - 1 downto 0); - signal StmBuf_Meta_SrcIPv4Address_Data : STD_LOGIC_VECTOR(TX_StmMux_SrcIPv4Address_Data'range); - signal StmBuf_Meta_DestIPv4Address_Data : STD_LOGIC_VECTOR(TX_StmMux_DestIPv4Address_Data'range); - signal StmBuf_Meta_Length : STD_LOGIC_VECTOR(TX_StmMux_Length'range); - signal StmBuf_Meta_Protocol : STD_LOGIC_VECTOR(TX_StmMux_Protocol'range); + signal StmBuf_Meta_SrcIPv4Address_Data : std_logic_vector(TX_StmMux_SrcIPv4Address_Data'range); + signal StmBuf_Meta_DestIPv4Address_Data : std_logic_vector(TX_StmMux_DestIPv4Address_Data'range); + signal StmBuf_Meta_Length : std_logic_vector(TX_StmMux_Length'range); + signal StmBuf_Meta_Protocol : std_logic_vector(TX_StmMux_Protocol'range); - signal StmMux_MetaIn_Data : STD_LOGIC_VECTOR(isum(TXSTMMUX_META_BITS) - 1 downto 0); + signal StmMux_MetaIn_Data : std_logic_vector(isum(TXSTMMUX_META_BITS) - 1 downto 0); begin StmBuf_MetaIn_Data(high(TXSTMBUF_META_BITS, TXSTMBUF_META_STREAMID_SRCADR) downto low(TXSTMBUF_META_BITS, TXSTMBUF_META_STREAMID_SRCADR)) <= TX_Meta_SrcIPv4Address_Data(i); @@ -389,9 +388,9 @@ begin Out_Meta_DestMACAddress_Data => MAC_TX_Meta_DestMACAddress_Data ); --- ============================================================================================================================================================ +-- ============================================================================= -- RX Path --- ============================================================================================================================================================ +-- ============================================================================= IPv4_RX : entity PoC.ipv4_RX generic map ( DEBUG => DEBUG diff --git a/src/net/ipv6/ipv6_FrameLoopback.vhdl b/src/net/ipv6/ipv6_FrameLoopback.vhdl index 51f2b54f..9de601dd 100644 --- a/src/net/ipv6/ipv6_FrameLoopback.vhdl +++ b/src/net/ipv6/ipv6_FrameLoopback.vhdl @@ -1,18 +1,17 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: TODO +-- Entity: TODO -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -27,7 +26,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -42,42 +41,42 @@ use PoC.net.all; entity ipv6_FrameLoopback is generic ( - MAX_FRAMES : POSITIVE := 4 + MAX_FRAMES : positive := 4 ); port ( - Clock : in STD_LOGIC; - Reset : in STD_LOGIC; + Clock : in std_logic; + Reset : in std_logic; -- IN port - In_Valid : in STD_LOGIC; + In_Valid : in std_logic; In_Data : in T_SLV_8; - In_SOF : in STD_LOGIC; - In_EOF : in STD_LOGIC; - In_Ack : out STD_LOGIC; - In_Meta_rst : out STD_LOGIC; - In_Meta_SrcIPv6Address_nxt : out STD_LOGIC; + In_SOF : in std_logic; + In_EOF : in std_logic; + In_Ack : out std_logic; + In_Meta_rst : out std_logic; + In_Meta_SrcIPv6Address_nxt : out std_logic; In_Meta_SrcIPv6Address_Data : in T_SLV_8; - In_Meta_DestIPv6Address_nxt : out STD_LOGIC; + In_Meta_DestIPv6Address_nxt : out std_logic; In_Meta_DestIPv6Address_Data : in T_SLV_8; In_Meta_Length : in T_SLV_16; -- OUT port - Out_Valid : out STD_LOGIC; + Out_Valid : out std_logic; Out_Data : out T_SLV_8; - Out_SOF : out STD_LOGIC; - Out_EOF : out STD_LOGIC; - Out_Ack : in STD_LOGIC; - Out_Meta_rst : in STD_LOGIC; - Out_Meta_SrcIPv6Address_nxt : in STD_LOGIC; + Out_SOF : out std_logic; + Out_EOF : out std_logic; + Out_Ack : in std_logic; + Out_Meta_rst : in std_logic; + Out_Meta_SrcIPv6Address_nxt : in std_logic; Out_Meta_SrcIPv6Address_Data : out T_SLV_8; - Out_Meta_DestIPv6Address_nxt : in STD_LOGIC; + Out_Meta_DestIPv6Address_nxt : in std_logic; Out_Meta_DestIPv6Address_Data : out T_SLV_8; Out_Meta_Length : out T_SLV_16 ); end entity; architecture rtl of ipv6_FrameLoopback is - constant META_STREAMID_SRCADDR : NATURAL := 0; - constant META_STREAMID_DESTADDR : NATURAL := 1; - constant META_STREAMID_LENGTH : NATURAL := 2; + constant META_STREAMID_SRCADDR : natural := 0; + constant META_STREAMID_DESTADDR : natural := 1; + constant META_STREAMID_LENGTH : natural := 2; constant META_BITS : T_POSVEC := ( META_STREAMID_SRCADDR => 8, @@ -91,10 +90,10 @@ architecture rtl of ipv6_FrameLoopback is META_STREAMID_LENGTH => 1 ); - signal StmBuf_MetaIn_nxt : STD_LOGIC_VECTOR(META_BITS'length - 1 downto 0); - signal StmBuf_MetaIn_Data : STD_LOGIC_VECTOR(isum(META_BITS) - 1 downto 0); - signal StmBuf_MetaOut_nxt : STD_LOGIC_VECTOR(META_BITS'length - 1 downto 0); - signal StmBuf_MetaOut_Data : STD_LOGIC_VECTOR(isum(META_BITS) - 1 downto 0); + signal StmBuf_MetaIn_nxt : std_logic_vector(META_BITS'length - 1 downto 0); + signal StmBuf_MetaIn_Data : std_logic_vector(isum(META_BITS) - 1 downto 0); + signal StmBuf_MetaOut_nxt : std_logic_vector(META_BITS'length - 1 downto 0); + signal StmBuf_MetaOut_Data : std_logic_vector(isum(META_BITS) - 1 downto 0); begin diff --git a/src/net/ipv6/ipv6_RX.vhdl b/src/net/ipv6/ipv6_RX.vhdl index 16844b4d..7f871366 100644 --- a/src/net/ipv6/ipv6_RX.vhdl +++ b/src/net/ipv6/ipv6_RX.vhdl @@ -1,18 +1,17 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: TODO +-- Entity: TODO -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -27,7 +26,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -42,40 +41,40 @@ use PoC.net.all; entity ipv6_RX is generic ( - DEBUG : BOOLEAN := FALSE + DEBUG : boolean := FALSE ); port ( - Clock : in STD_LOGIC; -- - Reset : in STD_LOGIC; -- + Clock : in std_logic; -- + Reset : in std_logic; -- -- STATUS port - Error : out STD_LOGIC; + Error : out std_logic; -- IN port - In_Valid : in STD_LOGIC; + In_Valid : in std_logic; In_Data : in T_SLV_8; - In_SOF : in STD_LOGIC; - In_EOF : in STD_LOGIC; - In_Ack : out STD_LOGIC; - In_Meta_rst : out STD_LOGIC; - In_Meta_SrcMACAddress_nxt : out STD_LOGIC; + In_SOF : in std_logic; + In_EOF : in std_logic; + In_Ack : out std_logic; + In_Meta_rst : out std_logic; + In_Meta_SrcMACAddress_nxt : out std_logic; In_Meta_SrcMACAddress_Data : in T_SLV_8; - In_Meta_DestMACAddress_nxt : out STD_LOGIC; + In_Meta_DestMACAddress_nxt : out std_logic; In_Meta_DestMACAddress_Data : in T_SLV_8; In_Meta_EthType : in T_SLV_16; -- OUT port - Out_Valid : out STD_LOGIC; + Out_Valid : out std_logic; Out_Data : out T_SLV_8; - Out_SOF : out STD_LOGIC; - Out_EOF : out STD_LOGIC; - Out_Ack : in STD_LOGIC; - Out_Meta_rst : in STD_LOGIC; - Out_Meta_SrcMACAddress_nxt : in STD_LOGIC; + Out_SOF : out std_logic; + Out_EOF : out std_logic; + Out_Ack : in std_logic; + Out_Meta_rst : in std_logic; + Out_Meta_SrcMACAddress_nxt : in std_logic; Out_Meta_SrcMACAddress_Data : out T_SLV_8; - Out_Meta_DestMACAddress_nxt : in STD_LOGIC; + Out_Meta_DestMACAddress_nxt : in std_logic; Out_Meta_DestMACAddress_Data : out T_SLV_8; Out_Meta_EthType : out T_SLV_16; - Out_Meta_SrcIPv6Address_nxt : in STD_LOGIC; + Out_Meta_SrcIPv6Address_nxt : in std_logic; Out_Meta_SrcIPv6Address_Data : out T_SLV_8; - Out_Meta_DestIPv6Address_nxt : in STD_LOGIC; + Out_Meta_DestIPv6Address_nxt : in std_logic; Out_Meta_DestIPv6Address_Data : out T_SLV_8; Out_Meta_TrafficClass : out T_SLV_8; Out_Meta_FlowLabel : out T_SLV_24; --STD_LOGIC_VECTOR(19 downto 0); @@ -86,10 +85,10 @@ end entity; architecture rtl of ipv6_RX is - attribute FSM_ENCODING : STRING; + attribute FSM_ENCODING : string; - subtype T_BYTEINDEX is NATURAL range 0 to 1; - subtype T_IPV6_BYTEINDEX is NATURAL range 0 to 15; + subtype T_BYTEINDEX is natural range 0 to 1; + subtype T_IPV6_BYTEINDEX is natural range 0 to 15; type T_STATE is ( ST_IDLE, @@ -107,56 +106,56 @@ architecture rtl of ipv6_RX is signal State : T_STATE := ST_IDLE; signal NextState : T_STATE; - attribute FSM_ENCODING of State : signal IS ite(DEBUG, "gray", ite((VENDOR = VENDOR_XILINX), "auto", "default")); + attribute FSM_ENCODING of State : signal is ite(DEBUG, "gray", ite((VENDOR = VENDOR_XILINX), "auto", "default")); - signal In_Ack_i : STD_LOGIC; - signal Is_DataFlow : STD_LOGIC; - signal Is_SOF : STD_LOGIC; - signal Is_EOF : STD_LOGIC; + signal In_Ack_i : std_logic; + signal Is_DataFlow : std_logic; + signal Is_SOF : std_logic; + signal Is_EOF : std_logic; - signal Out_Valid_i : STD_LOGIC; - signal Out_SOF_i : STD_LOGIC; - signal Out_EOF_i : STD_LOGIC; + signal Out_Valid_i : std_logic; + signal Out_SOF_i : std_logic; + signal Out_EOF_i : std_logic; - subtype T_IP_BYTEINDEX is NATURAL range 0 to 15; + subtype T_IP_BYTEINDEX is natural range 0 to 15; signal IP_ByteIndex : T_IP_BYTEINDEX; - signal Register_rst : STD_LOGIC; + signal Register_rst : std_logic; -- IPv6 basic header fields - signal TrafficClass_en0 : STD_LOGIC; - signal TrafficClass_en1 : STD_LOGIC; - signal FlowLabel_en0 : STD_LOGIC; - signal FlowLabel_en1 : STD_LOGIC; - signal FlowLabel_en2 : STD_LOGIC; - signal Length_en0 : STD_LOGIC; - signal Length_en1 : STD_LOGIC; - signal NextHeader_en : STD_LOGIC; - signal HopLimit_en : STD_LOGIC; - signal SourceIPv6Address_en : STD_LOGIC; - signal DestIPv6Address_en : STD_LOGIC; + signal TrafficClass_en0 : std_logic; + signal TrafficClass_en1 : std_logic; + signal FlowLabel_en0 : std_logic; + signal FlowLabel_en1 : std_logic; + signal FlowLabel_en2 : std_logic; + signal Length_en0 : std_logic; + signal Length_en1 : std_logic; + signal NextHeader_en : std_logic; + signal HopLimit_en : std_logic; + signal SourceIPv6Address_en : std_logic; + signal DestIPv6Address_en : std_logic; signal TrafficClass_d : T_SLV_8 := (others => '0'); - signal FlowLabel_d : STD_LOGIC_VECTOR(19 downto 0) := (others => '0'); + signal FlowLabel_d : std_logic_vector(19 downto 0) := (others => '0'); signal Length_d : T_SLV_16 := (others => '0'); signal NextHeader_d : T_SLV_8 := (others => '0'); signal HopLimit_d : T_SLV_8 := (others => '0'); signal SourceIPv6Address_d : T_NET_IPV6_ADDRESS := (others => (others => '0')); signal DestIPv6Address_d : T_NET_IPV6_ADDRESS := (others => (others => '0')); - constant IPV6_ADDRESS_LENGTH : POSITIVE := 16; -- IPv6 -> 16 bytes - constant IPV6_ADDRESS_READER_BITS : POSITIVE := log2ceilnz(IPV6_ADDRESS_LENGTH); + constant IPV6_ADDRESS_LENGTH : positive := 16; -- IPv6 -> 16 bytes + constant IPV6_ADDRESS_READER_BITS : positive := log2ceilnz(IPV6_ADDRESS_LENGTH); - signal IPv6SeqCounter_rst : STD_LOGIC; - signal IPv6SeqCounter_en : STD_LOGIC; - signal IPv6SeqCounter_us : UNSIGNED(IPV6_ADDRESS_READER_BITS - 1 downto 0) := to_unsigned(IPV6_ADDRESS_LENGTH - 1, IPV6_ADDRESS_READER_BITS); + signal IPv6SeqCounter_rst : std_logic; + signal IPv6SeqCounter_en : std_logic; + signal IPv6SeqCounter_us : unsigned(IPV6_ADDRESS_READER_BITS - 1 downto 0) := to_unsigned(IPV6_ADDRESS_LENGTH - 1, IPV6_ADDRESS_READER_BITS); - signal SrcIPv6Address_Reader_rst : STD_LOGIC; - signal SrcIPv6Address_Reader_en : STD_LOGIC; - signal SrcIPv6Address_Reader_us : UNSIGNED(IPV6_ADDRESS_READER_BITS - 1 downto 0) := to_unsigned(IPV6_ADDRESS_LENGTH - 1, IPV6_ADDRESS_READER_BITS); - signal DestIPv6Address_Reader_rst : STD_LOGIC; - signal DestIPv6Address_Reader_en : STD_LOGIC; - signal DestIPv6Address_Reader_us : UNSIGNED(IPV6_ADDRESS_READER_BITS - 1 downto 0) := to_unsigned(IPV6_ADDRESS_LENGTH - 1, IPV6_ADDRESS_READER_BITS); + signal SrcIPv6Address_Reader_rst : std_logic; + signal SrcIPv6Address_Reader_en : std_logic; + signal SrcIPv6Address_Reader_us : unsigned(IPV6_ADDRESS_READER_BITS - 1 downto 0) := to_unsigned(IPV6_ADDRESS_LENGTH - 1, IPV6_ADDRESS_READER_BITS); + signal DestIPv6Address_Reader_rst : std_logic; + signal DestIPv6Address_Reader_en : std_logic; + signal DestIPv6Address_Reader_us : unsigned(IPV6_ADDRESS_READER_BITS - 1 downto 0) := to_unsigned(IPV6_ADDRESS_LENGTH - 1, IPV6_ADDRESS_READER_BITS); -- ExtensionHeader: Fragmentation -- signal FragmentOffset_en0 : STD_LOGIC; @@ -393,7 +392,7 @@ begin process(Clock) begin if rising_edge(Clock) then - if ((Reset OR Register_rst) = '1') then + if ((Reset or Register_rst) = '1') then TrafficClass_d <= (others => '0'); FlowLabel_d <= (others => '0'); Length_d <= (others => '0'); @@ -446,7 +445,7 @@ begin process(Clock) begin if rising_edge(Clock) then - if ((Reset OR IPv6SeqCounter_rst) = '1') then + if ((Reset or IPv6SeqCounter_rst) = '1') then IPv6SeqCounter_us <= to_unsigned(IPV6_ADDRESS_LENGTH - 1, IPV6_ADDRESS_READER_BITS); elsif (IPv6SeqCounter_en = '1') then IPv6SeqCounter_us <= IPv6SeqCounter_us - 1; @@ -462,7 +461,7 @@ begin process(Clock) begin if rising_edge(Clock) then - if ((Reset OR SrcIPv6Address_Reader_rst) = '1') then + if ((Reset or SrcIPv6Address_Reader_rst) = '1') then SrcIPv6Address_Reader_us <= to_unsigned(IPV6_ADDRESS_LENGTH - 1, IPV6_ADDRESS_READER_BITS); elsif (SrcIPv6Address_Reader_en = '1') then SrcIPv6Address_Reader_us <= SrcIPv6Address_Reader_us - 1; @@ -473,7 +472,7 @@ begin process(Clock) begin if rising_edge(Clock) then - if ((Reset OR DestIPv6Address_Reader_rst) = '1') then + if ((Reset or DestIPv6Address_Reader_rst) = '1') then DestIPv6Address_Reader_us <= to_unsigned(IPV6_ADDRESS_LENGTH - 1, IPV6_ADDRESS_READER_BITS); elsif (DestIPv6Address_Reader_en = '1') then DestIPv6Address_Reader_us <= DestIPv6Address_Reader_us - 1; diff --git a/src/net/ipv6/ipv6_TX.vhdl b/src/net/ipv6/ipv6_TX.vhdl index 6b86b2f1..982837e5 100644 --- a/src/net/ipv6/ipv6_TX.vhdl +++ b/src/net/ipv6/ipv6_TX.vhdl @@ -1,18 +1,17 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: TODO +-- Entity: TODO -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -27,7 +26,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -42,51 +41,51 @@ use PoC.net.all; entity ipv6_TX is generic ( - DEBUG : BOOLEAN := FALSE + DEBUG : boolean := FALSE ); port ( - Clock : in STD_LOGIC; -- - Reset : in STD_LOGIC; -- + Clock : in std_logic; -- + Reset : in std_logic; -- -- IN port - In_Valid : in STD_LOGIC; + In_Valid : in std_logic; In_Data : in T_SLV_8; - In_SOF : in STD_LOGIC; - In_EOF : in STD_LOGIC; - In_Ack : out STD_LOGIC; - In_Meta_rst : out STD_LOGIC; - In_Meta_SrcIPv6Address_nxt : out STD_LOGIC; + In_SOF : in std_logic; + In_EOF : in std_logic; + In_Ack : out std_logic; + In_Meta_rst : out std_logic; + In_Meta_SrcIPv6Address_nxt : out std_logic; In_Meta_SrcIPv6Address_Data : in T_SLV_8; - In_Meta_DestIPv6Address_nxt : out STD_LOGIC; + In_Meta_DestIPv6Address_nxt : out std_logic; In_Meta_DestIPv6Address_Data : in T_SLV_8; In_Meta_TrafficClass : in T_SLV_8; In_Meta_FlowLabel : in T_SLV_24; --STD_LOGIC_VECTOR(19 downto 0); In_Meta_Length : in T_SLV_16; In_Meta_NextHeader : in T_SLV_8; -- to NDP layer - NDP_NextHop_Query : out STD_LOGIC; - NDP_NextHop_IPv6Address_rst : in STD_LOGIC; - NDP_NextHop_IPv6Address_nxt : in STD_LOGIC; + NDP_NextHop_Query : out std_logic; + NDP_NextHop_IPv6Address_rst : in std_logic; + NDP_NextHop_IPv6Address_nxt : in std_logic; NDP_NextHop_IPv6Address_Data : out T_SLV_8; -- from NDP layer - NDP_NextHop_Valid : in STD_LOGIC; - NDP_NextHop_MACAddress_rst : out STD_LOGIC; - NDP_NextHop_MACAddress_nxt : out STD_LOGIC; + NDP_NextHop_Valid : in std_logic; + NDP_NextHop_MACAddress_rst : out std_logic; + NDP_NextHop_MACAddress_nxt : out std_logic; NDP_NextHop_MACAddress_Data : in T_SLV_8; -- OUT port - Out_Valid : out STD_LOGIC; + Out_Valid : out std_logic; Out_Data : out T_SLV_8; - Out_SOF : out STD_LOGIC; - Out_EOF : out STD_LOGIC; - Out_Ack : in STD_LOGIC; - Out_Meta_rst : in STD_LOGIC; - Out_Meta_DestMACAddress_nxt : in STD_LOGIC; + Out_SOF : out std_logic; + Out_EOF : out std_logic; + Out_Ack : in std_logic; + Out_Meta_rst : in std_logic; + Out_Meta_DestMACAddress_nxt : in std_logic; Out_Meta_DestMACAddress_Data : out T_SLV_8 ); end entity; architecture rtl of ipv6_TX is - attribute FSM_ENCODING : STRING; + attribute FSM_ENCODING : string; type T_STATE is ( ST_IDLE, @@ -105,13 +104,13 @@ architecture rtl of ipv6_TX is signal State : T_STATE := ST_IDLE; signal NextState : T_STATE; - attribute FSM_ENCODING of State : signal IS ite(DEBUG, "gray", ite((VENDOR = VENDOR_XILINX), "auto", "default")); + attribute FSM_ENCODING of State : signal is ite(DEBUG, "gray", ite((VENDOR = VENDOR_XILINX), "auto", "default")); - signal In_Ack_i : STD_LOGIC; + signal In_Ack_i : std_logic; - signal IPv6SeqCounter_rst : STD_LOGIC; - signal IPv6SeqCounter_en : STD_LOGIC; - signal IPv6SeqCounter_us : UNSIGNED(3 downto 0) := (others => '0'); + signal IPv6SeqCounter_rst : std_logic; + signal IPv6SeqCounter_en : std_logic; + signal IPv6SeqCounter_us : unsigned(3 downto 0) := (others => '0'); begin @@ -320,7 +319,7 @@ begin process(Clock) begin if rising_edge(Clock) then - if ((Reset OR IPv6SeqCounter_rst) = '1') then + if ((Reset or IPv6SeqCounter_rst) = '1') then IPv6SeqCounter_us <= (others => '0'); elsif (IPv6SeqCounter_en = '1') then IPv6SeqCounter_us <= IPv6SeqCounter_us + 1; @@ -330,4 +329,4 @@ begin In_Ack <= In_Ack_i; -end architecture; \ No newline at end of file +end architecture; diff --git a/src/net/ipv6/ipv6_Wrapper.vhdl b/src/net/ipv6/ipv6_Wrapper.vhdl index 05453c43..fd52f561 100644 --- a/src/net/ipv6/ipv6_Wrapper.vhdl +++ b/src/net/ipv6/ipv6_Wrapper.vhdl @@ -1,18 +1,17 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: TODO +-- Entity: TODO -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -27,7 +26,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -42,72 +41,72 @@ use PoC.net.all; entity ipv6_Wrapper is generic ( - DEBUG : BOOLEAN := FALSE; + DEBUG : boolean := FALSE; PACKET_TYPES : T_NET_IPV6_NEXT_HEADER_VECTOR := (0 => x"00") ); port ( - Clock : in STD_LOGIC; - Reset : in STD_LOGIC; + Clock : in std_logic; + Reset : in std_logic; -- to MAC layer - MAC_TX_Valid : out STD_LOGIC; + MAC_TX_Valid : out std_logic; MAC_TX_Data : out T_SLV_8; - MAC_TX_SOF : out STD_LOGIC; - MAC_TX_EOF : out STD_LOGIC; - MAC_TX_Ack : in STD_LOGIC; - MAC_TX_Meta_rst : in STD_LOGIC; - MAC_TX_Meta_DestMACAddress_nxt : in STD_LOGIC; + MAC_TX_SOF : out std_logic; + MAC_TX_EOF : out std_logic; + MAC_TX_Ack : in std_logic; + MAC_TX_Meta_rst : in std_logic; + MAC_TX_Meta_DestMACAddress_nxt : in std_logic; MAC_TX_Meta_DestMACAddress_Data : out T_SLV_8; -- from MAC layer - MAC_RX_Valid : in STD_LOGIC; + MAC_RX_Valid : in std_logic; MAC_RX_Data : in T_SLV_8; - MAC_RX_SOF : in STD_LOGIC; - MAC_RX_EOF : in STD_LOGIC; - MAC_RX_Ack : out STD_LOGIC; - MAC_RX_Meta_rst : out STD_LOGIC; - MAC_RX_Meta_SrcMACAddress_nxt : out STD_LOGIC; + MAC_RX_SOF : in std_logic; + MAC_RX_EOF : in std_logic; + MAC_RX_Ack : out std_logic; + MAC_RX_Meta_rst : out std_logic; + MAC_RX_Meta_SrcMACAddress_nxt : out std_logic; MAC_RX_Meta_SrcMACAddress_Data : in T_SLV_8; - MAC_RX_Meta_DestMACAddress_nxt : out STD_LOGIC; + MAC_RX_Meta_DestMACAddress_nxt : out std_logic; MAC_RX_Meta_DestMACAddress_Data : in T_SLV_8; MAC_RX_Meta_EthType : in T_SLV_16; -- to NDP layer - NDP_NextHop_Query : out STD_LOGIC; - NDP_NextHop_IPv6Address_rst : in STD_LOGIC; - NDP_NextHop_IPv6Address_nxt : in STD_LOGIC; + NDP_NextHop_Query : out std_logic; + NDP_NextHop_IPv6Address_rst : in std_logic; + NDP_NextHop_IPv6Address_nxt : in std_logic; NDP_NextHop_IPv6Address_Data : out T_SLV_8; -- from NDP layer - NDP_NextHop_Valid : in STD_LOGIC; - NDP_NextHop_MACAddress_rst : out STD_LOGIC; - NDP_NextHop_MACAddress_nxt : out STD_LOGIC; + NDP_NextHop_Valid : in std_logic; + NDP_NextHop_MACAddress_rst : out std_logic; + NDP_NextHop_MACAddress_nxt : out std_logic; NDP_NextHop_MACAddress_Data : in T_SLV_8; -- from upper layer - TX_Valid : in STD_LOGIC_VECTOR(PACKET_TYPES'length - 1 downto 0); + TX_Valid : in std_logic_vector(PACKET_TYPES'length - 1 downto 0); TX_Data : in T_SLVV_8(PACKET_TYPES'length - 1 downto 0); - TX_SOF : in STD_LOGIC_VECTOR(PACKET_TYPES'length - 1 downto 0); - TX_EOF : in STD_LOGIC_VECTOR(PACKET_TYPES'length - 1 downto 0); - TX_Ack : out STD_LOGIC_VECTOR(PACKET_TYPES'length - 1 downto 0); - TX_Meta_rst : out STD_LOGIC_VECTOR(PACKET_TYPES'length - 1 downto 0); - TX_Meta_SrcIPv6Address_nxt : out STD_LOGIC_VECTOR(PACKET_TYPES'length - 1 downto 0); + TX_SOF : in std_logic_vector(PACKET_TYPES'length - 1 downto 0); + TX_EOF : in std_logic_vector(PACKET_TYPES'length - 1 downto 0); + TX_Ack : out std_logic_vector(PACKET_TYPES'length - 1 downto 0); + TX_Meta_rst : out std_logic_vector(PACKET_TYPES'length - 1 downto 0); + TX_Meta_SrcIPv6Address_nxt : out std_logic_vector(PACKET_TYPES'length - 1 downto 0); TX_Meta_SrcIPv6Address_Data : in T_SLVV_8(PACKET_TYPES'length - 1 downto 0); - TX_Meta_DestIPv6Address_nxt : out STD_LOGIC_VECTOR(PACKET_TYPES'length - 1 downto 0); + TX_Meta_DestIPv6Address_nxt : out std_logic_vector(PACKET_TYPES'length - 1 downto 0); TX_Meta_DestIPv6Address_Data : in T_SLVV_8(PACKET_TYPES'length - 1 downto 0); TX_Meta_TrafficClass : in T_SLVV_8(PACKET_TYPES'length - 1 downto 0); TX_Meta_FlowLabel : in T_SLVV_24(PACKET_TYPES'length - 1 downto 0); TX_Meta_Length : in T_SLVV_16(PACKET_TYPES'length - 1 downto 0); -- to upper layer - RX_Valid : out STD_LOGIC_VECTOR(PACKET_TYPES'length - 1 downto 0); + RX_Valid : out std_logic_vector(PACKET_TYPES'length - 1 downto 0); RX_Data : out T_SLVV_8(PACKET_TYPES'length - 1 downto 0); - RX_SOF : out STD_LOGIC_VECTOR(PACKET_TYPES'length - 1 downto 0); - RX_EOF : out STD_LOGIC_VECTOR(PACKET_TYPES'length - 1 downto 0); - RX_Ack : in STD_LOGIC_VECTOR(PACKET_TYPES'length - 1 downto 0); - RX_Meta_rst : in STD_LOGIC_VECTOR(PACKET_TYPES'length - 1 downto 0); - RX_Meta_SrcMACAddress_nxt : in STD_LOGIC_VECTOR(PACKET_TYPES'length - 1 downto 0); + RX_SOF : out std_logic_vector(PACKET_TYPES'length - 1 downto 0); + RX_EOF : out std_logic_vector(PACKET_TYPES'length - 1 downto 0); + RX_Ack : in std_logic_vector(PACKET_TYPES'length - 1 downto 0); + RX_Meta_rst : in std_logic_vector(PACKET_TYPES'length - 1 downto 0); + RX_Meta_SrcMACAddress_nxt : in std_logic_vector(PACKET_TYPES'length - 1 downto 0); RX_Meta_SrcMACAddress_Data : out T_SLVV_8(PACKET_TYPES'length - 1 downto 0); - RX_Meta_DestMACAddress_nxt : in STD_LOGIC_VECTOR(PACKET_TYPES'length - 1 downto 0); + RX_Meta_DestMACAddress_nxt : in std_logic_vector(PACKET_TYPES'length - 1 downto 0); RX_Meta_DestMACAddress_Data : out T_SLVV_8(PACKET_TYPES'length - 1 downto 0); RX_Meta_EthType : out T_SLVV_16(PACKET_TYPES'length - 1 downto 0); - RX_Meta_SrcIPv6Address_nxt : in STD_LOGIC_VECTOR(PACKET_TYPES'length - 1 downto 0); + RX_Meta_SrcIPv6Address_nxt : in std_logic_vector(PACKET_TYPES'length - 1 downto 0); RX_Meta_SrcIPv6Address_Data : out T_SLVV_8(PACKET_TYPES'length - 1 downto 0); - RX_Meta_DestIPv6Address_nxt : in STD_LOGIC_VECTOR(PACKET_TYPES'length - 1 downto 0); + RX_Meta_DestIPv6Address_nxt : in std_logic_vector(PACKET_TYPES'length - 1 downto 0); RX_Meta_DestIPv6Address_Data : out T_SLVV_8(PACKET_TYPES'length - 1 downto 0); RX_Meta_TrafficClass : out T_SLVV_8(PACKET_TYPES'length - 1 downto 0); RX_Meta_FlowLabel : out T_SLVV_24(PACKET_TYPES'length - 1 downto 0); @@ -117,12 +116,12 @@ entity ipv6_Wrapper is end entity; architecture rtl of ipv6_Wrapper is - constant IPV6_SWITCH_PORTS : POSITIVE := PACKET_TYPES'length; + constant IPV6_SWITCH_PORTS : positive := PACKET_TYPES'length; - constant TXSTMMUX_META_STREAMID_SRCADR : NATURAL := 0; - constant TXSTMMUX_META_STREAMID_DESTADR : NATURAL := 1; - constant TXSTMMUX_META_STREAMID_LENGTH : NATURAL := 2; - constant TXSTMMUX_META_STREAMID_HEADER : NATURAL := 3; + constant TXSTMMUX_META_STREAMID_SRCADR : natural := 0; + constant TXSTMMUX_META_STREAMID_DESTADR : natural := 1; + constant TXSTMMUX_META_STREAMID_LENGTH : natural := 2; + constant TXSTMMUX_META_STREAMID_HEADER : natural := 3; constant TXSTMMUX_META_BITS : T_POSVEC := ( TXSTMMUX_META_STREAMID_SRCADR => 8, @@ -131,40 +130,40 @@ architecture rtl of ipv6_Wrapper is TXSTMMUX_META_STREAMID_HEADER => 8 ); - constant TXSTMMUX_META_RST_BIT : NATURAL := 0; - constant TXSTMMUX_META_SRC_NXT_BIT : NATURAL := 1; - constant TXSTMMUX_META_DEST_NXT_BIT : NATURAL := 2; + constant TXSTMMUX_META_RST_BIT : natural := 0; + constant TXSTMMUX_META_SRC_NXT_BIT : natural := 1; + constant TXSTMMUX_META_DEST_NXT_BIT : natural := 2; - constant TXSTMMUX_META_REV_BITS : NATURAL := 3; + constant TXSTMMUX_META_REV_BITS : natural := 3; - signal StmMux_In_Valid : STD_LOGIC_VECTOR(IPV6_SWITCH_PORTS - 1 downto 0); + signal StmMux_In_Valid : std_logic_vector(IPV6_SWITCH_PORTS - 1 downto 0); signal StmMux_In_Data : T_SLM(IPV6_SWITCH_PORTS - 1 downto 0, T_SLV_8'range) := (others => (others => 'Z')); -- necessary default assignment 'Z' to get correct simulation results (iSIM, vSIM, ghdl/gtkwave) signal StmMux_In_Meta : T_SLM(IPV6_SWITCH_PORTS - 1 downto 0, isum(TXSTMMUX_META_BITS) - 1 downto 0) := (others => (others => 'Z')); -- necessary default assignment 'Z' to get correct simulation results (iSIM, vSIM, ghdl/gtkwave) signal StmMux_In_Meta_rev : T_SLM(IPV6_SWITCH_PORTS - 1 downto 0, TXSTMMUX_META_REV_BITS - 1 downto 0) := (others => (others => 'Z')); -- necessary default assignment 'Z' to get correct simulation results (iSIM, vSIM, ghdl/gtkwave) - signal StmMux_In_SOF : STD_LOGIC_VECTOR(IPV6_SWITCH_PORTS - 1 downto 0); - signal StmMux_In_EOF : STD_LOGIC_VECTOR(IPV6_SWITCH_PORTS - 1 downto 0); - signal StmMux_In_Ack : STD_LOGIC_VECTOR(IPV6_SWITCH_PORTS - 1 downto 0); + signal StmMux_In_SOF : std_logic_vector(IPV6_SWITCH_PORTS - 1 downto 0); + signal StmMux_In_EOF : std_logic_vector(IPV6_SWITCH_PORTS - 1 downto 0); + signal StmMux_In_Ack : std_logic_vector(IPV6_SWITCH_PORTS - 1 downto 0); - signal TX_StmMux_Valid : STD_LOGIC; + signal TX_StmMux_Valid : std_logic; signal TX_StmMux_Data : T_SLV_8; - signal TX_StmMux_Meta : STD_LOGIC_VECTOR(isum(TXSTMMUX_META_BITS) - 1 downto 0); - signal TX_StmMux_Meta_rev : STD_LOGIC_VECTOR(TXSTMMUX_META_REV_BITS - 1 downto 0); - signal TX_StmMux_SOF : STD_LOGIC; - signal TX_StmMux_EOF : STD_LOGIC; + signal TX_StmMux_Meta : std_logic_vector(isum(TXSTMMUX_META_BITS) - 1 downto 0); + signal TX_StmMux_Meta_rev : std_logic_vector(TXSTMMUX_META_REV_BITS - 1 downto 0); + signal TX_StmMux_SOF : std_logic; + signal TX_StmMux_EOF : std_logic; signal TX_StmMux_SrcIPv6Address_Data : T_SLV_8; signal TX_StmMux_DestIPv6Address_Data : T_SLV_8; signal TX_StmMux_Length : T_SLV_16; signal TX_StmMux_NextHeader : T_SLV_8; - signal IPv6_TX_Ack : STD_LOGIC; - signal IPv6_TX_Meta_rst : STD_LOGIC; - signal IPv6_TX_Meta_SrcIPv6Address_nxt : STD_LOGIC; - signal IPv6_TX_Meta_DestIPv6Address_nxt : STD_LOGIC; + signal IPv6_TX_Ack : std_logic; + signal IPv6_TX_Meta_rst : std_logic; + signal IPv6_TX_Meta_SrcIPv6Address_nxt : std_logic; + signal IPv6_TX_Meta_DestIPv6Address_nxt : std_logic; - signal IPv6_RX_Valid : STD_LOGIC; + signal IPv6_RX_Valid : std_logic; signal IPv6_RX_Data : T_SLV_8; - signal IPv6_RX_SOF : STD_LOGIC; - signal IPv6_RX_EOF : STD_LOGIC; + signal IPv6_RX_SOF : std_logic; + signal IPv6_RX_EOF : std_logic; signal IPv6_RX_Meta_SrcMACAddress_Data : T_SLV_8; signal IPv6_RX_Meta_DestMACAddress_Data : T_SLV_8; @@ -176,21 +175,21 @@ architecture rtl of ipv6_Wrapper is signal IPv6_RX_Meta_Length : T_SLV_16; signal IPv6_RX_Meta_NextHeader : T_SLV_8; - constant STMDEMUX_META_RST_BIT : NATURAL := 0; - constant STMDEMUX_META_MACSRC_NXT_BIT : NATURAL := 1; - constant STMDEMUX_META_MACDEST_NXT_BIT : NATURAL := 2; - constant STMDEMUX_META_IPV6SRC_NXT_BIT : NATURAL := 3; - constant STMDEMUX_META_IPV6DEST_NXT_BIT : NATURAL := 4; - - constant STMDEMUX_META_STREAMID_SRCMAC : NATURAL := 0; - constant STMDEMUX_META_STREAMID_DESTMAC : NATURAL := 1; - constant STMDEMUX_META_STREAMID_ETHTYPE : NATURAL := 2; - constant STMDEMUX_META_STREAMID_SRCIP : NATURAL := 3; - constant STMDEMUX_META_STREAMID_DESTIP : NATURAL := 4; - constant STMDEMUX_META_STREAMID_LENGTH : NATURAL := 5; - constant STMDEMUX_META_STREAMID_HEADER : NATURAL := 6; - - constant STMDEMUX_DATA_BITS : NATURAL := 8; -- + constant STMDEMUX_META_RST_BIT : natural := 0; + constant STMDEMUX_META_MACSRC_NXT_BIT : natural := 1; + constant STMDEMUX_META_MACDEST_NXT_BIT : natural := 2; + constant STMDEMUX_META_IPV6SRC_NXT_BIT : natural := 3; + constant STMDEMUX_META_IPV6DEST_NXT_BIT : natural := 4; + + constant STMDEMUX_META_STREAMID_SRCMAC : natural := 0; + constant STMDEMUX_META_STREAMID_DESTMAC : natural := 1; + constant STMDEMUX_META_STREAMID_ETHTYPE : natural := 2; + constant STMDEMUX_META_STREAMID_SRCIP : natural := 3; + constant STMDEMUX_META_STREAMID_DESTIP : natural := 4; + constant STMDEMUX_META_STREAMID_LENGTH : natural := 5; + constant STMDEMUX_META_STREAMID_HEADER : natural := 6; + + constant STMDEMUX_DATA_BITS : natural := 8; -- constant STMDEMUX_META_BITS : T_POSVEC := ( STMDEMUX_META_STREAMID_SRCMAC => 8, STMDEMUX_META_STREAMID_DESTMAC => 8, @@ -200,31 +199,31 @@ architecture rtl of ipv6_Wrapper is STMDEMUX_META_STREAMID_LENGTH => 16, STMDEMUX_META_STREAMID_HEADER => 8 ); - constant STMDEMUX_META_REV_BITS : NATURAL := 5; -- sum over all control bits (rst, nxt, nxt, nxt, nxt) + constant STMDEMUX_META_REV_BITS : natural := 5; -- sum over all control bits (rst, nxt, nxt, nxt, nxt) - signal RX_StmDeMux_Ack : STD_LOGIC; - signal RX_StmDeMux_Meta_rst : STD_LOGIC; - signal RX_StmDeMux_Meta_SrcMACAddress_nxt : STD_LOGIC; - signal RX_StmDeMux_Meta_DestMACAddress_nxt : STD_LOGIC; - signal RX_StmDeMux_Meta_SrcIPv6Address_nxt : STD_LOGIC; - signal RX_StmDeMux_Meta_DestIPv6Address_nxt : STD_LOGIC; + signal RX_StmDeMux_Ack : std_logic; + signal RX_StmDeMux_Meta_rst : std_logic; + signal RX_StmDeMux_Meta_SrcMACAddress_nxt : std_logic; + signal RX_StmDeMux_Meta_DestMACAddress_nxt : std_logic; + signal RX_StmDeMux_Meta_SrcIPv6Address_nxt : std_logic; + signal RX_StmDeMux_Meta_DestIPv6Address_nxt : std_logic; - signal RX_StmDeMux_MetaIn : STD_LOGIC_VECTOR(isum(STMDEMUX_META_BITS) - 1 downto 0); - signal RX_StmDeMux_MetaIn_rev : STD_LOGIC_VECTOR(STMDEMUX_META_REV_BITS - 1 downto 0); + signal RX_StmDeMux_MetaIn : std_logic_vector(isum(STMDEMUX_META_BITS) - 1 downto 0); + signal RX_StmDeMux_MetaIn_rev : std_logic_vector(STMDEMUX_META_REV_BITS - 1 downto 0); signal RX_StmDeMux_Data : T_SLM(IPV6_SWITCH_PORTS - 1 downto 0, STMDEMUX_DATA_BITS - 1 downto 0) := (others => (others => 'Z')); -- necessary default assignment 'Z' to get correct simulation results (iSIM, vSIM, ghdl/gtkwave) signal RX_StmDeMux_MetaOut : T_SLM(IPV6_SWITCH_PORTS - 1 downto 0, isum(STMDEMUX_META_BITS) - 1 downto 0) := (others => (others => 'Z')); -- necessary default assignment 'Z' to get correct simulation results (iSIM, vSIM, ghdl/gtkwave) signal RX_StmDeMux_MetaOut_rev : T_SLM(IPV6_SWITCH_PORTS - 1 downto 0, STMDEMUX_META_REV_BITS - 1 downto 0) := (others => (others => 'Z')); -- necessary default assignment 'Z' to get correct simulation results (iSIM, vSIM, ghdl/gtkwave) - signal StmDeMux_Control : STD_LOGIC_VECTOR(IPV6_SWITCH_PORTS - 1 downto 0); + signal StmDeMux_Control : std_logic_vector(IPV6_SWITCH_PORTS - 1 downto 0); begin --- ============================================================================================================================================================ +-- ============================================================================= -- TX Path --- ============================================================================================================================================================ +-- ============================================================================= genTXStmBuf : for i in 0 to IPV6_SWITCH_PORTS - 1 generate - constant TXSTMBUF_META_STREAMID_SRCADR : NATURAL := 0; - constant TXSTMBUF_META_STREAMID_DESTADR : NATURAL := 1; - constant TXSTMBUF_META_STREAMID_LENGTH : NATURAL := 2; + constant TXSTMBUF_META_STREAMID_SRCADR : natural := 0; + constant TXSTMBUF_META_STREAMID_DESTADR : natural := 1; + constant TXSTMBUF_META_STREAMID_LENGTH : natural := 2; constant TXSTMBUF_META_BITS : T_POSVEC := ( TXSTMBUF_META_STREAMID_SRCADR => 8, @@ -240,19 +239,19 @@ begin signal StmBuf_DataOut : T_SLV_8; -- signal Meta_rst : STD_LOGIC; - signal StmBuf_MetaIn_nxt : STD_LOGIC_VECTOR(TXSTMBUF_META_BITS'length - 1 downto 0); - signal StmBuf_MetaIn_Data : STD_LOGIC_VECTOR(isum(TXSTMBUF_META_BITS) - 1 downto 0); + signal StmBuf_MetaIn_nxt : std_logic_vector(TXSTMBUF_META_BITS'length - 1 downto 0); + signal StmBuf_MetaIn_Data : std_logic_vector(isum(TXSTMBUF_META_BITS) - 1 downto 0); - signal StmBuf_Meta_rst : STD_LOGIC; - signal StmBuf_MetaOut_nxt : STD_LOGIC_VECTOR(TXSTMBUF_META_BITS'length - 1 downto 0); - signal StmBuf_MetaOut_Data : STD_LOGIC_VECTOR(isum(TXSTMBUF_META_BITS) - 1 downto 0); + signal StmBuf_Meta_rst : std_logic; + signal StmBuf_MetaOut_nxt : std_logic_vector(TXSTMBUF_META_BITS'length - 1 downto 0); + signal StmBuf_MetaOut_Data : std_logic_vector(isum(TXSTMBUF_META_BITS) - 1 downto 0); - signal StmBuf_Meta_SrcIPv6Address_Data : STD_LOGIC_VECTOR(TX_StmMux_SrcIPv6Address_Data'range); - signal StmBuf_Meta_DestIPv6Address_Data : STD_LOGIC_VECTOR(TX_StmMux_DestIPv6Address_Data'range); - signal StmBuf_Meta_Length : STD_LOGIC_VECTOR(TX_StmMux_Length'range); - signal StmBuf_Meta_NextHeader : STD_LOGIC_VECTOR(TX_StmMux_NextHeader'range); + signal StmBuf_Meta_SrcIPv6Address_Data : std_logic_vector(TX_StmMux_SrcIPv6Address_Data'range); + signal StmBuf_Meta_DestIPv6Address_Data : std_logic_vector(TX_StmMux_DestIPv6Address_Data'range); + signal StmBuf_Meta_Length : std_logic_vector(TX_StmMux_Length'range); + signal StmBuf_Meta_NextHeader : std_logic_vector(TX_StmMux_NextHeader'range); - signal StmMux_MetaIn_Data : STD_LOGIC_VECTOR(isum(TXSTMMUX_META_BITS) - 1 downto 0); + signal StmMux_MetaIn_Data : std_logic_vector(isum(TXSTMMUX_META_BITS) - 1 downto 0); begin StmBuf_MetaIn_Data(high(TXSTMBUF_META_BITS, TXSTMBUF_META_STREAMID_SRCADR) downto low(TXSTMBUF_META_BITS, TXSTMBUF_META_STREAMID_SRCADR)) <= TX_Meta_SrcIPv6Address_Data(i); @@ -395,9 +394,9 @@ begin Out_Meta_DestMACAddress_Data => MAC_TX_Meta_DestMACAddress_Data ); --- ============================================================================================================================================================ +-- ============================================================================= -- RX Path --- ============================================================================================================================================================ +-- ============================================================================= RX_IPv6 : entity PoC.ipv6_RX generic map ( DEBUG => DEBUG diff --git a/src/net/mac/mac_FrameLoopback.vhdl b/src/net/mac/mac_FrameLoopback.vhdl index 78a7d384..6655dd4b 100644 --- a/src/net/mac/mac_FrameLoopback.vhdl +++ b/src/net/mac/mac_FrameLoopback.vhdl @@ -1,18 +1,17 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: TODO +-- Entity: TODO -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -27,7 +26,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -42,40 +41,40 @@ use PoC.net.all; entity mac_FrameLoopback is generic ( - MAX_FRAMES : POSITIVE := 4 + MAX_FRAMES : positive := 4 ); port ( - Clock : in STD_LOGIC; - Reset : in STD_LOGIC; + Clock : in std_logic; + Reset : in std_logic; -- IN Port - In_Valid : in STD_LOGIC; + In_Valid : in std_logic; In_Data : in T_SLV_8; - In_SOF : in STD_LOGIC; - In_EOF : in STD_LOGIC; - In_Ack : out STD_LOGIC; - In_Meta_rst : out STD_LOGIC; - In_Meta_SrcMACAddress_nxt : out STD_LOGIC; + In_SOF : in std_logic; + In_EOF : in std_logic; + In_Ack : out std_logic; + In_Meta_rst : out std_logic; + In_Meta_SrcMACAddress_nxt : out std_logic; In_Meta_SrcMACAddress_Data : in T_SLV_8; - In_Meta_DestMACAddress_nxt : out STD_LOGIC; + In_Meta_DestMACAddress_nxt : out std_logic; In_Meta_DestMACAddress_Data : in T_SLV_8; -- OUT Port - Out_Valid : out STD_LOGIC; + Out_Valid : out std_logic; Out_Data : out T_SLV_8; - Out_SOF : out STD_LOGIC; - Out_EOF : out STD_LOGIC; - Out_Ack : in STD_LOGIC; - Out_Meta_rst : in STD_LOGIC; - Out_Meta_SrcMACAddress_nxt : in STD_LOGIC; + Out_SOF : out std_logic; + Out_EOF : out std_logic; + Out_Ack : in std_logic; + Out_Meta_rst : in std_logic; + Out_Meta_SrcMACAddress_nxt : in std_logic; Out_Meta_SrcMACAddress_Data : out T_SLV_8; - Out_Meta_DestMACAddress_nxt : in STD_LOGIC; + Out_Meta_DestMACAddress_nxt : in std_logic; Out_Meta_DestMACAddress_Data : out T_SLV_8 ); end entity; architecture rtl of mac_FrameLoopback is - constant META_STREAMID_SRCADDR : NATURAL := 0; - constant META_STREAMID_DESTADDR : NATURAL := 1; + constant META_STREAMID_SRCADDR : natural := 0; + constant META_STREAMID_DESTADDR : natural := 1; constant META_BITS : T_POSVEC := ( META_STREAMID_SRCADDR => 8, @@ -87,10 +86,10 @@ architecture rtl of mac_FrameLoopback is META_STREAMID_DESTADDR => 6 ); - signal LLBuf_MetaIn_nxt : STD_LOGIC_VECTOR(META_BITS'length - 1 downto 0); - signal LLBuf_MetaIn_Data : STD_LOGIC_VECTOR(isum(META_BITS) - 1 downto 0); - signal LLBuf_MetaOut_nxt : STD_LOGIC_VECTOR(META_BITS'length - 1 downto 0); - signal LLBuf_MetaOut_Data : STD_LOGIC_VECTOR(isum(META_BITS) - 1 downto 0); + signal LLBuf_MetaIn_nxt : std_logic_vector(META_BITS'length - 1 downto 0); + signal LLBuf_MetaIn_Data : std_logic_vector(isum(META_BITS) - 1 downto 0); + signal LLBuf_MetaOut_nxt : std_logic_vector(META_BITS'length - 1 downto 0); + signal LLBuf_MetaOut_Data : std_logic_vector(isum(META_BITS) - 1 downto 0); begin LLBuf_MetaIn_Data(high(META_BITS, META_STREAMID_SRCADDR) downto low(META_BITS, META_STREAMID_SRCADDR)) <= In_Meta_SrcMACAddress_Data; diff --git a/src/net/mac/mac_RX_DestMAC_Switch.vhdl b/src/net/mac/mac_RX_DestMAC_Switch.vhdl index 8d8ac2e8..358ca465 100644 --- a/src/net/mac/mac_RX_DestMAC_Switch.vhdl +++ b/src/net/mac/mac_RX_DestMAC_Switch.vhdl @@ -1,18 +1,17 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: TODO +-- Entity: TODO -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -27,7 +26,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -42,36 +41,36 @@ use PoC.net.all; entity mac_RX_DestMAC_Switch is generic ( - DEBUG : BOOLEAN := FALSE; + DEBUG : boolean := FALSE; MAC_ADDRESSES : T_NET_MAC_ADDRESS_VECTOR := (0 => C_NET_MAC_ADDRESS_EMPTY); MAC_ADDRESSE_MASKS : T_NET_MAC_ADDRESS_VECTOR := (0 => C_NET_MAC_MASK_DEFAULT) ); port ( - Clock : in STD_LOGIC; - Reset : in STD_LOGIC; + Clock : in std_logic; + Reset : in std_logic; - In_Valid : in STD_LOGIC; + In_Valid : in std_logic; In_Data : in T_SLV_8; - In_SOF : in STD_LOGIC; - In_EOF : in STD_LOGIC; - In_Ack : out STD_LOGIC; + In_SOF : in std_logic; + In_EOF : in std_logic; + In_Ack : out std_logic; - Out_Valid : out STD_LOGIC_VECTOR(MAC_ADDRESSES'length - 1 downto 0); + Out_Valid : out std_logic_vector(MAC_ADDRESSES'length - 1 downto 0); Out_Data : out T_SLVV_8(MAC_ADDRESSES'length - 1 downto 0); - Out_SOF : out STD_LOGIC_VECTOR(MAC_ADDRESSES'length - 1 downto 0); - Out_EOF : out STD_LOGIC_VECTOR(MAC_ADDRESSES'length - 1 downto 0); - Out_Ack : in STD_LOGIC_VECTOR(MAC_ADDRESSES'length - 1 downto 0); - Out_Meta_DestMACAddress_rst : in STD_LOGIC_VECTOR(MAC_ADDRESSES'length - 1 downto 0); - Out_Meta_DestMACAddress_nxt : in STD_LOGIC_VECTOR(MAC_ADDRESSES'length - 1 downto 0); + Out_SOF : out std_logic_vector(MAC_ADDRESSES'length - 1 downto 0); + Out_EOF : out std_logic_vector(MAC_ADDRESSES'length - 1 downto 0); + Out_Ack : in std_logic_vector(MAC_ADDRESSES'length - 1 downto 0); + Out_Meta_DestMACAddress_rst : in std_logic_vector(MAC_ADDRESSES'length - 1 downto 0); + Out_Meta_DestMACAddress_nxt : in std_logic_vector(MAC_ADDRESSES'length - 1 downto 0); Out_Meta_DestMACAddress_Data : out T_SLVV_8(MAC_ADDRESSES'length - 1 downto 0) ); end entity; architecture rtl of mac_RX_DestMAC_Switch is - attribute FSM_ENCODING : STRING; + attribute FSM_ENCODING : string; - constant PORTS : POSITIVE := MAC_ADDRESSES'length; + constant PORTS : positive := MAC_ADDRESSES'length; constant MAC_ADDRESSES_I : T_NET_MAC_ADDRESS_VECTOR(0 to PORTS - 1) := MAC_ADDRESSES; constant MAC_ADDRESSE_MASKS_I : T_NET_MAC_ADDRESS_VECTOR(0 to PORTS - 1) := MAC_ADDRESSE_MASKS; @@ -87,47 +86,47 @@ architecture rtl of mac_RX_DestMAC_Switch is ST_DISCARD_FRAME ); - subtype T_MAC_BYTEINDEX is NATURAL range 0 to 5; + subtype T_MAC_BYTEINDEX is natural range 0 to 5; signal State : T_STATE := ST_IDLE; signal NextState : T_STATE; attribute FSM_ENCODING of State : signal is ite(DEBUG, "gray", ite((VENDOR = VENDOR_XILINX), "auto", "default")); - signal In_Ack_i : STD_LOGIC; - signal Is_DataFlow : STD_LOGIC; - signal Is_SOF : STD_LOGIC; - signal Is_EOF : STD_LOGIC; + signal In_Ack_i : std_logic; + signal Is_DataFlow : std_logic; + signal Is_SOF : std_logic; + signal Is_EOF : std_logic; - signal New_Valid_i : STD_LOGIC; - signal New_SOF_i : STD_LOGIC; - signal Out_Ack_i : STD_LOGIC; + signal New_Valid_i : std_logic; + signal New_SOF_i : std_logic; + signal Out_Ack_i : std_logic; signal MAC_ByteIndex : T_MAC_BYTEINDEX; - signal CompareRegister_rst : STD_LOGIC; - signal CompareRegister_init : STD_LOGIC; - signal CompareRegister_clear : STD_LOGIC; - signal CompareRegister_en : STD_LOGIC; - signal CompareRegister_d : STD_LOGIC_VECTOR(PORTS - 1 downto 0) := (others => '1'); - signal NoHits : STD_LOGIC; + signal CompareRegister_rst : std_logic; + signal CompareRegister_init : std_logic; + signal CompareRegister_clear : std_logic; + signal CompareRegister_en : std_logic; + signal CompareRegister_d : std_logic_vector(PORTS - 1 downto 0) := (others => '1'); + signal NoHits : std_logic; - constant MAC_ADDRESS_LENGTH : POSITIVE := 6; -- MAC -> 6 bytes - constant READER_COUNTER_BITS : POSITIVE := log2ceilnz(MAC_ADDRESS_LENGTH); + constant MAC_ADDRESS_LENGTH : positive := 6; -- MAC -> 6 bytes + constant READER_COUNTER_BITS : positive := log2ceilnz(MAC_ADDRESS_LENGTH); - signal Reader_Counter_rst : STD_LOGIC; - signal Reader_Counter_en : STD_LOGIC; - signal Reader_Counter_us : UNSIGNED(READER_COUNTER_BITS - 1 downto 0) := (others => '0'); + signal Reader_Counter_rst : std_logic; + signal Reader_Counter_en : std_logic; + signal Reader_Counter_us : unsigned(READER_COUNTER_BITS - 1 downto 0) := (others => '0'); - signal DestinationMAC_rst : STD_LOGIC; - signal DestinationMAC_en : STD_LOGIC; + signal DestinationMAC_rst : std_logic; + signal DestinationMAC_en : std_logic; signal DestinationMAC_sel : T_MAC_BYTEINDEX; signal DestinationMAC_d : T_NET_MAC_ADDRESS := C_NET_MAC_ADDRESS_EMPTY; - signal Out_Meta_DestMACAddress_rst_i : STD_LOGIC; - signal Out_Meta_DestMACAddress_nxt_i : STD_LOGIC; + signal Out_Meta_DestMACAddress_rst_i : std_logic; + signal Out_Meta_DestMACAddress_nxt_i : std_logic; begin - assert FALSE report "RX_DestMAC_Switch: ports=" & INTEGER'image(PORTS) severity NOTE; + assert FALSE report "RX_DestMAC_Switch: ports=" & integer'image(PORTS) severity NOTE; In_Ack <= In_Ack_i; Is_DataFlow <= In_Valid and In_Ack_i; @@ -296,14 +295,14 @@ begin gen0 : for i in 0 to PORTS - 1 generate - signal Hit : STD_LOGIC; + signal Hit : std_logic; begin Hit <= to_sl((In_Data and MAC_ADDRESSE_MASKS_I(i)(MAC_ByteIndex)) = (MAC_ADDRESSES_I(i)(MAC_ByteIndex) and MAC_ADDRESSE_MASKS_I(i)(MAC_ByteIndex))); process(Clock) begin if rising_edge(Clock) then - if ((Reset OR CompareRegister_rst) = '1') then + if ((Reset or CompareRegister_rst) = '1') then CompareRegister_d(i) <= '0'; elsif (CompareRegister_init = '1') then CompareRegister_d(i) <= Hit; @@ -323,7 +322,7 @@ begin process(Clock) begin if rising_edge(Clock) then - if ((Reset OR DestinationMAC_rst) = '1') then + if ((Reset or DestinationMAC_rst) = '1') then DestinationMAC_d <= C_NET_MAC_ADDRESS_EMPTY; elsif (DestinationMAC_en = '1') then DestinationMAC_d(DestinationMAC_sel) <= In_Data; @@ -337,7 +336,7 @@ begin process(Clock) begin if rising_edge(Clock) then - if ((Reset OR Reader_Counter_rst) = '1') then + if ((Reset or Reader_Counter_rst) = '1') then Reader_Counter_us <= to_unsigned(T_MAC_BYTEINDEX'high, Reader_Counter_us'length); elsif (Reader_Counter_en = '1') then Reader_Counter_us <= Reader_Counter_us - 1; diff --git a/src/net/mac/mac_RX_SrcMAC_Filter.vhdl b/src/net/mac/mac_RX_SrcMAC_Filter.vhdl index 413d16ee..bbb838fb 100644 --- a/src/net/mac/mac_RX_SrcMAC_Filter.vhdl +++ b/src/net/mac/mac_RX_SrcMAC_Filter.vhdl @@ -1,18 +1,17 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: TODO +-- Entity: TODO -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -27,7 +26,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -42,41 +41,41 @@ use PoC.net.all; entity mac_RX_SrcMAC_Filter is generic ( - DEBUG : BOOLEAN := FALSE; + DEBUG : boolean := FALSE; MAC_ADDRESSES : T_NET_MAC_ADDRESS_VECTOR := (0 => C_NET_MAC_ADDRESS_EMPTY); MAC_ADDRESSE_MASKS : T_NET_MAC_ADDRESS_VECTOR := (0 => C_NET_MAC_MASK_DEFAULT) ); port ( - Clock : in STD_LOGIC; - Reset : in STD_LOGIC; + Clock : in std_logic; + Reset : in std_logic; - In_Valid : in STD_LOGIC; + In_Valid : in std_logic; In_Data : in T_SLV_8; - In_SOF : in STD_LOGIC; - In_EOF : in STD_LOGIC; - In_Ack : out STD_LOGIC; - In_Meta_rst : out STD_LOGIC; - In_Meta_DestMACAddress_nxt : out STD_LOGIC; + In_SOF : in std_logic; + In_EOF : in std_logic; + In_Ack : out std_logic; + In_Meta_rst : out std_logic; + In_Meta_DestMACAddress_nxt : out std_logic; In_Meta_DestMACAddress_Data : in T_SLV_8; - Out_Valid : out STD_LOGIC; + Out_Valid : out std_logic; Out_Data : out T_SLV_8; - Out_SOF : out STD_LOGIC; - Out_EOF : out STD_LOGIC; - Out_Ack : in STD_LOGIC; - Out_Meta_rst : in STD_LOGIC; - Out_Meta_DestMACAddress_nxt : in STD_LOGIC; + Out_SOF : out std_logic; + Out_EOF : out std_logic; + Out_Ack : in std_logic; + Out_Meta_rst : in std_logic; + Out_Meta_DestMACAddress_nxt : in std_logic; Out_Meta_DestMACAddress_Data : out T_SLV_8; - Out_Meta_SrcMACAddress_nxt : in STD_LOGIC; + Out_Meta_SrcMACAddress_nxt : in std_logic; Out_Meta_SrcMACAddress_Data : out T_SLV_8 ); end entity; architecture rtl of mac_RX_SrcMAC_Filter is - attribute FSM_ENCODING : STRING; + attribute FSM_ENCODING : string; - constant PATTERN_COUNT : POSITIVE := MAC_ADDRESSES'length; + constant PATTERN_COUNT : positive := MAC_ADDRESSES'length; constant MAC_ADDRESSES_I : T_NET_MAC_ADDRESS_VECTOR(0 to PATTERN_COUNT - 1) := MAC_ADDRESSES; constant MAC_ADDRESSE_MASKS_I : T_NET_MAC_ADDRESS_VECTOR(0 to PATTERN_COUNT - 1) := MAC_ADDRESSE_MASKS; @@ -92,47 +91,47 @@ architecture rtl of mac_RX_SrcMAC_Filter is ST_DISCARD_FRAME ); - subtype T_MAC_BYTEINDEX is NATURAL range 0 to 5; + subtype T_MAC_BYTEINDEX is natural range 0 to 5; signal State : T_STATE := ST_IDLE; signal NextState : T_STATE; attribute FSM_ENCODING of State : signal is ite(DEBUG, "gray", ite((VENDOR = VENDOR_XILINX), "auto", "default")); - signal In_Ack_i : STD_LOGIC; - signal Is_DataFlow : STD_LOGIC; - signal Is_SOF : STD_LOGIC; - signal Is_EOF : STD_LOGIC; + signal In_Ack_i : std_logic; + signal Is_DataFlow : std_logic; + signal Is_SOF : std_logic; + signal Is_EOF : std_logic; - signal New_Valid_i : STD_LOGIC; - signal New_SOF_i : STD_LOGIC; - signal Out_Ack_i : STD_LOGIC; + signal New_Valid_i : std_logic; + signal New_SOF_i : std_logic; + signal Out_Ack_i : std_logic; signal MAC_ByteIndex : T_MAC_BYTEINDEX; - signal CompareRegister_rst : STD_LOGIC; - signal CompareRegister_init : STD_LOGIC; - signal CompareRegister_clear : STD_LOGIC; - signal CompareRegister_en : STD_LOGIC; - signal CompareRegister_d : STD_LOGIC_VECTOR(PATTERN_COUNT - 1 downto 0) := (others => '1'); - signal NoHits : STD_LOGIC; + signal CompareRegister_rst : std_logic; + signal CompareRegister_init : std_logic; + signal CompareRegister_clear : std_logic; + signal CompareRegister_en : std_logic; + signal CompareRegister_d : std_logic_vector(PATTERN_COUNT - 1 downto 0) := (others => '1'); + signal NoHits : std_logic; - signal SourceMACAddress_rst : STD_LOGIC; - signal SourceMACAddress_en : STD_LOGIC; + signal SourceMACAddress_rst : std_logic; + signal SourceMACAddress_en : std_logic; signal SourceMACAddress_sel : T_MAC_BYTEINDEX; signal SourceMACAddress_d : T_NET_MAC_ADDRESS := C_NET_MAC_ADDRESS_EMPTY; - constant MAC_ADDRESS_LENGTH : POSITIVE := 6; -- MAC -> 6 bytes - constant READER_COUNTER_BITS : POSITIVE := log2ceilnz(MAC_ADDRESS_LENGTH); + constant MAC_ADDRESS_LENGTH : positive := 6; -- MAC -> 6 bytes + constant READER_COUNTER_BITS : positive := log2ceilnz(MAC_ADDRESS_LENGTH); - signal Reader_Counter_rst : STD_LOGIC; - signal Reader_Counter_en : STD_LOGIC; - signal Reader_Counter_us : UNSIGNED(READER_COUNTER_BITS - 1 downto 0) := (others => '0'); + signal Reader_Counter_rst : std_logic; + signal Reader_Counter_en : std_logic; + signal Reader_Counter_us : unsigned(READER_COUNTER_BITS - 1 downto 0) := (others => '0'); - signal Out_Meta_rst_i : STD_LOGIC; - signal Out_Meta_SrcMACAddress_nxt_i : STD_LOGIC; + signal Out_Meta_rst_i : std_logic; + signal Out_Meta_SrcMACAddress_nxt_i : std_logic; begin - assert FALSE report "RX_SrcMAC_Filter: patterns=" & INTEGER'image(PATTERN_COUNT) severity NOTE; + assert FALSE report "RX_SrcMAC_Filter: patterns=" & integer'image(PATTERN_COUNT) severity NOTE; In_Ack <= In_Ack_i; Is_DataFlow <= In_Valid and In_Ack_i; @@ -301,14 +300,14 @@ begin gen0 : for i in 0 to PATTERN_COUNT - 1 generate - signal Hit : STD_LOGIC; + signal Hit : std_logic; begin Hit <= to_sl((In_Data and MAC_ADDRESSE_MASKS_I(i)(MAC_ByteIndex)) = (MAC_ADDRESSES_I(i)(MAC_ByteIndex) and MAC_ADDRESSE_MASKS_I(i)(MAC_ByteIndex))); process(Clock) begin if rising_edge(Clock) then - if ((Reset OR CompareRegister_rst) = '1') then + if ((Reset or CompareRegister_rst) = '1') then CompareRegister_d(i) <= '0'; elsif (CompareRegister_init = '1') then CompareRegister_d(i) <= Hit; @@ -328,7 +327,7 @@ begin process(Clock) begin if rising_edge(Clock) then - if ((Reset OR SourceMACAddress_rst) = '1') then + if ((Reset or SourceMACAddress_rst) = '1') then SourceMACAddress_d <= C_NET_MAC_ADDRESS_EMPTY; elsif (SourceMACAddress_en = '1') then SourceMACAddress_d(SourceMACAddress_sel) <= In_Data; @@ -342,7 +341,7 @@ begin process(Clock) begin if rising_edge(Clock) then - if ((Reset OR Reader_Counter_rst) = '1') then + if ((Reset or Reader_Counter_rst) = '1') then Reader_Counter_us <= to_unsigned(T_MAC_BYTEINDEX'high, Reader_Counter_us'length); elsif (Reader_Counter_en = '1') then Reader_Counter_us <= Reader_Counter_us - 1; diff --git a/src/net/mac/mac_RX_Type_Switch.vhdl b/src/net/mac/mac_RX_Type_Switch.vhdl index 4e79f5c8..23d4cac0 100644 --- a/src/net/mac/mac_RX_Type_Switch.vhdl +++ b/src/net/mac/mac_RX_Type_Switch.vhdl @@ -1,18 +1,17 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: TODO +-- Entity: TODO -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -27,7 +26,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -42,33 +41,33 @@ use PoC.net.all; entity mac_RX_Type_Switch is generic ( - DEBUG : BOOLEAN := FALSE; + DEBUG : boolean := FALSE; ETHERNET_TYPES : T_NET_MAC_ETHERNETTYPE_VECTOR := (0 => C_NET_MAC_ETHERNETTYPE_EMPTY) ); port ( - Clock : in STD_LOGIC; - Reset : in STD_LOGIC; + Clock : in std_logic; + Reset : in std_logic; - In_Valid : in STD_LOGIC; + In_Valid : in std_logic; In_Data : in T_SLV_8; - In_SOF : in STD_LOGIC; - In_EOF : in STD_LOGIC; - In_Ack : out STD_LOGIC; - In_Meta_rst : out STD_LOGIC; - In_Meta_SrcMACAddress_nxt : out STD_LOGIC; + In_SOF : in std_logic; + In_EOF : in std_logic; + In_Ack : out std_logic; + In_Meta_rst : out std_logic; + In_Meta_SrcMACAddress_nxt : out std_logic; In_Meta_SrcMACAddress_Data : in T_SLV_8; - In_Meta_DestMACAddress_nxt : out STD_LOGIC; + In_Meta_DestMACAddress_nxt : out std_logic; In_Meta_DestMACAddress_Data : in T_SLV_8; - Out_Valid : out STD_LOGIC_VECTOR(ETHERNET_TYPES'length - 1 downto 0); + Out_Valid : out std_logic_vector(ETHERNET_TYPES'length - 1 downto 0); Out_Data : out T_SLVV_8(ETHERNET_TYPES'length - 1 downto 0); - Out_SOF : out STD_LOGIC_VECTOR(ETHERNET_TYPES'length - 1 downto 0); - Out_EOF : out STD_LOGIC_VECTOR(ETHERNET_TYPES'length - 1 downto 0); - Out_Ack : in STD_LOGIC_VECTOR(ETHERNET_TYPES'length - 1 downto 0); - Out_Meta_rst : in STD_LOGIC_VECTOR(ETHERNET_TYPES'length - 1 downto 0); - Out_Meta_SrcMACAddress_nxt : in STD_LOGIC_VECTOR(ETHERNET_TYPES'length - 1 downto 0); + Out_SOF : out std_logic_vector(ETHERNET_TYPES'length - 1 downto 0); + Out_EOF : out std_logic_vector(ETHERNET_TYPES'length - 1 downto 0); + Out_Ack : in std_logic_vector(ETHERNET_TYPES'length - 1 downto 0); + Out_Meta_rst : in std_logic_vector(ETHERNET_TYPES'length - 1 downto 0); + Out_Meta_SrcMACAddress_nxt : in std_logic_vector(ETHERNET_TYPES'length - 1 downto 0); Out_Meta_SrcMACAddress_Data : out T_SLVV_8(ETHERNET_TYPES'length - 1 downto 0); - Out_Meta_DestMACAddress_nxt : in STD_LOGIC_VECTOR(ETHERNET_TYPES'length - 1 downto 0); + Out_Meta_DestMACAddress_nxt : in std_logic_vector(ETHERNET_TYPES'length - 1 downto 0); Out_Meta_DestMACAddress_Data : out T_SLVV_8(ETHERNET_TYPES'length - 1 downto 0); Out_Meta_EthType : out T_NET_MAC_ETHERNETTYPE_VECTOR(ETHERNET_TYPES'length - 1 downto 0) ); @@ -76,9 +75,9 @@ end entity; architecture rtl of mac_RX_Type_Switch is - attribute FSM_ENCODING : STRING; + attribute FSM_ENCODING : string; - constant PORTS : POSITIVE := ETHERNET_TYPES'length; + constant PORTS : positive := ETHERNET_TYPES'length; constant ETHERNET_TYPES_I : T_NET_MAC_ETHERNETTYPE_VECTOR(0 to PORTS - 1) := ETHERNET_TYPES; type T_STATE is ( @@ -89,32 +88,32 @@ architecture rtl of mac_RX_Type_Switch is ST_DISCARD_FRAME ); - subtype T_ETHERNETTYPE_BYTEINDEX is NATURAL range 0 to 1; + subtype T_ETHERNETTYPE_BYTEINDEX is natural range 0 to 1; signal State : T_STATE := ST_IDLE; signal NextState : T_STATE; attribute FSM_ENCODING of State : signal is ite(DEBUG, "gray", ite((VENDOR = VENDOR_XILINX), "auto", "default")); - signal In_Ack_i : STD_LOGIC; - signal Is_DataFlow : STD_LOGIC; - signal Is_SOF : STD_LOGIC; - signal Is_EOF : STD_LOGIC; + signal In_Ack_i : std_logic; + signal Is_DataFlow : std_logic; + signal Is_SOF : std_logic; + signal Is_EOF : std_logic; - signal New_Valid_i : STD_LOGIC; - signal New_SOF_i : STD_LOGIC; - signal Out_Ack_i : STD_LOGIC; + signal New_Valid_i : std_logic; + signal New_SOF_i : std_logic; + signal Out_Ack_i : std_logic; signal EthernetType_CompareIndex : T_ETHERNETTYPE_BYTEINDEX; - signal CompareRegister_rst : STD_LOGIC; - signal CompareRegister_init : STD_LOGIC; - signal CompareRegister_clear : STD_LOGIC; - signal CompareRegister_en : STD_LOGIC; - signal CompareRegister_d : STD_LOGIC_VECTOR(PORTS - 1 downto 0) := (others => '1'); - signal NoHits : STD_LOGIC; + signal CompareRegister_rst : std_logic; + signal CompareRegister_init : std_logic; + signal CompareRegister_clear : std_logic; + signal CompareRegister_en : std_logic; + signal CompareRegister_d : std_logic_vector(PORTS - 1 downto 0) := (others => '1'); + signal NoHits : std_logic; - signal EthernetType_rst : STD_LOGIC; - signal EthernetType_en : STD_LOGIC; + signal EthernetType_rst : std_logic; + signal EthernetType_en : std_logic; signal EthernetType_sel : T_ETHERNETTYPE_BYTEINDEX; signal EthernetType_d : T_NET_MAC_ETHERNETTYPE := C_NET_MAC_ETHERNETTYPE_EMPTY; @@ -230,14 +229,14 @@ begin gen0 : for i in 0 to PORTS - 1 generate - signal Hit : STD_LOGIC; + signal Hit : std_logic; begin Hit <= to_sl(In_Data = ETHERNET_TYPES_I(i)(EthernetType_CompareIndex)); process(Clock) begin if rising_edge(Clock) then - if ((Reset OR CompareRegister_rst) = '1') then + if ((Reset or CompareRegister_rst) = '1') then CompareRegister_d(i) <= '0'; elsif (CompareRegister_init = '1') then CompareRegister_d(i) <= Hit; diff --git a/src/net/mac/mac_TX_DestMAC_Prepender.vhdl b/src/net/mac/mac_TX_DestMAC_Prepender.vhdl index 25e71ff1..7117b9bd 100644 --- a/src/net/mac/mac_TX_DestMAC_Prepender.vhdl +++ b/src/net/mac/mac_TX_DestMAC_Prepender.vhdl @@ -1,18 +1,17 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: TODO +-- Entity: TODO -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -27,7 +26,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -42,32 +41,32 @@ use PoC.net.all; entity mac_TX_DestMAC_Prepender is generic ( - DEBUG : BOOLEAN := FALSE + DEBUG : boolean := FALSE ); port ( - Clock : in STD_LOGIC; - Reset : in STD_LOGIC; + Clock : in std_logic; + Reset : in std_logic; - In_Valid : in STD_LOGIC; + In_Valid : in std_logic; In_Data : in T_SLV_8; - In_SOF : in STD_LOGIC; - In_EOF : in STD_LOGIC; - In_Ack : out STD_LOGIC; - In_Meta_rst : out STD_LOGIC; - In_Meta_DestMACAddress_nxt : out STD_LOGIC; + In_SOF : in std_logic; + In_EOF : in std_logic; + In_Ack : out std_logic; + In_Meta_rst : out std_logic; + In_Meta_DestMACAddress_nxt : out std_logic; In_Meta_DestMACAddress_Data : in T_SLV_8; - Out_Valid : out STD_LOGIC; + Out_Valid : out std_logic; Out_Data : out T_SLV_8; - Out_SOF : out STD_LOGIC; - Out_EOF : out STD_LOGIC; - Out_Ack : in STD_LOGIC + Out_SOF : out std_logic; + Out_EOF : out std_logic; + Out_Ack : in std_logic ); end entity; architecture rtl of mac_TX_DestMAC_Prepender is - attribute FSM_ENCODING : STRING; + attribute FSM_ENCODING : string; type T_STATE is ( ST_IDLE, @@ -83,9 +82,9 @@ architecture rtl of mac_TX_DestMAC_Prepender is signal NextState : T_STATE; attribute FSM_ENCODING of State : signal is ite(DEBUG, "gray", ite((VENDOR = VENDOR_XILINX), "auto", "default")); - signal Is_DataFlow : STD_LOGIC; - signal Is_SOF : STD_LOGIC; - signal Is_EOF : STD_LOGIC; + signal Is_DataFlow : std_logic; + signal Is_SOF : std_logic; + signal Is_EOF : std_logic; begin diff --git a/src/net/mac/mac_TX_SrcMAC_Prepender.vhdl b/src/net/mac/mac_TX_SrcMAC_Prepender.vhdl index f1946608..ff70cafc 100644 --- a/src/net/mac/mac_TX_SrcMAC_Prepender.vhdl +++ b/src/net/mac/mac_TX_SrcMAC_Prepender.vhdl @@ -1,18 +1,17 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: TODO +-- Entity: TODO -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -27,7 +26,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -42,44 +41,44 @@ use PoC.net.all; entity mac_TX_SrcMAC_Prepender is generic ( - DEBUG : BOOLEAN := FALSE; + DEBUG : boolean := FALSE; MAC_ADDRESSES : T_NET_MAC_ADDRESS_VECTOR := (0 => C_NET_MAC_ADDRESS_EMPTY) ); port ( - Clock : in STD_LOGIC; - Reset : in STD_LOGIC; + Clock : in std_logic; + Reset : in std_logic; -- IN Port - In_Valid : in STD_LOGIC_VECTOR(MAC_ADDRESSES'length - 1 downto 0); + In_Valid : in std_logic_vector(MAC_ADDRESSES'length - 1 downto 0); In_Data : in T_SLVV_8(MAC_ADDRESSES'length - 1 downto 0); - In_SOF : in STD_LOGIC_VECTOR(MAC_ADDRESSES'length - 1 downto 0); - In_EOF : in STD_LOGIC_VECTOR(MAC_ADDRESSES'length - 1 downto 0); - In_Ack : out STD_LOGIC_VECTOR(MAC_ADDRESSES'length - 1 downto 0); - In_Meta_rst : OUT STD_LOGIC_VECTOR(MAC_ADDRESSES'length - 1 downto 0); - In_Meta_DestMACAddress_nxt : OUT STD_LOGIC_VECTOR(MAC_ADDRESSES'length - 1 downto 0); + In_SOF : in std_logic_vector(MAC_ADDRESSES'length - 1 downto 0); + In_EOF : in std_logic_vector(MAC_ADDRESSES'length - 1 downto 0); + In_Ack : out std_logic_vector(MAC_ADDRESSES'length - 1 downto 0); + In_Meta_rst : out std_logic_vector(MAC_ADDRESSES'length - 1 downto 0); + In_Meta_DestMACAddress_nxt : out std_logic_vector(MAC_ADDRESSES'length - 1 downto 0); In_Meta_DestMACAddress_Data : in T_SLVV_8(MAC_ADDRESSES'length - 1 downto 0); -- OUT Port - Out_Valid : out STD_LOGIC; + Out_Valid : out std_logic; Out_Data : out T_SLV_8; - Out_SOF : out STD_LOGIC; - Out_EOF : out STD_LOGIC; - Out_Ack : in STD_LOGIC; - Out_Meta_rst : in STD_LOGIC; - Out_Meta_DestMACAddress_nxt : in STD_LOGIC; + Out_SOF : out std_logic; + Out_EOF : out std_logic; + Out_Ack : in std_logic; + Out_Meta_rst : in std_logic; + Out_Meta_DestMACAddress_nxt : in std_logic; Out_Meta_DestMACAddress_Data : out T_SLV_8 ); end entity; architecture rtl of mac_TX_SrcMAC_Prepender is - attribute FSM_ENCODING : STRING; + attribute FSM_ENCODING : string; - constant PORTS : POSITIVE := MAC_ADDRESSES'length; + constant PORTS : positive := MAC_ADDRESSES'length; - constant META_RST_BIT : NATURAL := 0; - constant META_DEST_NXT_BIT : NATURAL := 1; + constant META_RST_BIT : natural := 0; + constant META_DEST_NXT_BIT : natural := 1; - constant META_BITS : POSITIVE := 56; - constant META_REV_BITS : POSITIVE := 2; + constant META_BITS : positive := 56; + constant META_REV_BITS : positive := 2; type T_STATE is ( ST_IDLE, @@ -95,25 +94,25 @@ architecture rtl of mac_TX_SrcMAC_Prepender is signal NextState : T_STATE; attribute FSM_ENCODING of State : signal is ite(DEBUG, "gray", ite((VENDOR = VENDOR_XILINX), "auto", "default")); - signal LLMux_In_Valid : STD_LOGIC_VECTOR(PORTS - 1 downto 0); + signal LLMux_In_Valid : std_logic_vector(PORTS - 1 downto 0); signal LLMux_In_Data : T_SLM(PORTS - 1 downto 0, T_SLV_8'range) := (others => (others => 'Z')); -- necessary default assignment 'Z' to get correct simulation results (iSIM, vSIM, ghdl/gtkwave) signal LLMux_In_Meta : T_SLM(PORTS - 1 downto 0, META_BITS - 1 downto 0) := (others => (others => 'Z')); -- necessary default assignment 'Z' to get correct simulation results (iSIM, vSIM, ghdl/gtkwave) signal LLMux_In_Meta_rev : T_SLM(PORTS - 1 downto 0, META_REV_BITS - 1 downto 0) := (others => (others => 'Z')); -- necessary default assignment 'Z' to get correct simulation results (iSIM, vSIM, ghdl/gtkwave) - signal LLMux_In_SOF : STD_LOGIC_VECTOR(PORTS - 1 downto 0); - signal LLMux_In_EOF : STD_LOGIC_VECTOR(PORTS - 1 downto 0); - signal LLMux_In_Ack : STD_LOGIC_VECTOR(PORTS - 1 downto 0); + signal LLMux_In_SOF : std_logic_vector(PORTS - 1 downto 0); + signal LLMux_In_EOF : std_logic_vector(PORTS - 1 downto 0); + signal LLMux_In_Ack : std_logic_vector(PORTS - 1 downto 0); - signal LLMux_Out_Valid : STD_LOGIC; + signal LLMux_Out_Valid : std_logic; signal LLMux_Out_Data : T_SLV_8; - signal LLMux_Out_Meta : STD_LOGIC_VECTOR(META_BITS - 1 downto 0); - signal LLMux_Out_Meta_rev : STD_LOGIC_VECTOR(META_REV_BITS - 1 downto 0); - signal LLMux_Out_SOF : STD_LOGIC; - signal LLMux_Out_EOF : STD_LOGIC; - signal LLMux_Out_Ack : STD_LOGIC; + signal LLMux_Out_Meta : std_logic_vector(META_BITS - 1 downto 0); + signal LLMux_Out_Meta_rev : std_logic_vector(META_REV_BITS - 1 downto 0); + signal LLMux_Out_SOF : std_logic; + signal LLMux_Out_EOF : std_logic; + signal LLMux_Out_Ack : std_logic; - signal Is_DataFlow : STD_LOGIC; - signal Is_SOF : STD_LOGIC; - signal Is_EOF : STD_LOGIC; + signal Is_DataFlow : std_logic; + signal Is_SOF : std_logic; + signal Is_EOF : std_logic; begin @@ -124,7 +123,7 @@ begin In_Ack <= LLMux_In_Ack; genLLMuxIn : for i in 0 to PORTS - 1 generate - signal Meta : STD_LOGIC_VECTOR(META_BITS - 1 downto 0); + signal Meta : std_logic_vector(META_BITS - 1 downto 0); begin Meta(55 downto 48) <= In_Meta_DestMACAddress_Data(i); Meta(47 downto 0) <= to_slv(MAC_ADDRESSES(i)); diff --git a/src/net/mac/mac_Wrapper.vhdl b/src/net/mac/mac_Wrapper.vhdl index fc4b9c27..fcd42e3a 100644 --- a/src/net/mac/mac_Wrapper.vhdl +++ b/src/net/mac/mac_Wrapper.vhdl @@ -1,18 +1,17 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: TODO +-- Entity: TODO -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -27,7 +26,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -42,43 +41,43 @@ use PoC.net.all; entity mac_Wrapper is generic ( - DEBUG : BOOLEAN := FALSE; + DEBUG : boolean := FALSE; MAC_CONFIG : T_NET_MAC_CONFIGURATION_VECTOR ); port ( - Clock : in STD_LOGIC; - Reset : in STD_LOGIC; + Clock : in std_logic; + Reset : in std_logic; - Eth_TX_Valid : out STD_LOGIC; + Eth_TX_Valid : out std_logic; Eth_TX_Data : out T_SLV_8; - Eth_TX_SOF : out STD_LOGIC; - Eth_TX_EOF : out STD_LOGIC; - Eth_TX_Ack : in STD_LOGIC; + Eth_TX_SOF : out std_logic; + Eth_TX_EOF : out std_logic; + Eth_TX_Ack : in std_logic; - Eth_RX_Valid : in STD_LOGIC; + Eth_RX_Valid : in std_logic; Eth_RX_Data : in T_SLV_8; - Eth_RX_SOF : in STD_LOGIC; - Eth_RX_EOF : in STD_LOGIC; - Eth_RX_Ack : out STD_LOGIC; + Eth_RX_SOF : in std_logic; + Eth_RX_EOF : in std_logic; + Eth_RX_Ack : out std_logic; - TX_Valid : in STD_LOGIC_VECTOR(getPortCount(MAC_CONFIG) - 1 downto 0); + TX_Valid : in std_logic_vector(getPortCount(MAC_CONFIG) - 1 downto 0); TX_Data : in T_SLVV_8(getPortCount(MAC_CONFIG) - 1 downto 0); - TX_SOF : in STD_LOGIC_VECTOR(getPortCount(MAC_CONFIG) - 1 downto 0); - TX_EOF : in STD_LOGIC_VECTOR(getPortCount(MAC_CONFIG) - 1 downto 0); - TX_Ack : out STD_LOGIC_VECTOR(getPortCount(MAC_CONFIG) - 1 downto 0); - TX_Meta_rst : out STD_LOGIC_VECTOR(getPortCount(MAC_CONFIG) - 1 downto 0); - TX_Meta_DestMACAddress_nxt : out STD_LOGIC_VECTOR(getPortCount(MAC_CONFIG) - 1 downto 0); + TX_SOF : in std_logic_vector(getPortCount(MAC_CONFIG) - 1 downto 0); + TX_EOF : in std_logic_vector(getPortCount(MAC_CONFIG) - 1 downto 0); + TX_Ack : out std_logic_vector(getPortCount(MAC_CONFIG) - 1 downto 0); + TX_Meta_rst : out std_logic_vector(getPortCount(MAC_CONFIG) - 1 downto 0); + TX_Meta_DestMACAddress_nxt : out std_logic_vector(getPortCount(MAC_CONFIG) - 1 downto 0); TX_Meta_DestMACAddress_Data : in T_SLVV_8(getPortCount(MAC_CONFIG) - 1 downto 0); - RX_Valid : out STD_LOGIC_VECTOR(getPortCount(MAC_CONFIG) - 1 downto 0); + RX_Valid : out std_logic_vector(getPortCount(MAC_CONFIG) - 1 downto 0); RX_Data : out T_SLVV_8(getPortCount(MAC_CONFIG) - 1 downto 0); - RX_SOF : out STD_LOGIC_VECTOR(getPortCount(MAC_CONFIG) - 1 downto 0); - RX_EOF : out STD_LOGIC_VECTOR(getPortCount(MAC_CONFIG) - 1 downto 0); - RX_Ack : in STD_LOGIC_VECTOR(getPortCount(MAC_CONFIG) - 1 downto 0); - RX_Meta_rst : in STD_LOGIC_VECTOR(getPortCount(MAC_CONFIG) - 1 downto 0); - RX_Meta_SrcMACAddress_nxt : in STD_LOGIC_VECTOR(getPortCount(MAC_CONFIG) - 1 downto 0); + RX_SOF : out std_logic_vector(getPortCount(MAC_CONFIG) - 1 downto 0); + RX_EOF : out std_logic_vector(getPortCount(MAC_CONFIG) - 1 downto 0); + RX_Ack : in std_logic_vector(getPortCount(MAC_CONFIG) - 1 downto 0); + RX_Meta_rst : in std_logic_vector(getPortCount(MAC_CONFIG) - 1 downto 0); + RX_Meta_SrcMACAddress_nxt : in std_logic_vector(getPortCount(MAC_CONFIG) - 1 downto 0); RX_Meta_SrcMACAddress_Data : out T_SLVV_8(getPortCount(MAC_CONFIG) - 1 downto 0); - RX_Meta_DestMACAddress_nxt : in STD_LOGIC_VECTOR(getPortCount(MAC_CONFIG) - 1 downto 0); + RX_Meta_DestMACAddress_nxt : in std_logic_vector(getPortCount(MAC_CONFIG) - 1 downto 0); RX_Meta_DestMACAddress_Data : out T_SLVV_8(getPortCount(MAC_CONFIG) - 1 downto 0); RX_Meta_EthType : out T_NET_MAC_ETHERNETTYPE_VECTOR(getPortCount(MAC_CONFIG) - 1 downto 0) ); @@ -86,7 +85,7 @@ end entity; architecture rtl of mac_Wrapper is - function getInterfaceAddresses(MAC_CONFIG : T_NET_MAC_CONFIGURATION_VECTOR) return T_NET_MAC_ADDRESS_VECTOR IS + function getInterfaceAddresses(MAC_CONFIG : T_NET_MAC_CONFIGURATION_VECTOR) return T_NET_MAC_ADDRESS_VECTOR is variable temp : T_NET_MAC_ADDRESS_VECTOR(MAC_CONFIG'range); begin for i in MAC_CONFIG'range loop @@ -96,7 +95,7 @@ architecture rtl of mac_Wrapper is return temp; end function; - function getInterfaceMasks(MAC_CONFIG : T_NET_MAC_CONFIGURATION_VECTOR) return T_NET_MAC_ADDRESS_VECTOR IS + function getInterfaceMasks(MAC_CONFIG : T_NET_MAC_CONFIGURATION_VECTOR) return T_NET_MAC_ADDRESS_VECTOR is variable temp : T_NET_MAC_ADDRESS_VECTOR(MAC_CONFIG'range); begin for i in MAC_CONFIG'range loop @@ -106,11 +105,11 @@ architecture rtl of mac_Wrapper is return temp; end function; - function getSourceFilterCount(Interfaces : T_NET_MAC_INTERFACE_VECTOR) return NATURAL IS - variable count : NATURAL := 0; + function getSourceFilterCount(Interfaces : T_NET_MAC_INTERFACE_VECTOR) return natural is + variable count : natural := 0; begin for i in Interfaces'range loop - if ((Interfaces(i).Address /= C_NET_MAC_ADDRESS_EMPTY) OR (Interfaces(i).Mask /= C_NET_MAC_MASK_EMPTY)) then + if ((Interfaces(i).Address /= C_NET_MAC_ADDRESS_EMPTY) or (Interfaces(i).Mask /= C_NET_MAC_MASK_EMPTY)) then count := count + 1; end if; end loop; @@ -118,7 +117,7 @@ architecture rtl of mac_Wrapper is return count; end function; - function getSourceFilterAddresses(Interfaces : T_NET_MAC_INTERFACE_VECTOR) return T_NET_MAC_ADDRESS_VECTOR IS + function getSourceFilterAddresses(Interfaces : T_NET_MAC_INTERFACE_VECTOR) return T_NET_MAC_ADDRESS_VECTOR is variable temp : T_NET_MAC_ADDRESS_VECTOR(Interfaces'range); begin for i in Interfaces'range loop @@ -128,7 +127,7 @@ architecture rtl of mac_Wrapper is return temp; end function; - function getSourceFilterMasks(Interfaces : T_NET_MAC_INTERFACE_VECTOR) return T_NET_MAC_ADDRESS_VECTOR IS + function getSourceFilterMasks(Interfaces : T_NET_MAC_INTERFACE_VECTOR) return T_NET_MAC_ADDRESS_VECTOR is variable temp : T_NET_MAC_ADDRESS_VECTOR(Interfaces'range); begin for i in Interfaces'range loop @@ -138,8 +137,8 @@ architecture rtl of mac_Wrapper is return temp; end function; - function getTypeSwitchCount(Types : T_NET_MAC_ETHERNETTYPE_VECTOR) return NATURAL IS - variable count : NATURAL := 0; + function getTypeSwitchCount(Types : T_NET_MAC_ETHERNETTYPE_VECTOR) return natural is + variable count : natural := 0; begin for i in Types'range loop if (Types(i) /= C_NET_MAC_ETHERNETTYPE_EMPTY) then @@ -150,8 +149,8 @@ architecture rtl of mac_Wrapper is return count; end function; - function calcPortIndex(MAC_CONFIG : T_NET_MAC_CONFIGURATION_VECTOR; CurrentInterfaceID : NATURAL) return NATURAL IS - variable count : NATURAL := 0; + function calcPortIndex(MAC_CONFIG : T_NET_MAC_CONFIGURATION_VECTOR; CurrentInterfaceID : natural) return natural is + variable count : natural := 0; begin if (CurrentInterfaceID = 0) then return 0; @@ -165,39 +164,39 @@ architecture rtl of mac_Wrapper is end function; - constant PORTS : POSITIVE := getPortCount(MAC_CONFIG); - constant INTERFACE_COUNT : POSITIVE := MAC_CONFIG'length; + constant PORTS : positive := getPortCount(MAC_CONFIG); + constant INTERFACE_COUNT : positive := MAC_CONFIG'length; constant INTERFACE_ADDRESSES : T_NET_MAC_ADDRESS_VECTOR := getInterfaceAddresses(MAC_CONFIG); constant INTERFACE_MASKS : T_NET_MAC_ADDRESS_VECTOR := getInterfaceMasks(MAC_CONFIG); - signal DestEth_RX_Valid : STD_LOGIC_VECTOR(INTERFACE_COUNT - 1 downto 0); + signal DestEth_RX_Valid : std_logic_vector(INTERFACE_COUNT - 1 downto 0); signal DestEth_RX_Data : T_SLVV_8(INTERFACE_COUNT - 1 downto 0); - signal DestEth_RX_SOF : STD_LOGIC_VECTOR(INTERFACE_COUNT - 1 downto 0); - signal DestEth_RX_EOF : STD_LOGIC_VECTOR(INTERFACE_COUNT - 1 downto 0); + signal DestEth_RX_SOF : std_logic_vector(INTERFACE_COUNT - 1 downto 0); + signal DestEth_RX_EOF : std_logic_vector(INTERFACE_COUNT - 1 downto 0); signal DestEth_RX_Meta_DestMACAddress_Data : T_SLVV_8(INTERFACE_COUNT - 1 downto 0); - signal SrcEth_RX_Ack : STD_LOGIC_VECTOR(INTERFACE_COUNT - 1 downto 0); - signal SrcEth_RX_Meta_rst : STD_LOGIC_VECTOR(INTERFACE_COUNT - 1 downto 0); - signal SrcEth_RX_Meta_DestMACAddress_nxt : STD_LOGIC_VECTOR(INTERFACE_COUNT - 1 downto 0); + signal SrcEth_RX_Ack : std_logic_vector(INTERFACE_COUNT - 1 downto 0); + signal SrcEth_RX_Meta_rst : std_logic_vector(INTERFACE_COUNT - 1 downto 0); + signal SrcEth_RX_Meta_DestMACAddress_nxt : std_logic_vector(INTERFACE_COUNT - 1 downto 0); - signal EthType_TX_Valid : STD_LOGIC_VECTOR(INTERFACE_COUNT - 1 downto 0); + signal EthType_TX_Valid : std_logic_vector(INTERFACE_COUNT - 1 downto 0); signal EthType_TX_Data : T_SLVV_8(INTERFACE_COUNT - 1 downto 0); - signal EthType_TX_SOF : STD_LOGIC_VECTOR(INTERFACE_COUNT - 1 downto 0); - signal EthType_TX_EOF : STD_LOGIC_VECTOR(INTERFACE_COUNT - 1 downto 0); + signal EthType_TX_SOF : std_logic_vector(INTERFACE_COUNT - 1 downto 0); + signal EthType_TX_EOF : std_logic_vector(INTERFACE_COUNT - 1 downto 0); signal EthType_TX_Meta_DestMACAddress_Data : T_SLVV_8(INTERFACE_COUNT - 1 downto 0); - signal SrcEth_TX_Valid : STD_LOGIC; + signal SrcEth_TX_Valid : std_logic; signal SrcEth_TX_Data : T_SLV_8; - signal SrcEth_TX_SOF : STD_LOGIC; - signal SrcEth_TX_EOF : STD_LOGIC; - signal SrcEth_TX_Ack : STD_LOGIC_VECTOR(INTERFACE_COUNT - 1 downto 0); - signal SrcEth_TX_Meta_rst : STD_LOGIC_VECTOR(INTERFACE_COUNT - 1 downto 0); - signal SrcEth_TX_Meta_DestMACAddress_nxt : STD_LOGIC_VECTOR(INTERFACE_COUNT - 1 downto 0); + signal SrcEth_TX_SOF : std_logic; + signal SrcEth_TX_EOF : std_logic; + signal SrcEth_TX_Ack : std_logic_vector(INTERFACE_COUNT - 1 downto 0); + signal SrcEth_TX_Meta_rst : std_logic_vector(INTERFACE_COUNT - 1 downto 0); + signal SrcEth_TX_Meta_DestMACAddress_nxt : std_logic_vector(INTERFACE_COUNT - 1 downto 0); signal SrcEth_TX_Meta_DestMACAddress_Data : T_SLV_8; - signal DestEth_TX_Ack : STD_LOGIC; - signal DestEth_TX_Meta_rst : STD_LOGIC; - signal DestEth_TX_Meta_DestMACAddress_nxt : STD_LOGIC; + signal DestEth_TX_Ack : std_logic; + signal DestEth_TX_Meta_rst : std_logic; + signal DestEth_TX_Meta_DestMACAddress_nxt : std_logic; begin @@ -228,30 +227,30 @@ begin ); genInterface : for i in MAC_CONFIG'range generate - constant FILTER_COUNT : NATURAL := getSourceFilterCount(MAC_CONFIG(i).SourceFilter); + constant FILTER_COUNT : natural := getSourceFilterCount(MAC_CONFIG(i).SourceFilter); constant FILTER_ADDRESSES : T_NET_MAC_ADDRESS_VECTOR := getSourceFilterAddresses(MAC_CONFIG(i).SourceFilter(0 to FILTER_COUNT - 1)); constant FILTER_MASKS : T_NET_MAC_ADDRESS_VECTOR := getSourceFilterMasks(MAC_CONFIG(i).SourceFilter(0 to FILTER_COUNT - 1)); - constant SWITCH_COUNT : NATURAL := getTypeSwitchCount(MAC_CONFIG(i).TypeSwitch); + constant SWITCH_COUNT : natural := getTypeSwitchCount(MAC_CONFIG(i).TypeSwitch); constant SWITCH_TYPES : T_NET_MAC_ETHERNETTYPE_VECTOR := MAC_CONFIG(i).TypeSwitch(0 to SWITCH_COUNT - 1); - constant PORT_INDEX_FROM : NATURAL := calcPortIndex(MAC_CONFIG, i); - constant PORT_INDEX_TO : NATURAL := PORT_INDEX_FROM + SWITCH_COUNT - 1; + constant PORT_INDEX_FROM : natural := calcPortIndex(MAC_CONFIG, i); + constant PORT_INDEX_TO : natural := PORT_INDEX_FROM + SWITCH_COUNT - 1; - signal SrcEth_RX_Valid : STD_LOGIC; + signal SrcEth_RX_Valid : std_logic; signal SrcEth_RX_Data : T_SLV_8; - signal SrcEth_RX_SOF : STD_LOGIC; - signal SrcEth_RX_EOF : STD_LOGIC; + signal SrcEth_RX_SOF : std_logic; + signal SrcEth_RX_EOF : std_logic; -- signal SrcEth_RX_Meta_SrcMACAddress_rst : STD_LOGIC; -- signal SrcEth_RX_Meta_SrcMACAddress_nxt : STD_LOGIC; signal SrcEth_RX_Meta_DestMACAddress_Data : T_SLV_8; signal SrcEth_RX_Meta_SrcMACAddress_Data : T_SLV_8; - signal EthEth_RX_Ack : STD_LOGIC; - signal EthEth_RX_Meta_rst : STD_LOGIC; - signal EthEth_RX_Meta_DestMACAddress_nxt : STD_LOGIC; - signal EthEth_RX_Meta_SrcMACAddress_nxt : STD_LOGIC; + signal EthEth_RX_Ack : std_logic; + signal EthEth_RX_Meta_rst : std_logic; + signal EthEth_RX_Meta_DestMACAddress_nxt : std_logic; + signal EthEth_RX_Meta_SrcMACAddress_nxt : std_logic; begin -- assert FALSE report "Filter: Count=" & INTEGER'image(FILTER_COUNT) severity NOTE; diff --git a/src/net/net.pkg.vhdl b/src/net/net.pkg.vhdl index 3f6cce2f..96aa291b 100644 --- a/src/net/net.pkg.vhdl +++ b/src/net/net.pkg.vhdl @@ -1,18 +1,17 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: TODO +-- Entity: TODO -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -27,7 +26,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -92,46 +91,46 @@ package net is -- FPGA <=> PHY physical interface: GMII (Gigabit Media Independant Interface) type T_NET_ETH_PHY_INTERFACE_GMII is record - RX_RefClock : STD_LOGIC; + RX_RefClock : std_logic; - TX_Clock : STD_LOGIC; - TX_Valid : STD_LOGIC; + TX_Clock : std_logic; + TX_Valid : std_logic; TX_Data : T_SLV_8; - TX_Error : STD_LOGIC; + TX_Error : std_logic; - RX_Clock : STD_LOGIC; - RX_Valid : STD_LOGIC; + RX_Clock : std_logic; + RX_Valid : std_logic; RX_Data : T_SLV_8; - RX_Error : STD_LOGIC; + RX_Error : std_logic; end record; -- FPGA <=> PHY physical interface: RGMII (Reduced Gigabit Media Independant Interface) type T_NET_ETH_PHY_INTERFACE_RGMII is record - RX_RefClock : STD_LOGIC; + RX_RefClock : std_logic; - TX_Clock : STD_LOGIC; + TX_Clock : std_logic; TX_Data : T_SLV_4; - TX_Control : STD_LOGIC; + TX_Control : std_logic; - RX_Clock : STD_LOGIC; + RX_Clock : std_logic; RX_Data : T_SLV_4; - RX_Control : STD_LOGIC; + RX_Control : std_logic; end record; -- FPGA <=> PHY physical interface: SGMII (Serial GMII) type T_NET_ETH_PHY_INTERFACE_SGMII is record - DGB_SystemClock_In : STD_LOGIC; - DGB_AutoNeg_Restart : STD_LOGIC; + DGB_SystemClock_In : std_logic; + DGB_AutoNeg_Restart : std_logic; - SGMII_RefClock_In : STD_LOGIC; - SGMII_TXRefClock_Out : STD_LOGIC; - SGMII_RXRefClock_Out : STD_LOGIC; + SGMII_RefClock_In : std_logic; + SGMII_TXRefClock_Out : std_logic; + SGMII_RXRefClock_Out : std_logic; - TX_n : STD_LOGIC; - TX_p : STD_LOGIC; + TX_n : std_logic; + TX_p : std_logic; - RX_n : STD_LOGIC; - RX_p : STD_LOGIC; + RX_n : std_logic; + RX_p : std_logic; end record; -- FPGA <=> PHY management interface: MDIO (Management Data Input/Output) @@ -141,8 +140,8 @@ package net is end record; type T_NET_ETH_PHY_INTERFACE_COMMON is record - Reset : STD_LOGIC; - Interrupt : STD_LOGIC; + Reset : std_logic; + Interrupt : std_logic; end record; -- combined interface definition - union-types are still not supported in VHDL @@ -211,18 +210,18 @@ package net is -- ========================================================================================================================================================== -- Ethernet: ???????????????????? -- ========================================================================================================================================================== - function to_net_eth_RSDataInterface(str : STRING) return T_NET_ETH_RS_DATA_INTERFACE; - function to_net_eth_PHYDataInterface(str : STRING) return T_NET_ETH_PHY_DATA_INTERFACE; - function to_net_eth_PHYManagementInterface(str : STRING) return T_NET_ETH_PHY_MANAGEMENT_INTERFACE; - function to_net_eth_PHYDevice(str : STRING) return T_NET_ETH_PHY_DEVICE; + function to_net_eth_RSDataInterface(str : string) return T_NET_ETH_RS_DATA_INTERFACE; + function to_net_eth_PHYDataInterface(str : string) return T_NET_ETH_PHY_DATA_INTERFACE; + function to_net_eth_PHYManagementInterface(str : string) return T_NET_ETH_PHY_MANAGEMENT_INTERFACE; + function to_net_eth_PHYDevice(str : string) return T_NET_ETH_PHY_DEVICE; -- limitations - constant C_NET_ETH_PREMABLE_LENGTH : POSITIVE := 7; - constant C_NET_ETH_INTER_FRAME_GAP_LENGTH : POSITIVE := 12; - constant C_NET_ETH_MIN_FRAME_LENGTH : POSITIVE := 64; - constant C_NET_ETH_MAX_NORMALFRAME_LENGTH : POSITIVE := 1518; - constant C_NET_ETH_MAX_TAGGEDFRAME_LENGTH : POSITIVE := 1522; - constant C_NET_ETH_MAX_JUMBOFRAME_LENGTH : POSITIVE := 9018; + constant C_NET_ETH_PREMABLE_LENGTH : positive := 7; + constant C_NET_ETH_INTER_FRAME_GAP_LENGTH : positive := 12; + constant C_NET_ETH_MIN_FRAME_LENGTH : positive := 64; + constant C_NET_ETH_MAX_NORMALFRAME_LENGTH : positive := 1518; + constant C_NET_ETH_MAX_TAGGEDFRAME_LENGTH : positive := 1522; + constant C_NET_ETH_MAX_JUMBOFRAME_LENGTH : positive := 9018; -- ========================================================================================================================================================== -- Ethernet: MAC Data-Link-Layer @@ -232,8 +231,8 @@ package net is type T_NET_MAC_ETHERNETTYPE is array (1 downto 0) of T_SLV_8; -- arrays - type T_NET_MAC_ADDRESS_VECTOR is array (NATURAL range <>) of T_NET_MAC_ADDRESS; - type T_NET_MAC_ETHERNETTYPE_VECTOR is array (NATURAL range <>) of T_NET_MAC_ETHERNETTYPE; + type T_NET_MAC_ADDRESS_VECTOR is array (natural range <>) of T_NET_MAC_ADDRESS; + type T_NET_MAC_ETHERNETTYPE_VECTOR is array (natural range <>) of T_NET_MAC_ETHERNETTYPE; -- predefined constants constant C_NET_MAC_ADDRESS_EMPTY : T_NET_MAC_ADDRESS := (others => (others => '0')); @@ -245,17 +244,17 @@ package net is -- type conversion functions function to_net_mac_address(slv : T_SLV_48) return T_NET_MAC_ADDRESS; function to_net_mac_address(slvv : T_SLVV_8) return T_NET_MAC_ADDRESS; - function to_net_mac_address(str : STRING) return T_NET_MAC_ADDRESS; + function to_net_mac_address(str : string) return T_NET_MAC_ADDRESS; function to_net_mac_ethernettype(slv : T_SLV_16) return T_NET_MAC_ETHERNETTYPE; - function to_slv(mac : T_NET_MAC_ADDRESS) return STD_LOGIC_VECTOR; - function to_slv(Ethtype : T_NET_MAC_ETHERNETTYPE) return STD_LOGIC_VECTOR; + function to_slv(mac : T_NET_MAC_ADDRESS) return std_logic_vector; + function to_slv(Ethtype : T_NET_MAC_ETHERNETTYPE) return std_logic_vector; function to_slvv_8(mac : T_NET_MAC_ADDRESS) return T_SLVV_8; function to_slvv_8(Ethtype : T_NET_MAC_ETHERNETTYPE) return T_SLVV_8; - function to_string(mac : T_NET_MAC_ADDRESS) return STRING; - function to_string(Ethtype : T_NET_MAC_ETHERNETTYPE) return STRING; + function to_string(mac : T_NET_MAC_ADDRESS) return string; + function to_string(Ethtype : T_NET_MAC_ETHERNETTYPE) return string; -- ========================================================================================================================================================== -- ETH_Wrapper: configuration data structures @@ -265,7 +264,7 @@ package net is Mask : T_NET_MAC_ADDRESS; end record; - type T_NET_MAC_INTERFACE_VECTOR is array(NATURAL range <>) of T_NET_MAC_INTERFACE; + type T_NET_MAC_INTERFACE_VECTOR is array(natural range <>) of T_NET_MAC_INTERFACE; constant C_NET_MAC_SOURCEFILTER_NONE : T_NET_MAC_INTERFACE := (Address => to_net_mac_address("00:00:00:00:00:01"), Mask => C_NET_MAC_MASK_EMPTY); @@ -276,10 +275,10 @@ package net is end record; -- arrays - type T_NET_MAC_CONFIGURATION_VECTOR is array(NATURAL range <>) of T_NET_MAC_CONFIGURATION; + type T_NET_MAC_CONFIGURATION_VECTOR is array(natural range <>) of T_NET_MAC_CONFIGURATION; -- functions - function getPortCount(MACConfiguration : T_NET_MAC_CONFIGURATION_VECTOR) return POSITIVE; + function getPortCount(MACConfiguration : T_NET_MAC_CONFIGURATION_VECTOR) return positive; -- ========================================================================================================================================================== -- local network: sequence and flow control protocol (SFC) @@ -288,7 +287,7 @@ package net is subtype T_NET_MAC_SFC_TYPE is T_SLV_16; -- arrays - type T_ETH_SFC_TYPE_VECTOR is array (NATURAL range <>) of T_NET_MAC_SFC_TYPE; + type T_ETH_SFC_TYPE_VECTOR is array (natural range <>) of T_NET_MAC_SFC_TYPE; -- predefined constants constant C_NET_MAC_SFC_TYPE_EMPTY : T_NET_MAC_SFC_TYPE := (others => '0'); @@ -305,19 +304,19 @@ package net is -- types type T_NET_IPV4_ADDRESS is array (3 downto 0) of T_SLV_8; subtype T_NET_IPV4_PROTOCOL is T_NET_IP_PROTOCOL; - subtype T_NET_IPV4_TOS_PRECEDENCE is STD_LOGIC_VECTOR(2 downto 0); + subtype T_NET_IPV4_TOS_PRECEDENCE is std_logic_vector(2 downto 0); type T_NET_IPV4_TYPE_OF_SERVICE is record Precedence : T_NET_IPV4_TOS_PRECEDENCE; - Delay : STD_LOGIC; - Throughput : STD_LOGIC; - Relibility : STD_LOGIC; + Delay : std_logic; + Throughput : std_logic; + Relibility : std_logic; end record; -- arrays - type T_NET_IPV4_ADDRESS_VECTOR is array (NATURAL range <>) of T_NET_IPV4_ADDRESS; - type T_NET_IPV4_PROTOCOL_VECTOR is array (NATURAL range <>) of T_NET_IPV4_PROTOCOL; - type T_NET_IPV4_TYPE_OF_SERVICE_VECTOR is array (NATURAL range <>) of T_NET_IPV4_TYPE_OF_SERVICE; + type T_NET_IPV4_ADDRESS_VECTOR is array (natural range <>) of T_NET_IPV4_ADDRESS; + type T_NET_IPV4_PROTOCOL_VECTOR is array (natural range <>) of T_NET_IPV4_PROTOCOL; + type T_NET_IPV4_TYPE_OF_SERVICE_VECTOR is array (natural range <>) of T_NET_IPV4_TYPE_OF_SERVICE; -- predefined constants constant C_NET_IPV4_ADDRESS_EMPTY : T_NET_IPV4_ADDRESS := (others => (others => '0')); @@ -336,16 +335,16 @@ package net is -- type conversion functions function to_net_ipv4_address(slv : T_SLV_32) return T_NET_IPV4_ADDRESS; - function to_net_ipv4_address(str : STRING) return T_NET_IPV4_ADDRESS; + function to_net_ipv4_address(str : string) return T_NET_IPV4_ADDRESS; function to_net_ipv4_TYPE_of_service(slv : T_SLV_8) return T_NET_IPV4_TYPE_OF_SERVICE; - function to_slv(ip : T_NET_IPV4_ADDRESS) return STD_LOGIC_VECTOR; + function to_slv(ip : T_NET_IPV4_ADDRESS) return std_logic_vector; -- function to_slv(proto : T_NET_IPV4_PROTOCOL) return STD_LOGIC_VECTOR; - function to_slv(tos : T_NET_IPV4_TYPE_OF_SERVICE) return STD_LOGIC_VECTOR; + function to_slv(tos : T_NET_IPV4_TYPE_OF_SERVICE) return std_logic_vector; function to_slvv_8(ip : T_NET_IPV4_ADDRESS) return T_SLVV_8; - function to_string(ip : T_NET_IPV4_ADDRESS) return STRING; + function to_string(ip : T_NET_IPV4_ADDRESS) return string; -- ========================================================================================================================================================== -- internet layer: Internet Protocol Version 6 (IPv6) @@ -354,14 +353,14 @@ package net is type T_NET_IPV6_ADDRESS is array (15 downto 0) of T_SLV_8; type T_NET_IPV6_PREFIX is record Prefix : T_NET_IPV6_ADDRESS; - PrefixLength : STD_LOGIC_VECTOR(6 downto 0); + PrefixLength : std_logic_vector(6 downto 0); end record; subtype T_NET_IPV6_NEXT_HEADER is T_NET_IP_PROTOCOL; -- arrays - type T_NET_IPV6_ADDRESS_VECTOR is array (NATURAL range <>) of T_NET_IPV6_ADDRESS; - type T_NET_IPV6_PREFIX_VECTOR is array (NATURAL range <>) of T_NET_IPV6_PREFIX; - type T_NET_IPV6_NEXT_HEADER_VECTOR is array (NATURAL range <>) of T_NET_IPV6_NEXT_HEADER; + type T_NET_IPV6_ADDRESS_VECTOR is array (natural range <>) of T_NET_IPV6_ADDRESS; + type T_NET_IPV6_PREFIX_VECTOR is array (natural range <>) of T_NET_IPV6_PREFIX; + type T_NET_IPV6_NEXT_HEADER_VECTOR is array (natural range <>) of T_NET_IPV6_NEXT_HEADER; -- predefined constants constant C_NET_IPV6_ADDRESS_EMPTY : T_NET_IPV6_ADDRESS := (others => (others => '0')); @@ -369,14 +368,14 @@ package net is -- type conversion functions function to_net_ipv6_address(slv : T_SLV_128) return T_NET_IPV6_ADDRESS; - function to_net_ipv6_address(str : STRING) return T_NET_IPV6_ADDRESS; - function to_net_ipv6_prefix(str : STRING) return T_NET_IPV6_PREFIX; + function to_net_ipv6_address(str : string) return T_NET_IPV6_ADDRESS; + function to_net_ipv6_prefix(str : string) return T_NET_IPV6_PREFIX; - function to_slv(ip : T_NET_IPV6_ADDRESS) return STD_LOGIC_VECTOR; + function to_slv(ip : T_NET_IPV6_ADDRESS) return std_logic_vector; function to_slvv_8(ip : T_NET_IPV6_ADDRESS) return T_SLVV_8; - function to_string(IP : T_NET_IPV6_ADDRESS) return STRING; - function to_string(Prefix : T_NET_IPV6_PREFIX) return STRING; + function to_string(IP : T_NET_IPV6_ADDRESS) return string; + function to_string(Prefix : T_NET_IPV6_PREFIX) return string; -- ========================================================================================================================================================== -- internet layer: Address Resolution Protocol (ARP) @@ -409,7 +408,7 @@ package net is MAC : T_NET_MAC_ADDRESS; end record; - type T_NET_ARP_ARPCACHE_VECTOR is array (NATURAL range <>) of T_NET_ARP_ARPCACHE_LINE; + type T_NET_ARP_ARPCACHE_VECTOR is array (natural range <>) of T_NET_ARP_ARPCACHE_LINE; -- commands type T_NET_ARP_TESTER_COMMAND is ( @@ -511,8 +510,8 @@ package net is MAC : T_NET_MAC_ADDRESS; end record; - type T_NET_NDP_DESTINATIONCACHE_VECTOR is array (NATURAL range <>) of T_NET_NDP_DESTINATIONCACHE_LINE; - type T_NET_NDP_NEIGHBORCACHE_VECTOR is array (NATURAL range <>) of T_NET_NDP_NEIGHBORCACHE_LINE; + type T_NET_NDP_DESTINATIONCACHE_VECTOR is array (natural range <>) of T_NET_NDP_DESTINATIONCACHE_LINE; + type T_NET_NDP_NEIGHBORCACHE_VECTOR is array (natural range <>) of T_NET_NDP_NEIGHBORCACHE_LINE; type T_NET_NDP_REACHABILITY_STATE is ( NET_NDP_REACHABILITY_STATE_UNKNOWN, @@ -534,7 +533,7 @@ package net is Egress : T_NET_UDP_PORT; -- outgoing port number end record; - type T_NET_UDP_PORTPAIR_VECTOR is array(NATURAL range <>) of T_NET_UDP_PORTPAIR; + type T_NET_UDP_PORTPAIR_VECTOR is array(natural range <>) of T_NET_UDP_PORTPAIR; -- ========================================================================================================================================================== @@ -678,7 +677,7 @@ end package; package body net is - function to_net_eth_RSDataInterface(str : STRING) return T_NET_ETH_RS_DATA_INTERFACE is + function to_net_eth_RSDataInterface(str : string) return T_NET_ETH_RS_DATA_INTERFACE is begin for i in T_NET_ETH_RS_DATA_INTERFACE'pos(T_NET_ETH_RS_DATA_INTERFACE'low) to T_NET_ETH_RS_DATA_INTERFACE'pos(T_NET_ETH_RS_DATA_INTERFACE'high) loop if str_match(str_toUpper(str), str_toUpper(T_NET_ETH_RS_DATA_INTERFACE'image(T_NET_ETH_RS_DATA_INTERFACE'val(i)))) then @@ -688,7 +687,7 @@ package body net is report "Unknown RS_DATA_INTERFACE: " & str severity FAILURE; end function; - function to_net_eth_PHYDataInterface(str : STRING) return T_NET_ETH_PHY_DATA_INTERFACE is + function to_net_eth_PHYDataInterface(str : string) return T_NET_ETH_PHY_DATA_INTERFACE is begin for i in T_NET_ETH_PHY_DATA_INTERFACE'pos(T_NET_ETH_PHY_DATA_INTERFACE'low) to T_NET_ETH_PHY_DATA_INTERFACE'pos(T_NET_ETH_PHY_DATA_INTERFACE'high) loop if str_match(str_toUpper(str), str_toUpper(T_NET_ETH_PHY_DATA_INTERFACE'image(T_NET_ETH_PHY_DATA_INTERFACE'val(i)))) then @@ -698,7 +697,7 @@ package body net is report "Unknown PHY_DATA_INTERFACE: " & str severity FAILURE; end function; - function to_net_eth_PHYManagementInterface(str : STRING) return T_NET_ETH_PHY_MANAGEMENT_INTERFACE is + function to_net_eth_PHYManagementInterface(str : string) return T_NET_ETH_PHY_MANAGEMENT_INTERFACE is begin for i in T_NET_ETH_PHY_MANAGEMENT_INTERFACE'pos(T_NET_ETH_PHY_MANAGEMENT_INTERFACE'low) to T_NET_ETH_PHY_MANAGEMENT_INTERFACE'pos(T_NET_ETH_PHY_MANAGEMENT_INTERFACE'high) loop if str_match(str_toUpper(str), str_toUpper(T_NET_ETH_PHY_MANAGEMENT_INTERFACE'image(T_NET_ETH_PHY_MANAGEMENT_INTERFACE'val(i)))) then @@ -708,7 +707,7 @@ package body net is report "Unknown PHY_MANAGEMENT_INTERFACE: " & str severity FAILURE; end function; - function to_net_eth_PHYDevice(str : STRING) return T_NET_ETH_PHY_DEVICE is + function to_net_eth_PHYDevice(str : string) return T_NET_ETH_PHY_DEVICE is begin for i in T_NET_ETH_PHY_DEVICE'pos(T_NET_ETH_PHY_DEVICE'low) to T_NET_ETH_PHY_DEVICE'pos(T_NET_ETH_PHY_DEVICE'high) loop if str_match(str_toUpper(str), str_toUpper(T_NET_ETH_PHY_DEVICE'image(T_NET_ETH_PHY_DEVICE'val(i)))) then @@ -719,8 +718,8 @@ package body net is end function; - function getPortCount(MACConfiguration : T_NET_MAC_CONFIGURATION_VECTOR) return POSITIVE is - variable count : NATURAL := 0; + function getPortCount(MACConfiguration : T_NET_MAC_CONFIGURATION_VECTOR) return positive is + variable count : natural := 0; begin for i in MACConfiguration'range loop for j in MACConfiguration(i).TypeSwitch'range loop @@ -748,21 +747,21 @@ package body net is function to_net_mac_address(slvv : T_SLVV_8) return T_NET_MAC_ADDRESS is variable mac : T_NET_MAC_ADDRESS; begin - if (slvv'length /= 6) then report "to_net_mac_address: vector-length mismatch - slvv'length=" & INTEGER'image(slvv'length) severity ERROR; end if; + if (slvv'length /= 6) then report "to_net_mac_address: vector-length mismatch - slvv'length=" & integer'image(slvv'length) severity ERROR; end if; for i in slvv'range loop mac(i) := slvv(i); end loop; return mac; end function; - subtype MAC_ADDRESS_SEGMENT is STRING(1 to 2); - type MAC_ADDRESS_SEGMENT_VECTOR is array (NATURAL range <>) of MAC_ADDRESS_SEGMENT; + subtype MAC_ADDRESS_SEGMENT is string(1 to 2); + type MAC_ADDRESS_SEGMENT_VECTOR is array (natural range <>) of MAC_ADDRESS_SEGMENT; - function mac_split(str : STRING) return MAC_ADDRESS_SEGMENT_VECTOR is - variable input : STRING(str'range) := str_toUpper(str); + function mac_split(str : string) return MAC_ADDRESS_SEGMENT_VECTOR is + variable input : string(str'range) := str_toUpper(str); variable Segments : MAC_ADDRESS_SEGMENT_VECTOR(0 to 5) := (others => (others => '0')); - variable SegmentPointer : NATURAL := 0; - variable CharPointer : NATURAL := 2; + variable SegmentPointer : natural := 0; + variable CharPointer : natural := 2; begin -- report "mac_split of " & str severity NOTE; for i in str'reverse_range loop @@ -771,7 +770,7 @@ package body net is Segments(SegmentPointer)(CharPointer) := input(i); -- report " copy to seg=" & INTEGER'image(SegmentPointer) & " pos=" & INTEGER'image(CharPointer) severity NOTE; CharPointer := CharPointer - 1; - elsif ((input(i) = ':') OR (input(i) = '-')) then + elsif ((input(i) = ':') or (input(i) = '-')) then SegmentPointer := SegmentPointer + 1; CharPointer := 2; else @@ -784,7 +783,7 @@ package body net is -- converts MAC address strings to T_NET_MAC_ADDRESS -- allowed delimiter signs: ':' or '-' - function to_net_mac_address(str : STRING) return T_NET_MAC_ADDRESS is + function to_net_mac_address(str : string) return T_NET_MAC_ADDRESS is variable Segments : MAC_ADDRESS_SEGMENT_VECTOR(0 to 5) := mac_split(str); variable MAC : T_NET_MAC_ADDRESS; begin @@ -803,7 +802,7 @@ package body net is return EthType; end function; - function to_slv(mac : T_NET_MAC_ADDRESS) return STD_LOGIC_VECTOR is + function to_slv(mac : T_NET_MAC_ADDRESS) return std_logic_vector is variable slv : T_SLV_48; begin for i in 0 to 5 loop @@ -812,7 +811,7 @@ package body net is return slv; end function; - function to_slv(EthType : T_NET_MAC_ETHERNETTYPE) return STD_LOGIC_VECTOR is + function to_slv(EthType : T_NET_MAC_ETHERNETTYPE) return std_logic_vector is variable slv : T_SLV_16; begin for i in 0 to 1 loop @@ -839,8 +838,8 @@ package body net is return slvv; end function; - function to_string(mac : T_NET_MAC_ADDRESS) return STRING is - variable str : STRING(1 to 18) := (others => ':'); + function to_string(mac : T_NET_MAC_ADDRESS) return string is + variable str : string(1 to 18) := (others => ':'); begin for i in 0 to 5 loop str((i * 3) + 1 to (i * 3) + 2) := to_string(mac(5 - i), 'h'); @@ -848,7 +847,7 @@ package body net is return str(1 to 17); end function; - function to_string(EthType : T_NET_MAC_ETHERNETTYPE) return STRING is + function to_string(EthType : T_NET_MAC_ETHERNETTYPE) return string is begin -- TODO: replace this case-statement by substring(image(EthType), 10,0) case to_slv(EthType) is @@ -881,14 +880,14 @@ package body net is return ip; end function; - subtype IPV4_ADDRESS_SEGMENT is STRING(1 to 3); - type IPV4_ADDRESS_SEGMENT_VECTOR is array (NATURAL range <>) of IPV4_ADDRESS_SEGMENT; + subtype IPV4_ADDRESS_SEGMENT is string(1 to 3); + type IPV4_ADDRESS_SEGMENT_VECTOR is array (natural range <>) of IPV4_ADDRESS_SEGMENT; - function ipv4_split(str : STRING) return IPV4_ADDRESS_SEGMENT_VECTOR is - variable input : STRING(str'range) := str_toUpper(str); + function ipv4_split(str : string) return IPV4_ADDRESS_SEGMENT_VECTOR is + variable input : string(str'range) := str_toUpper(str); variable Segments : IPV4_ADDRESS_SEGMENT_VECTOR(0 to 3) := (others => (others => '0')); - variable SegmentPointer : NATURAL := 0; - variable CharPointer : NATURAL := 3; + variable SegmentPointer : natural := 0; + variable CharPointer : natural := 3; begin -- report "ipv4_split of " & str severity NOTE; for i in str'reverse_range loop @@ -910,7 +909,7 @@ package body net is -- converts MAC address strings to T_NET_MAC_ADDRESS -- allowed delimiter sign: '.' - function to_net_ipv4_address(str : STRING) return T_NET_IPV4_ADDRESS is + function to_net_ipv4_address(str : string) return T_NET_IPV4_ADDRESS is variable Segments : IPV4_ADDRESS_SEGMENT_VECTOR(0 to 3) := ipv4_split(str); variable Segment : T_SLV_8; variable IP : T_NET_IPV4_ADDRESS; @@ -931,7 +930,7 @@ package body net is return tos; end function; - function to_slv(ip : T_NET_IPV4_ADDRESS) return STD_LOGIC_VECTOR is + function to_slv(ip : T_NET_IPV4_ADDRESS) return std_logic_vector is variable slv : T_SLV_32; begin for i in 0 to 3 loop @@ -947,7 +946,7 @@ package body net is -- return slv; -- end function; - function to_slv(tos : T_NET_IPV4_TYPE_OF_SERVICE) return STD_LOGIC_VECTOR is + function to_slv(tos : T_NET_IPV4_TYPE_OF_SERVICE) return std_logic_vector is variable slv : T_SLV_8; begin slv(2 downto 0) := tos.Precedence; @@ -967,18 +966,18 @@ package body net is return slvv; end function; - function to_string(IP : T_NET_IPV4_ADDRESS) return STRING is - variable temp : STRING(1 to 16) := (others => '.'); - variable str : STRING(1 to 3); - variable len : POSITIVE; - variable CharPointer : NATURAL := 1; + function to_string(IP : T_NET_IPV4_ADDRESS) return string is + variable temp : string(1 to 16) := (others => '.'); + variable str : string(1 to 3); + variable len : positive; + variable CharPointer : natural := 1; begin -- report "converting IPv4 address" severity NOTE; for i in 3 downto 0 loop -- report " I=" & INTEGER'image(i) & " IP(i)=" & INTEGER'image(to_integer(unsigned(IP(i)))) & " CP=" & INTEGER'image(CharPointer) severity NOTE; - str := resize(INTEGER'image(to_integer(unsigned(IP(i)))), str'length); + str := resize(integer'image(to_integer(unsigned(IP(i)))), str'length); len := str_length(str); temp(CharPointer to CharPointer + len - 1) := str(1 to len); CharPointer := CharPointer + len + 1; @@ -1000,16 +999,16 @@ package body net is return ip; end function; - subtype IPV6_ADDRESS_SEGMENT is STRING(1 to 4); - type IPV6_ADDRESS_SEGMENT_VECTOR is array (NATURAL range <>) of IPV6_ADDRESS_SEGMENT; + subtype IPV6_ADDRESS_SEGMENT is string(1 to 4); + type IPV6_ADDRESS_SEGMENT_VECTOR is array (natural range <>) of IPV6_ADDRESS_SEGMENT; - function ipv6_split(str : STRING) return IPV6_ADDRESS_SEGMENT_VECTOR is - variable input : STRING(str'range) := str_toUpper(str); + function ipv6_split(str : string) return IPV6_ADDRESS_SEGMENT_VECTOR is + variable input : string(str'range) := str_toUpper(str); variable Segments : IPV6_ADDRESS_SEGMENT_VECTOR(0 to 7) := (others => (others => '0')); - variable DelimiterPointer : NATURAL := 0; - variable SegmentPointer : NATURAL := 0; - variable CharPointer : NATURAL := 4; - variable RemainingDelimiters : NATURAL := 0; + variable DelimiterPointer : natural := 0; + variable SegmentPointer : natural := 0; + variable CharPointer : natural := 4; + variable RemainingDelimiters : natural := 0; begin -- report "ipv6_split of " & str severity NOTE; @@ -1045,7 +1044,7 @@ package body net is return Segments; end function; - function to_net_ipv6_address(str : STRING) return T_NET_IPV6_ADDRESS is + function to_net_ipv6_address(str : string) return T_NET_IPV6_ADDRESS is variable Segments : IPV6_ADDRESS_SEGMENT_VECTOR(0 to 7) := ipv6_split(str); variable Segment : T_SLV_16; variable IP : T_NET_IPV6_ADDRESS; @@ -1058,33 +1057,33 @@ package body net is return IP; end function; - function to_net_ipv6_prefix(str : STRING) return T_NET_IPV6_PREFIX is - variable Pos : POSITIVE; + function to_net_ipv6_prefix(str : string) return T_NET_IPV6_PREFIX is + variable Pos : positive; variable Prefix : T_NET_IPV6_PREFIX; variable IPv6Address : T_NET_IPV6_ADDRESS; - variable Len : NATURAL; + variable Len : natural; begin for i in str'reverse_range loop if (str(i) = '/') then Pos := i; - EXIT; + exit; end if; end loop; if (Pos = str'high) then report "syntax error in IPv6 prefix: " & str severity ERROR; end if; IPv6Address := to_net_ipv6_address(str(str'low to Pos - 1)); - Len := INTEGER'value(str(Pos + 1 to str'high)); + Len := integer'value(str(Pos + 1 to str'high)); - if (NOT ((0 < Len) AND (Len < 128))) then report "IPv6 prefix length is out of range: IPv6=" & str & " Length=" & INTEGER'image(Len) severity ERROR; end if; - if ((to_slv(IPv6Address) AND genmask_low(128 - Len, 128)) /= (127 downto 0 => '0')) then report "IPv6 prefix is longer then it's mask: IPv6=" & str severity ERROR; end if; + if (not ((0 < Len) and (Len < 128))) then report "IPv6 prefix length is out of range: IPv6=" & str & " Length=" & integer'image(Len) severity ERROR; end if; + if ((to_slv(IPv6Address) and genmask_low(128 - Len, 128)) /= (127 downto 0 => '0')) then report "IPv6 prefix is longer then it's mask: IPv6=" & str severity ERROR; end if; Prefix.Prefix := IPv6Address; Prefix.PrefixLength := to_slv(Len, Prefix.PrefixLength'length); return Prefix; end function; - function to_slv(ip : T_NET_IPV6_ADDRESS) return STD_LOGIC_VECTOR is + function to_slv(ip : T_NET_IPV6_ADDRESS) return std_logic_vector is variable slv : T_SLV_128; begin for i in 0 to 15 loop @@ -1102,12 +1101,12 @@ package body net is return slvv; end function; - function to_string(IP : T_NET_IPV6_ADDRESS) return STRING is - variable temp : STRING(1 to 40) := (others => ':'); - variable CharPointer : NATURAL := 1; - variable Char : CHARACTER; + function to_string(IP : T_NET_IPV6_ADDRESS) return string is + variable temp : string(1 to 40) := (others => ':'); + variable CharPointer : natural := 1; + variable Char : character; - variable copy : BOOLEAN := FALSE; + variable copy : boolean := FALSE; begin for i in 7 downto 0 loop temp(CharPointer + 0 to CharPointer + 1) := to_string(IP((i * 2) + 1), 'h'); @@ -1122,8 +1121,8 @@ package body net is -- report " I=" & INTEGER'image(i) & " char=" & temp(i) & " CP=" & INTEGER'image(CharPointer) & " copy=" & to_string(copy) severity NOTE; if (copy = FALSE) then - if ((temp(i) = '0') AND (temp(i + 1) /= ':')) then - NULL; + if ((temp(i) = '0') and (temp(i + 1) /= ':')) then + null; else temp(CharPointer) := temp(i); CharPointer := CharPointer + 1; @@ -1141,7 +1140,7 @@ package body net is return temp(1 to CharPointer - 2); end function; - function to_string(Prefix : T_NET_IPV6_PREFIX) return STRING is + function to_string(Prefix : T_NET_IPV6_PREFIX) return string is begin return to_string(Prefix.Prefix) & "/" & to_string(Prefix.PrefixLength, 'd'); end function; diff --git a/src/net/net_FrameChecksum.vhdl b/src/net/net_FrameChecksum.vhdl index 17b33462..c63d632a 100644 --- a/src/net/net_FrameChecksum.vhdl +++ b/src/net/net_FrameChecksum.vhdl @@ -1,18 +1,17 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: TODO +-- Entity: TODO -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -27,7 +26,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -41,32 +40,32 @@ use PoC.vectors.all; entity net_FrameChecksum is generic ( - MAX_FRAMES : POSITIVE := 8; - MAX_FRAME_LENGTH : POSITIVE := 2048; + MAX_FRAMES : positive := 8; + MAX_FRAME_LENGTH : positive := 2048; META_BITS : T_POSVEC := (0 => 8); META_FIFO_DEPTH : T_POSVEC := (0 => 16) ); port ( - Clock : in STD_LOGIC; - Reset : in STD_LOGIC; + Clock : in std_logic; + Reset : in std_logic; -- IN port - In_Valid : in STD_LOGIC; + In_Valid : in std_logic; In_Data : in T_SLV_8; - In_SOF : in STD_LOGIC; - In_EOF : in STD_LOGIC; - In_Ack : out STD_LOGIC; - In_Meta_rst : out STD_LOGIC; - In_Meta_nxt : out STD_LOGIC_VECTOR(META_BITS'length - 1 downto 0); - In_Meta_Data : in STD_LOGIC_VECTOR(isum(META_BITS) - 1 downto 0); + In_SOF : in std_logic; + In_EOF : in std_logic; + In_Ack : out std_logic; + In_Meta_rst : out std_logic; + In_Meta_nxt : out std_logic_vector(META_BITS'length - 1 downto 0); + In_Meta_Data : in std_logic_vector(isum(META_BITS) - 1 downto 0); -- OUT port - Out_Valid : out STD_LOGIC; + Out_Valid : out std_logic; Out_Data : out T_SLV_8; - Out_SOF : out STD_LOGIC; - Out_EOF : out STD_LOGIC; - Out_Ack : in STD_LOGIC; - Out_Meta_rst : in STD_LOGIC; - Out_Meta_nxt : in STD_LOGIC_VECTOR(META_BITS'length - 1 downto 0); - Out_Meta_Data : out STD_LOGIC_VECTOR(isum(META_BITS) - 1 downto 0); + Out_SOF : out std_logic; + Out_EOF : out std_logic; + Out_Ack : in std_logic; + Out_Meta_rst : in std_logic; + Out_Meta_nxt : in std_logic_vector(META_BITS'length - 1 downto 0); + Out_Meta_Data : out std_logic_vector(isum(META_BITS) - 1 downto 0); Out_Meta_Length : out T_SLV_16; Out_Meta_Checksum : out T_SLV_16 ); @@ -75,11 +74,11 @@ end entity; -- FIXME: review writer-FSM: check full signals => block incoming words/frames if datafifo or metafifo is full architecture rtl of net_FrameChecksum is - attribute FSM_ENCODING : STRING; + attribute FSM_ENCODING : string; - type T_WRITER_STATE IS (ST_IDLE, ST_FRAME, ST_CARRY_1, ST_CARRY_2); - type T_METAWRITER_STATE IS (ST_IDLE, ST_METADATA); - type T_READER_STATE IS (ST_IDLE, ST_FRAME); + type T_WRITER_STATE is (ST_IDLE, ST_FRAME, ST_CARRY_1, ST_CARRY_2); + type T_METAWRITER_STATE is (ST_IDLE, ST_METADATA); + type T_READER_STATE is (ST_IDLE, ST_FRAME); signal Writer_State : T_WRITER_STATE := ST_IDLE; signal Writer_NextState : T_WRITER_STATE; @@ -88,44 +87,44 @@ architecture rtl of net_FrameChecksum is signal Reader_State : T_READER_STATE := ST_IDLE; signal Reader_NextState : T_READER_STATE; - signal Checksum_rst : STD_LOGIC; - signal Checksum_en : STD_LOGIC; - signal Checksum_Data_us : UNSIGNED(In_Data'range); - signal Checksum0_nxt_us : UNSIGNED(In_Data'length downto 0); - signal Checksum0_d_us : UNSIGNED(In_Data'length downto 0) := (others => '0'); - signal Checksum0_nxt_cy : STD_LOGIC; - signal Checksum1_nxt_us : UNSIGNED(In_Data'range); - signal Checksum1_d_us : UNSIGNED(In_Data'range) := (others => '0'); + signal Checksum_rst : std_logic; + signal Checksum_en : std_logic; + signal Checksum_Data_us : unsigned(In_Data'range); + signal Checksum0_nxt_us : unsigned(In_Data'length downto 0); + signal Checksum0_d_us : unsigned(In_Data'length downto 0) := (others => '0'); + signal Checksum0_nxt_cy : std_logic; + signal Checksum1_nxt_us : unsigned(In_Data'range); + signal Checksum1_d_us : unsigned(In_Data'range) := (others => '0'); signal Checksum : T_SLV_16; - constant WORDCOUNTER_BITS : POSITIVE := log2ceilnz(MAX_FRAME_LENGTH); - signal WordCounter_rst : STD_LOGIC; - signal WordCounter_en : STD_LOGIC; - signal WordCounter_us : UNSIGNED(WORDCOUNTER_BITS - 1 downto 0) := to_unsigned(1, log2ceilnz(MAX_FRAME_LENGTH)); - signal WordCount : STD_LOGIC_VECTOR(WORDCOUNTER_BITS + 15 downto 16); + constant WORDCOUNTER_BITS : positive := log2ceilnz(MAX_FRAME_LENGTH); + signal WordCounter_rst : std_logic; + signal WordCounter_en : std_logic; + signal WordCounter_us : unsigned(WORDCOUNTER_BITS - 1 downto 0) := to_unsigned(1, log2ceilnz(MAX_FRAME_LENGTH)); + signal WordCount : std_logic_vector(WORDCOUNTER_BITS + 15 downto 16); - signal FrameCommit : STD_LOGIC; + signal FrameCommit : std_logic; - constant DATA_BITS : POSITIVE := 8; - constant EOF_BIT : NATURAL := DATA_BITS; + constant DATA_BITS : positive := 8; + constant EOF_BIT : natural := DATA_BITS; - signal DataFIFO_put : STD_LOGIC; - signal DataFIFO_DataIn : STD_LOGIC_VECTOR(DATA_BITS downto 0); - signal DataFIFO_Full : STD_LOGIC; - signal DataFIFO_got : STD_LOGIC; - signal DataFIFO_DataOut : STD_LOGIC_VECTOR(DATA_BITS downto 0); - signal DataFIFO_Valid : STD_LOGIC; + signal DataFIFO_put : std_logic; + signal DataFIFO_DataIn : std_logic_vector(DATA_BITS downto 0); + signal DataFIFO_Full : std_logic; + signal DataFIFO_got : std_logic; + signal DataFIFO_DataOut : std_logic_vector(DATA_BITS downto 0); + signal DataFIFO_Valid : std_logic; - constant META_MISC_BITS : POSITIVE := Checksum'length + WordCount'length; + constant META_MISC_BITS : positive := Checksum'length + WordCount'length; - signal MetaFIFO_Misc_put : STD_LOGIC; - signal MetaFIFO_Misc_DataIn : STD_LOGIC_VECTOR(META_MISC_BITS - 1 downto 0); - signal MetaFIFO_Misc_Full : STD_LOGIC; - signal MetaFIFO_Misc_got : STD_LOGIC; - signal MetaFIFO_Misc_DataOut : STD_LOGIC_VECTOR(META_MISC_BITS - 1 downto 0); - signal MetaFIFO_Misc_Valid : STD_LOGIC; + signal MetaFIFO_Misc_put : std_logic; + signal MetaFIFO_Misc_DataIn : std_logic_vector(META_MISC_BITS - 1 downto 0); + signal MetaFIFO_Misc_Full : std_logic; + signal MetaFIFO_Misc_got : std_logic; + signal MetaFIFO_Misc_DataOut : std_logic_vector(META_MISC_BITS - 1 downto 0); + signal MetaFIFO_Misc_Valid : std_logic; - signal Meta_rst : STD_LOGIC_VECTOR(META_BITS'length - 1 downto 0); + signal Meta_rst : std_logic_vector(META_BITS'length - 1 downto 0); begin @@ -152,7 +151,7 @@ begin DataFIFO_put <= '0'; MetaFIFO_Misc_put <= '0'; - In_Ack <= NOT DataFIFO_Full; + In_Ack <= not DataFIFO_Full; WordCounter_rst <= '0'; WordCounter_en <= '0'; @@ -163,7 +162,7 @@ begin case Writer_State is when ST_IDLE => - if ((In_Valid AND In_SOF AND (NOT DataFIFO_Full)) = '1') then + if ((In_Valid and In_SOF and (not DataFIFO_Full)) = '1') then WordCounter_en <= '1'; Checksum_en <= '1'; DataFIFO_put <= In_Valid; @@ -180,7 +179,7 @@ begin when ST_FRAME => DataFIFO_put <= In_Valid; - if ((In_Valid AND (NOT DataFIFO_Full)) = '1') then + if ((In_Valid and (not DataFIFO_Full)) = '1') then WordCounter_en <= '1'; Checksum_en <= '1'; @@ -249,11 +248,11 @@ begin DataFIFO_got <= '0'; - case Reader_State IS + case Reader_State is when ST_IDLE => Out_SOF <= '1'; - if ((DataFIFO_Valid AND MetaFIFO_Misc_Valid) = '1') then + if ((DataFIFO_Valid and MetaFIFO_Misc_Valid) = '1') then Out_Valid <= '1'; if (Out_Ack = '1') then @@ -369,24 +368,24 @@ begin Out_Meta_Length <= resize(MetaFIFO_Misc_DataOut(WordCount'range), Out_Meta_Length'length); Out_Meta_Checksum <= MetaFIFO_Misc_DataOut(Checksum'range); - FrameCommit <= DataFIFO_Valid AND DataFIFO_DataOut(EOF_BIT) AND Out_Ack; + FrameCommit <= DataFIFO_Valid and DataFIFO_DataOut(EOF_BIT) and Out_Ack; MetaFIFO_Misc_got <= FrameCommit; genMeta : for i in 0 to META_BITS'length - 1 generate - signal MetaFIFO_put : STD_LOGIC; - signal MetaFIFO_DataIn : STD_LOGIC_VECTOR(META_BITS(i) - 1 downto 0); - signal MetaFIFO_Full : STD_LOGIC; - signal MetaFIFO_got : STD_LOGIC; - signal MetaFIFO_DataOut : STD_LOGIC_VECTOR(META_BITS(i) - 1 downto 0); - signal MetaFIFO_Valid : STD_LOGIC; - signal MetaFIFO_Commit : STD_LOGIC; - signal MetaFIFO_Rollback : STD_LOGIC; - - signal Writer_CounterControl : STD_LOGIC := '0'; - - signal Writer_Counter_rst : STD_LOGIC; - signal Writer_Counter_en : STD_LOGIC; - signal Writer_Counter_us : UNSIGNED(log2ceilnz(META_FIFO_DEPTH(i) * MAX_FRAMES) - 1 downto 0) := (others => '0'); + signal MetaFIFO_put : std_logic; + signal MetaFIFO_DataIn : std_logic_vector(META_BITS(i) - 1 downto 0); + signal MetaFIFO_Full : std_logic; + signal MetaFIFO_got : std_logic; + signal MetaFIFO_DataOut : std_logic_vector(META_BITS(i) - 1 downto 0); + signal MetaFIFO_Valid : std_logic; + signal MetaFIFO_Commit : std_logic; + signal MetaFIFO_Rollback : std_logic; + + signal Writer_CounterControl : std_logic := '0'; + + signal Writer_Counter_rst : std_logic; + signal Writer_Counter_en : std_logic; + signal Writer_Counter_us : unsigned(log2ceilnz(META_FIFO_DEPTH(i) * MAX_FRAMES) - 1 downto 0) := (others => '0'); begin Writer_Counter_rst <= '0'; -- FIXME: is this correct? @@ -395,7 +394,7 @@ begin if rising_edge(Clock) then if (Reset = '1') then Writer_CounterControl <= '0'; - elsif ((In_Valid AND In_SOF) = '1') then + elsif ((In_Valid and In_SOF) = '1') then Writer_CounterControl <= '1'; elsif (Writer_Counter_us = (META_FIFO_DEPTH(i) - 1)) then Writer_CounterControl <= '0'; @@ -403,12 +402,12 @@ begin end if; end process; - Writer_Counter_en <= (In_Valid AND In_SOF) OR Writer_CounterControl; + Writer_Counter_en <= (In_Valid and In_SOF) or Writer_CounterControl; process(Clock) begin if rising_edge(Clock) then - if ((Reset OR Writer_Counter_rst) = '1') then + if ((Reset or Writer_Counter_rst) = '1') then Writer_Counter_us <= (others => '0'); elsif (Writer_Counter_en = '1') then Writer_Counter_us <= Writer_Counter_us + 1; @@ -416,7 +415,7 @@ begin end if; end process; - Meta_rst(i) <= NOT Writer_Counter_en; + Meta_rst(i) <= not Writer_Counter_en; In_Meta_nxt(i) <= Writer_Counter_en; MetaFIFO_put <= Writer_Counter_en; diff --git a/src/net/net_FrameLoopback.vhdl b/src/net/net_FrameLoopback.vhdl index c29cc1e0..f57940c5 100644 --- a/src/net/net_FrameLoopback.vhdl +++ b/src/net/net_FrameLoopback.vhdl @@ -1,18 +1,17 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: TODO +-- Entity: TODO -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -27,7 +26,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -41,49 +40,49 @@ use PoC.vectors.all; entity FrameLoopback is generic ( - DATA_BW : POSITIVE := 8; - META_BW : NATURAL := 0 + DATA_BW : positive := 8; + META_BW : natural := 0 ); port ( - Clock : in STD_LOGIC; - Reset : in STD_LOGIC; - - In_Valid : in STD_LOGIC; - In_Data : in STD_LOGIC_VECTOR(DATA_BW - 1 downto 0); - In_Meta : in STD_LOGIC_VECTOR(META_BW - 1 downto 0); - In_SOF : in STD_LOGIC; - In_EOF : in STD_LOGIC; - In_Ack : out STD_LOGIC; - - - Out_Valid : out STD_LOGIC; - Out_Data : out STD_LOGIC_VECTOR(DATA_BW - 1 downto 0); - Out_Meta : out STD_LOGIC_VECTOR(META_BW - 1 downto 0); - Out_SOF : out STD_LOGIC; - Out_EOF : out STD_LOGIC; - Out_Ack : in STD_LOGIC + Clock : in std_logic; + Reset : in std_logic; + + In_Valid : in std_logic; + In_Data : in std_logic_vector(DATA_BW - 1 downto 0); + In_Meta : in std_logic_vector(META_BW - 1 downto 0); + In_SOF : in std_logic; + In_EOF : in std_logic; + In_Ack : out std_logic; + + + Out_Valid : out std_logic; + Out_Data : out std_logic_vector(DATA_BW - 1 downto 0); + Out_Meta : out std_logic_vector(META_BW - 1 downto 0); + Out_SOF : out std_logic; + Out_EOF : out std_logic; + Out_Ack : in std_logic ); end entity; architecture rtl of FrameLoopback is - constant META_STREAMID_SRC : NATURAL := 0; - constant META_STREAMID_DEST : NATURAL := 1; - constant META_STREAMID_type : NATURAL := 2; - constant META_STREAMS : POSITIVE := 3; -- Source, Destination, Type + constant META_STREAMID_SRC : natural := 0; + constant META_STREAMID_DEST : natural := 1; + constant META_STREAMID_type : natural := 2; + constant META_STREAMS : positive := 3; -- Source, Destination, Type - signal Meta_rst : STD_LOGIC; - signal Meta_nxt : STD_LOGIC_VECTOR(META_STREAMS - 1 downto 0); + signal Meta_rst : std_logic; + signal Meta_nxt : std_logic_vector(META_STREAMS - 1 downto 0); signal Pipe_DataOut : T_SLV_8; signal Pipe_MetaIn : T_SLM(META_STREAMS - 1 downto 0, 31 downto 0) := (others => (others => 'Z')); signal Pipe_MetaOut : T_SLM(META_STREAMS - 1 downto 0, 31 downto 0); - signal Pipe_Meta_rst : STD_LOGIC; - signal Pipe_Meta_nxt : STD_LOGIC_VECTOR(META_STREAMS - 1 downto 0); + signal Pipe_Meta_rst : std_logic; + signal Pipe_Meta_nxt : std_logic_vector(META_STREAMS - 1 downto 0); - signal Pipe_Meta_SrcMACAddress_Data : STD_LOGIC_VECTOR(TX_Funnel_SrcIPv6Address_Data'range); - signal Pipe_Meta_DestMACAddress_Data : STD_LOGIC_VECTOR(TX_Funnel_DestIPv6Address_Data'range); - signal Pipe_Meta_EthType : STD_LOGIC_VECTOR(TX_Funnel_Payload_Type'range); + signal Pipe_Meta_SrcMACAddress_Data : std_logic_vector(TX_Funnel_SrcIPv6Address_Data'range); + signal Pipe_Meta_DestMACAddress_Data : std_logic_vector(TX_Funnel_DestIPv6Address_Data'range); + signal Pipe_Meta_EthType : std_logic_vector(TX_Funnel_Payload_Type'range); begin diff --git a/src/net/udp/udp_FrameLoopback.vhdl b/src/net/udp/udp_FrameLoopback.vhdl index 5f6c3dea..defd96dc 100644 --- a/src/net/udp/udp_FrameLoopback.vhdl +++ b/src/net/udp/udp_FrameLoopback.vhdl @@ -1,18 +1,17 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: TODO +-- Entity: TODO -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -27,7 +26,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -42,35 +41,35 @@ use PoC.net.all; entity udp_FrameLoopback is generic ( - IP_VERSION : POSITIVE := 6; - MAX_FRAMES : POSITIVE := 4 + IP_VERSION : positive := 6; + MAX_FRAMES : positive := 4 ); port ( - Clock : in STD_LOGIC; - Reset : in STD_LOGIC; + Clock : in std_logic; + Reset : in std_logic; -- IN port - In_Valid : in STD_LOGIC; + In_Valid : in std_logic; In_Data : in T_SLV_8; - In_SOF : in STD_LOGIC; - In_EOF : in STD_LOGIC; - In_Ack : out STD_LOGIC; - In_Meta_rst : out STD_LOGIC; - In_Meta_DestIPAddress_nxt : out STD_LOGIC; + In_SOF : in std_logic; + In_EOF : in std_logic; + In_Ack : out std_logic; + In_Meta_rst : out std_logic; + In_Meta_DestIPAddress_nxt : out std_logic; In_Meta_DestIPAddress_Data : in T_SLV_8; - In_Meta_SrcIPAddress_nxt : out STD_LOGIC; + In_Meta_SrcIPAddress_nxt : out std_logic; In_Meta_SrcIPAddress_Data : in T_SLV_8; In_Meta_DestPort : in T_NET_UDP_PORT; In_Meta_SrcPort : in T_NET_UDP_PORT; -- OUT port - Out_Valid : out STD_LOGIC; + Out_Valid : out std_logic; Out_Data : out T_SLV_8; - Out_SOF : out STD_LOGIC; - Out_EOF : out STD_LOGIC; - Out_Ack : in STD_LOGIC; - Out_Meta_rst : in STD_LOGIC; - Out_Meta_DestIPAddress_nxt : in STD_LOGIC; + Out_SOF : out std_logic; + Out_EOF : out std_logic; + Out_Ack : in std_logic; + Out_Meta_rst : in std_logic; + Out_Meta_DestIPAddress_nxt : in std_logic; Out_Meta_DestIPAddress_Data : out T_SLV_8; - Out_Meta_SrcIPAddress_nxt : in STD_LOGIC; + Out_Meta_SrcIPAddress_nxt : in std_logic; Out_Meta_SrcIPAddress_Data : out T_SLV_8; Out_Meta_DestPort : out T_NET_UDP_PORT; Out_Meta_SrcPort : out T_NET_UDP_PORT @@ -79,12 +78,12 @@ end entity; architecture rtl of udp_FrameLoopback is - constant IPADDRESS_LENGTH : POSITIVE := ite((IP_VERSION = 4), 4, 16); + constant IPADDRESS_LENGTH : positive := ite((IP_VERSION = 4), 4, 16); - constant META_STREAMID_SRCADDR : NATURAL := 0; - constant META_STREAMID_DESTADDR : NATURAL := 1; - constant META_STREAMID_SRCPORT : NATURAL := 2; - constant META_STREAMID_DESTPORT : NATURAL := 3; + constant META_STREAMID_SRCADDR : natural := 0; + constant META_STREAMID_DESTADDR : natural := 1; + constant META_STREAMID_SRCPORT : natural := 2; + constant META_STREAMID_DESTPORT : natural := 3; constant META_BITS : T_POSVEC := ( META_STREAMID_SRCADDR => 8, @@ -100,10 +99,10 @@ architecture rtl of udp_FrameLoopback is META_STREAMID_DESTPORT => 1 ); - signal StmBuf_MetaIn_nxt : STD_LOGIC_VECTOR(META_BITS'length - 1 downto 0); - signal StmBuf_MetaIn_Data : STD_LOGIC_VECTOR(isum(META_BITS) - 1 downto 0); - signal StmBuf_MetaOut_nxt : STD_LOGIC_VECTOR(META_BITS'length - 1 downto 0); - signal StmBuf_MetaOut_Data : STD_LOGIC_VECTOR(isum(META_BITS) - 1 downto 0); + signal StmBuf_MetaIn_nxt : std_logic_vector(META_BITS'length - 1 downto 0); + signal StmBuf_MetaIn_Data : std_logic_vector(isum(META_BITS) - 1 downto 0); + signal StmBuf_MetaOut_nxt : std_logic_vector(META_BITS'length - 1 downto 0); + signal StmBuf_MetaOut_Data : std_logic_vector(isum(META_BITS) - 1 downto 0); begin StmBuf_MetaIn_Data(high(META_BITS, META_STREAMID_SRCADDR) downto low(META_BITS, META_STREAMID_SRCADDR)) <= In_Meta_SrcIPAddress_Data; diff --git a/src/net/udp/udp_RX.vhdl b/src/net/udp/udp_RX.vhdl index 4d0621a6..febd624d 100644 --- a/src/net/udp/udp_RX.vhdl +++ b/src/net/udp/udp_RX.vhdl @@ -1,18 +1,17 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: TODO +-- Entity: TODO -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -27,7 +26,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -42,49 +41,49 @@ use PoC.net.all; entity udp_RX is generic ( - DEBUG : BOOLEAN := FALSE; - IP_VERSION : POSITIVE := 6 + DEBUG : boolean := FALSE; + IP_VERSION : positive := 6 ); port ( - Clock : in STD_LOGIC; -- - Reset : in STD_LOGIC; -- + Clock : in std_logic; -- + Reset : in std_logic; -- -- STATUS port - Error : out STD_LOGIC; + Error : out std_logic; -- IN port - In_Valid : in STD_LOGIC; + In_Valid : in std_logic; In_Data : in T_SLV_8; - In_SOF : in STD_LOGIC; - In_EOF : in STD_LOGIC; - In_Ack : out STD_LOGIC; - In_Meta_rst : out STD_LOGIC; - In_Meta_SrcMACAddress_nxt : out STD_LOGIC; + In_SOF : in std_logic; + In_EOF : in std_logic; + In_Ack : out std_logic; + In_Meta_rst : out std_logic; + In_Meta_SrcMACAddress_nxt : out std_logic; In_Meta_SrcMACAddress_Data : in T_SLV_8; - In_Meta_DestMACAddress_nxt : out STD_LOGIC; + In_Meta_DestMACAddress_nxt : out std_logic; In_Meta_DestMACAddress_Data : in T_SLV_8; In_Meta_EthType : in T_SLV_16; - In_Meta_SrcIPAddress_nxt : out STD_LOGIC; + In_Meta_SrcIPAddress_nxt : out std_logic; In_Meta_SrcIPAddress_Data : in T_SLV_8; - In_Meta_DestIPAddress_nxt : out STD_LOGIC; + In_Meta_DestIPAddress_nxt : out std_logic; In_Meta_DestIPAddress_Data : in T_SLV_8; -- In_Meta_TrafficClass : in T_SLV_8; -- In_Meta_FlowLabel : in T_SLV_24; In_Meta_Length : in T_SLV_16; In_Meta_Protocol : in T_SLV_8; -- OUT port - Out_Valid : out STD_LOGIC; + Out_Valid : out std_logic; Out_Data : out T_SLV_8; - Out_SOF : out STD_LOGIC; - Out_EOF : out STD_LOGIC; - Out_Ack : in STD_LOGIC; - Out_Meta_rst : in STD_LOGIC; - Out_Meta_SrcMACAddress_nxt : in STD_LOGIC; + Out_SOF : out std_logic; + Out_EOF : out std_logic; + Out_Ack : in std_logic; + Out_Meta_rst : in std_logic; + Out_Meta_SrcMACAddress_nxt : in std_logic; Out_Meta_SrcMACAddress_Data : out T_SLV_8; - Out_Meta_DestMACAddress_nxt : in STD_LOGIC; + Out_Meta_DestMACAddress_nxt : in std_logic; Out_Meta_DestMACAddress_Data : out T_SLV_8; Out_Meta_EthType : out T_SLV_16; - Out_Meta_SrcIPAddress_nxt : in STD_LOGIC; + Out_Meta_SrcIPAddress_nxt : in std_logic; Out_Meta_SrcIPAddress_Data : out T_SLV_8; - Out_Meta_DestIPAddress_nxt : in STD_LOGIC; + Out_Meta_DestIPAddress_nxt : in std_logic; Out_Meta_DestIPAddress_Data : out T_SLV_8; -- Out_Meta_TrafficClass : out T_SLV_8; -- Out_Meta_FlowLabel : out T_SLV_24; @@ -162,7 +161,7 @@ end entity; architecture rtl of udp_RX is - attribute FSM_ENCODING : STRING; + attribute FSM_ENCODING : string; type T_STATE is ( ST_IDLE, @@ -177,26 +176,26 @@ architecture rtl of udp_RX is signal State : T_STATE := ST_IDLE; signal NextState : T_STATE; - attribute FSM_ENCODING of State : signal IS ite(DEBUG, "gray", ite((VENDOR = VENDOR_XILINX), "auto", "default")); + attribute FSM_ENCODING of State : signal is ite(DEBUG, "gray", ite((VENDOR = VENDOR_XILINX), "auto", "default")); - signal In_Ack_i : STD_LOGIC; - signal Is_DataFlow : STD_LOGIC; - signal Is_SOF : STD_LOGIC; - signal Is_EOF : STD_LOGIC; + signal In_Ack_i : std_logic; + signal Is_DataFlow : std_logic; + signal Is_SOF : std_logic; + signal Is_EOF : std_logic; - signal Out_Valid_i : STD_LOGIC; - signal Out_SOF_i : STD_LOGIC; - signal Out_EOF_i : STD_LOGIC; + signal Out_Valid_i : std_logic; + signal Out_SOF_i : std_logic; + signal Out_EOF_i : std_logic; - signal Register_rst : STD_LOGIC; + signal Register_rst : std_logic; -- UDP header fields - signal SourcePort_en0 : STD_LOGIC; - signal SourcePort_en1 : STD_LOGIC; - signal DestinationPort_en0 : STD_LOGIC; - signal DestinationPort_en1 : STD_LOGIC; - signal Length_en0 : STD_LOGIC; - signal Length_en1 : STD_LOGIC; + signal SourcePort_en0 : std_logic; + signal SourcePort_en1 : std_logic; + signal DestinationPort_en0 : std_logic; + signal DestinationPort_en1 : std_logic; + signal Length_en0 : std_logic; + signal Length_en1 : std_logic; signal SourcePort_d : T_SLV_16 := (others => '0'); signal DestinationPort_d : T_SLV_16 := (others => '0'); @@ -205,9 +204,9 @@ architecture rtl of udp_RX is begin In_Ack <= In_Ack_i; - Is_DataFlow <= In_Valid AND In_Ack_i; - Is_SOF <= In_Valid AND In_SOF; - Is_EOF <= In_Valid AND In_EOF; + Is_DataFlow <= In_Valid and In_Ack_i; + Is_SOF <= In_Valid and In_SOF; + Is_EOF <= In_Valid and In_EOF; process(Clock) begin @@ -375,7 +374,7 @@ begin process(Clock) begin if rising_edge(Clock) then - if ((Reset OR Register_rst) = '1') then + if ((Reset or Register_rst) = '1') then SourcePort_d <= (others => '0'); DestinationPort_d <= (others => '0'); Length_d <= (others => '0'); diff --git a/src/net/udp/udp_TX.vhdl b/src/net/udp/udp_TX.vhdl index 62923fc4..96c32444 100644 --- a/src/net/udp/udp_TX.vhdl +++ b/src/net/udp/udp_TX.vhdl @@ -1,18 +1,17 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: TODO +-- Entity: TODO -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -27,7 +26,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -40,39 +39,39 @@ use PoC.vectors.all; use PoC.net.all; -entity udp_TX IS +entity udp_TX is generic ( - DEBUG : BOOLEAN := FALSE; - IP_VERSION : POSITIVE := 6 + DEBUG : boolean := FALSE; + IP_VERSION : positive := 6 ); port ( - Clock : in STD_LOGIC; -- - Reset : in STD_LOGIC; -- + Clock : in std_logic; -- + Reset : in std_logic; -- -- IN port - In_Valid : in STD_LOGIC; + In_Valid : in std_logic; In_Data : in T_SLV_8; - In_SOF : in STD_LOGIC; - In_EOF : in STD_LOGIC; - In_Ack : out STD_LOGIC; - In_Meta_rst : out STD_LOGIC; - In_Meta_SrcIPAddress_nxt : out STD_LOGIC; + In_SOF : in std_logic; + In_EOF : in std_logic; + In_Ack : out std_logic; + In_Meta_rst : out std_logic; + In_Meta_SrcIPAddress_nxt : out std_logic; In_Meta_SrcIPAddress_Data : in T_SLV_8; - In_Meta_DestIPAddress_nxt : out STD_LOGIC; + In_Meta_DestIPAddress_nxt : out std_logic; In_Meta_DestIPAddress_Data : in T_SLV_8; In_Meta_SrcPort : in T_SLV_16; In_Meta_DestPort : in T_SLV_16; In_Meta_Length : in T_SLV_16; In_Meta_Checksum : in T_SLV_16; -- OUT port - Out_Valid : out STD_LOGIC; + Out_Valid : out std_logic; Out_Data : out T_SLV_8; - Out_SOF : out STD_LOGIC; - Out_EOF : out STD_LOGIC; - Out_Ack : in STD_LOGIC; - Out_Meta_rst : in STD_LOGIC; - Out_Meta_SrcIPAddress_nxt : in STD_LOGIC; + Out_SOF : out std_logic; + Out_EOF : out std_logic; + Out_Ack : in std_logic; + Out_Meta_rst : in std_logic; + Out_Meta_SrcIPAddress_nxt : in std_logic; Out_Meta_SrcIPAddress_Data : out T_SLV_8; - Out_Meta_DestIPAddress_nxt : in STD_LOGIC; + Out_Meta_DestIPAddress_nxt : in std_logic; Out_Meta_DestIPAddress_Data : out T_SLV_8; Out_Meta_Length : out T_SLV_16 ); @@ -143,7 +142,7 @@ end entity; -- +================================+================================+================================+================================+ architecture rtl of udp_TX is - attribute FSM_ENCODING : STRING; + attribute FSM_ENCODING : string; type T_STATE is ( ST_IDLE, @@ -167,39 +166,39 @@ architecture rtl of udp_TX is signal State : T_STATE := ST_IDLE; signal NextState : T_STATE; - attribute FSM_ENCODING of State : signal IS ite(DEBUG, "gray", ite((VENDOR = VENDOR_XILINX), "auto", "default")); - - signal In_Ack_i : STD_LOGIC; - - signal UpperLayerPacketLength : STD_LOGIC_VECTOR(15 downto 0); - - signal IPSeqCounter_rst : STD_LOGIC; - signal IPSeqCounter_en : STD_LOGIC; - signal IPSeqCounter_us : UNSIGNED(3 downto 0) := (others => '0'); - - signal Checksum_rst : STD_LOGIC; - signal Checksum_en : STD_LOGIC; - signal Checksum_Addend0_us : UNSIGNED(T_SLV_8'range); - signal Checksum_Addend1_us : UNSIGNED(T_SLV_8'range); - signal Checksum0_nxt0_us : UNSIGNED(T_SLV_8'high + 1 downto 0); - signal Checksum0_nxt1_us : UNSIGNED(T_SLV_8'high + 1 downto 0); - signal Checksum0_d_us : UNSIGNED(T_SLV_8'high downto 0) := (others => '0'); - signal Checksum0_cy : UNSIGNED(T_SLV_2'range); - signal Checksum1_nxt_us : UNSIGNED(T_SLV_8'range); - signal Checksum1_d_us : UNSIGNED(T_SLV_8'range) := (others => '0'); - signal Checksum0_cy0 : STD_LOGIC; - signal Checksum0_cy0_d : STD_LOGIC := '0'; - signal Checksum0_cy1 : STD_LOGIC; - signal Checksum0_cy1_d : STD_LOGIC := '0'; + attribute FSM_ENCODING of State : signal is ite(DEBUG, "gray", ite((VENDOR = VENDOR_XILINX), "auto", "default")); + + signal In_Ack_i : std_logic; + + signal UpperLayerPacketLength : std_logic_vector(15 downto 0); + + signal IPSeqCounter_rst : std_logic; + signal IPSeqCounter_en : std_logic; + signal IPSeqCounter_us : unsigned(3 downto 0) := (others => '0'); + + signal Checksum_rst : std_logic; + signal Checksum_en : std_logic; + signal Checksum_Addend0_us : unsigned(T_SLV_8'range); + signal Checksum_Addend1_us : unsigned(T_SLV_8'range); + signal Checksum0_nxt0_us : unsigned(T_SLV_8'high + 1 downto 0); + signal Checksum0_nxt1_us : unsigned(T_SLV_8'high + 1 downto 0); + signal Checksum0_d_us : unsigned(T_SLV_8'high downto 0) := (others => '0'); + signal Checksum0_cy : unsigned(T_SLV_2'range); + signal Checksum1_nxt_us : unsigned(T_SLV_8'range); + signal Checksum1_d_us : unsigned(T_SLV_8'range) := (others => '0'); + signal Checksum0_cy0 : std_logic; + signal Checksum0_cy0_d : std_logic := '0'; + signal Checksum0_cy1 : std_logic; + signal Checksum0_cy1_d : std_logic := '0'; signal Checksum_i : T_SLV_16; signal Checksum : T_SLV_16; - signal Checksum_mux_rst : STD_LOGIC; - signal Checksum_mux_set : STD_LOGIC; - signal Checksum_mux_r : STD_LOGIC := '0'; + signal Checksum_mux_rst : std_logic; + signal Checksum_mux_set : std_logic; + signal Checksum_mux_r : std_logic := '0'; begin - assert ((IP_VERSION = 6) OR (IP_VERSION = 4)) report "Internet Protocol Version not supported." severity ERROR; + assert ((IP_VERSION = 6) or (IP_VERSION = 4)) report "Internet Protocol Version not supported." severity ERROR; UpperLayerPacketLength <= std_logic_vector(unsigned(In_Meta_Length) + 8); @@ -256,7 +255,7 @@ begin IPSeqCounter_rst <= '1'; Checksum_rst <= '1'; - if ((In_Valid AND In_SOF) = '1') then + if ((In_Valid and In_SOF) = '1') then if (IP_VERSION = 4) then NextState <= ST_CHECKSUMV4_IPV4_ADDRESSES; elsif (IP_VERSION = 6) then @@ -485,7 +484,7 @@ begin Out_EOF <= In_EOF; In_Ack_i <= Out_Ack; - if ((In_EOF AND Out_Ack) = '1') then + if ((In_EOF and Out_Ack) = '1') then NextState <= ST_IDLE; end if; @@ -499,7 +498,7 @@ begin process(Clock) begin if rising_edge(Clock) then - if ((Reset OR IPSeqCounter_rst) = '1') then + if ((Reset or IPSeqCounter_rst) = '1') then IPSeqCounter_us <= to_unsigned(0, IPSeqCounter_us'length); elsif (IPSeqCounter_en = '1') then IPSeqCounter_us <= IPSeqCounter_us + 1; @@ -542,7 +541,7 @@ begin process(Clock) begin if rising_edge(Clock) then - if ((Reset OR Checksum_mux_rst) = '1') then + if ((Reset or Checksum_mux_rst) = '1') then Checksum_mux_r <= '0'; elsif (Checksum_mux_set = '1') then Checksum_mux_r <= '1'; @@ -553,4 +552,4 @@ begin In_Ack <= In_Ack_i; Out_Meta_Length <= UpperLayerPacketLength; -end architecture; \ No newline at end of file +end architecture; diff --git a/src/net/udp/udp_Wrapper.vhdl b/src/net/udp/udp_Wrapper.vhdl index 663cb67c..6c5acd3b 100644 --- a/src/net/udp/udp_Wrapper.vhdl +++ b/src/net/udp/udp_Wrapper.vhdl @@ -1,18 +1,17 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: TODO +-- Entity: TODO -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -27,7 +26,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -42,74 +41,74 @@ use PoC.net.all; entity udp_Wrapper is generic ( - DEBUG : BOOLEAN := FALSE; - IP_VERSION : POSITIVE := 6; + DEBUG : boolean := FALSE; + IP_VERSION : positive := 6; PORTPAIRS : T_NET_UDP_PORTPAIR_VECTOR := (0 => (x"0000", x"0000")) ); port ( - Clock : in STD_LOGIC; - Reset : in STD_LOGIC; + Clock : in std_logic; + Reset : in std_logic; -- from IP layer - IP_TX_Valid : out STD_LOGIC; + IP_TX_Valid : out std_logic; IP_TX_Data : out T_SLV_8; - IP_TX_SOF : out STD_LOGIC; - IP_TX_EOF : out STD_LOGIC; - IP_TX_Ack : in STD_LOGIC; - IP_TX_Meta_rst : in STD_LOGIC; - IP_TX_Meta_SrcIPAddress_nxt : in STD_LOGIC; + IP_TX_SOF : out std_logic; + IP_TX_EOF : out std_logic; + IP_TX_Ack : in std_logic; + IP_TX_Meta_rst : in std_logic; + IP_TX_Meta_SrcIPAddress_nxt : in std_logic; IP_TX_Meta_SrcIPAddress_Data : out T_SLV_8; - IP_TX_Meta_DestIPAddress_nxt : in STD_LOGIC; + IP_TX_Meta_DestIPAddress_nxt : in std_logic; IP_TX_Meta_DestIPAddress_Data : out T_SLV_8; IP_TX_Meta_Length : out T_SLV_16; -- to IP layer - IP_RX_Valid : in STD_LOGIC; + IP_RX_Valid : in std_logic; IP_RX_Data : in T_SLV_8; - IP_RX_SOF : in STD_LOGIC; - IP_RX_EOF : in STD_LOGIC; - IP_RX_Ack : out STD_LOGIC; - IP_RX_Meta_rst : out STD_LOGIC; - IP_RX_Meta_SrcMACAddress_nxt : out STD_LOGIC; + IP_RX_SOF : in std_logic; + IP_RX_EOF : in std_logic; + IP_RX_Ack : out std_logic; + IP_RX_Meta_rst : out std_logic; + IP_RX_Meta_SrcMACAddress_nxt : out std_logic; IP_RX_Meta_SrcMACAddress_Data : in T_SLV_8; - IP_RX_Meta_DestMACAddress_nxt : out STD_LOGIC; + IP_RX_Meta_DestMACAddress_nxt : out std_logic; IP_RX_Meta_DestMACAddress_Data : in T_SLV_8; IP_RX_Meta_EthType : in T_SLV_16; - IP_RX_Meta_SrcIPAddress_nxt : out STD_LOGIC; + IP_RX_Meta_SrcIPAddress_nxt : out std_logic; IP_RX_Meta_SrcIPAddress_Data : in T_SLV_8; - IP_RX_Meta_DestIPAddress_nxt : out STD_LOGIC; + IP_RX_Meta_DestIPAddress_nxt : out std_logic; IP_RX_Meta_DestIPAddress_Data : in T_SLV_8; -- IP_RX_Meta_TrafficClass : in T_SLV_8; -- IP_RX_Meta_FlowLabel : in T_SLV_24; IP_RX_Meta_Length : in T_SLV_16; IP_RX_Meta_Protocol : in T_SLV_8; -- from upper layer - TX_Valid : in STD_LOGIC_VECTOR(PORTPAIRS'length - 1 downto 0); + TX_Valid : in std_logic_vector(PORTPAIRS'length - 1 downto 0); TX_Data : in T_SLVV_8(PORTPAIRS'length - 1 downto 0); - TX_SOF : in STD_LOGIC_VECTOR(PORTPAIRS'length - 1 downto 0); - TX_EOF : in STD_LOGIC_VECTOR(PORTPAIRS'length - 1 downto 0); - TX_Ack : out STD_LOGIC_VECTOR(PORTPAIRS'length - 1 downto 0); - TX_Meta_rst : out STD_LOGIC_VECTOR(PORTPAIRS'length - 1 downto 0); - TX_Meta_SrcIPAddress_nxt : out STD_LOGIC_VECTOR(PORTPAIRS'length - 1 downto 0); + TX_SOF : in std_logic_vector(PORTPAIRS'length - 1 downto 0); + TX_EOF : in std_logic_vector(PORTPAIRS'length - 1 downto 0); + TX_Ack : out std_logic_vector(PORTPAIRS'length - 1 downto 0); + TX_Meta_rst : out std_logic_vector(PORTPAIRS'length - 1 downto 0); + TX_Meta_SrcIPAddress_nxt : out std_logic_vector(PORTPAIRS'length - 1 downto 0); TX_Meta_SrcIPAddress_Data : in T_SLVV_8(PORTPAIRS'length - 1 downto 0); - TX_Meta_DestIPAddress_nxt : out STD_LOGIC_VECTOR(PORTPAIRS'length - 1 downto 0); + TX_Meta_DestIPAddress_nxt : out std_logic_vector(PORTPAIRS'length - 1 downto 0); TX_Meta_DestIPAddress_Data : in T_SLVV_8(PORTPAIRS'length - 1 downto 0); TX_Meta_SrcPort : in T_SLVV_16(PORTPAIRS'length - 1 downto 0); TX_Meta_DestPort : in T_SLVV_16(PORTPAIRS'length - 1 downto 0); TX_Meta_Length : in T_SLVV_16(PORTPAIRS'length - 1 downto 0); -- to upper layer - RX_Valid : out STD_LOGIC_VECTOR(PORTPAIRS'length - 1 downto 0); + RX_Valid : out std_logic_vector(PORTPAIRS'length - 1 downto 0); RX_Data : out T_SLVV_8(PORTPAIRS'length - 1 downto 0); - RX_SOF : out STD_LOGIC_VECTOR(PORTPAIRS'length - 1 downto 0); - RX_EOF : out STD_LOGIC_VECTOR(PORTPAIRS'length - 1 downto 0); - RX_Ack : in STD_LOGIC_VECTOR(PORTPAIRS'length - 1 downto 0); - RX_Meta_rst : in STD_LOGIC_VECTOR(PORTPAIRS'length - 1 downto 0); - RX_Meta_SrcMACAddress_nxt : in STD_LOGIC_VECTOR(PORTPAIRS'length - 1 downto 0); + RX_SOF : out std_logic_vector(PORTPAIRS'length - 1 downto 0); + RX_EOF : out std_logic_vector(PORTPAIRS'length - 1 downto 0); + RX_Ack : in std_logic_vector(PORTPAIRS'length - 1 downto 0); + RX_Meta_rst : in std_logic_vector(PORTPAIRS'length - 1 downto 0); + RX_Meta_SrcMACAddress_nxt : in std_logic_vector(PORTPAIRS'length - 1 downto 0); RX_Meta_SrcMACAddress_Data : out T_SLVV_8(PORTPAIRS'length - 1 downto 0); - RX_Meta_DestMACAddress_nxt : in STD_LOGIC_VECTOR(PORTPAIRS'length - 1 downto 0); + RX_Meta_DestMACAddress_nxt : in std_logic_vector(PORTPAIRS'length - 1 downto 0); RX_Meta_DestMACAddress_Data : out T_SLVV_8(PORTPAIRS'length - 1 downto 0); RX_Meta_EthType : out T_SLVV_16(PORTPAIRS'length - 1 downto 0); - RX_Meta_SrcIPAddress_nxt : in STD_LOGIC_VECTOR(PORTPAIRS'length - 1 downto 0); + RX_Meta_SrcIPAddress_nxt : in std_logic_vector(PORTPAIRS'length - 1 downto 0); RX_Meta_SrcIPAddress_Data : out T_SLVV_8(PORTPAIRS'length - 1 downto 0); - RX_Meta_DestIPAddress_nxt : in STD_LOGIC_VECTOR(PORTPAIRS'length - 1 downto 0); + RX_Meta_DestIPAddress_nxt : in std_logic_vector(PORTPAIRS'length - 1 downto 0); RX_Meta_DestIPAddress_Data : out T_SLVV_8(PORTPAIRS'length - 1 downto 0); -- RX_Meta_TrafficClass : out T_SLVV_8(PORTPAIRS'length - 1 downto 0); -- RX_Meta_FlowLabel : out T_SLVV_24(PORTPAIRS'length - 1 downto 0); @@ -122,19 +121,19 @@ end entity; architecture rtl of udp_Wrapper is - constant UDP_SWITCH_PORTS : POSITIVE := PORTPAIRS'length; + constant UDP_SWITCH_PORTS : positive := PORTPAIRS'length; - constant STMMUX_META_RST_BIT : NATURAL := 0; - constant STMMUX_META_SRCIP_NXT_BIT : NATURAL := 1; - constant STMMUX_META_DESTIP_NXT_BIT : NATURAL := 2; + constant STMMUX_META_RST_BIT : natural := 0; + constant STMMUX_META_SRCIP_NXT_BIT : natural := 1; + constant STMMUX_META_DESTIP_NXT_BIT : natural := 2; - constant STMMUX_META_REV_BITS : NATURAL := 3; + constant STMMUX_META_REV_BITS : natural := 3; - constant STMMUX_META_STREAMID_SRCIP : NATURAL := 0; - constant STMMUX_META_STREAMID_DESTIP : NATURAL := 1; - constant STMMUX_META_STREAMID_SRCPORT : NATURAL := 2; - constant STMMUX_META_STREAMID_DESTPORT : NATURAL := 3; - constant STMMUX_META_STREAMID_LENGTH : NATURAL := 4; + constant STMMUX_META_STREAMID_SRCIP : natural := 0; + constant STMMUX_META_STREAMID_DESTIP : natural := 1; + constant STMMUX_META_STREAMID_SRCPORT : natural := 2; + constant STMMUX_META_STREAMID_DESTPORT : natural := 3; + constant STMMUX_META_STREAMID_LENGTH : natural := 4; constant STMMUX_META_BITS : T_POSVEC := ( STMMUX_META_STREAMID_SRCIP => 8, @@ -144,30 +143,30 @@ architecture rtl of udp_Wrapper is STMMUX_META_STREAMID_LENGTH => 16 ); - signal StmMux_In_Valid : STD_LOGIC_VECTOR(UDP_SWITCH_PORTS - 1 downto 0); + signal StmMux_In_Valid : std_logic_vector(UDP_SWITCH_PORTS - 1 downto 0); signal StmMux_In_Data : T_SLM(UDP_SWITCH_PORTS - 1 downto 0, T_SLV_8'range) := (others => (others => 'Z')); -- necessary default assignment 'Z' to get correct simulation results (iSIM, vSIM, ghdl/gtkwave) signal StmMux_In_Meta : T_SLM(UDP_SWITCH_PORTS - 1 downto 0, isum(STMMUX_META_BITS) - 1 downto 0) := (others => (others => 'Z')); -- necessary default assignment 'Z' to get correct simulation results (iSIM, vSIM, ghdl/gtkwave) signal StmMux_In_Meta_rev : T_SLM(UDP_SWITCH_PORTS - 1 downto 0, STMMUX_META_REV_BITS - 1 downto 0) := (others => (others => 'Z')); -- necessary default assignment 'Z' to get correct simulation results (iSIM, vSIM, ghdl/gtkwave) - signal StmMux_In_SOF : STD_LOGIC_VECTOR(UDP_SWITCH_PORTS - 1 downto 0); - signal StmMux_In_EOF : STD_LOGIC_VECTOR(UDP_SWITCH_PORTS - 1 downto 0); - signal StmMux_In_Ack : STD_LOGIC_VECTOR(UDP_SWITCH_PORTS - 1 downto 0); + signal StmMux_In_SOF : std_logic_vector(UDP_SWITCH_PORTS - 1 downto 0); + signal StmMux_In_EOF : std_logic_vector(UDP_SWITCH_PORTS - 1 downto 0); + signal StmMux_In_Ack : std_logic_vector(UDP_SWITCH_PORTS - 1 downto 0); - signal StmMux_Out_Valid : STD_LOGIC; + signal StmMux_Out_Valid : std_logic; signal StmMux_Out_Data : T_SLV_8; - signal StmMux_Out_Meta : STD_LOGIC_VECTOR(isum(STMMUX_META_BITS) - 1 downto 0); - signal StmMux_Out_Meta_rev : STD_LOGIC_VECTOR(STMMUX_META_REV_BITS - 1 downto 0); - signal StmMux_Out_SOF : STD_LOGIC; - signal StmMux_Out_EOF : STD_LOGIC; + signal StmMux_Out_Meta : std_logic_vector(isum(STMMUX_META_BITS) - 1 downto 0); + signal StmMux_Out_Meta_rev : std_logic_vector(STMMUX_META_REV_BITS - 1 downto 0); + signal StmMux_Out_SOF : std_logic; + signal StmMux_Out_EOF : std_logic; signal StmMux_Out_SrcIPAddress_Data : T_SLV_8; signal StmMux_Out_DestIPAddress_Data : T_SLV_8; signal StmMux_Out_Length : T_SLV_16; signal StmMux_Out_Protocol : T_SLV_8; - constant TX_FCS_META_STREAMID_SRCIP : NATURAL := 0; - constant TX_FCS_META_STREAMID_DESTIP : NATURAL := 1; - constant TX_FCS_META_STREAMID_SRCPORT : NATURAL := 2; - constant TX_FCS_META_STREAMID_DESTPORT : NATURAL := 3; - constant TX_FCS_META_STREAMID_LEN : NATURAL := 4; + constant TX_FCS_META_STREAMID_SRCIP : natural := 0; + constant TX_FCS_META_STREAMID_DESTIP : natural := 1; + constant TX_FCS_META_STREAMID_SRCPORT : natural := 2; + constant TX_FCS_META_STREAMID_DESTPORT : natural := 3; + constant TX_FCS_META_STREAMID_LEN : natural := 4; constant TX_FCS_META_BITS : T_POSVEC := ( TX_FCS_META_STREAMID_SRCIP => 8, @@ -185,13 +184,13 @@ architecture rtl of udp_Wrapper is TX_FCS_META_STREAMID_LEN => 1 ); - signal TX_FCS_Valid : STD_LOGIC; + signal TX_FCS_Valid : std_logic; signal TX_FCS_Data : T_SLV_8; - signal TX_FCS_SOF : STD_LOGIC; - signal TX_FCS_EOF : STD_LOGIC; - signal TX_FCS_MetaOut_rst : STD_LOGIC; - signal TX_FCS_MetaOut_nxt : STD_LOGIC_VECTOR(TX_FCS_META_BITS'length - 1 downto 0); - signal TX_FCS_MetaOut_Data : STD_LOGIC_VECTOR(isum(TX_FCS_META_BITS) - 1 downto 0); + signal TX_FCS_SOF : std_logic; + signal TX_FCS_EOF : std_logic; + signal TX_FCS_MetaOut_rst : std_logic; + signal TX_FCS_MetaOut_nxt : std_logic_vector(TX_FCS_META_BITS'length - 1 downto 0); + signal TX_FCS_MetaOut_Data : std_logic_vector(isum(TX_FCS_META_BITS) - 1 downto 0); signal TX_FCS_Meta_SrcIPAddress_Data : T_SLV_8; signal TX_FCS_Meta_DestIPAddress_Data : T_SLV_8; signal TX_FCS_Meta_SrcPort : T_SLV_16; @@ -199,20 +198,20 @@ architecture rtl of udp_Wrapper is signal TX_FCS_Meta_Checksum : T_SLV_16; signal TX_FCS_Meta_Length : T_SLV_16; - signal TX_FCS_Ack : STD_LOGIC; - signal TX_FCS_MetaIn_rst : STD_LOGIC; - signal TX_FCS_MetaIn_nxt : STD_LOGIC_VECTOR(TX_FCS_META_BITS'length - 1 downto 0); - signal TX_FCS_MetaIn_Data : STD_LOGIC_VECTOR(isum(TX_FCS_META_BITS) - 1 downto 0); + signal TX_FCS_Ack : std_logic; + signal TX_FCS_MetaIn_rst : std_logic; + signal TX_FCS_MetaIn_nxt : std_logic_vector(TX_FCS_META_BITS'length - 1 downto 0); + signal TX_FCS_MetaIn_Data : std_logic_vector(isum(TX_FCS_META_BITS) - 1 downto 0); - signal UDP_TX_Ack : STD_LOGIC; - signal UDP_TX_Meta_rst : STD_LOGIC; - signal UDP_TX_Meta_SrcIPAddress_nxt : STD_LOGIC; - signal UDP_TX_Meta_DestIPAddress_nxt : STD_LOGIC; + signal UDP_TX_Ack : std_logic; + signal UDP_TX_Meta_rst : std_logic; + signal UDP_TX_Meta_SrcIPAddress_nxt : std_logic; + signal UDP_TX_Meta_DestIPAddress_nxt : std_logic; - signal UDP_RX_Valid : STD_LOGIC; + signal UDP_RX_Valid : std_logic; signal UDP_RX_Data : T_SLV_8; - signal UDP_RX_SOF : STD_LOGIC; - signal UDP_RX_EOF : STD_LOGIC; + signal UDP_RX_SOF : std_logic; + signal UDP_RX_EOF : std_logic; signal UDP_RX_Meta_SrcMACAddress_Data : T_SLV_8; signal UDP_RX_Meta_DestMACAddress_Data : T_SLV_8; @@ -224,23 +223,23 @@ architecture rtl of udp_Wrapper is signal UDP_RX_Meta_SrcPort : T_SLV_16; signal UDP_RX_Meta_DestPort : T_SLV_16; - constant STMDEMUX_META_RST_BIT : NATURAL := 0; - constant STMDEMUX_META_MACSRC_NXT_BIT : NATURAL := 1; - constant STMDEMUX_META_MACDEST_NXT_BIT : NATURAL := 2; - constant STMDEMUX_META_IPSRC_NXT_BIT : NATURAL := 3; - constant STMDEMUX_META_IPDEST_NXT_BIT : NATURAL := 4; - - constant STMDEMUX_META_STREAMID_SRCMAC : NATURAL := 0; - constant STMDEMUX_META_STREAMID_DESTMAC : NATURAL := 1; - constant STMDEMUX_META_STREAMID_ETHTYPE : NATURAL := 2; - constant STMDEMUX_META_STREAMID_SRCIP : NATURAL := 3; - constant STMDEMUX_META_STREAMID_DESTIP : NATURAL := 4; - constant STMDEMUX_META_STREAMID_LENGTH : NATURAL := 5; - constant STMDEMUX_META_STREAMID_PROTO : NATURAL := 6; - constant STMDEMUX_META_STREAMID_SRCPORT : NATURAL := 7; - constant STMDEMUX_META_STREAMID_DESTPORT : NATURAL := 8; - - constant STMDEMUX_DATA_BITS : NATURAL := 8; -- + constant STMDEMUX_META_RST_BIT : natural := 0; + constant STMDEMUX_META_MACSRC_NXT_BIT : natural := 1; + constant STMDEMUX_META_MACDEST_NXT_BIT : natural := 2; + constant STMDEMUX_META_IPSRC_NXT_BIT : natural := 3; + constant STMDEMUX_META_IPDEST_NXT_BIT : natural := 4; + + constant STMDEMUX_META_STREAMID_SRCMAC : natural := 0; + constant STMDEMUX_META_STREAMID_DESTMAC : natural := 1; + constant STMDEMUX_META_STREAMID_ETHTYPE : natural := 2; + constant STMDEMUX_META_STREAMID_SRCIP : natural := 3; + constant STMDEMUX_META_STREAMID_DESTIP : natural := 4; + constant STMDEMUX_META_STREAMID_LENGTH : natural := 5; + constant STMDEMUX_META_STREAMID_PROTO : natural := 6; + constant STMDEMUX_META_STREAMID_SRCPORT : natural := 7; + constant STMDEMUX_META_STREAMID_DESTPORT : natural := 8; + + constant STMDEMUX_DATA_BITS : natural := 8; -- constant STMDEMUX_META_BITS : T_POSVEC := ( STMDEMUX_META_STREAMID_SRCMAC => 8, STMDEMUX_META_STREAMID_DESTMAC => 8, @@ -252,33 +251,33 @@ architecture rtl of udp_Wrapper is STMDEMUX_META_STREAMID_SRCPORT => 16, STMDEMUX_META_STREAMID_DESTPORT => 16 ); - constant STMDEMUX_META_REV_BITS : NATURAL := 5; -- sum over all control bits (rst, nxt, nxt, nxt, nxt) + constant STMDEMUX_META_REV_BITS : natural := 5; -- sum over all control bits (rst, nxt, nxt, nxt, nxt) - signal StmDeMux_Out_Ack : STD_LOGIC; - signal StmDeMux_Out_Meta_rst : STD_LOGIC; - signal StmDeMux_Out_Meta_SrcMACAddress_nxt : STD_LOGIC; - signal StmDeMux_Out_Meta_DestMACAddress_nxt : STD_LOGIC; - signal StmDeMux_Out_Meta_SrcIPAddress_nxt : STD_LOGIC; - signal StmDeMux_Out_Meta_DestIPAddress_nxt : STD_LOGIC; + signal StmDeMux_Out_Ack : std_logic; + signal StmDeMux_Out_Meta_rst : std_logic; + signal StmDeMux_Out_Meta_SrcMACAddress_nxt : std_logic; + signal StmDeMux_Out_Meta_DestMACAddress_nxt : std_logic; + signal StmDeMux_Out_Meta_SrcIPAddress_nxt : std_logic; + signal StmDeMux_Out_Meta_DestIPAddress_nxt : std_logic; - signal StmDeMux_Out_MetaIn : STD_LOGIC_VECTOR(isum(STMDEMUX_META_BITS) - 1 downto 0); - signal StmDeMux_Out_MetaIn_rev : STD_LOGIC_VECTOR(STMDEMUX_META_REV_BITS - 1 downto 0); + signal StmDeMux_Out_MetaIn : std_logic_vector(isum(STMDEMUX_META_BITS) - 1 downto 0); + signal StmDeMux_Out_MetaIn_rev : std_logic_vector(STMDEMUX_META_REV_BITS - 1 downto 0); signal StmDeMux_Out_Data : T_SLM(UDP_SWITCH_PORTS - 1 downto 0, STMDEMUX_DATA_BITS - 1 downto 0) := (others => (others => 'Z')); -- necessary default assignment 'Z' to get correct simulation results (iSIM, vSIM, ghdl/gtkwave) signal StmDeMux_Out_MetaOut : T_SLM(UDP_SWITCH_PORTS - 1 downto 0, isum(STMDEMUX_META_BITS) - 1 downto 0) := (others => (others => 'Z')); -- necessary default assignment 'Z' to get correct simulation results (iSIM, vSIM, ghdl/gtkwave) signal StmDeMux_Out_MetaOut_rev : T_SLM(UDP_SWITCH_PORTS - 1 downto 0, STMDEMUX_META_REV_BITS - 1 downto 0) := (others => (others => 'Z')); -- necessary default assignment 'Z' to get correct simulation results (iSIM, vSIM, ghdl/gtkwave) - signal StmDeMux_Control : STD_LOGIC_VECTOR(UDP_SWITCH_PORTS - 1 downto 0); + signal StmDeMux_Control : std_logic_vector(UDP_SWITCH_PORTS - 1 downto 0); begin - assert ((IP_VERSION = 4) OR (IP_VERSION = 6)) report "Unsupported Internet Protocol (IP) version." severity ERROR; + assert ((IP_VERSION = 4) or (IP_VERSION = 6)) report "Unsupported Internet Protocol (IP) version." severity ERROR; --- ============================================================================================================================================================ +-- ============================================================================= -- TX Path --- ============================================================================================================================================================ +-- ============================================================================= StmMux_In_Data <= to_slm(TX_Data); genStmMuxIn : for i in 0 to UDP_SWITCH_PORTS - 1 generate - signal Meta : STD_LOGIC_VECTOR(isum(STMMUX_META_BITS) - 1 downto 0); + signal Meta : std_logic_vector(isum(STMMUX_META_BITS) - 1 downto 0); begin Meta(high(STMMUX_META_BITS, STMMUX_META_STREAMID_SRCIP) downto low(STMMUX_META_BITS, STMMUX_META_STREAMID_SRCIP)) <= TX_Meta_SrcIPAddress_Data(i); Meta(high(STMMUX_META_BITS, STMMUX_META_STREAMID_DESTIP) downto low(STMMUX_META_BITS, STMMUX_META_STREAMID_DESTIP)) <= TX_Meta_DestIPAddress_Data(i); @@ -408,9 +407,9 @@ begin Out_Meta_Length => IP_TX_Meta_Length ); --- ============================================================================================================================================================ +-- ============================================================================= -- RX Path --- ============================================================================================================================================================ +-- ============================================================================= RX_UDP : entity PoC.udp_RX generic map ( DEBUG => DEBUG, diff --git a/src/sim/sim.files b/src/sim/sim.files index b942fcc3..713c705b 100644 --- a/src/sim/sim.files +++ b/src/sim/sim.files @@ -7,12 +7,12 @@ # PoC simulation packages if (ToolChain != "Cocotb") then vhdl poc "src/sim/sim_types.vhdl" # PoC simulation helper - if (VHDL < 2002) then + if (VHDLVersion < 2002) then vhdl poc "src/sim/sim_random.v93.vhdl" # PoC simulation helper vhdl poc "src/sim/sim_global.v93.vhdl" # PoC simulation helper vhdl poc "src/sim/sim_unprotected.v93.vhdl" # PoC simulation helper vhdl poc "src/sim/sim_simulation.v93.vhdl" # PoC simulation helper - elseif (VHDL >= 2002) then + elseif (VHDLVersion <= 2008) then vhdl poc "src/sim/sim_random.v08.vhdl" # PoC simulation helper vhdl poc "src/sim/sim_protected.v08.vhdl" # PoC simulation helper vhdl poc "src/sim/sim_global.v08.vhdl" # PoC simulation helper diff --git a/src/sim/sim_global.v08.vhdl b/src/sim/sim_global.v08.vhdl index 59b377fb..9d706a4b 100644 --- a/src/sim/sim_global.v08.vhdl +++ b/src/sim/sim_global.v08.vhdl @@ -1,15 +1,14 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Patrick Lehmann -- -- Package: Global simulation constants and shared varibales. -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: -- ============================================================================= diff --git a/src/sim/sim_global.v93.vhdl b/src/sim/sim_global.v93.vhdl index dee353d4..d3a594f7 100644 --- a/src/sim/sim_global.v93.vhdl +++ b/src/sim/sim_global.v93.vhdl @@ -1,15 +1,14 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Patrick Lehmann -- -- Package: Global simulation constants and shared varibales. -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: -- ============================================================================= @@ -37,30 +36,30 @@ use PoC.sim_types.all; package sim_global is -- The default global status objects. -- =========================================================================== - shared variable globalSim_StateIsInitialized : BOOLEAN := FALSE; - shared variable globalSim_StateIsFinalized : BOOLEAN := FALSE; + shared variable globalSim_StateIsInitialized : boolean := FALSE; + shared variable globalSim_StateIsFinalized : boolean := FALSE; - shared variable globalSim_MaxAssertFailures : NATURAL := NATURAL'high; - shared variable globalSim_MaxSimulationRuntime : TIME := TIME'high; + shared variable globalSim_MaxAssertFailures : natural := natural'high; + shared variable globalSim_MaxSimulationRuntime : time := time'high; -- Internal state variable to log a failure condition for final reporting. -- Once de-asserted, this variable will never return to a value of true. - shared variable globalSim_Passed : BOOLEAN := TRUE; - shared variable globalSim_AssertCount : NATURAL := 0; - shared variable globalSim_FailedAssertCount : NATURAL := 0; + shared variable globalSim_Passed : boolean := TRUE; + shared variable globalSim_AssertCount : natural := 0; + shared variable globalSim_FailedAssertCount : natural := 0; -- Clock Management shared variable globalSim_MainProcessEnables : T_SIM_BOOLVEC(T_SIM_TEST_ID) := (others => TRUE); shared variable globalSim_MainClockEnables : T_SIM_BOOLVEC(T_SIM_TEST_ID) := (others => TRUE); -- Process Management - shared variable globalSim_ProcessCount : NATURAL := 0; - shared variable globalSim_ActiveProcessCount : NATURAL := 0; + shared variable globalSim_ProcessCount : natural := 0; + shared variable globalSim_ActiveProcessCount : natural := 0; shared variable globalSim_Processes : T_SIM_PROCESS_VECTOR(T_SIM_PROCESS_ID); -- Test Management - shared variable globalSim_TestCount : NATURAL := 0; - shared variable globalSim_ActiveTestCount : NATURAL := 0; + shared variable globalSim_TestCount : natural := 0; + shared variable globalSim_ActiveTestCount : natural := 0; shared variable globalSim_Tests : T_SIM_TEST_VECTOR(T_SIM_TEST_ID); end package; diff --git a/src/sim/sim_protected.v08.vhdl b/src/sim/sim_protected.v08.vhdl index 7fd8a06c..b97ea1c1 100644 --- a/src/sim/sim_protected.v08.vhdl +++ b/src/sim/sim_protected.v08.vhdl @@ -1,7 +1,6 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Patrick Lehmann -- Thomas B. Preusser @@ -9,8 +8,8 @@ -- Package: Simulation constants, functions and utilities. -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: -- ============================================================================= @@ -49,25 +48,25 @@ package sim_protected is -- =========================================================================== type T_SIM_STATUS is protected -- Initializer and Finalizer - procedure initialize(MaxAssertFailures : NATURAL := NATURAL'high; MaxSimulationRuntime : TIME := TIME'high); + procedure initialize(MaxAssertFailures : natural := natural'high; MaxSimulationRuntime : TIME := TIME'high); procedure finalize; -- Assertions - procedure fail(Message : STRING := ""); - procedure assertion(Condition : BOOLEAN; Message : STRING := ""); - procedure writeMessage(Message : STRING); + procedure fail(Message : string := ""); + procedure assertion(Condition : boolean; Message : string := ""); + procedure writeMessage(Message : string); procedure writeReport; -- Process Management - impure function registerProcess(Name : STRING; IsLowPriority : BOOLEAN := FALSE) return T_SIM_PROCESS_ID; - impure function registerProcess(TestID : T_SIM_TEST_ID; Name : STRING; IsLowPriority : BOOLEAN := FALSE) return T_SIM_PROCESS_ID; - procedure deactivateProcess(procID : T_SIM_PROCESS_ID; SkipLowPriority : BOOLEAN := FALSE); + impure function registerProcess(Name : string; IsLowPriority : boolean := FALSE) return T_SIM_PROCESS_ID; + impure function registerProcess(TestID : T_SIM_TEST_ID; Name : string; IsLowPriority : boolean := FALSE) return T_SIM_PROCESS_ID; + procedure deactivateProcess(procID : T_SIM_PROCESS_ID; SkipLowPriority : boolean := FALSE); procedure stopAllProcesses; procedure stopProcesses(TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID); -- Test Management procedure createDefaultTest; - impure function createTest(Name : STRING) return T_SIM_TEST_ID; + impure function createTest(Name : string) return T_SIM_TEST_ID; procedure activateDefaultTest; procedure finalizeTest; procedure finalizeTest(TestID : T_SIM_TEST_ID); @@ -76,9 +75,9 @@ package sim_protected is procedure stopAllClocks; procedure stopClocks(TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID); - impure function isStopped(TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID) return BOOLEAN; - impure function isFinalized(TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID) return BOOLEAN; - impure function isAllFinalized return BOOLEAN; + impure function isStopped(TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID) return boolean; + impure function isFinalized(TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID) return boolean; + impure function isAllFinalized return boolean; end protected; end package; @@ -87,35 +86,35 @@ package body sim_protected is -- Simulation process and Status Management -- =========================================================================== type T_SIM_STATUS_STATE is record - IsInitialized : BOOLEAN; - IsFinalized : BOOLEAN; + IsInitialized : boolean; + IsFinalized : boolean; end record; type T_SIM_STATUS is protected body -- status variable State : T_SIM_STATUS_STATE := (FALSE, FALSE); - variable Max_AssertFailures : NATURAL := NATURAL'high; - variable Max_SimulationRuntime : TIME := TIME'high; + variable Max_AssertFailures : natural := natural'high; + variable Max_SimulationRuntime : time := time'high; -- Internal state variable to log a failure condition for final reporting. -- Once de-asserted, this variable will never return to a value of true. - variable Passed : BOOLEAN := TRUE; - variable AssertCount : NATURAL := 0; - variable FailedAssertCount : NATURAL := 0; + variable Passed : boolean := TRUE; + variable AssertCount : natural := 0; + variable FailedAssertCount : natural := 0; -- Clock Management variable MainProcessEnables : T_SIM_BOOLVEC(T_SIM_TEST_ID) := (others => TRUE); variable MainClockEnables : T_SIM_BOOLVEC(T_SIM_TEST_ID) := (others => TRUE); -- Process Management - variable ProcessCount : NATURAL := 0; - variable ActiveProcessCount : NATURAL := 0; + variable ProcessCount : natural := 0; + variable ActiveProcessCount : natural := 0; variable Processes : T_SIM_PROCESS_VECTOR(T_SIM_PROCESS_ID); -- Test Management - variable TestCount : NATURAL := 0; - variable ActiveTestCount : NATURAL := 0; + variable TestCount : natural := 0; + variable ActiveTestCount : natural := 0; variable Tests : T_SIM_TEST_VECTOR(T_SIM_TEST_ID); -- Initializer @@ -128,26 +127,19 @@ package body sim_protected is end if; end procedure; - procedure initialize(MaxAssertFailures : NATURAL := NATURAL'high; MaxSimulationRuntime : TIME := TIME'high) is + procedure initialize(MaxAssertFailures : natural := natural'high; MaxSimulationRuntime : TIME := TIME'high) is begin if C_SIM_VERBOSE then report "initialize:" severity NOTE; end if; init; Max_AssertFailures := MaxAssertFailures; Max_SimulationRuntime := MaxSimulationRuntime; - -- if (MaxSimulationRuntime /= TIME'high) then - -- wait until (State.IsFinalized = TRUE) for MaxSimulationRuntime; - -- report "initialize: TIMEOUT" severity ERROR; - -- finalize; - -- end if; end procedure; procedure finalize is - variable Dummy : BOOLEAN; begin if (State.IsFinalized = FALSE) then if C_SIM_VERBOSE then report "finalize: " severity NOTE; end if; State.IsFinalized := TRUE; - -- Dummy := finalizeDefaultTest; for i in C_SIM_DEFAULT_TEST_ID to TestCount - 1 loop finalizeTest(i); end loop; @@ -158,50 +150,50 @@ package body sim_protected is procedure writeReport_Header is variable LineBuffer : LINE; begin - write(LineBuffer, ( STRING'("========================================"))); - write(LineBuffer, (CR & STRING'("POC TESTBENCH REPORT"))); - write(LineBuffer, (CR & STRING'("========================================"))); + write(LineBuffer, ( string'("========================================"))); + write(LineBuffer, (LF & string'("POC TESTBENCH REPORT"))); + write(LineBuffer, (LF & string'("========================================"))); writeline(output, LineBuffer); end procedure; - procedure writeReport_TestReport(Prefix : STRING := "") is + procedure writeReport_TestReport(Prefix : string := "") is variable LineBuffer : LINE; begin if (Tests(C_SIM_DEFAULT_TEST_ID).Status /= SIM_TEST_STATUS_CREATED) then - write(LineBuffer, Prefix & "Tests " & INTEGER'image(TestCount + 1)); - write(LineBuffer, CR & Prefix & " " & str_ralign("-1", log10ceilnz(TestCount + 1) + 1) & ": " & C_SIM_DEFAULT_TEST_NAME); + write(LineBuffer, Prefix & "Tests " & integer'image(TestCount + 1)); + write(LineBuffer, LF & Prefix & " " & str_ralign("-1", log10ceilnz(TestCount + 1) + 1) & ": " & C_SIM_DEFAULT_TEST_NAME); else - write(LineBuffer, Prefix & "Tests " & INTEGER'image(TestCount)); + write(LineBuffer, Prefix & "Tests " & integer'image(TestCount)); end if; for i in 0 to TestCount - 1 loop - write(LineBuffer, CR & Prefix & " " & str_ralign(INTEGER'image(i), log10ceilnz(TestCount)) & ": " & str_trim(Tests(i).Name)); + write(LineBuffer, LF & Prefix & " " & str_ralign(integer'image(i), log10ceilnz(TestCount)) & ": " & str_trim(Tests(i).Name)); end loop; writeline(output, LineBuffer); end procedure; - procedure writeReport_AssertReport(Prefix : STRING := "") is + procedure writeReport_AssertReport(Prefix : string := "") is variable LineBuffer : LINE; begin - write(LineBuffer, Prefix & "Assertions " & INTEGER'image(AssertCount)); - write(LineBuffer, CR & Prefix & " failed " & INTEGER'image(FailedAssertCount) & ite((FailedAssertCount >= Max_AssertFailures), " Too many failed asserts!", "")); + write(LineBuffer, Prefix & "Assertions " & integer'image(AssertCount)); + write(LineBuffer, LF & Prefix & " failed " & integer'image(FailedAssertCount) & ite((FailedAssertCount >= Max_AssertFailures), " Too many failed asserts!", "")); writeline(output, LineBuffer); end procedure; - procedure writeReport_ProcessReport(Prefix : STRING := "") is + procedure writeReport_ProcessReport(Prefix : string := "") is variable LineBuffer : LINE; begin - write(LineBuffer, Prefix & "Processes " & INTEGER'image(ProcessCount)); - write(LineBuffer, CR & Prefix & " active " & INTEGER'image(ActiveProcessCount)); + write(LineBuffer, Prefix & "Processes " & integer'image(ProcessCount)); + write(LineBuffer, LF & Prefix & " active " & integer'image(ActiveProcessCount)); -- report killed processes for i in 0 to ProcessCount - 1 loop if ((Processes(i).Status = SIM_PROCESS_STATUS_ACTIVE) and (Processes(i).IsLowPriority = FALSE)) then - write(LineBuffer, CR & Prefix & " " & str_ralign(INTEGER'image(i), log10ceilnz(ProcessCount)) & ": " & str_trim(Processes(i).Name)); + write(LineBuffer, LF & Prefix & " " & str_ralign(integer'image(i), log10ceilnz(ProcessCount)) & ": " & str_trim(Processes(i).Name)); end if; end loop; writeline(output, LineBuffer); end procedure; - procedure writeReport_RuntimeReport(Prefix : STRING := "") is + procedure writeReport_RuntimeReport(Prefix : string := "") is variable LineBuffer : LINE; begin write(LineBuffer, Prefix & "Runtime " & to_string(now, 1)); @@ -211,12 +203,12 @@ package body sim_protected is procedure writeReport_SimulationResult is variable LineBuffer : LINE; begin - write(LineBuffer, ( STRING'("========================================"))); - if (AssertCount = 0) then write(LineBuffer, (CR & STRING'("SIMULATION RESULT = NO ASSERTS"))); - elsif (Passed = TRUE) then write(LineBuffer, (CR & STRING'("SIMULATION RESULT = PASSED"))); - else write(LineBuffer, (CR & STRING'("SIMULATION RESULT = FAILED"))); + write(LineBuffer, ( string'("========================================"))); + if not Passed then write(LineBuffer, (LF & string'("SIMULATION RESULT = FAILED"))); + elsif AssertCount = 0 then write(LineBuffer, (LF & string'("SIMULATION RESULT = NO ASSERTS"))); + elsif Passed then write(LineBuffer, (LF & string'("SIMULATION RESULT = PASSED"))); end if; - write(LineBuffer, (CR & STRING'("========================================"))); + write(LineBuffer, (LF & string'("========================================"))); writeline(output, LineBuffer); end procedure; @@ -225,7 +217,7 @@ package body sim_protected is begin writeReport_Header; writeReport_TestReport(""); - write(LineBuffer, CR & "Overall"); + write(LineBuffer, LF & "Overall"); writeline(output, LineBuffer); writeReport_AssertReport(" "); writeReport_ProcessReport(" "); @@ -233,10 +225,10 @@ package body sim_protected is writeReport_SimulationResult; end procedure; - procedure assertion(condition : BOOLEAN; Message : STRING := "") is + procedure assertion(condition : boolean; Message : string := "") is begin AssertCount := AssertCount + 1; - if (condition = FALSE) then + if not condition then fail(Message); FailedAssertCount := FailedAssertCount + 1; if (FailedAssertCount >= Max_AssertFailures) then @@ -245,7 +237,7 @@ package body sim_protected is end if; end procedure; - procedure fail(Message : STRING := "") is + procedure fail(Message : string := "") is begin if (Message'length > 0) then report Message severity ERROR; @@ -253,7 +245,7 @@ package body sim_protected is Passed := FALSE; end procedure; - procedure writeMessage(Message : STRING) is + procedure writeMessage(Message : string) is variable LineBuffer : LINE; begin write(LineBuffer, Message); @@ -277,7 +269,7 @@ package body sim_protected is Tests(Test.ID) := Test; end procedure; - impure function createTest(Name : STRING) return T_SIM_TEST_ID is + impure function createTest(Name : string) return T_SIM_TEST_ID is variable Test : T_SIM_TEST; begin if (State.IsInitialized = FALSE) then @@ -318,21 +310,21 @@ package body sim_protected is return; end if; - if (TestID = C_SIM_DEFAULT_TEST_ID) then + if TestID = C_SIM_DEFAULT_TEST_ID then if (Tests(C_SIM_DEFAULT_TEST_ID).Status = SIM_TEST_STATUS_CREATED) then - if C_SIM_VERBOSE then report "finalizeTest(" & INTEGER'image(C_SIM_DEFAULT_TEST_ID) & "): inactive" severity NOTE; end if; + if C_SIM_VERBOSE then report "finalizeTest(" & integer'image(C_SIM_DEFAULT_TEST_ID) & "): inactive" severity NOTE; end if; Tests(C_SIM_DEFAULT_TEST_ID).Status := SIM_TEST_STATUS_ENDED; stopProcesses(C_SIM_DEFAULT_TEST_ID); return; elsif (Tests(C_SIM_DEFAULT_TEST_ID).Status = SIM_TEST_STATUS_ACTIVE) then - if (ActiveTestCount > 1) then + if ActiveTestCount > 1 then for ProcIdx in 0 to Tests(C_SIM_DEFAULT_TEST_ID).ProcessCount - 1 loop deactivateProcess(Tests(C_SIM_DEFAULT_TEST_ID).ProcessIDs(ProcIdx), TRUE); end loop; Tests(C_SIM_DEFAULT_TEST_ID).Status := SIM_TEST_STATUS_ZOMBI; return; else - if C_SIM_VERBOSE then report "finalizeTest(" & INTEGER'image(C_SIM_DEFAULT_TEST_ID) & "): active" severity NOTE; end if; + if C_SIM_VERBOSE then report "finalizeTest(" & integer'image(C_SIM_DEFAULT_TEST_ID) & "): active" severity NOTE; end if; Tests(C_SIM_DEFAULT_TEST_ID).Status := SIM_TEST_STATUS_ENDED; ActiveTestCount := ActiveTestCount - 1; stopProcesses(C_SIM_DEFAULT_TEST_ID); @@ -344,7 +336,7 @@ package body sim_protected is ActiveTestCount := ActiveTestCount - 1; if (Tests(TestID).ActiveProcessCount > 0) then - report "Test " & INTEGER'image(TestID) & " '" & str_trim(Tests(TestID).Name) & "' has still active process while finalizing:" severity WARNING; + fail("Test " & integer'image(TestID) & " '" & str_trim(Tests(TestID).Name) & "' has still active process while finalizing:"); for ProcIdx in 0 to Tests(TestID).ProcessCount - 1 loop if (Processes(Tests(TestID).ProcessIDs(ProcIdx)).Status = SIM_PROCESS_STATUS_ACTIVE) then report " " & Processes(Tests(TestID).ProcessIDs(ProcIdx)).Name severity WARNING; @@ -354,31 +346,33 @@ package body sim_protected is stopProcesses(TestID); end if; - if (ActiveTestCount = 0) then + if ActiveTestCount = 0 then finalize; - elsif (ActiveTestCount = 1) then + elsif ActiveTestCount = 1 then if (Tests(C_SIM_DEFAULT_TEST_ID).Status = SIM_TEST_STATUS_ACTIVE) then finalizeTest(C_SIM_DEFAULT_TEST_ID); elsif (Tests(C_SIM_DEFAULT_TEST_ID).Status = SIM_TEST_STATUS_ZOMBI) then stopProcesses(C_SIM_DEFAULT_TEST_ID); + else + return; end if; finalize; end if; end procedure; - impure function registerProcess(Name : STRING; IsLowPriority : BOOLEAN := FALSE) return T_SIM_PROCESS_ID is + impure function registerProcess(Name : string; IsLowPriority : boolean := FALSE) return T_SIM_PROCESS_ID is begin return registerProcess(C_SIM_DEFAULT_TEST_ID, Name, IsLowPriority); end function; - impure function registerProcess(TestID : T_SIM_TEST_ID; Name : STRING; IsLowPriority : BOOLEAN := FALSE) return T_SIM_PROCESS_ID is + impure function registerProcess(TestID : T_SIM_TEST_ID; Name : string; IsLowPriority : boolean := FALSE) return T_SIM_PROCESS_ID is variable Proc : T_SIM_PROCESS; variable TestProcID : T_SIM_TEST_ID; begin if (State.IsInitialized = FALSE) then init; end if; - if (TestID = C_SIM_DEFAULT_TEST_ID) then + if TestID = C_SIM_DEFAULT_TEST_ID then activateDefaultTest; end if; @@ -397,17 +391,17 @@ package body sim_protected is -- add process to list Processes(Proc.ID) := Proc; ProcessCount := ProcessCount + 1; - ActiveProcessCount := inc(not IsLowPriority, ActiveProcessCount); + ActiveProcessCount := inc_if(not IsLowPriority, ActiveProcessCount); -- add process to test TestProcID := Tests(TestID).ProcessCount; Tests(TestID).ProcessIDs(TestProcID) := Proc.ID; Tests(TestID).ProcessCount := TestProcID + 1; - Tests(TestID).ActiveProcessCount := inc(not IsLowPriority, Tests(TestID).ActiveProcessCount); + Tests(TestID).ActiveProcessCount := inc_if(not IsLowPriority, Tests(TestID).ActiveProcessCount); -- return the process ID return Proc.ID; end function; - procedure deactivateProcess(ProcID : T_SIM_PROCESS_ID; SkipLowPriority : BOOLEAN := FALSE) is + procedure deactivateProcess(ProcID : T_SIM_PROCESS_ID; SkipLowPriority : boolean := FALSE) is variable TestID : T_SIM_TEST_ID; begin if (ProcID >= ProcessCount) then @@ -422,8 +416,8 @@ package body sim_protected is if (Processes(ProcID).Status = SIM_PROCESS_STATUS_ACTIVE) then if C_SIM_VERBOSE then report "deactivateProcess(ProcID=" & T_SIM_PROCESS_ID'image(ProcID) & "): TestID=" & T_SIM_TEST_ID'image(TestID) & " Name=" & str_trim(Processes(ProcID).Name) severity NOTE; end if; Processes(ProcID).Status := SIM_PROCESS_STATUS_ENDED; - ActiveProcessCount := dec(not Processes(ProcID).IsLowPriority, ActiveProcessCount); - Tests(TestID).ActiveProcessCount := dec(not Processes(ProcID).IsLowPriority, Tests(TestID).ActiveProcessCount); + ActiveProcessCount := dec_if(not Processes(ProcID).IsLowPriority, ActiveProcessCount); + Tests(TestID).ActiveProcessCount := dec_if(not Processes(ProcID).IsLowPriority, Tests(TestID).ActiveProcessCount); if (Tests(TestID).ActiveProcessCount = 0) then finalizeTest(TestID); end if; @@ -469,20 +463,20 @@ package body sim_protected is MainClockEnables(TestID) := FALSE; end procedure; - impure function isStopped(TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID) return BOOLEAN is + impure function isStopped(TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID) return boolean is begin return not MainClockEnables(TestID); end function; - impure function isFinalized(TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID) return BOOLEAN is + impure function isFinalized(TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID) return boolean is begin return (Tests(TestID).Status = SIM_TEST_STATUS_ENDED); end function; - impure function isAllFinalized return BOOLEAN is + impure function isAllFinalized return boolean is begin if (State.IsFinalized = TRUE) then - if (ActiveTestCount = 0) then + if ActiveTestCount = 0 then return TRUE; end if; report "isAllFinalized: " severity ERROR; diff --git a/src/sim/sim_random.v08.vhdl b/src/sim/sim_random.v08.vhdl index 4f06f7b7..ffc7a71f 100644 --- a/src/sim/sim_random.v08.vhdl +++ b/src/sim/sim_random.v08.vhdl @@ -1,15 +1,14 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Patrick Lehmann -- -- Package: Simulation constants, functions and utilities. -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: -- ============================================================================= @@ -61,31 +60,31 @@ package sim_random is -- protected type interface type T_RANDOM is protected procedure SetSeed; - procedure SetSeed(Seed1 : INTEGER; Seed2 : INTEGER); + procedure SetSeed(Seed1 : integer; Seed2 : integer); procedure SetSeed(SeedValue : T_SIM_SEED); procedure SetSeed(SeedVector : T_INTVEC); - procedure SetSeed(SeedVector : STRING); + procedure SetSeed(SeedVector : string); impure function GetSeed return T_SIM_SEED; procedure GetUniformDistributedValue(Value : out REAL); - procedure GetUniformDistributedValue(Value : out INTEGER; Minimum : in INTEGER; Maximum : in INTEGER); + procedure GetUniformDistributedValue(Value : out integer; Minimum : in integer; Maximum : in integer); procedure GetUniformDistributedValue(Value : out REAL; Minimum : in REAL; Maximum : in REAL); impure function GetUniformDistributedValue return REAL; - impure function GetUniformDistributedValue(Minimum : in INTEGER; Maximum : in INTEGER) return INTEGER; + impure function GetUniformDistributedValue(Minimum : in integer; Maximum : in integer) return integer; impure function GetUniformDistributedValue(Minimum : in REAL; Maximum : in REAL) return REAL; procedure GetNormalDistributedValue(Value : out REAL; StandardDeviation : in REAL := 1.0; Mean : in REAL := 0.0); - procedure GetNormalDistributedValue(Value : out INTEGER; StandardDeviation : in REAL; Mean : in REAL; Minimum : in INTEGER; Maximum : in INTEGER); + procedure GetNormalDistributedValue(Value : out integer; StandardDeviation : in REAL; Mean : in REAL; Minimum : in integer; Maximum : in integer); procedure GetNormalDistributedValue(Value : out REAL; StandardDeviation : in REAL; Mean : in REAL; Minimum : in REAL; Maximum : in REAL); impure function GetNormalDistributedValue(StandardDeviation : in REAL := 1.0; Mean : in REAL := 0.0) return REAL; - impure function GetNormalDistributedValue(StandardDeviation : in REAL; Mean : in REAL; Minimum : in INTEGER; Maximum : in INTEGER) return INTEGER; + impure function GetNormalDistributedValue(StandardDeviation : in REAL; Mean : in REAL; Minimum : in integer; Maximum : in integer) return integer; impure function GetNormalDistributedValue(StandardDeviation : in REAL; Mean : in REAL; Minimum : in REAL; Maximum : in REAL) return REAL; procedure GetPoissonDistributedValue(Value : out REAL; Mean : in REAL); - procedure GetPoissonDistributedValue(Value : out INTEGER; Mean : in REAL; Minimum : in INTEGER; Maximum : in INTEGER); + procedure GetPoissonDistributedValue(Value : out integer; Mean : in REAL; Minimum : in integer; Maximum : in integer); procedure GetPoissonDistributedValue(Value : out REAL; Mean : in REAL; Minimum : in REAL; Maximum : in REAL); impure function GetPoissonDistributedValue(Mean : in REAL) return REAL; - impure function GetPoissonDistributedValue(Mean : in REAL; Minimum : in INTEGER; Maximum : in INTEGER) return INTEGER; + impure function GetPoissonDistributedValue(Mean : in REAL; Minimum : in integer; Maximum : in integer) return integer; impure function GetPoissonDistributedValue(Mean : in REAL; Minimum : in REAL; Maximum : in REAL) return REAL; end protected; end package; @@ -101,7 +100,7 @@ package body sim_random is Local_Seed := randInitializeSeed; end procedure; - procedure SetSeed(Seed1 : INTEGER; Seed2 : INTEGER) is + procedure SetSeed(Seed1 : integer; Seed2 : integer) is begin Local_Seed := randInitializeSeed(T_SIM_RAND_SEED'(Seed1, Seed2)); end procedure; @@ -116,7 +115,7 @@ package body sim_random is Local_Seed := randInitializeSeed(SeedVector); end procedure; - procedure SetSeed(SeedVector : STRING) is + procedure SetSeed(SeedVector : string) is begin Local_Seed := randInitializeSeed(SeedVector); end procedure; @@ -139,14 +138,14 @@ package body sim_random is randUniformDistributedValue(Local_Seed, Value); end procedure; - impure function GetUniformDistributedValue(Minimum : in INTEGER; Maximum : in INTEGER) return INTEGER is - variable Result : INTEGER; + impure function GetUniformDistributedValue(Minimum : in integer; Maximum : in integer) return integer is + variable Result : integer; begin randUniformDistributedValue(Local_Seed, Result, Minimum, Maximum); return Result; end function; - procedure getUniformDistributedValue(Value : out INTEGER; Minimum : in INTEGER; Maximum : in INTEGER) is + procedure getUniformDistributedValue(Value : out integer; Minimum : in integer; Maximum : in integer) is begin randUniformDistributedValue(Local_Seed, Value, Minimum, Maximum); end procedure; @@ -176,14 +175,14 @@ package body sim_random is randNormalDistributedValue(Local_Seed, Value, StandardDeviation, Mean); end procedure; - impure function getNormalDistributedValue(StandardDeviation : in REAL; Mean : in REAL; Minimum : in INTEGER; Maximum : in INTEGER) return INTEGER is - variable Result : INTEGER; + impure function getNormalDistributedValue(StandardDeviation : in REAL; Mean : in REAL; Minimum : in integer; Maximum : in integer) return integer is + variable Result : integer; begin randNormalDistributedValue(Local_Seed, Result, StandardDeviation, Mean, Minimum, Maximum); return Result; end function; - procedure getNormalDistributedValue(Value : out INTEGER; StandardDeviation : in REAL; Mean : in REAL; Minimum : in INTEGER; Maximum : in INTEGER) is + procedure getNormalDistributedValue(Value : out integer; StandardDeviation : in REAL; Mean : in REAL; Minimum : in integer; Maximum : in integer) is begin randNormalDistributedValue(Local_Seed, Value, StandardDeviation, Mean, Minimum, Maximum); end procedure; @@ -213,14 +212,14 @@ package body sim_random is randPoissonDistributedValue(Local_Seed, Value, Mean); end procedure; - impure function getPoissonDistributedValue(Mean : in REAL; Minimum : in INTEGER; Maximum : in INTEGER) return INTEGER is - variable Result : INTEGER; + impure function getPoissonDistributedValue(Mean : in REAL; Minimum : in integer; Maximum : in integer) return integer is + variable Result : integer; begin randPoissonDistributedValue(Local_Seed, Result, Mean, Minimum, Maximum); return Result; end function; - procedure getPoissonDistributedValue(Value : out INTEGER; Mean : in REAL; Minimum : in INTEGER; Maximum : in INTEGER) is + procedure getPoissonDistributedValue(Value : out integer; Mean : in REAL; Minimum : in integer; Maximum : in integer) is begin randPoissonDistributedValue(Local_Seed, Value, Mean, Minimum, Maximum); end procedure; diff --git a/src/sim/sim_random.v93.vhdl b/src/sim/sim_random.v93.vhdl index 2e95b2cb..30df741f 100644 --- a/src/sim/sim_random.v93.vhdl +++ b/src/sim/sim_random.v93.vhdl @@ -1,15 +1,14 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Patrick Lehmann -- -- Package: Simulation constants, functions and utilities. -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: -- ============================================================================= @@ -50,38 +49,38 @@ package sim_random is -- procedural interface procedure randomInitializeSeed; procedure randomInitializeSeed(Seed : T_SIM_SEED); - procedure randomInitializeSeed(Seed1 : INTEGER; Seed2 : INTEGER); + procedure randomInitializeSeed(Seed1 : integer; Seed2 : integer); procedure randomInitializeSeed(SeedVector : T_INTVEC); - procedure randomInitializeSeed(SeedVector : STRING); + procedure randomInitializeSeed(SeedVector : string); -- Uniform distributed random values -- =========================================================================== procedure randomUniformDistributedValue(Value : out REAL); - procedure randomUniformDistributedValue(Value : out INTEGER; Minimum : in INTEGER; Maximum : in INTEGER); + procedure randomUniformDistributedValue(Value : out integer; Minimum : in integer; Maximum : in integer); procedure randomUniformDistributedValue(Value : out REAL; Minimum : in REAL; Maximum : in REAL); impure function randomUniformDistributedValue return REAL; - impure function randomUniformDistributedValue(Minimum : in INTEGER; Maximum : in INTEGER) return INTEGER; + impure function randomUniformDistributedValue(Minimum : in integer; Maximum : in integer) return integer; impure function randomUniformDistributedValue(Minimum : in REAL; Maximum : in REAL) return REAL; -- Normal / Gaussian distributed random values -- =========================================================================== procedure randomNormalDistributedValue(Value : out REAL; StandardDeviation : in REAL := 1.0; Mean : in REAL := 0.0); - procedure randomNormalDistributedValue(Value : out INTEGER; StandardDeviation : in REAL; Mean : in REAL; Minimum : in INTEGER; Maximum : in INTEGER); + procedure randomNormalDistributedValue(Value : out integer; StandardDeviation : in REAL; Mean : in REAL; Minimum : in integer; Maximum : in integer); procedure randomNormalDistributedValue(Value : out REAL; StandardDeviation : in REAL; Mean : in REAL; Minimum : in REAL; Maximum : in REAL); impure function randomNormalDistributedValue(StandardDeviation : in REAL := 1.0; Mean : in REAL := 0.0) return REAL; - impure function randomNormalDistributedValue(StandardDeviation : in REAL; Mean : in REAL; Minimum : in INTEGER; Maximum : in INTEGER) return INTEGER; + impure function randomNormalDistributedValue(StandardDeviation : in REAL; Mean : in REAL; Minimum : in integer; Maximum : in integer) return integer; impure function randomNormalDistributedValue(StandardDeviation : in REAL; Mean : in REAL; Minimum : in REAL; Maximum : in REAL) return REAL; -- Poisson distributed random values -- =========================================================================== procedure randomPoissonDistributedValue(Value : out REAL; Mean : in REAL); - procedure randomPoissonDistributedValue(Value : out INTEGER; Mean : in REAL; Minimum : in INTEGER; Maximum : in INTEGER); + procedure randomPoissonDistributedValue(Value : out integer; Mean : in REAL; Minimum : in integer; Maximum : in integer); procedure randomPoissonDistributedValue(Value : out REAL; Mean : in REAL; Minimum : in REAL; Maximum : in REAL); impure function randomPoissonDistributedValue(Mean : in REAL) return REAL; - impure function randomPoissonDistributedValue(Mean : in REAL; Minimum : in INTEGER; Maximum : in INTEGER) return INTEGER; + impure function randomPoissonDistributedValue(Mean : in REAL; Minimum : in integer; Maximum : in integer) return integer; impure function randomPoissonDistributedValue(Mean : in REAL; Minimum : in REAL; Maximum : in REAL) return REAL; end package; @@ -99,7 +98,7 @@ package body sim_random is randInitializeSeed(SeedValue, Seed); end procedure; - procedure randomInitializeSeed(Seed1 : INTEGER; Seed2 : INTEGER) is + procedure randomInitializeSeed(Seed1 : integer; Seed2 : integer) is begin randInitializeSeed(SeedValue, T_SIM_RAND_SEED'(Seed1, Seed2)); end procedure; @@ -109,7 +108,7 @@ package body sim_random is randInitializeSeed(SeedValue, SeedVector); end procedure; - procedure randomInitializeSeed(SeedVector : STRING) is + procedure randomInitializeSeed(SeedVector : string) is begin randInitializeSeed(SeedValue, SeedVector); end procedure; @@ -122,7 +121,7 @@ package body sim_random is randUniformDistributedValue(SeedValue, Value); end procedure; - procedure randomUniformDistributedValue(Value : out INTEGER; Minimum : in INTEGER; Maximum : in INTEGER) is + procedure randomUniformDistributedValue(Value : out integer; Minimum : in integer; Maximum : in integer) is begin randUniformDistributedValue(SeedValue, Value, Minimum, Maximum); end procedure; @@ -139,8 +138,8 @@ package body sim_random is return Result; end function; - impure function randomUniformDistributedValue(Minimum : in INTEGER; Maximum : in INTEGER) return INTEGER is - variable Result : INTEGER; + impure function randomUniformDistributedValue(Minimum : in integer; Maximum : in integer) return integer is + variable Result : integer; begin randUniformDistributedValue(SeedValue, Result, Minimum, Maximum); return Result; @@ -161,7 +160,7 @@ package body sim_random is randNormalDistributedValue(SeedValue, Value, StandardDeviation, Mean); end procedure; - procedure randomNormalDistributedValue(Value : out INTEGER; StandardDeviation : in REAL; Mean : in REAL; Minimum : in INTEGER; Maximum : in INTEGER) is + procedure randomNormalDistributedValue(Value : out integer; StandardDeviation : in REAL; Mean : in REAL; Minimum : in integer; Maximum : in integer) is begin randNormalDistributedValue(SeedValue, Value, StandardDeviation, Mean, Minimum, Maximum); end procedure; @@ -178,8 +177,8 @@ package body sim_random is return Result; end function; - impure function randomNormalDistributedValue(StandardDeviation : in REAL; Mean : in REAL; Minimum : in INTEGER; Maximum : in INTEGER) return INTEGER is - variable Result : INTEGER; + impure function randomNormalDistributedValue(StandardDeviation : in REAL; Mean : in REAL; Minimum : in integer; Maximum : in integer) return integer is + variable Result : integer; begin randNormalDistributedValue(SeedValue, Result, StandardDeviation, Mean, Minimum, Maximum); return Result; @@ -200,7 +199,7 @@ package body sim_random is randPoissonDistributedValue(SeedValue, Value, Mean); end procedure; - procedure randomPoissonDistributedValue(Value : out INTEGER; Mean : in REAL; Minimum : in INTEGER; Maximum : in INTEGER) is + procedure randomPoissonDistributedValue(Value : out integer; Mean : in REAL; Minimum : in integer; Maximum : in integer) is begin randPoissonDistributedValue(SeedValue, Value, Mean, Minimum, Maximum); end procedure; @@ -217,8 +216,8 @@ package body sim_random is return Result; end function; - impure function randomPoissonDistributedValue(Mean : in REAL; Minimum : in INTEGER; Maximum : in INTEGER) return INTEGER is - variable Result : INTEGER; + impure function randomPoissonDistributedValue(Mean : in REAL; Minimum : in integer; Maximum : in integer) return integer is + variable Result : integer; begin randPoissonDistributedValue(SeedValue, Result, Mean, Minimum, Maximum); return Result; diff --git a/src/sim/sim_simulation.v08.vhdl b/src/sim/sim_simulation.v08.vhdl index 526f8065..6eec27c4 100644 --- a/src/sim/sim_simulation.v08.vhdl +++ b/src/sim/sim_simulation.v08.vhdl @@ -1,7 +1,6 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Patrick Lehmann -- Thomas B. Preusser @@ -9,8 +8,8 @@ -- Package: Simulation constants, functions and utilities. -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: -- ============================================================================= @@ -67,22 +66,22 @@ package simulation is -- alias simmFail is globalSimulationStatus.fail[STRING]; -- alias simmWriteMessage is globalSimulationStatus.writeMessage[STRING]; - procedure simInitialize(MaxAssertFailures : NATURAL := NATURAL'high; MaxSimulationRuntime : TIME := TIME'high); + procedure simInitialize(MaxAssertFailures : natural := natural'high; MaxSimulationRuntime : TIME := TIME'high); procedure simFinalize; - impure function simCreateTest(Name : STRING) return T_SIM_TEST_ID; + impure function simCreateTest(Name : string) return T_SIM_TEST_ID; procedure simFinalizeTest(constant TestID : T_SIM_TEST_ID); - impure function simRegisterProcess(Name : STRING; constant IsLowPriority : BOOLEAN := FALSE) return T_SIM_PROCESS_ID; - impure function simRegisterProcess(constant TestID : T_SIM_TEST_ID; Name : STRING; constant IsLowPriority : BOOLEAN := FALSE) return T_SIM_PROCESS_ID; + impure function simRegisterProcess(Name : string; constant IsLowPriority : boolean := FALSE) return T_SIM_PROCESS_ID; + impure function simRegisterProcess(constant TestID : T_SIM_TEST_ID; Name : string; constant IsLowPriority : boolean := FALSE) return T_SIM_PROCESS_ID; procedure simDeactivateProcess(ProcID : T_SIM_PROCESS_ID); - impure function simIsStopped(constant TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID) return BOOLEAN; - impure function simIsFinalized(constant TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID) return BOOLEAN; - impure function simIsAllFinalized return BOOLEAN; + impure function simIsStopped(constant TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID) return boolean; + impure function simIsFinalized(constant TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID) return boolean; + impure function simIsAllFinalized return boolean; - procedure simAssertion(cond : in BOOLEAN; Message : in STRING := ""); - procedure simFail(Message : in STRING := ""); - procedure simWriteMessage(Message : in STRING := ""); + procedure simAssertion(cond : in boolean; Message : in string := ""); + procedure simFail(Message : in string := ""); + procedure simWriteMessage(Message : in string := ""); -- TODO: integrate VCD simulation functions and procedures from sim_value_change_dump.vhdl here @@ -96,11 +95,11 @@ package body simulation is -- legacy procedures -- =========================================================================== -- TODO: undocumented group - procedure simInitialize(MaxAssertFailures : NATURAL := NATURAL'high; MaxSimulationRuntime : TIME := TIME'high) is + procedure simInitialize(MaxAssertFailures : natural := natural'high; MaxSimulationRuntime : TIME := TIME'high) is begin globalSimulationStatus.initialize(MaxAssertFailures, MaxSimulationRuntime); if C_SIM_VERBOSE then report "simInitialize:" severity NOTE; end if; - if (MaxSimulationRuntime /= TIME'high) then + if (MaxSimulationRuntime /= time'high) then wait for MaxSimulationRuntime; report "simInitialize: TIMEOUT" severity ERROR; globalSimulationStatus.finalize; @@ -112,7 +111,7 @@ package body simulation is globalSimulationStatus.finalize; end procedure; - impure function simCreateTest(Name : STRING) return T_SIM_TEST_ID is + impure function simCreateTest(Name : string) return T_SIM_TEST_ID is begin return globalSimulationStatus.createTest(Name); end function; @@ -122,12 +121,12 @@ package body simulation is globalSimulationStatus.finalizeTest(TestID); end procedure; - impure function simRegisterProcess(Name : STRING; constant IsLowPriority : BOOLEAN := FALSE) return T_SIM_PROCESS_ID is + impure function simRegisterProcess(Name : string; constant IsLowPriority : boolean := FALSE) return T_SIM_PROCESS_ID is begin return globalSimulationStatus.registerProcess(Name, IsLowPriority); end function; - impure function simRegisterProcess(constant TestID : T_SIM_TEST_ID; Name : STRING; constant IsLowPriority : BOOLEAN := FALSE) return T_SIM_PROCESS_ID is + impure function simRegisterProcess(constant TestID : T_SIM_TEST_ID; Name : string; constant IsLowPriority : boolean := FALSE) return T_SIM_PROCESS_ID is begin return globalSimulationStatus.registerProcess(TestID, Name, IsLowPriority); end function; @@ -137,33 +136,33 @@ package body simulation is globalSimulationStatus.deactivateProcess(ProcID); end procedure; - impure function simIsStopped(constant TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID) return BOOLEAN is + impure function simIsStopped(constant TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID) return boolean is begin return globalSimulationStatus.isStopped(TestID); end function; - impure function simIsFinalized(constant TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID) return BOOLEAN is + impure function simIsFinalized(constant TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID) return boolean is begin return globalSimulationStatus.isFinalized(TestID); end function; - impure function simIsAllFinalized return BOOLEAN is + impure function simIsAllFinalized return boolean is begin return globalSimulationStatus.isAllFinalized; end function; -- TODO: undocumented group - procedure simWriteMessage(Message : in STRING := "") is + procedure simWriteMessage(Message : in string := "") is begin globalSimulationStatus.writeMessage(Message); end procedure; - procedure simFail(Message : in STRING := "") is + procedure simFail(Message : in string := "") is begin globalSimulationStatus.fail(Message); end procedure; - procedure simAssertion(cond : in BOOLEAN; Message : in STRING := "") is + procedure simAssertion(cond : in boolean; Message : in string := "") is begin globalSimulationStatus.assertion(cond, Message); end procedure; diff --git a/src/sim/sim_simulation.v93.vhdl b/src/sim/sim_simulation.v93.vhdl index 9802698a..e418fb15 100644 --- a/src/sim/sim_simulation.v93.vhdl +++ b/src/sim/sim_simulation.v93.vhdl @@ -1,7 +1,6 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Patrick Lehmann -- Thomas B. Preusser @@ -10,8 +9,8 @@ -- Package: Simulation constants, functions and utilities. -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: -- ============================================================================= @@ -42,29 +41,29 @@ use PoC.sim_unprotected.all; package simulation is -- mimic definition of VHDL-2008 - type TIME_VECTOR is array(natural range<>) of TIME; + type TIME_VECTOR is array(natural range<>) of time; -- Testbench Status Management -- =========================================================================== -- alias simInitialize is work.sim_unprotected.initialize[NATURAL, TIME]; - procedure simInitialize(MaxAssertFailures : NATURAL := NATURAL'high; MaxSimulationRuntime : TIME := TIME'high); + procedure simInitialize(MaxAssertFailures : natural := natural'high; MaxSimulationRuntime : TIME := TIME'high); alias simFinalize is work.sim_unprotected.finalize[]; - alias simCreateTest is work.sim_unprotected.createTest[STRING return T_SIM_TEST_ID]; + alias simCreateTest is work.sim_unprotected.createTest[string return T_SIM_TEST_ID]; alias simFinalizeTest is work.sim_unprotected.finalizeTest[T_SIM_TEST_ID]; - alias simRegisterProcess is work.sim_unprotected.registerProcess[T_SIM_TEST_ID, STRING, BOOLEAN return T_SIM_PROCESS_ID]; - alias simRegisterProcess is work.sim_unprotected.registerProcess[STRING, BOOLEAN return T_SIM_PROCESS_ID]; + alias simRegisterProcess is work.sim_unprotected.registerProcess[T_SIM_TEST_ID, string, boolean return T_SIM_PROCESS_ID]; + alias simRegisterProcess is work.sim_unprotected.registerProcess[string, boolean return T_SIM_PROCESS_ID]; alias simDeactivateProcess is work.sim_unprotected.deactivateProcess[T_SIM_PROCESS_ID]; procedure simStopAllClocks; --alias simStopAllClocks is work.sim_unprotected.stopAllClocks[]; - alias simIsStopped is work.sim_unprotected.isStopped[T_SIM_TEST_ID return BOOLEAN]; - alias simIsFinalized is work.sim_unprotected.isFinalized[T_SIM_TEST_ID return BOOLEAN]; - alias simIsAllFinalized is work.sim_unprotected.isAllFinalized [return BOOLEAN]; + alias simIsStopped is work.sim_unprotected.isStopped[T_SIM_TEST_ID return boolean]; + alias simIsFinalized is work.sim_unprotected.isFinalized[T_SIM_TEST_ID return boolean]; + alias simIsAllFinalized is work.sim_unprotected.isAllFinalized [return boolean]; - alias simAssertion is work.sim_unprotected.assertion[BOOLEAN, STRING]; - alias simFail is work.sim_unprotected.fail[STRING]; - alias simWriteMessage is work.sim_unprotected.writeMessage[STRING]; + alias simAssertion is work.sim_unprotected.assertion[boolean, string]; + alias simFail is work.sim_unprotected.fail[string]; + alias simWriteMessage is work.sim_unprotected.writeMessage[string]; -- checksum functions -- =========================================================================== @@ -72,11 +71,11 @@ package simulation is end package; package body simulation is - procedure simInitialize(MaxAssertFailures : NATURAL := NATURAL'high; MaxSimulationRuntime : TIME := TIME'high) is + procedure simInitialize(MaxAssertFailures : natural := natural'high; MaxSimulationRuntime : TIME := TIME'high) is begin work.sim_unprotected.initialize(MaxAssertFailures, MaxSimulationRuntime); if C_SIM_VERBOSE then report "simInitialize:" severity NOTE; end if; - if (MaxSimulationRuntime /= TIME'high) then + if (MaxSimulationRuntime /= time'high) then wait for MaxSimulationRuntime; report "simInitialize: TIMEOUT" severity ERROR; work.sim_unprotected.finalize; @@ -87,4 +86,4 @@ package body simulation is begin work.sim_unprotected.stopAllClocks; end procedure; -end package body; \ No newline at end of file +end package body; diff --git a/src/sim/sim_types.vhdl b/src/sim/sim_types.vhdl index ba0949c7..d8fa1f68 100644 --- a/src/sim/sim_types.vhdl +++ b/src/sim/sim_types.vhdl @@ -1,7 +1,6 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Patrick Lehmann -- Thomas B. Preusser @@ -9,8 +8,8 @@ -- Package: Simulation constants, functions and utilities. -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: -- ============================================================================= @@ -43,22 +42,20 @@ use PoC.vectors.all; package sim_types is - attribute pocIsSimulation : BOOLEAN; - attribute pocIsSimulation of sim_types : package is TRUE; - constant C_SIM_VERBOSE : BOOLEAN := FALSE; -- POC_VERBOSE + constant C_SIM_VERBOSE : boolean := FALSE; -- POC_VERBOSE -- =========================================================================== -- Simulation Task and Status Management -- =========================================================================== - type T_SIM_BOOLVEC is array(INTEGER range <>) of BOOLEAN; + type T_SIM_BOOLVEC is array(integer range <>) of boolean; - subtype T_SIM_TEST_ID is INTEGER range -1 to 1023; - subtype T_SIM_TEST_NAME is STRING(1 to 256); - subtype T_SIM_PROCESS_ID is NATURAL range 0 to 1023; - subtype T_SIM_PROCESS_NAME is STRING(1 to 64); - subtype T_SIM_PROCESS_INSTNAME is STRING(1 to 256); - type T_SIM_PROCESS_ID_VECTOR is array(NATURAL range <>) of T_SIM_PROCESS_ID; + subtype T_SIM_TEST_ID is integer range -1 to 1023; + subtype T_SIM_TEST_NAME is string(1 to 256); + subtype T_SIM_PROCESS_ID is natural range 0 to 1023; + subtype T_SIM_PROCESS_NAME is string(1 to 64); + subtype T_SIM_PROCESS_INSTNAME is string(1 to 256); + type T_SIM_PROCESS_ID_VECTOR is array(natural range <>) of T_SIM_PROCESS_ID; type T_SIM_TEST_STATUS is ( SIM_TEST_STATUS_CREATED, @@ -80,62 +77,61 @@ package sim_types is ProcessCount : T_SIM_PROCESS_ID; ActiveProcessCount : T_SIM_PROCESS_ID; end record; - type T_SIM_TEST_VECTOR is array(INTEGER range <>) of T_SIM_TEST; + type T_SIM_TEST_VECTOR is array(integer range <>) of T_SIM_TEST; type T_SIM_PROCESS is record ID : T_SIM_PROCESS_ID; TestID : T_SIM_TEST_ID; Name : T_SIM_PROCESS_NAME; Status : T_SIM_PROCESS_STATUS; - IsLowPriority : BOOLEAN; + IsLowPriority : boolean; end record; - type T_SIM_PROCESS_VECTOR is array(NATURAL range <>) of T_SIM_PROCESS; + type T_SIM_PROCESS_VECTOR is array(natural range <>) of T_SIM_PROCESS; constant C_SIM_DEFAULT_TEST_ID : T_SIM_TEST_ID := -1; - constant C_SIM_DEFAULT_TEST_NAME : STRING := "Default test"; + constant C_SIM_DEFAULT_TEST_NAME : string := "Default test"; -- =========================================================================== -- Random Numbers -- =========================================================================== type T_SIM_RAND_SEED is record - Seed1 : INTEGER; - Seed2 : INTEGER; + Seed1 : integer; + Seed2 : integer; end record; procedure randInitializeSeed(Seed : inout T_SIM_RAND_SEED); procedure randInitializeSeed(Seed : inout T_SIM_RAND_SEED; SeedValue : in T_SIM_RAND_SEED); procedure randInitializeSeed(Seed : inout T_SIM_RAND_SEED; SeedVector : in T_INTVEC); - procedure randInitializeSeed(Seed : inout T_SIM_RAND_SEED; SeedVector : in STRING); + procedure randInitializeSeed(Seed : inout T_SIM_RAND_SEED; SeedVector : in string); function randInitializeSeed return T_SIM_RAND_SEED; function randInitializeSeed(SeedValue : T_SIM_RAND_SEED) return T_SIM_RAND_SEED; function randInitializeSeed(SeedVector : T_INTVEC) return T_SIM_RAND_SEED; - function randInitializeSeed(SeedVector : STRING) return T_SIM_RAND_SEED; + function randInitializeSeed(SeedVector : string) return T_SIM_RAND_SEED; - attribute pocIsSimulation of randInitializeSeed[T_SIM_RAND_SEED] : procedure is TRUE; -- Uniform distributed random values -- =========================================================================== procedure randUniformDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out REAL); - procedure randUniformDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out INTEGER; Minimum : INTEGER; Maximum : INTEGER); + procedure randUniformDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out integer; Minimum : integer; Maximum : integer); procedure randUniformDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out REAL; Minimum : REAL; Maximum : REAL); -- Normal / Gaussian distributed random values -- =========================================================================== procedure randNormalDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out REAL; StandardDeviation : REAL := 1.0; Mean : REAL := 0.0); - procedure randNormalDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out INTEGER; StandardDeviation : in REAL; Mean : in REAL; Minimum : in INTEGER; Maximum : in INTEGER); + procedure randNormalDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out integer; StandardDeviation : in REAL; Mean : in REAL; Minimum : in integer; Maximum : in integer); procedure randNormalDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out REAL; StandardDeviation : in REAL; Mean : in REAL; Minimum : in REAL; Maximum : in REAL); -- Poisson distributed random values -- =========================================================================== procedure randPoissonDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out REAL; Mean : in REAL); - procedure randPoissonDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out INTEGER; Mean : in REAL; Minimum : in INTEGER; Maximum : in INTEGER); + procedure randPoissonDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out integer; Mean : in REAL; Minimum : in integer; Maximum : in integer); procedure randPoissonDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out REAL; Mean : in REAL; Minimum : in REAL; Maximum : in REAL); -- =========================================================================== -- Clock Generation -- =========================================================================== -- type T_PERCENT is INTEGER'range units - type T_PERCENT is range INTEGER'low to INTEGER'high units + type T_PERCENT is range integer'low to INTEGER'high units ppb; ppm = 1000 ppb; permil = 1000 ppm; @@ -145,19 +141,19 @@ package sim_types is subtype T_WANDER is T_PERCENT range -1 one to 1 one; subtype T_DUTYCYCLE is T_PERCENT range 0 ppb to 1 one; - type T_DEGREE is range INTEGER'low to INTEGER'high units + type T_DEGREE is range integer'low to INTEGER'high units second; minute = 60 second; deg = 60 minute; end units; subtype T_PHASE is T_DEGREE range -360 deg to 360 deg; - function ite(cond : BOOLEAN; value1 : T_DEGREE; value2 : T_DEGREE) return T_DEGREE; + function ite(cond : boolean; value1 : T_DEGREE; value2 : T_DEGREE) return T_DEGREE; end package; package body sim_types is - function ite(cond : BOOLEAN; value1 : T_DEGREE; value2 : T_DEGREE) return T_DEGREE is + function ite(cond : boolean; value1 : T_DEGREE; value2 : T_DEGREE) return T_DEGREE is begin if cond then return value1; @@ -169,8 +165,8 @@ package body sim_types is -- =========================================================================== -- Random Numbers -- =========================================================================== - constant MAX_SEED1_VALUE : POSITIVE := 2147483562; - constant MAX_SEED2_VALUE : POSITIVE := 2147483398; + constant MAX_SEED1_VALUE : positive := 2147483562; + constant MAX_SEED2_VALUE : positive := 2147483398; function randGenerateInitialSeed return T_SIM_RAND_SEED is begin @@ -219,19 +215,19 @@ package body sim_types is end if; end procedure; - procedure randInitializeSeed(Seed : inout T_SIM_RAND_SEED; SeedVector : in STRING) is + procedure randInitializeSeed(Seed : inout T_SIM_RAND_SEED; SeedVector : in string) is begin if (SeedVector'length = 0) then Seed := randGenerateInitialSeed; elsif (SeedVector'length = 1) then Seed := T_SIM_RAND_SEED'( - Seed1 => CHARACTER'pos(SeedVector(1)), + Seed1 => character'pos(SeedVector(1)), Seed2 => 39834 ); elsif (SeedVector'length = 2) then Seed := T_SIM_RAND_SEED'( - Seed1 => CHARACTER'pos(SeedVector(1)), - Seed2 => CHARACTER'pos(SeedVector(2)) + Seed1 => character'pos(SeedVector(1)), + Seed2 => character'pos(SeedVector(2)) ); else -- FIXME: @@ -257,7 +253,7 @@ package body sim_types is return Result; end function; - function randInitializeSeed(SeedVector : STRING) return T_SIM_RAND_SEED is + function randInitializeSeed(SeedVector : string) return T_SIM_RAND_SEED is variable Result : T_SIM_RAND_SEED; begin randInitializeSeed(Result, SeedVector); @@ -272,10 +268,10 @@ package body sim_types is ieee.math_real.Uniform(Seed.Seed1, Seed.Seed2, Value); end procedure; - procedure randUniformDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out INTEGER; Minimum : INTEGER; Maximum : INTEGER) is + procedure randUniformDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out integer; Minimum : integer; Maximum : integer) is variable rand : REAL; begin - if (Maximum < Minimum) then report "randUniformDistributedValue: Maximum must be greater than Minimum." severity FAILURE; end if; + if Maximum < Minimum then report "randUniformDistributedValue: Maximum must be greater than Minimum." severity FAILURE; end if; ieee.math_real.Uniform(Seed.Seed1, Seed.Seed2, rand); Value := scale(rand, Minimum, Maximum); end procedure; @@ -283,7 +279,7 @@ package body sim_types is procedure randUniformDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out REAL; Minimum : REAL; Maximum : REAL) is variable rand : REAL; begin - if (Maximum < Minimum) then report "randUniformDistributedValue: Maximum must be greater than Minimum." severity FAILURE; end if; + if Maximum < Minimum then report "randUniformDistributedValue: Maximum must be greater than Minimum." severity FAILURE; end if; ieee.math_real.Uniform(Seed.Seed1, Seed.Seed2, rand); Value := scale(rand, Minimum, Maximum); end procedure; @@ -303,13 +299,13 @@ package body sim_types is Value := StandardDeviation * (sqrt(-2.0 * log(rand1)) * cos(MATH_2_PI * rand2)) + Mean; end procedure; - procedure randNormalDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out INTEGER; StandardDeviation : in REAL; Mean : in REAL; Minimum : in INTEGER; Maximum : in INTEGER) is + procedure randNormalDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out integer; StandardDeviation : in REAL; Mean : in REAL; Minimum : in integer; Maximum : in integer) is variable rand_real : REAL; - variable rand_int : INTEGER; + variable rand_int : integer; begin - if (Maximum < Minimum) then report "randNormalDistributedValue: Maximum must be greater than Minimum." severity FAILURE; end if; + if Maximum < Minimum then report "randNormalDistributedValue: Maximum must be greater than Minimum." severity FAILURE; end if; if StandardDeviation < 0.0 then report "randNormalDistributedValue: Standard deviation must be >= 0.0" severity FAILURE; end if; - while (TRUE) loop + while TRUE loop randNormalDistributedValue(Seed, rand_real, StandardDeviation, Mean); rand_int := integer(round(rand_real)); exit when ((Minimum <= rand_int) and (rand_int <= Maximum)); @@ -320,9 +316,9 @@ package body sim_types is procedure randNormalDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out REAL; StandardDeviation : in REAL; Mean : in REAL; Minimum : in REAL; Maximum : in REAL) is variable rand : REAL; begin - if (Maximum < Minimum) then report "randNormalDistributedValue: Maximum must be greater than Minimum." severity FAILURE; end if; + if Maximum < Minimum then report "randNormalDistributedValue: Maximum must be greater than Minimum." severity FAILURE; end if; if StandardDeviation < 0.0 then report "randNormalDistributedValue: Standard deviation must be >= 0.0" severity FAILURE; end if; - while (TRUE) loop + while TRUE loop randNormalDistributedValue(Seed, rand, StandardDeviation, Mean); exit when ((Minimum <= rand) and (rand <= Maximum)); end loop; @@ -354,12 +350,12 @@ package body sim_types is Value := Result; end procedure; - procedure randPoissonDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out INTEGER; Mean : in REAL; Minimum : in INTEGER; Maximum : in INTEGER) is + procedure randPoissonDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out integer; Mean : in REAL; Minimum : in integer; Maximum : in integer) is variable rand_real : REAL; - variable rand_int : INTEGER; + variable rand_int : integer; begin - if (Maximum < Minimum) then report "randPoissonDistributedValue: Maximum must be greater than Minimum." severity FAILURE; end if; - while (TRUE) loop + if Maximum < Minimum then report "randPoissonDistributedValue: Maximum must be greater than Minimum." severity FAILURE; end if; + while TRUE loop randPoissonDistributedValue(Seed, rand_real, Mean); rand_int := integer(round(rand_real)); exit when ((Minimum <= rand_int) and (rand_int <= Maximum)); @@ -370,8 +366,8 @@ package body sim_types is procedure randPoissonDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out REAL; Mean : in REAL; Minimum : in REAL; Maximum : in REAL) is variable rand : REAL; begin - if (Maximum < Minimum) then report "randPoissonDistributedValue: Maximum must be greater than Minimum." severity FAILURE; end if; - while (TRUE) loop + if Maximum < Minimum then report "randPoissonDistributedValue: Maximum must be greater than Minimum." severity FAILURE; end if; + while TRUE loop randPoissonDistributedValue(Seed, rand, Mean); exit when ((Minimum <= rand) and (rand <= Maximum)); end loop; diff --git a/src/sim/sim_unprotected.v93.vhdl b/src/sim/sim_unprotected.v93.vhdl index 04df2293..10a095cd 100644 --- a/src/sim/sim_unprotected.v93.vhdl +++ b/src/sim/sim_unprotected.v93.vhdl @@ -1,15 +1,14 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Patrick Lehmann -- -- Package: Simulation constants, functions and utilities. -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: -- ============================================================================= @@ -48,36 +47,36 @@ package sim_unprotected is -- Simulation Task and Status Management -- =========================================================================== -- Initializer and Finalizer - procedure initialize(MaxAssertFailures : NATURAL := NATURAL'high; MaxSimulationRuntime : TIME := TIME'high); + procedure initialize(MaxAssertFailures : natural := natural'high; MaxSimulationRuntime : TIME := TIME'high); procedure finalize; -- Assertions - procedure fail(Message : STRING := ""); - procedure assertion(Condition : BOOLEAN; Message : STRING := ""); - procedure writeMessage(Message : STRING); + procedure fail(Message : string := ""); + procedure assertion(Condition : boolean; Message : string := ""); + procedure writeMessage(Message : string); procedure writeReport; -- Process Management - impure function registerProcess(Name : STRING; IsLowPriority : BOOLEAN := FALSE) return T_SIM_PROCESS_ID; - impure function registerProcess(TestID : T_SIM_TEST_ID; Name : STRING; IsLowPriority : BOOLEAN := FALSE) return T_SIM_PROCESS_ID; + impure function registerProcess(Name : string; IsLowPriority : boolean := FALSE) return T_SIM_PROCESS_ID; + impure function registerProcess(TestID : T_SIM_TEST_ID; Name : string; IsLowPriority : boolean := FALSE) return T_SIM_PROCESS_ID; procedure deactivateProcess(procID : T_SIM_PROCESS_ID); procedure stopAllProcesses; procedure stopProcesses(TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID); -- Test Management procedure createDefaultTest; - impure function createTest(Name : STRING) return T_SIM_TEST_ID; + impure function createTest(Name : string) return T_SIM_TEST_ID; procedure activateDefaultTest; - impure function finalizeDefaultTest return BOOLEAN; + impure function finalizeDefaultTest return boolean; procedure finalizeTest(TestID : T_SIM_TEST_ID); -- Clock Management procedure stopAllClocks; procedure stopClocks(TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID); - impure function isStopped(TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID) return BOOLEAN; - impure function isFinalized(TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID) return BOOLEAN; - impure function isAllFinalized return BOOLEAN; + impure function isStopped(TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID) return boolean; + impure function isFinalized(TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID) return boolean; + impure function isAllFinalized return boolean; end package; @@ -87,14 +86,14 @@ package body sim_unprotected is -- =========================================================================== procedure init is begin - if (globalSim_StateIsInitialized = FALSE) then + if not globalSim_StateIsInitialized then if C_SIM_VERBOSE then report "init:" severity NOTE; end if; globalSim_StateIsInitialized := TRUE; createDefaultTest; end if; end procedure; - procedure initialize(MaxAssertFailures : NATURAL := NATURAL'high; MaxSimulationRuntime : TIME := TIME'high) is + procedure initialize(MaxAssertFailures : natural := natural'high; MaxSimulationRuntime : TIME := TIME'high) is begin if C_SIM_VERBOSE then report "initialize:" severity NOTE; end if; init; @@ -108,9 +107,9 @@ package body sim_unprotected is end procedure; procedure finalize is - variable Dummy : BOOLEAN; + variable Dummy : boolean; begin - if (globalSim_StateIsFinalized = FALSE) then + if not globalSim_StateIsFinalized then if C_SIM_VERBOSE then report "finalize: " severity NOTE; end if; globalSim_StateIsFinalized := TRUE; for i in 0 to globalSim_TestCount - 1 loop @@ -124,50 +123,50 @@ package body sim_unprotected is procedure writeReport_Header is variable LineBuffer : LINE; begin - write(LineBuffer, ( STRING'("========================================"))); - write(LineBuffer, (CR & STRING'("POC TESTBENCH REPORT"))); - write(LineBuffer, (CR & STRING'("========================================"))); + write(LineBuffer, ( string'("========================================"))); + write(LineBuffer, (LF & string'("POC TESTBENCH REPORT"))); + write(LineBuffer, (LF & string'("========================================"))); writeline(output, LineBuffer); end procedure; - procedure writeReport_TestReport(Prefix : STRING := "") is + procedure writeReport_TestReport(Prefix : string := "") is variable LineBuffer : LINE; begin if (globalSim_Tests(C_SIM_DEFAULT_TEST_ID).Status /= SIM_TEST_STATUS_CREATED) then - write(LineBuffer, Prefix & "Tests " & INTEGER'image(globalSim_TestCount + 1)); - write(LineBuffer, CR & Prefix & " " & str_ralign("-1", log10ceilnz(globalSim_TestCount + 1) + 1) & ": " & C_SIM_DEFAULT_TEST_NAME); + write(LineBuffer, Prefix & "Tests " & integer'image(globalSim_TestCount + 1)); + write(LineBuffer, LF & Prefix & " " & str_ralign("-1", log10ceilnz(globalSim_TestCount + 1) + 1) & ": " & C_SIM_DEFAULT_TEST_NAME); else - write(LineBuffer, Prefix & "Tests " & INTEGER'image(globalSim_TestCount)); + write(LineBuffer, Prefix & "Tests " & integer'image(globalSim_TestCount)); end if; for i in 0 to globalSim_TestCount - 1 loop - write(LineBuffer, CR & Prefix & " " & str_ralign(INTEGER'image(i), log10ceilnz(globalSim_TestCount)) & ": " & str_trim(globalSim_Tests(i).Name)); + write(LineBuffer, LF & Prefix & " " & str_ralign(integer'image(i), log10ceilnz(globalSim_TestCount)) & ": " & str_trim(globalSim_Tests(i).Name)); end loop; writeline(output, LineBuffer); end procedure; - procedure writeReport_AssertReport(Prefix : STRING := "") is + procedure writeReport_AssertReport(Prefix : string := "") is variable LineBuffer : LINE; begin - write(LineBuffer, Prefix & "Assertions " & INTEGER'image(globalSim_AssertCount)); - write(LineBuffer, CR & Prefix & " failed " & INTEGER'image(globalSim_FailedAssertCount) & ite((globalSim_FailedAssertCount >= globalSim_MaxAssertFailures), " Too many failed asserts!", "")); + write(LineBuffer, Prefix & "Assertions " & integer'image(globalSim_AssertCount)); + write(LineBuffer, LF & Prefix & " failed " & integer'image(globalSim_FailedAssertCount) & ite((globalSim_FailedAssertCount >= globalSim_MaxAssertFailures), " Too many failed asserts!", "")); writeline(output, LineBuffer); end procedure; - procedure writeReport_ProcessReport(Prefix : STRING := "") is + procedure writeReport_ProcessReport(Prefix : string := "") is variable LineBuffer : LINE; begin - write(LineBuffer, Prefix & "Processes " & INTEGER'image(globalSim_ProcessCount)); - write(LineBuffer, CR & Prefix & " active " & INTEGER'image(globalSim_ActiveProcessCount)); + write(LineBuffer, Prefix & "Processes " & integer'image(globalSim_ProcessCount)); + write(LineBuffer, LF & Prefix & " active " & integer'image(globalSim_ActiveProcessCount)); -- report killed processes for i in 0 to globalSim_ProcessCount - 1 loop if ((globalSim_Processes(i).Status = SIM_PROCESS_STATUS_ACTIVE) and (globalSim_Processes(i).IsLowPriority = FALSE)) then - write(LineBuffer, CR & Prefix & " " & str_ralign(INTEGER'image(i), log10ceilnz(globalSim_ProcessCount)) & ": " & str_trim(globalSim_Processes(i).Name)); + write(LineBuffer, LF & Prefix & " " & str_ralign(integer'image(i), log10ceilnz(globalSim_ProcessCount)) & ": " & str_trim(globalSim_Processes(i).Name)); end if; end loop; writeline(output, LineBuffer); end procedure; - procedure writeReport_RuntimeReport(Prefix : STRING := "") is + procedure writeReport_RuntimeReport(Prefix : string := "") is variable LineBuffer : LINE; begin write(LineBuffer, Prefix & "Runtime " & to_string(now, 1)); @@ -177,12 +176,12 @@ package body sim_unprotected is procedure writeReport_SimulationResult is variable LineBuffer : LINE; begin - write(LineBuffer, ( STRING'("========================================"))); - if (globalSim_AssertCount = 0) then write(LineBuffer, (CR & STRING'("SIMULATION RESULT = NO ASSERTS"))); - elsif (globalSim_Passed = TRUE) then write(LineBuffer, (CR & STRING'("SIMULATION RESULT = PASSED"))); - else write(LineBuffer, (CR & STRING'("SIMULATION RESULT = FAILED"))); + write(LineBuffer, ( string'("========================================"))); + if globalSim_AssertCount = 0 then write(LineBuffer, (LF & string'("SIMULATION RESULT = NO ASSERTS"))); + elsif globalSim_Passed then write(LineBuffer, (LF & string'("SIMULATION RESULT = PASSED"))); + else write(LineBuffer, (LF & string'("SIMULATION RESULT = FAILED"))); end if; - write(LineBuffer, (CR & STRING'("========================================"))); + write(LineBuffer, (LF & string'("========================================"))); writeline(output, LineBuffer); end procedure; @@ -191,7 +190,7 @@ package body sim_unprotected is begin writeReport_Header; writeReport_TestReport(""); - write(LineBuffer, CR & "Overall"); + write(LineBuffer, LF & "Overall"); writeline(output, LineBuffer); writeReport_AssertReport(" "); writeReport_ProcessReport(" "); @@ -199,10 +198,10 @@ package body sim_unprotected is writeReport_SimulationResult; end procedure; - procedure assertion(condition : BOOLEAN; Message : STRING := "") is + procedure assertion(condition : boolean; Message : string := "") is begin globalSim_AssertCount := globalSim_AssertCount + 1; - if (condition = FALSE) then + if not condition then fail(Message); globalSim_FailedAssertCount := globalSim_FailedAssertCount + 1; if (globalSim_FailedAssertCount >= globalSim_MaxAssertFailures) then @@ -211,7 +210,7 @@ package body sim_unprotected is end if; end procedure; - procedure fail(Message : STRING := "") is + procedure fail(Message : string := "") is begin if (Message'length > 0) then report Message severity ERROR; @@ -219,7 +218,7 @@ package body sim_unprotected is globalSim_Passed := FALSE; end procedure; - procedure writeMessage(Message : STRING) is + procedure writeMessage(Message : string) is variable LineBuffer : LINE; begin write(LineBuffer, Message); @@ -229,7 +228,7 @@ package body sim_unprotected is procedure createDefaultTest is variable Test : T_SIM_TEST; begin - if (globalSim_StateIsInitialized = FALSE) then + if not globalSim_StateIsInitialized then init; end if; if C_SIM_VERBOSE then report "createDefaultTest(" & C_SIM_DEFAULT_TEST_NAME & "): => " & T_SIM_TEST_ID'image(C_SIM_DEFAULT_TEST_ID) severity NOTE; end if; @@ -243,10 +242,10 @@ package body sim_unprotected is globalSim_Tests(Test.ID) := Test; end procedure; - impure function createTest(Name : STRING) return T_SIM_TEST_ID is + impure function createTest(Name : string) return T_SIM_TEST_ID is variable Test : T_SIM_TEST; begin - if (globalSim_StateIsInitialized = FALSE) then + if not globalSim_StateIsInitialized then init; end if; if C_SIM_VERBOSE then report "createTest(" & Name & "): => " & T_SIM_TEST_ID'image(globalSim_TestCount) severity NOTE; end if; @@ -272,7 +271,7 @@ package body sim_unprotected is end if; end procedure; - impure function finalizeDefaultTest return BOOLEAN is + impure function finalizeDefaultTest return boolean is begin if (globalSim_Tests(C_SIM_DEFAULT_TEST_ID).Status = SIM_TEST_STATUS_CREATED) then if C_SIM_VERBOSE then report "finalizeDefaultTest: inactive" severity NOTE; end if; @@ -284,7 +283,7 @@ package body sim_unprotected is globalSim_Tests(C_SIM_DEFAULT_TEST_ID).Status := SIM_TEST_STATUS_ENDED; globalSim_ActiveTestCount := globalSim_ActiveTestCount - 1; stopProcesses(C_SIM_DEFAULT_TEST_ID); - if (globalSim_ActiveTestCount = 0) then + if globalSim_ActiveTestCount = 0 then finalize; end if; return TRUE; @@ -293,25 +292,25 @@ package body sim_unprotected is end function; procedure finalizeTest(TestID : T_SIM_TEST_ID) is - variable Dummy : BOOLEAN; + variable Dummy : boolean; begin - if (TestID = C_SIM_DEFAULT_TEST_ID) then - if (globalSim_ActiveTestCount = 1) then - if (finalizeDefaultTest = TRUE) then + if TestID = C_SIM_DEFAULT_TEST_ID then + if globalSim_ActiveTestCount = 1 then + if finalizeDefaultTest then finalize; end if; end if; - elsif (TestID < globalSim_TestCount) then + elsif TestID < globalSim_TestCount then if (globalSim_Tests(TestID).Status /= SIM_TEST_STATUS_ENDED) then if C_SIM_VERBOSE then report "finalizeTest(TestID=" & T_SIM_TEST_ID'image(TestID) & "): " severity NOTE; end if; globalSim_Tests(TestID).Status := SIM_TEST_STATUS_ENDED; globalSim_ActiveTestCount := globalSim_ActiveTestCount - 1; stopProcesses(TestID); - if (globalSim_ActiveTestCount = 0) then + if globalSim_ActiveTestCount = 0 then finalize; - elsif (globalSim_ActiveTestCount = 1) then - if (finalizeDefaultTest = TRUE) then + elsif globalSim_ActiveTestCount = 1 then + if finalizeDefaultTest then finalize; end if; end if; @@ -321,22 +320,22 @@ package body sim_unprotected is end if; end procedure; - impure function registerProcess(Name : STRING; IsLowPriority : BOOLEAN := FALSE) return T_SIM_PROCESS_ID is + impure function registerProcess(Name : string; IsLowPriority : boolean := FALSE) return T_SIM_PROCESS_ID is begin return registerProcess(C_SIM_DEFAULT_TEST_ID, Name, IsLowPriority); end function; - impure function registerProcess(TestID : T_SIM_TEST_ID; Name : STRING; IsLowPriority : BOOLEAN := FALSE) return T_SIM_PROCESS_ID is + impure function registerProcess(TestID : T_SIM_TEST_ID; Name : string; IsLowPriority : boolean := FALSE) return T_SIM_PROCESS_ID is variable Proc : T_SIM_PROCESS; variable TestProcID : T_SIM_TEST_ID; begin - if (globalSim_StateIsInitialized = FALSE) then + if not globalSim_StateIsInitialized then init; end if; - if (TestID = C_SIM_DEFAULT_TEST_ID) then + if TestID = C_SIM_DEFAULT_TEST_ID then activateDefaultTest; end if; - if (TestID < globalSim_TestCount) then + if TestID < globalSim_TestCount then if C_SIM_VERBOSE then report "registerProcess(TestID=" & T_SIM_TEST_ID'image(TestID) & ", " & Name & "): => " & T_SIM_PROCESS_ID'image(globalSim_ProcessCount) severity NOTE; end if; Proc.ID := globalSim_ProcessCount; Proc.TestID := TestID; @@ -347,12 +346,12 @@ package body sim_unprotected is -- add process to list globalSim_Processes(Proc.ID) := Proc; globalSim_ProcessCount := globalSim_ProcessCount + 1; - globalSim_ActiveProcessCount := inc(not IsLowPriority, globalSim_ActiveProcessCount); + globalSim_ActiveProcessCount := inc_if(not IsLowPriority, globalSim_ActiveProcessCount); -- add process to test TestProcID := globalSim_Tests(TestID).ProcessCount; globalSim_Tests(TestID).ProcessIDs(TestProcID) := Proc.ID; globalSim_Tests(TestID).ProcessCount := TestProcID + 1; - globalSim_Tests(TestID).ActiveProcessCount := inc(not IsLowPriority, globalSim_Tests(TestID).ActiveProcessCount); + globalSim_Tests(TestID).ActiveProcessCount := inc_if(not IsLowPriority, globalSim_Tests(TestID).ActiveProcessCount); -- return the process ID return Proc.ID; else @@ -364,14 +363,14 @@ package body sim_unprotected is procedure deactivateProcess(ProcID : T_SIM_PROCESS_ID) is variable TestID : T_SIM_TEST_ID; begin - if (ProcID < globalSim_ProcessCount) then + if ProcID < globalSim_ProcessCount then TestID := globalSim_Processes(ProcID).TestID; -- deactivate process if (globalSim_Processes(ProcID).Status = SIM_PROCESS_STATUS_ACTIVE) then if C_SIM_VERBOSE then report "deactivateProcess(ProcID=" & T_SIM_PROCESS_ID'image(ProcID) & "): TestID=" & T_SIM_TEST_ID'image(TestID) & " Name=" & str_trim(globalSim_Processes(ProcID).Name) severity NOTE; end if; globalSim_Processes(ProcID).Status := SIM_PROCESS_STATUS_ENDED; - globalSim_ActiveProcessCount := dec(not globalSim_Processes(ProcID).IsLowPriority, globalSim_ActiveProcessCount); - globalSim_Tests(TestID).ActiveProcessCount := dec(not globalSim_Processes(ProcID).IsLowPriority, globalSim_Tests(TestID).ActiveProcessCount); + globalSim_ActiveProcessCount := dec_if(not globalSim_Processes(ProcID).IsLowPriority, globalSim_ActiveProcessCount); + globalSim_Tests(TestID).ActiveProcessCount := dec_if(not globalSim_Processes(ProcID).IsLowPriority, globalSim_Tests(TestID).ActiveProcessCount); if (globalSim_Tests(TestID).ActiveProcessCount = 0) then finalizeTest(TestID); end if; @@ -391,7 +390,7 @@ package body sim_unprotected is procedure stopProcesses(TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID) is begin - if (TestID < globalSim_TestCount) then + if TestID < globalSim_TestCount then if C_SIM_VERBOSE then report "stopProcesses(TestID=" & T_SIM_TEST_ID'image(TestID) & "): Name=" & str_trim(globalSim_Tests(TestID).Name) severity NOTE; end if; globalSim_MainProcessEnables(TestID) := FALSE; stopClocks(TestID); @@ -410,7 +409,7 @@ package body sim_unprotected is procedure stopClocks(TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID) is begin - if (TestID < globalSim_TestCount) then + if TestID < globalSim_TestCount then if C_SIM_VERBOSE then report "stopClocks(TestID=" & T_SIM_TEST_ID'image(TestID) & "): Name=" & str_trim(globalSim_Tests(TestID).Name) severity NOTE; end if; globalSim_MainClockEnables(TestID) := FALSE; else @@ -418,17 +417,17 @@ package body sim_unprotected is end if; end procedure; - impure function isStopped(TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID) return BOOLEAN is + impure function isStopped(TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID) return boolean is begin return not globalSim_MainClockEnables(TestID); end function; - impure function isFinalized(TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID) return BOOLEAN is + impure function isFinalized(TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID) return boolean is begin return (globalSim_Tests(TestID).Status = SIM_TEST_STATUS_ENDED); end function; - impure function isAllFinalized return BOOLEAN is + impure function isAllFinalized return boolean is begin return (globalSim_ActiveTestCount = 0); end function; diff --git a/src/sim/sim_waveform.vhdl b/src/sim/sim_waveform.vhdl index 7acf003f..4842ca53 100644 --- a/src/sim/sim_waveform.vhdl +++ b/src/sim/sim_waveform.vhdl @@ -1,7 +1,6 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Patrick Lehmann -- Martin Zabel @@ -9,8 +8,8 @@ -- Package: Simulation constants, functions and utilities. -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: -- ============================================================================= @@ -50,7 +49,7 @@ package waveform is -- clock generation -- =========================================================================== procedure simGenerateClock( - signal Clock : out STD_LOGIC; + signal Clock : out std_logic; constant Frequency : in FREQ; constant Phase : in T_PHASE := 0 deg; constant DutyCycle : in T_DUTYCYCLE := 50 percent; @@ -58,116 +57,116 @@ package waveform is ); procedure simGenerateClock( constant TestID : in T_SIM_TEST_ID; - signal Clock : out STD_LOGIC; + signal Clock : out std_logic; constant Frequency : in FREQ; constant Phase : in T_PHASE := 0 deg; constant DutyCycle : in T_DUTYCYCLE := 50 percent; constant Wander : in T_WANDER := 0 permil ); procedure simGenerateClock( - signal Clock : out STD_LOGIC; - constant Period : in TIME; + signal Clock : out std_logic; + constant Period : in time; constant Phase : in T_PHASE := 0 deg; constant DutyCycle : in T_DUTYCYCLE := 50 percent; constant Wander : in T_WANDER := 0 permil ); procedure simGenerateClock( constant TestID : in T_SIM_TEST_ID; - signal Clock : out STD_LOGIC; - constant Period : in TIME; + signal Clock : out std_logic; + constant Period : in time; constant Phase : in T_PHASE := 0 deg; constant DutyCycle : in T_DUTYCYCLE := 50 percent; constant Wander : in T_WANDER := 0 permil ); - procedure simWaitUntilRisingEdge(signal Clock : in STD_LOGIC; constant Times : in POSITIVE); - procedure simWaitUntilRisingEdge(constant TestID : in T_SIM_TEST_ID; signal Clock : in STD_LOGIC; constant Times : in POSITIVE); - procedure simWaitUntilFallingEdge(signal Clock : in STD_LOGIC; constant Times : in POSITIVE); - procedure simWaitUntilFallingEdge(constant TestID : in T_SIM_TEST_ID; signal Clock : in STD_LOGIC; constant Times : in POSITIVE); + procedure simWaitUntilRisingEdge(signal Clock : in std_logic; constant Times : in positive); + procedure simWaitUntilRisingEdge(constant TestID : in T_SIM_TEST_ID; signal Clock : in std_logic; constant Times : in positive); + procedure simWaitUntilFallingEdge(signal Clock : in std_logic; constant Times : in positive); + procedure simWaitUntilFallingEdge(constant TestID : in T_SIM_TEST_ID; signal Clock : in std_logic; constant Times : in positive); - procedure simGenerateClock2(constant TestID : in T_SIM_TEST_ID; signal Clock : out STD_LOGIC; signal Debug : out REAL; constant Period : in TIME); + procedure simGenerateClock2(constant TestID : in T_SIM_TEST_ID; signal Clock : out std_logic; signal Debug : out REAL; constant Period : in time); -- waveform description -- =========================================================================== type T_SIM_WAVEFORM_TUPLE_SL is record - Delay : TIME; - Value : STD_LOGIC; + Delay : time; + Value : std_logic; end record; type T_SIM_WAVEFORM_TUPLE_SLV_8 is record - Delay : TIME; + Delay : time; Value : T_SLV_8; end record; type T_SIM_WAVEFORM_TUPLE_SLV_16 is record - Delay : TIME; + Delay : time; Value : T_SLV_16; end record; type T_SIM_WAVEFORM_TUPLE_SLV_24 is record - Delay : TIME; + Delay : time; Value : T_SLV_24; end record; type T_SIM_WAVEFORM_TUPLE_SLV_32 is record - Delay : TIME; + Delay : time; Value : T_SLV_32; end record; type T_SIM_WAVEFORM_TUPLE_SLV_48 is record - Delay : TIME; + Delay : time; Value : T_SLV_48; end record; type T_SIM_WAVEFORM_TUPLE_SLV_64 is record - Delay : TIME; + Delay : time; Value : T_SLV_64; end record; subtype T_SIM_WAVEFORM is TIME_VECTOR; -- use predefined physical type TIME here - type T_SIM_WAVEFORM_SL is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SL; - type T_SIM_WAVEFORM_SLV_8 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_8; - type T_SIM_WAVEFORM_SLV_16 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_16; - type T_SIM_WAVEFORM_SLV_24 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_24; - type T_SIM_WAVEFORM_SLV_32 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_32; - type T_SIM_WAVEFORM_SLV_48 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_48; - type T_SIM_WAVEFORM_SLV_64 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_64; + type T_SIM_WAVEFORM_SL is array(natural range <>) of T_SIM_WAVEFORM_TUPLE_SL; + type T_SIM_WAVEFORM_SLV_8 is array(natural range <>) of T_SIM_WAVEFORM_TUPLE_SLV_8; + type T_SIM_WAVEFORM_SLV_16 is array(natural range <>) of T_SIM_WAVEFORM_TUPLE_SLV_16; + type T_SIM_WAVEFORM_SLV_24 is array(natural range <>) of T_SIM_WAVEFORM_TUPLE_SLV_24; + type T_SIM_WAVEFORM_SLV_32 is array(natural range <>) of T_SIM_WAVEFORM_TUPLE_SLV_32; + type T_SIM_WAVEFORM_SLV_48 is array(natural range <>) of T_SIM_WAVEFORM_TUPLE_SLV_48; + type T_SIM_WAVEFORM_SLV_64 is array(natural range <>) of T_SIM_WAVEFORM_TUPLE_SLV_64; -- waveform generation procedures -- =========================================================================== -- TODO: get initial value from Waveform(0) if .Delay = o fs, otherwise use (others => 'U') ? procedure simGenerateWaveform( - signal Wave : out BOOLEAN; + signal Wave : out boolean; constant Waveform : in T_SIM_WAVEFORM; - constant InitialValue : in BOOLEAN := FALSE + constant InitialValue : in boolean := FALSE ); procedure simGenerateWaveform( constant TestID : in T_SIM_TEST_ID; - signal Wave : out BOOLEAN; + signal Wave : out boolean; constant Waveform : in T_SIM_WAVEFORM; - constant InitialValue : in BOOLEAN := FALSE + constant InitialValue : in boolean := FALSE ); procedure simGenerateWaveform( - signal Wave : out STD_LOGIC; + signal Wave : out std_logic; constant Waveform : in T_SIM_WAVEFORM; - constant InitialValue : in STD_LOGIC := '0' + constant InitialValue : in std_logic := '0' ); procedure simGenerateWaveform( constant TestID : in T_SIM_TEST_ID; - signal Wave : out STD_LOGIC; + signal Wave : out std_logic; constant Waveform : in T_SIM_WAVEFORM; - constant InitialValue : in STD_LOGIC := '0' + constant InitialValue : in std_logic := '0' ); procedure simGenerateWaveform( - signal Wave : out STD_LOGIC; + signal Wave : out std_logic; constant Waveform : in T_SIM_WAVEFORM_SL; - constant InitialValue : in STD_LOGIC := '0' + constant InitialValue : in std_logic := '0' ); procedure simGenerateWaveform( constant TestID : in T_SIM_TEST_ID; - signal Wave : out STD_LOGIC; + signal Wave : out std_logic; constant Waveform : in T_SIM_WAVEFORM_SL; - constant InitialValue : in STD_LOGIC := '0' + constant InitialValue : in std_logic := '0' ); procedure simGenerateWaveform( signal Wave : out T_SLV_8; @@ -236,48 +235,48 @@ package waveform is constant InitialValue : in T_SLV_64 := (others => '0') ); - function "*" (Wave : T_SIM_WAVEFORM; Times : NATURAL) return T_SIM_WAVEFORM; - function ">" (Wave : T_SIM_WAVEFORM; Offset : TIME) return T_SIM_WAVEFORM; - function "<" (Wave : T_SIM_WAVEFORM; Offset : TIME) return T_SIM_WAVEFORM; + function "*" (Wave : T_SIM_WAVEFORM; Times : natural) return T_SIM_WAVEFORM; + function ">" (Wave : T_SIM_WAVEFORM; Offset : time) return T_SIM_WAVEFORM; + function "<" (Wave : T_SIM_WAVEFORM; Offset : time) return T_SIM_WAVEFORM; - function "*" (Wave : T_SIM_WAVEFORM_SLV_8; Times : NATURAL) return T_SIM_WAVEFORM_SLV_8; - function ">" (Wave : T_SIM_WAVEFORM_SLV_8; Offset : TIME) return T_SIM_WAVEFORM_SLV_8; + function "*" (Wave : T_SIM_WAVEFORM_SLV_8; Times : natural) return T_SIM_WAVEFORM_SLV_8; + function ">" (Wave : T_SIM_WAVEFORM_SLV_8; Offset : time) return T_SIM_WAVEFORM_SLV_8; -- function "<" (Wave : T_SIM_WAVEFORM_SLV_8; Offset : TIME) return T_SIM_WAVEFORM_SLV_8; - function "*" (Wave : T_SIM_WAVEFORM_SLV_16; Times : NATURAL) return T_SIM_WAVEFORM_SLV_16; - function ">" (Wave : T_SIM_WAVEFORM_SLV_16; Offset : TIME) return T_SIM_WAVEFORM_SLV_16; + function "*" (Wave : T_SIM_WAVEFORM_SLV_16; Times : natural) return T_SIM_WAVEFORM_SLV_16; + function ">" (Wave : T_SIM_WAVEFORM_SLV_16; Offset : time) return T_SIM_WAVEFORM_SLV_16; -- function "<" (Wave : T_SIM_WAVEFORM_SLV_16; Offset : TIME) return T_SIM_WAVEFORM_SLV_16; - function "*" (Wave : T_SIM_WAVEFORM_SLV_24; Times : NATURAL) return T_SIM_WAVEFORM_SLV_24; - function ">" (Wave : T_SIM_WAVEFORM_SLV_24; Offset : TIME) return T_SIM_WAVEFORM_SLV_24; + function "*" (Wave : T_SIM_WAVEFORM_SLV_24; Times : natural) return T_SIM_WAVEFORM_SLV_24; + function ">" (Wave : T_SIM_WAVEFORM_SLV_24; Offset : time) return T_SIM_WAVEFORM_SLV_24; -- function "<" (Wave : T_SIM_WAVEFORM_SLV_24; Offset : TIME) return T_SIM_WAVEFORM_SLV_24; - function "*" (Wave : T_SIM_WAVEFORM_SLV_32; Times : NATURAL) return T_SIM_WAVEFORM_SLV_32; - function ">" (Wave : T_SIM_WAVEFORM_SLV_32; Offset : TIME) return T_SIM_WAVEFORM_SLV_32; + function "*" (Wave : T_SIM_WAVEFORM_SLV_32; Times : natural) return T_SIM_WAVEFORM_SLV_32; + function ">" (Wave : T_SIM_WAVEFORM_SLV_32; Offset : time) return T_SIM_WAVEFORM_SLV_32; -- function "<" (Wave : T_SIM_WAVEFORM_SLV_32; Offset : TIME) return T_SIM_WAVEFORM_SLV_32; - function "*" (Wave : T_SIM_WAVEFORM_SLV_48; Times : NATURAL) return T_SIM_WAVEFORM_SLV_48; - function ">" (Wave : T_SIM_WAVEFORM_SLV_48; Offset : TIME) return T_SIM_WAVEFORM_SLV_48; + function "*" (Wave : T_SIM_WAVEFORM_SLV_48; Times : natural) return T_SIM_WAVEFORM_SLV_48; + function ">" (Wave : T_SIM_WAVEFORM_SLV_48; Offset : time) return T_SIM_WAVEFORM_SLV_48; -- function "<" (Wave : T_SIM_WAVEFORM_SLV_48; Offset : TIME) return T_SIM_WAVEFORM_SLV_48; - function "*" (Wave : T_SIM_WAVEFORM_SLV_64; Times : NATURAL) return T_SIM_WAVEFORM_SLV_64; - function ">" (Wave : T_SIM_WAVEFORM_SLV_64; Offset : TIME) return T_SIM_WAVEFORM_SLV_64; + function "*" (Wave : T_SIM_WAVEFORM_SLV_64; Times : natural) return T_SIM_WAVEFORM_SLV_64; + function ">" (Wave : T_SIM_WAVEFORM_SLV_64; Offset : time) return T_SIM_WAVEFORM_SLV_64; -- function "<" (Wave : T_SIM_WAVEFORM_SLV_64; Offset : TIME) return T_SIM_WAVEFORM_SLV_64; -- convert arrays to waveforms -- TODO: optimize waveform if input data doesn't change -- TODO: write single bit variant - function to_waveform(bv : BIT_VECTOR; Delay : TIME) return T_SIM_WAVEFORM; - function to_waveform(slv : STD_LOGIC_VECTOR; Delay : TIME) return T_SIM_WAVEFORM_SL; - function to_waveform(slvv : T_SLVV_8; Delay : TIME) return T_SIM_WAVEFORM_SLV_8; - function to_waveform(slvv : T_SLVV_16; Delay : TIME) return T_SIM_WAVEFORM_SLV_16; - function to_waveform(slvv : T_SLVV_24; Delay : TIME) return T_SIM_WAVEFORM_SLV_24; - function to_waveform(slvv : T_SLVV_32; Delay : TIME) return T_SIM_WAVEFORM_SLV_32; - function to_waveform(slvv : T_SLVV_48; Delay : TIME) return T_SIM_WAVEFORM_SLV_48; - function to_waveform(slvv : T_SLVV_64; Delay : TIME) return T_SIM_WAVEFORM_SLV_64; + function to_waveform(bv : bit_vector; Delay : time) return T_SIM_WAVEFORM; + function to_waveform(slv : std_logic_vector; Delay : time) return T_SIM_WAVEFORM_SL; + function to_waveform(slvv : T_SLVV_8; Delay : time) return T_SIM_WAVEFORM_SLV_8; + function to_waveform(slvv : T_SLVV_16; Delay : time) return T_SIM_WAVEFORM_SLV_16; + function to_waveform(slvv : T_SLVV_24; Delay : time) return T_SIM_WAVEFORM_SLV_24; + function to_waveform(slvv : T_SLVV_32; Delay : time) return T_SIM_WAVEFORM_SLV_32; + function to_waveform(slvv : T_SLVV_48; Delay : time) return T_SIM_WAVEFORM_SLV_48; + function to_waveform(slvv : T_SLVV_64; Delay : time) return T_SIM_WAVEFORM_SLV_64; -- predefined common waveforms - function simGenerateWaveform_Reset(constant Pause : TIME := 0 ns; ResetPulse : TIME := 10 ns) return T_SIM_WAVEFORM; + function simGenerateWaveform_Reset(constant Pause : time := 0 ns; ResetPulse : time := 10 ns) return T_SIM_WAVEFORM; -- TODO: integrate VCD simulation functions and procedures from sim_value_change_dump.vhdl here end package; @@ -287,33 +286,33 @@ package body waveform is -- clock generation -- =========================================================================== procedure simGenerateClock( - signal Clock : out STD_LOGIC; + signal Clock : out std_logic; constant Frequency : in FREQ; constant Phase : in T_PHASE := 0 deg; constant DutyCycle : in T_DUTYCYCLE := 50 percent; constant Wander : in T_WANDER := 0 permil ) is - constant Period : TIME := to_time(Frequency); + constant Period : time := to_time(Frequency); begin simGenerateClock(C_SIM_DEFAULT_TEST_ID, Clock, Period, Phase, DutyCycle, Wander); end procedure; procedure simGenerateClock( constant TestID : in T_SIM_TEST_ID; - signal Clock : out STD_LOGIC; + signal Clock : out std_logic; constant Frequency : in FREQ; constant Phase : in T_PHASE := 0 deg; constant DutyCycle : in T_DUTYCYCLE := 50 percent; constant Wander : in T_WANDER := 0 permil ) is - constant Period : TIME := to_time(Frequency); + constant Period : time := to_time(Frequency); begin simGenerateClock(TestID, Clock, Period, Phase, DutyCycle, Wander); end procedure; procedure simGenerateClock( - signal Clock : out STD_LOGIC; - constant Period : in TIME; + signal Clock : out std_logic; + constant Period : in time; constant Phase : in T_PHASE := 0 deg; constant DutyCycle : in T_DUTYCYCLE := 50 percent; constant Wander : in T_WANDER := 0 permil @@ -324,8 +323,8 @@ package body waveform is procedure simGenerateClock( constant TestID : in T_SIM_TEST_ID; - signal Clock : out STD_LOGIC; - constant Period : in TIME; + signal Clock : out std_logic; + constant Period : in time; constant Phase : in T_PHASE := 0 deg; constant DutyCycle : in T_DUTYCYCLE := 50 percent; constant Wander : in T_WANDER := 0 permil @@ -334,22 +333,22 @@ package body waveform is constant PhaseAsFactor : REAL := real(NormalizedPhase / 1 second) / 1296000.0; -- 1,296,000 = 3,600 seconds * 360 degree per cycle constant WanderAsFactor : REAL := real(Wander / 1 ppb) / 1.0e9; constant DutyCycleAsFactor : REAL := real(DutyCycle / 1 permil) / 1000.0; - constant Delay : TIME := Period * PhaseAsFactor; - constant TimeHigh : TIME := Period * DutyCycleAsFactor + (Period * (WanderAsFactor / 2.0)); -- add 50% wander to the high level - constant TimeLow : TIME := Period - TimeHigh + (Period * WanderAsFactor); -- and 50% to the low level - constant ClockAfterRun_cy : POSITIVE := 5; + constant Delay : time := Period * PhaseAsFactor; + constant TimeHigh : time := Period * DutyCycleAsFactor + (Period * (WanderAsFactor / 2.0)); -- add 50% wander to the high level + constant TimeLow : time := Period - TimeHigh + (Period * WanderAsFactor); -- and 50% to the low level + constant ClockAfterRun_cy : positive := 5; constant PROCESS_ID : T_SIM_PROCESS_ID := simRegisterProcess(TestID, "simGenerateClock(period=" & to_string(Period, 2) & ")", IsLowPriority => TRUE); begin - -- report "simGenerateClock: (Instance: '" & Clock'instance_name & "')" & CR & - -- "Period: " & TIME'image(Period) & CR & - -- "Phase: " & T_PHASE'image(Phase) & CR & - -- "DutyCycle: " & T_DUTYCYCLE'image(DutyCycle) & CR & - -- "PhaseAsFactor: " & REAL'image(PhaseAsFactor) & CR & - -- "WanderAsFactor: " & REAL'image(WanderAsFactor) & CR & - -- "DutyCycleAsFactor: " & REAL'image(DutyCycleAsFactor) & CR & - -- "Delay: " & TIME'image(Delay) & CR & - -- "TimeHigh: " & TIME'image(TimeHigh) & CR & + -- report "simGenerateClock: (Instance: '" & Clock'instance_name & "')" & LF & + -- "Period: " & TIME'image(Period) & LF & + -- "Phase: " & T_PHASE'image(Phase) & LF & + -- "DutyCycle: " & T_DUTYCYCLE'image(DutyCycle) & LF & + -- "PhaseAsFactor: " & REAL'image(PhaseAsFactor) & LF & + -- "WanderAsFactor: " & REAL'image(WanderAsFactor) & LF & + -- "DutyCycleAsFactor: " & REAL'image(DutyCycleAsFactor) & LF & + -- "Delay: " & TIME'image(Delay) & LF & + -- "TimeHigh: " & TIME'image(TimeHigh) & LF & -- "TimeLow: " & TIME'image(TimeLow) -- severity NOTE; @@ -365,7 +364,7 @@ package body waveform is wait for TimeLow; end if; Clock <= '1'; - while (not simIsStopped(TestID)) loop + while not simIsStopped(TestID) loop wait for TimeHigh; Clock <= '0'; wait for TimeLow; @@ -386,16 +385,16 @@ package body waveform is StandardDeviation : REAL; Mean : REAL; end record; - type T_JITTER_DISTRIBUTION is array (NATURAL range <>) of T_SIM_NORMAL_DIST_PARAMETER; + type T_JITTER_DISTRIBUTION is array (natural range <>) of T_SIM_NORMAL_DIST_PARAMETER; procedure simGenerateClock2( constant TestID : in T_SIM_TEST_ID; - signal Clock : out STD_LOGIC; + signal Clock : out std_logic; signal Debug : out REAL; - constant Period : in TIME + constant Period : in time ) is - constant TimeHigh : TIME := Period * 0.5; - constant TimeLow : TIME := Period - TimeHigh; + constant TimeHigh : time := Period * 0.5; + constant TimeLow : time := Period - TimeHigh; constant JitterPeakPeak : REAL := 0.1; -- UI constant JitterAsFactor : REAL := JitterPeakPeak / 4.0; -- Maximum jitter per edge constant JitterDistribution : T_JITTER_DISTRIBUTION := ( @@ -419,14 +418,14 @@ package body waveform is variable Seed : T_SIM_RAND_SEED; variable rand : REAL; variable Jitter : REAL; - variable Index : NATURAL; + variable Index : natural; - constant ClockAfterRun_cy : POSITIVE := 5; + constant ClockAfterRun_cy : positive := 5; begin Clock <= '1'; randInitializeSeed(Seed); - while (not simIsStopped(TestID)) loop + while not simIsStopped(TestID) loop ieee.math_real.Uniform(Seed.Seed1, Seed.Seed2, rand); Index := scale(rand, 0, JitterDistribution'length * 10) mod JitterDistribution'length; randNormalDistributedValue(Seed, rand, JitterDistribution(Index).StandardDeviation, JitterDistribution(Index).Mean, -1.0, 1.0); @@ -451,12 +450,12 @@ package body waveform is end procedure; - procedure simWaitUntilRisingEdge(signal Clock : in STD_LOGIC; constant Times : in POSITIVE) is + procedure simWaitUntilRisingEdge(signal Clock : in std_logic; constant Times : in positive) is begin simWaitUntilRisingEdge(C_SIM_DEFAULT_TEST_ID, Clock, Times); end procedure; - procedure simWaitUntilRisingEdge(constant TestID : in T_SIM_TEST_ID; signal Clock : in STD_LOGIC; constant Times : in POSITIVE) is + procedure simWaitUntilRisingEdge(constant TestID : in T_SIM_TEST_ID; signal Clock : in std_logic; constant Times : in positive) is begin for i in 1 to Times loop wait until rising_edge(Clock); @@ -464,12 +463,12 @@ package body waveform is end loop; end procedure; - procedure simWaitUntilFallingEdge(signal Clock : in STD_LOGIC; constant Times : in POSITIVE) is + procedure simWaitUntilFallingEdge(signal Clock : in std_logic; constant Times : in positive) is begin simWaitUntilFallingEdge(C_SIM_DEFAULT_TEST_ID, Clock, Times); end procedure; - procedure simWaitUntilFallingEdge(constant TestID : in T_SIM_TEST_ID; signal Clock : in STD_LOGIC; constant Times : in POSITIVE) is + procedure simWaitUntilFallingEdge(constant TestID : in T_SIM_TEST_ID; signal Clock : in std_logic; constant Times : in positive) is begin for i in 1 to Times loop wait until falling_edge(Clock); @@ -480,9 +479,9 @@ package body waveform is -- waveform generation -- =========================================================================== procedure simGenerateWaveform( - signal Wave : out BOOLEAN; + signal Wave : out boolean; constant Waveform : in T_SIM_WAVEFORM; - constant InitialValue : in BOOLEAN := FALSE + constant InitialValue : in boolean := FALSE ) is begin simGenerateWaveform(C_SIM_DEFAULT_TEST_ID, Wave, Waveform, InitialValue); @@ -490,12 +489,12 @@ package body waveform is procedure simGenerateWaveform( constant TestID : in T_SIM_TEST_ID; - signal Wave : out BOOLEAN; + signal Wave : out boolean; constant Waveform : in T_SIM_WAVEFORM; - constant InitialValue : in BOOLEAN := FALSE + constant InitialValue : in boolean := FALSE ) is constant PROCESS_ID : T_SIM_PROCESS_ID := simRegisterProcess(TestID, "simGenerateWaveform"); - variable State : BOOLEAN; + variable State : boolean; begin State := InitialValue; Wave <= State; @@ -509,9 +508,9 @@ package body waveform is end procedure; procedure simGenerateWaveform( - signal Wave : out STD_LOGIC; + signal Wave : out std_logic; constant Waveform : in T_SIM_WAVEFORM; - constant InitialValue : in STD_LOGIC := '0' + constant InitialValue : in std_logic := '0' ) is begin simGenerateWaveform(C_SIM_DEFAULT_TEST_ID, Wave, Waveform, InitialValue); @@ -519,12 +518,12 @@ package body waveform is procedure simGenerateWaveform( constant TestID : in T_SIM_TEST_ID; - signal Wave : out STD_LOGIC; + signal Wave : out std_logic; constant Waveform : in T_SIM_WAVEFORM; - constant InitialValue : in STD_LOGIC := '0' + constant InitialValue : in std_logic := '0' ) is constant PROCESS_ID : T_SIM_PROCESS_ID := simRegisterProcess(TestID, "simGenerateWaveform"); - variable State : STD_LOGIC; + variable State : std_logic; begin State := InitialValue; Wave <= State; @@ -538,9 +537,9 @@ package body waveform is end procedure; procedure simGenerateWaveform( - signal Wave : out STD_LOGIC; + signal Wave : out std_logic; constant Waveform : in T_SIM_WAVEFORM_SL; - constant InitialValue : in STD_LOGIC := '0' + constant InitialValue : in std_logic := '0' ) is begin simGenerateWaveform(C_SIM_DEFAULT_TEST_ID, Wave, Waveform, InitialValue); @@ -548,9 +547,9 @@ package body waveform is procedure simGenerateWaveform( constant TestID : in T_SIM_TEST_ID; - signal Wave : out STD_LOGIC; + signal Wave : out std_logic; constant Waveform : in T_SIM_WAVEFORM_SL; - constant InitialValue : in STD_LOGIC := '0' + constant InitialValue : in std_logic := '0' ) is constant PROCESS_ID : T_SIM_PROCESS_ID := simRegisterProcess(TestID, "simGenerateWaveform"); begin @@ -720,7 +719,7 @@ package body waveform is end procedure; -- Waveform arithmetic - function "*" (Wave : T_SIM_WAVEFORM; Times : NATURAL) return T_SIM_WAVEFORM is + function "*" (Wave : T_SIM_WAVEFORM; Times : natural) return T_SIM_WAVEFORM is variable Result : T_SIM_WAVEFORM(0 to Wave'length * Times - 1); begin for i in 0 to Times - 1 loop @@ -729,27 +728,27 @@ package body waveform is return Result; end function; - function ">" (Wave : T_SIM_WAVEFORM; Offset : TIME) return T_SIM_WAVEFORM is + function ">" (Wave : T_SIM_WAVEFORM; Offset : time) return T_SIM_WAVEFORM is begin return (Wave(Wave'low) + Offset) & Wave(Wave'low + 1 to Wave'high); end function; - function "<" (Wave : T_SIM_WAVEFORM; Offset : TIME) return T_SIM_WAVEFORM is + function "<" (Wave : T_SIM_WAVEFORM; Offset : time) return T_SIM_WAVEFORM is variable Result : T_SIM_WAVEFORM(Wave'range); - variable TimePos : TIME; + variable TimePos : time; begin report "Has bugs" severity ERROR; TimePos := 0 fs; for i in Wave'range loop TimePos := TimePos + Wave(i); - if (TimePos > Offset) then + if TimePos > Offset then return (TimePos - Offset) & Wave(i + 1 to Wave'high); end if; end loop; return (0 => 0 fs); end function; - function "*" (Wave : T_SIM_WAVEFORM_SLV_8; Times : NATURAL) return T_SIM_WAVEFORM_SLV_8 is + function "*" (Wave : T_SIM_WAVEFORM_SLV_8; Times : natural) return T_SIM_WAVEFORM_SLV_8 is variable Result : T_SIM_WAVEFORM_SLV_8(0 to Wave'length * Times - 1); begin for i in 0 to Times - 1 loop @@ -758,7 +757,7 @@ package body waveform is return Result; end function; - function ">" (Wave : T_SIM_WAVEFORM_SLV_8; Offset : TIME) return T_SIM_WAVEFORM_SLV_8 is + function ">" (Wave : T_SIM_WAVEFORM_SLV_8; Offset : time) return T_SIM_WAVEFORM_SLV_8 is begin return T_SIM_WAVEFORM_TUPLE_SLV_8'( Delay => Wave(Wave'low).Delay + Offset, @@ -771,7 +770,7 @@ package body waveform is -- report "Not implemented" severity FAILURE; -- end function; - function "*" (Wave : T_SIM_WAVEFORM_SLV_16; Times : NATURAL) return T_SIM_WAVEFORM_SLV_16 is + function "*" (Wave : T_SIM_WAVEFORM_SLV_16; Times : natural) return T_SIM_WAVEFORM_SLV_16 is variable Result : T_SIM_WAVEFORM_SLV_16(0 to Wave'length * Times - 1); begin for i in 0 to Times - 1 loop @@ -780,7 +779,7 @@ package body waveform is return Result; end function; - function ">" (Wave : T_SIM_WAVEFORM_SLV_16; Offset : TIME) return T_SIM_WAVEFORM_SLV_16 is + function ">" (Wave : T_SIM_WAVEFORM_SLV_16; Offset : time) return T_SIM_WAVEFORM_SLV_16 is begin return T_SIM_WAVEFORM_TUPLE_SLV_16'( Delay => Wave(Wave'low).Delay + Offset, @@ -793,7 +792,7 @@ package body waveform is -- report "Not implemented" severity FAILURE; -- end function; - function "*" (Wave : T_SIM_WAVEFORM_SLV_24; Times : NATURAL) return T_SIM_WAVEFORM_SLV_24 is + function "*" (Wave : T_SIM_WAVEFORM_SLV_24; Times : natural) return T_SIM_WAVEFORM_SLV_24 is variable Result : T_SIM_WAVEFORM_SLV_24(0 to Wave'length * Times - 1); begin for i in 0 to Times - 1 loop @@ -802,7 +801,7 @@ package body waveform is return Result; end function; - function ">" (Wave : T_SIM_WAVEFORM_SLV_24; Offset : TIME) return T_SIM_WAVEFORM_SLV_24 is + function ">" (Wave : T_SIM_WAVEFORM_SLV_24; Offset : time) return T_SIM_WAVEFORM_SLV_24 is begin return T_SIM_WAVEFORM_TUPLE_SLV_24'( Delay => Wave(Wave'low).Delay + Offset, @@ -815,7 +814,7 @@ package body waveform is -- report "Not implemented" severity FAILURE; -- end function; - function "*" (Wave : T_SIM_WAVEFORM_SLV_32; Times : NATURAL) return T_SIM_WAVEFORM_SLV_32 is + function "*" (Wave : T_SIM_WAVEFORM_SLV_32; Times : natural) return T_SIM_WAVEFORM_SLV_32 is variable Result : T_SIM_WAVEFORM_SLV_32(0 to Wave'length * Times - 1); begin for i in 0 to Times - 1 loop @@ -824,7 +823,7 @@ package body waveform is return Result; end function; - function ">" (Wave : T_SIM_WAVEFORM_SLV_32; Offset : TIME) return T_SIM_WAVEFORM_SLV_32 is + function ">" (Wave : T_SIM_WAVEFORM_SLV_32; Offset : time) return T_SIM_WAVEFORM_SLV_32 is begin return T_SIM_WAVEFORM_TUPLE_SLV_32'( Delay => Wave(Wave'low).Delay + Offset, @@ -837,7 +836,7 @@ package body waveform is -- report "Not implemented" severity FAILURE; -- end function; - function "*" (Wave : T_SIM_WAVEFORM_SLV_48; Times : NATURAL) return T_SIM_WAVEFORM_SLV_48 is + function "*" (Wave : T_SIM_WAVEFORM_SLV_48; Times : natural) return T_SIM_WAVEFORM_SLV_48 is variable Result : T_SIM_WAVEFORM_SLV_48(0 to Wave'length * Times - 1); begin for i in 0 to Times - 1 loop @@ -846,7 +845,7 @@ package body waveform is return Result; end function; - function ">" (Wave : T_SIM_WAVEFORM_SLV_48; Offset : TIME) return T_SIM_WAVEFORM_SLV_48 is + function ">" (Wave : T_SIM_WAVEFORM_SLV_48; Offset : time) return T_SIM_WAVEFORM_SLV_48 is begin return T_SIM_WAVEFORM_TUPLE_SLV_48'( Delay => Wave(Wave'low).Delay + Offset, @@ -859,7 +858,7 @@ package body waveform is -- report "Not implemented" severity FAILURE; -- end function; - function "*" (Wave : T_SIM_WAVEFORM_SLV_64; Times : NATURAL) return T_SIM_WAVEFORM_SLV_64 is + function "*" (Wave : T_SIM_WAVEFORM_SLV_64; Times : natural) return T_SIM_WAVEFORM_SLV_64 is variable Result : T_SIM_WAVEFORM_SLV_64(0 to Wave'length * Times - 1); begin for i in 0 to Times - 1 loop @@ -868,7 +867,7 @@ package body waveform is return Result; end function; - function ">" (Wave : T_SIM_WAVEFORM_SLV_64; Offset : TIME) return T_SIM_WAVEFORM_SLV_64 is + function ">" (Wave : T_SIM_WAVEFORM_SLV_64; Offset : time) return T_SIM_WAVEFORM_SLV_64 is begin return T_SIM_WAVEFORM_TUPLE_SLV_64'( Delay => Wave(Wave'low).Delay + Offset, @@ -882,7 +881,7 @@ package body waveform is -- end function; - function to_waveform(bv : BIT_VECTOR; Delay : TIME) return T_SIM_WAVEFORM is + function to_waveform(bv : bit_vector; Delay : time) return T_SIM_WAVEFORM is variable Result : T_SIM_WAVEFORM(0 to bv'length - 1); begin report "Has bugs" severity ERROR; @@ -892,7 +891,7 @@ package body waveform is return Result; end function; - function to_waveform(slv : STD_LOGIC_VECTOR; Delay : TIME) return T_SIM_WAVEFORM_SL is + function to_waveform(slv : std_logic_vector; Delay : time) return T_SIM_WAVEFORM_SL is variable Result : T_SIM_WAVEFORM_SL(0 to slv'length - 1); begin for i in 0 to slv'length - 1 loop @@ -902,7 +901,7 @@ package body waveform is return Result; end function; - function to_waveform(slvv : T_SLVV_8; Delay : TIME) return T_SIM_WAVEFORM_SLV_8 is + function to_waveform(slvv : T_SLVV_8; Delay : time) return T_SIM_WAVEFORM_SLV_8 is variable Result : T_SIM_WAVEFORM_SLV_8(0 to slvv'length - 1); begin for i in 0 to slvv'length - 1 loop @@ -912,7 +911,7 @@ package body waveform is return Result; end function; - function to_waveform(slvv : T_SLVV_16; Delay : TIME) return T_SIM_WAVEFORM_SLV_16 is + function to_waveform(slvv : T_SLVV_16; Delay : time) return T_SIM_WAVEFORM_SLV_16 is variable Result : T_SIM_WAVEFORM_SLV_16(0 to slvv'length - 1); begin for i in 0 to slvv'length - 1 loop @@ -922,7 +921,7 @@ package body waveform is return Result; end function; - function to_waveform(slvv : T_SLVV_24; Delay : TIME) return T_SIM_WAVEFORM_SLV_24 is + function to_waveform(slvv : T_SLVV_24; Delay : time) return T_SIM_WAVEFORM_SLV_24 is variable Result : T_SIM_WAVEFORM_SLV_24(0 to slvv'length - 1); begin for i in 0 to slvv'length - 1 loop @@ -932,7 +931,7 @@ package body waveform is return Result; end function; - function to_waveform(slvv : T_SLVV_32; Delay : TIME) return T_SIM_WAVEFORM_SLV_32 is + function to_waveform(slvv : T_SLVV_32; Delay : time) return T_SIM_WAVEFORM_SLV_32 is variable Result : T_SIM_WAVEFORM_SLV_32(0 to slvv'length - 1); begin for i in 0 to slvv'length - 1 loop @@ -942,7 +941,7 @@ package body waveform is return Result; end function; - function to_waveform(slvv : T_SLVV_48; Delay : TIME) return T_SIM_WAVEFORM_SLV_48 is + function to_waveform(slvv : T_SLVV_48; Delay : time) return T_SIM_WAVEFORM_SLV_48 is variable Result : T_SIM_WAVEFORM_SLV_48(0 to slvv'length - 1); begin for i in 0 to slvv'length - 1 loop @@ -952,7 +951,7 @@ package body waveform is return Result; end function; - function to_waveform(slvv : T_SLVV_64; Delay : TIME) return T_SIM_WAVEFORM_SLV_64 is + function to_waveform(slvv : T_SLVV_64; Delay : time) return T_SIM_WAVEFORM_SLV_64 is variable Result : T_SIM_WAVEFORM_SLV_64(0 to slvv'length - 1); begin for i in 0 to slvv'length - 1 loop @@ -963,9 +962,9 @@ package body waveform is end function; -- predefined common waveforms - function simGenerateWaveform_Reset(constant Pause : TIME := 0 ns; ResetPulse : TIME := 10 ns) return T_SIM_WAVEFORM is - variable p : TIME; - variable rp : TIME; + function simGenerateWaveform_Reset(constant Pause : time := 0 ns; ResetPulse : time := 10 ns) return T_SIM_WAVEFORM is + variable p : time; + variable rp : time; begin -- WORKAROUND: for Mentor QuestaSim/ModelSim -- Version: 10.4c diff --git a/src/sort/sort_lru_cache.vhdl b/src/sort/sort_lru_cache.vhdl index 8486333b..85e11403 100644 --- a/src/sort/sort_lru_cache.vhdl +++ b/src/sort/sort_lru_cache.vhdl @@ -1,36 +1,33 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; +-- ============================================================================= +-- Authors: Patrick Lehmann +-- Martin Zabel -- --- ============================================================================ --- Authors: Patrick Lehmann --- Martin Zabel --- --- Module: Optimized LRU list implementation for Caches. +-- Entity: Optimized LRU list implementation for Caches. -- -- Description: --- ------------------------------------ --- This is an optimized implementation of `sort_lru_list` to be used for caches. +-- ------------------------------------- +-- This is an optimized implementation of ``sort_lru_list`` to be used for caches. -- Only keys are stored within this list, and these keys are the index of the -- cache lines. The list initially contains all indizes from 0 to ELEMENTS-1. --- The least-recently used index `KeyOut` is always valid. +-- The least-recently used index ``KeyOut`` is always valid. -- -- The first outputed least-recently used index will be ELEMENTS-1. -- --- The inputs `Insert`, `Free`, `KeyIn`, and `Reset` are synchronous to the --- rising-edge of the clock `clock`. All control signals are high-active. +-- The inputs ``Insert``, ``Free``, ``KeyIn``, and ``Reset`` are synchronous to the +-- rising-edge of the clock ``clock``. All control signals are high-active. -- -- Supported operations: --- --- * Insert: Mark index `KeyIn` as recently used, e.g., when a cache-line --- was accessed. --- --- * Free: Mark index `KeyIn` as least-recently used. Apply this operation, --- when a cache-line gets invalidated. +-- * **Insert:** Mark index ``KeyIn`` as recently used, e.g., when a cache-line +-- was accessed. +-- * **Free:** Mark index ``KeyIn`` as least-recently used. Apply this operation, +-- when a cache-line gets invalidated. -- -- License: --- ============================================================================ --- Copyright 2007-2014 Technische Universitaet Dresden - Germany +-- ============================================================================= +-- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); @@ -44,7 +41,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -70,7 +67,7 @@ entity sort_lru_cache is KeyOut : out std_logic_vector(log2ceilnz(ELEMENTS) - 1 downto 0) ); -end; +end entity; architecture rtl of sort_lru_cache is diff --git a/src/sort/sort_lru_list.vhdl b/src/sort/sort_lru_list.vhdl index 143a7d74..66ea7078 100644 --- a/src/sort/sort_lru_list.vhdl +++ b/src/sort/sort_lru_list.vhdl @@ -1,33 +1,30 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; +-- ============================================================================= +-- Authors: Patrick Lehmann +-- Martin Zabel -- --- ============================================================================ --- Authors: Patrick Lehmann --- Martin Zabel --- --- Module: List storing key-value pairs in recently-used order. +-- Entity: List storing key-value pairs in recently-used order. -- -- Description: --- ------------------------------------ --- List storing `(key, value)` pairs. The least-recently inserted pair is --- outputed on `DataOut` if `Valid = '1'`. If `Valid = '0'`, then the list +-- ------------------------------------- +-- List storing ``(key, value)`` pairs. The least-recently inserted pair is +-- outputed on ``DataOut`` if ``Valid = '1'``. If ``Valid = '0'``, then the list -- empty. -- --- The inputs `Insert`, `Remove`, `DataIn`, and `Reset` are synchronous --- to the rising-edge of the clock `clock`. All control signals are high-active. +-- The inputs ``Insert``, ``Remove``, ``DataIn``, and ``Reset`` are synchronous +-- to the rising-edge of the clock ``clock``. All control signals are high-active. -- -- Supported operations: --- --- * Insert: Insert `DataIn` as recently used `(key, value)` pair. If key is --- already within the list, then the corresponding value is updated and the --- pair is moved to the recently used position. --- --- * Remove: Remove `(key, value)` pair with the given key. The list is not --- modified if key is not within the list. +-- * **Insert:** Insert ``DataIn`` as recently used ``(key, value)`` pair. If +-- key is already within the list, then the corresponding value is updated and +-- the pair is moved to the recently used position. +-- * **Remove:** Remove ``(key, value)`` pair with the given key. The list is not +-- modified if key is not within the list. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -42,7 +39,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -57,41 +54,41 @@ use PoC.components.all; entity sort_lru_list is generic ( - ELEMENTS : POSITIVE := 16; - KEY_BITS : POSITIVE := 4; - DATA_BITS : POSITIVE := 8; + ELEMENTS : positive := 16; + KEY_BITS : positive := 4; + DATA_BITS : positive := 8; INITIAL_ELEMENTS : T_SLM := (0 to 15 => (0 to 7 => '0')); - INITIAL_VALIDS : STD_LOGIC_VECTOR := (0 to 15 => '0') + INITIAL_VALIDS : std_logic_vector := (0 to 15 => '0') ); port ( - Clock : in STD_LOGIC; - Reset : in STD_LOGIC; + Clock : in std_logic; + Reset : in std_logic; - Insert : in STD_LOGIC; - Remove : in STD_LOGIC; - DataIn : in STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0); + Insert : in std_logic; + Remove : in std_logic; + DataIn : in std_logic_vector(DATA_BITS - 1 downto 0); - Valid : out STD_LOGIC; - DataOut : out STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0) + Valid : out std_logic; + DataOut : out std_logic_vector(DATA_BITS - 1 downto 0) ); end entity; architecture rtl of sort_lru_list is - subtype T_ELEMENT is STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0); - type T_ELEMENT_VECTOR is array (NATURAL range <>) OF T_ELEMENT; + subtype T_ELEMENT is std_logic_vector(DATA_BITS - 1 downto 0); + type T_ELEMENT_VECTOR is array (natural range <>) of T_ELEMENT; signal NewElementsUp : T_ELEMENT_VECTOR(ELEMENTS downto 0); signal ElementsUp : T_ELEMENT_VECTOR(ELEMENTS downto 0); signal ElementsDown : T_ELEMENT_VECTOR(ELEMENTS downto 0); - signal ValidsUp : STD_LOGIC_VECTOR(ELEMENTS downto 0); - signal ValidsDown : STD_LOGIC_VECTOR(ELEMENTS downto 0); + signal ValidsUp : std_logic_vector(ELEMENTS downto 0); + signal ValidsDown : std_logic_vector(ELEMENTS downto 0); - signal Unequal : STD_LOGIC_VECTOR(ELEMENTS-1 downto 0); + signal Unequal : std_logic_vector(ELEMENTS-1 downto 0); - signal MovesDown : STD_LOGIC_VECTOR(ELEMENTS downto 0); - signal MovesUp : STD_LOGIC_VECTOR(ELEMENTS downto 0); + signal MovesDown : std_logic_vector(ELEMENTS downto 0); + signal MovesUp : std_logic_vector(ELEMENTS downto 0); signal DataOutDown : T_ELEMENT_VECTOR(ELEMENTS downto 0); @@ -111,16 +108,16 @@ begin -- current element genElements : for i in ELEMENTS - 1 downto 0 generate - constant INITIAL_ELEMENT : STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0) := get_row(INITIAL_ELEMENTS, I); - constant INITIAL_VALID : STD_LOGIC := INITIAL_VALIDS(I); + constant INITIAL_ELEMENT : std_logic_vector(DATA_BITS - 1 downto 0) := get_row(INITIAL_ELEMENTS, I); + constant INITIAL_VALID : std_logic := INITIAL_VALIDS(I); - signal Element_nxt : STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0); - signal Element_d : STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0) := INITIAL_ELEMENT; - signal Valid_nxt : STD_LOGIC; - signal Valid_d : STD_LOGIC := INITIAL_VALID; + signal Element_nxt : std_logic_vector(DATA_BITS - 1 downto 0); + signal Element_d : std_logic_vector(DATA_BITS - 1 downto 0) := INITIAL_ELEMENT; + signal Valid_nxt : std_logic; + signal Valid_d : std_logic := INITIAL_VALID; - signal MoveDown : STD_LOGIC; - signal MoveUp : STD_LOGIC; + signal MoveDown : std_logic; + signal MoveUp : std_logic; begin -- local movements diff --git a/src/sort/sortnet/sortnet.pkg.vhdl b/src/sort/sortnet/sortnet.pkg.vhdl index c29726c8..2a504a31 100644 --- a/src/sort/sortnet/sortnet.pkg.vhdl +++ b/src/sort/sortnet/sortnet.pkg.vhdl @@ -1,18 +1,17 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: TODO +-- Entity: TODO -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -27,7 +26,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; diff --git a/src/sort/sortnet/sortnet_BitonicSort.vhdl b/src/sort/sortnet/sortnet_BitonicSort.vhdl index 8b7bc993..daa1a800 100644 --- a/src/sort/sortnet/sortnet_BitonicSort.vhdl +++ b/src/sort/sortnet/sortnet_BitonicSort.vhdl @@ -1,18 +1,17 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: Sorting network: bitonic sort +-- Entity: Sorting network: bitonic sort -- -- Description: --- ------------------------------------ --- This sorting network uses the 'bitonic sort' algorithm. +-- ------------------------------------- +-- This sorting network uses the *bitonic sort* algorithm. -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -27,13 +26,14 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library PoC; +use PoC.config.all; use PoC.utils.all; use PoC.math.all; use PoC.vectors.all; @@ -42,50 +42,50 @@ use PoC.components.all; entity sortnet_BitonicSort is generic ( - INPUTS : POSITIVE := 8; -- input count - KEY_BITS : POSITIVE := 32; -- the first KEY_BITS of In_Data are used as a sorting critera (key) - DATA_BITS : POSITIVE := 32; -- inclusive KEY_BITS - META_BITS : NATURAL := 2; -- additional bits, not sorted but delayed as long as In_Data - PIPELINE_STAGE_AFTER : NATURAL := 2; -- add a pipline stage after n sorting stages - ADD_INPUT_REGISTERS : BOOLEAN := FALSE; -- - ADD_OUTPUT_REGISTERS : BOOLEAN := TRUE -- + INPUTS : positive := 32; -- input count + KEY_BITS : positive := 32; -- the first KEY_BITS of In_Data are used as a sorting critera (key) + DATA_BITS : positive := 64; -- inclusive KEY_BITS + META_BITS : natural := 2; -- additional bits, not sorted but delayed as long as In_Data + PIPELINE_STAGE_AFTER : natural := 2; -- add a pipline stage after n sorting stages + ADD_INPUT_REGISTERS : boolean := FALSE; -- + ADD_OUTPUT_REGISTERS : boolean := TRUE -- ); port ( - Clock : in STD_LOGIC; - Reset : in STD_LOGIC; + Clock : in std_logic; + Reset : in std_logic; - Inverse : in STD_LOGIC := '0'; + Inverse : in std_logic := '0'; - In_Valid : in STD_LOGIC; - In_IsKey : in STD_LOGIC; + In_Valid : in std_logic; + In_IsKey : in std_logic; In_Data : in T_SLM(INPUTS - 1 downto 0, DATA_BITS - 1 downto 0); - In_Meta : in STD_LOGIC_VECTOR(META_BITS - 1 downto 0); + In_Meta : in std_logic_vector(META_BITS - 1 downto 0); - Out_Valid : out STD_LOGIC; - Out_IsKey : out STD_LOGIC; + Out_Valid : out std_logic; + Out_IsKey : out std_logic; Out_Data : out T_SLM(INPUTS - 1 downto 0, DATA_BITS - 1 downto 0); - Out_Meta : out STD_LOGIC_VECTOR(META_BITS - 1 downto 0) + Out_Meta : out std_logic_vector(META_BITS - 1 downto 0) ); end entity; architecture rtl of sortnet_BitonicSort is - constant C_VERBOSE : BOOLEAN := POC_VERBOSE; + constant C_VERBOSE : boolean := POC_VERBOSE; - constant BLOCKS : POSITIVE := log2ceil(INPUTS); - constant STAGES : POSITIVE := triangularNumber(BLOCKS); - constant COMPARATORS : POSITIVE := STAGES * (INPUTS / 2); + constant BLOCKS : positive := log2ceil(INPUTS); + constant STAGES : positive := triangularNumber(BLOCKS); + constant COMPARATORS : positive := STAGES * (INPUTS / 2); - constant META_VALID_BIT : NATURAL := 0; - constant META_ISKEY_BIT : NATURAL := 1; - constant META_VECTOR_BITS : POSITIVE := META_BITS + 2; + constant META_VALID_BIT : natural := 0; + constant META_ISKEY_BIT : natural := 1; + constant META_VECTOR_BITS : positive := META_BITS + 2; - subtype T_META is STD_LOGIC_VECTOR(META_VECTOR_BITS - 1 downto 0); - type T_META_VECTOR is array(NATURAL range <>) of T_META; + subtype T_META is std_logic_vector(META_VECTOR_BITS - 1 downto 0); + type T_META_VECTOR is array(natural range <>) of T_META; - subtype T_DATA is STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0); - type T_DATA_VECTOR is array(NATURAL range <>) of T_DATA; - type T_DATA_MATRIX is array(NATURAL range <>) of T_DATA_VECTOR(INPUTS - 1 downto 0); + subtype T_DATA is std_logic_vector(DATA_BITS - 1 downto 0); + type T_DATA_VECTOR is array(natural range <>) of T_DATA; + type T_DATA_MATRIX is array(natural range <>) of T_DATA_VECTOR(INPUTS - 1 downto 0); function to_dv(slm : T_SLM) return T_DATA_VECTOR is variable Result : T_DATA_VECTOR(slm'range(1)); @@ -109,10 +109,10 @@ architecture rtl of sortnet_BitonicSort is return Result; end function; - signal In_Valid_d : STD_LOGIC := '0'; - signal In_IsKey_d : STD_LOGIC := '0'; + signal In_Valid_d : std_logic := '0'; + signal In_IsKey_d : std_logic := '0'; signal In_Data_d : T_SLM(INPUTS - 1 downto 0, DATA_BITS - 1 downto 0) := (others => (others => '0')); - signal In_Meta_d : STD_LOGIC_VECTOR(META_BITS - 1 downto 0) := (others => '0'); + signal In_Meta_d : std_logic_vector(META_BITS - 1 downto 0) := (others => '0'); signal MetaVector : T_META_VECTOR(STAGES downto 0) := (others => (others => '0')); signal DataMatrix : T_DATA_MATRIX(STAGES downto 0) := (others => (others => (others => '0'))); @@ -122,10 +122,10 @@ architecture rtl of sortnet_BitonicSort is begin assert (not C_VERBOSE) - report "sortnet_BitonicSort:" & CR & - " DATA_BITS=" & INTEGER'image(DATA_BITS) & - " KEY_BITS=" & INTEGER'image(KEY_BITS) & - " META_BITS=" & INTEGER'image(META_BITS) + report "sortnet_BitonicSort:" & LF & + " DATA_BITS=" & integer'image(DATA_BITS) & + " KEY_BITS=" & integer'image(KEY_BITS) & + " META_BITS=" & integer'image(META_BITS) severity NOTE; In_Valid_d <= In_Valid when registered(Clock, ADD_INPUT_REGISTERS); @@ -139,28 +139,28 @@ begin MetaVector(0)(META_VECTOR_BITS - 1 downto META_VECTOR_BITS - META_BITS) <= In_Meta_d; genBlocks : for b in 0 to BLOCKS - 1 generate - constant START_DISTANCE : POSITIVE := 2**b; + constant START_DISTANCE : positive := 2**b; begin genStage : for s in 0 to b generate - constant STAGE_INDEX : NATURAL := triangularNumber(b) + s; - constant DISTANCE : POSITIVE := 2**(b - s); - constant GROUPS : POSITIVE := INPUTS / (DISTANCE * 2); - constant INSERT_PIPELINE_REGISTER : BOOLEAN := (PIPELINE_STAGE_AFTER /= 0) and (STAGE_INDEX mod PIPELINE_STAGE_AFTER = 0); + constant STAGE_INDEX : natural := triangularNumber(b) + s; + constant DISTANCE : positive := 2**(b - s); + constant GROUPS : positive := INPUTS / (DISTANCE * 2); + constant INSERT_PIPELINE_REGISTER : boolean := (PIPELINE_STAGE_AFTER /= 0) and (STAGE_INDEX mod PIPELINE_STAGE_AFTER = 0); begin MetaVector(STAGE_INDEX + 1) <= MetaVector(STAGE_INDEX) when registered(Clock, INSERT_PIPELINE_REGISTER); genGroups : for g in 0 to GROUPS - 1 generate - constant INV : STD_LOGIC := to_sl((g / (2 ** s) mod 2 = 1)); + constant INV : std_logic := to_sl((g / (2 ** s) mod 2 = 1)); begin genLoop : for l in 0 to DISTANCE - 1 generate - constant SRC0 : NATURAL := g * (DISTANCE * 2) + l; - constant SRC1 : NATURAL := SRC0 + DISTANCE; - - signal Greater : STD_LOGIC; - signal Switch_d : STD_LOGIC; - signal Switch_en : STD_LOGIC; - signal Switch_r : STD_LOGIC := '0'; - signal Switch : STD_LOGIC; + constant SRC0 : natural := g * (DISTANCE * 2) + l; + constant SRC1 : natural := SRC0 + DISTANCE; + + signal Greater : std_logic; + signal Switch_d : std_logic; + signal Switch_en : std_logic; + signal Switch_r : std_logic := '0'; + signal Switch : std_logic; signal NewData0 : T_DATA; signal NewData1 : T_DATA; diff --git a/src/sort/sortnet/sortnet_MergeSort_Streamed.vhdl b/src/sort/sortnet/sortnet_MergeSort_Streamed.vhdl index 23096fb4..0c8debae 100644 --- a/src/sort/sortnet/sortnet_MergeSort_Streamed.vhdl +++ b/src/sort/sortnet/sortnet_MergeSort_Streamed.vhdl @@ -1,15 +1,14 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: Sorting Network: Streaming MergeSort +-- Entity: Sorting Network: Streaming MergeSort -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: -- ============================================================================= @@ -41,64 +40,64 @@ use PoC.components.all; entity sortnet_MergeSort_Streamed is generic ( - FIFO_DEPTH : POSITIVE := 32; - KEY_BITS : POSITIVE := 32; - DATA_BITS : POSITIVE := 32 + FIFO_DEPTH : positive := 32; + KEY_BITS : positive := 32; + DATA_BITS : positive := 32 ); port ( - Clock : in STD_LOGIC; - Reset : in STD_LOGIC; - - Inverse : in STD_LOGIC := '0'; - - In_Valid : in STD_LOGIC; - In_Data : in STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0); - In_SOF : in STD_LOGIC; - In_IsKey : in STD_LOGIC; - In_EOF : in STD_LOGIC; - In_Ack : out STD_LOGIC; - - Out_Sync : out STD_LOGIC; - Out_Valid : out STD_LOGIC; - Out_Data : out STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0); - Out_SOF : out STD_LOGIC; - Out_IsKey : out STD_LOGIC; - Out_EOF : out STD_LOGIC; - Out_Ack : in STD_LOGIC + Clock : in std_logic; + Reset : in std_logic; + + Inverse : in std_logic := '0'; + + In_Valid : in std_logic; + In_Data : in std_logic_vector(DATA_BITS - 1 downto 0); + In_SOF : in std_logic; + In_IsKey : in std_logic; + In_EOF : in std_logic; + In_Ack : out std_logic; + + Out_Sync : out std_logic; + Out_Valid : out std_logic; + Out_Data : out std_logic_vector(DATA_BITS - 1 downto 0); + Out_SOF : out std_logic; + Out_IsKey : out std_logic; + Out_EOF : out std_logic; + Out_Ack : in std_logic ); end entity; architecture rtl of sortnet_MergeSort_Streamed is - constant DATA_SOF_BIT : NATURAL := DATA_BITS + 0; - constant DATA_ISKEY_BIT : NATURAL := DATA_BITS + 1; - constant DATA_EOF_BIT : NATURAL := DATA_BITS + 2; - constant FIFO_BITS : POSITIVE := DATA_BITS + 3; + constant DATA_SOF_BIT : natural := DATA_BITS + 0; + constant DATA_ISKEY_BIT : natural := DATA_BITS + 1; + constant DATA_EOF_BIT : natural := DATA_BITS + 2; + constant FIFO_BITS : positive := DATA_BITS + 3; - subtype T_FIFO_DATA is STD_LOGIC_VECTOR(FIFO_BITS - 1 downto 0); + subtype T_FIFO_DATA is std_logic_vector(FIFO_BITS - 1 downto 0); - signal FIFO_sel_r : STD_LOGIC := '0'; + signal FIFO_sel_r : std_logic := '0'; - signal FIFO_0_put : STD_LOGIC; + signal FIFO_0_put : std_logic; signal FIFO_0_DataIn : T_FIFO_DATA; - signal FIFO_0_Full : STD_LOGIC; - signal FIFO_0_got : STD_LOGIC; + signal FIFO_0_Full : std_logic; + signal FIFO_0_got : std_logic; signal FIFO_0_DataOut : T_FIFO_DATA; - signal FIFO_0_Valid : STD_LOGIC; + signal FIFO_0_Valid : std_logic; - signal FIFO_1_put : STD_LOGIC; + signal FIFO_1_put : std_logic; signal FIFO_1_DataIn : T_FIFO_DATA; - signal FIFO_1_Full : STD_LOGIC; - signal FIFO_1_got : STD_LOGIC; + signal FIFO_1_Full : std_logic; + signal FIFO_1_got : std_logic; signal FIFO_1_DataOut : T_FIFO_DATA; - signal FIFO_1_Valid : STD_LOGIC; + signal FIFO_1_Valid : std_logic; - signal Greater : STD_LOGIC; - signal Switch_d : STD_LOGIC; - signal Switch_en : STD_LOGIC; - signal Switch_r : STD_LOGIC := '0'; - signal Switch : STD_LOGIC; + signal Greater : std_logic; + signal Switch_d : std_logic; + signal Switch_en : std_logic; + signal Switch_r : std_logic := '0'; + signal Switch : std_logic; type T_STATE is (ST_IDLE, ST_MERGE, ST_EMPTY_FIFO_0, ST_EMPTY_FIFO_1); signal State : T_STATE := ST_IDLE; @@ -186,11 +185,11 @@ begin end process; process(State, FIFO_0_Valid, FIFO_0_DataOut, FIFO_1_Valid, FIFO_1_DataOut, Switch, Out_Ack) - variable IsKey : STD_LOGIC; - variable FIFO_0_SOF : STD_LOGIC; - variable FIFO_0_EOF : STD_LOGIC; - variable FIFO_1_SOF : STD_LOGIC; - variable FIFO_1_EOF : STD_LOGIC; + variable IsKey : std_logic; + variable FIFO_0_SOF : std_logic; + variable FIFO_0_EOF : std_logic; + variable FIFO_1_SOF : std_logic; + variable FIFO_1_EOF : std_logic; begin IsKey := FIFO_0_DataOut(DATA_ISKEY_BIT); FIFO_0_SOF := FIFO_0_DataOut(DATA_SOF_BIT); diff --git a/src/sort/sortnet/sortnet_OddEvenMergeSort.vhdl b/src/sort/sortnet/sortnet_OddEvenMergeSort.vhdl index 097b07eb..9fe3866d 100644 --- a/src/sort/sortnet/sortnet_OddEvenMergeSort.vhdl +++ b/src/sort/sortnet/sortnet_OddEvenMergeSort.vhdl @@ -1,15 +1,14 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: Sorting Network: Odd-Even-Merge-Sort +-- Entity: Sorting Network: Odd-Even-Merge-Sort -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: -- ============================================================================= @@ -35,6 +34,7 @@ use IEEE.NUMERIC_STD.all; library PoC; use PoC.math.all; +use PoC.config.all; use PoC.utils.all; use PoC.vectors.all; use PoC.components.all; @@ -42,49 +42,49 @@ use PoC.components.all; entity sortnet_OddEvenMergeSort is generic ( - INPUTS : POSITIVE := 128; -- input count - KEY_BITS : POSITIVE := 32; -- the first KEY_BITS of In_Data are used as a sorting critera (key) - DATA_BITS : POSITIVE := 32; -- inclusive KEY_BITS - META_BITS : NATURAL := 2; -- additional bits, not sorted but delayed as long as In_Data - PIPELINE_STAGE_AFTER : NATURAL := 2; -- add a pipline stage after n sorting stages - ADD_INPUT_REGISTERS : BOOLEAN := FALSE; -- - ADD_OUTPUT_REGISTERS : BOOLEAN := TRUE -- + INPUTS : positive := 128; -- input count + KEY_BITS : positive := 32; -- the first KEY_BITS of In_Data are used as a sorting critera (key) + DATA_BITS : positive := 32; -- inclusive KEY_BITS + META_BITS : natural := 2; -- additional bits, not sorted but delayed as long as In_Data + PIPELINE_STAGE_AFTER : natural := 2; -- add a pipline stage after n sorting stages + ADD_INPUT_REGISTERS : boolean := FALSE; -- + ADD_OUTPUT_REGISTERS : boolean := TRUE -- ); port ( - Clock : in STD_LOGIC; - Reset : in STD_LOGIC; + Clock : in std_logic; + Reset : in std_logic; - Inverse : in STD_LOGIC := '0'; + Inverse : in std_logic := '0'; - In_Valid : in STD_LOGIC; - In_IsKey : in STD_LOGIC; + In_Valid : in std_logic; + In_IsKey : in std_logic; In_Data : in T_SLM(INPUTS - 1 downto 0, DATA_BITS - 1 downto 0); - In_Meta : in STD_LOGIC_VECTOR(META_BITS - 1 downto 0); + In_Meta : in std_logic_vector(META_BITS - 1 downto 0); - Out_Valid : out STD_LOGIC; - Out_IsKey : out STD_LOGIC; + Out_Valid : out std_logic; + Out_IsKey : out std_logic; Out_Data : out T_SLM(INPUTS - 1 downto 0, DATA_BITS - 1 downto 0); - Out_Meta : out STD_LOGIC_VECTOR(META_BITS - 1 downto 0) + Out_Meta : out std_logic_vector(META_BITS - 1 downto 0) ); end entity; architecture rtl of sortnet_OddEvenMergeSort is - constant C_VERBOSE : BOOLEAN := POC_VERBOSE; + constant C_VERBOSE : boolean := POC_VERBOSE; - constant BLOCKS : POSITIVE := log2ceil(INPUTS); - constant STAGES : POSITIVE := triangularNumber(BLOCKS); + constant BLOCKS : positive := log2ceil(INPUTS); + constant STAGES : positive := triangularNumber(BLOCKS); - constant META_VALID_BIT : NATURAL := 0; - constant META_ISKEY_BIT : NATURAL := 1; - constant META_VECTOR_BITS : POSITIVE := META_BITS + 2; + constant META_VALID_BIT : natural := 0; + constant META_ISKEY_BIT : natural := 1; + constant META_VECTOR_BITS : positive := META_BITS + 2; - subtype T_META is STD_LOGIC_VECTOR(META_VECTOR_BITS - 1 downto 0); - type T_META_VECTOR is array(NATURAL range <>) of T_META; + subtype T_META is std_logic_vector(META_VECTOR_BITS - 1 downto 0); + type T_META_VECTOR is array(natural range <>) of T_META; - subtype T_DATA is STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0); - type T_DATA_VECTOR is array(NATURAL range <>) of T_DATA; - type T_DATA_MATRIX is array(NATURAL range <>) of T_DATA_VECTOR(INPUTS - 1 downto 0); + subtype T_DATA is std_logic_vector(DATA_BITS - 1 downto 0); + type T_DATA_VECTOR is array(natural range <>) of T_DATA; + type T_DATA_MATRIX is array(natural range <>) of T_DATA_VECTOR(INPUTS - 1 downto 0); function to_dv(slm : T_SLM) return T_DATA_VECTOR is variable Result : T_DATA_VECTOR(slm'range(1)); @@ -108,10 +108,10 @@ architecture rtl of sortnet_OddEvenMergeSort is return Result; end function; - signal In_Valid_d : STD_LOGIC := '0'; - signal In_IsKey_d : STD_LOGIC := '0'; + signal In_Valid_d : std_logic := '0'; + signal In_IsKey_d : std_logic := '0'; signal In_Data_d : T_SLM(INPUTS - 1 downto 0, DATA_BITS - 1 downto 0) := (others => (others => '0')); - signal In_Meta_d : STD_LOGIC_VECTOR(META_BITS - 1 downto 0) := (others => '0'); + signal In_Meta_d : std_logic_vector(META_BITS - 1 downto 0) := (others => '0'); signal MetaVector : T_META_VECTOR(STAGES downto 0) := (others => (others => '0')); signal DataMatrix : T_DATA_MATRIX(STAGES downto 0) := (others => (others => (others => '0'))); @@ -121,10 +121,10 @@ architecture rtl of sortnet_OddEvenMergeSort is begin assert (not C_VERBOSE) - report "sortnet_OddEvenMergeSort:" & CR & - " DATA_BITS=" & INTEGER'image(DATA_BITS) & - " KEY_BITS=" & INTEGER'image(KEY_BITS) & - " META_BITS=" & INTEGER'image(META_BITS) + report "sortnet_OddEvenMergeSort:" & LF & + " DATA_BITS=" & integer'image(DATA_BITS) & + " KEY_BITS=" & integer'image(KEY_BITS) & + " META_BITS=" & integer'image(META_BITS) severity NOTE; In_Valid_d <= In_Valid when registered(Clock, ADD_INPUT_REGISTERS); @@ -138,41 +138,41 @@ begin MetaVector(0)(META_VECTOR_BITS - 1 downto META_VECTOR_BITS - META_BITS) <= In_Meta_d; genBlocks : for b in 0 to BLOCKS - 1 generate - constant GROUPS : POSITIVE := 2 ** (BLOCKS - b - 1); + constant GROUPS : positive := 2 ** (BLOCKS - b - 1); begin genGroups : for g in 0 to GROUPS - 1 generate genStages : for s in 0 to b generate - constant DISTANCE : POSITIVE := 2 ** (b-s); - constant STAGE_INDEX : NATURAL := triangularNumber(b) + s; - constant INSERT_PIPELINE_REGISTER : BOOLEAN := (PIPELINE_STAGE_AFTER /= 0) and (STAGE_INDEX mod PIPELINE_STAGE_AFTER = 0); - constant START_INDEX : NATURAL := ite((s = 0), 0, DISTANCE); - constant END_INDEX : NATURAL := ((2**(b+1))-DISTANCE-START_INDEX-1) / (2 * DISTANCE); - constant SRC : NATURAL := (g * (INPUTS / GROUPS)); + constant DISTANCE : positive := 2 ** (b-s); + constant STAGE_INDEX : natural := triangularNumber(b) + s; + constant INSERT_PIPELINE_REGISTER : boolean := (PIPELINE_STAGE_AFTER /= 0) and (STAGE_INDEX mod PIPELINE_STAGE_AFTER = 0); + constant START_INDEX : natural := ite((s = 0), 0, DISTANCE); + constant END_INDEX : natural := ((2**(b+1))-DISTANCE-START_INDEX-1) / (2 * DISTANCE); + constant SRC : natural := g * (INPUTS / GROUPS); begin - genMeta : if (g = 0) generate + genMeta : if g = 0 generate MetaVector(STAGE_INDEX + 1) <= MetaVector(STAGE_INDEX) when registered(Clock, INSERT_PIPELINE_REGISTER); end generate; genJ0 : for j in 0 to START_INDEX - 1 generate - assert (not C_VERBOSE) report INTEGER'image(STAGE_INDEX) & " passthrough: " & INTEGER'image(SRC + j) severity NOTE; + assert (not C_VERBOSE) report integer'image(STAGE_INDEX) & " passthrough: " & INTEGER'image(SRC + j) severity NOTE; DataMatrix(STAGE_INDEX + 1)(SRC + j) <= DataMatrix(STAGE_INDEX)(SRC + j) when registered(Clock, INSERT_PIPELINE_REGISTER); end generate; genJ1 : for j in 0 to END_INDEX generate - constant K : NATURAL := (j * 2 * DISTANCE) + START_INDEX; + constant K : natural := (j * 2 * DISTANCE) + START_INDEX; begin genLoop : for i in 0 to DISTANCE - 1 generate - constant SRC0 : NATURAL := SRC + K + i; - constant SRC1 : NATURAL := SRC0 + DISTANCE; - - signal Greater : STD_LOGIC; - signal Switch_d : STD_LOGIC; - signal Switch_en : STD_LOGIC; - signal Switch_r : STD_LOGIC := '0'; - signal Switch : STD_LOGIC; + constant SRC0 : natural := SRC + K + i; + constant SRC1 : natural := SRC0 + DISTANCE; + + signal Greater : std_logic; + signal Switch_d : std_logic; + signal Switch_en : std_logic; + signal Switch_r : std_logic := '0'; + signal Switch : std_logic; signal NewData0 : T_DATA; signal NewData1 : T_DATA; begin - assert (not C_VERBOSE) report INTEGER'image(STAGE_INDEX) & " compare: " & INTEGER'image(SRC0) & " <-> " & INTEGER'image(SRC1) severity NOTE; + assert (not C_VERBOSE) report integer'image(STAGE_INDEX) & " compare: " & INTEGER'image(SRC0) & " <-> " & integer'image(SRC1) severity NOTE; Greater <= to_sl(unsigned(DataMatrix(STAGE_INDEX)(SRC0)(KEY_BITS - 1 downto 0)) > unsigned(DataMatrix(STAGE_INDEX)(SRC1)(KEY_BITS - 1 downto 0))); Switch_d <= Greater xor Inverse; @@ -188,7 +188,7 @@ begin end generate; end generate; genJ2 : for j in (((END_INDEX * 2 * DISTANCE) + START_INDEX) + 2*DISTANCE) to (INPUTS / GROUPS) - 1 generate - assert (not C_VERBOSE) report INTEGER'image(STAGE_INDEX) & " passthrough: " & INTEGER'image(SRC + j) severity NOTE; + assert (not C_VERBOSE) report integer'image(STAGE_INDEX) & " passthrough: " & INTEGER'image(SRC + j) severity NOTE; DataMatrix(STAGE_INDEX + 1)(SRC + j) <= DataMatrix(STAGE_INDEX)(SRC + j) when registered(Clock, INSERT_PIPELINE_REGISTER); end generate; end generate; diff --git a/src/sort/sortnet/sortnet_OddEvenSort.vhdl b/src/sort/sortnet/sortnet_OddEvenSort.vhdl index cc13f2fc..7517134c 100644 --- a/src/sort/sortnet/sortnet_OddEvenSort.vhdl +++ b/src/sort/sortnet/sortnet_OddEvenSort.vhdl @@ -1,15 +1,14 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: Sorting Network: Odd-Even-Sort (Transposition) +-- Entity: Sorting Network: Odd-Even-Sort (Transposition) -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: -- ============================================================================= @@ -34,6 +33,7 @@ use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; library PoC; +use PoC.config.all; use PoC.utils.all; use PoC.vectors.all; use PoC.components.all; @@ -41,49 +41,49 @@ use PoC.components.all; entity sortnet_OddEvenSort is generic ( - INPUTS : POSITIVE := 8; -- input count - KEY_BITS : POSITIVE := 32; -- the first KEY_BITS of In_Data are used as a sorting critera (key) - DATA_BITS : POSITIVE := 32; -- inclusive KEY_BITS - META_BITS : NATURAL := 2; -- additional bits, not sorted but delayed as long as In_Data - PIPELINE_STAGE_AFTER : NATURAL := 2; -- add a pipline stage after n sorting stages - ADD_INPUT_REGISTERS : BOOLEAN := FALSE; -- - ADD_OUTPUT_REGISTERS : BOOLEAN := TRUE -- + INPUTS : positive := 8; -- input count + KEY_BITS : positive := 32; -- the first KEY_BITS of In_Data are used as a sorting critera (key) + DATA_BITS : positive := 32; -- inclusive KEY_BITS + META_BITS : natural := 2; -- additional bits, not sorted but delayed as long as In_Data + PIPELINE_STAGE_AFTER : natural := 2; -- add a pipline stage after n sorting stages + ADD_INPUT_REGISTERS : boolean := FALSE; -- + ADD_OUTPUT_REGISTERS : boolean := TRUE -- ); port ( - Clock : in STD_LOGIC; - Reset : in STD_LOGIC; + Clock : in std_logic; + Reset : in std_logic; - Inverse : in STD_LOGIC := '0'; + Inverse : in std_logic := '0'; - In_Valid : in STD_LOGIC; - In_IsKey : in STD_LOGIC; + In_Valid : in std_logic; + In_IsKey : in std_logic; In_Data : in T_SLM(INPUTS - 1 downto 0, DATA_BITS - 1 downto 0); - In_Meta : in STD_LOGIC_VECTOR(META_BITS - 1 downto 0); + In_Meta : in std_logic_vector(META_BITS - 1 downto 0); - Out_Valid : out STD_LOGIC; - Out_IsKey : out STD_LOGIC; + Out_Valid : out std_logic; + Out_IsKey : out std_logic; Out_Data : out T_SLM(INPUTS - 1 downto 0, DATA_BITS - 1 downto 0); - Out_Meta : out STD_LOGIC_VECTOR(META_BITS - 1 downto 0) + Out_Meta : out std_logic_vector(META_BITS - 1 downto 0) ); end entity; architecture rtl of sortnet_OddEvenSort is - constant C_VERBOSE : BOOLEAN := POC_VERBOSE; + constant C_VERBOSE : boolean := POC_VERBOSE; - constant STAGES : POSITIVE := INPUTS; - constant DELAY : POSITIVE := (STAGES / PIPELINE_STAGE_AFTER) + ite(ADD_INPUT_REGISTERS, 1, 0) + ite(ADD_OUTPUT_REGISTERS, 1, 0); + constant STAGES : positive := INPUTS; + constant DELAY : positive := (STAGES / PIPELINE_STAGE_AFTER) + ite(ADD_INPUT_REGISTERS, 1, 0) + ite(ADD_OUTPUT_REGISTERS, 1, 0); - constant META_VALID_BIT : NATURAL := 0; - constant META_ISKEY_BIT : NATURAL := 1; - constant META_VECTOR_BITS : POSITIVE := META_BITS + 2; + constant META_VALID_BIT : natural := 0; + constant META_ISKEY_BIT : natural := 1; + constant META_VECTOR_BITS : positive := META_BITS + 2; - subtype T_META is STD_LOGIC_VECTOR(META_VECTOR_BITS - 1 downto 0); - type T_META_VECTOR is array(NATURAL range <>) of T_META; + subtype T_META is std_logic_vector(META_VECTOR_BITS - 1 downto 0); + type T_META_VECTOR is array(natural range <>) of T_META; - subtype T_DATA is STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0); - type T_DATA_VECTOR is array(NATURAL range <>) of T_DATA; - type T_DATA_MATRIX is array(NATURAL range <>) of T_DATA_VECTOR(INPUTS - 1 downto 0); + subtype T_DATA is std_logic_vector(DATA_BITS - 1 downto 0); + type T_DATA_VECTOR is array(natural range <>) of T_DATA; + type T_DATA_MATRIX is array(natural range <>) of T_DATA_VECTOR(INPUTS - 1 downto 0); function to_dv(slm : T_SLM) return T_DATA_VECTOR is variable Result : T_DATA_VECTOR(slm'range(1)); @@ -107,10 +107,10 @@ architecture rtl of sortnet_OddEvenSort is return Result; end function; - signal In_Valid_d : STD_LOGIC := '0'; - signal In_IsKey_d : STD_LOGIC := '0'; + signal In_Valid_d : std_logic := '0'; + signal In_IsKey_d : std_logic := '0'; signal In_Data_d : T_SLM(INPUTS - 1 downto 0, DATA_BITS - 1 downto 0) := (others => (others => '0')); - signal In_Meta_d : STD_LOGIC_VECTOR(META_BITS - 1 downto 0) := (others => '0'); + signal In_Meta_d : std_logic_vector(META_BITS - 1 downto 0) := (others => '0'); signal MetaVector : T_META_VECTOR(STAGES downto 0) := (others => (others => '0')); signal DataMatrix : T_DATA_MATRIX(STAGES downto 0) := (others => (others => (others => '0'))); @@ -120,10 +120,10 @@ architecture rtl of sortnet_OddEvenSort is begin assert (not C_VERBOSE) - report "sortnet_OddEvenSort:" & CR & - " DATA_BITS=" & INTEGER'image(DATA_BITS) & - " KEY_BITS=" & INTEGER'image(KEY_BITS) & - " META_BITS=" & INTEGER'image(META_BITS) + report "sortnet_OddEvenSort:" & LF & + " DATA_BITS=" & integer'image(DATA_BITS) & + " KEY_BITS=" & integer'image(KEY_BITS) & + " META_BITS=" & integer'image(META_BITS) severity NOTE; In_Valid_d <= In_Valid when registered(Clock, ADD_INPUT_REGISTERS); @@ -137,27 +137,27 @@ begin MetaVector(0)(META_VECTOR_BITS - 1 downto META_VECTOR_BITS - META_BITS) <= In_Meta_d; genStages : for stage in 0 to STAGES - 1 generate - constant STAGE_INDEX : NATURAL := stage; - constant INSERT_PIPELINE_REGISTER : BOOLEAN := ((PIPELINE_STAGE_AFTER > 0) and (STAGE_INDEX mod PIPELINE_STAGE_AFTER = 0)); + constant STAGE_INDEX : natural := stage; + constant INSERT_PIPELINE_REGISTER : boolean := ((PIPELINE_STAGE_AFTER > 0) and (STAGE_INDEX mod PIPELINE_STAGE_AFTER = 0)); begin - assert (not C_VERBOSE) report "STAGE_INDEX: " & INTEGER'image(STAGE_INDEX) & " reg=" & BOOLEAN'image(INSERT_PIPELINE_REGISTER) severity NOTE; + assert (not C_VERBOSE) report "STAGE_INDEX: " & integer'image(STAGE_INDEX) & " reg=" & BOOLEAN'image(INSERT_PIPELINE_REGISTER) severity NOTE; MetaVector(STAGE_INDEX + 1) <= MetaVector(STAGE_INDEX) when registered(Clock, INSERT_PIPELINE_REGISTER); genEven : if (STAGE_INDEX mod 2 = 0) generate genEvenSwitch : for i in 0 to (INPUTS / 2) - 1 generate - constant SRC0 : NATURAL := 2 * i; - constant SRC1 : NATURAL := SRC0 + 1; - - signal Greater : STD_LOGIC; - signal Switch_d : STD_LOGIC; - signal Switch_en : STD_LOGIC; - signal Switch_r : STD_LOGIC := '0'; - signal Switch : STD_LOGIC; + constant SRC0 : natural := 2 * i; + constant SRC1 : natural := SRC0 + 1; + + signal Greater : std_logic; + signal Switch_d : std_logic; + signal Switch_en : std_logic; + signal Switch_r : std_logic := '0'; + signal Switch : std_logic; signal NewData0 : T_DATA; signal NewData1 : T_DATA; begin - assert (not C_VERBOSE) report INTEGER'image(STAGE_INDEX) & ": " & INTEGER'image(SRC0) & " <-> " & INTEGER'image(SRC1) severity NOTE; + assert (not C_VERBOSE) report integer'image(STAGE_INDEX) & ": " & INTEGER'image(SRC0) & " <-> " & integer'image(SRC1) severity NOTE; Greater <= to_sl(unsigned(DataMatrix(STAGE_INDEX)(SRC0)(KEY_BITS - 1 downto 0)) > unsigned(DataMatrix(STAGE_INDEX)(SRC1)(KEY_BITS - 1 downto 0))); Switch_d <= Greater xor Inverse; @@ -177,18 +177,18 @@ begin DataMatrix(STAGE_INDEX + 1)(INPUTS - 1) <= DataMatrix(STAGE_INDEX)(INPUTS - 1) when registered(Clock, INSERT_PIPELINE_REGISTER); genOddSwitch : for i in 0 to ((INPUTS - 1) / 2) - 1 generate - constant SRC0 : NATURAL := 2 * i + 1; - constant SRC1 : NATURAL := SRC0 + 1; - - signal Greater : STD_LOGIC; - signal Switch_d : STD_LOGIC; - signal Switch_en : STD_LOGIC; - signal Switch_r : STD_LOGIC := '0'; - signal Switch : STD_LOGIC; + constant SRC0 : natural := 2 * i + 1; + constant SRC1 : natural := SRC0 + 1; + + signal Greater : std_logic; + signal Switch_d : std_logic; + signal Switch_en : std_logic; + signal Switch_r : std_logic := '0'; + signal Switch : std_logic; signal NewData0 : T_DATA; signal NewData1 : T_DATA; begin - assert (not C_VERBOSE) report INTEGER'image(STAGE_INDEX) & ": " & INTEGER'image(SRC0) & " <-> " & INTEGER'image(SRC1) severity NOTE; + assert (not C_VERBOSE) report integer'image(STAGE_INDEX) & ": " & INTEGER'image(SRC0) & " <-> " & integer'image(SRC1) severity NOTE; Greater <= to_sl(unsigned(DataMatrix(STAGE_INDEX)(SRC0)(KEY_BITS - 1 downto 0)) > unsigned(DataMatrix(STAGE_INDEX)(SRC1)(KEY_BITS - 1 downto 0))); Switch_d <= Greater xor Inverse; diff --git a/src/sort/sortnet/sortnet_Stream_Adapter.vhdl b/src/sort/sortnet/sortnet_Stream_Adapter.vhdl index 50f15b05..e3dc377b 100644 --- a/src/sort/sortnet/sortnet_Stream_Adapter.vhdl +++ b/src/sort/sortnet/sortnet_Stream_Adapter.vhdl @@ -1,15 +1,14 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: Sorting Network: Stream to sortnet adapter +-- Entity: Sorting Network: Stream to sortnet adapter -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: -- ============================================================================= @@ -42,54 +41,54 @@ use PoC.sortnet.all; entity sortnet_Stream_Adapter is generic ( - STREAM_DATA_BITS : POSITIVE := 32; - STREAM_META_BITS : POSITIVE := 2; + STREAM_DATA_BITS : positive := 32; + STREAM_META_BITS : positive := 2; SORTNET_IMPL : T_SORTNET_IMPL := SORT_SORTNET_IMPL_ODDEVEN_MERGESORT; - SORTNET_SIZE : POSITIVE := 32; - SORTNET_KEY_BITS : POSITIVE := 32; - SORTNET_DATA_BITS : NATURAL := 32; - INVERSE : BOOLEAN := FALSE + SORTNET_SIZE : positive := 32; + SORTNET_KEY_BITS : positive := 32; + SORTNET_DATA_BITS : natural := 32; + INVERSE : boolean := FALSE ); port ( - Clock : in STD_LOGIC; - Reset : in STD_LOGIC; - - In_Valid : in STD_LOGIC; - In_IsKey : in STD_LOGIC; - In_Data : in STD_LOGIC_VECTOR(STREAM_DATA_BITS - 1 downto 0); - In_Meta : in STD_LOGIC_VECTOR(STREAM_META_BITS - 1 downto 0); - In_Ack : out STD_LOGIC; - - Out_Valid : out STD_LOGIC; - Out_IsKey : out STD_LOGIC; - Out_Data : out STD_LOGIC_VECTOR(STREAM_DATA_BITS - 1 downto 0); - Out_Meta : out STD_LOGIC_VECTOR(STREAM_META_BITS - 1 downto 0); - Out_Ack : in STD_LOGIC + Clock : in std_logic; + Reset : in std_logic; + + In_Valid : in std_logic; + In_IsKey : in std_logic; + In_Data : in std_logic_vector(STREAM_DATA_BITS - 1 downto 0); + In_Meta : in std_logic_vector(STREAM_META_BITS - 1 downto 0); + In_Ack : out std_logic; + + Out_Valid : out std_logic; + Out_IsKey : out std_logic; + Out_Data : out std_logic_vector(STREAM_DATA_BITS - 1 downto 0); + Out_Meta : out std_logic_vector(STREAM_META_BITS - 1 downto 0); + Out_Ack : in std_logic ); end entity; architecture rtl of sortnet_Stream_Adapter is - constant C_VERBOSE : BOOLEAN := FALSE; + constant C_VERBOSE : boolean := FALSE; - constant GEARBOX_BITS : POSITIVE := SORTNET_SIZE * SORTNET_DATA_BITS; - constant PIPELINE_STAGE_AFTER : NATURAL := 2; + constant GEARBOX_BITS : positive := SORTNET_SIZE * SORTNET_DATA_BITS; + constant PIPELINE_STAGE_AFTER : natural := 2; - constant META_ISKEY_BIT : NATURAL := 0; - constant META_BITS : POSITIVE := STREAM_META_BITS + 1; + constant META_ISKEY_BIT : natural := 0; + constant META_BITS : positive := STREAM_META_BITS + 1; - signal MetaIn : STD_LOGIC_VECTOR(META_BITS - 1 downto 0); + signal MetaIn : std_logic_vector(META_BITS - 1 downto 0); - signal gearup_Valid : STD_LOGIC; - signal gearup_Data : STD_LOGIC_VECTOR(GEARBOX_BITS - 1 downto 0); - signal gearup_Meta : STD_LOGIC_VECTOR(META_BITS - 1 downto 0); + signal gearup_Valid : std_logic; + signal gearup_Data : std_logic_vector(GEARBOX_BITS - 1 downto 0); + signal gearup_Meta : std_logic_vector(META_BITS - 1 downto 0); - signal sort_Valid : STD_LOGIC; - signal sort_IsKey : STD_LOGIC; - signal sort_Data : STD_LOGIC_VECTOR(GEARBOX_BITS - 1 downto 0); - signal sort_Meta : STD_LOGIC_VECTOR(STREAM_META_BITS - 1 downto 0); + signal sort_Valid : std_logic; + signal sort_IsKey : std_logic; + signal sort_Data : std_logic_vector(GEARBOX_BITS - 1 downto 0); + signal sort_Meta : std_logic_vector(STREAM_META_BITS - 1 downto 0); - signal geardown_nxt : STD_LOGIC; + signal geardown_nxt : std_logic; begin In_Ack <= '1'; @@ -118,7 +117,7 @@ begin Out_Valid => gearup_Valid ); - genOES : if (SORTNET_IMPL = SORT_SORTNET_IMPL_ODDEVEN_SORT) generate + genOES : if SORTNET_IMPL = SORT_SORTNET_IMPL_ODDEVEN_SORT generate signal DataInputMatrix : T_SLM(SORTNET_SIZE - 1 downto 0, SORTNET_DATA_BITS - 1 downto 0); signal DataOutputMatrix : T_SLM(SORTNET_SIZE - 1 downto 0, SORTNET_DATA_BITS - 1 downto 0); @@ -155,7 +154,7 @@ begin end generate; - genOEMS : if (SORTNET_IMPL = SORT_SORTNET_IMPL_ODDEVEN_MERGESORT) generate + genOEMS : if SORTNET_IMPL = SORT_SORTNET_IMPL_ODDEVEN_MERGESORT generate signal DataInputMatrix : T_SLM(SORTNET_SIZE - 1 downto 0, SORTNET_DATA_BITS - 1 downto 0); signal DataOutputMatrix : T_SLM(SORTNET_SIZE - 1 downto 0, SORTNET_DATA_BITS - 1 downto 0); @@ -190,7 +189,7 @@ begin end generate; - genBS : if (SORTNET_IMPL = SORT_SORTNET_IMPL_BITONIC_SORT) generate + genBS : if SORTNET_IMPL = SORT_SORTNET_IMPL_BITONIC_SORT generate signal DataInputMatrix : T_SLM(SORTNET_SIZE - 1 downto 0, SORTNET_DATA_BITS - 1 downto 0); signal DataOutputMatrix : T_SLM(SORTNET_SIZE - 1 downto 0, SORTNET_DATA_BITS - 1 downto 0); diff --git a/src/sort/sortnet/sortnet_Stream_Adapter2.vhdl b/src/sort/sortnet/sortnet_Stream_Adapter2.vhdl index 75709560..cf6e88c4 100644 --- a/src/sort/sortnet/sortnet_Stream_Adapter2.vhdl +++ b/src/sort/sortnet/sortnet_Stream_Adapter2.vhdl @@ -1,15 +1,14 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: Sorting Network: Stream to sortnet adapter +-- Entity: Sorting Network: Stream to sortnet adapter -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: -- ============================================================================= @@ -42,86 +41,86 @@ use PoC.sortnet.all; entity sortnet_Stream_Adapter2 is generic ( - STREAM_DATA_BITS : POSITIVE := 32; - STREAM_META_BITS : POSITIVE := 2; - DATA_COLUMNS : POSITIVE := 2; + STREAM_DATA_BITS : positive := 32; + STREAM_META_BITS : positive := 2; + DATA_COLUMNS : positive := 2; SORTNET_IMPL : T_SORTNET_IMPL := SORT_SORTNET_IMPL_ODDEVEN_MERGESORT; - SORTNET_SIZE : POSITIVE := 32; - SORTNET_KEY_BITS : POSITIVE := 32; - SORTNET_DATA_BITS : NATURAL := 32; - SORTNET_REG_AFTER : NATURAL := 2; - MERGENET_STAGES : POSITIVE := 2 + SORTNET_SIZE : positive := 32; + SORTNET_KEY_BITS : positive := 32; + SORTNET_DATA_BITS : natural := 32; + SORTNET_REG_AFTER : natural := 2; + MERGENET_STAGES : positive := 2 ); port ( - Clock : in STD_LOGIC; - Reset : in STD_LOGIC; - - Inverse : in STD_LOGIC := '0'; - - In_Valid : in STD_LOGIC; - In_Data : in STD_LOGIC_VECTOR(STREAM_DATA_BITS - 1 downto 0); - In_Meta : in STD_LOGIC_VECTOR(STREAM_META_BITS - 1 downto 0); - In_SOF : in STD_LOGIC; - In_IsKey : in STD_LOGIC; - In_EOF : in STD_LOGIC; - In_Ack : out STD_LOGIC; - - Out_Valid : out STD_LOGIC; - Out_Data : out STD_LOGIC_VECTOR(STREAM_DATA_BITS - 1 downto 0); - Out_Meta : out STD_LOGIC_VECTOR(STREAM_META_BITS - 1 downto 0); - Out_SOF : out STD_LOGIC; - Out_IsKey : out STD_LOGIC; - Out_EOF : out STD_LOGIC; - Out_Ack : in STD_LOGIC + Clock : in std_logic; + Reset : in std_logic; + + Inverse : in std_logic := '0'; + + In_Valid : in std_logic; + In_Data : in std_logic_vector(STREAM_DATA_BITS - 1 downto 0); + In_Meta : in std_logic_vector(STREAM_META_BITS - 1 downto 0); + In_SOF : in std_logic; + In_IsKey : in std_logic; + In_EOF : in std_logic; + In_Ack : out std_logic; + + Out_Valid : out std_logic; + Out_Data : out std_logic_vector(STREAM_DATA_BITS - 1 downto 0); + Out_Meta : out std_logic_vector(STREAM_META_BITS - 1 downto 0); + Out_SOF : out std_logic; + Out_IsKey : out std_logic; + Out_EOF : out std_logic; + Out_Ack : in std_logic ); end entity; architecture rtl of sortnet_Stream_Adapter2 is - constant C_VERBOSE : BOOLEAN := FALSE; - - constant GEARBOX_BITS : POSITIVE := SORTNET_SIZE * SORTNET_DATA_BITS; - constant TRANSFORM_BITS : POSITIVE := DATA_COLUMNS * SORTNET_DATA_BITS; - constant MERGE_BITS : POSITIVE := TRANSFORM_BITS; - - constant META_ISKEY_BIT : NATURAL := 0; - constant META_BITS : POSITIVE := STREAM_META_BITS + 1; - - signal Synchronized_r : STD_LOGIC := '0'; - - signal SyncIn : STD_LOGIC; - signal MetaIn : STD_LOGIC_VECTOR(META_BITS - 1 downto 0); - - signal gearup_Sync : STD_LOGIC; - signal gearup_Valid : STD_LOGIC; - signal gearup_Data : STD_LOGIC_VECTOR(GEARBOX_BITS - 1 downto 0); - signal gearup_Meta : STD_LOGIC_VECTOR(META_BITS - 1 downto 0); - signal gearup_First : STD_LOGIC; - signal gearup_Last : STD_LOGIC; - - signal sort_Valid : STD_LOGIC; - signal sort_IsKey : STD_LOGIC; - signal sort_Data : STD_LOGIC_VECTOR(GEARBOX_BITS - 1 downto 0); - signal sort_Meta : STD_LOGIC_VECTOR(STREAM_META_BITS - 1 downto 0); - - signal transform_Valid : STD_LOGIC; - signal transform_Data : STD_LOGIC_VECTOR(TRANSFORM_BITS - 1 downto 0); - signal transform_Meta : STD_LOGIC_VECTOR(STREAM_META_BITS - 1 downto 0); - signal transform_SOF : STD_LOGIC; - signal transform_EOF : STD_LOGIC; - - signal merge_Sync : STD_LOGIC; - signal merge_Valid : STD_LOGIC; - signal merge_Data : STD_LOGIC_VECTOR(MERGE_BITS - 1 downto 0); - signal merge_Meta : STD_LOGIC_VECTOR(STREAM_META_BITS - 1 downto 0); - signal merge_SOF : STD_LOGIC; - signal merge_EOF : STD_LOGIC; - signal merge_Ack : STD_LOGIC; - - signal geardown_nxt : STD_LOGIC; - signal geardown_Meta : STD_LOGIC_VECTOR(STREAM_META_BITS - 1 downto 0); - signal geardown_First : STD_LOGIC; - signal geardown_Last : STD_LOGIC; + constant C_VERBOSE : boolean := FALSE; + + constant GEARBOX_BITS : positive := SORTNET_SIZE * SORTNET_DATA_BITS; + constant TRANSFORM_BITS : positive := DATA_COLUMNS * SORTNET_DATA_BITS; + constant MERGE_BITS : positive := TRANSFORM_BITS; + + constant META_ISKEY_BIT : natural := 0; + constant META_BITS : positive := STREAM_META_BITS + 1; + + signal Synchronized_r : std_logic := '0'; + + signal SyncIn : std_logic; + signal MetaIn : std_logic_vector(META_BITS - 1 downto 0); + + signal gearup_Sync : std_logic; + signal gearup_Valid : std_logic; + signal gearup_Data : std_logic_vector(GEARBOX_BITS - 1 downto 0); + signal gearup_Meta : std_logic_vector(META_BITS - 1 downto 0); + signal gearup_First : std_logic; + signal gearup_Last : std_logic; + + signal sort_Valid : std_logic; + signal sort_IsKey : std_logic; + signal sort_Data : std_logic_vector(GEARBOX_BITS - 1 downto 0); + signal sort_Meta : std_logic_vector(STREAM_META_BITS - 1 downto 0); + + signal transform_Valid : std_logic; + signal transform_Data : std_logic_vector(TRANSFORM_BITS - 1 downto 0); + signal transform_Meta : std_logic_vector(STREAM_META_BITS - 1 downto 0); + signal transform_SOF : std_logic; + signal transform_EOF : std_logic; + + signal merge_Sync : std_logic; + signal merge_Valid : std_logic; + signal merge_Data : std_logic_vector(MERGE_BITS - 1 downto 0); + signal merge_Meta : std_logic_vector(STREAM_META_BITS - 1 downto 0); + signal merge_SOF : std_logic; + signal merge_EOF : std_logic; + signal merge_Ack : std_logic; + + signal geardown_nxt : std_logic; + signal geardown_Meta : std_logic_vector(STREAM_META_BITS - 1 downto 0); + signal geardown_First : std_logic; + signal geardown_Last : std_logic; begin In_Ack <= '1'; @@ -155,7 +154,7 @@ begin Out_Last => gearup_Last ); - genOES : if (SORTNET_IMPL = SORT_SORTNET_IMPL_ODDEVEN_SORT) generate + genOES : if SORTNET_IMPL = SORT_SORTNET_IMPL_ODDEVEN_SORT generate signal DataInputMatrix : T_SLM(SORTNET_SIZE - 1 downto 0, SORTNET_DATA_BITS - 1 downto 0); signal DataOutputMatrix : T_SLM(SORTNET_SIZE - 1 downto 0, SORTNET_DATA_BITS - 1 downto 0); @@ -194,7 +193,7 @@ begin end generate; - genOEMS : if (SORTNET_IMPL = SORT_SORTNET_IMPL_ODDEVEN_MERGESORT) generate + genOEMS : if SORTNET_IMPL = SORT_SORTNET_IMPL_ODDEVEN_MERGESORT generate signal DataInputMatrix : T_SLM(SORTNET_SIZE - 1 downto 0, SORTNET_DATA_BITS - 1 downto 0); signal DataOutputMatrix : T_SLM(SORTNET_SIZE - 1 downto 0, SORTNET_DATA_BITS - 1 downto 0); @@ -231,7 +230,7 @@ begin end generate; - genBS : if (SORTNET_IMPL = SORT_SORTNET_IMPL_BITONIC_SORT) generate + genBS : if SORTNET_IMPL = SORT_SORTNET_IMPL_BITONIC_SORT generate signal DataInputMatrix : T_SLM(SORTNET_SIZE - 1 downto 0, SORTNET_DATA_BITS - 1 downto 0); signal DataOutputMatrix : T_SLM(SORTNET_SIZE - 1 downto 0, SORTNET_DATA_BITS - 1 downto 0); @@ -300,14 +299,14 @@ begin end block; blkMergeSort : block - subtype T_MERGE_DATA is STD_LOGIC_VECTOR(TRANSFORM_BITS - 1 downto 0); - type T_MERGE_DATA_VECTOR is array(NATURAL range <>) of T_MERGE_DATA; + subtype T_MERGE_DATA is std_logic_vector(TRANSFORM_BITS - 1 downto 0); + type T_MERGE_DATA_VECTOR is array(natural range <>) of T_MERGE_DATA; - signal MergeSortMatrix_Valid : STD_LOGIC_VECTOR(MERGENET_STAGES downto 0); + signal MergeSortMatrix_Valid : std_logic_vector(MERGENET_STAGES downto 0); signal MergeSortMatrix_Data : T_MERGE_DATA_VECTOR(MERGENET_STAGES downto 0); - signal MergeSortMatrix_SOF : STD_LOGIC_VECTOR(MERGENET_STAGES downto 0); - signal MergeSortMatrix_EOF : STD_LOGIC_VECTOR(MERGENET_STAGES downto 0); - signal MergeSortMatrix_Ack : STD_LOGIC_VECTOR(MERGENET_STAGES downto 0); + signal MergeSortMatrix_SOF : std_logic_vector(MERGENET_STAGES downto 0); + signal MergeSortMatrix_EOF : std_logic_vector(MERGENET_STAGES downto 0); + signal MergeSortMatrix_Ack : std_logic_vector(MERGENET_STAGES downto 0); begin MergeSortMatrix_Valid(0) <= transform_Valid; MergeSortMatrix_Data(0) <= transform_Data; @@ -316,7 +315,7 @@ begin merge_Ack <= MergeSortMatrix_Ack(0); genMerge : for i in 0 to MERGENET_STAGES - 1 generate - constant FIFO_DEPTH : POSITIVE := 2**i * SORTNET_SIZE; + constant FIFO_DEPTH : positive := 2**i * SORTNET_SIZE; begin merge : entity PoC.sortnet_MergeSort_Streamed generic map ( diff --git a/src/sort/sortnet/sortnet_Transform.vhdl b/src/sort/sortnet/sortnet_Transform.vhdl index 532ba86d..ce9abc5b 100644 --- a/src/sort/sortnet/sortnet_Transform.vhdl +++ b/src/sort/sortnet/sortnet_Transform.vhdl @@ -1,15 +1,14 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- -- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: Sorting Network: Data structure transformation +-- Entity: Sorting Network: Data structure transformation -- -- Description: --- ------------------------------------ --- TODO +-- ------------------------------------- +-- .. TODO:: No documentation available. -- -- License: -- ============================================================================= @@ -41,32 +40,32 @@ use PoC.components.all; entity sortnet_Transform is generic ( - ROWS : POSITIVE := 16; - COLUMNS : POSITIVE := 4; - DATA_BITS : POSITIVE := 8 + ROWS : positive := 16; + COLUMNS : positive := 4; + DATA_BITS : positive := 8 ); port ( - Clock : in STD_LOGIC; - Reset : in STD_LOGIC; + Clock : in std_logic; + Reset : in std_logic; - In_Valid : in STD_LOGIC; + In_Valid : in std_logic; In_Data : in T_SLM(ROWS - 1 downto 0, DATA_BITS - 1 downto 0); - In_SOF : in STD_LOGIC; - In_EOF : in STD_LOGIC; + In_SOF : in std_logic; + In_EOF : in std_logic; - Out_Valid : out STD_LOGIC; + Out_Valid : out std_logic; Out_Data : out T_SLM(COLUMNS - 1 downto 0, DATA_BITS - 1 downto 0); - Out_SOF : out STD_LOGIC; - Out_EOF : out STD_LOGIC + Out_SOF : out std_logic; + Out_EOF : out std_logic ); end entity; architecture rtl of sortnet_Transform is - subtype T_DATA is STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0); - type T_DATA_VECTOR is array(NATURAL range <>) of T_DATA; - type T_DATA_MATRIX is array(NATURAL range <>) of T_DATA_VECTOR(ROWS - 1 downto 0); + subtype T_DATA is std_logic_vector(DATA_BITS - 1 downto 0); + type T_DATA_VECTOR is array(natural range <>) of T_DATA; + type T_DATA_MATRIX is array(natural range <>) of T_DATA_VECTOR(ROWS - 1 downto 0); function to_dv(slm : T_SLM) return T_DATA_VECTOR is variable Result : T_DATA_VECTOR(slm'range(1)); @@ -81,23 +80,23 @@ architecture rtl of sortnet_Transform is signal DataIn : T_DATA_VECTOR(ROWS - 1 downto 0); - signal ColumnWriter_rst : STD_LOGIC; - signal ColumnWriter_us : UNSIGNED(log2ceilnz(COLUMNS) - 1 downto 0) := (others => '0'); - signal ColumnWriter_ov : STD_LOGIC; + signal ColumnWriter_rst : std_logic; + signal ColumnWriter_us : unsigned(log2ceilnz(COLUMNS) - 1 downto 0) := (others => '0'); + signal ColumnWriter_ov : std_logic; signal InputBuffer : T_DATA_MATRIX(COLUMNS - 1 downto 0) := (others => (others => (others => '0'))); - signal RowReader_en_r : STD_LOGIC := '0'; + signal RowReader_en_r : std_logic := '0'; - signal RowReader_rst : STD_LOGIC; - signal RowReader_en : STD_LOGIC; - signal RowReader_us : UNSIGNED(log2ceilnz(ROWS) - 1 downto 0) := (others => '0'); - signal RowReader_ov : STD_LOGIC; + signal RowReader_rst : std_logic; + signal RowReader_en : std_logic; + signal RowReader_us : unsigned(log2ceilnz(ROWS) - 1 downto 0) := (others => '0'); + signal RowReader_ov : std_logic; begin DataIn <= to_dv(In_Data); - ColumnWriter_rst <= (ColumnWriter_ov and In_Valid); -- or In_Sync; + ColumnWriter_rst <= ColumnWriter_ov and In_Valid; -- or In_Sync; ColumnWriter_us <= upcounter_next(cnt => ColumnWriter_us, rst => ColumnWriter_rst, en => In_Valid) when rising_edge(Clock); ColumnWriter_ov <= upcounter_equal(cnt => ColumnWriter_us, value => COLUMNS - 1); @@ -114,7 +113,7 @@ begin RowReader_en_r <= ffrs(q => RowReader_en_r, set => (ColumnWriter_ov and In_Valid), rst => RowReader_ov) when rising_edge(Clock); - RowReader_rst <= (ColumnWriter_ov and RowReader_ov); -- or In_Sync; + RowReader_rst <= ColumnWriter_ov and RowReader_ov; -- or In_Sync; RowReader_en <= RowReader_en_r; RowReader_us <= upcounter_next(cnt => RowReader_us, rst => RowReader_rst, en => RowReader_en) when rising_edge(Clock); RowReader_ov <= upcounter_equal(cnt => RowReader_us, value => ROWS - 1); diff --git a/src/xil/mig/mig_KC705_MT8JTF12864HZ_1G6.rules b/src/xil/mig/mig_KC705_MT8JTF12864HZ_1G6.rules index 7435b6e7..9e1b3384 100644 --- a/src/xil/mig/mig_KC705_MT8JTF12864HZ_1G6.rules +++ b/src/xil/mig/mig_KC705_MT8JTF12864HZ_1G6.rules @@ -65,4 +65,7 @@ PostProcessRules Copy "${tempDir}/user_design/rtl/ui/mig_7series_v1_9_ui_cmd.v" To "${dstDir}/mig_7series_v1_9_ui_cmd.v" Copy "${tempDir}/user_design/rtl/${TopLevel}.vhd" To "${dstDir}/${TopLevel}_top.vhd" Copy "${tempDir}/user_design/constraints/${TopLevel}.ucf" To "${dstDir}/${TopLevel}.ncf" + File "${dstDir}/${TopLevel}.ncf" + Replace "DATAPATHONLY;" With "DATAPATHONLY;\\nINST \"*/xadc_supplied_temperature.rst_r1*\" TNM=\"TNM_XADC_ASYNC_RST\";\\nTIMESPEC \"TS_XADC_ASYNC_RST\" = TO \"TNM_XADC_ASYNC_RST\" TIG;" + End File End PostProcessRules diff --git a/src/xil/reconfig/reconfig_icap_fsm.vhdl b/src/xil/reconfig/reconfig_icap_fsm.vhdl new file mode 100644 index 00000000..717b065a --- /dev/null +++ b/src/xil/reconfig/reconfig_icap_fsm.vhdl @@ -0,0 +1,312 @@ +-- EMACS settings: -*- tab-width: 4; indent-tabs-mode: t -*- +-- vim: tabstop=4:shiftwidth=4:noexpandtab +-- kate: tab-width 4; replace-tabs off; indent-width 4; +-- ============================================================================= +-- Authors: Paul Genssler +-- +-- Entity: ICAP FSM +-- +-- Description: +-- ------------------------------------- +-- This module parses the data stream to the Xilinx "Internal Configuration Access Port" (ICAP) +-- primitives to generate control signals. Tested on: +-- +-- * Virtex-6 +-- * Virtex-7 +-- +-- License: +-- ============================================================================= +-- Copyright 2007-2016 Technische Universitaet Dresden - Germany, +-- Chair for VLSI-Design, Diagnostics and Architecture +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library poc; +use POC.utils.all; +use POC.vectors.all; + +entity reconfig_icap_fsm is + port ( + clk : in std_logic; + reset : in std_logic; -- high-active reset + -- interface to connect to the icap + icap_in : out std_logic_vector(31 downto 0); -- data that will go into the icap + icap_out : in std_logic_vector(31 downto 0); -- data from the icap + icap_csb : out std_logic; + icap_rw : out std_logic; + + -- data interface, no internal fifos + in_data : in std_logic_vector(31 downto 0); -- new configuration data + in_data_valid : in std_logic; -- input data is valid + in_data_rden : out std_logic; -- possible to send data + out_data : out std_logic_vector(31 downto 0); -- data read from the fifo + out_data_valid : out std_logic; -- data from icap is valid + out_data_full : in std_logic; -- receiving buffer is full, halt icap + + -- control structures + status : out std_logic_vector(31 downto 0) -- status vector + ); +end reconfig_icap_fsm; + +architecture arch of reconfig_icap_fsm is + + type t_state is (ready, abort0, abort1, abort2, abort3, write, writing, pre_reg_read0, pre_reg_read1, pre_stream_read0, read, reading, post_read); + signal cur_state : t_state := ready; + signal nxt_state : t_state := ready; + + -- detect the status of the synchronization + type t_sync_state is (none, dummy0, bus_width0, bus_width1, dummy1, synced, cmdWrite, dsynced); + signal sync_state : t_sync_state; + -- flag will be (re)set in the clocking process for the main fsm + signal sync_state_flag : boolean; + + constant sync_s_dummy : std_logic_vector(31 downto 0) := x"FFFFFFFF"; + constant sync_s_bus_p_0 : std_logic_vector(31 downto 0) := x"000000BB"; + constant sync_s_bus_p_1 : std_logic_vector(31 downto 0) := x"11220044"; + constant sync_s_sync : std_logic_vector(31 downto 0) := x"AA995566"; + constant sync_s_regW : std_logic_vector(31 downto 0) := x"30008001"; + constant sync_s_dsync : std_logic_vector(31 downto 0) := x"0000000D"; + + constant cmd_nop : std_logic_vector(31 downto 0) := x"20000000"; + + -- commands for icap's cmd register + constant cmd_reg_wcfg : std_logic_vector(4 downto 0) := "00001"; -- write cfg data prior to write + constant reg_fdro : std_logic_vector(4 downto 0) := "00011"; -- read cfg data register + + signal icap_enable : boolean := false; + signal icap_read : boolean := false; + signal icap_in_r : std_logic_vector(31 downto 0); + -- icap bit switching + signal in_data_swap : std_logic_vector(31 downto 0); + signal icap_out_swap : std_logic_vector(31 downto 0); + + -- icap status word signals + signal icap_error : std_logic := '0'; + signal icap_sync : std_logic := '0'; + signal icap_abort : std_logic := '0'; + signal icap_status_valid : std_logic := '0'; + + signal readback_cnt : unsigned(26 downto 0) := (others=>'0'); + signal readback_cnt_en : boolean; + signal readback_cnt_rst : boolean := true; + + -- delayed signals + signal in_data_valid_d : std_logic; + signal in_data_valid_re : std_logic; -- rising edge on in_data_valid signal + + -- status word signals + signal pr_reset : boolean := false; + signal status_error : boolean := false; +begin + -- map icap_enable to the low-active csb + icap_csb <= to_sl(not icap_enable) when rising_edge(clk); + icap_rw <= to_sl(icap_read) when rising_edge(clk); + + -- drive icap data + icap_in <= icap_in_r when rising_edge(clk); + icap_in_r <= in_data_swap when in_data_valid = '1' else x"00000000"; + + out_data <= icap_out_swap when rising_edge(clk); + + -- TODO detect errors + status_error <= false; + + -- construct status word + status(0) <= to_sl(pr_reset) when rising_edge(clk); + status(1) <= to_sl(not readback_cnt_rst) when rising_edge(clk); -- readback in progress + status(2) <= to_sl(status_error) when rising_edge(clk); + status(3) <= to_sl(cur_state = ready) when rising_edge(clk); + status(31 downto 4) <= (others => '0'); + + -- edge detection + in_data_valid_d <= in_data_valid when rising_edge(clk); + in_data_valid_re <= not in_data_valid_d and in_data_valid; + + -- combinatorial state machine + cur_state <= nxt_state when rising_edge(clk); + + combi : process (reset, nxt_state, cur_state, in_data, in_data_valid, in_data_valid_re, + sync_state, sync_state_flag, out_data_full, readback_cnt, pr_reset) begin + -- default assignments + nxt_state <= cur_state; + icap_enable <= false; + icap_read <= false; + out_data_valid <= '0'; + in_data_rden <= '0'; + readback_cnt_rst <= true; + readback_cnt_en <= false; + -- TODO abort when error or reset + case cur_state is + when ready => + in_data_rden <= '1'; + if in_data_valid_re = '1' then + nxt_state <= write; + end if; + when write => + in_data_rden <= '1'; + if in_data_valid = '1' then + nxt_state <= writing; + icap_enable <= true; + elsif sync_state_flag then + nxt_state <= ready; + end if; + when writing => + in_data_rden <= '1'; + if in_data_valid = '0' then + nxt_state <= write; + icap_enable <= false; + else + icap_enable <= true; + -- a type 1 package with a read op, after sync, but before pr_reset + if in_data(31 downto 27) = "00101" and sync_state = synced and pr_reset = false then + if in_data(17 downto 13) = reg_fdro then -- FDRO read cfg register + nxt_state <= pre_stream_read0; + else + nxt_state <= pre_reg_read0; + end if; + end if; + end if; + when pre_reg_read0 => + in_data_rden <= '1'; + readback_cnt_rst <= false; + icap_enable <= true; + if in_data /= cmd_nop then -- after the nops are done, there should be 00000000 an the stream + nxt_state <= pre_reg_read1; + in_data_rden <= '0'; + end if; + when pre_reg_read1 => + readback_cnt_rst <= false; + icap_read <= true; + if out_data_full = '0' then + nxt_state <= reading; + else + nxt_state <= read; + end if; + when pre_stream_read0 => -- delay for one cycle to get the correct readback counter value + in_data_rden <= '1'; + icap_enable <= true; + nxt_state <= pre_reg_read0; + when read => + readback_cnt_rst <= false; + icap_read <= true; + icap_enable <= false; + if out_data_full = '0' then + nxt_state <= reading; + end if; + when reading => + readback_cnt_rst <= false; + readback_cnt_en <= true; + icap_enable <= true; + icap_read <= true; + out_data_valid <= '1'; + if readback_cnt = 0 then + nxt_state <= post_read; + elsif out_data_full = '1' then + nxt_state <= read; + end if; + when post_read => + in_data_rden <= '1'; + nxt_state <= write; + when others => + + end case; + end process combi; + + -- readback counter process + readback_cnt_p : process(clk) + begin + if rising_edge(clk) then + if readback_cnt_rst then -- load coutner with length from data word + if in_data(31 downto 29) = "001" then -- type 1 package + readback_cnt(10 downto 0) <= unsigned(in_data(10 downto 0)); -- only 11 bit for count + readback_cnt(26 downto 11) <= (others=>'0'); + else -- type 2 package, 27 bit for count + readback_cnt <= unsigned(in_data(26 downto 0)); + end if; + elsif readback_cnt_en then + readback_cnt <= readback_cnt - 1; + end if; + end if; + end process; + + + -- update sync status + sync_p : process(clk) + begin + if rising_edge(clk) then + -- TODO consider status word's dsync bit + if in_data_valid = '1' then + case sync_state is + when none => + pr_reset <= false; + if cur_state = ready then + sync_state_flag <= false; -- reset flag after all data was passed to the icap + end if; + if in_data = sync_s_dummy then + sync_state <= dummy0; + end if; + when dummy0 => + if in_data = sync_s_bus_p_0 then + sync_state <= bus_width0; + elsif in_data /= sync_s_dummy then + sync_state <= none; + end if; + when bus_width0 => + if in_data = sync_s_bus_p_1 then + sync_state <= bus_width1; + else + sync_state <= none; + end if; + when bus_width1 => + if in_data = sync_s_dummy then + sync_state <= dummy1; + else + sync_state <= none; + end if; + when dummy1 => + if in_data = sync_s_sync then + sync_state <= synced; + elsif in_data /= sync_s_dummy then + sync_state <= none; + end if; + when synced => + if in_data = sync_s_regW then + sync_state <= cmdWrite; + end if; + when cmdWrite => + if in_data(4 downto 0) = cmd_reg_wcfg then -- wcfg command, reconfig imminent + pr_reset <= true; + end if; + if in_data = sync_s_dsync then + sync_state <= dsynced; + else + sync_state <= synced; + end if; + when dsynced => + pr_reset <= false; + sync_state <= none; + sync_state_flag <= true; -- set flag + end case; + end if; + end if; + end process; + + in_data_swap <= bit_swap(in_data, 8); + icap_out_swap <= bit_swap(icap_out, 8); + +end arch; + diff --git a/src/xil/reconfig/reconfig_icap_wrapper.vhdl b/src/xil/reconfig/reconfig_icap_wrapper.vhdl new file mode 100644 index 00000000..a8a8b89f --- /dev/null +++ b/src/xil/reconfig/reconfig_icap_wrapper.vhdl @@ -0,0 +1,247 @@ +-- EMACS settings: -*- tab-width: 4; indent-tabs-mode: t -*- +-- vim: tabstop=4:shiftwidth=4:noexpandtab +-- kate: tab-width 4; replace-tabs off; indent-width 4; +-- ============================================================================= +-- Authors: Paul Genssler +-- +-- Entity: Simple ICAP wrapper with a fifo interface and a few status signals +-- +-- Description: +-- ------------------------------------- +-- This module was designed to connect the Xilinx "Internal Configuration Access Port" (ICAP) +-- to a PCIe endpoint on a Dini board. Tested on: +-- +-- tbd +-- +-- License: +-- ============================================================================= +-- Copyright 2007-2016 Technische Universitaet Dresden - Germany, +-- Chair for VLSI-Design, Diagnostics and Architecture +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use ieee.numeric_std.all; + +library UNISIM; +use UNISIM.vcomponents.all; + +library poc; +use poc.utils.all; + +entity reconfig_icap_wrapper is + generic ( + MIN_DEPTH_OUT : positive := 256; + MIN_DEPTH_IN : positive := 256 + ); + port ( + clk : in std_logic; + reset : in std_logic; + clk_icap : in std_logic; -- clock signal for ICAP, max 100 MHz (double check with manual) + + icap_busy : out std_logic; -- the ICAP is processing the data + icap_readback : out std_logic; -- high during a readback + icap_partial_res: out std_logic; -- high during reconfiguration + + -- data in + write_put : in std_logic; + write_full : out std_logic; + write_data : in std_logic_vector(31 downto 0); + write_done : in std_logic; -- high pulse/edge after all data was written + + -- data out + read_got : in std_logic; + read_valid : out std_logic; + read_data : out std_logic_vector(31 downto 0) + ); +end reconfig_icap_wrapper; + +architecture Behavioral of reconfig_icap_wrapper is + signal reset_icap : std_logic; + + signal write_done_d : std_logic; + signal write_done_edge : std_logic; + signal write_done_icapclk : std_logic; + + signal in_data_valid : std_logic; + constant STATE_BITS : positive := 2; + constant state_almost_full : std_logic_vector(STATE_BITS -1 downto 0) := (0 => '0', others => '1'); + signal in_data_fill_state : std_logic_vector(STATE_BITS -1 downto 0); + signal in_data_rden : std_logic; + signal in_data_start : std_logic; -- high after enough data was written into the pci->icap fifo + -- or write done (status register) + signal icap_rden : std_logic; -- icap wants some yummy data + signal in_data : std_logic_vector(31 downto 0); + + signal out_data_full : std_logic; + signal out_data_put : std_logic; + signal out_data : std_logic_vector(31 downto 0); + + signal icap_data_config : std_logic_vector(31 downto 0); + signal icap_data_readback : std_logic_vector(31 downto 0); + signal icap_csb : std_logic; + signal icap_rw : std_logic; + + signal icap_data_config_r : std_logic_vector(31 downto 0); + signal icap_data_readback_r : std_logic_vector(31 downto 0); + signal icap_csb_r : std_logic; + signal icap_rw_r : std_logic; + + signal fsm_status : std_logic_vector(31 downto 0); + signal fsm_status_clk : std_logic_vector(31 downto 0); + signal fsm_ready : std_logic; + signal fsm_ready_d : std_logic; +begin + write_done_d <= write_done when rising_edge(clk); + write_done_edge <= to_sl(write_done = '1' and write_done_d = '0'); + + icap_busy <= not fsm_status_clk(3); + icap_readback <= fsm_status_clk(1); + icap_partial_res <= fsm_status_clk(0); + + fsm_ready <= fsm_status(3); + fsm_ready_d <= fsm_ready when rising_edge(clk_icap); + + -- buffer some data before starting the icap, icap needs to be sync'ed before it can be paused + in_data_buffer_p : process (clk_icap) begin + if rising_edge(clk_icap) then + if (reset_icap = '1') then + in_data_start <= '0'; + else + if fsm_ready = '1' and fsm_ready_d = '0' then -- reset after icap is done + in_data_start <= '0'; + elsif in_data_fill_state = state_almost_full or write_done_icapclk = '1' then -- set when fifo almost full or write already done + in_data_start <= '1'; + end if; + end if; + end if; + end process in_data_buffer_p; + + in_data_rden <= icap_rden and in_data_start and in_data_valid; + + -- sync the written pci data into the user clk + -- writer: pci + -- reader: core + fifo_in : entity poc.fifo_ic_got + generic map( + D_BITS => 32, + MIN_DEPTH => MIN_DEPTH_IN, + OUTPUT_REG => false, + FSTATE_RD_BITS => STATE_BITS + ) + port map( + clk_wr => clk, + rst_wr => reset, + put => write_put, + din => write_data, + full => write_full, + estate_wr => open, + + clk_rd => clk_icap, + rst_rd => reset_icap, + got => in_data_rden, + valid => in_data_valid, + dout => in_data, + fstate_rd => in_data_fill_state + ); + + -- sync data from this core to the pci bus + -- writer: core + -- reader: pci + fifo_out : entity poc.fifo_ic_got + generic map( + D_BITS => 32, + MIN_DEPTH => MIN_DEPTH_OUT, + OUTPUT_REG => false + ) + port map( + clk_wr => clk_icap, + rst_wr => reset_icap, + put => out_data_put, + din => out_data, + full => out_data_full, + + clk_rd => clk, + rst_rd => reset, + got => read_got, + valid => read_valid, + dout => read_data + ); + + icap_fsm_inst: entity poc.reconfig_icap_fsm port map( + clk => clk_icap, + reset => reset_icap, + icap_in => icap_data_config_r, + icap_out => icap_data_readback_r, + icap_csb => icap_csb_r, + icap_rw => icap_rw_r, + in_data => in_data, + in_data_valid => in_data_rden, -- TODO start one clock cycle later + in_data_rden => icap_rden, + out_data => out_data, + out_data_valid => out_data_put, + out_data_full => out_data_full, + status => fsm_status + ); + + -- icap + icap_reg_p : process (clk_icap) begin + if rising_edge(clk_icap) then + icap_data_readback_r <= icap_data_readback; + icap_csb <= icap_csb_r; + icap_rw <= icap_rw_r; + icap_data_config <= icap_data_config_r; + end if; + end process icap_reg_p; + + icap_inst : entity poc.xil_ICAP + port map ( + clk => clk_icap, + disable => icap_csb, + busy => open, + data_in => icap_data_config, + data_out => icap_data_readback, + rd_wr => icap_rw + ); + + strobe_sync : entity poc.sync_Strobe + port map ( + clock1 => clk, + clock2 => clk_icap, + input(0) => write_done_edge, + output(0) => write_done_icapclk, + busy => open + ); + + reset_sync : entity poc.sync_Bits + port map ( + clock => clk_icap, + input(0) => reset, + output(0) => reset_icap + ); + + fsm_status_sync : entity poc.sync_vector + generic map ( + master_bits => 32 + ) port map ( + clock1 => clk_icap, + clock2 => clk, + input => fsm_status, + output => fsm_status_clk, + busy => open, + changed => open + ); + + +end Behavioral; diff --git a/src/xil/xil.pkg.vhdl b/src/xil/xil.pkg.vhdl index 9415806a..dc0368fd 100644 --- a/src/xil/xil.pkg.vhdl +++ b/src/xil/xil.pkg.vhdl @@ -1,15 +1,14 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: VHDL package for component declarations, types and functions +-- Entity: VHDL package for component declarations, types and functions -- associated to the PoC.xil namespace -- -- Description: --- ------------------------------------ +-- ------------------------------------- -- This package declares types and components for -- - Xilinx ChipScope Pro IPCores (ICON, ILA, VIO) -- - Xilinx Dynamic Reconfiguration Port (DRP) related types @@ -18,7 +17,7 @@ -- - Component declarations for Xilinx related modules -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -33,7 +32,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -47,21 +46,21 @@ use PoC.vectors.all; package xil is -- ChipScope -- ========================================================================== - subtype T_XIL_CHIPSCOPE_CONTROL is STD_LOGIC_VECTOR(35 downto 0); - type T_XIL_CHIPSCOPE_CONTROL_VECTOR is array (NATURAL range <>) of T_XIL_CHIPSCOPE_CONTROL; + subtype T_XIL_CHIPSCOPE_CONTROL is std_logic_vector(35 downto 0); + type T_XIL_CHIPSCOPE_CONTROL_VECTOR is array (natural range <>) of T_XIL_CHIPSCOPE_CONTROL; -- Dynamic Reconfiguration Port (DRP) -- ========================================================================== subtype T_XIL_DRP_ADDRESS is T_SLV_16; subtype T_XIL_DRP_DATA is T_SLV_16; - type T_XIL_DRP_ADDRESS_VECTOR is array (NATURAL range <>) of T_XIL_DRP_ADDRESS; - type T_XIL_DRP_DATA_VECTOR is array (NATURAL range <>) of T_XIL_DRP_DATA; + type T_XIL_DRP_ADDRESS_VECTOR is array (natural range <>) of T_XIL_DRP_ADDRESS; + type T_XIL_DRP_DATA_VECTOR is array (natural range <>) of T_XIL_DRP_DATA; type T_XIL_DRP_BUS_IN is record - Clock : STD_LOGIC; - Enable : STD_LOGIC; - ReadWrite : STD_LOGIC; + Clock : std_logic; + Enable : std_logic; + ReadWrite : std_logic; Address : T_XIL_DRP_ADDRESS; Data : T_XIL_DRP_DATA; end record; @@ -75,9 +74,13 @@ package xil is type T_XIL_DRP_BUS_OUT is record Data : T_XIL_DRP_DATA; - Ack : STD_LOGIC; + Ack : std_logic; end record; + constant C_XIL_DRP_BUS_OUT_EMPTY : T_XIL_DRP_BUS_OUT := ( + Ack => '0', + Data => (others => '0')); + type T_XIL_DRP_CONFIG is record Address : T_XIL_DRP_ADDRESS; Mask : T_XIL_DRP_DATA; @@ -85,17 +88,17 @@ package xil is end record; -- define array indices - constant C_XIL_DRP_MAX_CONFIG_COUNT : POSITIVE := 8; + constant C_XIL_DRP_MAX_CONFIG_COUNT : positive := 8; - SUBtype T_XIL_DRP_CONFIG_INDEX IS INTEGER range 0 TO C_XIL_DRP_MAX_CONFIG_COUNT - 1; - type T_XIL_DRP_CONFIG_VECTOR is array (NATURAL range <>) of T_XIL_DRP_CONFIG; + subtype T_XIL_DRP_CONFIG_INDEX is integer range 0 to C_XIL_DRP_MAX_CONFIG_COUNT - 1; + type T_XIL_DRP_CONFIG_VECTOR is array (natural range <>) of T_XIL_DRP_CONFIG; type T_XIL_DRP_CONFIG_SET is record Configs : T_XIL_DRP_CONFIG_VECTOR(T_XIL_DRP_CONFIG_INDEX); LastIndex : T_XIL_DRP_CONFIG_INDEX; end record; - type T_XIL_DRP_CONFIG_ROM is array (NATURAL range <>) of T_XIL_DRP_CONFIG_SET; + type T_XIL_DRP_CONFIG_ROM is array (natural range <>) of T_XIL_DRP_CONFIG_SET; constant C_XIL_DRP_CONFIG_EMPTY : T_XIL_DRP_CONFIG := ( Address => (others => '0'), @@ -110,7 +113,7 @@ package xil is component xil_ChipScopeICON is generic ( - PORTS : POSITIVE + PORTS : positive ); port ( ControlBus : inout T_XIL_CHIPSCOPE_CONTROL_VECTOR(PORTS - 1 downto 0) @@ -119,25 +122,25 @@ package xil is component xil_SystemMonitor_Virtex6 is port ( - Reset : in STD_LOGIC; -- Reset signal for the System Monitor control logic + Reset : in std_logic; -- Reset signal for the System Monitor control logic - Alarm_UserTemp : out STD_LOGIC; -- Temperature-sensor alarm output - Alarm_OverTemp : out STD_LOGIC; -- Over-Temperature alarm output - Alarm : out STD_LOGIC; -- OR'ed output of all the alarms - VP : in STD_LOGIC; -- Dedicated analog input pair - VN : in STD_LOGIC + Alarm_UserTemp : out std_logic; -- Temperature-sensor alarm output + Alarm_OverTemp : out std_logic; -- Over-Temperature alarm output + Alarm : out std_logic; -- OR'ed output of all the alarms + VP : in std_logic; -- Dedicated analog input pair + VN : in std_logic ); end component; component xil_SystemMonitor_Series7 is port ( - Reset : in STD_LOGIC; -- Reset signal for the System Monitor control logic + Reset : in std_logic; -- Reset signal for the System Monitor control logic - Alarm_UserTemp : out STD_LOGIC; -- Temperature-sensor alarm output - Alarm_OverTemp : out STD_LOGIC; -- Over-Temperature alarm output - Alarm : out STD_LOGIC; -- OR'ed output of all the alarms - VP : in STD_LOGIC; -- Dedicated analog input pair - VN : in STD_LOGIC + Alarm_UserTemp : out std_logic; -- Temperature-sensor alarm output + Alarm_OverTemp : out std_logic; -- Over-Temperature alarm output + Alarm : out std_logic; -- OR'ed output of all the alarms + VP : in std_logic; -- Dedicated analog input pair + VN : in std_logic ); end component; diff --git a/src/xil/xil_BSCAN.vhdl b/src/xil/xil_BSCAN.vhdl index 994b9b44..8ccf5753 100644 --- a/src/xil/xil_BSCAN.vhdl +++ b/src/xil/xil_BSCAN.vhdl @@ -1,24 +1,23 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: JTAG / Boundary Scan wrapper +-- Entity: JTAG / Boundary Scan wrapper -- -- Description: --- ------------------------------------ --- This module wraps Xilinx "Boundary Scan" (JTAG) primitives in a generic module. --- Supported devices: --- - Spartan-3, Spartan-6 --- - Virtex-5, Virtex-6 --- - Series-7 --- +-- ------------------------------------- +-- This module wraps Xilinx "Boundary Scan" (JTAG) primitives in a generic +-- module. |br| +-- Supported devices are: +-- * Spartan-3, Spartan-6 +-- * Virtex-5, Virtex-6 +-- * Series-7 (Artix-7, Kintex-7, Virtex-7, Zynq-7000) -- -- License: --- ============================================================================ --- Copyright 2007-2015 Technische Universitaet Dresden - Germany, +-- ============================================================================= +-- Copyright 2007-2016 Technische Universitaet Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); @@ -32,11 +31,11 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; library UniSim; use UniSim.vComponents.all; @@ -47,32 +46,32 @@ use PoC.config.all; entity xil_BSCAN is generic ( - JTAG_CHAIN : NATURAL; - DISABLE_JTAG : BOOLEAN := FALSE + JTAG_CHAIN : natural; + DISABLE_JTAG : boolean := FALSE ); port ( - Reset : out STD_LOGIC; - RunTest : out STD_LOGIC; - Sel : out STD_LOGIC; - Capture : out STD_LOGIC; - drck : out STD_LOGIC; - Shift : out STD_LOGIC; - Test_Clock : out STD_LOGIC; - Test_DataIn : out STD_LOGIC; - Test_DataOut : in STD_LOGIC; - Test_ModeSelect : out STD_LOGIC; - Update : out STD_LOGIC + Reset : out std_logic; + RunTest : out std_logic; + Sel : out std_logic; + Capture : out std_logic; + drck : out std_logic; + Shift : out std_logic; + Test_Clock : out std_logic; + Test_DataIn : out std_logic; + Test_DataOut : in std_logic; + Test_ModeSelect : out std_logic; + Update : out std_logic ); -end; +end entity; architecture rtl of xil_BSCAN is constant DEV_INFO : T_DEVICE_INFO := DEVICE_INFO; begin genSpartan3 : if (DEV_INFO.Device = DEVICE_SPARTAN3) generate - signal drck_i : STD_LOGIC_VECTOR(1 downto 0); - signal sel_i : STD_LOGIC_VECTOR(1 downto 0); - signal tdo_i : STD_LOGIC_VECTOR(1 downto 0); + signal drck_i : std_logic_vector(1 downto 0); + signal sel_i : std_logic_vector(1 downto 0); + signal tdo_i : std_logic_vector(1 downto 0); begin drck <= drck_i(JTAG_CHAIN - 1); Sel <= sel_i(JTAG_CHAIN - 1); @@ -160,7 +159,7 @@ begin bscan : BSCANE2 generic map ( JTAG_CHAIN => JTAG_CHAIN, - DISABLE_JTAG => BOOLEAN'image(DISABLE_JTAG) + DISABLE_JTAG => boolean'image(DISABLE_JTAG) ) port map ( CAPTURE => Capture, @@ -176,4 +175,4 @@ begin TDO => Test_DataOut ); end generate; - end; +end architecture; diff --git a/src/xil/xil_ChipScopeICON.vhdl b/src/xil/xil_ChipScopeICON.vhdl index c834baa9..999665ac 100644 --- a/src/xil/xil_ChipScopeICON.vhdl +++ b/src/xil/xil_ChipScopeICON.vhdl @@ -1,32 +1,35 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: Generic Xilinx ChipScope ICON wrapper +-- Entity: Generic Xilinx ChipScope ICON wrapper -- -- Description: --- ------------------------------------ --- This module wraps 15 ChipScope ICON IPCore netlists generated from ChipScope --- ICON xco files. The generic parameter PORTS selects the apropriate ICON --- instance with 1 to 15 ICON ControlBus ports. Each ControlBus port is of type --- T_XIL_CHIPSCOPE_CONTROL and of mode 'inout'. +-- ------------------------------------- +-- This module wraps 15 ChipScope ICON IP core netlists generated from ChipScope +-- ICON xco files. The generic parameter ``PORTS`` selects the apropriate ICON +-- instance with 1 to 15 ICON ``ControlBus`` ports. Each ``ControlBus`` port is +-- of type ``T_XIL_CHIPSCOPE_CONTROL`` and of mode ``inout``. +-- +-- .. rubric:: Compile required CoreGenerator IP Cores to Netlists with PoC +-- +-- Please use the provided Xilinx ISE compile command ``ise`` in PoC to recreate +-- the needed source and netlist files on your local machine. +-- +-- .. code-block:: PowerShell -- --- PoC IPCore compiler: --- ------------------------------------ --- Please use the provided PoC netlist compiler tool to recreate the needed source --- and netlist files on your computer. +-- cd PoCRoot +-- .\poc.ps1 ise PoC.xil.ChipScopeICON --board=KC705 -- --- cd \netlist --- .\netlist.ps1 -rl --coregen PoC.xil.ChipScopeICON_1 --board KC705 --- [...] --- .\netlist.ps1 -rl --coregen PoC.xil.ChipScopeICON_15 --board KC705 +-- SeeAlso: +-- :doc:`Using PoC -> Synthesis ` +-- For how to run synthesis with PoC and CoreGenerator. -- -- License: --- ============================================================================ --- Copyright 2007-2015 Technische Universitaet Dresden - Germany +-- ============================================================================= +-- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); @@ -40,7 +43,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; @@ -52,7 +55,7 @@ use PoC.xil.all; entity xil_ChipScopeICON is generic ( - PORTS : POSITIVE + PORTS : positive ); port ( ControlBus : inout T_XIL_CHIPSCOPE_CONTROL_VECTOR(PORTS - 1 downto 0) @@ -64,14 +67,14 @@ architecture rtl of xil_ChipScopeICON is begin assert (PORTS < 16) report "To many ICON CONTROL ports." severity failure; - genICON1 : if (PORTS = 1) generate + genICON1 : if PORTS = 1 generate ICON : entity PoC.xil_ChipScopeICON_1 port map ( CONTROL0 => ControlBus(0) ); end generate; - genICON2 : if (PORTS = 2) generate + genICON2 : if PORTS = 2 generate ICON : entity PoC.xil_ChipScopeICON_2 port map ( CONTROL0 => ControlBus(0), @@ -79,7 +82,7 @@ begin ); end generate; - genICON3 : if (PORTS = 3) generate + genICON3 : if PORTS = 3 generate ICON : entity PoC.xil_ChipScopeICON_3 port map ( CONTROL0 => ControlBus(0), @@ -88,7 +91,7 @@ begin ); end generate; - genICON4 : if (PORTS = 4) generate + genICON4 : if PORTS = 4 generate ICON : entity PoC.xil_ChipScopeICON_4 port map ( CONTROL0 => ControlBus(0), @@ -98,7 +101,7 @@ begin ); end generate; - genICON5 : if (PORTS = 5) generate + genICON5 : if PORTS = 5 generate ICON : entity PoC.xil_ChipScopeICON_5 port map ( CONTROL0 => ControlBus(0), @@ -109,7 +112,7 @@ begin ); end generate; - genICON6 : if (PORTS = 6) generate + genICON6 : if PORTS = 6 generate ICON : entity PoC.xil_ChipScopeICON_6 port map ( CONTROL0 => ControlBus(0), @@ -121,7 +124,7 @@ begin ); end generate; - genICON7 : if (PORTS = 7) generate + genICON7 : if PORTS = 7 generate ICON : entity PoC.xil_ChipScopeICON_7 port map ( CONTROL0 => ControlBus(0), @@ -134,7 +137,7 @@ begin ); end generate; - genICON8 : if (PORTS = 8) generate + genICON8 : if PORTS = 8 generate ICON : entity PoC.xil_ChipScopeICON_8 port map ( CONTROL0 => ControlBus(0), @@ -148,7 +151,7 @@ begin ); end generate; - genICON9 : if (PORTS = 9) generate + genICON9 : if PORTS = 9 generate ICON : entity PoC.xil_ChipScopeICON_9 port map ( CONTROL0 => ControlBus(0), @@ -163,7 +166,7 @@ begin ); end generate; - genICON10 : if (PORTS = 10) generate + genICON10 : if PORTS = 10 generate ICON : entity PoC.xil_ChipScopeICON_10 port map ( CONTROL0 => ControlBus(0), @@ -179,7 +182,7 @@ begin ); end generate; - genICON11 : if (PORTS = 11) generate + genICON11 : if PORTS = 11 generate ICON : entity PoC.xil_ChipScopeICON_11 port map ( CONTROL0 => ControlBus(0), @@ -196,7 +199,7 @@ begin ); end generate; - genICON12 : if (PORTS = 12) generate + genICON12 : if PORTS = 12 generate ICON : entity PoC.xil_ChipScopeICON_12 port map ( CONTROL0 => ControlBus(0), @@ -214,7 +217,7 @@ begin ); end generate; - genICON13 : if (PORTS = 13) generate + genICON13 : if PORTS = 13 generate ICON : entity PoC.xil_ChipScopeICON_13 port map ( CONTROL0 => ControlBus(0), @@ -233,7 +236,7 @@ begin ); end generate; - genICON14 : if (PORTS = 14) generate + genICON14 : if PORTS = 14 generate ICON : entity PoC.xil_ChipScopeICON_14 port map ( CONTROL0 => ControlBus(0), @@ -253,7 +256,7 @@ begin ); end generate; - genICON15 : if (PORTS = 15) generate + genICON15 : if PORTS = 15 generate ICON : entity PoC.xil_ChipScopeICON_15 port map ( CONTROL0 => ControlBus(0), diff --git a/src/xil/xil_ICAP.files b/src/xil/xil_ICAP.files new file mode 100644 index 00000000..c2e22954 --- /dev/null +++ b/src/xil/xil_ICAP.files @@ -0,0 +1,15 @@ +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# ============================================================================== +# Note: all files are relative to PoC root directory +# +# Common PoC packages for configuration, synthesis and simulation +include "src/common/common.files" # load common packages + +# PoC.xil +if (Vendor = "Xilinx") then + vhdl PoC "src/xil/xil_ICAP.vhdl" # Top-Level +else + report "These modules are for Xilinx only." +end if diff --git a/src/xil/xil_ICAP.vhdl b/src/xil/xil_ICAP.vhdl new file mode 100644 index 00000000..5ee6828a --- /dev/null +++ b/src/xil/xil_ICAP.vhdl @@ -0,0 +1,159 @@ +-- EMACS settings: -*- tab-width: 4; indent-tabs-mode: t -*- +-- vim: tabstop=4:shiftwidth=4:noexpandtab +-- kate: tab-width 4; replace-tabs off; indent-width 4; +-- ============================================================================= +-- Authors: Paul Genssler +-- +-- Entity: ICAP Wrapper +-- +-- Description: +-- ------------------------------------- +-- This module wraps Xilinx "Internal Configuration Access Port" (ICAP) primitives in a generic +-- module. |br| +-- Supported devices are: +-- * Spartan-6 +-- * Virtex-4, Virtex-5, Virtex-6 +-- * Series-7 (Artix-7, Kintex-7, Virtex-7, Zynq-7000) +-- +-- License: +-- ============================================================================= +-- Copyright 2007-2016 Technische Universitaet Dresden - Germany, +-- Chair for VLSI-Design, Diagnostics and Architecture +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +library UniSim; +use UniSim.vComponents.all; + +library PoC; +use PoC.config.all; + + +entity xil_ICAP is + generic ( + ICAP_WIDTH : string := "X32"; -- Specifies the input and output data width to be used + -- Spartan 6: fixed to 16 bit + -- Virtex 4: X8 or X32 + -- Rest: X8, X16, X32 + DEVICE_ID : bit_vector := X"1234567"; -- pre-programmed Device ID value for simulation + -- supported by Spartan 6, Virtex 6 and above + SIM_CFG_FILE_NAME : string := "NONE" -- Raw Bitstream (RBT) file to be parsed by the simulation model + -- supported by Spartan 6, Virtex 6 and above + ); + port ( + clk : in std_logic; -- up to 100 MHz (Virtex-6 and above, Virtex-5??) + disable : in std_logic; -- low active enable -> high active disable + rd_wr : in std_logic; -- 0 - write, 1 - read + busy : out std_logic; -- on Series-7 devices always '0' + data_in : in std_logic_vector(31 downto 0); -- on Spartan-6 only 15 downto 0 + data_out : out std_logic_vector(31 downto 0) -- on Spartan-6 only 15 downto 0 + ); +end entity; + + +architecture rtl of xil_ICAP is + constant DEV_INFO : T_DEVICE_INFO := DEVICE_INFO; +begin + + genSpartan6 : if (DEV_INFO.Device = DEVICE_SPARTAN6) generate + begin + icap : ICAP_SPARTAN6 + generic map ( + DEVICE_ID => DEVICE_ID, + SIM_CFG_FILE_NAME => SIM_CFG_FILE_NAME + ) + port map ( + BUSY => busy, -- 1-bit output: Busy/Ready output + O => data_out(15 downto 0), -- 16-bit output: Configuartion data output bus + CE => disable, -- 1-bit input: Active-Low ICAP Enable input + CLK => clk, -- 1-bit input: Clock input + I => data_in(15 downto 0), -- 16-bit input: Configuration data input bus + WRITE => rd_wr -- 1-bit input: Read/Write control input + ); + end generate; + + genVirtex4 : if (DEV_INFO.Device = DEVICE_VIRTEX4) generate + signal ce : std_logic; + begin + ce <= not disable; + icap : ICAP_VIRTEX4 + generic map ( + ICAP_WIDTH => ICAP_WIDTH) -- "X8" or "X32" + port map ( + BUSY => busy, -- Busy output + O => data_out, -- 32-bit data output + CE => ce, -- Clock enable input + CLK => clk, -- Clock input + I => data_in, -- 32-bit data input + WRITE => rd_wr -- Write input + ); + end generate; + + genVirtex5 : if (DEV_INFO.Device = DEVICE_VIRTEX5) generate + signal ce : std_logic; + begin + ce <= not disable; + icap : ICAP_VIRTEX5 + generic map ( + ICAP_WIDTH => ICAP_WIDTH) + port map ( + BUSY => busy, -- Busy output + O => data_out, -- 32-bit data output + CE => ce, -- Clock enable input + CLK => clk, -- Clock input + I => data_in, -- 32-bit data input + WRITE => rd_wr -- Write input + ); + end generate; + + genVirtex6 : if (DEV_INFO.Device = DEVICE_VIRTEX6) generate + begin + icap : ICAP_VIRTEX6 + generic map ( + DEVICE_ID => DEVICE_ID, + ICAP_WIDTH => ICAP_WIDTH, + SIM_CFG_FILE_NAME => SIM_CFG_FILE_NAME + ) + port map ( + BUSY => busy, -- 1-bit output: Busy/Ready output + O => data_out, -- 32-bit output: Configuration data output bus + CLK => clk, -- 1-bit input: Clock Input + CSB => disable, -- 1-bit input: Active-Low ICAP input Enable + I => data_in, -- 32-bit input: Configuration data input bus + RDWRB => rd_wr -- 1-bit input: Read/Write Select input + ); + end generate; + + genSeries7 : if (DEV_INFO.DevSeries = DEVICE_SERIES_7_SERIES) generate + begin + icap : ICAPE2 + generic map ( + DEVICE_ID => X"0" & DEVICE_ID, + ICAP_WIDTH => ICAP_WIDTH, + SIM_CFG_FILE_NAME => SIM_CFG_FILE_NAME + ) + port map ( + O => data_out, -- 32-bit output: Configuration data output bus + CLK => clk, -- 1-bit input: Clock Input + CSIB => disable, -- 1-bit input: Active-Low ICAP Enable + I => data_in, -- 32-bit input: Configuration data input bus + RDWRB => rd_wr -- 1-bit input: Read/Write Select input + ); + busy <= '0'; + end generate; +end architecture; diff --git a/src/xil/xil_Reconfigurator.vhdl b/src/xil/xil_Reconfigurator.vhdl index 05c2da34..ad6dc57e 100644 --- a/src/xil/xil_Reconfigurator.vhdl +++ b/src/xil/xil_Reconfigurator.vhdl @@ -1,26 +1,26 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: Reconfiguration engine for DRP enabled Xilinx primtives +-- Entity: Reconfiguration engine for DRP enabled Xilinx primtives -- -- Description: --- ------------------------------------ --- Many complex primitives in a Xilinx device offer a Dynamic Reconfiguration --- Port (DRP) to reconfigure the primitive at runtime without reconfiguring then --- whole FPGA. --- This module is a DRP master that can be preconfigured at compile time with --- different configuration sets. The configuration sets are mapped into a ROM. --- The user can select a stored configuration with 'ConfigSelect' and sending a --- strobe to 'Reconfig'. The Operation completes with an other strobe on --- 'ReconfigDone'. +-- ------------------------------------- +-- Many complex primitives in a Xilinx device offer a Dynamic Reconfiguration +-- Port (DRP) to reconfigure a primitive at runtime without reconfiguring the +-- whole FPGA. +-- +-- This module is a DRP master that can be pre-configured at compile time with +-- different configuration sets. The configuration sets are mapped into a ROM. +-- The user can select a stored configuration with ``ConfigSelect``. Sending a +-- strobe to ``Reconfig`` will start the reconfiguration process. The operation +-- completes with another strobe on ``ReconfigDone``. -- -- License: --- ============================================================================ --- Copyright 2007-2015 Technische Universitaet Dresden - Germany +-- ============================================================================= +-- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); @@ -34,7 +34,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -50,32 +50,32 @@ use PoC.xil.all; entity xil_Reconfigurator is generic ( - DEBUG : BOOLEAN := FALSE; -- + DEBUG : boolean := FALSE; -- CLOCK_FREQ : FREQ := 100 MHz; -- CONFIG_ROM : in T_XIL_DRP_CONFIG_ROM := (0 downto 0 => C_XIL_DRP_CONFIG_SET_EMPTY) -- ); port ( - Clock : in STD_LOGIC; - Reset : in STD_LOGIC; + Clock : in std_logic; + Reset : in std_logic; - Reconfig : in STD_LOGIC; -- - ReconfigDone : out STD_LOGIC; -- - ConfigSelect : in STD_LOGIC_VECTOR(log2ceilnz(CONFIG_ROM'length) - 1 downto 0); -- + Reconfig : in std_logic; -- + ReconfigDone : out std_logic; -- + ConfigSelect : in std_logic_vector(log2ceilnz(CONFIG_ROM'length) - 1 downto 0); -- - DRP_en : out STD_LOGIC; -- + DRP_en : out std_logic; -- DRP_Address : out T_XIL_DRP_ADDRESS; -- - DRP_we : out STD_LOGIC; -- + DRP_we : out std_logic; -- DRP_DataIn : in T_XIL_DRP_DATA; -- DRP_DataOut : out T_XIL_DRP_DATA; -- - DRP_Ack : in STD_LOGIC -- + DRP_Ack : in std_logic -- ); -end; +end entity; architecture rtl of xil_Reconfigurator is - attribute KEEP : BOOLEAN; - attribute FSM_ENCODING : STRING; - attribute signal_ENCODING : STRING; + attribute KEEP : boolean; + attribute FSM_ENCODING : string; + attribute signal_ENCODING : string; type T_STATE is ( ST_IDLE, @@ -89,29 +89,31 @@ architecture rtl of xil_Reconfigurator is signal NextState : T_STATE; attribute FSM_ENCODING of State : signal is ite(DEBUG, "gray", "speed1"); - signal DataBuffer_en : STD_LOGIC; + signal DataBuffer_en : std_logic; signal DataBuffer_d : T_XIL_DRP_DATA := (others => '0'); signal ROM_Entry : T_XIL_DRP_CONFIG; - signal ROM_LastConfigWord : STD_LOGIC; + signal ROM_LastConfigWord : std_logic; + + signal ConfigSelect_d : std_logic_vector(ConfigSelect'range); - constant CONFIGINDEX_BITS : POSITIVE := log2ceilnz(CONFIG_ROM'length); - signal ConfigIndex_rst : STD_LOGIC; - signal ConfigIndex_en : STD_LOGIC; - signal ConfigIndex_us : UNSIGNED(CONFIGINDEX_BITS - 1 downto 0); + constant CONFIGINDEX_BITS : positive := log2ceilnz(CONFIG_ROM'length); + signal ConfigIndex_rst : std_logic; + signal ConfigIndex_en : std_logic; + signal ConfigIndex_us : unsigned(CONFIGINDEX_BITS - 1 downto 0); - attribute KEEP OF ROM_LastConfigWord : signal IS DEBUG; + attribute KEEP of ROM_LastConfigWord : signal is DEBUG; begin -- configuration ROM blkCONFIG_ROM : block - signal SetIndex : inTEGER range 0 to CONFIG_ROM'high; + signal SetIndex : integer range 0 to CONFIG_ROM'high; signal RowIndex : T_XIL_DRP_CONFIG_INDEX; - attribute KEEP OF SetIndex : signal IS DEBUG; - attribute KEEP OF RowIndex : signal IS DEBUG; + attribute KEEP of SetIndex : signal is DEBUG; + attribute KEEP of RowIndex : signal is DEBUG; begin - SetIndex <= to_index(ConfigSelect, CONFIG_ROM'high); + SetIndex <= to_index(ConfigSelect_d, CONFIG_ROM'high); RowIndex <= to_index(ConfigIndex_us, T_XIL_DRP_CONFIG_INDEX'high); ROM_Entry <= CONFIG_ROM(SetIndex).Configs(RowIndex); ROM_LastConfigWord <= to_sl(RowIndex = CONFIG_ROM(SetIndex).LastIndex); @@ -121,12 +123,11 @@ begin process(Clock) begin if rising_edge(Clock) then - if ((Reset or ConfigIndex_rst) = '1') then - ConfigIndex_us <= (others => '0'); - else - if (ConfigIndex_en = '1') then - ConfigIndex_us <= ConfigIndex_us + 1; - end if; + if (ConfigIndex_rst = '1') then + ConfigIndex_us <= (others => '0'); + ConfigSelect_d <= ConfigSelect; + elsif (ConfigIndex_en = '1') then + ConfigIndex_us <= ConfigIndex_us + 1; end if; end if; end process; @@ -136,12 +137,10 @@ begin begin if rising_edge(Clock) then if (Reset = '1') then - DataBuffer_d <= (others => '0'); - else - if (DataBuffer_en = '1') then - DataBuffer_d <= ((DRP_DataIn and not ROM_Entry.Mask) or - (ROM_Entry.Data and ROM_Entry.Mask)); - end if; + DataBuffer_d <= (others => '0'); + elsif (DataBuffer_en = '1') then + DataBuffer_d <= ((DRP_DataIn and not ROM_Entry.Mask) or + (ROM_Entry.Data and ROM_Entry.Mask)); end if; end if; end process; @@ -180,44 +179,40 @@ begin case State is when ST_IDLE => if (Reconfig = '1') then - ConfigIndex_rst <= '1'; - - NextState <= ST_READ_BEGIN; + ConfigIndex_rst <= '1'; + NextState <= ST_READ_BEGIN; end if; when ST_READ_BEGIN => - DRP_en <= '1'; - DRP_we <= '0'; - - NextState <= ST_READ_WAIT; + DRP_en <= '1'; + DRP_we <= '0'; + NextState <= ST_READ_WAIT; when ST_READ_WAIT => if (DRP_Ack = '1') then - DataBuffer_en <= '1'; - - NextState <= ST_WRITE_BEGIN; + DataBuffer_en <= '1'; + NextState <= ST_WRITE_BEGIN; end if; when ST_WRITE_BEGIN => - DRP_en <= '1'; - DRP_we <= '1'; - - NextState <= ST_WRITE_WAIT; + DRP_en <= '1'; + DRP_we <= '1'; + NextState <= ST_WRITE_WAIT; when ST_WRITE_WAIT => if (DRP_Ack = '1') then if (ROM_LastConfigWord = '1') then - NextState <= ST_DONE; - ELSE - ConfigIndex_en <= '1'; - NextState <= ST_READ_BEGIN; + NextState <= ST_DONE; + else + ConfigIndex_en <= '1'; + NextState <= ST_READ_BEGIN; end if; end if; when ST_DONE => - ReconfigDone <= '1'; - NextState <= ST_IDLE; + ReconfigDone <= '1'; + NextState <= ST_IDLE; end case; end process; -end; +end architecture; diff --git a/src/xil/xil_SystemMonitor_Series7.vhdl b/src/xil/xil_SystemMonitor_Series7.vhdl index 1d5e6477..43c4b8cd 100644 --- a/src/xil/xil_SystemMonitor_Series7.vhdl +++ b/src/xil/xil_SystemMonitor_Series7.vhdl @@ -1,35 +1,34 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: XADC wrapper for temperature supervision applications +-- Entity: XADC wrapper for temperature supervision applications -- -- Description: --- ------------------------------------ --- This module wraps a Series-7 XADC to report if preconfigured temperature values --- are overrun. The XADC was formerly known as "System Monitor". +-- ------------------------------------- +-- This module wraps a Series-7 XADC to report if preconfigured temperature values +-- are overrun. The XADC was formerly known as "System Monitor". -- --- Temperature curve: --- ------------------ +-- .. rubric:: Temperature Curve -- --- | /-----\ --- Temp_ov on=80 | - - - - - - /-------/ \ --- | / | \ --- Temp_ov off=60 | - - - - - / - - - - | - - - - \----\ --- | / | \ --- | / | | \ --- Temp_us on=35 | - /---/ | | \ --- Temp_us off=30 | - / - -|- - - - - - | - - - - - - -|- \------\ --- | / | | | \ --- ----------------|--------|------------|--------------|----------|--------- --- pwm = | min | medium | max | medium | min +-- .. code-block:: none -- +-- | /-----\ +-- Temp_ov on=80 | - - - - - - /-------/ \ +-- | / | \ +-- Temp_ov off=60 | - - - - - / - - - - | - - - - \----\ +-- | / | |\ +-- | / | | \ +-- Temp_us on=35 | - /---/ | | \ +-- Temp_us off=30 | - / - -|- - - - - - |- - - - - - - |- -\------\ +-- | / | | | \ +-- ----------------|--------|------------|--------------|-----------|-------- +-- pwm = | min | medium | max | medium | min -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -44,7 +43,7 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; @@ -56,25 +55,25 @@ use UniSim.vComponents.all; entity xil_SystemMonitor_Series7 is port ( - Reset : in STD_LOGIC; -- Reset signal for the System Monitor control logic + Reset : in std_logic; -- Reset signal for the System Monitor control logic - Alarm_UserTemp : out STD_LOGIC; -- Temperature-sensor alarm output - Alarm_OverTemp : out STD_LOGIC; -- Over-Temperature alarm output - Alarm : out STD_LOGIC; -- OR'ed output of all the Alarms - VP : in STD_LOGIC; -- Dedicated Analog Input Pair - VN : in STD_LOGIC + Alarm_UserTemp : out std_logic; -- Temperature-sensor alarm output + Alarm_OverTemp : out std_logic; -- Over-Temperature alarm output + Alarm : out std_logic; -- OR'ed output of all the Alarms + VP : in std_logic; -- Dedicated Analog Input Pair + VN : in std_logic ); -end; +end entity; -architecture xilinx of xil_SystemMonitor_Series7 IS - SIGNAL FLOAT_VCCAUX_ALARM : STD_LOGIC; - SIGNAL FLOAT_VCCINT_ALARM : STD_LOGIC; - SIGNAL FLOAT_VBRAM_ALARM : STD_LOGIC; - SIGNAL FLOAT_MUXADDR : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL aux_channel_p : STD_LOGIC_VECTOR(15 DOWNTO 0); - SIGNAL aux_channel_n : STD_LOGIC_VECTOR(15 DOWNTO 0); - SIGNAL XADC_Alarm : STD_LOGIC_VECTOR(7 DOWNTO 0); +architecture xilinx of xil_SystemMonitor_Series7 is + signal FLOAT_VCCAUX_ALARM : std_logic; + signal FLOAT_VCCINT_ALARM : std_logic; + signal FLOAT_VBRAM_ALARM : std_logic; + signal FLOAT_MUXADDR : std_logic_vector(4 downto 0); + signal aux_channel_p : std_logic_vector(15 downto 0); + signal aux_channel_n : std_logic_vector(15 downto 0); + signal XADC_Alarm : std_logic_vector(7 downto 0); begin diff --git a/src/xil/xil_SystemMonitor_Virtex6.vhdl b/src/xil/xil_SystemMonitor_Virtex6.vhdl index 806d9f79..a482932e 100644 --- a/src/xil/xil_SystemMonitor_Virtex6.vhdl +++ b/src/xil/xil_SystemMonitor_Virtex6.vhdl @@ -1,35 +1,34 @@ -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ +-- ============================================================================= -- Authors: Patrick Lehmann -- --- Module: System Monitor wrapper for temperature supervision applications +-- Entity: System Monitor wrapper for temperature supervision applications -- -- Description: --- ------------------------------------ --- This module wraps a Virtex-6 System Monitor primitive to report if preconfigured --- temperature values are overrun. +-- ------------------------------------- +-- This module wraps a Virtex-6 System Monitor primitive to report if preconfigured +-- temperature values are overrun. -- --- Temperature curve: --- ------------------ +-- .. rubric:: Temperature Curve -- --- | /-----\ --- Temp_ov on=80 | - - - - - - /-------/ \ --- | / | \ --- Temp_ov off=60 | - - - - - / - - - - | - - - - \----\ --- | / | \ --- | / | | \ --- Temp_us on=35 | - /---/ | | \ --- Temp_us off=30 | - / - -|- - - - - - | - - - - - - -|- \------\ --- | / | | | \ --- ----------------|--------|------------|--------------|----------|--------- --- pwm = | min | medium | max | medium | min +-- .. code-block:: none -- +-- | /-----\ +-- Temp_ov on=80 | - - - - - - /-------/ \ +-- | / | \ +-- Temp_ov off=60 | - - - - - / - - - - | - - - - \----\ +-- | / | |\ +-- | / | | \ +-- Temp_us on=35 | - /---/ | | \ +-- Temp_us off=30 | - / - -|- - - - - - |- - - - - - - |- -\------\ +-- | / | | | \ +-- ----------------|--------|------------|--------------|-----------|-------- +-- pwm = | min | medium | max | medium | min -- -- License: --- ============================================================================ +-- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- @@ -44,37 +43,37 @@ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. --- ============================================================================ +-- ============================================================================= -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.all; -USE IEEE.NUMERIC_STD.all; +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; -LIBRARY UniSim; -USE UniSim.vComponents.ALL; +library UniSim; +use UniSim.vComponents.all; entity xil_SystemMonitor_Virtex6 is port ( - Reset : in STD_LOGIC; -- Reset signal for the System Monitor control logic + Reset : in std_logic; -- Reset signal for the System Monitor control logic - Alarm_UserTemp : out STD_LOGIC; -- Temperature-sensor alarm output - Alarm_OverTemp : out STD_LOGIC; -- Over-Temperature alarm output - Alarm : out STD_LOGIC; -- OR'ed output of all the Alarms - VP : in STD_LOGIC; -- Dedicated Analog Input Pair - VN : in STD_LOGIC + Alarm_UserTemp : out std_logic; -- Temperature-sensor alarm output + Alarm_OverTemp : out std_logic; -- Over-Temperature alarm output + Alarm : out std_logic; -- OR'ed output of all the Alarms + VP : in std_logic; -- Dedicated Analog Input Pair + VN : in std_logic ); -end; +end entity; architecture xilinx of xil_SystemMonitor_Virtex6 is - signal FLOAT_VCCAUX_ALARM : STD_LOGIC; - signal FLOAT_VCCINT_ALARM : STD_LOGIC; - signal aux_channel_p : STD_LOGIC_VECTOR(15 downto 0); - signal aux_channel_n : STD_LOGIC_VECTOR(15 downto 0); + signal FLOAT_VCCAUX_ALARM : std_logic; + signal FLOAT_VCCINT_ALARM : std_logic; + signal aux_channel_p : std_logic_vector(15 downto 0); + signal aux_channel_n : std_logic_vector(15 downto 0); - signal SysMonitor_Alarm : STD_LOGIC_VECTOR(2 downto 0); - signal SysMonitor_OverTemp : STD_LOGIC; + signal SysMonitor_Alarm : std_logic_vector(2 downto 0); + signal SysMonitor_OverTemp : std_logic; begin genAUXChannel : for i in 0 to 15 generate aux_channel_p(i) <= '0'; diff --git a/tb/arith/arith_addw_tb.vhdl b/tb/arith/arith_addw_tb.vhdl index dc92f5a1..5b6d16f2 100644 --- a/tb/arith/arith_addw_tb.vhdl +++ b/tb/arith/arith_addw_tb.vhdl @@ -62,7 +62,7 @@ architecture tb of arith_addw_tb is type word_vector is array(tArch_test, tSkip_test, boolean) of word; type carry_vector is array(tArch_test, tSkip_test, boolean) of std_logic; - signal Clock : STD_LOGIC; + signal Clock : std_logic; signal a, b : word; signal cin : std_logic; signal s : word_vector; @@ -81,7 +81,7 @@ begin constant simTestID : T_SIM_TEST_ID := simCreateTest("Test setup: " & "ARCH=" & str_lalign(TARCH'image(i), 5) & "SKIPPING=" & str_lalign(TSKIPPING'image(j), 8) & - "P_INCLUSIVE=" & str_lalign(BOOLEAN'image(p), 7)); + "P_INCLUSIVE=" & str_lalign(boolean'image(p), 7)); begin DUT : entity PoC.arith_addw generic map ( diff --git a/tb/arith/arith_convert_bin2bcd_tb.vhdl b/tb/arith/arith_convert_bin2bcd_tb.vhdl index 2b17661b..ac48e544 100644 --- a/tb/arith/arith_convert_bin2bcd_tb.vhdl +++ b/tb/arith/arith_convert_bin2bcd_tb.vhdl @@ -51,30 +51,30 @@ end entity; architecture test of arith_convert_bin2bcd_tb is constant CLOCK_FREQ : FREQ := 100 MHz; - constant INPUT_1 : INTEGER := 38442113; - constant INPUT_2 : INTEGER := 78734531; - constant INPUT_3 : INTEGER := 14902385; + constant INPUT_1 : integer := 38442113; + constant INPUT_2 : integer := 78734531; + constant INPUT_3 : integer := 14902385; - constant CONV1_BITS : POSITIVE := 30; - constant CONV1_DIGITS : POSITIVE := 8; - constant CONV2_BITS : POSITIVE := 27; - constant CONV2_DIGITS : POSITIVE := 8; - constant simTestID : T_SIM_TEST_ID := simCreateTest("Test setup for CONV1_BITS=" & INTEGER'image(CONV1_BITS) & "; INPUT_1=" & INTEGER'image(INPUT_1)); + constant CONV1_BITS : positive := 30; + constant CONV1_DIGITS : positive := 8; + constant CONV2_BITS : positive := 27; + constant CONV2_DIGITS : positive := 8; + constant simTestID : T_SIM_TEST_ID := simCreateTest("Test setup for CONV1_BITS=" & integer'image(CONV1_BITS) & "; INPUT_1=" & INTEGER'image(INPUT_1)); - signal Clock : STD_LOGIC; - signal Reset : STD_LOGIC; + signal Clock : std_logic; + signal Reset : std_logic; - signal Start : STD_LOGIC := '0'; + signal Start : std_logic := '0'; - signal Conv1_Binary : STD_LOGIC_VECTOR(CONV1_BITS - 1 downto 0); - signal Conv1_BCDDigits : T_BCD_VECTOR(CONV1_DIGITS - 1 DOWNTO 0); - signal Conv1_Sign : STD_LOGIC; - signal Conv2_Binary : STD_LOGIC_VECTOR(CONV2_BITS - 1 downto 0); - signal Conv2_BCDDigits : T_BCD_VECTOR(CONV2_DIGITS - 1 DOWNTO 0); - signal Conv2_Sign : STD_LOGIC; + signal Conv1_Binary : std_logic_vector(CONV1_BITS - 1 downto 0); + signal Conv1_BCDDigits : T_BCD_VECTOR(CONV1_DIGITS - 1 downto 0); + signal Conv1_Sign : std_logic; + signal Conv2_Binary : std_logic_vector(CONV2_BITS - 1 downto 0); + signal Conv2_BCDDigits : T_BCD_VECTOR(CONV2_DIGITS - 1 downto 0); + signal Conv2_Sign : std_logic; - function Check_Conv2(INPUT : INTEGER; BITS : POSITIVE; DIGITS : POSITIVE; BCDDigits : T_BCD_VECTOR; Sign : STD_LOGIC) return BOOLEAN is + function Check_Conv2(INPUT : integer; BITS : positive; DIGITS : positive; BCDDigits : T_BCD_VECTOR; Sign : std_logic) return boolean is variable nat : natural; begin if INPUT >= 2**(BITS-1) then @@ -100,7 +100,7 @@ begin simGenerateWaveform(simTestID, Reset, simGenerateWaveform_Reset(Pause => 10 ns, ResetPulse => 10 ns)); procStimuli : process - constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess(simTestID, "Stimuli for " & INTEGER'image(CONV1_BITS) & " bits"); + constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess(simTestID, "Stimuli for " & integer'image(CONV1_BITS) & " bits"); begin simWaitUntilRisingEdge(Clock, 4); diff --git a/tb/arith/arith_counter_bcd_tb.vhdl b/tb/arith/arith_counter_bcd_tb.vhdl index 12cd62f7..a21f83e5 100644 --- a/tb/arith/arith_counter_bcd_tb.vhdl +++ b/tb/arith/arith_counter_bcd_tb.vhdl @@ -52,7 +52,7 @@ architecture rtl of arith_counter_bcd_tb is constant CLOCK_FREQ : FREQ := 100 MHz; constant TEST_PARAMETERS : T_INTVEC := (3, 4); - signal Clock : STD_LOGIC; + signal Clock : std_logic; begin -- initialize global simulation status @@ -61,17 +61,17 @@ begin simGenerateClock(Clock, CLOCK_FREQ); genTests : for i in TEST_PARAMETERS'range generate - constant DIGITS : POSITIVE := TEST_PARAMETERS(i); - constant simTestID : T_SIM_TEST_ID := simCreateTest("Test setup for DIGITS=" & INTEGER'image(DIGITS)); + constant DIGITS : positive := TEST_PARAMETERS(i); + constant simTestID : T_SIM_TEST_ID := simCreateTest("Test setup for DIGITS=" & integer'image(DIGITS)); - signal Reset : STD_LOGIC; - signal inc : STD_LOGIC; + signal Reset : std_logic; + signal inc : std_logic; signal Value : T_BCD_VECTOR(DIGITS - 1 downto 0); begin -- simGenerateWaveform(simTestID, Reset, simGenerateWaveform_Reset(Pause => 10 ns, ResetPulse => 10 ns)); procGenerator : process - constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess(simTestID, "Generator for " & INTEGER'image(DIGITS) & " digits"); + constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess(simTestID, "Generator for " & integer'image(DIGITS) & " digits"); begin Reset <= '0'; inc <= '0'; @@ -124,33 +124,33 @@ begin ); procChecker : process - constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess(simTestID, "Checker for " & INTEGER'image(DIGITS) & " digits"); + constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess(simTestID, "Checker for " & integer'image(DIGITS) & " digits"); variable Expected : T_BCD_VECTOR(DIGITS - 1 downto 0); begin wait until rising_edge(Clock); wait until rising_edge(Clock); Expected := to_BCD_Vector(0, DIGITS); - simAssertion((Value = Expected), "Test " & INTEGER'image(simTestID) & ": Wrong initial state. Value=" & to_string(Value) & " Expected=" & to_string(Expected)); + simAssertion((Value = Expected), "Test " & integer'image(simTestID) & ": Wrong initial state. Value=" & to_string(Value) & " Expected=" & to_string(Expected)); wait until rising_edge(Clock); - simAssertion((Value = Expected), "Test " & INTEGER'image(simTestID) & ": Wrong initial state. Value=" & to_string(Value) & " Expected=" & to_string(Expected)); + simAssertion((Value = Expected), "Test " & integer'image(simTestID) & ": Wrong initial state. Value=" & to_string(Value) & " Expected=" & to_string(Expected)); wait until rising_edge(Clock); for i in 1 to 10**DIGITS - 1 loop Expected := to_BCD_Vector(i, DIGITS); wait until rising_edge(Clock); - simAssertion((Value = Expected), "Test " & INTEGER'image(simTestID) & ": Must be incremented to state " & to_string(Expected) & " Value=" & to_string(Value)); + simAssertion((Value = Expected), "Test " & integer'image(simTestID) & ": Must be incremented to state " & to_string(Expected) & " Value=" & to_string(Value)); wait until rising_edge(Clock); - simAssertion((Value = Expected), "Test " & INTEGER'image(simTestID) & ": Must keep the state " & to_string(Expected) & " Value=" & to_string(Value)); + simAssertion((Value = Expected), "Test " & integer'image(simTestID) & ": Must keep the state " & to_string(Expected) & " Value=" & to_string(Value)); end loop; wait until rising_edge(Clock); - simAssertion(Value = (DIGITS - 1 downto 0 => x"0"), "Test " & INTEGER'image(simTestID) & ": Should be wrapped to 0000."); + simAssertion(Value = (DIGITS - 1 downto 0 => x"0"), "Test " & integer'image(simTestID) & ": Should be wrapped to 0000."); simWaitUntilRisingEdge(Clock, 5); wait until rising_edge(Clock); - simAssertion(Value = (DIGITS - 1 downto 0 => x"0"), "Test " & INTEGER'image(simTestID) & ": Should be resetted again."); + simAssertion(Value = (DIGITS - 1 downto 0 => x"0"), "Test " & integer'image(simTestID) & ": Should be resetted again."); -- This process is finished simDeactivateProcess(simProcessID); diff --git a/tb/arith/arith_div_tb.files b/tb/arith/arith_div_tb.files index 0b807ff7..8af761f0 100644 --- a/tb/arith/arith_div_tb.files +++ b/tb/arith/arith_div_tb.files @@ -7,7 +7,7 @@ # PoC.arith include "src/arith/arith_div.files" # Unit Under Test -if (VHDL < 2002) then +if (VHDLVersion < 2002) then report "VHDL version not supported." end if diff --git a/tb/arith/arith_firstone_tb.vhdl b/tb/arith/arith_firstone_tb.vhdl index 84e604e7..aa7ae153 100644 --- a/tb/arith/arith_firstone_tb.vhdl +++ b/tb/arith/arith_firstone_tb.vhdl @@ -51,9 +51,9 @@ architecture tb of arith_firstone_tb is -- component generics constant N : positive := 8; - constant simTestID : T_SIM_TEST_ID := simCreateTest("Test setup for N=" & INTEGER'image(N)); + constant simTestID : T_SIM_TEST_ID := simCreateTest("Test setup for N=" & integer'image(N)); - signal Clock : STD_LOGIC; + signal Clock : std_logic; -- component ports signal tin : std_logic; @@ -82,7 +82,7 @@ begin ); procStimuli : process - constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess(simTestID, "Checker for " & INTEGER'image(N) & " bits"); + constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess(simTestID, "Checker for " & integer'image(N) & " bits"); begin -- Exhaustive Testing for i in natural range 0 to 2**N-1 loop diff --git a/tb/arith/arith_prefix_and_tb.vhdl b/tb/arith/arith_prefix_and_tb.vhdl index 24a5f477..4c32dbf9 100644 --- a/tb/arith/arith_prefix_and_tb.vhdl +++ b/tb/arith/arith_prefix_and_tb.vhdl @@ -48,10 +48,10 @@ end entity; architecture tb of arith_prefix_and_tb is constant CLOCK_FREQ : FREQ := 100 MHz; - constant BITS : POSITIVE := 8; - constant simTestID : T_SIM_TEST_ID := simCreateTest("Test setup for BITS=" & INTEGER'image(BITS)); + constant BITS : positive := 8; + constant simTestID : T_SIM_TEST_ID := simCreateTest("Test setup for BITS=" & integer'image(BITS)); - signal Clock : STD_LOGIC; + signal Clock : std_logic; signal x : std_logic_vector(BITS - 1 downto 0); signal y : std_logic_vector(BITS - 1 downto 0); @@ -73,13 +73,13 @@ begin ); procChecker : process - constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess(simTestID, "Checker for " & INTEGER'image(BITS) & " bits"); + constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess(simTestID, "Checker for " & integer'image(BITS) & " bits"); begin x <= (others => '0'); wait until rising_edge(Clock); -- Exhaustive Testing - for i in NATURAL range 0 to 2**BITS - 1 loop + for i in natural range 0 to 2**BITS - 1 loop x <= std_logic_vector(to_unsigned(i, BITS)); wait until rising_edge(Clock); for j in 0 to BITS - 1 loop diff --git a/tb/arith/arith_prefix_or_tb.vhdl b/tb/arith/arith_prefix_or_tb.vhdl index aaa72027..3afced7b 100644 --- a/tb/arith/arith_prefix_or_tb.vhdl +++ b/tb/arith/arith_prefix_or_tb.vhdl @@ -49,10 +49,10 @@ end entity; architecture tb of arith_prefix_or_tb is constant CLOCK_FREQ : FREQ := 100 MHz; - constant BITS : POSITIVE := 8; - constant simTestID : T_SIM_TEST_ID := simCreateTest("Test setup for BITS=" & INTEGER'image(BITS)); + constant BITS : positive := 8; + constant simTestID : T_SIM_TEST_ID := simCreateTest("Test setup for BITS=" & integer'image(BITS)); - signal Clock : STD_LOGIC; + signal Clock : std_logic; signal x : std_logic_vector(BITS - 1 downto 0); signal y : std_logic_vector(BITS - 1 downto 0); @@ -74,13 +74,13 @@ begin ); procChecker : process - constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess(simTestID, "Checker for " & INTEGER'image(BITS) & " bits"); + constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess(simTestID, "Checker for " & integer'image(BITS) & " bits"); begin x <= (others => '0'); wait until rising_edge(Clock); -- Exhaustive Testing - for i in NATURAL range 0 to 2**BITS - 1 loop + for i in natural range 0 to 2**BITS - 1 loop x <= std_logic_vector(to_unsigned(i, BITS)); wait until rising_edge(Clock); for j in 0 to BITS - 1 loop diff --git a/tb/arith/arith_prng_tb.vhdl b/tb/arith/arith_prng_tb.vhdl index f9032a1c..37a03a22 100644 --- a/tb/arith/arith_prng_tb.vhdl +++ b/tb/arith/arith_prng_tb.vhdl @@ -72,14 +72,14 @@ architecture tb of arith_prng_tb is x"9A", x"34", x"69", x"D3", x"A7", x"4F", x"9E", x"3C", x"78", x"F0", x"E0", x"C1", x"82", x"04", x"09", x"12" ); - constant BITS : POSITIVE := 8; - constant SEED : STD_LOGIC_VECTOR := x"12"; - constant simTestID : T_SIM_TEST_ID := simCreateTest("Test setup for BITS=" & INTEGER'image(BITS) & "; SEED=0x" & raw_format_slv_hex(SEED)); + constant BITS : positive := 8; + constant SEED : std_logic_vector := x"12"; + constant simTestID : T_SIM_TEST_ID := simCreateTest("Test setup for BITS=" & integer'image(BITS) & "; SEED=0x" & raw_format_slv_hex(SEED)); - signal Clock : STD_LOGIC; - signal Reset : STD_LOGIC; - signal Test_got : STD_LOGIC; - signal PRNG_Value : STD_LOGIC_VECTOR(BITS - 1 downto 0); + signal Clock : std_logic; + signal Reset : std_logic; + signal Test_got : std_logic; + signal PRNG_Value : std_logic_vector(BITS - 1 downto 0); begin -- initialize global simulation status @@ -101,7 +101,7 @@ begin ); procChecker : process - constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess(simTestID, "Checker for " & INTEGER'image(BITS) & " bits"); + constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess(simTestID, "Checker for " & integer'image(BITS) & " bits"); begin Test_got <= '0'; @@ -113,7 +113,7 @@ begin wait until rising_edge(Clock); simAssertion((PRNG_Value = COMPARE_LIST_8_BITS(i)), - str_ralign(INTEGER'image(i), log10ceil(COMPARE_LIST_8_BITS'high)) & + str_ralign(integer'image(i), log10ceil(COMPARE_LIST_8_BITS'high)) & ": Value=" & raw_format_slv_hex(PRNG_Value) & " Expected=" & raw_format_slv_hex(COMPARE_LIST_8_BITS(i)) ); diff --git a/tb/cache/cache_par_cocotb.py b/tb/cache/cache_par_cocotb.py index 5afb2d5d..bbc196cc 100644 --- a/tb/cache/cache_par_cocotb.py +++ b/tb/cache/cache_par_cocotb.py @@ -1,12 +1,12 @@ # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2; replace-tabs off; indent-width 2; -# +# # ============================================================================== # Authors: Martin Zabel -# +# # Cocotb Testbench: Cache with parallel access to tags and data. -# +# # Description: # ------------------------------------ # Automated testbench for PoC.cache_par @@ -18,13 +18,13 @@ # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany # Chair for VLSI-Design, Diagnostics and Architecture -# +# # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at -# +# # http://www.apache.org/licenses/LICENSE-2.0 -# +# # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -55,7 +55,7 @@ class InputDriver(BusDriver): """Drives inputs of DUT.""" _signals = [ "Request", "ReadWrite", "Invalidate", "Replace", "Address", "CacheLineIn" ] - + def __init__(self, dut): BusDriver.__init__(self, dut, None, dut.Clock) @@ -66,23 +66,23 @@ def __init__(self, tb, request=0, readWrite=0, invalidate=0, replace=0, address= if (replace==1) and ((request==1) or (invalidate==1)): raise ValueError("InputTransaction.__init__ called with request=%d, invalidate=%d, replace=%d" % request, invalidate, replace) - + self.Replace = BinaryValue(replace, 1) self.Request = BinaryValue(request, 1) self.ReadWrite = BinaryValue(readWrite, 1) self.Invalidate = BinaryValue(invalidate, 1) self.Address = BinaryValue(address, tb.address_bits, False) self.CacheLineIn = BinaryValue(cacheLineIn, tb.data_bits, False) - + # ============================================================================== class InputMonitor(BusMonitor): """Observes inputs of DUT.""" _signals = [ "Request", "ReadWrite", "Invalidate", "Replace", "Address", "CacheLineIn" ] - + def __init__(self, dut, callback=None, event=None): BusMonitor.__init__(self, dut, None, dut.Clock, dut.Reset, callback=callback, event=event) self.name = "in" - + @coroutine def _monitor_recv(self): clkedge = RisingEdge(self.clock) @@ -106,7 +106,7 @@ class OutputMonitor(BusMonitor): def __init__(self, dut, callback=None, event=None): BusMonitor.__init__(self, dut, None, dut.Clock, dut.Reset, callback=callback, event=event) self.name = "out" - + @coroutine def _monitor_recv(self): clkedge = RisingEdge(self.clock) @@ -114,8 +114,8 @@ def _monitor_recv(self): while True: # Capture signals at rising-edge of clock. yield clkedge - - + + vec = tuple([getattr(self.bus,i).value.integer for i in self._signals]) self._recv(vec) @@ -133,13 +133,13 @@ def compare(self, got, exp, log, **_): if self._imm: raise TestFailure("Received transaction differed from expected transaction.") - + def __init__(self, dut): self.dut = dut self.stopped = False self.address_bits = dut.ADDRESS_BITS.value self.data_bits = dut.DATA_BITS.value - + cache_lines = dut.CACHE_LINES.value # total number of cache lines self.associativity = dut.ASSOCIATIVITY.value self.cache_sets = cache_lines / self.associativity # number of cache sets @@ -151,7 +151,7 @@ def __init__(self, dut): self.tag_mask = 2**tag_bits-1 if DEBUG: print("Testbench: {0}, {1}, {2}".format(self.index_bits, self.index_mask, self.tag_mask)) - + replacement_policy = dut.REPLACEMENT_POLICY.value if replacement_policy != "LRU": raise TestFailure("Unsupported configuration: REPLACEMENT_POLICY=%s" % replacement_policy) @@ -160,10 +160,10 @@ def __init__(self, dut): self.lrus = tuple([LeastRecentlyUsedDict(size_limit=self.associativity) for _ in range(self.cache_sets)]) init_val = (None, 0, 0, None) - + self.input_drv = InputDriver(dut) self.output_mon = OutputMonitor(dut) - + # Create a scoreboard on the outputs self.expected_output = [ init_val ] self.scoreboard = Testbench.MyScoreboard(dut) @@ -181,7 +181,7 @@ def model(self, transaction): index = address & self.index_mask #tag = (address >> self.index_bits) & self.tag_mask - + # expected outputs, None means ignore cacheLineOut, cacheHit, cacheMiss, oldAddress = None, 0, 0, None if not self.stopped: @@ -196,10 +196,10 @@ def model(self, transaction): if invalidate == 1: del self.lrus[index][address] - + else: cacheMiss = 1 - + elif replace == 1: # check if a valid cache line will be replaced if len(self.lrus[index]) == self.associativity: @@ -210,7 +210,7 @@ def model(self, transaction): if DEBUG >= 1: print("=== model: lrus[{0}] = {1!s}".format(index, self.lrus[index].items())) self.expected_output.append( (cacheLineOut, cacheHit, cacheMiss, oldAddress) ) - + def stop(self): """ Stop generation of expected output transactions. @@ -233,10 +233,10 @@ def random_input_gen(tb,n=100000): # it is forbidden to replace a cache line when the new address is already within the cache # we cannot directly access the content of the LRU list in the testbench because this function is called asynchronously lru_tags = tuple([LeastRecentlyUsedDict(size_limit=tb.associativity) for _ in range(tb.cache_sets)]) - + for i in range(n): if DEBUG and (i % 1000 == 0): print("Generating transaction #{0} ...".format(i)) - + command = random.randint(1,60) request, readWrite, invalidate, replace = 0, 0, 0, 0 # 10% for each possible command @@ -266,7 +266,7 @@ def random_input_gen(tb,n=100000): if DEBUG >= 2: print("=== random_input_gen: request={0}, readWrite={1}, invalidate={2}, replace={3}, address={4}".format(request, readWrite, invalidate, replace, address)) if DEBUG >= 2: print("=== random_input_gen: lru_tags[{0}]={1!s}".format(index, lru_tags[index].items())) - + yield InputTransaction(tb, request, readWrite, invalidate, replace, address, random.randint(0,data_high)) @cocotb.coroutine @@ -284,7 +284,7 @@ def run_test(dut): dut.Reset <= 0 input_gen = random_input_gen(tb) - + # Issue first transaction immediately. yield tb.input_drv.send(input_gen.next(), False) @@ -298,7 +298,7 @@ def run_test(dut): yield tb.input_drv.send(InputTransaction(tb)) tb.stop() yield RisingEdge(dut.Clock) - + # Print result of scoreboard. raise tb.scoreboard.result diff --git a/tb/common/config_tb.files b/tb/common/config_tb.files index c8b06fce..8e021ea8 100644 --- a/tb/common/config_tb.files +++ b/tb/common/config_tb.files @@ -5,4 +5,6 @@ # Note: all files are relative to PoC root directory # # Testbench file(s) +include "src/common/common.files" + vhdl test "tb/common/config_tb.vhdl" # Testbench diff --git a/tb/common/config_tb.vhdl b/tb/common/config_tb.vhdl index d736d657..31291c44 100644 --- a/tb/common/config_tb.vhdl +++ b/tb/common/config_tb.vhdl @@ -43,36 +43,36 @@ end config_tb; architecture tb of config_tb is - signal SimQuiet : BOOLEAN := true; + signal SimQuiet : boolean := true; begin procChecker : process constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess("Checker"); begin - if (SimQuiet = FALSE) then - report "is simulation?: " & BOOLEAN'image(SIMULATION) severity note; + if not SimQuiet then + report "is simulation?: " & boolean'image(SIMULATION) severity note; report "Vendor: " & T_VENDOR'image(VENDOR) severity note; report "Device: " & T_DEVICE'image(DEVICE) severity note; report "Device Family: " & T_DEVICE_FAMILY'image(DEVICE_FAMILY) severity note; report "Device Subtype: " & T_DEVICE_SUBTYPE'image(DEVICE_SUBTYPE) severity note; report "Device Series: " & T_DEVICE_SERIES'image(DEVICE_SERIES) severity note; - report "Device Generation: " & INTEGER'image(DEVICE_GENERATION) severity note; - report "Device Number: " & INTEGER'image(DEVICE_NUMBER) severity note; + report "Device Generation: " & integer'image(DEVICE_GENERATION) severity note; + report "Device Number: " & integer'image(DEVICE_NUMBER) severity note; report "--------------------------------------------------" severity note; - report "LUT fan-in: " & INTEGER'image(LUT_FANIN) severity note; + report "LUT fan-in: " & integer'image(LUT_FANIN) severity note; report "Transceiver: " & T_TRANSCEIVER'image(TRANSCEIVER_TYPE) severity note; end if; - simAssertion((SIMULATION = TRUE), "SIMULATION=" & BOOLEAN'image(SIMULATION) & " Expected=TRUE"); - simAssertion((VENDOR = VENDOR_XILINX), "VENDOR= " & T_VENDOR'image(VENDOR) & " Expected=VENDOR_XILINX"); - simAssertion((DEVICE = DEVICE_KINTEX7), "DEVICE=" & T_DEVICE'image(DEVICE) & " Expected=DEVICE_KINTEX7"); - simAssertion((DEVICE_FAMILY = DEVICE_FAMILY_KINTEX), "DEVICE_FAMILY=" & T_DEVICE_FAMILY'image(DEVICE_FAMILY) & " Expected=DEVICE_FAMILY_KINTEX"); - simAssertion((DEVICE_NUMBER = 325), "DEVICE_NUMBER=" & INTEGER'image(DEVICE_NUMBER) & " Expected=325"); - simAssertion((DEVICE_SUBTYPE = DEVICE_SUBTYPE_T), "DEVICE_SUBTYPE=" & T_DEVICE_SUBTYPE'image(DEVICE_SUBTYPE) & " Expected=DEVICE_SUBTYPE_T"); - simAssertion((DEVICE_GENERATION = 7), "DEVICE_GENERATION=" & INTEGER'image(DEVICE_GENERATION) & " Expected=7"); - simAssertion((DEVICE_SERIES = DEVICE_SERIES_7_SERIES), "DEVICE_SERIES=" & T_DEVICE_SERIES'image(DEVICE_SERIES) & " Expected=DEVICE_SERIES_7_SERIES"); - simAssertion((LUT_FANIN = 6), "LUT_FANIN=" & INTEGER'image(LUT_FANIN) & " Expected=6"); - simAssertion((TRANSCEIVER_TYPE = TRANSCEIVER_GTXE2), "TRANSCEIVER_TYPE=" & T_TRANSCEIVER'image(TRANSCEIVER_TYPE) & " Expected=TRANSCEIVER_GTXE2"); + simAssertion((SIMULATION = TRUE), "SIMULATION=" & boolean'image(SIMULATION) & " Expected=TRUE"); + simAssertion((VENDOR = VENDOR_GENERIC), "VENDOR= " & T_VENDOR'image(VENDOR) & " Expected=VENDOR_XILINX"); + simAssertion((DEVICE = DEVICE_GENERIC), "DEVICE=" & T_DEVICE'image(DEVICE) & " Expected=DEVICE_KINTEX7"); + simAssertion((DEVICE_FAMILY = DEVICE_FAMILY_GENERIC), "DEVICE_FAMILY=" & T_DEVICE_FAMILY'image(DEVICE_FAMILY) & " Expected=DEVICE_FAMILY_KINTEX"); + simAssertion((DEVICE_NUMBER = 0), "DEVICE_NUMBER=" & integer'image(DEVICE_NUMBER) & " Expected=325"); + simAssertion((DEVICE_SUBTYPE = DEVICE_SUBTYPE_GENERIC), "DEVICE_SUBTYPE=" & T_DEVICE_SUBTYPE'image(DEVICE_SUBTYPE) & " Expected=DEVICE_SUBTYPE_T"); + simAssertion((DEVICE_GENERATION = 0), "DEVICE_GENERATION=" & integer'image(DEVICE_GENERATION) & " Expected=7"); + simAssertion((DEVICE_SERIES = DEVICE_SERIES_GENERIC), "DEVICE_SERIES=" & T_DEVICE_SERIES'image(DEVICE_SERIES) & " Expected=DEVICE_SERIES_7_SERIES"); + simAssertion((LUT_FANIN = 6), "LUT_FANIN=" & integer'image(LUT_FANIN) & " Expected=6"); + simAssertion((TRANSCEIVER_TYPE = TRANSCEIVER_GENERIC), "TRANSCEIVER_TYPE=" & T_TRANSCEIVER'image(TRANSCEIVER_TYPE) & " Expected=TRANSCEIVER_GTXE2"); -- This process is finished simDeactivateProcess(simProcessID); diff --git a/tb/common/lru_dict.py b/tb/common/lru_dict.py index a4000417..2bfda85b 100644 --- a/tb/common/lru_dict.py +++ b/tb/common/lru_dict.py @@ -1,31 +1,31 @@ # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2; replace-tabs off; indent-width 2; -# +# # ============================================================================== # Authors: Martin Zabel -# +# # Python Module: LRU Dictionary used by various Cocotb Testbenches for LRU components -# +# # Description: # ------------------------------------ # Provides an ordered dictionary with LRU policy. # -# The entries in this dictionary are ordered by the last addition or update -# of key:value pairs. The maximum size of the dictionary can be specified -# during object creation. +# The entries in this dictionary are ordered by the last addition or update +# of key:value pairs. The maximum size of the dictionary can be specified +# during object creation. # # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany # Chair for VLSI-Design, Diagnostics and Architecture -# +# # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at -# +# # http://www.apache.org/licenses/LICENSE-2.0 -# +# # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -37,17 +37,17 @@ class LeastRecentlyUsedDict(OrderedDict): """ - The entries in this dictionary are ordered by the last addition or update - of key:value pairs. The maximum size of the dictionary can be specified - during object creation. - + The entries in this dictionary are ordered by the last addition or update + of key:value pairs. The maximum size of the dictionary can be specified + during object creation. + Based on this StackOverflow answer: http://stackoverflow.com/a/2437645/5466118 and the example on: https://docs.python.org/2/library/collections.html#ordereddict-examples-and-recipes """ def __init__(self, *args, **kwds): """ - The optional keyword 'size_limit' specifies the maximum size of the + The optional keyword 'size_limit' specifies the maximum size of the dictionary. """ self._size_limit = kwds.pop("size_limit", None) @@ -69,10 +69,10 @@ def _check_size_limit(self): def size_limit(self): """Get the size limit.""" return self._size_limit - + def moveLRU(self, key, value=None): """ - Mark key as least-recently used. + Mark key as least-recently used. Does nothing, if key is not within dictionary. If no value is specified, then the current value of the key is used. """ diff --git a/tb/common/my_config.files b/tb/common/my_config.files index ca17b7e0..5b06bd5f 100644 --- a/tb/common/my_config.files +++ b/tb/common/my_config.files @@ -13,6 +13,18 @@ vhdl poc "tb/common/my_project.vhdl" # ====================================== if (BoardName = "GENERIC") then vhdl poc "tb/common/my_config_GENERIC.vhdl" +elseif (BoardName = "Custom") then + path TempDirectory = ${CONFIG.DirectoryNames:TemporaryFiles} + if (Tool = "GHDL") then + path ToolDirectory = (TempDirectory / ${CONFIG.DirectoryNames:GHDLFiles}) + elseif (Tool in ["Mentor_vSim", "Cocotb_QuestaSim"]) then + path ToolDirectory = (TempDirectory / ${CONFIG.DirectoryNames:ModelSimFiles}) + else + report "Tool not supported." + end if + + path CustomConfigFile = (ToolDirectory / "my_config_Custom.vhdl") + vhdl poc CustomConfigFile # Altera boards # ====================================== @@ -50,9 +62,15 @@ elseif (BoardName = "Atlys") then vhdl poc "tb/common/my_config_Atlys.vhdl" # Zynq-7000 boards - -# Artix-7 BoardNames +elseif (BoardName = "ZC706") then + vhdl poc "tb/common/my_config_ZC706.vhdl" +elseif (BoardName = "ZedBoard") then + vhdl poc "tb/common/my_config_ZedBoard.vhdl" +# Artix-7 BoardNames +elseif (BoardName = "AC701") then + vhdl poc "tb/common/my_config_AC701.vhdl" + # Kintex-7 BoardNames elseif (BoardName = "KC705") then vhdl poc "tb/common/my_config_KC705.vhdl" @@ -72,8 +90,8 @@ elseif (BoardName = "ML605") then # Virtex-7 boards elseif (BoardName = "VC707") then vhdl poc "tb/common/my_config_VC707.vhdl" -#elseif (BoardName = "VC709") then -# vhdl poc "tb/common/my_config_VC709.vhdl" +elseif (BoardName = "VC709") then + vhdl poc "tb/common/my_config_VC709.vhdl" # other boards else diff --git a/tb/common/my_config_AC701.vhdl b/tb/common/my_config_AC701.vhdl new file mode 100644 index 00000000..68587376 --- /dev/null +++ b/tb/common/my_config_AC701.vhdl @@ -0,0 +1,43 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- +-- ============================================================================= +-- Authors: Thomas B. Preusser +-- Martin Zabel +-- Patrick Lehmann +-- +-- Package: Project specific configuration. +-- +-- Description: +-- ------------------------------------ +-- This file was created from template /src/common/my_config.template.vhdl. +-- +-- +-- License: +-- ============================================================================= +-- Copyright 2007-2016 Technische Universitaet Dresden - Germany, +-- Chair for VLSI-Design, Diagnostics and Architecture +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + + +package my_config is + -- Change these lines to setup configuration. + constant MY_BOARD : string := "AC701"; -- AC701 - Xilinx Artix-7 reference design board: XC7A200T + constant MY_DEVICE : string := "None"; -- infer from MY_BOARD + + -- For internal use only + constant MY_VERBOSE : boolean := FALSE; +end package; diff --git a/tb/common/my_config_S3SK1000.vhdl b/tb/common/my_config_S3SK1000.vhdl index f5b6df23..cbd8c2a5 100644 --- a/tb/common/my_config_S3SK1000.vhdl +++ b/tb/common/my_config_S3SK1000.vhdl @@ -44,7 +44,7 @@ package my_config is -- Change these lines to setup configuration. constant MY_BOARD : string := "S3SK1000"; -- Spartan-3 Starter Kit - constant MY_DEVICE : string := "XC3S1000-FT2564C"; + constant MY_DEVICE : string := "None"; -- For internal use only constant MY_VERBOSE : boolean := true; diff --git a/tb/common/my_config_VC709.vhdl b/tb/common/my_config_VC709.vhdl new file mode 100644 index 00000000..5a3b5972 --- /dev/null +++ b/tb/common/my_config_VC709.vhdl @@ -0,0 +1,43 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- +-- ============================================================================= +-- Authors: Thomas B. Preusser +-- Martin Zabel +-- Patrick Lehmann +-- +-- Package: Project specific configuration. +-- +-- Description: +-- ------------------------------------ +-- This file was created from template /src/common/my_config.template.vhdl. +-- +-- +-- License: +-- ============================================================================= +-- Copyright 2007-2016 Technische Universitaet Dresden - Germany, +-- Chair for VLSI-Design, Diagnostics and Architecture +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + + +package my_config is + -- Change these lines to setup configuration. + constant MY_BOARD : string := "VC709"; -- VC709 - Xilinx Virtex 7 reference design board: XC7VX690T + constant MY_DEVICE : string := "None"; -- infer from MY_BOARD + + -- For internal use only + constant MY_VERBOSE : boolean := FALSE; +end package; diff --git a/tb/common/my_config_ZC706.vhdl b/tb/common/my_config_ZC706.vhdl new file mode 100644 index 00000000..73419598 --- /dev/null +++ b/tb/common/my_config_ZC706.vhdl @@ -0,0 +1,43 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- +-- ============================================================================= +-- Authors: Thomas B. Preusser +-- Martin Zabel +-- Patrick Lehmann +-- +-- Package: Project specific configuration. +-- +-- Description: +-- ------------------------------------ +-- This file was created from template /src/common/my_config.template.vhdl. +-- +-- +-- License: +-- ============================================================================= +-- Copyright 2007-2016 Technische Universitaet Dresden - Germany, +-- Chair for VLSI-Design, Diagnostics and Architecture +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + + +package my_config is + -- Change these lines to setup configuration. + constant MY_BOARD : string := "ZC706"; -- ZC706 - Xilinx Zynq-7000 reference design board: XC7Z045 + constant MY_DEVICE : string := "None"; -- infer from MY_BOARD + + -- For internal use only + constant MY_VERBOSE : boolean := FALSE; +end package; diff --git a/tb/common/my_config_ZedBoard.vhdl b/tb/common/my_config_ZedBoard.vhdl new file mode 100644 index 00000000..8e983364 --- /dev/null +++ b/tb/common/my_config_ZedBoard.vhdl @@ -0,0 +1,43 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- +-- ============================================================================= +-- Authors: Thomas B. Preusser +-- Martin Zabel +-- Patrick Lehmann +-- +-- Package: Project specific configuration. +-- +-- Description: +-- ------------------------------------ +-- This file was created from template /src/common/my_config.template.vhdl. +-- +-- +-- License: +-- ============================================================================= +-- Copyright 2007-2016 Technische Universitaet Dresden - Germany, +-- Chair for VLSI-Design, Diagnostics and Architecture +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + + +package my_config is + -- Change these lines to setup configuration. + constant MY_BOARD : string := "ZedBoard"; -- ZedBoard - Digilent Zynq-7000 board: XC7Z020 + constant MY_DEVICE : string := "None"; -- infer from MY_BOARD + + -- For internal use only + constant MY_VERBOSE : boolean := FALSE; +end package; diff --git a/tb/common/physical_tb.files b/tb/common/physical_tb.files new file mode 100644 index 00000000..a1365e6d --- /dev/null +++ b/tb/common/physical_tb.files @@ -0,0 +1,10 @@ +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# ============================================================================== +# Note: all files are relative to PoC root directory +# +# Testbench file(s) +include "src/common/common.files" + +vhdl test "tb/common/physical_tb.vhdl" diff --git a/tb/common/physical_tb.vhdl b/tb/common/physical_tb.vhdl new file mode 100644 index 00000000..5890443f --- /dev/null +++ b/tb/common/physical_tb.vhdl @@ -0,0 +1,67 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- +-- ============================================================================= +-- Testbench: Testing the physical package. +-- +-- Authors: Thomas B. Preusser +-- Patrick Lehmann +-- +-- Description: +-- ------------------------------------ +-- TODO +-- +-- License: +-- ============================================================================= +-- Copyright 2007-2016 Technische Universitaet Dresden - Germany +-- Chair for VLSI-Design, Diagnostics and Architecture +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +entity physical_tb is +end; + + +library PoC; +use PoC.physical.all; + +-- simulation only packages +use PoC.sim_types.all; +use PoC.simulation.all; + +architecture tb of physical_tb is + constant simTestID : T_SIM_TEST_ID := simCreateTest("Physical types test."); +begin + simInitialize; + + process + constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess(simTestID, ""); + + variable t : time; + variable f : FREQ; + begin + t := 20 ns; + simAssertion(integer(10.0 * to_real(t, 1 ns)) = 200, "Failed stripping of time unit."); + f := 1.0 / t; + simAssertion(integer(10.0 * to_real(f, 1 MHz)) = 500, "Failed stripping of FREQ unit."); + + simAssertion(integer(10.0 * t*f) = 10, "Failed cycle computation."); + simAssertion(integer(10.0 * f*t) = 10, "Failed cycle computation."); + + simDeactivateProcess(simProcessID); + wait; --forever + end process; + +end; diff --git a/tb/common/strings_tb.files b/tb/common/strings_tb.files index f6436641..8bf79059 100644 --- a/tb/common/strings_tb.files +++ b/tb/common/strings_tb.files @@ -5,4 +5,6 @@ # Note: all files are relative to PoC root directory # # Testbench file(s) +include "src/common/common.files" + vhdl test "tb/common/strings_tb.vhdl" # Testbench diff --git a/tb/common/strings_tb.vhdl b/tb/common/strings_tb.vhdl index 936f363d..446530ee 100644 --- a/tb/common/strings_tb.vhdl +++ b/tb/common/strings_tb.vhdl @@ -48,31 +48,31 @@ end entity; architecture tb of strings_tb is - constant raw_format_slv_dec_result0 : STRING := raw_format_slv_dec(STD_LOGIC_VECTOR'(x"12")); - constant raw_format_slv_dec_result1 : STRING := raw_format_slv_dec(x"3456"); - constant raw_format_slv_dec_result2 : STRING := raw_format_slv_dec(x"12345678"); - constant raw_format_slv_dec_result3 : STRING := raw_format_slv_dec(x"A1B2C3D4E5F607A8"); - - constant str_length_result0 : INTEGER := str_length(""); - constant str_length_result1 : INTEGER := str_length((1 to 3 => C_POC_NUL)); - constant str_length_result2 : INTEGER := str_length("Hello"); - constant str_length_result3 : INTEGER := str_length("Hello" & (1 to 3 => C_POC_NUL)); - - constant str_match_result0 : BOOLEAN := str_match("", ""); - constant str_match_result1 : BOOLEAN := str_match("", (1 to 3 => C_POC_NUL)); - constant str_match_result2 : BOOLEAN := str_match("Hello", "hello"); - constant str_match_result3 : BOOLEAN := str_match("Hello", "Hello"); - constant str_match_result4 : BOOLEAN := str_match("Hello World", "Hello"); - constant str_match_result5 : BOOLEAN := str_match("Hello", "Hello World"); - constant str_match_result6 : BOOLEAN := str_match("Hello", "Hello" & (1 to 3 => C_POC_NUL)); - - constant str_imatch_result0 : BOOLEAN := str_imatch("", ""); - constant str_imatch_result1 : BOOLEAN := str_imatch("", (1 to 3 => C_POC_NUL)); - constant str_imatch_result2 : BOOLEAN := str_imatch("Hello", "hello"); - constant str_imatch_result3 : BOOLEAN := str_imatch("Hello", "Hello"); - constant str_imatch_result4 : BOOLEAN := str_imatch("Hello World", "Hello"); - constant str_imatch_result5 : BOOLEAN := str_imatch("Hello", "Hello World"); - constant str_imatch_result6 : BOOLEAN := str_imatch("Hello", "Hello" & (1 to 3 => C_POC_NUL)); + constant raw_format_slv_dec_result0 : string := raw_format_slv_dec(std_logic_vector'(x"12")); + constant raw_format_slv_dec_result1 : string := raw_format_slv_dec(x"3456"); + constant raw_format_slv_dec_result2 : string := raw_format_slv_dec(x"12345678"); + constant raw_format_slv_dec_result3 : string := raw_format_slv_dec(x"A1B2C3D4E5F607A8"); + + constant str_length_result0 : integer := str_length(""); + constant str_length_result1 : integer := str_length((1 to 3 => C_POC_NUL)); + constant str_length_result2 : integer := str_length("Hello"); + constant str_length_result3 : integer := str_length("Hello" & (1 to 3 => C_POC_NUL)); + + constant str_match_result0 : boolean := str_match("", ""); + constant str_match_result1 : boolean := str_match("", (1 to 3 => C_POC_NUL)); + constant str_match_result2 : boolean := str_match("Hello", "hello"); + constant str_match_result3 : boolean := str_match("Hello", "Hello"); + constant str_match_result4 : boolean := str_match("Hello World", "Hello"); + constant str_match_result5 : boolean := str_match("Hello", "Hello World"); + constant str_match_result6 : boolean := str_match("Hello", "Hello" & (1 to 3 => C_POC_NUL)); + + constant str_imatch_result0 : boolean := str_imatch("", ""); + constant str_imatch_result1 : boolean := str_imatch("", (1 to 3 => C_POC_NUL)); + constant str_imatch_result2 : boolean := str_imatch("Hello", "hello"); + constant str_imatch_result3 : boolean := str_imatch("Hello", "Hello"); + constant str_imatch_result4 : boolean := str_imatch("Hello World", "Hello"); + constant str_imatch_result5 : boolean := str_imatch("Hello", "Hello World"); + constant str_imatch_result6 : boolean := str_imatch("Hello", "Hello" & (1 to 3 => C_POC_NUL)); begin procChecker : process @@ -85,28 +85,28 @@ begin simAssertion((raw_format_slv_dec_result3 = "11651590505119483816"), "raw_format_slv_dec(0xA1b2c3d4e5f607a8)=" & raw_format_slv_dec_result3 & " Expected='11651590505119483816'"); -- str_length tests - simAssertion((str_length_result0 = 0), "str_length('')=" & INTEGER'image(str_length_result0) & " Expected=0"); - simAssertion((str_length_result1 = 0), "str_length('\0\0\0')=" & INTEGER'image(str_length_result1) & " Expected=0"); - simAssertion((str_length_result2 = 5), "str_length('Hello')=" & INTEGER'image(str_length_result2) & " Expected=5"); - simAssertion((str_length_result3 = 5), "str_length('Hello\0\0\0')=" & INTEGER'image(str_length_result3) & " Expected=5"); + simAssertion((str_length_result0 = 0), "str_length('')=" & integer'image(str_length_result0) & " Expected=0"); + simAssertion((str_length_result1 = 0), "str_length('\0\0\0')=" & integer'image(str_length_result1) & " Expected=0"); + simAssertion((str_length_result2 = 5), "str_length('Hello')=" & integer'image(str_length_result2) & " Expected=5"); + simAssertion((str_length_result3 = 5), "str_length('Hello\0\0\0')=" & integer'image(str_length_result3) & " Expected=5"); -- str_match tests - simAssertion((str_match_result0 = TRUE), "str_match('', '')=" & BOOLEAN'image(str_match_result0) & " Expected=TRUE"); - simAssertion((str_match_result1 = TRUE), "str_match('', '\0\0\0')=" & BOOLEAN'image(str_match_result1) & " Expected=TRUE"); - simAssertion((str_match_result2 = FALSE), "str_match('Hello', 'hello')=" & BOOLEAN'image(str_match_result2) & " Expected=FALSE"); - simAssertion((str_match_result3 = TRUE), "str_match('Hello', 'Hello')=" & BOOLEAN'image(str_match_result3) & " Expected=TRUE"); - simAssertion((str_match_result4 = FALSE), "str_match('Hello World', 'Hello')=" & BOOLEAN'image(str_match_result4) & " Expected=FALSE"); - simAssertion((str_match_result5 = FALSE), "str_match('Hello', 'Hello World')=" & BOOLEAN'image(str_match_result5) & " Expected=FALSE"); - simAssertion((str_match_result6 = TRUE), "str_match('Hello', 'Hello\0\0\0')=" & BOOLEAN'image(str_match_result6) & " Expected=TRUE"); + simAssertion((str_match_result0 = TRUE), "str_match('', '')=" & boolean'image(str_match_result0) & " Expected=TRUE"); + simAssertion((str_match_result1 = TRUE), "str_match('', '\0\0\0')=" & boolean'image(str_match_result1) & " Expected=TRUE"); + simAssertion((str_match_result2 = FALSE), "str_match('Hello', 'hello')=" & boolean'image(str_match_result2) & " Expected=FALSE"); + simAssertion((str_match_result3 = TRUE), "str_match('Hello', 'Hello')=" & boolean'image(str_match_result3) & " Expected=TRUE"); + simAssertion((str_match_result4 = FALSE), "str_match('Hello World', 'Hello')=" & boolean'image(str_match_result4) & " Expected=FALSE"); + simAssertion((str_match_result5 = FALSE), "str_match('Hello', 'Hello World')=" & boolean'image(str_match_result5) & " Expected=FALSE"); + simAssertion((str_match_result6 = TRUE), "str_match('Hello', 'Hello\0\0\0')=" & boolean'image(str_match_result6) & " Expected=TRUE"); -- str_imatch tests - simAssertion((str_imatch_result0 = TRUE), "str_imatch('', '')=" & BOOLEAN'image(str_imatch_result0) & " Expected=TRUE"); - simAssertion((str_imatch_result1 = TRUE), "str_imatch('', '\0\0\0')=" & BOOLEAN'image(str_imatch_result1) & " Expected=TRUE"); - simAssertion((str_imatch_result2 = TRUE), "str_imatch('Hello', 'hello')=" & BOOLEAN'image(str_imatch_result2) & " Expected=TRUE"); - simAssertion((str_imatch_result3 = TRUE), "str_imatch('Hello', 'Hello')=" & BOOLEAN'image(str_imatch_result3) & " Expected=TRUE"); - simAssertion((str_imatch_result4 = FALSE), "str_imatch('Hello World', 'Hello')=" & BOOLEAN'image(str_imatch_result4) & " Expected=FALSE"); - simAssertion((str_imatch_result5 = FALSE), "str_imatch('Hello', 'Hello World')=" & BOOLEAN'image(str_imatch_result5) & " Expected=FALSE"); - simAssertion((str_imatch_result6 = TRUE), "str_imatch('Hello', 'Hello\0\0\0')=" & BOOLEAN'image(str_imatch_result6) & " Expected=TRUE"); + simAssertion((str_imatch_result0 = TRUE), "str_imatch('', '')=" & boolean'image(str_imatch_result0) & " Expected=TRUE"); + simAssertion((str_imatch_result1 = TRUE), "str_imatch('', '\0\0\0')=" & boolean'image(str_imatch_result1) & " Expected=TRUE"); + simAssertion((str_imatch_result2 = TRUE), "str_imatch('Hello', 'hello')=" & boolean'image(str_imatch_result2) & " Expected=TRUE"); + simAssertion((str_imatch_result3 = TRUE), "str_imatch('Hello', 'Hello')=" & boolean'image(str_imatch_result3) & " Expected=TRUE"); + simAssertion((str_imatch_result4 = FALSE), "str_imatch('Hello World', 'Hello')=" & boolean'image(str_imatch_result4) & " Expected=FALSE"); + simAssertion((str_imatch_result5 = FALSE), "str_imatch('Hello', 'Hello World')=" & boolean'image(str_imatch_result5) & " Expected=FALSE"); + simAssertion((str_imatch_result6 = TRUE), "str_imatch('Hello', 'Hello\0\0\0')=" & boolean'image(str_imatch_result6) & " Expected=TRUE"); -- str_pos tests -- str_ipos tests diff --git a/tb/common/utils.py b/tb/common/utils.py index ab092039..41fa90ac 100644 --- a/tb/common/utils.py +++ b/tb/common/utils.py @@ -1,32 +1,32 @@ # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2; replace-tabs off; indent-width 2; -# +# # ============================================================================== # Authors: Martin Zabel -# Patrick Lehmann -# +# Patrick Lehmann +# # Python Module: LRU Dictionary used by various Cocotb Testbenches for LRU components -# +# # Description: # ------------------------------------ # Provides an ordered dictionary with LRU policy. # -# The entries in this dictionary are ordered by the last addition or update -# of key:value pairs. The maximum size of the dictionary can be specified -# during object creation. +# The entries in this dictionary are ordered by the last addition or update +# of key:value pairs. The maximum size of the dictionary can be specified +# during object creation. # # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany # Chair for VLSI-Design, Diagnostics and Architecture -# +# # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at -# +# # http://www.apache.org/licenses/LICENSE-2.0 -# +# # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -42,7 +42,7 @@ def log2ceil(arg): while arg > tmp: tmp = tmp * 2 log = log + 1 - + return log def log2ceilnz(arg): diff --git a/tb/dstruct/dstruct_deque_tb.vhdl b/tb/dstruct/dstruct_deque_tb.vhdl index 3ce18adb..a15be47e 100644 --- a/tb/dstruct/dstruct_deque_tb.vhdl +++ b/tb/dstruct/dstruct_deque_tb.vhdl @@ -145,7 +145,7 @@ begin simAssertion(fullA = '0', "fullA != 0!"); simAssertion(validA = '1', "validA != 1!"); simAssertion(fullB = '0', "fullB != 0!"); - if (i = 1) then + if i = 1 then simAssertion(validB = '0', "validB != 0!"); else simAssertion(validB = '1', "validB != 1!"); @@ -227,10 +227,10 @@ begin cycle; gotB <= '0'; cycle; - if (i > MIN_DEPTH/2) then + if i > MIN_DEPTH/2 then simAssertion(doutB = std_logic_vector(to_unsigned(j-2, D_BITS)), "doutB !=j-2"); j := j - 2; - elsif (i = MIN_DEPTH/2) then + elsif i = MIN_DEPTH/2 then simAssertion(doutB = std_logic_vector(to_unsigned(j-1, D_BITS)), "doutB !=j-2"); else simAssertion(doutB = std_logic_vector(to_unsigned(k+2, D_BITS)), "doutB !=k"); @@ -306,7 +306,7 @@ begin simAssertion(fullA = '0', "fullA != 0!"); simAssertion(validA = '1', "validA != 1!"); simAssertion(fullB = '0', "fullB != 0!"); - if (i = 1) then + if i = 1 then simAssertion(validB = '0', "validB != 0!"); else simAssertion(validB = '1', "validB != 1!"); @@ -997,7 +997,7 @@ begin simAssertion(validB = '1', "validB != 1!"); simAssertion(fullB = '0', "fullB != 0!"); simAssertion(doutB = std_logic_vector(to_unsigned(MIN_DEPTH-1, D_BITS)), "doutB != MIN_DEPTH-1"); - if (MIN_DEPTH > 4) then + if MIN_DEPTH > 4 then simAssertion(doutA = std_logic_vector(to_unsigned(MIN_DEPTH-6, D_BITS)), "doutA != MIN_DEPTH-6"); else simAssertion(doutA = std_logic_vector(to_unsigned(1, D_BITS)), "doutA != 0x01"); @@ -1010,7 +1010,7 @@ begin dinB <= std_logic_vector(to_unsigned(0, D_BITS)); putB <= '0'; simAssertion(doutB = std_logic_vector(to_unsigned(MIN_DEPTH-1, D_BITS)), "doutB != MIN_DEPTH-1"); - if (MIN_DEPTH > 4) then + if MIN_DEPTH > 4 then simAssertion(doutA = std_logic_vector(to_unsigned(MIN_DEPTH-6, D_BITS)), "doutA != MIN_DEPTH-6"); else simAssertion(doutA = std_logic_vector(to_unsigned(1, D_BITS)), "doutA != 0x01"); @@ -1053,7 +1053,7 @@ begin simAssertion(validB = '1', "validB != 1!"); simAssertion(fullB = '1', "fullB != 1!"); simAssertion(doutB = std_logic_vector(to_unsigned(175, D_BITS)), "doutB != 0xAF"); - if (MIN_DEPTH > 4) then + if MIN_DEPTH > 4 then simAssertion(doutA = std_logic_vector(to_unsigned(MIN_DEPTH-6, D_BITS)), "doutA != MIN_DEPTH-6"); else simAssertion(doutA = std_logic_vector(to_unsigned(1, D_BITS)), "doutA != 0x01"); @@ -1231,7 +1231,7 @@ begin simAssertion(validB = '1', "validB != 1!"); simAssertion(fullB = '1', "fullB != 1!"); simAssertion(doutA = std_logic_vector(to_unsigned(222, D_BITS)), "doutA != 0xDE"); - if (MIN_DEPTH > 4) then + if MIN_DEPTH > 4 then simAssertion(doutB = std_logic_vector(to_unsigned(MIN_DEPTH-5, D_BITS)), "doutB != MIN_DEPTH-5"); else simAssertion(doutB = std_logic_vector(to_unsigned(0, D_BITS)), "doutB != 0x00"); @@ -1244,7 +1244,7 @@ begin dinA <= std_logic_vector(to_unsigned(0, D_BITS)); putA <= '0'; simAssertion(doutA = std_logic_vector(to_unsigned(222, D_BITS)), "doutA != 0xDE"); - if (MIN_DEPTH > 4) then + if MIN_DEPTH > 4 then simAssertion(doutB = std_logic_vector(to_unsigned(MIN_DEPTH-5, D_BITS)), "doutB != MIN_DEPTH-5"); else simAssertion(doutB = std_logic_vector(to_unsigned(0, D_BITS)), "doutB != 0x00"); @@ -1255,7 +1255,7 @@ begin simAssertion(fullB = '1', "fullB != 1!"); cycle; simAssertion(doutA = std_logic_vector(to_unsigned(175, D_BITS)), "doutA != 0xAF"); - if (MIN_DEPTH > 4) then + if MIN_DEPTH > 4 then simAssertion(doutB = std_logic_vector(to_unsigned(MIN_DEPTH-5, D_BITS)), "doutB != MIN_DEPTH-5"); else simAssertion(doutB = std_logic_vector(to_unsigned(0, D_BITS)), "doutB != 0x00"); @@ -1274,7 +1274,7 @@ begin dinA <= std_logic_vector(to_unsigned(0, D_BITS)); gotB <= '0'; simAssertion(doutA = std_logic_vector(to_unsigned(175, D_BITS)), "doutB != 0xAF"); - if (MIN_DEPTH > 4) then + if MIN_DEPTH > 4 then simAssertion(doutB = std_logic_vector(to_unsigned(MIN_DEPTH-5, D_BITS)), "doutB != MIN_DEPTH-5"); else simAssertion(doutB = std_logic_vector(to_unsigned(0, D_BITS)), "doutB != 0x00"); @@ -1289,7 +1289,7 @@ begin simAssertion(validB = '1', "validB != 1!"); simAssertion(fullB = '1', "fullB != 1!"); simAssertion(doutA = std_logic_vector(to_unsigned(175, D_BITS)), "doutA != 0xAF"); - if (MIN_DEPTH > 4) then + if MIN_DEPTH > 4 then simAssertion(doutB = std_logic_vector(to_unsigned(MIN_DEPTH-7, D_BITS)), "doutB != MIN_DEPTH-7"); else simAssertion(doutB = std_logic_vector(to_unsigned(2, D_BITS)), "doutB != 0x02"); @@ -1473,7 +1473,7 @@ begin simAssertion(validA = '1', "validA != 1!"); simAssertion(fullB = '0', "fullB != 0!"); simAssertion(doutB = std_logic_vector(to_unsigned(MIN_DEPTH-3, D_BITS)), "doutB != MIN_DEPTH-3"); - if (MIN_DEPTH > 4) then + if MIN_DEPTH > 4 then simAssertion(doutA = std_logic_vector(to_unsigned(MIN_DEPTH-6, D_BITS)), "doutA != MIN_DEPTH-6"); simAssertion(validB = '1', "validB != 1!"); else @@ -1492,7 +1492,7 @@ begin putB <= '0'; putA <= '0'; simAssertion(doutB = std_logic_vector(to_unsigned(MIN_DEPTH-3, D_BITS)), "doutB != MIN_DEPTH-3"); - if (MIN_DEPTH > 4) then + if MIN_DEPTH > 4 then simAssertion(doutA = std_logic_vector(to_unsigned(MIN_DEPTH-6, D_BITS)), "doutA != MIN_DEPTH-6"); simAssertion(validB = '1', "validB != 1!"); else @@ -1722,7 +1722,7 @@ begin simAssertion(validB = '1', "validB != 1!"); simAssertion(fullB = '0', "fullB != 0!"); simAssertion(doutA = std_logic_vector(to_unsigned(222, D_BITS)), "doutB != 0xDE"); - if (MIN_DEPTH > 4) then + if MIN_DEPTH > 4 then simAssertion(doutB = std_logic_vector(to_unsigned(MIN_DEPTH-5, D_BITS)), "doutA != MIN_DEPTH-5"); else simAssertion(doutB = std_logic_vector(to_unsigned(0, D_BITS)), "doutB != 0x00"); @@ -1739,7 +1739,7 @@ begin putB <= '0'; putA <= '0'; simAssertion(doutA = std_logic_vector(to_unsigned(222, D_BITS)), "doutA != 0xDE"); - if (MIN_DEPTH > 4) then + if MIN_DEPTH > 4 then simAssertion(doutB = std_logic_vector(to_unsigned(MIN_DEPTH-5, D_BITS)), "doutB != MIN_DEPTH-5"); else simAssertion(doutB = std_logic_vector(to_unsigned(0, D_BITS)), "doutB != 0x00"); @@ -1778,7 +1778,7 @@ begin simAssertion(validB = '1', "validB != 1!"); simAssertion(fullB = '0', "fullB != 0!"); simAssertion(doutA = std_logic_vector(to_unsigned(222, D_BITS)), "doutB != 0xDE"); - if (MIN_DEPTH > 4) then + if MIN_DEPTH > 4 then simAssertion(doutB = std_logic_vector(to_unsigned(MIN_DEPTH-5, D_BITS)), "doutB != MIN_DEPTH-5"); else simAssertion(doutB = std_logic_vector(to_unsigned(0, D_BITS)), "doutB != 0x00"); @@ -1835,7 +1835,7 @@ begin simAssertion(fullA = '0', "fullA != 0!"); simAssertion(validA = '1', "validA != 1!"); simAssertion(validB = '1', "validB != 1!"); - if (MIN_DEPTH > 4) then + if MIN_DEPTH > 4 then simAssertion(fullB = '0', "fullB != 0!"); else simAssertion(fullB = '1', "fullB != 1!"); @@ -1852,7 +1852,7 @@ begin simAssertion(fullA = '0', "fullA != 0!"); simAssertion(validA = '1', "validA != 1!"); simAssertion(validB = '1', "validB != 1!"); - if (MIN_DEPTH > 4) then + if MIN_DEPTH > 4 then simAssertion(fullB = '0', "fullB != 0!"); else simAssertion(fullB = '1', "fullB != 1!"); @@ -1886,7 +1886,7 @@ begin simAssertion(fullA = '0', "fullA != 0!"); simAssertion(validA = '1', "validA != 1!"); simAssertion(validB = '1', "validB != 1!"); - if (MIN_DEPTH > 4) then + if MIN_DEPTH > 4 then simAssertion(fullB = '0', "fullB != 0!"); else simAssertion(fullB = '1', "fullB != 1!"); @@ -2057,7 +2057,7 @@ begin simAssertion(fullA = '0', "fullA != 0!"); simAssertion(validA = '1', "validA != 1!"); simAssertion(validB = '1', "validB != 1!"); - if (MIN_DEPTH > 4) then + if MIN_DEPTH > 4 then simAssertion(fullB = '0', "fullB != 0!"); else simAssertion(fullB = '1', "fullB != 1!"); @@ -2098,7 +2098,7 @@ begin simAssertion(fullA = '0', "fullA != 0!"); simAssertion(validA = '1', "validA != 1!"); simAssertion(validB = '1', "validB != 1!"); - if (MIN_DEPTH > 4) then + if MIN_DEPTH > 4 then simAssertion(fullB = '0', "fullB != 0!"); else simAssertion(fullB = '1', "fullB != 1!"); @@ -2207,7 +2207,7 @@ begin simAssertion(validA = '1', "validA != 1!"); simAssertion(validB = '1', "validB != 1!"); simAssertion(fullB = '1', "fullB != 1!"); - if (MIN_DEPTH > 4) then + if MIN_DEPTH > 4 then simAssertion(doutB = std_logic_vector(to_unsigned(MIN_DEPTH-5, D_BITS)), "doutB != MIN_DEPTH-5"); else simAssertion(doutB = std_logic_vector(to_unsigned(0, D_BITS)), "doutB != 0x00"); @@ -2382,7 +2382,7 @@ begin simAssertion(validB = '1', "validB != 1!"); simAssertion(fullB = '0', "fullB != 0!"); simAssertion(doutA = std_logic_vector(to_unsigned(222, D_BITS)), "doutA != 0xDE"); - if (MIN_DEPTH > 4) then + if MIN_DEPTH > 4 then simAssertion(doutB = std_logic_vector(to_unsigned(MIN_DEPTH-5, D_BITS)), "doutB != MIN_DEPTH-5"); else simAssertion(doutB = std_logic_vector(to_unsigned(0, D_BITS)), "doutB != 0x00"); @@ -2399,7 +2399,7 @@ begin dinB <= std_logic_vector(to_unsigned(0, D_BITS)); putB <= '0'; simAssertion(doutA = std_logic_vector(to_unsigned(222, D_BITS)), "doutA != 0xDE"); - if (MIN_DEPTH > 4) then + if MIN_DEPTH > 4 then simAssertion(doutB = std_logic_vector(to_unsigned(MIN_DEPTH-5, D_BITS)), "doutB != MIN_DEPTH-5"); else simAssertion(doutB = std_logic_vector(to_unsigned(0, D_BITS)), "doutB != 0x00"); @@ -2442,7 +2442,7 @@ begin simAssertion(validB = '1', "validB != 1!"); simAssertion(fullB = '0', "fullB != 0!"); simAssertion(doutA = std_logic_vector(to_unsigned(222, D_BITS)), "doutB != 0xDE"); - if (MIN_DEPTH > 4) then + if MIN_DEPTH > 4 then simAssertion(doutB = std_logic_vector(to_unsigned(MIN_DEPTH-5, D_BITS)), "doutB != MIN_DEPTH-5"); else simAssertion(doutB = std_logic_vector(to_unsigned(0, D_BITS)), "doutB != 0x00"); diff --git a/tb/fifo/fifo_cc_got_tb.vhdl b/tb/fifo/fifo_cc_got_tb.vhdl index 5508b84a..8a8585c1 100644 --- a/tb/fifo/fifo_cc_got_tb.vhdl +++ b/tb/fifo/fifo_cc_got_tb.vhdl @@ -72,7 +72,7 @@ begin constant STATE_REG : boolean := c mod 4 > 1; constant OUTPUT_REG : boolean := c mod 8 > 3; - constant simTestID : T_SIM_TEST_ID := simCreateTest("Test setup for DATA_REG=" & BOOLEAN'image(DATA_REG) & " STATE_REG=" & BOOLEAN'image(STATE_REG) & " OUTPUT_REG=" & BOOLEAN'image(OUTPUT_REG)); + constant simTestID : T_SIM_TEST_ID := simCreateTest("Test setup for DATA_REG=" & boolean'image(DATA_REG) & " STATE_REG=" & BOOLEAN'image(STATE_REG) & " OUTPUT_REG=" & boolean'image(OUTPUT_REG)); -- Local Component Ports signal put : std_logic; @@ -111,7 +111,7 @@ begin -- Writer procWriter : process - constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess(simTestID, "Writer for DATA_REG=" & BOOLEAN'image(DATA_REG) & " STATE_REG=" & BOOLEAN'image(STATE_REG) & " OUTPUT_REG=" & BOOLEAN'image(OUTPUT_REG)); + constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess(simTestID, "Writer for DATA_REG=" & boolean'image(DATA_REG) & " STATE_REG=" & BOOLEAN'image(STATE_REG) & " OUTPUT_REG=" & boolean'image(OUTPUT_REG)); begin din <= (others => '-'); put <= '0'; @@ -142,12 +142,12 @@ begin -- Reader procReader : process - constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess(simTestID, "Reader for DATA_REG=" & BOOLEAN'image(DATA_REG) & " STATE_REG=" & BOOLEAN'image(STATE_REG) & " OUTPUT_REG=" & BOOLEAN'image(OUTPUT_REG)); + constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess(simTestID, "Reader for DATA_REG=" & boolean'image(DATA_REG) & " STATE_REG=" & BOOLEAN'image(STATE_REG) & " OUTPUT_REG=" & boolean'image(OUTPUT_REG)); begin got <= '0'; for i in 0 to 2**D_BITS-1 loop wait until rising_edge(clk) and valid = '1'; - simAssertion((dout = std_logic_vector(to_unsigned(i, D_BITS))), "Output failure in configuration " & INTEGER'image(c) & " @ Pos " & INTEGER'image(i)); + simAssertion((dout = std_logic_vector(to_unsigned(i, D_BITS))), "Output failure in configuration " & integer'image(c) & " @ Pos " & INTEGER'image(i)); got <= '1'; wait until rising_edge(clk); got <= '0'; diff --git a/tb/fifo/fifo_cc_got_tempput_tb.vhdl b/tb/fifo/fifo_cc_got_tempput_tb.vhdl index a3418ccd..f44c7367 100644 --- a/tb/fifo/fifo_cc_got_tempput_tb.vhdl +++ b/tb/fifo/fifo_cc_got_tempput_tb.vhdl @@ -78,7 +78,7 @@ begin constant STATE_REG : boolean := c mod 4 > 1; constant OUTPUT_REG : boolean := c mod 8 > 3; - constant simTestID : T_SIM_TEST_ID := simCreateTest("Test setup for DATA_REG=" & BOOLEAN'image(DATA_REG) & " STATE_REG=" & BOOLEAN'image(STATE_REG) & " OUTPUT_REG=" & BOOLEAN'image(OUTPUT_REG)); + constant simTestID : T_SIM_TEST_ID := simCreateTest("Test setup for DATA_REG=" & boolean'image(DATA_REG) & " STATE_REG=" & BOOLEAN'image(STATE_REG) & " OUTPUT_REG=" & boolean'image(OUTPUT_REG)); signal put : std_logic; signal putx : std_logic; @@ -112,7 +112,7 @@ begin -- Writer procWriter : process - constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess(simTestID, "Writer for DATA_REG=" & BOOLEAN'image(DATA_REG) & " STATE_REG=" & BOOLEAN'image(STATE_REG) & " OUTPUT_REG=" & BOOLEAN'image(OUTPUT_REG)); + constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess(simTestID, "Writer for DATA_REG=" & boolean'image(DATA_REG) & " STATE_REG=" & BOOLEAN'image(STATE_REG) & " OUTPUT_REG=" & boolean'image(OUTPUT_REG)); begin wait until rising_edge(clk); @@ -187,7 +187,7 @@ begin -- Reader procReader : process - constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess(simTestID, "Reader for DATA_REG=" & BOOLEAN'image(DATA_REG) & " STATE_REG=" & BOOLEAN'image(STATE_REG) & " OUTPUT_REG=" & BOOLEAN'image(OUTPUT_REG)); + constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess(simTestID, "Reader for DATA_REG=" & boolean'image(DATA_REG) & " STATE_REG=" & BOOLEAN'image(STATE_REG) & " OUTPUT_REG=" & boolean'image(OUTPUT_REG)); begin for i in OSPEC'range loop case OSPEC(i) is @@ -198,7 +198,7 @@ begin when 'g' => got <= '1'; wait until rising_edge(clk) and vld = '1'; - simAssertion((do = dox), "Test #" & INTEGER'image(c) & ": Output Mismatch."); + simAssertion((do = dox), "Test #" & integer'image(c) & ": Output Mismatch."); when 'G' => got <= '1'; diff --git a/tb/io/ddrio/ddrio_in_tb.vhdl b/tb/io/ddrio/ddrio_in_tb.vhdl index eb516aaf..fceb9144 100644 --- a/tb/io/ddrio/ddrio_in_tb.vhdl +++ b/tb/io/ddrio/ddrio_in_tb.vhdl @@ -49,15 +49,15 @@ architecture sim of ddrio_in_tb is constant CLOCK_FREQ : FREQ := 100 MHz; -- component generics - constant BITS : POSITIVE := 2; - constant INIT_VALUE : BIT_VECTOR(1 downto 0) := "10"; + constant BITS : positive := 2; + constant INIT_VALUE : bit_vector(1 downto 0) := "10"; -- component ports - signal Clock : STD_LOGIC := '1'; - signal ClockEnable : STD_LOGIC := '0'; - signal DataIn_high : STD_LOGIC_VECTOR(BITS - 1 downto 0); - signal DataIn_low : STD_LOGIC_VECTOR(BITS - 1 downto 0); - signal Pad : STD_LOGIC_VECTOR(BITS - 1 downto 0); + signal Clock : std_logic := '1'; + signal ClockEnable : std_logic := '0'; + signal DataIn_high : std_logic_vector(BITS - 1 downto 0); + signal DataIn_low : std_logic_vector(BITS - 1 downto 0); + signal Pad : std_logic_vector(BITS - 1 downto 0); -- delay from "Clock" input to outputs of DUT -- must be less than CLOCK_PERIOD diff --git a/tb/io/ddrio/ddrio_inout_tb.vhdl b/tb/io/ddrio/ddrio_inout_tb.vhdl index 4ca98408..a79c1273 100644 --- a/tb/io/ddrio/ddrio_inout_tb.vhdl +++ b/tb/io/ddrio/ddrio_inout_tb.vhdl @@ -46,19 +46,19 @@ end entity; architecture sim of ddrio_inout_tb is -- component generics - constant BITS : POSITIVE := 2; + constant BITS : positive := 2; -- component ports - signal ClockOut : STD_LOGIC := '1'; - signal ClockOutEnable : STD_LOGIC := '0'; - signal OutputEnable : STD_LOGIC; - signal DataOut_high : STD_LOGIC_VECTOR(BITS - 1 downto 0); - signal DataOut_low : STD_LOGIC_VECTOR(BITS - 1 downto 0); - signal ClockIn : STD_LOGIC := '1'; - signal ClockInEnable : STD_LOGIC := '0'; - signal DataIn_high : STD_LOGIC_VECTOR(BITS - 1 downto 0); - signal DataIn_low : STD_LOGIC_VECTOR(BITS - 1 downto 0); - signal Pad : STD_LOGIC_VECTOR(BITS - 1 downto 0); + signal ClockOut : std_logic := '1'; + signal ClockOutEnable : std_logic := '0'; + signal OutputEnable : std_logic; + signal DataOut_high : std_logic_vector(BITS - 1 downto 0); + signal DataOut_low : std_logic_vector(BITS - 1 downto 0); + signal ClockIn : std_logic := '1'; + signal ClockInEnable : std_logic := '0'; + signal DataIn_high : std_logic_vector(BITS - 1 downto 0); + signal DataIn_low : std_logic_vector(BITS - 1 downto 0); + signal Pad : std_logic_vector(BITS - 1 downto 0); -- period of signal "ClockIn" constant CLOCK_IN_PERIOD : time := 12 ns; diff --git a/tb/io/ddrio/ddrio_out_tb.vhdl b/tb/io/ddrio/ddrio_out_tb.vhdl index 629f85f7..234d99f9 100644 --- a/tb/io/ddrio/ddrio_out_tb.vhdl +++ b/tb/io/ddrio/ddrio_out_tb.vhdl @@ -48,17 +48,17 @@ end entity; architecture sim of ddrio_out_tb is -- component generics - constant NO_OUTPUT_ENABLE : BOOLEAN := false; - constant BITS : POSITIVE := 2; - constant INIT_VALUE : BIT_VECTOR(1 downto 0) := "10"; + constant NO_OUTPUT_ENABLE : boolean := false; + constant BITS : positive := 2; + constant INIT_VALUE : bit_vector(1 downto 0) := "10"; -- component ports - signal Clock : STD_LOGIC := '1'; - signal ClockEnable : STD_LOGIC := '0'; - signal OutputEnable : STD_LOGIC := '0'; - signal DataOut_high : STD_LOGIC_VECTOR(BITS - 1 downto 0); - signal DataOut_low : STD_LOGIC_VECTOR(BITS - 1 downto 0); - signal Pad : STD_LOGIC_VECTOR(BITS - 1 downto 0); + signal Clock : std_logic := '1'; + signal ClockEnable : std_logic := '0'; + signal OutputEnable : std_logic := '0'; + signal DataOut_high : std_logic_vector(BITS - 1 downto 0); + signal DataOut_low : std_logic_vector(BITS - 1 downto 0); + signal Pad : std_logic_vector(BITS - 1 downto 0); -- period of signal "Clock" constant CLOCK_PERIOD : time := 10 ns; diff --git a/tb/io/io_Debounce_tb.vhdl b/tb/io/io_Debounce_tb.vhdl index 85dd4db6..ca64c9a0 100644 --- a/tb/io/io_Debounce_tb.vhdl +++ b/tb/io/io_Debounce_tb.vhdl @@ -53,16 +53,16 @@ architecture tb of io_Debounce_tb is constant CLOCK_FREQ : FREQ := 100 MHz; -- simulation signals - signal SimStop : STD_LOGIC := '0'; - signal Clock : STD_LOGIC := '1'; + signal SimStop : std_logic := '0'; + signal Clock : std_logic := '1'; - signal EventCounter : NATURAL := 0; + signal EventCounter : natural := 0; -- unit Under Test (UUT) configuration constant BOUNCE_TIME : T_TIME := 50.0e-9; - signal RawInput : STD_LOGIC := '0'; - signal deb_out : STD_LOGIC; + signal RawInput : std_logic := '0'; + signal deb_out : std_logic; begin -- initialize global simulation status @@ -107,7 +107,7 @@ begin RawInput <= '0'; -- final assertion - simAssertion((EventCounter = 6), "Events counted=" & INTEGER'image(EventCounter) & " Expected=6"); + simAssertion((EventCounter = 6), "Events counted=" & integer'image(EventCounter) & " Expected=6"); -- This process is finished simDeactivateProcess(simProcessID); diff --git a/tb/io/uart/uart_rx_tb.vhdl b/tb/io/uart/uart_rx_tb.vhdl index 540b6a42..bd0a76c1 100644 --- a/tb/io/uart/uart_rx_tb.vhdl +++ b/tb/io/uart/uart_rx_tb.vhdl @@ -53,19 +53,19 @@ architecture tb of uart_rx_tb is constant CLOCK_FREQ : FREQ := 100 MHz; constant BAUDRATE : BAUD := 2.1 MBd; - signal Clock : STD_LOGIC; - signal Reset : STD_LOGIC; + signal Clock : std_logic; + signal Reset : std_logic; - signal BitClock : STD_LOGIC; - signal BitClock_x8 : STD_LOGIC; + signal BitClock : std_logic; + signal BitClock_x8 : std_logic; - signal UART_RX : STD_LOGIC; + signal UART_RX : std_logic; - signal RX_Strobe : STD_LOGIC; + signal RX_Strobe : std_logic; signal RX_Data : T_SLV_8; function simGenerateWaveform_UART_Word(Data : T_SLV_8; Baudrate : BAUD := 115.200 kBd) return T_SIM_WAVEFORM_SL is - constant BIT_TIME : TIME := to_time(to_freq(Baudrate)); + constant BIT_TIME : time := to_time(to_freq(Baudrate)); variable Result : T_SIM_WAVEFORM_SL(0 to 9) := (others => (Delay => BIT_TIME, Value => '-')); begin Result(0).Value := '0'; @@ -120,7 +120,7 @@ begin for i in DATA_STREAM'range loop wait until rising_edge(Clock) and (RX_Strobe = '1'); -- report TIME'image(NOW) severity NOTE; - simAssertion((RX_Data = DATA_STREAM(i)), "Data Byte " & INTEGER'image(i) & " received: " & to_string(RX_Data, 'h') & " expected: " & to_string(DATA_STREAM(i), 'h')); + simAssertion((RX_Data = DATA_STREAM(i)), "Data Byte " & integer'image(i) & " received: " & to_string(RX_Data, 'h') & " expected: " & to_string(DATA_STREAM(i), 'h')); end loop; wait for 1 us; diff --git a/tb/mem/lut/lut_Sine_tb.vhdl b/tb/mem/lut/lut_Sine_tb.vhdl index 5a1d31e0..e66ad3ff 100644 --- a/tb/mem/lut/lut_Sine_tb.vhdl +++ b/tb/mem/lut/lut_Sine_tb.vhdl @@ -50,18 +50,18 @@ end entity; architecture test of lut_Sine_tb is constant CLOCK_FREQ : FREQ := 100 MHz; - signal Clock : STD_LOGIC := '1'; - signal sim_Stop : STD_LOGIC := '0'; - - signal lut_in : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); - signal lut_Q1_in : STD_LOGIC_VECTOR(7 downto 0); - signal lut_Q1_out : STD_LOGIC_VECTOR(7 downto 0); - signal lut_Q2_in : STD_LOGIC_VECTOR(7 downto 0); - signal lut_Q2_out : STD_LOGIC_VECTOR(7 downto 0); - signal lut_Q3_in : STD_LOGIC_VECTOR(7 downto 0); - signal lut_Q3_out : STD_LOGIC_VECTOR(7 downto 0); - signal lut_Q4_in : STD_LOGIC_VECTOR(7 downto 0); - signal lut_Q4_out : STD_LOGIC_VECTOR(7 downto 0); + signal Clock : std_logic := '1'; + signal sim_Stop : std_logic := '0'; + + signal lut_in : std_logic_vector(7 downto 0) := (others => '0'); + signal lut_Q1_in : std_logic_vector(7 downto 0); + signal lut_Q1_out : std_logic_vector(7 downto 0); + signal lut_Q2_in : std_logic_vector(7 downto 0); + signal lut_Q2_out : std_logic_vector(7 downto 0); + signal lut_Q3_in : std_logic_vector(7 downto 0); + signal lut_Q3_out : std_logic_vector(7 downto 0); + signal lut_Q4_in : std_logic_vector(7 downto 0); + signal lut_Q4_out : std_logic_vector(7 downto 0); begin -- initialize global simulation status diff --git a/tb/mem/ocram/ocram_esdp_tb.files b/tb/mem/ocram/ocram_esdp_tb.files new file mode 100644 index 00000000..848d8864 --- /dev/null +++ b/tb/mem/ocram/ocram_esdp_tb.files @@ -0,0 +1,11 @@ +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# ============================================================================== +# Note: all files are relative to PoC root directory +# +# PoC.mem.ocram +include "src/mem/ocram/ocram_esdp.files" # Unit Under Test + +# Testbench files +vhdl test "tb/mem/ocram/ocram_esdp_tb.vhdl" # Testbench diff --git a/tb/mem/ocram/ocram_esdp_tb.vhdl b/tb/mem/ocram/ocram_esdp_tb.vhdl new file mode 100644 index 00000000..853304d8 --- /dev/null +++ b/tb/mem/ocram/ocram_esdp_tb.vhdl @@ -0,0 +1,207 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- +-- ============================================================================= +-- Authors: Martin Zabel +-- +-- Testbench: On-Chip-RAM: Enhanced Simple-Dual-Port (ESDP). +-- +-- Description: +-- ------------------------------------ +-- Automated testbench for PoC.mem.ocram.esdp +-- +-- License: +-- ============================================================================= +-- Copyright 2007-2016 Technische Universitaet Dresden - Germany +-- Chair for VLSI-Design, Diagnostics and Architecture +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +library PoC; +use PoC.utils.all; +use PoC.physical.all; +-- simulation only packages +use PoC.sim_types.all; +use PoC.simulation.all; +use PoC.waveform.all; + + +entity ocram_esdp_tb is +end entity; + +architecture tb of ocram_esdp_tb is + constant CLOCK_FREQ : FREQ := 100 MHz; + + -- clock + signal clk : std_logic; + + -- component generics + -- Set to values used for synthesis when simulating a netlist. + constant A_BITS : positive := 10; + constant D_BITS : positive := 32; + + -- component ports + signal ce1 : std_logic; + signal ce2 : std_logic; + signal we1 : std_logic; + signal a1 : unsigned(A_BITS-1 downto 0); + signal a2 : unsigned(A_BITS-1 downto 0); + signal d1 : std_logic_vector(D_BITS-1 downto 0); + signal q1 : std_logic_vector(D_BITS-1 downto 0); + signal q2 : std_logic_vector(D_BITS-1 downto 0); + + -- Expected read data, assign together with read command + signal rd_d1 : std_logic_vector(D_BITS-1 downto 0); + signal rd_d2 : std_logic_vector(D_BITS-1 downto 0); + + -- Derived expected output on q1 / q2. + signal exp_q1 : std_logic_vector(D_BITS-1 downto 0) := (others => '-'); + signal exp_q2 : std_logic_vector(D_BITS-1 downto 0) := (others => '-'); + + -- Signaling between Stimuli and Checker process + signal finished : boolean := false; + +begin + -- initialize global simulation status + simInitialize; + -- generate global testbench clock + simGenerateClock(clk, CLOCK_FREQ); + + -- component instantiation + DUT: entity poc.ocram_esdp + generic map ( + A_BITS => A_BITS, + D_BITS => D_BITS, + FILENAME => "") + port map ( + clk1 => clk, + clk2 => clk, + ce1 => ce1, + ce2 => ce2, + we1 => we1, + a1 => a1, + a2 => a2, + d1 => d1, + q1 => q1, + q2 => q2); + + -- waveform generation + Stimuli: process + constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess("Stimuli process"); + begin + -- No operation on first rising clock edge + ce1 <= '0'; + we1 <= '-'; + a1 <= (others => '-'); + d1 <= (others => '-'); + rd_d1 <= (others => '-'); + ce2 <= '0'; + a2 <= (others => '-'); + rd_d2 <= (others => '-'); + + ------------------------------------------------------------------------- + -- Write in 8 consecutive clock cycles, read one cycle later + + for i in 0 to 7 loop + simWaitUntilRisingEdge(clk, 1); + ce1 <= '1'; + we1 <= '1'; + a1 <= to_unsigned(i, a1'length); + d1 <= std_logic_vector(to_unsigned(i, d1'length)); + rd_d1 <= std_logic_vector(to_unsigned(i, d1'length)); + + -- read is delayed by one clock cycle + ce2 <= ce1; + a2 <= a1; + rd_d2 <= d1; -- data to be read + end loop; + + simWaitUntilRisingEdge(clk, 1); + ce1 <= '0'; + we1 <= '0'; + a1 <= (others => '-'); + rd_d1 <= (others => '-'); + + -- last read is delayed by one clock cycle + ce2 <= ce1; + a2 <= a1; + rd_d2 <= d1; -- data to be read + + ------------------------------------------------------------------------- + -- Alternating write / read + for i in 8 to 15 loop + simWaitUntilRisingEdge(clk, 1); + ce1 <= not ce1; -- write @ even addresses + we1 <= '1'; + a1 <= to_unsigned(i, a1'length); + d1 <= std_logic_vector(to_unsigned(i, d1'length)); + rd_d1 <= std_logic_vector(to_unsigned(i, d1'length)); + + -- read is delayed by one clock cycle + ce2 <= ce1; + a2 <= a1; + rd_d2 <= d1; -- data to be read + end loop; + + simWaitUntilRisingEdge(clk, 1); + ce1 <= '0'; + we1 <= '0'; + a1 <= (others => '-'); + rd_d1 <= (others => '-'); + + -- last read is delayed by one clock cycle + ce2 <= ce1; + a2 <= a1; + rd_d2 <= d1; -- data to be read + + ------------------------------------------------------------------------- + -- Finish + simWaitUntilRisingEdge(clk, 1); + ce2 <= '0'; + a2 <= (others => '-'); + + finished <= true; + + -- This process is finished + simDeactivateProcess(simProcessID); + wait; -- forever + end process Stimuli; + + -- Also checks if old value is kept if ce1 = '0' + exp_q1 <= rd_d1 when rising_edge(clk) and ce1 = '1'; + + -- Also checks if old value is kept if ce2 = '0' + exp_q2 <= rd_d2 when rising_edge(clk) and ce2 = '1'; + + Checker: process + constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess("Checker process"); + variable i : integer; + begin + while not finished loop + simWaitUntilRisingEdge(clk, 1); + simAssertion(std_match(q1, exp_q1)); + simAssertion(std_match(q2, exp_q2)); + end loop; + + -- This process is finished + simDeactivateProcess(simProcessID); + wait; -- forever + end process Checker; + +end architecture; diff --git a/tb/mem/ocram/ocram_sp_tb.files b/tb/mem/ocram/ocram_sp_tb.files new file mode 100644 index 00000000..49142dcd --- /dev/null +++ b/tb/mem/ocram/ocram_sp_tb.files @@ -0,0 +1,11 @@ +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# ============================================================================== +# Note: all files are relative to PoC root directory +# +# PoC.mem.ocram +include "src/mem/ocram/ocram_sp.files" # Unit Under Test + +# Testbench files +vhdl test "tb/mem/ocram/ocram_sp_tb.vhdl" # Testbench diff --git a/tb/mem/ocram/ocram_sp_tb.vhdl b/tb/mem/ocram/ocram_sp_tb.vhdl new file mode 100644 index 00000000..ea4b8285 --- /dev/null +++ b/tb/mem/ocram/ocram_sp_tb.vhdl @@ -0,0 +1,163 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- ============================================================================= +-- Authors: Martin Zabel +-- Patrick Lehmann +-- +-- Testbench: Testbench for ocram_sp. +-- +-- Description: +-- ------------------------------------- +-- +-- License: +-- ============================================================================= +-- Copyright 2016-2016 Technische Universitaet Dresden - Germany +-- Chair for VLSI-Design, Diagnostics and Architecture +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library PoC; +use PoC.physical.all; +-- simulation specific packages +use PoC.sim_types.all; +use PoC.simulation.all; +use PoC.waveform.all; + +entity ocram_sp_tb is +end entity ocram_sp_tb; + +architecture sim of ocram_sp_tb is + constant A_BITS : positive := 8; + constant D_BITS : positive := A_BITS; -- for test pattern + + signal clk : std_logic := '1'; + signal ce : std_logic; + signal we : std_logic; + signal a : unsigned(A_BITS-1 downto 0); + signal d : std_logic_vector(D_BITS-1 downto 0); + signal q : std_logic_vector(D_BITS-1 downto 0); + +begin -- architecture sim + + uut: entity PoC.ocram_sp + generic map ( + A_BITS => A_BITS, + D_BITS => D_BITS, + FILENAME => "") + port map ( + clk => clk, + ce => ce, + we => we, + a => a, + d => d, + q => q); + + -- initialize global simulation status + simInitialize; + -- generate global testbench clock + simGenerateClock(clk, 100 MHz); + + Stimuli: process + constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess("Stimuli process"); + begin + -- 1) Fill memory and check read-during-write behavior + -- =================================================== + ce <= '1'; + we <= '1'; + a <= to_unsigned(0, a'length); + d <= std_logic_vector(to_unsigned(0, a'length)); + wait until rising_edge(clk); + + for addr in 1 to 2**A_BITS-1 loop + ce <= '1'; + we <= '1'; + a <= to_unsigned(addr, a'length); + d <= std_logic_vector(to_unsigned(addr, a'length)); + wait until rising_edge(clk); + -- At this clock edge, we can check the result of the preceding access. + -- Check read-during write behavior. + simAssertion(q = std_logic_vector(to_unsigned(addr-1, a'length)), + "Wrong read data during write to address:" & integer'image(addr-1)); + end loop; -- i + + ce <= '0'; + we <= '-'; + wait until rising_edge(clk); + -- At this clock edge, we can check the result of the last access. + -- Check read-during write behavior. + simAssertion(q = std_logic_vector(to_unsigned(2**A_BITS-1, a'length)), + "Wrong read data during write to address:" & integer'image(2**A_BITS-1)); + + -- 2) Read back + -- ============ + ce <= '1'; + we <= '0'; + a <= to_unsigned(0, a'length); + wait until rising_edge(clk); + + for addr in 1 to 2**A_BITS-1 loop + ce <= '1'; + we <= '0'; + a <= to_unsigned(addr, a'length); + d <= (others => '-'); + wait until rising_edge(clk); + -- At this clock edge, we can check the result of the preceding access. + simAssertion(q = std_logic_vector(to_unsigned(addr-1, a'length)), + "Wrong read data from address:" & integer'image(addr-1)); + end loop; -- i + + ce <= '0'; + we <= '-'; + wait until rising_edge(clk); + -- At this clock edge, we can check the result of the last access. + simAssertion(q = std_logic_vector(to_unsigned(2**A_BITS-1, a'length)), + "Wrong read data from address:" & integer'image(2**A_BITS-1)); + + -- 3) Read back in reverse order + -- ============================= + ce <= '1'; + we <= '0'; + a <= to_unsigned(2**A_BITS-1, a'length); + wait until rising_edge(clk); + + for addr in 2**A_BITS-2 downto 0 loop + ce <= '1'; + we <= '0'; + a <= to_unsigned(addr, a'length); + d <= (others => '-'); + wait until rising_edge(clk); + -- At this clock edge, we can check the result of the preceding access. + simAssertion(q = std_logic_vector(to_unsigned(addr+1, a'length)), + "Wrong read data from address:" & integer'image(addr-1)); + end loop; -- i + + ce <= '0'; + we <= '-'; + wait until rising_edge(clk); + -- At this clock edge, we can check the result of the last access. + simAssertion(q = std_logic_vector(to_unsigned(0, a'length)), + "Wrong read data from address:" & integer'image(0)); + + + -- This process is finished + simDeactivateProcess(simProcessID); + wait; -- forever + end process; + +end architecture sim; diff --git a/tb/mem/ocram/ocram_tdp_tb.files b/tb/mem/ocram/ocram_tdp_tb.files new file mode 100644 index 00000000..0371b8e8 --- /dev/null +++ b/tb/mem/ocram/ocram_tdp_tb.files @@ -0,0 +1,11 @@ +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# ============================================================================== +# Note: all files are relative to PoC root directory +# +# PoC.mem.ocram +include "src/mem/ocram/ocram_tdp.files" # Unit Under Test + +# Testbench files +vhdl test "tb/mem/ocram/ocram_tdp_tb.vhdl" # Testbench diff --git a/tb/mem/ocram/ocram_tdp_tb.vhdl b/tb/mem/ocram/ocram_tdp_tb.vhdl new file mode 100644 index 00000000..5c99222e --- /dev/null +++ b/tb/mem/ocram/ocram_tdp_tb.vhdl @@ -0,0 +1,286 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- +-- ============================================================================= +-- Authors: Martin Zabel +-- +-- Testbench: On-Chip-RAM: True Dual-Port (TDP). +-- +-- Description: +-- ------------------------------------ +-- Automated testbench for PoC.mem.ocram.tdp +-- +-- License: +-- ============================================================================= +-- Copyright 2007-2016 Technische Universitaet Dresden - Germany +-- Chair for VLSI-Design, Diagnostics and Architecture +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +library PoC; +use PoC.utils.all; +use PoC.physical.all; +-- simulation only packages +use PoC.sim_types.all; +use PoC.simulation.all; +use PoC.waveform.all; + + +entity ocram_tdp_tb is +end entity; + +architecture tb of ocram_tdp_tb is + constant CLOCK_FREQ : FREQ := 100 MHz; + + -- clock + signal clk : std_logic; + + -- component generics + -- Set to values used for synthesis when simulating a netlist. + constant A_BITS : positive := 10; + constant D_BITS : positive := 32; + + -- component ports + signal ce1 : std_logic; + signal ce2 : std_logic; + signal we1 : std_logic; + signal we2 : std_logic; + signal a1 : unsigned(A_BITS-1 downto 0); + signal a2 : unsigned(A_BITS-1 downto 0); + signal d1 : std_logic_vector(D_BITS-1 downto 0); + signal d2 : std_logic_vector(D_BITS-1 downto 0); + signal q1 : std_logic_vector(D_BITS-1 downto 0); + signal q2 : std_logic_vector(D_BITS-1 downto 0); + + -- Expected read data, assign together with read command + signal rd_d1 : std_logic_vector(D_BITS-1 downto 0); + signal rd_d2 : std_logic_vector(D_BITS-1 downto 0); + + -- Derived expected output on q1 / q2. + signal exp_q1 : std_logic_vector(D_BITS-1 downto 0) := (others => '-'); + signal exp_q2 : std_logic_vector(D_BITS-1 downto 0) := (others => '-'); + + -- Signaling between Stimuli and Checker process + signal finished : boolean := false; + +begin + -- initialize global simulation status + simInitialize; + -- generate global testbench clock + simGenerateClock(clk, CLOCK_FREQ); + + -- component instantiation + DUT: entity poc.ocram_tdp + generic map ( + A_BITS => A_BITS, + D_BITS => D_BITS, + FILENAME => "") + port map ( + clk1 => clk, + clk2 => clk, + ce1 => ce1, + ce2 => ce2, + we1 => we1, + we2 => we2, + a1 => a1, + a2 => a2, + d1 => d1, + d2 => d2, + q1 => q1, + q2 => q2); + + -- waveform generation + Stimuli: process + constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess("Stimuli process"); + begin + -- No operation on first rising clock edge + ce1 <= '0'; + we1 <= '-'; + a1 <= (others => '-'); + d1 <= (others => '-'); + rd_d1 <= (others => '-'); + ce2 <= '0'; + we2 <= '-'; + a2 <= (others => '-'); + d2 <= (others => '-'); + rd_d2 <= (others => '-'); + + ------------------------------------------------------------------------- + -- Write in 8 consecutive clock cycles on port 1, read one cycle later on + -- port 2 + + for i in 0 to 7 loop + simWaitUntilRisingEdge(clk, 1); + ce1 <= '1'; + we1 <= '1'; + a1 <= to_unsigned(i, a1'length); + d1 <= std_logic_vector(to_unsigned(i, d1'length)); + rd_d1 <= std_logic_vector(to_unsigned(i, d1'length)); + + -- read is delayed by one clock cycle + ce2 <= ce1; + we2 <= '0'; + a2 <= a1; + rd_d2 <= d1; -- data to be read + end loop; + + simWaitUntilRisingEdge(clk, 1); + ce1 <= '0'; + we1 <= '0'; + a1 <= (others => '-'); + rd_d1 <= (others => '-'); + + -- last read is delayed by one clock cycle + ce2 <= ce1; + we2 <= '0'; + a2 <= a1; + rd_d2 <= d1; -- data to be read + + ------------------------------------------------------------------------- + -- Alternating write on port 1 / read on port 2 + for i in 8 to 15 loop + simWaitUntilRisingEdge(clk, 1); + ce1 <= not ce1; -- write @ even addresses + we1 <= '1'; + a1 <= to_unsigned(i, a1'length); + d1 <= std_logic_vector(to_unsigned(i, d1'length)); + rd_d1 <= std_logic_vector(to_unsigned(i, d1'length)); + + -- read is delayed by one clock cycle + ce2 <= ce1; + we2 <= '0'; + a2 <= a1; + rd_d2 <= d1; -- data to be read + end loop; + + simWaitUntilRisingEdge(clk, 1); + ce1 <= '0'; + we1 <= '0'; + a1 <= (others => '-'); + rd_d1 <= (others => '-'); + + -- last read is delayed by one clock cycle + ce2 <= ce1; + we2 <= '0'; + a2 <= a1; + rd_d2 <= d1; -- data to be read + + simWaitUntilRisingEdge(clk, 1); + ce2 <= '0'; + we2 <= '-'; + a2 <= (others => '-'); + rd_d2 <= (others => '-'); + + ------------------------------------------------------------------------- + -- Write in 8 consecutive clock cycles on port 2, read one cycle later on + -- port 1 + + for i in 16 to 23 loop + simWaitUntilRisingEdge(clk, 1); + ce2 <= '1'; + we2 <= '1'; + a2 <= to_unsigned(i, a1'length); + d2 <= std_logic_vector(to_unsigned(i, d1'length)); + rd_d2 <= std_logic_vector(to_unsigned(i, d1'length)); + + -- read is delayed by one clock cycle + ce1 <= ce2; + we1 <= '0'; + a1 <= a2; + rd_d1 <= d2; -- data to be read + end loop; + + simWaitUntilRisingEdge(clk, 1); + ce2 <= '0'; + we2 <= '0'; + a2 <= (others => '-'); + rd_d2 <= (others => '-'); + + -- last read is delayed by one clock cycle + ce1 <= ce2; + we1 <= '0'; + a1 <= a2; + rd_d1 <= d2; -- data to be read + + ------------------------------------------------------------------------- + -- Alternating write on port 2 / read on port 1 + for i in 24 to 31 loop + simWaitUntilRisingEdge(clk, 1); + ce2 <= not ce2; -- write @ even addresses + we2 <= '1'; + a2 <= to_unsigned(i, a1'length); + d2 <= std_logic_vector(to_unsigned(i, d1'length)); + rd_d2 <= std_logic_vector(to_unsigned(i, d1'length)); + + -- read is delayed by one clock cycle + ce1 <= ce2; + we1 <= '0'; + a1 <= a2; + rd_d1 <= d2; -- data to be read + end loop; + + simWaitUntilRisingEdge(clk, 1); + ce2 <= '0'; + we2 <= '0'; + a2 <= (others => '-'); + rd_d2 <= (others => '-'); + + -- last read is delayed by one clock cycle + ce1 <= ce2; + we1 <= '0'; + a1 <= a2; + rd_d1 <= d2; -- data to be read + + simWaitUntilRisingEdge(clk, 1); + ce1 <= '0'; + we1 <= '-'; + a1 <= (others => '-'); + rd_d1 <= (others => '-'); + + ------------------------------------------------------------------------- + -- Finish + finished <= true; + + -- This process is finished + simDeactivateProcess(simProcessID); + wait; -- forever + end process Stimuli; + + -- Also checks if old value is kept if ce1 = '0' + exp_q1 <= rd_d1 when rising_edge(clk) and ce1 = '1'; + + -- Also checks if old value is kept if ce2 = '0' + exp_q2 <= rd_d2 when rising_edge(clk) and ce2 = '1'; + + Checker: process + constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess("Checker process"); + variable i : integer; + begin + while not finished loop + simWaitUntilRisingEdge(clk, 1); + simAssertion(std_match(q1, exp_q1)); + simAssertion(std_match(q2, exp_q2)); + end loop; + + -- This process is finished + simDeactivateProcess(simProcessID); + wait; -- forever + end process Checker; + +end architecture; diff --git a/tb/misc/gearbox/gearbox_down_cc_tb.vhdl b/tb/misc/gearbox/gearbox_down_cc_tb.vhdl index 5c3063d8..619817d1 100644 --- a/tb/misc/gearbox/gearbox_down_cc_tb.vhdl +++ b/tb/misc/gearbox/gearbox_down_cc_tb.vhdl @@ -53,16 +53,16 @@ end entity; architecture tb of gearbox_down_cc_tb is type T_TUPLE is record - InputBits : POSITIVE; - OutputBits : POSITIVE; + InputBits : positive; + OutputBits : positive; end record; - type T_TUPLE_VECTOR is array(NATURAL range <>) of T_TUPLE; + type T_TUPLE_VECTOR is array(natural range <>) of T_TUPLE; constant TB_GENERATOR_LIST : T_TUPLE_VECTOR := ((32, 8), (20, 8), (36, 8), (66, 64), (128, 12)); constant CLOCK_FREQ : FREQ := 100 MHz; - signal Clock : STD_LOGIC := '1'; + signal Clock : std_logic := '1'; begin -- initialize global simulation status @@ -72,21 +72,21 @@ begin genInstances : for i in TB_GENERATOR_LIST'range generate - constant INPUT_BITS : POSITIVE := TB_GENERATOR_LIST(i).InputBits; - constant OUTPUT_BITS : POSITIVE := TB_GENERATOR_LIST(i).OutputBits; + constant INPUT_BITS : positive := TB_GENERATOR_LIST(i).InputBits; + constant OUTPUT_BITS : positive := TB_GENERATOR_LIST(i).OutputBits; constant OUTPUT_ORDER : T_BIT_ORDER := MSB_FIRST; - constant ADD_INPUT_REGISTERS : BOOLEAN := TRUE; - constant ADD_OUTPUT_REGISTERS : BOOLEAN := FALSE; + constant ADD_INPUT_REGISTERS : boolean := TRUE; + constant ADD_OUTPUT_REGISTERS : boolean := FALSE; - constant BITS_PER_CHUNK : POSITIVE := greatestCommonDivisor(INPUT_BITS, OUTPUT_BITS); - constant INPUT_CHUNKS : POSITIVE := INPUT_BITS / BITS_PER_CHUNK; - constant OUTPUT_CHUNKS : POSITIVE := OUTPUT_BITS / BITS_PER_CHUNK; + constant BITS_PER_CHUNK : positive := greatestCommonDivisor(INPUT_BITS, OUTPUT_BITS); + constant INPUT_CHUNKS : positive := INPUT_BITS / BITS_PER_CHUNK; + constant OUTPUT_CHUNKS : positive := OUTPUT_BITS / BITS_PER_CHUNK; - subtype T_CHUNK is STD_LOGIC_VECTOR(BITS_PER_CHUNK - 1 downto 0); - type T_CHUNK_VECTOR is array(NATURAL range <>) of T_CHUNK; + subtype T_CHUNK is std_logic_vector(BITS_PER_CHUNK - 1 downto 0); + type T_CHUNK_VECTOR is array(natural range <>) of T_CHUNK; - function to_slv(slvv : T_CHUNK_VECTOR) return STD_LOGIC_VECTOR is - variable slv : STD_LOGIC_VECTOR((slvv'length * BITS_PER_CHUNK) - 1 downto 0); + function to_slv(slvv : T_CHUNK_VECTOR) return std_logic_vector is + variable slv : std_logic_vector((slvv'length * BITS_PER_CHUNK) - 1 downto 0); begin for i in slvv'range loop slv(((i + 1) * BITS_PER_CHUNK) - 1 downto (i * BITS_PER_CHUNK)) := slvv(i); @@ -94,29 +94,29 @@ begin return slv; end function; - constant LOOP_COUNT : POSITIVE := 64; - constant DELAY : POSITIVE := 16; + constant LOOP_COUNT : positive := 64; + constant DELAY : positive := 16; - signal SyncIn : STD_LOGIC; - signal ValidIn : STD_LOGIC; - signal DataIn : STD_LOGIC_VECTOR(INPUT_BITS - 1 downto 0); + signal SyncIn : std_logic; + signal ValidIn : std_logic; + signal DataIn : std_logic_vector(INPUT_BITS - 1 downto 0); - signal SyncOut : STD_LOGIC; - signal ValidOut : STD_LOGIC; - signal DataOut : STD_LOGIC_VECTOR(OUTPUT_BITS - 1 downto 0); - signal FirstOut : STD_LOGIC; - signal LastOut : STD_LOGIC; + signal SyncOut : std_logic; + signal ValidOut : std_logic; + signal DataOut : std_logic_vector(OUTPUT_BITS - 1 downto 0); + signal FirstOut : std_logic; + signal LastOut : std_logic; - constant simTestID : T_SIM_TEST_ID := simCreateTest("Test setup for " & INTEGER'image(INPUT_BITS) & "->" & INTEGER'image(OUTPUT_BITS)); + constant simTestID : T_SIM_TEST_ID := simCreateTest("Test setup for " & integer'image(INPUT_BITS) & "->" & INTEGER'image(OUTPUT_BITS)); begin procGenerator : process -- from Simulation - constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess(simTestID, "Generator " & INTEGER'image(i) & " for " & INTEGER'image(INPUT_BITS) & "->" & INTEGER'image(OUTPUT_BITS)); --, "aaa/bbb/ccc"); --globalSimulationStatus'instance_name); + constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess(simTestID, "Generator " & integer'image(i) & " for " & INTEGER'image(INPUT_BITS) & "->" & integer'image(OUTPUT_BITS)); --, "aaa/bbb/ccc"); --globalSimulationStatus'instance_name); -- protected type from RandomPkg variable RandomVar : RandomPType; - impure function genChunkedRandomValue return STD_LOGIC_VECTOR is + impure function genChunkedRandomValue return std_logic_vector is variable Temp : T_CHUNK_VECTOR(INPUT_CHUNKS - 1 downto 0); begin for j in 0 to INPUT_CHUNKS - 1 loop @@ -197,8 +197,8 @@ begin ); procChecker : process - constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess(simTestID, "Checker " & INTEGER'image(i) & " for " & INTEGER'image(INPUT_BITS) & "->" & INTEGER'image(OUTPUT_BITS)); - variable Check : BOOLEAN; + constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess(simTestID, "Checker " & integer'image(i) & " for " & INTEGER'image(INPUT_BITS) & "->" & integer'image(OUTPUT_BITS)); + variable Check : boolean; begin Check := TRUE; diff --git a/tb/misc/gearbox/gearbox_down_dc_tb.vhdl b/tb/misc/gearbox/gearbox_down_dc_tb.vhdl index fb30670e..e51a17dc 100644 --- a/tb/misc/gearbox/gearbox_down_dc_tb.vhdl +++ b/tb/misc/gearbox/gearbox_down_dc_tb.vhdl @@ -53,10 +53,10 @@ end entity; architecture tb of gearbox_down_dc_tb is type T_TUPLE is record - InputBits : POSITIVE; - OutputBits : POSITIVE; + InputBits : positive; + OutputBits : positive; end record; - type T_TUPLE_VECTOR is array(NATURAL range <>) of T_TUPLE; + type T_TUPLE_VECTOR is array(natural range <>) of T_TUPLE; constant TB_GENERATOR_LIST : T_TUPLE_VECTOR := ((32, 8), (128, 8)); @@ -65,23 +65,23 @@ begin simInitialize; genInstances : for i in TB_GENERATOR_LIST'range generate - constant INPUT_BITS : POSITIVE := TB_GENERATOR_LIST(i).InputBits; - constant OUTPUT_BITS : POSITIVE := TB_GENERATOR_LIST(i).OutputBits; + constant INPUT_BITS : positive := TB_GENERATOR_LIST(i).InputBits; + constant OUTPUT_BITS : positive := TB_GENERATOR_LIST(i).OutputBits; constant OUTPUT_ORDER : T_BIT_ORDER := MSB_FIRST; - constant ADD_INPUT_REGISTERS : BOOLEAN := TRUE; - constant ADD_OUTPUT_REGISTERS : BOOLEAN := TRUE; + constant ADD_INPUT_REGISTERS : boolean := TRUE; + constant ADD_OUTPUT_REGISTERS : boolean := TRUE; - constant RATIO : POSITIVE := INPUT_BITS / OUTPUT_BITS; + constant RATIO : positive := INPUT_BITS / OUTPUT_BITS; - constant BITS_PER_CHUNK : POSITIVE := greatestCommonDivisor(INPUT_BITS, OUTPUT_BITS); - constant INPUT_CHUNKS : POSITIVE := INPUT_BITS / BITS_PER_CHUNK; - constant OUTPUT_CHUNKS : POSITIVE := OUTPUT_BITS / BITS_PER_CHUNK; + constant BITS_PER_CHUNK : positive := greatestCommonDivisor(INPUT_BITS, OUTPUT_BITS); + constant INPUT_CHUNKS : positive := INPUT_BITS / BITS_PER_CHUNK; + constant OUTPUT_CHUNKS : positive := OUTPUT_BITS / BITS_PER_CHUNK; - subtype T_CHUNK is STD_LOGIC_VECTOR(BITS_PER_CHUNK - 1 downto 0); - type T_CHUNK_VECTOR is array(NATURAL range <>) of T_CHUNK; + subtype T_CHUNK is std_logic_vector(BITS_PER_CHUNK - 1 downto 0); + type T_CHUNK_VECTOR is array(natural range <>) of T_CHUNK; - function to_slv(slvv : T_CHUNK_VECTOR) return STD_LOGIC_VECTOR is - variable slv : STD_LOGIC_VECTOR((slvv'length * BITS_PER_CHUNK) - 1 downto 0); + function to_slv(slvv : T_CHUNK_VECTOR) return std_logic_vector is + variable slv : std_logic_vector((slvv'length * BITS_PER_CHUNK) - 1 downto 0); begin for i in slvv'range loop slv(((i + 1) * BITS_PER_CHUNK) - 1 downto (i * BITS_PER_CHUNK)) := slvv(i); @@ -89,18 +89,18 @@ begin return slv; end function; - constant LOOP_COUNT : POSITIVE := 8; - constant DELAY : POSITIVE := 5; + constant LOOP_COUNT : positive := 8; + constant DELAY : positive := 5; - constant CLOCK2_PERIOD : TIME := 10 ns; - constant CLOCK1_PERIOD : TIME := CLOCK2_PERIOD * RATIO; - signal Clock1 : STD_LOGIC := '1'; - signal Clock2 : STD_LOGIC := '1'; + constant CLOCK2_PERIOD : time := 10 ns; + constant CLOCK1_PERIOD : time := CLOCK2_PERIOD * RATIO; + signal Clock1 : std_logic := '1'; + signal Clock2 : std_logic := '1'; - signal DataIn : STD_LOGIC_VECTOR(INPUT_BITS - 1 downto 0); - signal DataOut : STD_LOGIC_VECTOR(OUTPUT_BITS - 1 downto 0); + signal DataIn : std_logic_vector(INPUT_BITS - 1 downto 0); + signal DataOut : std_logic_vector(OUTPUT_BITS - 1 downto 0); - constant simTestID : T_SIM_TEST_ID := simCreateTest("Test setup for " & INTEGER'image(INPUT_BITS) & "->" & INTEGER'image(OUTPUT_BITS)); + constant simTestID : T_SIM_TEST_ID := simCreateTest("Test setup for " & integer'image(INPUT_BITS) & "->" & INTEGER'image(OUTPUT_BITS)); begin -- generate global testbench clock @@ -109,11 +109,11 @@ begin procGenerator : process -- from Simulation - constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess(simTestID, "Generator " & INTEGER'image(i) & " for " & INTEGER'image(INPUT_BITS) & "->" & INTEGER'image(OUTPUT_BITS)); --, "aaa/bbb/ccc"); --globalSimulationStatus'instance_name); + constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess(simTestID, "Generator " & integer'image(i) & " for " & INTEGER'image(INPUT_BITS) & "->" & integer'image(OUTPUT_BITS)); --, "aaa/bbb/ccc"); --globalSimulationStatus'instance_name); -- protected type from RandomPkg variable RandomVar : RandomPType; - impure function genChunkedRandomValue return STD_LOGIC_VECTOR is + impure function genChunkedRandomValue return std_logic_vector is variable Temp : T_CHUNK_VECTOR(INPUT_CHUNKS - 1 downto 0); begin for j in 0 to INPUT_CHUNKS - 1 loop @@ -152,7 +152,7 @@ begin ); procChecker : process - constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess(simTestID, "Checker " & INTEGER'image(i) & " for " & INTEGER'image(INPUT_BITS) & "->" & INTEGER'image(OUTPUT_BITS)); --, "aaa/bbb/ccc"); --globalSimulationStatus'instance_name); + constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess(simTestID, "Checker " & integer'image(i) & " for " & INTEGER'image(INPUT_BITS) & "->" & integer'image(OUTPUT_BITS)); --, "aaa/bbb/ccc"); --globalSimulationStatus'instance_name); begin for i in 0 to (LOOP_COUNT * RATIO) - 1 loop wait until rising_edge(Clock2); diff --git a/tb/misc/gearbox/gearbox_up_cc_tb.vhdl b/tb/misc/gearbox/gearbox_up_cc_tb.vhdl index c7ca5590..520d77e5 100644 --- a/tb/misc/gearbox/gearbox_up_cc_tb.vhdl +++ b/tb/misc/gearbox/gearbox_up_cc_tb.vhdl @@ -53,15 +53,15 @@ end entity; architecture tb of gearbox_up_cc_tb is type T_TUPLE is record - InputBits : POSITIVE; - OutputBits : POSITIVE; + InputBits : positive; + OutputBits : positive; end record; - type T_TUPLE_VECTOR is array(NATURAL range <>) of T_TUPLE; + type T_TUPLE_VECTOR is array(natural range <>) of T_TUPLE; constant TB_GENERATOR_LIST : T_TUPLE_VECTOR := ((8, 32), (8, 20), (8, 36), (64, 66), (12, 128)); constant CLOCK_FREQ : FREQ := 100 MHz; - signal Clock : STD_LOGIC := '1'; + signal Clock : std_logic := '1'; begin -- initialize global simulation status @@ -71,21 +71,21 @@ begin genInstances : for i in TB_GENERATOR_LIST'range generate - constant INPUT_BITS : POSITIVE := TB_GENERATOR_LIST(i).InputBits; - constant OUTPUT_BITS : POSITIVE := TB_GENERATOR_LIST(i).OutputBits; + constant INPUT_BITS : positive := TB_GENERATOR_LIST(i).InputBits; + constant OUTPUT_BITS : positive := TB_GENERATOR_LIST(i).OutputBits; constant OUTPUT_ORDER : T_BIT_ORDER := MSB_FIRST; - constant ADD_INPUT_REGISTERS : BOOLEAN := TRUE; - constant ADD_OUTPUT_REGISTERS : BOOLEAN := FALSE; + constant ADD_INPUT_REGISTERS : boolean := TRUE; + constant ADD_OUTPUT_REGISTERS : boolean := FALSE; - constant BITS_PER_CHUNK : POSITIVE := greatestCommonDivisor(INPUT_BITS, OUTPUT_BITS); - constant INPUT_CHUNKS : POSITIVE := INPUT_BITS / BITS_PER_CHUNK; - constant OUTPUT_CHUNKS : POSITIVE := OUTPUT_BITS / BITS_PER_CHUNK; + constant BITS_PER_CHUNK : positive := greatestCommonDivisor(INPUT_BITS, OUTPUT_BITS); + constant INPUT_CHUNKS : positive := INPUT_BITS / BITS_PER_CHUNK; + constant OUTPUT_CHUNKS : positive := OUTPUT_BITS / BITS_PER_CHUNK; - subtype T_CHUNK is STD_LOGIC_VECTOR(BITS_PER_CHUNK - 1 downto 0); - type T_CHUNK_VECTOR is array(NATURAL range <>) of T_CHUNK; + subtype T_CHUNK is std_logic_vector(BITS_PER_CHUNK - 1 downto 0); + type T_CHUNK_VECTOR is array(natural range <>) of T_CHUNK; - function to_slv(slvv : T_CHUNK_VECTOR) return STD_LOGIC_VECTOR is - variable slv : STD_LOGIC_VECTOR((slvv'length * BITS_PER_CHUNK) - 1 downto 0); + function to_slv(slvv : T_CHUNK_VECTOR) return std_logic_vector is + variable slv : std_logic_vector((slvv'length * BITS_PER_CHUNK) - 1 downto 0); begin for i in slvv'range loop slv(((i + 1) * BITS_PER_CHUNK) - 1 downto (i * BITS_PER_CHUNK)) := slvv(i); @@ -93,28 +93,28 @@ begin return slv; end function; - constant LOOP_COUNT : POSITIVE := 64; - constant DELAY : POSITIVE := 16; + constant LOOP_COUNT : positive := 64; + constant DELAY : positive := 16; - signal SyncIn : STD_LOGIC; - signal ValidIn : STD_LOGIC; - signal DataIn : STD_LOGIC_VECTOR(INPUT_BITS - 1 downto 0); + signal SyncIn : std_logic; + signal ValidIn : std_logic; + signal DataIn : std_logic_vector(INPUT_BITS - 1 downto 0); - signal SyncOut : STD_LOGIC; - signal ValidOut : STD_LOGIC; - signal DataOut : STD_LOGIC_VECTOR(OUTPUT_BITS - 1 downto 0); - signal FirstOut : STD_LOGIC; - signal LastOut : STD_LOGIC; + signal SyncOut : std_logic; + signal ValidOut : std_logic; + signal DataOut : std_logic_vector(OUTPUT_BITS - 1 downto 0); + signal FirstOut : std_logic; + signal LastOut : std_logic; - constant simTestID : T_SIM_TEST_ID := simCreateTest("Test setup for " & INTEGER'image(INPUT_BITS) & "->" & INTEGER'image(OUTPUT_BITS)); + constant simTestID : T_SIM_TEST_ID := simCreateTest("Test setup for " & integer'image(INPUT_BITS) & "->" & INTEGER'image(OUTPUT_BITS)); begin procGenerator : process - constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess(simTestID, "Generator " & INTEGER'image(i) & " for " & INTEGER'image(INPUT_BITS) & "->" & INTEGER'image(OUTPUT_BITS)); --, "aaa/bbb/ccc"); --globalSimulationStatus'instance_name); + constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess(simTestID, "Generator " & integer'image(i) & " for " & INTEGER'image(INPUT_BITS) & "->" & integer'image(OUTPUT_BITS)); --, "aaa/bbb/ccc"); --globalSimulationStatus'instance_name); -- protected type from RandomPkg variable RandomVar : RandomPType; - impure function genChunkedRandomValue return STD_LOGIC_VECTOR is + impure function genChunkedRandomValue return std_logic_vector is variable Temp : T_CHUNK_VECTOR(INPUT_CHUNKS - 1 downto 0); begin for j in 0 to INPUT_CHUNKS - 1 loop @@ -195,8 +195,8 @@ begin ); procChecker : process - variable simProcessID : T_SIM_PROCESS_ID := simRegisterProcess(simTestID, "Checker " & INTEGER'image(i) & " for " & INTEGER'image(INPUT_BITS) & "->" & INTEGER'image(OUTPUT_BITS)); - variable Check : BOOLEAN; + variable simProcessID : T_SIM_PROCESS_ID := simRegisterProcess(simTestID, "Checker " & integer'image(i) & " for " & INTEGER'image(INPUT_BITS) & "->" & integer'image(OUTPUT_BITS)); + variable Check : boolean; begin Check := TRUE; diff --git a/tb/misc/gearbox/gearbox_up_dc_tb.vhdl b/tb/misc/gearbox/gearbox_up_dc_tb.vhdl index 080d1360..6918b696 100644 --- a/tb/misc/gearbox/gearbox_up_dc_tb.vhdl +++ b/tb/misc/gearbox/gearbox_up_dc_tb.vhdl @@ -53,10 +53,10 @@ end entity; architecture tb of gearbox_up_dc_tb is type T_TUPLE is record - InputBits : POSITIVE; - OutputBits : POSITIVE; + InputBits : positive; + OutputBits : positive; end record; - type T_TUPLE_VECTOR is array(NATURAL range <>) of T_TUPLE; + type T_TUPLE_VECTOR is array(natural range <>) of T_TUPLE; constant TB_GENERATOR_LIST : T_TUPLE_VECTOR := ((8, 32), (8, 128)); @@ -66,23 +66,23 @@ begin genInstances : for i in TB_GENERATOR_LIST'range generate - constant INPUT_BITS : POSITIVE := TB_GENERATOR_LIST(i).InputBits; - constant OUTPUT_BITS : POSITIVE := TB_GENERATOR_LIST(i).OutputBits; + constant INPUT_BITS : positive := TB_GENERATOR_LIST(i).InputBits; + constant OUTPUT_BITS : positive := TB_GENERATOR_LIST(i).OutputBits; constant INPUT_ORDER : T_BIT_ORDER := MSB_FIRST; - constant ADD_INPUT_REGISTERS : BOOLEAN := TRUE; - constant ADD_OUTPUT_REGISTERS : BOOLEAN := FALSE; + constant ADD_INPUT_REGISTERS : boolean := TRUE; + constant ADD_OUTPUT_REGISTERS : boolean := FALSE; - constant RATIO : POSITIVE := OUTPUT_BITS / INPUT_BITS; + constant RATIO : positive := OUTPUT_BITS / INPUT_BITS; - constant BITS_PER_CHUNK : POSITIVE := greatestCommonDivisor(INPUT_BITS, OUTPUT_BITS); - constant INPUT_CHUNKS : POSITIVE := INPUT_BITS / BITS_PER_CHUNK; - constant OUTPUT_CHUNKS : POSITIVE := OUTPUT_BITS / BITS_PER_CHUNK; + constant BITS_PER_CHUNK : positive := greatestCommonDivisor(INPUT_BITS, OUTPUT_BITS); + constant INPUT_CHUNKS : positive := INPUT_BITS / BITS_PER_CHUNK; + constant OUTPUT_CHUNKS : positive := OUTPUT_BITS / BITS_PER_CHUNK; - subtype T_CHUNK is STD_LOGIC_VECTOR(BITS_PER_CHUNK - 1 downto 0); - type T_CHUNK_VECTOR is array(NATURAL range <>) of T_CHUNK; + subtype T_CHUNK is std_logic_vector(BITS_PER_CHUNK - 1 downto 0); + type T_CHUNK_VECTOR is array(natural range <>) of T_CHUNK; - function to_slv(slvv : T_CHUNK_VECTOR) return STD_LOGIC_VECTOR is - variable slv : STD_LOGIC_VECTOR((slvv'length * BITS_PER_CHUNK) - 1 downto 0); + function to_slv(slvv : T_CHUNK_VECTOR) return std_logic_vector is + variable slv : std_logic_vector((slvv'length * BITS_PER_CHUNK) - 1 downto 0); begin for i in slvv'range loop slv(((i + 1) * BITS_PER_CHUNK) - 1 downto (i * BITS_PER_CHUNK)) := slvv(i); @@ -90,20 +90,20 @@ begin return slv; end function; - constant LOOP_COUNT : POSITIVE := 64; - constant DELAY : POSITIVE := 16; + constant LOOP_COUNT : positive := 64; + constant DELAY : positive := 16; - constant CLOCK1_PERIOD : TIME := 10 ns; - constant CLOCK2_PERIOD : TIME := CLOCK1_PERIOD * RATIO; - signal Clock1 : STD_LOGIC := '1'; - signal Clock2 : STD_LOGIC := '1'; + constant CLOCK1_PERIOD : time := 10 ns; + constant CLOCK2_PERIOD : time := CLOCK1_PERIOD * RATIO; + signal Clock1 : std_logic := '1'; + signal Clock2 : std_logic := '1'; - signal Align : STD_LOGIC := '0'; - signal DataIn : STD_LOGIC_VECTOR(INPUT_BITS - 1 downto 0); - signal DataOut : STD_LOGIC_VECTOR(OUTPUT_BITS - 1 downto 0); - signal Valid : STD_LOGIC; + signal Align : std_logic := '0'; + signal DataIn : std_logic_vector(INPUT_BITS - 1 downto 0); + signal DataOut : std_logic_vector(OUTPUT_BITS - 1 downto 0); + signal Valid : std_logic; - constant simTestID : T_SIM_TEST_ID := simCreateTest("Test setup for " & INTEGER'image(INPUT_BITS) & "->" & INTEGER'image(OUTPUT_BITS)); + constant simTestID : T_SIM_TEST_ID := simCreateTest("Test setup for " & integer'image(INPUT_BITS) & "->" & INTEGER'image(OUTPUT_BITS)); begin -- generate global testbench clock @@ -112,11 +112,11 @@ begin procGenerator : process -- from Simulation - constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess(simTestID, "Generator " & INTEGER'image(i) & " for " & INTEGER'image(INPUT_BITS) & "->" & INTEGER'image(OUTPUT_BITS)); --, "aaa/bbb/ccc"); --globalSimulationStatus'instance_name); + constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess(simTestID, "Generator " & integer'image(i) & " for " & INTEGER'image(INPUT_BITS) & "->" & integer'image(OUTPUT_BITS)); --, "aaa/bbb/ccc"); --globalSimulationStatus'instance_name); -- protected type from RandomPkg variable RandomVar : RandomPType; - impure function genChunkedRandomValue return STD_LOGIC_VECTOR is + impure function genChunkedRandomValue return std_logic_vector is variable Temp : T_CHUNK_VECTOR(INPUT_CHUNKS - 1 downto 0); begin for j in 0 to INPUT_CHUNKS - 1 loop @@ -157,9 +157,9 @@ begin ); procChecker : process - constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess(simTestID, "Checker " & INTEGER'image(i) & " for " & INTEGER'image(INPUT_BITS) & "->" & INTEGER'image(OUTPUT_BITS)); --, "aaa/bbb/ccc"); --globalSimulationStatus'instance_name); + constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess(simTestID, "Checker " & integer'image(i) & " for " & INTEGER'image(INPUT_BITS) & "->" & integer'image(OUTPUT_BITS)); --, "aaa/bbb/ccc"); --globalSimulationStatus'instance_name); - variable Check : BOOLEAN; + variable Check : boolean; begin -- Check := FALSE; diff --git a/tb/misc/stat/stat_Average_tb.vhdl b/tb/misc/stat/stat_Average_tb.vhdl index 2e524490..d5362b75 100644 --- a/tb/misc/stat/stat_Average_tb.vhdl +++ b/tb/misc/stat/stat_Average_tb.vhdl @@ -87,27 +87,27 @@ architecture tb of stat_Average_tb is ); type T_RESULT is record - Minimum : NATURAL; - Count : POSITIVE; + Minimum : natural; + Count : positive; end record; - type T_RESULT_VECTOR is array(NATURAL range <>) of T_RESULT; + type T_RESULT_VECTOR is array(natural range <>) of T_RESULT; - constant DATA_BITS : POSITIVE := 8; - constant COUNTER_BITS : POSITIVE := 16; - constant simTestID : T_SIM_TEST_ID := simCreateTest("Test setup for DATA_BITS=" & INTEGER'image(DATA_BITS) & " COUNTER_BITS=" & INTEGER'image(COUNTER_BITS)); + constant DATA_BITS : positive := 8; + constant COUNTER_BITS : positive := 16; + constant simTestID : T_SIM_TEST_ID := simCreateTest("Test setup for DATA_BITS=" & integer'image(DATA_BITS) & " COUNTER_BITS=" & INTEGER'image(COUNTER_BITS)); -- component ports - signal Clock : STD_LOGIC; - signal Reset : STD_LOGIC; + signal Clock : std_logic; + signal Reset : std_logic; - signal Enable : STD_LOGIC := '0'; - signal DataIn : STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0); + signal Enable : std_logic := '0'; + signal DataIn : std_logic_vector(DATA_BITS - 1 downto 0); - signal Count : STD_LOGIC_VECTOR(COUNTER_BITS - 1 downto 0); - signal Sum : STD_LOGIC_VECTOR(COUNTER_BITS - 1 downto 0); - signal Average : STD_LOGIC_VECTOR(COUNTER_BITS - 1 downto 0); - signal Valid : STD_LOGIC; + signal Count : std_logic_vector(COUNTER_BITS - 1 downto 0); + signal Sum : std_logic_vector(COUNTER_BITS - 1 downto 0); + signal Average : std_logic_vector(COUNTER_BITS - 1 downto 0); + signal Valid : std_logic; begin -- initialize global simulation status @@ -138,9 +138,9 @@ begin procStimuli : process constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess(simTestID, "Generator and Checker"); - variable ExpectedCnt : NATURAL; - variable ExpectedSum : NATURAL; - variable ExpectedAvg : NATURAL; + variable ExpectedCnt : natural; + variable ExpectedSum : natural; + variable ExpectedAvg : natural; begin DataIn <= (others => '0'); wait until (Enable = '1') and falling_edge(Clock); @@ -157,9 +157,9 @@ begin ExpectedSum := isum(VALUES); ExpectedAvg := ExpectedSum / ExpectedCnt; - simAssertion((unsigned(Count) = ExpectedCnt), "Count mismatch. Count=" & INTEGER'image(to_integer(unsigned(Count))) & " Expected=" & INTEGER'image(ExpectedCnt)); - simAssertion((unsigned(Sum) = ExpectedSum), "Sum mismatch. Sum=" & INTEGER'image(to_integer(unsigned(Sum))) & " Expected=" & INTEGER'image(ExpectedSum)); - simAssertion((unsigned(Average) = ExpectedAvg), "Average mismatch. Average=" & INTEGER'image(to_integer(unsigned(Average))) & " Expected=" & INTEGER'image(ExpectedAvg)); + simAssertion((unsigned(Count) = ExpectedCnt), "Count mismatch. Count=" & integer'image(to_integer(unsigned(Count))) & " Expected=" & INTEGER'image(ExpectedCnt)); + simAssertion((unsigned(Sum) = ExpectedSum), "Sum mismatch. Sum=" & integer'image(to_integer(unsigned(Sum))) & " Expected=" & INTEGER'image(ExpectedSum)); + simAssertion((unsigned(Average) = ExpectedAvg), "Average mismatch. Average=" & integer'image(to_integer(unsigned(Average))) & " Expected=" & INTEGER'image(ExpectedAvg)); -- This process is finished simDeactivateProcess(simProcessID); diff --git a/tb/misc/stat/stat_Histogram_tb.vhdl b/tb/misc/stat/stat_Histogram_tb.vhdl index f9e0cc46..b89e50b4 100644 --- a/tb/misc/stat/stat_Histogram_tb.vhdl +++ b/tb/misc/stat/stat_Histogram_tb.vhdl @@ -55,22 +55,22 @@ end entity; architecture tb of stat_Histogram_tb is constant CLOCK_FREQ : FREQ := 100 MHz; - constant GNUPLOT_DATA_FILE : STRING := "stat_Histogram.dat"; + constant GNUPLOT_DATA_FILE : string := "stat_Histogram.dat"; -- component generics - constant DATA_BITS : POSITIVE := 8; - constant COUNTER_BITS : POSITIVE := 8; - constant simTestID : T_SIM_TEST_ID := simCreateTest("Test setup for DATA_BITS=" & INTEGER'image(DATA_BITS)); + constant DATA_BITS : positive := 8; + constant COUNTER_BITS : positive := 8; + constant simTestID : T_SIM_TEST_ID := simCreateTest("Test setup for DATA_BITS=" & integer'image(DATA_BITS)); constant RESULT : T_INTVEC := (0 to (2**DATA_BITS - 1) => 3); - constant SIM_COUNT : POSITIVE := 10; + constant SIM_COUNT : positive := 10; -- component ports - signal Clock : STD_LOGIC; - signal Reset : STD_LOGIC; + signal Clock : std_logic; + signal Reset : std_logic; - signal Enable : STD_LOGIC; - signal DataIn : STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0); + signal Enable : std_logic; + signal DataIn : std_logic_vector(DATA_BITS - 1 downto 0); signal Histogram : T_SLM(2**DATA_BITS - 1 downto 0, COUNTER_BITS - 1 downto 0); signal Histogram_slvv : T_SLVV_8(2**DATA_BITS - 1 downto 0); @@ -105,8 +105,8 @@ begin procStimuli : process constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess(simTestID, "Generator and Checker"); variable RandomValue_real : REAL; - variable RandomValue_int : INTEGER; - variable good : BOOLEAN; + variable RandomValue_int : integer; + variable good : boolean; constant StandardDeviation : REAL := 0.8; constant Mean : REAL := 0.0; diff --git a/tb/misc/stat/stat_Maximum_tb.vhdl b/tb/misc/stat/stat_Maximum_tb.vhdl index a4cef761..e88c95b0 100644 --- a/tb/misc/stat/stat_Maximum_tb.vhdl +++ b/tb/misc/stat/stat_Maximum_tb.vhdl @@ -87,11 +87,11 @@ architecture tb of stat_Maximum_tb is ); type T_RESULT is record - Maximum : NATURAL; - Count : POSITIVE; + Maximum : natural; + Count : positive; end record; - type T_RESULT_VECTOR is array(NATURAL range <>) of T_RESULT; + type T_RESULT_VECTOR is array(natural range <>) of T_RESULT; constant RESULT : T_RESULT_VECTOR := ( (Maximum => 249, Count => 2), @@ -104,19 +104,19 @@ architecture tb of stat_Maximum_tb is (Maximum => 240, Count => 2) ); - constant DEPTH : POSITIVE := RESULT'length; - constant DATA_BITS : POSITIVE := 8; - constant COUNTER_BITS : POSITIVE := 4; - constant simTestID : T_SIM_TEST_ID := simCreateTest("Test setup for DEPTH=" & INTEGER'image(DEPTH)); + constant DEPTH : positive := RESULT'length; + constant DATA_BITS : positive := 8; + constant COUNTER_BITS : positive := 4; + constant simTestID : T_SIM_TEST_ID := simCreateTest("Test setup for DEPTH=" & integer'image(DEPTH)); -- component ports - signal Clock : STD_LOGIC; - signal Reset : STD_LOGIC; + signal Clock : std_logic; + signal Reset : std_logic; - signal Enable : STD_LOGIC := '0'; - signal DataIn : STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0); + signal Enable : std_logic := '0'; + signal DataIn : std_logic_vector(DATA_BITS - 1 downto 0); - signal Valids : STD_LOGIC_VECTOR(DEPTH - 1 downto 0); + signal Valids : std_logic_vector(DEPTH - 1 downto 0); signal Maximums : T_SLM(DEPTH - 1 downto 0, DATA_BITS - 1 downto 0); signal Counts : T_SLM(DEPTH - 1 downto 0, COUNTER_BITS - 1 downto 0); @@ -155,7 +155,7 @@ begin procStimuli : process constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess(simTestID, "Generator and Checker"); - variable good : BOOLEAN; + variable good : boolean; begin DataIn <= (others => '0'); wait until (Enable = '1') and falling_edge(Clock); diff --git a/tb/misc/stat/stat_Minimum_tb.vhdl b/tb/misc/stat/stat_Minimum_tb.vhdl index 238b8b35..89a756be 100644 --- a/tb/misc/stat/stat_Minimum_tb.vhdl +++ b/tb/misc/stat/stat_Minimum_tb.vhdl @@ -87,11 +87,11 @@ architecture tb of stat_Minimum_tb is ); type T_RESULT is record - Minimum : NATURAL; - Count : POSITIVE; + Minimum : natural; + Count : positive; end record; - type T_RESULT_VECTOR is array(NATURAL range <>) of T_RESULT; + type T_RESULT_VECTOR is array(natural range <>) of T_RESULT; constant RESULT : T_RESULT_VECTOR := ( (Minimum => 3, Count => 1), @@ -104,19 +104,19 @@ architecture tb of stat_Minimum_tb is (Minimum => 13, Count => 3) ); - constant DEPTH : POSITIVE := RESULT'length; - constant DATA_BITS : POSITIVE := 8; - constant COUNTER_BITS : POSITIVE := 4; - constant simTestID : T_SIM_TEST_ID := simCreateTest("Test setup for DEPTH=" & INTEGER'image(DEPTH)); + constant DEPTH : positive := RESULT'length; + constant DATA_BITS : positive := 8; + constant COUNTER_BITS : positive := 4; + constant simTestID : T_SIM_TEST_ID := simCreateTest("Test setup for DEPTH=" & integer'image(DEPTH)); -- component ports - signal Clock : STD_LOGIC; - signal Reset : STD_LOGIC; + signal Clock : std_logic; + signal Reset : std_logic; - signal Enable : STD_LOGIC := '0'; - signal DataIn : STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0); + signal Enable : std_logic := '0'; + signal DataIn : std_logic_vector(DATA_BITS - 1 downto 0); - signal Valids : STD_LOGIC_VECTOR(DEPTH - 1 downto 0); + signal Valids : std_logic_vector(DEPTH - 1 downto 0); signal Minimums : T_SLM(DEPTH - 1 downto 0, DATA_BITS - 1 downto 0); signal Counts : T_SLM(DEPTH - 1 downto 0, COUNTER_BITS - 1 downto 0); @@ -155,7 +155,7 @@ begin procStimuli : process constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess(simTestID, "Generator and Checker"); - variable good : BOOLEAN; + variable good : boolean; begin DataIn <= (others => '0'); wait until (Enable = '1') and falling_edge(Clock); diff --git a/tb/misc/sync/sync_Bits_tb.vhdl b/tb/misc/sync/sync_Bits_tb.vhdl index 485872c6..996a9df6 100644 --- a/tb/misc/sync/sync_Bits_tb.vhdl +++ b/tb/misc/sync/sync_Bits_tb.vhdl @@ -50,12 +50,12 @@ architecture tb of sync_Bits_tb is constant CLOCK_1_FREQ : FREQ := 100 MHz; constant CLOCK_2_FREQ : FREQ := 60 MHz; - signal Clock1 : STD_LOGIC; - signal Clock2 : STD_LOGIC; + signal Clock1 : std_logic; + signal Clock2 : std_logic; - constant INIT : STD_LOGIC_VECTOR(0 downto 0) := "0"; - signal Sync_in : STD_LOGIC_VECTOR(0 downto 0) := INIT; - signal Sync_out : STD_LOGIC_VECTOR(0 downto 0); + constant INIT : std_logic_vector(0 downto 0) := "0"; + signal Sync_in : std_logic_vector(0 downto 0) := INIT; + signal Sync_out : std_logic_vector(0 downto 0); begin -- initialize global simulation status simInitialize; diff --git a/tb/misc/sync/sync_Command_tb.vhdl b/tb/misc/sync/sync_Command_tb.vhdl index 11af54a8..70e6a018 100644 --- a/tb/misc/sync/sync_Command_tb.vhdl +++ b/tb/misc/sync/sync_Command_tb.vhdl @@ -50,13 +50,13 @@ architecture tb of sync_Command_tb is constant CLOCK_1_FREQ : FREQ := 100 MHz; constant CLOCK_2_FREQ : FREQ := 60 MHz; - signal Clock1 : STD_LOGIC; - signal Clock2 : STD_LOGIC; + signal Clock1 : std_logic; + signal Clock2 : std_logic; - signal Sync_in : STD_LOGIC_VECTOR(1 downto 0) := "00"; - signal Sync_out : STD_LOGIC_VECTOR(1 downto 0); - signal Sync_Busy : STD_LOGIC; - signal Sync_Changed : STD_LOGIC; + signal Sync_in : std_logic_vector(1 downto 0) := "00"; + signal Sync_out : std_logic_vector(1 downto 0); + signal Sync_Busy : std_logic; + signal Sync_Changed : std_logic; begin -- initialize global simulation status diff --git a/tb/misc/sync/sync_Reset_tb.vhdl b/tb/misc/sync/sync_Reset_tb.vhdl index 2d1b0188..e271e9c0 100644 --- a/tb/misc/sync/sync_Reset_tb.vhdl +++ b/tb/misc/sync/sync_Reset_tb.vhdl @@ -50,11 +50,11 @@ architecture tb of sync_Reset_tb is constant CLOCK_1_FREQ : FREQ := 100 MHz; constant CLOCK_2_FREQ : FREQ := 60 MHz; - signal Clock1 : STD_LOGIC; - signal Clock2 : STD_LOGIC; + signal Clock1 : std_logic; + signal Clock2 : std_logic; - signal Sync_in : STD_LOGIC := '0'; - signal Sync_out : STD_LOGIC; + signal Sync_in : std_logic := '0'; + signal Sync_out : std_logic; begin -- initialize global simulation status diff --git a/tb/misc/sync/sync_Strobe_tb.vhdl b/tb/misc/sync/sync_Strobe_tb.vhdl index 6f88685f..57bbdcfc 100644 --- a/tb/misc/sync/sync_Strobe_tb.vhdl +++ b/tb/misc/sync/sync_Strobe_tb.vhdl @@ -50,12 +50,12 @@ architecture tb of sync_Strobe_tb is constant CLOCK_1_FREQ : FREQ := 100 MHz; constant CLOCK_2_FREQ : FREQ := 60 MHz; - signal Clock1 : STD_LOGIC; - signal Clock2 : STD_LOGIC; + signal Clock1 : std_logic; + signal Clock2 : std_logic; - signal Sync_in : STD_LOGIC_VECTOR(0 downto 0) := "0"; - signal Sync_out : STD_LOGIC_VECTOR(0 downto 0); - signal Sync_Busy : STD_LOGIC_VECTOR(0 downto 0); + signal Sync_in : std_logic_vector(0 downto 0) := "0"; + signal Sync_out : std_logic_vector(0 downto 0); + signal Sync_Busy : std_logic_vector(0 downto 0); begin -- initialize global simulation status diff --git a/tb/misc/sync/sync_Vector_tb.vhdl b/tb/misc/sync/sync_Vector_tb.vhdl index ec5889ca..abf44b5f 100644 --- a/tb/misc/sync/sync_Vector_tb.vhdl +++ b/tb/misc/sync/sync_Vector_tb.vhdl @@ -50,13 +50,13 @@ architecture tb of sync_Vector_tb is constant CLOCK_1_FREQ : FREQ := 100 MHz; constant CLOCK_2_FREQ : FREQ := 60 MHz; - signal Clock1 : STD_LOGIC; - signal Clock2 : STD_LOGIC; + signal Clock1 : std_logic; + signal Clock2 : std_logic; - signal Sync_in : STD_LOGIC_VECTOR(1 downto 0) := "00"; - signal Sync_out : STD_LOGIC_VECTOR(1 downto 0); - signal Sync_Busy : STD_LOGIC; - signal Sync_Changed : STD_LOGIC; + signal Sync_in : std_logic_vector(1 downto 0) := "00"; + signal Sync_out : std_logic_vector(1 downto 0); + signal Sync_Busy : std_logic; + signal Sync_Changed : std_logic; begin -- initialize global simulation status diff --git a/tb/sim/sim_ClockGenerator_tb.vhdl b/tb/sim/sim_ClockGenerator_tb.vhdl index e8a08ad3..06ae6049 100644 --- a/tb/sim/sim_ClockGenerator_tb.vhdl +++ b/tb/sim/sim_ClockGenerator_tb.vhdl @@ -59,67 +59,67 @@ architecture tb of sim_ClockGenerator_tb is constant simTestID : T_SIM_TEST_ID := simCreateTest("Test clock generation"); - signal Clock : STD_LOGIC; - signal ClockIsActive : STD_LOGIC := '1'; - - signal Clock_01 : STD_LOGIC; - signal Clock_02 : STD_LOGIC; - signal Clock_03 : STD_LOGIC; - signal Clock_04 : STD_LOGIC; - signal Clock_05 : STD_LOGIC; - signal Clock_06 : STD_LOGIC; - - signal Clock_10 : STD_LOGIC; - signal Clock_11 : STD_LOGIC; - signal Clock_12 : STD_LOGIC; - signal Clock_13 : STD_LOGIC; - signal Clock_14 : STD_LOGIC; - signal Clock_15 : STD_LOGIC; - signal Clock_16 : STD_LOGIC; - signal Clock_17 : STD_LOGIC; - signal Clock_18 : STD_LOGIC; - signal Clock_19 : STD_LOGIC; - - signal Clock_21 : STD_LOGIC; - signal Clock_22 : STD_LOGIC; - signal Clock_23 : STD_LOGIC; - signal Clock_24 : STD_LOGIC; - signal Clock_25 : STD_LOGIC; - - signal Clock_31 : STD_LOGIC; - signal Clock_32 : STD_LOGIC; - signal Clock_33 : STD_LOGIC; - signal Clock_34 : STD_LOGIC; - signal Clock_35 : STD_LOGIC; - - signal Clock_40 : STD_LOGIC; - signal Clock_41 : STD_LOGIC; - signal Clock_42 : STD_LOGIC; - signal Clock_43 : STD_LOGIC; - signal Counter_Clock_40_us : UNSIGNED(15 downto 0) := (others => '0'); - signal Counter_Clock_41_us : UNSIGNED(15 downto 0) := (others => '0'); - signal Counter_Clock_42_us : UNSIGNED(15 downto 0) := (others => '0'); - signal Counter_Clock_43_us : UNSIGNED(15 downto 0) := (others => '0'); - signal Counter_41_cmp : UNSIGNED(1 downto 0); - signal Counter_42_cmp : UNSIGNED(1 downto 0); - signal Counter_43_cmp : UNSIGNED(1 downto 0); - signal Drift_Clock_41 : SIGNED(15 downto 0); - signal Drift_Clock_42 : SIGNED(15 downto 0); - signal Drift_Clock_43 : SIGNED(15 downto 0); - - signal Clock_50 : STD_LOGIC; - signal Clock_51 : STD_LOGIC; - signal Counter_Clock_50_us : UNSIGNED(15 downto 0) := (others => '0'); - signal Counter_Clock_51_us : UNSIGNED(15 downto 0) := (others => '0'); - signal Mean_Clock_51 : SIGNED(15 downto 0); - signal Drift_Clock_51 : SIGNED(15 downto 0); - signal Drift_Clock_52 : SIGNED(15 downto 0); + signal Clock : std_logic; + signal ClockIsActive : std_logic := '1'; + + signal Clock_01 : std_logic; + signal Clock_02 : std_logic; + signal Clock_03 : std_logic; + signal Clock_04 : std_logic; + signal Clock_05 : std_logic; + signal Clock_06 : std_logic; + + signal Clock_10 : std_logic; + signal Clock_11 : std_logic; + signal Clock_12 : std_logic; + signal Clock_13 : std_logic; + signal Clock_14 : std_logic; + signal Clock_15 : std_logic; + signal Clock_16 : std_logic; + signal Clock_17 : std_logic; + signal Clock_18 : std_logic; + signal Clock_19 : std_logic; + + signal Clock_21 : std_logic; + signal Clock_22 : std_logic; + signal Clock_23 : std_logic; + signal Clock_24 : std_logic; + signal Clock_25 : std_logic; + + signal Clock_31 : std_logic; + signal Clock_32 : std_logic; + signal Clock_33 : std_logic; + signal Clock_34 : std_logic; + signal Clock_35 : std_logic; + + signal Clock_40 : std_logic; + signal Clock_41 : std_logic; + signal Clock_42 : std_logic; + signal Clock_43 : std_logic; + signal Counter_Clock_40_us : unsigned(15 downto 0) := (others => '0'); + signal Counter_Clock_41_us : unsigned(15 downto 0) := (others => '0'); + signal Counter_Clock_42_us : unsigned(15 downto 0) := (others => '0'); + signal Counter_Clock_43_us : unsigned(15 downto 0) := (others => '0'); + signal Counter_41_cmp : unsigned(1 downto 0); + signal Counter_42_cmp : unsigned(1 downto 0); + signal Counter_43_cmp : unsigned(1 downto 0); + signal Drift_Clock_41 : signed(15 downto 0); + signal Drift_Clock_42 : signed(15 downto 0); + signal Drift_Clock_43 : signed(15 downto 0); + + signal Clock_50 : std_logic; + signal Clock_51 : std_logic; + signal Counter_Clock_50_us : unsigned(15 downto 0) := (others => '0'); + signal Counter_Clock_51_us : unsigned(15 downto 0) := (others => '0'); + signal Mean_Clock_51 : signed(15 downto 0); + signal Drift_Clock_51 : signed(15 downto 0); + signal Drift_Clock_52 : signed(15 downto 0); signal Debug_Jitter : REAL; - signal Debug2 : SIGNED(15 downto 0); + signal Debug2 : signed(15 downto 0); - signal Reset_1 : STD_LOGIC; - signal Reset_2 : STD_LOGIC; + signal Reset_1 : std_logic; + signal Reset_2 : std_logic; begin -- initialize OSVVM transcript file @@ -183,7 +183,7 @@ begin Drift_Clock_41 <= (others => '0'); wait until rising_edge(Clock_40); wait until rising_edge(Clock_41); - while (not simIsStopped) loop + while not simIsStopped loop wait until rising_edge(Clock_41); Drift_Clock_41 <= to_signed((Clock_40'last_event - Clock_41'last_event) / 10 ps, Drift_Clock_41'length); end loop; @@ -200,7 +200,7 @@ begin Drift_Clock_42 <= (others => '0'); wait until rising_edge(Clock_40); wait until rising_edge(Clock_42); - while (not simIsStopped) loop + while not simIsStopped loop wait until rising_edge(Clock_42); Drift_Clock_42 <= to_signed((Clock_40'last_event - Clock_42'last_event) / 10 ps, Drift_Clock_42'length); end loop; @@ -217,7 +217,7 @@ begin Drift_Clock_43 <= (others => '0'); wait until rising_edge(Clock_40); wait until rising_edge(Clock_43); - while (not simIsStopped) loop + while not simIsStopped loop wait until rising_edge(Clock_43); Drift_Clock_43 <= to_signed((Clock_40'last_event - Clock_43'last_event) / 10 ps, Drift_Clock_43'length); end loop; @@ -238,13 +238,13 @@ begin procHistogram : process -- constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess("Histogram"); - variable Sum : INTEGER; - variable Count : NATURAL; - variable Rand : INTEGER; - variable RandPointer : NATURAL; + variable Sum : integer; + variable Count : natural; + variable Rand : integer; + variable RandPointer : natural; variable RandBuffer : T_INTVEC(0 to 15); - constant BIN_SIZE : POSITIVE := 1000; + constant BIN_SIZE : positive := 1000; constant BIN_SIZE_2 : REAL := real(BIN_SIZE) / 2.0; variable CovBin1 : CovPType; begin @@ -258,7 +258,7 @@ begin RandBuffer := (others => (BIN_SIZE / 2)); wait until rising_edge(Clock_51); - while (not simIsStopped) loop + while not simIsStopped loop wait until rising_edge(Clock_51); -- subtract old random value from mean aggregator Sum := Sum - RandBuffer(RandPointer); @@ -291,7 +291,7 @@ begin wait until rising_edge(Clock_50); wait until rising_edge(Clock_51); - while (not simIsStopped) loop + while not simIsStopped loop wait until rising_edge(Clock_50); Drift_Clock_51 <= to_signed((Clock_50'last_event - Clock_51'last_event) / 100 fs, Drift_Clock_51'length); -- Drift_Clock_52 <= to_signed((Clock_51'last_event - Clock_50'last_event) / 100 fs, Drift_Clock_52'length); diff --git a/tb/sim/sim_Waveform_tb.vhdl b/tb/sim/sim_Waveform_tb.vhdl index 260c09ab..83c06cf8 100644 --- a/tb/sim/sim_Waveform_tb.vhdl +++ b/tb/sim/sim_Waveform_tb.vhdl @@ -54,24 +54,24 @@ architecture tb of sim_Waveform_tb is constant simTestID : T_SIM_TEST_ID := simCreateTest("Test waveform generation"); - signal Clock : STD_LOGIC; + signal Clock : std_logic; - signal Reset_1 : STD_LOGIC; - signal Reset_2 : STD_LOGIC; - signal Reset_3 : STD_LOGIC; + signal Reset_1 : std_logic; + signal Reset_2 : std_logic; + signal Reset_3 : std_logic; - signal Impulse_01 : STD_LOGIC; - signal Impulse_02 : STD_LOGIC; - signal Impulse_03 : STD_LOGIC; + signal Impulse_01 : std_logic; + signal Impulse_02 : std_logic; + signal Impulse_03 : std_logic; - signal Wave_01 : STD_LOGIC; - signal Wave_02 : STD_LOGIC; - signal Wave_03 : STD_LOGIC; - signal Wave_04 : STD_LOGIC; - signal Wave_05 : STD_LOGIC; - signal Wave_06 : STD_LOGIC; + signal Wave_01 : std_logic; + signal Wave_02 : std_logic; + signal Wave_03 : std_logic; + signal Wave_04 : std_logic; + signal Wave_05 : std_logic; + signal Wave_06 : std_logic; - signal Wave_11 : STD_LOGIC; + signal Wave_11 : std_logic; signal Bus_01 : T_SLV_8; signal Bus_02 : T_SLV_8; diff --git a/tb/sort/sort_lru_cache_cocotb.py b/tb/sort/sort_lru_cache_cocotb.py index f371f3da..6207e296 100644 --- a/tb/sort/sort_lru_cache_cocotb.py +++ b/tb/sort/sort_lru_cache_cocotb.py @@ -1,12 +1,12 @@ # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2; replace-tabs off; indent-width 2; -# +# # ============================================================================== # Authors: Martin Zabel -# +# # Cocotb Testbench: Least-Recently Used Sort Algorithm -# +# # Description: # ------------------------------------ # Automated testbench for PoC.sort_LeastRecentlyUsed @@ -15,13 +15,13 @@ # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany # Chair for VLSI-Design, Diagnostics and Architecture -# +# # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at -# +# # http://www.apache.org/licenses/LICENSE-2.0 -# +# # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -47,7 +47,7 @@ class InputDriver(BusDriver): """Drives inputs of DUT.""" _signals = [ "Insert", "Free", "KeyIn" ] - + def __init__(self, dut): BusDriver.__init__(self, dut, None, dut.Clock) @@ -57,16 +57,16 @@ def __init__(self, insert, invalidate, keyin): self.Insert = BinaryValue(insert, 1) self.Free = BinaryValue(invalidate, 1) self.KeyIn = BinaryValue(keyin, 5, False) - + # ============================================================================== class InputMonitor(BusMonitor): """Observes inputs of DUT.""" _signals = [ "Insert", "Free", "KeyIn" ] - + def __init__(self, dut, callback=None, event=None): BusMonitor.__init__(self, dut, None, dut.Clock, dut.Reset, callback=callback, event=event) self.name = "in" - + @coroutine def _monitor_recv(self): clkedge = RisingEdge(self.clock) @@ -85,7 +85,7 @@ class OutputMonitor(BusMonitor): def __init__(self, dut, callback=None, event=None): BusMonitor.__init__(self, dut, None, dut.Clock, dut.Reset, callback=callback, event=event) self.name = "out" - + @coroutine def _monitor_recv(self): clkedge = RisingEdge(self.clock) @@ -109,10 +109,10 @@ def __init__(self, dut): self.lru[keyin] = 1 init_val = elements-1 - + self.input_drv = InputDriver(dut) self.output_mon = OutputMonitor(dut) - + # Create a scoreboard on the outputs self.expected_output = [ init_val ] self.scoreboard = Scoreboard(dut) @@ -136,7 +136,7 @@ def model(self, transaction): keyout = self.lru.iterkeys().next() #print "=== model: KeyOut=%d" % keyout self.expected_output.append(keyout) - + def stop(self): """ Stop generation of expected output transactions. @@ -176,7 +176,7 @@ def run_test(dut): dut.Reset <= 0 input_gen = random_input_gen() - + # Issue first transaction immediately. yield tb.input_drv.send(input_gen.next(), False) @@ -190,7 +190,7 @@ def run_test(dut): yield tb.input_drv.send(InputTransaction(0, 0, 0)) tb.stop() yield RisingEdge(dut.Clock) - + # Print result of scoreboard. raise tb.scoreboard.result diff --git a/tb/sort/sort_lru_cache_tb.vhdl b/tb/sort/sort_lru_cache_tb.vhdl index d197f6a9..b94fe577 100644 --- a/tb/sort/sort_lru_cache_tb.vhdl +++ b/tb/sort/sort_lru_cache_tb.vhdl @@ -53,21 +53,21 @@ end entity; architecture tb of sort_lru_cache_tb is - constant ELEMENTS : POSITIVE := 8; - constant KEY_BITS : POSITIVE := log2ceilnz(ELEMENTS); + constant ELEMENTS : positive := 8; + constant KEY_BITS : positive := log2ceilnz(ELEMENTS); - constant LOOP_COUNT : POSITIVE := 32; + constant LOOP_COUNT : positive := 32; - constant CLOCK_PERIOD : TIME := 10 ns; - signal Clock : STD_LOGIC := '1'; + constant CLOCK_PERIOD : time := 10 ns; + signal Clock : std_logic := '1'; - signal Insert : STD_LOGIC; - signal Free : STD_LOGIC; - signal KeyIn : STD_LOGIC_VECTOR(KEY_BITS - 1 downto 0); + signal Insert : std_logic; + signal Free : std_logic; + signal KeyIn : std_logic_vector(KEY_BITS - 1 downto 0); - signal KeyOut : STD_LOGIC_VECTOR(KEY_BITS - 1 downto 0); + signal KeyOut : std_logic_vector(KEY_BITS - 1 downto 0); - signal StopSimulation : STD_LOGIC := '0'; + signal StopSimulation : std_logic := '0'; begin simInitialize; @@ -76,7 +76,7 @@ begin process variable RandomVar : RandomPType; -- protected type from RandomPkg - variable Command : INTEGER range 0 to 1;--2; + variable Command : integer range 0 to 1;--2; begin RandomVar.InitSeed(RandomVar'instance_name); -- Generate initial seeds diff --git a/tb/sort/sort_lru_list_cocotb.py b/tb/sort/sort_lru_list_cocotb.py index b880d213..dace1253 100644 --- a/tb/sort/sort_lru_list_cocotb.py +++ b/tb/sort/sort_lru_list_cocotb.py @@ -1,12 +1,12 @@ # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2; replace-tabs off; indent-width 2; -# +# # ============================================================================== # Authors: Martin Zabel -# +# # Cocotb Testbench: Least-Recently Used Sort Algorithm -# +# # Description: # ------------------------------------ # Automated testbench for PoC.sort_LeastRecentlyUsed @@ -15,13 +15,13 @@ # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany # Chair for VLSI-Design, Diagnostics and Architecture -# +# # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at -# +# # http://www.apache.org/licenses/LICENSE-2.0 -# +# # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -48,7 +48,7 @@ class InputDriver(BusDriver): """Drives inputs of DUT.""" _signals = [ "Insert", "Remove", "DataIn" ] - + def __init__(self, dut): BusDriver.__init__(self, dut, None, dut.Clock) @@ -58,16 +58,16 @@ def __init__(self, insert, remove, datain): self.Insert = BinaryValue(insert, 1) self.Remove = BinaryValue(remove, 1) self.DataIn = BinaryValue(datain, 8, False) - + # ============================================================================== class InputMonitor(BusMonitor): """Observes inputs of DUT.""" _signals = [ "Insert", "Remove", "DataIn" ] - + def __init__(self, dut, callback=None, event=None): BusMonitor.__init__(self, dut, None, dut.Clock, dut.Reset, callback=callback, event=event) self.name = "in" - + @coroutine def _monitor_recv(self): clkedge = RisingEdge(self.clock) @@ -86,7 +86,7 @@ class OutputMonitor(BusMonitor): def __init__(self, dut, callback=None, event=None): BusMonitor.__init__(self, dut, None, dut.Clock, dut.Reset, callback=callback, event=event) self.name = "out" - + @coroutine def _monitor_recv(self): clkedge = RisingEdge(self.clock) @@ -111,9 +111,9 @@ def compare(self, got, exp, log, **_): log.warning("Expected: Valid=%d.\nReceived: Valid=%d." % (exp_valid, got_valid)) if self._imm: raise TestFailure("Received transaction differed from expected transaction.") - + elif got_valid == 1: - if got_elem != exp_elem: + if got_elem != exp_elem: self.errors += 1 log.error("Received transaction differed from expected output.") log.warning("Expected: Valid=%d, DataOut=%d.\n" @@ -121,8 +121,8 @@ def compare(self, got, exp, log, **_): (exp_valid, exp_elem, got_valid, got_elem)) if self._imm: raise TestFailure("Received transaction differed from expected transaction.") - - + + def __init__(self, dut, init_val): self.dut = dut self.stopped = False @@ -134,7 +134,7 @@ def __init__(self, dut, init_val): self.input_drv = InputDriver(dut) self.output_mon = OutputMonitor(dut) - + # Create a scoreboard on the outputs self.expected_output = [ init_val ] self.scoreboard = Testbench.MyScoreboard(dut) @@ -165,7 +165,7 @@ def model(self, transaction): dataout = self.lru.itervalues().next() #print "=== model: LRU element=%d" % dataout self.expected_output.append( (1, dataout) ) - + def stop(self): """ Stop generation of expected output transactions. @@ -205,7 +205,7 @@ def run_test(dut): dut.Reset <= 0 input_gen = random_input_gen() - + # Issue first transaction immediately. yield tb.input_drv.send(input_gen.next(), False) @@ -219,7 +219,7 @@ def run_test(dut): yield tb.input_drv.send(InputTransaction(0, 0, 0)) tb.stop() yield RisingEdge(dut.Clock) - + # Print result of scoreboard. raise tb.scoreboard.result diff --git a/tb/sort/sortnet/sortnet_BitonicSort_tb.vhdl b/tb/sort/sortnet/sortnet_BitonicSort_tb.vhdl index f05a951d..3f305d96 100644 --- a/tb/sort/sortnet/sortnet_BitonicSort_tb.vhdl +++ b/tb/sort/sortnet/sortnet_BitonicSort_tb.vhdl @@ -54,23 +54,23 @@ end entity; architecture tb of sortnet_BitonicSort_tb is - constant TAG_BITS : POSITIVE := 4; + constant TAG_BITS : positive := 4; - constant INPUTS : POSITIVE := 64; - constant DATA_COLUMNS : POSITIVE := 2; + constant INPUTS : positive := 64; + constant DATA_COLUMNS : positive := 2; - constant KEY_BITS : POSITIVE := 8; - constant DATA_BITS : POSITIVE := 32; - constant META_BITS : POSITIVE := TAG_BITS; - constant PIPELINE_STAGE_AFTER : NATURAL := 2; + constant KEY_BITS : positive := 8; + constant DATA_BITS : positive := 32; + constant META_BITS : positive := TAG_BITS; + constant PIPELINE_STAGE_AFTER : natural := 2; - constant LOOP_COUNT : POSITIVE := 1024; + constant LOOP_COUNT : positive := 1024; - constant STAGES : POSITIVE := triangularNumber(log2ceil(INPUTS)); - constant DELAY : NATURAL := STAGES / PIPELINE_STAGE_AFTER; + constant STAGES : positive := triangularNumber(log2ceil(INPUTS)); + constant DELAY : natural := STAGES / PIPELINE_STAGE_AFTER; - subtype T_DATA is STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0); - type T_DATA_VECTOR is array(NATURAL range <>) of T_DATA; + subtype T_DATA is std_logic_vector(DATA_BITS - 1 downto 0); + type T_DATA_VECTOR is array(natural range <>) of T_DATA; function to_dv(slm : T_SLM) return T_DATA_VECTOR is variable Result : T_DATA_VECTOR(slm'range(1)); @@ -95,17 +95,17 @@ architecture tb of sortnet_BitonicSort_tb is end function; constant CLOCK_FREQ : FREQ := 100 MHz; - signal Clock : STD_LOGIC := '1'; + signal Clock : std_logic := '1'; - signal Generator_Valid : STD_LOGIC; - signal Generator_IsKey : STD_LOGIC; + signal Generator_Valid : std_logic; + signal Generator_IsKey : std_logic; signal Generator_Data : T_DATA_VECTOR(INPUTS - 1 downto 0); - signal Generator_Meta : STD_LOGIC_VECTOR(META_BITS - 1 downto 0); + signal Generator_Meta : std_logic_vector(META_BITS - 1 downto 0); - signal Sort_Valid : STD_LOGIC; - signal Sort_IsKey : STD_LOGIC; + signal Sort_Valid : std_logic; + signal Sort_IsKey : std_logic; signal Sort_Data : T_DATA_VECTOR(INPUTS - 1 downto 0); - signal Sort_Meta : STD_LOGIC_VECTOR(META_BITS - 1 downto 0); + signal Sort_Meta : std_logic_vector(META_BITS - 1 downto 0); signal DataInputMatrix : T_SLM(INPUTS - 1 downto 0, DATA_BITS - 1 downto 0); signal DataOutputMatrix : T_SLM(INPUTS - 1 downto 0, DATA_BITS - 1 downto 0); @@ -115,10 +115,10 @@ begin simInitialize; simWriteMessage("SETTINGS"); - simWriteMessage(" INPUTS: " & INTEGER'image(INPUTS)); - simWriteMessage(" KEY_BITS: " & INTEGER'image(KEY_BITS)); - simWriteMessage(" DATA_BITS: " & INTEGER'image(DATA_BITS)); - simWriteMessage(" REG AFTER: " & INTEGER'image(PIPELINE_STAGE_AFTER)); + simWriteMessage(" INPUTS: " & integer'image(INPUTS)); + simWriteMessage(" KEY_BITS: " & integer'image(KEY_BITS)); + simWriteMessage(" DATA_BITS: " & integer'image(DATA_BITS)); + simWriteMessage(" REG AFTER: " & integer'image(PIPELINE_STAGE_AFTER)); simGenerateClock(Clock, CLOCK_FREQ); @@ -126,9 +126,9 @@ begin constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess("Generator"); variable RandomVar : RandomPType; -- protected type from RandomPkg - variable KeyInput : STD_LOGIC_VECTOR(KEY_BITS - 1 downto 0); - variable DataInput : STD_LOGIC_VECTOR(DATA_BITS - KEY_BITS - 1 downto 0); - variable TagInput : STD_LOGIC_VECTOR(TAG_BITS - 1 downto 0); + variable KeyInput : std_logic_vector(KEY_BITS - 1 downto 0); + variable DataInput : std_logic_vector(DATA_BITS - KEY_BITS - 1 downto 0); + variable TagInput : std_logic_vector(TAG_BITS - 1 downto 0); begin RandomVar.InitSeed(RandomVar'instance_name); -- Generate initial seeds @@ -190,9 +190,9 @@ begin procChecker : process constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess("Checker"); - variable Check : BOOLEAN; - variable CurValue : UNSIGNED(KEY_BITS - 1 downto 0); - variable LastValue : UNSIGNED(KEY_BITS - 1 downto 0); + variable Check : boolean; + variable CurValue : unsigned(KEY_BITS - 1 downto 0); + variable LastValue : unsigned(KEY_BITS - 1 downto 0); begin wait until rising_edge(Sort_Valid); diff --git a/tb/sort/sortnet/sortnet_OddEvenMergeSort_tb.vhdl b/tb/sort/sortnet/sortnet_OddEvenMergeSort_tb.vhdl index 48128d42..35ece684 100644 --- a/tb/sort/sortnet/sortnet_OddEvenMergeSort_tb.vhdl +++ b/tb/sort/sortnet/sortnet_OddEvenMergeSort_tb.vhdl @@ -54,23 +54,23 @@ end entity; architecture tb of sortnet_OddEvenMergeSort_tb is - constant TAG_BITS : POSITIVE := 4; + constant TAG_BITS : positive := 4; - constant INPUTS : POSITIVE := 64; - constant DATA_COLUMNS : POSITIVE := 2; + constant INPUTS : positive := 64; + constant DATA_COLUMNS : positive := 2; - constant KEY_BITS : POSITIVE := 8; - constant DATA_BITS : POSITIVE := 32; - constant META_BITS : POSITIVE := TAG_BITS; - constant PIPELINE_STAGE_AFTER : NATURAL := 2; + constant KEY_BITS : positive := 8; + constant DATA_BITS : positive := 32; + constant META_BITS : positive := TAG_BITS; + constant PIPELINE_STAGE_AFTER : natural := 2; - constant LOOP_COUNT : POSITIVE := 1024; + constant LOOP_COUNT : positive := 1024; - constant STAGES : POSITIVE := triangularNumber(log2ceil(INPUTS)); - constant DELAY : NATURAL := STAGES / PIPELINE_STAGE_AFTER; + constant STAGES : positive := triangularNumber(log2ceil(INPUTS)); + constant DELAY : natural := STAGES / PIPELINE_STAGE_AFTER; - subtype T_DATA is STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0); - type T_DATA_VECTOR is array(NATURAL range <>) of T_DATA; + subtype T_DATA is std_logic_vector(DATA_BITS - 1 downto 0); + type T_DATA_VECTOR is array(natural range <>) of T_DATA; function to_dv(slm : T_SLM) return T_DATA_VECTOR is variable Result : T_DATA_VECTOR(slm'range(1)); @@ -95,17 +95,17 @@ architecture tb of sortnet_OddEvenMergeSort_tb is end function; constant CLOCK_FREQ : FREQ := 100 MHz; - signal Clock : STD_LOGIC := '1'; + signal Clock : std_logic := '1'; - signal Generator_Valid : STD_LOGIC; - signal Generator_IsKey : STD_LOGIC; + signal Generator_Valid : std_logic; + signal Generator_IsKey : std_logic; signal Generator_Data : T_DATA_VECTOR(INPUTS - 1 downto 0); - signal Generator_Meta : STD_LOGIC_VECTOR(META_BITS - 1 downto 0); + signal Generator_Meta : std_logic_vector(META_BITS - 1 downto 0); - signal Sort_Valid : STD_LOGIC; - signal Sort_IsKey : STD_LOGIC; + signal Sort_Valid : std_logic; + signal Sort_IsKey : std_logic; signal Sort_Data : T_DATA_VECTOR(INPUTS - 1 downto 0); - signal Sort_Meta : STD_LOGIC_VECTOR(META_BITS - 1 downto 0); + signal Sort_Meta : std_logic_vector(META_BITS - 1 downto 0); signal DataInputMatrix : T_SLM(INPUTS - 1 downto 0, DATA_BITS - 1 downto 0); signal DataOutputMatrix : T_SLM(INPUTS - 1 downto 0, DATA_BITS - 1 downto 0); @@ -115,10 +115,10 @@ begin simInitialize; simWriteMessage("SETTINGS"); - simWriteMessage(" INPUTS: " & INTEGER'image(INPUTS)); - simWriteMessage(" KEY_BITS: " & INTEGER'image(KEY_BITS)); - simWriteMessage(" DATA_BITS: " & INTEGER'image(DATA_BITS)); - simWriteMessage(" REG AFTER: " & INTEGER'image(PIPELINE_STAGE_AFTER)); + simWriteMessage(" INPUTS: " & integer'image(INPUTS)); + simWriteMessage(" KEY_BITS: " & integer'image(KEY_BITS)); + simWriteMessage(" DATA_BITS: " & integer'image(DATA_BITS)); + simWriteMessage(" REG AFTER: " & integer'image(PIPELINE_STAGE_AFTER)); simGenerateClock(Clock, CLOCK_FREQ); @@ -126,9 +126,9 @@ begin constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess("Generator"); variable RandomVar : RandomPType; -- protected type from RandomPkg - variable KeyInput : STD_LOGIC_VECTOR(KEY_BITS - 1 downto 0); - variable DataInput : STD_LOGIC_VECTOR(DATA_BITS - KEY_BITS - 1 downto 0); - variable TagInput : STD_LOGIC_VECTOR(TAG_BITS - 1 downto 0); + variable KeyInput : std_logic_vector(KEY_BITS - 1 downto 0); + variable DataInput : std_logic_vector(DATA_BITS - KEY_BITS - 1 downto 0); + variable TagInput : std_logic_vector(TAG_BITS - 1 downto 0); begin RandomVar.InitSeed(RandomVar'instance_name); -- Generate initial seeds @@ -190,9 +190,9 @@ begin procChecker : process constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess("Checker"); - variable Check : BOOLEAN; - variable CurValue : UNSIGNED(KEY_BITS - 1 downto 0); - variable LastValue : UNSIGNED(KEY_BITS - 1 downto 0); + variable Check : boolean; + variable CurValue : unsigned(KEY_BITS - 1 downto 0); + variable LastValue : unsigned(KEY_BITS - 1 downto 0); begin wait until rising_edge(Sort_Valid); diff --git a/tb/sort/sortnet/sortnet_OddEvenSort_tb.vhdl b/tb/sort/sortnet/sortnet_OddEvenSort_tb.vhdl index 53d18e9f..a8df4fd1 100644 --- a/tb/sort/sortnet/sortnet_OddEvenSort_tb.vhdl +++ b/tb/sort/sortnet/sortnet_OddEvenSort_tb.vhdl @@ -53,23 +53,23 @@ end entity; architecture tb of sortnet_OddEvenSort_tb is - constant TAG_BITS : POSITIVE := 4; + constant TAG_BITS : positive := 4; - constant INPUTS : POSITIVE := 64; - constant DATA_COLUMNS : POSITIVE := 2; + constant INPUTS : positive := 64; + constant DATA_COLUMNS : positive := 2; - constant KEY_BITS : POSITIVE := 8; - constant DATA_BITS : POSITIVE := 32; - constant META_BITS : POSITIVE := TAG_BITS; - constant PIPELINE_STAGE_AFTER : NATURAL := 2; + constant KEY_BITS : positive := 8; + constant DATA_BITS : positive := 32; + constant META_BITS : positive := TAG_BITS; + constant PIPELINE_STAGE_AFTER : natural := 2; - constant LOOP_COUNT : POSITIVE := 1024; + constant LOOP_COUNT : positive := 1024; - constant STAGES : POSITIVE := INPUTS; - constant DELAY : NATURAL := STAGES / PIPELINE_STAGE_AFTER; + constant STAGES : positive := INPUTS; + constant DELAY : natural := STAGES / PIPELINE_STAGE_AFTER; - subtype T_DATA is STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0); - type T_DATA_VECTOR is array(NATURAL range <>) of T_DATA; + subtype T_DATA is std_logic_vector(DATA_BITS - 1 downto 0); + type T_DATA_VECTOR is array(natural range <>) of T_DATA; function to_dv(slm : T_SLM) return T_DATA_VECTOR is variable Result : T_DATA_VECTOR(slm'range(1)); @@ -94,17 +94,17 @@ architecture tb of sortnet_OddEvenSort_tb is end function; constant CLOCK_FREQ : FREQ := 100 MHz; - signal Clock : STD_LOGIC := '1'; + signal Clock : std_logic := '1'; - signal Generator_Valid : STD_LOGIC; - signal Generator_IsKey : STD_LOGIC; + signal Generator_Valid : std_logic; + signal Generator_IsKey : std_logic; signal Generator_Data : T_DATA_VECTOR(INPUTS - 1 downto 0); - signal Generator_Meta : STD_LOGIC_VECTOR(META_BITS - 1 downto 0); + signal Generator_Meta : std_logic_vector(META_BITS - 1 downto 0); - signal Sort_Valid : STD_LOGIC; - signal Sort_IsKey : STD_LOGIC; + signal Sort_Valid : std_logic; + signal Sort_IsKey : std_logic; signal Sort_Data : T_DATA_VECTOR(INPUTS - 1 downto 0); - signal Sort_Meta : STD_LOGIC_VECTOR(META_BITS - 1 downto 0); + signal Sort_Meta : std_logic_vector(META_BITS - 1 downto 0); signal DataInputMatrix : T_SLM(INPUTS - 1 downto 0, DATA_BITS - 1 downto 0); signal DataOutputMatrix : T_SLM(INPUTS - 1 downto 0, DATA_BITS - 1 downto 0); @@ -114,10 +114,10 @@ begin simInitialize; simWriteMessage("SETTINGS"); - simWriteMessage(" INPUTS: " & INTEGER'image(INPUTS)); - simWriteMessage(" KEY_BITS: " & INTEGER'image(KEY_BITS)); - simWriteMessage(" DATA_BITS: " & INTEGER'image(DATA_BITS)); - simWriteMessage(" REG AFTER: " & INTEGER'image(PIPELINE_STAGE_AFTER)); + simWriteMessage(" INPUTS: " & integer'image(INPUTS)); + simWriteMessage(" KEY_BITS: " & integer'image(KEY_BITS)); + simWriteMessage(" DATA_BITS: " & integer'image(DATA_BITS)); + simWriteMessage(" REG AFTER: " & integer'image(PIPELINE_STAGE_AFTER)); -- generate global testbench clock simGenerateClock(Clock, CLOCK_FREQ); @@ -127,9 +127,9 @@ begin variable RandomVar : RandomPType; -- protected type from RandomPkg - variable KeyInput : STD_LOGIC_VECTOR(KEY_BITS - 1 downto 0); - variable DataInput : STD_LOGIC_VECTOR(DATA_BITS - KEY_BITS - 1 downto 0); - variable TagInput : STD_LOGIC_VECTOR(TAG_BITS - 1 downto 0); + variable KeyInput : std_logic_vector(KEY_BITS - 1 downto 0); + variable DataInput : std_logic_vector(DATA_BITS - KEY_BITS - 1 downto 0); + variable TagInput : std_logic_vector(TAG_BITS - 1 downto 0); begin RandomVar.InitSeed(RandomVar'instance_name); -- Generate initial seeds @@ -191,9 +191,9 @@ begin procChecker : process constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess("Checker"); - variable Check : BOOLEAN; - variable CurValue : UNSIGNED(KEY_BITS - 1 downto 0); - variable LastValue : UNSIGNED(KEY_BITS - 1 downto 0); + variable Check : boolean; + variable CurValue : unsigned(KEY_BITS - 1 downto 0); + variable LastValue : unsigned(KEY_BITS - 1 downto 0); begin wait until rising_edge(Sort_Valid); diff --git a/tb/sort/sortnet/sortnet_Stream_Adapter2_tb.vhdl b/tb/sort/sortnet/sortnet_Stream_Adapter2_tb.vhdl index fd39c21b..25d2cf4d 100644 --- a/tb/sort/sortnet/sortnet_Stream_Adapter2_tb.vhdl +++ b/tb/sort/sortnet/sortnet_Stream_Adapter2_tb.vhdl @@ -37,7 +37,7 @@ library PoC; use PoC.utils.all; use PoC.vectors.all; use PoC.physical.all; -use PoC.sortnet.ALL; +use PoC.sortnet.all; -- simulation only packages use PoC.sim_types.all; use PoC.simulation.all; @@ -52,51 +52,51 @@ end entity; architecture tb of sortnet_Stream_Adapter2_tb is - constant DEBUG : BOOLEAN := TRUE; + constant DEBUG : boolean := TRUE; - constant TAG_BITS : POSITIVE := 4; + constant TAG_BITS : positive := 4; - constant STREAM_DATA_BITS : POSITIVE := ite(DEBUG, 16, 32); - constant STREAM_META_BITS : POSITIVE := TAG_BITS; + constant STREAM_DATA_BITS : positive := ite(DEBUG, 16, 32); + constant STREAM_META_BITS : positive := TAG_BITS; - constant DATA_COLUMNS : POSITIVE := 2; + constant DATA_COLUMNS : positive := 2; - constant SORTNET_SIZE : POSITIVE := ite(DEBUG, 8, 32); --128); - constant SORTNET_KEY_BITS : POSITIVE := ite(DEBUG, 8, 32); - constant SORTNET_DATA_BITS : POSITIVE := ite(DEBUG, 16, 64); - constant SORTNET_REG_AFTER : POSITIVE := 2; + constant SORTNET_SIZE : positive := ite(DEBUG, 8, 32); --128); + constant SORTNET_KEY_BITS : positive := ite(DEBUG, 8, 32); + constant SORTNET_DATA_BITS : positive := ite(DEBUG, 16, 64); + constant SORTNET_REG_AFTER : positive := 2; - constant MERGENET_STAGES : POSITIVE := ite(DEBUG, 2, 4); + constant MERGENET_STAGES : positive := ite(DEBUG, 2, 4); - constant LOOP_COUNT : POSITIVE := 2; - constant SORTNET_BLOCK_COUNT : POSITIVE := 2**MERGENET_STAGES * DATA_COLUMNS * LOOP_COUNT; --ite(DEBUG, 10, 32); --1024); + constant LOOP_COUNT : positive := 2; + constant SORTNET_BLOCK_COUNT : positive := 2**MERGENET_STAGES * DATA_COLUMNS * LOOP_COUNT; --ite(DEBUG, 10, 32); --1024); -- constant STAGES : POSITIVE := SORTNET_SIZE; - constant DELAY : NATURAL := 3 * 2**MERGENET_STAGES * SORTNET_SIZE + 50; --STAGES / PIPELINE_STAGE_AFTER; + constant DELAY : natural := 3 * 2**MERGENET_STAGES * SORTNET_SIZE + 50; --STAGES / PIPELINE_STAGE_AFTER; constant CLOCK_FREQ : FREQ := 100 MHz; - signal Clock : STD_LOGIC := '1'; + signal Clock : std_logic := '1'; - signal Generator_Valid : STD_LOGIC; - signal Generator_Data : STD_LOGIC_VECTOR(STREAM_DATA_BITS - 1 downto 0); - signal Generator_SOF : STD_LOGIC; - signal Generator_IsKey : STD_LOGIC; - signal Generator_EOF : STD_LOGIC; - signal Generator_Meta : STD_LOGIC_VECTOR(TAG_BITS - 1 downto 0); + signal Generator_Valid : std_logic; + signal Generator_Data : std_logic_vector(STREAM_DATA_BITS - 1 downto 0); + signal Generator_SOF : std_logic; + signal Generator_IsKey : std_logic; + signal Generator_EOF : std_logic; + signal Generator_Meta : std_logic_vector(TAG_BITS - 1 downto 0); - signal Sort_Out_Valid : STD_LOGIC; - signal Sort_Out_Data : STD_LOGIC_VECTOR(STREAM_DATA_BITS - 1 downto 0); - signal Sort_Out_IsKey : STD_LOGIC; + signal Sort_Out_Valid : std_logic; + signal Sort_Out_Data : std_logic_vector(STREAM_DATA_BITS - 1 downto 0); + signal Sort_Out_IsKey : std_logic; - signal Tester_Ack : STD_LOGIC; + signal Tester_Ack : std_logic; begin -- initialize global simulation status simInitialize; simWriteMessage("SETTINGS"); - simWriteMessage(" SORTNET_BLOCK_COUNT: " & INTEGER'image(SORTNET_BLOCK_COUNT)); - simWriteMessage(" BYTES TRANSFERED: " & INTEGER'image(SORTNET_BLOCK_COUNT * SORTNET_SIZE * SORTNET_DATA_BITS / 8)); + simWriteMessage(" SORTNET_BLOCK_COUNT: " & integer'image(SORTNET_BLOCK_COUNT)); + simWriteMessage(" BYTES TRANSFERED: " & integer'image(SORTNET_BLOCK_COUNT * SORTNET_SIZE * SORTNET_DATA_BITS / 8)); -- generate global testbench clock simGenerateClock(Clock, CLOCK_FREQ); @@ -105,9 +105,9 @@ begin constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess("Generator"); variable RandomVar : RandomPType; -- protected type from RandomPkg - variable KeyInput : STD_LOGIC_VECTOR(SORTNET_KEY_BITS - 1 downto 0); - variable DataInput : STD_LOGIC_VECTOR(SORTNET_DATA_BITS - SORTNET_KEY_BITS - 1 downto 0); - variable TagInput : STD_LOGIC_VECTOR(TAG_BITS - 1 downto 0); + variable KeyInput : std_logic_vector(SORTNET_KEY_BITS - 1 downto 0); + variable DataInput : std_logic_vector(SORTNET_DATA_BITS - SORTNET_KEY_BITS - 1 downto 0); + variable TagInput : std_logic_vector(TAG_BITS - 1 downto 0); begin RandomVar.InitSeed(RandomVar'instance_name); -- Generate initial seeds @@ -187,9 +187,9 @@ begin procChecker : process constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess("Checker"); - variable Check : BOOLEAN; - variable CurValue : UNSIGNED(SORTNET_KEY_BITS - 1 downto 0); - variable LastValue : UNSIGNED(SORTNET_KEY_BITS - 1 downto 0); + variable Check : boolean; + variable CurValue : unsigned(SORTNET_KEY_BITS - 1 downto 0); + variable LastValue : unsigned(SORTNET_KEY_BITS - 1 downto 0); begin Tester_Ack <= '0'; diff --git a/tb/sort/sortnet/sortnet_Stream_Adapter_tb.vhdl b/tb/sort/sortnet/sortnet_Stream_Adapter_tb.vhdl index 3f14fee0..c8b9d8d3 100644 --- a/tb/sort/sortnet/sortnet_Stream_Adapter_tb.vhdl +++ b/tb/sort/sortnet/sortnet_Stream_Adapter_tb.vhdl @@ -37,7 +37,7 @@ library PoC; use PoC.utils.all; use PoC.vectors.all; use PoC.physical.all; -use PoC.sortnet.ALL; +use PoC.sortnet.all; -- simulation only packages use PoC.sim_types.all; use PoC.simulation.all; @@ -52,35 +52,35 @@ end entity; architecture tb of sortnet_Stream_Adapter_tb is - constant DEBUG : BOOLEAN := TRUE; + constant DEBUG : boolean := TRUE; - constant STREAM_DATA_BITS : POSITIVE := ite(DEBUG, 16, 32); + constant STREAM_DATA_BITS : positive := ite(DEBUG, 16, 32); - constant SORTNET_SIZE : POSITIVE := ite(DEBUG, 8, 128); - constant SORTNET_KEY_BITS : POSITIVE := ite(DEBUG, 8, 32); - constant SORTNET_DATA_BITS : POSITIVE := ite(DEBUG, 16, 64); + constant SORTNET_SIZE : positive := ite(DEBUG, 8, 128); + constant SORTNET_KEY_BITS : positive := ite(DEBUG, 8, 32); + constant SORTNET_DATA_BITS : positive := ite(DEBUG, 16, 64); - constant LOOP_COUNT : POSITIVE := ite(DEBUG, 10, 32); --1024); + constant LOOP_COUNT : positive := ite(DEBUG, 10, 32); --1024); - constant STAGES : POSITIVE := SORTNET_SIZE; - constant DELAY : NATURAL := 50; --STAGES / PIPELINE_STAGE_AFTER; + constant STAGES : positive := SORTNET_SIZE; + constant DELAY : natural := 50; --STAGES / PIPELINE_STAGE_AFTER; constant CLOCK_FREQ : FREQ := 100 MHz; - signal Clock : STD_LOGIC := '1'; + signal Clock : std_logic := '1'; - constant TAG_BITS : POSITIVE := 2; - signal Generator_Valid : STD_LOGIC; - signal Generator_Data : STD_LOGIC_VECTOR(STREAM_DATA_BITS - 1 downto 0); - signal Generator_IsKey : STD_LOGIC; - signal Generator_Tag : STD_LOGIC_VECTOR(TAG_BITS - 1 downto 0); + constant TAG_BITS : positive := 2; + signal Generator_Valid : std_logic; + signal Generator_Data : std_logic_vector(STREAM_DATA_BITS - 1 downto 0); + signal Generator_IsKey : std_logic; + signal Generator_Tag : std_logic_vector(TAG_BITS - 1 downto 0); - signal Sort_Out_Valid : STD_LOGIC; - signal Sort_Out_Data : STD_LOGIC_VECTOR(STREAM_DATA_BITS - 1 downto 0); - signal Sort_Out_IsKey : STD_LOGIC; + signal Sort_Out_Valid : std_logic; + signal Sort_Out_Data : std_logic_vector(STREAM_DATA_BITS - 1 downto 0); + signal Sort_Out_IsKey : std_logic; - signal Tester_Ack : STD_LOGIC; + signal Tester_Ack : std_logic; - signal StopSimulation : STD_LOGIC := '0'; + signal StopSimulation : std_logic := '0'; begin -- initialize global simulation status simInitialize; @@ -92,8 +92,8 @@ begin constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess("Generator"); variable RandomVar : RandomPType; -- protected type from RandomPkg - variable KeyInput : STD_LOGIC_VECTOR(SORTNET_KEY_BITS - 1 downto 0); - variable DataInput : STD_LOGIC_VECTOR(SORTNET_DATA_BITS - SORTNET_KEY_BITS - 1 downto 0); + variable KeyInput : std_logic_vector(SORTNET_KEY_BITS - 1 downto 0); + variable DataInput : std_logic_vector(SORTNET_DATA_BITS - SORTNET_KEY_BITS - 1 downto 0); begin RandomVar.InitSeed(RandomVar'instance_name); -- Generate initial seeds @@ -161,11 +161,11 @@ begin procChecker : process constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess("Checker"); - variable Check : BOOLEAN; - variable CurValue : UNSIGNED(SORTNET_KEY_BITS - 1 downto 0); - variable LastValue : UNSIGNED(SORTNET_KEY_BITS - 1 downto 0); + variable Check : boolean; + variable CurValue : unsigned(SORTNET_KEY_BITS - 1 downto 0); + variable LastValue : unsigned(SORTNET_KEY_BITS - 1 downto 0); begin - report "Delay=" & INTEGER'image(DELAY) severity NOTE; + report "Delay=" & integer'image(DELAY) severity NOTE; Tester_Ack <= '0'; diff --git a/tools/Notepad++/Syntax Highlighting - PoC Config.xml b/tools/Notepad++/Syntax Highlighting - PoC Config.xml new file mode 100644 index 00000000..a7154bd7 --- /dev/null +++ b/tools/Notepad++/Syntax Highlighting - PoC Config.xml @@ -0,0 +1,64 @@ + + + + + + + + 00# 01 02 03 04 + + + + + + + + = + + + + + + + + + + + InstallationDirectory Name DirectoryName HDLSourceFiles TestbenchFiles Prefix EntityPrefix FilesFile RulesFile Description Version BinaryDirectory Backend NetlistFiles ConstraintFiles SimulatorFiles TemporaryFiles PrecompiledFiles ActiveHDLFiles RivieraPROFiles AlteraSpecificFiles QuartusSynthesisFiles CocotbFiles GHDLFiles GTKWaveFiles LatticeSpecificFiles LatticeSynthesisFiles ModelSimFiles QuestaSimFiles XilinxSpecificFiles ISESynthesisFiles ISECoreGeneratorFiles ISESimulatorFiles VivadoSimulatorFiles + SrcDir TBDir RelDir SimDir NLDir XSTDir QIIDir + [DEFAULT] [PoC.DEFAULT] [TB.DEFAULT] [COCOTB.DEFAULT] [XST.DEFAULT] [CG.DEFAULT] [QII.DEFAULT] + VHDLTestbench CocoTestbench XSTNetlist QuartusNetlist CGNetlist LSENetlist + None Namespace Entity + [PoC] [Solutions] + [Aldec [Altera [Mentor [GHDL [GNU [GTKWave [Lattice [Xilinx [Synopsys + + 00%{ 01 02} 03${ 04$ 05} 06[PoC. 07 08] 09[TB. 09[COCOTB. 10 11] 11] 12[IP. 13 14] 15[XST. 15[CG. 15[QII. 15[LSE. 16 17] 17] 17] 17] 18 19 20 21 22 23 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/tools/Notepad++/Syntax Highlighting - PoC Files.xml b/tools/Notepad++/Syntax Highlighting - PoC Files.xml new file mode 100644 index 00000000..88c59115 --- /dev/null +++ b/tools/Notepad++/Syntax Highlighting - PoC Files.xml @@ -0,0 +1,64 @@ + + + + + + + + 00# 01 02 03 04 + + + + + + + + = != < <= > >= and or xor not ? in / & + + + + + + + + + + + if then elseif else end vhdl verilog cocotb include library ucf xdc sdc ldc report path + Tool ToolChain DeviceVendor DeviceFamily DeviceGeneration DeviceSeries BoardName VHDLVersion + poc test osvvm vunit_lib unisim unimacro unifast simprim secureip altera altera_mf l_ + EMACS vim kate + + + + + 00( 01 02) 03" 04 05" 06[ 07 08] 09" 10 11" 12${ 13 14} 15 16 17 18 19 20 21 22 23 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/tools/Notepad++/Syntax Highlighting - PoC Rules.xml b/tools/Notepad++/Syntax Highlighting - PoC Rules.xml new file mode 100644 index 00000000..0d8becc1 --- /dev/null +++ b/tools/Notepad++/Syntax Highlighting - PoC Rules.xml @@ -0,0 +1,64 @@ + + + + + + + + 00# 01 02 03 04 + + + + + + + + + + + + + + + + + + + End PreProcessRules PostProcessRules Copy To File Replace With Options Multiline DotAll Delete CaseInsensitive AppendLine + + + + + + + + 00" 01\ 02" 03${ 04 05} 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/tools/Travis-CI/config.private.ini b/tools/Travis-CI/config.private.ini index 5dd25616..fec7939f 100644 --- a/tools/Travis-CI/config.private.ini +++ b/tools/Travis-CI/config.private.ini @@ -1,5 +1,5 @@ [INSTALL.PoC] -Version = 0.0.0 +Version = 1.0.0 InstallationDirectory = /home/travis/build/VLSI-EDA/PoC [SOLUTION.Solutions] @@ -16,6 +16,7 @@ InstallationDirectory = /home/travis/build/VLSI-EDA/PoC Version = 0.34dev InstallationDirectory = ${INSTALL.PoC:InstallationDirectory}/temp/Travis-CI BinaryDirectory = ${InstallationDirectory}/bin +ScriptDirectory = ${InstallationDirectory}/lib/ghdl/vendors Backend = llvm [INSTALL.Lattice] diff --git a/tools/Travis-CI/ghdl.setup.sh b/tools/Travis-CI/ghdl.setup.sh index eaad3cc5..8ca2c815 100755 --- a/tools/Travis-CI/ghdl.setup.sh +++ b/tools/Travis-CI/ghdl.setup.sh @@ -1,9 +1,9 @@ -#! /bin/bash +#! /usr/bin/env bash # configure variables in the section below GHDL_BACKEND="llvm" GHDL_VERSION="0.34dev" -RELEASE_DATE="2016-05-03" +RELEASE_DATE="2016-09-14" GITHUB_SERVER="https://github.com" GITHUB_SLUG="tgingold/ghdl" @@ -26,7 +26,6 @@ GITHUB_URL="$GITHUB_SERVER/$GITHUB_SLUG/releases/download/$GITHUB_TAGNAME/$GITHU # other variables # -------------------------------------- GITROOT=$(pwd) -POCROOT=$(pwd) GHDL_TARBALL="ghdl.tgz" # define color escape codes @@ -47,7 +46,7 @@ cd $TRAVIS_DIR # downloading GHDL echo -e "${CYAN}Downloading $GHDL_TARBALL from $GITHUB_URL...${NOCOLOR}" -wget -q --show-progress $GITHUB_URL -O $GHDL_TARBALL +wget -q $GITHUB_URL -O $GHDL_TARBALL if [ $? -eq 0 ]; then echo -e "${GREEN}Download [SUCCESSFUL]${NOCOLOR}" else diff --git a/tools/Travis-CI/ghdl/compile-osvvm.sh b/tools/Travis-CI/ghdl/compile-osvvm.sh new file mode 100755 index 00000000..ab9c553f --- /dev/null +++ b/tools/Travis-CI/ghdl/compile-osvvm.sh @@ -0,0 +1,223 @@ +#! /usr/bin/env bash +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# +# ============================================================================== +# Authors: Patrick Lehmann +# +# Bash Script: Script to compile the OSVVM library for GHDL on Linux +# +# Description: +# ------------------------------------ +# This is a Bash script (executable) which: +# - creates a subdirectory in the current working directory +# - compiles all OSVVM packages +# +# ============================================================================== +# Copyright (C) 2015-2016 Patrick Lehmann +# +# GHDL is free software; you can redistribute it and/or modify it under +# the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 2, or (at your option) any later +# version. +# +# GHDL is distributed in the hope that it will be useful, but WITHOUT ANY +# WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# for more details. +# +# You should have received a copy of the GNU General Public License +# along with GHDL; see the file COPYING. If not, write to the Free +# Software Foundation, 59 Temple Place - Suite 330, Boston, MA +# 02111-1307, USA. +# ============================================================================== + +# --------------------------------------------- +# work around for Darwin (Mac OS) +READLINK=readlink; if [[ $(uname) == "Darwin" ]]; then READLINK=greadlink; fi + +# save working directory +WorkingDir=$(pwd) +ScriptDir="$(dirname $0)" +ScriptDir="$($READLINK -f $ScriptDir)" + +# source configuration file from GHDL's 'vendors' library directory +source $ScriptDir/config.sh +source $ScriptDir/shared.sh + +# command line argument processing +NO_COMMAND=1 +SUPPRESS_WARNINGS=0 +HALT_ON_ERROR=0 +GHDLBinDir="" +DestDir="" +SrcDir="" +while [[ $# > 0 ]]; do + key="$1" + case $key in + -c|--clean) + CLEAN=TRUE + NO_COMMAND=0 + ;; + -a|--all) + COMPILE_ALL=TRUE + NO_COMMAND=0 + ;; + --osvvm) + COMPILE_OSVVM=TRUE + NO_COMMAND=0 + ;; + -h|--help) + HELP=TRUE + NO_COMMAND=0 + ;; + -n|--no-warnings) + SUPPRESS_WARNINGS=1 + ;; + -H|--halt-on-error) + HALT_ON_ERROR=1 + ;; + --ghdl) + GHDLBinDir="$2" + shift # skip argument + ;; + --src) + SrcDir="$2" + shift # skip argument + ;; + --out) + DestDir="$2" + shift # skip argument + ;; + *) # unknown option + echo 1>&2 -e "${COLORED_ERROR} Unknown command line option '$key'.${ANSI_NOCOLOR}" + exit -1 + ;; + esac + shift # skip argument or value +done + +# makes no sense to enable it for OSVVM +SKIP_EXISTING_FILES=0 + +if [ $NO_COMMAND -eq 1 ]; then + HELP=TRUE +fi + +if [ "$HELP" == "TRUE" ]; then + test $NO_COMMAND -eq 1 && echo 1>&2 -e "\n${COLORED_ERROR} No command selected." + echo "" + echo "Synopsis:" + echo " A script to compile the simulation library 'OSVVM' for GHDL on Linux." + echo " A library folder 'osvvm/v08' will be created relative to the current" + echo " working directory." + echo "" + echo " Use the adv. options or edit 'config.sh' to supply paths and default params." + echo "" + echo "Usage:" + echo " compile-osvvm.sh | [] []" + echo "" + echo "Common commands:" + echo " -h --help Print this help page" + echo " -c --clean Remove all generated files" + echo "" + echo "Libraries:" + echo " -a --all Compile all libraries." + echo " --osvvm Compile library osvvm." + echo "" + echo "Library compile options:" + echo " -H --halt-on-error Halt on error(s)." + echo "" + echo "Advanced options:" + echo " --ghdl Path to GHDL's binary e.g. /usr/local/bin/ghdl." + echo " --out Name of the output directory." + echo " --src Path to the source directory." + echo "" + echo "Verbosity:" + echo " -n --no-warnings Suppress all warnings. Show only error messages." + echo "" + exit 0 +fi + +if [ "$COMPILE_ALL" == "TRUE" ]; then + COMPILE_OSVVM=TRUE +fi + + +# -> $SourceDirectories +# -> $DestinationDirectories +# -> $SrcDir +# -> $DestDir +# -> $GHDLBinDir +# <= $SourceDirectory +# <= $DestinationDirectory +# <= $GHDLBinary +SetupDirectories OSVVM "OSVVM" + +# create "osvvm" directory and change to it +# => $DestinationDirectory +CreateDestinationDirectory +cd $DestinationDirectory + + +# => $SUPPRESS_WARNINGS +# <= $GRC_COMMAND +SetupGRCat + + +# define global GHDL Options +GHDL_OPTIONS=(-fexplicit -frelaxed-rules --no-vital-checks --warn-binding --mb-comments) + + +# Cleanup directory +# ============================================================================== +if [ "$CLEAN" == "TRUE" ]; then + echo -e "${ANSI_YELLOW}Cleaning up directory ...${ANSI_NOCOLOR}" + rm *.o 2> /dev/null + rm *.cf 2> /dev/null +fi + + +# create local set of GHDL parameters +GHDL_PARAMS=(${GHDL_OPTIONS[@]}) +GHDL_PARAMS+=(--std=08) +VHDLVersion="v08" + +# Library osvvm +# ============================================================================== +# compile osvvm packages +ERRORCOUNT=0 +if [ "$COMPILE_OSVVM" == "TRUE" ]; then + Library="osvvm" + Files=( + NamePkg.vhd + OsvvmGlobalPkg.vhd + TextUtilPkg.vhd + TranscriptPkg.vhd + AlertLogPkg.vhd + MemoryPkg.vhd + MessagePkg.vhd + SortListPkg_int.vhd + RandomBasePkg.vhd + RandomPkg.vhd + CoveragePkg.vhd + OsvvmContext.vhd + ) + + # append absolute source path + SourceFiles=() + for File in ${Files[@]}; do + SourceFiles+=("$SourceDirectory/$File") + done + + GHDLCompilePackages +fi + +echo "--------------------------------------------------------------------------------" +echo -n "Compiling OSVVM packages " +if [ $ERRORCOUNT -gt 0 ]; then + echo -e $COLORED_FAILED +else + echo -e $COLORED_SUCCESSFUL +fi diff --git a/tools/Travis-CI/ghdl/config.sh b/tools/Travis-CI/ghdl/config.sh new file mode 100644 index 00000000..6eb3125f --- /dev/null +++ b/tools/Travis-CI/ghdl/config.sh @@ -0,0 +1,70 @@ +#! /bin/bash +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# +# ============================================================================== +# Authors: Patrick Lehmann +# +# Bash Script: Configurable directories to local installed tools +# +# Description: +# ------------------------------------ +# This Bash file exports variables containing the users local tool environment. +# +# ============================================================================== +# Copyright (C) 2015-2016 Patrick Lehmann +# +# GHDL is free software; you can redistribute it and/or modify it under +# the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 2, or (at your option) any later +# version. +# +# GHDL is distributed in the hope that it will be useful, but WITHOUT ANY +# WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# for more details. +# +# You should have received a copy of the GNU General Public License +# along with GHDL; see the file COPYING. If not, write to the Free +# Software Foundation, 59 Temple Place - Suite 330, Boston, MA +# 02111-1307, USA. +# ============================================================================== + + +# Configure +# - vendor tool chain installation paths or +# - library root directories +# in the following dictionary. +# +# These values are used if no command line argument (--src) is passed to a +# compile script. Empty strings means not configured. +declare -A InstallationDirectories +InstallationDirectories[AlteraQuartus]="" # "/opt/altera/16.0/quartus" +InstallationDirectories[LatticeDiamond]="" # "/usr/local/diamond/3.7_x64" +InstallationDirectories[OSVVM]="" # "~/git/github/osvvm" +InstallationDirectories[VUnit]="" # "~/git/github/vunit" +InstallationDirectories[XilinxISE]="" # "/opt/Xilinx/14.7/ISE_DS/ISE" +InstallationDirectories[XilinxVivado]="" # "/opt/Xilinx/Vivado/2016.2" + +# Configure preferred output directories for each library set: +declare -A DestinationDirectories +DestinationDirectories[AlteraQuartus]="altera" +DestinationDirectories[LatticeDiamond]="lattice" +DestinationDirectories[OSVVM]="." # "osvvm" +DestinationDirectories[VUnit]="." # "vunit_lib" +DestinationDirectories[XilinxISE]="xilinx-ise" +DestinationDirectories[XilinxVivado]="xilinx-vivado" + +# Declare source directories depending on the installation paths: +declare -A SourceDirectories +SourceDirectories[AlteraQuartus]="eda/sim_lib" +SourceDirectories[XilinxISE]="vhdl/src" +SourceDirectories[XilinxVivado]="data/vhdl/src" +SourceDirectories[LatticeDiamond]="cae_library/simulation/vhdl" +SourceDirectories[OSVVM]="." +SourceDirectories[VUnit]="vunit/vhdl" + +# input files greater than $LARGE_FILESIZE are skipped if '--skip-largefiles' is set +LARGE_FILESIZE=125000 + diff --git a/tools/Travis-CI/ghdl/ghdl.grcrules b/tools/Travis-CI/ghdl/ghdl.grcrules new file mode 100644 index 00000000..1bc60783 --- /dev/null +++ b/tools/Travis-CI/ghdl/ghdl.grcrules @@ -0,0 +1,15 @@ +# color warnings +regexp=^.*?:\d+:\d+:warning: .* +colours=yellow +count=stop +========= + +# color errors +regexp=^.*?:\d+:\d+: .* +colours=red +count=stop +========= + +# skip additional message line on Linux +regexp=^ghdl: compilation error +skip=yes diff --git a/tools/Travis-CI/ghdl/ghdl.skipwarning.grcrules b/tools/Travis-CI/ghdl/ghdl.skipwarning.grcrules new file mode 100644 index 00000000..0609b060 --- /dev/null +++ b/tools/Travis-CI/ghdl/ghdl.skipwarning.grcrules @@ -0,0 +1,14 @@ +# skip warnings +regexp=^.*?:\d+:\d+:warning: .* +skip=yes +========= + +# color errors +regexp=^.*?:\d+:\d+: .* +colours=red +count=stop +========= + +# skip additional message line on Linux +regexp=^ghdl: compilation error +skip=yes diff --git a/tools/Travis-CI/ghdl/shared.sh b/tools/Travis-CI/ghdl/shared.sh new file mode 100644 index 00000000..3c413bec --- /dev/null +++ b/tools/Travis-CI/ghdl/shared.sh @@ -0,0 +1,198 @@ +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# +# ============================================================================== +# Authors: Patrick Lehmann +# +# Bash Script: This is a Bash resource file. +# +# Description: +# ------------------------------------ +# TODO +# +# ============================================================================== +# Copyright (C) 2015 Patrick Lehmann +# +# GHDL is free software; you can redistribute it and/or modify it under +# the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 2, or (at your option) any later +# version. +# +# GHDL is distributed in the hope that it will be useful, but WITHOUT ANY +# WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# for more details. +# +# You should have received a copy of the GNU General Public License +# along with GHDL; see the file COPYING. If not, write to the Free +# Software Foundation, 59 Temple Place - Suite 330, Boston, MA +# 02111-1307, USA. +# ============================================================================== + +ANSI_RED="\e[31m" +ANSI_GREEN="\e[32m" +ANSI_YELLOW="\e[33m" +ANSI_BLUE="\e[34m" +ANSI_MAGENTA="\e[35m" +ANSI_CYAN="\e[36;1m" +ANSI_NOCOLOR="\e[0m" + +# red texts +COLORED_ERROR="$ANSI_RED[ERROR]$ANSI_NOCOLOR" +COLORED_FAILED="$ANSI_RED[FAILED]$ANSI_NOCOLOR" + +# green texts +COLORED_DONE="$ANSI_GREEN[DONE]$ANSI_NOCOLOR" +COLORED_SUCCESSFUL="$ANSI_GREEN[SUCCESSFUL]$ANSI_NOCOLOR" + +# set bash options +set -o pipefail + +SetupDirectories() { + Index=$1 + Name=$2 + + # source directory + # ---------------------- + # If a command line argument ('--src') was passed in, use it, else use the default value + # from config.sh + if [ ! -z "$SrcDir" ]; then + SourceDirectory=${SrcDir%/} # remove trailing slashes + elif [ ! -z "$EnvSourceDir" ]; then + SourceDirectory=$EnvSourceDir # fall back to environment variable + elif [ ! -z "${InstallationDirectories[$Index]}" ]; then + SourceDirectory=${InstallationDirectories[$Index]}/${SourceDirectories[$Index]} # fall back to value from config.sh + fi + # output directory + # ---------------------- + # If a command line argument ('--out') was passed in, use it, else use the default value + # from config.sh + if [ ! -z "$DestDir" ]; then + DestinationDirectory=${DestDir%/} # remove trailing slashes + else + DestinationDirectory=${DestinationDirectories[$Index]} # fall back to value from config.sh + fi + + if [ -z $SourceDirectory ] || [ -z $DestinationDirectory ]; then + echo 1>&2 -e "${COLORED_ERROR} $Name is not configured in '$ScriptDir/config.sh'${ANSI_NOCOLOR}" + echo 1>&2 -e " Use adv. options '--src' and '--out' or configure 'config.sh'." + exit -1 + elif [ ! -d $SourceDirectory ]; then + echo 1>&2 -e "${COLORED_ERROR} Path '$SourceDirectory' does not exist.${ANSI_NOCOLOR}" + exit -1 + fi + + # Resolve paths to an absolute paths + SourceDirectory=$(readlink -f $SourceDirectory) + if [[ ! "$DestinationDirectory" = /* ]]; then + DestinationDirectory=$WorkingDir/$DestinationDirectory + fi + + # Use GHDL binary directory from command line argument, if set + if [ ! -z "$GHDLBinDir" ]; then + GHDLBinary=${GHDLBinDir%/}/ghdl # remove trailing slashes + if [[ ! -x "$GHDLBinary" ]]; then + echo 1>&2 -e "${COLORED_ERROR} GHDL not found or is not executable.${ANSI_NOCOLOR}" + exit -1 + fi + elif [ ! -z "$GHDL" ]; then + if [ ! \( -f "$GHDL" -a -x "$GHDL" \) ]; then + echo 1>&2 -e "${COLORED_ERROR} Found GHDL environment variable, but '$GHDL' is not executable.${ANSI_NOCOLOR}" + exit -1 + fi + GHDLBinary=$GHDL + else # fall back to GHDL found via PATH + GHDLBinary=$(which ghdl 2>/dev/null) + if [ $? -ne 0 ]; then + echo 1>&2 -e "${COLORED_ERROR} GHDL not found in PATH.${ANSI_NOCOLOR}" + echo 1>&2 -e " Use adv. options '--ghdl' to set the GHDL binary directory." + exit -1 + fi + fi +} + +SetupGRCat() { + if [ -z "$(which grcat 2>/dev/null)" ]; then + # if grcat (generic colourizer) is not installed, use a dummy pipe command like 'cat' + GRC_COMMAND="cat" + elif [ $SUPPRESS_WARNINGS -eq 1 ]; then + GRC_COMMAND="grcat $ScriptDir/ghdl.skipwarning.grcrules" + else + GRC_COMMAND="grcat $ScriptDir/ghdl.grcrules" + fi +} + +CreateDestinationDirectory() { + if [ -d "$DestinationDirectory" ]; then + echo -e "${ANSI_YELLOW}Vendor directory '$DestinationDirectory' already exists.${ANSI_NOCOLOR}" + elif [ -f "$DestinationDirectory" ]; then + echo 1>&2 -e "${COLORED_ERROR} Vendor directory '$DestinationDirectory' already exists as a file.${ANSI_NOCOLOR}" + exit -1 + else + echo -e "${ANSI_YELLOW}Creating vendor directory: '$DestinationDirectory'${ANSI_NOCOLOR}" + mkdir -p "$DestinationDirectory" + fi +} + +GHDLSetup() { + if [ $VHDLStandard -eq 93 ]; then + VHDLVersion="v93" + VHDLStandard="93c" + VHDLFlavor="synopsys" + elif [ $VHDLStandard -eq 2008 ]; then + VHDLVersion="v08" + VHDLStandard="08" + VHDLFlavor="standard" + fi +} + +GHDLCompileLibrary() { + # assembling output directory + LibraryDirectory=$DestinationDirectory/$Library/$VHDLVersion + mkdir -p $LibraryDirectory + cd $LibraryDirectory + echo -e "${ANSI_YELLOW}Compiling library '$Library'...${ANSI_NOCOLOR}" + + for File in ${SourceFiles[@]}; do + FileName=$(basename "$File") + FileSize=($(wc -c $File)) + if [ $SKIP_EXISTING_FILES -eq 1 ] && [ -e "${FileName%.*}.o" ]; then + echo -e "${ANSI_CYAN}Skipping existing file '$File'${ANSI_NOCOLOR}" + elif [ $SKIP_LARGE_FILES -eq 1 ] && [ ${FileSize[0]} -gt $LARGE_FILESIZE ]; then + echo -e "${ANSI_CYAN}Skipping large file '$File'${ANSI_NOCOLOR}" + else + echo -e "${ANSI_CYAN}Analyzing file '$File'${ANSI_NOCOLOR}" + $GHDLBinary -a ${GHDL_PARAMS[@]} --work=$Library "$File" 2>&1 | $GRC_COMMAND + if [ $? -ne 0 ]; then + let ERRORCOUNT++ + test $HALT_ON_ERROR -eq 1 && return 1 + fi + fi + done + return 0 +} + +GHDLCompilePackages() { + # assembling output directory + LibraryDirectory=$DestinationDirectory/$Library/$VHDLVersion + mkdir -p $LibraryDirectory + cd $LibraryDirectory + echo -e "${ANSI_YELLOW}Compiling library '$Library'...${ANSI_NOCOLOR}" + + for File in ${SourceFiles[@]}; do + FileName=$(basename "$File") + if [ $SKIP_EXISTING_FILES -eq 1 ] && [ -e "${FileName%.*}.o" ]; then + echo -e "${ANSI_CYAN}Skipping existing package '$File'${ANSI_NOCOLOR}" + else + echo -e "${ANSI_CYAN}Analyzing package '$File'${ANSI_NOCOLOR}" + $GHDLBinary -a ${GHDL_PARAMS[@]} --work=$Library "$File" 2>&1 | $GRC_COMMAND + if [ $? -ne 0 ]; then + let ERRORCOUNT++ + test $HALT_ON_ERROR -eq 1 && return 1 + fi + fi + done + return 0 +} + diff --git a/tools/Travis-CI/grc.setup.sh b/tools/Travis-CI/grc.setup.sh index 175e94ad..2adc0f15 100755 --- a/tools/Travis-CI/grc.setup.sh +++ b/tools/Travis-CI/grc.setup.sh @@ -1,4 +1,4 @@ -#! /bin/bash +#! /usr/bin/env bash # configure variables in the section below GRC_FILE="grc_1.9-1_all.deb" @@ -12,7 +12,6 @@ GRC_URL="http://kassiopeia.juls.savba.sk/~garabik/software/grc/$GRC_FILE" # other variables # -------------------------------------- GITROOT=$(pwd) -POCROOT=$(pwd) GRC_DEB="grc.deb" # define color escape codes @@ -32,7 +31,7 @@ mkdir -p $TEMP_DIR && cd $TEMP_DIR # downloading GHDL echo -e "${CYAN}Downloading $GRC_DEB from $GRC_URL...${NOCOLOR}" -wget -q --show-progress $GRC_URL -O $GRC_DEB +wget -q $GRC_URL -O $GRC_DEB if [ $? -eq 0 ]; then echo -e "${GREEN}Download [SUCCESSFUL]${NOCOLOR}" else diff --git a/tools/Travis-CI/poc.run.sh b/tools/Travis-CI/poc.run.sh index 033d5212..ab726359 100755 --- a/tools/Travis-CI/poc.run.sh +++ b/tools/Travis-CI/poc.run.sh @@ -1,4 +1,4 @@ -#! /bin/bash +#! /usr/bin/env bash POC_GHDL_DIR="temp/ghdl" @@ -29,7 +29,12 @@ if grcat $TRAVIS_DIR/poc.run.grcrules/dev/null; then fi echo -e "Running all testbenches..." -$POCROOT/poc.sh -q ghdl $1 +mode=-q +if [ "x$1" = 'x-d' -o "x$1" = 'x-v' ]; then + mode=$1 + shift +fi +$POCROOT/poc.sh $mode ghdl "$@" ret=$? # Cleanup and exit diff --git a/tools/Travis-CI/poc.setup.sh b/tools/Travis-CI/poc.setup.sh index c6d1b4fb..802c2b4e 100755 --- a/tools/Travis-CI/poc.setup.sh +++ b/tools/Travis-CI/poc.setup.sh @@ -1,4 +1,4 @@ -#! /bin/bash +#! /usr/bin/env bash # define color escape codes RED='\e[0;31m' # Red @@ -18,9 +18,20 @@ if [ $? -ne 0 ]; then exit 1 fi +echo -e "${CYAN}Test PoC front-end script.${NOCOLOR}" +./poc.sh +if [ $? -ne 0 ]; then + echo 1>&2 -e "${RED}Testing PoC front-end script [FAILED]${NOCOLOR}" + exit 1 +fi + echo -e "${CYAN}Copy my_project.vhdl into ./tb/common directory${NOCOLOR}" cp ./tools/Travis-CI/my_project.vhdl ./tb/common if [ $? -ne 0 ]; then echo 1>&2 -e "${RED}Copy of ./tools/Travis-CI/my_project.vhdl [FAILED]${NOCOLOR}" exit 1 fi + +echo -e "${CYAN}Pre-compiling OSVVM with GHDL into ./temp/precompiled/ghdl/osvvm directory${NOCOLOR}" +cd tools/precompile +./compile-osvvm.sh --ghdl diff --git a/tools/git/build_md.py b/tools/git/build_md.py new file mode 100644 index 00000000..729b7600 --- /dev/null +++ b/tools/git/build_md.py @@ -0,0 +1,64 @@ +#!/usr/bin/python3 +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# +# ============================================================================== +# Authors: Thomas B. Preusser +# +# License: +# ============================================================================== +# Copyright 2007-2016 Technische Universitaet Dresden - Germany +# Chair for VLSI-Design, Diagnostics and Architecture +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# distributed under the License is distributed on an "AS IS" BASIS,default +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================== + +""" +[http://stackoverflow.com/questions/18673694/referencing-current-branch-in-github-readme-md] + +Referencing current branch in github readme.md[1] + +This pre-commit hook[2] updates the README.md file's +Travis badge with the current branch. Gist at[4]. + +[1] http://stackoverflow.com/questions/18673694/referencing-current-branch-in-github-readme-md +[2] http://www.git-scm.com/book/en/v2/Customizing-Git-Git-Hooks +[3] https://docs.travis-ci.com/user/status-images/ +[4] https://gist.github.com/dandye/dfe0870a6a1151c89ed9 +""" +from subprocess import check_output, check_call +import os + +# Collecting values to substitute +substitutions = {} +substitutions["BRANCH"] = check_output(["git", "rev-parse", "--abbrev-ref", "HEAD"], universal_newlines=True).strip() +substitutions["GENERATED_HEADER"] = '' + +# Patch templates .tpl to generate specialized .md files +git_root = check_output(['git', 'rev-parse', '--show-toplevel'], universal_newlines=True).strip() +for root, dirs, files in os.walk(git_root): + for file in files: + if file.endswith('.tpl'): + trgt = file[:-3]+'md' + print(' generate ' + file + ' -> ' + trgt); + tpl = open(os.path.join(root, file), 'r', encoding='utf-8') + md = open(os.path.join(root, trgt), 'w', encoding='utf-8') + for line in tpl: + for key in substitutions: + line = line.replace('{@'+key+'@}', substitutions[key]) + md.write(line) + md .close() + tpl.close() + check_call(['git', 'add', trgt ]) diff --git a/tools/git/filters/normalize.pl b/tools/git/filters/normalize.pl new file mode 100755 index 00000000..150e15cd --- /dev/null +++ b/tools/git/filters/normalize.pl @@ -0,0 +1,142 @@ +#!/usr/bin/perl -w +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# +# ============================================================================== +# Authors: Thomas B. Preusser +# +# License: +# ============================================================================== +# Copyright 2007-2016 Technische Universitaet Dresden - Germany +# Chair for VLSI-Design, Diagnostics and Architecture +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# ============================================================================== +# +# Provides implementations for 'smudge' and 'clean' filters for the sources +# within the PoC repo. +# +# Synopsis: +# +# # normalize (smudge|clean) [language] < input > output +# +# +# The basic filter implementations do: +# +# clean - remove trailing whitespace, and +# smudge - replace empty lines with the most recent indentation. +# +# +# Currently, only the 'clean' pass expands extra processing steps for +# the following language specifiers: +# +# vhdl - VHDL reserved words and standard types are put into lower case, and +# rest - headline markers 7x'=' are expanded to 8x'=' so as to avoid +# the misinterpretation as a conflict marker by git. +# +# ============================================================================== +use strict; +use feature 'state'; + +############################################################################## +# Filter Routines +# +# Input: string representing a source line +# Output: filtered source line +# +# The filters may maintain internal state to effect filtering. + +# Trims trailing whitespace. +sub rtrim { + $_[0] =~ s/\s*$//r; +} + +# Adjusts empty lines (all whitespace) to comprise most recent indentation. +sub whiteindent { + state $indent = ''; + my($line) = @_; + return $indent unless $line =~ /^(\s*)\S/; + $indent = $1; + return $line; +} + +# Lower-cases VHDL reserved words and standard types. +sub vhdlcap { + state $reserved = join '|', qw/ + abs after alias all and architecture array assert attribute + begin block body buffer bus + case component configuration constant + disconnect downto + else elsif end entity exit + file for function + generate generic group guarded + if impure in inertial inout is + label library linkage literal loop + map mod + nand new next nor not null + of on open or others out + package port postponed procedure process pure + range record register reject rem report return rol ror + select severity signal shared sla sll sra srl subtype + then to transport type + unaffected units until use + variable + wait when while with + xnor xor + + bit bit_vector boolean character integer natural positive signed + std_logic std_logic_vector string time unsigned + /; + $_[0] =~ s/(--.*$|(['"\\]).*?\2|\b($reserved)\b)/$3? lc $3 : $1/gier; +} + +# Fix headline markers in reST, which would coincide with git conflict markers. +sub restfix { + $_[0] =~ s/(^={7}$)/=$1/r; +} + +############################################################################## +# Main: Select Filters and apply them from stdin to stdout. + +# Build Filter Chain +my $pass; +my @chain = (); + +# open(my $fh, '>>', 'D:\git\PoC\temp\normalize.log'); + +if($pass = shift) { + my $lang = @ARGV? lc(shift) : ''; + # print $fh "$lang"; + if($pass eq 'clean') { + # print $fh " clean xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n"; + push @chain, \&rtrim; + push @chain, \&vhdlcap if $lang eq 'vhdl'; + push @chain, \&restfix if $lang eq 'rest'; + } + elsif($pass eq 'smudge') { + push @chain, \&whiteindent; + } +} + +# Apply Filter Chain +while(<>) { + chomp; + my $line = $_; + $line = $_->($line) for @chain; + print "$line\n"; + # print $fh "$line\n"; +} + +# close $fh; diff --git a/tools/git/git-alias.setup.ps1 b/tools/git/git-alias.setup.ps1 index d0aa88ee..153b7d06 100644 --- a/tools/git/git-alias.setup.ps1 +++ b/tools/git/git-alias.setup.ps1 @@ -1,7 +1,7 @@ # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2; replace-tabs off; indent-width 2; -# +# # ============================================================================= # Authors: Patrick Lehmann # @@ -10,18 +10,18 @@ # Description: # ------------------------------------ # TODO -# +# # License: # ============================================================================= # Copyright 2007-2015 Technische Universitaet Dresden - Germany # Chair for VLSI-Design, Diagnostics and Architecture -# +# # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at -# +# # http://www.apache.org/licenses/LICENSE-2.0 -# +# # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. diff --git a/tools/git/git-alias.setup.sh b/tools/git/git-alias.setup.sh index ad166f11..ccd066d8 100755 --- a/tools/git/git-alias.setup.sh +++ b/tools/git/git-alias.setup.sh @@ -1,8 +1,8 @@ -#!/bin/bash +#! /usr/bin/env bash # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2; replace-tabs off; indent-width 2; -# +# # ============================================================================= # Authors: Patrick Lehmann # @@ -11,18 +11,18 @@ # Description: # ------------------------------------ # TODO -# +# # License: # ============================================================================= # Copyright 2007-2015 Technische Universitaet Dresden - Germany # Chair for VLSI-Design, Diagnostics and Architecture -# +# # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at -# +# # http://www.apache.org/licenses/LICENSE-2.0 -# +# # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. diff --git a/tools/git/hooks/pre-commit.d/whitespace.sh b/tools/git/hooks/pre-commit.d/whitespace.sh new file mode 100755 index 00000000..6d120e6d --- /dev/null +++ b/tools/git/hooks/pre-commit.d/whitespace.sh @@ -0,0 +1,30 @@ +#!/bin/bash +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# +# ============================================================================== +# Authors: Thomas B. Preusser +# +# License: +# ============================================================================== +# Copyright 2007-2016 Technische Universitaet Dresden - Germany +# Chair for VLSI-Design, Diagnostics and Architecture +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================== + +if ! git diff --cached --check; then + echo 1>&2 'ERROR: Commit would introduce whitespace errors. Please fix and try again.' + exit 1 +fi diff --git a/tools/git/hooks/run-hook.sh b/tools/git/hooks/run-hook.sh new file mode 100755 index 00000000..7370ee1b --- /dev/null +++ b/tools/git/hooks/run-hook.sh @@ -0,0 +1,36 @@ +#!/bin/bash +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t; python-indent-offset: 2 -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# +# ============================================================================== +# Authors: Thomas B. Preusser +# +# License: +# ============================================================================== +# Copyright 2007-2016 Technische Universitaet Dresden - Germany +# Chair for VLSI-Design, Diagnostics and Architecture +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================== +hook=$(basename $0) +echo "POC: Executing $hook hooks..." +for i in tools/git/hooks/$hook.d/*; do + file=$(basename $i) + echo "POC: Executing '$file'" + if ! "$i"; then + echo "ERROR: $file FAILED" + exit 1 + fi +done +echo "PASSED" diff --git a/tools/hooks/README.md b/tools/hooks/README.md deleted file mode 100644 index 46f8779e..00000000 --- a/tools/hooks/README.md +++ /dev/null @@ -1,54 +0,0 @@ -# PoC Hook Files - -This folder contains "hook files", which are sourced: - - before (`PreHookFile`) and - - after (`PostHostFile`) -a PoC command gets executed with `poc.[sh|ps1]`. A common use case is the preparation -of special vendor or tool chain environments. E.g. many EDA tools are using FlexLM -as a license manager, which needs the environments variable `LM_LICENSE_FILE` to be -set. A `PreHookFile` can be used to load/export such a variable. - - -## Hook Files - -The `poc.[sh.ps1]` wrapper scripts scans the argument list for a known command. If such -a command is found, a pre- and post load event is triggered for a vendor hook file and a -tool hook file. - - -#### Example Mentor QuestaSim on Linux: - -The PoC Infrastructure is called with this command line: - -```Bash -./poc.sh -v vsim PoC.arith.prng -``` - -The `vsim` command is recognized and the following events are scheduled: - - - .\Mentor.pre.sh - - .\Mentor.QuestaSim.pre.sh - - running `./py/PoC.py -v vsim PoC.arith.prng` - - .\Mentor.QuestaSim.post.sh - - .\Mentor.post.sh - -If a hook files doesn't exist, its skipped. - - -#### Example Mentor QuestaSim on Windows: - -The PoC Infrastructure is called with this command line: - -```PowerShell -.\poc.ps1 -v vsim PoC.arith.prng -``` - -The `vsim` command is recognized and the following events are scheduled: - - - .\Mentor.pre.ps1 - - .\Mentor.QuestaSim.pre.ps1 - - running `.\py\PoC.py -v vsim PoC.arith.prng` - - .\Mentor.QuestaSim.post.ps1 - - .\Mentor.post.ps1 - -If a hook files doesn't exist, its skipped. diff --git a/tools/precompile/compile-altera.ps1 b/tools/precompile/compile-altera.ps1 new file mode 100644 index 00000000..21403541 --- /dev/null +++ b/tools/precompile/compile-altera.ps1 @@ -0,0 +1,190 @@ +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# +# ============================================================================== +# Authors: Patrick Lehmann +# +# PowerShell Script: Compile Altera's simulation libraries +# +# Description: +# ------------------------------------ +# This PowerShell script compiles Altera's simulation libraries into a local +# directory. +# +# License: +# ============================================================================== +# Copyright 2007-2016 Technische Universitaet Dresden - Germany +# Chair for VLSI-Design, Diagnostics and Architecture +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================== + +# .SYNOPSIS +# This CmdLet pre-compiles the simulation libraries from Altera Quartus. +# +# .DESCRIPTION +# This CmdLet: +# (1) Creates a sub-directory 'altera' in the current working directory +# (2) Compiles all Altera Quartus simulation libraries and packages for +# o GHDL +# o QuestaSim +# +[CmdletBinding()] +param( + # Pre-compile all libraries and packages for all simulators + [switch]$All = $false, + + # Pre-compile the Altera Quartus libraries for GHDL + [switch]$GHDL = $false, + + # Pre-compile the Altera Quartus libraries for QuestaSim + [switch]$Questa = $false, + + # Set VHDL Standard to '93 + [switch]$VHDL93 = $false, + # # Set VHDL Standard to '08 + [switch]$VHDL2008 = $false, + + # Clean up directory before analyzing. + [switch]$Clean = $false, + + # Show the embedded help page(s) + [switch]$Help = $false +) + +$PoCRootDir = "\..\.." + +# resolve paths +$WorkingDir = Get-Location +$PoCRootDir = Convert-Path (Resolve-Path ($PSScriptRoot + $PoCRootDir)) +$PoCPS1 = "$PoCRootDir\poc.ps1" + +Import-Module $PSScriptRoot\precompile.psm1 -Verbose:$false -Debug:$false -Scope Local -ArgumentList "$WorkingDir" + +# Display help if no command was selected +$Help = $Help -or (-not ($All -or $GHDL -or $Questa)) + +if ($Help) +{ Get-Help $MYINVOCATION.InvocationName -Detailed + Exit-PrecompileScript +} + +$GHDL,$Questa = Resolve-Simulator $All $GHDL $Questa +$VHDL93,$VHDL2008 = Resolve-VHDLVersion $VHDL93 $VHDL2008 + +$PreCompiledDir = Get-PrecompiledDirectoryName $PoCPS1 +$AlteraDirName = Get-AlteraDirectoryName $PoCPS1 + +# GHDL +# ============================================================================== +if ($GHDL) +{ Write-Host "Pre-compiling Altera's simulation libraries for GHDL" -ForegroundColor Cyan + Write-Host "--------------------------------------------------------------------------------" -ForegroundColor Cyan + + $GHDLBinDir = Get-GHDLBinaryDirectory $PoCPS1 + $GHDLScriptDir = Get-GHDLScriptDirectory $PoCPS1 + $GHDLDirName = Get-GHDLDirectoryName $PoCPS1 + + # Assemble output directory + $DestDir = "$PoCRootDir\$PrecompiledDir\$GHDLDirName" + # Create and change to destination directory + Initialize-DestinationDirectory $DestDir + + $GHDLAlteraScript = "$GHDLScriptDir\compile-altera.ps1" + if (-not (Test-Path $GHDLAlteraScript -PathType Leaf)) + { Write-Host "[ERROR]: Altera compile script from GHDL is not executable." -ForegroundColor Red + Exit-PrecompileScript -1 + } + + $QuartusInstallDir = Get-QuartusInstallationDirectory $PoCPS1 + $SourceDir = "$QuartusInstallDir\eda\sim_lib" + + # export GHDL environment variable if not allready set + if (-not (Test-Path env:GHDL)) + { $env:GHDL = $GHDLBinDir } + + if ($VHDL93) + { $Command = "$GHDLAlteraScript -All -VHDL93 -Source $SourceDir -Output $DestDir\$AlteraDirName" + Invoke-Expression $Command + if ($LastExitCode -ne 0) + { Write-Host "[ERROR]: While executing vendor library compile script from GHDL." -ForegroundColor Red + Exit-PrecompileScript -1 + } + } + if ($VHDL2008) + { $Command = "$GHDLAlteraScript -All -VHDL2008 -Source $SourceDir -Output $DestDir\$AlteraDirName" + Invoke-Expression $Command + if ($LastExitCode -ne 0) + { Write-Host "[ERROR]: While executing vendor library compile script from GHDL." -ForegroundColor Red + Exit-PrecompileScript -1 + } + } + + # restore working directory + cd $WorkingDir + Write-Host "--------------------------------------------------------------------------------" -ForegroundColor Cyan +} + +# QuestaSim/ModelSim +# ============================================================================== +if ($Questa) +{ Write-Host "Pre-compiling Altera's simulation libraries for QuestaSim" -ForegroundColor Cyan + Write-Host "--------------------------------------------------------------------------------" -ForegroundColor Cyan + + $VSimBinDir = Get-ModelSimBinaryDirectory $PoCPS1 + $VSimDirName = Get-QuestaSimDirectoryName $PoCPS1 + + # Assemble output directory + $DestDir="$PoCRootDir\$PrecompiledDir\$VSimDirName\$AlteraDirName" + # Create and change to destination directory + Initialize-DestinationDirectory $DestDir + + $QuartusBinDir = Get-QuartusBinaryDirectory $PoCPS1 + $Quartus_sh = "$QuartusBinDir\quartus_sh.exe" + + New-ModelSim_ini + + $Simulator = "questasim" + $Language = "vhdl" + $TargetArchitectures = @( + "all" + ) + + # compile common libraries + $Command = "$Quartus_sh --simlib_comp -tool $Simulator -language $Language -tool_path $VSimBinDir -directory $DestDir -rtl_only" + Invoke-Expression $Command + if ($LastExitCode -ne 0) + { Write-Host "[ERROR]: While compiling common libraries." -ForegroundColor Red + Exit-PrecompileScript -1 + } + + $VSimBinDir_TclPath = $VSimBinDir.Replace("\", "/") + $DestDir_TclPath = $DestDir.Replace("\", "/") + foreach ($Family in $TargetArchitectures) + { $Command = "$Quartus_sh --simlib_comp -tool $Simulator -language $Language -family $Family -tool_path $VSimBinDir_TclPath -directory $DestDir_TclPath -rtl_only" + Invoke-Expression $Command + if ($LastExitCode -ne 0) + { Write-Host "[ERROR]: While compiling family '$Family' libraries." -ForegroundColor Red + Exit-PrecompileScript -1 + } + } + + # restore working directory + cd $WorkingDir + Write-Host "--------------------------------------------------------------------------------" -ForegroundColor Cyan +} + +Write-Host "[COMPLETE]" -ForegroundColor Green + +Exit-PrecompileScript diff --git a/tools/precompile/compile-altera.sh b/tools/precompile/compile-altera.sh index e2866378..8701c1c2 100755 --- a/tools/precompile/compile-altera.sh +++ b/tools/precompile/compile-altera.sh @@ -1,13 +1,14 @@ -#!/bin/bash +#! /usr/bin/env bash # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2; replace-tabs off; indent-width 2; -# +# # ============================================================================== -# Authors: Martin Zabel -# +# Authors: Martin Zabel +# Patrick Lehmann +# # Bash Script: Compile Altera's simulation libraries -# +# # Description: # ------------------------------------ # This is a bash script compiles Altera's simulation libraries into a local @@ -17,13 +18,13 @@ # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany # Chair for VLSI-Design, Diagnostics and Architecture -# +# # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at -# +# # http://www.apache.org/licenses/LICENSE-2.0 -# +# # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -31,94 +32,215 @@ # limitations under the License. # ============================================================================== -poc_sh=../../poc.sh -Simulator=ghdl # questasim, ghdl, ... -Language=vhdl # vhdl -TargetArchitecture="cycloneiii stratixiv" # space separated device list +# work around for Darwin (Mac OS) +READLINK=readlink; if [[ $(uname) == "Darwin" ]]; then READLINK=greadlink; fi -ghdlScript=/space/install/ghdl/libraries/vendors/compile-altera.sh +# Save working directory +WorkingDir=$(pwd) +ScriptDir="$(dirname $0)" +ScriptDir="$($READLINK -f $ScriptDir)" -# define color escape codes -RED='\e[0;31m' # Red -YELLOW='\e[1;33m' # Yellow -NOCOLOR='\e[0m' # No Color +PoCRootDir="$($READLINK -f $ScriptDir/../..)" +PoC_sh=$PoCRootDir/poc.sh -# Setup command to execute -if [ "$Simulator" != ghdl ]; then - QuartusSH=$($poc_sh query INSTALL.Altera.Quartus:BinaryDirectory 2>/dev/null)/quartus_sh - if [ $? -ne 0 ]; then - echo 1>&2 -e "${RED}ERROR: Cannot get Altera Quartus binary dir.${NOCOLOR}" - exit; - fi -fi +# source shared file from precompile directory +source $ScriptDir/shared.sh -# Setup destination directory -DestDir=$($poc_sh query INSTALL.PoC:InstallationDirectory 2>/dev/null)/temp/precompiled -if [ $? -ne 0 ]; then - echo 1>&2 -e "${RED}ERROR: Cannot get PoC installation dir.${NOCOLOR}" - exit; -fi -case "$Simulator" in - ghdl) - DestDir=$DestDir/ghdl +# command line argument processing +NO_COMMAND=1 +VHDL93=0 +VHDL2008=0 +while [[ $# > 0 ]]; do + key="$1" + case $key in + -c|--clean) + CLEAN=TRUE ;; - questasim) - DestDir=$DestDir/vsim/altera + -a|--all) + COMPILE_ALL=TRUE + NO_COMMAND=0 ;; - *) - echo "Unsupported simulator." - exit 1 + --ghdl) + COMPILE_FOR_GHDL=TRUE + NO_COMMAND=0 ;; -esac - -# Setup simulator directory -case "$Simulator" in - questasim) - SimulatorDir=$($poc_sh query ModelSim:InstallationDirectory 2>/dev/null)/bin # Path to the simulators bin directory - if [ $? -ne 0 ]; then - echo 1>&2 -e "${RED}ERROR: Cannot get ModelSim installation dir.${NOCOLOR}" - exit; - fi + --questa) + COMPILE_FOR_VSIM=TRUE + NO_COMMAND=0 + ;; + -h|--help) + HELP=TRUE + NO_COMMAND=0 + ;; + --vhdl93) + VHDL93=1 ;; -esac + --vhdl2008) + VHDL2008=1 + ;; + *) # unknown option + echo 1>&2 -e "${COLORED_ERROR} Unknown command line option '$key'.${ANSI_NOCOLOR}" + exit -1 + ;; + esac + shift # past argument or value +done + +if [ $NO_COMMAND -eq 1 ]; then + HELP=TRUE +fi + +if [ "$HELP" == "TRUE" ]; then + test $NO_COMMAND -eq 1 && echo 1>&2 -e "\n${COLORED_ERROR} No command selected.${ANSI_NOCOLOR}" + echo "" + echo "Synopsis:" + echo " Script to compile the Altera Quartus simulation libraries for" + echo " - GHDL" + echo " - QuestaSim/ModelSim" + echo " on Linux." + echo "" + echo "Usage:" + echo " compile-altera.sh [-c] [--help|--all|--ghdl|--vsim] []" + echo "" + echo "Common commands:" + echo " -h --help Print this help page" + # echo " -c --clean Remove all generated files" + echo "" + echo "Tool chain:" + echo " -a --all Compile for all tool chains." + echo " --ghdl Compile for GHDL." + echo " --questa Compile for QuestaSim/ModelSim." + echo "" + echo "Options:" + echo " --vhdl93 Compile for VHDL-93." + echo " --vhdl2008 Compile for VHDL-2008." + echo "" + exit 0 +fi + -# Create and change to destination directory -mkdir -p $DestDir +if [ "$COMPILE_ALL" == "TRUE" ]; then + COMPILE_FOR_GHDL=TRUE + COMPILE_FOR_VSIM=TRUE +fi +if [ \( $VHDL93 -eq 0 \) -a \( $VHDL2008 -eq 0 \) ]; then + VHDL93=1 + VHDL2008=1 +fi + +PrecompiledDir=$($PoC_sh query CONFIG.DirectoryNames:PrecompiledFiles 2>/dev/null) if [ $? -ne 0 ]; then - echo 1>&2 -e "${RED}ERROR: Cannot create output directory.${NOCOLOR}" - exit; -fi + echo 1>&2 -e "${COLORED_ERROR} Cannot get precompiled directory.${ANSI_NOCOLOR}" + echo 1>&2 -e "${ANSI_RED}$PrecompiledDir${ANSI_NOCOLOR}" + exit -1; +fi -cd $DestDir +AlteraDirName=$($PoC_sh query CONFIG.DirectoryNames:AlteraSpecificFiles 2>/dev/null) if [ $? -ne 0 ]; then - echo 1>&2 -e "${RED}ERROR: Cannot change to output directory.${NOCOLOR}" - exit; + echo 1>&2 -e "${COLORED_ERROR} Cannot get Altera directory.${ANSI_NOCOLOR}" + echo 1>&2 -e "${ANSI_RED}$AlteraDirName${ANSI_NOCOLOR}" + exit -1; fi -# Compile libraries with simulator, executed in destination directory -case "$Simulator" in - ghdl) - $ghdlScript -a -s -S - ;; - questasim) - # create modelsim.ini - echo "[Library]" > modelsim.ini - echo "others = ../modelsim.ini" >> modelsim.ini +# GHDL +# ============================================================================== +if [ "$COMPILE_FOR_GHDL" == "TRUE" ]; then + # Get GHDL directories + # <= $GHDLBinDir + # <= $GHDLScriptDir + # <= $GHDLDirName + GetGHDLDirectories $PoC_sh + + # Assemble output directory + DestDir=$PoCRootDir/$PrecompiledDir/$GHDLDirName + # Create and change to destination directory + # -> $DestinationDirectory + CreateDestinationDirectory $DestDir + + # Assemble Altera compile script path + GHDLAlteraScript="$($READLINK -f $GHDLScriptDir/compile-altera.sh)" + + + echo "=> $GHDLAlteraScript" + + # Get Altera installation directory + QuartusInstallDir=$($PoC_sh query INSTALL.Altera.Quartus:InstallationDirectory 2>/dev/null) + if [ $? -ne 0 ]; then + echo 1>&2 -e "${COLORED_ERROR} Cannot get Altera Quartus installation directory.${ANSI_NOCOLOR}" + echo 1>&2 -e "${ANSI_RED}$QuartusInstallDir${ANSI_NOCOLOR}" + exit -1; + fi + SourceDir=$QuartusInstallDir/eda/sim_lib + + # export GHDL binary dir if not allready set + if [ -z $GHDL ]; then + export GHDL=$GHDLBinDir/ghdl + fi + + BASH=$(which bash) + + # compile all architectures, skip existing and large files, no wanrings + if [ $VHDL93 -eq 1 ]; then + $BASH $GHDLAlteraScript --all --vhdl93 -s -S -n --src $SourceDir --out $AlteraDirName + if [ $? -ne 0 ]; then + echo 1>&2 -e "${COLORED_ERROR} While executing vendor library compile script from GHDL.${ANSI_NOCOLOR}" + exit -1; + fi + fi + if [ $VHDL2008 -eq 1 ]; then + $BASH $GHDLAlteraScript --all --vhdl2008 -s -S -n --src $SourceDir --out $AlteraDirName if [ $? -ne 0 ]; then - echo 1>&2 -e "${RED}ERROR: Cannot create initial modelsim.ini.${NOCOLOR}" - exit; + echo 1>&2 -e "${COLORED_ERROR} While executing vendor library compile script from GHDL.${ANSI_NOCOLOR}" + exit -1; fi + fi +fi - # call compile script - $QuartusSH --simlib_comp -tool $Simulator -language $Language -tool_path $SimulatorDir -directory $DestDir -rtl_only +# QuestaSim/ModelSim +# ============================================================================== +if [ "$COMPILE_FOR_VSIM" == "TRUE" ]; then + # Get GHDL directories + # <= $VSimBinDir + # <= $VSimDirName + GetVSimDirectories $PoC_sh + + # Assemble output directory + DestDir=$PoCRootDir/$PrecompiledDir/$VSimDirName/$AlteraDirName + # Create and change to destination directory + # -> $DestinationDirectory + CreateDestinationDirectory $DestDir + + QuartusBinDir=$($PoC_sh query INSTALL.Altera.Quartus:BinaryDirectory 2>/dev/null) + if [ $? -ne 0 ]; then + echo 1>&2 -e "${COLORED_ERROR} Cannot get Altera Quartus binary directory.${ANSI_NOCOLOR}" + echo 1>&2 -e "${COLORED_MESSAGE} $QuartusBinDir${ANSI_NOCOLOR}" + echo 1>&2 -e "${ANSI_YELLOW}Run 'poc.sh configure' to configure your Altera Quartus installation.${ANSI_NOCOLOR}" + exit -1; + fi + Quartus_sh=$QuartusBinDir/quartus_sh + + # create an empty modelsim.ini in the altera directory and add reference to parent modelsim.ini + CreateLocalModelsim_ini + + + Simulator=questasim + Language=vhdl + TargetArchitectures=("all") # "cycloneiii" "stratixiv") + + # compile common libraries + $Quartus_sh --simlib_comp -tool $Simulator -language $Language -tool_path $VSimBinDir -directory $DestDir -rtl_only + if [ $? -ne 0 ]; then + echo 1>&2 -e "${COLORED_ERROR} While compiling common libraries.${ANSI_NOCOLOR}" + exit -1; + fi + + for Family in ${TargetArchitectures[@]}; do + $Quartus_sh --simlib_comp -tool $Simulator -language $Language -family $Family -tool_path $VSimBinDir -directory $DestDir -no_rtl + if [ $? -ne 0 ]; then + echo 1>&2 -e "${COLORED_ERROR} While compiling family '$Family' libraries.${ANSI_NOCOLOR}" + exit -1; + fi + done +fi - for Family in $TargetArchitecture; do - $QuartusSH --simlib_comp -tool $Simulator -language $Language -family $Family -tool_path $SimulatorDir -directory $DestDir -no_rtl - done - ;; - *) - echo "Unsupported simulator." - exit 1 - ;; -esac diff --git a/tools/precompile/compile-lattice.ps1 b/tools/precompile/compile-lattice.ps1 new file mode 100644 index 00000000..2de77ce3 --- /dev/null +++ b/tools/precompile/compile-lattice.ps1 @@ -0,0 +1,179 @@ +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# +# ============================================================================== +# Authors: Patrick Lehmann +# +# PowerShell Script: Compile Lattice's simulation libraries +# +# Description: +# ------------------------------------ +# This PowerShell script compiles Lattice's simulation libraries into a local +# directory. +# +# License: +# ============================================================================== +# Copyright 2007-2016 Technische Universitaet Dresden - Germany +# Chair for VLSI-Design, Diagnostics and Architecture +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================== + +# .SYNOPSIS +# This CmdLet pre-compiles the simulation libraries from Lattice Diamond. +# +# .DESCRIPTION +# This CmdLet: +# (1) Creates a sub-directory 'lattice' in the current working directory +# (2) Compiles all Lattice Diamond simulation libraries and packages for +# o GHDL +# o QuestaSim +# +[CmdletBinding()] +param( + # Pre-compile all libraries and packages for all simulators + [switch]$All = $false, + + # Pre-compile the Lattice Diamond libraries for GHDL + [switch]$GHDL = $false, + + # Pre-compile the Lattice Diamond libraries for QuestaSim + [switch]$Questa = $false, + + # Set VHDL Standard to '93 + [switch]$VHDL93 = $false, + # Set VHDL Standard to '08 + [switch]$VHDL2008 = $false, + + # Clean up directory before analyzing. + [switch]$Clean = $false, + + # Show the embedded help page(s) + [switch]$Help = $false +) + +$PoCRootDir = "\..\.." + +# resolve paths +$WorkingDir = Get-Location +$PoCRootDir = Convert-Path (Resolve-Path ($PSScriptRoot + $PoCRootDir)) +$PoCPS1 = "$PoCRootDir\poc.ps1" + +Import-Module $PSScriptRoot\precompile.psm1 -Verbose:$false -Debug:$false -ArgumentList "$WorkingDir" + +# Display help if no command was selected +$Help = $Help -or (-not ($All -or $GHDL -or $Questa)) + +if ($Help) +{ Get-Help $MYINVOCATION.InvocationName -Detailed + Exit-PrecompileScript +} + +$GHDL,$Questa = Resolve-Simulator $All $GHDL $Questa +$VHDL93,$VHDL2008 = Resolve-VHDLVersion $VHDL93 $VHDL2008 + +$PreCompiledDir = Get-PrecompiledDirectoryName $PoCPS1 +$LatticeDirName = Get-LatticeDirectoryName $PoCPS1 + +# GHDL +# ============================================================================== +if ($GHDL) +{ Write-Host "Pre-compiling Lattice's simulation libraries for GHDL" -ForegroundColor Cyan + Write-Host "--------------------------------------------------------------------------------" -ForegroundColor Cyan + + $GHDLBinDir = Get-GHDLBinaryDirectory $PoCPS1 + $GHDLScriptDir = Get-GHDLScriptDirectory $PoCPS1 + $GHDLDirName = Get-GHDLDirectoryName $PoCPS1 + + # Assemble output directory + $DestDir="$PoCRootDir\$PrecompiledDir\$GHDLDirName" + # Create and change to destination directory + Initialize-DestinationDirectory $DestDir + + $GHDLLatticeScript = "$GHDLScriptDir\compile-lattice.ps1" + if (-not (Test-Path $GHDLLatticeScript -PathType Leaf)) + { Write-Host "[ERROR]: Lattice compile script from GHDL is not executable." -ForegroundColor Red + Exit-PrecompileScript -1 + } + + $DiamondInstallDir = Get-DiamondInstallationDirectory $PoCPS1 + $SourceDir = "$DiamondInstallDir\cae_library\simulation\vhdl" + + # export GHDL environment variable if not allready set + if (-not (Test-Path env:GHDL)) + { $env:GHDL = $GHDLBinDir } + + if ($VHDL93) + { $Command = "$GHDLLatticeScript -All -VHDL93 -Source $SourceDir -Output $DestDir\$LatticeDirName" + Invoke-Expression $Command + if ($LastExitCode -ne 0) + { Write-Host "[ERROR]: While executing vendor library compile script from GHDL." -ForegroundColor Red + Exit-PrecompileScript -1 + } + } + if ($VHDL2008) + { $Command = "$GHDLLatticeScript -All -VHDL2008 -Source $SourceDir -Output $DestDir\$LatticeDirName" + Invoke-Expression $Command + if ($LastExitCode -ne 0) + { Write-Host "[ERROR]: While executing vendor library compile script from GHDL." -ForegroundColor Red + Exit-PrecompileScript -1 + } + } + + # restore working directory + cd $WorkingDir + Write-Host "--------------------------------------------------------------------------------" -ForegroundColor Cyan +} + +# QuestaSim/ModelSim +# ============================================================================== +if ($Questa) +{ Write-Host "Pre-compiling Lattice's simulation libraries for QuestaSim" -ForegroundColor Cyan + Write-Host "--------------------------------------------------------------------------------" -ForegroundColor Cyan + + $VSimBinDir = Get-ModelSimBinaryDirectory $PoCPS1 + $VSimDirName = Get-QuestaSimDirectoryName $PoCPS1 + + # Assemble output directory + $DestDir="$PoCRootDir\$PrecompiledDir\$VSimDirName\$LatticeDirName" + # Create and change to destination directory + Initialize-DestinationDirectory $DestDir + + $DiamondBinDir = Get-DiamondBinaryDirectory $PoCPS1 + $Diamond_tcl = "$DiamondBinDir\pnmainc.exe" + # Open-DiamondEnvironment $PoCPS1 + + New-ModelSim_ini + + $Simulator = "mentor" + $Language = "vhdl" + $Device = "all" # all, machxo, ecp, ... + + $VSimBinDir_TclPath = $VSimBinDir.Replace("\", "/") + "cmpl_libs -lang $Language -sim_vendor $Simulator -sim_path $VSimBinDir_TclPath -device $Device`nexit" | & $Diamond_tcl + if ($LastExitCode -ne 0) + { Write-Host "[ERROR]: While executing vendor library compile script from GHDL." -ForegroundColor Red + Exit-PrecompileScript -1 + } + + # Close-DiamondEnvironment + + # restore working directory + cd $WorkingDir + Write-Host "--------------------------------------------------------------------------------" -ForegroundColor Cyan +} + +Write-Host "[COMPLETE]" -ForegroundColor Green + +Exit-PrecompileScript diff --git a/tools/precompile/compile-lattice.sh b/tools/precompile/compile-lattice.sh new file mode 100755 index 00000000..1838eea1 --- /dev/null +++ b/tools/precompile/compile-lattice.sh @@ -0,0 +1,238 @@ +#! /usr/bin/env bash +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# +# ============================================================================== +# Authors: Martin Zabel +# Patrick Lehmann +# +# Bash Script: Compile Lattice's simulation libraries +# +# Description: +# ------------------------------------ +# This is a Bash script (executable) which: +# - creates a subdirectory in the current working directory +# - compiles all Lattice libraries +# +# License: +# ============================================================================== +# Copyright 2007-2016 Technische Universitaet Dresden - Germany +# Chair for VLSI-Design, Diagnostics and Architecture +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================== + +# work around for Darwin (Mac OS) +READLINK=readlink; if [[ $(uname) == "Darwin" ]]; then READLINK=greadlink; fi + +# Save working directory +WorkingDir=$(pwd) +ScriptDir="$(dirname $0)" +ScriptDir="$($READLINK -f $ScriptDir)" + +PoCRootDir="$($READLINK -f $ScriptDir/../..)" +PoC_sh=$PoCRootDir/poc.sh + +# source shared file from precompile directory +source $ScriptDir/shared.sh + + +# command line argument processing +NO_COMMAND=1 +VHDL93=0 +VHDL2008=0 +while [[ $# > 0 ]]; do + key="$1" + case $key in + -c|--clean) + CLEAN=TRUE + ;; + -a|--all) + COMPILE_ALL=TRUE + NO_COMMAND=0 + ;; + --ghdl) + COMPILE_FOR_GHDL=TRUE + NO_COMMAND=0 + ;; + --questa) + COMPILE_FOR_VSIM=TRUE + NO_COMMAND=0 + ;; + -h|--help) + HELP=TRUE + NO_COMMAND=0 + ;; + --vhdl93) + VHDL93=1 + ;; + --vhdl2008) + VHDL2008=1 + ;; + *) # unknown option + echo 1>&2 -e "${COLORED_ERROR} Unknown command line option '$key'.${ANSI_NOCOLOR}" + exit -1 + ;; + esac + shift # past argument or value +done + +if [ $NO_COMMAND -eq 1 ]; then + HELP=TRUE +fi + +if [ "$HELP" == "TRUE" ]; then + test $NO_COMMAND -eq 1 && echo 1>&2 -e "\n${COLORED_ERROR} No command selected.${ANSI_NOCOLOR}" + echo "" + echo "Synopsis:" + echo " Script to compile the Lattice Diamond simulation libraries for" + echo " - GHDL" + echo " - QuestaSim/ModelSim" + echo " on Linux." + echo "" + echo "Usage:" + echo " compile-lattice.sh [-c] [--help|--all|--ghdl|--vsim] []" + echo "" + echo "Common commands:" + echo " -h --help Print this help page" + # echo " -c --clean Remove all generated files" + echo "" + echo "Tool chain:" + echo " -a --all Compile for all tool chains." + echo " --ghdl Compile for GHDL." + echo " --questa Compile for QuestaSim/ModelSim." + echo "" + echo "Options:" + echo " --vhdl93 Compile for VHDL-93." + echo " --vhdl2008 Compile for VHDL-2008." + echo "" + exit 0 +fi + + +if [ "$COMPILE_ALL" == "TRUE" ]; then + COMPILE_FOR_GHDL=TRUE + # COMPILE_FOR_VSIM=TRUE +fi +if [ \( $VHDL93 -eq 0 \) -a \( $VHDL2008 -eq 0 \) ]; then + VHDL93=1 + VHDL2008=1 +fi + +PrecompiledDir=$($PoC_sh query CONFIG.DirectoryNames:PrecompiledFiles 2>/dev/null) +if [ $? -ne 0 ]; then + echo 1>&2 -e "${COLORED_ERROR} Cannot get precompiled directory.${ANSI_NOCOLOR}" + echo 1>&2 -e "${ANSI_RED}$PrecompiledDir${ANSI_NOCOLOR}" + exit -1; +fi + +LatticeDirName=$($PoC_sh query CONFIG.DirectoryNames:LatticeSpecificFiles 2>/dev/null) +if [ $? -ne 0 ]; then + echo 1>&2 -e "${COLORED_ERROR} Cannot get Lattice directory.${ANSI_NOCOLOR}" + echo 1>&2 -e "${ANSI_RED}$LatticeDirName${ANSI_NOCOLOR}" + exit -1; +fi + +# GHDL +# ============================================================================== +if [ "$COMPILE_FOR_GHDL" == "TRUE" ]; then + # Get GHDL directories + # <= $GHDLBinDir + # <= $GHDLScriptDir + # <= $GHDLDirName + GetGHDLDirectories $PoC_sh + + # Assemble output directory + DestDir=$PoCRootDir/$PrecompiledDir/$GHDLDirName + # Create and change to destination directory + # -> $DestinationDirectory + CreateDestinationDirectory $DestDir + + # Assemble Lattice compile script path + GHDLLatticeScript="$($READLINK -f $GHDLScriptDir/compile-lattice.sh)" + + + # Get Lattice installation directory + DiamondInstallDir=$($PoC_sh query INSTALL.Lattice.Diamond:InstallationDirectory 2>/dev/null) + if [ $? -ne 0 ]; then + echo 1>&2 -e "${COLORED_ERROR} Cannot get Lattice Diamond installation directory.${ANSI_NOCOLOR}" + echo 1>&2 -e "${COLORED_MESSAGE} $DiamondInstallDir${ANSI_NOCOLOR}" + echo 1>&2 -e "${ANSI_YELLOW}Run 'poc.sh configure' to configure your Lattice Diamond installation.${ANSI_NOCOLOR}" + exit -1; + fi + SourceDir=$DiamondInstallDir/cae_library/simulation/vhdl + + # export GHDL binary dir if not allready set + if [ -z $GHDL ]; then + export GHDL=$GHDLBinDir/ghdl + fi + + BASH=$(which bash) + + # compile all architectures, skip existing and large files, no wanrings + if [ $VHDL93 -eq 1 ]; then + $BASH $GHDLLatticeScript --all --vhdl93 -s -n --src $SourceDir --out $LatticeDirName + if [ $? -ne 0 ]; then + echo 1>&2 -e "${COLORED_ERROR} While executing vendor library compile script from GHDL.${ANSI_NOCOLOR}" + exit -1; + fi + fi + if [ $VHDL2008 -eq 1 ]; then + $BASH $GHDLLatticeScript --all --vhdl2008 -s -n --src $SourceDir --out $LatticeDirName + if [ $? -ne 0 ]; then + echo 1>&2 -e "${COLORED_ERROR} While executing vendor library compile script from GHDL.${ANSI_NOCOLOR}" + exit -1; + fi + fi +fi + +# QuestaSim/ModelSim +# ============================================================================== +if [ "$COMPILE_FOR_VSIM" == "TRUE" ]; then + # Get GHDL directories + # <= $VSimBinDir + # <= $VSimDirName + GetVSimDirectories $PoC_sh + + # Assemble output directory + DestDir=$PoCRootDir/$PrecompiledDir/$VSimDirName/$LatticeDirName + + # Create and change to destination directory + # -> $DestinationDirectory + CreateDestinationDirectory $DestDir + + DiamondBinDir=$($PoC_sh query INSTALL.Lattice.Diamond:BinaryDirectory 2>/dev/null) + if [ $? -ne 0 ]; then + echo 1>&2 -e "${COLORED_ERROR} Cannot get Lattice Diamond binary directory.${ANSI_NOCOLOR}" + echo 1>&2 -e "${COLORED_MESSAGE} $DiamondBinDir${ANSI_NOCOLOR}" + echo 1>&2 -e "${ANSI_YELLOW}Run 'poc.sh configure' to configure your Lattice Diamond installation.${ANSI_NOCOLOR}" + exit -1; + fi + Diamond_tcl=$DiamondBinDir/diamondc + + # create an empty modelsim.ini in the altera directory and add reference to parent modelsim.ini + CreateLocalModelsim_ini + + Simulator=mentor + Language=vhdl + Device=all # all, machxo, ecp, ... + + # compile common libraries + echo -e "cmpl_libs -lang $Language -sim_vendor $Simulator -sim_path $VSimBinDir -device $Device\nexit" | $Diamond_tcl + if [ $? -ne 0 ]; then + echo 1>&2 -e "${COLORED_ERROR} Error while compiling Lattice libraries.${ANSI_NOCOLOR}" + exit -1; + fi +fi + diff --git a/tools/precompile/compile-osvvm.ps1 b/tools/precompile/compile-osvvm.ps1 new file mode 100644 index 00000000..b8352a09 --- /dev/null +++ b/tools/precompile/compile-osvvm.ps1 @@ -0,0 +1,181 @@ +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# +# ============================================================================== +# Authors: Patrick Lehmann +# +# PowerShell Script: Compile OSVVM's simulation packages +# +# Description: +# ------------------------------------ +# This PowerShell script compiles OSVVM's simulation packages into a local +# directory. +# +# License: +# ============================================================================== +# Copyright 2007-2016 Technische Universitaet Dresden - Germany +# Chair for VLSI-Design, Diagnostics and Architecture +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================== + +# .SYNOPSIS +# This CmdLet pre-compiles the simulation libraries from OSVVM. +# +# .DESCRIPTION +# This CmdLet: +# (1) Creates a sub-directory 'osvvm' in the current working directory +# (2) Compiles all OSVVM simulation libraries and packages for +# o GHDL +# o QuestaSim +# +[CmdletBinding()] +param( + # Pre-compile all libraries and packages for all simulators + [switch]$All = $false, + + # Pre-compile the OSVVM libraries for GHDL + [switch]$GHDL = $false, + + # Pre-compile the OSVVM libraries for QuestaSim + [switch]$Questa = $false, + + # Clean up directory before analyzing. + [switch]$Clean = $false, + + # Show the embedded help page(s) + [switch]$Help = $false +) + +$PoCRootDir = "\..\.." +$OSVVMSourceDirectory = "lib\osvvm" + +# resolve paths +$WorkingDir = Get-Location +$PoCRootDir = Convert-Path (Resolve-Path ($PSScriptRoot + $PoCRootDir)) +$PoCPS1 = "$PoCRootDir\poc.ps1" + +Import-Module $PSScriptRoot\precompile.psm1 -Verbose:$false -Debug:$false -ArgumentList "$WorkingDir" + +# Display help if no command was selected +$Help = $Help -or (-not ($All -or $GHDL -or $Questa)) + +if ($Help) +{ Get-Help $MYINVOCATION.InvocationName -Detailed + Exit-PrecompileScript +} + +$GHDL,$Questa = Resolve-Simulator $All $GHDL $Questa + +$PreCompiledDir = Get-PrecompiledDirectoryName $PoCPS1 +$OSVVMDirName = "osvvm" +$SourceDirectory = "$PoCRootDir\$OSVVMSourceDirectory" + +# GHDL +# ============================================================================== +if ($GHDL) +{ Write-Host "Pre-compiling OSVVM's simulation libraries for GHDL" -ForegroundColor Cyan + Write-Host "--------------------------------------------------------------------------------" -ForegroundColor Cyan + + $GHDLBinDir = Get-GHDLBinaryDirectory $PoCPS1 + $GHDLScriptDir = Get-GHDLScriptDirectory $PoCPS1 + $GHDLDirName = Get-GHDLDirectoryName $PoCPS1 + + # Assemble output directory + $DestDir = Convert-Path (Resolve-Path "$PoCRootDir\$PrecompiledDir\$GHDLDirName") + # Create and change to destination directory + Initialize-DestinationDirectory $DestDir + + $GHDLOSVVMScript = "$GHDLScriptDir\compile-osvvm.ps1" + if (-not (Test-Path $GHDLOSVVMScript -PathType Leaf)) + { Write-Host "[ERROR]: OSVVM compile script from GHDL is not executable." -ForegroundColor Red + Exit-PrecompileScript -1 + } + + # export GHDL environment variable if not allready set + if (-not (Test-Path env:GHDL)) + { $env:GHDL = $GHDLBinDir } + + $Command = "$GHDLOSVVMScript -All -Source $SourceDirectory -Output $DestDir" + Invoke-Expression $Command + if ($LastExitCode -ne 0) + { Write-Host "[ERROR]: While executing vendor library compile script from GHDL." -ForegroundColor Red + Exit-PrecompileScript -1 + } + + + # restore working directory + cd $WorkingDir + Write-Host "--------------------------------------------------------------------------------" -ForegroundColor Cyan +} + +# QuestaSim/ModelSim +# ============================================================================== +if ($Questa) +{ Write-Host "Pre-compiling OSVVM's simulation libraries for QuestaSim" -ForegroundColor Cyan + Write-Host "--------------------------------------------------------------------------------" -ForegroundColor Cyan + + $VSimBinDir = Get-ModelSimBinaryDirectory $PoCPS1 + $VSimDirName = Get-QuestaSimDirectoryName $PoCPS1 + + # Assemble output directory + $DestDir = Convert-Path (Resolve-Path "$PoCRootDir\$PrecompiledDir\$VSimDirName\$OSVVMDirName") + # Create and change to destination directory + Initialize-DestinationDirectory $DestDir + cd .. + + $Library = "osvvm" + $Files = @( + "NamePkg.vhd", + "OsvvmGlobalPkg.vhd", + "TextUtilPkg.vhd", + "TranscriptPkg.vhd", + "AlertLogPkg.vhd", + "MemoryPkg.vhd", + "MessagePkg.vhd", + "SortListPkg_int.vhd", + "RandomBasePkg.vhd", + "RandomPkg.vhd", + "CoveragePkg.vhd", + "OsvvmContext.vhd" + ) + $SourceFiles = $Files | % { "$SourceDirectory\$_" } + + # Compile libraries with vcom, executed in destination directory + Write-Host "Creating library '$Library' with vlib/vmap..." -ForegroundColor Yellow + & "$VSimBinDir\vlib.exe" $Library + & "$VSimBinDir\vmap.exe" -del $Library + & "$VSimBinDir\vmap.exe" $Library "$DestDir" + + Write-Host "Compiling library '$Library' with vcom..." -ForegroundColor Yellow + $ErrorCount += 0 + foreach ($File in $SourceFiles) + { Write-Host "Compiling '$File'..." -ForegroundColor Cyan + $InvokeExpr = "$VSimBinDir\vcom.exe -2008 -work $Library " + $File + " 2>&1" + Invoke-Expression $InvokeExpr + if ($LastExitCode -ne 0) + { $ErrorCount += 1 + if ($HaltOnError) + { break } + } + } + + # restore working directory + cd $WorkingDir + Write-Host "--------------------------------------------------------------------------------" -ForegroundColor Cyan +} + +Write-Host "[COMPLETE]" -ForegroundColor Green + +Exit-PrecompileScript diff --git a/tools/precompile/compile-osvvm.sh b/tools/precompile/compile-osvvm.sh index bad5c210..0a0e1237 100755 --- a/tools/precompile/compile-osvvm.sh +++ b/tools/precompile/compile-osvvm.sh @@ -1,32 +1,31 @@ -#! /bin/bash +#! /usr/bin/env bash # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2; replace-tabs off; indent-width 2; -# +# # ============================================================================== -# Bash Script: Script to compile the OSVVM library for Questa / ModelSim -# on Linux -# -# Authors: Patrick Lehmann -# Martin Zabel -# +# Authors: Patrick Lehmann +# Martin Zabel +# +# Bash Script: Compile OSVVM simulation packages +# # Description: # ------------------------------------ # This is a Bash script (executable) which: # - creates a subdirectory in the current working directory -# - compiles all OSVVM packages +# - compiles all OSVVM packages # # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany # Chair for VLSI-Design, Diagnostics and Architecture -# +# # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at -# +# # http://www.apache.org/licenses/LICENSE-2.0 -# +# # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -34,110 +33,210 @@ # limitations under the License. # ============================================================================== -poc_sh=../../poc.sh -Simulator=questasim # questasim, ghdl, ... +# configure script here +OSVVMLibDir=lib/osvvm -# define color escape codes -RED='\e[0;31m' # Red -YELLOW='\e[1;33m' # Yellow -NOCOLOR='\e[0m' # No Color +# work around for Darwin (Mac OS) +READLINK=readlink; if [[ $(uname) == "Darwin" ]]; then READLINK=greadlink; fi -# Files -SourceDir=$($poc_sh query INSTALL.PoC:InstallationDirectory 2>/dev/null)/lib/osvvm -if [ $? -ne 0 ]; then - echo 1>&2 -e "${RED}ERROR: Cannot get PoC installation dir.${NOCOLOR}" - exit; -fi -Files=( - $SourceDir/NamePkg.vhd - $SourceDir/OsvvmGlobalPkg.vhd - $SourceDir/TextUtilPkg.vhd - $SourceDir/TranscriptPkg.vhd - $SourceDir/AlertLogPkg.vhd - $SourceDir/MemoryPkg.vhd - $SourceDir/MessagePkg.vhd - $SourceDir/SortListPkg_int.vhd - $SourceDir/RandomBasePkg.vhd - $SourceDir/RandomPkg.vhd - $SourceDir/CoveragePkg.vhd - $SourceDir/OsvvmContext.vhd -) - -# Simulator binary directory -case "$Simulator" in - ghdl) - BinDir=$($poc_sh query INSTALL.GHDL:BinaryDirectory 2>/dev/null) # Path to the simulators bin directory - if [ $? -ne 0 ]; then - echo 1>&2 -e "${RED}ERROR: Cannot get GHDL binary dir.${NOCOLOR}" - exit; - fi +# Save working directory +WorkingDir=$(pwd) +ScriptDir="$(dirname $0)" +ScriptDir="$($READLINK -f $ScriptDir)" + +PoCRootDir="$($READLINK -f $ScriptDir/../..)" +PoC_sh=$PoCRootDir/poc.sh + +# source shared file from precompile directory +source $ScriptDir/shared.sh + + +# command line argument processing +NO_COMMAND=1 +while [[ $# > 0 ]]; do + key="$1" + case $key in + -c|--clean) + CLEAN=TRUE ;; - questasim) - BinDir=$($poc_sh query ModelSim:BinaryDirectory 2>/dev/null) # Path to the simulators bin directory - if [ $? -ne 0 ]; then - echo 1>&2 -e "${RED}ERROR: Cannot get ModelSim binary dir.${NOCOLOR}" - exit; - fi + -a|--all) + COMPILE_ALL=TRUE + NO_COMMAND=0 ;; - *) - echo "Unsupported simulator." - exit 1 + --ghdl) + COMPILE_FOR_GHDL=TRUE + NO_COMMAND=0 ;; -esac - -# Setup destination directory -DestDir=$($poc_sh query INSTALL.PoC:InstallationDirectory 2>/dev/null)/temp/precompiled -if [ $? -ne 0 ]; then - echo 1>&2 -e "${RED}ERROR: Cannot get PoC installation dir.${NOCOLOR}" - exit; -fi - -case "$Simulator" in - ghdl) - DestDir=$DestDir/ghdl/osvvm + --questa) + COMPILE_FOR_VSIM=TRUE + NO_COMMAND=0 ;; - questasim) - DestDir=$DestDir/vsim + -h|--help) + HELP=TRUE + NO_COMMAND=0 ;; - *) - echo "Unsupported simulator." - exit 1 + *) # unknown option + echo 1>&2 -e "${COLORED_ERROR} Unknown command line option '$key'.${ANSI_NOCOLOR}" + exit -1 ;; -esac + esac + shift # past argument or value +done -# Create and change to destination directory -mkdir -p $DestDir -if [ $? -ne 0 ]; then - echo 1>&2 -e "${RED}ERROR: Cannot create output directory.${NOCOLOR}" - exit; -fi +if [ $NO_COMMAND -eq 1 ]; then + HELP=TRUE +fi + +if [ "$HELP" == "TRUE" ]; then + test $NO_COMMAND -eq 1 && echo 1>&2 -e "\n${COLORED_ERROR} No command selected.${ANSI_NOCOLOR}" + echo "" + echo "Synopsis:" + echo " Script to compile the simulation library OSVVM for" + echo " - GHDL" + echo " - QuestaSim/ModelSim" + echo " on Linux." + echo "" + echo "Usage:" + echo " compile-osvvm.sh [-c] [--help|--all|--ghdl|--vsim]" + echo "" + echo "Common commands:" + echo " -h --help Print this help page" + # echo " -c --clean Remove all generated files" + echo "" + echo "Tool chain:" + echo " -a --all Compile for all tool chains." + echo " --ghdl Compile for GHDL." + echo " --questa Compile for QuestaSim/ModelSim." + echo "" + exit 0 +fi + + +if [ "$COMPILE_ALL" == "TRUE" ]; then + COMPILE_FOR_GHDL=TRUE + COMPILE_FOR_VSIM=TRUE +fi -cd $DestDir +PrecompiledDir=$($PoC_sh query CONFIG.DirectoryNames:PrecompiledFiles 2>/dev/null) if [ $? -ne 0 ]; then - echo 1>&2 -e "${RED}ERROR: Cannot change to output directory.${NOCOLOR}" - exit; + echo 1>&2 -e "${COLORED_ERROR} Cannot get precompiled dir.${ANSI_NOCOLOR}" + echo 1>&2 -e "${ANSI_RED}$PrecompiledDir${ANSI_NOCOLOR}" + exit -1; fi -# Compile libraries with simulator, executed in destination directory -case "$Simulator" in - ghdl) - for file in ${Files[@]}; do - echo "Compiling $file..." - $BinDir/ghdl -a -fexplicit -frelaxed-rules --no-vital-checks --warn-binding --mb-comments --std=08 --work=osvvm $file - done - ;; - questasim) + +# GHDL +# ============================================================================== +if [ "$COMPILE_FOR_GHDL" == "TRUE" ]; then + # Get GHDL directories + # <= $GHDLBinDir + # <= $GHDLScriptDir + # <= $GHDLDirName + GetGHDLDirectories $PoC_sh + + # Assemble output directory + DestDir=$PoCRootDir/$PrecompiledDir/$GHDLDirName + # Create and change to destination directory + # -> $DestinationDirectory + CreateDestinationDirectory $DestDir + + # Assemble Altera compile script path + GHDLOSVVMScript="$($READLINK -f $GHDLScriptDir/compile-osvvm.sh)" + + + # Get OSVVM installation directory + OSVVMInstallDir=$PoCRootDir/$OSVVMLibDir + SourceDir=$OSVVMInstallDir + + # export GHDL binary dir if not allready set + if [ -z $GHDL ]; then + export GHDL=$GHDLBinDir/ghdl + fi + + BASH=$(which bash) + + # compile all architectures, skip existing and large files, no wanrings + $BASH $GHDLOSVVMScript --all -n --src $SourceDir --out "." + if [ $? -ne 0 ]; then + echo 1>&2 -e "${COLORED_ERROR} While executing vendor library compile script from GHDL.${ANSI_NOCOLOR}" + exit -1; + fi + + # # Cleanup + # if [ "$CLEAN" == "TRUE" ]; then + # echo -e "${YELLOW}Cleaning library 'osvvm' ...${ANSI_NOCOLOR}" + # rm -Rf $DestDir 2> /dev/null + # fi + + cd $WorkingDir +fi + +# QuestaSim/ModelSim +# ============================================================================== +if [ "$COMPILE_FOR_VSIM" == "TRUE" ]; then + # Get GHDL directories + # <= $VSimBinDir + # <= $VSimDirName + GetVSimDirectories $PoC_sh + + # Assemble output directory + DestDir=$PoCRootDir/$PrecompiledDir/$VSimDirName + # Create and change to destination directory + # -> $DestinationDirectory + CreateDestinationDirectory $DestDir + + + # clean osvvm directory + if [ -d $DestDir/osvvm ]; then + echo -e "${YELLOW}Cleaning library 'osvvm' ...${ANSI_NOCOLOR}" rm -rf osvvm - vlib osvvm - vmap -del osvvm - vmap osvvm $DestDir/osvvm - for file in ${Files[@]}; do - echo "Compiling $file..." - $BinDir/vcom -2008 -work osvvm $file - done - ;; - *) - echo "Unsupported simulator." - exit 1 - ;; -esac + fi + + # Get OSVVM installation directory + OSVVMInstallDir=$PoCRootDir/$OSVVMLibDir + SourceDir=$OSVVMInstallDir + + # Files + Library=osvvm + Files=( + NamePkg.vhd + OsvvmGlobalPkg.vhd + TextUtilPkg.vhd + TranscriptPkg.vhd + AlertLogPkg.vhd + MemoryPkg.vhd + MessagePkg.vhd + SortListPkg_int.vhd + RandomBasePkg.vhd + RandomPkg.vhd + CoveragePkg.vhd + OsvvmContext.vhd + ) + + # Compile libraries with vcom, executed in destination directory + echo -e "${YELLOW}Creating library '$Library' with vlib/vmap...${ANSI_NOCOLOR}" + $VSimBinDir/vlib $Library + $VSimBinDir/vmap -del $Library + $VSimBinDir/vmap $Library $DestDir/$Library + + echo -e "${YELLOW}Compiling library '$Library' with vcom...${ANSI_NOCOLOR}" + ERRORCOUNT=0 + for File in ${Files[@]}; do + echo " Compiling '$File'..." + $VSimBinDir/vcom -2008 -work $Library $SourceDir/$File + if [ $? -ne 0 ]; then + let ERRORCOUNT++ + fi + done + + # print overall result + echo -n "Compiling library '$Library' with vcom " + if [ $ERRORCOUNT -gt 0 ]; then + echo -e $COLORED_FAILED + else + echo -e $COLORED_SUCCESSFUL + fi + + cd $WorkingDir +fi + diff --git a/tools/precompile/compile-xilinx-ise.ps1 b/tools/precompile/compile-xilinx-ise.ps1 index 185b4819..9ccf83f2 100644 --- a/tools/precompile/compile-xilinx-ise.ps1 +++ b/tools/precompile/compile-xilinx-ise.ps1 @@ -1,28 +1,28 @@ # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2; replace-tabs off; indent-width 2; -# +# # ============================================================================== -# Authors: Patrick Lehmann -# -# Bash Script: Compile Xilinx's simulation libraries -# +# Authors: Patrick Lehmann +# +# PowerShell Script: Compile Xilinx's simulation libraries +# # Description: # ------------------------------------ -# This is a bash script compiles Xilinx's simulation libraries into a local +# This PowerShell script compiles Xilinx's ISE simulation libraries into a local # directory. # # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany # Chair for VLSI-Design, Diagnostics and Architecture -# +# # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at -# +# # http://www.apache.org/licenses/LICENSE-2.0 -# +# # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -30,60 +30,170 @@ # limitations under the License. # ============================================================================== -$PoC_RootDir = "\..\.." -$Simulator = "questa" # questa, ... -$Language = "vhdl" # all, vhdl, verilog -$TargetArchitecture = "all" # all, virtex5, virtex6, virtex7, ... +# .SYNOPSIS +# This CmdLet pre-compiles the simulation libraries from Xilinx ISE. +# +# .DESCRIPTION +# This CmdLet: +# (1) Creates a sub-directory 'xilinx-ise' in the current working directory +# (2) Compiles all Xilinx ISE simulation libraries and packages for +# o GHDL +# o QuestaSim +# (3) Creates a symlink 'xilinx' -> 'xilinx-ise' +# +[CmdletBinding()] +param( + # Pre-compile all libraries and packages for all simulators + [switch]$All = $false, + + # Pre-compile the Xilinx ISE libraries for GHDL + [switch]$GHDL = $false, + + # Pre-compile the Xilinx ISE libraries for QuestaSim + [switch]$Questa = $false, + + # Change the 'xilinx' symlink to 'xilinx-ise' + [switch]$ReLink = $false, + + # Set VHDL Standard to '93 + [switch]$VHDL93 = $false, + # Set VHDL Standard to '08 + [switch]$VHDL2008 = $false, + + # Clean up directory before analyzing. + [switch]$Clean = $false, + + # Show the embedded help page(s) + [switch]$Help = $false +) + +$PoCRootDir = "\..\.." # resolve paths -$PoC_RootDir = Convert-Path (Resolve-Path ($PSScriptRoot + $PoC_RootDir)) - -# load Xilinx ISE environment -$Command = "$PoC_RootDir\poc.ps1 --ise-settingsfile" -$ISE_SettingsFile = Invoke-Expression $Command -if (($LastExitCode -ne 0) -or ($ISE_SettingsFile -eq "")) -{ Write-Host "ERROR: No Xilinx ISE installation found." -ForegroundColor Red - Write-Host "Run '.\poc.ps1 --configure' to configure your Xilinx ISE installation." -ForegroundColor Red - exit 1 +$WorkingDir = Get-Location +$PoCRootDir = Convert-Path (Resolve-Path ($PSScriptRoot + $PoCRootDir)) +$PoCPS1 = "$PoCRootDir\poc.ps1" + +Import-Module $PSScriptRoot\precompile.psm1 -Verbose:$false -Debug:$false -ArgumentList "$WorkingDir" + +# Display help if no command was selected +$Help = $Help -or (-not ($All -or $GHDL -or $Questa)) + +if ($Help) +{ Get-Help $MYINVOCATION.InvocationName -Detailed + Exit-PrecompileScript } -else -{ Write-Host "Loading Xilinx ISE environment '$ISE_SettingsFile'" -ForegroundColor Yellow - if (($ISE_SettingsFile -like "*.bat") -or ($ISE_SettingsFile -like "*.cmd")) - { Import-Module PSCX - Invoke-BatchFile -path $ISE_SettingsFile + +$GHDL,$Questa = Resolve-Simulator $All $GHDL $Questa +$VHDL93,$VHDL2008 = Resolve-VHDLVersion $VHDL93 $VHDL2008 + +$PreCompiledDir = Get-PrecompiledDirectoryName $PoCPS1 +$XilinxDirName = Get-XilinxDirectoryName $PoCPS1 +$XilinxDirName2 = "$XilinxDirName-ise" + +# GHDL +# ============================================================================== +if ($GHDL) +{ Write-Host "Pre-compiling Xilinx's simulation libraries for GHDL" -ForegroundColor Cyan + Write-Host "--------------------------------------------------------------------------------" -ForegroundColor Cyan + + $GHDLBinDir = Get-GHDLBinaryDirectory $PoCPS1 + $GHDLScriptDir = Get-GHDLScriptDirectory $PoCPS1 + $GHDLDirName = Get-GHDLDirectoryName $PoCPS1 + + # Assemble output directory + $DestDir="$PoCRootDir\$PrecompiledDir\$GHDLDirName" + # Create and change to destination directory + Initialize-DestinationDirectory $DestDir + + $GHDLXilinxScript = "$GHDLScriptDir\compile-xilinx-ise.ps1" + if (-not (Test-Path $GHDLXilinxScript -PathType Leaf)) + { Write-Host "[ERROR]: Xilinx compile script from GHDL is not executable." -ForegroundColor Red + Exit-PrecompileScript -1 } - else - { . $ISE_SettingsFile } -} -if (-not (Test-Path env:XILINX)) -{ Write-Host "ERROR: No Xilinx ISE environment loaded." -ForegroundColor Red - exit 1 -} -Write-Host "Recompiling Xilinx's simulation libraries for QuestaSim" -ForegroundColor Cyan -Write-Host "--------------------------------------------------------------------------------" -ForegroundColor Cyan + $ISEInstallDir = Get-ISEInstallationDirectory $PoCPS1 + $SourceDir = "$ISEInstallDir\ISE\vhdl\src" + + # export GHDL environment variable if not allready set + if (-not (Test-Path env:GHDL)) -# Output directory -$Command = "$PoC_RootDir\poc.ps1 --poc-installdir" -$DestDir = Invoke-Expression $Command -if (($LastExitCode -ne 0) -or ($DestDir -eq "")) -{ Write-Host "ERROR: No PoC installation found." -ForegroundColor Red - exit 1 + { $env:GHDL = $GHDLBinDir } + if ($VHDL93) + { $Command = "$GHDLXilinxScript -All -VHDL93 -Source $SourceDir -Output $DestDir\$XilinxDirName2" + Invoke-Expression $Command + if ($LastExitCode -ne 0) + { Write-Host "[ERROR]: Error while compiling Xilinx ISE libraries." -ForegroundColor Red + Exit-PrecompileScript -1 + } + } + if ($VHDL2008) + { $Command = "$GHDLXilinxScript -All -VHDL2008 -Source $SourceDir -Output $DestDir\$XilinxDirName2" + Invoke-Expression $Command + if ($LastExitCode -ne 0) + { Write-Host "[ERROR]: Error while compiling Xilinx ISE libraries." -ForegroundColor Red + Exit-PrecompileScript -1 + } + } + + if (Test-Path $XilinxDirName -PathType Leaf) + { rm $XilinxDirName -ErrorAction SilentlyContinue } + # New-Symlink $XilinxDirName2 $XilinxDirName -ErrorAction SilentlyContinue + # if ($LastExitCode -ne 0) + # { Write-Host "[ERROR]: While creating a symlink. Not enough rights?" -ForegroundColor Red + # Exit-PrecompileScript -1 + # } + + # restore working directory + cd $WorkingDir + Write-Host "--------------------------------------------------------------------------------" -ForegroundColor Cyan } -$DestDir += "\temp\vsim" - -# Path to the simulators bin directory -$Command = "$PoC_RootDir\poc.ps1 --modelsim-installdir" -$SimulatorDir = Invoke-Expression $Command -if (($LastExitCode -ne 0) -or ($SimulatorDir -eq "")) -{ Write-Host "ERROR: No QuestaSim installation found." -ForegroundColor Red - Write-Host "Run '.\poc.ps1 --configure' to configure your Mentor QuestaSim installation." -ForegroundColor Red - exit 1 + +# QuestaSim/ModelSim +# ============================================================================== +if ($Questa) +{ Write-Host "Pre-compiling Xilinx's simulation libraries for QuestaSim" -ForegroundColor Cyan + Write-Host "--------------------------------------------------------------------------------" -ForegroundColor Cyan + + $VSimBinDir = Get-ModelSimBinaryDirectory $PoCPS1 + $VSimDirName = Get-QuestaSimDirectoryName $PoCPS1 + + # Assemble output directory + $DestDir="$PoCRootDir\$PrecompiledDir\$VSimDirName\$XilinxDirName2" + # Create and change to destination directory + Initialize-DestinationDirectory $DestDir + + $ISEBinDir = Get-ISEBinaryDirectory $PoCPS1 + $ISE_compxlib = "$ISEBinDir\compxlib.exe" + Open-ISEEnvironment $PoCPS1 + + New-ModelSim_ini + + $Simulator = "questa" + $Language = "vhdl" + $TargetArchitecture = "all" + + $Command = "$ISE_compxlib -64bit -s $Simulator -l $Language -dir $DestDir -p $VSimBinDir -arch $TargetArchitecture -lib unisim -lib simprim -lib xilinxcorelib -intstyle ise" + Invoke-Expression $Command + if (-not $?) + { Write-Host "[ERROR]: While executing vendor library compile script from GHDL." -ForegroundColor Red + Exit-PrecompileScript -1 + } + + rm $XilinxDirName -ErrorAction SilentlyContinue + # New-Symlink $XilinxDirName2 $XilinxDirName -ErrorAction SilentlyContinue + # if ($LastExitCode -ne 0) + # { Write-Host "[ERROR]: While creating a symlink. Not enough rights?" -ForegroundColor Red + # Exit-PrecompileScript -1 + # } + + Close-ISEEnvironment + + # restore working directory + cd $WorkingDir + Write-Host "--------------------------------------------------------------------------------" -ForegroundColor Cyan } -$SimulatorDir += "\win64" -$Command = $env:XILINX + "\bin\nt64\compxlib.exe -s $Simulator -l $Language -dir $DestDir -p $SimulatorDir -arch $TargetArchitecture -lib unisim -lib simprim -lib xilinxcorelib -intstyle ise" -Invoke-Expression $Command +Write-Host "[COMPLETE]" -ForegroundColor Green -Write-Host "--------------------------------------------------------------------------------" -ForegroundColor Cyan -Write-Host "[COMPLETE]" -ForegroundColor Green \ No newline at end of file +Exit-PrecompileScript diff --git a/tools/precompile/compile-xilinx-ise.sh b/tools/precompile/compile-xilinx-ise.sh index a8ad8950..859f39d0 100755 --- a/tools/precompile/compile-xilinx-ise.sh +++ b/tools/precompile/compile-xilinx-ise.sh @@ -1,29 +1,31 @@ -#!/bin/bash +#! /usr/bin/env bash # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- # vim: tabstop=2:shiftwidth=2:noexpandtab # kate: tab-width 2; replace-tabs off; indent-width 2; -# +# # ============================================================================== -# Authors: Martin Zabel -# -# Bash Script: Compile Xilinx's simulation libraries -# +# Authors: Martin Zabel +# Patrick Lehmann +# +# Bash Script: Compile Xilinx's ISE simulation libraries +# # Description: # ------------------------------------ -# This is a bash script compiles Xilinx's simulation libraries into a local -# directory. +# This is a Bash script (executable) which: +# - creates a subdirectory in the current working directory +# - compiles all Xilinx ISE libraries # # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany # Chair for VLSI-Design, Diagnostics and Architecture -# +# # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at -# +# # http://www.apache.org/licenses/LICENSE-2.0 -# +# # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -31,101 +33,231 @@ # limitations under the License. # ============================================================================== -poc_sh=../../poc.sh -Simulator=questa # questa, ghdl, ... -Language=vhdl # all, vhdl, verilog -TargetArchitecture=all # all, virtex5, virtex6, virtex7, ... +# work around for Darwin (Mac OS) +READLINK=readlink; if [[ $(uname) == "Darwin" ]]; then READLINK=greadlink; fi -ghdlScript=/space/install/ghdl/libraries/vendors/compile-xilinx-ise.sh +# Save working directory +WorkingDir=$(pwd) +ScriptDir="$(dirname $0)" +ScriptDir="$($READLINK -f $ScriptDir)" -# define color escape codes -RED='\e[0;31m' # Red -YELLOW='\e[1;33m' # Yellow -NOCOLOR='\e[0m' # No Color +PoCRootDir="$($READLINK -f $ScriptDir/../..)" +PoC_sh=$PoCRootDir/poc.sh -# if $XILINX environment variable is not set and Simulator /= ghdl -if [ -z "$XILINX" -a \( "$Simulator" != "ghdl" \) ]; then - PoC_ISE_SettingsFile=$($poc_sh query Xilinx.ISE:SettingsFile) - if [ $? -ne 0 ]; then - echo 1>&2 -e "${RED}ERROR: No Xilinx ISE installation found.${NOCOLOR}" - echo 1>&2 -e "${RED}Run 'PoC.py --configure' to configure your Xilinx ISE installation.${NOCOLOR}" - exit 1 - fi - echo -e "${YELLOW}Loading Xilinx ISE environment '$PoC_ISE_SettingsFile'${NOCOLOR}" - PyWrapper_RescueArgs=$@ - set -- - source "$PoC_ISE_SettingsFile" - set -- $PyWrapper_RescueArgs -fi +# source shared file from precompile directory +source $ScriptDir/shared.sh -# Setup destination directory -DestDir=$($poc_sh query INSTALL.PoC:InstallationDirectory 2>/dev/null)/temp/precompiled -if [ $? -ne 0 ]; then - echo 1>&2 -e "${RED}ERROR: Cannot get PoC installation dir.${NOCOLOR}" - exit; -fi -case "$Simulator" in - ghdl) - DestDir=$DestDir/ghdl +# command line argument processing +NO_COMMAND=1 +VHDL93=0 +VHDL2008=0 +while [[ $# > 0 ]]; do + key="$1" + case $key in + -c|--clean) + CLEAN=TRUE ;; - questa) - DestDir=$DestDir/vsim/xilinx-ise + -a|--all) + COMPILE_ALL=TRUE + NO_COMMAND=0 ;; - *) - echo "Unsupported simulator." - exit 1 + --ghdl) + COMPILE_FOR_GHDL=TRUE + NO_COMMAND=0 ;; -esac - -# Setup simulator directory -case "$Simulator" in - questa) - SimulatorDir=$($poc_sh query ModelSim:InstallationDirectory 2>/dev/null)/bin # Path to the simulators bin directory - if [ $? -ne 0 ]; then - echo 1>&2 -e "${RED}ERROR: Cannot get ModelSim installation dir.${NOCOLOR}" - exit; - fi + --questa) + COMPILE_FOR_VSIM=TRUE + NO_COMMAND=0 + ;; + -h|--help) + HELP=TRUE + NO_COMMAND=0 + ;; + --vhdl93) + VHDL93=1 + ;; + --vhdl2008) + VHDL2008=1 ;; -esac + *) # unknown option + echo 1>&2 -e "${COLORED_ERROR} Unknown command line option '$key'.${ANSI_NOCOLOR}" + exit -1 + ;; + esac + shift # past argument or value +done + +if [ $NO_COMMAND -eq 1 ]; then + HELP=TRUE +fi + +if [ "$HELP" == "TRUE" ]; then + test $NO_COMMAND -eq 1 && echo 1>&2 -e "\n${COLORED_ERROR} No command selected.${ANSI_NOCOLOR}" + echo "" + echo "Synopsis:" + echo " Script to compile the Xilinx ISE simulation libraries for" + echo " - GHDL" + echo " - QuestaSim/ModelSim" + echo " on Linux." + echo "" + echo "Usage:" + echo " compile-xilinx-ise.sh [-c] [--help|--all|--ghdl|--vsim] []" + echo "" + echo "Common commands:" + echo " -h --help Print this help page" + # echo " -c --clean Remove all generated files" + echo "" + echo "Tool chain:" + echo " -a --all Compile for all tool chains." + echo " --ghdl Compile for GHDL." + echo " --questa Compile for QuestaSim/ModelSim." + echo "" + echo "Options:" + echo " --vhdl93 Compile for VHDL-93." + echo " --vhdl2008 Compile for VHDL-2008." + echo "" + exit 0 +fi + -# Create and change to destination directory -mkdir -p $DestDir +if [ "$COMPILE_ALL" == "TRUE" ]; then + COMPILE_FOR_GHDL=TRUE + COMPILE_FOR_VSIM=TRUE +fi +if [ \( $VHDL93 -eq 0 \) -a \( $VHDL2008 -eq 0 \) ]; then + VHDL93=1 + VHDL2008=1 +fi + +PrecompiledDir=$($PoC_sh query CONFIG.DirectoryNames:PrecompiledFiles 2>/dev/null) if [ $? -ne 0 ]; then - echo 1>&2 -e "${RED}ERROR: Cannot create output directory.${NOCOLOR}" - exit; -fi + echo 1>&2 -e "${COLORED_ERROR} Cannot get precompiled directory name.${ANSI_NOCOLOR}" + echo 1>&2 -e "${ANSI_RED}$PrecompiledDir${ANSI_NOCOLOR}" + exit -1; +fi -cd $DestDir +XilinxDirName=$($PoC_sh query CONFIG.DirectoryNames:XilinxSpecificFiles 2>/dev/null) if [ $? -ne 0 ]; then - echo 1>&2 -e "${RED}ERROR: Cannot change to output directory.${NOCOLOR}" - exit; + echo 1>&2 -e "${COLORED_ERROR} Cannot get Xilinx directory name.${ANSI_NOCOLOR}" + echo 1>&2 -e "${ANSI_RED}$XilinxDirName${ANSI_NOCOLOR}" + exit -1; fi +XilinxDirName2=$XilinxDirName-ise -# Compile libraries with simulator, executed in $DestDir -case "$Simulator" in - ghdl) - $ghdlScript -a -s -S - ;; - questa) - # create modelsim.ini - echo "[Library]" > modelsim.ini - echo "others = ../modelsim.ini" >> modelsim.ini +# GHDL +# ============================================================================== +if [ "$COMPILE_FOR_GHDL" == "TRUE" ]; then + # Get GHDL directories + # <= $GHDLBinDir + # <= $GHDLScriptDir + # <= $GHDLDirName + GetGHDLDirectories $PoC_sh + + # Assemble output directory + DestDir=$PoCRootDir/$PrecompiledDir/$GHDLDirName + # Create and change to destination directory + # -> $DestinationDirectory + CreateDestinationDirectory $DestDir + + # Assemble Xilinx compile script path + GHDLXilinxScript="$($READLINK -f $GHDLScriptDir/compile-xilinx-ise.sh)" + + + # Get Xilinx installation directory + ISEInstallDir=$($PoC_sh query INSTALL.Xilinx.ISE:InstallationDirectory 2>/dev/null) + if [ $? -ne 0 ]; then + echo 1>&2 -e "${COLORED_ERROR} Cannot get Xilinx ISE installation directory.${ANSI_NOCOLOR}" + echo 1>&2 -e "${COLORED_MESSAGE} $ISEInstallDir${ANSI_NOCOLOR}" + echo 1>&2 -e "${ANSI_YELLOW}Run 'poc.sh configure' to configure your Xilinx ISE installation.${ANSI_NOCOLOR}" + exit -1; + fi + SourceDir=$ISEInstallDir/ISE/vhdl/src + + # export GHDL binary dir if not allready set + if [ -z $GHDL ]; then + export GHDL=$GHDLBinDir/ghdl + fi + + BASH=$(which bash) + + # compile all architectures, skip existing and large files, no wanrings + if [ $VHDL93 -eq 1 ]; then + $BASH $GHDLXilinxScript --all --vhdl93 -s -S -n --src $SourceDir --out $XilinxDirName2 if [ $? -ne 0 ]; then - echo 1>&2 -e "${RED}ERROR: Cannot create initial modelsim.ini.${NOCOLOR}" - exit; + echo 1>&2 -e "${COLORED_ERROR} While executing vendor library compile script from GHDL.${ANSI_NOCOLOR}" + exit -1; fi + fi + if [ $VHDL2008 -eq 1 ]; then + $BASH $GHDLXilinxScript --all --vhdl2008 -s -S -n --src $SourceDir --out $XilinxDirName2 + if [ $? -ne 0 ]; then + echo 1>&2 -e "${COLORED_ERROR} While executing vendor library compile script from GHDL.${ANSI_NOCOLOR}" + exit -1; + fi + fi - # call Xilinx script - compxlib -64bit -s $Simulator -l $Language -dir $DestDir -p $SimulatorDir -arch $TargetArchitecture -lib unisim -lib simprim -lib xilinxcorelib -intstyle ise - cd .. - ;; - *) - echo "Unsupported simulator." - exit 1 - ;; -esac + # create "xilinx" symlink + rm -f $XilinxDirName + ln -s $XilinxDirName2 $XilinxDirName +fi + +# QuestaSim/ModelSim +# ============================================================================== +if [ "$COMPILE_FOR_VSIM" == "TRUE" ]; then + # Get GHDL directories + # <= $VSimBinDir + # <= $VSimDirName + GetVSimDirectories $PoC_sh + + # Assemble output directory + DestDir=$PoCRootDir/$PrecompiledDir/$VSimDirName/$XilinxDirName2 + # Create and change to destination directory + # -> $DestinationDirectory + CreateDestinationDirectory $DestDir + + # if XILINX environment variable is not set, load ISE environment + if [ -z "$XILINX" ]; then + ISE_SettingsFile=$($PoC_sh query Xilinx.ISE:SettingsFile) + if [ $? -ne 0 ]; then + echo 1>&2 -e "${COLORED_ERROR} No Xilinx ISE installation found.${ANSI_NOCOLOR}" + echo 1>&2 -e "${COLORED_MESSAGE} $ISE_SettingsFile${ANSI_NOCOLOR}" + echo 1>&2 -e "${ANSI_YELLOW}Run 'poc.sh configure' to configure your Xilinx ISE installation.${ANSI_NOCOLOR}" + exit -1 + fi + echo -e "${ANSI_YELLOW}Loading Xilinx ISE environment '$ISE_SettingsFile'${ANSI_NOCOLOR}" + RescueArgs=$@ + set -- + source "$ISE_SettingsFile" + set -- $RescueArgs + fi + + ISEBinDir=$($PoC_sh query INSTALL.Xilinx.ISE:BinaryDirectory 2>/dev/null) + if [ $? -ne 0 ]; then + echo 1>&2 -e "${COLORED_ERROR} Cannot get Xilinx ISE binary directory.${ANSI_NOCOLOR}" + echo 1>&2 -e "${COLORED_MESSAGE} $ISEBinDir${ANSI_NOCOLOR}" + echo 1>&2 -e "${ANSI_YELLOW}Run 'poc.sh configure' to configure your Xilinx ISE installation.${ANSI_NOCOLOR}" + exit -1; + fi + ISE_compxlib=$ISEBinDir/compxlib + + # create an empty modelsim.ini in the 'xilinx-ise' directory and add reference to parent modelsim.ini + CreateLocalModelsim_ini + + Simulator=questa + Language=vhdl + TargetArchitecture=all # all, virtex5, virtex6, virtex7, ... + + # compile common libraries + $ISE_compxlib -64bit -s $Simulator -l $Language -dir $DestDir -p $VSimBinDir -arch $TargetArchitecture -lib unisim -lib simprim -lib xilinxcorelib -intstyle ise + if [ $? -ne 0 ]; then + echo 1>&2 -e "${COLORED_ERROR} Error while compiling Xilinx ISE libraries.${ANSI_NOCOLOR}" + exit -1; + fi + + # create "xilinx" symlink + cd .. + rm -f $XilinxDirName + ln -s $XilinxDirName2 $XilinxDirName +fi -# create "xilinx" symlink -rm -f xilinx -ln -s xilinx-ise xilinx diff --git a/tools/precompile/compile-xilinx-vivado.ps1 b/tools/precompile/compile-xilinx-vivado.ps1 new file mode 100644 index 00000000..74bf01e7 --- /dev/null +++ b/tools/precompile/compile-xilinx-vivado.ps1 @@ -0,0 +1,209 @@ +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# +# ============================================================================== +# Authors: Patrick Lehmann +# +# PowerShell Script: Compile Xilinx's simulation libraries +# +# Description: +# ------------------------------------ +# This PowerShell script compiles Xilinx's Vivado simulation libraries into a +# local directory. +# +# License: +# ============================================================================== +# Copyright 2007-2016 Technische Universitaet Dresden - Germany +# Chair for VLSI-Design, Diagnostics and Architecture +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================== + +# .SYNOPSIS +# This CmdLet pre-compiles the simulation libraries from Xilinx Vivado. +# +# .DESCRIPTION +# This CmdLet: +# (1) Creates a sub-directory 'xilinx-vivado' in the current working directory +# (2) Compiles all Xilinx Vivado simulation libraries and packages for +# o GHDL +# o QuestaSim +# (3) Creates a symlink 'xilinx' -> 'xilinx-vivado' +# +[CmdletBinding()] +param( + # Pre-compile all libraries and packages for all simulators + [switch]$All = $false, + + # Pre-compile the Xilinx Vivado libraries for GHDL + [switch]$GHDL = $false, + + # Pre-compile the Xilinx Vivado libraries for QuestaSim + [switch]$Questa = $false, + + # Change the 'xilinx' symlink to 'xilinx-vivado' + [switch]$ReLink = $false, + + # Set VHDL Standard to '93 + [switch]$VHDL93 = $false, + # Set VHDL Standard to '08 + [switch]$VHDL2008 = $false, + + # Clean up directory before analyzing. + [switch]$Clean = $false, + + # Show the embedded help page(s) + [switch]$Help = $false +) + +$PoCRootDir = "\..\.." + +# resolve paths +$WorkingDir = Get-Location +$PoCRootDir = Convert-Path (Resolve-Path ($PSScriptRoot + $PoCRootDir)) +$PoCPS1 = "$PoCRootDir\poc.ps1" + +Import-Module $PSScriptRoot\precompile.psm1 -Verbose:$false -Debug:$false -ArgumentList "$WorkingDir" + +# Display help if no command was selected +$Help = $Help -or (-not ($All -or $GHDL -or $Questa)) + +if ($Help) +{ Get-Help $MYINVOCATION.InvocationName -Detailed + Exit-PrecompileScript +} + +$GHDL,$Questa = Resolve-Simulator $All $GHDL $Questa +$VHDL93,$VHDL2008 = Resolve-VHDLVersion $VHDL93 $VHDL2008 + +$PreCompiledDir = Get-PrecompiledDirectoryName $PoCPS1 +$XilinxDirName = Get-XilinxDirectoryName $PoCPS1 +$XilinxDirName2 = "$XilinxDirName-vivado" + +# GHDL +# ============================================================================== +if ($GHDL) +{ Write-Host "Pre-compiling Xilinx's simulation libraries for GHDL" -ForegroundColor Cyan + Write-Host "--------------------------------------------------------------------------------" -ForegroundColor Cyan + + $GHDLBinDir = Get-GHDLBinaryDirectory $PoCPS1 + $GHDLScriptDir = Get-GHDLScriptDirectory $PoCPS1 + $GHDLDirName = Get-GHDLDirectoryName $PoCPS1 + + # Assemble output directory + $DestDir="$PoCRootDir\$PrecompiledDir\$GHDLDirName" + # Create and change to destination directory + Initialize-DestinationDirectory $DestDir + + $GHDLXilinxScript = "$GHDLScriptDir\compile-xilinx-vivado.ps1" + if (-not (Test-Path $GHDLXilinxScript -PathType Leaf)) + { Write-Host "[ERROR]: Xilinx compile script from GHDL is not executable." -ForegroundColor Red + Exit-PrecompileScript -1 + } + + $VivadoInstallDir = Get-VivadoInstallationDirectory $PoCPS1 + $SourceDir = "$VivadoInstallDir\data\vhdl\src" + + # export GHDL environment variable if not allready set + if (-not (Test-Path env:GHDL)) + { $env:GHDL = $GHDLBinDir } + + if ($VHDL93) + { $Command = "$GHDLXilinxScript -All -VHDL93 -Source $SourceDir -Output $DestDir\$XilinxDirName2" + Invoke-Expression $Command + if ($LastExitCode -ne 0) + { Write-Host "[ERROR]: While executing vendor library compile script from GHDL." -ForegroundColor Red + Exit-PrecompileScript -1 + } + } + if ($VHDL2008) + { $Command = "$GHDLXilinxScript -All -VHDL2008 -Source $SourceDir -Output $DestDir\$XilinxDirName2" + Invoke-Expression $Command + if ($LastExitCode -ne 0) + { Write-Host "[ERROR]: While executing vendor library compile script from GHDL." -ForegroundColor Red + Exit-PrecompileScript -1 + } + } + + if (Test-Path $XilinxDirName -PathType Leaf) + { rm $XilinxDirName -ErrorAction SilentlyContinue } + # New-Symlink $XilinxDirName2 $XilinxDirName -ErrorAction SilentlyContinue + # if ($LastExitCode -ne 0) + # { Write-Host "[ERROR]: While creating a symlink. Not enough rights?" -ForegroundColor Red + # Exit-PrecompileScript -1 + # } + + # restore working directory + cd $WorkingDir + Write-Host "--------------------------------------------------------------------------------" -ForegroundColor Cyan +} + +# QuestaSim/ModelSim +# ============================================================================== +if ($Questa) +{ Write-Host "Pre-compiling Xilinx's simulation libraries for QuestaSim" -ForegroundColor Cyan + Write-Host "--------------------------------------------------------------------------------" -ForegroundColor Cyan + + $VSimBinDir = Get-ModelSimBinaryDirectory $PoCPS1 + $VSimDirName = Get-QuestaSimDirectoryName $PoCPS1 + + # Assemble output directory + $DestDir="$PoCRootDir\$PrecompiledDir\$VSimDirName\$XilinxDirName2" + # Create and change to destination directory + Initialize-DestinationDirectory $DestDir + + $VivadoBinDir = Get-VivadoBinaryDirectory $PoCPS1 + $Vivado_tcl = "$VivadoBinDir\vivado.bat" + Open-VivadoEnvironment $PoCPS1 + + New-ModelSim_ini + + $Simulator = "questa" + $Language = "all" + $Library = "all" + $Family = "all" + + $CommandFile = "vivado.tcl" + $VSimBinDir_TclPath = $VSimBinDir.Replace("\", "/") + $DestDir_TclPath = $DestDir.Replace("\", "/") + "compile_simlib -force -library $Library -family $Family -language $Language -simulator $Simulator -simulator_exec_path $VSimBinDir_TclPath -directory $DestDir_TclPath`nexit" | Out-File $CommandFile -Encoding ascii + if (-not $?) + { Write-Host "[ERROR]: Cannot create temporary tcl script." -ForegroundColor Red + Exit-PrecompileScript -1 + } + + $Command = "$Vivado_tcl -mode batch -source $CommandFile" + Invoke-Expression $Command + if ($LastExitCode -ne 0) + { Write-Host "[ERROR]: Error while compiling Xilinx Vivado libraries." -ForegroundColor Red + Exit-PrecompileScript -1 + } + + rm $XilinxDirName -ErrorAction SilentlyContinue + # New-Symlink $XilinxDirName2 $XilinxDirName -ErrorAction SilentlyContinue + # if ($LastExitCode -ne 0) + # { Write-Host "[ERROR]: While creating a symlink. Not enough rights?" -ForegroundColor Red + # Exit-PrecompileScript -1 + # } + + Close-VivadoEnvironment + + # restore working directory + cd $WorkingDir + Write-Host "--------------------------------------------------------------------------------" -ForegroundColor Cyan +} + +Write-Host "[COMPLETE]" -ForegroundColor Green + +Exit-PrecompileScript diff --git a/tools/precompile/compile-xilinx-vivado.sh b/tools/precompile/compile-xilinx-vivado.sh new file mode 100755 index 00000000..d3b4a23e --- /dev/null +++ b/tools/precompile/compile-xilinx-vivado.sh @@ -0,0 +1,273 @@ +#! /usr/bin/env bash +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# +# ============================================================================== +# Authors: Martin Zabel +# Patrick Lehmann +# +# Bash Script: Compile Xilinx's Vivado simulation libraries +# +# Description: +# ------------------------------------ +# This is a Bash script (executable) which: +# - creates a subdirectory in the current working directory +# - compiles all Xilinx Vivado libraries +# +# License: +# ============================================================================== +# Copyright 2007-2016 Technische Universitaet Dresden - Germany +# Chair for VLSI-Design, Diagnostics and Architecture +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================== + +# work around for Darwin (Mac OS) +READLINK=readlink; if [[ $(uname) == "Darwin" ]]; then READLINK=greadlink; fi + +# Save working directory +WorkingDir=$(pwd) +ScriptDir="$(dirname $0)" +ScriptDir="$($READLINK -f $ScriptDir)" + +PoCRootDir="$($READLINK -f $ScriptDir/../..)" +PoC_sh=$PoCRootDir/poc.sh + +# source shared file from precompile directory +source $ScriptDir/shared.sh + + +# command line argument processing +NO_COMMAND=1 +VHDL93=0 +VHDL2008=0 +while [[ $# > 0 ]]; do + key="$1" + case $key in + -c|--clean) + CLEAN=TRUE + ;; + -a|--all) + COMPILE_ALL=TRUE + NO_COMMAND=0 + ;; + --ghdl) + COMPILE_FOR_GHDL=TRUE + NO_COMMAND=0 + ;; + --questa) + COMPILE_FOR_VSIM=TRUE + NO_COMMAND=0 + ;; + -h|--help) + HELP=TRUE + NO_COMMAND=0 + ;; + --vhdl93) + VHDL93=1 + ;; + --vhdl2008) + VHDL2008=1 + ;; + *) # unknown option + echo 1>&2 -e "${COLORED_ERROR} Unknown command line option '$key'.${ANSI_NOCOLOR}" + exit -1 + ;; + esac + shift # past argument or value +done + +if [ $NO_COMMAND -eq 1 ]; then + HELP=TRUE +fi + +if [ "$HELP" == "TRUE" ]; then + test $NO_COMMAND -eq 1 && echo 1>&2 -e "\n${COLORED_ERROR} No command selected.${ANSI_NOCOLOR}" + echo "" + echo "Synopsis:" + echo " Script to compile the Xilinx Vivado simulation libraries for" + echo " - GHDL" + echo " - QuestaSim/ModelSim" + echo " on Linux." + echo "" + echo "Usage:" + echo " compile-xilinx-vivado.sh [-c] [--help|--all|--ghdl|--vsim] []" + echo "" + echo "Common commands:" + echo " -h --help Print this help page" + # echo " -c --clean Remove all generated files" + echo "" + echo "Tool chain:" + echo " -a --all Compile for all tool chains." + echo " --ghdl Compile for GHDL." + echo " --questa Compile for QuestaSim/ModelSim." + echo "" + echo "Options:" + echo " --vhdl93 Compile for VHDL-93." + echo " --vhdl2008 Compile for VHDL-2008." + echo "" + exit 0 +fi + + +if [ "$COMPILE_ALL" == "TRUE" ]; then + COMPILE_FOR_GHDL=TRUE + COMPILE_FOR_VSIM=TRUE +fi +if [ \( $VHDL93 -eq 0 \) -a \( $VHDL2008 -eq 0 \) ]; then + VHDL93=1 + VHDL2008=1 +fi + +PrecompiledDir=$($PoC_sh query CONFIG.DirectoryNames:PrecompiledFiles 2>/dev/null) +if [ $? -ne 0 ]; then + echo 1>&2 -e "${COLORED_ERROR} Cannot get precompiled directory.${ANSI_NOCOLOR}" + echo 1>&2 -e "${ANSI_RED}$PrecompiledDir${ANSI_NOCOLOR}" + exit -1; +fi + +XilinxDirName=$($PoC_sh query CONFIG.DirectoryNames:XilinxSpecificFiles 2>/dev/null) +if [ $? -ne 0 ]; then + echo 1>&2 -e "${COLORED_ERROR} Cannot get Xilinx directory.${ANSI_NOCOLOR}" + echo 1>&2 -e "${ANSI_RED}$XilinxDirName${ANSI_NOCOLOR}" + exit -1; +fi +XilinxDirName2=$XilinxDirName-vivado + +# GHDL +# ============================================================================== +if [ "$COMPILE_FOR_GHDL" == "TRUE" ]; then + # Get GHDL directories + # <= $GHDLBinDir + # <= $GHDLScriptDir + # <= $GHDLDirName + GetGHDLDirectories $PoC_sh + + # Assemble output directory + DestDir=$PoCRootDir/$PrecompiledDir/$GHDLDirName + # Create and change to destination directory + # -> $DestinationDirectory + CreateDestinationDirectory $DestDir + + # Assemble Xilinx compile script path + GHDLXilinxScript="$($READLINK -f $GHDLScriptDir/compile-xilinx-vivado.sh)" + + + # Get Xilinx installation directory + VivadoInstallDir=$($PoC_sh query INSTALL.Xilinx.Vivado:InstallationDirectory 2>/dev/null) + if [ $? -ne 0 ]; then + echo 1>&2 -e "${COLORED_ERROR} Cannot get Xilinx Vivado installation directory.${ANSI_NOCOLOR}" + echo 1>&2 -e "${COLORED_MESSAGE} $VivadoInstallDir${ANSI_NOCOLOR}" + echo 1>&2 -e "${ANSI_YELLOW}Run 'poc.sh configure' to configure your Xilinx Vivado installation.${ANSI_NOCOLOR}" + exit -1; + fi + SourceDir=$VivadoInstallDir/data/vhdl/src + + # export GHDL binary dir if not allready set + if [ -z $GHDL ]; then + export GHDL=$GHDLBinDir/ghdl + fi + + BASH=$(which bash) + + # compile all architectures, skip existing and large files, no wanrings + if [ $VHDL93 -eq 1 ]; then + $BASH $GHDLXilinxScript --all --vhdl93 -s -S -n --src $SourceDir --out $XilinxDirName2 + if [ $? -ne 0 ]; then + echo 1>&2 -e "${COLORED_ERROR} While executing vendor library compile script from GHDL.${ANSI_NOCOLOR}" + exit -1; + fi + fi + if [ $VHDL2008 -eq 1 ]; then + $BASH $GHDLXilinxScript --all --vhdl2008 -s -S -n --src $SourceDir --out $XilinxDirName2 + if [ $? -ne 0 ]; then + echo 1>&2 -e "${COLORED_ERROR} While executing vendor library compile script from GHDL.${ANSI_NOCOLOR}" + exit -1; + fi + fi + + # create "xilinx" symlink + rm -f $XilinxDirName + ln -s $XilinxDirName2 $XilinxDirName +fi + +# QuestaSim/ModelSim +# ============================================================================== +if [ "$COMPILE_FOR_VSIM" == "TRUE" ]; then + # Get GHDL directories + # <= $VSimBinDir + # <= $VSimDirName + GetVSimDirectories $PoC_sh + + # Assemble output directory + DestDir=$PoCRootDir/$PrecompiledDir/$VSimDirName/$XilinxDirName2 + + # Create and change to destination directory + # -> $DestinationDirectory + CreateDestinationDirectory $DestDir + + # if XILINX_VIVADO environment variable is not set, load Vivado environment + if [ -z "$XILINX_VIVADO" ]; then + Vivado_SettingsFile=$($PoC_sh query Xilinx.Vivado:SettingsFile) + if [ $? -ne 0 ]; then + echo 1>&2 -e "${COLORED_ERROR} No Xilinx Vivado installation found.${ANSI_NOCOLOR}" + echo 1>&2 -e "${COLORED_MESSAGE} $Vivado_SettingsFile${ANSI_NOCOLOR}" + echo 1>&2 -e "${ANSI_YELLOW}Run 'poc.sh configure' to configure your Xilinx Vivado installation.${ANSI_NOCOLOR}" + exit -1 + fi + echo -e "${ANSI_YELLOW}Loading Xilinx Vivado environment '$Vivado_SettingsFile'${ANSI_NOCOLOR}" + RescueArgs=$@ + set -- + source "$Vivado_SettingsFile" + set -- $RescueArgs + fi + + VivadoBinDir=$($PoC_sh query INSTALL.Xilinx.Vivado:BinaryDirectory 2>/dev/null) + if [ $? -ne 0 ]; then + echo 1>&2 -e "${COLORED_ERROR} Cannot get Xilinx Vivado binary directory.${ANSI_NOCOLOR}" + echo 1>&2 -e "${COLORED_MESSAGE} $VivadoBinDir${ANSI_NOCOLOR}" + echo 1>&2 -e "${ANSI_YELLOW}Run 'poc.sh configure' to configure your Xilinx Vivado installation.${ANSI_NOCOLOR}" + exit -1; + fi + Vivado_tcl=$VivadoBinDir/vivado + + # create an empty modelsim.ini in the 'xilinx-vivado' directory and add reference to parent modelsim.ini + CreateLocalModelsim_ini + + Simulator=questa + Language=all + Library=all + Family=all # all, virtex5, virtex6, virtex7, ... + + CommandFile=vivado.tcl + + echo -e "compile_simlib -force -no_ip_compile -library $Library -family $Family -language $Language -simulator $Simulator -simulator_exec_path $VSimBinDir -directory $DestDir\nexit" > $CommandFile + if [ $? -ne 0 ]; then + echo 1>&2 -e "${COLORED_ERROR} Cannot create temporary tcl script.${ANSI_NOCOLOR}" + exit -1; + fi + + # compile common libraries + $Vivado_tcl -mode batch -source $CommandFile + if [ $? -ne 0 ]; then + echo 1>&2 -e "${COLORED_ERROR} Error while compiling Xilinx Vivado libraries.${ANSI_NOCOLOR}" + exit -1; + fi + + # create "xilinx" symlink + cd .. + rm -f $XilinxDirName + ln -s $XilinxDirName2 $XilinxDirName +fi + diff --git a/tools/precompile/ghdl.grcrules b/tools/precompile/ghdl.grcrules new file mode 100644 index 00000000..1bc60783 --- /dev/null +++ b/tools/precompile/ghdl.grcrules @@ -0,0 +1,15 @@ +# color warnings +regexp=^.*?:\d+:\d+:warning: .* +colours=yellow +count=stop +========= + +# color errors +regexp=^.*?:\d+:\d+: .* +colours=red +count=stop +========= + +# skip additional message line on Linux +regexp=^ghdl: compilation error +skip=yes diff --git a/tools/precompile/ghdl.skipwarning.grcrules b/tools/precompile/ghdl.skipwarning.grcrules new file mode 100644 index 00000000..0609b060 --- /dev/null +++ b/tools/precompile/ghdl.skipwarning.grcrules @@ -0,0 +1,14 @@ +# skip warnings +regexp=^.*?:\d+:\d+:warning: .* +skip=yes +========= + +# color errors +regexp=^.*?:\d+:\d+: .* +colours=red +count=stop +========= + +# skip additional message line on Linux +regexp=^ghdl: compilation error +skip=yes diff --git a/tools/precompile/precompile.psm1 b/tools/precompile/precompile.psm1 new file mode 100644 index 00000000..6fe8beb9 --- /dev/null +++ b/tools/precompile/precompile.psm1 @@ -0,0 +1,959 @@ +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# +# ============================================================================== +# Authors: Patrick Lehmann +# +# PowerShell Module: The module provides common CmdLets for the library +# pre-compilation process. +# +# Description: +# ------------------------------------ +# This PowerShell module provides CommandLets (CmdLets) to handle the GHDL.exe +# output streams (stdout and stderr). +# +# ============================================================================== +# Copyright (C) 2015-2016 Patrick Lehmann +# +# GHDL is free software; you can redistribute it and/or modify it under +# the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 2, or (at your option) any later +# version. +# +# GHDL is distributed in the hope that it will be useful, but WITHOUT ANY +# WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# for more details. +# +# You should have received a copy of the GNU General Public License +# along with GHDL; see the file COPYING. If not, write to the Free +# Software Foundation, 59 Temple Place - Suite 330, Boston, MA +# 02111-1307, USA. +# ============================================================================== + +[CmdletBinding()] +param( + [Parameter(Mandatory=$true)][string]$WorkingDir +) + +$Module_WorkingDir = $WorkingDir + +function Exit-PrecompileScript +{ <# + .SYNOPSIS + Undocumented + + .DESCRIPTION + Undocumented + + .PARAMETER ExitCode + ExitCode of this script run + #> + [CmdletBinding()] + param( + [int]$ExitCode = 0 + ) + + # restore environment + rm env:GHDL -ErrorAction SilentlyContinue + + cd $Module_WorkingDir + + # unload modules + Remove-Module precompile -Verbose:$false + + if ($ExitCode -eq 0) + { exit 0 } + else + { Write-Host "[DEBUG]: HARD EXIT" -ForegroundColor Cyan + exit $ExitCode + } +} + +function Resolve-Simulator +{ <# + .SYNOPSIS + Undocumented + + .DESCRIPTION + Undocumented + + .PARAMETER All + Undocumented + .PARAMETER GHDL + Undocumented + .PARAMETER QuestaSim + Undocumented + #> + [CmdletBinding()] + param( + [Parameter(Mandatory=$true)][bool]$All, + [Parameter(Mandatory=$true)][bool]$GHDL, + [Parameter(Mandatory=$true)][bool]$QuestaSim + ) + if ($All) + { return $true, $true } + else + { return $GHDL, $QuestaSim } +} + +function Resolve-VHDLVersion +{ <# + .SYNOPSIS + Undocumented + + .DESCRIPTION + Undocumented + + .PARAMETER VHDL93 + Undocumented + .PARAMETER VHDL2008 + Undocumented + #> + [CmdletBinding()] + param( + [Parameter(Mandatory=$true)][bool]$VHDL93, + [Parameter(Mandatory=$true)][bool]$VHDL2008 + ) + if (-not $VHDL93 -and -not $VHDL2008) # no Version selected + { return $true, $true } # => compile all versions + elseif ($VHDL93 -and -not $VHDL2008) + { return $true, $false } + elseif (-not $VHDL93 -and $VHDL2008) + { return $false, $true } +} + +function Get-PrecompiledDirectoryName +{ <# + .SYNOPSIS + Undocumented + + .DESCRIPTION + Undocumented + + .PARAMETER PoCPS1 + PoC's front-end script + #> + [CmdletBinding()] + param( + [Parameter(Mandatory=$true)][string]$PoCPS1 + ) + + $Command = "$PoCPS1 query CONFIG.DirectoryNames:PrecompiledFiles" + $Result = Invoke-Expression $Command + if (($LastExitCode -ne 0) -or ($Result -eq "")) + { Write-Host "[ERROR]: Cannot get precompiled directory name." -ForegroundColor Red + Write-Host "$Result" -ForegroundColor Red + Exit-PrecompileScript -1 + } + return $Result +} + +function Get-AlteraDirectoryName +{ <# + .SYNOPSIS + Undocumented + + .DESCRIPTION + Undocumented + + .PARAMETER PoCPS1 + PoC's front-end script + #> + [CmdletBinding()] + param( + [Parameter(Mandatory=$true)][string]$PoCPS1 + ) + + $Command = "$PoCPS1 query CONFIG.DirectoryNames:AlteraSpecificFiles" + $Result = Invoke-Expression $Command + if (($LastExitCode -ne 0) -or ($Result -eq "")) + { Write-Host "[ERROR]: Cannot get Altera directory name." -ForegroundColor Red + Write-Host "$Result" -ForegroundColor Red + Exit-PrecompileScript -1 + } + return $Result +} + +function Get-LatticeDirectoryName +{ <# + .SYNOPSIS + Undocumented + + .DESCRIPTION + Undocumented + + .PARAMETER PoCPS1 + PoC's front-end script + #> + [CmdletBinding()] + param( + [Parameter(Mandatory=$true)][string]$PoCPS1 + ) + + $Command = "$PoCPS1 query CONFIG.DirectoryNames:LatticeSpecificFiles" + $Result = Invoke-Expression $Command + if (($LastExitCode -ne 0) -or ($Result -eq "")) + { Write-Host "[ERROR]: Cannot get Lattice directory name." -ForegroundColor Red + Write-Host "$Result" -ForegroundColor Red + Exit-PrecompileScript -1 + } + return $Result +} + +function Get-XilinxDirectoryName +{ <# + .SYNOPSIS + Undocumented + + .DESCRIPTION + Undocumented + + .PARAMETER PoCPS1 + PoC's front-end script + #> + [CmdletBinding()] + param( + [Parameter(Mandatory=$true)][string]$PoCPS1 + ) + + $Command = "$PoCPS1 query CONFIG.DirectoryNames:XilinxSpecificFiles" + $Result = Invoke-Expression $Command + if (($LastExitCode -ne 0) -or ($Result -eq "")) + { Write-Host "[ERROR]: Cannot get Xilinx directory name." -ForegroundColor Red + Write-Host "$Result" -ForegroundColor Red + Exit-PrecompileScript -1 + } + return $Result +} + +function Get-GHDLDirectoryName +{ <# + .SYNOPSIS + Undocumented + + .DESCRIPTION + Undocumented + + .PARAMETER PoCPS1 + PoC's front-end script + #> + [CmdletBinding()] + param( + [Parameter(Mandatory=$true)][string]$PoCPS1 + ) + + $Command = "$PoCPS1 query CONFIG.DirectoryNames:GHDLFiles" + $Result = Invoke-Expression $Command + if (($LastExitCode -ne 0) -or ($Result -eq "")) + { Write-Host "[ERROR]: Cannot get GHDL directory name." -ForegroundColor Red + Write-Host "$Result" -ForegroundColor Red + Exit-PrecompileScript -1 + } + return $Result +} + +function Get-GHDLBinaryDirectory +{ <# + .SYNOPSIS + Undocumented + + .DESCRIPTION + Undocumented + + .PARAMETER PoCPS1 + PoC's front-end script + #> + [CmdletBinding()] + param( + [Parameter(Mandatory=$true)][string]$PoCPS1 + ) + + $Command = "$PoCPS1 query INSTALL.GHDL:BinaryDirectory" + $Result = Invoke-Expression $Command + if (($LastExitCode -ne 0) -or ($Result -eq "")) + { Write-Host "[ERROR]: Cannot get GHDL binary directory." -ForegroundColor Red + Write-Host " $Result" -ForegroundColor Yellow + Write-Host "Run 'poc.ps1 configure' to configure your GHDL installation." -ForegroundColor Yellow + Exit-PrecompileScript -1 + } + return $Result.Replace("/", "\") +} + +function Get-GHDLScriptDirectory +{ <# + .SYNOPSIS + Undocumented + + .DESCRIPTION + Undocumented + + .PARAMETER PoCPS1 + PoC's front-end script + #> + [CmdletBinding()] + param( + [Parameter(Mandatory=$true)][string]$PoCPS1 + ) + + $Command = "$PoCPS1 query INSTALL.GHDL:ScriptDirectory" + $Result = Invoke-Expression $Command + if (($LastExitCode -ne 0) -or ($Result -eq "")) + { Write-Host "[ERROR]: Cannot get GHDL script directory." -ForegroundColor Red + Write-Host " $Result" -ForegroundColor Yellow + Write-Host "Run 'poc.ps1 configure' to configure your GHDL installation." -ForegroundColor Yellow + Exit-PrecompileScript -1 + } + return $Result.Replace("/", "\") +} + +function Get-QuestaSimDirectoryName +{ <# + .SYNOPSIS + Undocumented + + .DESCRIPTION + Undocumented + + .PARAMETER PoCPS1 + PoC's front-end script + #> + [CmdletBinding()] + param( + [Parameter(Mandatory=$true)][string]$PoCPS1 + ) + + $Command = "$PoCPS1 query CONFIG.DirectoryNames:QuestaSimFiles" + $Result = Invoke-Expression $Command + if (($LastExitCode -ne 0) -or ($Result -eq "")) + { Write-Host "[ERROR]: Cannot get Mentor QuestaSim directory name." -ForegroundColor Red + Write-Host "$Result" -ForegroundColor Red + Exit-PrecompileScript -1 + } + return $Result +} + +function Get-ModelSimBinaryDirectory +{ <# + .SYNOPSIS + Undocumented + + .DESCRIPTION + Undocumented + + .PARAMETER PoCPS1 + PoC's front-end script + #> + [CmdletBinding()] + param( + [Parameter(Mandatory=$true)][string]$PoCPS1 + ) + + $Command = "$PoCPS1 query ModelSim:BinaryDirectory" + $Result = Invoke-Expression $Command + if (($LastExitCode -ne 0) -or ($Result -eq "")) + { Write-Host "[ERROR]: Cannot get QuestaSim/ModelSim binary directory." -ForegroundColor Red + Write-Host " $Result" -ForegroundColor Yellow + Write-Host "Run 'poc.ps1 configure' to configure your Mentor QuestaSim/ModelSim installation." -ForegroundColor Yellow + Exit-PrecompileScript -1 + } + return $Result.Replace("/", "\") +} + +function Get-QuartusInstallationDirectory +{ <# + .SYNOPSIS + Undocumented + + .DESCRIPTION + Undocumented + + .PARAMETER PoCPS1 + PoC's front-end script + #> + [CmdletBinding()] + param( + [Parameter(Mandatory=$true)][string]$PoCPS1 + ) + + $Command = "$PoCPS1 query INSTALL.Altera.Quartus:InstallationDirectory" + $Result = Invoke-Expression $Command + if (($LastExitCode -ne 0) -or ($Result -eq "")) + { Write-Host "[ERROR]: Cannot get Altera Quartus installation directory." -ForegroundColor Red + Write-Host " $Result" -ForegroundColor Yellow + Write-Host "Run 'poc.ps1 configure' to configure your Altera Quartus installation." -ForegroundColor Yellow + Exit-PrecompileScript -1 + } + return $Result.Replace("/", "\") +} + +function Get-QuartusBinaryDirectory +{ <# + .SYNOPSIS + Undocumented + + .DESCRIPTION + Undocumented + + .PARAMETER PoCPS1 + PoC's front-end script + #> + [CmdletBinding()] + param( + [Parameter(Mandatory=$true)][string]$PoCPS1 + ) + + $Command = "$PoCPS1 query INSTALL.Altera.Quartus:BinaryDirectory" + $Result = Invoke-Expression $Command + if (($LastExitCode -ne 0) -or ($Result -eq "")) + { Write-Host "[ERROR]: Cannot get Altera Quartus installation directory." -ForegroundColor Red + Write-Host " $Result" -ForegroundColor Yellow + Write-Host "Run 'poc.ps1 configure' to configure your Altera Quartus installation." -ForegroundColor Yellow + Exit-PrecompileScript -1 + } + return $Result.Replace("/", "\") +} + +function Get-DiamondInstallationDirectory +{ <# + .SYNOPSIS + Undocumented + + .DESCRIPTION + Undocumented + + .PARAMETER PoCPS1 + PoC's front-end script + #> + [CmdletBinding()] + param( + [Parameter(Mandatory=$true)][string]$PoCPS1 + ) + + $Command = "$PoCPS1 query INSTALL.Lattice.Diamond:InstallationDirectory" + $Result = Invoke-Expression $Command + if (($LastExitCode -ne 0) -or ($Result -eq "")) + { Write-Host "[ERROR]: Cannot get Lattice Diamond installation directory." -ForegroundColor Red + Write-Host " $Result" -ForegroundColor Yellow + Write-Host "Run 'poc.ps1 configure' to configure your Lattice Diamond installation." -ForegroundColor Yellow + Exit-PrecompileScript -1 + } + return $Result.Replace("/", "\") +} + +function Get-DiamondBinaryDirectory +{ <# + .SYNOPSIS + Undocumented + + .DESCRIPTION + Undocumented + + .PARAMETER PoCPS1 + PoC's front-end script + #> + [CmdletBinding()] + param( + [Parameter(Mandatory=$true)][string]$PoCPS1 + ) + + $Command = "$PoCPS1 query INSTALL.Lattice.Diamond:BinaryDirectory" + $Result = Invoke-Expression $Command + if (($LastExitCode -ne 0) -or ($Result -eq "")) + { Write-Host "[ERROR]: Cannot get Lattice Diamond installation directory." -ForegroundColor Red + Write-Host " $Result" -ForegroundColor Yellow + Write-Host "Run 'poc.ps1 configure' to configure your Lattice Diamond installation." -ForegroundColor Yellow + Exit-PrecompileScript -1 + } + return $Result.Replace("/", "\") +} + +function Get-ISEInstallationDirectory +{ <# + .SYNOPSIS + Undocumented + + .DESCRIPTION + Undocumented + + .PARAMETER PoCPS1 + PoC's front-end script + #> + [CmdletBinding()] + param( + [Parameter(Mandatory=$true)][string]$PoCPS1 + ) + + $Command = "$PoCPS1 query INSTALL.Xilinx.ISE:InstallationDirectory" + $Result = Invoke-Expression $Command + if (($LastExitCode -ne 0) -or ($Result -eq "")) + { Write-Host "[ERROR]: Cannot get Xilinx ISE installation directory." -ForegroundColor Red + Write-Host " $Result" -ForegroundColor Yellow + Write-Host "Run 'poc.ps1 configure' to configure your Xilinx ISE installation." -ForegroundColor Yellow + Exit-PrecompileScript -1 + } + return $Result.Replace("/", "\") +} + +function Get-ISEBinaryDirectory +{ <# + .SYNOPSIS + Undocumented + + .DESCRIPTION + Undocumented + + .PARAMETER PoCPS1 + PoC's front-end script + #> + [CmdletBinding()] + param( + [Parameter(Mandatory=$true)][string]$PoCPS1 + ) + + $Command = "$PoCPS1 query INSTALL.Xilinx.ISE:BinaryDirectory" + $Result = Invoke-Expression $Command + if (($LastExitCode -ne 0) -or ($Result -eq "")) + { Write-Host "[ERROR]: Cannot get Xilinx ISE installation directory." -ForegroundColor Red + Write-Host " $Result" -ForegroundColor Yellow + Write-Host "Run 'poc.ps1 configure' to configure your Xilinx ISE installation." -ForegroundColor Yellow + Exit-PrecompileScript -1 + } + return $Result.Replace("/", "\") +} + +function Get-VivadoInstallationDirectory +{ <# + .SYNOPSIS + Undocumented + + .DESCRIPTION + Undocumented + + .PARAMETER PoCPS1 + PoC's front-end script + #> + [CmdletBinding()] + param( + [Parameter(Mandatory=$true)][string]$PoCPS1 + ) + + $Command = "$PoCPS1 query INSTALL.Xilinx.Vivado:InstallationDirectory" + $Result = Invoke-Expression $Command + if (($LastExitCode -ne 0) -or ($Result -eq "")) + { Write-Host "[ERROR]: Cannot get Xilinx Vivado installation directory." -ForegroundColor Red + Write-Host " $Result" -ForegroundColor Yellow + Write-Host "Run 'poc.ps1 configure' to configure your Xilinx Vivado installation." -ForegroundColor Yellow + Exit-PrecompileScript -1 + } + return $Result.Replace("/", "\") +} + +function Get-VivadoBinaryDirectory +{ <# + .SYNOPSIS + Undocumented + + .DESCRIPTION + Undocumented + + .PARAMETER PoCPS1 + PoC's front-end script + #> + [CmdletBinding()] + param( + [Parameter(Mandatory=$true)][string]$PoCPS1 + ) + + $Command = "$PoCPS1 query INSTALL.Xilinx.Vivado:BinaryDirectory" + $Result = Invoke-Expression $Command + if (($LastExitCode -ne 0) -or ($Result -eq "")) + { Write-Host "[ERROR]: Cannot get Xilinx Vivado installation directory." -ForegroundColor Red + Write-Host " $Result" -ForegroundColor Yellow + Write-Host "Run 'poc.ps1 configure' to configure your Xilinx Vivado installation." -ForegroundColor Yellow + Exit-PrecompileScript -1 + } + return $Result.Replace("/", "\") +} + + +function Initialize-DestinationDirectory +{ <# + .SYNOPSIS + Undocumented + + .DESCRIPTION + Undocumented + + .PARAMETER PoCPS1 + PoC's front-end script + #> + [CmdletBinding()] + param( + [string]$DestinationDirectory + ) + + if (-not (Test-Path $DestinationDirectory -PathType Container)) + { mkdir $DestinationDirectory -ErrorAction SilentlyContinue | Out-Null + if (-not $?) + { Write-Host "[ERROR]: Cannot create output directory '$DestinationDirectory'." -ForegroundColor Red + Exit-PrecompileScript -1 + } + } + cd $DestinationDirectory + if (-not $?) + { Write-Host "[ERROR]: Cannot change to output directory '$DestinationDirectory'." -ForegroundColor Red + Exit-PrecompileScript -1 + } +} + +function New-ModelSim_ini +{ <# + .SYNOPSIS + Undocumented + + .DESCRIPTION + Undocumented + #> + $ModelSim_ini = "modelsim.ini" + "[Library]" | Out-File $ModelSim_ini -Encoding ascii + if (-not $?) + { Write-Host "[ERROR]: Cannot create initial modelsim.ini." -ForegroundColor Red + Exit-PrecompileScript -1 + } + if (Test-Path "..\modelsim.ini") + { "others = ../modelsim.ini" | Out-File $ModelSim_ini -Append -Encoding ascii } +} + +function Open-ISEEnvironment +{ <# + .SYNOPSIS + Undocumented + + .DESCRIPTION + Undocumented + + .PARAMETER PoCPS1 + PoC's front-end script + #> + [CmdletBinding()] + param( + [Parameter(Mandatory=$true)][string]$PoCPS1 + ) + + # load Xilinx ISE environment if not loaded before + if (-not (Test-Path env:XILINX)) + { $Command = "$PoCPS1 query Xilinx.ISE:SettingsFile" + $ISE_SettingsFile = Invoke-Expression $Command + if (($LastExitCode -ne 0) -or ($ISE_SettingsFile -eq "")) + { Write-Host "[ERROR]: Cannot get Xilinx ISE settings file." -ForegroundColor Red + Write-Host " $ISE_SettingsFile" -ForegroundColor Yellow + Write-Host "Run 'poc.ps1 configure' to configure your Xilinx ISE installation." -ForegroundColor Yellow + Exit-PrecompileScript -1 + } + + if (-not (Test-Path $ISE_SettingsFile -PathType Leaf)) + { Write-Host "[ERROR]: Xilinx ISE is configured in PoC, but settings file '$ISE_SettingsFile' does not exist." -ForegroundColor Red + Write-Host "Run 'poc.ps1 configure' to configure your Xilinx ISE installation." -ForegroundColor Red + Exit-PrecompileScript -1 + } + elseif (($ISE_SettingsFile -like "*.bat") -or ($ISE_SettingsFile -like "*.cmd")) + { Write-Host "Loading Xilinx ISE environment '$ISE_SettingsFile'" -ForegroundColor Yellow + if (-not (Get-Module -ListAvailable PSCX)) + { Write-Host "ERROR: PowerShell Community Extensions (PSCX) is not installed." -ForegroundColor Red + Exit-PrecompileScript -1 + } + Import-Module PSCX + Invoke-BatchFile -path $ISE_SettingsFile + + if (-not (Test-Path env:XILINX)) + { Write-Host "[ERROR]: No Xilinx ISE environment loaded." -ForegroundColor Red + Exit-PrecompileScript -1 + } + return + } + else + { Write-Host "[ERROR]: Xilinx ISE is configured in PoC, but settings file format is not supported." -ForegroundColor Red + Exit-PrecompileScript -1 + } + } +} + +function Close-ISEEnvironment +{ <# + .SYNOPSIS + Undocumented + + .DESCRIPTION + Undocumented + #> + + Write-Host "Unloading Xilinx ISE environment..." -ForegroundColor Yellow + $env:XILINX = $null + $env:XILINX_EDK = $null + $env:XILINX_PLANAHEAD = $null + $env:XILINX_DSP = $null +} + +function Open-VivadoEnvironment +{ <# + .SYNOPSIS + Undocumented + + .DESCRIPTION + Undocumented + + .PARAMETER PoCPS1 + PoC's front-end script + #> + [CmdletBinding()] + param( + [Parameter(Mandatory=$true)][string]$PoCPS1 + ) + + # load Xilinx Vivado environment if not loaded before + if (-not (Test-Path env:XILINX_VIVADO)) + { $Command = "$PoCPS1 query Xilinx.Vivado:SettingsFile" + $Vivado_SettingsFile = Invoke-Expression $Command + if (($LastExitCode -ne 0) -or ($Vivado_SettingsFile -eq "")) + { Write-Host "[ERROR]: Cannot get Xilinx Vivado settings file." -ForegroundColor Red + Write-Host " $Vivado_SettingsFile" -ForegroundColor Yellow + Write-Host "Run 'poc.ps1 configure' to configure your Xilinx Vivado installation." -ForegroundColor Yellow + Exit-PrecompileScript -1 + } + + if (-not (Test-Path $Vivado_SettingsFile -PathType Leaf)) + { Write-Host "[ERROR]: Xilinx Vivado is configured in PoC, but settings file '$Vivado_SettingsFile' does not exist." -ForegroundColor Red + Write-Host "Run 'poc.ps1 configure' to configure your Xilinx Vivado installation." -ForegroundColor Red + Exit-PrecompileScript -1 + } + elseif (($Vivado_SettingsFile -like "*.bat") -or ($Vivado_SettingsFile -like "*.cmd")) + { Write-Host "Loading Xilinx Vivado environment '$Vivado_SettingsFile'" -ForegroundColor Yellow + if (-not (Get-Module -ListAvailable PSCX)) + { Write-Host "ERROR: PowerShell Community Extensions (PSCX) is not installed." -ForegroundColor Red + Exit-PrecompileScript -1 + } + Import-Module PSCX + Invoke-BatchFile -path $Vivado_SettingsFile + + if (-not (Test-Path env:XILINX_VIVADO)) + { Write-Host "[ERROR]: No Xilinx Vivado environment loaded." -ForegroundColor Red + Exit-PrecompileScript -1 + } + return + } + else + { Write-Host "[ERROR]: Xilinx Vivado is configured in PoC, but settings file format is not supported." -ForegroundColor Red + Exit-PrecompileScript -1 + } + } +} + +function Close-VivadoEnvironment +{ <# + .SYNOPSIS + Undocumented + + .DESCRIPTION + Undocumented + #> + + Write-Host "Unloading Xilinx Vivado environment..." -ForegroundColor Yellow + $env:XILINX_VIVADO = $null +} + +function Restore-NativeCommandStream +{ <# + .SYNOPSIS + This CmdLet gathers multiple ErrorRecord objects and reconstructs outputs + as a single line. + + .DESCRIPTION + This CmdLet collects multiple ErrorRecord objects and emits one string + object per line. + + .PARAMETER InputObject + A object stream is required as an input. + #> + [CmdletBinding()] + param( + [Parameter(ValueFromPipeline=$true)] + $InputObject + ) + + begin + { $LineRemainer = "" } + + process + { if (-not $InputObject) + { Write-Host "Empty pipeline!" } + elseif ($InputObject -is [System.Management.Automation.ErrorRecord]) + { if ($InputObject.FullyQualifiedErrorId -eq "NativeCommandError") + { Write-Output $InputObject.Tostring() } + elseif ($InputObject.FullyQualifiedErrorId -eq "NativeCommandErrorMessage") + { $NewLine = $LineRemainer + $InputObject.Tostring() + while (($NewLinePos = $NewLine.IndexOf("`n")) -ne -1) + { Write-Output $NewLine.Substring(0, $NewLinePos) + $NewLine = $NewLine.Substring($NewLinePos + 1) + } + $LineRemainer = $NewLine + } + } + elseif ($InputObject -is [string]) + { Write-Output $InputObject } + else + { Write-Host "Unsupported object in pipeline stream" } + } + + end + { if ($LineRemainer -ne "") + { Write-Output $LineRemainer } + } +} + +function Write-ColoredGHDLLine +{ <# + .SYNOPSIS + This CmdLet colors GHDL output lines. + + .DESCRIPTION + This CmdLet colors GHDL output lines. Warnings are prefixed with 'WARNING: ' + in yellow and errors are prefixed with 'ERROR: ' in red. + + .PARAMETER InputObject + A object stream is required as an input. + + .PARAMETER SuppressWarnings + Skip warning messages. (Show errors only.) + #> + [CmdletBinding()] + param( + [Parameter(ValueFromPipeline=$true)] + $InputObject, + + [Parameter(Position=1)] + [switch]$SuppressWarnings = $false + ) + + begin + { $ErrorRecordFound = $false } + + process + { if (-not $InputObject) + { Write-Host "Empty pipeline!" } + elseif ($InputObject -is [string]) + { if ($InputObject.Contains("warning")) + { if (-not $SuppressWarnings) + { Write-Host "WARNING: " -NoNewline -ForegroundColor Yellow + Write-Host $InputObject + } + } + else + { $ErrorRecordFound = $true + Write-Host "ERROR: " -NoNewline -ForegroundColor Red + Write-Host $InputObject + } + } + else + { Write-Host "Unsupported object in pipeline stream" } + } + + end + { $ErrorRecordFound } +} + +function Write-ColoredActiveHDLLine +{ <# + .SYNOPSIS + This CmdLet colors GHDL output lines. + + .DESCRIPTION + This CmdLet colors GHDL output lines. Warnings are prefixed with 'WARNING: ' + in yellow and errors are prefixed with 'ERROR: ' in red. + + .PARAMETER InputObject + A object stream is required as an input. + + .PARAMETER SuppressWarnings + Skip warning messages. (Show errors only.) + #> + [CmdletBinding()] + param( + [Parameter(ValueFromPipeline=$true)] + $InputObject, + + [Parameter(Position=1)] + [switch]$SuppressWarnings = $false + ) + + begin + { $ErrorRecordFound = $false } + + process + { if (-not $InputObject) + { Write-Host "Empty pipeline!" } + elseif ($InputObject -is [string]) + { if ($InputObject.Contains("WARNING")) + { if (-not $SuppressWarnings) + { Write-Host "WARNING: " -NoNewline -ForegroundColor Yellow + Write-Host $InputObject + } + } + elseif ($InputObject.Contains("ERROR")) + { if (-not $SuppressWarnings) + { Write-Host "ERROR: " -NoNewline -ForegroundColor Red + Write-Host $InputObject + } + } + else + { $ErrorRecordFound = $true + Write-Host $InputObject + } + } + else + { Write-Host "Unsupported object in pipeline stream" } + } + + end + { $ErrorRecordFound } +} + +Export-ModuleMember -Function 'Exit-PrecompileScript' + +Export-ModuleMember -Function 'Resolve-Simulator' +Export-ModuleMember -Function 'Resolve-VHDLVersion' + +# Directory names +Export-ModuleMember -Function 'Get-PrecompiledDirectoryName' +Export-ModuleMember -Function 'Get-AlteraDirectoryName' +Export-ModuleMember -Function 'Get-GHDLDirectoryName' +Export-ModuleMember -Function 'Get-LatticeDirectoryName' +Export-ModuleMember -Function 'Get-QuestaSimDirectoryName' +Export-ModuleMember -Function 'Get-XilinxDirectoryName' + +# Tool directories +Export-ModuleMember -Function 'Get-QuartusInstallationDirectory' +Export-ModuleMember -Function 'Get-QuartusBinaryDirectory' +Export-ModuleMember -Function 'Get-DiamondInstallationDirectory' +Export-ModuleMember -Function 'Get-DiamondBinaryDirectory' +Export-ModuleMember -Function 'Get-GHDLBinaryDirectory' +Export-ModuleMember -Function 'Get-GHDLScriptDirectory' +Export-ModuleMember -Function 'Get-ModelSimBinaryDirectory' +Export-ModuleMember -Function 'Get-ISEInstallationDirectory' +Export-ModuleMember -Function 'Get-ISEBinaryDirectory' +Export-ModuleMember -Function 'Get-VivadoInstallationDirectory' +Export-ModuleMember -Function 'Get-VivadoBinaryDirectory' + +Export-ModuleMember -Function 'Initialize-DestinationDirectory' + +Export-ModuleMember -Function 'New-ModelSim_ini' + +Export-ModuleMember -Function 'Open-ISEEnvironment' +Export-ModuleMember -Function 'Close-ISEEnvironment' +Export-ModuleMember -Function 'Open-VivadoEnvironment' +Export-ModuleMember -Function 'Close-VivadoEnvironment' + +Export-ModuleMember -Function 'Restore-NativeCommandStream' +Export-ModuleMember -Function 'Write-ColoredGHDLLine' +Export-ModuleMember -Function 'Write-ColoredActiveHDLLine' diff --git a/tools/precompile/shared.sh b/tools/precompile/shared.sh new file mode 100644 index 00000000..f73bbbd4 --- /dev/null +++ b/tools/precompile/shared.sh @@ -0,0 +1,153 @@ +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# +# ============================================================================== +# Authors: Patrick Lehmann +# Martin Zabel +# +# Bash include file: Common constants and functions for all compile scripts. +# +# Description: +# ------------------------------------ +# +# +# License: +# ============================================================================== +# Copyright 2007-2016 Technische Universitaet Dresden - Germany +# Chair for VLSI-Design, Diagnostics and Architecture +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================== + +ANSI_RED="\e[31m" +ANSI_GREEN="\e[32m" +ANSI_YELLOW="\e[33m" +ANSI_BLUE="\e[34m" +ANSI_MAGENTA="\e[35m" +ANSI_CYAN="\e[36;1m" +ANSI_DARKCYAN="\e[36m" +ANSI_NOCOLOR="\e[0m" + +# red texts +COLORED_ERROR="${ANSI_RED}[ERROR]" +COLORED_MESSAGE="${ANSI_YELLOW} " +COLORED_FAILED="${ANSI_RED}[FAILED]${ANSI_NOCOLOR}" + +# green texts +COLORED_DONE="${ANSI_GREEN}[DONE]${ANSI_NOCOLOR}" +COLORED_SUCCESSFUL="${ANSI_GREEN}[SUCCESSFUL]${ANSI_NOCOLOR}" + + +# set bash options +set -o pipefail + + +# -> $SUPPRESS_WARNINGS +# <= $GRC_COMMAND +SetupGRCat() { + if [ -z "$(which grcat 2>/dev/null)" ]; then + # if grcat (generic colourizer) is not installed, use a dummy pipe command like 'cat' + GRC_COMMAND="cat" + elif [ $SUPPRESS_WARNINGS -eq 1 ]; then + GRC_COMMAND="grcat $ScriptDir/ghdl.skipwarning.grcrules" + else + GRC_COMMAND="grcat $ScriptDir/ghdl.grcrules" + fi +} + +CreateDestinationDirectory() { + DestinationDirectory=$1 + + mkdir -p $DestinationDirectory + if [ $? -ne 0 ]; then + echo 1>&2 -e "${COLORED_ERROR} Cannot create output directory '$DestinationDirectory'.${ANSI_NOCOLOR}" + exit -1; + fi + cd $DestinationDirectory + if [ $? -ne 0 ]; then + echo 1>&2 -e "${COLORED_ERROR} Cannot change to output directory '$DestinationDirectory'.${ANSI_NOCOLOR}" + exit -1; + fi +} + +# GetGHDLDirectories +# -> $PoC_sh +# <= $GHDLBinDir +# <= $GHDLScriptDir +# <= $GHDLDirName +GetGHDLDirectories() { + PoC_sh=$1 + + # Get GHDL binary directory + GHDLBinDir=$($PoC_sh query INSTALL.GHDL:BinaryDirectory 2>/dev/null) # Path to the simulators bin directory + if [ $? -ne 0 ]; then + echo 1>&2 -e "${COLORED_ERROR} Cannot get GHDL binary directory.${ANSI_NOCOLOR}" + echo 1>&2 -e "${COLORED_MESSAGE} $GHDLBinDir${ANSI_NOCOLOR}" + echo 1>&2 -e "${ANSI_YELLOW}Run 'poc.sh configure' to configure your GHDL installation.${ANSI_NOCOLOR}" + exit -1; + fi + + # Get GHDL script directory + GHDLScriptDir=$($PoC_sh query INSTALL.GHDL:ScriptDirectory 2>/dev/null) # Path to the simulators bin directory + if [ $? -ne 0 ]; then + echo 1>&2 -e "${COLORED_ERROR} Cannot get GHDL vendor script directory.${ANSI_NOCOLOR}" + echo 1>&2 -e "${COLORED_MESSAGE} $GHDLScriptDir${ANSI_NOCOLOR}" + echo 1>&2 -e "${ANSI_YELLOW}Run 'poc.sh configure' to configure your GHDL installation.${ANSI_NOCOLOR}" + exit -1; + fi + + # + GHDLDirName=$($PoC_sh query CONFIG.DirectoryNames:GHDLFiles 2>/dev/null) + if [ $? -ne 0 ]; then + echo 1>&2 -e "${COLORED_ERROR} Cannot get GHDL directory name.${ANSI_NOCOLOR}" + echo 1>&2 -e "${COLORED_MESSAGE} $GHDLDirName${ANSI_NOCOLOR}" + exit -1; + fi +} + +# GetVSimDirectories +# -> $PoC_sh +# <= $VSimBinDir +# <= $VSimDirName +GetVSimDirectories() { + # Get QuestaSim/ModelSim binary + VSimBinDir=$($PoC_sh query ModelSim:BinaryDirectory 2>/dev/null) # Path to the simulators bin directory + if [ $? -ne 0 ]; then + echo 1>&2 -e "${COLORED_ERROR} Cannot get QuestaSim/ModelSim binary directory.${ANSI_NOCOLOR}" + echo 1>&2 -e "${COLORED_MESSAGE} $VSimBinDir${ANSI_NOCOLOR}" + echo 1>&2 -e "${ANSI_YELLOW}Run 'poc.sh configure' to configure your Mentor QuestaSim/ModelSim installation.${ANSI_NOCOLOR}" + exit -1; + fi + + VSimDirName=$($PoC_sh query CONFIG.DirectoryNames:QuestaSimFiles 2>/dev/null) + if [ $? -ne 0 ]; then + echo 1>&2 -e "${COLORED_ERROR} Cannot get QuestaSim directory name.${ANSI_NOCOLOR}" + echo 1>&2 -e "${COLORED_MESSAGE} $VSimDirName${ANSI_NOCOLOR}" + exit -1; + fi +} + +CreateLocalModelsim_ini() { + # create an empty modelsim.ini in the altera directory + echo "[Library]" > modelsim.ini + if [ $? -ne 0 ]; then + echo 1>&2 -e "${COLORED_ERROR} Cannot create initial modelsim.ini.${ANSI_NOCOLOR}" + exit -1; + fi + # add reference to parent modelsim.ini + if [ -e "../modelsim.ini" ]; then + echo "others = ../modelsim.ini" >> modelsim.ini + fi +} + diff --git a/ucf/Atlys/Clock.SystemClock.ucf b/ucf/Atlys/Clock.SystemClock.ucf index 2f6756ea..68a5e3d1 100644 --- a/ucf/Atlys/Clock.SystemClock.ucf +++ b/ucf/Atlys/Clock.SystemClock.ucf @@ -12,6 +12,6 @@ ## Frequency: 100 MHz, 100ppm NET "Atlys_SystemClock_100MHz" LOC = "L15"; ## {IN} IC12.3 NET "Atlys_SystemClock_100MHz" IOSTANDARD = LVCMOS33; -NET "Atlys_SystemClock_100MHz" TNM_NET = "NET_SystemClock_100MHz"; +NET "Atlys_SystemClock_100MHz" TNM_NET = "PIN_SystemClock_100MHz"; -TIMESPEC "TS_SystemClock" = PERIOD "NET_SystemClock_100MHz" 100 MHz HIGH 50 %; # 100 MHz oscillator (50%/50% duty-cycle) +TIMESPEC "TS_SystemClock" = PERIOD "PIN_SystemClock_100MHz" 100 MHz HIGH 50 %; # 100 MHz oscillator (50%/50% duty-cycle) diff --git a/ucf/Atlys/Default.ucf b/ucf/Atlys/Default.ucf index 4d54de06..abfbd0fe 100644 --- a/ucf/Atlys/Default.ucf +++ b/ucf/Atlys/Default.ucf @@ -6,7 +6,7 @@ ## Device: XC6SLX45 ## Package: CSG324 ## Speedgrade: -3 -## +## ## Notes: ## VCCB2 (Bank2) is defaulted to 2.5V (choices: 2.5V, 3.3V) by jumper JP12 ## diff --git a/ucf/Atlys/GPIO.Button.Special.ucf b/ucf/Atlys/GPIO.Button.Special.ucf index aba7b044..3ee961a8 100644 --- a/ucf/Atlys/GPIO.Button.Special.ucf +++ b/ucf/Atlys/GPIO.Button.Special.ucf @@ -4,7 +4,7 @@ ## ## Special Buttons ## ----------------------------------------------------------------------------- -## Bank: +## Bank: ## VCCO: 3.3V (VCC3V3) ## Location: BTN1 ## ----------------------------------------------------------------------------- diff --git a/ucf/Atlys/HDMI.RX.ucf b/ucf/Atlys/HDMI.RX.ucf index a94b7f99..e186df6e 100644 --- a/ucf/Atlys/HDMI.RX.ucf +++ b/ucf/Atlys/HDMI.RX.ucf @@ -7,19 +7,19 @@ ## Vendor: Texas Instruments ## Device: TMDS141RHAR ## ----------------------------------------------------------------------------- -NET "Atlys_TMDS_RX_Clock_p" LOC = "H17" ## {IN} -NET "Atlys_TMDS_RX_Clock_n" LOC = "H18" ## {IN} -NET "Atlys_TMDS_RX_0_p" LOC = "K17" ## {IN} -NET "Atlys_TMDS_RX_0_n" LOC = "K18" ## {IN} -NET "Atlys_TMDS_RX_1_p" LOC = "L17" ## {IN} -NET "Atlys_TMDS_RX_1_n" LOC = "L18" ## {IN} -NET "Atlys_TMDS_RX_2_p" LOC = "J16" ## {IN} -NET "Atlys_TMDS_RX_2_n" LOC = "J18" ## {IN} +NET "Atlys_TMDS_RX_Clock_p" LOC = "H17" ## {IN} +NET "Atlys_TMDS_RX_Clock_n" LOC = "H18" ## {IN} +NET "Atlys_TMDS_RX_0_p" LOC = "K17" ## {IN} +NET "Atlys_TMDS_RX_0_n" LOC = "K18" ## {IN} +NET "Atlys_TMDS_RX_1_p" LOC = "L17" ## {IN} +NET "Atlys_TMDS_RX_1_n" LOC = "L18" ## {IN} +NET "Atlys_TMDS_RX_2_p" LOC = "J16" ## {IN} +NET "Atlys_TMDS_RX_2_n" LOC = "J18" ## {IN} NET "Atlys_TMDS_RX_*_?" IOSTANDARD = LVCMOS33; NET "Atlys_TMDS_RX_*_?" SLEW = FAST; -NET "Atlys_TMDS_RX_SerialClock" LOC = "M16" ## {INOUT} -NET "Atlys_TMDS_RX_SerialData" LOC = "M18" ## {INOUT} +NET "Atlys_TMDS_RX_SerialClock" LOC = "M16" ## {INOUT} +NET "Atlys_TMDS_RX_SerialData" LOC = "M18" ## {INOUT} NET "Atlys_TMDS_RX_Serial*" IOSTANDARD = LVCMOS33; NET "Atlys_TMDS_RX_Serial*" SLEW = FAST; diff --git a/ucf/Atlys/HDMI.TX.ucf b/ucf/Atlys/HDMI.TX.ucf index fc46ed4f..4721b2cf 100644 --- a/ucf/Atlys/HDMI.TX.ucf +++ b/ucf/Atlys/HDMI.TX.ucf @@ -7,19 +7,19 @@ ## Vendor: Texas Instruments ## Device: TMDS141RHAR ## ----------------------------------------------------------------------------- -NET "Atlys_TMDS_TX_Clock_p" LOC = "B6" ## {OUT} -NET "Atlys_TMDS_TX_Clock_n" LOC = "A6" ## {OUT} -NET "Atlys_TMDS_TX_0_p" LOC = "D8" ## {OUT} -NET "Atlys_TMDS_TX_0_n" LOC = "C8" ## {OUT} -NET "Atlys_TMDS_TX_1_p" LOC = "C7" ## {OUT} -NET "Atlys_TMDS_TX_1_n" LOC = "A7" ## {OUT} -NET "Atlys_TMDS_TX_2_p" LOC = "B8" ## {OUT} -NET "Atlys_TMDS_TX_2_n" LOC = "A8" ## {OUT} +NET "Atlys_TMDS_TX_Clock_p" LOC = "B6" ## {OUT} +NET "Atlys_TMDS_TX_Clock_n" LOC = "A6" ## {OUT} +NET "Atlys_TMDS_TX_0_p" LOC = "D8" ## {OUT} +NET "Atlys_TMDS_TX_0_n" LOC = "C8" ## {OUT} +NET "Atlys_TMDS_TX_1_p" LOC = "C7" ## {OUT} +NET "Atlys_TMDS_TX_1_n" LOC = "A7" ## {OUT} +NET "Atlys_TMDS_TX_2_p" LOC = "B8" ## {OUT} +NET "Atlys_TMDS_TX_2_n" LOC = "A8" ## {OUT} NET "Atlys_TMDS_TX_*_?" IOSTANDARD = LVCMOS33; NET "Atlys_TMDS_TX_*_?" SLEW = FAST; -NET "Atlys_TMDS_TX_SerialClock" LOC = "D9" ## {INOUT} -NET "Atlys_TMDS_TX_SerialData" LOC = "C9" ## {INOUT} +NET "Atlys_TMDS_TX_SerialClock" LOC = "D9" ## {INOUT} +NET "Atlys_TMDS_TX_SerialData" LOC = "C9" ## {INOUT} NET "Atlys_TMDS_TX_Serial*" IOSTANDARD = LVCMOS33; NET "Atlys_TMDS_TX_Serial*" SLEW = FAST; diff --git a/ucf/DE4/Bus.IIC.EEPROM.sdc b/ucf/DE4/Bus.IIC.EEPROM.sdc index 3637f0cb..e6300f37 100644 --- a/ucf/DE4/Bus.IIC.EEPROM.sdc +++ b/ucf/DE4/Bus.IIC.EEPROM.sdc @@ -1,11 +1,11 @@ ## ============================================================================= ## I2C bus to EEPROM ## ============================================================================= -## Bank: -## VCCO: -## Location: -## Vendor: -## Device: +## Bank: +## VCCO: +## Location: +## Vendor: +## Device: ## ============================================================================= if {$TimingConstraints == 0} then { # is it possible to define pin and I/O standard constraints here? diff --git a/ucf/DE4/Bus.SMBus.sdc b/ucf/DE4/Bus.SMBus.sdc index 762a8186..5e2cd285 100644 --- a/ucf/DE4/Bus.SMBus.sdc +++ b/ucf/DE4/Bus.SMBus.sdc @@ -1,11 +1,11 @@ ## ============================================================================= ## System Management Bus (SMBus) ## ============================================================================= -## Bank: -## VCCO: -## Location: -## Vendor: -## Device: +## Bank: +## VCCO: +## Location: +## Vendor: +## Device: ## ============================================================================= if {$TimingConstraints == 0} then { # is it possible to define pin and I/O standard constraints here? diff --git a/ucf/DE4/Clock.SystemClock.sdc b/ucf/DE4/Clock.SystemClock.sdc index e785b9ca..5c2070b2 100644 --- a/ucf/DE4/Clock.SystemClock.sdc +++ b/ucf/DE4/Clock.SystemClock.sdc @@ -4,15 +4,15 @@ ## ## System Clock ## ============================================================================= -## Bank: -## VCCO: -## Location: -## Vendor: -## Device: +## Bank: +## VCCO: +## Location: +## Vendor: +## Device: ## Frequency: 100 MHz if {$TimingConstraints == 0} then { # is it possible to define pin and I/O standard constraints here? } else { ## specify a 100 MHz clock - create_clock -name NET_SystemClock_100MHz -period 10.000 -waveform {0.000 5.000} [get_ports DE4_SystemClock_100MHz] + create_clock -name PIN_SystemClock_100MHz -period 10.000 -waveform {0.000 5.000} [get_ports DE4_SystemClock_100MHz] } diff --git a/ucf/DE4/GPIO.Button.Special.sdc b/ucf/DE4/GPIO.Button.Special.sdc index 1a49c29b..84bc11f6 100644 --- a/ucf/DE4/GPIO.Button.Special.sdc +++ b/ucf/DE4/GPIO.Button.Special.sdc @@ -4,9 +4,9 @@ ## ## Special Buttons ## ============================================================================= -## Bank: -## VCCO: -## Location: +## Bank: +## VCCO: +## Location: ## ----------------------------------------------------------------------------- if {$TimingConstraints == 0} then { # is it possible to define pin and I/O standard constraints here? diff --git a/ucf/DE4/GPIO.Button.sdc b/ucf/DE4/GPIO.Button.sdc index 5e79062c..af5eb60b 100644 --- a/ucf/DE4/GPIO.Button.sdc +++ b/ucf/DE4/GPIO.Button.sdc @@ -4,9 +4,9 @@ ## ## Cursor Buttons ## ============================================================================= -## Bank: -## VCCO: -## Location: +## Bank: +## VCCO: +## Location: ## ----------------------------------------------------------------------------- if {$TimingConstraints == 0} then { # is it possible to define pin and I/O standard constraints here? diff --git a/ucf/DE4/GPIO.DipSwitch.sdc b/ucf/DE4/GPIO.DipSwitch.sdc index c338c0d7..f5d07b45 100644 --- a/ucf/DE4/GPIO.DipSwitch.sdc +++ b/ucf/DE4/GPIO.DipSwitch.sdc @@ -4,9 +4,9 @@ ## ## DIP-Switches ## ============================================================================= -## Bank: -## VCCO: -## Location: +## Bank: +## VCCO: +## Location: ## ----------------------------------------------------------------------------- if {$TimingConstraints == 0} then { # is it possible to define pin and I/O standard constraints here? diff --git a/ucf/DE4/GPIO.LED.sdc b/ucf/DE4/GPIO.LED.sdc index ea3323b9..ae6b3e54 100644 --- a/ucf/DE4/GPIO.LED.sdc +++ b/ucf/DE4/GPIO.LED.sdc @@ -1,13 +1,13 @@ ## ## LEDs ## ============================================================================= -## Bank: -## VCCO: -## Location: +## Bank: +## VCCO: +## Location: ## ----------------------------------------------------------------------------- if {$TimingConstraints == 0} then { # is it possible to define pin and I/O standard constraints here? } else { # Ignore timings on async I/O pins set_false_path -to [get_ports DE4_GPIO_LED_n*] -} \ No newline at end of file +} diff --git a/ucf/DE4/GPIO.Seg7.sdc b/ucf/DE4/GPIO.Seg7.sdc index aa42733a..c0af6c36 100644 --- a/ucf/DE4/GPIO.Seg7.sdc +++ b/ucf/DE4/GPIO.Seg7.sdc @@ -1,9 +1,9 @@ ## ## LEDs ## ============================================================================= -## Bank: -## VCCO: -## Location: +## Bank: +## VCCO: +## Location: ## ----------------------------------------------------------------------------- if {$TimingConstraints == 0} then { # is it possible to define pin and I/O standard constraints here? diff --git a/ucf/DE4/GPIO.SlideSwitch.sdc b/ucf/DE4/GPIO.SlideSwitch.sdc index 4a8b60d1..f0caee68 100644 --- a/ucf/DE4/GPIO.SlideSwitch.sdc +++ b/ucf/DE4/GPIO.SlideSwitch.sdc @@ -4,9 +4,9 @@ ## ## DIP-Switches ## ============================================================================= -## Bank: -## VCCO: -## Location: +## Bank: +## VCCO: +## Location: ## ----------------------------------------------------------------------------- if {$TimingConstraints == 0} then { # is it possible to define pin and I/O standard constraints here? diff --git a/ucf/DE4/UART.sdc b/ucf/DE4/UART.sdc index 6a450aa3..5724e4b9 100644 --- a/ucf/DE4/UART.sdc +++ b/ucf/DE4/UART.sdc @@ -1,11 +1,11 @@ ## ============================================================================= ## UART (RS232) ## ============================================================================= -## Bank: -## VCCO: -## Location: -## Vendor: -## Device: +## Bank: +## VCCO: +## Location: +## Vendor: +## Device: ## ============================================================================= if {$TimingConstraints == 0} then { # is it possible to define pin and I/O standard constraints here? diff --git a/ucf/KC705/Bus.IIC.ucf b/ucf/KC705/Bus.IIC.ucf index 18a62dfb..bf2ee1b1 100644 --- a/ucf/KC705/Bus.IIC.ucf +++ b/ucf/KC705/Bus.IIC.ucf @@ -15,24 +15,24 @@ ## Device: Si570 ## Address: 0xBA (1011 101xb) ## Channel 1: FMC Connector 1 (HPC) -## Location: +## Location: ## Channel 2: FMC Connector 2 (LPC) -## Location: +## Location: ## Channel 3: EEPROM -## Location: -## Vendor: -## Device: +## Location: +## Vendor: +## Device: ## Address: 0xA8 (1010 100xb) ## Channel 4: SFP cage ## Location: P5 ## Address: 0xA0 (1010 000xb) ## Channel 5: HDMI -## Location: -## Vendor: -## Device: +## Location: +## Vendor: +## Device: ## Address: 0x72 (0111 001xb) ## Channel 6: DDR3 -## Location: +## Location: ## Address: 0xA0, 0x30 (1010 000xb, 0011 000xb) ## Channel 7: SI5324 ## Location: U70 (SI5324-C-GM) diff --git a/ucf/KC705/Bus.IIC.xdc b/ucf/KC705/Bus.IIC.xdc index 01c07e2e..43ae679d 100644 --- a/ucf/KC705/Bus.IIC.xdc +++ b/ucf/KC705/Bus.IIC.xdc @@ -15,24 +15,24 @@ ## Device: Si570 ## Address: 0xBA (1011 101xb) ## Channel 1: FMC Connector 1 (HPC) -## Location: +## Location: ## Channel 2: FMC Connector 2 (LPC) -## Location: +## Location: ## Channel 3: EEPROM -## Location: -## Vendor: -## Device: +## Location: +## Vendor: +## Device: ## Address: 0xA8 (1010 100xb) ## Channel 4: SFP cage ## Location: P5 ## Address: 0xA0 (1010 000xb) ## Channel 5: HDMI -## Location: -## Vendor: -## Device: +## Location: +## Vendor: +## Device: ## Address: 0x72 (0111 001xb) ## Channel 6: DDR3 -## Location: +## Location: ## Address: 0xA0, 0x30 (1010 000xb, 0011 000xb) ## Channel 7: SI5324 ## Location: U70 (SI5324-C-GM) diff --git a/ucf/KC705/Bus.PMBus.ucf b/ucf/KC705/Bus.PMBus.ucf index 00c5f9c6..e37a1966 100644 --- a/ucf/KC705/Bus.PMBus.ucf +++ b/ucf/KC705/Bus.PMBus.ucf @@ -3,12 +3,12 @@ ## ----------------------------------------------------------------------------- #$ ## Bank: 15 #$ ## VCCO: 1,8V (VCC1V8_FPGA) -#$ ## Location: -#$ ## Vendor: -#$ ## Device: -#$ ##NET "KC705_PMBus_Clock" LOC = "AW37" | IOSTANDARD = LVCMOS18; ## -#$ ##NET "KC705_PMBus_Data" LOC = "AY39" | IOSTANDARD = LVCMOS18; ## -#$ ##NET "KC705_PMBus_Alert" LOC = "AV38" | IOSTANDARD = LVCMOS18; ## +#$ ## Location: +#$ ## Vendor: +#$ ## Device: +#$ ##NET "KC705_PMBus_Clock" LOC = "AW37" | IOSTANDARD = LVCMOS18; ## +#$ ##NET "KC705_PMBus_Data" LOC = "AY39" | IOSTANDARD = LVCMOS18; ## +#$ ##NET "KC705_PMBus_Alert" LOC = "AV38" | IOSTANDARD = LVCMOS18; ## ## Ignore timings on async I/O pins #$ NET "KC705_LCD_*" TIG; diff --git a/ucf/KC705/Clock.ProgUserClock.ucf b/ucf/KC705/Clock.ProgUserClock.ucf index 980459ce..a4faacd8 100644 --- a/ucf/KC705/Clock.ProgUserClock.ucf +++ b/ucf/KC705/Clock.ProgUserClock.ucf @@ -6,7 +6,7 @@ ## Device: XC7K325T ## Package: FFG900 ## Speedgrade: -2 -## +## ## Notes: ## Power Rail 4 driving VADJ_FPGA is defaulted to 2.5V (choices: 1.8V, 2.5V, 3.3V) ## @@ -24,6 +24,7 @@ ## Frequency: 10 - 810 MHz, 50ppm ## Default Freq: 156.250 MHz ## I²C-Address: 0x5D #$ (0111 010xb) -NET "KC705_ProgUserClock_n" LOC = "K29" | IOSTANDARD = LVDS_25; ## {IN} U45.5 -NET "KC705_ProgUserClock_p" LOC = "K28" | IOSTANDARD = LVDS_25; ## {IN} U45.4 -NET "KC705_ProgUserClock_p" TNM_NET = "NET_ProgUserClock"; +NET "KC705_ProgUserClock_p" LOC = "K28"; ## {IN} U45.4 +NET "KC705_ProgUserClock_n" LOC = "K29"; ## {IN} U45.5 +NET "KC705_ProgUserClock_p" IOSTANDARD = LVDS_25; +NET "KC705_ProgUserClock_p" TNM_NET = "PIN_ProgUserClock"; diff --git a/ucf/KC705/Clock.ProgUserClock.xdc b/ucf/KC705/Clock.ProgUserClock.xdc index 608e8591..e1e24fff 100644 --- a/ucf/KC705/Clock.ProgUserClock.xdc +++ b/ucf/KC705/Clock.ProgUserClock.xdc @@ -6,7 +6,7 @@ ## Device: XC7K325T ## Package: FFG900 ## Speedgrade: -2 -## +## ## Notes: ## Power Rail 4 driving VADJ_FPGA is defaulted to 2.5V (choices: 1.8V, 2.5V, 3.3V) ## @@ -28,4 +28,3 @@ set_property PACKAGE_PIN K28 [get_ports KC705_ProgUserClock_p] set_property PACKAGE_PIN K29 [get_ports KC705_ProgUserClock_n] # set I/O standard set_property IOSTANDARD LVDS_25 [get_ports -regexp {KC705_ProgUserClock_[p|n]}] -#$ NET "KC705_ProgUserClock_p" TNM_NET = "NET_ProgUserClock"; diff --git a/ucf/KC705/Clock.Si5324.ucf b/ucf/KC705/Clock.Si5324.ucf index 239c8324..91275982 100644 --- a/ucf/KC705/Clock.Si5324.ucf +++ b/ucf/KC705/Clock.Si5324.ucf @@ -6,7 +6,7 @@ ## Device: XC7K325T ## Package: FFG900 ## Speedgrade: -2 -## +## ## Notes: ## Power Rail 4 driving VADJ_FPGA is defaulted to 2.5V (choices: 1.8V, 2.5V, 3.3V) ## @@ -24,7 +24,7 @@ #$ ## I²C-Address: 0xA0 (1010 000xb) #$ NET "KC705_Si5324_Alarm_n" LOC = "AU34" | IOSTANDARD = LVCMOS25; ## U24.3; level shifted by U33 (SN74AVC1T45) #$ NET "KC705_Si5324_Reset_n" LOC = "AT36" | IOSTANDARD = LVCMOS25; ## U24.1; level shifted by U39 (SN74AVC4T245) -#$ +#$ ## recovered clock output #$ NET "KC705_Si5324_ClockIn_n" LOC = "AW33" | IOSTANDARD = LVCMOS25; ## U24.17 #$ NET "KC705_Si5324_ClockIn_p" LOC = "AW32" | IOSTANDARD = LVCMOS25; ## U24.16 diff --git a/ucf/KC705/Clock.SystemClock.ucf b/ucf/KC705/Clock.SystemClock.ucf index 82d79073..14e1316c 100644 --- a/ucf/KC705/Clock.SystemClock.ucf +++ b/ucf/KC705/Clock.SystemClock.ucf @@ -6,7 +6,7 @@ ## Device: XC7K325T ## Package: FFG900 ## Speedgrade: -2 -## +## ## Notes: ## Power Rail 4 driving VADJ_FPGA is defaulted to 2.5V (choices: 1.8V, 2.5V, 3.3V) ## @@ -22,9 +22,9 @@ ## Vendor: SiTime ## Device: SIT9102AI-243N25E200.0000 - 1 to 220 MHz High Performance Oscillator ## Frequency: 200 MHz, 50ppm -NET "KC705_SystemClock_200MHz_n" LOC = "AD11"; ## {IN} U6.5 NET "KC705_SystemClock_200MHz_p" LOC = "AD12"; ## {IN} U6.4 +NET "KC705_SystemClock_200MHz_n" LOC = "AD11"; ## {IN} U6.5 NET "KC705_SystemClock_200MHz_?" IOSTANDARD = LVDS; -NET "KC705_SystemClock_200MHz_p" TNM_NET = "NET_SystemClock_200MHz"; +NET "KC705_SystemClock_200MHz_p" TNM_NET = "PIN_SystemClock_200MHz"; -TIMESPEC "TS_SystemClock" = PERIOD "NET_SystemClock_200MHz" 200 MHz HIGH 50 %; +TIMESPEC "TS_SystemClock" = PERIOD "PIN_SystemClock_200MHz" 200 MHz HIGH 50 %; diff --git a/ucf/KC705/Clock.SystemClock.xdc b/ucf/KC705/Clock.SystemClock.xdc index 46919e5a..854ba86f 100644 --- a/ucf/KC705/Clock.SystemClock.xdc +++ b/ucf/KC705/Clock.SystemClock.xdc @@ -6,7 +6,7 @@ ## Device: XC7K325T ## Package: FFG900 ## Speedgrade: -2 -## +## ## Notes: ## Power Rail 4 driving VADJ_FPGA is defaulted to 2.5V (choices: 1.8V, 2.5V, 3.3V) ## @@ -27,4 +27,4 @@ set_property PACKAGE_PIN AD11 [get_ports KC705_SystemClock_200MHz_n] # set I/O standard set_property IOSTANDARD LVDS [get_ports -regexp {KC705_SystemClock_200MHz_[p|n]}] # specify a 200 MHz clock -create_clock -period 5.000 -name NET_SystemClock_200MHz [get_ports KC705_SystemClock_200MHz_p] +create_clock -period 5.000 -name PIN_SystemClock_200MHz [get_ports KC705_SystemClock_200MHz_p] diff --git a/ucf/KC705/Default.ucf b/ucf/KC705/Default.ucf index 1b04cf19..13066d6c 100644 --- a/ucf/KC705/Default.ucf +++ b/ucf/KC705/Default.ucf @@ -6,7 +6,7 @@ ## Device: XC7K325T ## Package: FFG900 ## Speedgrade: -2 -## +## ## Notes: ## Power Rail 4 driving VADJ_FPGA is defaulted to 2.5V (choices: 1.8V, 2.5V, 3.3V) ## diff --git a/ucf/KC705/EthernetPHY.SGMII.ucf b/ucf/KC705/EthernetPHY.SGMII.ucf index a792580c..f5f26e4d 100644 --- a/ucf/KC705/EthernetPHY.SGMII.ucf +++ b/ucf/KC705/EthernetPHY.SGMII.ucf @@ -12,12 +12,12 @@ ## SGMII LVDS signal-pairs ## -------------------------- ## Bank: 117 -## Quad117: +## Quad117: ## RefClock0 SGMII RefClock (ICS844021I) ## RefClock1 KC705_SMA_RefClock ## Placement: ## Lane: Quad117.Channel1 (GTXE2_CHANNEL_X0Y9) -## ReferenceClock: +## ReferenceClock: ## RefClock: Quad117.MGTRefClock0 ## Location: U2 (ICS844021I) ## Vendor: Integrated Circuit Systems diff --git a/ucf/KC705/GPIO.SMA.ucf b/ucf/KC705/GPIO.SMA.ucf new file mode 100644 index 00000000..d838cddb --- /dev/null +++ b/ucf/KC705/GPIO.SMA.ucf @@ -0,0 +1,11 @@ +## ============================================================================================================================================================= +## General Purpose I/O +## ============================================================================================================================================================= +## +## GPIO SMA +## ----------------------------------------------------------------------------- +## Bank: 12 +## VCCO: 2.5V (VADJ_FPGA) +## Location: J13, J14 +NET "KC705_GPIO_SMA_n" LOC = "Y24" | IOSTANDARD = LVDS_25; ## {INOUT} J14 +NET "KC705_GPIO_SMA_p" LOC = "Y23" | IOSTANDARD = LVDS_25; ## {INOUT} J13 diff --git a/ucf/KC705/GPIO.SMA.xdc b/ucf/KC705/GPIO.SMA.xdc new file mode 100644 index 00000000..ed081e6e --- /dev/null +++ b/ucf/KC705/GPIO.SMA.xdc @@ -0,0 +1,13 @@ +## ============================================================================================================================================================= +## General Purpose I/O +## ============================================================================================================================================================= +## +## GPIO SMA +## ----------------------------------------------------------------------------- +## Bank: 12 +## VCCO: 2.5V (VADJ_FPGA) +## Location: J13, J14 +set_property PACKAGE_PIN Y23 [get_ports KC705_GPIO_SMA_p] +set_property PACKAGE_PIN Y24 [get_ports KC705_GPIO_SMA_n] +# set I/O standard +set_property IOSTANDARD LVDS_25 [get_ports -regexp {KC705_GPIO_SMA_.}] diff --git a/ucf/KC705/Transceiver.SFP.ucf b/ucf/KC705/Transceiver.SFP.ucf index bfb5d3b9..a4702075 100644 --- a/ucf/KC705/Transceiver.SFP.ucf +++ b/ucf/KC705/Transceiver.SFP.ucf @@ -3,8 +3,8 @@ ## ----------------------------------------------------------------------------- ## Bank: 12, 15, 117 ## VCCO: 2.5V, 2.5V (VADJ_FPGA, VADJ_FPGA) -## Quad117: -## RefClock0 +## Quad117: +## RefClock0 ## RefClock1 KC705_SMA_RefClock ## Placement: ## SFP: Quad117.Channel2 (GTXE2_CHANNEL_X0Y10) @@ -15,10 +15,10 @@ NET "KC705_SFP_LossOfSignal" LOC = "P19" | IOSTANDARD = LVCMOS25; ## #$ ; high- ## ## -------------------------- ## SFP+ LVDS signal-pairs -NET "KC705_SFP_TX_n" LOC = "H1"; ## {OUT} -NET "KC705_SFP_TX_p" LOC = "H2"; ## {OUT} -NET "KC705_SFP_RX_n" LOC = "G3"; ## {IN} -NET "KC705_SFP_RX_p" LOC = "G4"; ## {IN} +NET "KC705_SFP_TX_n" LOC = "H1"; ## {OUT} +NET "KC705_SFP_TX_p" LOC = "H2"; ## {OUT} +NET "KC705_SFP_RX_n" LOC = "G3"; ## {IN} +NET "KC705_SFP_RX_p" LOC = "G4"; ## {IN} # Ignore timings on async I/O pins NET "KC705_SFP_TX_Disable_n" TIG; diff --git a/ucf/KC705/Transceiver.SFP.xdc b/ucf/KC705/Transceiver.SFP.xdc index 03d9383f..232f55cf 100644 --- a/ucf/KC705/Transceiver.SFP.xdc +++ b/ucf/KC705/Transceiver.SFP.xdc @@ -3,13 +3,13 @@ ## ----------------------------------------------------------------------------- ## Bank: 12, 15, 117 ## VCCO: 2.5V, 2.5V (VADJ_FPGA, VADJ_FPGA) -## Quad117: -## RefClock0 +## Quad117: +## RefClock0 ## RefClock1 KC705_SMA_RefClock ## Placement: ## SFP: Quad117.Channel2 (GTXE2_CHANNEL_X0Y10) ## Location: P5 -#$ ## I²C-Address: 0xA0 (1010 000xb) +#$ ## I2C-Address: 0xA0 (1010 000xb) ## ----------------------------------------------------------------------------- ## #$ ; low-active; external 4k7 pullup resistor; level shifted by Q4 (NDS331N) set_property PACKAGE_PIN Y20 [get_ports KC705_SFP_TX_Disable_n] @@ -21,14 +21,14 @@ set_property IOSTANDARD LVCMOS25 [get_ports KC705_SFP_LossOfSignal] ## ## -------------------------- ## SFP+ LVDS signal-pairs -## {OUT} -set_property PACKAGE_PIN H1 [get_ports KC705_SFP_TX_n] -## {OUT} +## {OUT} set_property PACKAGE_PIN H2 [get_ports KC705_SFP_TX_p] -## {IN} -set_property PACKAGE_PIN G3 [get_ports KC705_SFP_RX_n] -## {IN} +## {OUT} +set_property PACKAGE_PIN H1 [get_ports KC705_SFP_TX_n] +## {IN} set_property PACKAGE_PIN G4 [get_ports KC705_SFP_RX_p] +## {IN} +set_property PACKAGE_PIN G3 [get_ports KC705_SFP_RX_n] # Ignore timings on async I/O pins set_false_path -to [get_ports KC705_SFP_TX_Disable_n] diff --git a/ucf/KC705/Transceiver.SMA.ucf b/ucf/KC705/Transceiver.SMA.ucf index 7ad03b6d..73e36d93 100644 --- a/ucf/KC705/Transceiver.SMA.ucf +++ b/ucf/KC705/Transceiver.SMA.ucf @@ -2,8 +2,8 @@ ## Transceiver - SMA interface ## ----------------------------------------------------------------------------- ## Bank: 117 -## Quad117: -## RefClock0 +## Quad117: +## RefClock0 ## RefClock1 KC705_SMA_RefClock (see separate file "Transceiver.SMA_RefClock.ucf) ## ## Placement: diff --git a/ucf/KC705/Transceiver.SMA_RefClock.ucf b/ucf/KC705/Transceiver.SMA_RefClock.ucf index 97114064..a2dbbb3f 100644 --- a/ucf/KC705/Transceiver.SMA_RefClock.ucf +++ b/ucf/KC705/Transceiver.SMA_RefClock.ucf @@ -2,8 +2,8 @@ ## Transceiver - SMA interface ## ----------------------------------------------------------------------------- ## Bank: 117 -## Quad117: -## RefClock0 +## Quad117: +## RefClock0 ## RefClock1 KC705_SMA_RefClock ## Placement: ## SMA: Quad117.Channel0 (GTXE2_CHANNEL_X0Y8) @@ -13,5 +13,5 @@ ## ## reference clock ## -------------------------- -NET "KC705_SMA_RefClock_n" LOC = "J7"; ## {IN} J15; external 0.01 uF decoupling capacitor -NET "KC705_SMA_RefClock_p" LOC = "J8"; ## {IN} J16; external 0.01 uF decoupling capacitor +NET "KC705_SMA_RefClock_n" LOC = "J7" | IOSTANDARD = LVDS; ## {IN} J15; external 0.01 uF decoupling capacitor +NET "KC705_SMA_RefClock_p" LOC = "J8" | IOSTANDARD = LVDS; ## {IN} J16; external 0.01 uF decoupling capacitor diff --git a/ucf/ML505/Bus.IIC.Monitor.ucf b/ucf/ML505/Bus.IIC.Monitor.ucf index 247c10d7..a39c0df6 100644 --- a/ucf/ML505/Bus.IIC.Monitor.ucf +++ b/ucf/ML505/Bus.IIC.Monitor.ucf @@ -5,12 +5,12 @@ ## VCCO: 1.8V (VCC1V8) ## ----------------------------------------------------------------------------- ## Devices: ?? -## Location: -## Vendor: -## Device: -## I²C-Address: -NET "ML505_IIC_Monitor_SerialClock" LOC = "U27"; ## -NET "ML505_IIC_Monitor_SerialData" LOC = "T29"; ## +## Location: +## Vendor: +## Device: +## I²C-Address: +NET "ML505_IIC_Monitor_SerialClock" LOC = "U27"; ## +NET "ML505_IIC_Monitor_SerialData" LOC = "T29"; ## NET "ML505_IIC_Monitor_*" PULLUP; NET "ML505_IIC_Monitor_*" IOSTANDARD = LVCMOS18; diff --git a/ucf/ML505/Clock.SystemClock.ucf b/ucf/ML505/Clock.SystemClock.ucf index 4e12e05f..cd833140 100644 --- a/ucf/ML505/Clock.SystemClock.ucf +++ b/ucf/ML505/Clock.SystemClock.ucf @@ -8,9 +8,9 @@ ## Device: IDT5V9885 ## IIC-Address: 0x6A ## Frequency: 200 MHz -NET "ML505_SystemClock_200MHz_n" LOC = "K19"; ## {IN} U8.OUT5_N_16 NET "ML505_SystemClock_200MHz_p" LOC = "L19"; ## {IN} U8.OUT5_P_15 +NET "ML505_SystemClock_200MHz_n" LOC = "K19"; ## {IN} U8.OUT5_N_16 NET "ML505_SystemClock_200MHz_?" IOSTANDARD = LVDS_25; ## -NET "ML505_SystemClock_200MHz_p" TNM_NET = "TGRP_SystemClock"; -TIMESPEC "TS_SystemClock" = PERIOD "TGRP_SystemClock" 200 MHz HIGH 50 %; +NET "ML505_SystemClock_200MHz_p" TNM_NET = "PIN_SystemClock_200MHz"; +TIMESPEC "TS_SystemClock" = PERIOD "PIN_SystemClock_200MHz" 200 MHz HIGH 50 %; diff --git a/ucf/ML505/Clock.UserClock.ucf b/ucf/ML505/Clock.UserClock.ucf index 811a95e4..c1ee09be 100644 --- a/ucf/ML505/Clock.UserClock.ucf +++ b/ucf/ML505/Clock.UserClock.ucf @@ -4,8 +4,8 @@ ## VCCO: 3.3V (VCC3V3) ## Location: X1; single-ended clock socket ## Oscillator: 100 MHz -## Vendor: -## Device: +## Vendor: +## Device: ## Frequency: 100.0 MHz NET "ML505_UserClock" LOC = "AH15"; ## {IN} X1.Out NET "ML505_UserClock" IOSTANDARD = LVCMOS33; diff --git a/ucf/ML505/EthernetPHY.SGMII.ucf b/ucf/ML505/EthernetPHY.SGMII.ucf index 54d63097..7dc98d8c 100644 --- a/ucf/ML505/EthernetPHY.SGMII.ucf +++ b/ucf/ML505/EthernetPHY.SGMII.ucf @@ -2,7 +2,7 @@ ## SGMII LVDS signal-pairs ## -------------------------- ## Bank: 112 -## Transceiver: +## Transceiver: ## Location: X0Y3 - Port 0 ## Device: Ethernet PHY ## Location: U16 (M88E1111) diff --git a/ucf/ML505/EthernetPHY.ucf b/ucf/ML505/EthernetPHY.ucf index f6b2ade0..1c976ca0 100644 --- a/ucf/ML505/EthernetPHY.ucf +++ b/ucf/ML505/EthernetPHY.ucf @@ -6,7 +6,7 @@ ## VCCO: 2.5V (VCC2V5_FPGA), 2.5V (VCC2V5_FPGA), 3.3V (VCC3V3_FPGA) ## Location: U16 ## Vendor: Marvell -## Device: M88E1111 - +## Device: M88E1111 - ## MDIO-Address: 0x05 (---0 0111b) ## I²C-Address: I²C management mode is not enabled ## Configuration: set J20 to 3-5 and 4-6 to select 2.5 V for VCCO_EXP (Bank 11 and 13) diff --git a/ucf/ML505/GPIO.Button.Cursor.ucf b/ucf/ML505/GPIO.Button.Cursor.ucf index 49e14d27..109aa91e 100644 --- a/ucf/ML505/GPIO.Button.Cursor.ucf +++ b/ucf/ML505/GPIO.Button.Cursor.ucf @@ -10,7 +10,7 @@ NET "ML505_GPIO_Button_West" LOC = "AJ7" | IOSTANDARD = LVCMOS18; ## SW13 NET "ML505_GPIO_Button_Center" LOC = "AJ6" | IOSTANDARD = LVCMOS18; ## SW14; high-active; external 4k7 pulldown resistor NET "ML505_GPIO_Button_East" LOC = "AK7" | IOSTANDARD = LVCMOS18; ## SW12; high-active; external 4k7 pulldown resistor NET "ML505_GPIO_Button_South" LOC = "V8" | IOSTANDARD = LVCMOS18; ## SW11; high-active; external 4k7 pulldown resistor -NET "ML505_GPIO_Button_*" IOSTANDARD = LVCMOS33; ## +NET "ML505_GPIO_Button_*" IOSTANDARD = LVCMOS33; ## ## Ignore timings on async I/O pins NET "ML505_GPIO_Button_*" TIG; diff --git a/ucf/ML505/Monitor.DVI.Output.ucf b/ucf/ML505/Monitor.DVI.Output.ucf index 8a91de83..537b284f 100644 --- a/ucf/ML505/Monitor.DVI.Output.ucf +++ b/ucf/ML505/Monitor.DVI.Output.ucf @@ -5,25 +5,25 @@ ## VCCO: 1.8V, 3.3V, 3.3V (VCC1V8, VCC3V3, VCC3V3) ## Location: U17 ## ----------------------------------------------------------------------------- -NET "ML505_Video_DVI_Reset_n" LOC = "AK6"; ## -NET "ML505_Video_DVI_Clock_n" LOC = "AL10"; ## -NET "ML505_Video_DVI_Clock_p" LOC = "AL11"; ## -NET "ML505_Video_DVI_HSync" LOC = "AM12"; ## -NET "ML505_Video_DVI_VSync" LOC = "AM11"; ## -NET "ML505_Video_DVI_DataEnable" LOC = "AE8"; ## -NET "ML505_Video_DVI_Data<0>" LOC = "AB8"; ## -NET "ML505_Video_DVI_Data<1>" LOC = "AC8"; ## -NET "ML505_Video_DVI_Data<2>" LOC = "AN12"; ## -NET "ML505_Video_DVI_Data<3>" LOC = "AP12"; ## -NET "ML505_Video_DVI_Data<4>" LOC = "AA9"; ## -NET "ML505_Video_DVI_Data<5>" LOC = "AA8"; ## -NET "ML505_Video_DVI_Data<6>" LOC = "AM13"; ## -NET "ML505_Video_DVI_Data<7>" LOC = "AN13"; ## -NET "ML505_Video_DVI_Data<8>" LOC = "AA10"; ## -NET "ML505_Video_DVI_Data<9>" LOC = "AB10"; ## -NET "ML505_Video_DVI_Data<10>" LOC = "AP14"; ## -NET "ML505_Video_DVI_Data<11>" LOC = "AN14"; ## -NET "ML505_Video_DVI_GPIO1" LOC = "N30"; ## +NET "ML505_Video_DVI_Reset_n" LOC = "AK6"; ## +NET "ML505_Video_DVI_Clock_n" LOC = "AL10"; ## +NET "ML505_Video_DVI_Clock_p" LOC = "AL11"; ## +NET "ML505_Video_DVI_HSync" LOC = "AM12"; ## +NET "ML505_Video_DVI_VSync" LOC = "AM11"; ## +NET "ML505_Video_DVI_DataEnable" LOC = "AE8"; ## +NET "ML505_Video_DVI_Data<0>" LOC = "AB8"; ## +NET "ML505_Video_DVI_Data<1>" LOC = "AC8"; ## +NET "ML505_Video_DVI_Data<2>" LOC = "AN12"; ## +NET "ML505_Video_DVI_Data<3>" LOC = "AP12"; ## +NET "ML505_Video_DVI_Data<4>" LOC = "AA9"; ## +NET "ML505_Video_DVI_Data<5>" LOC = "AA8"; ## +NET "ML505_Video_DVI_Data<6>" LOC = "AM13"; ## +NET "ML505_Video_DVI_Data<7>" LOC = "AN13"; ## +NET "ML505_Video_DVI_Data<8>" LOC = "AA10"; ## +NET "ML505_Video_DVI_Data<9>" LOC = "AB10"; ## +NET "ML505_Video_DVI_Data<10>" LOC = "AP14"; ## +NET "ML505_Video_DVI_Data<11>" LOC = "AN14"; ## +NET "ML505_Video_DVI_GPIO1" LOC = "N30"; ## NET "ML505_Video_DVI_*" SLEW = FAST; ## Ignore timings on async I/O pins diff --git a/ucf/ML505/Transceiver.SFP.ucf b/ucf/ML505/Transceiver.SFP.ucf index c28bf7f2..7d9a6739 100644 --- a/ucf/ML505/Transceiver.SFP.ucf +++ b/ucf/ML505/Transceiver.SFP.ucf @@ -12,10 +12,10 @@ NET "ML505_SFP_TX_Disable" LOC = "K24" | IOSTANDARD = LVCMOS18; ## ; low-a ## ReferenceClock ## Location: P3 ## LOC X0Y4 - GTP_DUAL port 0 -NET "ML505_SFP_TX_p" LOC = "F2"; ## -NET "ML505_SFP_TX_n" LOC = "G2"; ## -NET "ML505_SFP_RX_p" LOC = "G1"; ## -NET "ML505_SFP_RX_n" LOC = "H1"; ## +NET "ML505_SFP_TX_p" LOC = "F2"; ## +NET "ML505_SFP_TX_n" LOC = "G2"; ## +NET "ML505_SFP_RX_p" LOC = "G1"; ## +NET "ML505_SFP_RX_n" LOC = "H1"; ## ## Bank 15; 1.8 V NET "ML505_SFP_SerialClock" LOC = "R26"; ## level shifted by Q42 (NDS331N) diff --git a/ucf/ML505/UART.ucf b/ucf/ML505/UART.ucf index d2cb52d2..0e3f898e 100644 --- a/ucf/ML505/UART.ucf +++ b/ucf/ML505/UART.ucf @@ -7,10 +7,10 @@ ## Device: ADM3202 - Low Power, 3.3 V, RS-232 Line Driver/Receiver ## Baud-Rate: up to 460 kBaud ## Note: FPGA is the master => so TX is an output and RX an input -NET "ML505_UART1_TX" LOC = "AG20"; ## {OUT} U13.10 {IN} -NET "ML505_UART1_RX" LOC = "AG15"; ## {IN} U13.9 {OUT} -NET "ML505_UART2_TX" LOC = "F10"; ## {OUT} U13.11 {IN} -NET "ML505_UART2_RX" LOC = "G10"; ## {IN} U13.12 {OUT} +NET "ML505_UART1_TX" LOC = "AG20"; ## {OUT} U13.10 {IN} +NET "ML505_UART1_RX" LOC = "AG15"; ## {IN} U13.9 {OUT} +NET "ML505_UART2_TX" LOC = "F10"; ## {OUT} U13.11 {IN} +NET "ML505_UART2_RX" LOC = "G10"; ## {IN} U13.12 {OUT} NET "ML505_UART?_?X" IOSTANDARD = LVCMOS33; NET "ML505_UART?_?X" SLEW = FAST; diff --git a/ucf/ML605/Bus.IIC.ucf b/ucf/ML605/Bus.IIC.ucf index 382663b0..c700e866 100644 --- a/ucf/ML605/Bus.IIC.ucf +++ b/ucf/ML605/Bus.IIC.ucf @@ -22,28 +22,28 @@ ## Devices: 8 ## Channel 0: UserClock ## Location: U34 -## Vendor: +## Vendor: ## Device: Si570 ## Address: 0xE0 (1110 000xb) ## Channel 1: FMC Connector 1 -## Location: +## Location: ## Channel 2: FMC Connector 2 -## Location: +## Location: ## Channel 3: EEPROM -## Location: -## Vendor: -## Device: +## Location: +## Vendor: +## Device: ## Address: 0xA8 (1010 100xb) ## Channel 4: SFP ## Location: P3 ## Address: 0xA0 (1010 000xb) ## Channel 5: HDMI -## Location: -## Vendor: -## Device: +## Location: +## Vendor: +## Device: ## Address: 0x72 (0111 001xb) ## Channel 6: DDR3 -## Location: +## Location: ## Address: 0xA0, 0x30 (1010 000xb, 0011 000xb) ## Channel 7: SI5324 ## Location: U24 (SI5324C-C-GM) diff --git a/ucf/ML605/Bus.PMBus.ucf b/ucf/ML605/Bus.PMBus.ucf index e1f81596..d386b7d1 100644 --- a/ucf/ML605/Bus.PMBus.ucf +++ b/ucf/ML605/Bus.PMBus.ucf @@ -12,9 +12,9 @@ ## ============================================================================= ## Bank: 15 ## VCCO: 1,8V (VCC1V8_FPGA) -## Location: -## Vendor: -## Device: -##NET "VC707_PMBus_Clock" LOC = "AW37" | IOSTANDARD = LVCMOS18; ## -##NET "VC707_PMBus_Data" LOC = "AY39" | IOSTANDARD = LVCMOS18; ## -##NET "VC707_PMBus_Alert" LOC = "AV38" | IOSTANDARD = LVCMOS18; ## +## Location: +## Vendor: +## Device: +##NET "VC707_PMBus_Clock" LOC = "AW37" | IOSTANDARD = LVCMOS18; ## +##NET "VC707_PMBus_Data" LOC = "AY39" | IOSTANDARD = LVCMOS18; ## +##NET "VC707_PMBus_Alert" LOC = "AV38" | IOSTANDARD = LVCMOS18; ## diff --git a/ucf/ML605/Clock.SystemClock.ucf b/ucf/ML605/Clock.SystemClock.ucf index 1bf5fd11..09eb1e8c 100644 --- a/ucf/ML605/Clock.SystemClock.ucf +++ b/ucf/ML605/Clock.SystemClock.ucf @@ -18,9 +18,9 @@ ## Vendor: SiTime ## Device: SiT9102 - 1 to 220 MHz High Performance Oscillator ## Frequency: 200 MHz, 50ppm -NET "ML605_SystemClock_200MHz_n" LOC = "H9"; ## {IN} U11.5 NET "ML605_SystemClock_200MHz_p" LOC = "J9"; ## {IN} U11.4 +NET "ML605_SystemClock_200MHz_n" LOC = "H9"; ## {IN} U11.5 NET "ML605_SystemClock_200MHz_?" IOSTANDARD = LVDS_25; ## -NET "ML605_SystemClock_200MHz_p" TNM_NET = "NET_SystemClock_200MHz"; -TIMESPEC "TS_SystemClock" = PERIOD "NET_SystemClock_200MHz" 200 MHz HIGH 50 %; +NET "ML605_SystemClock_200MHz_p" TNM_NET = "PIN_SystemClock_200MHz"; +TIMESPEC "TS_SystemClock" = PERIOD "PIN_SystemClock_200MHz" 200 MHz HIGH 50 %; diff --git a/ucf/ML605/EthernetPHY.GMII.ucf b/ucf/ML605/EthernetPHY.GMII.ucf index 854c14fa..42d312e8 100644 --- a/ucf/ML605/EthernetPHY.GMII.ucf +++ b/ucf/ML605/EthernetPHY.GMII.ucf @@ -13,7 +13,7 @@ ## VCCO: 2,5V (VCC2V5_FPGA) ## Location: U80 ## Vendor: Marvell -## Device: M88E1111 - +## Device: M88E1111 - ## MDIO-Address: 0x05 (---0 0111b) ## I²C-Address: I²C management mode is not enabled ## diff --git a/ucf/ML605/EthernetPHY.RGMII.ucf b/ucf/ML605/EthernetPHY.RGMII.ucf index 6b737b97..26b37c59 100644 --- a/ucf/ML605/EthernetPHY.RGMII.ucf +++ b/ucf/ML605/EthernetPHY.RGMII.ucf @@ -13,7 +13,7 @@ ## VCCO: 2,5V (VCC2V5_FPGA) ## Location: U80 ## Vendor: Marvell -## Device: M88E1111 - +## Device: M88E1111 - ## MDIO-Address: 0x05 (---0 0111b) ## I²C-Address: I²C management mode is not enabled ## diff --git a/ucf/ML605/EthernetPHY.SGMII.ucf b/ucf/ML605/EthernetPHY.SGMII.ucf index a928ae73..8f5de7a7 100644 --- a/ucf/ML605/EthernetPHY.SGMII.ucf +++ b/ucf/ML605/EthernetPHY.SGMII.ucf @@ -13,7 +13,7 @@ ## VCCO: 2,5V (VCC2V5_FPGA) ## Location: U80 ## Vendor: Marvell -## Device: M88E1111 - +## Device: M88E1111 - ## MDIO-Address: 0x05 (---0 0111b) ## I²C-Address: I²C management mode is not enabled ## @@ -21,10 +21,10 @@ ## -------------------------- ## Bank: 116 ## Transceiver: -## Location: +## Location: ## ReferenceClock ## Location: U82 (ICS844021I_TSSOP8) -## Vendor: +## Vendor: ## Device: ICS844021I ## Frequency: 125 MHz NET "ML605_EthernetPHY_RefClock_125MHz_p" LOC = "H6"; ## {IN} U82.7 diff --git a/ucf/ML605/EthernetPHY.ucf b/ucf/ML605/EthernetPHY.ucf index 88456fe8..156deccc 100644 --- a/ucf/ML605/EthernetPHY.ucf +++ b/ucf/ML605/EthernetPHY.ucf @@ -13,7 +13,7 @@ ## VCCO: 2,5V (VCC2V5_FPGA) ## Location: U80 ## Vendor: Marvell -## Device: M88E1111 - +## Device: M88E1111 - ## MDIO-Address: 0x05 (---0 0111b) ## I²C-Address: I²C management mode is not enabled ## diff --git a/ucf/ML605/GPIO.Button.Cursor.ucf b/ucf/ML605/GPIO.Button.Cursor.ucf index d8b3d17c..935dc67f 100644 --- a/ucf/ML605/GPIO.Button.Cursor.ucf +++ b/ucf/ML605/GPIO.Button.Cursor.ucf @@ -21,7 +21,7 @@ NET "ML605_GPIO_Button_West" LOC = "H17"; ## SW 8; high-active; exter NET "ML605_GPIO_Button_Center" LOC = "G26"; ## SW 9; high-active; external 4k7 pulldown resistor NET "ML605_GPIO_Button_East" LOC = "G17"; ## SW 7; high-active; external 4k7 pulldown resistor NET "ML605_GPIO_Button_South" LOC = "A18"; ## SW 6; high-active; external 4k7 pulldown resistor -NET "ML605_GPIO_Button_*" IOSTANDARD = LVCMOS18; ## +NET "ML605_GPIO_Button_*" IOSTANDARD = LVCMOS18; ## ## Ignore timings on async I/O pins NET "ML605_GPIO_Button_*" TIG; diff --git a/ucf/ML605/GPIO.LED.ucf b/ucf/ML605/GPIO.LED.ucf index 3b3d82c8..8cbea2c0 100644 --- a/ucf/ML605/GPIO.LED.ucf +++ b/ucf/ML605/GPIO.LED.ucf @@ -24,7 +24,7 @@ NET "ML605_GPIO_LED<4>" LOC = "AB23"; ## DS15 NET "ML605_GPIO_LED<5>" LOC = "AG23"; ## DS14 NET "ML605_GPIO_LED<6>" LOC = "AE24"; ## DS22 NET "ML605_GPIO_LED<7>" LOC = "AD24"; ## DS21 -NET "ML605_GPIO_LED" IOSTANDARD = LVCMOS18; ## +NET "ML605_GPIO_LED" IOSTANDARD = LVCMOS18; ## ## Ignore timings on async I/O pins NET "ML605_GPIO_LED" TIG; diff --git a/ucf/VC707/Bus.IIC.ucf b/ucf/VC707/Bus.IIC.ucf index f0be601a..4691a608 100644 --- a/ucf/VC707/Bus.IIC.ucf +++ b/ucf/VC707/Bus.IIC.ucf @@ -10,28 +10,28 @@ ## Devices: 8 ## Channel 0: UserClock ## Location: U34 -## Vendor: +## Vendor: ## Device: Si570 ## Address: 0xE0 (1110 000xb) ## Channel 1: FMC Connector 1 -## Location: +## Location: ## Channel 2: FMC Connector 2 -## Location: +## Location: ## Channel 3: EEPROM -## Location: -## Vendor: -## Device: +## Location: +## Vendor: +## Device: ## Address: 0xA8 (1010 100xb) ## Channel 4: SFP ## Location: P3 ## Address: 0xA0 (1010 000xb) ## Channel 5: HDMI -## Location: -## Vendor: -## Device: +## Location: +## Vendor: +## Device: ## Address: 0x72 (0111 001xb) ## Channel 6: DDR3 -## Location: +## Location: ## Address: 0xA0, 0x30 (1010 000xb, 0011 000xb) ## Channel 7: SI5324 ## Location: U24 (SI5324C-C-GM) diff --git a/ucf/VC707/Bus.PMBus.ucf b/ucf/VC707/Bus.PMBus.ucf index 3caf486b..346939e5 100644 --- a/ucf/VC707/Bus.PMBus.ucf +++ b/ucf/VC707/Bus.PMBus.ucf @@ -2,9 +2,9 @@ ## ============================================================================= ## Bank: 15 ## VCCO: 1,8V (VCC1V8_FPGA) -## Location: -## Vendor: -## Device: -##NET "VC707_PMBus_Clock" LOC = "AW37" | IOSTANDARD = LVCMOS18; ## -##NET "VC707_PMBus_Data" LOC = "AY39" | IOSTANDARD = LVCMOS18; ## -##NET "VC707_PMBus_Alert" LOC = "AV38" | IOSTANDARD = LVCMOS18; ## +## Location: +## Vendor: +## Device: +##NET "VC707_PMBus_Clock" LOC = "AW37" | IOSTANDARD = LVCMOS18; ## +##NET "VC707_PMBus_Data" LOC = "AY39" | IOSTANDARD = LVCMOS18; ## +##NET "VC707_PMBus_Alert" LOC = "AV38" | IOSTANDARD = LVCMOS18; ## diff --git a/ucf/VC707/Clock.ProgUserClock.ucf b/ucf/VC707/Clock.ProgUserClock.ucf index abb6d2b0..f89d88be 100644 --- a/ucf/VC707/Clock.ProgUserClock.ucf +++ b/ucf/VC707/Clock.ProgUserClock.ucf @@ -11,4 +11,4 @@ ## I²C-Address: 0x5D #$ (0111 010xb) NET "VC707_ProgUserClock_p" LOC = "AK34" | IOSTANDARD = LVDS; ## {IN} U34.4 NET "VC707_ProgUserClock_n" LOC = "AL34" | IOSTANDARD = LVDS; ## {IN} U34.5 -NET "VC707_ProgUserClock_p" TNM_NET = "NET_ProgUserClock"; +NET "VC707_ProgUserClock_p" TNM_NET = "PIN_ProgUserClock"; diff --git a/ucf/VC707/Clock.ProgUserClock.xdc b/ucf/VC707/Clock.ProgUserClock.xdc index d42848b2..c48ec580 100644 --- a/ucf/VC707/Clock.ProgUserClock.xdc +++ b/ucf/VC707/Clock.ProgUserClock.xdc @@ -13,4 +13,3 @@ set_property PACKAGE_PIN AK34 [get_ports VC707_ProgUserClock_p] set_property PACKAGE_PIN AL34 [get_ports VC707_ProgUserClock_n] # set I/O standard set_property IOSTANDARD LVDS [get_ports -regexp {VC707_ProgUserClock_[p|n]}] -#$ NET "VC707_ProgUserClock_p" TNM_NET = "NET_ProgUserClock"; diff --git a/ucf/VC707/Clock.SystemClock.ucf b/ucf/VC707/Clock.SystemClock.ucf index cd159cce..8091b6b2 100644 --- a/ucf/VC707/Clock.SystemClock.ucf +++ b/ucf/VC707/Clock.SystemClock.ucf @@ -13,6 +13,6 @@ NET "VC707_SystemClock_200MHz_p" LOC = "E19"; ## U51.4 NET "VC707_SystemClock_200MHz_n" LOC = "E18"; ## U51.5 NET "VC707_SystemClock_200MHz_?" IOSTANDARD = LVDS; -NET "VC707_SystemClock_200MHz_p" TNM_NET = "NET_SystemClock_200MHz"; +NET "VC707_SystemClock_200MHz_p" TNM_NET = "PIN_SystemClock_200MHz"; -TIMESPEC "TS_SystemClock" = PERIOD "NET_SystemClock_200MHz" 200 MHz HIGH 50 %; +TIMESPEC "TS_SystemClock" = PERIOD "PIN_SystemClock_200MHz" 200 MHz HIGH 50 %; diff --git a/ucf/VC707/Clock.SystemClock.xdc b/ucf/VC707/Clock.SystemClock.xdc index b6be1525..941dd040 100644 --- a/ucf/VC707/Clock.SystemClock.xdc +++ b/ucf/VC707/Clock.SystemClock.xdc @@ -15,4 +15,4 @@ set_property PACKAGE_PIN E18 [get_ports VC707_SystemClock_200MHz_n] # set I/O standard set_property IOSTANDARD LVDS [get_ports -regexp {VC707_SystemClock_200MHz_[p|n]}] # specify a 200 MHz clock -create_clock -period 5.000 -name NET_SystemClock_200MHz [get_ports VC707_SystemClock_200MHz_p] +create_clock -period 5.000 -name PIN_SystemClock_200MHz [get_ports VC707_SystemClock_200MHz_p] diff --git a/ucf/VC707/EthernetPHY.SGMII.ucf b/ucf/VC707/EthernetPHY.SGMII.ucf index 8ccd5313..aaabd303 100644 --- a/ucf/VC707/EthernetPHY.SGMII.ucf +++ b/ucf/VC707/EthernetPHY.SGMII.ucf @@ -4,7 +4,7 @@ ## VCCO: 1,8V (VCC1V8_FPGA) ## Location: U50 ## Vendor: Marvell -## Device: M88E1111 - +## Device: M88E1111 - ## MDIO-Address: 0x05 (---0 0111b) ## I²C-Address: I²C management mode is not enabled ## @@ -13,12 +13,12 @@ ## Bank: 113 ## ReferenceClock ## Location: U2 (ICS844021I_TSSOP8) -## Vendor: +## Vendor: ## Device: ICS844021I ## Frequency: 125 MHz -NET "VC707_EthernetPHY_RefClock_125MHz_n" LOC = "AH7"; ## -NET "VC707_EthernetPHY_RefClock_125MHz_p" LOC = "AH8"; ## -NET "VC707_EthernetPHY_SGMII_TX_n" LOC = "AN1"; ## -NET "VC707_EthernetPHY_SGMII_TX_p" LOC = "AN2"; ## -NET "VC707_EthernetPHY_SGMII_RX_n" LOC = "AM7"; ## -NET "VC707_EthernetPHY_SGMII_RX_p" LOC = "AM8"; ## +NET "VC707_EthernetPHY_RefClock_125MHz_n" LOC = "AH7"; ## +NET "VC707_EthernetPHY_RefClock_125MHz_p" LOC = "AH8"; ## +NET "VC707_EthernetPHY_SGMII_TX_n" LOC = "AN1"; ## +NET "VC707_EthernetPHY_SGMII_TX_p" LOC = "AN2"; ## +NET "VC707_EthernetPHY_SGMII_RX_n" LOC = "AM7"; ## +NET "VC707_EthernetPHY_SGMII_RX_p" LOC = "AM8"; ## diff --git a/ucf/VC707/EthernetPHY.ucf b/ucf/VC707/EthernetPHY.ucf index 5e06315b..96a717a7 100644 --- a/ucf/VC707/EthernetPHY.ucf +++ b/ucf/VC707/EthernetPHY.ucf @@ -4,7 +4,7 @@ ## VCCO: 1,8V (VCC1V8_FPGA) ## Location: U50 ## Vendor: Marvell -## Device: M88E1111 - +## Device: M88E1111 - ## MDIO-Address: 0x05 (---0 0111b) ## I²C-Address: I²C management mode is not enabled NET "VC707_EthernetPHY_Reset_n" LOC = "AJ33" | IOSTANDARD = LVCMOS18; ## U50 - Pin K3 ; level shifted by U70 (TXS0108E) diff --git a/ucf/VC707/GPIO.SMA.ucf b/ucf/VC707/GPIO.SMA.ucf new file mode 100644 index 00000000..eaf44c24 --- /dev/null +++ b/ucf/VC707/GPIO.SMA.ucf @@ -0,0 +1,12 @@ +## ============================================================================================================================================================= +## General Purpose I/O +## ============================================================================================================================================================= +## +## GPIO SMA +## ----------------------------------------------------------------------------- +## Bank: 13 +## VCCO: 1.8V (VCC1V8_FPGA) +## Location: J33, J34 +NET "VC707_GPIO_SMA_p" LOC = "AN31"; ## {INOUT} J33 +NET "VC707_GPIO_SMA_n" LOC = "AP31"; ## {INOUT} J34 +NET "VC707_GPIO_SMA_?" IOSTANDARD = LVDS; diff --git a/ucf/VC707/GPIO.SMA.xdc b/ucf/VC707/GPIO.SMA.xdc new file mode 100644 index 00000000..48204fee --- /dev/null +++ b/ucf/VC707/GPIO.SMA.xdc @@ -0,0 +1,13 @@ +## ============================================================================================================================================================= +## General Purpose I/O +## ============================================================================================================================================================= +## +## GPIO SMA +## ----------------------------------------------------------------------------- +## Bank: 13 +## VCCO: 1.8V (VCC1V8_FPGA) +## Location: J33, J34 +set_property PACKAGE_PIN AN31 [get_ports VC707_GPIO_SMA_p] +set_property PACKAGE_PIN AP31 [get_ports VC707_GPIO_SMA_n] +# set I/O standard +set_property IOSTANDARD LVDS [get_ports -regexp {VC707_GPIO_SMA_.}] diff --git a/ucf/VC707/Transceiver.SFP.ucf b/ucf/VC707/Transceiver.SFP.ucf index 7eac1de6..c23a5e46 100644 --- a/ucf/VC707/Transceiver.SFP.ucf +++ b/ucf/VC707/Transceiver.SFP.ucf @@ -12,10 +12,10 @@ NET "VC707_SFP_LossOfSignal" LOC = "BB38" | IOSTANDARD = LVCMOS18; ## ; hig ## Bank: 113 ## ReferenceClock ## Location: P3 -NET "VC707_SFP_TX_p" LOC = "AM4"; ## -NET "VC707_SFP_TX_n" LOC = "AM3"; ## -NET "VC707_SFP_RX_p" LOC = "AL6"; ## -NET "VC707_SFP_RX_n" LOC = "AL5"; ## +NET "VC707_SFP_TX_p" LOC = "AM4"; ## +NET "VC707_SFP_TX_n" LOC = "AM3"; ## +NET "VC707_SFP_RX_p" LOC = "AL6"; ## +NET "VC707_SFP_RX_n" LOC = "AL5"; ## ## Ignore timings on async I/O pins NET "VC707_SFP_TX_Disable_n" TIG; diff --git a/ucf/VC707/USB_UART.ucf b/ucf/VC707/USB_UART.ucf index 8e71238d..d436ea7d 100644 --- a/ucf/VC707/USB_UART.ucf +++ b/ucf/VC707/USB_UART.ucf @@ -3,12 +3,12 @@ ## Bank: 13 ## VCCO: 1,8V (VCC1V8_FPGA) ## Location: U44 -## Vendor: -## Device: -NET "VC707_USB_UART_RX" LOC = "AU36"; ## -NET "VC707_USB_UART_RTS_n" LOC = "AT32"; ## -NET "VC707_USB_UART_TX" LOC = "AU33"; ## -NET "VC707_USB_UART_CTS_n" LOC = "AR34"; ## +## Vendor: +## Device: +NET "VC707_USB_UART_RX" LOC = "AU36"; ## +NET "VC707_USB_UART_RTS_n" LOC = "AT32"; ## +NET "VC707_USB_UART_TX" LOC = "AU33"; ## +NET "VC707_USB_UART_CTS_n" LOC = "AR34"; ## NET "VC707_USB_UART_*" IOSTANDARD = LVCMOS18; ## Ignore timings on async I/O pins diff --git a/ucf/VC707/USB_UART.xdc b/ucf/VC707/USB_UART.xdc index 3fa1107f..4f53c869 100644 --- a/ucf/VC707/USB_UART.xdc +++ b/ucf/VC707/USB_UART.xdc @@ -3,15 +3,15 @@ ## Bank: 13 ## VCCO: 1,8V (VCC1V8_FPGA) ## Location: U44 -## Vendor: -## Device: -## {IN} +## Vendor: +## Device: +## {IN} set_property PACKAGE_PIN AU33 [get_ports VC707_USB_UART_TX] -## {OUT} +## {OUT} set_property PACKAGE_PIN AU36 [get_ports VC707_USB_UART_RX] -## {IN} +## {IN} set_property PACKAGE_PIN AT32 [get_ports VC707_USB_UART_RTS_n] -## {OUT} +## {OUT} set_property PACKAGE_PIN AR34 [get_ports VC707_USB_UART_CTS_n] # set I/O standard set_property IOSTANDARD LVCMOS18 [get_ports -regexp {VC707_USB_UART_.*}] diff --git a/ucf/ZC706/Bus.IIC.ucf b/ucf/ZC706/Bus.IIC.ucf index 2a5daebc..499ceaed 100644 --- a/ucf/ZC706/Bus.IIC.ucf +++ b/ucf/ZC706/Bus.IIC.ucf @@ -22,8 +22,8 @@ ## Address: 0xA8 (1010 100xb) ## Channel 3: I2C Port Expander ## Location: U16 -## Vendor: -## Device: +## Vendor: +## Device: ## Address: 0x42 (0100 001xb) ## Channel 0: DDR3 SODIMM J1 ## Address: 0xA0, 0x30 (1010 000xb, 0011 000xb) @@ -33,13 +33,13 @@ ## Device: / SI5324 - Any-Frequency Precision Clock Multiplier/Jitter Attenuator ## Address: 0xA2 (1010 001xb) / 0xD0 (1101 000xb) ## Channel 5: FMC HPC -## Location: -## Vendor: -## Device: -## Address: +## Location: +## Vendor: +## Device: +## Address: ## Channel 6: FMX LPC -## Location: -## Address: +## Location: +## Address: ## Channel 7: UCD90120A (PMbus) ## Location: U48 ## Address: 0xCA (1100 101xb) diff --git a/ucf/ZC706/Bus.IIC.xdc b/ucf/ZC706/Bus.IIC.xdc index ecf8db3f..8f85ca89 100644 --- a/ucf/ZC706/Bus.IIC.xdc +++ b/ucf/ZC706/Bus.IIC.xdc @@ -22,8 +22,8 @@ ## Address: 0xA8 (1010 100xb) ## Channel 3: I2C Port Expander ## Location: U16 -## Vendor: -## Device: +## Vendor: +## Device: ## Address: 0x42 (0100 001xb) ## Channel 0: DDR3 SODIMM J1 ## Address: 0xA0, 0x30 (1010 000xb, 0011 000xb) @@ -33,13 +33,13 @@ ## Device: / SI5324 - Any-Frequency Precision Clock Multiplier/Jitter Attenuator ## Address: 0xA2 (1010 001xb) / 0xD0 (1101 000xb) ## Channel 5: FMC HPC -## Location: -## Vendor: -## Device: -## Address: +## Location: +## Vendor: +## Device: +## Address: ## Channel 6: FMX LPC -## Location: -## Address: +## Location: +## Address: ## Channel 7: UCD90120A (PMbus) ## Location: U48 ## Address: 0xCA (1100 101xb) diff --git a/ucf/ZC706/Clock.ProgUserClock.ucf b/ucf/ZC706/Clock.ProgUserClock.ucf index b7b5270c..18c0bda7 100644 --- a/ucf/ZC706/Clock.ProgUserClock.ucf +++ b/ucf/ZC706/Clock.ProgUserClock.ucf @@ -7,7 +7,7 @@ ## Device: SI570BAB0000544DG ## Frequency: 10 - 810 MHz, 50ppm ## Default Freq: 156.250 MHz -## I²C-Address: +## I²C-Address: NET "ZC706_ProgUserClock_p" LOC = "AF14" | IOSTANDARD = LVDS_25; ## {IN} U37.4 NET "ZC706_ProgUserClock_n" LOC = "AG14" | IOSTANDARD = LVDS_25; ## {IN} U37.5 -NET "ZC706_ProgUserClock_p" TNM_NET = "NET_ProgUserClock"; +NET "ZC706_ProgUserClock_p" TNM_NET = "PIN_ProgUserClock"; diff --git a/ucf/ZC706/Clock.ProgUserClock.xdc b/ucf/ZC706/Clock.ProgUserClock.xdc index 8b5bf4fa..7fda08ce 100644 --- a/ucf/ZC706/Clock.ProgUserClock.xdc +++ b/ucf/ZC706/Clock.ProgUserClock.xdc @@ -7,9 +7,8 @@ ## Device: SI570BAB0000544DG ## Frequency: 10 - 810 MHz, 50ppm ## Default Freq: 156.250 MHz -## I²C-Address: +## I²C-Address: set_property PACKAGE_PIN AF14 [get_ports ZC706_ProgUserClock_p] set_property PACKAGE_PIN AG14 [get_ports ZC706_ProgUserClock_n] # set I/O standard set_property IOSTANDARD LVDS_25 [get_ports -regexp {ZC706_ProgUserClock_[p|n]}] -#$ NET "ZC706_ProgUserClock_p" TNM_NET = "NET_ProgUserClock"; diff --git a/ucf/ZC706/Clock.SystemClock.ucf b/ucf/ZC706/Clock.SystemClock.ucf index 9664aff7..745b5629 100644 --- a/ucf/ZC706/Clock.SystemClock.ucf +++ b/ucf/ZC706/Clock.SystemClock.ucf @@ -9,6 +9,6 @@ NET "ZC706_SystemClock_200MHz_p" LOC = "H9"; ## {IN} U64.4 NET "ZC706_SystemClock_200MHz_n" LOC = "G9"; ## {IN} U64.5 NET "ZC706_SystemClock_200MHz_?" IOSTANDARD = LVDS; -NET "ZC706_SystemClock_200MHz_p" TNM_NET = "NET_SystemClock_200MHz"; +NET "ZC706_SystemClock_200MHz_p" TNM_NET = "PIN_SystemClock_200MHz"; -TIMESPEC "TS_SystemClock" = PERIOD "NET_SystemClock_200MHz" 200 MHz HIGH 50 %; +TIMESPEC "TS_SystemClock" = PERIOD "PIN_SystemClock_200MHz" 200 MHz HIGH 50 %; diff --git a/ucf/ZC706/Clock.SystemClock.xdc b/ucf/ZC706/Clock.SystemClock.xdc index 9de3fcc3..91178d96 100644 --- a/ucf/ZC706/Clock.SystemClock.xdc +++ b/ucf/ZC706/Clock.SystemClock.xdc @@ -9,6 +9,6 @@ set_property PACKAGE_PIN H9 [get_ports ZC706_SystemClock_200MHz_p] set_property PACKAGE_PIN G9 [get_ports ZC706_SystemClock_200MHz_n] # set I/O standard -set_property IOSTANDARD LVDS [get_ports -regexp {ZC706_SystemClock_200MHz_[p|n]}] +set_property IOSTANDARD LVDS [get_ports -regexp {ZC706_SystemClock_200MHz_[p|n]}] # specify a 200 MHz clock -create_clock -period 5.000 -name NET_SystemClock_200MHz [get_ports ZC706_SystemClock_200MHz_p] +create_clock -period 5.000 -name PIN_SystemClock_200MHz [get_ports ZC706_SystemClock_200MHz_p] diff --git a/ucf/ZC706/Default.ucf b/ucf/ZC706/Default.ucf index 61cca553..8610c9d4 100644 --- a/ucf/ZC706/Default.ucf +++ b/ucf/ZC706/Default.ucf @@ -6,7 +6,7 @@ ## Device: XC7Z045 ## Package: FFG900 ## Speedgrade: -2 -## +## ## Notes: ## Power Rail 4 driving VADJ_FPGA is defaulted to 2.5V (choices: 1.8V, 2.5V, 3.3V) ## diff --git a/ucf/ZC706/Transceiver.SFP.ucf b/ucf/ZC706/Transceiver.SFP.ucf index 4a498d66..52ca797c 100644 --- a/ucf/ZC706/Transceiver.SFP.ucf +++ b/ucf/ZC706/Transceiver.SFP.ucf @@ -3,21 +3,21 @@ ## ----------------------------------------------------------------------------- ## Bank: 9, 111 ## VCCO: 2.5V (VADJ_FPGA) -## Quad117: -## RefClock0 +## Quad117: +## RefClock0 ## RefClock1 ZC706_SMA_RefClock ## Placement: ## SFP: Quad??.Channel2 (GTXE2_CHANNEL_X??Y??) ## Location: P2 -## I²C-Address: +## I²C-Address: NET "ZC706_SFP_TX_Disable_n" LOC = "AA18" | IOSTANDARD = LVCMOS25; ## ; low-active; external 4k7 pullup resistor; level shifted by Q4 (NDS331N) ## ## -------------------------- ## SFP+ LVDS signal-pairs -NET "ZC706_SFP_TX_p" LOC = "W4"; ## {OUT} -NET "ZC706_SFP_TX_n" LOC = "W3"; ## {OUT} -NET "ZC706_SFP_RX_p" LOC = "Y6"; ## {IN} -NET "ZC706_SFP_RX_n" LOC = "Y5"; ## {IN} +NET "ZC706_SFP_TX_p" LOC = "W4"; ## {OUT} +NET "ZC706_SFP_TX_n" LOC = "W3"; ## {OUT} +NET "ZC706_SFP_RX_p" LOC = "Y6"; ## {IN} +NET "ZC706_SFP_RX_n" LOC = "Y5"; ## {IN} # Ignore timings on async I/O pins NET "ZC706_SFP_TX_Disable_n" TIG; diff --git a/ucf/ZC706/Transceiver.SFP.xdc b/ucf/ZC706/Transceiver.SFP.xdc index 51f94974..306f0840 100644 --- a/ucf/ZC706/Transceiver.SFP.xdc +++ b/ucf/ZC706/Transceiver.SFP.xdc @@ -3,8 +3,8 @@ ## ----------------------------------------------------------------------------- ## Bank: 12, 15, 117 ## VCCO: 2.5V, 2.5V (VADJ_FPGA, VADJ_FPGA) -## Quad117: -## RefClock0 +## Quad117: +## RefClock0 ## RefClock1 ZC706_SMA_RefClock ## Placement: ## SFP: Quad117.Channel2 (GTXE2_CHANNEL_X0Y10) @@ -18,13 +18,13 @@ set_property IOSTANDARD LVCMOS25 [get_ports ZC706_SFP_TX_Disable_n] ## ## -------------------------- ## SFP+ LVDS signal-pairs -## {OUT} +## {OUT} set_property PACKAGE_PIN W4 [get_ports ZC706_SFP_TX_p] -## {OUT} +## {OUT} set_property PACKAGE_PIN W3 [get_ports ZC706_SFP_TX_n] -## {IN} +## {IN} set_property PACKAGE_PIN Y6 [get_ports ZC706_SFP_RX_p] -## {IN} +## {IN} set_property PACKAGE_PIN Y5 [get_ports ZC706_SFP_RX_n] # Ignore timings on async I/O pins diff --git a/ucf/ZedBoard/Clock.SystemClock.ucf b/ucf/ZedBoard/Clock.SystemClock.ucf index 36379cc1..a6ae2478 100644 --- a/ucf/ZedBoard/Clock.SystemClock.ucf +++ b/ucf/ZedBoard/Clock.SystemClock.ucf @@ -7,7 +7,9 @@ ## VCCO: 3.3V (VCC3V3) ## Location: IC17 (Fox Electronics FXO-HC53 SERIES 767-100-136) ## Vendor: Fox Electronics -## Device: +## Device: ## Frequency: 100 MHz, 50ppm NET "ZED_SystemClock_100MHz" LOC = "Y9" | IOSTANDARD = LVCMOS33; ## {IN} IC17.3 -NET "ZED_SystemClock_100MHz" TNM_NET = "NET_SystemClock_100MHz"; +NET "ZED_SystemClock_100MHz" TNM_NET = "PIN_SystemClock_100MHz"; + +TIMESPEC "TS_SystemClock" = PERIOD "PIN_SystemClock_100MHz" 100 MHz HIGH 50 %; diff --git a/ucf/ZedBoard/Default.ucf b/ucf/ZedBoard/Default.ucf index 9188e4cc..e53d29ae 100644 --- a/ucf/ZedBoard/Default.ucf +++ b/ucf/ZedBoard/Default.ucf @@ -6,7 +6,7 @@ ## Device: XC7Z020 ## Package: CLG484 ## Speedgrade: -1 -## +## ## ============================================================================= ## Miscellaneous ## ============================================================================= diff --git a/ucf/misc/sync/sync_Bits_Xilinx.ucf b/ucf/misc/sync/sync_Bits_Xilinx.ucf index 29dee8dc..ae00d3f9 100644 --- a/ucf/misc/sync/sync_Bits_Xilinx.ucf +++ b/ucf/misc/sync/sync_Bits_Xilinx.ucf @@ -1,2 +1,2 @@ -# +# INST "*FF1_METASTABILITY_FFS" TNM = "METASTABILITY_FFS"; diff --git a/ucf/misc/sync/sync_Reset_Xilinx.ucf b/ucf/misc/sync/sync_Reset_Xilinx.ucf index 97729acf..81995d80 100644 --- a/ucf/misc/sync/sync_Reset_Xilinx.ucf +++ b/ucf/misc/sync/sync_Reset_Xilinx.ucf @@ -1,3 +1,3 @@ -# +# INST "*FF2_METASTABILITY_FFS" TNM = "METASTABILITY_FFS"; INST "*FF3_METASTABILITY_FFS" TNM = "METASTABILITY_FFS"; diff --git a/vhdl_coding.md b/vhdl_coding.md new file mode 100644 index 00000000..6ad6d3cb --- /dev/null +++ b/vhdl_coding.md @@ -0,0 +1,87 @@ +# PoC VHDL Coding Guide + +## Licensing +PoC is published under the [Apache License, Version 2.0](LICENSE.md). +Please, make sure you are able and willing to submit your contibutions to +this license. + +## Naming +1. VHDL sources have the file extension `.vhdl`. +2. Prepend the name of an entity with its containing package using snake case, + e.g.: `arith_addw` for the wide adder in package `arith`. Each module is + implemented in its own source file, the name of which is `.vhdl`. +3. Synthesizable module implementations are provided through an + architecture named `rtl`. +4. The name of a testbench entity copies the name of the tested module or + package, to which `_tb` is appended. Its implementing architecture is + named `tb`. + +## Formatting + +### Header +* Include the configuration header to automatically configure common editors + to the tab width of two spaces: +```vhdl +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +``` +* Document your package or module within a documentation header: + * starting with a separator line matching `/^--\s*={16,}$/`, + * containing the appropriate sections of + `Authors|Entity|Description|SeeAlso`, and + * providing the license statement: +```vhdl +-- =========================================================================== +-- Copyright 2007-2016 Technische Universitaet Dresden - Germany +-- Chair for VLSI-Design, Diagnostics and Architecture +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- =========================================================================== +``` + +### Whitespace +* Indent with one tab character per indentation level. +* Assume a tab width of two spaces. +* Eliminate all trailing whitespace. + +## Coding Style + +### Capitalization +1. Both snake and camel case are acceptable for signal and variable names as + well as for labels. Be consistent in the capitalization when naming any such + instance. +2. Use all lower case for VHDL keywords (e.g. `process`, `case`, ...) + and common standard types (e.g. `integer`, `std_logic_vector`). +3. Use all upper case for constants and generic parameters. + +### Signal Initialization +1. Specify an initiatilizer for all signals that are to represent sequential + logic, i.e. some state. If their initial state is irrelevant, initialize + them to a don't-care value as appropriate, e.g. `(others => '-')`. Typically + the same initial state should be assigned upon a reset condition. +2. Combinational signals never have a user-specified initializer. + +### Expressions +1. Always use parentheses within expressions as soon as operator precedence + is relevant and not trivial. +2. Avoid extraneous parentheses around expressions already framed by their + syntactical contexts, such as `if ... then` or `while ... loop`. +3. Evaluate `boolean` expressions directly without comparing them to + a `boolean` literal: use plain `B` instead of `B = true` and `not B` + rather than `B = false`. + +### Instantiations +1. Do not use the positional binding of generic parameters or ports. +2. Prefer the instantiation of components if their declarations are + readily available through designated packages. diff --git a/xst/xil/mig/mig_KC705_MT8JTF12864HZ_1G6.xcf b/xst/xil/mig/mig_KC705_MT8JTF12864HZ_1G6.xcf index 6df701e3..e9742670 100644 --- a/xst/xil/mig/mig_KC705_MT8JTF12864HZ_1G6.xcf +++ b/xst/xil/mig/mig_KC705_MT8JTF12864HZ_1G6.xcf @@ -1,9 +1,9 @@ ################################################################################################## -## -## Xilinx, Inc. 2010 www.xilinx.com +## +## Xilinx, Inc. 2010 www.xilinx.com ## Fri Feb 19 15:25:45 2016 ## Generated by MIG Version 1.9 -## +## ################################################################################################## ## File name : mig_KC705_MT8JTF12864HZ_1G6.ucf ## Details : Constraints file @@ -25,7 +25,7 @@ NET "sys_clk_i" TNM_NET = TNM_sys_clk; TIMESPEC "TS_sys_clk" = PERIOD "TNM_sys_clk" 4.998 ns; - + NET "clk_ref_i" TNM_NET = TNM_clk_ref; TIMESPEC "TS_clk_ref" = PERIOD "TNM_clk_ref" 5 ns ;