diff --git a/.appveyor.yml b/.appveyor.yml new file mode 100644 index 00000000..64986a16 --- /dev/null +++ b/.appveyor.yml @@ -0,0 +1,36 @@ +version: 1.1.0-b{build} +clone_folder: c:\projects\poc +init: + # Checking that DEP is enabled + - ps: Write-Host "Initializing virtual machine ..." + - ps: git --version + - ps: $env:Path = $env:Path.Replace("Python27", "Python35-x64") + +install: + - ps: Write-Host "Installing requirements..." + - ps: python --version + - ps: python -m pip install pip --upgrade + - ps: python -m pip install -r .\requirements.txt + - ps: python -m pip list --format=columns + - ps: Write-Host "Configuring PoC..." + - ps: cp .\tools\AppVeyor\config.private.ini .\py\ + - ps: cp .\tools\AppVeyor\my_project.vhdl .\tb\common\ + - ps: .\poc.ps1 + +build: off + +build_script: + - ps: Write-Host "Testing query interface..." + - ps: .\poc.ps1 query INSTALL.PoC:InstallationDirectory + - ps: Write-Host "Testing information interface..." + - ps: .\poc.ps1 list-testbench PoC.* + - ps: .\poc.ps1 list-netlist PoC.* + - ps: Write-Host "Testing simulators..." + - ps: .\poc.ps1 --dryrun ghdl PoC.arith.prng --analyze --elaborate + - ps: Write-Host "Testing synthesizers..." +# - ps: .\poc.ps1 --dryrun quartus PoC.arith.prng --board=DE4 +# - ps: .\poc.ps1 --dryrun lse PoC.arith.prng --board=ECP5Versa +# - ps: .\poc.ps1 --dryrun xst PoC.arith.prng --board=KC705 +# - ps: .\poc.ps1 --dryrun vivado PoC.arith.prng --board=KC705 +# - ps: Write-Host "Testing core generators..." +# - ps: .\poc.ps1 --dryrun coregen PoC.xil.mig.Atlys_1x128 --board=Atlys diff --git a/.gitignore b/.gitignore index a673e46e..40fb9426 100644 --- a/.gitignore +++ b/.gitignore @@ -9,7 +9,13 @@ __pycache__ # ignore build directories -docs/_build/ +/docs/_build/ +/docs/PyInfrastructure/* +!/docs/PyInfrastructure/.gitempty +!/docs/PyInfrastructure/.publish +!/docs/PyInfrastructure/README.md +!/docs/PyInfrastructure/index.rst + # ignore files in netlist/ /netlist/ @@ -94,3 +100,4 @@ other/diamond/.spreadsheet_view.ini !.git* !.publish !README.md +other/PrecisionRTL/ diff --git a/.gitmodules b/.gitmodules index 06b72da2..19e704da 100644 --- a/.gitmodules +++ b/.gitmodules @@ -10,3 +10,6 @@ [submodule "docs/_themes/sphinx_rtd_theme"] path = docs/_themes/sphinx_rtd_theme url = https://github.com/VLSI-EDA/sphinx_rtd_theme.git +[submodule "lib/uvvm"] + path = lib/uvvm + url = https://github.com/VLSI-EDA/UVVM_All.git diff --git a/.landscape.yml b/.landscape.yml index 45d79860..3f8858a6 100644 --- a/.landscape.yml +++ b/.landscape.yml @@ -30,6 +30,7 @@ ignore-paths: - sim - src # - tb +- tcl - temp # - tools - ucf diff --git a/.readthedocs.yml b/.readthedocs.yml new file mode 100644 index 00000000..cd8a4d65 --- /dev/null +++ b/.readthedocs.yml @@ -0,0 +1,5 @@ +#formats: +# - pdf +requirements_file: tools/ReadTheDocs/requirements.txt +python: + version: 3 diff --git a/README.md b/README.md index dae6e3be..0d4a19eb 100644 --- a/README.md +++ b/README.md @@ -3,7 +3,9 @@ [![Python Infrastructure tested by Landscape.io](https://landscape.io/github/VLSI-EDA/PoC/Vivado/landscape.svg?style=flat)](https://landscape.io/github/VLSI-EDA/PoC/Vivado) [![Build Status by Travis-CI](https://travis-ci.org/VLSI-EDA/PoC.svg?branch=Vivado)](https://travis-ci.org/VLSI-EDA/PoC/branches) +[![Build status by AppVeyor](https://ci.appveyor.com/api/projects/status/r5dtv6amsppigpsp/branch/Vivado?svg=true)](https://ci.appveyor.com/project/Paebbels/poc/branch/Vivado) [![Documentation Status](https://readthedocs.org/projects/poc-library/badge/?version=latest)](http://poc-library.readthedocs.io/en/latest/?badge=latest) +[![Requirements Status](https://requires.io/github/VLSI-EDA/PoC/requirements.svg?branch=Vivado)](https://requires.io/github/VLSI-EDA/PoC/requirements/?branch=Vivado) [![Join the chat at https://gitter.im/VLSI-EDA/PoC](https://badges.gitter.im/VLSI-EDA/PoC.svg)](https://gitter.im/VLSI-EDA/PoC) ![Latest tag](https://img.shields.io/github/tag/VLSI-EDA/PoC.svg?style=flat) [![Latest release](https://img.shields.io/github/release/VLSI-EDA/PoC.svg?style=flat)](https://github.com/VLSI-EDA/PoC/releases) @@ -85,7 +87,9 @@ Windows. See [Requirements][211] for further details. A coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python. - [OS-VVM][2132] Open Source VHDL Verification Methodology. - - [VUnit][2133] + - [UVVM][2133] + Universal VHDL Verification Methodology. + - [VUnit][2134] An unit testing framework for VHDL. All dependencies are available as GitHub repositories and are linked to PoC as Git submodules into the @@ -93,7 +97,8 @@ All dependencies are available as GitHub repositories and are linked to PoC as G [2131]: https://github.com/potentialventures/cocotb [2132]: https://github.com/JimLewis/OSVVM -[2133]: https://github.com/VUnit/vunit +[2133]: https://github.com/UVVM/UVVM_All +[2134]: https://github.com/VUnit/vunit [201]: http://poc-library.readthedocs.io/en/latest/UsingPoC/index.html [202]: http://poc-library.readthedocs.io/ @@ -103,7 +108,7 @@ All dependencies are available as GitHub repositories and are linked to PoC as G ### 2.2 Download -The PoC-Library can be downloaded as a [zip-file][221] (latest 'release' branch), cloned with `git clone` +The PoC-Library can be downloaded as a [zip-file][221] (latest 'Vivado' branch), cloned with `git clone` or embedded with `git submodule add` from GitHub. GitHub offers HTTPS and SSH as transfer protocols. See the [Download][222] page for further details. The installation directory is referred to as `PoCRoot`. diff --git a/README.tpl b/README.tpl index c68ec27a..0cbb56d1 100644 --- a/README.tpl +++ b/README.tpl @@ -3,12 +3,15 @@ [![Python Infrastructure tested by Landscape.io](https://landscape.io/github/VLSI-EDA/PoC/{@BRANCH@}/landscape.svg?style=flat)](https://landscape.io/github/VLSI-EDA/PoC/{@BRANCH@}) [![Build Status by Travis-CI](https://travis-ci.org/VLSI-EDA/PoC.svg?branch={@BRANCH@})](https://travis-ci.org/VLSI-EDA/PoC/branches) +[![Build status by AppVeyor](https://ci.appveyor.com/api/projects/status/r5dtv6amsppigpsp/branch/{@BRANCH@}?svg=true)](https://ci.appveyor.com/project/Paebbels/poc/branch/{@BRANCH@}) [![Documentation Status](https://readthedocs.org/projects/poc-library/badge/?version=latest)](http://poc-library.readthedocs.io/en/latest/?badge=latest) +[![Requirements Status](https://requires.io/github/VLSI-EDA/PoC/requirements.svg?branch={@BRANCH@})](https://requires.io/github/VLSI-EDA/PoC/requirements/?branch={@BRANCH@}) [![Join the chat at https://gitter.im/VLSI-EDA/PoC](https://badges.gitter.im/VLSI-EDA/PoC.svg)](https://gitter.im/VLSI-EDA/PoC) ![Latest tag](https://img.shields.io/github/tag/VLSI-EDA/PoC.svg?style=flat) [![Latest release](https://img.shields.io/github/release/VLSI-EDA/PoC.svg?style=flat)](https://github.com/VLSI-EDA/PoC/releases) [![Apache License 2.0](https://img.shields.io/github/license/VLSI-EDA/PoC.svg?style=flat)](LICENSE.md) + This library is published and maintained by **Chair for VLSI Design, Diagnostics and Architecture** - Faculty of Computer Science, Technische Universität Dresden, Germany **http://vlsi-eda.inf.tu-dresden.de** @@ -48,8 +51,8 @@ infrastructure to offer a command line based frontend. ## 2 Quick Start Guide -This **Quick Start Guide** gives a fast and simple introduction into PoC. All topics can be found in the -[Using PoC][201] section at [ReadTheDocs.io][202] with much more details and examples. +This **Quick Start Guide** gives a fast and simple introduction into PoC. All topics can be found in +the [Using PoC][201] section at [ReadTheDocs.io][202] with much more details and examples. ### 2.1 Requirements and Dependencies @@ -84,7 +87,9 @@ Windows. See [Requirements][211] for further details. A coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python. - [OS-VVM][2132] Open Source VHDL Verification Methodology. - - [VUnit][2133] + - [UVVM][2133] + Universal VHDL Verification Methodology. + - [VUnit][2134] An unit testing framework for VHDL. All dependencies are available as GitHub repositories and are linked to PoC as Git submodules into the @@ -92,7 +97,8 @@ All dependencies are available as GitHub repositories and are linked to PoC as G [2131]: https://github.com/potentialventures/cocotb [2132]: https://github.com/JimLewis/OSVVM -[2133]: https://github.com/VUnit/vunit +[2133]: https://github.com/UVVM/UVVM_All +[2134]: https://github.com/VUnit/vunit [201]: http://poc-library.readthedocs.io/en/latest/UsingPoC/index.html [202]: http://poc-library.readthedocs.io/ @@ -102,7 +108,7 @@ All dependencies are available as GitHub repositories and are linked to PoC as G ### 2.2 Download -The PoC-Library can be downloaded as a [zip-file][221] (latest 'release' branch), cloned with `git clone` +The PoC-Library can be downloaded as a [zip-file][221] (latest '{@BRANCH@}' branch), cloned with `git clone` or embedded with `git submodule add` from GitHub. GitHub offers HTTPS and SSH as transfer protocols. See the [Download][222] page for further details. The installation directory is referred to as `PoCRoot`. diff --git a/docs/ChangeLog/2014/index.rst b/docs/ChangeLog/2014/index.rst new file mode 100644 index 00000000..5a16b240 --- /dev/null +++ b/docs/ChangeLog/2014/index.rst @@ -0,0 +1,11 @@ +.. _CHANGE:2014: + +2014 +#### + +.. contents:: Content of this page + :local: + +.. toctree:: + + v0.0.0 diff --git a/docs/ChangeLog/2014/v0.0.0.rst b/docs/ChangeLog/2014/v0.0.0.rst new file mode 100644 index 00000000..fd699aef --- /dev/null +++ b/docs/ChangeLog/2014/v0.0.0.rst @@ -0,0 +1,6 @@ +.. _CHANGE:v0.0.0: + +New in v0.0.0 (16.12.2014) +================================================================================================================================================================ + +* Initial commit diff --git a/docs/ChangeLog/2015/index.rst b/docs/ChangeLog/2015/index.rst new file mode 100644 index 00000000..22bcfb5f --- /dev/null +++ b/docs/ChangeLog/2015/index.rst @@ -0,0 +1,55 @@ +.. _CHANGE:2015: + +2015 +#### + +.. contents:: Content of this page + :local: + +.. only:: html + + .. toctree:: + + v0.18.0 + v0.17.0 + v0.16.0 + v0.15.0 + v0.14.0 + v0.13.0 + v0.12.0 + v0.11.0 + v0.10.0 + v0.9.0 + v0.8.0 + v0.7.0 + v0.6.0 + v0.5.0 + v0.4.0 + v0.3.0 + v0.2.0 + v0.1.0 + + + +.. only:: latex + + .. toctree:: + + v0.1.0 + v0.2.0 + v0.3.0 + v0.4.0 + v0.5.0 + v0.6.0 + v0.7.0 + v0.8.0 + v0.9.0 + v0.10.0 + v0.11.0 + v0.12.0 + v0.13.0 + v0.14.0 + v0.15.0 + v0.16.0 + v0.17.0 + v0.18.0 diff --git a/docs/ChangeLog/2015/v0.1.0.rst b/docs/ChangeLog/2015/v0.1.0.rst new file mode 100644 index 00000000..e417a50f --- /dev/null +++ b/docs/ChangeLog/2015/v0.1.0.rst @@ -0,0 +1,44 @@ +.. :CHANGE:v0.1.0: + +New in v0.1.0 (19.02.2015) +================================================================================================================================================================ + +* New packages: + + * board - common development board configurations + * config - extract configuration parameters from device names + * utils - common utility functions + * strings - a helper package for string handling + * vectors - a helper package for std_logic_vector and std_logic_matrix + * arith + * fifo + +* New modules + + * PoC.arith - arithmetic modules + + * arith_counter_gray + * arith_counter_ring + * arith_div + * arith_prefix_and + * arith_prefix_or + * arith_prng + * arith_scaler + * arith_sqrt + + * PoC.fifo - FIFOs + + * fifo_cc_got + * fifo_cc_got_tempgot + * fifo_cc_got_tempput + * fifo_ic_got + * fifo_glue + * fifo_shift + + * PoC.mem.ocram - On-Chip RAMs + + * ocram_sp + * ocram_sdp + * ocram_esdp + * ocram_tdp + * ocram_wb diff --git a/docs/ChangeLog/2015/v0.10.0.rst b/docs/ChangeLog/2015/v0.10.0.rst new file mode 100644 index 00000000..dfb8c2f1 --- /dev/null +++ b/docs/ChangeLog/2015/v0.10.0.rst @@ -0,0 +1,4 @@ +.. :CHANGE:v0.10.0: + +New in v0.10.0 (23.07.2015) +================================================================================================================================================================ diff --git a/docs/ChangeLog/2015/v0.11.0.rst b/docs/ChangeLog/2015/v0.11.0.rst new file mode 100644 index 00000000..05e55e90 --- /dev/null +++ b/docs/ChangeLog/2015/v0.11.0.rst @@ -0,0 +1,4 @@ +.. :CHANGE:v0.11.0: + +New in v0.11.0 (07.08.2015) +================================================================================================================================================================ diff --git a/docs/ChangeLog/2015/v0.12.0.rst b/docs/ChangeLog/2015/v0.12.0.rst new file mode 100644 index 00000000..933f3448 --- /dev/null +++ b/docs/ChangeLog/2015/v0.12.0.rst @@ -0,0 +1,4 @@ +.. :CHANGE:v0.12.0: + +New in v0.12.0 (25.08.2015) +================================================================================================================================================================ diff --git a/docs/ChangeLog/2015/v0.13.0.rst b/docs/ChangeLog/2015/v0.13.0.rst new file mode 100644 index 00000000..eaa6643c --- /dev/null +++ b/docs/ChangeLog/2015/v0.13.0.rst @@ -0,0 +1,4 @@ +.. :CHANGE:v0.13.0: + +New in v0.13.0 (04.09.2015) +================================================================================================================================================================ diff --git a/docs/ChangeLog/2015/v0.14.0.rst b/docs/ChangeLog/2015/v0.14.0.rst new file mode 100644 index 00000000..364538f1 --- /dev/null +++ b/docs/ChangeLog/2015/v0.14.0.rst @@ -0,0 +1,4 @@ +.. :CHANGE:v0.14.0: + +New in v0.14.0 (28.09.2015) +================================================================================================================================================================ diff --git a/docs/ChangeLog/2015/v0.15.0.rst b/docs/ChangeLog/2015/v0.15.0.rst new file mode 100644 index 00000000..8b1f223d --- /dev/null +++ b/docs/ChangeLog/2015/v0.15.0.rst @@ -0,0 +1,4 @@ +.. :CHANGE:v0.15.0: + +New in v0.15.0 (13.11.2015) +================================================================================================================================================================ diff --git a/docs/ChangeLog/2015/v0.16.0.rst b/docs/ChangeLog/2015/v0.16.0.rst new file mode 100644 index 00000000..ee8f6692 --- /dev/null +++ b/docs/ChangeLog/2015/v0.16.0.rst @@ -0,0 +1,4 @@ +.. :CHANGE:v0.16.0: + +New in v0.16.0 (01.12.2015) +================================================================================================================================================================ diff --git a/docs/ChangeLog/2015/v0.17.0.rst b/docs/ChangeLog/2015/v0.17.0.rst new file mode 100644 index 00000000..bc53b6aa --- /dev/null +++ b/docs/ChangeLog/2015/v0.17.0.rst @@ -0,0 +1,4 @@ +.. :CHANGE:v0.17.0: + +New in v0.17.0 (08.12.2015) +================================================================================================================================================================ diff --git a/docs/ChangeLog/2015/v0.18.0.rst b/docs/ChangeLog/2015/v0.18.0.rst new file mode 100644 index 00000000..84757126 --- /dev/null +++ b/docs/ChangeLog/2015/v0.18.0.rst @@ -0,0 +1,4 @@ +.. :CHANGE:v0.18.0: + +New in v0.18.0 (16.12.2015) +================================================================================================================================================================ diff --git a/docs/ChangeLog/2015/v0.2.0.rst b/docs/ChangeLog/2015/v0.2.0.rst new file mode 100644 index 00000000..5f198e90 --- /dev/null +++ b/docs/ChangeLog/2015/v0.2.0.rst @@ -0,0 +1,46 @@ +.. :CHANGE:v0.2.0: + +New in v0.2.0 (09.03.2015) +================================================================================================================================================================ + +* New packages: + + * xil + * stream + +* New modules: + + * PoC.bus - Modules for busses + + * bus_Arbiter + + * PoC.bus.stream - Modules for the PoC.Stream protocol + + * stream_Buffer + * stream_DeMux + * stream_FrameGenerator + * stream_Mirror + * stream_Mux + * stream_Source + + * PoC.misc.sync - Cross-Clock Synchronizers + + * sync_Reset + * sync_Flag + * sync_Strobe + * sync_Vector + * sync_Command + + * PoC.xil - Xilinx specific modules + + * xil_SyncBits + * xil_SyncReset + * xil_BSCAN + * xil_Reconfigurator + * xil_SystemMonitor_Virtex6 + * xil_SystemMonitor_Series7 + +* Updated packages: + + * utils + * arith diff --git a/docs/ChangeLog/2015/v0.3.0.rst b/docs/ChangeLog/2015/v0.3.0.rst new file mode 100644 index 00000000..ea163cac --- /dev/null +++ b/docs/ChangeLog/2015/v0.3.0.rst @@ -0,0 +1,72 @@ +.. :CHANGE:v0.3.0: + +New in v0.3.0 (31.03.20015) +================================================================================================================================================================ + +* Added Python infrastructure + + * Added platform wrapper scripts (\*.sh, \*.ps1) + * Added IP-core compiler scripts Netlist.py + +* Added Tools + + * Notepad++ syntax file for Xilinx UCF/XCF files + * Git configuration script to register global aliases + +* New packages: + + * components - hardware described as functions + * physical - physical types like frequency, memory and baudrate + * io + +* New modules: + + * PoC.misc + + * misc_FrequencyMeasurement + + * PoC.io - Low-speed I/O interfaces + + * io_7SegmentMux_BCD + * io_7SegmentMux_HEX + * io_FanControl + * io_PulseWidthModulation + * io_TimingCounter + * io_Debounce + * io_GlitchFilter + +* New IP-cores: + + * PoC.xil - Xilinx specific modules + + * xil_ChipScopeICON_1 + * xil_ChipScopeICON_2 + * xil_ChipScopeICON_3 + * xil_ChipScopeICON_4 + * xil_ChipScopeICON_6 + * xil_ChipScopeICON_7 + * xil_ChipScopeICON_8 + * xil_ChipScopeICON_9 + * xil_ChipScopeICON_10 + * xil_ChipScopeICON_11 + * xil_ChipScopeICON_12 + * xil_ChipScopeICON_13 + * xil_ChipScopeICON_14 + * xil_ChipScopeICON_15 + +* New constraint files: + + * ML605 + * KC705 + * VC707 + * MetaStability + * xil_Sync + +* Updated packages: + + * board + * config + +* Updated modules: + + * xil_BSCAN diff --git a/docs/ChangeLog/2015/v0.4.0.rst b/docs/ChangeLog/2015/v0.4.0.rst new file mode 100644 index 00000000..b96307c3 --- /dev/null +++ b/docs/ChangeLog/2015/v0.4.0.rst @@ -0,0 +1,50 @@ +.. :CHANGE:v0.4.0: + +New in v0.4 (29.04.2015) +================================================================================================================================================================ + +* New Python infrastructure + + * Added simulators for: + + * GHDL + GTKWave + * Mentor Graphic QuestaSim + * Xilinx ISE Simulator + * Xilinx Vivado Simulator + +* New packages: + + * simulation + +* New modules: + + * PoC.comm - communication modules + + * comm_crc + + * PoC.comm.remote - remote communication modules + + * remote_terminal_control + +* New testbenches: + + * arith_addw_tb + * arith_counter_bcd_tb + * arith_prefix_and_tb + * arith_prefix_or_tb + * arith_prng_tb + +* Updated packages: + + * board + * config + * physical + * strings + * utils + +* Updated modules: + + * io_Debounce + * misc_FrequencyMeasurement + * sync_Bits + * sync_Reset diff --git a/docs/ChangeLog/2015/v0.5.0.rst b/docs/ChangeLog/2015/v0.5.0.rst new file mode 100644 index 00000000..cf1a8a3f --- /dev/null +++ b/docs/ChangeLog/2015/v0.5.0.rst @@ -0,0 +1,25 @@ +.. :CHANGE:v0.5.0: + +New in v0.5 (27.05.2015) +================================================================================================================================================================ + +* Updated Python infrastructure +* New testbenches: + + * sync_Reset_tb + * sync_Flag_tb + * sync_Strobe_tb + * sync_Vector_tb + * sync_Command_tb + +* Updated modules: + + * sync_Vector + * sync_Command + +* Updated packages: + + * physical + * utils + * vectors + * xil diff --git a/docs/ChangeLog/2015/v0.6.0.rst b/docs/ChangeLog/2015/v0.6.0.rst new file mode 100644 index 00000000..b7e56019 --- /dev/null +++ b/docs/ChangeLog/2015/v0.6.0.rst @@ -0,0 +1,4 @@ +.. :CHANGE:v0.6.0: + +New in v0.6 (09.06.2015) +================================================================================================================================================================ diff --git a/docs/ChangeLog/2015/v0.7.0.rst b/docs/ChangeLog/2015/v0.7.0.rst new file mode 100644 index 00000000..e205edeb --- /dev/null +++ b/docs/ChangeLog/2015/v0.7.0.rst @@ -0,0 +1,4 @@ +.. :CHANGE:v0.7.0: + +New in v0.7 (27.06.2015) +================================================================================================================================================================ diff --git a/docs/ChangeLog/2015/v0.8.0.rst b/docs/ChangeLog/2015/v0.8.0.rst new file mode 100644 index 00000000..8e02f6f2 --- /dev/null +++ b/docs/ChangeLog/2015/v0.8.0.rst @@ -0,0 +1,4 @@ +.. :CHANGE:v0.8.0: + +New in v0.8.0 (03.07.2015) +================================================================================================================================================================ diff --git a/docs/ChangeLog/2015/v0.9.0.rst b/docs/ChangeLog/2015/v0.9.0.rst new file mode 100644 index 00000000..629ee965 --- /dev/null +++ b/docs/ChangeLog/2015/v0.9.0.rst @@ -0,0 +1,4 @@ +.. :CHANGE:v0.9.0: + +New in v0.9.0 (21.07.2015) +================================================================================================================================================================ diff --git a/docs/ChangeLog/2016/index.rst b/docs/ChangeLog/2016/index.rst new file mode 100644 index 00000000..7ce94019 --- /dev/null +++ b/docs/ChangeLog/2016/index.rst @@ -0,0 +1,33 @@ +.. _CHANGE:2016: + +2016 +#### + +.. contents:: Content of this page + :local: + +.. only:: html + + .. toctree:: + + v1.x + v1.1.0 + v1.0.1 + v1.0.0 + v0.21.0 + v0.20.0 + v0.19.0 + + + +.. only:: latex + + .. toctree:: + + v0.19.0 + v0.20.0 + v0.21.0 + v1.0.0 + v1.0.1 + v1.1.0 + v1.x diff --git a/docs/ChangeLog/2016/v0.19.0.rst b/docs/ChangeLog/2016/v0.19.0.rst new file mode 100644 index 00000000..8d42c3c3 --- /dev/null +++ b/docs/ChangeLog/2016/v0.19.0.rst @@ -0,0 +1,4 @@ +.. _CHANGE:v0.10: + +New in 0.19 (16.01.2016) +================================================================================================================================================================ diff --git a/docs/ChangeLog/2016/v0.20.0.rst b/docs/ChangeLog/2016/v0.20.0.rst new file mode 100644 index 00000000..18a9577c --- /dev/null +++ b/docs/ChangeLog/2016/v0.20.0.rst @@ -0,0 +1,4 @@ +.. _CHANGE:v0.20: + +New in 0.20 (16.01.2016) +================================================================================================================================================================ diff --git a/docs/ChangeLog/2016/v0.21.0.rst b/docs/ChangeLog/2016/v0.21.0.rst new file mode 100644 index 00000000..389c98b7 --- /dev/null +++ b/docs/ChangeLog/2016/v0.21.0.rst @@ -0,0 +1,4 @@ +.. _CHANGE:v0.21: + +New in 0.21 (17.02.2016) +================================================================================================================================================================ diff --git a/docs/ChangeLog/2016/v1.0.0.rst b/docs/ChangeLog/2016/v1.0.0.rst new file mode 100644 index 00000000..c569c0dd --- /dev/null +++ b/docs/ChangeLog/2016/v1.0.0.rst @@ -0,0 +1,107 @@ +.. _CHANGE:v1.0.0: + +New in 1.0 (13.05.2016) +================================================================================================================================================================ + +* Python Infrastructure (Completely Reworked) + + * New Requirements + + * Python 3.5 + * py-flags + + * New command line interface + + * Synopsis: ``poc.sh|ps1 [common options] [options]`` + * Removed task specific wrapper scripts: ``testbench.sh|ps1``, ``netlist.sh|ps1``, ... + * Updated ``wrapper.ps1`` and ``wrapper.sh`` files + + * New ini-file database + + * + * Added a new config.boards.ini file to list known boards (real and virtual ones) + + * New parser for ``*.files`` files + + * conditional compiling (if-then-elseif-else) + * include statement - include other ``*.files`` files + * library statement - reference external VHDL libraries + * prepared for Cocotb testbenches + + * New parser for ``*.rules`` files + + * + + * All Tool Flows + + * Unbuffered outputs from vendor tools (realtime output to stdout from subprocess) + * Output filtering from vendor tools + + * verbose message suppression + * error and warning message highlighting + * abort flow on vendor tool errors + + * All Simulators + + * Run testbenches for different board or device configurations (see ``--board`` and ``--device`` command line options) + + * New Simulators + + * Aldec Active-HDL support (no GUI support) + + * Tested with Active-HDL from Lattice Diamond + * Tested with Active-HDL Student Edition + + * Cocotb (with QuestaSim backend on Linux) + + * New Synthesizers + + * Altera Quartus II and Quartus Prime + + * Command: ``quartus`` + + * Lattice Synthesis Engine (LSE) from Diamond + + * Command: ``lse`` + + * Xilinx Vivado + + * Command: ``vivado`` + + * GHDL + + * GHDLSimulator can distinguish different backends (mcode, gcc, llvm) + * Pre-compiled library support for GHDL + + * QuestaSim / ModelSim Altera Edition + + * Pre-compiled library support for GHDL + + * Vivado Simulator + + * Tested Vivado Simulator 2016.1 (xSim) with PoC -> still produces errors or false results + +* New Entities + + * + +* New Testbenches + + * + +* New Constraints + + * + +* New dependencies + + * Embedded Cocotb in ``/lib/cocotb`` + +* Shipped Tool and Helper Scripts + + * Updated and new Notepad++ syntax files + * Pre-compiled vendor library support + + * Added a new ``/temp/precompiled`` folder for precompiled vendor libraries + * QuestaSim supports Altera QuartusII, Xilinx ISE and Xilinx Vivado libraries + * GHDL supports Altera QuartusII, Xilinx ISE and Xilinx Vivado libraries diff --git a/docs/ChangeLog/2016/v1.0.1.rst b/docs/ChangeLog/2016/v1.0.1.rst new file mode 100644 index 00000000..888b37cb --- /dev/null +++ b/docs/ChangeLog/2016/v1.0.1.rst @@ -0,0 +1,63 @@ +.. _CHANGE:v1.0.1: + + + +New in 1.x (upcomming) +======================= + +Already documented changes are available on the ``release`` branch at GitHub. + +* Python Infrastructure + + * Common changes + + * The classes ``Simulator`` and ``Compiler`` now share common methods in base class called ``Shared``. + + * ``*.files`` Parser + + * Implemented path expressions: sub-directory expression, concatenate expression + * Implemented InterpolateLiteral: access database keys in ``*.files`` files + * New Path statement, which defines a path constant calculated from a path expression + * Replaced string arguments in statements with path expressions if the desired string was a path + * Replaced simple StringToken matches with Identifier expressions + + * All Simulators + + * + + * All Compilers + + * + + * GHDL + + * Reduced ``-P`` parameters: Removed doublings + +* Documentation + + * + +* VHDL common packages + + * + +* VHDL Simulation helpers + + * Mark a testbench as failed if (registered) processes are active while finilize is called + +* New Entities + + * + +* New Testbenches + + * + +* New Constraints + + * + +* Shipped Tool and Helper Scripts + + * Updated and new Notepad++ syntax files + diff --git a/docs/ChangeLog/2016/v1.1.0.rst b/docs/ChangeLog/2016/v1.1.0.rst new file mode 100644 index 00000000..1de07e67 --- /dev/null +++ b/docs/ChangeLog/2016/v1.1.0.rst @@ -0,0 +1,62 @@ +.. _CHANGE:v1.1.0: + + +New in 1.x (upcomming) +======================= + +Already documented changes are available on the ``release`` branch at GitHub. + +* Python Infrastructure + + * Common changes + + * The classes ``Simulator`` and ``Compiler`` now share common methods in base class called ``Shared``. + + * ``*.files`` Parser + + * Implemented path expressions: sub-directory expression, concatenate expression + * Implemented InterpolateLiteral: access database keys in ``*.files`` files + * New Path statement, which defines a path constant calculated from a path expression + * Replaced string arguments in statements with path expressions if the desired string was a path + * Replaced simple StringToken matches with Identifier expressions + + * All Simulators + + * + + * All Compilers + + * + + * GHDL + + * Reduced ``-P`` parameters: Removed doublings + +* Documentation + + * + +* VHDL common packages + + * + +* VHDL Simulation helpers + + * Mark a testbench as failed if (registered) processes are active while finilize is called + +* New Entities + + * + +* New Testbenches + + * + +* New Constraints + + * + +* Shipped Tool and Helper Scripts + + * Updated and new Notepad++ syntax files + diff --git a/docs/ChangeLog/2016/v1.x.rst b/docs/ChangeLog/2016/v1.x.rst new file mode 100644 index 00000000..f690763d --- /dev/null +++ b/docs/ChangeLog/2016/v1.x.rst @@ -0,0 +1,69 @@ +.. _CHANGE:v1.x: + +New in 1.x (upcoming) +======================= + +Already documented changes are available on the ``release`` branch at GitHub. + +* VHDL common packages +* VHDL Simulation helpers + +* New Entities + + * :ref:`IP:ocram_sdp_wf` + * :ref:`IP:ocram_tdp_wf` + * :ref:`IP:cache_par2` + * :ref:`IP:cache_cpu` + * :ref:`IP:cache_mem` + * Simulation helper :ref:`IP:ocram_tdp_sim` + +* Updated Entities + + * Interface of :ref:`IP:cache_tagunit_par` changed slightly. + * New port "write-mask" in :ref:`IP:ddr3_mem2mig_adapter_Series7`. + * New port "write-mask" in :ref:`IP:ddr2_mem2mig_adapter_Spartan6`. + * Fixed :ref:`IP:dstruct_deque` + +* New Testbenches + + * Testbench for :ref:`IP:ocram_sdp_wf` + * Testbench for :ref:`IP:ocram_tdp_wf` + * Testbench for :ref:`IP:cache_par2` + * Testbench for :ref:`IP:cache_cpu` + * Testbench for :ref:`IP:cache_mem` + +* Updated Testbenches + + * Testbench for :ref:`IP:ocram_sdp` + * Testbench for :ref:`IP:ocram_esdp` + * Testbench for :ref:`IP:ocram_tdp` + * Testbench for :ref:`IP:sortnet_BitonicSort` + * Testbench for :ref:`IP:sortnet_OddEvenSort` + * Testbench for :ref:`IP:sortnet_OddEvenMergeSort` + +* New Constraints +* Updated Constraints +* Shipped Tool and Helper Scripts +* Python Infrastructure + + * Common changes + * All Simulators + * Aldec Active-HDL + * GHDL + * Mentor QuestaSim + * Xilinx ISE Simulator + * Xilinx Vivado Simulator + * All Compilers + * Altera Quartus Synthesis + * Lattice Diamond (LSE) + * Xilinx ISE (XST) + * Xilinx ISE Core Generator + * Xilinx Vivado Synthesis + +* Continuous Integration + + * Implemented a simple Python infrastructe test on AppVeyor + +* Documentation + + * Improved PDF rendering diff --git a/docs/ChangeLog/index.rst b/docs/ChangeLog/index.rst new file mode 100644 index 00000000..f4854538 --- /dev/null +++ b/docs/ChangeLog/index.rst @@ -0,0 +1,24 @@ +.. _CHANGE: + +Change Log +########## + +.. only:: html + + .. toctree:: + + 2016/index + 2015/index + 2014/index + + + +.. only:: latex + + .. toctree:: + + 2014/index + 2015/index + 2016/index + +.. # 2017/index diff --git a/docs/ChangeLog/template.rst b/docs/ChangeLog/template.rst new file mode 100644 index 00000000..9980438c --- /dev/null +++ b/docs/ChangeLog/template.rst @@ -0,0 +1,36 @@ +.. # This file is a template for new release notes. It's marked as orphan to suppress warnings. + +:orphan: + +New in 1.x (upcomming) +======================= + +Already documented changes are available on the ``release`` branch at GitHub. + +* VHDL common packages +* VHDL Simulation helpers +* New Entities +* Updated Entities +* New Testbenches +* Updated Testbenches +* New Constraints +* Updated Constraints +* Shipped Tool and Helper Scripts +* Python Infrastructure + + * Common changes + * All Simulators + * Aldec Active-HDL + * GHDL + * Mentor QuestaSim + * Xilinx ISE Simulator + * Xilinx Vivado Simulator + * All Compilers + * Altera Quartus Synthesis + * Lattice Diamond (LSE) + * Xilinx ISE (XST) + * Xilinx ISE Core Generator + * Xilinx Vivado Synthesis + +* Continuous Integration +* Documentation diff --git a/docs/ConstraintFiles/index.rst b/docs/ConstraintFiles/index.rst index 294ef1e9..b593e029 100644 --- a/docs/ConstraintFiles/index.rst +++ b/docs/ConstraintFiles/index.rst @@ -1,61 +1,54 @@ +.. _CONST: Constraint Files ################ -IP Core Contraint Files -*********************** +IP Core Constraint Files +************************ - * fifo - * misc - * sync - * net - * eth +* fifo +* misc -.. only:: PoCInternal + * sync - * sata - * xilinx +* net + + * eth -.. #PoCInternal .. toctree:: :hidden: - fifo/index - misc/index - net/index + fifo + misc + net -.. only:: PoCInternal - .. toctree:: - :hidden: +Board Constraint Files +********************** - sata/index -.. #PoCInternal +* Altera Boards + * Cyclone III + * Stratix IV + * Stratix V -Board Contraint Files -********************* +* Lattice Boards +* Xilinx Boards - * Altera Boards - * Cyclone III - * Stratix IV - * Stratix V - * Lattice Boards - * Xilinx Boards - * Spartan-3 Boards - * Spartan-6 Boards - * Artix-7 - * Kintex-7 - * Virtex-5 - * Virtex-6 - * Virtex-7 - * Zynq-7000 + * Artix-7 + * Kintex-7 + * Spartan-3 Boards + * Spartan-6 Boards + * Virtex-5 + * Virtex-6 + * Virtex-7 + * Zynq-7000 .. toctree:: :hidden: - Altera/index - Lattice/index - Xilinx/index + Altera + Lattice + Xilinx diff --git a/docs/Examples/index.rst b/docs/Examples/index.rst new file mode 100644 index 00000000..eef3b790 --- /dev/null +++ b/docs/Examples/index.rst @@ -0,0 +1,10 @@ +.. _EX: + +Examples +######## + +.. note:: + + Under construction. + +PoC-Exmaples repository on GitHub. diff --git a/docs/GetInvolved/Authors.rst b/docs/GetInvolved/Authors.rst deleted file mode 100644 index bb7b061f..00000000 --- a/docs/GetInvolved/Authors.rst +++ /dev/null @@ -1,21 +0,0 @@ -.. - Include this file. - -========================= ============================================================ -Contributor [#f1]_ Contact E-Mail -========================= ============================================================ -Genßler, Paul paul.genssler@tu-dresden.de -Köhler, Steffen steffen.koehler@tu-dresden.de -Lehmann, Patrick [#f2]_ patrick.lehmann@tu-dresden.de; paebbels@gmail.com -Preußer, Thomas B. [#f2]_ thomas.preusser@tu-dresden.de; thomas.preusser@utexas.edu -Reichel, Peter peter.reichel@eas.iis.fraunhofer.de; peter@peterreichel.info -Schirok, Jan janschirok@gmx.net -Voß, Jens jens.voss@mailbox.tu-dresden.de -Zabel, Martin [#f2]_ martin.zabel@tu-dresden.de -========================= ============================================================ - - -.. rubric:: Footnotes - -.. [#f1] In alphabetical order. -.. [#f2] Maintainer. diff --git a/docs/GetInvolved/index.rst b/docs/GetInvolved/index.rst index c8ad85ae..a1986e8c 100644 --- a/docs/GetInvolved/index.rst +++ b/docs/GetInvolved/index.rst @@ -3,17 +3,17 @@ Get Involved ############ A first step might be to use and explore PoC and it's infrastructure in an own -project. Moreover, we encurage to read our `online help `_ -which covers all aspects from quickstart example up to detailed IP core -documentation. While using PoC, you might discover issues or missing feature. -Please report them as `listed below <#report-a-bug>`_. If you have an -interresting project, please send us feedback or get listed on our -:doc:`Who uses PoC? ` +project. Moreover, we encurage to read our online help which covers all aspects +from quickstart example up to detailed IP core documentation. While using PoC, +you might discover issues or missing feature. Please report them as +`listed below <#report-a-bug>`_. If you have an interresting project, please +send us feedback or get listed on our :doc:`Who uses PoC? ` +page. If you are more familiar with PoC and it's components, you might start asking youself how components internally work. Please read our more advanced topics in the online help, read our inline source code comments or start a discussion on -`Gitter <#discuss-with-us-on-gitter>`_ to ask us directly. +`Gitter <#talk-to-us-on-gitter>`_ to ask us directly. Now you should be very familiar with our work and you might be interessted in developing own components and contribute them to the main repository. See the @@ -35,7 +35,7 @@ Report a Bug Please report issues of any kind in our Git provider's issue tracker. This allows us to categorize issues into groups and assign developers to them. You can track -the issue's state and see how it's getting closed. All enhancements and feature +the issue's state and see how it's getting solved. All enhancements and feature requests are tracked on GitHub at `GitHub Issues `_. @@ -58,7 +58,7 @@ Talk to us on Gitter You can chat with us on `Gitter `_ in our Giiter Room `VLSI-EDA/PoC `_. You can use Gitter for free -with your GitHub account. +with your existing GitHub or Twitter account. Contributers License Agreement @@ -66,13 +66,13 @@ Contributers License Agreement We require all contributers to sign a Contributor License Agreement (CLA). If you don't know whatfore a CLA is needed and how it prevents legal issues on both -sides, read `this short blog `_ post.PoC -uses the :doc:`Apache Contributor License Agreement ` +sides, read `this short blog `_ post. PoC +uses the :doc:`Apache Contributor License Agreement ` to match the :doc:`Apache License 2.0 `. So to get started, `sign the Contributor License Agreement (CLA) `_ -at `CLAHub.com `_. You can can login with your GitHub -account. +at `CLAHub.com `_. You can authenticate yourself with +an existing GitHub account. Contribute to PoC @@ -82,21 +82,23 @@ Contribute to PoC Contibuting source code via Git is very easy. We don't provide direct write access to our repositories. Git offers the fork and pull-request philosophy, -which means: You clone a repository, provide you changes in your own repository -and notify us about outstanding changes via pull-requests. +which means: You clone a repository, provide your changes in your own repository +and notify us about outstanding changes via a pull-requests. We will then review +your proposed changes and integrate them into our repository. -The steps 1 to 5 are done only once for setting up a forked repository. +*Steps 1 to 5 are done only once for setting up a forked repository.* -1. Fork our Repository -====================== +1. Fork the PoC Repository +========================== .. image:: https://img.shields.io/github/forks/VLSI-EDA/PoC.svg :target: https://github.com/VLSI-EDA/PoC/network/members Git repositories can be cloned on a Git provider's server. This procedure is -called *forking*. This allows Git providers to track the repositories network -and if repositories are related to each other and if pull-requests are possible. +called *forking*. This allows Git providers to track the repository's network, +check if repositories are related to each other and notify if pull-requests are +available. Fork our repository ``VLSI-EDA/PoC`` on GitHub into your or your's Git organisation's account. In the following the forked repository is referenced as @@ -105,7 +107,7 @@ organisation's account. In the following the forked repository is referenced as 2. Clone the new Fork ===================== -Clone this new fork to your machine. See :doc:`Downloading via git clone ` +Clone this new fork to your machine. See :ref:`Downloading via Git clone ` for more details on how to clone PoC. If you have already cloned PoC, then you can setup the new fork as an additional *remote*. You should set ``VLSI-EDA/PoC`` as fetch target and the new fork ``/PoC`` as push target. @@ -140,19 +142,18 @@ Checkout the ``master`` or ``release`` branch and maybe stash outstanding change .. code-block:: PowerShell cd PoCRoot - git checkout master + git checkout release 4. Setup PoC for Developers =========================== -Run PoC's :doc:`configuration routines ` and setup -the developer tools. You can skip (:kbd:`P`) all tool chain questions until you -reach the Git questions. +Run PoC's :ref:`configuration routines ` and setup the +developer tools. .. code-block:: PowerShell cd PoCRoot - .\PoC.ps1 configure + .\PoC.ps1 configure git 5. Create your own ``master`` Branch ==================================== @@ -177,11 +178,11 @@ branch names: +-----------------+--------------------------------------+ | Branch name | Description | +=================+======================================+ -| bugfix-utils | Fixes a bug in ``utils.vhdl`` | +| bugfix-utils | Fixes a bug in ``utils.vhdl``. | +-----------------+--------------------------------------+ -| docs-spelling | Fixes the documentation | +| docs-spelling | Fixes the documentation. | +-----------------+--------------------------------------+ -| spi-controller | A new SPI controller implementation | +| spi-controller | A new SPI controller implementation. | +-----------------+--------------------------------------+ @@ -194,7 +195,8 @@ branch names: 7. Commit and Push Changes ========================== -Commit your porposed changes to your feature branch and push all changes to GitHub. + +Commit your porposed changes onto your feature branch and push all changes to GitHub. .. code-block:: PowerShell @@ -212,7 +214,7 @@ Commit your porposed changes to your feature branch and push all changes to GitH :target: https://github.com/VLSI-EDA/PoC/pulls Go to your forked repository and klick on "Compare and Pull-Request" or go to -our PoC repository and create a new `pull request `_. +our PoC repository and create a new `pull request `_. If this is your first Pull-Request, you need to sign our Contributers License Agreement (CLA). @@ -233,5 +235,22 @@ story on how you use PoC. List of Contributers ******************** -.. include:: ./Authors.rst - +========================= ============================================================ +Contributor [#f1]_ Contact E-Mail +========================= ============================================================ +Genßler, Paul paul.genssler@tu-dresden.de +Köhler, Steffen steffen.koehler@tu-dresden.de +Lehmann, Patrick [#f2]_ patrick.lehmann@tu-dresden.de; paebbels@gmail.com +Preußer, Thomas B. [#f2]_ thomas.preusser@tu-dresden.de; thomas.preusser@utexas.edu +Reichel, Peter peter.reichel@eas.iis.fraunhofer.de; peter@peterreichel.info +Schirok, Jan janschirok@gmx.net +Voß, Jens jens.voss@mailbox.tu-dresden.de +Zabel, Martin [#f2]_ martin.zabel@tu-dresden.de +========================= ============================================================ + +-------------------------------------------------------------------------------- + +.. rubric:: Footnotes + +.. [#f1] In alphabetical order. +.. [#f2] Maintainer. diff --git a/docs/PoC/alt/index.rst b/docs/IPCores/alt/index.rst similarity index 70% rename from docs/PoC/alt/index.rst rename to docs/IPCores/alt/index.rst index a54a3239..c0752f3f 100644 --- a/docs/PoC/alt/index.rst +++ b/docs/IPCores/alt/index.rst @@ -1,5 +1,6 @@ +.. _NS:alt: -alt -=== +PoC.alt +======== .. TODO:: This namespace is reserved for Altera specific entities. diff --git a/docs/IPCores/arith/arith.pkg.rst b/docs/IPCores/arith/arith.pkg.rst new file mode 100644 index 00000000..4857abab --- /dev/null +++ b/docs/IPCores/arith/arith.pkg.rst @@ -0,0 +1,47 @@ +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith.pkg.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` + +.. _PKG:arith: + +PoC.arith Package +================= + +This package holds all component declarations for this namespace. + +.. rubric:: Exported Enumerations + +* ``tArch`` +* ``tBlocking`` +* ``tSkipping`` + +.. rubric:: Exported Functions + +* ``arith_div_latency`` + +.. rubric:: Exported Components + +* :ref:`PoC.arith.addw ` +* PoC.arith.carrychain_inc_xilinx +* :ref:`PoC.arith.counter_bcd ` +* :ref:`PoC.arith.counter_gray ` +* :ref:`PoC.arith.div ` +* :ref:`PoC.arith.firstone ` +* PoC.arith.inc_ovcy_xilinx +* :ref:`PoC.arith.muls_wide ` +* PoC.arith.prefix_and_xilinx +* PoC.arith.prefix_or_xilinx +* :ref:`PoC.arith.prng ` +* :ref:`PoC.arith.same ` +* :ref:`PoC.arith.sqrt ` + +.. only:: latex + + Source file: :pocsrc:`arith.pkg.vhdl ` diff --git a/docs/IPCores/arith/arith_addw.rst b/docs/IPCores/arith/arith_addw.rst new file mode 100644 index 00000000..80f450fd --- /dev/null +++ b/docs/IPCores/arith/arith_addw.rst @@ -0,0 +1,60 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:arith_addw: + +PoC.arith.addw +############## + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_addw.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_addw_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +Implements wide addition providing several options all based +on an adaptation of a carry-select approach. + +References: + +* Hong Diep Nguyen and Bogdan Pasca and Thomas B. Preusser: + FPGA-Specific Arithmetic Optimizations of Short-Latency Adders, + FPL 2011. + -> ARCH: AAM, CAI, CCA + -> SKIPPING: CCC + +* Marcin Rogawski, Kris Gaj and Ekawat Homsirikamol: + A Novel Modular Adder for One Thousand Bits and More + Using Fast Carry Chains of Modern FPGAs, FPL 2014. + -> ARCH: PAI + -> SKIPPING: PPN_KS, PPN_BK + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/arith/arith_addw.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 54-71 + + + +.. only:: latex + + Source file: :pocsrc:`arith/arith_addw.vhdl ` diff --git a/docs/IPCores/arith/arith_bcdcollect.rst b/docs/IPCores/arith/arith_bcdcollect.rst new file mode 100644 index 00000000..a8aec2c6 --- /dev/null +++ b/docs/IPCores/arith/arith_bcdcollect.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:arith_bcdcollect: + +PoC.arith.bcdcollect +#################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_bcdcollect.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_bcdcollect_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/arith/arith_bcdcollect.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 37-55 + + + +.. only:: latex + + Source file: :pocsrc:`arith/arith_bcdcollect.vhdl ` diff --git a/docs/IPCores/arith/arith_carrychain_inc.rst b/docs/IPCores/arith/arith_carrychain_inc.rst new file mode 100644 index 00000000..03f8e481 --- /dev/null +++ b/docs/IPCores/arith/arith_carrychain_inc.rst @@ -0,0 +1,47 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:arith_carrychain_inc: + +PoC.arith.carrychain_inc +######################## + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_carrychain_inc.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_carrychain_inc_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +This is a generic carry-chain abstraction for increment by one operations. + +Y <= X + (0...0) & Cin + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/arith/arith_carrychain_inc.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 43-52 + + + +.. only:: latex + + Source file: :pocsrc:`arith/arith_carrychain_inc.vhdl ` diff --git a/docs/PoC/arith/arith_cca.rst b/docs/IPCores/arith/arith_cca.rst similarity index 100% rename from docs/PoC/arith/arith_cca.rst rename to docs/IPCores/arith/arith_cca.rst diff --git a/docs/IPCores/arith/arith_convert_bin2bcd.rst b/docs/IPCores/arith/arith_convert_bin2bcd.rst new file mode 100644 index 00000000..ca4322e6 --- /dev/null +++ b/docs/IPCores/arith/arith_convert_bin2bcd.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:arith_convert_bin2bcd: + +PoC.arith.convert_bin2bcd +######################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_convert_bin2bcd.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_convert_bin2bcd_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/arith/arith_convert_bin2bcd.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 40-58 + + + +.. only:: latex + + Source file: :pocsrc:`arith/arith_convert_bin2bcd.vhdl ` diff --git a/docs/IPCores/arith/arith_counter_bcd.rst b/docs/IPCores/arith/arith_counter_bcd.rst new file mode 100644 index 00000000..33ffbb93 --- /dev/null +++ b/docs/IPCores/arith/arith_counter_bcd.rst @@ -0,0 +1,56 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:arith_counter_bcd: + +PoC.arith.counter_bcd +##################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_counter_bcd.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_counter_bcd_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +Counter with output in binary coded decimal (BCD). The number of BCD digits +is configurable by ``DIGITS``. + +All control signals (reset ``rst``, increment ``inc``) are high-active and +synchronous to clock ``clk``. The output ``val`` is the current counter +state. Groups of 4 bit represent one BCD digit. The lowest significant digit +is specified by ``val(3 downto 0)``. + +.. TODO:: + + * implement a ``dec`` input for decrementing + * implement a ``load`` input to load a value + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/arith/arith_counter_bcd.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 51-61 + + + +.. only:: latex + + Source file: :pocsrc:`arith/arith_counter_bcd.vhdl ` diff --git a/docs/IPCores/arith/arith_counter_free.rst b/docs/IPCores/arith/arith_counter_free.rst new file mode 100644 index 00000000..b4b702e8 --- /dev/null +++ b/docs/IPCores/arith/arith_counter_free.rst @@ -0,0 +1,52 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:arith_counter_free: + +PoC.arith.counter_free +###################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_counter_free.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_counter_free_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +Implements a free-running counter that generates a strobe signal every +DIVIDER-th cycle the increment input was asserted. There is deliberately no +output or specification of the counter value so as to allow an implementation +to optimize as much as possible. + +The implementation guarantees a strobe output directly from a register. It is +asserted exactly for one clock after DIVIDER cycles of an asserted increment +input have been observed. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/arith/arith_counter_free.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 41-53 + + + +.. only:: latex + + Source file: :pocsrc:`arith/arith_counter_free.vhdl ` diff --git a/docs/IPCores/arith/arith_counter_gray.rst b/docs/IPCores/arith/arith_counter_gray.rst new file mode 100644 index 00000000..5078f9ba --- /dev/null +++ b/docs/IPCores/arith/arith_counter_gray.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:arith_counter_gray: + +PoC.arith.counter_gray +###################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_counter_gray.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_counter_gray_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/arith/arith_counter_gray.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 38-51 + + + +.. only:: latex + + Source file: :pocsrc:`arith/arith_counter_gray.vhdl ` diff --git a/docs/IPCores/arith/arith_counter_ring.rst b/docs/IPCores/arith/arith_counter_ring.rst new file mode 100644 index 00000000..603fcf24 --- /dev/null +++ b/docs/IPCores/arith/arith_counter_ring.rst @@ -0,0 +1,48 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:arith_counter_ring: + +PoC.arith.counter_ring +###################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_counter_ring.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_counter_ring_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +This module implements an up/down ring-counter with loadable initial value +(``seed``) on reset. The counter can be configured to a Johnson counter by +enabling ``INVERT_FEEDBACK``. The number of counter bits is configurable with +``BITS``. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/arith/arith_counter_ring.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 41-54 + + + +.. only:: latex + + Source file: :pocsrc:`arith/arith_counter_ring.vhdl ` diff --git a/docs/IPCores/arith/arith_div.rst b/docs/IPCores/arith/arith_div.rst new file mode 100644 index 00000000..71963fa9 --- /dev/null +++ b/docs/IPCores/arith/arith_div.rst @@ -0,0 +1,49 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:arith_div: + +PoC.arith.div +############# + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_div.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_div_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +Implementation of a Non-Performing restoring divider with a configurable radix. +The multi-cycle division is controlled by 'start' / 'rdy'. A new division is +started by asserting 'start'. The result Q = A/D is available when 'rdy' +returns to '1'. A division by zero is identified by output Z. The Q and R +outputs are undefined in this case. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/arith/arith_div.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 38-61 + + + +.. only:: latex + + Source file: :pocsrc:`arith/arith_div.vhdl ` diff --git a/docs/IPCores/arith/arith_firstone.rst b/docs/IPCores/arith/arith_firstone.rst new file mode 100644 index 00000000..c693f15e --- /dev/null +++ b/docs/IPCores/arith/arith_firstone.rst @@ -0,0 +1,58 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:arith_firstone: + +PoC.arith.firstone +################## + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_firstone.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_firstone_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +Computes from an input word, a word of the same size that has, at most, +one bit set. The output contains a set bit at the position of the rightmost +set bit of the input if and only if such a set bit exists in the input. + +A typical use case for this computation would be an arbitration over +requests with a fixed and strictly ordered priority. The terminology of +the interface assumes this use case and provides some useful extras: + +* Set tin <= '0' (no input token) to disallow grants altogether. +* Read tout (unused token) to see whether or any grant was issued. +* Read bin to obtain the binary index of the rightmost detected one bit. + The index starts at zero (0) in the rightmost bit position. + +This implementation uses carry chains for wider implementations. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/arith/arith_firstone.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 50-61 + + + +.. only:: latex + + Source file: :pocsrc:`arith/arith_firstone.vhdl ` diff --git a/docs/IPCores/arith/arith_muls_wide.rst b/docs/IPCores/arith/arith_muls_wide.rst new file mode 100644 index 00000000..380105ea --- /dev/null +++ b/docs/IPCores/arith/arith_muls_wide.rst @@ -0,0 +1,47 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:arith_muls_wide: + +PoC.arith.muls_wide +################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_muls_wide.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_muls_wide_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +Signed wide multiplication spanning multiple DSP or MULT blocks. +Small partial products are calculated through LUTs. +For detailed documentation see below. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/arith/arith_muls_wide.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 38-49 + + + +.. only:: latex + + Source file: :pocsrc:`arith/arith_muls_wide.vhdl ` diff --git a/docs/IPCores/arith/arith_prefix_and.rst b/docs/IPCores/arith/arith_prefix_and.rst new file mode 100644 index 00000000..18747671 --- /dev/null +++ b/docs/IPCores/arith/arith_prefix_and.rst @@ -0,0 +1,47 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:arith_prefix_and: + +PoC.arith.prefix_and +#################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_prefix_and.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_prefix_and_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +Prefix AND computation: +``y(i) <= '1' when x(i downto 0) = (i downto 0 => '1') else '0';`` +This implementation uses carry chains for wider implementations. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/arith/arith_prefix_and.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 43-51 + + + +.. only:: latex + + Source file: :pocsrc:`arith/arith_prefix_and.vhdl ` diff --git a/docs/IPCores/arith/arith_prefix_or.rst b/docs/IPCores/arith/arith_prefix_or.rst new file mode 100644 index 00000000..e7d41994 --- /dev/null +++ b/docs/IPCores/arith/arith_prefix_or.rst @@ -0,0 +1,47 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:arith_prefix_or: + +PoC.arith.prefix_or +################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_prefix_or.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_prefix_or_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +Prefix OR computation: +``y(i) <= '0' when x(i downto 0) = (i downto 0 => '0') else '1';`` +This implementation uses carry chains for wider implementations. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/arith/arith_prefix_or.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 43-51 + + + +.. only:: latex + + Source file: :pocsrc:`arith/arith_prefix_or.vhdl ` diff --git a/docs/IPCores/arith/arith_prng.rst b/docs/IPCores/arith/arith_prng.rst new file mode 100644 index 00000000..1b04974c --- /dev/null +++ b/docs/IPCores/arith/arith_prng.rst @@ -0,0 +1,51 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:arith_prng: + +PoC.arith.prng +############## + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_prng.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_prng_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +This module implementes a Pseudo-Random Number Generator (PRNG) with +configurable bit count (``BITS``). This module uses an internal list of FPGA +optimized polynomials from 3 to 168 bits. The polynomials have at most 5 tap +positions, so that long shift registers can be inferred instead of single +flip-flops. + +The generated number sequence includes the value all-zeros, but not all-ones. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/arith/arith_prng.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 46-57 + + + +.. only:: latex + + Source file: :pocsrc:`arith/arith_prng.vhdl ` diff --git a/docs/IPCores/arith/arith_same.rst b/docs/IPCores/arith/arith_same.rst new file mode 100644 index 00000000..9ac34e36 --- /dev/null +++ b/docs/IPCores/arith/arith_same.rst @@ -0,0 +1,52 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:arith_same: + +PoC.arith.same +############## + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_same.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_same_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +This circuit may, for instance, be used to detect the first sign change +and, thus, the range of a two's complement number. + +These components may be chained by using the output of the predecessor as +guard input. This chaining allows to have intermediate results available +while still ensuring the use of a fast carry chain on supporting FPGA +architectures. When chaining, make sure to overlap both vector slices by one +bit position as to avoid an undetected sign change between the slices. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/arith/arith_same.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 48-57 + + + +.. only:: latex + + Source file: :pocsrc:`arith/arith_same.vhdl ` diff --git a/docs/PoC/arith/arith_scaler.rst b/docs/IPCores/arith/arith_scaler.rst similarity index 51% rename from docs/PoC/arith/arith_scaler.rst rename to docs/IPCores/arith/arith_scaler.rst index ab1d609d..7ea0e576 100644 --- a/docs/PoC/arith/arith_scaler.rst +++ b/docs/IPCores/arith/arith_scaler.rst @@ -1,6 +1,30 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include -arith_scaler -############ +.. include:: +.. include:: + +.. _IP:arith_scaler: + +PoC.arith.scaler +################ + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_scaler.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_scaler_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` A flexible scaler for fixed-point values. The scaler is implemented for a set of multiplier and divider values. Each individual scaling operation can @@ -28,7 +52,8 @@ highest scaling ratio to be used in order to avoid a truncation overflow. :linenos: :lines: 52-69 -Source file: `arith/arith_scaler.vhdl `_ +.. only:: latex + Source file: :pocsrc:`arith/arith_scaler.vhdl ` diff --git a/docs/IPCores/arith/arith_shifter_barrel.rst b/docs/IPCores/arith/arith_shifter_barrel.rst new file mode 100644 index 00000000..70ca9fe1 --- /dev/null +++ b/docs/IPCores/arith/arith_shifter_barrel.rst @@ -0,0 +1,51 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:arith_shifter_barrel: + +PoC.arith.shifter_barrel +######################## + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_shifter_barrel.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_shifter_barrel_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +This Barrel-Shifter supports: + +* shifting and rotating +* right and left operations +* arithmetic and logic mode (only valid for shift operations) + +This is equivalent to the CPU instructions: SLL, SLA, SRL, SRA, RL, RR + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/arith/arith_shifter_barrel.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 45-57 + + + +.. only:: latex + + Source file: :pocsrc:`arith/arith_shifter_barrel.vhdl ` diff --git a/docs/IPCores/arith/arith_sqrt.rst b/docs/IPCores/arith/arith_sqrt.rst new file mode 100644 index 00000000..bce7f010 --- /dev/null +++ b/docs/IPCores/arith/arith_sqrt.rst @@ -0,0 +1,47 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:arith_sqrt: + +PoC.arith.sqrt +############## + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/arith/arith_sqrt.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/arith/arith_sqrt_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +Iterative Square Root Extractor. + +Its computation requires (N+1)/2 steps for an argument bit width of N. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/arith/arith_sqrt.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 38-55 + + + +.. only:: latex + + Source file: :pocsrc:`arith/arith_sqrt.vhdl ` diff --git a/docs/IPCores/arith/index.rst b/docs/IPCores/arith/index.rst new file mode 100644 index 00000000..11da2e3a --- /dev/null +++ b/docs/IPCores/arith/index.rst @@ -0,0 +1,57 @@ +.. _NS:arith: + +PoC.arith +========= + +These are arithmetic entities.... + +**Package** + +:ref:`PKG:arith` + +**Entities** + + * :ref:`IP:arith_addw` + * :ref:`IP:arith_carrychain_inc` + * :ref:`IP:arith_convert_bin2bcd` + * :ref:`IP:arith_counter_bcd` + * :ref:`IP:arith_counter_free` + * :ref:`IP:arith_counter_gray` + * :ref:`IP:arith_counter_ring` + * :ref:`IP:arith_div` + * :ref:`IP:arith_firstone` + * :ref:`IP:arith_muls_wide` + * :ref:`IP:arith_prefix_and` + * :ref:`IP:arith_prefix_or` + * :ref:`IP:arith_prng` + * :ref:`IP:arith_same` + * :ref:`IP:arith_scaler` + * :ref:`IP:arith_shifter_barrel` + * :ref:`IP:arith_sqrt` + + +.. toctree:: + :hidden: + + Package + +.. toctree:: + :hidden: + + arith_addw + arith_carrychain_inc + arith_convert_bin2bcd + arith_counter_bcd + arith_counter_free + arith_counter_gray + arith_counter_ring + arith_div + arith_firstone + arith_muls_wide + arith_prefix_and + arith_prefix_or + arith_prng + arith_same + arith_scaler + arith_shifter_barrel + arith_sqrt diff --git a/docs/IPCores/bus/bus_Arbiter.rst b/docs/IPCores/bus/bus_Arbiter.rst new file mode 100644 index 00000000..ed049fbc --- /dev/null +++ b/docs/IPCores/bus/bus_Arbiter.rst @@ -0,0 +1,48 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:bus_Arbiter: + +PoC.bus.Arbiter +############### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/bus/bus_Arbiter.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/bus/bus_Arbiter_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +This module implements a generic arbiter. It currently supports the +following arbitration strategies: + +* Round Robin (RR) + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/bus/bus_Arbiter.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-60 + + + +.. only:: latex + + Source file: :pocsrc:`bus/bus_Arbiter.vhdl ` diff --git a/docs/IPCores/bus/index.rst b/docs/IPCores/bus/index.rst new file mode 100644 index 00000000..ebda5e61 --- /dev/null +++ b/docs/IPCores/bus/index.rst @@ -0,0 +1,26 @@ +.. _NS:bus: + +PoC.bus +======== + +These are bus entities.... + +**Sub-namespaces** + + * :ref:`NS:stream` + * :ref:`NS:wb` + +**Entities** + + * :ref:`IP:bus_Arbiter` + +.. toctree:: + :hidden: + + stream + wb + +.. toctree:: + :hidden: + + bus_Arbiter diff --git a/docs/IPCores/bus/stream/index.rst b/docs/IPCores/bus/stream/index.rst new file mode 100644 index 00000000..a39eaf75 --- /dev/null +++ b/docs/IPCores/bus/stream/index.rst @@ -0,0 +1,22 @@ +.. _NS:stream: + +PoC.bus.stream +============== + +PoC.Stream modules ... + +.. toctree:: + :hidden: + + Package + +.. toctree:: + :hidden: + + stream_Buffer + stream_DeMux + stream_Mux + stream_Mirror + stream_Sink + stream_Source + stream_FrameGenerator diff --git a/docs/IPCores/bus/stream/stream.pkg.rst b/docs/IPCores/bus/stream/stream.pkg.rst new file mode 100644 index 00000000..03161076 --- /dev/null +++ b/docs/IPCores/bus/stream/stream.pkg.rst @@ -0,0 +1,19 @@ +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/bus/stream/stream.pkg.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` + +.. _PKG:stream: + +PoC.bus.stream Package +====================== + +.. only:: latex + + Source file: :pocsrc:`stream.pkg.vhdl ` diff --git a/docs/IPCores/bus/stream/stream_Buffer.rst b/docs/IPCores/bus/stream/stream_Buffer.rst new file mode 100644 index 00000000..404b79f0 --- /dev/null +++ b/docs/IPCores/bus/stream/stream_Buffer.rst @@ -0,0 +1,48 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:stream_Buffer: + +PoC.bus.stream.Buffer +##################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/bus/stream/stream_Buffer.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/bus/stream/stream_Buffer_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +This module implements a generic buffer (FIFO) for the +:doc:`PoC.Stream ` protocol. It is generic in +``DATA_BITS`` and in ``META_BITS`` as well as in FIFO depths for data and +meta information. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/bus/stream/stream_Buffer.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 44-74 + + + +.. only:: latex + + Source file: :pocsrc:`bus/stream/stream_Buffer.vhdl ` diff --git a/docs/IPCores/bus/stream/stream_DeMux.rst b/docs/IPCores/bus/stream/stream_DeMux.rst new file mode 100644 index 00000000..e9c88780 --- /dev/null +++ b/docs/IPCores/bus/stream/stream_DeMux.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:stream_DeMux: + +PoC.bus.stream.DeMux +#################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/bus/stream/stream_DeMux.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/bus/stream/stream_DeMux_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/bus/stream/stream_DeMux.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 41-70 + + + +.. only:: latex + + Source file: :pocsrc:`bus/stream/stream_DeMux.vhdl ` diff --git a/docs/IPCores/bus/stream/stream_FrameGenerator.rst b/docs/IPCores/bus/stream/stream_FrameGenerator.rst new file mode 100644 index 00000000..372aa835 --- /dev/null +++ b/docs/IPCores/bus/stream/stream_FrameGenerator.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:stream_FrameGenerator: + +PoC.bus.stream.FrameGenerator +############################# + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/bus/stream/stream_FrameGenerator.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/bus/stream/stream_FrameGenerator_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/bus/stream/stream_FrameGenerator.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 40-66 + + + +.. only:: latex + + Source file: :pocsrc:`bus/stream/stream_FrameGenerator.vhdl ` diff --git a/docs/IPCores/bus/stream/stream_Mirror.rst b/docs/IPCores/bus/stream/stream_Mirror.rst new file mode 100644 index 00000000..d8263ec4 --- /dev/null +++ b/docs/IPCores/bus/stream/stream_Mirror.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:stream_Mirror: + +PoC.bus.stream.Mirror +##################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/bus/stream/stream_Mirror.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/bus/stream/stream_Mirror_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/bus/stream/stream_Mirror.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 41-70 + + + +.. only:: latex + + Source file: :pocsrc:`bus/stream/stream_Mirror.vhdl ` diff --git a/docs/IPCores/bus/stream/stream_Mux.rst b/docs/IPCores/bus/stream/stream_Mux.rst new file mode 100644 index 00000000..348d1e3f --- /dev/null +++ b/docs/IPCores/bus/stream/stream_Mux.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:stream_Mux: + +PoC.bus.stream.Mux +################## + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/bus/stream/stream_Mux.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/bus/stream/stream_Mux_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/bus/stream/stream_Mux.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 41-69 + + + +.. only:: latex + + Source file: :pocsrc:`bus/stream/stream_Mux.vhdl ` diff --git a/docs/IPCores/bus/stream/stream_Sink.rst b/docs/IPCores/bus/stream/stream_Sink.rst new file mode 100644 index 00000000..fd94e9f3 --- /dev/null +++ b/docs/IPCores/bus/stream/stream_Sink.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:stream_Sink: + +PoC.bus.stream.Sink +################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/bus/stream/stream_Sink.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/bus/stream/stream_Sink_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/bus/stream/stream_Sink.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-59 + + + +.. only:: latex + + Source file: :pocsrc:`bus/stream/stream_Sink.vhdl ` diff --git a/docs/IPCores/bus/stream/stream_Source.rst b/docs/IPCores/bus/stream/stream_Source.rst new file mode 100644 index 00000000..c25768fd --- /dev/null +++ b/docs/IPCores/bus/stream/stream_Source.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:stream_Source: + +PoC.bus.stream.Source +##################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/bus/stream/stream_Source.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/bus/stream/stream_Source_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/bus/stream/stream_Source.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-58 + + + +.. only:: latex + + Source file: :pocsrc:`bus/stream/stream_Source.vhdl ` diff --git a/docs/IPCores/bus/wb/index.rst b/docs/IPCores/bus/wb/index.rst new file mode 100644 index 00000000..d3cf6e0d --- /dev/null +++ b/docs/IPCores/bus/wb/index.rst @@ -0,0 +1,20 @@ +.. _NS:wb: + +PoC.bus.wb +========== + +WishBone modules ... + +**Entities:** + +.. toctree:: + :hidden: + + Package + +.. toctree:: + :hidden: + + wb_ocram + wb_fifo_adapter + wb_uart_wrapper diff --git a/docs/IPCores/bus/wb/wb.pkg.rst b/docs/IPCores/bus/wb/wb.pkg.rst new file mode 100644 index 00000000..97492a80 --- /dev/null +++ b/docs/IPCores/bus/wb/wb.pkg.rst @@ -0,0 +1,19 @@ +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/bus/wb/wb.pkg.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` + +.. _PKG:wb: + +PoC.bus.wb Package +====================== + +.. only:: latex + + Source file: :pocsrc:`wb.pkg.vhdl ` diff --git a/docs/IPCores/bus/wb/wb_fifo_adapter.rst b/docs/IPCores/bus/wb/wb_fifo_adapter.rst new file mode 100644 index 00000000..f98dc881 --- /dev/null +++ b/docs/IPCores/bus/wb/wb_fifo_adapter.rst @@ -0,0 +1,52 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:wb_fifo_adapter: + +PoC.bus.wb.fifo_adapter +####################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/bus/wb/wb_fifo_adapter.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/bus/wb/wb_fifo_adapter_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +Small FIFOs are included in this module, if larger or asynchronous +transmit / receive FIFOs are required, then they must be connected +externally. + +old comments: + UART BAUD rate generator + bclk_r = bit clock is rising + bclk_x8_r = bit clock times 8 is rising + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/bus/wb/wb_fifo_adapter.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 80-104 + + + +.. only:: latex + + Source file: :pocsrc:`bus/wb/wb_fifo_adapter.vhdl ` diff --git a/docs/IPCores/bus/wb/wb_ocram.rst b/docs/IPCores/bus/wb/wb_ocram.rst new file mode 100644 index 00000000..56e8a887 --- /dev/null +++ b/docs/IPCores/bus/wb/wb_ocram.rst @@ -0,0 +1,64 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:ocram_wb: + +PoC.bus.wb.ocram +################ + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/bus/wb/wb_ocram.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/bus/wb/wb_ocram_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +This slave supports Wishbone Registered Feedback bus cycles (aka. burst +transfers / advanced synchronous cycle termination). The mode "Incrementing +burst cycle" (CTI = 010) with "Linear burst" (BTE = 00) is supported. + +If your master does support Wishbone Classis bus cycles only, then connect +wb_cti_i = "000" and wb_bte_i = "00". + +Connect the ocram of your choice to the ram_* port signals. (Every RAM with +single cyle read latency is supported.) + +Configuration: +-------------- +PIPE_STAGES = 1 + The RAM output is directly connected to the bus. Thus, the + read access latency (one cycle) is short. But, the RAM's read timing delay + must be respected. + +PIPE_STAGES = 2 + The RAM output is registered again. Thus, the read access + latency is two cycles. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/bus/wb/wb_ocram.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 54-80 + + + +.. only:: latex + + Source file: :pocsrc:`bus/wb/wb_ocram.vhdl ` diff --git a/docs/IPCores/bus/wb/wb_uart_wrapper.rst b/docs/IPCores/bus/wb/wb_uart_wrapper.rst new file mode 100644 index 00000000..08bf064a --- /dev/null +++ b/docs/IPCores/bus/wb/wb_uart_wrapper.rst @@ -0,0 +1,47 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:uart_wb: + +PoC.bus.wb.uart_wrapper +####################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/bus/wb/wb_uart_wrapper.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/bus/wb/wb_uart_wrapper_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +Wrapper module for :doc:`PoC.io.uart.rx ` and +:doc:`PoC.io.uart.tx ` to support the Wishbone +interface. Synchronized reset is used. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/bus/wb/wb_uart_wrapper.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 40-69 + + + +.. only:: latex + + Source file: :pocsrc:`bus/wb/wb_uart_wrapper.vhdl ` diff --git a/docs/IPCores/cache/cache_cpu.rst b/docs/IPCores/cache/cache_cpu.rst new file mode 100644 index 00000000..15020678 --- /dev/null +++ b/docs/IPCores/cache/cache_cpu.rst @@ -0,0 +1,183 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:cache_cpu: + +PoC.cache.cpu +############# + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/cache/cache_cpu.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/cache/cache_cpu_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +This unit provides a cache (:ref:`IP:cache_par2`) together +with a cache controller which reads / writes cache lines from / to memory. +The memory is accessed using a :ref:`INT:PoC.Mem` interfaces, the related +ports and parameters are prefixed with ``mem_``. + +The CPU side (prefix ``cpu_``) has a modified PoC.Mem interface, so that +this unit can be easily integrated into processor pipelines. For example, +let's have a pipeline where a load/store instruction is executed in 3 +stages (after fetching, decoding, ...): + +1. Execute (EX) for address calculation, +2. Load/Store 1 (LS1) for the cache access, +3. Load/Store 2 (LS2) where the cache returns the read data. + +The read data is always returned one cycle after the cache access completes, +so there is conceptually a pipeline register within this unit. The stage LS2 +can be merged with a write-back stage if the clock period allows so. + +The stage LS1 and thus EX and LS2 must stall, until the cache access is +completed, i.e., the EX/LS1 pipeline register must hold the cache request +until it is acknowledged by the cache. This is signaled by ``cpu_got`` as +described in Section Operation below. The pipeline moves forward (is +enabled) when:: + + pipeline_enable <= (not cpu_req) or cpu_got; + +If the pipeline can stall due to other reasons, care must be taken to not +unintentionally executing the cache access twice or missing the read data. + +Of course, the EX/LS1 pipeline register can be omitted and the CPU side +directly fed by the address caculator. But be aware of the high setup time +of this unit and high propate time for ``cpu_got``. + +This unit supports only one outstanding CPU request. More outstanding +requests are provided by :ref:`IP:cache_mem`. + + +Configuration +************* + ++--------------------+-----------------------------------------------------+ +| Parameter | Description | ++====================+=====================================================+ +| REPLACEMENT_POLICY | Replacement policy of embedded cache. For supported | +| | values see PoC.cache_replacement_policy. | ++--------------------+-----------------------------------------------------+ +| CACHE_LINES | Number of cache lines. | ++--------------------+-----------------------------------------------------+ +| ASSOCIATIVITY | Associativity of embedded cache. | ++--------------------+-----------------------------------------------------+ +| CPU_ADDR_BITS | Number of address bits on the CPU side. Each address| +| | identifies one memory word as seen from the CPU. | +| | Calculated from other parameters as described below.| ++--------------------+-----------------------------------------------------+ +| CPU_DATA_BITS | Width of the data bus (in bits) on the CPU side. | +| | CPU_DATA_BITS must be divisible by 8. | ++--------------------+-----------------------------------------------------+ +| MEM_ADDR_BITS | Number of address bits on the memory side. Each | +| | address identifies one word in the memory. | ++--------------------+-----------------------------------------------------+ +| MEM_DATA_BITS | Width of a memory word and of a cache line in bits. | +| | MEM_DATA_BITS must be divisible by CPU_DATA_BITS. | ++--------------------+-----------------------------------------------------+ + +If the CPU data-bus width is smaller than the memory data-bus width, then +the CPU needs additional address bits to identify one CPU data word inside a +memory word. Thus, the CPU address-bus width is calculated from:: + + CPU_ADDR_BITS=log2ceil(MEM_DATA_BITS/CPU_DATA_BITS)+MEM_ADDR_BITS + +The write policy is: write-through, no-write-allocate. + + +Operation +********* + +Alignment of Cache / Memory Accesses +++++++++++++++++++++++++++++++++++++ + +Memory accesses are always aligned to a word boundary. Each memory word +(and each cache line) consists of MEM_DATA_BITS bits. +For example if MEM_DATA_BITS=128: + +* memory address 0 selects the bits 0..127 in memory, +* memory address 1 selects the bits 128..256 in memory, and so on. + +Cache accesses are always aligned to a CPU word boundary. Each CPU word +consists of CPU_DATA_BITS bits. For example if CPU_DATA_BITS=32: + +* CPU address 0 selects the bits 0.. 31 in memory word 0, +* CPU address 1 selects the bits 32.. 63 in memory word 0, +* CPU address 2 selects the bits 64.. 95 in memory word 0, +* CPU address 3 selects the bits 96..127 in memory word 0, +* CPU address 4 selects the bits 0.. 31 in memory word 1, +* CPU address 5 selects the bits 32.. 63 in memory word 1, and so on. + + +Shared and Memory Side Interface +++++++++++++++++++++++++++++++++ + +A synchronous reset must be applied even on a FPGA. + +The memory side interface is documented in detail :ref:`here `. + + +CPU Side Interface +++++++++++++++++++ + +The CPU (pipeline stage LS1, see above) issues a request by setting +``cpu_req``, ``cpu_write``, ``cpu_addr``, ``cpu_wdata`` and ``cpu_wmask`` as +in the :ref:`INT:PoC.Mem` interface. The cache acknowledges the request by +setting ``cpu_got`` to '1'. If the request is not acknowledged (``cpu_got = +'0'``) in the current clock cycle, then the request must be repeated in the +following clock cycle(s) until it is acknowledged, i.e., the pipeline must +stall. + +A cache access is completed when it is acknowledged. A new request can be +issued in the following clock cycle. + +Of course, ``cpu_got`` may be asserted in the same clock cycle where the +request was issued if a read hit occurs. This allows a throughput of one +(read) request per clock cycle, but the drawback is, that ``cpu_got`` has a +high propagation delay. Thus, this output should only control a simple +pipeline enable logic. + +When ``cpu_got`` is asserted for a read access, then the read data will be +available in the following clock cycle. + +Due to the write-through policy, a write will always take several clock +cycles and acknowledged when the data has been issued to the memory. + +.. WARNING:: + + If the design is synthesized with Xilinx ISE / XST, then the synthesis + option "Keep Hierarchy" must be set to SOFT or TRUE. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/cache/cache_cpu.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 175-207 + +.. seealso:: + + :ref:`IP:cache_mem` + + + +.. only:: latex + + Source file: :pocsrc:`cache/cache_cpu.vhdl ` diff --git a/docs/IPCores/cache/cache_mem.rst b/docs/IPCores/cache/cache_mem.rst new file mode 100644 index 00000000..e7e931b8 --- /dev/null +++ b/docs/IPCores/cache/cache_mem.rst @@ -0,0 +1,143 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:cache_mem: + +PoC.cache.mem +############# + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/cache/cache_mem.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/cache/cache_mem_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +This unit provides a cache (:ref:`IP:cache_par2`) together +with a cache controller which reads / writes cache lines from / to memory. +It has two :ref:`INT:PoC.Mem` interfaces: + +* one for the "CPU" side (ports with prefix ``cpu_``), and +* one for the memory side (ports with prefix ``mem_``). + +Thus, this unit can be placed into an already available memory path between +the CPU and the memory (controller). If you want to plugin a cache into a +CPU pipeline, see :ref:`IP:cache_cpu`. + + +Configuration +************* + ++--------------------+-----------------------------------------------------+ +| Parameter | Description | ++====================+=====================================================+ +| REPLACEMENT_POLICY | Replacement policy of embedded cache. For supported | +| | values see PoC.cache_replacement_policy. | ++--------------------+-----------------------------------------------------+ +| CACHE_LINES | Number of cache lines. | ++--------------------+-----------------------------------------------------+ +| ASSOCIATIVITY | Associativity of embedded cache. | ++--------------------+-----------------------------------------------------+ +| CPU_ADDR_BITS | Number of address bits on the CPU side. Each address| +| | identifies one memory word as seen from the CPU. | +| | Calculated from other parameters as described below.| ++--------------------+-----------------------------------------------------+ +| CPU_DATA_BITS | Width of the data bus (in bits) on the CPU side. | +| | CPU_DATA_BITS must be divisible by 8. | ++--------------------+-----------------------------------------------------+ +| MEM_ADDR_BITS | Number of address bits on the memory side. Each | +| | address identifies one word in the memory. | ++--------------------+-----------------------------------------------------+ +| MEM_DATA_BITS | Width of a memory word and of a cache line in bits. | +| | MEM_DATA_BITS must be divisible by CPU_DATA_BITS. | ++--------------------+-----------------------------------------------------+ +| OUTSTANDING_REQ | Number of oustanding requests, see notes below. | ++--------------------+-----------------------------------------------------+ + +If the CPU data-bus width is smaller than the memory data-bus width, then +the CPU needs additional address bits to identify one CPU data word inside a +memory word. Thus, the CPU address-bus width is calculated from:: + + CPU_ADDR_BITS=log2ceil(MEM_DATA_BITS/CPU_DATA_BITS)+MEM_ADDR_BITS + +The write policy is: write-through, no-write-allocate. + +The maximum throughput is one request per clock cycle, except for +``OUSTANDING_REQ = 1``. + +If ``OUTSTANDING_REQ`` is: + +* 1: then 1 request is buffered by a single register. To give a short + critical path (clock-to-output delay) for ``cpu_rdy``, the throughput is + degraded to one request per 2 clock cycles at maximum. + +* 2: then 2 requests are buffered by :ref:`IP:fifo_glue`. This setting has + the lowest area requirements without degrading the performance. + +* >2: then the requests are buffered by :ref:`IP:fifo_cc_got`. The number of + outstanding requests is rounded up to the next suitable value. This setting + is useful in applications with out-of-order execution (of other + operations). The CPU requests to the cache are always processed in-order. + + +Operation +********* + +Memory accesses are always aligned to a word boundary. Each memory word +(and each cache line) consists of MEM_DATA_BITS bits. +For example if MEM_DATA_BITS=128: + +* memory address 0 selects the bits 0..127 in memory, +* memory address 1 selects the bits 128..256 in memory, and so on. + +Cache accesses are always aligned to a CPU word boundary. Each CPU word +consists of CPU_DATA_BITS bits. For example if CPU_DATA_BITS=32: + +* CPU address 0 selects the bits 0.. 31 in memory word 0, +* CPU address 1 selects the bits 32.. 63 in memory word 0, +* CPU address 2 selects the bits 64.. 95 in memory word 0, +* CPU address 3 selects the bits 96..127 in memory word 0, +* CPU address 4 selects the bits 0.. 31 in memory word 1, +* CPU address 5 selects the bits 32.. 63 in memory word 1, and so on. + +A synchronous reset must be applied even on a FPGA. + +The interface is documented in detail :ref:`here `. + +.. WARNING:: + + If the design is synthesized with Xilinx ISE / XST, then the synthesis + option "Keep Hierarchy" must be set to SOFT or TRUE. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/cache/cache_mem.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 135-169 + +.. seealso:: + + :ref:`IP:cache_cpu` + + + +.. only:: latex + + Source file: :pocsrc:`cache/cache_mem.vhdl ` diff --git a/docs/PoC/cache/cache_par.rst b/docs/IPCores/cache/cache_par.rst similarity index 58% rename from docs/PoC/cache/cache_par.rst rename to docs/IPCores/cache/cache_par.rst index 0ba198f5..8bf8d0f7 100644 --- a/docs/PoC/cache/cache_par.rst +++ b/docs/IPCores/cache/cache_par.rst @@ -1,6 +1,40 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include -cache_par -######### +.. include:: +.. include:: + +.. _IP:cache_par: + +PoC.cache.par +############# + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/cache/cache_par.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/cache/cache_par_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +Implements a cache with parallel tag-unit and data memory. + +.. NOTE:: + This component infers a single-port memory with read-first behavior, that + is, upon writes the old-data is returned on the read output. Such memory + (e.g. LUT-RAM) is not available on all devices. Thus, synthesis may + infer a lot of flip-flops plus multiplexers instead, which is very inefficient. + It is recommended to use :doc:`PoC.cache.par2 ` instead which has a + slightly different interface. All inputs are synchronous to the rising-edge of the clock `clock`. @@ -39,6 +73,11 @@ Upon replacing a cache line, the new content is given by ``CacheLineIn``. The old content is outputed on ``CacheLineOut`` and the old tag on ``OldAddress``, both with a latency of one clock cycle. +.. WARNING:: + + If the design is synthesized with Xilinx ISE / XST, then the synthesis + option "Keep Hierarchy" must be set to SOFT or TRUE. + .. rubric:: Entity Declaration: @@ -47,9 +86,10 @@ both with a latency of one clock cycle. :language: vhdl :tab-width: 2 :linenos: - :lines: 76-100 + :lines: 91-115 -Source file: `cache/cache_par.vhdl `_ +.. only:: latex + Source file: :pocsrc:`cache/cache_par.vhdl ` diff --git a/docs/IPCores/cache/cache_par2.rst b/docs/IPCores/cache/cache_par2.rst new file mode 100644 index 00000000..f025e904 --- /dev/null +++ b/docs/IPCores/cache/cache_par2.rst @@ -0,0 +1,127 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:cache_par2: + +PoC.cache.par2 +############## + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/cache/cache_par2.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/cache/cache_par2_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +Cache with parallel tag-unit and data memory. For the data memory, +:ref:`IP:ocram_sp` is used. + +Configuration +************* + ++--------------------+----------------------------------------------------+ +| Parameter | Description | ++====================+====================================================+ +| REPLACEMENT_POLICY | Replacement policy. For supported policies see | +| | PoC.cache_replacement_policy. | ++--------------------+----------------------------------------------------+ +| CACHE_LINES | Number of cache lines. | ++--------------------+----------------------------------------------------+ +| ASSOCIATIVITY | Associativity of the cache. | ++--------------------+----------------------------------------------------+ +| ADDR_BITS | Number of address bits. Each address identifies | +| | exactly one cache line in memory. | ++--------------------+----------------------------------------------------+ +| DATA_BITS | Size of a cache line in bits. | +| | DATA_BITS must be divisible by 8. | ++--------------------+----------------------------------------------------+ + + +Command truth table +******************* + ++---------+-----------+-------------+---------+---------------------------------+ +| Request | ReadWrite | Invalidate | Replace | Command | ++=========+===========+=============+=========+=================================+ +| 0 | 0 | 0 | 0 | None | ++---------+-----------+-------------+---------+---------------------------------+ +| 1 | 0 | 0 | 0 | Read cache line | ++---------+-----------+-------------+---------+---------------------------------+ +| 1 | 1 | 0 | 0 | Update cache line | ++---------+-----------+-------------+---------+---------------------------------+ +| 1 | 0 | 1 | 0 | Read cache line and discard it | ++---------+-----------+-------------+---------+---------------------------------+ +| 1 | 1 | 1 | 0 | Write cache line and discard it | ++---------+-----------+-------------+---------+---------------------------------+ +| 0 | 0 | 0 | 1 | Read cache line before replace. | ++---------+-----------+-------------+---------+---------------------------------+ +| 0 | 1 | 0 | 1 | Replace cache line. | ++---------+-----------+-------------+---------+---------------------------------+ + + +Operation +********* + +All inputs are synchronous to the rising-edge of the clock `clock`. + +All commands use ``Address`` to lookup (request) or replace a cache line. +``Address`` and ``OldAddress`` do not include the word/byte select part. +Each command is completed within one clock cycle, but outputs are delayed as +described below. + +Upon requests, the outputs ``CacheMiss`` and ``CacheHit`` indicate (high-active) +whether the ``Address`` is stored within the cache, or not. Both outputs have a +latency of one clock cycle (pipelined) if ``HIT_MISS_REG`` is true, otherwise the +result is outputted immediately (combinational). + +Upon writing a cache line, the new content is given by ``CacheLineIn``. +Only the bytes which are not masked, i.e. the corresponding bit in WriteMask +is '0', are actually written. + +Upon reading a cache line, the current content is outputed on ``CacheLineOut`` +with a latency of one clock cycle. + +Replacing a cache line requires two steps, both with ``Replace = '1'``: + +1. Read old contents of cache line by setting ``ReadWrite`` to '0'. The old + content is outputed on ``CacheLineOut`` and the old tag on ``OldAddress``, + both with a latency of one clock cycle. + +2. Write new cache line by setting ``ReadWrite`` to '1'. The new content is + given by ``CacheLineIn``. All bytes shall be written, i.e. + ``WriteMask = 0``. The new cache line content will be outputed + again on ``CacheLineOut`` in the next clock cycle (latency = 1). + +.. WARNING:: + + If the design is synthesized with Xilinx ISE / XST, then the synthesis + option "Keep Hierarchy" must be set to SOFT or TRUE. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/cache/cache_par2.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 123-149 + + + +.. only:: latex + + Source file: :pocsrc:`cache/cache_par2.vhdl ` diff --git a/docs/PoC/cache/cache_replacement_policy.rst b/docs/IPCores/cache/cache_replacement_policy.rst similarity index 71% rename from docs/PoC/cache/cache_replacement_policy.rst rename to docs/IPCores/cache/cache_replacement_policy.rst index edd0530d..fc53ddb7 100644 --- a/docs/PoC/cache/cache_replacement_policy.rst +++ b/docs/IPCores/cache/cache_replacement_policy.rst @@ -1,6 +1,30 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include -cache_replacement_policy -######################## +.. include:: +.. include:: + +.. _IP:cache_replacement_policy: + +PoC.cache.replacement_policy +############################ + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/cache/cache_replacement_policy.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/cache/cache_replacement_policy_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` **Supported policies:** @@ -56,7 +80,8 @@ cache set (see above). :linenos: :lines: 85-104 -Source file: `cache/cache_replacement_policy.vhdl `_ +.. only:: latex + Source file: :pocsrc:`cache/cache_replacement_policy.vhdl ` diff --git a/docs/IPCores/cache/cache_tagunit_par.rst b/docs/IPCores/cache/cache_tagunit_par.rst new file mode 100644 index 00000000..d06d32c3 --- /dev/null +++ b/docs/IPCores/cache/cache_tagunit_par.rst @@ -0,0 +1,119 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:cache_tagunit_par: + +PoC.cache.tagunit_par +##################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/cache/cache_tagunit_par.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/cache/cache_tagunit_par_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +Tag-unit with fully-parallel compare of tag. + +Configuration +************* + ++--------------------+----------------------------------------------------+ +| Parameter | Description | ++====================+====================================================+ +| REPLACEMENT_POLICY | Replacement policy. For supported policies see | +| | PoC.cache_replacement_policy. | ++--------------------+----------------------------------------------------+ +| CACHE_LINES | Number of cache lines. | ++--------------------+----------------------------------------------------+ +| ASSOCIATIVITY | Associativity of the cache. | ++--------------------+----------------------------------------------------+ +| ADDRESS_BITS | Number of address bits. Each address identifies | +| | exactly one cache line in memory. | ++--------------------+----------------------------------------------------+ + + +Command truth table +******************* + ++---------+-----------+-------------+---------+----------------------------------+ +| Request | ReadWrite | Invalidate | Replace | Command | ++=========+===========+=============+=========+==================================+ +| 0 | 0 | 0 | 0 | None | ++---------+-----------+-------------+---------+----------------------------------+ +| 1 | 0 | 0 | 0 | Read cache line | ++---------+-----------+-------------+---------+----------------------------------+ +| 1 | 1 | 0 | 0 | Update cache line | ++---------+-----------+-------------+---------+----------------------------------+ +| 1 | 0 | 1 | 0 | Read cache line and discard it | ++---------+-----------+-------------+---------+----------------------------------+ +| 1 | 1 | 1 | 0 | Write cache line and discard it | ++---------+-----------+-------------+---------+----------------------------------+ +| 0 | | 0 | 1 | Replace cache line. | ++---------+-----------+-------------+---------+----------------------------------+ + + +Operation +********* + +All inputs are synchronous to the rising-edge of the clock `clock`. + +All commands use ``Address`` to lookup (request) or replace a cache line. +Each command is completed within one clock cycle. + +Upon requests, the outputs ``CacheMiss`` and ``CacheHit`` indicate (high-active) +immediately (combinational) whether the ``Address`` is stored within the cache, or not. +But, the cache-line usage is updated at the rising-edge of the clock. +If hit, ``LineIndex`` specifies the cache line where to find the content. + +The output ``ReplaceLineIndex`` indicates which cache line will be replaced as +next by a replace command. The output ``OldAddress`` specifies the old tag stored at this +index. The replace command will store the ``Address`` and update the cache-line +usage at the rising-edge of the clock. + +For a direct-mapped cache, the number of ``CACHE_LINES`` must be a power of 2. +For a set-associative cache, the expression ``CACHE_LINES / ASSOCIATIVITY`` +must be a power of 2. + +.. NOTE:: + The port ``NewAddress`` has been removed. Use ``Address`` instead as + described above. + + If ``Address`` is fed from a register and an Altera FPGA is used, then + Quartus Map converts the tag memory from a memory with asynchronous read to a + memory with synchronous read by adding a pass-through logic. Quartus Map + reports warning 276020 which is intended. + +.. WARNING:: + + If the design is synthesized with Xilinx ISE / XST, then the synthesis + option "Keep Hierarchy" must be set to SOFT or TRUE. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/cache/cache_tagunit_par.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 114-137 + + + +.. only:: latex + + Source file: :pocsrc:`cache/cache_tagunit_par.vhdl ` diff --git a/docs/IPCores/cache/cache_tagunit_seq.rst b/docs/IPCores/cache/cache_tagunit_seq.rst new file mode 100644 index 00000000..b3439f23 --- /dev/null +++ b/docs/IPCores/cache/cache_tagunit_seq.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:cache_tagunit_seq: + +PoC.cache.tagunit_seq +##################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/cache/cache_tagunit_seq.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/cache/cache_tagunit_seq_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/cache/cache_tagunit_seq.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 39-73 + + + +.. only:: latex + + Source file: :pocsrc:`cache/cache_tagunit_seq.vhdl ` diff --git a/docs/IPCores/cache/index.rst b/docs/IPCores/cache/index.rst new file mode 100644 index 00000000..ae107330 --- /dev/null +++ b/docs/IPCores/cache/index.rst @@ -0,0 +1,45 @@ +.. _NS:cache: + +PoC.cache +========= + +The namespace `PoC.cache` offers different cache implementations. + +**Entities** + + * :ref:`IP:cache_cpu`: Cache with cache controller to be used within a CPU. + + * :ref:`IP:cache_mem`: Cache with :ref:`INT:PoC.Mem` interface on the "CPU" side. + + * :ref:`IP:cache_par`: Cache with parallel tag-unit and + data memory (using infered memory). + + * :ref:`IP:cache_par2`: Cache with parallel tag-unit and + data memory (using :ref:`IP:ocram_sp`). + + * :ref:`IP:cache_tagunit_par`: Tag-Unit with + parallel tag comparison. Configurable as: + + * Full-associative cache, + * Direct-mapped cache, or + * Set-associative cache. + + * :ref:`IP:cache_tagunit_seq`: Tag-Unit with + sequential tag comparison. Configurable as: + + * Full-associative cache, + * Direct-mapped cache, or + * Set-associative cache. + + + +.. toctree:: + :hidden: + + cache_cpu + cache_mem + cache_par + cache_par2 + cache_replacement_policy + cache_tagunit_par + cache_tagunit_seq diff --git a/docs/IPCores/comm/comm.pkg.rst b/docs/IPCores/comm/comm.pkg.rst new file mode 100644 index 00000000..23080d59 --- /dev/null +++ b/docs/IPCores/comm/comm.pkg.rst @@ -0,0 +1,19 @@ +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/comm/comm.pkg.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` + +.. _PKG:comm: + +PoC.comm Package +================ + +.. only:: latex + + Source file: :pocsrc:`comm.pkg.vhdl ` diff --git a/docs/IPCores/comm/comm_crc.rst b/docs/IPCores/comm/comm_crc.rst new file mode 100644 index 00000000..f8b22284 --- /dev/null +++ b/docs/IPCores/comm/comm_crc.rst @@ -0,0 +1,51 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:comm_crc: + +PoC.comm.crc +############ + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/comm/comm_crc.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/comm/comm_crc_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +Computes the Cyclic Redundancy Check (CRC) for a data packet as remainder +of the polynomial division of the message by the given generator +polynomial (GEN). + +The computation is unrolled so as to process an arbitrary number of +message bits per step. The generated CRC is independent from the chosen +processing width. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/comm/comm_crc.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 45-64 + + + +.. only:: latex + + Source file: :pocsrc:`comm/comm_crc.vhdl ` diff --git a/docs/IPCores/comm/comm_scramble.rst b/docs/IPCores/comm/comm_scramble.rst new file mode 100644 index 00000000..35b45b67 --- /dev/null +++ b/docs/IPCores/comm/comm_scramble.rst @@ -0,0 +1,47 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:comm_scramble: + +PoC.comm.scramble +################# + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/comm/comm_scramble.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/comm/comm_scramble_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +The LFSR computation is unrolled to generate an arbitrary number of mask +bits in parallel. The mask are output in little endian. The generated bit +sequence is independent from the chosen output width. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/comm/comm_scramble.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 37-51 + + + +.. only:: latex + + Source file: :pocsrc:`comm/comm_scramble.vhdl ` diff --git a/docs/IPCores/comm/index.rst b/docs/IPCores/comm/index.rst new file mode 100644 index 00000000..12fb724f --- /dev/null +++ b/docs/IPCores/comm/index.rst @@ -0,0 +1,17 @@ +.. _NS:comm: + +PoC.comm +======== + +These are communication entities.... + +.. toctree:: + :hidden: + + Package + +.. toctree:: + :hidden: + + comm_crc + comm_scramble diff --git a/docs/PoC/common/components.rst b/docs/IPCores/common/components.rst similarity index 100% rename from docs/PoC/common/components.rst rename to docs/IPCores/common/components.rst diff --git a/docs/PoC/common/config.rst b/docs/IPCores/common/config.rst similarity index 100% rename from docs/PoC/common/config.rst rename to docs/IPCores/common/config.rst diff --git a/docs/PoC/common/context.rst b/docs/IPCores/common/context.rst similarity index 100% rename from docs/PoC/common/context.rst rename to docs/IPCores/common/context.rst diff --git a/docs/PoC/common/fileio.rst b/docs/IPCores/common/fileio.rst similarity index 100% rename from docs/PoC/common/fileio.rst rename to docs/IPCores/common/fileio.rst diff --git a/docs/PoC/common/index.rst b/docs/IPCores/common/index.rst similarity index 91% rename from docs/PoC/common/index.rst rename to docs/IPCores/common/index.rst index e96eda89..ed575ec4 100644 --- a/docs/PoC/common/index.rst +++ b/docs/IPCores/common/index.rst @@ -1,3 +1,4 @@ +.. _PKG_Common: Common Packages =============== diff --git a/docs/PoC/common/math.rst b/docs/IPCores/common/math.rst similarity index 100% rename from docs/PoC/common/math.rst rename to docs/IPCores/common/math.rst diff --git a/docs/PoC/common/strings.rst b/docs/IPCores/common/strings.rst similarity index 100% rename from docs/PoC/common/strings.rst rename to docs/IPCores/common/strings.rst diff --git a/docs/PoC/common/utils.rst b/docs/IPCores/common/utils.rst similarity index 100% rename from docs/PoC/common/utils.rst rename to docs/IPCores/common/utils.rst diff --git a/docs/PoC/common/vectors.rst b/docs/IPCores/common/vectors.rst similarity index 100% rename from docs/PoC/common/vectors.rst rename to docs/IPCores/common/vectors.rst diff --git a/docs/IPCores/fifo/fifo.pkg.rst b/docs/IPCores/fifo/fifo.pkg.rst new file mode 100644 index 00000000..7a11a06c --- /dev/null +++ b/docs/IPCores/fifo/fifo.pkg.rst @@ -0,0 +1,21 @@ +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/fifo/fifo.pkg.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` + +.. _PKG:fifo: + +PoC.fifo Package +================ + +This package holds all component declarations for this namespace. + +.. only:: latex + + Source file: :pocsrc:`fifo.pkg.vhdl ` diff --git a/docs/PoC/fifo/fifo_cc_got.rst b/docs/IPCores/fifo/fifo_cc_got.rst similarity index 69% rename from docs/PoC/fifo/fifo_cc_got.rst rename to docs/IPCores/fifo/fifo_cc_got.rst index da288a1c..ac7cf083 100644 --- a/docs/PoC/fifo/fifo_cc_got.rst +++ b/docs/IPCores/fifo/fifo_cc_got.rst @@ -1,6 +1,30 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include -fifo_cc_got -########### +.. include:: +.. include:: + +.. _IP:fifo_cc_got: + +PoC.fifo.cc_got +############### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/fifo/fifo_cc_got.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/fifo/fifo_cc_got_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` This module implements a regular FIFO with common clock (cc), pipelined interface. Common clock means read and write port use the same clock. The @@ -60,16 +84,17 @@ comparator (subtractor) in their path. :linenos: :lines: 98-124 -Source file: `fifo/fifo_cc_got.vhdl `_ - .. seealso:: - :doc:`PoC.fifo.dc_got ` + :ref:`IP:fifo_dc_got` For a FIFO with dependent clocks. - :doc:`PoC.fifo.ic_got ` + :ref:`IP:fifo_ic_got` For a FIFO with independent clocks (cross-clock FIFO). - :doc:`PoC.fifo.glue ` + :ref:`IP:fifo_glue` For a minimal FIFO / pipeline decoupling. +.. only:: latex + + Source file: :pocsrc:`fifo/fifo_cc_got.vhdl ` diff --git a/docs/PoC/fifo/fifo_cc_got_tempgot.rst b/docs/IPCores/fifo/fifo_cc_got_tempgot.rst similarity index 54% rename from docs/PoC/fifo/fifo_cc_got_tempgot.rst rename to docs/IPCores/fifo/fifo_cc_got_tempgot.rst index 1cca8eec..6e8a2f82 100644 --- a/docs/PoC/fifo/fifo_cc_got_tempgot.rst +++ b/docs/IPCores/fifo/fifo_cc_got_tempgot.rst @@ -1,6 +1,30 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include -fifo_cc_got_tempgot -################### +.. include:: +.. include:: + +.. _IP:fifo_cc_got_tempgot: + +PoC.fifo.cc_got_tempgot +####################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/fifo/fifo_cc_got_tempgot.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/fifo/fifo_cc_got_tempgot_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` The specified depth (``MIN_DEPTH``) is rounded up to the next suitable value. @@ -31,14 +55,19 @@ If a fill state is not of interest, set ``*STATE_*_BITS = 0``. ``fstate_rd`` and ``estate_wr`` are combinatorial outputs and include an address comparator (subtractor) in their path. -Examples: -- FSTATE_RD_BITS = 1: fstate_rd == 0 => 0/2 full - fstate_rd == 1 => 1/2 full (half full) +**Examples:** + +* FSTATE_RD_BITS = 1: + + * fstate_rd == 0 => 0/2 full + * fstate_rd == 1 => 1/2 full (half full) + +* FSTATE_RD_BITS = 2: -- FSTATE_RD_BITS = 2: fstate_rd == 0 => 0/4 full - fstate_rd == 1 => 1/4 full - fstate_rd == 2 => 2/4 full - fstate_rd == 3 => 3/4 full + * fstate_rd == 0 => 0/4 full + * fstate_rd == 1 => 1/4 full + * fstate_rd == 2 => 2/4 full + * fstate_rd == 3 => 3/4 full @@ -48,9 +77,10 @@ Examples: :language: vhdl :tab-width: 2 :linenos: - :lines: 80-109 + :lines: 85-114 -Source file: `fifo/fifo_cc_got_tempgot.vhdl `_ +.. only:: latex + Source file: :pocsrc:`fifo/fifo_cc_got_tempgot.vhdl ` diff --git a/docs/PoC/fifo/fifo_cc_got_tempput.rst b/docs/IPCores/fifo/fifo_cc_got_tempput.rst similarity index 54% rename from docs/PoC/fifo/fifo_cc_got_tempput.rst rename to docs/IPCores/fifo/fifo_cc_got_tempput.rst index 40a9a611..1cc78a19 100644 --- a/docs/PoC/fifo/fifo_cc_got_tempput.rst +++ b/docs/IPCores/fifo/fifo_cc_got_tempput.rst @@ -1,6 +1,30 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include -fifo_cc_got_tempput -################### +.. include:: +.. include:: + +.. _IP:fifo_cc_got_tempput: + +PoC.fifo.cc_got_tempput +####################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/fifo/fifo_cc_got_tempput.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/fifo/fifo_cc_got_tempput_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` The specified depth (``MIN_DEPTH``) is rounded up to the next suitable value. @@ -31,14 +55,19 @@ If a fill state is not of interest, set ``*STATE_*_BITS = 0``. ``fstate_rd`` and ``estate_wr`` are combinatorial outputs and include an address comparator (subtractor) in their path. -Examples: -- FSTATE_RD_BITS = 1: fstate_rd == 0 => 0/2 full - fstate_rd == 1 => 1/2 full (half full) +**Examples:** + +* FSTATE_RD_BITS = 1: + + * fstate_rd == 0 => 0/2 full + * fstate_rd == 1 => 1/2 full (half full) + +* FSTATE_RD_BITS = 2: -- FSTATE_RD_BITS = 2: fstate_rd == 0 => 0/4 full - fstate_rd == 1 => 1/4 full - fstate_rd == 2 => 2/4 full - fstate_rd == 3 => 3/4 full + * fstate_rd == 0 => 0/4 full + * fstate_rd == 1 => 1/4 full + * fstate_rd == 2 => 2/4 full + * fstate_rd == 3 => 3/4 full @@ -48,9 +77,10 @@ Examples: :language: vhdl :tab-width: 2 :linenos: - :lines: 80-109 + :lines: 85-114 -Source file: `fifo/fifo_cc_got_tempput.vhdl `_ +.. only:: latex + Source file: :pocsrc:`fifo/fifo_cc_got_tempput.vhdl ` diff --git a/docs/PoC/fifo/fifo_dc_got_sm.rst b/docs/IPCores/fifo/fifo_dc_got_sm.rst similarity index 56% rename from docs/PoC/fifo/fifo_dc_got_sm.rst rename to docs/IPCores/fifo/fifo_dc_got_sm.rst index 573c8d58..7a175fd8 100644 --- a/docs/PoC/fifo/fifo_dc_got_sm.rst +++ b/docs/IPCores/fifo/fifo_dc_got_sm.rst @@ -1,6 +1,30 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include -fifo_dc_got_sm -############## +.. include:: +.. include:: + +.. _IP:fifo_dc_got_sm: + +PoC.fifo.dc_got_sm +################## + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/fifo/fifo_dc_got_sm.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/fifo/fifo_dc_got_sm_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` Dependent clocks meens, that one clock must be a multiple of the other one. And your synthesis tool must check for setup- and hold-time violations. @@ -37,7 +61,8 @@ Synchronous reset is used. Both resets must overlap. :linenos: :lines: 62-85 -Source file: `fifo/fifo_dc_got_sm.vhdl `_ +.. only:: latex + Source file: :pocsrc:`fifo/fifo_dc_got_sm.vhdl ` diff --git a/docs/IPCores/fifo/fifo_glue.rst b/docs/IPCores/fifo/fifo_glue.rst new file mode 100644 index 00000000..ef2013ba --- /dev/null +++ b/docs/IPCores/fifo/fifo_glue.rst @@ -0,0 +1,47 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:fifo_glue: + +PoC.fifo.glue +############# + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/fifo/fifo_glue.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/fifo/fifo_glue_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +Its primary use is the decoupling of enable domains in a processing +pipeline. Data storage is limited to two words only so as to allow both +the ``ful`` and the ``vld`` indicators to be driven by registers. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/fifo/fifo_glue.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 36-55 + + + +.. only:: latex + + Source file: :pocsrc:`fifo/fifo_glue.vhdl ` diff --git a/docs/IPCores/fifo/fifo_ic_assembly.rst b/docs/IPCores/fifo/fifo_ic_assembly.rst new file mode 100644 index 00000000..a1daa7b2 --- /dev/null +++ b/docs/IPCores/fifo/fifo_ic_assembly.rst @@ -0,0 +1,56 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:fifo_ic_assembly: + +PoC.fifo.ic_assembly +#################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/fifo/fifo_ic_assembly.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/fifo/fifo_ic_assembly_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +This module assembles a FIFO stream from data blocks that may arrive +slightly out of order. The arriving data is ordered according to their +address. The streamed output starts with the data word written to +address zero (0) and may proceed all the way to just before the first yet +missing data. The association of data with addresses is used on the input +side for the sole purpose of reconstructing the correct order of the data. +It is assumed to wrap so as to allow an infinite input sequence. Addresses +are not actively exposed to the purely stream-based FIFO output. + +The implemented functionality enables the reconstruction of streams that +are tunnelled across address-based transports that are allowed to reorder +the transmission of data blocks. This applies to many DMA implementations. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/fifo/fifo_ic_assembly.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 45-78 + + + +.. only:: latex + + Source file: :pocsrc:`fifo/fifo_ic_assembly.vhdl ` diff --git a/docs/PoC/fifo/fifo_ic_got.rst b/docs/IPCores/fifo/fifo_ic_got.rst similarity index 64% rename from docs/PoC/fifo/fifo_ic_got.rst rename to docs/IPCores/fifo/fifo_ic_got.rst index 493f7940..6785e7d0 100644 --- a/docs/PoC/fifo/fifo_ic_got.rst +++ b/docs/IPCores/fifo/fifo_ic_got.rst @@ -1,6 +1,30 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include -fifo_ic_got -########### +.. include:: +.. include:: + +.. _IP:fifo_ic_got: + +PoC.fifo.ic_got +############### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/fifo/fifo_ic_got.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/fifo/fifo_ic_got_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` Independent clocks meens that read and write clock are unrelated. @@ -49,7 +73,8 @@ Examples: :linenos: :lines: 77-103 -Source file: `fifo/fifo_ic_got.vhdl `_ +.. only:: latex + Source file: :pocsrc:`fifo/fifo_ic_got.vhdl ` diff --git a/docs/IPCores/fifo/fifo_shift.rst b/docs/IPCores/fifo/fifo_shift.rst new file mode 100644 index 00000000..83bfa04e --- /dev/null +++ b/docs/IPCores/fifo/fifo_shift.rst @@ -0,0 +1,51 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:fifo_shift: + +PoC.fifo.shift +############## + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/fifo/fifo_shift.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/fifo/fifo_shift_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +This FIFO implementation is based on an internal shift register. This is +especially useful for smaller FIFO sizes, which can be implemented in LUT +storage on some devices (e.g. Xilinx' SRLs). Only a single read pointer is +maintained, which determines the number of valid entries within the +underlying shift register. + +The specified depth (``MIN_DEPTH``) is rounded up to the next suitable value. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/fifo/fifo_shift.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 44-64 + + + +.. only:: latex + + Source file: :pocsrc:`fifo/fifo_shift.vhdl ` diff --git a/docs/IPCores/fifo/index.rst b/docs/IPCores/fifo/index.rst new file mode 100644 index 00000000..27ee6f03 --- /dev/null +++ b/docs/IPCores/fifo/index.rst @@ -0,0 +1,54 @@ +.. _NS:fifo: + +PoC.fifo +======== + +The namespace `PoC.fifo` offers different :abbr:`FIFO (first-in, first-out)` implementations. + +**Package** + +The package :ref:`NS:fifo` holds all component declarations for this namespace. + +**Entities** + +PoC offers FIFOs with a `got`-interface. This means, the current read-pointer value +is available on the output. Asserting the `got`-input, acknoledge the processing of +the current output signals and moves the read-pointer to the next value, if available. + +All FIFOs implement a bidirectional flow control (`put`/`full` and `valid`/`got`). +Each FIFO also offers a EmptyState (write-side) and FullState (read-side) to indicate +the current fill-state. + +The prefixes `cc_` (common clock), `dc_` (dependent clock) and `ic_` (independent +clock) refer to the write- and read-side clock relationship. + + * :ref:`IP:fifo_cc_got` implements a regular FIFO (one common clock, + got-interface) + * :ref:`IP:fifo_cc_got_tempgot` implements a regular FIFO (one common clock, + got-interface), extended by a transactional `tempgot`-interface (read-side). + * :ref:`IP:fifo_cc_got_tempput` implements a regular FIFO (one common clock, + got-interface), extended by a transactional `tempput`-interface (write-side). + * :ref:`IP:fifo_dc_got` implements a cross-clock FIFO (two related clocks, + got-interface) + * :ref:`IP:fifo_ic_got` implements a cross-clock FIFO (two independent clocks, + got-interface) + * :ref:`IP:fifo_glue` implements a two-stage FIFO (one common clock, + got-interface) + * :ref:`IP:fifo_shift` implements a regular FIFO (one common clock, + got-interface, optimized for FPGAs with shifter primitives) + +.. toctree:: + :hidden: + + Package + +.. toctree:: + :hidden: + + fifo_cc_got + fifo_cc_got_tempgot + fifo_cc_got_tempput + fifo_glue + fifo_ic_assembly + fifo_ic_got + fifo_shift diff --git a/docs/IPCores/index.rst b/docs/IPCores/index.rst new file mode 100644 index 00000000..4ecd9237 --- /dev/null +++ b/docs/IPCores/index.rst @@ -0,0 +1,29 @@ +.. _NS: + +IP Core Documentations +###################### + +Namespace for Packages: + +.. toctree:: + + common + sim + +Namespaces for Entities: + +.. toctree:: + + alt + arith + bus + cache + comm + dstruct + fifo + io + mem + misc + net + sort + xil diff --git a/docs/IPCores/io/ddrio/ddrio.pkg.rst b/docs/IPCores/io/ddrio/ddrio.pkg.rst new file mode 100644 index 00000000..ed54e5f3 --- /dev/null +++ b/docs/IPCores/io/ddrio/ddrio.pkg.rst @@ -0,0 +1,19 @@ +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/ddrio/ddrio.pkg.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` + +.. _PKG:ddrio: + +PoC.io.ddrio Package +==================== + +.. only:: latex + + Source file: :pocsrc:`ddrio.pkg.vhdl ` diff --git a/docs/IPCores/io/ddrio/ddrio_in.rst b/docs/IPCores/io/ddrio/ddrio_in.rst new file mode 100644 index 00000000..927f3f47 --- /dev/null +++ b/docs/IPCores/io/ddrio/ddrio_in.rst @@ -0,0 +1,77 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:ddrio_in: + +PoC.io.ddrio.in +############### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/ddrio/ddrio_in.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/ddrio/ddrio_in_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +Instantiates chip-specific :abbr:`DDR (Double Data Rate)` input registers. + +Both data ``DataIn_high/low`` are synchronously outputted to the on-chip logic +with the rising edge of ``Clock``. ``DataIn_high`` is the value at the ``Pad`` +sampled with the same rising edge. ``DataIn_low`` is the value sampled with +the falling edge directly before this rising edge. Thus sampling starts with +the falling edge of the clock as depicted in the following waveform. + +.. wavedrom:: + + { signal: [ + ['DataIn', + {name: 'ClockIn', wave: 'L.H.L.H.L.H.L.H.L.'}, + {name: 'ClockInEnable', wave: '01............0...'}, + {name: 'DataIn_low', wave: 'x.....2...4...x...', data: ['0', '2'], node: '......u...w.'}, + {name: 'DataIn_high', wave: 'x.....3...5...x...', data: ['1', '3'], node: '......v...x.'} + ], + {name: 'Pad', wave: 'x2.3.4.5.x........', data: ['0', '1', '2', '3'], node: '.a.b.c.d.....'}, + ], + edge: ['a~>u', 'b~>v', 'c~>w', 'd~>x'], + foot: { + text: ['tspan', + ['tspan', {'font-weight': 'bold'}, 'PoC.io.ddrio.inout'], + ' -- DDR Data Input/Output sampled from pad.' + ] + } + } + +After power-up, the output ports ``DataIn_high`` and ``DataIn_low`` both equal +INIT_VALUE. + +``Pad`` must be connected to a PAD because FPGAs only have these registers in +IOBs. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/ddrio/ddrio_in.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 74-86 + + + +.. only:: latex + + Source file: :pocsrc:`io/ddrio/ddrio_in.vhdl ` diff --git a/docs/IPCores/io/ddrio/ddrio_inout.rst b/docs/IPCores/io/ddrio/ddrio_inout.rst new file mode 100644 index 00000000..de0708df --- /dev/null +++ b/docs/IPCores/io/ddrio/ddrio_inout.rst @@ -0,0 +1,92 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:ddrio_inout: + +PoC.io.ddrio.inout +################## + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/ddrio/ddrio_inout.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/ddrio/ddrio_inout_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +Instantiates chip-specific :abbr:`DDR (Double Data Rate)` input and output +registers. + +Both data ``DataOut_high/low`` as well as ``OutputEnable`` are sampled with +the ``rising_edge(Clock)`` from the on-chip logic. ``DataOut_high`` is brought +out with this rising edge. ``DataOut_low`` is brought out with the falling +edge. + +``OutputEnable`` (Tri-State) is high-active. It is automatically inverted if +necessary. Output is disabled after power-up. + +Both data ``DataIn_high/low`` are synchronously outputted to the on-chip logic +with the rising edge of ``Clock``. ``DataIn_high`` is the value at the ``Pad`` +sampled with the same rising edge. ``DataIn_low`` is the value sampled with +the falling edge directly before this rising edge. Thus sampling starts with +the falling edge of the clock as depicted in the following waveform. + +.. wavedrom:: + + { signal: [ + ['DataOut', + {name: 'ClockOut', wave: 'LH.L.H.L.H.L.H.L.H.L.H.'}, + {name: 'ClockOutEnable', wave: '0..1...................'}, + {name: 'OutputEnable', wave: '0.......1.......0......'}, + {name: 'DataOut_low', wave: 'x.......2...4...x......', data: ['4', '6'], node: '........k...m...o..'}, + {name: 'DataOut_high', wave: 'x.......3...5...x......', data: ['5', '7'], node: '........l...n...p..'} + ], + {}, + {name: 'Pad', wave: 'x2.3.4.5.z...2.3.4.5.z.', data: ['0', '1', '2', '3', '4', '5', '6', '7'], node: '.a.b.c.d.....e.f.g.h.'}, + {}, + ['DataIn', + {name: 'ClockIn', wave: 'L.H.L.H.L.H.L.H.L.H.L.H'}, + {name: 'ClockInEnable', wave: '01.......0.............'}, + {name: 'DataIn_low', wave: 'x.....2...4...z...2...4', data: ['0', '2', '4'], node: '......u...w.......y..'}, + {name: 'DataIn_high', wave: 'x.....3...5...z...3...5', data: ['1', '3', '5'], node: '......v...x.......z..'} + ] + ], + edge: ['a~>u', 'b~>v', 'c~>w', 'd~>x', 'k~>e', 'l~>f', 'm~>g', 'n~>h', 'e~>y', 'f~>z'], + foot: { + text: ['tspan', + ['tspan', {'font-weight': 'bold'}, 'PoC.io.ddrio.inout'], + ' -- DDR Data Input/Output sampled from pad.' + ] + } + } + +``Pad`` must be connected to a PAD because FPGAs only have these registers in +IOBs. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/ddrio/ddrio_inout.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 89-107 + + + +.. only:: latex + + Source file: :pocsrc:`io/ddrio/ddrio_inout.vhdl ` diff --git a/docs/IPCores/io/ddrio/ddrio_out.rst b/docs/IPCores/io/ddrio/ddrio_out.rst new file mode 100644 index 00000000..d1acc9fa --- /dev/null +++ b/docs/IPCores/io/ddrio/ddrio_out.rst @@ -0,0 +1,82 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:ddrio_out: + +PoC.io.ddrio.out +################ + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/ddrio/ddrio_out.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/ddrio/ddrio_out_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +Instantiates chip-specific :abbr:`DDR (Double Data Rate)` output registers. + +Both data ``DataOut_high/low`` as well as ``OutputEnable`` are sampled with +the ``rising_edge(Clock)`` from the on-chip logic. ``DataOut_high`` is brought +out with this rising edge. ``DataOut_low`` is brought out with the falling +edge. + +``OutputEnable`` (Tri-State) is high-active. It is automatically inverted if +necessary. If an output enable is not required, you may save some logic by +setting ``NO_OUTPUT_ENABLE = true``. + +If ``NO_OUTPUT_ENABLE = false`` then output is disabled after power-up. +If ``NO_OUTPUT_ENABLE = true`` then output after power-up equals ``INIT_VALUE``. + +.. wavedrom:: + + { signal: [ + ['DataOut', + {name: 'ClockOut', wave: 'L.H.L.H.L.H.L.H.'}, + {name: 'ClockOutEnable', wave: '01...........0..'}, + {name: 'OutputEnable', wave: '01.......0......'}, + {name: 'DataOut_low', wave: 'x2...4...x......', data: ['0', '2'], node: '.k...m'}, + {name: 'DataOut_high', wave: 'x3...5...x......', data: ['1', '3'], node: '.l...n'} + ], + {}, + {name: 'Pad', wave: 'x.....2.3.4.5.z.', data: ['0', '1', '2', '3'], node: '......a.b.c.d.'}, + ], + edge: ['k~>a', 'l~>b', 'm~>c', 'n~>d'], + foot: { + text: ['tspan', + ['tspan', {'font-weight': 'bold'}, 'PoC.io.ddrio.out'], + ' -- DDR Data Output sampled from pad.' + ] + } + } + +``Pad`` must be connected to a PAD because FPGAs only have these registers in +IOBs. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/ddrio/ddrio_out.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 79-93 + + + +.. only:: latex + + Source file: :pocsrc:`io/ddrio/ddrio_out.vhdl ` diff --git a/docs/IPCores/io/ddrio/index.rst b/docs/IPCores/io/ddrio/index.rst new file mode 100644 index 00000000..0960d607 --- /dev/null +++ b/docs/IPCores/io/ddrio/index.rst @@ -0,0 +1,25 @@ +.. _NS:ddrio: + +PoC.io.ddrio +============ + +These are :abbr:`DDR-I/O (Double Data Rate - Input/Output)` entities.... + +**Entities** + + * :ref:`IP:ddrio_in` + * :ref:`IP:ddrio_inout` + * :ref:`IP:ddrio_out` + + +.. toctree:: + :hidden: + + Package + +.. toctree:: + :hidden: + + ddrio_in + ddrio_inout + ddrio_out diff --git a/docs/IPCores/io/iic/iic.pkg.rst b/docs/IPCores/io/iic/iic.pkg.rst new file mode 100644 index 00000000..32081b55 --- /dev/null +++ b/docs/IPCores/io/iic/iic.pkg.rst @@ -0,0 +1,19 @@ +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/iic/iic.pkg.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` + +.. _PKG:iic: + +PoC.io.iic Package +================== + +.. only:: latex + + Source file: :pocsrc:`iic.pkg.vhdl ` diff --git a/docs/IPCores/io/iic/iic_BusController.rst b/docs/IPCores/io/iic/iic_BusController.rst new file mode 100644 index 00000000..5f605701 --- /dev/null +++ b/docs/IPCores/io/iic/iic_BusController.rst @@ -0,0 +1,48 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:iic_BusController: + +PoC.io.iic.BusController +######################## + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/iic/iic_BusController.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/iic/iic_BusController_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +The I2C BusController transmitts bits over the I2C bus (SerialClock - SCL, +SerialData - SDA) and also receives them. To send/receive words over the +I2C bus, use the I2C Controller, which utilizes this controller. This +controller is compatible to the System Management Bus (SMBus). + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/iic/iic_BusController.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 47-65 + + + +.. only:: latex + + Source file: :pocsrc:`io/iic/iic_BusController.vhdl ` diff --git a/docs/IPCores/io/iic/iic_Controller.rst b/docs/IPCores/io/iic/iic_Controller.rst new file mode 100644 index 00000000..bb48406c --- /dev/null +++ b/docs/IPCores/io/iic/iic_Controller.rst @@ -0,0 +1,48 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:iic_Controller: + +PoC.io.iic.Controller +##################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/iic/iic_Controller.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/iic/iic_Controller_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +The I2C Controller transmitts words over the I2C bus (SerialClock - SCL, +SerialData - SDA) and also receives them. This controller utilizes the +I2C BusController to send/receive bits over the I2C bus. This controller +is compatible to the System Management Bus (SMBus). + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/iic/iic_Controller.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 47-82 + + + +.. only:: latex + + Source file: :pocsrc:`io/iic/iic_Controller.vhdl ` diff --git a/docs/IPCores/io/iic/iic_Controller_SFF8431.rst b/docs/IPCores/io/iic/iic_Controller_SFF8431.rst new file mode 100644 index 00000000..c4c5c1b0 --- /dev/null +++ b/docs/IPCores/io/iic/iic_Controller_SFF8431.rst @@ -0,0 +1,43 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:IICController_SFF8431: + +PoC.io.iic.Controller_SFF8431 +############################# + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/iic/iic_Controller_SFF8431.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/iic/iic_Controller_SFF8431_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/iic/iic_Controller_SFF8431.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 15-49 + + + +.. only:: latex + + Source file: :pocsrc:`io/iic/iic_Controller_SFF8431.vhdl ` diff --git a/docs/IPCores/io/iic/iic_Switch_PCA9548A.rst b/docs/IPCores/io/iic/iic_Switch_PCA9548A.rst new file mode 100644 index 00000000..d369b936 --- /dev/null +++ b/docs/IPCores/io/iic/iic_Switch_PCA9548A.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:iic_Switch_PCA9548A: + +PoC.io.iic.Switch_PCA9548A +########################## + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/iic/iic_Switch_PCA9548A.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/iic/iic_Switch_PCA9548A_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. TODO + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/iic/iic_Switch_PCA9548A.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-90 + + + +.. only:: latex + + Source file: :pocsrc:`io/iic/iic_Switch_PCA9548A.vhdl ` diff --git a/docs/IPCores/io/iic/index.rst b/docs/IPCores/io/iic/index.rst new file mode 100644 index 00000000..d0c7e20b --- /dev/null +++ b/docs/IPCores/io/iic/index.rst @@ -0,0 +1,18 @@ +.. _NS:iic: + +PoC.io.iic +========== + +These are I2C entities.... + +.. toctree:: + :hidden: + + Package + +.. toctree:: + :hidden: + + iic_BusController + iic_Controller + iic_Switch_PCA9548A diff --git a/docs/PoC/io/index.rst b/docs/IPCores/io/index.rst similarity index 83% rename from docs/PoC/io/index.rst rename to docs/IPCores/io/index.rst index 65c21ad4..3723afcf 100644 --- a/docs/PoC/io/index.rst +++ b/docs/IPCores/io/index.rst @@ -1,6 +1,7 @@ +.. _NS:io: -io -== +PoC.io +====== The namespace ``PoC.io`` offers different general purpose I/O (GPIO) implementations, as well as low-speed bus protocol controllers. @@ -32,22 +33,29 @@ The package :doc:`PoC.io ` holds all enum, function and component declar * :doc:`PoC.io.PulseWidthModulation ` * :doc:`PoC.io.TimingCounter ` + +.. toctree:: + :hidden: + + ddrio + iic + jtag + lcd + mdio + ow + pio + pmod + ps2 + uart + vga + .. toctree:: :hidden: - ddrio/index - iic/index - jtag/index - lcd/index - mdio/index - ow/index - pio/index - pmod/index - ps2/index - uart/index - vga/index - - io.pkg + Package + +.. toctree:: + :hidden: io_7SegmentMux_BCD io_7SegmentMux_HEX diff --git a/docs/IPCores/io/io.pkg.rst b/docs/IPCores/io/io.pkg.rst new file mode 100644 index 00000000..97c941c0 --- /dev/null +++ b/docs/IPCores/io/io.pkg.rst @@ -0,0 +1,21 @@ +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/io.pkg.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` + +.. _PKG:io: + +PoC.io Package +============== + +This package holds all component declarations for this namespace. + +.. only:: latex + + Source file: :pocsrc:`io.pkg.vhdl ` diff --git a/docs/IPCores/io/io_7SegmentMux_BCD.rst b/docs/IPCores/io/io_7SegmentMux_BCD.rst new file mode 100644 index 00000000..b0946660 --- /dev/null +++ b/docs/IPCores/io/io_7SegmentMux_BCD.rst @@ -0,0 +1,48 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:io_7SegmentMux_BCD: + +PoC.io.7SegmentMux_BCD +###################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/io_7SegmentMux_BCD.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/io_7SegmentMux_BCD_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +This module is a 7 segment display controller that uses time multiplexing +to control a common anode for each digit in the display. The shown characters +are BCD encoded. A dot per digit is optional. A minus sign for negative +numbers is supported. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/io/io_7SegmentMux_BCD.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 45-60 + + + +.. only:: latex + + Source file: :pocsrc:`io/io_7SegmentMux_BCD.vhdl ` diff --git a/docs/IPCores/io/io_7SegmentMux_HEX.rst b/docs/IPCores/io/io_7SegmentMux_HEX.rst new file mode 100644 index 00000000..dd3c016b --- /dev/null +++ b/docs/IPCores/io/io_7SegmentMux_HEX.rst @@ -0,0 +1,47 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:io_7SegmentMux_HEX: + +PoC.io.7SegmentMux_HEX +###################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/io_7SegmentMux_HEX.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/io_7SegmentMux_HEX_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +This module is a 7 segment display controller that uses time multiplexing +to control a common anode for each digit in the display. The shown characters +are HEX encoded. A dot per digit is optional. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/io/io_7SegmentMux_HEX.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 45-60 + + + +.. only:: latex + + Source file: :pocsrc:`io/io_7SegmentMux_HEX.vhdl ` diff --git a/docs/IPCores/io/io_Debounce.rst b/docs/IPCores/io/io_Debounce.rst new file mode 100644 index 00000000..178d724a --- /dev/null +++ b/docs/IPCores/io/io_Debounce.rst @@ -0,0 +1,56 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:io_Debounce: + +PoC.io.Debounce +############### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/io_Debounce.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/io_Debounce_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +This module debounces several input pins preventing input changes +following a previous one within the configured ``BOUNCE_TIME`` to pass. +Internally, the forwarded state is locked for, at least, this ``BOUNCE_TIME``. +As the backing timer is restarted on every input fluctuation, the next +passing input update must have seen a stabilized input. + +The parameter ``COMMON_LOCK`` uses a single internal timer for all processed +inputs. Thus, all inputs must stabilize before any one may pass changed. +This option is usually fully acceptable for user inputs such as push buttons. + +The parameter ``ADD_INPUT_SYNCHRONIZERS`` triggers the optional instantiation +of a two-FF input synchronizer on each input bit. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/io/io_Debounce.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 52-67 + + + +.. only:: latex + + Source file: :pocsrc:`io/io_Debounce.vhdl ` diff --git a/docs/PoC/io/io_FanControl.rst b/docs/IPCores/io/io_FanControl.rst similarity index 50% rename from docs/PoC/io/io_FanControl.rst rename to docs/IPCores/io/io_FanControl.rst index f91d7bfa..f2c015d9 100644 --- a/docs/PoC/io/io_FanControl.rst +++ b/docs/IPCores/io/io_FanControl.rst @@ -1,6 +1,30 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include -io_FanControl -############# +.. include:: +.. include:: + +.. _IP:io_FanControl: + +PoC.io.FanControl +################# + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/io_FanControl.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/io_FanControl_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` .. code-block:: none @@ -33,7 +57,8 @@ io_FanControl :linenos: :lines: 63-81 -Source file: `io/io_FanControl.vhdl `_ +.. only:: latex + Source file: :pocsrc:`io/io_FanControl.vhdl ` diff --git a/docs/IPCores/io/io_FrequencyCounter.rst b/docs/IPCores/io/io_FrequencyCounter.rst new file mode 100644 index 00000000..da769a8e --- /dev/null +++ b/docs/IPCores/io/io_FrequencyCounter.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:io_FrequencyCounter: + +PoC.io.FrequencyCounter +####################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/io_FrequencyCounter.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/io_FrequencyCounter_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/io/io_FrequencyCounter.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 40-52 + + + +.. only:: latex + + Source file: :pocsrc:`io/io_FrequencyCounter.vhdl ` diff --git a/docs/IPCores/io/io_GlitchFilter.rst b/docs/IPCores/io/io_GlitchFilter.rst new file mode 100644 index 00000000..b510c0e7 --- /dev/null +++ b/docs/IPCores/io/io_GlitchFilter.rst @@ -0,0 +1,46 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:io_GlitchFilter: + +PoC.io.GlitchFilter +################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/io_GlitchFilter.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/io_GlitchFilter_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +This module filters glitches on a wire. The high and low spike suppression +cycle counts can be configured. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/io/io_GlitchFilter.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 41-51 + + + +.. only:: latex + + Source file: :pocsrc:`io/io_GlitchFilter.vhdl ` diff --git a/docs/IPCores/io/io_KeyPadScanner.rst b/docs/IPCores/io/io_KeyPadScanner.rst new file mode 100644 index 00000000..68d0219f --- /dev/null +++ b/docs/IPCores/io/io_KeyPadScanner.rst @@ -0,0 +1,49 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:io_KeyPadScanner: + +PoC.io.KeyPadScanner +#################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/io_KeyPadScanner.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/io_KeyPadScanner_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +This module drives a one-hot encoded column vector to read back a rows +vector. By scanning column-by-column it's possible to extract the current +button state of the whole keypad. The scanner uses high-active logic. The +keypad size and scan frequency can be configured. The outputed signal +matrix is not debounced. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/io/io_KeyPadScanner.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 46-63 + + + +.. only:: latex + + Source file: :pocsrc:`io/io_KeyPadScanner.vhdl ` diff --git a/docs/IPCores/io/io_PulseWidthModulation.rst b/docs/IPCores/io/io_PulseWidthModulation.rst new file mode 100644 index 00000000..907fe614 --- /dev/null +++ b/docs/IPCores/io/io_PulseWidthModulation.rst @@ -0,0 +1,46 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:io_PulseWidthModulation: + +PoC.io.PulseWidthModulation +########################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/io_PulseWidthModulation.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/io_PulseWidthModulation_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +This module generates a pulse width modulated signal, that can be configured +in frequency (``PWM_FREQ``) and modulation granularity (``PWM_RESOLUTION``). + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/io/io_PulseWidthModulation.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 41-53 + + + +.. only:: latex + + Source file: :pocsrc:`io/io_PulseWidthModulation.vhdl ` diff --git a/docs/IPCores/io/io_TimingCounter.rst b/docs/IPCores/io/io_TimingCounter.rst new file mode 100644 index 00000000..5e73423b --- /dev/null +++ b/docs/IPCores/io/io_TimingCounter.rst @@ -0,0 +1,48 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:io_TimingCounter: + +PoC.io.TimingCounter +#################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/io_TimingCounter.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/io_TimingCounter_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +This down-counter can be configured with a ``TIMING_TABLE`` (a ROM), from which +the initial counter value is loaded. The table index can be selected by +``Slot``. ``Timeout`` is a registered output. Up to 16 values fit into one ROM +consisting of ``log2ceilnz(imax(TIMING_TABLE)) + 1`` 6-input LUTs. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/io/io_TimingCounter.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 43-54 + + + +.. only:: latex + + Source file: :pocsrc:`io/io_TimingCounter.vhdl ` diff --git a/docs/IPCores/io/jtag/index.rst b/docs/IPCores/io/jtag/index.rst new file mode 100644 index 00000000..c5faf6d4 --- /dev/null +++ b/docs/IPCores/io/jtag/index.rst @@ -0,0 +1,10 @@ +.. _NS:jtag: + +PoC.io.jtag +=========== + +These are JTAG entities.... + +.. toctree:: + :hidden: + diff --git a/docs/PoC/io/lcd/BCDDigit.rst b/docs/IPCores/io/lcd/BCDDigit.rst similarity index 100% rename from docs/PoC/io/lcd/BCDDigit.rst rename to docs/IPCores/io/lcd/BCDDigit.rst diff --git a/docs/IPCores/io/lcd/index.rst b/docs/IPCores/io/lcd/index.rst new file mode 100644 index 00000000..6c4ac133 --- /dev/null +++ b/docs/IPCores/io/lcd/index.rst @@ -0,0 +1,19 @@ +.. _NS:lcd: + +PoC.io.lcd +========== + +These are LCD entities.... + +.. toctree:: + :hidden: + + Package + +.. toctree:: + :hidden: + + lcd_LCDBuffer + lcd_LCDBusController + lcd_LCDController_KS0066U + lcd_LCDSynchronizer diff --git a/docs/IPCores/io/lcd/lcd.pkg.rst b/docs/IPCores/io/lcd/lcd.pkg.rst new file mode 100644 index 00000000..c0b93e55 --- /dev/null +++ b/docs/IPCores/io/lcd/lcd.pkg.rst @@ -0,0 +1,19 @@ +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/lcd/lcd.pkg.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` + +.. _PKG:lcd: + +PoC.io.lcd Package +================== + +.. only:: latex + + Source file: :pocsrc:`lcd.pkg.vhdl ` diff --git a/docs/IPCores/io/lcd/lcd_LCDBuffer.rst b/docs/IPCores/io/lcd/lcd_LCDBuffer.rst new file mode 100644 index 00000000..71f4ee13 --- /dev/null +++ b/docs/IPCores/io/lcd/lcd_LCDBuffer.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:lcd_LCDBuffer: + +PoC.io.lcd.LCDBuffer +#################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/lcd/lcd_LCDBuffer.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/lcd/lcd_LCDBuffer_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/lcd/lcd_LCDBuffer.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-58 + + + +.. only:: latex + + Source file: :pocsrc:`io/lcd/lcd_LCDBuffer.vhdl ` diff --git a/docs/IPCores/io/lcd/lcd_LCDBusController.rst b/docs/IPCores/io/lcd/lcd_LCDBusController.rst new file mode 100644 index 00000000..3df150ad --- /dev/null +++ b/docs/IPCores/io/lcd/lcd_LCDBusController.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:lcd_LCDBusController: + +PoC.io.lcd.LCDBusController +########################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/lcd/lcd_LCDBusController.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/lcd/lcd_LCDBusController_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/lcd/lcd_LCDBusController.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 43-67 + + + +.. only:: latex + + Source file: :pocsrc:`io/lcd/lcd_LCDBusController.vhdl ` diff --git a/docs/IPCores/io/lcd/lcd_LCDController_KS0066U.rst b/docs/IPCores/io/lcd/lcd_LCDController_KS0066U.rst new file mode 100644 index 00000000..ddf85c92 --- /dev/null +++ b/docs/IPCores/io/lcd/lcd_LCDController_KS0066U.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:lcd_LCDController_KS0066U: + +PoC.io.lcd.LCDController_KS0066U +################################ + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/lcd/lcd_LCDController_KS0066U.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/lcd/lcd_LCDController_KS0066U_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/lcd/lcd_LCDController_KS0066U.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-64 + + + +.. only:: latex + + Source file: :pocsrc:`io/lcd/lcd_LCDController_KS0066U.vhdl ` diff --git a/docs/IPCores/io/lcd/lcd_LCDSynchronizer.rst b/docs/IPCores/io/lcd/lcd_LCDSynchronizer.rst new file mode 100644 index 00000000..ed9a0b7b --- /dev/null +++ b/docs/IPCores/io/lcd/lcd_LCDSynchronizer.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:lcd_LCDSynchronizer: + +PoC.io.lcd.LCDSynchronizer +########################## + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/lcd/lcd_LCDSynchronizer.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/lcd/lcd_LCDSynchronizer_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/lcd/lcd_LCDSynchronizer.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-64 + + + +.. only:: latex + + Source file: :pocsrc:`io/lcd/lcd_LCDSynchronizer.vhdl ` diff --git a/docs/IPCores/io/lcd/lcd_dotmatrix.rst b/docs/IPCores/io/lcd/lcd_dotmatrix.rst new file mode 100644 index 00000000..5604b7ad --- /dev/null +++ b/docs/IPCores/io/lcd/lcd_dotmatrix.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:lcd_dotmatrix: + +PoC.io.lcd.dotmatrix +#################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/lcd/lcd_dotmatrix.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/lcd/lcd_dotmatrix_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/lcd/lcd_dotmatrix.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 36-67 + + + +.. only:: latex + + Source file: :pocsrc:`io/lcd/lcd_dotmatrix.vhdl ` diff --git a/docs/IPCores/io/mdio/index.rst b/docs/IPCores/io/mdio/index.rst new file mode 100644 index 00000000..24bb8c4a --- /dev/null +++ b/docs/IPCores/io/mdio/index.rst @@ -0,0 +1,13 @@ +.. _NS:mdio: + +PoC.io.mdio +=========== + +These are MDIO entities.... + +.. toctree:: + :hidden: + + mdio_BusController + mdio_Controller + mdio_IIC_Adapter diff --git a/docs/PoC/io/mdio/mdio_BusController.rst b/docs/IPCores/io/mdio/mdio_BusController.rst similarity index 100% rename from docs/PoC/io/mdio/mdio_BusController.rst rename to docs/IPCores/io/mdio/mdio_BusController.rst diff --git a/docs/IPCores/io/mdio/mdio_Controller.rst b/docs/IPCores/io/mdio/mdio_Controller.rst new file mode 100644 index 00000000..ad603bb2 --- /dev/null +++ b/docs/IPCores/io/mdio/mdio_Controller.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:mdio_Controller: + +PoC.io.mdio.Controller +###################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/mdio/mdio_Controller.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/mdio/mdio_Controller_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/mdio/mdio_Controller.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 44-73 + + + +.. only:: latex + + Source file: :pocsrc:`io/mdio/mdio_Controller.vhdl ` diff --git a/docs/IPCores/io/mdio/mdio_IIC_Adapter.rst b/docs/IPCores/io/mdio/mdio_IIC_Adapter.rst new file mode 100644 index 00000000..20181eb3 --- /dev/null +++ b/docs/IPCores/io/mdio/mdio_IIC_Adapter.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:mdio_IIC_Adapter: + +PoC.io.mdio.IIC_Adapter +####################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/mdio/mdio_IIC_Adapter.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/mdio/mdio_IIC_Adapter_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/mdio/mdio_IIC_Adapter.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 44-80 + + + +.. only:: latex + + Source file: :pocsrc:`io/mdio/mdio_IIC_Adapter.vhdl ` diff --git a/docs/IPCores/io/ow/index.rst b/docs/IPCores/io/ow/index.rst new file mode 100644 index 00000000..21e868f0 --- /dev/null +++ b/docs/IPCores/io/ow/index.rst @@ -0,0 +1,12 @@ +.. _NS:ow: + +PoC.io.ow +========= + +These are OneWire entities.... + +.. toctree:: + :hidden: + + ow_BusController + ow_Controller diff --git a/docs/PoC/io/ow/ow_BusController.rst b/docs/IPCores/io/ow/ow_BusController.rst similarity index 100% rename from docs/PoC/io/ow/ow_BusController.rst rename to docs/IPCores/io/ow/ow_BusController.rst diff --git a/docs/PoC/io/ow/ow_Controller.rst b/docs/IPCores/io/ow/ow_Controller.rst similarity index 100% rename from docs/PoC/io/ow/ow_Controller.rst rename to docs/IPCores/io/ow/ow_Controller.rst diff --git a/docs/IPCores/io/pio/index.rst b/docs/IPCores/io/pio/index.rst new file mode 100644 index 00000000..b66aca7c --- /dev/null +++ b/docs/IPCores/io/pio/index.rst @@ -0,0 +1,14 @@ +.. _NS:pio: + +PoC.io.pio +========== + +These are Pmod entities.... + +.. toctree:: + :hidden: + + pio_in + pio_out + pio_fifo_in + pio_fifo_out diff --git a/docs/IPCores/io/pio/pio_fifo_in.rst b/docs/IPCores/io/pio/pio_fifo_in.rst new file mode 100644 index 00000000..f2e57d82 --- /dev/null +++ b/docs/IPCores/io/pio/pio_fifo_in.rst @@ -0,0 +1,44 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:pio_fifo_in: + +PoC.io.pio.fifo_in +################## + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/pio/pio_fifo_in.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/pio/pio_fifo_in_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/pio/pio_fifo_in.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 38-55 + + + +.. only:: latex + + Source file: :pocsrc:`io/pio/pio_fifo_in.vhdl ` diff --git a/docs/IPCores/io/pio/pio_fifo_out.rst b/docs/IPCores/io/pio/pio_fifo_out.rst new file mode 100644 index 00000000..e50bbdb7 --- /dev/null +++ b/docs/IPCores/io/pio/pio_fifo_out.rst @@ -0,0 +1,44 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:pio_fifo_out: + +PoC.io.pio.fifo_out +################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/pio/pio_fifo_out.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/pio/pio_fifo_out_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/pio/pio_fifo_out.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 38-55 + + + +.. only:: latex + + Source file: :pocsrc:`io/pio/pio_fifo_out.vhdl ` diff --git a/docs/IPCores/io/pio/pio_in.rst b/docs/IPCores/io/pio/pio_in.rst new file mode 100644 index 00000000..e4869f25 --- /dev/null +++ b/docs/IPCores/io/pio/pio_in.rst @@ -0,0 +1,44 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:pio_in: + +PoC.io.pio.in +############# + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/pio/pio_in.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/pio/pio_in_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/pio/pio_in.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 40-55 + + + +.. only:: latex + + Source file: :pocsrc:`io/pio/pio_in.vhdl ` diff --git a/docs/IPCores/io/pio/pio_out.rst b/docs/IPCores/io/pio/pio_out.rst new file mode 100644 index 00000000..a7b895c7 --- /dev/null +++ b/docs/IPCores/io/pio/pio_out.rst @@ -0,0 +1,44 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:pio_out: + +PoC.io.pio.out +############## + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/pio/pio_out.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/pio/pio_out_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/pio/pio_out.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 40-55 + + + +.. only:: latex + + Source file: :pocsrc:`io/pio/pio_out.vhdl ` diff --git a/docs/IPCores/io/pmod/index.rst b/docs/IPCores/io/pmod/index.rst new file mode 100644 index 00000000..16a0ce73 --- /dev/null +++ b/docs/IPCores/io/pmod/index.rst @@ -0,0 +1,25 @@ +.. _NS:pmod: + +PoC.io.pmod +=========== + +These are Pmod entities.... + +**Entities** + + * :ref:`IP:pmod_KYPD` + * :ref:`IP:pmod_SSD` + * :ref:`IP:pmod_USBUART` + + +.. toctree:: + :hidden: + + Package + +.. toctree:: + :hidden: + + pmod_KYPD + pmod_SSD + pmod_USBUART diff --git a/docs/IPCores/io/pmod/pmod.pkg.rst b/docs/IPCores/io/pmod/pmod.pkg.rst new file mode 100644 index 00000000..c14884f6 --- /dev/null +++ b/docs/IPCores/io/pmod/pmod.pkg.rst @@ -0,0 +1,19 @@ +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/pmod/pmod.pkg.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` + +.. _PKG:pmod: + +PoC.io.pmod Package +=================== + +.. only:: latex + + Source file: :pocsrc:`pmod.pkg.vhdl ` diff --git a/docs/IPCores/io/pmod/pmod_KYPD.rst b/docs/IPCores/io/pmod/pmod_KYPD.rst new file mode 100644 index 00000000..0f7d8f50 --- /dev/null +++ b/docs/IPCores/io/pmod/pmod_KYPD.rst @@ -0,0 +1,50 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:pmod_KYPD: + +PoC.io.pmod.KYPD +################ + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/pmod/pmod_KYPD.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/pmod/pmod_KYPD_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +This module drives a 4-bit one-cold encoded column vector to read back a +4-bit rows vector. By scanning column-by-column it's possible to extract +the current button state of the whole keypad. This wrapper converts the +high-active signals from :doc:`PoC.io.KeypadScanner <../io_KeyPadScanner>` +to low-active signals for the pmod. An additional debounce circuit filters +the button signals. The scan frequency and bounce time can be configured. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/pmod/pmod_KYPD.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 46-61 + + + +.. only:: latex + + Source file: :pocsrc:`io/pmod/pmod_KYPD.vhdl ` diff --git a/docs/IPCores/io/pmod/pmod_SSD.rst b/docs/IPCores/io/pmod/pmod_SSD.rst new file mode 100644 index 00000000..3e13a55b --- /dev/null +++ b/docs/IPCores/io/pmod/pmod_SSD.rst @@ -0,0 +1,58 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:pmod_SSD: + +PoC.io.pmod.SSD +############### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/pmod/pmod_SSD.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/pmod/pmod_SSD_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +This module drives a dual-digit 7-segment display (Pmod_SSD). The module +expects two binary encoded 4-bit ``Digit`` signals and drives a 2x6 bit +Pmod connector (7 anode bits, 1 cathode bit). + +.. code-block:: none + + Segment Pos./ Index + AAA | 000 + F B | 5 1 + F B | 5 1 + GGG | 666 + E C | 4 2 + E C | 4 2 + DDD DOT | 333 7 + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/pmod/pmod_SSD.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 56-69 + + + +.. only:: latex + + Source file: :pocsrc:`io/pmod/pmod_SSD.vhdl ` diff --git a/docs/IPCores/io/pmod/pmod_USBUART.rst b/docs/IPCores/io/pmod/pmod_USBUART.rst new file mode 100644 index 00000000..a1d34d33 --- /dev/null +++ b/docs/IPCores/io/pmod/pmod_USBUART.rst @@ -0,0 +1,48 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:pmod_USBUART: + +PoC.io.pmod.USBUART +################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/pmod/pmod_USBUART.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/pmod/pmod_USBUART_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +This module abstracts a FTDI FT232R USB-UART bridge by instantiating a +:doc:`PoC.io.uart.fifo <../uart/uart_fifo>`. The FT232R supports up to +3 MBaud. A synchronous FIFO interface with a 32 words buffer is provided. +Hardware flow control (RTS_CTS) is enabled. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/pmod/pmod_USBUART.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 43-65 + + + +.. only:: latex + + Source file: :pocsrc:`io/pmod/pmod_USBUART.vhdl ` diff --git a/docs/IPCores/io/ps2/index.rst b/docs/IPCores/io/ps2/index.rst new file mode 100644 index 00000000..9cd1c3a2 --- /dev/null +++ b/docs/IPCores/io/ps2/index.rst @@ -0,0 +1,9 @@ +.. _NS:ps2: + +PoC.io.ps2 +========== + +These are PS/2 entities.... + +.. toctree:: + :hidden: diff --git a/docs/IPCores/io/uart/index.rst b/docs/IPCores/io/uart/index.rst new file mode 100644 index 00000000..45ed08f6 --- /dev/null +++ b/docs/IPCores/io/uart/index.rst @@ -0,0 +1,27 @@ +.. _NS:uart: + +PoC.io.uart +=========== + +These are :abbr:`UART (Universal Asynchronous Receiver Transmitter)` entities.... + +**Entities** + + * :ref:`IP:uart_bclk` + * :ref:`IP:uart_rx` + * :ref:`IP:uart_tx` + * :ref:`IP:uart_fifo` + + +.. toctree:: + :hidden: + + Package + +.. toctree:: + :hidden: + + uart_bclk + uart_rx + uart_tx + uart_fifo diff --git a/docs/IPCores/io/uart/uart.pkg.rst b/docs/IPCores/io/uart/uart.pkg.rst new file mode 100644 index 00000000..37d06f2a --- /dev/null +++ b/docs/IPCores/io/uart/uart.pkg.rst @@ -0,0 +1,19 @@ +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/uart/uart.pkg.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` + +.. _PKG:uart: + +PoC.io.uart Package +=================== + +.. only:: latex + + Source file: :pocsrc:`uart.pkg.vhdl ` diff --git a/docs/IPCores/io/uart/uart_bclk.rst b/docs/IPCores/io/uart/uart_bclk.rst new file mode 100644 index 00000000..32710006 --- /dev/null +++ b/docs/IPCores/io/uart/uart_bclk.rst @@ -0,0 +1,51 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:uart_bclk: + +PoC.io.uart.bclk +################ + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/uart/uart_bclk.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/uart/uart_bclk_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + +old comments: + :abbr:`UART (Universal Asynchronous Receiver Transmitter)` BAUD rate generator + bclk_r = bit clock is rising + bclk_x8_r = bit clock times 8 is rising + + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/uart/uart_bclk.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 50-61 + + + +.. only:: latex + + Source file: :pocsrc:`io/uart/uart_bclk.vhdl ` diff --git a/docs/IPCores/io/uart/uart_fifo.rst b/docs/IPCores/io/uart/uart_fifo.rst new file mode 100644 index 00000000..9730b0c8 --- /dev/null +++ b/docs/IPCores/io/uart/uart_fifo.rst @@ -0,0 +1,53 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:uart_fifo: + +PoC.io.uart.fifo +################ + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/uart/uart_fifo.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/uart/uart_fifo_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +Small :abbr:`FIFO (first-in, first-out)` s are included in this module, if +larger or asynchronous transmit / receive FIFOs are required, then they must +be connected externally. + +old comments: + :abbr:`UART (Universal Asynchronous Receiver Transmitter)` BAUD rate generator + bclk = bit clock is rising + bclk_x8 = bit clock times 8 is rising + + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/uart/uart_fifo.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 52-94 + + + +.. only:: latex + + Source file: :pocsrc:`io/uart/uart_fifo.vhdl ` diff --git a/docs/IPCores/io/uart/uart_ft245.rst b/docs/IPCores/io/uart/uart_ft245.rst new file mode 100644 index 00000000..3d2845c4 --- /dev/null +++ b/docs/IPCores/io/uart/uart_ft245.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:uart_ft245: + +PoC.io.uart.ft245 +################# + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/uart/uart_ft245.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/uart/uart_ft245_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/uart/uart_ft245.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 37-63 + + + +.. only:: latex + + Source file: :pocsrc:`io/uart/uart_ft245.vhdl ` diff --git a/docs/IPCores/io/uart/uart_rx.rst b/docs/IPCores/io/uart/uart_rx.rst new file mode 100644 index 00000000..094445e0 --- /dev/null +++ b/docs/IPCores/io/uart/uart_rx.rst @@ -0,0 +1,46 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:uart_rx: + +PoC.io.uart.rx +############## + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/uart/uart_rx.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/uart/uart_rx_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +:abbr:`UART (Universal Asynchronous Receiver Transmitter)` Receiver: +1 Start + 8 Data + 1 Stop + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/uart/uart_rx.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 39-56 + + + +.. only:: latex + + Source file: :pocsrc:`io/uart/uart_rx.vhdl ` diff --git a/docs/IPCores/io/uart/uart_tx.rst b/docs/IPCores/io/uart/uart_tx.rst new file mode 100644 index 00000000..47911a65 --- /dev/null +++ b/docs/IPCores/io/uart/uart_tx.rst @@ -0,0 +1,46 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:uart_tx: + +PoC.io.uart.tx +############## + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/uart/uart_tx.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/uart/uart_tx_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +:abbr:`UART (Universal Asynchronous Receiver Transmitter)` Transmitter: +1 Start + 8 Data + 1 Stop + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/uart/uart_tx.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 35-50 + + + +.. only:: latex + + Source file: :pocsrc:`io/uart/uart_tx.vhdl ` diff --git a/docs/IPCores/io/vga/index.rst b/docs/IPCores/io/vga/index.rst new file mode 100644 index 00000000..49c6c421 --- /dev/null +++ b/docs/IPCores/io/vga/index.rst @@ -0,0 +1,18 @@ +.. _NS:vga: + +PoC.io.vga +========== + +These are VGA entities.... + +.. toctree:: + :hidden: + + Package + +.. toctree:: + :hidden: + + vga_phy + vga_phy_ch7301c + vga_timing diff --git a/docs/IPCores/io/vga/vga.pkg.rst b/docs/IPCores/io/vga/vga.pkg.rst new file mode 100644 index 00000000..d90f2041 --- /dev/null +++ b/docs/IPCores/io/vga/vga.pkg.rst @@ -0,0 +1,19 @@ +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/vga/vga.pkg.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` + +.. _PKG:vga: + +PoC.io.vga Package +================== + +.. only:: latex + + Source file: :pocsrc:`vga.pkg.vhdl ` diff --git a/docs/IPCores/io/vga/vga_phy.rst b/docs/IPCores/io/vga/vga_phy.rst new file mode 100644 index 00000000..d928c1a8 --- /dev/null +++ b/docs/IPCores/io/vga/vga_phy.rst @@ -0,0 +1,49 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:vga_phy: + +PoC.io.vga.phy +############## + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/vga/vga_phy.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/vga/vga_phy_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + + The clock frequency must be the same as used for the timing module. + + The number of color-bits per pixel can be configured with the generic + "COLOR_BITS". The format of the pixel data is defined the picture generator + in use. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/vga/vga_phy.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 43-55 + + + +.. only:: latex + + Source file: :pocsrc:`io/vga/vga_phy.vhdl ` diff --git a/docs/IPCores/io/vga/vga_phy_ch7301c.rst b/docs/IPCores/io/vga/vga_phy_ch7301c.rst new file mode 100644 index 00000000..fed2655c --- /dev/null +++ b/docs/IPCores/io/vga/vga_phy_ch7301c.rst @@ -0,0 +1,76 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:vga_phy_ch7301c: + +PoC.io.vga.phy_ch7301c +###################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/vga/vga_phy_ch7301c.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/vga/vga_phy_ch7301c_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +The clock frequency must be the same as used for the timing module, +e.g., 25 MHZ for VGA 640x480. A phase-shifted clock must be provided: +- clk0 : 0 degrees +- clk90 : 90 degrees + +pixel_data(23 downto 16) : red +pixel_data(15 downto 8) : green +pixel_data( 7 downto 0) : blue + +The ``reset_b``-pin must be driven by other logic (such as the reset button). + +The IIC_interface is not part of this modules, as an IIC-master controls +several slaves. The following registers must be set, see +tests/ml505/vga_test_ml505.vhdl for an example. + ++----------+--------------------------------------+---------------------------------+ +| Register | Value | Description | ++==========+======================================+=================================+ +|0x49 PM | 0xC0 | Enable DVI, RGB bypass off | +| | 0xD0 | Enable DVI, RGB bypass on | ++----------+--------------------------------------+---------------------------------+ +|0x33 TPCP | 0x08 if clk_freq <= 65 MHz else 0x06 | | ++----------+--------------------------------------+---------------------------------+ +|0x34 TPD | 0x16 if clk_freq <= 65 MHz else 0x26 | | ++----------+--------------------------------------+---------------------------------+ +|0x36 TPF | 0x60 if clk_freq <= 65 MHz else 0xA0 | | ++----------+--------------------------------------+---------------------------------+ +|0x1F IDF | 0x80 | when using SMT (VS0, HS0) | +| | 0x90 | when using CVT (VS1, HS0) | ++----------+--------------------------------------+---------------------------------+ +|0x21 DC | 0x09 | Enable DAC if RGB bypass is on | ++----------+--------------------------------------+---------------------------------+ + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/vga/vga_phy_ch7301c.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 70-83 + + + +.. only:: latex + + Source file: :pocsrc:`io/vga/vga_phy_ch7301c.vhdl ` diff --git a/docs/IPCores/io/vga/vga_timing.rst b/docs/IPCores/io/vga/vga_timing.rst new file mode 100644 index 00000000..c41c34f2 --- /dev/null +++ b/docs/IPCores/io/vga/vga_timing.rst @@ -0,0 +1,84 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:vga_timing: + +PoC.io.vga.timing +################# + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/vga/vga_timing.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/io/vga/vga_timing_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +Configuration: +-------------- +MODE = 0: VGA mode with 640x480 pixels, 60 Hz, frequency(clk) ~ 25 MHz +MODE = 1: HD 720p with 1280x720 pixels, 60 Hz, frequency(clk) = 74,5 MHz +MODE = 2: HD 1080p with 1920x1080 pixels, 60 Hz, frequency(clk) = 138,5 MHz + +MODE = 2 uses reduced blanking => only suitable for LCDs. + +For MODE = 0, CVT can be configured: +- CVT = false: Use Safe Mode Timing (SMT). + The legacy fall-back mode supported by CRTs as well as LCDs. + HSync: low-active. VSync: low-active. + frequency(clk) = 25.175 MHz. (25 MHz works => 31 kHz / 59 Hz) +- CVT = true: The "new" Coordinated Video Timing (since 2003). + The CVT supports some new features, such as reduced blanking (for LCDs) or + aspect ratio encoding. See the web for more details. + Standard CRT-based timing (CVT-GTF) has been implemented for best + compatibility: + HSync: low-active. VSync: high-active. + frequency(clk) = 23.75 MHz. (25 MHz works => 31 kHz / 62 Hz) + +Usage: +------ +The frequency of ``clk`` must be equal to the pixel clock frequency of the +selected video mode, see also above. + +When using analog output, the VGA color signals must be blanked, during +horizontal and vertical beam return. This could be achieved by +combinatorial "anding" the color value with "beam_on" (part of "phy_ctrl") +inside the PHY. + +When using digital output (DVI), then "beam_on" is equal to "DE" +(Data Enable) of the DVI transmitter. + +xvalid and yvalid show if xpos respectivly ypos are in a valid range. +beam_on is '1' iff both xvalid and yvalid = '1'. + +xpos and ypos also show the pixel location during blanking. +This might be useful in some applications. But be careful, that the ranges +differ between SMT and CVT. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/io/vga/vga_timing.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 80-96 + + + +.. only:: latex + + Source file: :pocsrc:`io/vga/vga_timing.vhdl ` diff --git a/docs/IPCores/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.rst b/docs/IPCores/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.rst new file mode 100644 index 00000000..a87e1f96 --- /dev/null +++ b/docs/IPCores/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.rst @@ -0,0 +1,67 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:ddr2_mem2mig_adapter_Spartan6: + +PoC.mem.ddr2.mem2mig_adapter_Spartan6 +##################################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/ddr2/ddr2_mem2mig_adapter_Spartan6_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +Adapter between the :ref:`PoC.Mem ` +interface and the User Interface of the Xilinx MIG IP core for the +Spartan-6 FPGA Memory Controller Block (MCB). The MCB can be configured to +have multiple ports. One instance of this adapter is required for every +port. The control signals for one port of the MIG IP core are prefixed by +"cX_pY", meaning port Y on controller X. + +Simplifies the User Interface ("user") of the Xilinx MIG IP core (UG388). +The PoC.Mem interface provides single-cycle fully pipelined read/write access +to the memory. All accesses are word-aligned. Always all bytes of a word are +written to the memory. More details can be found +:ref:`here `. + +Generic parameters: + +* D_BITS: Data bus width of the PoC.Mem and MIG / MCBinterface. Also size of + one word in bits. + +* MEM_A_BITS: Address bus width of the PoC.Mem interface. + +* APP_A_BTIS: Address bus width of the MIG / MCB interface. + +Containts only combinational logic. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 61-96 + + + +.. only:: latex + + Source file: :pocsrc:`mem/ddr2/ddr2_mem2mig_adapter_Spartan6.vhdl ` diff --git a/docs/IPCores/mem/ddr2/index.rst b/docs/IPCores/mem/ddr2/index.rst new file mode 100644 index 00000000..1f98bb54 --- /dev/null +++ b/docs/IPCores/mem/ddr2/index.rst @@ -0,0 +1,22 @@ +.. _NS:ddr2: + +PoC.mem.ddr2 +============ + +The namespace ``PoC.mem.ddr2`` is designated for own implementations of +DDR2 memory controllers as well as for adapters for vendor-specific +implementations. At the top-level, all controllers and adapters +provide the same simple memory interface to the user application. + +.. **Package** + +**Entities** + + * :ref:`IP:ddr2_mem2mig_adapter_Spartan6` - Adapter for the Xilinx MIG core + for Spartan-6 FPGAs + + +.. toctree:: + :hidden: + + ddr2_mem2mig_adapter_Spartan6 diff --git a/docs/IPCores/mem/ddr3/ddr3_mem2mig_adapter_Series7.rst b/docs/IPCores/mem/ddr3/ddr3_mem2mig_adapter_Series7.rst new file mode 100644 index 00000000..46b46c38 --- /dev/null +++ b/docs/IPCores/mem/ddr3/ddr3_mem2mig_adapter_Series7.rst @@ -0,0 +1,66 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:ddr3_mem2mig_adapter_Series7: + +PoC.mem.ddr3.mem2mig_adapter_Series7 +#################################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ddr3/ddr3_mem2mig_adapter_Series7.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/ddr3/ddr3_mem2mig_adapter_Series7_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +Adapter between the :ref:`PoC.Mem ` interface and the +application interface ("app") of the Xilinx MIG IP core for 7-Series FPGAs. + +Simplifies the application interface ("app") of the Xilinx MIG IP core. +The PoC.Mem interface provides single-cycle fully pipelined read/write access +to the memory. All accesses are word-aligned. Always all bytes of a word are +written to the memory. More details can be found +:ref:`here `. + +Generic parameters: + +* D_BITS: Data bus width of the PoC.Mem and "app" interface. Also size of one + word in bits. + +* DQ_BITS: Size of data bus between memory controller and external memory + (DIMM, SoDIMM). + +* MEM_A_BITS: Address bus width of the PoC.Mem interface. + +* APP_A_BTIS: Address bus width of the "app" interface. + +Containts only combinational logic. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/mem/ddr3/ddr3_mem2mig_adapter_Series7.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 60-96 + + + +.. only:: latex + + Source file: :pocsrc:`mem/ddr3/ddr3_mem2mig_adapter_Series7.vhdl ` diff --git a/docs/IPCores/mem/ddr3/index.rst b/docs/IPCores/mem/ddr3/index.rst new file mode 100644 index 00000000..f6232571 --- /dev/null +++ b/docs/IPCores/mem/ddr3/index.rst @@ -0,0 +1,22 @@ +.. _NS:ddr3: + +PoC.mem.ddr3 +============ + +The namespace ``PoC.mem.ddr3`` is designated for own implementations of +DDR3 memory controllers as well as for adapters for vendor-specific +implementations. At the top-level, all controllers and adapters +provide the same simple memory interface to the user application. + +.. **Package** + +**Entities** + + * :ref:`IP:ddr3_mem2mig_adapter_Series7` - Adapter for the Xilinx MIG core + for 7-Series FPGAs + + +.. toctree:: + :hidden: + + ddr3_mem2mig_adapter_Series7 diff --git a/docs/IPCores/mem/index.rst b/docs/IPCores/mem/index.rst new file mode 100644 index 00000000..05a166f8 --- /dev/null +++ b/docs/IPCores/mem/index.rst @@ -0,0 +1,38 @@ +.. _NS:mem: + +PoC.mem +======== + +The namespace ``PoC.mem`` offers different on-chip and off-chip memory and memory-controller +implementations. + + +**Sub-Namespaces** + + * :ref:`NS:ddr2` - DDR2 memory controllers + * :ref:`NS:ddr3` - DDR3 memory controllers + * :ref:`NS:lut` - Lookup-Table (LUT) implementations + * :ref:`NS:ocram` - On-Chip RAM abstraction layer + * :ref:`NS:ocrom` - On-Chip ROM abstraction layer + * :ref:`NS:sdram` - SDRAM controllers + +**Package** + +:ref:`PoC.mem ` + + +.. toctree:: + :hidden: + + Package + +.. toctree:: + :hidden: + + ddr2 + ddr3 + lut + ocram + ocrom + sdram + diff --git a/docs/IPCores/mem/lut/index.rst b/docs/IPCores/mem/lut/index.rst new file mode 100644 index 00000000..c714731c --- /dev/null +++ b/docs/IPCores/mem/lut/index.rst @@ -0,0 +1,16 @@ +.. _NS:lut: + +PoC.mem.lut +=========== + +The namespace ``PoC.mem.lut`` offers different lookup-tables (LUTs). + +**Entities** + + * :ref:`IP:lut_Sine` - a Sine implementation with 1,2 or 4 quadrants. + + +.. toctree:: + :hidden: + + lut_Sine diff --git a/docs/IPCores/mem/lut/lut_Sine.rst b/docs/IPCores/mem/lut/lut_Sine.rst new file mode 100644 index 00000000..236f3939 --- /dev/null +++ b/docs/IPCores/mem/lut/lut_Sine.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:lut_Sine: + +PoC.mem.lut.Sine +################ + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/lut/lut_Sine.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/lut/lut_Sine_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/mem/lut/lut_Sine.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 41-54 + + + +.. only:: latex + + Source file: :pocsrc:`mem/lut/lut_Sine.vhdl ` diff --git a/docs/IPCores/mem/mem.pkg.rst b/docs/IPCores/mem/mem.pkg.rst new file mode 100644 index 00000000..35fa5997 --- /dev/null +++ b/docs/IPCores/mem/mem.pkg.rst @@ -0,0 +1,35 @@ +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/mem.pkg.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` + +.. _PKG:mem: + +PoC.mem Package +=============== + +This package holds all component declarations, types and functions of the +:ref:`PoC.mem ` namespace. + +It provides the following enumerations: + +* ``T_MEM_FILEFORMAT`` specifies whether a file is in Intel Hex, Lattice + Mem, or Xilinx Mem format. + +* ``T_MEM_CONTENT`` specifies whether data in text file is in binary, decimal + or hexadecimal format. + +It provides the following functions: + +* ``mem_FileExtension`` returns the file extension of a given filename. +* ``mem_ReadMemoryFile`` reads initial memory content from a given file. + +.. only:: latex + + Source file: :pocsrc:`mem.pkg.vhdl ` diff --git a/docs/IPCores/mem/ocram/index.rst b/docs/IPCores/mem/ocram/index.rst new file mode 100644 index 00000000..c415e438 --- /dev/null +++ b/docs/IPCores/mem/ocram/index.rst @@ -0,0 +1,59 @@ +.. _NS:ocram: + +PoC.mem.ocram +============= + +The namespace ``PoC.mem.ocram`` offers different on-chip RAM abstractions. + +**Package** + +The package PoC.mem.ocram holds all component declarations for this namespace. + +.. code-block:: VHDL + + library PoC; + use PoC.ocram.all; + + +**Entities** + + * :ref:`IP:ocram_sp` - An on-chip RAM with a single port interface. + * :ref:`IP:ocram_sdp` - An on-chip RAM with a simple dual-port interface. + * :ref:`IP:ocram_sdp_wf` - An on-chip RAM with a simple dual-port + interface and write-first behavior. + * :ref:`IP:ocram_tdp` - An on-chip RAM with a true dual-port interface. + * :ref:`IP:ocram_tdp_wf` - An on-chip RAM with a true dual-port + interface and write-first behavior. + +**Simulation Helper** + + * :ref:`IP:ocram_tdp_sim` - Simulation model of on-chip RAM with a true dual port interface. + +**Deprecated Entities** + + * :ref:`IP:ocram_esdp` - An on-chip RAM with an extended simple dual port interface. + + +.. toctree:: + :hidden: + + Package + +.. toctree:: + :hidden: + + ocram_sp + ocram_sdp + ocram_sdp_wf + ocram_tdp + ocram_tdp_wf + +.. toctree:: + :hidden: + + ocram_tdp_sim + +.. toctree:: + :hidden: + + ocram_esdp diff --git a/docs/IPCores/mem/ocram/ocram.pkg.rst b/docs/IPCores/mem/ocram/ocram.pkg.rst new file mode 100644 index 00000000..cd8bcb34 --- /dev/null +++ b/docs/IPCores/mem/ocram/ocram.pkg.rst @@ -0,0 +1,19 @@ +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ocram/ocram.pkg.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` + +.. _PKG:ocram: + +PoC.mem.ocram Package +===================== + +.. only:: latex + + Source file: :pocsrc:`ocram.pkg.vhdl ` diff --git a/docs/PoC/mem/ocram/ocram_esdp.rst b/docs/IPCores/mem/ocram/ocram_esdp.rst similarity index 55% rename from docs/PoC/mem/ocram/ocram_esdp.rst rename to docs/IPCores/mem/ocram/ocram_esdp.rst index 3c181384..d6276cc7 100644 --- a/docs/PoC/mem/ocram/ocram_esdp.rst +++ b/docs/IPCores/mem/ocram/ocram_esdp.rst @@ -1,17 +1,41 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include -ocram_esdp -########## +.. include:: +.. include:: + +.. _IP:ocram_esdp: + +PoC.mem.ocram.esdp +################## + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ocram/ocram_esdp.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/ocram/ocram_esdp_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` Inferring / instantiating enhanced simple dual-port memory, with: * dual clock, clock enable, * 1 read/write port (1st port) plus 1 read port (2nd port). -.. NOTE:: - This component is **deprecated**. - Please use :doc:`PoC.mem.ocram.tdp ` for new designs. +.. deprecated:: 1.1 + + **Please use** :ref:`IP:ocram_tdp` **for new designs. This component has been provided because older FPGA compilers where not - able to infer true dual-port memory from an RTL description. + able to infer true dual-port memory from an RTL description.** Command truth table for port 1: @@ -42,10 +66,7 @@ Stratix/Cyclone and Spartan-3/Virtex-5, respectively, is as follows: Same-Port Read-During-Write When writing data through port 1, the read output of the same port (``q1``) will output the new data (``d1``, in the following clock cycle) - which is aka. "write-first behavior". This behavior also applies to Altera - M20K memory blocks as described in the Altera: "Stratix 5 Device Handbook" - (S5-5V1). The documentation in the Altera: "Embedded Memory User Guide" - (UG-01068) is wrong. + which is aka. "write-first behavior". Mixed-Port Read-During-Write When reading at the write address, the read value will be unknown which is @@ -54,9 +75,8 @@ Mixed-Port Read-During-Write rising-edge of the write clock (``clk1``) and (in the worst case) extends until the next rising-edge of the write clock. -.. WARNING:: - The simulated behavior on RT-level is too optimistic. When reading - at the write address always the new data will be returned. +For simulation, always our dedicated simulation model :ref:`IP:ocram_tdp_sim` +is used. @@ -66,9 +86,10 @@ Mixed-Port Read-During-Write :language: vhdl :tab-width: 2 :linenos: - :lines: 101-119 + :lines: 97-115 -Source file: `mem/ocram/ocram_esdp.vhdl `_ +.. only:: latex + Source file: :pocsrc:`mem/ocram/ocram_esdp.vhdl ` diff --git a/docs/IPCores/mem/ocram/ocram_sdp.rst b/docs/IPCores/mem/ocram/ocram_sdp.rst new file mode 100644 index 00000000..8467dead --- /dev/null +++ b/docs/IPCores/mem/ocram/ocram_sdp.rst @@ -0,0 +1,65 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:ocram_sdp: + +PoC.mem.ocram.sdp +################# + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ocram/ocram_sdp.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/ocram/ocram_sdp_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +Inferring / instantiating simple dual-port memory, with: + +* dual clock, clock enable, +* 1 read port plus 1 write port. + +Both reading and writing are synchronous to the rising-edge of the clock. +Thus, when reading, the memory data will be outputted after the +clock edge, i.e, in the following clock cycle. + +The generalized behavior across Altera and Xilinx FPGAs since +Stratix/Cyclone and Spartan-3/Virtex-5, respectively, is as follows: + +Mixed-Port Read-During-Write + When reading at the write address, the read value will be unknown which is + aka. "don't care behavior". This applies to all reads (at the same + address) which are issued during the write-cycle time, which starts at the + rising-edge of the write clock and (in the worst case) extends until the + next rising-edge of the write clock. + +For simulation, always our dedicated simulation model :ref:`IP:ocram_tdp_sim` +is used. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/mem/ocram/ocram_sdp.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 65-82 + + + +.. only:: latex + + Source file: :pocsrc:`mem/ocram/ocram_sdp.vhdl ` diff --git a/docs/IPCores/mem/ocram/ocram_sdp_wf.rst b/docs/IPCores/mem/ocram/ocram_sdp_wf.rst new file mode 100644 index 00000000..7933e540 --- /dev/null +++ b/docs/IPCores/mem/ocram/ocram_sdp_wf.rst @@ -0,0 +1,67 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:ocram_sdp_wf: + +PoC.mem.ocram.sdp_wf +#################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ocram/ocram_sdp_wf.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/ocram/ocram_sdp_wf_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +Inferring / instantiating simple dual-port memory, with: + +* single clock, clock enable, +* 1 read port plus 1 write port. + +Command truth table: + +== == =============================== +ce we Command +== == =============================== +0 X No operation +1 0 Read only from memory +1 1 Read from and Write to memory +== == =============================== + +Both reading and writing are synchronous to the rising-edge of the clock. +Thus, when reading, the memory data will be outputted after the +clock edge, i.e, in the following clock cycle. + +Mixed-Port Read-During-Write + When reading at the write address, the read value will be the new data, + aka. "write-first behavior". Of course, the read is still synchronous, + i.e, the latency is still one clock cyle. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/mem/ocram/ocram_sdp_wf.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 57-72 + + + +.. only:: latex + + Source file: :pocsrc:`mem/ocram/ocram_sdp_wf.vhdl ` diff --git a/docs/IPCores/mem/ocram/ocram_sp.rst b/docs/IPCores/mem/ocram/ocram_sp.rst new file mode 100644 index 00000000..e749c5b3 --- /dev/null +++ b/docs/IPCores/mem/ocram/ocram_sp.rst @@ -0,0 +1,68 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:ocram_sp: + +PoC.mem.ocram.sp +################ + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ocram/ocram_sp.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/ocram/ocram_sp_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +Inferring / instantiating single port memory, with: + +* single clock, clock enable, +* 1 read/write port. + +Command Truth Table: + +== == ================ +ce we Command +== == ================ +0 X No operation +1 0 Read from memory +1 1 Write to memory +== == ================ + +Both reading and writing are synchronous to the rising-edge of the clock. +Thus, when reading, the memory data will be outputted after the +clock edge, i.e, in the following clock cycle. + +When writing data, the read output will output the new data (in the +following clock cycle) which is aka. "write-first behavior". This behavior +also applies to Altera M20K memory blocks as described in the Altera: +"Stratix 5 Device Handbook" (S5-5V1). The documentation in the Altera: +"Embedded Memory User Guide" (UG-01068) is wrong. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/mem/ocram/ocram_sp.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 68-82 + + + +.. only:: latex + + Source file: :pocsrc:`mem/ocram/ocram_sp.vhdl ` diff --git a/docs/IPCores/mem/ocram/ocram_tdp.rst b/docs/IPCores/mem/ocram/ocram_tdp.rst new file mode 100644 index 00000000..b71e0353 --- /dev/null +++ b/docs/IPCores/mem/ocram/ocram_tdp.rst @@ -0,0 +1,82 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:ocram_tdp: + +PoC.mem.ocram.tdp +################# + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ocram/ocram_tdp.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/ocram/ocram_tdp_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +Inferring / instantiating true dual-port memory, with: + +* dual clock, clock enable, +* 2 read/write ports. + +Command truth table for port 1, same applies to port 2: + +=== === ================ +ce1 we1 Command +=== === ================ +0 X No operation +1 0 Read from memory +1 1 Write to memory +=== === ================ + +Both reading and writing are synchronous to the rising-edge of the clock. +Thus, when reading, the memory data will be outputted after the +clock edge, i.e, in the following clock cycle. + +The generalized behavior across Altera and Xilinx FPGAs since +Stratix/Cyclone and Spartan-3/Virtex-5, respectively, is as follows: + +Same-Port Read-During-Write + When writing data through port 1, the read output of the same port + (``q1``) will output the new data (``d1``, in the following clock cycle) + which is aka. "write-first behavior". + + Same applies to port 2. + +Mixed-Port Read-During-Write + When reading at the write address, the read value will be unknown which is + aka. "don't care behavior". This applies to all reads (at the same + address) which are issued during the write-cycle time, which starts at the + rising-edge of the write clock and (in the worst case) extends + until the next rising-edge of that write clock. + +For simulation, always our dedicated simulation model :ref:`IP:ocram_tdp_sim` +is used. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/mem/ocram/ocram_tdp.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 82-102 + + + +.. only:: latex + + Source file: :pocsrc:`mem/ocram/ocram_tdp.vhdl ` diff --git a/docs/IPCores/mem/ocram/ocram_tdp_sim.rst b/docs/IPCores/mem/ocram/ocram_tdp_sim.rst new file mode 100644 index 00000000..db5dbdff --- /dev/null +++ b/docs/IPCores/mem/ocram/ocram_tdp_sim.rst @@ -0,0 +1,53 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:ocram_tdp_sim: + +PoC.mem.ocram.tdp_sim +##################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ocram/ocram_tdp_sim.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/ocram/ocram_tdp_sim_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +Simulation model for true dual-port memory, with: + +* dual clock, clock enable, +* 2 read/write ports. + +The interface matches that of the IP core PoC.mem.ocram.tdp. +But the implementation there is restricted to the description supported by +various synthesis compilers. The implementation here also simulates the +correct Mixed-Port Read-During-Write Behavior and handles X propagation. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/mem/ocram/ocram_tdp_sim.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 51-71 + + + +.. only:: latex + + Source file: :pocsrc:`mem/ocram/ocram_tdp_sim.vhdl ` diff --git a/docs/IPCores/mem/ocram/ocram_tdp_wf.rst b/docs/IPCores/mem/ocram/ocram_tdp_wf.rst new file mode 100644 index 00000000..22c7d623 --- /dev/null +++ b/docs/IPCores/mem/ocram/ocram_tdp_wf.rst @@ -0,0 +1,83 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:ocram_tdp_wf: + +PoC.mem.ocram.tdp_wf +#################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ocram/ocram_tdp_wf.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/ocram/ocram_tdp_wf_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +Inferring / instantiating true dual-port memory, with: + +* single clock, clock enable, +* 2 read/write ports. + +Command truth table: + +== === === ===================================================== +ce we1 we2 Command +== === === ===================================================== +0 X X No operation +1 0 0 Read only from memory +1 0 1 Read from memory on port 1, write to memory on port 2 +1 1 0 Write to memory on port 1, read from memory on port 2 +1 1 1 Write to memory on both ports +== === === ===================================================== + +Both reads and writes are synchronous to the clock. + +The generalized behavior across Altera and Xilinx FPGAs since +Stratix/Cyclone and Spartan-3/Virtex-5, respectively, is as follows: + +Same-Port Read-During-Write + When writing data through port 1, the read output of the same port + (``q1``) will output the new data (``d1``, in the following clock cycle) + which is aka. "write-first behavior". + + Same applies to port 2. + +Mixed-Port Read-During-Write + When reading at the write address, the read value will be the new data, + aka. "write-first behavior". Of course, the read is still synchronous, + i.e, the latency is still one clock cyle. + +If a write is issued on both ports to the same address, then the output of +this unit and the content of the addressed memory cell are undefined. + +For simulation, always our dedicated simulation model :ref:`IP:ocram_tdp_sim` +is used. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/mem/ocram/ocram_tdp_wf.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 83-101 + + + +.. only:: latex + + Source file: :pocsrc:`mem/ocram/ocram_tdp_wf.vhdl ` diff --git a/docs/IPCores/mem/ocrom/index.rst b/docs/IPCores/mem/ocrom/index.rst new file mode 100644 index 00000000..f9453dae --- /dev/null +++ b/docs/IPCores/mem/ocrom/index.rst @@ -0,0 +1,33 @@ +.. _NS:ocrom: + +PoC.mem.ocrom +============= + +The namespace ``PoC.mem.ocrom`` offers different on-chip ROM abstractions. + +**Package** + +The package PoC.mem.ocrom holds all component declarations for this namespace. + +.. code-block:: VHDL + + library PoC; + use PoC.ocrom.all; + + +**Entities** + + - :ref:`ocrom_sp ` is a on-chip RAM with a single port interface. + - :ref:`ocrom_dp ` is a on-chip RAM with a dual port interface. + + +.. toctree:: + :hidden: + + Package + +.. toctree:: + :hidden: + + ocrom_sp + ocrom_dp diff --git a/docs/IPCores/mem/ocrom/ocrom.pkg.rst b/docs/IPCores/mem/ocrom/ocrom.pkg.rst new file mode 100644 index 00000000..a1d7c051 --- /dev/null +++ b/docs/IPCores/mem/ocrom/ocrom.pkg.rst @@ -0,0 +1,19 @@ +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ocrom/ocrom.pkg.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` + +.. _PKG:ocrom: + +PoC.mem.ocrom Package +===================== + +.. only:: latex + + Source file: :pocsrc:`ocrom.pkg.vhdl ` diff --git a/docs/IPCores/mem/ocrom/ocrom_dp.rst b/docs/IPCores/mem/ocrom/ocrom_dp.rst new file mode 100644 index 00000000..cc69c160 --- /dev/null +++ b/docs/IPCores/mem/ocrom/ocrom_dp.rst @@ -0,0 +1,56 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:ocrom_dp: + +PoC.mem.ocrom.dp +################ + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ocrom/ocrom_dp.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/ocrom/ocrom_dp_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +Inferring / instantiating dual-port read-only memory, with: + +* dual clock, clock enable, +* 2 read ports. + +The generalized behavior across Altera and Xilinx FPGAs since +Stratix/Cyclone and Spartan-3/Virtex-5, respectively, is as follows: + +WARNING: The simulated behavior on RT-level is not correct. + +TODO: add timing diagram +TODO: implement correct behavior for RT-level simulation + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/mem/ocrom/ocrom_dp.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 60-76 + + + +.. only:: latex + + Source file: :pocsrc:`mem/ocrom/ocrom_dp.vhdl ` diff --git a/docs/IPCores/mem/ocrom/ocrom_sp.rst b/docs/IPCores/mem/ocrom/ocrom_sp.rst new file mode 100644 index 00000000..488bc59b --- /dev/null +++ b/docs/IPCores/mem/ocrom/ocrom_sp.rst @@ -0,0 +1,49 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:ocrom_sp: + +PoC.mem.ocrom.sp +################ + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ocrom/ocrom_sp.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/ocrom/ocrom_sp_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +Inferring / instantiating single-port read-only memory + +- single clock, clock enable +- 1 read port + + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/mem/ocrom/ocrom_sp.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 53-65 + + + +.. only:: latex + + Source file: :pocsrc:`mem/ocrom/ocrom_sp.vhdl ` diff --git a/docs/IPCores/mem/sdram/index.rst b/docs/IPCores/mem/sdram/index.rst new file mode 100644 index 00000000..fafe582b --- /dev/null +++ b/docs/IPCores/mem/sdram/index.rst @@ -0,0 +1,44 @@ +.. _NS:sdram: + +PoC.mem.sdram +============= + +The namespace ``PoC.mem.sdram`` offers components for the access of external SDRAMs. +A common finite state-machine is used to address the memory via banks, rows and +columns. Different physical layers are provide for the single-data-rate (SDR) or +double-data-rate (DDR, DDR2, ...) data bus. One has to instantiate the specific +module required by the FPGA board. + +.. rubric:: SDRAM Controller for the Altera DE0 Board + +The module :ref:`sdram_ctrl_de0 ` combines the finite state machine +:ref:`sdram_ctrl_fsm ` and the DE0 specific physical layer +:ref:`sdram_ctrl_phy_de0 `. It has been tested with the +IS42S16400F SDR memory at a frequency of 133 MHz. A usage example +is given in PoC-Examples_. + + +.. rubric:: SDRAM Controller for the Xilinx Spartan-3E Starter Kit (S3ESK) + +The module :ref:`sdram_ctrl_s3esk ` combines the finite state +machine :ref:`sdram_ctrl_fsm ` and the S3ESK specific physical layer +:ref:`sdram_ctrl_phy_s3esk `. It has been tested with the +MT46V32M16-6T DDR memory at a frequency of 100 MHz (DDR-200). A usage +example is given in PoC-Examples_. + +.. Note:: + See also :ref:`NS:mig` for board specific memory controller implementations + created by Xilinx's Memory Interface Generator (MIG). + + + +.. _PoC-Examples: https://github.com/VLSI-EDA/PoC-Examples + +.. toctree:: + :hidden: + + sdram_ctrl_fsm + sdram_ctrl_de0 + sdram_ctrl_phy_de0 + sdram_ctrl_s3esk + sdram_ctrl_phy_s3esk diff --git a/docs/IPCores/mem/sdram/sdram_ctrl_de0.rst b/docs/IPCores/mem/sdram/sdram_ctrl_de0.rst new file mode 100644 index 00000000..78b9c9c5 --- /dev/null +++ b/docs/IPCores/mem/sdram/sdram_ctrl_de0.rst @@ -0,0 +1,75 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:sdram_ctrl_de0: + +PoC.mem.sdram.ctrl_de0 +###################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/sdram/sdram_ctrl_de0.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/sdram/sdram_ctrl_de0_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +Complete controller for ISSI SDR-SDRAM for Altera DE0 Board. + +SDRAM Device: IS42S16400F + +Configuration +************* + ++------------+----------------------------------------------------+ +| Parameter | Description | ++============+====================================================+ +| CLK_PERIOD | Clock period in nano seconds. All SDRAM timings are| +| | calculated for the device stated above. | ++------------+----------------------------------------------------+ +| CL | CAS latency, choose according to clock frequency. | ++------------+----------------------------------------------------+ +| BL | Burst length. Choose BL=1 for single cycle memory | +| | transactions as required for the PoC.Mem interface.| ++------------+----------------------------------------------------+ + +Tested with: CLK_PERIOD = 7.5 (133 MHz), CL=2, BL=1. + +Operation +********* + +Command, address and write data is sampled with ``clk``. +Read data is also aligned with ``clk``. + +For description on ``clkout`` see +:ref:`sdram_ctrl_phy_de0 `. + +Synchronous resets are used. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/mem/sdram/sdram_ctrl_de0.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 68-100 + + + +.. only:: latex + + Source file: :pocsrc:`mem/sdram/sdram_ctrl_de0.vhdl ` diff --git a/docs/PoC/mem/sdram/sdram_ctrl_fsm.rst b/docs/IPCores/mem/sdram/sdram_ctrl_fsm.rst similarity index 57% rename from docs/PoC/mem/sdram/sdram_ctrl_fsm.rst rename to docs/IPCores/mem/sdram/sdram_ctrl_fsm.rst index 4db5364f..f6cae9cf 100644 --- a/docs/PoC/mem/sdram/sdram_ctrl_fsm.rst +++ b/docs/IPCores/mem/sdram/sdram_ctrl_fsm.rst @@ -1,14 +1,39 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include -sdram_ctrl_fsm -############## +.. include:: +.. include:: + +.. _IP:sdram_ctrl_fsm: + +PoC.mem.sdram.ctrl_fsm +###################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/sdram/sdram_ctrl_fsm.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/sdram/sdram_ctrl_fsm_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` This file contains the FSM as well as parts of the datapath. -The board specific physical layer is defined in another file -sdram_ctrl_phy_*.vhdl +The board specific physical layer is defined in another file. + +Configuration +************* -Generics: ---------- SDRAM_TYPE activates some special cases: + - 0 for SDR-SDRAM - 1 for DDR-SDRAM - 2 for DDR2-SDRAM (no special support yet like ODT) @@ -23,16 +48,19 @@ by the physical interface for DDR interfaces. Furthermore, the memory array is divided into 2**R_BITS rows, 2**C_BITS columns and 2**B_BITS banks. -For example, the MT46V32M16 has 512 Mbit = 8M x 4 banks x 16 bit = -32M cells x 16 bit, with 8K rows and 1K columns. -- A_BITS = log2ceil(32M) = 25 -- D_BITS = 16 -- data-path width of phy on user side: 32-bit because of DDR -- R_BITS = log2ceil(8K) = 13 -- C_BITS = log2ceil(1K) = 10 -- B_BITS = log2ceil(4) = 2 +.. NOTE:: + For example, the MT46V32M16 has 512 Mbit = 8M x 4 banks x 16 bit = + 32M cells x 16 bit, with 8K rows and 1K columns. Thus, the configuration + is: + + - A_BITS = :math:`\log_2(32\,\mbox{M}) = 25` + - D_BITS = 16 + - data-path width of phy on user side: 32-bit because of DDR + - R_BITS = :math:`\log_2(8\,\mbox{K}) = 13` + - C_BITS = :math:`\log_2(1\,\mbox{K}) = 10` + - B_BITS = :math:`\log_2(4) = 2` -Set cas latency (CL, MR_CL) and burst length (BL, MR_BL) according to +Set CAS latency (CL, MR_CL) and burst length (BL, MR_BL) according to your needs. If you have a DDR-SDRAM then set INIT_DLL = true, otherwise false. @@ -52,8 +80,8 @@ specified in number of average refresh periods (specified by T_REFI): INIT_WAIT = ceil(wait_time / clock_period / T_REFI) e.g. INIT_WAIT = ceil(200 us / 10 ns / 700) = 29 -Signals: --------- +Operation +********* After user_cmd_valid is asserted high, the command (user_write) and address (user_addr) must be hold until user_got_cmd is asserted. @@ -74,9 +102,10 @@ The write data must directly connected to the physical layer. :language: vhdl :tab-width: 2 :linenos: - :lines: 120-164 + :lines: 104-148 -Source file: `mem/sdram/sdram_ctrl_fsm.vhdl `_ +.. only:: latex + Source file: :pocsrc:`mem/sdram/sdram_ctrl_fsm.vhdl ` diff --git a/docs/IPCores/mem/sdram/sdram_ctrl_phy_de0.rst b/docs/IPCores/mem/sdram/sdram_ctrl_phy_de0.rst new file mode 100644 index 00000000..667b32b3 --- /dev/null +++ b/docs/IPCores/mem/sdram/sdram_ctrl_phy_de0.rst @@ -0,0 +1,77 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:sdram_ctrl_phy_de0: + +PoC.mem.sdram.ctrl_phy_de0 +########################## + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/sdram/sdram_ctrl_phy_de0.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/sdram/sdram_ctrl_phy_de0_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +Physical layer used by module :ref:`sdram_ctrl_de0 `. + +Instantiates input and output buffer components and adjusts the timing for +the Altera DE0 board. + +Clock and Reset Signals +*********************** + ++-----------+-----------------------------------------------------------+ +| Port | Description | ++===========+===========================================================+ +|clk | Base clock for command and write data path. | ++-----------+-----------------------------------------------------------+ +|rst | Reset for ``clk``. | ++-----------+-----------------------------------------------------------+ + +Command signals and write data are sampled with ``clk``. +Read data is also aligned with ``clk``. + +Write and read enable (wren_nxt, rden_nxt) must be hold for: + +* 1 clock cycle if BL = 1, +* 2 clock cycles if BL = 2, or +* 4 clock cycles if BL = 4, or +* 8 clock cycles if BL = 8. + +They must be first asserted with the read and write command. Proper delay is +included in this unit. + +The first word to write must be asserted with the write command. Proper +delay is included in this unit. + +Synchronous resets are used. Reset must be hold for at least two cycles. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/mem/sdram/sdram_ctrl_phy_de0.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 89-122 + + + +.. only:: latex + + Source file: :pocsrc:`mem/sdram/sdram_ctrl_phy_de0.vhdl ` diff --git a/docs/IPCores/mem/sdram/sdram_ctrl_phy_s3esk.rst b/docs/IPCores/mem/sdram/sdram_ctrl_phy_s3esk.rst new file mode 100644 index 00000000..a15c736d --- /dev/null +++ b/docs/IPCores/mem/sdram/sdram_ctrl_phy_s3esk.rst @@ -0,0 +1,115 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:sdram_ctrl_phy_s3esk: + +PoC.mem.sdram.ctrl_phy_s3esk +############################ + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/sdram/sdram_ctrl_phy_s3esk.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/sdram/sdram_ctrl_phy_s3esk_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +Physical layer used by module :ref:`sdram_ctrl_s3esk `. + +Instantiates input and output buffer components and adjusts the timing for +the Spartan-3E Starter Kit Board. + +Clock and Reset Signals +*********************** + ++-----------+-----------------------------------------------------------+ +| Port | Description | ++===========+===========================================================+ +|clk | Base clock for command and write data path. | ++-----------+-----------------------------------------------------------+ +|clk_n | ``clk`` phase shifted by 180 degrees. | ++-----------+-----------------------------------------------------------+ +|clk90 | ``clk`` phase shifted by 90 degrees. | ++-----------+-----------------------------------------------------------+ +|clk90_n | ``clk`` phase shifted by 270 degrees. | ++-----------+-----------------------------------------------------------+ +|clk_fb | Driven by external feedback (sd_ck_fb) of DDR-SDRAM clock | +|(on PCB) | (sd_ck_p). Actually unused, just referenced below. | ++-----------+-----------------------------------------------------------+ +|clk_fb90 | ``clk_fb`` phase shifted by 90 degrees. | ++-----------+-----------------------------------------------------------+ +|clk_fb90_n | ``clk_fb`` phase shifted by 270 degrees. | ++-----------+-----------------------------------------------------------+ +|rst | Reset for ``clk``. | ++-----------+-----------------------------------------------------------+ +|rst180 | Reset for ``clk_n`` | ++-----------+-----------------------------------------------------------+ +|rst90 | Reset for ``clk90``. | ++-----------+-----------------------------------------------------------+ +|rst270 | Reset for ``clk270``. | ++-----------+-----------------------------------------------------------+ +|rst_fb90 | Reset for ``clk_fb90``. | ++-----------+-----------------------------------------------------------+ +|rst_fb90_n | Reset for ``clk_fb90_n``. | ++-----------+-----------------------------------------------------------+ + + +Operation +********* + +Command signals and write data are sampled with the rising edge of ``clk``. + +Read data is aligned with ``clk_fb90_n``. Either process data in this clock +domain, or connect a FIFO to transfer data into another clock domain of your +choice. This FIFO should capable of storing at least one burst (size BL/2) ++ start of next burst (size 1). + +Write and read enable (``wren_nxt``, ``rden_nxt``) must be hold for: + +* 1 clock cycle if BL = 2, +* 2 clock cycles if BL = 4, or +* 4 clock cycles if BL = 8. + +They must be first asserted with the read and write command. Proper delay is +included in this unit. + +The first word to write must be asserted with the write command. Proper +delay is included in this unit. + +The SDRAM clock is regenerated in this module. The following timing is +chosen for minimum latency (should work up to 100 MHz): + +* ``rising_edge(clk90)`` triggers ``rising_edge(sd_ck_p)``, +* ``rising_edge(clk90_n)`` triggers ``falling_edge(sd_ck_p)``. + +XST options: Disable equivalent register removal. + +Synchronous resets are used. Reset must be hold for at least two cycles. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/mem/sdram/sdram_ctrl_phy_s3esk.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 107-151 + + + +.. only:: latex + + Source file: :pocsrc:`mem/sdram/sdram_ctrl_phy_s3esk.vhdl ` diff --git a/docs/IPCores/mem/sdram/sdram_ctrl_s3esk.rst b/docs/IPCores/mem/sdram/sdram_ctrl_s3esk.rst new file mode 100644 index 00000000..e1403dc7 --- /dev/null +++ b/docs/IPCores/mem/sdram/sdram_ctrl_s3esk.rst @@ -0,0 +1,76 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:sdram_ctrl_s3esk: + +PoC.mem.sdram.ctrl_s3esk +######################## + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/sdram/sdram_ctrl_s3esk.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/mem/sdram/sdram_ctrl_s3esk_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +Controller for Micron DDR-SDRAM on Spartan-3E Starter Kit Board. + +SDRAM Device: MT46V32M16-6T + +Configuration +************* + ++------------+----------------------------------------------------+ +| Parameter | Description | ++============+====================================================+ +| CLK_PERIOD | Clock period in nano seconds. All SDRAM timings are| +| | calculated for the device stated above. | ++------------+----------------------------------------------------+ +| CL | CAS latency, choose according to clock frequency. | ++------------+----------------------------------------------------+ +| BL | Burst length. Choose BL=2 for single cycle memory | +| | transactions as required for the PoC.Mem interface.| ++------------+----------------------------------------------------+ + +Tested with: CLK_PERIOD = 10.0, CL=2, BL=2. + +Operation +********* + +Command, address and write data are sampled with the rising edge of ``clk``. + +Read data is aligned with ``clk_fb90_n``. Either process data in this clock +domain, or connect a FIFO to transfer data into another clock domain of your +choice. This FIFO should capable of storing at least one burst (size BL/2) ++ start of next burst (size 1). + +Synchronous resets are used. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/mem/sdram/sdram_ctrl_s3esk.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 69-112 + + + +.. only:: latex + + Source file: :pocsrc:`mem/sdram/sdram_ctrl_s3esk.vhdl ` diff --git a/docs/IPCores/misc/filter/filter_and.rst b/docs/IPCores/misc/filter/filter_and.rst new file mode 100644 index 00000000..53745bcc --- /dev/null +++ b/docs/IPCores/misc/filter/filter_and.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:filter_and: + +PoC.misc.filter.and +################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/filter/filter_and.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/filter/filter_and_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/misc/filter/filter_and.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 37-48 + + + +.. only:: latex + + Source file: :pocsrc:`misc/filter/filter_and.vhdl ` diff --git a/docs/IPCores/misc/filter/filter_mean.rst b/docs/IPCores/misc/filter/filter_mean.rst new file mode 100644 index 00000000..e3b681b9 --- /dev/null +++ b/docs/IPCores/misc/filter/filter_mean.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:filter_mean: + +PoC.misc.filter.mean +#################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/filter/filter_mean.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/filter/filter_mean_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/misc/filter/filter_mean.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 37-48 + + + +.. only:: latex + + Source file: :pocsrc:`misc/filter/filter_mean.vhdl ` diff --git a/docs/IPCores/misc/filter/filter_or.rst b/docs/IPCores/misc/filter/filter_or.rst new file mode 100644 index 00000000..0fb428eb --- /dev/null +++ b/docs/IPCores/misc/filter/filter_or.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:filter_or: + +PoC.misc.filter.or +################## + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/filter/filter_or.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/filter/filter_or_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/misc/filter/filter_or.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 37-48 + + + +.. only:: latex + + Source file: :pocsrc:`misc/filter/filter_or.vhdl ` diff --git a/docs/IPCores/misc/filter/index.rst b/docs/IPCores/misc/filter/index.rst new file mode 100644 index 00000000..a6bc70d6 --- /dev/null +++ b/docs/IPCores/misc/filter/index.rst @@ -0,0 +1,19 @@ +.. _NS:filter: + +PoC.misc.filter +=============== + +These are filter entities.... + +**Entities** + + * :ref:`IP:filter_and` + * :ref:`IP:filter_mean` + * :ref:`IP:filter_or` + +.. toctree:: + :hidden: + + filter_and + filter_mean + filter_or diff --git a/docs/IPCores/misc/gearbox/gearbox_down_cc.rst b/docs/IPCores/misc/gearbox/gearbox_down_cc.rst new file mode 100644 index 00000000..39a760db --- /dev/null +++ b/docs/IPCores/misc/gearbox/gearbox_down_cc.rst @@ -0,0 +1,49 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:gearbox_down_cc: + +PoC.misc.gearbox.down_cc +######################## + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/gearbox/gearbox_down_cc.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/gearbox/gearbox_down_cc_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +This module provides a downscaling gearbox with a common clock (cc) +interface. It perfoems a 'word' to 'byte' splitting. The default order is +LITTLE_ENDIAN (starting at byte(0)). Input "In_Data" and output "Out_Data" +are of the same clock domain "Clock". Optional input and output registers +can be added by enabling (ADD_***PUT_REGISTERS = TRUE). + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/misc/gearbox/gearbox_down_cc.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 46-70 + + + +.. only:: latex + + Source file: :pocsrc:`misc/gearbox/gearbox_down_cc.vhdl ` diff --git a/docs/IPCores/misc/gearbox/gearbox_down_dc.rst b/docs/IPCores/misc/gearbox/gearbox_down_dc.rst new file mode 100644 index 00000000..4556ca02 --- /dev/null +++ b/docs/IPCores/misc/gearbox/gearbox_down_dc.rst @@ -0,0 +1,54 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:gearbox_down_dc: + +PoC.misc.gearbox.down_dc +######################## + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/gearbox/gearbox_down_dc.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/gearbox/gearbox_down_dc_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +This module provides a downscaling gearbox with a dependent clock (dc) +interface. It perfoems a 'word' to 'byte' splitting. The default order is +LITTLE_ENDIAN (starting at byte(0)). Input "In_Data" is of clock domain +"Clock1"; output "Out_Data" is of clock domain "Clock2". Optional input and +output registers can be added by enabling (ADD_***PUT_REGISTERS = TRUE). + +Assertions: +=========== +- Clock periods of Clock1 and Clock2 MUST be multiples of each other. +- Clock1 and Clock2 MUST be phase aligned (related) to each other. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/misc/gearbox/gearbox_down_dc.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 50-64 + + + +.. only:: latex + + Source file: :pocsrc:`misc/gearbox/gearbox_down_dc.vhdl ` diff --git a/docs/IPCores/misc/gearbox/gearbox_up_cc.rst b/docs/IPCores/misc/gearbox/gearbox_up_cc.rst new file mode 100644 index 00000000..81114563 --- /dev/null +++ b/docs/IPCores/misc/gearbox/gearbox_up_cc.rst @@ -0,0 +1,49 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:gearbox_up_cc: + +PoC.misc.gearbox.up_cc +###################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/gearbox/gearbox_up_cc.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/gearbox/gearbox_up_cc_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +This module provides a downscaling gearbox with a common clock (cc) +interface. It perfoems a 'byte' to 'word' collection. The default order is +LITTLE_ENDIAN (starting at byte(0)). Input "In_Data" and output "Out_Data" +are of the same clock domain "Clock". Optional input and output registers +can be added by enabling (ADD_***PUT_REGISTERS = TRUE). + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/misc/gearbox/gearbox_up_cc.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 46-69 + + + +.. only:: latex + + Source file: :pocsrc:`misc/gearbox/gearbox_up_cc.vhdl ` diff --git a/docs/IPCores/misc/gearbox/gearbox_up_dc.rst b/docs/IPCores/misc/gearbox/gearbox_up_dc.rst new file mode 100644 index 00000000..495bdffb --- /dev/null +++ b/docs/IPCores/misc/gearbox/gearbox_up_dc.rst @@ -0,0 +1,55 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:gearbox_up_dc: + +PoC.misc.gearbox.up_dc +###################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/gearbox/gearbox_up_dc.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/gearbox/gearbox_up_dc_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +This module provides a upscaling gearbox with a dependent clock (dc) +interface. It perfoems a 'byte' to 'word' collection. The default order is +LITTLE_ENDIAN (starting at byte(0)). Input "In_Data" is of clock domain +"Clock1"; output "Out_Data" is of clock domain "Clock2". The "In_Align" +is required to mark the starting byte in the word. An optional input +register can be added by enabling (ADD_INPUT_REGISTERS = TRUE). + +Assertions: +=========== +- Clock periods of Clock1 and Clock2 MUST be multiples of each other. +- Clock1 and Clock2 MUST be phase aligned (related) to each other. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/misc/gearbox/gearbox_up_dc.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 51-66 + + + +.. only:: latex + + Source file: :pocsrc:`misc/gearbox/gearbox_up_dc.vhdl ` diff --git a/docs/IPCores/misc/gearbox/index.rst b/docs/IPCores/misc/gearbox/index.rst new file mode 100644 index 00000000..b66ca2fe --- /dev/null +++ b/docs/IPCores/misc/gearbox/index.rst @@ -0,0 +1,21 @@ +.. _NS:gearbox: + +PoC.misc.gearbox +================ + +These are gearbox entities.... + +**Entities** + + * :ref:`IP:gearbox_down_cc` + * :ref:`IP:gearbox_down_dc` + * :ref:`IP:gearbox_up_cc` + * :ref:`IP:gearbox_up_dc` + +.. toctree:: + :hidden: + + gearbox_down_cc + gearbox_down_dc + gearbox_up_cc + gearbox_up_dc diff --git a/docs/IPCores/misc/index.rst b/docs/IPCores/misc/index.rst new file mode 100644 index 00000000..d8920515 --- /dev/null +++ b/docs/IPCores/misc/index.rst @@ -0,0 +1,50 @@ +.. _NS:misc: + +PoC.misc +======== + +The namespace ``PoC.misc`` offers different yet uncathegorized entities. + +**Sub-Namespaces** + + * :ref:`NS:filter` contains 1-bit filter algorithms. + * :ref:`NS:stat` contains statistic modules. + * :ref:`NS:sync` offers clock-domain-crossing (CDC) modules. + +**Package** + +The package :ref:`PoC.misc ` holds all component declarations for this namespace. + +**Entities** + + * :ref:`IP:misc_Delay` + * :ref:`IP:misc_FrequencyMeasurement` + * :ref:`IP:misc_PulseTrain` + * :ref:`IP:misc_Sequencer` + * :ref:`IP:misc_StrobeGenerator` + * :ref:`IP:misc_StrobeLimiter` + * :ref:`IP:misc_WordAligner` + +.. toctree:: + :hidden: + + filter + gearbox + stat + sync + +.. toctree:: + :hidden: + + Package + +.. toctree:: + :hidden: + + misc_Delay + misc_FrequencyMeasurement + misc_PulseTrain + misc_Sequencer + misc_StrobeGenerator + misc_StrobeLimiter + misc_WordAligner diff --git a/docs/IPCores/misc/misc.pkg.rst b/docs/IPCores/misc/misc.pkg.rst new file mode 100644 index 00000000..77f5f7f5 --- /dev/null +++ b/docs/IPCores/misc/misc.pkg.rst @@ -0,0 +1,21 @@ +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/misc.pkg.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` + +.. _PKG:misc: + +PoC.misc Package +================ + +This package holds all component declarations for this namespace. + +.. only:: latex + + Source file: :pocsrc:`misc.pkg.vhdl ` diff --git a/docs/IPCores/misc/misc_BitwidthConverter.rst b/docs/IPCores/misc/misc_BitwidthConverter.rst new file mode 100644 index 00000000..4c4f05a2 --- /dev/null +++ b/docs/IPCores/misc/misc_BitwidthConverter.rst @@ -0,0 +1,43 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:misc_BitwidthConverter: + +PoC.misc.BitwidthConverter +########################## + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/misc_BitwidthConverter.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/misc_BitwidthConverter_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/misc/misc_BitwidthConverter.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 32-45 + + + +.. only:: latex + + Source file: :pocsrc:`misc/misc_BitwidthConverter.vhdl ` diff --git a/docs/IPCores/misc/misc_ByteAligner.rst b/docs/IPCores/misc/misc_ByteAligner.rst new file mode 100644 index 00000000..d07ef3ce --- /dev/null +++ b/docs/IPCores/misc/misc_ByteAligner.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:misc_ByteAligner: + +PoC.misc.ByteAligner +#################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/misc_ByteAligner.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/misc_ByteAligner_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/misc/misc_ByteAligner.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 40-53 + + + +.. only:: latex + + Source file: :pocsrc:`misc/misc_ByteAligner.vhdl ` diff --git a/docs/IPCores/misc/misc_Delay.rst b/docs/IPCores/misc/misc_Delay.rst new file mode 100644 index 00000000..90a36c73 --- /dev/null +++ b/docs/IPCores/misc/misc_Delay.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:misc_Delay: + +PoC.misc.Delay +############## + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/misc_Delay.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/misc_Delay_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/misc/misc_Delay.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 38-50 + + + +.. only:: latex + + Source file: :pocsrc:`misc/misc_Delay.vhdl ` diff --git a/docs/IPCores/misc/misc_FrequencyMeasurement.rst b/docs/IPCores/misc/misc_FrequencyMeasurement.rst new file mode 100644 index 00000000..26d6c7d0 --- /dev/null +++ b/docs/IPCores/misc/misc_FrequencyMeasurement.rst @@ -0,0 +1,47 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:misc_FrequencyMeasurement: + +PoC.misc.FrequencyMeasurement +############################# + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/misc_FrequencyMeasurement.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/misc_FrequencyMeasurement_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +This module counts 1 second in a reference timer at reference clock. This +reference time is used to start and stop a timer at input clock. The counter +value is the measured frequency in Hz. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/misc/misc_FrequencyMeasurement.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 44-56 + + + +.. only:: latex + + Source file: :pocsrc:`misc/misc_FrequencyMeasurement.vhdl ` diff --git a/docs/IPCores/misc/misc_PulseTrain.rst b/docs/IPCores/misc/misc_PulseTrain.rst new file mode 100644 index 00000000..62ac200d --- /dev/null +++ b/docs/IPCores/misc/misc_PulseTrain.rst @@ -0,0 +1,46 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:misc_PulseTrain: + +PoC.misc.PulseTrain +################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/misc_PulseTrain.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/misc_PulseTrain_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +This module generates pulse trains. This module was written as a answer for +a StackOverflow question: http://stackoverflow.com/questions/25783320 + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/misc/misc_PulseTrain.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 41-51 + + + +.. only:: latex + + Source file: :pocsrc:`misc/misc_PulseTrain.vhdl ` diff --git a/docs/IPCores/misc/misc_Sequencer.rst b/docs/IPCores/misc/misc_Sequencer.rst new file mode 100644 index 00000000..5acfc3f3 --- /dev/null +++ b/docs/IPCores/misc/misc_Sequencer.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:misc_Sequencer: + +PoC.misc.Sequencer +################## + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/misc_Sequencer.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/misc_Sequencer_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/misc/misc_Sequencer.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 40-56 + + + +.. only:: latex + + Source file: :pocsrc:`misc/misc_Sequencer.vhdl ` diff --git a/docs/IPCores/misc/misc_StrobeGenerator.rst b/docs/IPCores/misc/misc_StrobeGenerator.rst new file mode 100644 index 00000000..d4191531 --- /dev/null +++ b/docs/IPCores/misc/misc_StrobeGenerator.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:misc_StrobeGenerator: + +PoC.misc.StrobeGenerator +######################## + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/misc_StrobeGenerator.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/misc_StrobeGenerator_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/misc/misc_StrobeGenerator.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 40-49 + + + +.. only:: latex + + Source file: :pocsrc:`misc/misc_StrobeGenerator.vhdl ` diff --git a/docs/IPCores/misc/misc_StrobeLimiter.rst b/docs/IPCores/misc/misc_StrobeLimiter.rst new file mode 100644 index 00000000..185bdf06 --- /dev/null +++ b/docs/IPCores/misc/misc_StrobeLimiter.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:misc_StrobeLimiter: + +PoC.misc.StrobeLimiter +###################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/misc_StrobeLimiter.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/misc_StrobeLimiter_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/misc/misc_StrobeLimiter.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 39-51 + + + +.. only:: latex + + Source file: :pocsrc:`misc/misc_StrobeLimiter.vhdl ` diff --git a/docs/PoC/misc/misc_WordAligner.rst b/docs/IPCores/misc/misc_WordAligner.rst similarity index 100% rename from docs/PoC/misc/misc_WordAligner.rst rename to docs/IPCores/misc/misc_WordAligner.rst diff --git a/docs/PoC/misc/misc_bit_lz.rst b/docs/IPCores/misc/misc_bit_lz.rst similarity index 64% rename from docs/PoC/misc/misc_bit_lz.rst rename to docs/IPCores/misc/misc_bit_lz.rst index 10b20231..9a269319 100644 --- a/docs/PoC/misc/misc_bit_lz.rst +++ b/docs/IPCores/misc/misc_bit_lz.rst @@ -1,6 +1,30 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include -misc_bit_lz -########### +.. include:: +.. include:: + +.. _IP:misc_bit_lz: + +PoC.misc.bit_lz +############### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/misc_bit_lz.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/misc_bit_lz_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` An LZ77-based bit stream compressor. @@ -50,7 +74,8 @@ misc_bit_lz :linenos: :lines: 69-91 -Source file: `misc/misc_bit_lz.vhdl `_ +.. only:: latex + Source file: :pocsrc:`misc/misc_bit_lz.vhdl ` diff --git a/docs/IPCores/misc/stat/index.rst b/docs/IPCores/misc/stat/index.rst new file mode 100644 index 00000000..72d74210 --- /dev/null +++ b/docs/IPCores/misc/stat/index.rst @@ -0,0 +1,22 @@ +.. _NS:stat: + +PoC.misc.stat +============= + +These are stat entities.... + +**Entities** + + * :ref:`IP:stat_Average` + * :ref:`IP:stat_Histogram` + * :ref:`IP:stat_Maximum` + * :ref:`IP:stat_Minimum` + + +.. toctree:: + :hidden: + + stat_Average + stat_Histogram + stat_Maximum + stat_Minimum diff --git a/docs/IPCores/misc/stat/stat_Average.rst b/docs/IPCores/misc/stat/stat_Average.rst new file mode 100644 index 00000000..012eb182 --- /dev/null +++ b/docs/IPCores/misc/stat/stat_Average.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:stat_Average: + +PoC.misc.stat.Average +##################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/stat/stat_Average.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/stat/stat_Average_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/misc/stat/stat_Average.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 41-58 + + + +.. only:: latex + + Source file: :pocsrc:`misc/stat/stat_Average.vhdl ` diff --git a/docs/IPCores/misc/stat/stat_Histogram.rst b/docs/IPCores/misc/stat/stat_Histogram.rst new file mode 100644 index 00000000..93c8b441 --- /dev/null +++ b/docs/IPCores/misc/stat/stat_Histogram.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:stat_Histogram: + +PoC.misc.stat.Histogram +####################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/stat/stat_Histogram.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/stat/stat_Histogram_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/misc/stat/stat_Histogram.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 40-54 + + + +.. only:: latex + + Source file: :pocsrc:`misc/stat/stat_Histogram.vhdl ` diff --git a/docs/IPCores/misc/stat/stat_Maximum.rst b/docs/IPCores/misc/stat/stat_Maximum.rst new file mode 100644 index 00000000..08b82f37 --- /dev/null +++ b/docs/IPCores/misc/stat/stat_Maximum.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:stat_Maximum: + +PoC.misc.stat.Maximum +##################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/stat/stat_Maximum.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/stat/stat_Maximum_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/misc/stat/stat_Maximum.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 40-57 + + + +.. only:: latex + + Source file: :pocsrc:`misc/stat/stat_Maximum.vhdl ` diff --git a/docs/IPCores/misc/stat/stat_Minimum.rst b/docs/IPCores/misc/stat/stat_Minimum.rst new file mode 100644 index 00000000..faf868b6 --- /dev/null +++ b/docs/IPCores/misc/stat/stat_Minimum.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:stat_Minimum: + +PoC.misc.stat.Minimum +##################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/stat/stat_Minimum.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/stat/stat_Minimum_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/misc/stat/stat_Minimum.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 40-57 + + + +.. only:: latex + + Source file: :pocsrc:`misc/stat/stat_Minimum.vhdl ` diff --git a/docs/IPCores/misc/sync/index.rst b/docs/IPCores/misc/sync/index.rst new file mode 100644 index 00000000..06b7e8ff --- /dev/null +++ b/docs/IPCores/misc/sync/index.rst @@ -0,0 +1,85 @@ +.. _NS:sync: + +PoC.misc.sync +============= + +The namespace ``PoC.misc.sync`` offers different clock-domain-crossing (CDC) +synchronizer circuits. All synchronizers are based on the basic 2 flip-flop +synchonizer called :ref:`sync_Bits `. PoC has two +platform specific implementations for Altera and Xilinx, which are choosen, +if the appropriate ``MY_DEVICE`` constant is configured in ``my_config.vhdl``. + +**Decision Table:** + ++----------+-------------------------------------+---------------------------------------+--------------------+-----------------------------------+-----------------------------------+ +| Behavior | Flag [#f1]_ | Strobe [#f2]_ | Continuous Data | Reset [#f4]_ | Pulse [#f3]_ | ++==========+=====================================+=======================================+====================+===================================+===================================+ +| 1 Bit | :ref:`sync_Bits ` | :ref:`sync_Strobe ` | fifo_ic_got [#f5]_ | :ref:`sync_Reset ` | :ref:`sync_Pulse ` | ++----------+-------------------------------------+---------------------------------------+--------------------+-----------------------------------+-----------------------------------+ +| n Bit | :ref:`sync_Vector ` | :ref:`sync_Command ` | fifo_ic_got [#f5]_ | | | ++----------+-------------------------------------+---------------------------------------+--------------------+-----------------------------------+-----------------------------------+ + +.. rubric:: Basic 2 Flip-Flop Synchronizer + +The basic 2 flip-flop synchronizer is called :ref:`sync_Bits `. It's +possible to configure the bit count of indivital bits. If a vector shall be +synchronized, use one of the special synchronizers like `sync_Vector`. The +vendor specific implementations are named ``sync_Bits_Altera`` and +``sync_Bits_Xilinx`` respectivily. + +A second variant of the 2-FF synchronizer is called :ref:`sync_Reset `. +It's for ``Reset``-signals, implementing asynchronous assertion and synchronous +deassertion. The vendor specific implementations are named ``sync_Reset_Altera`` +and ``sync_Reset_Xilinx`` respectivily. + +A third variant of a 2-FF synchronizer is called :ref:`sync_Pulse `. +It's for very short ``Pulsed``-signals. It uses an addition asynchronous capture FF to latch the +very short pulse. The vendor specific implementations are named ``sync_Pulse_Altera`` and +``sync_Pulse_Xilinx`` respectivily. + +.. rubric:: Special Synchronizers + +Based on the 2-FF synchronizer, several "high-level" synchronizers are build. + +* :ref:`sync_Strobe ` synchronizer ``strobe``-signals + across clock-domain-boundaries. A busy signal indicates the synchronization + status and can be used as a internal gate-signal to disallow new incoming + strobes. A ``strobe``-signal is only for one clock period active. +* :ref:`sync_Command ` like ``sync_Strobe``, it synchronizes + a one clock period active signal across the clock-domain-boundary, but the + input has multiple bits. After the multi bit strobe (Command) was transfered, + the output goes to its idle value. +* :ref:`sync_Vector ` synchronizes a complete vector + across the clock-domain-boundary. A changed detection on the input vector + causes a register to latch the current state. The changed event is transfered + to the new clock-domain and triggers a register to store the latched content, + but in the new clock domain. + +.. seealso:: + + :ref:`IP:fifo_ic_got` + For a cross-clock capable FIFO. + +.. rubric:: Footnotes + +.. [#f1] A *flag* or *status* signal is a continuous, long time stable signal. +.. [#f2] A *strobe* signal is active for only one cycle. +.. [#f3] A *pulse* signal is a very short event. +.. [#f4] To be refumented +.. [#f5] See the ``PoC.fifo`` namespace for cross-clock capable FIFOs. + + +.. toctree:: + :hidden: + + Package + +.. toctree:: + :hidden: + + sync_Bits + sync_Command + sync_Pulse + sync_Reset + sync_Strobe + sync_Vector diff --git a/docs/IPCores/misc/sync/sync.pkg.rst b/docs/IPCores/misc/sync/sync.pkg.rst new file mode 100644 index 00000000..87a92d03 --- /dev/null +++ b/docs/IPCores/misc/sync/sync.pkg.rst @@ -0,0 +1,19 @@ +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/sync/sync.pkg.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` + +.. _PKG:sync: + +PoC.misc.sync Package +===================== + +.. only:: latex + + Source file: :pocsrc:`sync.pkg.vhdl ` diff --git a/docs/IPCores/misc/sync/sync_Bits.rst b/docs/IPCores/misc/sync/sync_Bits.rst new file mode 100644 index 00000000..27c14d0b --- /dev/null +++ b/docs/IPCores/misc/sync/sync_Bits.rst @@ -0,0 +1,74 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:sync_Bits: + +PoC.misc.sync.Bits +################## + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/sync/sync_Bits.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/sync/sync_Bits_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +This module synchronizes multiple flag bits into clock-domain ``Clock``. +The clock-domain boundary crossing is done by two synchronizer D-FFs. All +bits are independent from each other. If a known vendor like Altera or Xilinx +are recognized, a vendor specific implementation is chosen. + +.. ATTENTION:: + Use this synchronizer only for long time stable signals (flags). + +Constraints: + General: + Please add constraints for meta stability to all '_meta' signals and + timing ignore constraints to all '_async' signals. + + Xilinx: + In case of a Xilinx device, this module will instantiate the optimized + module PoC.xil.sync.Bits. Please attend to the notes of sync_Bits.vhdl. + + Altera sdc file: + TODO + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/misc/sync/sync_Bits.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 68-79 + +.. seealso:: + + :doc:`PoC.misc.sync.Reset ` + For a special 2 D-FF synchronizer for *reset*-signals. + :doc:`PoC.misc.sync.Pulse ` + For a special 1+2 D-FF synchronizer for *pulse*-signals. + :doc:`PoC.misc.sync.Strobe ` + For a synchronizer for *strobe*-signals. + :doc:`PoC.misc.sync.Vector ` + For a multiple bits capable synchronizer. + + + +.. only:: latex + + Source file: :pocsrc:`misc/sync/sync_Bits.vhdl ` diff --git a/docs/IPCores/misc/sync/sync_Command.rst b/docs/IPCores/misc/sync/sync_Command.rst new file mode 100644 index 00000000..29e278f7 --- /dev/null +++ b/docs/IPCores/misc/sync/sync_Command.rst @@ -0,0 +1,55 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:sync_Command: + +PoC.misc.sync.Command +##################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/sync/sync_Command.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/sync/sync_Command_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +This module synchronizes a vector of bits from clock-domain ``Clock1`` to +clock-domain ``Clock2``. The clock-domain boundary crossing is done by a +change comparator, a T-FF, two synchronizer D-FFs and a reconstructive +XOR indicating a value change on the input. This changed signal is used +to capture the input for the new output. A busy flag is additionally +calculated for the input clock-domain. The output has strobe character +and is reset to it's ``INIT`` value after one clock cycle. + +Constraints: + This module uses sub modules which need to be constrained. Please + attend to the notes of the instantiated sub modules. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/misc/sync/sync_Command.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 50-63 + + + +.. only:: latex + + Source file: :pocsrc:`misc/sync/sync_Command.vhdl ` diff --git a/docs/IPCores/misc/sync/sync_Pulse.rst b/docs/IPCores/misc/sync/sync_Pulse.rst new file mode 100644 index 00000000..6586a2dc --- /dev/null +++ b/docs/IPCores/misc/sync/sync_Pulse.rst @@ -0,0 +1,74 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:sync_Pulse: + +PoC.misc.sync.Pulse +################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/sync/sync_Pulse.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/sync/sync_Pulse_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +This module synchronizes multiple pulsed bits into the clock-domain ``Clock``. +The clock-domain boundary crossing is done by two synchronizer D-FFs. All bits +are independent from each other. If a known vendor like Altera or Xilinx are +recognized, a vendor specific implementation is chosen. + +.. ATTENTION:: + Use this synchronizer for very short signals (pulse). + +Constraints: + General: + Please add constraints for meta stability to all '_meta' signals and + timing ignore constraints to all '_async' signals. + + Xilinx: + In case of a Xilinx device, this module will instantiate the optimized + module PoC.xil.sync.Pulse. Please attend to the notes of sync_Bits.vhdl. + + Altera sdc file: + TODO + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/misc/sync/sync_Pulse.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 68-78 + +.. seealso:: + + :doc:`PoC.misc.sync.Bits ` + For a common 2 D-FF synchronizer for *flag*-signals. + :doc:`PoC.misc.sync.Reset ` + For a special 2 D-FF synchronizer for *reset*-signals. + :doc:`PoC.misc.sync.Strobe ` + For a synchronizer for *strobe*-signals. + :doc:`PoC.misc.sync.Vector ` + For a multiple bits capable synchronizer. + + + +.. only:: latex + + Source file: :pocsrc:`misc/sync/sync_Pulse.vhdl ` diff --git a/docs/IPCores/misc/sync/sync_Reset.rst b/docs/IPCores/misc/sync/sync_Reset.rst new file mode 100644 index 00000000..94d35475 --- /dev/null +++ b/docs/IPCores/misc/sync/sync_Reset.rst @@ -0,0 +1,65 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:sync_Reset: + +PoC.misc.sync.Reset +################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/sync/sync_Reset.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/sync/sync_Reset_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +This module synchronizes an asynchronous reset signal to the clock +``Clock``. The ``Input`` can be asserted and de-asserted at any time. +The ``Output`` is asserted asynchronously and de-asserted synchronously +to the clock. + +.. ATTENTION:: + Use this synchronizer only to asynchronously reset your design. + The 'Output' should be feed by global buffer to the destination FFs, so + that, it reaches their reset inputs within one clock cycle. + +Constraints: + General: + Please add constraints for meta stability to all '_meta' signals and + timing ignore constraints to all '_async' signals. + + Xilinx: + In case of a Xilinx device, this module will instantiate the optimized + module xil_SyncReset. Please attend to the notes of xil_SyncReset. + + Altera sdc file: + TODO + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/misc/sync/sync_Reset.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 60-69 + + + +.. only:: latex + + Source file: :pocsrc:`misc/sync/sync_Reset.vhdl ` diff --git a/docs/IPCores/misc/sync/sync_Strobe.rst b/docs/IPCores/misc/sync/sync_Strobe.rst new file mode 100644 index 00000000..bf8600c6 --- /dev/null +++ b/docs/IPCores/misc/sync/sync_Strobe.rst @@ -0,0 +1,60 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:sync_Strobe: + +PoC.misc.sync.Strobe +#################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/sync/sync_Strobe.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/sync/sync_Strobe_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +This module synchronizes multiple high-active bits from clock-domain +``Clock1`` to clock-domain ``Clock2``. The clock-domain boundary crossing is +done by a T-FF, two synchronizer D-FFs and a reconstructive XOR. A busy +flag is additionally calculated and can be used to block new inputs. All +bits are independent from each other. Multiple consecutive strobes are +suppressed by a rising edge detection. + +.. ATTENTION:: + Use this synchronizer only for one-cycle high-active signals (strobes). + +.. image:: /_static/misc/sync/sync_Strobe.* + :target: ../../../_static/misc/sync/sync_Strobe.svg + +Constraints: + This module uses sub modules which need to be constrained. Please + attend to the notes of the instantiated sub modules. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/misc/sync/sync_Strobe.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 54-66 + + + +.. only:: latex + + Source file: :pocsrc:`misc/sync/sync_Strobe.vhdl ` diff --git a/docs/IPCores/misc/sync/sync_Vector.rst b/docs/IPCores/misc/sync/sync_Vector.rst new file mode 100644 index 00000000..4516bd13 --- /dev/null +++ b/docs/IPCores/misc/sync/sync_Vector.rst @@ -0,0 +1,54 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:sync_Vector: + +PoC.misc.sync.Vector +#################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/sync/sync_Vector.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/misc/sync/sync_Vector_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +This module synchronizes a vector of bits from clock-domain ``Clock1`` to +clock-domain ``Clock2``. The clock-domain boundary crossing is done by a +change comparator, a T-FF, two synchronizer D-FFs and a reconstructive +XOR indicating a value change on the input. This changed signal is used +to capture the input for the new output. A busy flag is additionally +calculated for the input clock domain. + +Constraints: + This module uses sub modules which need to be constrainted. Please + attend to the notes of the instantiated sub modules. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/misc/sync/sync_Vector.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 49-63 + + + +.. only:: latex + + Source file: :pocsrc:`misc/sync/sync_Vector.vhdl ` diff --git a/docs/IPCores/net/arp/arp_BroadCast_Receiver.rst b/docs/IPCores/net/arp/arp_BroadCast_Receiver.rst new file mode 100644 index 00000000..d5a641a6 --- /dev/null +++ b/docs/IPCores/net/arp/arp_BroadCast_Receiver.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:arp_BroadCast_Receiver: + +PoC.net.arp.BroadCast_Receiver +############################## + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/arp/arp_BroadCast_Receiver.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/arp/arp_BroadCast_Receiver_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/arp/arp_BroadCast_Receiver.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-74 + + + +.. only:: latex + + Source file: :pocsrc:`net/arp/arp_BroadCast_Receiver.vhdl ` diff --git a/docs/IPCores/net/arp/arp_BroadCast_Requester.rst b/docs/IPCores/net/arp/arp_BroadCast_Requester.rst new file mode 100644 index 00000000..9087b91f --- /dev/null +++ b/docs/IPCores/net/arp/arp_BroadCast_Requester.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:arp_BroadCast_Requester: + +PoC.net.arp.BroadCast_Requester +############################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/arp/arp_BroadCast_Requester.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/arp/arp_BroadCast_Requester_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/arp/arp_BroadCast_Requester.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-73 + + + +.. only:: latex + + Source file: :pocsrc:`net/arp/arp_BroadCast_Requester.vhdl ` diff --git a/docs/IPCores/net/arp/arp_Cache.rst b/docs/IPCores/net/arp/arp_Cache.rst new file mode 100644 index 00000000..a80b6829 --- /dev/null +++ b/docs/IPCores/net/arp/arp_Cache.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:arp_Cache: + +PoC.net.arp.Cache +################# + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/arp/arp_Cache.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/arp/arp_Cache_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/arp/arp_Cache.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 44-75 + + + +.. only:: latex + + Source file: :pocsrc:`net/arp/arp_Cache.vhdl ` diff --git a/docs/IPCores/net/arp/arp_IPPool.rst b/docs/IPCores/net/arp/arp_IPPool.rst new file mode 100644 index 00000000..a4d2db02 --- /dev/null +++ b/docs/IPCores/net/arp/arp_IPPool.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:arp_IPPool: + +PoC.net.arp.IPPool +################## + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/arp/arp_IPPool.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/arp/arp_IPPool_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/arp/arp_IPPool.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 43-63 + + + +.. only:: latex + + Source file: :pocsrc:`net/arp/arp_IPPool.vhdl ` diff --git a/docs/IPCores/net/arp/arp_Tester.rst b/docs/IPCores/net/arp/arp_Tester.rst new file mode 100644 index 00000000..d7dd8f23 --- /dev/null +++ b/docs/IPCores/net/arp/arp_Tester.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:arp_Tester: + +PoC.net.arp.Tester +################## + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/arp/arp_Tester.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/arp/arp_Tester_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/arp/arp_Tester.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 43-65 + + + +.. only:: latex + + Source file: :pocsrc:`net/arp/arp_Tester.vhdl ` diff --git a/docs/IPCores/net/arp/arp_UniCast_Receiver.rst b/docs/IPCores/net/arp/arp_UniCast_Receiver.rst new file mode 100644 index 00000000..defafdd9 --- /dev/null +++ b/docs/IPCores/net/arp/arp_UniCast_Receiver.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:arp_UniCast_Receiver: + +PoC.net.arp.UniCast_Receiver +############################ + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/arp/arp_UniCast_Receiver.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/arp/arp_UniCast_Receiver_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/arp/arp_UniCast_Receiver.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-76 + + + +.. only:: latex + + Source file: :pocsrc:`net/arp/arp_UniCast_Receiver.vhdl ` diff --git a/docs/IPCores/net/arp/arp_UniCast_Responder.rst b/docs/IPCores/net/arp/arp_UniCast_Responder.rst new file mode 100644 index 00000000..28561bc3 --- /dev/null +++ b/docs/IPCores/net/arp/arp_UniCast_Responder.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:arp_UniCast_Responder: + +PoC.net.arp.UniCast_Responder +############################# + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/arp/arp_UniCast_Responder.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/arp/arp_UniCast_Responder_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/arp/arp_UniCast_Responder.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-73 + + + +.. only:: latex + + Source file: :pocsrc:`net/arp/arp_UniCast_Responder.vhdl ` diff --git a/docs/IPCores/net/arp/arp_Wrapper.rst b/docs/IPCores/net/arp/arp_Wrapper.rst new file mode 100644 index 00000000..505fbeff --- /dev/null +++ b/docs/IPCores/net/arp/arp_Wrapper.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:arp_Wrapper: + +PoC.net.arp.Wrapper +################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/arp/arp_Wrapper.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/arp/arp_Wrapper_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/arp/arp_Wrapper.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 44-100 + + + +.. only:: latex + + Source file: :pocsrc:`net/arp/arp_Wrapper.vhdl ` diff --git a/docs/IPCores/net/arp/index.rst b/docs/IPCores/net/arp/index.rst new file mode 100644 index 00000000..05bd2b95 --- /dev/null +++ b/docs/IPCores/net/arp/index.rst @@ -0,0 +1,17 @@ +.. _NS:arp: + +PoC.net.arp +=========== + +These are ARP entities.... + +.. toctree:: + + arp_BroadCast_Receiver + arp_BroadCast_Requester + arp_Cache + arp_IPPool + arp_Tester + arp_UniCast_Receiver + arp_UniCast_Responder + arp_Wrapper diff --git a/docs/IPCores/net/eth/eth_GEMAC_GMII.rst b/docs/IPCores/net/eth/eth_GEMAC_GMII.rst new file mode 100644 index 00000000..d91d05a3 --- /dev/null +++ b/docs/IPCores/net/eth/eth_GEMAC_GMII.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:eth_GEMAC_GMII: + +PoC.net.eth.GEMAC_GMII +###################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/eth/eth_GEMAC_GMII.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/eth/eth_GEMAC_GMII_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/eth/eth_GEMAC_GMII.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-101 + + + +.. only:: latex + + Source file: :pocsrc:`net/eth/eth_GEMAC_GMII.vhdl ` diff --git a/docs/IPCores/net/eth/eth_GEMAC_RX.rst b/docs/IPCores/net/eth/eth_GEMAC_RX.rst new file mode 100644 index 00000000..16f20131 --- /dev/null +++ b/docs/IPCores/net/eth/eth_GEMAC_RX.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:Eth_GEMAC_RX: + +PoC.net.eth.GEMAC_RX +#################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/eth/eth_GEMAC_RX.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/eth/eth_GEMAC_RX_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/eth/eth_GEMAC_RX.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-62 + + + +.. only:: latex + + Source file: :pocsrc:`net/eth/eth_GEMAC_RX.vhdl ` diff --git a/docs/IPCores/net/eth/eth_GEMAC_TX.rst b/docs/IPCores/net/eth/eth_GEMAC_TX.rst new file mode 100644 index 00000000..9f0096e6 --- /dev/null +++ b/docs/IPCores/net/eth/eth_GEMAC_TX.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:Eth_GEMAC_TX: + +PoC.net.eth.GEMAC_TX +#################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/eth/eth_GEMAC_TX.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/eth/eth_GEMAC_TX_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/eth/eth_GEMAC_TX.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-65 + + + +.. only:: latex + + Source file: :pocsrc:`net/eth/eth_GEMAC_TX.vhdl ` diff --git a/docs/IPCores/net/eth/eth_PHYController.rst b/docs/IPCores/net/eth/eth_PHYController.rst new file mode 100644 index 00000000..f2bdddeb --- /dev/null +++ b/docs/IPCores/net/eth/eth_PHYController.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:Eth_PHYController: + +PoC.net.eth.PHYController +######################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/eth/eth_PHYController.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/eth/eth_PHYController_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/eth/eth_PHYController.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 45-68 + + + +.. only:: latex + + Source file: :pocsrc:`net/eth/eth_PHYController.vhdl ` diff --git a/docs/IPCores/net/eth/eth_PHYController_Marvell_88E1111.rst b/docs/IPCores/net/eth/eth_PHYController_Marvell_88E1111.rst new file mode 100644 index 00000000..7d367011 --- /dev/null +++ b/docs/IPCores/net/eth/eth_PHYController_Marvell_88E1111.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:Eth_PHYController_Marvell_88E1111: + +PoC.net.eth.PHYController_Marvell_88E1111 +######################################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/eth/eth_PHYController_Marvell_88E1111.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/eth/eth_PHYController_Marvell_88E1111_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/eth/eth_PHYController_Marvell_88E1111.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 44-71 + + + +.. only:: latex + + Source file: :pocsrc:`net/eth/eth_PHYController_Marvell_88E1111.vhdl ` diff --git a/docs/IPCores/net/eth/eth_Wrapper.rst b/docs/IPCores/net/eth/eth_Wrapper.rst new file mode 100644 index 00000000..13295c4c --- /dev/null +++ b/docs/IPCores/net/eth/eth_Wrapper.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:Eth_Wrapper: + +PoC.net.eth.Wrapper +################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/eth/eth_Wrapper.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/eth/eth_Wrapper_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/eth/eth_Wrapper.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 68-112 + + + +.. only:: latex + + Source file: :pocsrc:`net/eth/eth_Wrapper.vhdl ` diff --git a/docs/IPCores/net/eth/index.rst b/docs/IPCores/net/eth/index.rst new file mode 100644 index 00000000..d3d74f8e --- /dev/null +++ b/docs/IPCores/net/eth/index.rst @@ -0,0 +1,15 @@ +.. _NS:eth: + +PoC.net.eth +=========== + +These are eth entities.... + +.. toctree:: + + eth_GEMAC_GMII + eth_GEMAC_RX + eth_GEMAC_TX + eth_PHYController + eth_PHYController_Marvell_88E1111 + eth_Wrapper diff --git a/docs/IPCores/net/icmpv4/icmpv4_RX.rst b/docs/IPCores/net/icmpv4/icmpv4_RX.rst new file mode 100644 index 00000000..84c762ec --- /dev/null +++ b/docs/IPCores/net/icmpv4/icmpv4_RX.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:icmpv4_RX: + +PoC.net.icmpv4.RX +################# + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/icmpv4/icmpv4_RX.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/icmpv4/icmpv4_RX_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/icmpv4/icmpv4_RX.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-88 + + + +.. only:: latex + + Source file: :pocsrc:`net/icmpv4/icmpv4_RX.vhdl ` diff --git a/docs/IPCores/net/icmpv4/icmpv4_TX.rst b/docs/IPCores/net/icmpv4/icmpv4_TX.rst new file mode 100644 index 00000000..57b45871 --- /dev/null +++ b/docs/IPCores/net/icmpv4/icmpv4_TX.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:icmpv4_TX: + +PoC.net.icmpv4.TX +################# + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/icmpv4/icmpv4_TX.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/icmpv4/icmpv4_TX_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/icmpv4/icmpv4_TX.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-78 + + + +.. only:: latex + + Source file: :pocsrc:`net/icmpv4/icmpv4_TX.vhdl ` diff --git a/docs/IPCores/net/icmpv4/icmpv4_Wrapper.rst b/docs/IPCores/net/icmpv4/icmpv4_Wrapper.rst new file mode 100644 index 00000000..229c9902 --- /dev/null +++ b/docs/IPCores/net/icmpv4/icmpv4_Wrapper.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:icmpv4_Wrapper: + +PoC.net.icmpv4.Wrapper +###################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/icmpv4/icmpv4_Wrapper.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/icmpv4/icmpv4_Wrapper_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/icmpv4/icmpv4_Wrapper.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-91 + + + +.. only:: latex + + Source file: :pocsrc:`net/icmpv4/icmpv4_Wrapper.vhdl ` diff --git a/docs/IPCores/net/icmpv4/index.rst b/docs/IPCores/net/icmpv4/index.rst new file mode 100644 index 00000000..ab12b94e --- /dev/null +++ b/docs/IPCores/net/icmpv4/index.rst @@ -0,0 +1,12 @@ +.. _NS:icmpv4: + +PoC.net.icmpv4 +============== + +These are icmpv4 entities.... + +.. toctree:: + + icmpv4_RX + icmpv4_TX + icmpv4_Wrapper diff --git a/docs/IPCores/net/icmpv6/icmpv6_RX.rst b/docs/IPCores/net/icmpv6/icmpv6_RX.rst new file mode 100644 index 00000000..7d28138a --- /dev/null +++ b/docs/IPCores/net/icmpv6/icmpv6_RX.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:icmpv6_RX: + +PoC.net.icmpv6.RX +################# + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/icmpv6/icmpv6_RX.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/icmpv6/icmpv6_RX_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/icmpv6/icmpv6_RX.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-57 + + + +.. only:: latex + + Source file: :pocsrc:`net/icmpv6/icmpv6_RX.vhdl ` diff --git a/docs/IPCores/net/icmpv6/icmpv6_TX.rst b/docs/IPCores/net/icmpv6/icmpv6_TX.rst new file mode 100644 index 00000000..8aab7d21 --- /dev/null +++ b/docs/IPCores/net/icmpv6/icmpv6_TX.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:icmpv6_TX: + +PoC.net.icmpv6.TX +################# + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/icmpv6/icmpv6_TX.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/icmpv6/icmpv6_TX_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/icmpv6/icmpv6_TX.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-56 + + + +.. only:: latex + + Source file: :pocsrc:`net/icmpv6/icmpv6_TX.vhdl ` diff --git a/docs/IPCores/net/icmpv6/icmpv6_Wrapper.rst b/docs/IPCores/net/icmpv6/icmpv6_Wrapper.rst new file mode 100644 index 00000000..cf24a66e --- /dev/null +++ b/docs/IPCores/net/icmpv6/icmpv6_Wrapper.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:icmpv6_Wrapper: + +PoC.net.icmpv6.Wrapper +###################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/icmpv6/icmpv6_Wrapper.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/icmpv6/icmpv6_Wrapper_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/icmpv6/icmpv6_Wrapper.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-67 + + + +.. only:: latex + + Source file: :pocsrc:`net/icmpv6/icmpv6_Wrapper.vhdl ` diff --git a/docs/IPCores/net/icmpv6/index.rst b/docs/IPCores/net/icmpv6/index.rst new file mode 100644 index 00000000..452d9eea --- /dev/null +++ b/docs/IPCores/net/icmpv6/index.rst @@ -0,0 +1,12 @@ +.. _NS:icmpv6: + +PoC.net.icmpv6 +============== + +These are icmpv6 entities.... + +.. toctree:: + + icmpv6_RX + icmpv6_TX + icmpv6_Wrapper diff --git a/docs/IPCores/net/index.rst b/docs/IPCores/net/index.rst new file mode 100644 index 00000000..259af559 --- /dev/null +++ b/docs/IPCores/net/index.rst @@ -0,0 +1,49 @@ +.. _NS:net: + +PoC.net +======== + +These are bus entities.... + +**Sub-Namespaces** + + * :ref:`NS:arp` + * :ref:`NS:eth` + * :ref:`NS:icmpv4` + * :ref:`NS:icmpv6` + * :ref:`NS:ipv4` + * :ref:`NS:ipv6` + * :ref:`NS:mac` + * :ref:`NS:ndp` + * :ref:`NS:stack` + * :ref:`NS:udp` + +**Entities** + + * :ref:`IP:net_FrameChecksum` + * :ref:`IP:net_FrameLoopback` + +.. toctree:: + :hidden: + + arp + eth + icmpv4 + icmpv6 + ipv4 + ipv6 + mac + ndp + stack + udp + +.. toctree:: + :hidden: + + Package + +.. toctree:: + :hidden: + + net_FrameChecksum + net_FrameLoopback diff --git a/docs/IPCores/net/ipv4/index.rst b/docs/IPCores/net/ipv4/index.rst new file mode 100644 index 00000000..0aaec125 --- /dev/null +++ b/docs/IPCores/net/ipv4/index.rst @@ -0,0 +1,13 @@ +.. _NS:ipv4: + +PoC.net.ipv4 +============ + +These are ipv4 entities.... + +.. toctree:: + + ipv4_RX + ipv4_TX + ipv4_FrameLoopback + ipv4_Wrapper diff --git a/docs/IPCores/net/ipv4/ipv4_FrameLoopback.rst b/docs/IPCores/net/ipv4/ipv4_FrameLoopback.rst new file mode 100644 index 00000000..4fc10a52 --- /dev/null +++ b/docs/IPCores/net/ipv4/ipv4_FrameLoopback.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:ipv4_FrameLoopback: + +PoC.net.ipv4.FrameLoopback +########################## + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/ipv4/ipv4_FrameLoopback.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/ipv4/ipv4_FrameLoopback_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/ipv4/ipv4_FrameLoopback.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-74 + + + +.. only:: latex + + Source file: :pocsrc:`net/ipv4/ipv4_FrameLoopback.vhdl ` diff --git a/docs/IPCores/net/ipv4/ipv4_RX.rst b/docs/IPCores/net/ipv4/ipv4_RX.rst new file mode 100644 index 00000000..d1936146 --- /dev/null +++ b/docs/IPCores/net/ipv4/ipv4_RX.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:ipv4_RX: + +PoC.net.ipv4.RX +############### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/ipv4/ipv4_RX.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/ipv4/ipv4_RX_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/ipv4/ipv4_RX.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-82 + + + +.. only:: latex + + Source file: :pocsrc:`net/ipv4/ipv4_RX.vhdl ` diff --git a/docs/IPCores/net/ipv4/ipv4_TX.rst b/docs/IPCores/net/ipv4/ipv4_TX.rst new file mode 100644 index 00000000..c4ea3487 --- /dev/null +++ b/docs/IPCores/net/ipv4/ipv4_TX.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:ipv4_TX: + +PoC.net.ipv4.TX +############### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/ipv4/ipv4_TX.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/ipv4/ipv4_TX_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/ipv4/ipv4_TX.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-81 + + + +.. only:: latex + + Source file: :pocsrc:`net/ipv4/ipv4_TX.vhdl ` diff --git a/docs/IPCores/net/ipv4/ipv4_Wrapper.rst b/docs/IPCores/net/ipv4/ipv4_Wrapper.rst new file mode 100644 index 00000000..2be0304c --- /dev/null +++ b/docs/IPCores/net/ipv4/ipv4_Wrapper.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:ipv4_Wrapper: + +PoC.net.ipv4.Wrapper +#################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/ipv4/ipv4_Wrapper.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/ipv4/ipv4_Wrapper_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/ipv4/ipv4_Wrapper.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-112 + + + +.. only:: latex + + Source file: :pocsrc:`net/ipv4/ipv4_Wrapper.vhdl ` diff --git a/docs/IPCores/net/ipv6/index.rst b/docs/IPCores/net/ipv6/index.rst new file mode 100644 index 00000000..205edfb8 --- /dev/null +++ b/docs/IPCores/net/ipv6/index.rst @@ -0,0 +1,13 @@ +.. _NS:ipv6: + +PoC.net.ipv6 +============ + +These are ipv6 entities.... + +.. toctree:: + + ipv6_RX + ipv6_TX + ipv6_FrameLoopback + ipv6_Wrapper diff --git a/docs/IPCores/net/ipv6/ipv6_FrameLoopback.rst b/docs/IPCores/net/ipv6/ipv6_FrameLoopback.rst new file mode 100644 index 00000000..a499f902 --- /dev/null +++ b/docs/IPCores/net/ipv6/ipv6_FrameLoopback.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:ipv6_FrameLoopback: + +PoC.net.ipv6.FrameLoopback +########################## + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/ipv6/ipv6_FrameLoopback.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/ipv6/ipv6_FrameLoopback_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/ipv6/ipv6_FrameLoopback.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-74 + + + +.. only:: latex + + Source file: :pocsrc:`net/ipv6/ipv6_FrameLoopback.vhdl ` diff --git a/docs/IPCores/net/ipv6/ipv6_RX.rst b/docs/IPCores/net/ipv6/ipv6_RX.rst new file mode 100644 index 00000000..896a0dbd --- /dev/null +++ b/docs/IPCores/net/ipv6/ipv6_RX.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:ipv6_RX: + +PoC.net.ipv6.RX +############### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/ipv6/ipv6_RX.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/ipv6/ipv6_RX_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/ipv6/ipv6_RX.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-84 + + + +.. only:: latex + + Source file: :pocsrc:`net/ipv6/ipv6_RX.vhdl ` diff --git a/docs/IPCores/net/ipv6/ipv6_TX.rst b/docs/IPCores/net/ipv6/ipv6_TX.rst new file mode 100644 index 00000000..85136704 --- /dev/null +++ b/docs/IPCores/net/ipv6/ipv6_TX.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:ipv6_TX: + +PoC.net.ipv6.TX +############### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/ipv6/ipv6_TX.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/ipv6/ipv6_TX_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/ipv6/ipv6_TX.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-84 + + + +.. only:: latex + + Source file: :pocsrc:`net/ipv6/ipv6_TX.vhdl ` diff --git a/docs/IPCores/net/ipv6/ipv6_Wrapper.rst b/docs/IPCores/net/ipv6/ipv6_Wrapper.rst new file mode 100644 index 00000000..40f1823c --- /dev/null +++ b/docs/IPCores/net/ipv6/ipv6_Wrapper.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:ipv6_Wrapper: + +PoC.net.ipv6.Wrapper +#################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/ipv6/ipv6_Wrapper.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/ipv6/ipv6_Wrapper_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/ipv6/ipv6_Wrapper.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-116 + + + +.. only:: latex + + Source file: :pocsrc:`net/ipv6/ipv6_Wrapper.vhdl ` diff --git a/docs/IPCores/net/mac/index.rst b/docs/IPCores/net/mac/index.rst new file mode 100644 index 00000000..e4cf7704 --- /dev/null +++ b/docs/IPCores/net/mac/index.rst @@ -0,0 +1,17 @@ +.. _NS:mac: + +PoC.net.mac +=========== + +These are mac entities.... + +.. toctree:: + + mac_RX_DestMAC_Switch + mac_RX_SrcMAC_Filter + mac_RX_Type_Switch + mac_TX_SrcMAC_Prepender + mac_TX_DestMAC_Prepender + mac_TX_Type_Prepender + mac_FrameLoopback + mac_Wrapper diff --git a/docs/IPCores/net/mac/mac_FrameLoopback.rst b/docs/IPCores/net/mac/mac_FrameLoopback.rst new file mode 100644 index 00000000..fdcf100e --- /dev/null +++ b/docs/IPCores/net/mac/mac_FrameLoopback.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:mac_FrameLoopback: + +PoC.net.mac.FrameLoopback +######################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/mac/mac_FrameLoopback.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/mac/mac_FrameLoopback_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/mac/mac_FrameLoopback.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-72 + + + +.. only:: latex + + Source file: :pocsrc:`net/mac/mac_FrameLoopback.vhdl ` diff --git a/docs/IPCores/net/mac/mac_RX_DestMAC_Switch.rst b/docs/IPCores/net/mac/mac_RX_DestMAC_Switch.rst new file mode 100644 index 00000000..49045289 --- /dev/null +++ b/docs/IPCores/net/mac/mac_RX_DestMAC_Switch.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:mac_RX_DestMAC_Switch: + +PoC.net.mac.RX_DestMAC_Switch +############################# + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/mac/mac_RX_DestMAC_Switch.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/mac/mac_RX_DestMAC_Switch_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/mac/mac_RX_DestMAC_Switch.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-67 + + + +.. only:: latex + + Source file: :pocsrc:`net/mac/mac_RX_DestMAC_Switch.vhdl ` diff --git a/docs/IPCores/net/mac/mac_RX_SrcMAC_Filter.rst b/docs/IPCores/net/mac/mac_RX_SrcMAC_Filter.rst new file mode 100644 index 00000000..049e1496 --- /dev/null +++ b/docs/IPCores/net/mac/mac_RX_SrcMAC_Filter.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:mac_RX_SrcMAC_Filter: + +PoC.net.mac.RX_SrcMAC_Filter +############################ + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/mac/mac_RX_SrcMAC_Filter.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/mac/mac_RX_SrcMAC_Filter_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/mac/mac_RX_SrcMAC_Filter.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-72 + + + +.. only:: latex + + Source file: :pocsrc:`net/mac/mac_RX_SrcMAC_Filter.vhdl ` diff --git a/docs/IPCores/net/mac/mac_RX_Type_Switch.rst b/docs/IPCores/net/mac/mac_RX_Type_Switch.rst new file mode 100644 index 00000000..2ce1c3d6 --- /dev/null +++ b/docs/IPCores/net/mac/mac_RX_Type_Switch.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:mac_RX_Type_Switch: + +PoC.net.mac.RX_Type_Switch +########################## + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/mac/mac_RX_Type_Switch.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/mac/mac_RX_Type_Switch_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/mac/mac_RX_Type_Switch.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-74 + + + +.. only:: latex + + Source file: :pocsrc:`net/mac/mac_RX_Type_Switch.vhdl ` diff --git a/docs/IPCores/net/mac/mac_TX_DestMAC_Prepender.rst b/docs/IPCores/net/mac/mac_TX_DestMAC_Prepender.rst new file mode 100644 index 00000000..d2a4cdaf --- /dev/null +++ b/docs/IPCores/net/mac/mac_TX_DestMAC_Prepender.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:mac_TX_DestMAC_Prepender: + +PoC.net.mac.TX_DestMAC_Prepender +################################ + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/mac/mac_TX_DestMAC_Prepender.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/mac/mac_TX_DestMAC_Prepender_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/mac/mac_TX_DestMAC_Prepender.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-65 + + + +.. only:: latex + + Source file: :pocsrc:`net/mac/mac_TX_DestMAC_Prepender.vhdl ` diff --git a/docs/IPCores/net/mac/mac_TX_SrcMAC_Prepender.rst b/docs/IPCores/net/mac/mac_TX_SrcMAC_Prepender.rst new file mode 100644 index 00000000..c71d2f5d --- /dev/null +++ b/docs/IPCores/net/mac/mac_TX_SrcMAC_Prepender.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:mac_TX_SrcMAC_Prepender: + +PoC.net.mac.TX_SrcMAC_Prepender +############################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/mac/mac_TX_SrcMAC_Prepender.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/mac/mac_TX_SrcMAC_Prepender_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/mac/mac_TX_SrcMAC_Prepender.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-69 + + + +.. only:: latex + + Source file: :pocsrc:`net/mac/mac_TX_SrcMAC_Prepender.vhdl ` diff --git a/docs/IPCores/net/mac/mac_TX_Type_Prepender.rst b/docs/IPCores/net/mac/mac_TX_Type_Prepender.rst new file mode 100644 index 00000000..8a71ace0 --- /dev/null +++ b/docs/IPCores/net/mac/mac_TX_Type_Prepender.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:mac_TX_Type_Prepender: + +PoC.net.mac.TX_Type_Prepender +############################# + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/mac/mac_TX_Type_Prepender.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/mac/mac_TX_Type_Prepender_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/mac/mac_TX_Type_Prepender.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-69 + + + +.. only:: latex + + Source file: :pocsrc:`net/mac/mac_TX_Type_Prepender.vhdl ` diff --git a/docs/IPCores/net/mac/mac_Wrapper.rst b/docs/IPCores/net/mac/mac_Wrapper.rst new file mode 100644 index 00000000..778354a2 --- /dev/null +++ b/docs/IPCores/net/mac/mac_Wrapper.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:mac_Wrapper: + +PoC.net.mac.Wrapper +################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/mac/mac_Wrapper.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/mac/mac_Wrapper_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/mac/mac_Wrapper.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-84 + + + +.. only:: latex + + Source file: :pocsrc:`net/mac/mac_Wrapper.vhdl ` diff --git a/docs/IPCores/net/ndp/index.rst b/docs/IPCores/net/ndp/index.rst new file mode 100644 index 00000000..5d718eae --- /dev/null +++ b/docs/IPCores/net/ndp/index.rst @@ -0,0 +1,13 @@ +.. _NS:ndp: + +PoC.net.ndp +=========== + +These are ndp entities.... + +.. toctree:: + + ndp_DestinationCache + ndp_FSMQuery + ndp_NeighborCache + ndp_Wrapper diff --git a/docs/IPCores/net/ndp/ndp_DestinationCache.rst b/docs/IPCores/net/ndp/ndp_DestinationCache.rst new file mode 100644 index 00000000..c9235632 --- /dev/null +++ b/docs/IPCores/net/ndp/ndp_DestinationCache.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:ndp_DestinationCache: + +PoC.net.ndp.DestinationCache +############################ + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/ndp/ndp_DestinationCache.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/ndp/ndp_DestinationCache_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/ndp/ndp_DestinationCache.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-65 + + + +.. only:: latex + + Source file: :pocsrc:`net/ndp/ndp_DestinationCache.vhdl ` diff --git a/docs/IPCores/net/ndp/ndp_FSMQuery.rst b/docs/IPCores/net/ndp/ndp_FSMQuery.rst new file mode 100644 index 00000000..e48e606b --- /dev/null +++ b/docs/IPCores/net/ndp/ndp_FSMQuery.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:ndp_FSMQuery: + +PoC.net.ndp.FSMQuery +#################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/ndp/ndp_FSMQuery.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/ndp/ndp_FSMQuery_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/ndp/ndp_FSMQuery.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-79 + + + +.. only:: latex + + Source file: :pocsrc:`net/ndp/ndp_FSMQuery.vhdl ` diff --git a/docs/IPCores/net/ndp/ndp_NeighborCache.rst b/docs/IPCores/net/ndp/ndp_NeighborCache.rst new file mode 100644 index 00000000..d813debe --- /dev/null +++ b/docs/IPCores/net/ndp/ndp_NeighborCache.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:ndp_NeighborCache: + +PoC.net.ndp.NeighborCache +######################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/ndp/ndp_NeighborCache.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/ndp/ndp_NeighborCache_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/ndp/ndp_NeighborCache.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-65 + + + +.. only:: latex + + Source file: :pocsrc:`net/ndp/ndp_NeighborCache.vhdl ` diff --git a/docs/IPCores/net/ndp/ndp_Wrapper.rst b/docs/IPCores/net/ndp/ndp_Wrapper.rst new file mode 100644 index 00000000..95102466 --- /dev/null +++ b/docs/IPCores/net/ndp/ndp_Wrapper.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:NDP_Wrapper: + +PoC.net.ndp.Wrapper +################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/ndp/ndp_Wrapper.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/ndp/ndp_Wrapper_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/ndp/ndp_Wrapper.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 43-65 + + + +.. only:: latex + + Source file: :pocsrc:`net/ndp/ndp_Wrapper.vhdl ` diff --git a/docs/IPCores/net/net.pkg.rst b/docs/IPCores/net/net.pkg.rst new file mode 100644 index 00000000..5ee24dfd --- /dev/null +++ b/docs/IPCores/net/net.pkg.rst @@ -0,0 +1,19 @@ +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/net.pkg.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` + +.. _PKG:net: + +PoC.net Package +=============== + +.. only:: latex + + Source file: :pocsrc:`net.pkg.vhdl ` diff --git a/docs/IPCores/net/net_FrameChecksum.rst b/docs/IPCores/net/net_FrameChecksum.rst new file mode 100644 index 00000000..0ca47cbe --- /dev/null +++ b/docs/IPCores/net/net_FrameChecksum.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:net_FrameChecksum: + +PoC.net.FrameChecksum +##################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/net_FrameChecksum.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/net_FrameChecksum_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/net/net_FrameChecksum.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 41-72 + + + +.. only:: latex + + Source file: :pocsrc:`net/net_FrameChecksum.vhdl ` diff --git a/docs/IPCores/net/net_FrameLoopback.rst b/docs/IPCores/net/net_FrameLoopback.rst new file mode 100644 index 00000000..dffbfcd0 --- /dev/null +++ b/docs/IPCores/net/net_FrameLoopback.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:FrameLoopback: + +PoC.net.FrameLoopback +##################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/net_FrameLoopback.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/net_FrameLoopback_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/net/net_FrameLoopback.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 41-65 + + + +.. only:: latex + + Source file: :pocsrc:`net/net_FrameLoopback.vhdl ` diff --git a/docs/IPCores/net/net_FramePerformanceCounter.rst b/docs/IPCores/net/net_FramePerformanceCounter.rst new file mode 100644 index 00000000..b98041fd --- /dev/null +++ b/docs/IPCores/net/net_FramePerformanceCounter.rst @@ -0,0 +1,43 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:LocalLink_PerformanceCounter: + +PoC.net.FramePerformanceCounter +############################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/net_FramePerformanceCounter.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/net_FramePerformanceCounter_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/net/net_FramePerformanceCounter.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 11-35 + + + +.. only:: latex + + Source file: :pocsrc:`net/net_FramePerformanceCounter.vhdl ` diff --git a/docs/IPCores/net/stack/index.rst b/docs/IPCores/net/stack/index.rst new file mode 100644 index 00000000..2513173d --- /dev/null +++ b/docs/IPCores/net/stack/index.rst @@ -0,0 +1,14 @@ +.. _NS:stack: + +PoC.net.stack +============= + +These are udp entities.... + +.. toctree:: + + stack_IPv4 + stack_IPv6 + stack_UDPv4 + stack_UDPv6 + stack_MAC diff --git a/docs/PoC/net/stack/stack_IPv4.rst b/docs/IPCores/net/stack/stack_IPv4.rst similarity index 100% rename from docs/PoC/net/stack/stack_IPv4.rst rename to docs/IPCores/net/stack/stack_IPv4.rst diff --git a/docs/PoC/net/stack/stack_IPv6.rst b/docs/IPCores/net/stack/stack_IPv6.rst similarity index 100% rename from docs/PoC/net/stack/stack_IPv6.rst rename to docs/IPCores/net/stack/stack_IPv6.rst diff --git a/docs/PoC/net/stack/stack_MAC.rst b/docs/IPCores/net/stack/stack_MAC.rst similarity index 100% rename from docs/PoC/net/stack/stack_MAC.rst rename to docs/IPCores/net/stack/stack_MAC.rst diff --git a/docs/IPCores/net/stack/stack_UDPv4.rst b/docs/IPCores/net/stack/stack_UDPv4.rst new file mode 100644 index 00000000..03cf1e52 --- /dev/null +++ b/docs/IPCores/net/stack/stack_UDPv4.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:stack_UDPv4: + +PoC.net.stack.UDPv4 +################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/stack/stack_UDPv4.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/stack/stack_UDPv4_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/stack/stack_UDPv4.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 44-111 + + + +.. only:: latex + + Source file: :pocsrc:`net/stack/stack_UDPv4.vhdl ` diff --git a/docs/PoC/net/stack/stack_UDPv6.rst b/docs/IPCores/net/stack/stack_UDPv6.rst similarity index 100% rename from docs/PoC/net/stack/stack_UDPv6.rst rename to docs/IPCores/net/stack/stack_UDPv6.rst diff --git a/docs/IPCores/net/udp/index.rst b/docs/IPCores/net/udp/index.rst new file mode 100644 index 00000000..bbc99c00 --- /dev/null +++ b/docs/IPCores/net/udp/index.rst @@ -0,0 +1,13 @@ +.. _NS:udp: + +PoC.net.udp +=========== + +These are udp entities.... + +.. toctree:: + + udp_RX + udp_TX + udp_FrameLoopback + udp_Wrapper diff --git a/docs/IPCores/net/udp/udp_FrameLoopback.rst b/docs/IPCores/net/udp/udp_FrameLoopback.rst new file mode 100644 index 00000000..bcad8e4a --- /dev/null +++ b/docs/IPCores/net/udp/udp_FrameLoopback.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:udp_FrameLoopback: + +PoC.net.udp.FrameLoopback +######################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/udp/udp_FrameLoopback.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/udp/udp_FrameLoopback_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/udp/udp_FrameLoopback.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-77 + + + +.. only:: latex + + Source file: :pocsrc:`net/udp/udp_FrameLoopback.vhdl ` diff --git a/docs/IPCores/net/udp/udp_RX.rst b/docs/IPCores/net/udp/udp_RX.rst new file mode 100644 index 00000000..8875d645 --- /dev/null +++ b/docs/IPCores/net/udp/udp_RX.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:udp_RX: + +PoC.net.udp.RX +############## + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/udp/udp_RX.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/udp/udp_RX_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/udp/udp_RX.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-95 + + + +.. only:: latex + + Source file: :pocsrc:`net/udp/udp_RX.vhdl ` diff --git a/docs/IPCores/net/udp/udp_TX.rst b/docs/IPCores/net/udp/udp_TX.rst new file mode 100644 index 00000000..351da0e8 --- /dev/null +++ b/docs/IPCores/net/udp/udp_TX.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:udp_TX: + +PoC.net.udp.TX +############## + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/udp/udp_TX.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/udp/udp_TX_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/udp/udp_TX.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-78 + + + +.. only:: latex + + Source file: :pocsrc:`net/udp/udp_TX.vhdl ` diff --git a/docs/IPCores/net/udp/udp_Wrapper.rst b/docs/IPCores/net/udp/udp_Wrapper.rst new file mode 100644 index 00000000..3c286454 --- /dev/null +++ b/docs/IPCores/net/udp/udp_Wrapper.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:udp_Wrapper: + +PoC.net.udp.Wrapper +################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/udp/udp_Wrapper.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/net/udp/udp_Wrapper_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/net/udp/udp_Wrapper.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-120 + + + +.. only:: latex + + Source file: :pocsrc:`net/udp/udp_Wrapper.vhdl ` diff --git a/docs/PoC/sim/index.rst b/docs/IPCores/sim/index.rst similarity index 94% rename from docs/PoC/sim/index.rst rename to docs/IPCores/sim/index.rst index 4eb0873b..680789e1 100644 --- a/docs/PoC/sim/index.rst +++ b/docs/IPCores/sim/index.rst @@ -1,3 +1,4 @@ +.. _PKG_Sim: Simulation Packages ################### diff --git a/docs/PoC/sim/sim_global.v08.rst b/docs/IPCores/sim/sim_global.v08.rst similarity index 100% rename from docs/PoC/sim/sim_global.v08.rst rename to docs/IPCores/sim/sim_global.v08.rst diff --git a/docs/PoC/sim/sim_global.v93.rst b/docs/IPCores/sim/sim_global.v93.rst similarity index 100% rename from docs/PoC/sim/sim_global.v93.rst rename to docs/IPCores/sim/sim_global.v93.rst diff --git a/docs/PoC/sim/sim_protected.v08.rst b/docs/IPCores/sim/sim_protected.v08.rst similarity index 100% rename from docs/PoC/sim/sim_protected.v08.rst rename to docs/IPCores/sim/sim_protected.v08.rst diff --git a/docs/PoC/sim/sim_simulation.v08.rst b/docs/IPCores/sim/sim_simulation.v08.rst similarity index 100% rename from docs/PoC/sim/sim_simulation.v08.rst rename to docs/IPCores/sim/sim_simulation.v08.rst diff --git a/docs/PoC/sim/sim_simulation.v93.rst b/docs/IPCores/sim/sim_simulation.v93.rst similarity index 100% rename from docs/PoC/sim/sim_simulation.v93.rst rename to docs/IPCores/sim/sim_simulation.v93.rst diff --git a/docs/PoC/sim/sim_types.rst b/docs/IPCores/sim/sim_types.rst similarity index 100% rename from docs/PoC/sim/sim_types.rst rename to docs/IPCores/sim/sim_types.rst diff --git a/docs/PoC/sim/sim_unprotected.v93.rst b/docs/IPCores/sim/sim_unprotected.v93.rst similarity index 100% rename from docs/PoC/sim/sim_unprotected.v93.rst rename to docs/IPCores/sim/sim_unprotected.v93.rst diff --git a/docs/PoC/sim/sim_waveform.rst b/docs/IPCores/sim/sim_waveform.rst similarity index 100% rename from docs/PoC/sim/sim_waveform.rst rename to docs/IPCores/sim/sim_waveform.rst diff --git a/docs/IPCores/sort/index.rst b/docs/IPCores/sort/index.rst new file mode 100644 index 00000000..11139acc --- /dev/null +++ b/docs/IPCores/sort/index.rst @@ -0,0 +1,32 @@ +.. _NS:sort: + +PoC.sort +======== + +These are sorting entities.... + +**Sub-Namespaces** + + * :ref:`NS:sortnet` + +**Entities** + + * :ref:`IP:sort_ExpireList` + * :ref:`IP:sort_InsertSort` + * :ref:`IP:sort_LeastFrequentlyUsed` + * :ref:`IP:sort_lru_cache` + * :ref:`IP:sort_lru_list` + +.. toctree:: + :hidden: + + sortnet + +.. toctree:: + :hidden: + + sort_ExpireList + sort_InsertSort + sort_LeastFrequentlyUsed + sort_lru_cache + sort_lru_list diff --git a/docs/IPCores/sort/sort_ExpireList.rst b/docs/IPCores/sort/sort_ExpireList.rst new file mode 100644 index 00000000..f2fd3446 --- /dev/null +++ b/docs/IPCores/sort/sort_ExpireList.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:list_expire: + +PoC.sort.ExpireList +################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sort/sort_ExpireList.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/sort/sort_ExpireList_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/sort/sort_ExpireList.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-61 + + + +.. only:: latex + + Source file: :pocsrc:`sort/sort_ExpireList.vhdl ` diff --git a/docs/IPCores/sort/sort_InsertSort.rst b/docs/IPCores/sort/sort_InsertSort.rst new file mode 100644 index 00000000..cf48afe9 --- /dev/null +++ b/docs/IPCores/sort/sort_InsertSort.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:list_lru_systolic: + +PoC.sort.InsertSort +################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sort/sort_InsertSort.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/sort/sort_InsertSort_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/sort/sort_InsertSort.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 44-64 + + + +.. only:: latex + + Source file: :pocsrc:`sort/sort_InsertSort.vhdl ` diff --git a/docs/IPCores/sort/sort_LeastFrequentlyUsed.rst b/docs/IPCores/sort/sort_LeastFrequentlyUsed.rst new file mode 100644 index 00000000..a3b9b40c --- /dev/null +++ b/docs/IPCores/sort/sort_LeastFrequentlyUsed.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:sort_LeastFrequentlyUsed: + +PoC.sort.LeastFrequentlyUsed +############################ + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sort/sort_LeastFrequentlyUsed.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/sort/sort_LeastFrequentlyUsed_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/sort/sort_LeastFrequentlyUsed.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 36-53 + + + +.. only:: latex + + Source file: :pocsrc:`sort/sort_LeastFrequentlyUsed.vhdl ` diff --git a/docs/IPCores/sort/sort_lru_cache.rst b/docs/IPCores/sort/sort_lru_cache.rst new file mode 100644 index 00000000..f2e88ece --- /dev/null +++ b/docs/IPCores/sort/sort_lru_cache.rst @@ -0,0 +1,59 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:sort_lru_cache: + +PoC.sort.lru_cache +################## + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sort/sort_lru_cache.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/sort/sort_lru_cache_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +This is an optimized implementation of ``sort_lru_list`` to be used for caches. +Only keys are stored within this list, and these keys are the index of the +cache lines. The list initially contains all indizes from 0 to ELEMENTS-1. +The least-recently used index ``KeyOut`` is always valid. + +The first outputed least-recently used index will be ELEMENTS-1. + +The inputs ``Insert``, ``Free``, ``KeyIn``, and ``Reset`` are synchronous to the +rising-edge of the clock ``clock``. All control signals are high-active. + +Supported operations: + * **Insert:** Mark index ``KeyIn`` as recently used, e.g., when a cache-line + was accessed. + * **Free:** Mark index ``KeyIn`` as least-recently used. Apply this operation, + when a cache-line gets invalidated. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/sort/sort_lru_cache.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 56-70 + + + +.. only:: latex + + Source file: :pocsrc:`sort/sort_lru_cache.vhdl ` diff --git a/docs/IPCores/sort/sort_lru_list.rst b/docs/IPCores/sort/sort_lru_list.rst new file mode 100644 index 00000000..761b35e8 --- /dev/null +++ b/docs/IPCores/sort/sort_lru_list.rst @@ -0,0 +1,57 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:sort_lru_list: + +PoC.sort.lru_list +################# + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sort/sort_lru_list.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/sort/sort_lru_list_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +List storing ``(key, value)`` pairs. The least-recently inserted pair is +outputed on ``DataOut`` if ``Valid = '1'``. If ``Valid = '0'``, then the list +empty. + +The inputs ``Insert``, ``Remove``, ``DataIn``, and ``Reset`` are synchronous +to the rising-edge of the clock ``clock``. All control signals are high-active. + +Supported operations: + * **Insert:** Insert ``DataIn`` as recently used ``(key, value)`` pair. If + key is already within the list, then the corresponding value is updated and + the pair is moved to the recently used position. + * **Remove:** Remove ``(key, value)`` pair with the given key. The list is not + modified if key is not within the list. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/sort/sort_lru_list.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 55-74 + + + +.. only:: latex + + Source file: :pocsrc:`sort/sort_lru_list.vhdl ` diff --git a/docs/IPCores/sort/sortnet/index.rst b/docs/IPCores/sort/sortnet/index.rst new file mode 100644 index 00000000..5b25deb3 --- /dev/null +++ b/docs/IPCores/sort/sortnet/index.rst @@ -0,0 +1,33 @@ +.. _NS:sortnet: + +PoC.sort.sortnet +================ + +This sub-namespace contains sorting network implementations. + +**Entities** + + * :ref:`IP:sortnet_BitonicSort` + * :ref:`IP:sortnet_MergeSort_Streamed` + * :ref:`IP:sortnet_OddEvenMergeSort` + * :ref:`IP:sortnet_OddEvenSort` + * :ref:`IP:sortnet_Stream_Adapter` + * :ref:`IP:sortnet_Stream_Adapter2` + * :ref:`IP:sortnet_Transform` + + +.. toctree:: + :hidden: + + Package + +.. toctree:: + :hidden: + + sortnet_BitonicSort + sortnet_MergeSort_Streamed + sortnet_OddEvenMergeSort + sortnet_OddEvenSort + sortnet_Stream_Adapter + sortnet_Stream_Adapter2 + sortnet_Transform diff --git a/docs/IPCores/sort/sortnet/sortnet.pkg.rst b/docs/IPCores/sort/sortnet/sortnet.pkg.rst new file mode 100644 index 00000000..ed9f79f8 --- /dev/null +++ b/docs/IPCores/sort/sortnet/sortnet.pkg.rst @@ -0,0 +1,39 @@ +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sort/sortnet/sortnet.pkg.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` + +.. _PKG:sortnet: + +PoC.sort.sortnet Package +======================== + +.. code-block:: VHDL + + type T_SORTNET_IMPL is ( + SORT_SORTNET_IMPL_ODDEVEN_SORT, + SORT_SORTNET_IMPL_ODDEVEN_MERGESORT, + SORT_SORTNET_IMPL_BITONIC_SORT + ); + +.. c:type:: T_SORTNET_IMPL + + SORT_SORTNET_IMPL_ODDEVEN_SORT + Instantiate a :ref:`IP:sortnet_OddEvenSort` sorting network. + + SORT_SORTNET_IMPL_ODDEVEN_MERGESORT + Instantiate a :ref:`IP:sortnet_OddEvenMergeSort` sorting network. + + SORT_SORTNET_IMPL_BITONIC_SORT + Instantiate a :ref:`IP:sortnet_BitonicSort` sorting network. + + +.. only:: latex + + Source file: :pocsrc:`sortnet.pkg.vhdl ` diff --git a/docs/IPCores/sort/sortnet/sortnet_BitonicSort.rst b/docs/IPCores/sort/sortnet/sortnet_BitonicSort.rst new file mode 100644 index 00000000..a07323e5 --- /dev/null +++ b/docs/IPCores/sort/sortnet/sortnet_BitonicSort.rst @@ -0,0 +1,48 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:sortnet_BitonicSort: + +PoC.sort.sortnet.BitonicSort +############################ + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sort/sortnet/sortnet_BitonicSort.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/sort/sortnet/sortnet_BitonicSort_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +This sorting network uses the *bitonic sort* algorithm. + +.. image:: /_static/sort/sortnet/sortnet_BitonicSort.* + :target: ../../../_static/sort/sortnet/sortnet_BitonicSort.svg + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/sort/sortnet/sortnet_BitonicSort.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 46-72 + + + +.. only:: latex + + Source file: :pocsrc:`sort/sortnet/sortnet_BitonicSort.vhdl ` diff --git a/docs/IPCores/sort/sortnet/sortnet_MergeSort_Streamed.rst b/docs/IPCores/sort/sortnet/sortnet_MergeSort_Streamed.rst new file mode 100644 index 00000000..fdd2fa72 --- /dev/null +++ b/docs/IPCores/sort/sortnet/sortnet_MergeSort_Streamed.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:sortnet_MergeSort_Streamed: + +PoC.sort.sortnet.MergeSort_Streamed +################################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sort/sortnet/sortnet_MergeSort_Streamed.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/sort/sortnet/sortnet_MergeSort_Streamed_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/sort/sortnet/sortnet_MergeSort_Streamed.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 41-68 + + + +.. only:: latex + + Source file: :pocsrc:`sort/sortnet/sortnet_MergeSort_Streamed.vhdl ` diff --git a/docs/IPCores/sort/sortnet/sortnet_OddEvenMergeSort.rst b/docs/IPCores/sort/sortnet/sortnet_OddEvenMergeSort.rst new file mode 100644 index 00000000..2771a913 --- /dev/null +++ b/docs/IPCores/sort/sortnet/sortnet_OddEvenMergeSort.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:sortnet_OddEvenMergeSort: + +PoC.sort.sortnet.OddEvenMergeSort +################################# + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sort/sortnet/sortnet_OddEvenMergeSort.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/sort/sortnet/sortnet_OddEvenMergeSort_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/sort/sortnet/sortnet_OddEvenMergeSort.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 43-69 + + + +.. only:: latex + + Source file: :pocsrc:`sort/sortnet/sortnet_OddEvenMergeSort.vhdl ` diff --git a/docs/IPCores/sort/sortnet/sortnet_OddEvenSort.rst b/docs/IPCores/sort/sortnet/sortnet_OddEvenSort.rst new file mode 100644 index 00000000..f87dad1e --- /dev/null +++ b/docs/IPCores/sort/sortnet/sortnet_OddEvenSort.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:sortnet_OddEvenSort: + +PoC.sort.sortnet.OddEvenSort +############################ + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sort/sortnet/sortnet_OddEvenSort.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/sort/sortnet/sortnet_OddEvenSort_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/sort/sortnet/sortnet_OddEvenSort.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-68 + + + +.. only:: latex + + Source file: :pocsrc:`sort/sortnet/sortnet_OddEvenSort.vhdl ` diff --git a/docs/IPCores/sort/sortnet/sortnet_Stream_Adapter.rst b/docs/IPCores/sort/sortnet/sortnet_Stream_Adapter.rst new file mode 100644 index 00000000..b9e1d7e1 --- /dev/null +++ b/docs/IPCores/sort/sortnet/sortnet_Stream_Adapter.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:sortnet_Stream_Adapter: + +PoC.sort.sortnet.Stream_Adapter +############################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sort/sortnet/sortnet_Stream_Adapter.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/sort/sortnet/sortnet_Stream_Adapter_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/sort/sortnet/sortnet_Stream_Adapter.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-68 + + + +.. only:: latex + + Source file: :pocsrc:`sort/sortnet/sortnet_Stream_Adapter.vhdl ` diff --git a/docs/IPCores/sort/sortnet/sortnet_Stream_Adapter2.rst b/docs/IPCores/sort/sortnet/sortnet_Stream_Adapter2.rst new file mode 100644 index 00000000..def9d412 --- /dev/null +++ b/docs/IPCores/sort/sortnet/sortnet_Stream_Adapter2.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:sortnet_Stream_Adapter2: + +PoC.sort.sortnet.Stream_Adapter2 +################################ + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sort/sortnet/sortnet_Stream_Adapter2.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/sort/sortnet/sortnet_Stream_Adapter2_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/sort/sortnet/sortnet_Stream_Adapter2.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-76 + + + +.. only:: latex + + Source file: :pocsrc:`sort/sortnet/sortnet_Stream_Adapter2.vhdl ` diff --git a/docs/IPCores/sort/sortnet/sortnet_Transform.rst b/docs/IPCores/sort/sortnet/sortnet_Transform.rst new file mode 100644 index 00000000..a001656d --- /dev/null +++ b/docs/IPCores/sort/sortnet/sortnet_Transform.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:sortnet_Transform: + +PoC.sort.sortnet.Transform +########################## + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/sort/sortnet/sortnet_Transform.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/sort/sortnet/sortnet_Transform_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/sort/sortnet/sortnet_Transform.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 41-61 + + + +.. only:: latex + + Source file: :pocsrc:`sort/sortnet/sortnet_Transform.vhdl ` diff --git a/docs/IPCores/xil/index.rst b/docs/IPCores/xil/index.rst new file mode 100644 index 00000000..b5420586 --- /dev/null +++ b/docs/IPCores/xil/index.rst @@ -0,0 +1,48 @@ +.. _NS:xil: + +PoC.xil +======== + +This namespace is for Xilinx specific modules. + +**Sub-Namespaces** + + * :ref:`NS:mig` + * :ref:`NS:reconfig` + +**Entities** + + * :ref:`IP:xil_BSCAN` + * :ref:`IP:xil_ChipScopeICON` + * :ref:`IP:xil_DRP_BusMux` + * :ref:`IP:xil_DRP_BusSync` + * :ref:`IP:xil_ICAP` + * :ref:`IP:xil_Reconfigurator` + * :ref:`IP:xil_SystemMonitor` + * :ref:`IP:xil_SystemMonitor_Virtex6` + * :ref:`IP:xil_SystemMonitor_Series7` + + +.. toctree:: + :hidden: + + mig + reconfig + +.. toctree:: + :hidden: + + Package + +.. toctree:: + :hidden: + + xil_BSCAN + xil_ChipScopeICON + xil_DRP_BusMux + xil_DRP_BusSync + xil_ICAP + xil_Reconfigurator + xil_SystemMonitor + xil_SystemMonitor_Virtex6 + xil_SystemMonitor_Series7 diff --git a/docs/IPCores/xil/mig/index.rst b/docs/IPCores/xil/mig/index.rst new file mode 100644 index 00000000..bd2d9961 --- /dev/null +++ b/docs/IPCores/xil/mig/index.rst @@ -0,0 +1,24 @@ +.. _NS:mig: + +PoC.xil.mig +=========== + +The namespace ``PoC.xil.mig`` offers pre-configured memory controllers generated +with Xilinx's Memory Interface Generator (MIG). + +* **for Spartan-6 boards:** + + * :ref:`mig_Atlys_1x128 ` - A DDR2 memory controller for the Digilent Atlys board. + +* **for Kintex-7 boards:** + + * :ref:`mig_KC705_MT8JTF12864HZ_1G6 ` - A DDR3 memory controller for the Xilinx KC705 board. + +* **for Virtex-7 boards:** + + +.. toctree:: + :hidden: + + mig_Atlys_1x128 + mig_KC705_MT8JTF12864HZ_1G6 diff --git a/docs/PoC/xil/mig/mig_Atlys_1x128.rst b/docs/IPCores/xil/mig/mig_Atlys_1x128.rst similarity index 96% rename from docs/PoC/xil/mig/mig_Atlys_1x128.rst rename to docs/IPCores/xil/mig/mig_Atlys_1x128.rst index 337b1f3a..5acdcb4e 100644 --- a/docs/PoC/xil/mig/mig_Atlys_1x128.rst +++ b/docs/IPCores/xil/mig/mig_Atlys_1x128.rst @@ -1,3 +1,4 @@ +.. _IP:mig_Atlys_1x128: mig_Atlys_1x128 ############### diff --git a/docs/PoC/xil/mig/mig_KC705_MT8JTF12864HZ_1G6.rst b/docs/IPCores/xil/mig/mig_KC705_MT8JTF12864HZ_1G6.rst similarity index 95% rename from docs/PoC/xil/mig/mig_KC705_MT8JTF12864HZ_1G6.rst rename to docs/IPCores/xil/mig/mig_KC705_MT8JTF12864HZ_1G6.rst index 5e66ef52..75f7caf4 100644 --- a/docs/PoC/xil/mig/mig_KC705_MT8JTF12864HZ_1G6.rst +++ b/docs/IPCores/xil/mig/mig_KC705_MT8JTF12864HZ_1G6.rst @@ -1,3 +1,4 @@ +.. _IP:mig_KC705_MT8JTF12864HZ_1G6: mig_KC705_MT8JTF12864HZ_1G6 ########################### diff --git a/docs/IPCores/xil/reconfig/index.rst b/docs/IPCores/xil/reconfig/index.rst new file mode 100644 index 00000000..079beba3 --- /dev/null +++ b/docs/IPCores/xil/reconfig/index.rst @@ -0,0 +1,17 @@ +.. _NS:reconfig: + +PoC.xil.reconfig +================ + +These are reconfig entities.... + +**Entities** + + * :ref:`IP:reconfig_icap_fsm` + * :ref:`IP:reconfig_icap_wrapper` + +.. toctree:: + :hidden: + + reconfig_icap_fsm + reconfig_icap_wrapper diff --git a/docs/IPCores/xil/reconfig/reconfig_icap_fsm.rst b/docs/IPCores/xil/reconfig/reconfig_icap_fsm.rst new file mode 100644 index 00000000..7d93b55c --- /dev/null +++ b/docs/IPCores/xil/reconfig/reconfig_icap_fsm.rst @@ -0,0 +1,49 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:reconfig_icap_fsm: + +PoC.xil.reconfig.icap_fsm +######################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/xil/reconfig/reconfig_icap_fsm.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/xil/reconfig/reconfig_icap_fsm_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +This module parses the data stream to the Xilinx "Internal Configuration Access Port" (ICAP) +primitives to generate control signals. Tested on: + +* Virtex-6 +* Virtex-7 + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/xil/reconfig/reconfig_icap_fsm.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-63 + + + +.. only:: latex + + Source file: :pocsrc:`xil/reconfig/reconfig_icap_fsm.vhdl ` diff --git a/docs/IPCores/xil/reconfig/reconfig_icap_wrapper.rst b/docs/IPCores/xil/reconfig/reconfig_icap_wrapper.rst new file mode 100644 index 00000000..94d71bf4 --- /dev/null +++ b/docs/IPCores/xil/reconfig/reconfig_icap_wrapper.rst @@ -0,0 +1,48 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:reconfig_icap_wrapper: + +PoC.xil.reconfig.icap_wrapper +############################# + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/xil/reconfig/reconfig_icap_wrapper.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/xil/reconfig/reconfig_icap_wrapper_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +This module was designed to connect the Xilinx "Internal Configuration Access Port" (ICAP) +to a PCIe endpoint on a Dini board. Tested on: + +tbd + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../../src/xil/reconfig/reconfig_icap_wrapper.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 43-68 + + + +.. only:: latex + + Source file: :pocsrc:`xil/reconfig/reconfig_icap_wrapper.vhdl ` diff --git a/docs/IPCores/xil/xil.pkg.rst b/docs/IPCores/xil/xil.pkg.rst new file mode 100644 index 00000000..09fd08f4 --- /dev/null +++ b/docs/IPCores/xil/xil.pkg.rst @@ -0,0 +1,21 @@ +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/xil/xil.pkg.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + |gh-src| :pocsrc:`Sourcecode ` + +.. _PKG:xil: + +PoC.xil Package +================ + +This package holds all component declarations for this namespace. + +.. only:: latex + + Source file: :pocsrc:`xil.pkg.vhdl ` diff --git a/docs/IPCores/xil/xil_BSCAN.rst b/docs/IPCores/xil/xil_BSCAN.rst new file mode 100644 index 00000000..21eef34f --- /dev/null +++ b/docs/IPCores/xil/xil_BSCAN.rst @@ -0,0 +1,50 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:xil_BSCAN: + +PoC.xil.BSCAN +############# + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/xil/xil_BSCAN.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/xil/xil_BSCAN_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +This module wraps Xilinx "Boundary Scan" (JTAG) primitives in a generic +module. |br| +Supported devices are: + * Spartan-3, Spartan-6 + * Virtex-5, Virtex-6 + * Series-7 (Artix-7, Kintex-7, Virtex-7, Zynq-7000) + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/xil/xil_BSCAN.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 47-65 + + + +.. only:: latex + + Source file: :pocsrc:`xil/xil_BSCAN.vhdl ` diff --git a/docs/IPCores/xil/xil_ChipScopeICON.rst b/docs/IPCores/xil/xil_ChipScopeICON.rst new file mode 100644 index 00000000..ae957c26 --- /dev/null +++ b/docs/IPCores/xil/xil_ChipScopeICON.rst @@ -0,0 +1,63 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:xil_ChipScopeICON: + +PoC.xil.ChipScopeICON +##################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/xil/xil_ChipScopeICON.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/xil/xil_ChipScopeICON_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +This module wraps 15 ChipScope ICON IP core netlists generated from ChipScope +ICON xco files. The generic parameter ``PORTS`` selects the apropriate ICON +instance with 1 to 15 ICON ``ControlBus`` ports. Each ``ControlBus`` port is +of type ``T_XIL_CHIPSCOPE_CONTROL`` and of mode ``inout``. + +.. rubric:: Compile required CoreGenerator IP Cores to Netlists with PoC + +Please use the provided Xilinx ISE compile command ``ise`` in PoC to recreate +the needed source and netlist files on your local machine. + +.. code-block:: PowerShell + + cd PoCRoot + .\poc.ps1 ise PoC.xil.ChipScopeICON --board=KC705 + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/xil/xil_ChipScopeICON.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 56-63 + +.. seealso:: + + :doc:`Using PoC -> Synthesis ` + For how to run synthesis with PoC and CoreGenerator. + + + +.. only:: latex + + Source file: :pocsrc:`xil/xil_ChipScopeICON.vhdl ` diff --git a/docs/IPCores/xil/xil_DRP_BusMux.rst b/docs/IPCores/xil/xil_DRP_BusMux.rst new file mode 100644 index 00000000..6d668125 --- /dev/null +++ b/docs/IPCores/xil/xil_DRP_BusMux.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:xil_DRP_BusMux: + +PoC.xil.DRP_BusMux +################## + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/xil/xil_DRP_BusMux.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/xil/xil_DRP_BusMux_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/xil/xil_DRP_BusMux.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 42-65 + + + +.. only:: latex + + Source file: :pocsrc:`xil/xil_DRP_BusMux.vhdl ` diff --git a/docs/IPCores/xil/xil_DRP_BusSync.rst b/docs/IPCores/xil/xil_DRP_BusSync.rst new file mode 100644 index 00000000..6d51d68b --- /dev/null +++ b/docs/IPCores/xil/xil_DRP_BusSync.rst @@ -0,0 +1,45 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:xil_DRP_BusSync: + +PoC.xil.DRP_BusSync +################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/xil/xil_DRP_BusSync.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/xil/xil_DRP_BusSync_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +.. TODO:: No documentation available. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/xil/xil_DRP_BusSync.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 40-58 + + + +.. only:: latex + + Source file: :pocsrc:`xil/xil_DRP_BusSync.vhdl ` diff --git a/docs/IPCores/xil/xil_ICAP.rst b/docs/IPCores/xil/xil_ICAP.rst new file mode 100644 index 00000000..8d22cbc3 --- /dev/null +++ b/docs/IPCores/xil/xil_ICAP.rst @@ -0,0 +1,50 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:xil_ICAP: + +PoC.xil.ICAP +############ + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/xil/xil_ICAP.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/xil/xil_ICAP_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +This module wraps Xilinx "Internal Configuration Access Port" (ICAP) primitives in a generic +module. |br| +Supported devices are: + * Spartan-6 + * Virtex-4, Virtex-5, Virtex-6 + * Series-7 (Artix-7, Kintex-7, Virtex-7, Zynq-7000) + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/xil/xil_ICAP.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 47-66 + + + +.. only:: latex + + Source file: :pocsrc:`xil/xil_ICAP.vhdl ` diff --git a/docs/IPCores/xil/xil_Reconfigurator.rst b/docs/IPCores/xil/xil_Reconfigurator.rst new file mode 100644 index 00000000..2e041977 --- /dev/null +++ b/docs/IPCores/xil/xil_Reconfigurator.rst @@ -0,0 +1,53 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:xil_Reconfigurator: + +PoC.xil.Reconfigurator +###################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/xil/xil_Reconfigurator.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/xil/xil_Reconfigurator_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +Many complex primitives in a Xilinx device offer a Dynamic Reconfiguration +Port (DRP) to reconfigure a primitive at runtime without reconfiguring the +whole FPGA. + +This module is a DRP master that can be pre-configured at compile time with +different configuration sets. The configuration sets are mapped into a ROM. +The user can select a stored configuration with ``ConfigSelect``. Sending a +strobe to ``Reconfig`` will start the reconfiguration process. The operation +completes with another strobe on ``ReconfigDone``. + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/xil/xil_Reconfigurator.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 51-72 + + + +.. only:: latex + + Source file: :pocsrc:`xil/xil_Reconfigurator.vhdl ` diff --git a/docs/PoC/xil/xil_SystemMonitor.rst b/docs/IPCores/xil/xil_SystemMonitor.rst similarity index 53% rename from docs/PoC/xil/xil_SystemMonitor.rst rename to docs/IPCores/xil/xil_SystemMonitor.rst index 43a64195..50f16b89 100644 --- a/docs/PoC/xil/xil_SystemMonitor.rst +++ b/docs/IPCores/xil/xil_SystemMonitor.rst @@ -1,6 +1,30 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include -xil_SystemMonitor -################# +.. include:: +.. include:: + +.. _IP:xil_SystemMonitor: + +PoC.xil.SystemMonitor +##################### + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/xil/xil_SystemMonitor.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/xil/xil_SystemMonitor_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` This module generates a PWM signal for a 3-pin (transistor controlled) or 4-pin fan header. The FPGAs temperature is read from device specific system @@ -32,7 +56,8 @@ monitors (normal, user temperature, over temperature). :linenos: :lines: 62-73 -Source file: `xil/xil_SystemMonitor.vhdl `_ +.. only:: latex + Source file: :pocsrc:`xil/xil_SystemMonitor.vhdl ` diff --git a/docs/IPCores/xil/xil_SystemMonitor_Series7.rst b/docs/IPCores/xil/xil_SystemMonitor_Series7.rst new file mode 100644 index 00000000..4ab4a031 --- /dev/null +++ b/docs/IPCores/xil/xil_SystemMonitor_Series7.rst @@ -0,0 +1,62 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:xil_SystemMonitor_Series7: + +PoC.xil.SystemMonitor_Series7 +############################# + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/xil/xil_SystemMonitor_Series7.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/xil/xil_SystemMonitor_Series7_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +This module wraps a Series-7 XADC to report if preconfigured temperature values +are overrun. The XADC was formerly known as "System Monitor". + +.. rubric:: Temperature Curve + +.. code-block:: none + + | /-----\ + Temp_ov on=80 | - - - - - - /-------/ \ + | / | \ + Temp_ov off=60 | - - - - - / - - - - | - - - - \----\ + | / | |\ + | / | | \ + Temp_us on=35 | - /---/ | | \ + Temp_us off=30 | - / - -|- - - - - - |- - - - - - - |- -\------\ + | / | | | \ + ----------------|--------|------------|--------------|-----------|-------- + pwm = | min | medium | max | medium | min + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/xil/xil_SystemMonitor_Series7.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 56-66 + + + +.. only:: latex + + Source file: :pocsrc:`xil/xil_SystemMonitor_Series7.vhdl ` diff --git a/docs/IPCores/xil/xil_SystemMonitor_Virtex6.rst b/docs/IPCores/xil/xil_SystemMonitor_Virtex6.rst new file mode 100644 index 00000000..b1c47af1 --- /dev/null +++ b/docs/IPCores/xil/xil_SystemMonitor_Virtex6.rst @@ -0,0 +1,62 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + +.. _IP:xil_SystemMonitor_Virtex6: + +PoC.xil.SystemMonitor_Virtex6 +############################# + +.. only:: html + + .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/src/xil/xil_SystemMonitor_Virtex6.vhdl + :alt: Source Code on GitHub + .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/xil/xil_SystemMonitor_Virtex6_tb.vhdl + :alt: Source Code on GitHub + + .. sidebar:: GitHub Links + + * |gh-src| :pocsrc:`Sourcecode ` + * |gh-tb| :poctb:`Testbench ` + +This module wraps a Virtex-6 System Monitor primitive to report if preconfigured +temperature values are overrun. + +.. rubric:: Temperature Curve + +.. code-block:: none + + | /-----\ + Temp_ov on=80 | - - - - - - /-------/ \ + | / | \ + Temp_ov off=60 | - - - - - / - - - - | - - - - \----\ + | / | |\ + | / | | \ + Temp_us on=35 | - /---/ | | \ + Temp_us off=30 | - / - -|- - - - - - |- - - - - - - |- -\------\ + | / | | | \ + ----------------|--------|------------|--------------|-----------|-------- + pwm = | min | medium | max | medium | min + + + +.. rubric:: Entity Declaration: + +.. literalinclude:: ../../../src/xil/xil_SystemMonitor_Virtex6.vhdl + :language: vhdl + :tab-width: 2 + :linenos: + :lines: 56-66 + + + +.. only:: latex + + Source file: :pocsrc:`xil/xil_SystemMonitor_Virtex6.vhdl ` diff --git a/docs/Interfaces/CommandStatusError.rst b/docs/Interfaces/CommandStatusError.rst new file mode 100644 index 00000000..c34b596d --- /dev/null +++ b/docs/Interfaces/CommandStatusError.rst @@ -0,0 +1,7 @@ +.. _INT:PoC.CSE: + +Command-Status-Error (PoC.CSE) Interface +######################################## + +.. TODO:: + Define the PoC.CSE (Command-Status-Error) interface used in ... diff --git a/docs/Interfaces/FIFO.rst b/docs/Interfaces/FIFO.rst new file mode 100644 index 00000000..7475a127 --- /dev/null +++ b/docs/Interfaces/FIFO.rst @@ -0,0 +1,7 @@ +.. _INT:PoC.FIFO: + +PoC.FIFO Interface +################## + +.. TODO:: + Define the PoC.FIFO interface (writer and reader) used in ``PoC.fifo.*`` ... diff --git a/docs/Interfaces/Memory.rst b/docs/Interfaces/Memory.rst new file mode 100644 index 00000000..2d2d9ede --- /dev/null +++ b/docs/Interfaces/Memory.rst @@ -0,0 +1,130 @@ +.. _INT:PoC.Mem: + +PoC.Mem Interface +################# + +PoC.Mem is a single-cycle, pipelined memory interface used by various +memory controllers and related components like caches. Memory accesses +are always word aligned, and during writes a mask defines which bytes +are actually written to the memory (if supported by the memory +controller). + + +Configuration +************* + +Each entity may have an individual configuration, especially if it has +two PoC.Mem interfaces or if it adapts between PoC.Mem and another +interface. + +The typical configuration parameters are: + ++--------------------+------------------------------------------------+ +| Parameter | Description | ++====================+================================================+ +| ADDR_BITS or | Number of address bits. Each address identifies| +| A_BITS | exactly one memory word. | ++--------------------+------------------------------------------------+ +| DATA_BITS or | Size of a memory word in bits. DATA_BITS must | +| D_BITS | be divisible by 8. | ++--------------------+------------------------------------------------+ + +A memory word consists of DATA_BITS/8 bytes. + +Individual bytes are only addressed during writes by the write +mask. The write mask has one mask-bit for each byte in a memory word. + +For example, a 1 KiByte memory with a 32-bit datapath has the +following configuration: + +* 4 bytes per memory word, +* ADDR_BITS=8 because :math:`\log_2(1\,\mbox{KiByte} / 4\,\mbox{bytes}) = 8`, and +* DATA_BITS=32 which is the datapath size in bits. + + +Interface signals +***************** + +The following signal names are typically prefixed in the port list of +a concrete entity to separate the PoC.Mem interface from other +interfaces of the entity. Moreover, clock and reset may be shared +with other interfaces of the entity. + +The PoC.Mem interface consists of the following signals: + ++--------------------+------------------------------------------------+ +| Signal | Description | ++====================+================================================+ +| clk | The clock. All other signals are synchronous | +| | to the rising edge of this clock. | ++--------------------+------------------------------------------------+ +| rst | High-active synchronous reset. | ++--------------------+------------------------------------------------+ +| rdy | High-active ready for request. | ++--------------------+------------------------------------------------+ +| req | High-active request. | ++--------------------+------------------------------------------------+ +| write | '1' if write request, '0' if read request | ++--------------------+------------------------------------------------+ +| addr | The (word) address. | ++--------------------+------------------------------------------------+ +| wdata | The data to be written to the memory. | ++--------------------+------------------------------------------------+ +| wmask | Write-mask, for each byte: '0' = write byte, | +| (optional) | '1' = mask byte from write. Signal/port is | +| | omitted if write mask is not supported. | ++--------------------+------------------------------------------------+ +| rstb | High-active read-strobe. | ++--------------------+------------------------------------------------+ +| rdata | The read-data returned from the memory. | ++--------------------+------------------------------------------------+ + +The interface is actually splitted into two parts: + +* the request part: signals ``rdy``, ``req``, ``write``, ``addr``, + ``wdata`` and ``wmask``, and + +* the read-reply part: signals ``rstb`` and ``rdata``. + + +Operation +********* + +The request and the read-reply part operate indepent of each other to +support pipelined reading from memory. The pipeline depth is defined +by the actual memory controller. If a user application does support +only a specific number of outstanding reads, then the application must +limit the number of issued reads on its own. + + +Requests +++++++++ + +If ``req`` is low, then no request is issued to the memory in the current +clock cycle. The state of the signals ``write``, ``addr``, ``wdata`` +and ``wmask`` doesn't care. + +If ``req`` is high, then a request is issued to the memory in the current +clock cycle as given by ``write``, ``addr``, ``wdata`` and +``wmask``. The request will be accepted by the memory, if ``rdy`` is +high in the same clock cycle, otherwise the request will be ignored. +``wdata`` and ``wmask`` doesn't care if a read request is issued. + +``rdy`` does not depend on ``req`` in the current clock cycle. ``rdy`` +may go low in the following clock cycle after a request has been +issued or a synchronous reset has been applied. + + +Read Replies +++++++++++++ + +If ``rstb`` is high in the current clock cycle, then ``rdata`` +delivers the requested read data (read reply). Otherwise, if ``rstb`` +is low, then ``rdata`` is unknown. The user application has to +immediatly handle the incoming read data, because it cannot +signal ready or acknowledge. + +After issuing a read request, the memory responds with a read reply in +the following clock cycle (i.e. synchronous read) or any later clock +cycle depending on the pipeline depth. For each read request, a read +reply is generated. Read requests are not reordered. diff --git a/docs/References/Interfaces/Stream.rst b/docs/Interfaces/Stream.rst similarity index 60% rename from docs/References/Interfaces/Stream.rst rename to docs/Interfaces/Stream.rst index 38ef2d0f..d6df1e10 100644 --- a/docs/References/Interfaces/Stream.rst +++ b/docs/Interfaces/Stream.rst @@ -1,6 +1,7 @@ +.. _INT:PoC.Stream: -PoC.Stream -########## +PoC.Stream Interface +#################### .. TODO:: Define the PoC.Stream interface used in PoC.net.* and ``PoC.bus.stream.*`` ... diff --git a/docs/Interfaces/index.rst b/docs/Interfaces/index.rst new file mode 100644 index 00000000..240ebca0 --- /dev/null +++ b/docs/Interfaces/index.rst @@ -0,0 +1,14 @@ +.. _INT: + +IP Core Interfaces +################## + +PoC defines a set of on-chip interfaces described in the next sections. + +.. toctree:: + :maxdepth: 1 + + PoC.CSE + PoC.FIFO + PoC.Mem + PoC.Stream diff --git a/docs/Miscelaneous/ChangeLog.rst b/docs/Miscelaneous/ChangeLog.rst deleted file mode 100644 index f07b88bd..00000000 --- a/docs/Miscelaneous/ChangeLog.rst +++ /dev/null @@ -1,514 +0,0 @@ -Change Log -########## - -.. contents:: Content of this page - :local: - -**************************************************************************************************************************************************************** -2016 -**************************************************************************************************************************************************************** - -.. This is a comment block. Copy this block for a new release version. - - New in 1.x (upcomming) - ======================= - - Already documented changes are available on the ``release`` branch at GitHub. - - * Python Infrastructure - * Common changes - * All Simulators - * Aldec Active-HDL - * GHDL - * Mentor QuestaSim - * Xilinx ISE Simulator - * Xilinx Vivado Simulator - * All Compilers - * Altera Quartus Synthesis - * Lattice Diamond (LSE) - * Xilinx ISE (XST) - * Xilinx ISE Core Generator - * Xilinx Vivado Synthesis - * Documentation - * VHDL common packages - * VHDL Simulation helpers - * New Entities - * New Testbenches - * New Constraints - * Shipped Tool and Helper Scripts - - -New in 1.x (upcomming) -======================= - -Already documented changes are available on the ``release`` branch at GitHub. - -* Python Infrastructure - - * Common changes - - * The classes ``Simulator`` and ``Compiler`` now share common methods in base class called ``Shared``. - - * ``*.files`` Parser - - * Implemented path expressions: sub-directory expression, concatenate expression - * Implemented InterpolateLiteral: access database keys in ``*.files`` files - * New Path statement, which defines a path constant calculated from a path expression - * Replaced string arguments in statements with path expressions if the desired string was a path - * Replaced simple StringToken matches with Identifier expressions - - * All Simulators - - * - - * All Compilers - - * - - * GHDL - - * Reduced ``-P`` parameters: Removed doublings - -* Documentation - - * - -* VHDL common packages - - * - -* VHDL Simulation helpers - - * Mark a testbench as failed if (registered) processes are active while finilize is called - -* New Entities - - * - -* New Testbenches - - * - -* New Constraints - - * - -* Shipped Tool and Helper Scripts - - * Updated and new Notepad++ syntax files - - -New in 1.0 (13.05.2016) -================================================================================================================================================================ - -* Python Infrastructure (Completely Reworked) - - * New Requirements - - * Python 3.5 - * py-flags - - * New command line interface - - * Synopsis: ``poc.sh|ps1 [common options] [options]`` - * Removed task specific wrapper scripts: ``testbench.sh|ps1``, ``netlist.sh|ps1``, ... - * Updated ``wrapper.ps1`` and ``wrapper.sh`` files - - * New ini-file database - - * - * Added a new config.boards.ini file to list known boards (real and virtual ones) - - * New parser for ``*.files`` files - - * conditional compiling (if-then-elseif-else) - * include statement - include other ``*.files`` files - * library statement - reference external VHDL libraries - * prepared for Cocotb testbenches - - * New parser for ``*.rules`` files - - * - - * All Tool Flows - - * Unbuffered outputs from vendor tools (realtime output to stdout from subprocess) - * Output filtering from vendor tools - - * verbose message suppression - * error and warning message highlighting - * abort flow on vendor tool errors - - * All Simulators - - * Run testbenches for different board or device configurations (see ``--board`` and ``--device`` command line options) - - * New Simulators - - * Aldec Active-HDL support (no GUI support) - - * Tested with Active-HDL from Lattice Diamond - * Tested with Active-HDL Student Edition - - * Cocotb (with QuestaSim backend on Linux) - - * New Synthesizers - - * Altera Quartus II and Quartus Prime - - * Command: ``quartus`` - - * Lattice Synthesis Engine (LSE) from Diamond - - * Command: ``lse`` - - * Xilinx Vivado - - * Command: ``vivado`` - - * GHDL - - * GHDLSimulator can distinguish different backends (mcode, gcc, llvm) - * Pre-compiled library support for GHDL - - * QuestaSim / ModelSim Altera Edition - - * Pre-compiled library support for GHDL - - * Vivado Simulator - - * Tested Vivado Simulator 2016.1 (xSim) with PoC -> still produces errors or false results - -* New Entities - - * - -* New Testbenches - - * - -* New Constraints - - * - -* New dependencies - - * Embedded Cocotb in ``/lib/cocotb`` - -* Shipped Tool and Helper Scripts - - * Updated and new Notepad++ syntax files - * Pre-compiled vendor library support - - * Added a new ``/temp/precompiled`` folder for precompiled vendor libraries - * QuestaSim supports Altera QuartusII, Xilinx ISE and Xilinx Vivado libraries - * GHDL supports Altera QuartusII, Xilinx ISE and Xilinx Vivado libraries - - -New in 0.21 (17.02.2016) -================================================================================================================================================================ - - -New in 0.20 (16.01.2016) -================================================================================================================================================================ - - -New in 0.19 (16.01.2016) -================================================================================================================================================================ - -**************************************************************************************************************************************************************** -2015 -**************************************************************************************************************************************************************** - -New in 0.18 (16.12.2015) -================================================================================================================================================================ - - -New in 0.17 (08.12.2015) -================================================================================================================================================================ - - -New in 0.16 (01.12.2015) -================================================================================================================================================================ - - -New in 0.15 (13.11.2015) -================================================================================================================================================================ - - -New in 0.14 (28.09.2015) -================================================================================================================================================================ - - -New in 0.13 (04.09.2015) -================================================================================================================================================================ - - -New in 0.12 (25.08.2015) -================================================================================================================================================================ - - -New in 0.11 (07.08.2015) -================================================================================================================================================================ - - -New in 0.10 (23.07.2015) -================================================================================================================================================================ - - -New in 0.9 (21.07.2015) -================================================================================================================================================================ - - -New in 0.8 (03.07.2015) -================================================================================================================================================================ - - -New in 0.7 (27.06.2015) -================================================================================================================================================================ - - -New in 0.6 (09.06.2015) -================================================================================================================================================================ - - -New in 0.5 (27.05.2015) -================================================================================================================================================================ - -* Updated Python infrastructure -* New testbenches: - - * sync_Reset_tb - * sync_Flag_tb - * sync_Strobe_tb - * sync_Vector_tb - * sync_Command_tb - -* Updated modules: - - * sync_Vector - * sync_Command - -* Updated packages: - - * physical - * utils - * vectors - * xil - -New in 0.4 (29.04.2015) -================================================================================================================================================================ - -* New Python infrastructure - - * Added simulators for: - - * GHDL + GTKWave - * Mentor Graphic QuestaSim - * Xilinx ISE Simulator - * Xilinx Vivado Simulator - -* New packages: - - * simulation - -* New modules: - - * PoC.comm - communication modules - - * comm_crc - - * PoC.comm.remote - remote communication modules - - * remote_terminal_control - -* New testbenches: - - * arith_addw_tb - * arith_counter_bcd_tb - * arith_prefix_and_tb - * arith_prefix_or_tb - * arith_prng_tb - -* Updated packages: - - * board - * config - * physical - * strings - * utils - -* Updated modules: - - * io_Debounce - * misc_FrequencyMeasurement - * sync_Bits - * sync_Reset - -New in 0.3 (31.03.20015) -================================================================================================================================================================ - -* Added Python infrastructure - - * Added platform wrapper scripts (\*.sh, \*.ps1) - * Added IP-core compiler scripts Netlist.py - -* Added Tools - - * Notepad++ syntax file for Xilinx UCF/XCF files - * Git configuration script to register global aliases - -* New packages: - - * components - hardware described as functions - * physical - physical types like frequency, memory and baudrate - * io - -* New modules: - - * PoC.misc - - * misc_FrequencyMeasurement - - * PoC.io - Low-speed I/O interfaces - - * io_7SegmentMux_BCD - * io_7SegmentMux_HEX - * io_FanControl - * io_PulseWidthModulation - * io_TimingCounter - * io_Debounce - * io_GlitchFilter - -* New IP-cores: - - * PoC.xil - Xilinx specific modules - - * xil_ChipScopeICON_1 - * xil_ChipScopeICON_2 - * xil_ChipScopeICON_3 - * xil_ChipScopeICON_4 - * xil_ChipScopeICON_6 - * xil_ChipScopeICON_7 - * xil_ChipScopeICON_8 - * xil_ChipScopeICON_9 - * xil_ChipScopeICON_10 - * xil_ChipScopeICON_11 - * xil_ChipScopeICON_12 - * xil_ChipScopeICON_13 - * xil_ChipScopeICON_14 - * xil_ChipScopeICON_15 - -* New constraint files: - - * ML605 - * KC705 - * VC707 - * MetaStability - * xil_Sync - -* Updated packages: - - * board - * config - -* Updated modules: - - * xil_BSCAN - -New in 0.2 (09.03.2015) -================================================================================================================================================================ - -* New packages: - - * xil - * stream - -* New modules: - - * PoC.bus - Modules for busses - - * bus_Arbiter - - * PoC.bus.stream - Modules for the PoC.Stream protocol - - * stream_Buffer - * stream_DeMux - * stream_FrameGenerator - * stream_Mirror - * stream_Mux - * stream_Source - - * PoC.misc.sync - Cross-Clock Synchronizers - - * sync_Reset - * sync_Flag - * sync_Strobe - * sync_Vector - * sync_Command - - * PoC.xil - Xilinx specific modules - - * xil_SyncBits - * xil_SyncReset - * xil_BSCAN - * xil_Reconfigurator - * xil_SystemMonitor_Virtex6 - * xil_SystemMonitor_Series7 - -* Updated packages: - - * utils - * arith - -New in 0.1 (19.02.2015) -================================================================================================================================================================ - -* New packages: - - * board - common development board configurations - * config - extract configuration parameters from device names - * utils - common utility functions - * strings - a helper package for string handling - * vectors - a helper package for std_logic_vector and std_logic_matrix - * arith - * fifo - -* New modules - - * PoC.arith - arithmetic modules - - * arith_counter_gray - * arith_counter_ring - * arith_div - * arith_prefix_and - * arith_prefix_or - * arith_prng - * arith_scaler - * arith_sqrt - - * PoC.fifo - FIFOs - - * fifo_cc_got - * fifo_cc_got_tempgot - * fifo_cc_got_tempput - * fifo_ic_got - * fifo_glue - * fifo_shift - - * PoC.mem.ocram - On-Chip RAMs - - * ocram_sp - * ocram_sdp - * ocram_esdp - * ocram_tdp - * ocram_wb - -**************************************************************************************************************************************************************** -2014 -**************************************************************************************************************************************************************** - -New in 0.0 (16.12.2014) -================================================================================================================================================================ - -* Initial commit diff --git a/docs/Miscelaneous/ThirdParty.rst b/docs/Miscelaneous/ThirdParty.rst index b5b6caf5..787a2363 100644 --- a/docs/Miscelaneous/ThirdParty.rst +++ b/docs/Miscelaneous/ThirdParty.rst @@ -1,3 +1,8 @@ +.. index:: + single: Third-Party Libraries + +.. _THIRD: + Third Party Libraries ##################### @@ -6,6 +11,13 @@ located in the ``/lib/`` folder. This document lists all these libraries, their websites and licenses. +.. # =========================================================================================================================================================== + +.. index:: + pair: Third-Party Libraries; Cocotb + +.. _THIRD:Cocotb: + Cocotb ****** @@ -17,7 +29,7 @@ library for writing VHDL and Verilog testbenches in Python. +--------------------+-----------------------------------------------------------------------------------------------------------+ | **Copyright:** | Copyright © 2013, `Potential Ventures Ltd. `_, SolarFlare Communications Inc. | +--------------------+-----------------------------------------------------------------------------------------------------------+ -| **License:** | :doc:`Revised BSD License (local copy) ` | +| **License:** | :doc:`Revised BSD License (local copy) ` | +--------------------+-----------------------------------------------------------------------------------------------------------+ | **Documentation:** | `http://cocotb.readthedocs.org/ `_ | +--------------------+-----------------------------------------------------------------------------------------------------------+ @@ -25,6 +37,13 @@ library for writing VHDL and Verilog testbenches in Python. +--------------------+-----------------------------------------------------------------------------------------------------------+ +.. # =========================================================================================================================================================== + +.. index:: + pair: Third-Party Libraries; OSVVM + +.. _THIRD:OSVVM: + OSVVM ***** @@ -49,6 +68,52 @@ existing testbench or testbench models. +----------------+---------------------------------------------------------------------------------------+ +.. # =========================================================================================================================================================== + +.. index:: + pair: Third-Party Libraries; UVVM + +.. _THIRD:UVVM: + +UVVM +**** + +The Open Source **UVVM (Universal VHDL Verification Methodology) - VVC (VHDL +Verification Component) Framework** for making structured VHDL testbenches for +verification of FPGA. UVVM consists currently of: Utility Library, VVC +Framework and Verification IPs (VIP) for various protocols. + +**For what do I need this VVC Framework?** |br| +The VVC Framework is a VHDL Verification Component system that allows multiple +interfaces on a DUT to be stimulated/handled simultaneously in a very structured +manner, and controlled by a very simple to understand software like a test +sequencer. VVC Framework is unique as an open source VHDL approach to building +a structured testbench architecture using Verification components and a simple +protocol to access these. As an example a simple command like +``uart_expect(UART_VVCT, my_data)``, or ``axilite_write(AXILITE_VVCT, my_addr, my_data, my_message)`` +will automatically tell the respective VVC (for UART or AXI-Lite) to execute +the ``uart_receive()`` or ``axilite_write()`` BFM respectively. + ++----------------+---------------------------------------------------------------------------------------+ +| **Folder:** | ``\lib\uvvm\`` | ++----------------+---------------------------------------------------------------------------------------+ +| **Copyright:** | Copyright © 2016 by `Bitvis AS `_ | ++----------------+---------------------------------------------------------------------------------------+ +| **License:** | :doc:`The MIT License (local copy) ` | ++----------------+---------------------------------------------------------------------------------------+ +| **Website:** | `http://bitvis.no/ `_ | ++----------------+---------------------------------------------------------------------------------------+ +| **Source:** | `https://github.com/UVVM/UVVM_All `_ | ++----------------+---------------------------------------------------------------------------------------+ + + +.. # =========================================================================================================================================================== + +.. index:: + pair: Third-Party Libraries; VUnit + +.. _THIRD:VUnit: + VUnit ***** diff --git a/docs/PoC/arith/arith.pkg.rst b/docs/PoC/arith/arith.pkg.rst deleted file mode 100644 index bbf3b007..00000000 --- a/docs/PoC/arith/arith.pkg.rst +++ /dev/null @@ -1,34 +0,0 @@ - -Package -======== - -This package holds all component declarations for this namespace. - -.. rubric:: Exported Enumerations - - * ``tArch`` - * ``tBlocking`` - * ``tSkipping`` - -.. rubric:: Exported Functions - - * ``arith_div_latency`` - -.. rubric:: Exported Components - - * :doc:`PoC.arith.addw ` - * :doc:`PoC.arith.carrychain_inc_xilinx ` - * :doc:`PoC.arith.counter_bcd ` - * :doc:`PoC.arith.counter_gray ` - * :doc:`PoC.arith.div ` - * :doc:`PoC.arith.firstone ` - * :doc:`PoC.arith.inc_ovcy_xilinx ` - * :doc:`PoC.arith.muls_wide ` - * :doc:`PoC.arith.prefix_and_xilinx ` - * :doc:`PoC.arith.prefix_or_xilinx ` - * :doc:`PoC.arith.prng ` - * :doc:`PoC.arith.same ` - * :doc:`PoC.arith.sqrt ` - -Source file: `arith/arith.pkg.vhdl `_ - diff --git a/docs/PoC/arith/arith_addw.rst b/docs/PoC/arith/arith_addw.rst deleted file mode 100644 index b96675bc..00000000 --- a/docs/PoC/arith/arith_addw.rst +++ /dev/null @@ -1,34 +0,0 @@ - -arith_addw -########## - - Implements wide addition providing several options all based - on an adaptation of a carry-select approach. - - References: - * Hong Diep Nguyen and Bogdan Pasca and Thomas B. Preusser: - FPGA-Specific Arithmetic Optimizations of Short-Latency Adders, - FPL 2011. - -> ARCH: AAM, CAI, CCA - -> SKIPPING: CCC - - * Marcin Rogawski, Kris Gaj and Ekawat Homsirikamol: - A Novel Modular Adder for One Thousand Bits and More - Using Fast Carry Chains of Modern FPGAs, FPL 2014. - -> ARCH: PAI - -> SKIPPING: PPN_KS, PPN_BK - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/arith/arith_addw.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 53-70 - -Source file: `arith/arith_addw.vhdl `_ - - - diff --git a/docs/PoC/arith/arith_bcdcollect.rst b/docs/PoC/arith/arith_bcdcollect.rst deleted file mode 100644 index 05298e28..00000000 --- a/docs/PoC/arith/arith_bcdcollect.rst +++ /dev/null @@ -1,20 +0,0 @@ - -arith_bcdcollect -################ - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/arith/arith_bcdcollect.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 37-55 - -Source file: `arith/arith_bcdcollect.vhdl `_ - - - diff --git a/docs/PoC/arith/arith_carrychain_inc.rst b/docs/PoC/arith/arith_carrychain_inc.rst deleted file mode 100644 index c9cbaf9a..00000000 --- a/docs/PoC/arith/arith_carrychain_inc.rst +++ /dev/null @@ -1,22 +0,0 @@ - -arith_carrychain_inc -#################### - - This is a generic carry-chain abstraction for increment by one operations. - - Y <= X + (0...0) & Cin - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/arith/arith_carrychain_inc.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 43-52 - -Source file: `arith/arith_carrychain_inc.vhdl `_ - - - diff --git a/docs/PoC/arith/arith_convert_bin2bcd.rst b/docs/PoC/arith/arith_convert_bin2bcd.rst deleted file mode 100644 index 01e101cc..00000000 --- a/docs/PoC/arith/arith_convert_bin2bcd.rst +++ /dev/null @@ -1,20 +0,0 @@ - -arith_convert_bin2bcd -##################### - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/arith/arith_convert_bin2bcd.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 40-58 - -Source file: `arith/arith_convert_bin2bcd.vhdl `_ - - - diff --git a/docs/PoC/arith/arith_counter_bcd.rst b/docs/PoC/arith/arith_counter_bcd.rst deleted file mode 100644 index c41824ec..00000000 --- a/docs/PoC/arith/arith_counter_bcd.rst +++ /dev/null @@ -1,31 +0,0 @@ - -arith_counter_bcd -################# - -Counter with output in binary coded decimal (BCD). The number of BCD digits -is configurable by ``DIGITS``. - -All control signals (reset ``rst``, increment ``inc``) are high-active and -synchronous to clock ``clk``. The output ``val`` is the current counter -state. Groups of 4 bit represent one BCD digit. The lowest significant digit -is specified by ``val(3 downto 0)``. - -.. TODO:: - - * implement a ``dec`` input for decrementing - * implement a ``load`` input to load a value - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/arith/arith_counter_bcd.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 51-61 - -Source file: `arith/arith_counter_bcd.vhdl `_ - - - diff --git a/docs/PoC/arith/arith_counter_free.rst b/docs/PoC/arith/arith_counter_free.rst deleted file mode 100644 index b62a3526..00000000 --- a/docs/PoC/arith/arith_counter_free.rst +++ /dev/null @@ -1,27 +0,0 @@ - -arith_counter_free -################## - -Implements a free-running counter that generates a strobe signal every -DIVIDER-th cycle the increment input was asserted. There is deliberately no -output or specification of the counter value so as to allow an implementation -to optimize as much as possible. - -The implementation guarantees a strobe output directly from a register. It is -asserted exactly for one clock after DIVIDER cycles of an asserted increment -input have been observed. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/arith/arith_counter_free.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 41-53 - -Source file: `arith/arith_counter_free.vhdl `_ - - - diff --git a/docs/PoC/arith/arith_counter_gray.rst b/docs/PoC/arith/arith_counter_gray.rst deleted file mode 100644 index af2e3fc5..00000000 --- a/docs/PoC/arith/arith_counter_gray.rst +++ /dev/null @@ -1,20 +0,0 @@ - -arith_counter_gray -################## - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/arith/arith_counter_gray.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 38-51 - -Source file: `arith/arith_counter_gray.vhdl `_ - - - diff --git a/docs/PoC/arith/arith_counter_ring.rst b/docs/PoC/arith/arith_counter_ring.rst deleted file mode 100644 index 0a27c8c6..00000000 --- a/docs/PoC/arith/arith_counter_ring.rst +++ /dev/null @@ -1,23 +0,0 @@ - -arith_counter_ring -################## - -This module implements an up/down ring-counter with loadable initial value -(``seed``) on reset. The counter can be configured to a Johnson counter by -enabling ``INVERT_FEEDBACK``. The number of counter bits is configurable with -``BITS``. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/arith/arith_counter_ring.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 41-54 - -Source file: `arith/arith_counter_ring.vhdl `_ - - - diff --git a/docs/PoC/arith/arith_div.rst b/docs/PoC/arith/arith_div.rst deleted file mode 100644 index aa2a1b0d..00000000 --- a/docs/PoC/arith/arith_div.rst +++ /dev/null @@ -1,24 +0,0 @@ - -arith_div -######### - -Implementation of a Non-Performing restoring divider with a configurable radix. -The multi-cycle division is controlled by 'start' / 'rdy'. A new division is -started by asserting 'start'. The result Q = A/D is available when 'rdy' -returns to '1'. A division by zero is identified by output Z. The Q and R -outputs are undefined in this case. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/arith/arith_div.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 38-61 - -Source file: `arith/arith_div.vhdl `_ - - - diff --git a/docs/PoC/arith/arith_firstone.rst b/docs/PoC/arith/arith_firstone.rst deleted file mode 100644 index d5e5a5b3..00000000 --- a/docs/PoC/arith/arith_firstone.rst +++ /dev/null @@ -1,33 +0,0 @@ - -arith_firstone -############## - -Computes from an input word, a word of the same size that has, at most, -one bit set. The output contains a set bit at the position of the rightmost -set bit of the input if and only if such a set bit exists in the input. - -A typical use case for this computation would be an arbitration over -requests with a fixed and strictly ordered priority. The terminology of -the interface assumes this use case and provides some useful extras: - -* Set tin <= '0' (no input token) to disallow grants altogether. -* Read tout (unused token) to see whether or any grant was issued. -* Read bin to obtain the binary index of the rightmost detected one bit. - The index starts at zero (0) in the rightmost bit position. - -This implementation uses carry chains for wider implementations. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/arith/arith_firstone.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 50-61 - -Source file: `arith/arith_firstone.vhdl `_ - - - diff --git a/docs/PoC/arith/arith_muls_wide.rst b/docs/PoC/arith/arith_muls_wide.rst deleted file mode 100644 index 80bb5fb7..00000000 --- a/docs/PoC/arith/arith_muls_wide.rst +++ /dev/null @@ -1,22 +0,0 @@ - -arith_muls_wide -############### - -Signed wide multiplication spanning multiple DSP or MULT blocks. -Small partial products are calculated through LUTs. -For detailed documentation see below. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/arith/arith_muls_wide.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 38-49 - -Source file: `arith/arith_muls_wide.vhdl `_ - - - diff --git a/docs/PoC/arith/arith_prefix_and.rst b/docs/PoC/arith/arith_prefix_and.rst deleted file mode 100644 index 8e939c2f..00000000 --- a/docs/PoC/arith/arith_prefix_and.rst +++ /dev/null @@ -1,22 +0,0 @@ - -arith_prefix_and -################ - -Prefix AND computation: -``y(i) <= '1' when x(i downto 0) = (i downto 0 => '1') else '0';`` -This implementation uses carry chains for wider implementations. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/arith/arith_prefix_and.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 43-51 - -Source file: `arith/arith_prefix_and.vhdl `_ - - - diff --git a/docs/PoC/arith/arith_prefix_or.rst b/docs/PoC/arith/arith_prefix_or.rst deleted file mode 100644 index 3c40904b..00000000 --- a/docs/PoC/arith/arith_prefix_or.rst +++ /dev/null @@ -1,22 +0,0 @@ - -arith_prefix_or -############### - -Prefix OR computation: -``y(i) <= '0' when x(i downto 0) = (i downto 0 => '0') else '1';`` -This implementation uses carry chains for wider implementations. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/arith/arith_prefix_or.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 43-51 - -Source file: `arith/arith_prefix_or.vhdl `_ - - - diff --git a/docs/PoC/arith/arith_prng.rst b/docs/PoC/arith/arith_prng.rst deleted file mode 100644 index 4c56a7d2..00000000 --- a/docs/PoC/arith/arith_prng.rst +++ /dev/null @@ -1,26 +0,0 @@ - -arith_prng -########## - -This module implementes a Pseudo-Random Number Generator (PRNG) with -configurable bit count (``BITS``). This module uses an internal list of FPGA -optimized polynomials from 3 to 168 bits. The polynomials have at most 5 tap -positions, so that long shift registers can be inferred instead of single -flip-flops. - -The generated number sequence includes the value all-zeros, but not all-ones. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/arith/arith_prng.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 46-57 - -Source file: `arith/arith_prng.vhdl `_ - - - diff --git a/docs/PoC/arith/arith_same.rst b/docs/PoC/arith/arith_same.rst deleted file mode 100644 index 2a54dbc5..00000000 --- a/docs/PoC/arith/arith_same.rst +++ /dev/null @@ -1,27 +0,0 @@ - -arith_same -########## - -This circuit may, for instance, be used to detect the first sign change -and, thus, the range of a two's complement number. - -These components may be chained by using the output of the predecessor as -guard input. This chaining allows to have intermediate results available -while still ensuring the use of a fast carry chain on supporting FPGA -architectures. When chaining, make sure to overlap both vector slices by one -bit position as to avoid an undetected sign change between the slices. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/arith/arith_same.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 48-57 - -Source file: `arith/arith_same.vhdl `_ - - - diff --git a/docs/PoC/arith/arith_shifter_barrel.rst b/docs/PoC/arith/arith_shifter_barrel.rst deleted file mode 100644 index 309c3295..00000000 --- a/docs/PoC/arith/arith_shifter_barrel.rst +++ /dev/null @@ -1,26 +0,0 @@ - -arith_shifter_barrel -#################### - -This Barrel-Shifter supports: - -* shifting and rotating -* right and left operations -* arithmetic and logic mode (only valid for shift operations) - -This is equivalent to the CPU instructions: SLL, SLA, SRL, SRA, RL, RR - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/arith/arith_shifter_barrel.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 45-57 - -Source file: `arith/arith_shifter_barrel.vhdl `_ - - - diff --git a/docs/PoC/arith/arith_sqrt.rst b/docs/PoC/arith/arith_sqrt.rst deleted file mode 100644 index 8f3d9fb8..00000000 --- a/docs/PoC/arith/arith_sqrt.rst +++ /dev/null @@ -1,22 +0,0 @@ - -arith_sqrt -########## - -Iterative Square Root Extractor. - -Its computation requires (N+1)/2 steps for an argument bit width of N. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/arith/arith_sqrt.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 38-55 - -Source file: `arith/arith_sqrt.vhdl `_ - - - diff --git a/docs/PoC/arith/index.rst b/docs/PoC/arith/index.rst deleted file mode 100644 index 786577f1..00000000 --- a/docs/PoC/arith/index.rst +++ /dev/null @@ -1,52 +0,0 @@ -arith -===== - -These are arithmetic entities.... - -**Package** - -:doc:`PoC.arith ` - -**Entities** - - * :doc:`PoC.arith.addw ` - * :doc:`PoC.arith.carrychain_inc ` - * :doc:`PoC.arith.convert_bin2bcd ` - * :doc:`PoC.arith.counter_bcd ` - * :doc:`PoC.arith.counter_free ` - * :doc:`PoC.arith.counter_gray ` - * :doc:`PoC.arith.counter_ring ` - * :doc:`PoC.arith.div ` - * :doc:`PoC.arith.firstone ` - * :doc:`PoC.arith.muls_wide ` - * :doc:`PoC.arith.prefix_and ` - * :doc:`PoC.arith.prefix_or ` - * :doc:`PoC.arith.prng ` - * :doc:`PoC.arith.same ` - * :doc:`PoC.arith.scaler ` - * :doc:`PoC.arith.shifter_barrel ` - * :doc:`PoC.arith.sqrt ` - - -.. toctree:: - :hidden: - - arith.pkg - - arith_addw - arith_carrychain_inc - arith_convert_bin2bcd - arith_counter_bcd - arith_counter_free - arith_counter_gray - arith_counter_ring - arith_div - arith_firstone - arith_muls_wide - arith_prefix_and - arith_prefix_or - arith_prng - arith_same - arith_scaler - arith_shifter_barrel - arith_sqrt diff --git a/docs/PoC/bus/bus_Arbiter.rst b/docs/PoC/bus/bus_Arbiter.rst deleted file mode 100644 index 2fbef755..00000000 --- a/docs/PoC/bus/bus_Arbiter.rst +++ /dev/null @@ -1,23 +0,0 @@ - -bus_Arbiter -########### - -This module implements a generic arbiter. It currently supports the -following arbitration strategies: - -* Round Robin (RR) - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/bus/bus_Arbiter.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 42-60 - -Source file: `bus/bus_Arbiter.vhdl `_ - - - diff --git a/docs/PoC/bus/index.rst b/docs/PoC/bus/index.rst deleted file mode 100644 index 911fe07b..00000000 --- a/docs/PoC/bus/index.rst +++ /dev/null @@ -1,22 +0,0 @@ - -bus -=== - -These are bus entities.... - -**Sub-namespaces** - - * :doc:`PoC.bus.stream ` - * :doc:`PoC.bus.wb ` - -**Entities** - - * :doc:`PoC.bus.Arbiter ` - -.. toctree:: - :hidden: - - stream/index - wb/index - - bus_Arbiter diff --git a/docs/PoC/bus/stream/index.rst b/docs/PoC/bus/stream/index.rst deleted file mode 100644 index 7d23fbf0..00000000 --- a/docs/PoC/bus/stream/index.rst +++ /dev/null @@ -1,15 +0,0 @@ - -stream -^^^^^^ - -PoC.Stream modules ... - -.. toctree:: - - stream_Buffer - stream_DeMux - stream_Mux - stream_Mirror - stream_Sink - stream_Source - stream_FrameGenerator diff --git a/docs/PoC/bus/stream/stream_Buffer.rst b/docs/PoC/bus/stream/stream_Buffer.rst deleted file mode 100644 index 0cab881a..00000000 --- a/docs/PoC/bus/stream/stream_Buffer.rst +++ /dev/null @@ -1,23 +0,0 @@ - -stream_Buffer -############# - -This module implements a generic buffer (FIFO) for the -:doc:`PoC.Stream ` protocol. It is generic in -``DATA_BITS`` and in ``META_BITS`` as well as in FIFO depths for data and -meta information. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/bus/stream/stream_Buffer.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 44-74 - -Source file: `bus/stream/stream_Buffer.vhdl `_ - - - diff --git a/docs/PoC/bus/stream/stream_DeMux.rst b/docs/PoC/bus/stream/stream_DeMux.rst deleted file mode 100644 index 4a75cdc4..00000000 --- a/docs/PoC/bus/stream/stream_DeMux.rst +++ /dev/null @@ -1,20 +0,0 @@ - -stream_DeMux -############ - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/bus/stream/stream_DeMux.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 41-70 - -Source file: `bus/stream/stream_DeMux.vhdl `_ - - - diff --git a/docs/PoC/bus/stream/stream_FrameGenerator.rst b/docs/PoC/bus/stream/stream_FrameGenerator.rst deleted file mode 100644 index 83531c5d..00000000 --- a/docs/PoC/bus/stream/stream_FrameGenerator.rst +++ /dev/null @@ -1,20 +0,0 @@ - -stream_FrameGenerator -##################### - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/bus/stream/stream_FrameGenerator.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 40-66 - -Source file: `bus/stream/stream_FrameGenerator.vhdl `_ - - - diff --git a/docs/PoC/bus/stream/stream_Mirror.rst b/docs/PoC/bus/stream/stream_Mirror.rst deleted file mode 100644 index 166f44b3..00000000 --- a/docs/PoC/bus/stream/stream_Mirror.rst +++ /dev/null @@ -1,20 +0,0 @@ - -stream_Mirror -############# - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/bus/stream/stream_Mirror.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 41-70 - -Source file: `bus/stream/stream_Mirror.vhdl `_ - - - diff --git a/docs/PoC/bus/stream/stream_Mux.rst b/docs/PoC/bus/stream/stream_Mux.rst deleted file mode 100644 index 4f8f069b..00000000 --- a/docs/PoC/bus/stream/stream_Mux.rst +++ /dev/null @@ -1,20 +0,0 @@ - -stream_Mux -########## - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/bus/stream/stream_Mux.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 41-69 - -Source file: `bus/stream/stream_Mux.vhdl `_ - - - diff --git a/docs/PoC/bus/stream/stream_Sink.rst b/docs/PoC/bus/stream/stream_Sink.rst deleted file mode 100644 index 718ef6c0..00000000 --- a/docs/PoC/bus/stream/stream_Sink.rst +++ /dev/null @@ -1,20 +0,0 @@ - -stream_Sink -########### - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/bus/stream/stream_Sink.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 42-59 - -Source file: `bus/stream/stream_Sink.vhdl `_ - - - diff --git a/docs/PoC/bus/stream/stream_Source.rst b/docs/PoC/bus/stream/stream_Source.rst deleted file mode 100644 index 5f182b9b..00000000 --- a/docs/PoC/bus/stream/stream_Source.rst +++ /dev/null @@ -1,20 +0,0 @@ - -stream_Source -############# - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/bus/stream/stream_Source.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 42-58 - -Source file: `bus/stream/stream_Source.vhdl `_ - - - diff --git a/docs/PoC/bus/wb/index.rst b/docs/PoC/bus/wb/index.rst deleted file mode 100644 index 1248d92b..00000000 --- a/docs/PoC/bus/wb/index.rst +++ /dev/null @@ -1,12 +0,0 @@ - -wb -^^ - -WishBone modules ... - -**Entities:** - -.. toctree:: - wb_ocram - wb_fifo_adapter - wb_uart_wrapper diff --git a/docs/PoC/bus/wb/wb_fifo_adapter.rst b/docs/PoC/bus/wb/wb_fifo_adapter.rst deleted file mode 100644 index bbffb8e4..00000000 --- a/docs/PoC/bus/wb/wb_fifo_adapter.rst +++ /dev/null @@ -1,27 +0,0 @@ - -wb_fifo_adapter -############### - -Small FIFOs are included in this module, if larger or asynchronous -transmit / receive FIFOs are required, then they must be connected -externally. - -old comments: - UART BAUD rate generator - bclk_r = bit clock is rising - bclk_x8_r = bit clock times 8 is rising - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/bus/wb/wb_fifo_adapter.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 80-104 - -Source file: `bus/wb/wb_fifo_adapter.vhdl `_ - - - diff --git a/docs/PoC/bus/wb/wb_ocram.rst b/docs/PoC/bus/wb/wb_ocram.rst deleted file mode 100644 index 89a2daf7..00000000 --- a/docs/PoC/bus/wb/wb_ocram.rst +++ /dev/null @@ -1,39 +0,0 @@ - -ocram_wb -######## - -This slave supports Wishbone Registered Feedback bus cycles (aka. burst -transfers / advanced synchronous cycle termination). The mode "Incrementing -burst cycle" (CTI = 010) with "Linear burst" (BTE = 00) is supported. - -If your master does support Wishbone Classis bus cycles only, then connect -wb_cti_i = "000" and wb_bte_i = "00". - -Connect the ocram of your choice to the ram_* port signals. (Every RAM with -single cyle read latency is supported.) - -Configuration: --------------- -PIPE_STAGES = 1 - The RAM output is directly connected to the bus. Thus, the - read access latency (one cycle) is short. But, the RAM's read timing delay - must be respected. - -PIPE_STAGES = 2 - The RAM output is registered again. Thus, the read access - latency is two cycles. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/bus/wb/wb_ocram.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 54-80 - -Source file: `bus/wb/wb_ocram.vhdl `_ - - - diff --git a/docs/PoC/bus/wb/wb_uart_wrapper.rst b/docs/PoC/bus/wb/wb_uart_wrapper.rst deleted file mode 100644 index 48e5bd7c..00000000 --- a/docs/PoC/bus/wb/wb_uart_wrapper.rst +++ /dev/null @@ -1,22 +0,0 @@ - -uart_wb -####### - -Wrapper module for :doc:`PoC.io.uart.rx ` and -:doc:`PoC.io.uart.tx ` to support the Wishbone -interface. Synchronized reset is used. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/bus/wb/wb_uart_wrapper.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 40-69 - -Source file: `bus/wb/wb_uart_wrapper.vhdl `_ - - - diff --git a/docs/PoC/cache/cache_tagunit_par.rst b/docs/PoC/cache/cache_tagunit_par.rst deleted file mode 100644 index 5f31022f..00000000 --- a/docs/PoC/cache/cache_tagunit_par.rst +++ /dev/null @@ -1,55 +0,0 @@ - -cache_tagunit_par -################# - -All inputs are synchronous to the rising-edge of the clock ``clock``. - -**Command thruth table:** - -+---------+-----------+-------------+---------+----------------------------------+ -| Request | ReadWrite | Invalidate | Replace | Command | -+=========+===========+=============+=========+==================================+ -| 0 | 0 | 0 | 0 | None | -+---------+-----------+-------------+---------+----------------------------------+ -| 1 | 0 | 0 | 0 | Read cache line | -+---------+-----------+-------------+---------+----------------------------------+ -| 1 | 1 | 0 | 0 | Update cache line | -+---------+-----------+-------------+---------+----------------------------------+ -| 1 | 0 | 1 | 0 | Read cache line and discard it | -+---------+-----------+-------------+---------+----------------------------------+ -| 1 | 1 | 1 | 0 | Write cache line and discard it | -+---------+-----------+-------------+---------+----------------------------------+ -| 0 | | 0 | 1 | Replace cache line. | -+---------+-----------+-------------+---------+----------------------------------+ - -All commands use ``Address`` to lookup (request) or replace a cache line. -Each command is completed within one clock cycle. - -Upon requests, the outputs ``CacheMiss`` and ``CacheHit`` indicate (high-active) -immediately (combinational) whether the ``Address`` is stored within the cache, or not. -But, the cache-line usage is updated at the rising-edge of the clock. -If hit, ``LineIndex`` specifies the cache line where to find the content. - -The output ``ReplaceLineIndex`` indicates which cache line will be replaced as -next by a replace command. The output ``OldAddress`` specifies the old tag stored at this -index. The replace command will store the ``NewAddress`` and update the cache-line -usage at the rising-edge of the clock. - -For a direct-mapped cache, the number of ``CACHE_LINES`` must be a power of 2. -For a set-associative cache, the expression ``CACHE_LINES / ASSOCIATIVITY`` -must be a power of 2. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/cache/cache_tagunit_par.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 75-99 - -Source file: `cache/cache_tagunit_par.vhdl `_ - - - diff --git a/docs/PoC/cache/cache_tagunit_seq.rst b/docs/PoC/cache/cache_tagunit_seq.rst deleted file mode 100644 index 1268786c..00000000 --- a/docs/PoC/cache/cache_tagunit_seq.rst +++ /dev/null @@ -1,20 +0,0 @@ - -cache_tagunit_seq -################# - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/cache/cache_tagunit_seq.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 39-73 - -Source file: `cache/cache_tagunit_seq.vhdl `_ - - - diff --git a/docs/PoC/cache/index.rst b/docs/PoC/cache/index.rst deleted file mode 100644 index a49a74df..00000000 --- a/docs/PoC/cache/index.rst +++ /dev/null @@ -1,20 +0,0 @@ - -cache -===== - -These are cache entities.... - -**Entities** - - * :doc:`PoC.cache.par ` - * :doc:`PoC.cache.tagunit_par ` - * :doc:`PoC.cache.tagunit_seq ` - - -.. toctree:: - :hidden: - - cache_par - cache_replacement_policy - cache_tagunit_par - cache_tagunit_seq diff --git a/docs/PoC/comm/comm_crc.rst b/docs/PoC/comm/comm_crc.rst deleted file mode 100644 index f50c7508..00000000 --- a/docs/PoC/comm/comm_crc.rst +++ /dev/null @@ -1,26 +0,0 @@ - -comm_crc -######## - -Computes the Cyclic Redundancy Check (CRC) for a data packet as remainder -of the polynomial division of the message by the given generator -polynomial (GEN). - -The computation is unrolled so as to process an arbitrary number of -message bits per step. The generated CRC is independent from the chosen -processing width. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/comm/comm_crc.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 45-64 - -Source file: `comm/comm_crc.vhdl `_ - - - diff --git a/docs/PoC/comm/comm_scramble.rst b/docs/PoC/comm/comm_scramble.rst deleted file mode 100644 index 1a6d0c3d..00000000 --- a/docs/PoC/comm/comm_scramble.rst +++ /dev/null @@ -1,22 +0,0 @@ - -comm_scramble -############# - -The LFSR computation is unrolled to generate an arbitrary number of mask -bits in parallel. The mask are output in little endian. The generated bit -sequence is independent from the chosen output width. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/comm/comm_scramble.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 37-51 - -Source file: `comm/comm_scramble.vhdl `_ - - - diff --git a/docs/PoC/comm/index.rst b/docs/PoC/comm/index.rst deleted file mode 100644 index 5063c228..00000000 --- a/docs/PoC/comm/index.rst +++ /dev/null @@ -1,10 +0,0 @@ - -comm -==== - -These are communication entities.... - -.. toctree:: - - comm_crc - comm_scramble diff --git a/docs/PoC/fifo/fifo.pkg.rst b/docs/PoC/fifo/fifo.pkg.rst deleted file mode 100644 index 967ddd16..00000000 --- a/docs/PoC/fifo/fifo.pkg.rst +++ /dev/null @@ -1,7 +0,0 @@ - -Package -======== - -This package holds all component declarations for this namespace. - -Source file: `fifo/fifo.pkg.vhdl `_ diff --git a/docs/PoC/fifo/fifo_glue.rst b/docs/PoC/fifo/fifo_glue.rst deleted file mode 100644 index 5ec75bcb..00000000 --- a/docs/PoC/fifo/fifo_glue.rst +++ /dev/null @@ -1,22 +0,0 @@ - -fifo_glue -######### - -Its primary use is the decoupling of enable domains in a processing -pipeline. Data storage is limited to two words only so as to allow both -the ``ful`` and the ``vld`` indicators to be driven by registers. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/fifo/fifo_glue.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 36-55 - -Source file: `fifo/fifo_glue.vhdl `_ - - - diff --git a/docs/PoC/fifo/fifo_ic_assembly.rst b/docs/PoC/fifo/fifo_ic_assembly.rst deleted file mode 100644 index 52c30ac4..00000000 --- a/docs/PoC/fifo/fifo_ic_assembly.rst +++ /dev/null @@ -1,31 +0,0 @@ - -fifo_ic_assembly -################ - -This module assembles a FIFO stream from data blocks that may arrive -slightly out of order. The arriving data is ordered according to their -address. The streamed output starts with the data word written to -address zero (0) and may proceed all the way to just before the first yet -missing data. The association of data with addresses is used on the input -side for the sole purpose of reconstructing the correct order of the data. -It is assumed to wrap so as to allow an infinite input sequence. Addresses -are not actively exposed to the purely stream-based FIFO output. - -The implemented functionality enables the reconstruction of streams that -are tunnelled across address-based transports that are allowed to reorder -the transmission of data blocks. This applies to many DMA implementations. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/fifo/fifo_ic_assembly.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 45-78 - -Source file: `fifo/fifo_ic_assembly.vhdl `_ - - - diff --git a/docs/PoC/fifo/fifo_shift.rst b/docs/PoC/fifo/fifo_shift.rst deleted file mode 100644 index eafbe1cb..00000000 --- a/docs/PoC/fifo/fifo_shift.rst +++ /dev/null @@ -1,26 +0,0 @@ - -fifo_shift -########## - -This FIFO implementation is based on an internal shift register. This is -especially useful for smaller FIFO sizes, which can be implemented in LUT -storage on some devices (e.g. Xilinx' SRLs). Only a single read pointer is -maintained, which determines the number of valid entries within the -underlying shift register. - -The specified depth (``MIN_DEPTH``) is rounded up to the next suitable value. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/fifo/fifo_shift.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 44-64 - -Source file: `fifo/fifo_shift.vhdl `_ - - - diff --git a/docs/PoC/fifo/index.rst b/docs/PoC/fifo/index.rst deleted file mode 100644 index b05de404..00000000 --- a/docs/PoC/fifo/index.rst +++ /dev/null @@ -1,50 +0,0 @@ - -fifo -==== - -The namespace `PoC.fifo` offers different :abbr:`FIFO (first-in, first-out)` implementations. - -**Package** - -The package :doc:`PoC.fifo ` holds all component declarations for this namespace. - -**Entities** - -PoC offers FIFOs with a `got`-interface. This means, the current read-pointer value -is available on the output. Asserting the `got`-input, acknoledge the processing of -the current output signals and moves the read-pointer to the next value, if available. - -All FIFOs implement a bidirectional flow control (`put`/`full` and `valid`/`got`). -Each FIFO also offers a EmptyState (write-side) and FullState (read-side) to indicate -the current fill-state. - -The prefixes `cc_` (common clock), `dc_` (dependent clock) and `ic_` (independent -clock) refer to the write- and read-side clock relationship. - - * :doc:`PoC.fifo.cc_got ` implements a regular FIFO (one common clock, - got-interface) - * :doc:`PoC.fifo.cc_got_tempgot ` implements a regular FIFO (one common - clock, got-interface), extended by a transactional `tempgot`-interface (read-side). - * :doc:`PoC.fifo.cc_got_tempput ` implements a regular FIFO (one common - clock, got-interface), extended by a transactional `tempput`-interface (write-side). - * :doc:`PoC.fifo.dc_got ` implements a cross-clock FIFO (two related clocks, - got-interface) - * :doc:`PoC.fifo.ic_got ` implements a cross-clock FIFO (two independent clocks, - got-interface) - * :doc:`PoC.fifo.glue ` implements a two-stage FIFO (one common clock, - got-interface) - * :doc:`PoC.fifo.shift ` implements a regular FIFO (one common clock, - got-interface, optimized for FPGAs with shifter primitives) - -.. toctree:: - :hidden: - - fifo.pkg - - fifo_cc_got - fifo_cc_got_tempgot - fifo_cc_got_tempput - fifo_glue - fifo_ic_assembly - fifo_ic_got - fifo_shift diff --git a/docs/PoC/index.rst b/docs/PoC/index.rst deleted file mode 100644 index ea416c0b..00000000 --- a/docs/PoC/index.rst +++ /dev/null @@ -1,36 +0,0 @@ - -IP Core Documentations -###################### - -Namespace for Packages: - -.. toctree:: - - common/index - sim/index - -Namespaces for Entities: - -.. toctree:: - - alt/index - arith/index - bus/index - cache/index - comm/index - dstruct/index - fifo/index - io/index - mem/index - misc/index - net/index - -.. only:: PoCInternal - - .. toctree:: - sata/index - -.. toctree:: - - sort/index - xil/index diff --git a/docs/PoC/io/ddrio/ddrio_in.rst b/docs/PoC/io/ddrio/ddrio_in.rst deleted file mode 100644 index 32f3b50b..00000000 --- a/docs/PoC/io/ddrio/ddrio_in.rst +++ /dev/null @@ -1,42 +0,0 @@ - -ddrio_in -######## - -Instantiates chip-specific :abbr:`DDR (Double Data Rate)` input registers. - -Both data ``DataIn_high/low`` are synchronously outputted to the on-chip logic -with the rising edge of ``Clock``. ``DataIn_high`` is the value at the ``Pad`` -sampled with the same rising edge. ``DataIn_low`` is the value sampled with -the falling edge directly before this rising edge. Thus sampling starts with -the falling edge of the clock as depicted in the following waveform. - -.. code-block:: none - - __ ____ ____ __ - Clock |____| |____| |____| - Pad < 0 >< 1 >< 2 >< 3 >< 4 >< 5 > - DataIn_low ... >< 0 >< 2 >< - DataIn_high ... >< 1 >< 3 >< - - < i > is the value of the i-th data bit on the line. - -After power-up, the output ports ``DataIn_high`` and ``DataIn_low`` both equal -INIT_VALUE. - -``Pad`` must be connected to a PAD because FPGAs only have these registers in -IOBs. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/io/ddrio/ddrio_in.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 64-76 - -Source file: `io/ddrio/ddrio_in.vhdl `_ - - - diff --git a/docs/PoC/io/ddrio/ddrio_inout.rst b/docs/PoC/io/ddrio/ddrio_inout.rst deleted file mode 100644 index 95fd3698..00000000 --- a/docs/PoC/io/ddrio/ddrio_inout.rst +++ /dev/null @@ -1,48 +0,0 @@ - -ddrio_inout -########### - -Instantiates chip-specific :abbr:`DDR (Double Data Rate)` input and output -registers. - -Both data ``DataOut_high/low`` as well as ``OutputEnable`` are sampled with -the ``rising_edge(Clock)`` from the on-chip logic. ``DataOut_high`` is brought -out with this rising edge. ``DataOut_low`` is brought out with the falling -edge. - -``OutputEnable`` (Tri-State) is high-active. It is automatically inverted if -necessary. Output is disabled after power-up. - -Both data ``DataIn_high/low`` are synchronously outputted to the on-chip logic -with the rising edge of ``Clock``. ``DataIn_high`` is the value at the ``Pad`` -sampled with the same rising edge. ``DataIn_low`` is the value sampled with -the falling edge directly before this rising edge. Thus sampling starts with -the falling edge of the clock as depicted in the following waveform. - -.. code-block:: none - - __ ____ ____ __ - Clock |____| |____| |____| - Pad < 0 >< 1 >< 2 >< 3 >< 4 >< 5 > - DataIn_low ... >< 0 >< 2 >< - DataIn_high ... >< 1 >< 3 >< - - < i > is the value of the i-th data bit on the line. - -``Pad`` must be connected to a PAD because FPGAs only have these registers in -IOBs. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/io/ddrio/ddrio_inout.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 70-88 - -Source file: `io/ddrio/ddrio_inout.vhdl `_ - - - diff --git a/docs/PoC/io/ddrio/ddrio_out.rst b/docs/PoC/io/ddrio/ddrio_out.rst deleted file mode 100644 index 43c9fab6..00000000 --- a/docs/PoC/io/ddrio/ddrio_out.rst +++ /dev/null @@ -1,35 +0,0 @@ - -ddrio_out -######### - -Instantiates chip-specific :abbr:`DDR (Double Data Rate)` output registers. - -Both data ``DataOut_high/low`` as well as ``OutputEnable`` are sampled with -the ``rising_edge(Clock)`` from the on-chip logic. ``DataOut_high`` is brought -out with this rising edge. ``DataOut_low`` is brought out with the falling -edge. - -``OutputEnable`` (Tri-State) is high-active. It is automatically inverted if -necessary. If an output enable is not required, you may save some logic by -setting ``NO_OUTPUT_ENABLE = true``. - -If ``NO_OUTPUT_ENABLE = false`` then output is disabled after power-up. -If ``NO_OUTPUT_ENABLE = true`` then output after power-up equals ``INIT_VALUE``. - -``Pad`` must be connected to a PAD because FPGAs only have these registers in -IOBs. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/io/ddrio/ddrio_out.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 57-71 - -Source file: `io/ddrio/ddrio_out.vhdl `_ - - - diff --git a/docs/PoC/io/ddrio/index.rst b/docs/PoC/io/ddrio/index.rst deleted file mode 100644 index 0be35a42..00000000 --- a/docs/PoC/io/ddrio/index.rst +++ /dev/null @@ -1,19 +0,0 @@ - -ddrio -===== - -These are :abbr:`DDR-I/O (Double Data Rate - Input/Output)` entities.... - -**Entities** - - * :doc:`PoC.io.ddrio.in ` - * :doc:`PoC.io.ddrio.inout ` - * :doc:`PoC.io.ddrio.out ` - - -.. toctree:: - :hidden: - - ddrio_in - ddrio_inout - ddrio_out diff --git a/docs/PoC/io/iic/iic_BusController.rst b/docs/PoC/io/iic/iic_BusController.rst deleted file mode 100644 index 139e99e1..00000000 --- a/docs/PoC/io/iic/iic_BusController.rst +++ /dev/null @@ -1,23 +0,0 @@ - -iic_BusController -################# - -The I2C BusController transmitts bits over the I2C bus (SerialClock - SCL, -SerialData - SDA) and also receives them. To send/receive words over the -I2C bus, use the I2C Controller, which utilizes this controller. This -controller is compatible to the System Management Bus (SMBus). - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/io/iic/iic_BusController.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 47-70 - -Source file: `io/iic/iic_BusController.vhdl `_ - - - diff --git a/docs/PoC/io/iic/iic_Controller.rst b/docs/PoC/io/iic/iic_Controller.rst deleted file mode 100644 index 25ced5c3..00000000 --- a/docs/PoC/io/iic/iic_Controller.rst +++ /dev/null @@ -1,23 +0,0 @@ - -iic_Controller -############## - -The I2C Controller transmitts words over the I2C bus (SerialClock - SCL, -SerialData - SDA) and also receives them. This controller utilizes the -I2C BusController to send/receive bits over the I2C bus. This controller -is compatible to the System Management Bus (SMBus). - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/io/iic/iic_Controller.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 47-87 - -Source file: `io/iic/iic_Controller.vhdl `_ - - - diff --git a/docs/PoC/io/iic/iic_Controller_SFF8431.rst b/docs/PoC/io/iic/iic_Controller_SFF8431.rst deleted file mode 100644 index 87280961..00000000 --- a/docs/PoC/io/iic/iic_Controller_SFF8431.rst +++ /dev/null @@ -1,18 +0,0 @@ - -IICController_SFF8431 -##################### - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/io/iic/iic_Controller_SFF8431.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 15-49 - -Source file: `io/iic/iic_Controller_SFF8431.vhdl `_ - - - diff --git a/docs/PoC/io/iic/iic_Switch_PCA9548A.rst b/docs/PoC/io/iic/iic_Switch_PCA9548A.rst deleted file mode 100644 index b4da4a8b..00000000 --- a/docs/PoC/io/iic/iic_Switch_PCA9548A.rst +++ /dev/null @@ -1,20 +0,0 @@ - -iic_Switch_PCA9548A -################### - -.. TODO:: No documentation available. TODO - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/io/iic/iic_Switch_PCA9548A.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 42-90 - -Source file: `io/iic/iic_Switch_PCA9548A.vhdl `_ - - - diff --git a/docs/PoC/io/iic/index.rst b/docs/PoC/io/iic/index.rst deleted file mode 100644 index 04460025..00000000 --- a/docs/PoC/io/iic/index.rst +++ /dev/null @@ -1,11 +0,0 @@ - -iic -===== - -These are I2C entities.... - -.. toctree:: - - iic_BusController - iic_Controller - iic_Switch_PCA9548A diff --git a/docs/PoC/io/io.pkg.rst b/docs/PoC/io/io.pkg.rst deleted file mode 100644 index 00a8c8a5..00000000 --- a/docs/PoC/io/io.pkg.rst +++ /dev/null @@ -1,7 +0,0 @@ - -Package -======== - -This package holds all component declarations for this namespace. - -Source file: `io/io.pkg.vhdl `_ diff --git a/docs/PoC/io/io_7SegmentMux_BCD.rst b/docs/PoC/io/io_7SegmentMux_BCD.rst deleted file mode 100644 index be066af6..00000000 --- a/docs/PoC/io/io_7SegmentMux_BCD.rst +++ /dev/null @@ -1,23 +0,0 @@ - -io_7SegmentMux_BCD -################## - -This module is a 7 segment display controller that uses time multiplexing -to control a common anode for each digit in the display. The shown characters -are BCD encoded. A dot per digit is optional. A minus sign for negative -numbers is supported. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/io/io_7SegmentMux_BCD.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 45-60 - -Source file: `io/io_7SegmentMux_BCD.vhdl `_ - - - diff --git a/docs/PoC/io/io_7SegmentMux_HEX.rst b/docs/PoC/io/io_7SegmentMux_HEX.rst deleted file mode 100644 index 4926b941..00000000 --- a/docs/PoC/io/io_7SegmentMux_HEX.rst +++ /dev/null @@ -1,22 +0,0 @@ - -io_7SegmentMux_HEX -################## - -This module is a 7 segment display controller that uses time multiplexing -to control a common anode for each digit in the display. The shown characters -are HEX encoded. A dot per digit is optional. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/io/io_7SegmentMux_HEX.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 45-60 - -Source file: `io/io_7SegmentMux_HEX.vhdl `_ - - - diff --git a/docs/PoC/io/io_Debounce.rst b/docs/PoC/io/io_Debounce.rst deleted file mode 100644 index 4e0c4b86..00000000 --- a/docs/PoC/io/io_Debounce.rst +++ /dev/null @@ -1,31 +0,0 @@ - -io_Debounce -########### - -This module debounces several input pins preventing input changes -following a previous one within the configured ``BOUNCE_TIME`` to pass. -Internally, the forwarded state is locked for, at least, this ``BOUNCE_TIME``. -As the backing timer is restarted on every input fluctuation, the next -passing input update must have seen a stabilized input. - -The parameter ``COMMON_LOCK`` uses a single internal timer for all processed -inputs. Thus, all inputs must stabilize before any one may pass changed. -This option is usually fully acceptable for user inputs such as push buttons. - -The parameter ``ADD_INPUT_SYNCHRONIZERS`` triggers the optional instantiation -of a two-FF input synchronizer on each input bit. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/io/io_Debounce.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 52-67 - -Source file: `io/io_Debounce.vhdl `_ - - - diff --git a/docs/PoC/io/io_FrequencyCounter.rst b/docs/PoC/io/io_FrequencyCounter.rst deleted file mode 100644 index 80e9bc94..00000000 --- a/docs/PoC/io/io_FrequencyCounter.rst +++ /dev/null @@ -1,20 +0,0 @@ - -io_FrequencyCounter -################### - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/io/io_FrequencyCounter.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 40-52 - -Source file: `io/io_FrequencyCounter.vhdl `_ - - - diff --git a/docs/PoC/io/io_GlitchFilter.rst b/docs/PoC/io/io_GlitchFilter.rst deleted file mode 100644 index 48c4f1bf..00000000 --- a/docs/PoC/io/io_GlitchFilter.rst +++ /dev/null @@ -1,21 +0,0 @@ - -io_GlitchFilter -############### - -This module filters glitches on a wire. The high and low spike suppression -cycle counts can be configured. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/io/io_GlitchFilter.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 41-51 - -Source file: `io/io_GlitchFilter.vhdl `_ - - - diff --git a/docs/PoC/io/io_KeyPadScanner.rst b/docs/PoC/io/io_KeyPadScanner.rst deleted file mode 100644 index b1b06f23..00000000 --- a/docs/PoC/io/io_KeyPadScanner.rst +++ /dev/null @@ -1,24 +0,0 @@ - -io_KeyPadScanner -################ - -This module drives a one-hot encoded column vector to read back a rows -vector. By scanning column-by-column it's possible to extract the current -button state of the whole keypad. The scanner uses high-active logic. The -keypad size and scan frequency can be configured. The outputed signal -matrix is not debounced. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/io/io_KeyPadScanner.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 46-63 - -Source file: `io/io_KeyPadScanner.vhdl `_ - - - diff --git a/docs/PoC/io/io_PulseWidthModulation.rst b/docs/PoC/io/io_PulseWidthModulation.rst deleted file mode 100644 index f130f1dc..00000000 --- a/docs/PoC/io/io_PulseWidthModulation.rst +++ /dev/null @@ -1,21 +0,0 @@ - -io_PulseWidthModulation -####################### - -This module generates a pulse width modulated signal, that can be configured -in frequency (``PWM_FREQ``) and modulation granularity (``PWM_RESOLUTION``). - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/io/io_PulseWidthModulation.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 41-53 - -Source file: `io/io_PulseWidthModulation.vhdl `_ - - - diff --git a/docs/PoC/io/io_TimingCounter.rst b/docs/PoC/io/io_TimingCounter.rst deleted file mode 100644 index 02862613..00000000 --- a/docs/PoC/io/io_TimingCounter.rst +++ /dev/null @@ -1,23 +0,0 @@ - -io_TimingCounter -################ - -This down-counter can be configured with a ``TIMING_TABLE`` (a ROM), from which -the initial counter value is loaded. The table index can be selected by -``Slot``. ``Timeout`` is a registered output. Up to 16 values fit into one ROM -consisting of ``log2ceilnz(imax(TIMING_TABLE)) + 1`` 6-input LUTs. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/io/io_TimingCounter.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 43-54 - -Source file: `io/io_TimingCounter.vhdl `_ - - - diff --git a/docs/PoC/io/jtag/index.rst b/docs/PoC/io/jtag/index.rst deleted file mode 100644 index 0ed83f3e..00000000 --- a/docs/PoC/io/jtag/index.rst +++ /dev/null @@ -1,8 +0,0 @@ - -jtag -==== - -These are JTAG entities.... - -.. toctree:: - diff --git a/docs/PoC/io/lcd/index.rst b/docs/PoC/io/lcd/index.rst deleted file mode 100644 index 144729aa..00000000 --- a/docs/PoC/io/lcd/index.rst +++ /dev/null @@ -1,12 +0,0 @@ - -lcd -=== - -These are LCD entities.... - -.. toctree:: - - lcd_LCDBuffer - lcd_LCDBusController - lcd_LCDController_KS0066U - lcd_LCDSynchronizer diff --git a/docs/PoC/io/lcd/lcd_LCDBuffer.rst b/docs/PoC/io/lcd/lcd_LCDBuffer.rst deleted file mode 100644 index da24ae53..00000000 --- a/docs/PoC/io/lcd/lcd_LCDBuffer.rst +++ /dev/null @@ -1,20 +0,0 @@ - -lcd_LCDBuffer -############# - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/io/lcd/lcd_LCDBuffer.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 42-58 - -Source file: `io/lcd/lcd_LCDBuffer.vhdl `_ - - - diff --git a/docs/PoC/io/lcd/lcd_LCDBusController.rst b/docs/PoC/io/lcd/lcd_LCDBusController.rst deleted file mode 100644 index 5512701f..00000000 --- a/docs/PoC/io/lcd/lcd_LCDBusController.rst +++ /dev/null @@ -1,20 +0,0 @@ - -lcd_LCDBusController -#################### - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/io/lcd/lcd_LCDBusController.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 43-67 - -Source file: `io/lcd/lcd_LCDBusController.vhdl `_ - - - diff --git a/docs/PoC/io/lcd/lcd_LCDController_KS0066U.rst b/docs/PoC/io/lcd/lcd_LCDController_KS0066U.rst deleted file mode 100644 index 9ca3f647..00000000 --- a/docs/PoC/io/lcd/lcd_LCDController_KS0066U.rst +++ /dev/null @@ -1,20 +0,0 @@ - -lcd_LCDController_KS0066U -######################### - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/io/lcd/lcd_LCDController_KS0066U.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 42-64 - -Source file: `io/lcd/lcd_LCDController_KS0066U.vhdl `_ - - - diff --git a/docs/PoC/io/lcd/lcd_LCDSynchronizer.rst b/docs/PoC/io/lcd/lcd_LCDSynchronizer.rst deleted file mode 100644 index 1ad67e80..00000000 --- a/docs/PoC/io/lcd/lcd_LCDSynchronizer.rst +++ /dev/null @@ -1,20 +0,0 @@ - -lcd_LCDSynchronizer -################### - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/io/lcd/lcd_LCDSynchronizer.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 42-64 - -Source file: `io/lcd/lcd_LCDSynchronizer.vhdl `_ - - - diff --git a/docs/PoC/io/lcd/lcd_dotmatrix.rst b/docs/PoC/io/lcd/lcd_dotmatrix.rst deleted file mode 100644 index fe397947..00000000 --- a/docs/PoC/io/lcd/lcd_dotmatrix.rst +++ /dev/null @@ -1,20 +0,0 @@ - -lcd_dotmatrix -############# - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/io/lcd/lcd_dotmatrix.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 36-67 - -Source file: `io/lcd/lcd_dotmatrix.vhdl `_ - - - diff --git a/docs/PoC/io/mdio/index.rst b/docs/PoC/io/mdio/index.rst deleted file mode 100644 index 67b40b87..00000000 --- a/docs/PoC/io/mdio/index.rst +++ /dev/null @@ -1,11 +0,0 @@ - -mdio -==== - -These are MDIO entities.... - -.. toctree:: - - mdio_BusController - mdio_Controller - mdio_IIC_Adapter diff --git a/docs/PoC/io/mdio/mdio_Controller.rst b/docs/PoC/io/mdio/mdio_Controller.rst deleted file mode 100644 index f06789d2..00000000 --- a/docs/PoC/io/mdio/mdio_Controller.rst +++ /dev/null @@ -1,20 +0,0 @@ - -mdio_Controller -############### - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/io/mdio/mdio_Controller.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 44-73 - -Source file: `io/mdio/mdio_Controller.vhdl `_ - - - diff --git a/docs/PoC/io/mdio/mdio_IIC_Adapter.rst b/docs/PoC/io/mdio/mdio_IIC_Adapter.rst deleted file mode 100644 index 65373fe9..00000000 --- a/docs/PoC/io/mdio/mdio_IIC_Adapter.rst +++ /dev/null @@ -1,20 +0,0 @@ - -mdio_IIC_Adapter -################ - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/io/mdio/mdio_IIC_Adapter.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 44-80 - -Source file: `io/mdio/mdio_IIC_Adapter.vhdl `_ - - - diff --git a/docs/PoC/io/ow/index.rst b/docs/PoC/io/ow/index.rst deleted file mode 100644 index 436fb3f4..00000000 --- a/docs/PoC/io/ow/index.rst +++ /dev/null @@ -1,10 +0,0 @@ - -ow -== - -These are OneWire entities.... - -.. toctree:: - - ow_BusController - ow_Controller diff --git a/docs/PoC/io/pio/index.rst b/docs/PoC/io/pio/index.rst deleted file mode 100644 index 69dd0a40..00000000 --- a/docs/PoC/io/pio/index.rst +++ /dev/null @@ -1,12 +0,0 @@ - -pio -### - -These are Pmod entities.... - -.. toctree:: - - pio_in - pio_out - pio_fifo_in - pio_fifo_out diff --git a/docs/PoC/io/pio/pio_fifo_in.rst b/docs/PoC/io/pio/pio_fifo_in.rst deleted file mode 100644 index f09a6af0..00000000 --- a/docs/PoC/io/pio/pio_fifo_in.rst +++ /dev/null @@ -1,19 +0,0 @@ - -pio_fifo_in -########### - - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/io/pio/pio_fifo_in.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 38-55 - -Source file: `io/pio/pio_fifo_in.vhdl `_ - - - diff --git a/docs/PoC/io/pio/pio_fifo_out.rst b/docs/PoC/io/pio/pio_fifo_out.rst deleted file mode 100644 index 49fffc17..00000000 --- a/docs/PoC/io/pio/pio_fifo_out.rst +++ /dev/null @@ -1,19 +0,0 @@ - -pio_fifo_out -############ - - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/io/pio/pio_fifo_out.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 38-55 - -Source file: `io/pio/pio_fifo_out.vhdl `_ - - - diff --git a/docs/PoC/io/pio/pio_in.rst b/docs/PoC/io/pio/pio_in.rst deleted file mode 100644 index e7eccec2..00000000 --- a/docs/PoC/io/pio/pio_in.rst +++ /dev/null @@ -1,19 +0,0 @@ - -pio_in -###### - - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/io/pio/pio_in.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 40-55 - -Source file: `io/pio/pio_in.vhdl `_ - - - diff --git a/docs/PoC/io/pio/pio_out.rst b/docs/PoC/io/pio/pio_out.rst deleted file mode 100644 index 2e36dd20..00000000 --- a/docs/PoC/io/pio/pio_out.rst +++ /dev/null @@ -1,19 +0,0 @@ - -pio_out -####### - - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/io/pio/pio_out.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 40-55 - -Source file: `io/pio/pio_out.vhdl `_ - - - diff --git a/docs/PoC/io/pmod/index.rst b/docs/PoC/io/pmod/index.rst deleted file mode 100644 index adfaf17a..00000000 --- a/docs/PoC/io/pmod/index.rst +++ /dev/null @@ -1,19 +0,0 @@ - -pmod -#### - -These are Pmod entities.... - -**Entities** - - * :doc:`PoC.io.pmod.KYPD ` - * :doc:`PoC.io.pmod.SSD ` - * :doc:`PoC.io.pmod.USBUART ` - - -.. toctree:: - :hidden: - - pmod_KYPD - pmod_SSD - pmod_USBUART diff --git a/docs/PoC/io/pmod/pmod_KYPD.rst b/docs/PoC/io/pmod/pmod_KYPD.rst deleted file mode 100644 index b160a86b..00000000 --- a/docs/PoC/io/pmod/pmod_KYPD.rst +++ /dev/null @@ -1,25 +0,0 @@ - -pmod_KYPD -######### - -This module drives a 4-bit one-cold encoded column vector to read back a -4-bit rows vector. By scanning column-by-column it's possible to extract -the current button state of the whole keypad. This wrapper converts the -high-active signals from :doc:`PoC.io.KeypadScanner <../io_KeyPadScanner>` -to low-active signals for the pmod. An additional debounce circuit filters -the button signals. The scan frequency and bounce time can be configured. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/io/pmod/pmod_KYPD.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 46-61 - -Source file: `io/pmod/pmod_KYPD.vhdl `_ - - - diff --git a/docs/PoC/io/pmod/pmod_SSD.rst b/docs/PoC/io/pmod/pmod_SSD.rst deleted file mode 100644 index 113c74ef..00000000 --- a/docs/PoC/io/pmod/pmod_SSD.rst +++ /dev/null @@ -1,33 +0,0 @@ - -pmod_SSD -######## - -This module drives a dual-digit 7-segment display (Pmod_SSD). The module -expects two binary encoded 4-bit ``Digit`` signals and drives a 2x6 bit -Pmod connector (7 anode bits, 1 cathode bit). - --- code-block:. none - - Segment Pos./ Index - AAA | 000 - F B | 5 1 - F B | 5 1 - GGG | 666 - E C | 4 2 - E C | 4 2 - DDD DOT | 333 7 - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/io/pmod/pmod_SSD.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 56-69 - -Source file: `io/pmod/pmod_SSD.vhdl `_ - - - diff --git a/docs/PoC/io/pmod/pmod_USBUART.rst b/docs/PoC/io/pmod/pmod_USBUART.rst deleted file mode 100644 index a5a1c9b4..00000000 --- a/docs/PoC/io/pmod/pmod_USBUART.rst +++ /dev/null @@ -1,23 +0,0 @@ - -pmod_USBUART -############ - -This module abstracts a FTDI FT232R USB-UART bridge by instantiating a -:doc:`PoC.io.uart.fifo <../uart/uart_fifo>`. The FT232R supports up to -3 MBaud. A synchronous FIFO interface with a 32 words buffer is provided. -Hardware flow control (RTS_CTS) is enabled. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/io/pmod/pmod_USBUART.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 43-65 - -Source file: `io/pmod/pmod_USBUART.vhdl `_ - - - diff --git a/docs/PoC/io/ps2/index.rst b/docs/PoC/io/ps2/index.rst deleted file mode 100644 index 3638c2f7..00000000 --- a/docs/PoC/io/ps2/index.rst +++ /dev/null @@ -1,8 +0,0 @@ - -ps2 -=== - -These are PS/2 entities.... - -.. toctree:: - diff --git a/docs/PoC/io/uart/index.rst b/docs/PoC/io/uart/index.rst deleted file mode 100644 index f356581c..00000000 --- a/docs/PoC/io/uart/index.rst +++ /dev/null @@ -1,21 +0,0 @@ - -uart -==== - -These are :abbr:`UART (Universal Asynchronous Receiver Transmitter)` entities.... - -**Entities** - - * :doc:`PoC.io.uart.bclk ` - * :doc:`PoC.io.uart.rx ` - * :doc:`PoC.io.uart.tx ` - * :doc:`PoC.io.uart.fifo ` - - -.. toctree:: - :hidden: - - uart_bclk - uart_rx - uart_tx - uart_fifo diff --git a/docs/PoC/io/uart/uart_bclk.rst b/docs/PoC/io/uart/uart_bclk.rst deleted file mode 100644 index b6fc0837..00000000 --- a/docs/PoC/io/uart/uart_bclk.rst +++ /dev/null @@ -1,26 +0,0 @@ - -uart_bclk -######### - -.. TODO:: No documentation available. - -old comments: - :abbr:`UART (Universal Asynchronous Receiver Transmitter)` BAUD rate generator - bclk_r = bit clock is rising - bclk_x8_r = bit clock times 8 is rising - - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/io/uart/uart_bclk.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 50-61 - -Source file: `io/uart/uart_bclk.vhdl `_ - - - diff --git a/docs/PoC/io/uart/uart_fifo.rst b/docs/PoC/io/uart/uart_fifo.rst deleted file mode 100644 index 283e63bd..00000000 --- a/docs/PoC/io/uart/uart_fifo.rst +++ /dev/null @@ -1,28 +0,0 @@ - -uart_fifo -######### - -Small :abbr:`FIFO (first-in, first-out)` s are included in this module, if -larger or asynchronous transmit / receive FIFOs are required, then they must -be connected externally. - -old comments: - :abbr:`UART (Universal Asynchronous Receiver Transmitter)` BAUD rate generator - bclk = bit clock is rising - bclk_x8 = bit clock times 8 is rising - - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/io/uart/uart_fifo.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 52-94 - -Source file: `io/uart/uart_fifo.vhdl `_ - - - diff --git a/docs/PoC/io/uart/uart_ft245.rst b/docs/PoC/io/uart/uart_ft245.rst deleted file mode 100644 index 8152cb77..00000000 --- a/docs/PoC/io/uart/uart_ft245.rst +++ /dev/null @@ -1,20 +0,0 @@ - -uart_ft245 -########## - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/io/uart/uart_ft245.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 37-63 - -Source file: `io/uart/uart_ft245.vhdl `_ - - - diff --git a/docs/PoC/io/uart/uart_rx.rst b/docs/PoC/io/uart/uart_rx.rst deleted file mode 100644 index 85f74718..00000000 --- a/docs/PoC/io/uart/uart_rx.rst +++ /dev/null @@ -1,21 +0,0 @@ - -uart_rx -####### - -:abbr:`UART (Universal Asynchronous Receiver Transmitter)` Receiver: -1 Start + 8 Data + 1 Stop - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/io/uart/uart_rx.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 39-56 - -Source file: `io/uart/uart_rx.vhdl `_ - - - diff --git a/docs/PoC/io/uart/uart_tx.rst b/docs/PoC/io/uart/uart_tx.rst deleted file mode 100644 index b4c63f15..00000000 --- a/docs/PoC/io/uart/uart_tx.rst +++ /dev/null @@ -1,21 +0,0 @@ - -uart_tx -####### - -:abbr:`UART (Universal Asynchronous Receiver Transmitter)` Transmitter: -1 Start + 8 Data + 1 Stop - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/io/uart/uart_tx.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 35-50 - -Source file: `io/uart/uart_tx.vhdl `_ - - - diff --git a/docs/PoC/io/vga/index.rst b/docs/PoC/io/vga/index.rst deleted file mode 100644 index 9cdebbc4..00000000 --- a/docs/PoC/io/vga/index.rst +++ /dev/null @@ -1,11 +0,0 @@ - -vga -=== - -These are VGA entities.... - -.. toctree:: - - vga_phy - vga_phy_ch7301c - vga_timing diff --git a/docs/PoC/io/vga/vga_phy.rst b/docs/PoC/io/vga/vga_phy.rst deleted file mode 100644 index 8ed5ade8..00000000 --- a/docs/PoC/io/vga/vga_phy.rst +++ /dev/null @@ -1,24 +0,0 @@ - -vga_phy -####### - - The clock frequency must be the same as used for the timing module. - - The number of color-bits per pixel can be configured with the generic - "COLOR_BITS". The format of the pixel data is defined the picture generator - in use. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/io/vga/vga_phy.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 43-55 - -Source file: `io/vga/vga_phy.vhdl `_ - - - diff --git a/docs/PoC/io/vga/vga_phy_ch7301c.rst b/docs/PoC/io/vga/vga_phy_ch7301c.rst deleted file mode 100644 index b8889bf5..00000000 --- a/docs/PoC/io/vga/vga_phy_ch7301c.rst +++ /dev/null @@ -1,44 +0,0 @@ - -vga_phy_ch7301c -############### - - The clock frequency must be the same as used for the timing module, - e.g., 25 MHZ for VGA 640x480. A phase-shifted clock must be provided: - - clk0 : 0 degrees - - clk90 : 90 degrees - - pixel_data(23 downto 16) : red - pixel_data(15 downto 8) : green - pixel_data( 7 downto 0) : blue - - The "reset_b"-pin must be driven by other logic (such as the reset button). - - The IIC_interface is not part of this modules, as an IIC-master controls - several slaves. The following registers must be set, see - tests/ml505/vga_test_ml505.vhdl for an example. - - Register Value Description - ----------------------------------- - 0x49 PM 0xC0 Enable DVI, RGB bypass off - or 0xD0 Enable DVI, RGB bypass on - 0x33 TPCP 0x08 if clk_freq <= 65 MHz else 0x06 - 0x34 TPD 0x16 if clk_freq <= 65 MHz else 0x26 - 0x36 TPF 0x60 if clk_freq <= 65 MHz else 0xA0 - 0x1F IDF 0x80 when using SMT (VS0, HS0) - or 0x90 when using CVT (VS1, HS0) - 0x21 DC 0x09 Enable DAC if RGB bypass is on - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/io/vga/vga_phy_ch7301c.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 63-76 - -Source file: `io/vga/vga_phy_ch7301c.vhdl `_ - - - diff --git a/docs/PoC/io/vga/vga_timing.rst b/docs/PoC/io/vga/vga_timing.rst deleted file mode 100644 index 445402bf..00000000 --- a/docs/PoC/io/vga/vga_timing.rst +++ /dev/null @@ -1,59 +0,0 @@ - -vga_timing -########## - - Configuration: - -------------- - MODE = 0: VGA mode with 640x480 pixels, 60 Hz, frequency(clk) ~ 25 MHz - MODE = 1: HD 720p with 1280x720 pixels, 60 Hz, frequency(clk) = 74,5 MHz - MODE = 2: HD 1080p with 1920x1080 pixels, 60 Hz, frequency(clk) = 138,5 MHz - - MODE = 2 uses reduced blanking => only suitable for LCDs. - - For MODE = 0, CVT can be configured: - - CVT = false: Use Safe Mode Timing (SMT). - The legacy fall-back mode supported by CRTs as well as LCDs. - HSync: low-active. VSync: low-active. - frequency(clk) = 25.175 MHz. (25 MHz works => 31 kHz / 59 Hz) - - CVT = true: The "new" Coordinated Video Timing (since 2003). - The CVT supports some new features, such as reduced blanking (for LCDs) or - aspect ratio encoding. See the web for more details. - Standard CRT-based timing (CVT-GTF) has been implemented for best - compatibility: - HSync: low-active. VSync: high-active. - frequency(clk) = 23.75 MHz. (25 MHz works => 31 kHz / 62 Hz) - - Usage: - ------ - The frequency of 'clk' must be equal to the pixel clock frequency of the - selected video mode, see also above. - - When using analog output, the VGA color signals must be blanked, during - horizontal and vertical beam return. This could be achieved by - combinatorial "anding" the color value with "beam_on" (part of "phy_ctrl") - inside the PHY. - - When using digital output (DVI), then "beam_on" is equal to "DE" - (Data Enable) of the DVI transmitter. - - xvalid and yvalid show if xpos respectivly ypos are in a valid range. - beam_on is '1' iff both xvalid and yvalid = '1'. - - xpos and ypos also show the pixel location during blanking. - This might be useful in some applications. But be careful, that the ranges - differ between SMT and CVT. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/io/vga/vga_timing.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 80-96 - -Source file: `io/vga/vga_timing.vhdl `_ - - - diff --git a/docs/PoC/mem/index.rst b/docs/PoC/mem/index.rst deleted file mode 100644 index 7ac07d59..00000000 --- a/docs/PoC/mem/index.rst +++ /dev/null @@ -1,35 +0,0 @@ - -mem -=== - -The namespace ``PoC.mem`` offers different on-chip and off-chip memory and memory-controller -implementations. - - -**Sub-Namespaces** - - * :doc:`PoC.mem.ddr3 ` - DDR3 memory controllers - * :doc:`PoC.mem.is61lv ` - ISSI - IS61LV SRAM controller - * :doc:`PoC.mem.is61nlp ` - ISSI - IS61NLP SRAM controller - * :doc:`PoC.mem.lut ` - Lookup-Table (LUT) implementations - * :doc:`PoC.mem.ocram ` - On-Chip RAM abstraction layer - * :doc:`PoC.mem.ocrom ` - On-Chip ROM abstraction layer - * :doc:`PoC.mem.sdram ` - SDRAM controllers - -**Package** - -:doc:`PoC.mem ` - - -.. toctree:: - :hidden: - - ddr3/index - is61lv/index - is61nlp/index - lut/index - ocram/index - ocrom/index - sdram/index - - mem.pkg diff --git a/docs/PoC/mem/is61lv/index.rst b/docs/PoC/mem/is61lv/index.rst deleted file mode 100644 index cda93f51..00000000 --- a/docs/PoC/mem/is61lv/index.rst +++ /dev/null @@ -1,8 +0,0 @@ - -is61lv -====== - -These are IS61LV entities.... - -.. toctree:: - diff --git a/docs/PoC/mem/is61nlp/index.rst b/docs/PoC/mem/is61nlp/index.rst deleted file mode 100644 index 5a697cca..00000000 --- a/docs/PoC/mem/is61nlp/index.rst +++ /dev/null @@ -1,8 +0,0 @@ - -is61nlp -======== - -These are IS61NLP entities.... - -.. toctree:: - diff --git a/docs/PoC/mem/lut/index.rst b/docs/PoC/mem/lut/index.rst deleted file mode 100644 index 0bd93772..00000000 --- a/docs/PoC/mem/lut/index.rst +++ /dev/null @@ -1,9 +0,0 @@ - -lut -=== - -These are Lookup-Table entities.... - -.. toctree:: - - lut_Sine diff --git a/docs/PoC/mem/lut/lut_Sine.rst b/docs/PoC/mem/lut/lut_Sine.rst deleted file mode 100644 index ea7d1b82..00000000 --- a/docs/PoC/mem/lut/lut_Sine.rst +++ /dev/null @@ -1,20 +0,0 @@ - -lut_Sine -######## - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/mem/lut/lut_Sine.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 41-54 - -Source file: `mem/lut/lut_Sine.vhdl `_ - - - diff --git a/docs/PoC/mem/mem.pkg.rst b/docs/PoC/mem/mem.pkg.rst deleted file mode 100644 index cb5820d1..00000000 --- a/docs/PoC/mem/mem.pkg.rst +++ /dev/null @@ -1,7 +0,0 @@ - -Package -======== - -This package holds all component declarations for this namespace. - -Source file: `mem/mem.pkg.vhdl `_ diff --git a/docs/PoC/mem/ocram/index.rst b/docs/PoC/mem/ocram/index.rst deleted file mode 100644 index a824c7ed..00000000 --- a/docs/PoC/mem/ocram/index.rst +++ /dev/null @@ -1,33 +0,0 @@ - -ocram -===== - -These are On-Chip RAM (OCRAM) entities... - -**Package** - -The package PoC.mem.ocram holds all component declarations for this namespace. - -.. code-block:: VHDL - - library PoC; - use PoC.ocram.all; - - -**Entities** - - * :doc:`PoC.mem.ocram.sp ` - An on-chip RAM with a single port interface. - * :doc:`PoC.mem.ocram.sdp ` - An on-chip RAM with a simple dual port interface. - * :doc:`PoC.mem.ocram.tdp ` - An on-chip RAM with a true dual port interface. - -**Deprecated Entities** - - * :doc:`PoC.mem.ocram.esdp ` - An on-chip RAM with an extended simple dual port interface. - -.. toctree:: - :hidden: - - ocram_sp - ocram_esdp - ocram_sdp - ocram_tdp diff --git a/docs/PoC/mem/ocram/ocram_sdp.rst b/docs/PoC/mem/ocram/ocram_sdp.rst deleted file mode 100644 index eec1100e..00000000 --- a/docs/PoC/mem/ocram/ocram_sdp.rst +++ /dev/null @@ -1,40 +0,0 @@ - -ocram_sdp -######### - -Inferring / instantiating simple dual-port memory, with: - -* dual clock, clock enable, -* 1 read port plus 1 write port. - -The generalized behavior across Altera and Xilinx FPGAs since -Stratix/Cyclone and Spartan-3/Virtex-5, respectively, is as follows: - -Mixed-Port Read-During-Write - When reading at the write address, the read value will be unknown which is - aka. "don't care behavior". This applies to all reads (at the same - address) which are issued during the write-cycle time, which starts at the - rising-edge of the write clock and (in the worst case) extends until the - next rising-edge of the write clock. - -.. WARNING:: - The simulated behavior on RT-level is too optimistic. The - mixed-port read-during-write behavior is only valid if the read and write - clock are in phase. Otherwise, simulation will always show known data. - -.. TODO:: Implement correct behavior for RT-level simulation. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/mem/ocram/ocram_sdp.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 65-82 - -Source file: `mem/ocram/ocram_sdp.vhdl `_ - - - diff --git a/docs/PoC/mem/ocram/ocram_sp.rst b/docs/PoC/mem/ocram/ocram_sp.rst deleted file mode 100644 index 131c4b5f..00000000 --- a/docs/PoC/mem/ocram/ocram_sp.rst +++ /dev/null @@ -1,43 +0,0 @@ - -ocram_sp -######## - -Inferring / instantiating single port memory, with: - -* single clock, clock enable, -* 1 read/write port. - -Command Truth Table: - -== == ================ -ce we Command -== == ================ -0 X No operation -1 0 Read from memory -1 1 Write to memory -== == ================ - -Both reading and writing are synchronous to the rising-edge of the clock. -Thus, when reading, the memory data will be outputted after the -clock edge, i.e, in the following clock cycle. - -When writing data, the read output will output the new data (in the -following clock cycle) which is aka. "write-first behavior". This behavior -also applies to Altera M20K memory blocks as described in the Altera: -"Stratix 5 Device Handbook" (S5-5V1). The documentation in the Altera: -"Embedded Memory User Guide" (UG-01068) is wrong. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/mem/ocram/ocram_sp.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 68-82 - -Source file: `mem/ocram/ocram_sp.vhdl `_ - - - diff --git a/docs/PoC/mem/ocram/ocram_tdp.rst b/docs/PoC/mem/ocram/ocram_tdp.rst deleted file mode 100644 index 8690b8fc..00000000 --- a/docs/PoC/mem/ocram/ocram_tdp.rst +++ /dev/null @@ -1,59 +0,0 @@ - -ocram_tdp -######### - -Inferring / instantiating true dual-port memory, with: - -* dual clock, clock enable, -* 2 read/write ports. - -Command truth table for port 1, same applies to port 2: - -=== === ================ -ce1 we1 Command -=== === ================ -0 X No operation -1 0 Read from memory -1 1 Write to memory -=== === ================ - -The generalized behavior across Altera and Xilinx FPGAs since -Stratix/Cyclone and Spartan-3/Virtex-5, respectively, is as follows: - -Same-Port Read-During-Write - When writing data through port 1, the read output of the same port - (``q1``) will output the new data (``d1``, in the following clock cycle) - which is aka. "write-first behavior". This behavior also applies to Altera - M20K memory blocks as described in the Altera: "Stratix 5 Device Handbook" - (S5-5V1). The documentation in the Altera: "Embedded Memory User Guide" - (UG-01068) is wrong. - - Same applies to port 2. - -Mixed-Port Read-During-Write - When reading at the write address, the read value will be unknown which is - aka. "don't care behavior". This applies to all reads (at the same - address) which are issued during the write-cycle time, which starts at the - rising-edge of the write clock and (in the worst case) extends - until the next rising-edge of that write clock. - -.. WARNING:: - The simulated behavior on RT-level is too optimistic. When reading - at the write address always the new data will be returned. - -.. TODO:: Implement correct behavior for RT-level simulation. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/mem/ocram/ocram_tdp.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 84-104 - -Source file: `mem/ocram/ocram_tdp.vhdl `_ - - - diff --git a/docs/PoC/mem/ocrom/index.rst b/docs/PoC/mem/ocrom/index.rst deleted file mode 100644 index 5a5b0260..00000000 --- a/docs/PoC/mem/ocrom/index.rst +++ /dev/null @@ -1,37 +0,0 @@ - -ocrom -===== - -These are On-Chip ROM (OCROM) entities.... - -# Namespace `PoC.mem.ocrom` - -The namespace `PoC.mem.ocrom` offers different on-chip ROM abstractions. - - -## Package(s) - -The package [`ocrom`][ocrom.pkg] holds all component declarations for this namespace. - -```VHDL -library PoC; -use PoC.ocrom.all; -``` - - -## Entities - - - [`ocrom_sp`][ocrom_sp] is a on-chip RAM with a single port interface. - - [`ocrom_dp`][ocrom_dp] is a on-chip RAM with a dual port interface. - - - [ocrom.pkg]: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ocrom/ocrom.pkg.vhdl - [ocrom_sp]: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ocrom/ocrom_sp.vhdl - [ocrom_dp]: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ocrom/ocrom_dp.vhdl - - - -.. toctree:: - - ocrom_sp - ocrom_dp diff --git a/docs/PoC/mem/ocrom/ocrom_dp.rst b/docs/PoC/mem/ocrom/ocrom_dp.rst deleted file mode 100644 index c889d0ec..00000000 --- a/docs/PoC/mem/ocrom/ocrom_dp.rst +++ /dev/null @@ -1,31 +0,0 @@ - -ocrom_dp -######## - -Inferring / instantiating dual-port read-only memory, with: - -* dual clock, clock enable, -* 2 read ports. - -The generalized behavior across Altera and Xilinx FPGAs since -Stratix/Cyclone and Spartan-3/Virtex-5, respectively, is as follows: - -WARNING: The simulated behavior on RT-level is not correct. - -TODO: add timing diagram -TODO: implement correct behavior for RT-level simulation - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/mem/ocrom/ocrom_dp.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 60-76 - -Source file: `mem/ocrom/ocrom_dp.vhdl `_ - - - diff --git a/docs/PoC/mem/ocrom/ocrom_sp.rst b/docs/PoC/mem/ocrom/ocrom_sp.rst deleted file mode 100644 index 6bf43afa..00000000 --- a/docs/PoC/mem/ocrom/ocrom_sp.rst +++ /dev/null @@ -1,24 +0,0 @@ - -ocrom_sp -######## - -Inferring / instantiating single-port read-only memory - -- single clock, clock enable -- 1 read port - - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/mem/ocrom/ocrom_sp.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 53-65 - -Source file: `mem/ocrom/ocrom_sp.vhdl `_ - - - diff --git a/docs/PoC/mem/sdram/index.rst b/docs/PoC/mem/sdram/index.rst deleted file mode 100644 index eee9bb1b..00000000 --- a/docs/PoC/mem/sdram/index.rst +++ /dev/null @@ -1,8 +0,0 @@ - -sdram -===== - -These are SDRAM entities.... - -.. toctree:: - diff --git a/docs/PoC/mem/sdram/sdram_ctrl_de0.rst b/docs/PoC/mem/sdram/sdram_ctrl_de0.rst deleted file mode 100644 index a0b80eda..00000000 --- a/docs/PoC/mem/sdram/sdram_ctrl_de0.rst +++ /dev/null @@ -1,39 +0,0 @@ - -sdram_ctrl_de0 -############## - -Complete controller for ISSI SDR-SDRAM for Altera DE0 Board. -SDRAM Device: IS42S16400F - -CLK_PERIOD = clock period in nano seconds. All SDRAM timings are -calculated for the device stated above. - -CL = cas latency, choose according to clock frequency. -BL = burst length. - -Command, address and write data is sampled with clk. - -Tested with: CLK_PERIOD = 7.5 (133 MHz), CL=2, BL=1. - -Read data is aligned with clk. Either process data in this clock -domain, or connect a FIFO to transfer data into another clock domain of your -choice. - -For description on 'clkout' see sdram_ctrl_phy_de0.vhdl. - -Synchronous resets are used. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/mem/sdram/sdram_ctrl_de0.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 77-109 - -Source file: `mem/sdram/sdram_ctrl_de0.vhdl `_ - - - diff --git a/docs/PoC/mem/sdram/sdram_ctrl_phy_de0.rst b/docs/PoC/mem/sdram/sdram_ctrl_phy_de0.rst deleted file mode 100644 index 49030a40..00000000 --- a/docs/PoC/mem/sdram/sdram_ctrl_phy_de0.rst +++ /dev/null @@ -1,42 +0,0 @@ - -sdram_ctrl_phy_de0 -################## - -Physical layer used by module 'sdram_ctrl_de0' - -Instantiates input and output buffer components and adjusts timing for -the Altera DE0 board. - -Command signals and write data are sampled with clk. -Read data is also aligned with clk. - -clk : Base clock for command and write data path. -rst : Reset for clk. - -Write and read enable (wren_nxt, rden_nxt) must be hold for - 1 clock cycle if BL = 1, - 2 clock cycles if BL = 2, or - 4 clock cycles if BL = 4, or - 8 clock cycles if BL = 8. -They must be first asserted with the read and write command. Proper delay is -included in this unit. - -The first word to write must be asserted with the write command. Proper -delay is included in this unit. - -Synchronous resets are used. Reset must be hold for at least two cycles. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/mem/sdram/sdram_ctrl_phy_de0.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 79-112 - -Source file: `mem/sdram/sdram_ctrl_phy_de0.vhdl `_ - - - diff --git a/docs/PoC/mem/sdram/sdram_ctrl_phy_s3esk.rst b/docs/PoC/mem/sdram/sdram_ctrl_phy_s3esk.rst deleted file mode 100644 index e5625bd2..00000000 --- a/docs/PoC/mem/sdram/sdram_ctrl_phy_s3esk.rst +++ /dev/null @@ -1,67 +0,0 @@ - -sdram_ctrl_phy_s3esk -#################### - -Physical layer used by module 'sdram_ctrl_s3esk' - -Instantiates input and output buffer components and adjusts timing for -the Spartan-3E Starter Kit Board. - -Command signals and write data are sampled with clk. - -Read data is aligned with clk_fb90_n. Either process data in this clock -domain, or connect a FIFO to transfer data into another clock domain of your -choice. This FIFO should capable of storing at least one burst (size BL/2) -+ start of next burst (size 1). - -clk : base clock for command and write data path. -clk_n : clk phase shifted by 180 degrees. -clk90 : clk phase shifted by 90 degrees. -clk90_n : clk phase shifted by 270 degrees. - -clk_fb : driven by external feedback (sd_ck_fb) of DDR-SDRAM clock - (sd_ck_p). (Actually unused, just for reference.) -clk_fb90 : clk_fb phase shifted by 90 degrees. -clk_fb90_n : clk_fb phase shifted by 270 degrees. - -rst : Reset for clk. -rst180 : Reset for clk_n. -rst90 : Reset for clk90. -rst270 : Reset for clk270. -rst_fb90 : Reset for clk_fb90. -rst_fb90_n : Reset for clk_fb90_n. - -Write and read enable (wren_nxt, rden_nxt) must be hold for - 1 clock cycle if BL = 2, - 2 clock cycles if BL = 4, or - 4 clock cycles if BL = 8. -They must be first asserted with the read and write command. Proper delay is -included in this unit. - -The first word to write must be asserted with the write command. Proper -delay is included in this unit. - -The SDRAM clock is regenerated in this module. The following timing is -chosen for minimum latency. (Should work up to 100 MHz.) - rising_edge(clk90) triggers rising_edge(sd_ck_p) - rising_edge(clk90_n) triggers falling_edge(sd_ck_p) - - -XST options: Disable equivalent register removal. - -Synchronous resets are used. Reset must be hold for at least two cycles. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/mem/sdram/sdram_ctrl_phy_s3esk.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 104-148 - -Source file: `mem/sdram/sdram_ctrl_phy_s3esk.vhdl `_ - - - diff --git a/docs/PoC/mem/sdram/sdram_ctrl_s3esk.rst b/docs/PoC/mem/sdram/sdram_ctrl_s3esk.rst deleted file mode 100644 index 4b464ed1..00000000 --- a/docs/PoC/mem/sdram/sdram_ctrl_s3esk.rst +++ /dev/null @@ -1,38 +0,0 @@ - -sdram_ctrl_s3esk -################ - -Controller for Micron DDR-SDRAM on Spartan-3E Starter Kit Board. -SDRAM Device: MT46V32M16-6T - -CLK_PERIOD = clock period in nano seconds. All SDRAM timings are -calculated for the device stated above. - -CL = cas latency, choose according to clock frequency. -BL = burst length. - -Tested with: CLK_PERIOD = 10.0, CL=2, BL=2. - -Command, address and write data is sampled with clk. - -Read data is aligned with clk_fb90_n. Either process data in this clock -domain, or connect a FIFO to transfer data into another clock domain of your -choice. This FIFO should capable of storing at least one burst (size BL/2) -+ start of next burst (size 1). - -Synchronous resets are used. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/mem/sdram/sdram_ctrl_s3esk.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 76-119 - -Source file: `mem/sdram/sdram_ctrl_s3esk.vhdl `_ - - - diff --git a/docs/PoC/misc/filter/filter_and.rst b/docs/PoC/misc/filter/filter_and.rst deleted file mode 100644 index b5b9508d..00000000 --- a/docs/PoC/misc/filter/filter_and.rst +++ /dev/null @@ -1,20 +0,0 @@ - -filter_and -########## - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/misc/filter/filter_and.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 37-48 - -Source file: `misc/filter/filter_and.vhdl `_ - - - diff --git a/docs/PoC/misc/filter/filter_mean.rst b/docs/PoC/misc/filter/filter_mean.rst deleted file mode 100644 index 09812062..00000000 --- a/docs/PoC/misc/filter/filter_mean.rst +++ /dev/null @@ -1,20 +0,0 @@ - -filter_mean -########### - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/misc/filter/filter_mean.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 37-48 - -Source file: `misc/filter/filter_mean.vhdl `_ - - - diff --git a/docs/PoC/misc/filter/filter_or.rst b/docs/PoC/misc/filter/filter_or.rst deleted file mode 100644 index 18f5377e..00000000 --- a/docs/PoC/misc/filter/filter_or.rst +++ /dev/null @@ -1,20 +0,0 @@ - -filter_or -######### - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/misc/filter/filter_or.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 37-48 - -Source file: `misc/filter/filter_or.vhdl `_ - - - diff --git a/docs/PoC/misc/filter/index.rst b/docs/PoC/misc/filter/index.rst deleted file mode 100644 index 3e6e224d..00000000 --- a/docs/PoC/misc/filter/index.rst +++ /dev/null @@ -1,18 +0,0 @@ - -filter -====== - -These are filter entities.... - -**Entities** - - * :doc:`PoC.misc.filter.and ` - * :doc:`PoC.misc.filter.mean ` - * :doc:`PoC.misc.filter.or ` - -.. toctree:: - :hidden: - - filter_and - filter_mean - filter_or diff --git a/docs/PoC/misc/gearbox/gearbox_down_cc.rst b/docs/PoC/misc/gearbox/gearbox_down_cc.rst deleted file mode 100644 index 73f094b0..00000000 --- a/docs/PoC/misc/gearbox/gearbox_down_cc.rst +++ /dev/null @@ -1,24 +0,0 @@ - -gearbox_down_cc -############### - - This module provides a downscaling gearbox with a common clock (cc) - interface. It perfoems a 'word' to 'byte' splitting. The default order is - LITTLE_ENDIAN (starting at byte(0)). Input "In_Data" and output "Out_Data" - are of the same clock domain "Clock". Optional input and output registers - can be added by enabling (ADD_***PUT_REGISTERS = TRUE). - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/misc/gearbox/gearbox_down_cc.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 46-70 - -Source file: `misc/gearbox/gearbox_down_cc.vhdl `_ - - - diff --git a/docs/PoC/misc/gearbox/gearbox_down_dc.rst b/docs/PoC/misc/gearbox/gearbox_down_dc.rst deleted file mode 100644 index 6e26413f..00000000 --- a/docs/PoC/misc/gearbox/gearbox_down_dc.rst +++ /dev/null @@ -1,29 +0,0 @@ - -gearbox_down_dc -############### - - This module provides a downscaling gearbox with a dependent clock (dc) - interface. It perfoems a 'word' to 'byte' splitting. The default order is - LITTLE_ENDIAN (starting at byte(0)). Input "In_Data" is of clock domain - "Clock1"; output "Out_Data" is of clock domain "Clock2". Optional input and - output registers can be added by enabling (ADD_***PUT_REGISTERS = TRUE). - -Assertions: -=========== - - Clock periods of Clock1 and Clock2 MUST be multiples of each other. - - Clock1 and Clock2 MUST be phase aligned (related) to each other. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/misc/gearbox/gearbox_down_dc.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 50-64 - -Source file: `misc/gearbox/gearbox_down_dc.vhdl `_ - - - diff --git a/docs/PoC/misc/gearbox/gearbox_up_cc.rst b/docs/PoC/misc/gearbox/gearbox_up_cc.rst deleted file mode 100644 index 86042b81..00000000 --- a/docs/PoC/misc/gearbox/gearbox_up_cc.rst +++ /dev/null @@ -1,24 +0,0 @@ - -gearbox_up_cc -############# - - This module provides a downscaling gearbox with a common clock (cc) - interface. It perfoems a 'byte' to 'word' collection. The default order is - LITTLE_ENDIAN (starting at byte(0)). Input "In_Data" and output "Out_Data" - are of the same clock domain "Clock". Optional input and output registers - can be added by enabling (ADD_***PUT_REGISTERS = TRUE). - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/misc/gearbox/gearbox_up_cc.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 46-69 - -Source file: `misc/gearbox/gearbox_up_cc.vhdl `_ - - - diff --git a/docs/PoC/misc/gearbox/gearbox_up_dc.rst b/docs/PoC/misc/gearbox/gearbox_up_dc.rst deleted file mode 100644 index 8d90a465..00000000 --- a/docs/PoC/misc/gearbox/gearbox_up_dc.rst +++ /dev/null @@ -1,30 +0,0 @@ - -gearbox_up_dc -############# - - This module provides a upscaling gearbox with a dependent clock (dc) - interface. It perfoems a 'byte' to 'word' collection. The default order is - LITTLE_ENDIAN (starting at byte(0)). Input "In_Data" is of clock domain - "Clock1"; output "Out_Data" is of clock domain "Clock2". The "In_Align" - is required to mark the starting byte in the word. An optional input - register can be added by enabling (ADD_INPUT_REGISTERS = TRUE). - -Assertions: -=========== - - Clock periods of Clock1 and Clock2 MUST be multiples of each other. - - Clock1 and Clock2 MUST be phase aligned (related) to each other. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/misc/gearbox/gearbox_up_dc.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 51-66 - -Source file: `misc/gearbox/gearbox_up_dc.vhdl `_ - - - diff --git a/docs/PoC/misc/gearbox/index.rst b/docs/PoC/misc/gearbox/index.rst deleted file mode 100644 index 765ae347..00000000 --- a/docs/PoC/misc/gearbox/index.rst +++ /dev/null @@ -1,20 +0,0 @@ - -gearbox -======== - -These are gearbox entities.... - -**Entities** - - * :doc:`PoC.misc.gearbox.down_cc ` - * :doc:`PoC.misc.gearbox.down_dc ` - * :doc:`PoC.misc.gearbox.up_cc ` - * :doc:`PoC.misc.gearbox.up_dc ` - -.. toctree:: - :hidden: - - gearbox_down_cc - gearbox_down_dc - gearbox_up_cc - gearbox_up_dc diff --git a/docs/PoC/misc/index.rst b/docs/PoC/misc/index.rst deleted file mode 100644 index 7651ed65..00000000 --- a/docs/PoC/misc/index.rst +++ /dev/null @@ -1,43 +0,0 @@ - -misc -==== - -The namespace ``PoC.misc`` offers different yet uncathegorized entities. - -**Sub-Namespaces** - - * :doc:`PoC.misc.filter ` contains 1-bit filter algorithms. - * :doc:`PoC.misc.stat ` contains statistic modules. - * :doc:`PoC.misc.sync ` offers clock-domain-crossing (CDC) modules. - -**Package** - -The package :doc:`PoC.misc ` holds all component declarations for this namespace. - -**Entities** - - * :doc:`PoC.misc.Delay ` - * :doc:`PoC.misc.FrequencyMeasurement ` - * :doc:`PoC.misc.PulseTrain ` - * :doc:`PoC.misc.Sequencer ` - * :doc:`PoC.misc.StrobeGenerator ` - * :doc:`PoC.misc.StrobeLimiter ` - * :doc:`PoC.misc.WordAligner ` - -.. toctree:: - :hidden: - - filter/index - gearbox/index - stat/index - sync/index - - misc.pkg - - misc_Delay - misc_FrequencyMeasurement - misc_PulseTrain - misc_Sequencer - misc_StrobeGenerator - misc_StrobeLimiter - misc_WordAligner diff --git a/docs/PoC/misc/misc.pkg.rst b/docs/PoC/misc/misc.pkg.rst deleted file mode 100644 index 7ea587d9..00000000 --- a/docs/PoC/misc/misc.pkg.rst +++ /dev/null @@ -1,7 +0,0 @@ - -Package -======== - -This package holds all component declarations for this namespace. - -Source file: `misc/misc.pkg.vhdl `_ diff --git a/docs/PoC/misc/misc_BitwidthConverter.rst b/docs/PoC/misc/misc_BitwidthConverter.rst deleted file mode 100644 index 2b78114f..00000000 --- a/docs/PoC/misc/misc_BitwidthConverter.rst +++ /dev/null @@ -1,18 +0,0 @@ - -misc_BitwidthConverter -###################### - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/misc/misc_BitwidthConverter.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 32-45 - -Source file: `misc/misc_BitwidthConverter.vhdl `_ - - - diff --git a/docs/PoC/misc/misc_ByteAligner.rst b/docs/PoC/misc/misc_ByteAligner.rst deleted file mode 100644 index b7024d4f..00000000 --- a/docs/PoC/misc/misc_ByteAligner.rst +++ /dev/null @@ -1,20 +0,0 @@ - -misc_ByteAligner -################ - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/misc/misc_ByteAligner.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 40-53 - -Source file: `misc/misc_ByteAligner.vhdl `_ - - - diff --git a/docs/PoC/misc/misc_Delay.rst b/docs/PoC/misc/misc_Delay.rst deleted file mode 100644 index edd17178..00000000 --- a/docs/PoC/misc/misc_Delay.rst +++ /dev/null @@ -1,20 +0,0 @@ - -misc_Delay -########## - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/misc/misc_Delay.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 38-50 - -Source file: `misc/misc_Delay.vhdl `_ - - - diff --git a/docs/PoC/misc/misc_FrequencyMeasurement.rst b/docs/PoC/misc/misc_FrequencyMeasurement.rst deleted file mode 100644 index c8d13954..00000000 --- a/docs/PoC/misc/misc_FrequencyMeasurement.rst +++ /dev/null @@ -1,22 +0,0 @@ - -misc_FrequencyMeasurement -######################### - -This module counts 1 second in a reference timer at reference clock. This -reference time is used to start and stop a timer at input clock. The counter -value is the measured frequency in Hz. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/misc/misc_FrequencyMeasurement.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 44-56 - -Source file: `misc/misc_FrequencyMeasurement.vhdl `_ - - - diff --git a/docs/PoC/misc/misc_PulseTrain.rst b/docs/PoC/misc/misc_PulseTrain.rst deleted file mode 100644 index d0a88636..00000000 --- a/docs/PoC/misc/misc_PulseTrain.rst +++ /dev/null @@ -1,21 +0,0 @@ - -misc_PulseTrain -############### - - This module generates pulse trains. This module was written as a answer for - a StackOverflow question: http://stackoverflow.com/questions/25783320 - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/misc/misc_PulseTrain.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 41-51 - -Source file: `misc/misc_PulseTrain.vhdl `_ - - - diff --git a/docs/PoC/misc/misc_Sequencer.rst b/docs/PoC/misc/misc_Sequencer.rst deleted file mode 100644 index 73209bb0..00000000 --- a/docs/PoC/misc/misc_Sequencer.rst +++ /dev/null @@ -1,20 +0,0 @@ - -misc_Sequencer -############## - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/misc/misc_Sequencer.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 40-56 - -Source file: `misc/misc_Sequencer.vhdl `_ - - - diff --git a/docs/PoC/misc/misc_StrobeGenerator.rst b/docs/PoC/misc/misc_StrobeGenerator.rst deleted file mode 100644 index 8471f24f..00000000 --- a/docs/PoC/misc/misc_StrobeGenerator.rst +++ /dev/null @@ -1,20 +0,0 @@ - -misc_StrobeGenerator -#################### - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/misc/misc_StrobeGenerator.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 40-49 - -Source file: `misc/misc_StrobeGenerator.vhdl `_ - - - diff --git a/docs/PoC/misc/misc_StrobeLimiter.rst b/docs/PoC/misc/misc_StrobeLimiter.rst deleted file mode 100644 index 7eea3f38..00000000 --- a/docs/PoC/misc/misc_StrobeLimiter.rst +++ /dev/null @@ -1,20 +0,0 @@ - -misc_StrobeLimiter -################## - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/misc/misc_StrobeLimiter.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 39-51 - -Source file: `misc/misc_StrobeLimiter.vhdl `_ - - - diff --git a/docs/PoC/misc/stat/index.rst b/docs/PoC/misc/stat/index.rst deleted file mode 100644 index 542f6f0c..00000000 --- a/docs/PoC/misc/stat/index.rst +++ /dev/null @@ -1,21 +0,0 @@ - -stat -==== - -These are stat entities.... - -**Entities** - - * :doc:`PoC.misc.stat.Average ` - * :doc:`PoC.misc.stat.Histogram ` - * :doc:`PoC.misc.stat.Maximum ` - * :doc:`PoC.misc.stat.Minimum ` - - -.. toctree:: - :hidden: - - stat_Average - stat_Histogram - stat_Maximum - stat_Minimum diff --git a/docs/PoC/misc/stat/stat_Average.rst b/docs/PoC/misc/stat/stat_Average.rst deleted file mode 100644 index 6d149fd1..00000000 --- a/docs/PoC/misc/stat/stat_Average.rst +++ /dev/null @@ -1,20 +0,0 @@ - -stat_Average -############ - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/misc/stat/stat_Average.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 41-58 - -Source file: `misc/stat/stat_Average.vhdl `_ - - - diff --git a/docs/PoC/misc/stat/stat_Histogram.rst b/docs/PoC/misc/stat/stat_Histogram.rst deleted file mode 100644 index 3fa0400f..00000000 --- a/docs/PoC/misc/stat/stat_Histogram.rst +++ /dev/null @@ -1,20 +0,0 @@ - -stat_Histogram -############## - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/misc/stat/stat_Histogram.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 40-54 - -Source file: `misc/stat/stat_Histogram.vhdl `_ - - - diff --git a/docs/PoC/misc/stat/stat_Maximum.rst b/docs/PoC/misc/stat/stat_Maximum.rst deleted file mode 100644 index 36f9adeb..00000000 --- a/docs/PoC/misc/stat/stat_Maximum.rst +++ /dev/null @@ -1,20 +0,0 @@ - -stat_Maximum -############ - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/misc/stat/stat_Maximum.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 40-57 - -Source file: `misc/stat/stat_Maximum.vhdl `_ - - - diff --git a/docs/PoC/misc/stat/stat_Minimum.rst b/docs/PoC/misc/stat/stat_Minimum.rst deleted file mode 100644 index e98f7545..00000000 --- a/docs/PoC/misc/stat/stat_Minimum.rst +++ /dev/null @@ -1,20 +0,0 @@ - -stat_Minimum -############ - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/misc/stat/stat_Minimum.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 40-57 - -Source file: `misc/stat/stat_Minimum.vhdl `_ - - - diff --git a/docs/PoC/misc/sync/index.rst b/docs/PoC/misc/sync/index.rst deleted file mode 100644 index 8468f00f..00000000 --- a/docs/PoC/misc/sync/index.rst +++ /dev/null @@ -1,77 +0,0 @@ -sync -==== - -The namespace ``PoC.misc.sync`` offers different clock-domain-crossing (CDC) -synchronizer circuits. All synchronizers are based on the basic 2 flip-flop -synchonizer called :doc:`sync_Bits `. PoC has two -platform specific implementations for Altera and Xilinx, which are choosen, -if the appropriate ``MY_DEVICE`` constant is configured in :doc:`my_config.vhdl `. - -**Decision Table:** - -+----------+-------------------------------------------------+---------------------------------------------------+--------------------+-----------------------------------------------+-----------------------------------------------+ -| Behavior | Flag [#f1]_ | Strobe [#f2]_ | Continuous Data | Reset [#f4]_ | Pulse [#f3]_ | -+==========+=================================================+===================================================+====================+===============================================+===============================================+ -| 1 Bit | :doc:`sync_Bits ` | :doc:`sync_Strobe ` | fifo_ic_got [#f5]_ | :doc:`sync_Reset ` | :doc:`sync_Pulse ` | -+----------+-------------------------------------------------+---------------------------------------------------+--------------------+-----------------------------------------------+-----------------------------------------------+ -| n Bit | :doc:`sync_Vector ` | :doc:`sync_Command ` | fifo_ic_got [#f5]_ | | | -+----------+-------------------------------------------------+---------------------------------------------------+--------------------+-----------------------------------------------+-----------------------------------------------+ - -.. rubric:: Basic 2 Flip-Flop Synchronizer - -The basic 2 flip-flop synchronizer is called :doc:`sync_Bits `. It's -possible to configure the bit count of indivital bits. If a vector shall be -synchronized, use one of the special synchronizers like `sync_Vector`. The -vendor specific implementations are named ``sync_Bits_Altera`` and -``sync_Bits_Xilinx`` respectivily. - -A second variant of the 2-FF synchronizer is called :doc:`sync_Reset `. -It's for ``Reset``-signals, implementing asynchronous assertion and synchronous -deassertion. The vendor specific implementations are named ``sync_Reset_Altera`` -and ``sync_Reset_Xilinx`` respectivily. - -A third variant of a 2-FF synchronizer is called :doc:`sync_Pulse `. -It's for very short ``Pulsed``-signals. It uses an addition asynchronous capture FF to latch the -very short pulse. The vendor specific implementations are named ``sync_Pulse_Altera`` and -``sync_Pulse_Xilinx`` respectivily. - -.. rubric:: Special Synchronizers - -Based on the 2-FF synchronizer, several "high-level" synchronizers are build. - -* :doc:`sync_Strobe ` synchronizer ``strobe``-signals - across clock-domain-boundaries. A busy signal indicates the synchronization - status and can be used as a internal gate-signal to disallow new incoming - strobes. A ``strobe``-signal is only for one clock period active. -* :doc:`sync_Command ` like ``sync_Strobe``, it synchronizes - a one clock period active signal across the clock-domain-boundary, but the - input has multiple bits. After the multi bit strobe (Command) was transfered, - the output goes to its idle value. -* :doc:`sync_Vector ` synchronizes a complete vector - across the clock-domain-boundary. A changed detection on the input vector - causes a register to latch the current state. The changed event is transfered - to the new clock-domain and triggers a register to store the latched content, - but in the new clock domain. - -.. seealso:: - - :doc:`PoC.fifo.ic_got ` - For a cross-clock capable FIFO. - -.. rubric:: Footnotes - -.. [#f1] A *flag* or *status* signal is a continuous, long time stable signal. -.. [#f2] A *strobe* signal is active for only one cycle. -.. [#f3] A *pulse* signal is a very short event. -.. [#f4] To be documented -.. [#f5] See the ``PoC.fifo`` namespace for cross-clock capable FIFOs. - -.. toctree:: - :hidden: - - sync_Bits - sync_Command - sync_Pulse - sync_Reset - sync_Strobe - sync_Vector diff --git a/docs/PoC/misc/sync/sync_Bits.rst b/docs/PoC/misc/sync/sync_Bits.rst deleted file mode 100644 index 0c88cfae..00000000 --- a/docs/PoC/misc/sync/sync_Bits.rst +++ /dev/null @@ -1,49 +0,0 @@ - -sync_Bits -######### - -This module synchronizes multiple flag bits into clock-domain ``Clock``. -The clock-domain boundary crossing is done by two synchronizer D-FFs. All -bits are independent from each other. If a known vendor like Altera or Xilinx -are recognized, a vendor specific implementation is choosen. - -.. ATTENTION:: - Use this synchronizer only for long time stable signals (flags). - -Constraints: - General: - Please add constraints for meta stability to all '_meta' signals and - timing ignore constraints to all '_async' signals. - - Xilinx: - In case of a Xilinx device, this module will instantiate the optimized - module PoC.xil.sync.Bits. Please attend to the notes of sync_Bits.vhdl. - - Altera sdc file: - TODO - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/misc/sync/sync_Bits.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 68-79 - -Source file: `misc/sync/sync_Bits.vhdl `_ - -.. seealso:: - - :doc:`PoC.misc.sync.Reset ` - For a special 2 D-FF synchronizer for *reset*-signals. - :doc:`PoC.misc.sync.Pulse ` - For a special 1+2 D-FF synchronizer for *pulse*-signals. - :doc:`PoC.misc.sync.Strobe ` - For a synchronizer for *strobe*-signals. - :doc:`PoC.misc.sync.Vector ` - For a multiple bits capable synchronizer. - - - diff --git a/docs/PoC/misc/sync/sync_Command.rst b/docs/PoC/misc/sync/sync_Command.rst deleted file mode 100644 index 8224d838..00000000 --- a/docs/PoC/misc/sync/sync_Command.rst +++ /dev/null @@ -1,30 +0,0 @@ - -sync_Command -############ - -This module synchronizes a vector of bits from clock-domain ``Clock1`` to -clock-domain ``Clock2``. The clock-domain boundary crossing is done by a -change comparator, a T-FF, two synchronizer D-FFs and a reconstructive -XOR indicating a value change on the input. This changed signal is used -to capture the input for the new output. A busy flag is additionally -calculated for the input clock-domain. The output has strobe character -and is reset to it's ``INIT`` value after one clock cycle. - -Constraints: - This module uses sub modules which need to be constrained. Please - attend to the notes of the instantiated sub modules. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/misc/sync/sync_Command.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 50-63 - -Source file: `misc/sync/sync_Command.vhdl `_ - - - diff --git a/docs/PoC/misc/sync/sync_Pulse.rst b/docs/PoC/misc/sync/sync_Pulse.rst deleted file mode 100644 index 90c685ff..00000000 --- a/docs/PoC/misc/sync/sync_Pulse.rst +++ /dev/null @@ -1,49 +0,0 @@ - -sync_Pulse -########## - -This module synchronizes multiple pulsed bits into the clock-domain ``Clock``. -The clock-domain boundary crossing is done by two synchronizer D-FFs. All bits -are independent from each other. If a known vendor like Altera or Xilinx are -recognized, a vendor specific implementation is choosen. - -.. ATTENTION:: - Use this synchronizer for very short signals (pulse). - -Constraints: - General: - Please add constraints for meta stability to all '_meta' signals and - timing ignore constraints to all '_async' signals. - - Xilinx: - In case of a Xilinx device, this module will instantiate the optimized - module PoC.xil.sync.Pulse. Please attend to the notes of sync_Bits.vhdl. - - Altera sdc file: - TODO - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/misc/sync/sync_Pulse.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 68-78 - -Source file: `misc/sync/sync_Pulse.vhdl `_ - -.. seealso:: - - :doc:`PoC.misc.sync.Bits ` - For a common 2 D-FF synchronizer for *flag*-signals. - :doc:`PoC.misc.sync.Reset ` - For a special 2 D-FF synchronizer for *reset*-signals. - :doc:`PoC.misc.sync.Strobe ` - For a synchronizer for *strobe*-signals. - :doc:`PoC.misc.sync.Vector ` - For a multiple bits capable synchronizer. - - - diff --git a/docs/PoC/misc/sync/sync_Reset.rst b/docs/PoC/misc/sync/sync_Reset.rst deleted file mode 100644 index 191a0f65..00000000 --- a/docs/PoC/misc/sync/sync_Reset.rst +++ /dev/null @@ -1,40 +0,0 @@ - -sync_Reset -########## - -This module synchronizes an asynchronous reset signal to the clock -``Clock``. The ``Input`` can be asserted and de-asserted at any time. -The ``Output`` is asserted asynchronously and de-asserted synchronously -to the clock. - -.. ATTENTION:: - Use this synchronizer only to asynchronously reset your design. - The 'Output' should be feed by global buffer to the destination FFs, so - that, it reaches their reset inputs within one clock cycle. - -Constraints: - General: - Please add constraints for meta stability to all '_meta' signals and - timing ignore constraints to all '_async' signals. - - Xilinx: - In case of a Xilinx device, this module will instantiate the optimized - module xil_SyncReset. Please attend to the notes of xil_SyncReset. - - Altera sdc file: - TODO - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/misc/sync/sync_Reset.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 60-69 - -Source file: `misc/sync/sync_Reset.vhdl `_ - - - diff --git a/docs/PoC/misc/sync/sync_Strobe.rst b/docs/PoC/misc/sync/sync_Strobe.rst deleted file mode 100644 index 84e566a8..00000000 --- a/docs/PoC/misc/sync/sync_Strobe.rst +++ /dev/null @@ -1,32 +0,0 @@ - -sync_Strobe -########### - -This module synchronizes multiple high-active bits from clock-domain -``Clock1`` to clock-domain ``Clock2``. The clock-domain boundary crossing is -done by a T-FF, two synchronizer D-FFs and a reconstructive XOR. A busy -flag is additionally calculated and can be used to block new inputs. All -bits are independent from each other. Multiple consecutive strobes are -suppressed by a rising edge detection. - -.. ATTENTION:: - Use this synchronizer only for one-cycle high-active signals (strobes). - -Constraints: - This module uses sub modules which need to be constrained. Please - attend to the notes of the instantiated sub modules. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/misc/sync/sync_Strobe.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 51-63 - -Source file: `misc/sync/sync_Strobe.vhdl `_ - - - diff --git a/docs/PoC/misc/sync/sync_Vector.rst b/docs/PoC/misc/sync/sync_Vector.rst deleted file mode 100644 index c2ace981..00000000 --- a/docs/PoC/misc/sync/sync_Vector.rst +++ /dev/null @@ -1,29 +0,0 @@ - -sync_Vector -########### - -This module synchronizes a vector of bits from clock-domain ``Clock1`` to -clock-domain ``Clock2``. The clock-domain boundary crossing is done by a -change comparator, a T-FF, two synchronizer D-FFs and a reconstructive -XOR indicating a value change on the input. This changed signal is used -to capture the input for the new output. A busy flag is additionally -calculated for the input clock domain. - -Constraints: - This module uses sub modules which need to be constrainted. Please - attend to the notes of the instantiated sub modules. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/misc/sync/sync_Vector.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 49-63 - -Source file: `misc/sync/sync_Vector.vhdl `_ - - - diff --git a/docs/PoC/net/arp/arp_BroadCast_Receiver.rst b/docs/PoC/net/arp/arp_BroadCast_Receiver.rst deleted file mode 100644 index 9aeca321..00000000 --- a/docs/PoC/net/arp/arp_BroadCast_Receiver.rst +++ /dev/null @@ -1,20 +0,0 @@ - -arp_BroadCast_Receiver -###################### - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/net/arp/arp_BroadCast_Receiver.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 42-74 - -Source file: `net/arp/arp_BroadCast_Receiver.vhdl `_ - - - diff --git a/docs/PoC/net/arp/arp_BroadCast_Requester.rst b/docs/PoC/net/arp/arp_BroadCast_Requester.rst deleted file mode 100644 index 45f11821..00000000 --- a/docs/PoC/net/arp/arp_BroadCast_Requester.rst +++ /dev/null @@ -1,20 +0,0 @@ - -arp_BroadCast_Requester -####################### - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/net/arp/arp_BroadCast_Requester.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 42-73 - -Source file: `net/arp/arp_BroadCast_Requester.vhdl `_ - - - diff --git a/docs/PoC/net/arp/arp_Cache.rst b/docs/PoC/net/arp/arp_Cache.rst deleted file mode 100644 index 5007fdb0..00000000 --- a/docs/PoC/net/arp/arp_Cache.rst +++ /dev/null @@ -1,20 +0,0 @@ - -arp_Cache -######### - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/net/arp/arp_Cache.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 44-75 - -Source file: `net/arp/arp_Cache.vhdl `_ - - - diff --git a/docs/PoC/net/arp/arp_IPPool.rst b/docs/PoC/net/arp/arp_IPPool.rst deleted file mode 100644 index dceffcdf..00000000 --- a/docs/PoC/net/arp/arp_IPPool.rst +++ /dev/null @@ -1,20 +0,0 @@ - -arp_IPPool -########## - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/net/arp/arp_IPPool.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 43-63 - -Source file: `net/arp/arp_IPPool.vhdl `_ - - - diff --git a/docs/PoC/net/arp/arp_Tester.rst b/docs/PoC/net/arp/arp_Tester.rst deleted file mode 100644 index 39ce6b01..00000000 --- a/docs/PoC/net/arp/arp_Tester.rst +++ /dev/null @@ -1,20 +0,0 @@ - -arp_Tester -########## - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/net/arp/arp_Tester.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 43-65 - -Source file: `net/arp/arp_Tester.vhdl `_ - - - diff --git a/docs/PoC/net/arp/arp_UniCast_Receiver.rst b/docs/PoC/net/arp/arp_UniCast_Receiver.rst deleted file mode 100644 index 518ba0ea..00000000 --- a/docs/PoC/net/arp/arp_UniCast_Receiver.rst +++ /dev/null @@ -1,20 +0,0 @@ - -arp_UniCast_Receiver -#################### - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/net/arp/arp_UniCast_Receiver.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 42-76 - -Source file: `net/arp/arp_UniCast_Receiver.vhdl `_ - - - diff --git a/docs/PoC/net/arp/arp_UniCast_Responder.rst b/docs/PoC/net/arp/arp_UniCast_Responder.rst deleted file mode 100644 index 6cb4e232..00000000 --- a/docs/PoC/net/arp/arp_UniCast_Responder.rst +++ /dev/null @@ -1,20 +0,0 @@ - -arp_UniCast_Responder -##################### - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/net/arp/arp_UniCast_Responder.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 42-73 - -Source file: `net/arp/arp_UniCast_Responder.vhdl `_ - - - diff --git a/docs/PoC/net/arp/arp_Wrapper.rst b/docs/PoC/net/arp/arp_Wrapper.rst deleted file mode 100644 index 5a480ad7..00000000 --- a/docs/PoC/net/arp/arp_Wrapper.rst +++ /dev/null @@ -1,20 +0,0 @@ - -arp_Wrapper -########### - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/net/arp/arp_Wrapper.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 44-100 - -Source file: `net/arp/arp_Wrapper.vhdl `_ - - - diff --git a/docs/PoC/net/arp/index.rst b/docs/PoC/net/arp/index.rst deleted file mode 100644 index f4dd1fe2..00000000 --- a/docs/PoC/net/arp/index.rst +++ /dev/null @@ -1,16 +0,0 @@ - -arp -=== - -These are ARP entities.... - -.. toctree:: - - arp_BroadCast_Receiver - arp_BroadCast_Requester - arp_Cache - arp_IPPool - arp_Tester - arp_UniCast_Receiver - arp_UniCast_Responder - arp_Wrapper diff --git a/docs/PoC/net/eth/eth_GEMAC_GMII.rst b/docs/PoC/net/eth/eth_GEMAC_GMII.rst deleted file mode 100644 index 75094c88..00000000 --- a/docs/PoC/net/eth/eth_GEMAC_GMII.rst +++ /dev/null @@ -1,20 +0,0 @@ - -eth_GEMAC_GMII -############## - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/net/eth/eth_GEMAC_GMII.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 42-101 - -Source file: `net/eth/eth_GEMAC_GMII.vhdl `_ - - - diff --git a/docs/PoC/net/eth/eth_GEMAC_RX.rst b/docs/PoC/net/eth/eth_GEMAC_RX.rst deleted file mode 100644 index 24745ee6..00000000 --- a/docs/PoC/net/eth/eth_GEMAC_RX.rst +++ /dev/null @@ -1,20 +0,0 @@ - -Eth_GEMAC_RX -############ - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/net/eth/eth_GEMAC_RX.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 42-62 - -Source file: `net/eth/eth_GEMAC_RX.vhdl `_ - - - diff --git a/docs/PoC/net/eth/eth_GEMAC_TX.rst b/docs/PoC/net/eth/eth_GEMAC_TX.rst deleted file mode 100644 index 6cbfea27..00000000 --- a/docs/PoC/net/eth/eth_GEMAC_TX.rst +++ /dev/null @@ -1,20 +0,0 @@ - -Eth_GEMAC_TX -############ - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/net/eth/eth_GEMAC_TX.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 42-65 - -Source file: `net/eth/eth_GEMAC_TX.vhdl `_ - - - diff --git a/docs/PoC/net/eth/eth_PHYController.rst b/docs/PoC/net/eth/eth_PHYController.rst deleted file mode 100644 index dd91ac10..00000000 --- a/docs/PoC/net/eth/eth_PHYController.rst +++ /dev/null @@ -1,20 +0,0 @@ - -Eth_PHYController -################# - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/net/eth/eth_PHYController.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 45-68 - -Source file: `net/eth/eth_PHYController.vhdl `_ - - - diff --git a/docs/PoC/net/eth/eth_PHYController_Marvell_88E1111.rst b/docs/PoC/net/eth/eth_PHYController_Marvell_88E1111.rst deleted file mode 100644 index 8be2545e..00000000 --- a/docs/PoC/net/eth/eth_PHYController_Marvell_88E1111.rst +++ /dev/null @@ -1,20 +0,0 @@ - -Eth_PHYController_Marvell_88E1111 -################################# - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/net/eth/eth_PHYController_Marvell_88E1111.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 44-71 - -Source file: `net/eth/eth_PHYController_Marvell_88E1111.vhdl `_ - - - diff --git a/docs/PoC/net/eth/eth_Wrapper.rst b/docs/PoC/net/eth/eth_Wrapper.rst deleted file mode 100644 index f54362b9..00000000 --- a/docs/PoC/net/eth/eth_Wrapper.rst +++ /dev/null @@ -1,20 +0,0 @@ - -Eth_Wrapper -########### - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/net/eth/eth_Wrapper.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 68-112 - -Source file: `net/eth/eth_Wrapper.vhdl `_ - - - diff --git a/docs/PoC/net/eth/index.rst b/docs/PoC/net/eth/index.rst deleted file mode 100644 index 555d552e..00000000 --- a/docs/PoC/net/eth/index.rst +++ /dev/null @@ -1,14 +0,0 @@ - -eth -=== - -These are eth entities.... - -.. toctree:: - - eth_GEMAC_GMII - eth_GEMAC_RX - eth_GEMAC_TX - eth_PHYController - eth_PHYController_Marvell_88E1111 - eth_Wrapper diff --git a/docs/PoC/net/icmpv4/icmpv4_RX.rst b/docs/PoC/net/icmpv4/icmpv4_RX.rst deleted file mode 100644 index 32d296c8..00000000 --- a/docs/PoC/net/icmpv4/icmpv4_RX.rst +++ /dev/null @@ -1,20 +0,0 @@ - -icmpv4_RX -######### - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/net/icmpv4/icmpv4_RX.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 42-88 - -Source file: `net/icmpv4/icmpv4_RX.vhdl `_ - - - diff --git a/docs/PoC/net/icmpv4/icmpv4_TX.rst b/docs/PoC/net/icmpv4/icmpv4_TX.rst deleted file mode 100644 index 67986f7c..00000000 --- a/docs/PoC/net/icmpv4/icmpv4_TX.rst +++ /dev/null @@ -1,20 +0,0 @@ - -icmpv4_TX -######### - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/net/icmpv4/icmpv4_TX.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 42-78 - -Source file: `net/icmpv4/icmpv4_TX.vhdl `_ - - - diff --git a/docs/PoC/net/icmpv4/icmpv4_Wrapper.rst b/docs/PoC/net/icmpv4/icmpv4_Wrapper.rst deleted file mode 100644 index c08141e8..00000000 --- a/docs/PoC/net/icmpv4/icmpv4_Wrapper.rst +++ /dev/null @@ -1,20 +0,0 @@ - -icmpv4_Wrapper -############## - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/net/icmpv4/icmpv4_Wrapper.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 42-91 - -Source file: `net/icmpv4/icmpv4_Wrapper.vhdl `_ - - - diff --git a/docs/PoC/net/icmpv4/index.rst b/docs/PoC/net/icmpv4/index.rst deleted file mode 100644 index e8276ba9..00000000 --- a/docs/PoC/net/icmpv4/index.rst +++ /dev/null @@ -1,11 +0,0 @@ - -icmpv4 -====== - -These are icmpv4 entities.... - -.. toctree:: - - icmpv4_RX - icmpv4_TX - icmpv4_Wrapper diff --git a/docs/PoC/net/icmpv6/icmpv6_RX.rst b/docs/PoC/net/icmpv6/icmpv6_RX.rst deleted file mode 100644 index 9a57ab9f..00000000 --- a/docs/PoC/net/icmpv6/icmpv6_RX.rst +++ /dev/null @@ -1,20 +0,0 @@ - -icmpv6_RX -######### - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/net/icmpv6/icmpv6_RX.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 42-57 - -Source file: `net/icmpv6/icmpv6_RX.vhdl `_ - - - diff --git a/docs/PoC/net/icmpv6/icmpv6_TX.rst b/docs/PoC/net/icmpv6/icmpv6_TX.rst deleted file mode 100644 index 24e6dee4..00000000 --- a/docs/PoC/net/icmpv6/icmpv6_TX.rst +++ /dev/null @@ -1,20 +0,0 @@ - -icmpv6_TX -######### - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/net/icmpv6/icmpv6_TX.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 42-56 - -Source file: `net/icmpv6/icmpv6_TX.vhdl `_ - - - diff --git a/docs/PoC/net/icmpv6/icmpv6_Wrapper.rst b/docs/PoC/net/icmpv6/icmpv6_Wrapper.rst deleted file mode 100644 index 23718664..00000000 --- a/docs/PoC/net/icmpv6/icmpv6_Wrapper.rst +++ /dev/null @@ -1,20 +0,0 @@ - -icmpv6_Wrapper -############## - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/net/icmpv6/icmpv6_Wrapper.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 42-67 - -Source file: `net/icmpv6/icmpv6_Wrapper.vhdl `_ - - - diff --git a/docs/PoC/net/icmpv6/index.rst b/docs/PoC/net/icmpv6/index.rst deleted file mode 100644 index 2586053b..00000000 --- a/docs/PoC/net/icmpv6/index.rst +++ /dev/null @@ -1,11 +0,0 @@ - -icmpv6 -====== - -These are icmpv6 entities.... - -.. toctree:: - - icmpv6_RX - icmpv6_TX - icmpv6_Wrapper diff --git a/docs/PoC/net/index.rst b/docs/PoC/net/index.rst deleted file mode 100644 index 728d253f..00000000 --- a/docs/PoC/net/index.rst +++ /dev/null @@ -1,43 +0,0 @@ - -net -=== - -These are bus entities.... - -**Sub-Namespaces** - - * :doc:`PoC.net.arp ` - * :doc:`PoC.net.eth ` - * :doc:`PoC.net.icmpv4 ` - * :doc:`PoC.net.icmpv6 ` - * :doc:`PoC.net.ipv4 ` - * :doc:`PoC.net.ipv6 ` - * :doc:`PoC.net.mac ` - * :doc:`PoC.net.ndp ` - * :doc:`PoC.net.stack ` - * :doc:`PoC.net.udp ` - -**Entities** - - * :doc:`PoC.net.FrameChecksum ` - * :doc:`PoC.net.FrameLoopback ` - -.. toctree:: - :hidden: - - arp/index - eth/index - icmpv4/index - icmpv6/index - ipv4/index - ipv6/index - mac/index - ndp/index - stack/index - udp/index - -.. toctree:: - :hidden: - - net_FrameChecksum - net_FrameLoopback diff --git a/docs/PoC/net/ipv4/index.rst b/docs/PoC/net/ipv4/index.rst deleted file mode 100644 index abd71311..00000000 --- a/docs/PoC/net/ipv4/index.rst +++ /dev/null @@ -1,12 +0,0 @@ - -ipv4 -==== - -These are ipv4 entities.... - -.. toctree:: - - ipv4_RX - ipv4_TX - ipv4_FrameLoopback - ipv4_Wrapper diff --git a/docs/PoC/net/ipv4/ipv4_FrameLoopback.rst b/docs/PoC/net/ipv4/ipv4_FrameLoopback.rst deleted file mode 100644 index d551fa49..00000000 --- a/docs/PoC/net/ipv4/ipv4_FrameLoopback.rst +++ /dev/null @@ -1,20 +0,0 @@ - -ipv4_FrameLoopback -################## - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/net/ipv4/ipv4_FrameLoopback.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 42-74 - -Source file: `net/ipv4/ipv4_FrameLoopback.vhdl `_ - - - diff --git a/docs/PoC/net/ipv4/ipv4_RX.rst b/docs/PoC/net/ipv4/ipv4_RX.rst deleted file mode 100644 index 71f65197..00000000 --- a/docs/PoC/net/ipv4/ipv4_RX.rst +++ /dev/null @@ -1,20 +0,0 @@ - -ipv4_RX -####### - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/net/ipv4/ipv4_RX.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 42-82 - -Source file: `net/ipv4/ipv4_RX.vhdl `_ - - - diff --git a/docs/PoC/net/ipv4/ipv4_TX.rst b/docs/PoC/net/ipv4/ipv4_TX.rst deleted file mode 100644 index c7143b05..00000000 --- a/docs/PoC/net/ipv4/ipv4_TX.rst +++ /dev/null @@ -1,20 +0,0 @@ - -ipv4_TX -####### - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/net/ipv4/ipv4_TX.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 42-81 - -Source file: `net/ipv4/ipv4_TX.vhdl `_ - - - diff --git a/docs/PoC/net/ipv4/ipv4_Wrapper.rst b/docs/PoC/net/ipv4/ipv4_Wrapper.rst deleted file mode 100644 index 587c5e1e..00000000 --- a/docs/PoC/net/ipv4/ipv4_Wrapper.rst +++ /dev/null @@ -1,20 +0,0 @@ - -ipv4_Wrapper -############ - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/net/ipv4/ipv4_Wrapper.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 42-112 - -Source file: `net/ipv4/ipv4_Wrapper.vhdl `_ - - - diff --git a/docs/PoC/net/ipv6/index.rst b/docs/PoC/net/ipv6/index.rst deleted file mode 100644 index ca51fd7e..00000000 --- a/docs/PoC/net/ipv6/index.rst +++ /dev/null @@ -1,12 +0,0 @@ - -ipv6 -==== - -These are ipv6 entities.... - -.. toctree:: - - ipv6_RX - ipv6_TX - ipv6_FrameLoopback - ipv6_Wrapper diff --git a/docs/PoC/net/ipv6/ipv6_FrameLoopback.rst b/docs/PoC/net/ipv6/ipv6_FrameLoopback.rst deleted file mode 100644 index 8262fcc3..00000000 --- a/docs/PoC/net/ipv6/ipv6_FrameLoopback.rst +++ /dev/null @@ -1,20 +0,0 @@ - -ipv6_FrameLoopback -################## - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/net/ipv6/ipv6_FrameLoopback.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 42-74 - -Source file: `net/ipv6/ipv6_FrameLoopback.vhdl `_ - - - diff --git a/docs/PoC/net/ipv6/ipv6_RX.rst b/docs/PoC/net/ipv6/ipv6_RX.rst deleted file mode 100644 index c364261b..00000000 --- a/docs/PoC/net/ipv6/ipv6_RX.rst +++ /dev/null @@ -1,20 +0,0 @@ - -ipv6_RX -####### - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/net/ipv6/ipv6_RX.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 42-84 - -Source file: `net/ipv6/ipv6_RX.vhdl `_ - - - diff --git a/docs/PoC/net/ipv6/ipv6_TX.rst b/docs/PoC/net/ipv6/ipv6_TX.rst deleted file mode 100644 index 48dfb6ff..00000000 --- a/docs/PoC/net/ipv6/ipv6_TX.rst +++ /dev/null @@ -1,20 +0,0 @@ - -ipv6_TX -####### - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/net/ipv6/ipv6_TX.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 42-84 - -Source file: `net/ipv6/ipv6_TX.vhdl `_ - - - diff --git a/docs/PoC/net/ipv6/ipv6_Wrapper.rst b/docs/PoC/net/ipv6/ipv6_Wrapper.rst deleted file mode 100644 index 20470586..00000000 --- a/docs/PoC/net/ipv6/ipv6_Wrapper.rst +++ /dev/null @@ -1,20 +0,0 @@ - -ipv6_Wrapper -############ - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/net/ipv6/ipv6_Wrapper.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 42-116 - -Source file: `net/ipv6/ipv6_Wrapper.vhdl `_ - - - diff --git a/docs/PoC/net/mac/index.rst b/docs/PoC/net/mac/index.rst deleted file mode 100644 index 88884649..00000000 --- a/docs/PoC/net/mac/index.rst +++ /dev/null @@ -1,16 +0,0 @@ - -mac -=== - -These are mac entities.... - -.. toctree:: - - mac_RX_DestMAC_Switch - mac_RX_SrcMAC_Filter - mac_RX_Type_Switch - mac_TX_SrcMAC_Prepender - mac_TX_DestMAC_Prepender - mac_TX_Type_Prepender - mac_FrameLoopback - mac_Wrapper diff --git a/docs/PoC/net/mac/mac_FrameLoopback.rst b/docs/PoC/net/mac/mac_FrameLoopback.rst deleted file mode 100644 index 9306aa6e..00000000 --- a/docs/PoC/net/mac/mac_FrameLoopback.rst +++ /dev/null @@ -1,20 +0,0 @@ - -mac_FrameLoopback -################# - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/net/mac/mac_FrameLoopback.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 42-72 - -Source file: `net/mac/mac_FrameLoopback.vhdl `_ - - - diff --git a/docs/PoC/net/mac/mac_RX_DestMAC_Switch.rst b/docs/PoC/net/mac/mac_RX_DestMAC_Switch.rst deleted file mode 100644 index f030f20b..00000000 --- a/docs/PoC/net/mac/mac_RX_DestMAC_Switch.rst +++ /dev/null @@ -1,20 +0,0 @@ - -mac_RX_DestMAC_Switch -##################### - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/net/mac/mac_RX_DestMAC_Switch.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 42-67 - -Source file: `net/mac/mac_RX_DestMAC_Switch.vhdl `_ - - - diff --git a/docs/PoC/net/mac/mac_RX_SrcMAC_Filter.rst b/docs/PoC/net/mac/mac_RX_SrcMAC_Filter.rst deleted file mode 100644 index 5a167feb..00000000 --- a/docs/PoC/net/mac/mac_RX_SrcMAC_Filter.rst +++ /dev/null @@ -1,20 +0,0 @@ - -mac_RX_SrcMAC_Filter -#################### - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/net/mac/mac_RX_SrcMAC_Filter.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 42-72 - -Source file: `net/mac/mac_RX_SrcMAC_Filter.vhdl `_ - - - diff --git a/docs/PoC/net/mac/mac_RX_Type_Switch.rst b/docs/PoC/net/mac/mac_RX_Type_Switch.rst deleted file mode 100644 index 895056a6..00000000 --- a/docs/PoC/net/mac/mac_RX_Type_Switch.rst +++ /dev/null @@ -1,20 +0,0 @@ - -mac_RX_Type_Switch -################## - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/net/mac/mac_RX_Type_Switch.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 42-74 - -Source file: `net/mac/mac_RX_Type_Switch.vhdl `_ - - - diff --git a/docs/PoC/net/mac/mac_TX_DestMAC_Prepender.rst b/docs/PoC/net/mac/mac_TX_DestMAC_Prepender.rst deleted file mode 100644 index 84ae9d79..00000000 --- a/docs/PoC/net/mac/mac_TX_DestMAC_Prepender.rst +++ /dev/null @@ -1,20 +0,0 @@ - -mac_TX_DestMAC_Prepender -######################## - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/net/mac/mac_TX_DestMAC_Prepender.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 42-65 - -Source file: `net/mac/mac_TX_DestMAC_Prepender.vhdl `_ - - - diff --git a/docs/PoC/net/mac/mac_TX_SrcMAC_Prepender.rst b/docs/PoC/net/mac/mac_TX_SrcMAC_Prepender.rst deleted file mode 100644 index c2dcf82c..00000000 --- a/docs/PoC/net/mac/mac_TX_SrcMAC_Prepender.rst +++ /dev/null @@ -1,20 +0,0 @@ - -mac_TX_SrcMAC_Prepender -####################### - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/net/mac/mac_TX_SrcMAC_Prepender.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 42-69 - -Source file: `net/mac/mac_TX_SrcMAC_Prepender.vhdl `_ - - - diff --git a/docs/PoC/net/mac/mac_TX_Type_Prepender.rst b/docs/PoC/net/mac/mac_TX_Type_Prepender.rst deleted file mode 100644 index fcb6f29e..00000000 --- a/docs/PoC/net/mac/mac_TX_Type_Prepender.rst +++ /dev/null @@ -1,20 +0,0 @@ - -mac_TX_Type_Prepender -##################### - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/net/mac/mac_TX_Type_Prepender.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 42-69 - -Source file: `net/mac/mac_TX_Type_Prepender.vhdl `_ - - - diff --git a/docs/PoC/net/mac/mac_Wrapper.rst b/docs/PoC/net/mac/mac_Wrapper.rst deleted file mode 100644 index 16be2b8a..00000000 --- a/docs/PoC/net/mac/mac_Wrapper.rst +++ /dev/null @@ -1,20 +0,0 @@ - -mac_Wrapper -########### - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/net/mac/mac_Wrapper.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 42-84 - -Source file: `net/mac/mac_Wrapper.vhdl `_ - - - diff --git a/docs/PoC/net/ndp/index.rst b/docs/PoC/net/ndp/index.rst deleted file mode 100644 index f054b692..00000000 --- a/docs/PoC/net/ndp/index.rst +++ /dev/null @@ -1,12 +0,0 @@ - -ndp -=== - -These are ndp entities.... - -.. toctree:: - - ndp_DestinationCache - ndp_FSMQuery - ndp_NeighborCache - ndp_Wrapper diff --git a/docs/PoC/net/ndp/ndp_DestinationCache.rst b/docs/PoC/net/ndp/ndp_DestinationCache.rst deleted file mode 100644 index b1ef4627..00000000 --- a/docs/PoC/net/ndp/ndp_DestinationCache.rst +++ /dev/null @@ -1,20 +0,0 @@ - -ndp_DestinationCache -#################### - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/net/ndp/ndp_DestinationCache.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 42-65 - -Source file: `net/ndp/ndp_DestinationCache.vhdl `_ - - - diff --git a/docs/PoC/net/ndp/ndp_FSMQuery.rst b/docs/PoC/net/ndp/ndp_FSMQuery.rst deleted file mode 100644 index 842125a4..00000000 --- a/docs/PoC/net/ndp/ndp_FSMQuery.rst +++ /dev/null @@ -1,20 +0,0 @@ - -ndp_FSMQuery -############ - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/net/ndp/ndp_FSMQuery.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 42-79 - -Source file: `net/ndp/ndp_FSMQuery.vhdl `_ - - - diff --git a/docs/PoC/net/ndp/ndp_NeighborCache.rst b/docs/PoC/net/ndp/ndp_NeighborCache.rst deleted file mode 100644 index 7b5647c5..00000000 --- a/docs/PoC/net/ndp/ndp_NeighborCache.rst +++ /dev/null @@ -1,20 +0,0 @@ - -ndp_NeighborCache -################# - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/net/ndp/ndp_NeighborCache.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 42-65 - -Source file: `net/ndp/ndp_NeighborCache.vhdl `_ - - - diff --git a/docs/PoC/net/ndp/ndp_Wrapper.rst b/docs/PoC/net/ndp/ndp_Wrapper.rst deleted file mode 100644 index b7e5a34b..00000000 --- a/docs/PoC/net/ndp/ndp_Wrapper.rst +++ /dev/null @@ -1,20 +0,0 @@ - -NDP_Wrapper -########### - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/net/ndp/ndp_Wrapper.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 43-65 - -Source file: `net/ndp/ndp_Wrapper.vhdl `_ - - - diff --git a/docs/PoC/net/net_FrameChecksum.rst b/docs/PoC/net/net_FrameChecksum.rst deleted file mode 100644 index ed1530a3..00000000 --- a/docs/PoC/net/net_FrameChecksum.rst +++ /dev/null @@ -1,20 +0,0 @@ - -net_FrameChecksum -################# - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/net/net_FrameChecksum.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 41-72 - -Source file: `net/net_FrameChecksum.vhdl `_ - - - diff --git a/docs/PoC/net/net_FrameLoopback.rst b/docs/PoC/net/net_FrameLoopback.rst deleted file mode 100644 index 71e0148a..00000000 --- a/docs/PoC/net/net_FrameLoopback.rst +++ /dev/null @@ -1,20 +0,0 @@ - -FrameLoopback -############# - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/net/net_FrameLoopback.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 41-65 - -Source file: `net/net_FrameLoopback.vhdl `_ - - - diff --git a/docs/PoC/net/net_FramePerformanceCounter.rst b/docs/PoC/net/net_FramePerformanceCounter.rst deleted file mode 100644 index 0ed18f58..00000000 --- a/docs/PoC/net/net_FramePerformanceCounter.rst +++ /dev/null @@ -1,18 +0,0 @@ - -LocalLink_PerformanceCounter -############################ - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/net/net_FramePerformanceCounter.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 11-35 - -Source file: `net/net_FramePerformanceCounter.vhdl `_ - - - diff --git a/docs/PoC/net/stack/index.rst b/docs/PoC/net/stack/index.rst deleted file mode 100644 index 21b64c1f..00000000 --- a/docs/PoC/net/stack/index.rst +++ /dev/null @@ -1,13 +0,0 @@ - -stack -===== - -These are udp entities.... - -.. toctree:: - - stack_IPv4 - stack_IPv6 - stack_UDPv4 - stack_UDPv6 - stack_MAC diff --git a/docs/PoC/net/stack/stack_UDPv4.rst b/docs/PoC/net/stack/stack_UDPv4.rst deleted file mode 100644 index fbaf061d..00000000 --- a/docs/PoC/net/stack/stack_UDPv4.rst +++ /dev/null @@ -1,20 +0,0 @@ - -stack_UDPv4 -########### - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/net/stack/stack_UDPv4.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 44-111 - -Source file: `net/stack/stack_UDPv4.vhdl `_ - - - diff --git a/docs/PoC/net/udp/index.rst b/docs/PoC/net/udp/index.rst deleted file mode 100644 index e58e8535..00000000 --- a/docs/PoC/net/udp/index.rst +++ /dev/null @@ -1,12 +0,0 @@ - -udp -=== - -These are udp entities.... - -.. toctree:: - - udp_RX - udp_TX - udp_FrameLoopback - udp_Wrapper diff --git a/docs/PoC/net/udp/udp_FrameLoopback.rst b/docs/PoC/net/udp/udp_FrameLoopback.rst deleted file mode 100644 index eb379923..00000000 --- a/docs/PoC/net/udp/udp_FrameLoopback.rst +++ /dev/null @@ -1,20 +0,0 @@ - -udp_FrameLoopback -################# - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/net/udp/udp_FrameLoopback.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 42-77 - -Source file: `net/udp/udp_FrameLoopback.vhdl `_ - - - diff --git a/docs/PoC/net/udp/udp_RX.rst b/docs/PoC/net/udp/udp_RX.rst deleted file mode 100644 index 80d4854a..00000000 --- a/docs/PoC/net/udp/udp_RX.rst +++ /dev/null @@ -1,20 +0,0 @@ - -udp_RX -###### - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/net/udp/udp_RX.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 42-95 - -Source file: `net/udp/udp_RX.vhdl `_ - - - diff --git a/docs/PoC/net/udp/udp_TX.rst b/docs/PoC/net/udp/udp_TX.rst deleted file mode 100644 index 9c8cdb84..00000000 --- a/docs/PoC/net/udp/udp_TX.rst +++ /dev/null @@ -1,20 +0,0 @@ - -udp_TX -###### - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/net/udp/udp_TX.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 42-78 - -Source file: `net/udp/udp_TX.vhdl `_ - - - diff --git a/docs/PoC/net/udp/udp_Wrapper.rst b/docs/PoC/net/udp/udp_Wrapper.rst deleted file mode 100644 index 01d8c187..00000000 --- a/docs/PoC/net/udp/udp_Wrapper.rst +++ /dev/null @@ -1,20 +0,0 @@ - -udp_Wrapper -########### - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/net/udp/udp_Wrapper.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 42-120 - -Source file: `net/udp/udp_Wrapper.vhdl `_ - - - diff --git a/docs/PoC/sort/index.rst b/docs/PoC/sort/index.rst deleted file mode 100644 index c9993826..00000000 --- a/docs/PoC/sort/index.rst +++ /dev/null @@ -1,31 +0,0 @@ - -sort -==== - -These are sorting entities.... - -**Sub-Namespaces** - - * :doc:`PoC.sort.sortnet ` - -**Entities** - - * :doc:`PoC.sort.ExpireList ` - * :doc:`PoC.sort.InsertSort ` - * :doc:`PoC.sort.LeastFrequentlyUsed ` - * :doc:`PoC.sort.lru_cache ` - * :doc:`PoC.sort.lru_list ` - -.. toctree:: - :hidden: - - sortnet/index - -.. toctree:: - :hidden: - - sort_ExpireList - sort_InsertSort - sort_LeastFrequentlyUsed - sort_lru_cache - sort_lru_list diff --git a/docs/PoC/sort/sort_ExpireList.rst b/docs/PoC/sort/sort_ExpireList.rst deleted file mode 100644 index f73f680c..00000000 --- a/docs/PoC/sort/sort_ExpireList.rst +++ /dev/null @@ -1,20 +0,0 @@ - -list_expire -########### - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/sort/sort_ExpireList.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 42-61 - -Source file: `sort/sort_ExpireList.vhdl `_ - - - diff --git a/docs/PoC/sort/sort_InsertSort.rst b/docs/PoC/sort/sort_InsertSort.rst deleted file mode 100644 index 8bcb56f4..00000000 --- a/docs/PoC/sort/sort_InsertSort.rst +++ /dev/null @@ -1,20 +0,0 @@ - -list_lru_systolic -################# - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/sort/sort_InsertSort.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 44-64 - -Source file: `sort/sort_InsertSort.vhdl `_ - - - diff --git a/docs/PoC/sort/sort_LeastFrequentlyUsed.rst b/docs/PoC/sort/sort_LeastFrequentlyUsed.rst deleted file mode 100644 index ac1d9ea8..00000000 --- a/docs/PoC/sort/sort_LeastFrequentlyUsed.rst +++ /dev/null @@ -1,20 +0,0 @@ - -sort_LeastFrequentlyUsed -######################## - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/sort/sort_LeastFrequentlyUsed.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 36-53 - -Source file: `sort/sort_LeastFrequentlyUsed.vhdl `_ - - - diff --git a/docs/PoC/sort/sort_lru_cache.rst b/docs/PoC/sort/sort_lru_cache.rst deleted file mode 100644 index 870aaf75..00000000 --- a/docs/PoC/sort/sort_lru_cache.rst +++ /dev/null @@ -1,34 +0,0 @@ - -sort_lru_cache -############## - -This is an optimized implementation of ``sort_lru_list`` to be used for caches. -Only keys are stored within this list, and these keys are the index of the -cache lines. The list initially contains all indizes from 0 to ELEMENTS-1. -The least-recently used index ``KeyOut`` is always valid. - -The first outputed least-recently used index will be ELEMENTS-1. - -The inputs ``Insert``, ``Free``, ``KeyIn``, and ``Reset`` are synchronous to the -rising-edge of the clock ``clock``. All control signals are high-active. - -Supported operations: - * **Insert:** Mark index ``KeyIn`` as recently used, e.g., when a cache-line - was accessed. - * **Free:** Mark index ``KeyIn`` as least-recently used. Apply this operation, - when a cache-line gets invalidated. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/sort/sort_lru_cache.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 56-70 - -Source file: `sort/sort_lru_cache.vhdl `_ - - - diff --git a/docs/PoC/sort/sort_lru_list.rst b/docs/PoC/sort/sort_lru_list.rst deleted file mode 100644 index 8a199844..00000000 --- a/docs/PoC/sort/sort_lru_list.rst +++ /dev/null @@ -1,32 +0,0 @@ - -sort_lru_list -############# - -List storing ``(key, value)`` pairs. The least-recently inserted pair is -outputed on ``DataOut`` if ``Valid = '1'``. If ``Valid = '0'``, then the list -empty. - -The inputs ``Insert``, ``Remove``, ``DataIn``, and ``Reset`` are synchronous -to the rising-edge of the clock ``clock``. All control signals are high-active. - -Supported operations: - * **Insert:** Insert ``DataIn`` as recently used ``(key, value)`` pair. If - key is already within the list, then the corresponding value is updated and - the pair is moved to the recently used position. - * **Remove:** Remove ``(key, value)`` pair with the given key. The list is not - modified if key is not within the list. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/sort/sort_lru_list.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 55-74 - -Source file: `sort/sort_lru_list.vhdl `_ - - - diff --git a/docs/PoC/sort/sortnet/index.rst b/docs/PoC/sort/sortnet/index.rst deleted file mode 100644 index e62cee53..00000000 --- a/docs/PoC/sort/sortnet/index.rst +++ /dev/null @@ -1,26 +0,0 @@ - -sortnet -======== - -This sub-namespace contains sorting network implementations. - -**Entities** - - * :doc:`PoC.sort.sortnet.BitonicSort ` - * :doc:`PoC.sort.sortnet.MergeSort_Streamed ` - * :doc:`PoC.sort.sortnet.OddEvenMergeSort ` - * :doc:`PoC.sort.sortnet.OddEvenSort ` - * :doc:`PoC.sort.sortnet.Stream_Adapter ` - * :doc:`PoC.sort.sortnet.Stream_Adapter2 ` - * :doc:`PoC.sort.sortnet.Transform ` - -.. toctree:: - :hidden: - - sortnet_BitonicSort - sortnet_MergeSort_Streamed - sortnet_OddEvenMergeSort - sortnet_OddEvenSort - sortnet_Stream_Adapter - sortnet_Stream_Adapter2 - sortnet_Transform diff --git a/docs/PoC/sort/sortnet/sortnet_BitonicSort.rst b/docs/PoC/sort/sortnet/sortnet_BitonicSort.rst deleted file mode 100644 index 01d04f8e..00000000 --- a/docs/PoC/sort/sortnet/sortnet_BitonicSort.rst +++ /dev/null @@ -1,20 +0,0 @@ - -sortnet_BitonicSort -################### - -This sorting network uses the *bitonic sort* algorithm. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/sort/sortnet/sortnet_BitonicSort.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 43-69 - -Source file: `sort/sortnet/sortnet_BitonicSort.vhdl `_ - - - diff --git a/docs/PoC/sort/sortnet/sortnet_MergeSort_Streamed.rst b/docs/PoC/sort/sortnet/sortnet_MergeSort_Streamed.rst deleted file mode 100644 index 88d64260..00000000 --- a/docs/PoC/sort/sortnet/sortnet_MergeSort_Streamed.rst +++ /dev/null @@ -1,20 +0,0 @@ - -sortnet_MergeSort_Streamed -########################## - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/sort/sortnet/sortnet_MergeSort_Streamed.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 41-68 - -Source file: `sort/sortnet/sortnet_MergeSort_Streamed.vhdl `_ - - - diff --git a/docs/PoC/sort/sortnet/sortnet_OddEvenMergeSort.rst b/docs/PoC/sort/sortnet/sortnet_OddEvenMergeSort.rst deleted file mode 100644 index 88007f23..00000000 --- a/docs/PoC/sort/sortnet/sortnet_OddEvenMergeSort.rst +++ /dev/null @@ -1,20 +0,0 @@ - -sortnet_OddEvenMergeSort -######################## - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/sort/sortnet/sortnet_OddEvenMergeSort.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 43-69 - -Source file: `sort/sortnet/sortnet_OddEvenMergeSort.vhdl `_ - - - diff --git a/docs/PoC/sort/sortnet/sortnet_OddEvenSort.rst b/docs/PoC/sort/sortnet/sortnet_OddEvenSort.rst deleted file mode 100644 index 32a53603..00000000 --- a/docs/PoC/sort/sortnet/sortnet_OddEvenSort.rst +++ /dev/null @@ -1,20 +0,0 @@ - -sortnet_OddEvenSort -################### - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/sort/sortnet/sortnet_OddEvenSort.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 42-68 - -Source file: `sort/sortnet/sortnet_OddEvenSort.vhdl `_ - - - diff --git a/docs/PoC/sort/sortnet/sortnet_Stream_Adapter.rst b/docs/PoC/sort/sortnet/sortnet_Stream_Adapter.rst deleted file mode 100644 index 21e0f97a..00000000 --- a/docs/PoC/sort/sortnet/sortnet_Stream_Adapter.rst +++ /dev/null @@ -1,20 +0,0 @@ - -sortnet_Stream_Adapter -###################### - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/sort/sortnet/sortnet_Stream_Adapter.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 42-68 - -Source file: `sort/sortnet/sortnet_Stream_Adapter.vhdl `_ - - - diff --git a/docs/PoC/sort/sortnet/sortnet_Stream_Adapter2.rst b/docs/PoC/sort/sortnet/sortnet_Stream_Adapter2.rst deleted file mode 100644 index 6d893c7e..00000000 --- a/docs/PoC/sort/sortnet/sortnet_Stream_Adapter2.rst +++ /dev/null @@ -1,20 +0,0 @@ - -sortnet_Stream_Adapter2 -####################### - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/sort/sortnet/sortnet_Stream_Adapter2.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 42-76 - -Source file: `sort/sortnet/sortnet_Stream_Adapter2.vhdl `_ - - - diff --git a/docs/PoC/sort/sortnet/sortnet_Transform.rst b/docs/PoC/sort/sortnet/sortnet_Transform.rst deleted file mode 100644 index 503e4450..00000000 --- a/docs/PoC/sort/sortnet/sortnet_Transform.rst +++ /dev/null @@ -1,20 +0,0 @@ - -sortnet_Transform -################# - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/sort/sortnet/sortnet_Transform.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 41-61 - -Source file: `sort/sortnet/sortnet_Transform.vhdl `_ - - - diff --git a/docs/PoC/xil/index.rst b/docs/PoC/xil/index.rst deleted file mode 100644 index 9d89b376..00000000 --- a/docs/PoC/xil/index.rst +++ /dev/null @@ -1,42 +0,0 @@ - -xil -=== - -This namespace is for Xilinx specific modules. - -**Sub-Namespaces** - - * :doc:`PoC.xil.mig ` - * :doc:`PoC.xil.reconfig ` - -**Entities** - - * :doc:`PoC.xil.BSCAN ` - * :doc:`PoC.xil.ChipScopeICON ` - * :doc:`PoC.xil.DRP_BusMux ` - * :doc:`PoC.xil.DRP_BusSync ` - * :doc:`PoC.xil.ICAP ` - * :doc:`PoC.xil.Reconfigurator ` - * :doc:`PoC.xil.SystemMonitor ` - * :doc:`PoC.xil.SystemMonitor_Virtex6 ` - * :doc:`PoC.xil.SystemMonitor_Series7 ` - - -.. toctree:: - :hidden: - - mig/index - reconfig/index - -.. toctree:: - :hidden: - - xil_BSCAN - xil_ChipScopeICON - xil_DRP_BusMux - xil_DRP_BusSync - xil_ICAP - xil_Reconfigurator - xil_SystemMonitor - xil_SystemMonitor_Virtex6 - xil_SystemMonitor_Series7 diff --git a/docs/PoC/xil/mig/index.rst b/docs/PoC/xil/mig/index.rst deleted file mode 100644 index 001fd816..00000000 --- a/docs/PoC/xil/mig/index.rst +++ /dev/null @@ -1,23 +0,0 @@ - -mig -=== - -The namespace ``PoC.xil.mig`` offers pre-configured memory controllers generated -with Xilinx's Memory Interface Generator (MIG). - -* **for Spartan-6 boards:** - - * :doc:`mig_Atlys_1x128 ` - A DDR2 memory controller for the Digilent Atlys board. - -* **for Kintex-7 boards:** - - * :doc:`mig_KC705_MT8JTF12864HZ_1G6 ` - A DDR3 memory controller for the Xilinx KC705 board. - -* **for Virtex-7 boards:** - - -.. toctree:: - :hidden: - - mig_Atlys_1x128 - mig_KC705_MT8JTF12864HZ_1G6 diff --git a/docs/PoC/xil/reconfig/index.rst b/docs/PoC/xil/reconfig/index.rst deleted file mode 100644 index 0f84f4d5..00000000 --- a/docs/PoC/xil/reconfig/index.rst +++ /dev/null @@ -1,16 +0,0 @@ - -reconfig -======== - -These are reconfig entities.... - -**Entities** - - * :doc:`PoC.xil.reconfig.icap_fsm ` - * :doc:`PoC.xil.reconfig.icap_wrapper ` - -.. toctree:: - :hidden: - - reconfig_icap_fsm - reconfig_icap_wrapper diff --git a/docs/PoC/xil/reconfig/reconfig_icap_fsm.rst b/docs/PoC/xil/reconfig/reconfig_icap_fsm.rst deleted file mode 100644 index 3a53c1b4..00000000 --- a/docs/PoC/xil/reconfig/reconfig_icap_fsm.rst +++ /dev/null @@ -1,24 +0,0 @@ - -reconfig_icap_fsm -################# - -This module parses the data stream to the Xilinx "Internal Configuration Access Port" (ICAP) -primitives to generate control signals. Tested on: - -* Virtex-6 -* Virtex-7 - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/xil/reconfig/reconfig_icap_fsm.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 42-63 - -Source file: `xil/reconfig/reconfig_icap_fsm.vhdl `_ - - - diff --git a/docs/PoC/xil/reconfig/reconfig_icap_wrapper.rst b/docs/PoC/xil/reconfig/reconfig_icap_wrapper.rst deleted file mode 100644 index baabe148..00000000 --- a/docs/PoC/xil/reconfig/reconfig_icap_wrapper.rst +++ /dev/null @@ -1,23 +0,0 @@ - -reconfig_icap_wrapper -##################### - -This module was designed to connect the Xilinx "Internal Configuration Access Port" (ICAP) -to a PCIe endpoint on a Dini board. Tested on: - -tbd - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../../src/xil/reconfig/reconfig_icap_wrapper.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 43-68 - -Source file: `xil/reconfig/reconfig_icap_wrapper.vhdl `_ - - - diff --git a/docs/PoC/xil/xil_BSCAN.rst b/docs/PoC/xil/xil_BSCAN.rst deleted file mode 100644 index 2eb45615..00000000 --- a/docs/PoC/xil/xil_BSCAN.rst +++ /dev/null @@ -1,25 +0,0 @@ - -xil_BSCAN -######### - -This module wraps Xilinx "Boundary Scan" (JTAG) primitives in a generic -module. |br| -Supported devices are: - * Spartan-3, Spartan-6 - * Virtex-5, Virtex-6 - * Series-7 (Artix-7, Kintex-7, Virtex-7, Zynq-7000) - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/xil/xil_BSCAN.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 47-65 - -Source file: `xil/xil_BSCAN.vhdl `_ - - - diff --git a/docs/PoC/xil/xil_ChipScopeICON.rst b/docs/PoC/xil/xil_ChipScopeICON.rst deleted file mode 100644 index ee254a98..00000000 --- a/docs/PoC/xil/xil_ChipScopeICON.rst +++ /dev/null @@ -1,38 +0,0 @@ - -xil_ChipScopeICON -################# - -This module wraps 15 ChipScope ICON IP core netlists generated from ChipScope -ICON xco files. The generic parameter ``PORTS`` selects the apropriate ICON -instance with 1 to 15 ICON ``ControlBus`` ports. Each ``ControlBus`` port is -of type ``T_XIL_CHIPSCOPE_CONTROL`` and of mode ``inout``. - -.. rubric:: Compile required CoreGenerator IP Cores to Netlists with PoC - -Please use the provided Xilinx ISE compile command ``ise`` in PoC to recreate -the needed source and netlist files on your local machine. - -.. code-block:: PowerShell - - cd PoCRoot - .\poc.ps1 ise PoC.xil.ChipScopeICON --board=KC705 - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/xil/xil_ChipScopeICON.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 56-63 - -Source file: `xil/xil_ChipScopeICON.vhdl `_ - -.. seealso:: - - :doc:`Using PoC -> Synthesis ` - For how to run synthesis with PoC and CoreGenerator. - - - diff --git a/docs/PoC/xil/xil_DRP_BusMux.rst b/docs/PoC/xil/xil_DRP_BusMux.rst deleted file mode 100644 index f5d79d77..00000000 --- a/docs/PoC/xil/xil_DRP_BusMux.rst +++ /dev/null @@ -1,20 +0,0 @@ - -xil_DRP_BusMux -############## - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/xil/xil_DRP_BusMux.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 42-65 - -Source file: `xil/xil_DRP_BusMux.vhdl `_ - - - diff --git a/docs/PoC/xil/xil_DRP_BusSync.rst b/docs/PoC/xil/xil_DRP_BusSync.rst deleted file mode 100644 index 31baf6b0..00000000 --- a/docs/PoC/xil/xil_DRP_BusSync.rst +++ /dev/null @@ -1,20 +0,0 @@ - -xil_DRP_BusSync -############### - -.. TODO:: No documentation available. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/xil/xil_DRP_BusSync.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 40-58 - -Source file: `xil/xil_DRP_BusSync.vhdl `_ - - - diff --git a/docs/PoC/xil/xil_ICAP.rst b/docs/PoC/xil/xil_ICAP.rst deleted file mode 100644 index b445d6a9..00000000 --- a/docs/PoC/xil/xil_ICAP.rst +++ /dev/null @@ -1,25 +0,0 @@ - -xil_ICAP -######## - -This module wraps Xilinx "Internal Configuration Access Port" (ICAP) primitives in a generic -module. |br| -Supported devices are: - * Spartan-6 - * Virtex-4, Virtex-5, Virtex-6 - * Series-7 (Artix-7, Kintex-7, Virtex-7, Zynq-7000) - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/xil/xil_ICAP.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 47-66 - -Source file: `xil/xil_ICAP.vhdl `_ - - - diff --git a/docs/PoC/xil/xil_Reconfigurator.rst b/docs/PoC/xil/xil_Reconfigurator.rst deleted file mode 100644 index 99f35b93..00000000 --- a/docs/PoC/xil/xil_Reconfigurator.rst +++ /dev/null @@ -1,28 +0,0 @@ - -xil_Reconfigurator -################## - -Many complex primitives in a Xilinx device offer a Dynamic Reconfiguration -Port (DRP) to reconfigure a primitive at runtime without reconfiguring the -whole FPGA. - -This module is a DRP master that can be pre-configured at compile time with -different configuration sets. The configuration sets are mapped into a ROM. -The user can select a stored configuration with ``ConfigSelect``. Sending a -strobe to ``Reconfig`` will start the reconfiguration process. The operation -completes with another strobe on ``ReconfigDone``. - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/xil/xil_Reconfigurator.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 51-72 - -Source file: `xil/xil_Reconfigurator.vhdl `_ - - - diff --git a/docs/PoC/xil/xil_SystemMonitor_Series7.rst b/docs/PoC/xil/xil_SystemMonitor_Series7.rst deleted file mode 100644 index 23d050ce..00000000 --- a/docs/PoC/xil/xil_SystemMonitor_Series7.rst +++ /dev/null @@ -1,37 +0,0 @@ - -xil_SystemMonitor_Series7 -######################### - -This module wraps a Series-7 XADC to report if preconfigured temperature values -are overrun. The XADC was formerly known as "System Monitor". - -.. rubric:: Temperature Curve - -.. code-block:: none - - | /-----\ - Temp_ov on=80 | - - - - - - /-------/ \ - | / | \ - Temp_ov off=60 | - - - - - / - - - - | - - - - \----\ - | / | |\ - | / | | \ - Temp_us on=35 | - /---/ | | \ - Temp_us off=30 | - / - -|- - - - - - |- - - - - - - |- -\------\ - | / | | | \ - ----------------|--------|------------|--------------|-----------|-------- - pwm = | min | medium | max | medium | min - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/xil/xil_SystemMonitor_Series7.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 56-66 - -Source file: `xil/xil_SystemMonitor_Series7.vhdl `_ - - - diff --git a/docs/PoC/xil/xil_SystemMonitor_Virtex6.rst b/docs/PoC/xil/xil_SystemMonitor_Virtex6.rst deleted file mode 100644 index a56624dc..00000000 --- a/docs/PoC/xil/xil_SystemMonitor_Virtex6.rst +++ /dev/null @@ -1,37 +0,0 @@ - -xil_SystemMonitor_Virtex6 -######################### - -This module wraps a Virtex-6 System Monitor primitive to report if preconfigured -temperature values are overrun. - -.. rubric:: Temperature Curve - -.. code-block:: none - - | /-----\ - Temp_ov on=80 | - - - - - - /-------/ \ - | / | \ - Temp_ov off=60 | - - - - - / - - - - | - - - - \----\ - | / | |\ - | / | | \ - Temp_us on=35 | - /---/ | | \ - Temp_us off=30 | - / - -|- - - - - - |- - - - - - - |- -\------\ - | / | | | \ - ----------------|--------|------------|--------------|-----------|-------- - pwm = | min | medium | max | medium | min - - - -.. rubric:: Entity Declaration: - -.. literalinclude:: ../../../src/xil/xil_SystemMonitor_Virtex6.vhdl - :language: vhdl - :tab-width: 2 - :linenos: - :lines: 56-66 - -Source file: `xil/xil_SystemMonitor_Virtex6.vhdl `_ - - - diff --git a/py/PoC/__init__.py b/docs/PoCSphinx.py similarity index 65% rename from py/PoC/__init__.py rename to docs/PoCSphinx.py index 78c2cfdc..0bdc0e5d 100644 --- a/py/PoC/__init__.py +++ b/docs/PoCSphinx.py @@ -3,19 +3,18 @@ # kate: tab-width 2; replace-tabs off; indent-width 2; # # ============================================================================== -# Authors: Patrick Lehmann +# Authors: Patrick Lehmann # -# Python Sub Module: Saves The PoC-Library configuration as python source code. +# Python Main Module: Entry point for Sphinx analysis tools (e.g. autoprogram). # # Description: # ------------------------------------ -# TODO: -# +# Undocumented # # License: # ============================================================================== -# Copyright 2007-2015 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Copyright 2007-2016 Technische Universitaet Dresden - Germany +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -25,22 +24,17 @@ # # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, +# distributed under the License is distributed on an "AS IS" BASIS,default # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # See the License for the specific language governing permissions and # limitations under the License. # ============================================================================== +# +from sys import path as sys_path -# entry point -if __name__ != "__main__": - # place library initialization code here - pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("The PoC-Library - Repository Service Tool") - -# load dependencies - +sys_path.append("../py") -__POC_SOLUTION_KEYWORD__ = "Solution" -__POC_PROJECT_KEYWORD__ = "Project" +from PoC import PileOfCores +# entry point +parser = PileOfCores(False, False, False, True, sphinx=True).MainParser diff --git a/docs/PyInfrastructure/.gitempty b/docs/PyInfrastructure/.gitempty new file mode 100644 index 00000000..e69de29b diff --git a/docs/PyInfrastructure/index.rst b/docs/PyInfrastructure/index.rst new file mode 100644 index 00000000..50700416 --- /dev/null +++ b/docs/PyInfrastructure/index.rst @@ -0,0 +1,25 @@ + +Python Infrastructure +##################### + +.. toctree:: + + PoC + + +.. toctree:: + + Base + Compiler + DataBase + Parser + Simulator + ToolChains + lib + +.. # + automodule:: PoC + :members: + :undoc-members: + :inherited-members: + :show-inheritance: diff --git a/docs/QuickStart.rst b/docs/QuickStart.rst index 8e12e863..1ea4990e 100644 --- a/docs/QuickStart.rst +++ b/docs/QuickStart.rst @@ -1,15 +1,55 @@ +.. _QUICK: + +.. raw:: html + + + +.. |kbd-Y| raw:: html + + Y + +.. |kbd-N| raw:: html + + N + +.. |kbd-P| raw:: html + + P + +.. |kbd-Return| raw:: html + + Return Quick Start Guide ################# -This **quick start guide** gives a fast and simple introduction into PoC. All -topics can be found in the :doc:`Using PoC ` section with much -more details and examples. +This **Quick Start Guide** gives a fast and simple introduction into PoC. All +topics can be found in the :ref:`Using PoC ` section with much more +details and examples. .. contents:: Contents of this Page :local: +.. _QUICK:Requirements: + Requirements and Dependencies ***************************** @@ -17,13 +57,13 @@ The PoC-Library comes with some scripts to ease most of the common tasks, like running testbenches or generating IP cores. PoC uses Python 3 as a platform independent scripting environment. All Python scripts are wrapped in Bash or PowerShell scripts, to hide some platform specifics of Darwin, Linux or Windows. -See :doc:`/UsingPoC/Requirements` for further details. +See :ref:`USING:Require` for further details. .. rubric:: PoC requires: -* A :doc:`supported synthesis tool chain `, if you want to synthezise IP cores. -* A :doc:`supported simulator too chain `, if you want to simulate IP cores. +* A :ref:`supported synthesis tool chain `, if you want to synthezise IP cores. +* A :ref:`supported simulator too chain `, if you want to simulate IP cores. * The **Python 3** programming language and runtime, if you want to use PoC's infrastructure. * A shell to execute shell scripts: @@ -33,31 +73,53 @@ See :doc:`/UsingPoC/Requirements` for further details. .. rubric:: PoC optionally requires: -* **Git command line** tools or +* **Git** command line tools or * **Git User Interface**, if you want to check out the latest 'master' or 'release' branch. .. rubric:: PoC depends on third part libraries: -* `Cocotb `_ |br| +.. |gh-cocotb| image:: _static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/potentialventures/cocotb + :alt: Source Code on GitHub +.. |gh-osvvm| image:: _static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/JimLewis/OSVVM + :alt: Source Code on GitHub +.. |gh-uvvm| image:: _static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/UVVM/UVVM_All + :alt: Source Code on GitHub +.. |gh-vunit| image:: _static/logos/GitHub-Mark-32px.png + :scale: 40 + :target: https://github.com/VUnit/vunit + :alt: Source Code on GitHub + +* :ref:`THIRD:Cocotb` |gh-cocotb| |br| A coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python. -* `OS-VVM `_ |br| +* :ref:`THIRD:OSVVM` |gh-osvvm| |br| Open Source VHDL Verification Methodology. -* `VUnit `_ |br| +* :ref:`THIRD:UVVM` |gh-uvvm| |br| + Universal VHDL Verification Methodology. +* :ref:`THIRD:VUnit` |gh-vunit| |br| An unit testing framework for VHDL. All dependencies are available as GitHub repositories and are linked to PoC as Git submodules into the `PoCRoot\\lib `_ -directory. See :doc:`Third Party Libraries ` for more details on these libraries. +directory. See :ref:`Third Party Libraries ` for more details on these +libraries. +.. _QUICK:Download: + Download ******** The PoC-Library can be downloaded as a `zip-file `_ (latest 'master' branch), cloned with ``git clone`` or embedded with ``git submodule add`` from GitHub. GitHub offers HTTPS and SSH as transfer -protocols. See the :doc:`Download ` page for further +protocols. See the :ref:`Download ` page for further details. The installation directory is referred to as ``PoCRoot``. +----------+---------------------------------------------------------------------+ @@ -69,6 +131,8 @@ details. The installation directory is referred to as ``PoCRoot``. +----------+---------------------------------------------------------------------+ +.. _QUICK:Configuration: + Configuring PoC on a Local System ********************************* @@ -76,7 +140,7 @@ To explore PoC's full potential, it's required to configure some paths and synthesis or simulation tool chains. The following commands start a guided configuration process. Please follow the instructions on screen. It's possible to relaunch the process at any time, for example to register new tools or to -update tool versions. See :doc:`Configuration ` for +update tool versions. See :ref:`Configuration ` for more details. Run the following command line instructions to configure PoC on your local system: @@ -85,10 +149,14 @@ your local system: cd PoCRoot .\poc.ps1 configure -Use the keyboard buttons: :kbd:`Y` to accept, :kbd:`N` to decline, :kbd:`P` to -skip/pass a step and :kbd:`Return` to accept a default value displayed in brackets. + +Use the keyboard buttons: |kbd-Y| to accept, |kbd-N| to decline, |kbd-P| to +skip/pass a step and |kbd-Return| to accept a default value displayed in +brackets. +.. _QUICK:Integration: + Integration *********** @@ -106,7 +174,7 @@ clone the PoC-Library as a Git `submodule `. -.. code-block:: powershell +.. code-block:: PowerShell cd ProjectRoot mkdir lib | cd @@ -117,13 +185,14 @@ list of steps can be found at :doc:`Integration `. git add .gitmodules lib\PoC git commit -m "Added new git submodule PoC in 'lib\PoC' (PoC-Library)." + .. rubric:: 2. Configuring PoC The PoC-Library should be configured to explore its full potential. See :doc:`Configuration ` for more details. The following command lines will start the configuration process: -.. code-block:: powershell +.. code-block:: PowerShell cd ProjectRoot .\lib\PoC\poc.ps1 configure @@ -137,7 +206,7 @@ target information. Copy the following two template files into your project's source folder. Rename these files to \*.vhdl and configure the VHDL constants in the files: -.. code-block:: powershell +.. code-block:: PowerShell cd ProjectRoot cp lib\PoC\src\common\my_config.vhdl.template src\common\my_config.vhdl @@ -185,6 +254,8 @@ and if needed patch these IP cores. See :doc:`Synthesis ` for more details. +.. _QUICK:RunSimulation: + Run a Simulation **************** @@ -221,6 +292,8 @@ status (``... ERROR``, ``FAILED``, ``NO ASSERTS`` or ``PASSED``). See :doc:`Simulation ` for more details. +.. _QUICK:RunSynthesis: + Run a Synthesis *************** @@ -248,6 +321,8 @@ synthesized to a netlist. :alt: PowerShell console output after running PoC.arith.prng with XST. +.. _QUICK:Updating: + Updating ******** diff --git a/docs/References/CmdRefs/Compile-Altera-ps1.rst b/docs/References/CmdRefs/Compile-Altera-ps1.rst new file mode 100644 index 00000000..f15e9560 --- /dev/null +++ b/docs/References/CmdRefs/Compile-Altera-ps1.rst @@ -0,0 +1,65 @@ +compile-altera.ps1 +------------------ + +.. program:: compile-altera.ps1 + +This script pre-compiles the Altera primitives. This script will generate all +outputs into a :file:`altera` directory. + + +.. rubric:: Supported Simulators + ++----------+--------------------------------------------+ +| Target | Description | ++==========+============================================+ +| All | pre-compile for all simulators | ++----------+--------------------------------------------+ +| GHDL | pre-compile for the GHDL simulator | ++----------+--------------------------------------------+ +| Questa | pre-compile for Metor Graphics QuestaSim | ++----------+--------------------------------------------+ + + +.. rubric:: Command Line Options + +.. option:: -Help + + Show the embedded help page(s). + +.. option:: -Clean + + Clean up directory before analyzing. + +.. option:: -All + + Pre-compile all libraries and packages for all simulators. + +.. option:: -GHDL + + Pre-compile the Altera Quartus libraries for GHDL. + +.. option:: -Questa + + Pre-compile the Altera Quartus libraries for QuestaSim. + + +.. rubric:: Additional Options for GHDL + +.. option:: -VHDL93 + + For GHDL only: Set VHDL Standard to '93. + +.. option:: -VHDL2008 + + For GHDL only: Set VHDL Standard to '08. + + +.. rubric:: GHDL Notes + +Not all primitives and macros are available as plain VHDL source code. Encrypted +primitives and netlists cannot be pre-compiled by GHDL. + + +.. rubric:: QuestaSim Notes + +The pre-compilation for QuestaSim uses a build in program from Altera. diff --git a/docs/References/CmdRefs/Compile-Altera-sh.rst b/docs/References/CmdRefs/Compile-Altera-sh.rst new file mode 100644 index 00000000..72b37394 --- /dev/null +++ b/docs/References/CmdRefs/Compile-Altera-sh.rst @@ -0,0 +1,65 @@ +compile-altera.sh +----------------- + +.. program:: compile-altera.sh + +This script pre-compiles the Altera primitives. This script will generate all +outputs into a :file:`altera` directory. + + +.. rubric:: Supported Simulators + ++----------+--------------------------------------------+ +| Target | Description | ++==========+============================================+ +| All | pre-compile for all simulators | ++----------+--------------------------------------------+ +| GHDL | pre-compile for the GHDL simulator | ++----------+--------------------------------------------+ +| Questa | pre-compile for Metor Graphics QuestaSim | ++----------+--------------------------------------------+ + + +.. rubric:: Command Line Options + +.. option:: --help + + Show the embedded help page(s). + +.. option:: --clean + + Clean up directory before analyzing. + +.. option:: --all + + Pre-compile all libraries and packages for all simulators. + +.. option:: --ghdl + + Pre-compile the Altera Quartus libraries for GHDL. + +.. option:: --questa + + Pre-compile the Altera Quartus libraries for QuestaSim. + + +.. rubric:: Additional Options for GHDL + +.. option:: --vhdl93 + + For GHDL only: Set VHDL Standard to '93. + +.. option:: --vhdl2008 + + For GHDL only: Set VHDL Standard to '08. + + +.. rubric:: GHDL Notes + +Not all primitives and macros are available as plain VHDL source code. Encrypted +primitives and netlists cannot be pre-compiled by GHDL. + + +.. rubric:: QuestaSim Notes + +The pre-compilation for QuestaSim uses a build in program from Altera. diff --git a/docs/References/CmdRefs/Compile-Lattice-ps1.rst b/docs/References/CmdRefs/Compile-Lattice-ps1.rst new file mode 100644 index 00000000..228c5470 --- /dev/null +++ b/docs/References/CmdRefs/Compile-Lattice-ps1.rst @@ -0,0 +1,65 @@ +compile-lattice.ps1 +------------------- + +.. program:: compile-lattice.ps1 + +This script pre-compiles the Lattice primitives. This script will generate all +outputs into a :file:`lattice` directory. + + +.. rubric:: Supported Simulators + ++----------+--------------------------------------------+ +| Target | Description | ++==========+============================================+ +| All | pre-compile for all simulators | ++----------+--------------------------------------------+ +| GHDL | pre-compile for the GHDL simulator | ++----------+--------------------------------------------+ +| Questa | pre-compile for Metor Graphics QuestaSim | ++----------+--------------------------------------------+ + + +.. rubric:: Command Line Options + +.. option:: -Help + + Show the embedded help page(s). + +.. option:: -Clean + + Clean up directory before analyzing. + +.. option:: -All + + Pre-compile all libraries and packages for all simulators. + +.. option:: -GHDL + + Pre-compile the Altera Quartus libraries for GHDL. + +.. option:: -Questa + + Pre-compile the Altera Quartus libraries for QuestaSim. + + +.. rubric:: Additional Options for GHDL + +.. option:: -VHDL93 + + For GHDL only: Set VHDL Standard to '93. + +.. option:: -VHDL2008 + + For GHDL only: Set VHDL Standard to '08. + + +.. rubric:: GHDL Notes + +Not all primitives and macros are available as plain VHDL source code. Encrypted +primitives and netlists cannot be pre-compiled by GHDL. + + +.. rubric:: QuestaSim Notes + +The pre-compilation for QuestaSim uses a build in program from Lattice. diff --git a/docs/References/CmdRefs/Compile-Lattice-sh.rst b/docs/References/CmdRefs/Compile-Lattice-sh.rst new file mode 100644 index 00000000..6f8df6b9 --- /dev/null +++ b/docs/References/CmdRefs/Compile-Lattice-sh.rst @@ -0,0 +1,65 @@ +compile-lattice.sh +------------------ + +.. program:: compile-lattice.sh + +This script pre-compiles the Lattice primitives. This script will generate all +outputs into a :file:`lattice` directory. + + +.. rubric:: Supported Simulators + ++----------+--------------------------------------------+ +| Target | Description | ++==========+============================================+ +| All | pre-compile for all simulators | ++----------+--------------------------------------------+ +| GHDL | pre-compile for the GHDL simulator | ++----------+--------------------------------------------+ +| Questa | pre-compile for Metor Graphics QuestaSim | ++----------+--------------------------------------------+ + + +.. rubric:: Command Line Options + +.. option:: --help + + Show the embedded help page(s). + +.. option:: --clean + + Clean up directory before analyzing. + +.. option:: --all + + Pre-compile all libraries and packages for all simulators. + +.. option:: --ghdl + + Pre-compile the Altera Quartus libraries for GHDL. + +.. option:: --questa + + Pre-compile the Altera Quartus libraries for QuestaSim. + + +.. rubric:: Additional Options for GHDL + +.. option:: --vhdl93 + + For GHDL only: Set VHDL Standard to '93. + +.. option:: --vhdl2008 + + For GHDL only: Set VHDL Standard to '08. + + +.. rubric:: GHDL Notes + +Not all primitives and macros are available as plain VHDL source code. Encrypted +primitives and netlists cannot be pre-compiled by GHDL. + + +.. rubric:: QuestaSim Notes + +The pre-compilation for QuestaSim uses a build in program from Lattice. diff --git a/docs/References/CmdRefs/Compile-OSVVM-ps1.rst b/docs/References/CmdRefs/Compile-OSVVM-ps1.rst new file mode 100644 index 00000000..2eda7260 --- /dev/null +++ b/docs/References/CmdRefs/Compile-OSVVM-ps1.rst @@ -0,0 +1,54 @@ +compile-osvvm.ps1 +----------------- + +.. program:: compile-osvvm.ps1 + +This script pre-compiles the OSVVM packages. This script will generate all +outputs into a :file:`osvvm` directory. + + +.. rubric:: Supported Simulators + ++----------+--------------------------------------------+ +| Target | Description | ++==========+============================================+ +| All | pre-compile for all simulators | ++----------+--------------------------------------------+ +| GHDL | pre-compile for the GHDL simulator | ++----------+--------------------------------------------+ +| Questa | pre-compile for Metor Graphics QuestaSim | ++----------+--------------------------------------------+ + + +.. rubric:: Command Line Options + +.. option:: -Help + + Show the embedded help page(s). + +.. option:: -Clean + + Clean up directory before analyzing. + +.. option:: -All + + Pre-compile all libraries and packages for all simulators. + +.. option:: -GHDL + + Pre-compile the Altera Quartus libraries for GHDL. + +.. option:: -Questa + + Pre-compile the Altera Quartus libraries for QuestaSim. + + +.. rubric:: Additional Options for GHDL + +.. option:: -VHDL93 + + For GHDL only: Set VHDL Standard to '93. + +.. option:: -VHDL2008 + + For GHDL only: Set VHDL Standard to '08. diff --git a/docs/References/CmdRefs/Compile-OSVVM-sh.rst b/docs/References/CmdRefs/Compile-OSVVM-sh.rst new file mode 100644 index 00000000..8b9f1334 --- /dev/null +++ b/docs/References/CmdRefs/Compile-OSVVM-sh.rst @@ -0,0 +1,54 @@ +compile-osvvm.sh +---------------- + +.. program:: compile-osvvm.sh + +This script pre-compiles the OSVVM packages. This script will generate all +outputs into a :file:`osvvm` directory. + + +.. rubric:: Supported Simulators + ++----------+--------------------------------------------+ +| Target | Description | ++==========+============================================+ +| All | pre-compile for all simulators | ++----------+--------------------------------------------+ +| GHDL | pre-compile for the GHDL simulator | ++----------+--------------------------------------------+ +| Questa | pre-compile for Metor Graphics QuestaSim | ++----------+--------------------------------------------+ + + +.. rubric:: Command Line Options + +.. option:: --help + + Show the embedded help page(s). + +.. option:: --clean + + Clean up directory before analyzing. + +.. option:: --all + + Pre-compile all libraries and packages for all simulators. + +.. option:: --ghdl + + Pre-compile the Altera Quartus libraries for GHDL. + +.. option:: --questa + + Pre-compile the Altera Quartus libraries for QuestaSim. + + +.. rubric:: Additional Options for GHDL + +.. option:: --vhdl93 + + For GHDL only: Set VHDL Standard to '93. + +.. option:: --vhdl2008 + + For GHDL only: Set VHDL Standard to '08. diff --git a/docs/References/CmdRefs/Compile-UVVM-ps1.rst b/docs/References/CmdRefs/Compile-UVVM-ps1.rst new file mode 100644 index 00000000..41c34f50 --- /dev/null +++ b/docs/References/CmdRefs/Compile-UVVM-ps1.rst @@ -0,0 +1,54 @@ +compile-uvvm.ps1 +---------------- + +.. program:: compile-uvvm.ps1 + +This script pre-compiles the UVVM framework. This script will generate all +outputs into a :file:`uvvm` directory. + + +.. rubric:: Supported Simulators + ++----------+--------------------------------------------+ +| Target | Description | ++==========+============================================+ +| All | pre-compile for all simulators | ++----------+--------------------------------------------+ +| GHDL | pre-compile for the GHDL simulator | ++----------+--------------------------------------------+ +| Questa | pre-compile for Metor Graphics QuestaSim | ++----------+--------------------------------------------+ + + +.. rubric:: Command Line Options + +.. option:: -Help + + Show the embedded help page(s). + +.. option:: -Clean + + Clean up directory before analyzing. + +.. option:: -All + + Pre-compile all libraries and packages for all simulators. + +.. option:: -GHDL + + Pre-compile the Altera Quartus libraries for GHDL. + +.. option:: -Questa + + Pre-compile the Altera Quartus libraries for QuestaSim. + + +.. rubric:: Additional Options for GHDL + +.. option:: -VHDL93 + + For GHDL only: Set VHDL Standard to '93. + +.. option:: -VHDL2008 + + For GHDL only: Set VHDL Standard to '08. diff --git a/docs/References/CmdRefs/Compile-UVVM-sh.rst b/docs/References/CmdRefs/Compile-UVVM-sh.rst new file mode 100644 index 00000000..0a3fd45f --- /dev/null +++ b/docs/References/CmdRefs/Compile-UVVM-sh.rst @@ -0,0 +1,54 @@ +compile-uvvm.sh +--------------- + +.. program:: compile-uvvm.sh + +This script pre-compiles the UVVM framework. This script will generate all +outputs into a :file:`uvvm` directory. + + +.. rubric:: Supported Simulators + ++----------+--------------------------------------------+ +| Target | Description | ++==========+============================================+ +| All | pre-compile for all simulators | ++----------+--------------------------------------------+ +| GHDL | pre-compile for the GHDL simulator | ++----------+--------------------------------------------+ +| Questa | pre-compile for Metor Graphics QuestaSim | ++----------+--------------------------------------------+ + + +.. rubric:: Command Line Options + +.. option:: --help + + Show the embedded help page(s). + +.. option:: --clean + + Clean up directory before analyzing. + +.. option:: --all + + Pre-compile all libraries and packages for all simulators. + +.. option:: --ghdl + + Pre-compile the Altera Quartus libraries for GHDL. + +.. option:: --questa + + Pre-compile the Altera Quartus libraries for QuestaSim. + + +.. rubric:: Additional Options for GHDL + +.. option:: --vhdl93 + + For GHDL only: Set VHDL Standard to '93. + +.. option:: --vhdl2008 + + For GHDL only: Set VHDL Standard to '08. diff --git a/docs/References/CmdRefs/Compile-Xilinx-ISE-ps1.rst b/docs/References/CmdRefs/Compile-Xilinx-ISE-ps1.rst new file mode 100644 index 00000000..9b993b4d --- /dev/null +++ b/docs/References/CmdRefs/Compile-Xilinx-ISE-ps1.rst @@ -0,0 +1,70 @@ +compile-xilinx-ise.ps1 +---------------------- + +.. program:: compile-xilinx-ise.ps1 + +This script pre-compiles the Xilinx primitives. Because Xilinx offers two tool +chains (ISE, Vivado), this script will generate all outputs into a +:file:`xilinx-ise` directory and a symlink to :file:`xilinx` will be created. +This eases the coexistence of pre-compiled primitives from ISE and Vivado. The +symlink can be changed by the user or via :option:`-ReLink`. + +.. rubric:: Supported Simulators + ++----------+--------------------------------------------+ +| Target | Description | ++==========+============================================+ +| All | pre-compile for all simulators | ++----------+--------------------------------------------+ +| GHDL | pre-compile for the GHDL simulator | ++----------+--------------------------------------------+ +| Questa | pre-compile for Metor Graphics QuestaSim | ++----------+--------------------------------------------+ + +.. rubric:: Command Line Options + +.. option:: -Help + + Show the embedded help page(s). + +.. option:: -Clean + + Clean up directory before analyzing. + +.. option:: -All + + Pre-compile all libraries and packages for all simulators. + +.. option:: -GHDL + + Pre-compile the Altera Quartus libraries for GHDL. + +.. option:: -Questa + + Pre-compile the Altera Quartus libraries for QuestaSim. + +.. option:: -ReLink + + Change the 'xilinx' symlink to 'xilinx-ise'. + + +.. rubric:: Additional Options for GHDL + +.. option:: -VHDL93 + + For GHDL only: Set VHDL Standard to '93. + +.. option:: -VHDL2008 + + For GHDL only: Set VHDL Standard to '08. + + +.. rubric:: GHDL Notes + +Not all primitives and macros are available as plain VHDL source code. Encrypted +SecureIP primitives and netlists cannot be pre-compiled by GHDL. + + +.. rubric:: QuestaSim Notes + +The pre-compilation for QuestaSim uses a build in program from Xilinx. diff --git a/docs/References/CmdRefs/Compile-Xilinx-ISE-sh.rst b/docs/References/CmdRefs/Compile-Xilinx-ISE-sh.rst new file mode 100644 index 00000000..36de7540 --- /dev/null +++ b/docs/References/CmdRefs/Compile-Xilinx-ISE-sh.rst @@ -0,0 +1,67 @@ +compile-xilinx-ise.sh +--------------------- + +.. program:: compile-xilinx-ise.sh + +This script pre-compiles the Xilinx primitives. Because Xilinx offers two tool +chains (ISE, Vivado), this script will generate all outputs into a +:file:`xilinx-ise` directory and a symlink to :file:`xilinx` will be created. +This eases the coexistence of pre-compiled primitives from ISE and Vivado. + +.. The symlink can be changed by the user or via :option:`--relink`. + +.. rubric:: Supported Simulators + ++----------+--------------------------------------------+ +| Target | Description | ++==========+============================================+ +| All | pre-compile for all simulators | ++----------+--------------------------------------------+ +| GHDL | pre-compile for the GHDL simulator | ++----------+--------------------------------------------+ +| Questa | pre-compile for Metor Graphics QuestaSim | ++----------+--------------------------------------------+ + +.. rubric:: Command Line Options + +.. option:: --help + + Show the embedded help page(s). + +.. option:: --clean + + Clean up directory before analyzing. + +.. option:: --all + + Pre-compile all libraries and packages for all simulators. + +.. option:: --ghdl + + Pre-compile the Altera Quartus libraries for GHDL. + +.. option:: --questa + + Pre-compile the Altera Quartus libraries for QuestaSim. + + +.. rubric:: Additional Options for GHDL + +.. option:: --vhdl93 + + For GHDL only: Set VHDL Standard to '93. + +.. option:: --vhdl2008 + + For GHDL only: Set VHDL Standard to '08. + + +.. rubric:: GHDL Notes + +Not all primitives and macros are available as plain VHDL source code. Encrypted +SecureIP primitives and netlists cannot be pre-compiled by GHDL. + + +.. rubric:: QuestaSim Notes + +The pre-compilation for QuestaSim uses a build in program from Xilinx. diff --git a/docs/References/CmdRefs/Compile-Xilinx-Vivado-ps1.rst b/docs/References/CmdRefs/Compile-Xilinx-Vivado-ps1.rst new file mode 100644 index 00000000..59a3aee7 --- /dev/null +++ b/docs/References/CmdRefs/Compile-Xilinx-Vivado-ps1.rst @@ -0,0 +1,72 @@ +compile-xilinx-vivado.ps1 +------------------------- + +.. program:: compile-xilinx-vivado.ps1 + +This script pre-compiles the Xilinx primitives. Because Xilinx offers two tool +chains (ISE, Vivado), this script will generate all outputs into a +:file:`xilinx-vivado` directory and a symlink to :file:`xilinx` will be created. +This eases the coexistence of pre-compiled primitives from ISE and Vivado. The +symlink can be changed by the user or via :option:`-ReLink`. + + +.. rubric:: Supported Simulators + ++----------+--------------------------------------------+ +| Target | Description | ++==========+============================================+ +| All | pre-compile for all simulators | ++----------+--------------------------------------------+ +| GHDL | pre-compile for the GHDL simulator | ++----------+--------------------------------------------+ +| Questa | pre-compile for Metor Graphics QuestaSim | ++----------+--------------------------------------------+ + + +.. rubric:: Command Line Options + +.. option:: -Help + + Show the embedded help page(s). + +.. option:: -Clean + + Clean up directory before analyzing. + +.. option:: -All + + Pre-compile all libraries and packages for all simulators. + +.. option:: -GHDL + + Pre-compile the Altera Quartus libraries for GHDL. + +.. option:: -Questa + + Pre-compile the Altera Quartus libraries for QuestaSim. + +.. option:: -ReLink + + Change the 'xilinx' symlink to 'xilinx-vivado'. + + +.. rubric:: Additional Options for GHDL + +.. option:: -VHDL93 + + For GHDL only: Set VHDL Standard to '93. + +.. option:: -VHDL2008 + + For GHDL only: Set VHDL Standard to '08. + + +.. rubric:: GHDL Notes + +Not all primitives and macros are available as plain VHDL source code. Encrypted +SecureIP primitives and netlists cannot be pre-compiled by GHDL. + + +.. rubric:: QuestaSim Notes + +The pre-compilation for QuestaSim uses a build in program from Xilinx. diff --git a/docs/References/CmdRefs/Compile-Xilinx-Vivado-sh.rst b/docs/References/CmdRefs/Compile-Xilinx-Vivado-sh.rst new file mode 100644 index 00000000..73d32f49 --- /dev/null +++ b/docs/References/CmdRefs/Compile-Xilinx-Vivado-sh.rst @@ -0,0 +1,69 @@ +compile-xilinx-vivado.sh +------------------------ + +.. program:: compile-xilinx-vivado.sh + +This script pre-compiles the Xilinx primitives. Because Xilinx offers two tool +chains (ISE, Vivado), this script will generate all outputs into a +:file:`xilinx-vivado` directory and a symlink to :file:`xilinx` will be created. +This eases the coexistence of pre-compiled primitives from ISE and Vivado. + +.. The symlink can be changed by the user or via :option:`--relink`. + + +.. rubric:: Supported Simulators + ++----------+--------------------------------------------+ +| Target | Description | ++==========+============================================+ +| All | pre-compile for all simulators | ++----------+--------------------------------------------+ +| GHDL | pre-compile for the GHDL simulator | ++----------+--------------------------------------------+ +| Questa | pre-compile for Metor Graphics QuestaSim | ++----------+--------------------------------------------+ + + +.. rubric:: Command Line Options + +.. option:: --help + + Show the embedded help page(s). + +.. option:: --clean + + Clean up directory before analyzing. + +.. option:: --all + + Pre-compile all libraries and packages for all simulators. + +.. option:: --ghdl + + Pre-compile the Altera Quartus libraries for GHDL. + +.. option:: --questa + + Pre-compile the Altera Quartus libraries for QuestaSim. + + +.. rubric:: Additional Options for GHDL + +.. option:: --vhdl93 + + For GHDL only: Set VHDL Standard to '93. + +.. option:: --vhdl2008 + + For GHDL only: Set VHDL Standard to '08. + + +.. rubric:: GHDL Notes + +Not all primitives and macros are available as plain VHDL source code. Encrypted +SecureIP primitives and netlists cannot be pre-compiled by GHDL. + + +.. rubric:: QuestaSim Notes + +The pre-compilation for QuestaSim uses a build in program from Xilinx. diff --git a/docs/References/CmdRefs/Compile.rst b/docs/References/CmdRefs/Compile.rst new file mode 100644 index 00000000..e6af334e --- /dev/null +++ b/docs/References/CmdRefs/Compile.rst @@ -0,0 +1,86 @@ +.. _CmdRef:PreCompile: + +Pre-compile Scripts +################### + +The following scripts can be used to pre-compile vendor's primitives or third +party libraries. Pre-compile vendor primitives are required for vendor specific +simulations or if no generic IP core implementation is available. Third party +libraries are usually used as simulation helpers and thus needed by many +testbenches. + +The pre-compiled packages and libraries are stored in the directory :file:`/temp/precompiled/`. +Per simulator, one :file:`/` sub-directory is created. Each simulator +directory in turn contains library directories, which may be grouped by the +library vendor's name: :file:`[/]/`. + +So for example: :ref:`THIRD:OSVVM` pre-compiled with GHDL is stored in +:file:`/temp/precompiled/ghdl/osvvm/`. Note OSVVM is a single library and thus +no vendor directory is used to group the generated files. GHDL will also create +VHDL language revision sub-directories like :file:`v93/` or :file:`v08/`. + +Currently the provided scripts support 2 simulator targets and one combined +target: + ++----------+--------------------------------------------+ +| Target | Description | ++==========+============================================+ +| All | pre-compile for all simulators | ++----------+--------------------------------------------+ +| GHDL | pre-compile for the GHDL simulator | ++----------+--------------------------------------------+ +| Questa | pre-compile for Metor Graphics QuestaSim | ++----------+--------------------------------------------+ + +The GHDL simulator distinguishes various VHDL language revisions and thus can +pre-compile the source for these language revisions into separate output +directories. The command line switch ``-All``/``--all`` will build the libraries +for all major VHDL revisions (93, 2008). + + +.. rubric:: Pre-compile Altera Libraries + +.. toctree:: + + Compile-Altera-sh + Compile-Altera-ps1 + + +.. rubric:: Pre-compile Lattice Libraries + +.. toctree:: + + Compile-Lattice-sh + Compile-Lattice-ps1 + + +.. rubric:: Pre-compile OSVVM Libraries + +.. toctree:: + + Compile-OSVVM-sh + Compile-OSVVM-ps1 + + +.. rubric:: Pre-compile UVVM Libraries + +.. toctree:: + + Compile-UVVM-sh + Compile-UVVM-ps1 + + +.. rubric:: Pre-compile Xilinx ISE Libraries + +.. toctree:: + + Compile-Xilinx-ISE-sh + Compile-Xilinx-ISE-ps1 + + +.. rubric:: Pre-compile Xilinx Vivado Libraries + +.. toctree:: + + Compile-Xilinx-Vivado-sh + Compile-Xilinx-Vivado-ps1 diff --git a/docs/References/CmdRefs/PoC.rst b/docs/References/CmdRefs/PoC.rst new file mode 100644 index 00000000..99c9be03 --- /dev/null +++ b/docs/References/CmdRefs/PoC.rst @@ -0,0 +1,172 @@ +.. This files requires a Python module called 'PoCSphinx' to be located in the + docs root folder. It expects a variable 'parser' of type ArgumentParser. + +.. _CMDREF:PoC: + +Main Program (:file:`PoC.py`) +############################# + +The main program :file:`PoC.py` expects the environment variable +:envvar:`PoCRootDirectory` to be set. + + +.. autoprogram:: PoCSphinx:parser + :prog: PoC.py + :label: CMDREF: + + +.. foo :maxdepth: 1 + + ----------------------------- + + .. autoprogram:: PoCSphinx:parser + :start_command: add-solution + :label: CmdRef:poc-add-solution + + ----------------------------- + + .. autoprogram:: PoCSphinx:parser + :start_command: asim + :prog: PoC.py + :label: CmdRef:poc-asim + + ----------------------------- + + .. autoprogram:: PoCSphinx:parser + :start_command: cocotb + :prog: PoC.py foo + :label: CmdRef:poc-cocotb + + ----------------------------- + + .. autoprogram:: PoCSphinx:parser + :prog: PoC.py + :start_command: configure + :label: CmdRef:poc-configure + + ----------------------------- + + .. autoprogram:: PoCSphinx:parser + :prog: PoC.py + :start_command: coregen + :label: CmdRef:poc-coregen + + ----------------------------- + + .. autoprogram:: PoCSphinx:parser + :prog: PoC.py + :start_command: ghdl + :label: CmdRef:poc-ghdl + + ----------------------------- + + .. autoprogram:: PoCSphinx:parser + :prog: PoC.py + :start_command: help + :label: CmdRef:poc-help + + ----------------------------- + + .. autoprogram:: PoCSphinx:parser + :prog: PoC.py + :start_command: ise + :label: CmdRef:poc-ise + + ----------------------------- + + .. autoprogram:: PoCSphinx:parser + :prog: PoC.py + :start_command: isim + :label: CmdRef:poc-isim + + ----------------------------- + + .. autoprogram:: PoCSphinx:parser + :prog: PoC.py + :start_command: list-netlist + :label: CmdRef:poc-list-netlist + + ----------------------------- + + .. autoprogram:: PoCSphinx:parser + :prog: PoC.py + :start_command: list-project + :label: CmdRef:poc-list-project + + ----------------------------- + + .. autoprogram:: PoCSphinx:parser + :prog: PoC.py + :start_command: list-solution + :label: CmdRef:poc-list-solution + + ----------------------------- + + .. autoprogram:: PoCSphinx:parser + :prog: PoC.py + :start_command: list-testbench + :label: CmdRef:poc-list-testbench + + ----------------------------- + + .. autoprogram:: PoCSphinx:parser + :prog: PoC.py + :start_command: lse + :label: CmdRef:poc-lse + + ----------------------------- + + .. autoprogram:: PoCSphinx:parser + :prog: PoC.py + :start_command: quartus + :label: CmdRef:poc-quartus + + ----------------------------- + + .. autoprogram:: PoCSphinx:parser + :prog: PoC.py + :start_command: query + :label: CmdRef:poc-query + + ----------------------------- + + .. autoprogram:: PoCSphinx:parser + :prog: PoC.py + :start_command: remove-solution + :label: CmdRef:poc-remove-solution + + ----------------------------- + + .. autoprogram:: PoCSphinx:parser + :prog: PoC.py + :start_command: vivado + :label: CmdRef:poc-vivado + + ----------------------------- + + .. autoprogram:: PoCSphinx:parser + :prog: PoC.py + :start_command: vsim + :label: CmdRef:poc-vsim + + ----------------------------- + + .. autoprogram:: PoCSphinx:parser + :prog: PoC.py + :start_command: xci + :label: CmdRef:poc-xci + + ----------------------------- + + .. autoprogram:: PoCSphinx:parser + :prog: PoC.py + :start_command: xsim + :label: CmdRef:poc-xsim + + ----------------------------- + + .. autoprogram:: PoCSphinx:parser + :prog: PoC.py + :start_command: xst + :label: CmdRef:poc-xst + diff --git a/docs/References/CmdRefs/Wrapper.rst b/docs/References/CmdRefs/Wrapper.rst new file mode 100644 index 00000000..705d9069 --- /dev/null +++ b/docs/References/CmdRefs/Wrapper.rst @@ -0,0 +1,59 @@ +.. _CmdRef:Wrapper: + +PoC Wrapper Scripts +################### + +The PoC main program :program:`PoC.py` requires a prepared environment, which +needs to be setup by platform specific wrapper scripts written as shell +scripts language (PowerShell/Bash). Moreover, the main program requires a +supported Python version, so the wrapper script will search the best matching +language environment. + +The wrapper script offers the ability to hook in user-defined scripts to prepared +(before) and clean up the environment (after) a PoC execution. E.g. it's possible +to load the environment variable :envvar:`LM_LICENSE_FILE` for the FlexLM license +manager. + + +.. rubric:: Created Environment Variables + +.. envvar:: PoCRootDirectory + + The path to PoC's root directory. + +--------------------------------- + +poc.ps1 +======== + +.. program:: poc.ps1 + +:file:`PoC.ps1` is the wrapper for the Windows platform using a PowerShell script. +It can be debugged by adding the command line switch :option:`-D`. All parameters +are passed to :file:`PoC.py`. + +.. option:: -D + + Enabled debug mode in the wrapper script. + +.. describe:: Other arguments + + All remaining arguments are passed to :file:`PoC.py`. + + +poc.sh +====== + +.. program:: poc.sh + +:file:`PoC.sh` is the wrapper for Linux and Unix platforms using a Bash script. +It can be debugged by adding the command line switch :option:`-D`. All parameters +are passed to :file:`PoC.py`. + +.. option:: -D + + Enabled debug mode in the wrapper script. + +.. describe:: Other arguments + + All remaining arguments are passed to :file:`PoC.py`. diff --git a/docs/References/CommandReference.rst b/docs/References/CommandReference.rst index 5aea0ba5..c3f7ec09 100644 --- a/docs/References/CommandReference.rst +++ b/docs/References/CommandReference.rst @@ -1,32 +1,13 @@ +.. _CmdRef: Command Reference ################# -.. contents:: Contents of this Page +This is the command line option reference for all provided scripts +(Bash, PowerShell, Perl) and programs (Python) shipped with PoC. +.. toctree:: -Headline 4 -********************** - -Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. -At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor -sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et -accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet - - -Headline 5 -********************** - -Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. -At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor -sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et -accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet - - -Headline 6 -******************* - -Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. -At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor -sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et -accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet + CmdRefs/Wrapper + Main Program + CmdRefs/Compile diff --git a/docs/References/Database.rst b/docs/References/Database.rst new file mode 100644 index 00000000..21ef4b76 --- /dev/null +++ b/docs/References/Database.rst @@ -0,0 +1,299 @@ +.. _IPDB: + +IP Core Database +################ + +.. contents:: Contents of this Page + :local: + +Overview +******** + +PoC internal IP core database uses INI files and advanced interpolation rules +provided by ExtendedConfigParser_. The database consists of 5 *.ini files: + +* :file:`py\config.boards.ini` + This files contains all known :doc:`FPGA boards ` and + :doc:`FPGA devices `. +* :file:`py\config.defaults.ini` + This files contains all default options and values for all supported node + types. +* :file:`py\config.entity.ini` + This file contains all IP cores (entities) and theirs corresponding testbench + or netlist settings. +* :file:`py\config.private.ini` + This files is created by ``.\poc.ps1 configure`` and contains settings for the + local PoC installation. This files must not be shared with other PoC instances. + See :doc:`Configuring PoC's Infrastructure ` on how + to configure PoC on a local system. +* :file:`py\config.structure.ini` + Nodes in this file describe PoC's namespace tree and which IP cores are + assigned to which namespace. + +Additionally, the database refers to :ref:`*.files ` +and :ref:`*.rules ` files. The first file type describes, in +an imperative language, which files are needed to compile a simulation or to +run a synthesis. The latter file type contains patch instructions per IP core. +See :ref:`Files Formats ` for more details. + +.. _ExtendedConfigParser: https://github.com/Paebbels/ExtendedConfigParser + + +.. _IPDB:Structure: + +Database Structure +****************** + +The database is stored in multiple :ref:`INI files `, +which are merged in memory to a single configuration database. Each INI file +defines an associative array of *sections* and option lines. The content itself +is an associative array of *options* and values. Section names are inclosed in +square brackets ``[...]`` and allow simple case-sensitive strings as names. A +section name is followed by its section content, which consists of option lines. + +One option is stored per option line and consists of an option name and a value +separated by an equal sign ``=``. The option name is also a case-sensitive +simple string. The value is string, starts after the first non-whitespace +character and end before the newline character at the end of the line. The +content can be of any string, except for the newline characters. Support for +escape sequences depends on the option usage. + +Values containing ``${...}`` and ``%{...}`` are raw values, which need to be +interpolated by the ExtendedConfigParser. See `Value Interpolation`_ and +`Node Interpolation`_ for more details. + +Sections can have a default section called ``DEFAULT``. Options not found in a +normal section are looked up in the default section. If found, the value of the +matching option name is the lookup result. + +.. rubric:: Example + +.. code-block:: ini + + [section1] + option1 = value1 + opt2 = val ue $2 + + [section2] + option1 = ${section1:option1} + opt2 = ${option1} + + +Option lines can be of three kinds: An option, a reference, or a user defined +variable. While the syntax is always the same, the meaning is infered from the +context. + ++---------------------------+-----------------------------------------------------------------+ +| Option Line Kind | Distinguishing Characteristic | ++===========================+=================================================================+ +| **Reference** | The option name is called a (node) reference, if the value\ | +| | of an option is a predefined keyword for the current node\ | +| | class. Because the option's value is a keyword, it can not\ | +| | be an interpolated value. | ++---------------------------+-----------------------------------------------------------------+ +| **Option** | The option uses a defined option name valid for the current\ | +| | node class. The value can be a fixed or interpolated string. | ++---------------------------+-----------------------------------------------------------------+ +| **User Defined Variable** | Otherwise an option line is a user defined variable. It can\ | +| | have fixed or interpolated string values. | ++---------------------------+-----------------------------------------------------------------+ + +.. code-block:: ini + + [PoC] + Name = + Prefix = + arith = Namespace + bus = Namespace + + [PoC.arith] + addw = Entity + prng = Entity + + [PoC.bus] + stream = Namespace + wb = Namespace + Arbiter = Entity + + [PoC.bus.stream] + Buffer = Entity + DeMux = Entity + Mirror = Entity + Mux = Entity + + [PoC.bus.wb] + fifo_adapter = Entity + ocram_adapter = Entity + uart_wrapper = Entity + + +.. _IPDB:Nodes: + +Nodes +===== + +The database is build of nested associative arrays and generated in-memory from +5 *.ini files. This implies that all section names are required to be unique. +(Section merging is not allowed.) A fully qualified section name has a prefix +and a section name delimited by a dot character. The section name itself can +consist of parts also delimited by dot characters. All nodes with the same +prefix shape a node class. + +.. rubric:: The following table lists all used prefixes: + ++---------------+---------------------------------------------------------------------------------+ +| Prefix | Description | ++===============+=================================================================================+ +| ``INSTALL`` | A installed tool (chain) or program. | ++---------------+---------------------------------------------------------------------------------+ +| ``SOLUTION`` | Registered external solutions / projects. | ++---------------+---------------------------------------------------------------------------------+ +| ``CONFIG`` | Configurable PoC settings. | ++---------------+---------------------------------------------------------------------------------+ +| ``BOARD`` | A node to describe a known board. | ++---------------+---------------------------------------------------------------------------------+ +| ``CONST`` | A node to describe constraint file set for a known board. | ++---------------+---------------------------------------------------------------------------------+ +| ``PoC`` | Nodes to describe PoC's namespace structure. | ++---------------+---------------------------------------------------------------------------------+ +| ``IP`` | A node describing an IP core. | ++---------------+---------------------------------------------------------------------------------+ +| ``TB`` | A node describing testbenches. | ++---------------+---------------------------------------------------------------------------------+ +| ``COCOTB`` | A node describing Cocotb testbenches. | ++---------------+---------------------------------------------------------------------------------+ +| ``CG`` | A node storing Core Generator settings. | ++---------------+---------------------------------------------------------------------------------+ +| ``LSE`` | A node storing settings for LSE based netlist generation. | ++---------------+---------------------------------------------------------------------------------+ +| ``QMAP`` | A node storing settings for Quartus based netlist generation. | ++---------------+---------------------------------------------------------------------------------+ +| ``XST`` | A node storing settings for XST based netlist generation. | ++---------------+---------------------------------------------------------------------------------+ +| ``VIVADO`` | A node storing settings for Vivado based netlist generation. | ++---------------+---------------------------------------------------------------------------------+ +| ``XCI`` | A node storing settings for IP Catalog based netlist generation. | ++---------------+---------------------------------------------------------------------------------+ + +.. rubric:: The database has 3 special sections without prefixes: + ++---------------+------------------------------------------------------------------------------------+ +| Section Name | Description | ++===============+====================================================================================+ +| ``PoC`` | Root node for PoC's namespace hierarchy. | ++---------------+------------------------------------------------------------------------------------+ +| ``BOARDS`` | Lists all known boards. | ++---------------+------------------------------------------------------------------------------------+ +| ``SPECIAL`` | Section with dummy values. This is needed by synthesis and overwritten at runtime. | ++---------------+------------------------------------------------------------------------------------+ + + +.. rubric:: Example section names + +.. code-block:: ini + + [PoC] + [PoC.arith] + [PoC.bus] + [PoC.bus.stream] + [PoC.bus.wb] + +The fully qualified section name ``PoC.bus.stream`` has the prefix ``PoC`` and +the section name ``bus.stream``. The section name has two parts: ``bus`` and +``stream``. The dot delimited section name can be considered a path in a +hierarchical database. The parent node is ``PoC.bus`` and its grandparent is +``PoC``. (Note this is a special section. See the special sections table from +above.) + + +.. _IPDB:Refs: + +References +========== + + + +:Whatever: this is handy to create new field + + +.. _IPDB:Options: + +Options +======== + + +.. _IPDB:Values: + +Values +====== + + +.. _IPDB:ValueInterpol: + +Value Interpolation +=================== + + +.. _IPDB:NodeInterpol: + +Node Interpolation +================== + + +.. _IPDB:Roots: + +Root Nodes +========== + +Supported Options +***************** + + +.. NOTE:: + See ``py\config.defaults.ini`` for predefined default values (options) and + predefined variables, which can be used as a shortcut. + + +.. _IPDB:Files: + +Files in detail +*************** + + + +.. _IPDB:File:Structure: + +config.structure.ini +==================== + + + +.. _IPDB:File:Entity: + +config.entity.ini +================= + + + +.. _IPDB:File:Boards: + +config.boards.ini +================= + + + +.. _IPDB:File:Private: + +config.private.ini +================== + +.. _IPDB:UserDefVar: + +User Defined Variables +********************** + + +.. |date| date:: %d.%m.%Y +.. |time| date:: %H:%M + + diff --git a/docs/References/FileFormats/FilesFormat.rst b/docs/References/FileFormats/FilesFormat.rst index e724121b..5187a0a2 100644 --- a/docs/References/FileFormats/FilesFormat.rst +++ b/docs/References/FileFormats/FilesFormat.rst @@ -1,3 +1,4 @@ +.. _FileFormat:files: *.files Format ############## diff --git a/docs/References/FileFormats/IniFormat.rst b/docs/References/FileFormats/IniFormat.rst new file mode 100644 index 00000000..f41b787f --- /dev/null +++ b/docs/References/FileFormats/IniFormat.rst @@ -0,0 +1,124 @@ +.. _FileFormat:ini: + +.. raw:: html + + + + + +*.ini Format +############ + +.. contents:: Contents of this Page + :local: + +**Document rule:** + +.. raw:: html + +
+ +
+ +**DocumentLine rule:** + +.. raw:: html + +
+ +
+ +**Section rule:** + +.. raw:: html + +
+ +
+ +**OptionLine rule:** + +.. raw:: html + +
+ +
+ +**FQSectionName rule:** + +.. raw:: html + +
+ +
+ + +.. + productionlist:: + Document: `DocumentLine`* + DocumentLine: `SpecialSection` | `Section` | `CommentLine` | `EmptyLine` + CommentLine: "#" `CommentText` `LineBreak` + EmptyLine: `WhiteSpace`* `LineBreak` + SpecialSection: "[" `SimpleString` "]" + : (`OptionLine`)* + Section: "[" `FQSectionName` "]" + : (`OptionLine`)* + OptionLine: `Reference` | `Option` | `UserDefVariable` + Reference: `ReferenceName` `WhiteSpace`* "=" `WhiteSpace`* `Keyword` + Option: `OptionName` `WhiteSpace`* "=" `WhiteSpace`* `OptionValue` + UserDefVariable: `VariableName` `WhiteSpace`* "=" `WhiteSpace`* `VariableValue` + FQSectionName: `Prefix` "." `SectionName` + SectionName: `SectionNamePart` ("." `SectionNamePart`)* + SectionNamePart: `SimpleString` + ReferenceName: `SimpleString` + OptionName: `SimpleString` + VariableName: `SimpleString` diff --git a/docs/References/FileFormats/RulesFormat.rst b/docs/References/FileFormats/RulesFormat.rst index 617ca121..887683b6 100644 --- a/docs/References/FileFormats/RulesFormat.rst +++ b/docs/References/FileFormats/RulesFormat.rst @@ -1,3 +1,4 @@ +.. _FileFormat:rules: *.rules Format ############## diff --git a/docs/References/FileFormats/index.rst b/docs/References/FileFormats/index.rst index a379df4e..b35d451d 100644 --- a/docs/References/FileFormats/index.rst +++ b/docs/References/FileFormats/index.rst @@ -1,3 +1,4 @@ +.. _FileFormats: File Formats ############ @@ -5,5 +6,6 @@ File Formats .. toctree:: :maxdepth: 1 + IniFormat FilesFormat RulesFormat diff --git a/docs/References/Glossary.rst b/docs/References/Glossary.rst deleted file mode 100644 index afc37f7f..00000000 --- a/docs/References/Glossary.rst +++ /dev/null @@ -1,48 +0,0 @@ - -Glossary -######## - -Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. -At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor -sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et -accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet - -.. glossary:: - - cc - Common clock - All ports of a module use the same clock. - - dc - Dependent clock - The clock inputs of a module have a known relation in phase or are - multiples of a shared base clock. - - *flag*-signal - No documentation available. - - FWFT - First-word-fall-through - No documentation available. - - ic - Independent clock - The clock inputs have no known relation and are considdered independent. - Modules with ic interfaces implement clock domain crossing (CDC) circuits. - - OCRAM - On-Chip RAM - OCROM - On-Chip ROM - An On-Chip RAM is a embedded memory block, mostly called BlockRAM, - Dirstributed Memory, ... - - PoC.CSE - Command-Status-Error - A control and monitoring protocol in a layer-based architecture. - - PoC.Stream - A streaming optimized, FIFO-like on-chip protocol. - - PoCRoot - The PoC root directory. - - ProjectRoot - The project's root directory, which hosts PoC. - - *strobe*-signal - No documentation available. - diff --git a/docs/References/Interfaces/CommandStatusError.rst b/docs/References/Interfaces/CommandStatusError.rst deleted file mode 100644 index d7207f10..00000000 --- a/docs/References/Interfaces/CommandStatusError.rst +++ /dev/null @@ -1,6 +0,0 @@ - -PoC.CSE -####### - -.. TODO:: - Define the PoC.CSE (Command-Status-Error) interface used in ... diff --git a/docs/References/Interfaces/Memory.rst b/docs/References/Interfaces/Memory.rst deleted file mode 100644 index c02c66c9..00000000 --- a/docs/References/Interfaces/Memory.rst +++ /dev/null @@ -1,6 +0,0 @@ - -PoC.Mem -####### - -.. TODO:: - Define the PoC.Memory interface used in ... diff --git a/docs/References/Interfaces/index.rst b/docs/References/Interfaces/index.rst deleted file mode 100644 index 895d4e56..00000000 --- a/docs/References/Interfaces/index.rst +++ /dev/null @@ -1,11 +0,0 @@ - -Interfaces -########## - -.. toctree:: - :maxdepth: 1 - - CommandStatusError - Memory - Stream - diff --git a/docs/References/KnownIssues.rst b/docs/References/KnownIssues.rst index 2521b483..f56da099 100644 --- a/docs/References/KnownIssues.rst +++ b/docs/References/KnownIssues.rst @@ -1,38 +1,124 @@ +.. _ISSUE: Known Issues ############ -Aldec -***** -Active-HDL Student-Edition -========================== +.. _ISSUE:General: + +General +******* + + +.. _ISSUE:General:tristate: + +Synthesis of tri-state signals +============================== + +Tri-state signals should be only used when they are connected +(through the hierarchy) to top-level bidirectional or output pins. + +Descriptions which infer a tri-state driver like:: + + pin <= data when tri = '0' else 'Z'; + +should not be included in any IP core description because these hinder +or even inhibit block-based design flows. If a netlist is generated +from such an IP core, the netlist may contain only a simple internal +(on-chip) tri-state buffer instead of the correct tri-state I/O block +primitive because I/O buffers are not automatically added for netlist +generation. If the netlist is then used in another design, the +mapper, e.g. Xilinx ISE Map, may fail to merge the +internal tri-state buffer of the IP core netlist with the I/O buffer +automatically created for the top-level netlist. This failing behavior +is not considered as a tool bug. + +Thus, if tri-state drivers should be included in an IP core, then the +IP core description must instantiate the appropiate I/O block +primitive of the target architecture like it is done by the Xilinx MIG. + + +.. _ISSUE:General:inout_records: + +Synthesis of bidirectional records +================================== + +Records are useful to group several signals of an IP core +interface. But the corresponding port of this record type should not +be of mode ``inout`` to pass data in both direction. This restriction +holds even if a record member will be driven only by one source in the +real hardware and even if all the drivers (one for each record member) +are visible to the current synthesis run. The following +observations have been made: + +* An IP core (entity or procedure) must drive all record members with + value 'Z' which are only used as an input in the IP core. If this is + missed, then the respective record member will be driven by 'U' and + the effective value after resolution will be 'U' as well, see IEEE + Std. 1076-2008 para. 12.6.1. Thus simulation will fail. + + But these 'Z' drivers will flood the RTL / Netlist view of Altera + Quartus-II, Intel Quartus Prime and Lattice Diamond with always + tri-stated drivers and make this view unusable. + + Note: Simulation with ModelSim shows correct output even when the + 'Z' driver is missing, but a warning is reported that the behavior + is not VHDL Standard compliant. + +* Altera Quartus-II and Intel Quartus Prime report warnings about this + meaningless 'Z' drivers. Synthesis result is as expected if each + record member is only driven by one source in real hardware. + +* The synthesis result of the Lattice Synthesis Engine (3.7.0 / 3.8.0) + is not optimal. It seems that the synthesizer tries to implement the + internal (on-chip) tristate bus using AND-OR logic but failed to + optimize it away because there was only one real source. Test case + was a simple SRAM controller which used the record type + ``T_IO_TRISTATE`` to bring-out the data-bus so that the tri-state + driver could be instantiated on the top-level. + +Use separate records for the input and output data flow instead. + + +-------------------------------------------------------------------------------- + +.. _ISSUE:Aldec:ActiveHDL: + +Aldec Active-HDL +**************** * Aliases to functions and protected type methods -Altera -****** -Quartus-II -========== +.. _ISSUE:Altera:Quartus: +.. _ISSUE:Intel:Quartus: + +Altera Quartus-II / Intel Quartus Prime +*************************************** * Generic types of type strings filled with NUL + +.. _ISSUE:GHDL: + GHDL **** * Aliases to protected type methods -Xilinx -****** -ISE -=== +.. _ISSUE:Xilinx:ISE: + +Xilinx ISE +********** * Shared Variables in Simulation (VHDL-93) -Vivado -====== + +.. _ISSUE:Xilinx:Vivado: + +Xilinx Vivado +************* * Physical types in synthesis * VHDL-2008 mode in simulation diff --git a/docs/References/Licenses/CCLA.rst b/docs/References/Licenses/ApacheLicense2.0_CCLA.rst similarity index 98% rename from docs/References/Licenses/CCLA.rst rename to docs/References/Licenses/ApacheLicense2.0_CCLA.rst index 47f53e83..4147668f 100644 --- a/docs/References/Licenses/CCLA.rst +++ b/docs/References/Licenses/ApacheLicense2.0_CCLA.rst @@ -1,7 +1,9 @@ -.. image:: /_static/images/logo_tud.jpg +.. image:: /_static/logos/tu-dresden.jpg :scale: 10 :alt: Logo: Technische Universität Dresden +----------------------------------- + Modified Apache Corporate Contributor License Agreement v2.0 ############################################################ diff --git a/docs/References/Licenses/ICLA.rst b/docs/References/Licenses/ApacheLicense2.0_ICLA.rst similarity index 97% rename from docs/References/Licenses/ICLA.rst rename to docs/References/Licenses/ApacheLicense2.0_ICLA.rst index acf5b704..314020d2 100644 --- a/docs/References/Licenses/ICLA.rst +++ b/docs/References/Licenses/ApacheLicense2.0_ICLA.rst @@ -1,7 +1,9 @@ -.. image:: /_static/images/logo_tud.jpg +.. image:: /_static/logos/tu-dresden.jpg :scale: 10 :alt: Logo: Technische Universität Dresden +----------------------------------- + Modified Apache Contributor License Agreement v2.0 ################################################## @@ -86,7 +88,8 @@ and interest in and to Your Contributions. that you have received permission to make Contributions on behalf of that employer, that your employer has waived such rights for your Contributions to the Chair, or that your employer has - executed a separate :doc:`Corporate CLA ` with the Chair. + executed a separate :doc:`Corporate CLA ` + with the Chair. 5. You represent that each of Your Contributions is Your original creation (see section 7 for submissions on behalf of others). You diff --git a/docs/References/Licenses/BSDLicense_Cocotb.rst b/docs/References/Licenses/Cocotb_BSDLicense.rst similarity index 94% rename from docs/References/Licenses/BSDLicense_Cocotb.rst rename to docs/References/Licenses/Cocotb_BSDLicense.rst index 17eda5c8..f9c4389c 100644 --- a/docs/References/Licenses/BSDLicense_Cocotb.rst +++ b/docs/References/Licenses/Cocotb_BSDLicense.rst @@ -12,8 +12,8 @@ BSD License for Cocotb Cocotb is licensed under the Revised BSD License. Full license text below. -**Copyright (c) 2013 Potential Ventures Ltd** |br| -**Copyright (c) 2013 SolarFlare Communications Inc** |br| +**Copyright © 2013 Potential Ventures Ltd** |br| +**Copyright © 2013 SolarFlare Communications Inc** |br| **All rights reserved.** Redistribution and use in source and binary forms, with or without diff --git a/docs/References/Licenses/UVVM_MIT.rst b/docs/References/Licenses/UVVM_MIT.rst new file mode 100644 index 00000000..a4ce5d5d --- /dev/null +++ b/docs/References/Licenses/UVVM_MIT.rst @@ -0,0 +1,31 @@ +.. Note:: + This is a local copy of `The MIT License (MIT) `_ + used in the UVVM library. The original can be found in file :file:`LICENSE` in the + UVVM_All source tree. + +.. TODO:: Check link to the lib/uvvm/LICENSE file. + +-------------------------------------------------------------------------------- + +The MIT License (MIT) +##################### + +**Copyright © 2016 by Bitvis AS** + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. diff --git a/docs/References/Licenses/index.rst b/docs/References/Licenses/index.rst index d648002d..1018632f 100644 --- a/docs/References/Licenses/index.rst +++ b/docs/References/Licenses/index.rst @@ -11,10 +11,11 @@ which contains a link to the orginal license file source. :maxdepth: 1 ApacheLicense2.0 - ICLA - CCLA + Apache License 2.0 - ICLA + Apache License 2.0 - CCLA ArtisticLicense2.0 - BSDLicense_Cocotb + Cocotb - BSD License + UVVM - MIT License MozillaPublicLicense2.0 .. rubric:: Footnotes diff --git a/docs/References/NamingConventions.rst b/docs/References/NamingConventions.rst index 875e205d..cf6a715c 100644 --- a/docs/References/NamingConventions.rst +++ b/docs/References/NamingConventions.rst @@ -11,7 +11,7 @@ Root Directory Overview (PoCRoot) The PoC-Library is structured into several sub-directories, naming the purpose of the directory like ``src`` for sources files or ``tb`` for testbench files. The structure within these directories is most likely the same and based on -PoC's :doc:`sub-namespace tree `. PoC's installation directory is +PoC's :doc:`sub-namespace tree `. PoC's installation directory is also referred to as ``PoCRoot``. * ``lib`` @@ -40,7 +40,7 @@ also referred to as ``PoCRoot``. * ``src`` The source files of PoC's IP cores are stored in this directory. The IP cores are grouped by their sub-namespace into sub-directories according to - the :doc:`sub-namespace tree `. See the paragraph below, for + the :doc:`sub-namespace tree `. See the paragraph below, for how IP cores are named and how PoC core names map to the sub-namespace hierachy and the resulting sub-namespace directory structure. * ``tb`` diff --git a/docs/References/index.rst b/docs/References/more.rst similarity index 69% rename from docs/References/index.rst rename to docs/References/more.rst index a25607cb..0fea6380 100644 --- a/docs/References/index.rst +++ b/docs/References/more.rst @@ -1,17 +1,14 @@ -References -########## +More References +############### .. toctree:: :maxdepth: 1 - CommandReference + ListOfDevices + ListOfBoards WrapperScriptHookFiles FileFormats/index - Interfaces/index NamingConventions - ListOfDevices - ListOfBoards - Glossary KnownIssues Licenses/index diff --git a/docs/ToolChains/index.rst b/docs/ToolChains/index.rst new file mode 100644 index 00000000..c90fb085 --- /dev/null +++ b/docs/ToolChains/index.rst @@ -0,0 +1,34 @@ +.. _CHAIN: + +Tool Chain Specifics +#################### + +.. attention:: + + This page is under construction. + + +Aldec Active-HDL +================ + +.. todo:: + + * No GUI mode supported + * VHDL-2008 parser bug in Active-HDL 10.3 + + +Mentor QuestaSim +================ + +Special feature: embedded poc prodecures to recompile relaunch, rerun and save waveforms... + +Xilinx ISE +========== + +* Describe the ``use_new_parser yes`` option + +Xilinx Vivado +============= + +* Describe the ``vivado`` branch (Git). + diff --git a/docs/UsingPoC/AddingIPCores.rst b/docs/UsingPoC/AddingIPCores.rst index ee96bc4c..45a3ae66 100644 --- a/docs/UsingPoC/AddingIPCores.rst +++ b/docs/UsingPoC/AddingIPCores.rst @@ -1,3 +1,4 @@ +.. _USING:AddIP: Adding IP Cores to a Project ############################ diff --git a/docs/UsingPoC/Download.rst b/docs/UsingPoC/Download.rst index 64bbfbd6..4f4d9c31 100644 --- a/docs/UsingPoC/Download.rst +++ b/docs/UsingPoC/Download.rst @@ -1,3 +1,4 @@ +.. _USING:Download: Downloading PoC ############### @@ -5,21 +6,35 @@ Downloading PoC .. contents:: Contents of this Page :local: + +.. _USING:Zip: + Downloading from GitHub *********************** The PoC-Library can be downloaded as a zip-file from GitHub. See the following table, to choose your desired git branch. -+----------+--------------------------------------------------------------------+ -| Branch | download link | -+==========+====================================================================+ -| master | `zip-file `_ | -+----------+--------------------------------------------------------------------+ -| release | `zip-file `_ | -+----------+--------------------------------------------------------------------+ +.. |zip-master| image:: /_static/icons/ZIP.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/archive/master.zip + :alt: Source Code from GitHub - 'master' branch. +.. |zip-release| image:: /_static/icons/ZIP.png + :scale: 40 + :target: https://github.com/VLSI-EDA/PoC/archive/release.zip + :alt: Source Code from GitHub - 'release' branch. + ++----------+------------------------+ +| Branch | Download Link | ++==========+========================+ +| master | zip-file |zip-master| | ++----------+------------------------+ +| release | zip-file |zip-release| | ++----------+------------------------+ +.. _USING:GitClone: + Downloading via ``git clone`` ***************************** @@ -28,7 +43,7 @@ GitHub offers the transfer protocols HTTPS and SSH. You should use SSH if you have a GitHub account and have already uploaded an OpenSSH public key to GitHub, otherwise use HTTPS if you have no account or you want to use login credentials. -The created folder :file:`\PoC` is used as :file:`` in later +The created folder :file:`\\PoC` is used as :file:`` in later instructions or on other pages in this documentation. +----------+----------------------------------------+ @@ -78,7 +93,7 @@ On Windows All Windows command line instructions are intended for :program:`Windows PowerShell`, if not marked otherwise. So executing the following instructions in Windows Command Prompt (:program:`cmd.exe`) won't function or result in errors! See - the :doc:`Requirements section ` on where to + the :ref:`Requirements section ` on where to download or update PowerShell. Command line instructions to clone the PoC-Library onto a Windows machine with @@ -109,6 +124,8 @@ SSH protocol: needed anymore. +.. _USING:GitSubmodule: + Downloading via ``git submodule add`` ************************************* @@ -165,7 +182,7 @@ On Windows All Windows command line instructions are intended for :program:`Windows PowerShell`, if not marked otherwise. So executing the following instructions in Windows Command Prompt (:program:`cmd.exe`) won't function or result in errors! See - the :doc:`Requirements section ` on where to + the :ref:`Requirements section ` on where to download or update PowerShell. Command line instructions to clone the PoC-Library onto a Windows machine with diff --git a/docs/UsingPoC/Integration.rst b/docs/UsingPoC/Integration.rst index ab106804..b5f9089e 100644 --- a/docs/UsingPoC/Integration.rst +++ b/docs/UsingPoC/Integration.rst @@ -1,3 +1,4 @@ +.. _USING:Integration: Integrating PoC into Projects ############################# @@ -7,6 +8,8 @@ Integrating PoC into Projects :depth: 2 +.. _USING:Integration:GitSubmodule: + As a Git submodule ****************** @@ -176,4 +179,3 @@ On Windows } ``` - diff --git a/docs/UsingPoC/PoCConfiguration.rst b/docs/UsingPoC/PoCConfiguration.rst index 66e08875..7c09d8cf 100644 --- a/docs/UsingPoC/PoCConfiguration.rst +++ b/docs/UsingPoC/PoCConfiguration.rst @@ -1,3 +1,41 @@ +.. _USING:PoCConfig: + +.. raw:: html + + + +.. |kbd-Y| raw:: html + + Y + +.. |kbd-N| raw:: html + + N + +.. |kbd-P| raw:: html + + P + +.. |kbd-Return| raw:: html + + Return Configuring PoC's Infrastructure ################################ @@ -11,13 +49,15 @@ at any time, for example to register new tools or to update tool versions. :depth: 2 +.. _USING:PoCConf:Over: + Overview ======== The setup process is started by invoking PoC's frontend script with the command ``configure``. Please follow the instructions on screen. Use the keyboard -buttons: :kbd:`Y` to accept, :kbd:`N` to decline, :kbd:`P` to skip/pass a step -and :kbd:`Return` to accept a default value displayed in brackets. +buttons: |kbd-Y| to accept, |kbd-N| to decline, |kbd-P| to skip/pass a step and +|kbd-Return| to accept a default value displayed in brackets. Optionally, a vendor or tool chain name can be passed to the configuration process to launch only its configuration routines. @@ -73,6 +113,8 @@ Please see the Linux instructions. Installation directory: D:\git\PoC (found in environment variable) +.. _USING:PoCConf:PoC: + The PoC-Library =============== PoC itself has a fully automated configuration routine. It detects if PoC is @@ -86,6 +128,9 @@ by ``PoC.ps1`` or ``poc.sh``. PoC version: v1.0.1 (found in git) Installation directory: D:\git\PoC (found in environment variable) + +.. _USING:PoCConf:Git: + Git === .. NOTE:: @@ -103,6 +148,9 @@ Git Installing Git hooks... Setting 'pre-commit' hook for PoC... + +.. _USING:PoCConf:Aldec: + Aldec ===== Configure the installation directory for all Aldec tools. @@ -122,6 +170,9 @@ Active-HDL Aldec Active-HDL version [10.3]: Aldec Active-HDL installation directory [C:\Aldec\Active-HDL]: C:\Aldec\Active-HDL-Student-Edition + +.. _USING:PoCConf:Altera: + Altera ====== Configure the installation directory for all Altera tools. @@ -149,6 +200,9 @@ ModelSim Altera Edition Is ModelSim Altera Edition installed on your system? [Y/n/p]: Y ModelSim Altera Edition installation directory [C:\Altera\15.0\modelsim_ae]: C:\Altera\16.0\modelsim_ase + +.. _USING:PoCConf:Lattice: + Lattice ======== Configure the installation directory for all Lattice Semiconductor tools. @@ -177,6 +231,9 @@ Active-HDL Lattice Edition Active-HDL Lattice Edition version [10.2]: Active-HDL Lattice Edition installation directory [D:\Lattice\Diamond\3.7_x64\active-hdl]: + +.. _USING:PoCConf:Mentor: + Mentor Graphics =============== Configure the installation directory for all mentor Graphics tools. @@ -196,6 +253,9 @@ QuestaSim Mentor QuestaSim version [10.4d]: 10.4c Mentor QuestaSim installation directory [C:\Mentor\QuestaSim\10.4c]: C:\Mentor\QuestaSim64\10.4c + +.. _USING:PoCConf:Xilinx: + Xilinx ====== Configure the installation directory for all Xilinx tools. @@ -233,6 +293,9 @@ answer the following questions: Xilinx Vivado version [2016.2]: Xilinx Vivado installation directory [C:\Xilinx\Vivado\2016.2]: + +.. _USING:PoCConf:GHDL: + GHDL ==== .. code-block:: none @@ -241,6 +304,9 @@ GHDL Is GHDL installed on your system? [Y/n/p]: Y GHDL installation directory [C:\Tools\GHDL\0.34dev]: + +.. _USING:PoCConf:GTKWave: + GTKWave ======== .. code-block:: none @@ -249,6 +315,9 @@ GTKWave Is GTKWave installed on your system? [Y/n/p]: Y GTKWave installation directory [C:\Tools\GTKWave\3.3.71]: + +.. _USING:PoCConf:HookFiles: + Hook Files ========== diff --git a/docs/UsingPoC/PrecompilingVendorLibraries.rst b/docs/UsingPoC/PrecompilingVendorLibraries.rst index 1f28f2c8..b4e4f776 100644 --- a/docs/UsingPoC/PrecompilingVendorLibraries.rst +++ b/docs/UsingPoC/PrecompilingVendorLibraries.rst @@ -1,11 +1,19 @@ +.. _USING:PreCompile: Pre-Compiling Vendor Libraries ############################## .. contents:: Contents of this Page :local: + :depth: 2 + :backlinks: entry +.. index:: + single: Pre-compilation + +.. _USING:PreCompile:Over: + Overview ******** @@ -22,39 +30,56 @@ are located in ``\tools\precompile\`` and the output is stored in ``\temp\precompiled\\``. +.. index:: + pair: Pre-compilation; Supported Simulators + +.. _USING:PreCompile:Simulators: + Supported Simulators ******************** The current set of pre-compile scripts support these simulators: -+------------+------------------------------+--------------+--------------+---------------+--------------------+ -| Vendor | Simulator and Edition | Altera | Lattice | Xilinx (ISE) | Xilinx (Vivado) | -+============+==============================+==============+==============+===============+====================+ -| T. Gingold | GHDL with ``--std=93c`` |br| | yes |br| | yes |br| | yes |br| | yes |br| | -| | GHDL with ``--std=08`` | yes | yes | yes | yes | -+------------+------------------------------+--------------+--------------+---------------+--------------------+ -| Aldec | Active-HDL |br| | planned |br| | planned |br| | planned |br| | planned |br| | -| | Active-HDL Lattice Ed. |br| | planned |br| | shipped |br| | planned |br| | planned |br| | -| | Reviera-PRO | planned | planned | planned | planned | -+------------+------------------------------+--------------+--------------+---------------+--------------------+ -| Mentor | ModelSim |br| | yes |br| | yes |br| | yes |br| | yes |br| | -| | ModelSim Altera Ed. |br| | shipped |br| | yes |br| | yes |br| | yes |br| | -| | QuestaSim | yes | yes | yes | yes | -+------------+------------------------------+--------------+--------------+---------------+--------------------+ -| Xilinx | ISE Simulator |br| | | | shipped |br| | not supported |br| | -| | Vivado Simulator | | | not supported | shipped | -+------------+------------------------------+--------------+--------------+---------------+--------------------+ - ++------------------+--------------------------------------+--------------+--------------+-----------------+----------------------+ +| Vendor | Simulator and Edition | Altera | Lattice | Xilinx (ISE) | Xilinx (Vivado) | ++==================+======================================+==============+==============+=================+======================+ +| T. Gingold |br| | GHDL with ``--std=93c`` |br| | yes |br| | yes |br| | yes |br| | yes |br| | +| | GHDL with ``--std=08`` | yes | yes | yes | yes | ++------------------+--------------------------------------+--------------+--------------+-----------------+----------------------+ +| Aldec |br| | Active-HDL (or Stududent Ed.) |br| | planned |br| | planned |br| | planned |br| | planned |br| | +| |br| | Active-HDL Lattice Ed. |br| | planned |br| | shipped |br| | planned |br| | planned |br| | +| | Reviera-PRO | planned | planned | planned | planned | ++------------------+--------------------------------------+--------------+--------------+-----------------+----------------------+ +| Mentor |br| | ModelSim PE (or Stududent Ed.) |br| | yes |br| | yes |br| | yes |br| | yes |br| | +| |br| | ModelSim SE |br| | yes |br| | yes |br| | yes |br| | yes |br| | +| |br| | ModelSim Altera Ed. |br| | shipped |br| | yes |br| | yes |br| | yes |br| | +| | QuestaSim | yes | yes | yes | yes | ++------------------+--------------------------------------+--------------+--------------+-----------------+----------------------+ +| Xilinx |br| | ISE Simulator |br| | | | shipped |br| | not supported |br| | +| | Vivado Simulator | | | not supported | shipped | ++------------------+--------------------------------------+--------------+--------------+-----------------+----------------------+ + + +.. index:: + pair: Pre-compilation; Vendor Primitives + +.. _USING:PreCompile:Primitives: FPGA Vendor's Primitive Libraries -********************************* +**************************************************************************************************************************************************************** + +.. # =========================================================================================================================================================== +.. index:: + pair: Pre-compilation; Altera + +.. _USING:PreCompile:Primitives:Altera: Altera ====== .. note:: The Altera Quartus tool chain needs to be configured in PoC. |br| - See :doc:`Configuring PoC's Infrastruture ` for further details. + See :ref:`Configuring PoC's Infrastruture ` for further details. On Linux -------- @@ -68,23 +93,34 @@ On Linux **List of command line arguments:** -+------------------+-------------------------------+ -| Common Option | Description | -+=====+============+===============================+ -| -h | --help | Print embedded help page(s) | -+-----+------------+-------------------------------+ -| -c | --clean | Clean-up directories | -+-----+------------+-------------------------------+ -| -a | --all | Compile for all simulators | -+-----+------------+-------------------------------+ -| | --ghdl | Compile for GHDL | -+-----+------------+-------------------------------+ -| | --questa | Compile for QuestaSim | -+-----+------------+-------------------------------+ -| | --vhdl93 | Compile only for VHDL-93 | -+-----+------------+-------------------------------+ -| | --vhdl2008 | Compile only for VHDL-2008 | -+-----+------------+-------------------------------+ +.. |c-altera-sh-h| replace:: :option:`-h ` +.. |c-altera-sh-c| replace:: :option:`-c ` +.. |c-altera-sh-a| replace:: :option:`-a ` +.. |c-altera-sh-help| replace:: :option:`--help ` +.. |c-altera-sh-clean| replace:: :option:`--clean ` +.. |c-altera-sh-all| replace:: :option:`--all ` +.. |c-altera-sh-ghdl| replace:: :option:`--ghdl ` +.. |c-altera-sh-questa| replace:: :option:`--questa ` +.. |c-altera-sh-vhdl93| replace:: :option:`--vhdl93 ` +.. |c-altera-sh-vhdl08| replace:: :option:`--vhdl2008 ` + ++------------------------------------------+---------------------------------------------------------------------------+ +| Common Option | Parameter Description | ++==================+=======================+===========================================================================+ +| |c-altera-sh-h| | |c-altera-sh-help| | Print embedded help page(s). | ++------------------+-----------------------+---------------------------------------------------------------------------+ +| |c-altera-sh-c| | |c-altera-sh-clean| | Clean-up directories. | ++------------------+-----------------------+---------------------------------------------------------------------------+ +| |c-altera-sh-a| | |c-altera-sh-all| | Compile for all simulators. | ++------------------+-----------------------+---------------------------------------------------------------------------+ +| | |c-altera-sh-ghdl| | Compile for GHDL. | ++------------------+-----------------------+---------------------------------------------------------------------------+ +| | |c-altera-sh-questa| | Compile for QuestaSim. | ++------------------+-----------------------+---------------------------------------------------------------------------+ +| | |c-altera-sh-vhdl93| | GHDL only: Compile only for VHDL-93. | ++------------------+-----------------------+---------------------------------------------------------------------------+ +| | |c-altera-sh-vhdl08| | GHDL only: Compile only for VHDL-2008. | ++------------------+-----------------------+---------------------------------------------------------------------------+ On Windows @@ -99,31 +135,47 @@ On Windows **List of command line arguments:** -+-----------------+-------------------------------+ -| Common Option | Description | -+=====+===========+===============================+ -| -h | -Help | Print embedded help page(s) | -+-----+-----------+-------------------------------+ -| -c | -Clean | Clean-up directories | -+-----+-----------+-------------------------------+ -| -a | -All | Compile for all simulators | -+-----+-----------+-------------------------------+ -| | -GHDL | Compile for GHDL | -+-----+-----------+-------------------------------+ -| | -Questa | Compile for QuestaSim | -+-----+-----------+-------------------------------+ -| | -VHDL93 | Compile only for VHDL-93 | -+-----+-----------+-------------------------------+ -| | -VHDL2008 | Compile only for VHDL-2008 | -+-----+-----------+-------------------------------+ - +.. |c-altera-ps-h| replace:: ``-h`` +.. |c-altera-ps-c| replace:: ``-c`` +.. |c-altera-ps-a| replace:: ``-a`` +.. |c-altera-ps-help| replace:: :option:`-Help ` +.. |c-altera-ps-clean| replace:: :option:`-Clean ` +.. |c-altera-ps-all| replace:: :option:`-All ` +.. |c-altera-ps-ghdl| replace:: :option:`-GHDL ` +.. |c-altera-ps-questa| replace:: :option:`-Questa ` +.. |c-altera-ps-vhdl93| replace:: :option:`-VHDL93 ` +.. |c-altera-ps-vhdl08| replace:: :option:`-VHDL2008 ` + ++------------------------------------------+---------------------------------------------------------------------------+ +| Common Option | Parameter Description | ++==================+=======================+===========================================================================+ +| |c-altera-ps-h| | |c-altera-ps-help| | Print embedded help page(s). | ++------------------+-----------------------+---------------------------------------------------------------------------+ +| |c-altera-ps-c| | |c-altera-ps-clean| | Clean-up directories. | ++------------------+-----------------------+---------------------------------------------------------------------------+ +| |c-altera-ps-a| | |c-altera-ps-all| | Compile for all simulators. | ++------------------+-----------------------+---------------------------------------------------------------------------+ +| | |c-altera-ps-ghdl| | Compile for GHDL. | ++------------------+-----------------------+---------------------------------------------------------------------------+ +| | |c-altera-ps-questa| | Compile for QuestaSim. | ++------------------+-----------------------+---------------------------------------------------------------------------+ +| | |c-altera-ps-vhdl93| | GHDL only: Compile only for VHDL-93. | ++------------------+-----------------------+---------------------------------------------------------------------------+ +| | |c-altera-ps-vhdl08| | GHDL only: Compile only for VHDL-2008. | ++------------------+-----------------------+---------------------------------------------------------------------------+ + +.. # =========================================================================================================================================================== +.. index:: + pair: Pre-compilation; Lattice + +.. _USING:PreCompile:Primitives:Lattice: Lattice ======== .. note:: The Lattice Diamond tool chain needs to be configured in PoC. |br| - See :doc:`Configuring PoC's Infrastruture ` for further details. + See :ref:`Configuring PoC's Infrastruture ` for further details. On Linux -------- @@ -137,23 +189,34 @@ On Linux **List of command line arguments:** -+------------------+-------------------------------+ -| Common Option | Description | -+=====+============+===============================+ -| -h | --help | Print embedded help page(s) | -+-----+------------+-------------------------------+ -| -c | --clean | Clean-up directories | -+-----+------------+-------------------------------+ -| -a | --all | Compile for all simulators | -+-----+------------+-------------------------------+ -| | --ghdl | Compile for GHDL | -+-----+------------+-------------------------------+ -| | --questa | Compile for QuestaSim | -+-----+------------+-------------------------------+ -| | --vhdl93 | Compile only for VHDL-93 | -+-----+------------+-------------------------------+ -| | --vhdl2008 | Compile only for VHDL-2008 | -+-----+------------+-------------------------------+ +.. |c-lattice-sh-h| replace:: :option:`-h ` +.. |c-lattice-sh-c| replace:: :option:`-c ` +.. |c-lattice-sh-a| replace:: :option:`-a ` +.. |c-lattice-sh-help| replace:: :option:`--help ` +.. |c-lattice-sh-clean| replace:: :option:`--clean ` +.. |c-lattice-sh-all| replace:: :option:`--all ` +.. |c-lattice-sh-ghdl| replace:: :option:`--ghdl ` +.. |c-lattice-sh-questa| replace:: :option:`--questa ` +.. |c-lattice-sh-vhdl93| replace:: :option:`--vhdl93 ` +.. |c-lattice-sh-vhdl08| replace:: :option:`--vhdl2008 ` + ++--------------------------------------------+-------------------------------------------------------------------------+ +| Common Option | Parameter Description | ++===================+========================+=========================================================================+ +| |c-lattice-sh-h| | |c-lattice-sh-help| | Print embedded help page(s). | ++-------------------+------------------------+-------------------------------------------------------------------------+ +| |c-lattice-sh-c| | |c-lattice-sh-clean| | Clean-up directories. | ++-------------------+------------------------+-------------------------------------------------------------------------+ +| |c-lattice-sh-a| | |c-lattice-sh-all| | Compile for all simulators. | ++-------------------+------------------------+-------------------------------------------------------------------------+ +| | |c-lattice-sh-ghdl| | Compile for GHDL. | ++-------------------+------------------------+-------------------------------------------------------------------------+ +| | |c-lattice-sh-questa| | Compile for QuestaSim. | ++-------------------+------------------------+-------------------------------------------------------------------------+ +| | |c-lattice-sh-vhdl93| | GHDL only: Compile only for VHDL-93. | ++-------------------+------------------------+-------------------------------------------------------------------------+ +| | |c-lattice-sh-vhdl08| | GHDL only: Compile only for VHDL-2008. | ++-------------------+------------------------+-------------------------------------------------------------------------+ On Windows @@ -168,30 +231,47 @@ On Windows **List of command line arguments:** -+-----------------+-------------------------------+ -| Common Option | Description | -+=====+===========+===============================+ -| -h | -Help | Print embedded help page(s) | -+-----+-----------+-------------------------------+ -| -c | -Clean | Clean-up directories | -+-----+-----------+-------------------------------+ -| -a | -All | Compile for all simulators | -+-----+-----------+-------------------------------+ -| | -GHDL | Compile for GHDL | -+-----+-----------+-------------------------------+ -| | -Questa | Compile for QuestaSim | -+-----+-----------+-------------------------------+ -| | -VHDL93 | Compile only for VHDL-93 | -+-----+-----------+-------------------------------+ -| | -VHDL2008 | Compile only for VHDL-2008 | -+-----+-----------+-------------------------------+ +.. |c-lattice-ps-h| replace:: ``-h`` +.. |c-lattice-ps-c| replace:: ``-c`` +.. |c-lattice-ps-a| replace:: ``-a`` +.. |c-lattice-ps-help| replace:: :option:`-Help ` +.. |c-lattice-ps-clean| replace:: :option:`-Clean ` +.. |c-lattice-ps-all| replace:: :option:`-All ` +.. |c-lattice-ps-ghdl| replace:: :option:`-GHDL ` +.. |c-lattice-ps-questa| replace:: :option:`-Questa ` +.. |c-lattice-ps-vhdl93| replace:: :option:`-VHDL93 ` +.. |c-lattice-ps-vhdl08| replace:: :option:`-VHDL2008 ` + ++--------------------------------------------+-------------------------------------------------------------------------+ +| Common Option | Parameter Description | ++===================+========================+=========================================================================+ +| |c-lattice-ps-h| | |c-lattice-ps-help| | Print embedded help page(s). | ++-------------------+------------------------+-------------------------------------------------------------------------+ +| |c-lattice-ps-c| | |c-lattice-ps-clean| | Clean-up directories. | ++-------------------+------------------------+-------------------------------------------------------------------------+ +| |c-lattice-ps-a| | |c-lattice-ps-all| | Compile for all simulators. | ++-------------------+------------------------+-------------------------------------------------------------------------+ +| | |c-lattice-ps-ghdl| | Compile for GHDL. | ++-------------------+------------------------+-------------------------------------------------------------------------+ +| | |c-lattice-ps-questa| | Compile for QuestaSim. | ++-------------------+------------------------+-------------------------------------------------------------------------+ +| | |c-lattice-ps-vhdl93| | GHDL only: Compile only for VHDL-93. | ++-------------------+------------------------+-------------------------------------------------------------------------+ +| | |c-lattice-ps-vhdl08| | GHDL only: Compile only for VHDL-2008. | ++-------------------+------------------------+-------------------------------------------------------------------------+ + +.. # =========================================================================================================================================================== +.. index:: + pair: Pre-compilation; Xilinx ISE + +.. _USING:PreCompile:Primitives:XilinxISE: Xilinx ISE ========== .. note:: The Xilinx ISE tool chain needs to be configured in PoC. |br| - See :doc:`Configuring PoC's Infrastruture ` for further details. + See :ref:`Configuring PoC's Infrastruture ` for further details. On Linux -------- @@ -205,23 +285,34 @@ On Linux **List of command line arguments:** -+------------------+-------------------------------+ -| Common Option | Description | -+=====+============+===============================+ -| -h | --help | Print embedded help page(s) | -+-----+------------+-------------------------------+ -| -c | --clean | Clean-up directories | -+-----+------------+-------------------------------+ -| -a | --all | Compile for all simulators | -+-----+------------+-------------------------------+ -| | --ghdl | Compile for GHDL | -+-----+------------+-------------------------------+ -| | --questa | Compile for QuestaSim | -+-----+------------+-------------------------------+ -| | --vhdl93 | Compile only for VHDL-93 | -+-----+------------+-------------------------------+ -| | --vhdl2008 | Compile only for VHDL-2008 | -+-----+------------+-------------------------------+ +.. |c-ise-sh-h| replace:: :option:`-h ` +.. |c-ise-sh-c| replace:: :option:`-c ` +.. |c-ise-sh-a| replace:: :option:`-a ` +.. |c-ise-sh-help| replace:: :option:`--help ` +.. |c-ise-sh-clean| replace:: :option:`--clean ` +.. |c-ise-sh-all| replace:: :option:`--all ` +.. |c-ise-sh-ghdl| replace:: :option:`--ghdl ` +.. |c-ise-sh-questa| replace:: :option:`--questa ` +.. |c-ise-sh-vhdl93| replace:: :option:`--vhdl93 ` +.. |c-ise-sh-vhdl08| replace:: :option:`--vhdl2008 ` + ++------------------------------------+---------------------------------------------------------------------------------+ +| Common Option | Parameter Description | ++===============+====================+=================================================================================+ +| |c-ise-sh-h| | |c-ise-sh-help| | Print embedded help page(s). | ++---------------+--------------------+---------------------------------------------------------------------------------+ +| |c-ise-sh-c| | |c-ise-sh-clean| | Clean-up directories. | ++---------------+--------------------+---------------------------------------------------------------------------------+ +| |c-ise-sh-a| | |c-ise-sh-all| | Compile for all simulators. | ++---------------+--------------------+---------------------------------------------------------------------------------+ +| | |c-ise-sh-ghdl| | Compile for GHDL. | ++---------------+--------------------+---------------------------------------------------------------------------------+ +| | |c-ise-sh-questa| | Compile for QuestaSim. | ++---------------+--------------------+---------------------------------------------------------------------------------+ +| | |c-ise-sh-vhdl93| | GHDL only: Compile only for VHDL-93. | ++---------------+--------------------+---------------------------------------------------------------------------------+ +| | |c-ise-sh-vhdl08| | GHDL only: Compile only for VHDL-2008. | ++---------------+--------------------+---------------------------------------------------------------------------------+ On Windows @@ -236,30 +327,47 @@ On Windows **List of command line arguments:** -+-----------------+-------------------------------+ -| Common Option | Description | -+=====+===========+===============================+ -| -h | -Help | Print embedded help page(s) | -+-----+-----------+-------------------------------+ -| -c | -Clean | Clean-up directories | -+-----+-----------+-------------------------------+ -| -a | -All | Compile for all simulators | -+-----+-----------+-------------------------------+ -| | -GHDL | Compile for GHDL | -+-----+-----------+-------------------------------+ -| | -Questa | Compile for QuestaSim | -+-----+-----------+-------------------------------+ -| | -VHDL93 | Compile only for VHDL-93 | -+-----+-----------+-------------------------------+ -| | -VHDL2008 | Compile only for VHDL-2008 | -+-----+-----------+-------------------------------+ +.. |c-ise-ps-h| replace:: ``-h`` +.. |c-ise-ps-c| replace:: ``-c`` +.. |c-ise-ps-a| replace:: ``-a`` +.. |c-ise-ps-help| replace:: :option:`-Help ` +.. |c-ise-ps-clean| replace:: :option:`-Clean ` +.. |c-ise-ps-all| replace:: :option:`-All ` +.. |c-ise-ps-ghdl| replace:: :option:`-GHDL ` +.. |c-ise-ps-questa| replace:: :option:`-Questa ` +.. |c-ise-ps-vhdl93| replace:: :option:`-VHDL93 ` +.. |c-ise-ps-vhdl08| replace:: :option:`-VHDL2008 ` + ++------------------------------------+---------------------------------------------------------------------------------+ +| Common Option | Parameter Description | ++===============+====================+=================================================================================+ +| |c-ise-ps-h| | |c-ise-ps-help| | Print embedded help page(s). | ++---------------+--------------------+---------------------------------------------------------------------------------+ +| |c-ise-ps-c| | |c-ise-ps-clean| | Clean-up directories. | ++---------------+--------------------+---------------------------------------------------------------------------------+ +| |c-ise-ps-a| | |c-ise-ps-all| | Compile for all simulators. | ++---------------+--------------------+---------------------------------------------------------------------------------+ +| | |c-ise-ps-ghdl| | Compile for GHDL. | ++---------------+--------------------+---------------------------------------------------------------------------------+ +| | |c-ise-ps-questa| | Compile for QuestaSim. | ++---------------+--------------------+---------------------------------------------------------------------------------+ +| | |c-ise-ps-vhdl93| | GHDL only: Compile only for VHDL-93. | ++---------------+--------------------+---------------------------------------------------------------------------------+ +| | |c-ise-ps-vhdl08| | GHDL only: Compile only for VHDL-2008. | ++---------------+--------------------+---------------------------------------------------------------------------------+ + +.. # =========================================================================================================================================================== +.. index:: + pair: Pre-compilation; Xilinx Vivado + +.. _USING:PreCompile:Primitives:XilinxVivado Xilinx Vivado ============= .. note:: The Xilinx Vivado tool chain needs to be configured in PoC. |br| - See :doc:`Configuring PoC's Infrastruture ` for further details. + See :ref:`Configuring PoC's Infrastruture ` for further details. On Linux -------- @@ -273,23 +381,34 @@ On Linux **List of command line arguments:** -+------------------+-------------------------------+ -| Common Option | Description | -+=====+============+===============================+ -| -h | --help | Print embedded help page(s) | -+-----+------------+-------------------------------+ -| -c | --clean | Clean-up directories | -+-----+------------+-------------------------------+ -| -a | --all | Compile for all simulators | -+-----+------------+-------------------------------+ -| | --ghdl | Compile for GHDL | -+-----+------------+-------------------------------+ -| | --questa | Compile for QuestaSim | -+-----+------------+-------------------------------+ -| | --vhdl93 | Compile only for VHDL-93 | -+-----+------------+-------------------------------+ -| | --vhdl2008 | Compile only for VHDL-2008 | -+-----+------------+-------------------------------+ +.. |c-vivado-sh-h| replace:: :option:`-h ` +.. |c-vivado-sh-c| replace:: :option:`-c ` +.. |c-vivado-sh-a| replace:: :option:`-a ` +.. |c-vivado-sh-help| replace:: :option:`--help ` +.. |c-vivado-sh-clean| replace:: :option:`--clean ` +.. |c-vivado-sh-all| replace:: :option:`--all ` +.. |c-vivado-sh-ghdl| replace:: :option:`--ghdl ` +.. |c-vivado-sh-questa| replace:: :option:`--questa ` +.. |c-vivado-sh-vhdl93| replace:: :option:`--vhdl93 ` +.. |c-vivado-sh-vhdl08| replace:: :option:`--vhdl2008 ` + ++------------------------------------------+---------------------------------------------------------------------------+ +| Common Option | Parameter Description | ++==================+=======================+===========================================================================+ +| |c-vivado-sh-h| | |c-vivado-sh-help| | Print embedded help page(s). | ++------------------+-----------------------+---------------------------------------------------------------------------+ +| |c-vivado-sh-c| | |c-vivado-sh-clean| | Clean-up directories. | ++------------------+-----------------------+---------------------------------------------------------------------------+ +| |c-vivado-sh-a| | |c-vivado-sh-all| | Compile for all simulators. | ++------------------+-----------------------+---------------------------------------------------------------------------+ +| | |c-vivado-sh-ghdl| | Compile for GHDL. | ++------------------+-----------------------+---------------------------------------------------------------------------+ +| | |c-vivado-sh-questa| | Compile for QuestaSim. | ++------------------+-----------------------+---------------------------------------------------------------------------+ +| | |c-vivado-sh-vhdl93| | GHDL only: Compile only for VHDL-93. | ++------------------+-----------------------+---------------------------------------------------------------------------+ +| | |c-vivado-sh-vhdl08| | GHDL only: Compile only for VHDL-2008. | ++------------------+-----------------------+---------------------------------------------------------------------------+ On Windows @@ -304,26 +423,49 @@ On Windows **List of command line arguments:** -+-----------------+-------------------------------+ -| Common Option | Description | -+=====+===========+===============================+ -| -h | -Help | Print embedded help page(s) | -+-----+-----------+-------------------------------+ -| -c | -Clean | Clean-up directories | -+-----+-----------+-------------------------------+ -| -a | -All | Compile for all simulators | -+-----+-----------+-------------------------------+ -| | -GHDL | Compile for GHDL | -+-----+-----------+-------------------------------+ -| | -Questa | Compile for QuestaSim | -+-----+-----------+-------------------------------+ -| | -VHDL93 | Compile only for VHDL-93 | -+-----+-----------+-------------------------------+ -| | -VHDL2008 | Compile only for VHDL-2008 | -+-----+-----------+-------------------------------+ +.. |c-vivado-ps-h| replace:: ``-h`` +.. |c-vivado-ps-c| replace:: ``-c`` +.. |c-vivado-ps-a| replace:: ``-a`` +.. |c-vivado-ps-help| replace:: :option:`-Help ` +.. |c-vivado-ps-clean| replace:: :option:`-Clean ` +.. |c-vivado-ps-all| replace:: :option:`-All ` +.. |c-vivado-ps-ghdl| replace:: :option:`-GHDL ` +.. |c-vivado-ps-questa| replace:: :option:`-Questa ` +.. |c-vivado-ps-vhdl93| replace:: :option:`-VHDL93 ` +.. |c-vivado-ps-vhdl08| replace:: :option:`-VHDL2008 ` + ++------------------------------------------+---------------------------------------------------------------------------+ +| Common Option | Parameter Description | ++==================+=======================+===========================================================================+ +| |c-vivado-ps-h| | |c-vivado-ps-help| | Print embedded help page(s). | ++------------------+-----------------------+---------------------------------------------------------------------------+ +| |c-vivado-ps-c| | |c-vivado-ps-clean| | Clean-up directories. | ++------------------+-----------------------+---------------------------------------------------------------------------+ +| |c-vivado-ps-a| | |c-vivado-ps-all| | Compile for all simulators. | ++------------------+-----------------------+---------------------------------------------------------------------------+ +| | |c-vivado-ps-ghdl| | Compile for GHDL. | ++------------------+-----------------------+---------------------------------------------------------------------------+ +| | |c-vivado-ps-questa| | Compile for QuestaSim. | ++------------------+-----------------------+---------------------------------------------------------------------------+ +| | |c-vivado-ps-vhdl93| | GHDL only: Compile only for VHDL-93. | ++------------------+-----------------------+---------------------------------------------------------------------------+ +| | |c-vivado-ps-vhdl08| | GHDL only: Compile only for VHDL-2008. | ++------------------+-----------------------+---------------------------------------------------------------------------+ + +.. # =========================================================================================================================================================== +.. index:: + pair: Pre-compilation; Third-Party Libraries + +.. _USING:PreCompile:ThirdParty: Third-Party Libraries -********************* +**************************************************************************************************************************************************************** + +.. # =========================================================================================================================================================== +.. index:: + pair: Pre-compilation; OSVVM + +.. _USING:PreCompile:ThirdParty:OSVVM: OSVVM ===== @@ -340,19 +482,28 @@ On Linux **List of command line arguments:** -+------------------+-------------------------------+ -| Common Option | Description | -+=====+============+===============================+ -| -h | --help | Print embedded help page(s) | -+-----+------------+-------------------------------+ -| -c | --clean | Clean-up directories | -+-----+------------+-------------------------------+ -| -a | --all | Compile for all simulators | -+-----+------------+-------------------------------+ -| | --ghdl | Compile for GHDL | -+-----+------------+-------------------------------+ -| | --questa | Compile for QuestaSim | -+-----+------------+-------------------------------+ +.. |c-osvvm-sh-h| replace:: :option:`-h ` +.. |c-osvvm-sh-c| replace:: :option:`-c ` +.. |c-osvvm-sh-a| replace:: :option:`-a ` +.. |c-osvvm-sh-help| replace:: :option:`--help ` +.. |c-osvvm-sh-clean| replace:: :option:`--clean ` +.. |c-osvvm-sh-all| replace:: :option:`--all ` +.. |c-osvvm-sh-ghdl| replace:: :option:`--ghdl ` +.. |c-osvvm-sh-questa| replace:: :option:`--questa ` + ++----------------------------------------+-----------------------------------------------------------------------------+ +| Common Option | Parameter Description | ++=================+======================+=============================================================================+ +| |c-osvvm-sh-h| | |c-osvvm-sh-help| | Print embedded help page(s). | ++-----------------+----------------------+-----------------------------------------------------------------------------+ +| |c-osvvm-sh-c| | |c-osvvm-sh-clean| | Clean-up directories. | ++-----------------+----------------------+-----------------------------------------------------------------------------+ +| |c-osvvm-sh-a| | |c-osvvm-sh-all| | Compile for all simulators. | ++-----------------+----------------------+-----------------------------------------------------------------------------+ +| | |c-osvvm-sh-ghdl| | Compile for GHDL. | ++-----------------+----------------------+-----------------------------------------------------------------------------+ +| | |c-osvvm-sh-questa| | Compile for QuestaSim. | ++-----------------+----------------------+-----------------------------------------------------------------------------+ On Windows @@ -367,28 +518,206 @@ On Windows **List of command line arguments:** -+-----------------+-------------------------------+ -| Common Option | Description | -+=====+===========+===============================+ -| -h | -Help | Print embedded help page(s) | -+-----+-----------+-------------------------------+ -| -c | -Clean | Clean-up directories | -+-----+-----------+-------------------------------+ -| -a | -All | Compile for all simulators | -+-----+-----------+-------------------------------+ -| | -GHDL | Compile for GHDL | -+-----+-----------+-------------------------------+ -| | -Questa | Compile for QuestaSim | -+-----+-----------+-------------------------------+ +.. |c-osvvm-ps-h| replace:: ``-h`` +.. |c-osvvm-ps-c| replace:: ``-c`` +.. |c-osvvm-ps-a| replace:: ``-a`` +.. |c-osvvm-ps-help| replace:: :option:`-Help ` +.. |c-osvvm-ps-clean| replace:: :option:`-Clean ` +.. |c-osvvm-ps-all| replace:: :option:`-All ` +.. |c-osvvm-ps-ghdl| replace:: :option:`-GHDL ` +.. |c-osvvm-ps-questa| replace:: :option:`-Questa ` + ++----------------------------------------+-----------------------------------------------------------------------------+ +| Common Option | Parameter Description | ++=================+======================+=============================================================================+ +| |c-osvvm-ps-h| | |c-osvvm-ps-help| | Print embedded help page(s). | ++-----------------+----------------------+-----------------------------------------------------------------------------+ +| |c-osvvm-ps-c| | |c-osvvm-ps-clean| | Clean-up directories. | ++-----------------+----------------------+-----------------------------------------------------------------------------+ +| |c-osvvm-ps-a| | |c-osvvm-ps-all| | Compile for all simulators. | ++-----------------+----------------------+-----------------------------------------------------------------------------+ +| | |c-osvvm-ps-ghdl| | Compile for GHDL. | ++-----------------+----------------------+-----------------------------------------------------------------------------+ +| | |c-osvvm-ps-questa| | Compile for QuestaSim. | ++-----------------+----------------------+-----------------------------------------------------------------------------+ + +.. # =========================================================================================================================================================== +.. index:: + pair: Pre-compilation; UVVM + +.. _USING:PreCompile:ThirdParty:UVVM: + +UVVM +==== +On Linux +-------- + +.. code-block:: Bash + + # Example 1 - Compile for all Simulators + ./tools/precompile/compile-uvvm.sh --all + # Example 2 - Compile only for GHDL + ./tools/precompile/compile-uvvm.sh --ghdl + +**List of command line arguments:** + +.. |c-uvvm-sh-h| replace:: :option:`-h ` +.. |c-uvvm-sh-c| replace:: :option:`-c ` +.. |c-uvvm-sh-a| replace:: :option:`-a ` +.. |c-uvvm-sh-help| replace:: :option:`--help ` +.. |c-uvvm-sh-clean| replace:: :option:`--clean ` +.. |c-uvvm-sh-all| replace:: :option:`--all ` +.. |c-uvvm-sh-ghdl| replace:: :option:`--ghdl ` +.. |c-uvvm-sh-questa| replace:: :option:`--questa ` + ++--------------------------------------+-------------------------------------------------------------------------------+ +| Common Option | Parameter Description | ++================+=====================+===============================================================================+ +| |c-uvvm-sh-h| | |c-uvvm-sh-help| | Print embedded help page(s). | ++----------------+---------------------+-------------------------------------------------------------------------------+ +| |c-uvvm-sh-c| | |c-uvvm-sh-clean| | Clean-up directories. | ++----------------+---------------------+-------------------------------------------------------------------------------+ +| |c-uvvm-sh-a| | |c-uvvm-sh-all| | Compile for all simulators. | ++----------------+---------------------+-------------------------------------------------------------------------------+ +| | |c-uvvm-sh-ghdl| | Compile for GHDL. | ++----------------+---------------------+-------------------------------------------------------------------------------+ +| | |c-uvvm-sh-questa| | Compile for QuestaSim. | ++----------------+---------------------+-------------------------------------------------------------------------------+ + + +On Windows +---------- + +.. code-block:: PowerShell + + # Example 1 - Compile for all Simulators + .\tools\precompile\compile-uvvm.ps1 -All + # Example 2 - Compile only for GHDL + .\tools\precompile\compile-uvvm.ps1 -GHDL + +**List of command line arguments:** + +.. |c-uvvm-ps-h| replace:: ``-h`` +.. |c-uvvm-ps-c| replace:: ``-c`` +.. |c-uvvm-ps-a| replace:: ``-a`` +.. |c-uvvm-ps-help| replace:: :option:`-Help ` +.. |c-uvvm-ps-clean| replace:: :option:`-Clean ` +.. |c-uvvm-ps-all| replace:: :option:`-All ` +.. |c-uvvm-ps-ghdl| replace:: :option:`-GHDL ` +.. |c-uvvm-ps-questa| replace:: :option:`-Questa ` + ++--------------------------------------+-------------------------------------------------------------------------------+ +| Common Option | Parameter Description | ++================+=====================+===============================================================================+ +| |c-uvvm-ps-h| | |c-uvvm-ps-help| | Print embedded help page(s). | ++----------------+---------------------+-------------------------------------------------------------------------------+ +| |c-uvvm-ps-c| | |c-uvvm-ps-clean| | Clean-up directories. | ++----------------+---------------------+-------------------------------------------------------------------------------+ +| |c-uvvm-ps-a| | |c-uvvm-ps-all| | Compile for all simulators. | ++----------------+---------------------+-------------------------------------------------------------------------------+ +| | |c-uvvm-ps-ghdl| | Compile for GHDL. | ++----------------+---------------------+-------------------------------------------------------------------------------+ +| | |c-uvvm-ps-questa| | Compile for QuestaSim. | ++----------------+---------------------+-------------------------------------------------------------------------------+ + +.. # =========================================================================================================================================================== + .. index:: + pair: Pre-compilation; VUnit + + .. _USING:PreCompile:ThirdParty:VUnit: + + VUnit + ===== + + On Linux + -------- + + .. code-block:: Bash + + # Example 1 - Compile for all Simulators + ./tools/precompile/compile-vunit.sh --all + # Example 2 - Compile only for GHDL + ./tools/precompile/compile-vunit.sh --ghdl + + **List of command line arguments:** + + .. |c-vunit-sh-h| replace:: :option:`-h ` + .. |c-vunit-sh-c| replace:: :option:`-c ` + .. |c-vunit-sh-a| replace:: :option:`-a ` + .. |c-vunit-sh-help| replace:: :option:`--help ` + .. |c-vunit-sh-clean| replace:: :option:`--clean ` + .. |c-vunit-sh-all| replace:: :option:`--all ` + .. |c-vunit-sh-ghdl| replace:: :option:`--ghdl ` + .. |c-vunit-sh-questa| replace:: :option:`--questa ` + + +----------------------------------------+-----------------------------------------------------------------------------+ + | Common Option | Parameter Description | + +=================+======================+=============================================================================+ + | |c-vunit-sh-h| | |c-vunit-sh-help| | Print embedded help page(s). | + +-----------------+----------------------+-----------------------------------------------------------------------------+ + | |c-vunit-sh-c| | |c-vunit-sh-clean| | Clean-up directories. | + +-----------------+----------------------+-----------------------------------------------------------------------------+ + | |c-vunit-sh-a| | |c-vunit-sh-all| | Compile for all simulators. | + +-----------------+----------------------+-----------------------------------------------------------------------------+ + | | |c-vunit-sh-ghdl| | Compile for GHDL. | + +-----------------+----------------------+-----------------------------------------------------------------------------+ + | | |c-vunit-sh-questa| | Compile for QuestaSim. | + +-----------------+----------------------+-----------------------------------------------------------------------------+ + + + On Windows + ---------- + + .. code-block:: PowerShell + + # Example 1 - Compile for all Simulators + .\tools\precompile\compile-vunit.ps1 -All + # Example 2 - Compile only for GHDL + .\tools\precompile\compile-vunit.ps1 -GHDL + + **List of command line arguments:** + + .. |c-vunit-ps-h| replace:: ``-h`` + .. |c-vunit-ps-c| replace:: ``-c`` + .. |c-vunit-ps-a| replace:: ``-a`` + .. |c-vunit-ps-help| replace:: :option:`-Help ` + .. |c-vunit-ps-clean| replace:: :option:`-Clean ` + .. |c-vunit-ps-all| replace:: :option:`-All ` + .. |c-vunit-ps-ghdl| replace:: :option:`-GHDL ` + .. |c-vunit-ps-questa| replace:: :option:`-Questa ` + + +----------------------------------------+-------------------------------------------------------------------------------+ + | Common Option | Parameter Description | + +=================+======================+===============================================================================+ + | |c-vunit-ps-h| | |c-vunit-ps-help| | Print embedded help page(s). | + +-----------------+----------------------+-------------------------------------------------------------------------------+ + | |c-vunit-ps-c| | |c-vunit-ps-clean| | Clean-up directories. | + +-----------------+----------------------+-------------------------------------------------------------------------------+ + | |c-vunit-ps-a| | |c-vunit-ps-all| | Compile for all simulators. | + +-----------------+----------------------+-------------------------------------------------------------------------------+ + | | |c-vunit-ps-ghdl| | Compile for GHDL. | + +-----------------+----------------------+-------------------------------------------------------------------------------+ + | | |c-vunit-ps-questa| | Compile for QuestaSim. | + +-----------------+----------------------+-------------------------------------------------------------------------------+ + +.. # =========================================================================================================================================================== +.. index:: + pair: Pre-compilation; Simulator Adapters + +.. _USING:PreCompile:Adapter: Simulator Adapters -****************** +**************************************************************************************************************************************************************** + +.. index:: + pair: Pre-compilation; Cocotb + +.. _USING:PreCompile:Adapter:Cocotb: Cocotb ====== - On Linux -------- @@ -404,19 +733,28 @@ On Linux **List of command line arguments:** -+------------------+-------------------------------+ -| Common Option | Description | -+=====+============+===============================+ -| -h | --help | Print embedded help page(s) | -+-----+------------+-------------------------------+ -| -c | --clean | Clean-up directories | -+-----+------------+-------------------------------+ -| -a | --all | Compile for all simulators | -+-----+------------+-------------------------------+ -| | --ghdl | Compile for GHDL | -+-----+------------+-------------------------------+ -| | --questa | Compile for QuestaSim | -+-----+------------+-------------------------------+ +.. |c-cocotb-sh-h| replace:: :option:`-h ` +.. |c-cocotb-sh-c| replace:: :option:`-c ` +.. |c-cocotb-sh-a| replace:: :option:`-a ` +.. |c-cocotb-sh-help| replace:: :option:`--help ` +.. |c-cocotb-sh-clean| replace:: :option:`--clean ` +.. |c-cocotb-sh-all| replace:: :option:`--all ` +.. |c-cocotb-sh-ghdl| replace:: :option:`--ghdl ` +.. |c-cocotb-sh-questa| replace:: :option:`--questa ` + ++----------------------------------------+-----------------------------------------------------------------------------+ +| Common Option | Parameter Description | ++=================+======================+=============================================================================+ +| |c-cocotb-sh-h| | |c-cocotb-sh-help| | Print embedded help page(s). | ++-----------------+----------------------+-----------------------------------------------------------------------------+ +| |c-cocotb-sh-c| | |c-cocotb-sh-clean| | Clean-up directories. | ++-----------------+----------------------+-----------------------------------------------------------------------------+ +| |c-cocotb-sh-a| | |c-cocotb-sh-all| | Compile for all simulators. | ++-----------------+----------------------+-----------------------------------------------------------------------------+ +| | |c-cocotb-sh-ghdl| | Compile for GHDL. | ++-----------------+----------------------+-----------------------------------------------------------------------------+ +| | |c-cocotb-sh-questa| | Compile for QuestaSim. | ++-----------------+----------------------+-----------------------------------------------------------------------------+ On Windows @@ -434,21 +772,30 @@ On Windows **List of command line arguments:** -+-----------------+-------------------------------+ -| Common Option | Description | -+=====+===========+===============================+ -| -h | -Help | Print embedded help page(s) | -+-----+-----------+-------------------------------+ -| -c | -Clean | Clean-up directories | -+-----+-----------+-------------------------------+ -| -a | -All | Compile for all simulators | -+-----+-----------+-------------------------------+ -| | -GHDL | Compile for GHDL | -+-----+-----------+-------------------------------+ -| | -Questa | Compile for QuestaSim | -+-----+-----------+-------------------------------+ - -.. comment +.. |c-cocotb-ps-h| replace:: ``-h`` +.. |c-cocotb-ps-c| replace:: ``-c`` +.. |c-cocotb-ps-a| replace:: ``-a`` +.. |c-cocotb-ps-help| replace:: :option:`-Help ` +.. |c-cocotb-ps-clean| replace:: :option:`-Clean ` +.. |c-cocotb-ps-all| replace:: :option:`-All ` +.. |c-cocotb-ps-ghdl| replace:: :option:`-GHDL ` +.. |c-cocotb-ps-questa| replace:: :option:`-Questa ` + ++----------------------------------------+-----------------------------------------------------------------------------+ +| Common Option | Parameter Description | ++=================+======================+=============================================================================+ +| |c-cocotb-ps-h| | |c-cocotb-ps-help| | Print embedded help page(s). | ++-----------------+----------------------+-----------------------------------------------------------------------------+ +| |c-cocotb-ps-c| | |c-cocotb-ps-clean| | Clean-up directories. | ++-----------------+----------------------+-----------------------------------------------------------------------------+ +| |c-cocotb-ps-a| | |c-cocotb-ps-all| | Compile for all simulators. | ++-----------------+----------------------+-----------------------------------------------------------------------------+ +| | |c-cocotb-ps-ghdl| | Compile for GHDL. | ++-----------------+----------------------+-----------------------------------------------------------------------------+ +| | |c-cocotb-ps-questa| | Compile for QuestaSim. | ++-----------------+----------------------+-----------------------------------------------------------------------------+ + +.. # Supported Simulators: diff --git a/docs/UsingPoC/ProjectManagement.rst b/docs/UsingPoC/ProjectManagement.rst index 0343913e..bff3930a 100644 --- a/docs/UsingPoC/ProjectManagement.rst +++ b/docs/UsingPoC/ProjectManagement.rst @@ -1,3 +1,4 @@ +.. _USING:Project: Project Management ################## diff --git a/docs/UsingPoC/Requirements.rst b/docs/UsingPoC/Requirements.rst index be08a693..e34021c4 100644 --- a/docs/UsingPoC/Requirements.rst +++ b/docs/UsingPoC/Requirements.rst @@ -1,9 +1,12 @@ .. # Load pre-defined aliases from docutils # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include .. include:: +.. _USING:Require: + Requirements ############ @@ -16,11 +19,12 @@ platform independent scripting environment. All Python scripts are wrapped in Bash or PowerShell scripts, to hide some platform specifics of Darwin, Linux or Windows. +.. _USING:Require:Common: + Common requirements: ******************** -* Programming Languages and Runtime Environments: - +Programming Languages and Runtime Environments: * `Python 3 `_ (|geq| 3.5): * `colorama `_ @@ -28,104 +32,118 @@ Common requirements: All Python requirements are listed in `requirements.txt `_ and can be installed via: |br| ``sudo python3.5 -m pip install -r requirements.txt`` - -* Synthesis tool chains: - - * Altera Quartus |geq| 13.0 or - * Lattice Diamond or +Synthesis tool chains: + * Altera Quartus II |geq| 13.0 or + * Altera Quartus Prime |geq| 15.1 or + * Intel Quartus Prime |geq| 16.1 or + * Lattice Diamond |geq| 3.6 or * Xilinx ISE 14.7 [#f1]_ or - * Xilinx Vivado [#f2]_ - -* Simulation tool chains - - * Aldec Active-HDL or + * Xilinx Vivado |geq| 2016.3 [#f2]_ +Simulation tool chains + * Aldec Active-HDL (or Student Edition) or + * Aldec Active-HDL Lattice Edition or + * Mentor Graphics ModelSim PE (or Student Edition) or + * Mentor Graphics ModelSim SE or * Mentor Graphics ModelSim Altera Edition or * Mentor Graphics QuestaSim or * Xilinx ISE Simulator 14.7 or - * Xilinx Vivado Simulator |geq| 2016.1 [#f3]_ or + * Xilinx Vivado Simulator |geq| 2016.3 [#f3]_ or * `GHDL `_ |geq| 0.34dev and `GTKWave `_ |geq| 3.3.70 +.. _USING:Require:Linux: + Linux specific requirements: **************************** -* Debian and Ubuntu specific: - - * bash is configured as :file:`/bin/sh` (`read more `_) |br| +Debian and Ubuntu specific: + * ``bash`` is configured as :file:`/bin/sh` (`read more `_) |br| ``dpkg-reconfigure dash`` Optional Tools on Linux: ======================== -* Git - The command line tools to manage Git repositories. It's possible to extend - the shell prompt with Git information. +Git + The command line tools to manage Git repositories. It's possible to extend + the shell prompt with Git information. +SmartGit + A Git client to handle complex Git flows in a GUI. +`Generic Colouriser `_ (grc) |geq| 1.9 + Colorizes outputs of foreign scripts and programs. GRC is hosted on `GitHub `_ + The latest *.deb installation packages can be downloaded `here `_. -* SmartGit - A Git client to handle complex Git flows in a GUI. - -* `Generic Colouriser `_ (grc) |geq| 1.9 - Colorizes outputs of foreign scripts and programs. GRC is hosted on `GitHub `_ - The latest *.deb installation packages can be downloaded `here `_. +.. _USING:Require:MacOS: Mac OS specific requirements: ***************************** -* Bash |geq| 4.3 - Mac OS is shipped with Bash 3.2. Use Homebrew to install an up-to-date Bash |br| - ``brew install bash`` - -* coreutils - Mac OS' ``readlink`` program has a different behavior than the Linux version. - The ``coreutils`` package installs a GNU readlink clone called ``greadlink``. |br| - ``brew install coreutils`` +Bash |geq| 4.3 + Mac OS is shipped with Bash 3.2. Use Homebrew to install an up-to-date Bash |br| + ``brew install bash`` +coreutils + Mac OS' ``readlink`` program has a different behavior than the Linux version. + The ``coreutils`` package installs a GNU readlink clone called ``greadlink``. |br| + ``brew install coreutils`` Optional Tools on Mac OS: ========================= -* Git - The command line tools to manage Git repositories. It's possible to extend - the shell prompt with Git information. +Git + The command line tools to manage Git repositories. It's possible to extend + the shell prompt with Git information. +SmartGit or SourceTree + A Git client to handle complex Git flows in a GUI. +`Generic Colouriser `_ (grc) |geq| 1.9 + Colorizes outputs of foreign scripts and programs. GRC is hosted on `GitHub `_ |br| + ``brew install Grc`` -* SmartGit or SourceTree - A Git client to handle complex Git flows in a GUI. - -* `Generic Colouriser `_ (grc) |geq| 1.9 - Colorizes outputs of foreign scripts and programs. GRC is hosted on `GitHub `_ |br| - ``brew install Grc`` +.. _USING:Require:Windows: Windows specific requirements: ****************************** -* PowerShell |geq| 4.0 - PowerShell shipped with Windows since Vista. It is a part if the Windows - Management Framework. If the required version not already included in - Windows, it can be downloaded from microsoft.com: `WMF 4.0 `_, - `WMF 5.0 `_ (recommended). +PowerShell + * **Allow local script execution** (`read more `_) |br| + ``PS> Set-ExecutionPolicy RemoteSigned`` + + * **PowerShell** |geq| **5.0 (recommended)** |br| + PowerShell 5.0 is shipped since Windows 10. It is a part if the `Windows Management Framework 5.0 `_ + (WMF). Windows 7 and 8/8.1 can be updated to WMF 5.0. The package does not + include **PSReadLine**, which is included in the Windows 10 + PowerShell environment. Install PSReadLine manually: |br| + ``PS> Install-Module PSReadline``. - * Allow local script execution (`read more `_) |br| - ``Set-ExecutionPolicy RemoteSigned`` - * PowerShell Community Extensions (PSCX) |geq| 3.2 |br| - The latest PSCX can be downloaded from `PowerShellGallery `_ + * **PowerShell 4.0** |br| + PowerShell is shipped with Windows since Vista. If the required version + not already included in Windows, it can be downloaded from Microsoft.com: + `WMF 4.0 `_ Optional Tools on Windows: ========================== -* Git (MSys-Git) - The command line tools to manage Git repositories. +PowerShell |geq| 4.0 + * **PSReadLine** replaces the command line editing experience in PowerShell for versions 3 and up. + * **PowerShell Community Extensions (PSCX)** |geq| **3.2** |br| + The latest PSCX can be downloaded from `PowerShellGallery `_ |br| + ``PS> Install-Module Pscx`` |br| + Note: PSCX |geq| 3.2.1 is required for PowerShell |geq| 5.0. + +Git (MSys-Git) + The command line tools to manage Git repositories. -* SmartGit or SourceTree - A Git client to handle complex Git flows in a GUI. +SmartGit or SourceTree + A Git client to handle complex Git flows in a GUI. -* `posh-git `_ - PowerShell integration for Git |br| - Installing posh-git with `PsGet `_ package manager: ``Install-Module posh-git`` +`posh-git `_ + PowerShell integration for Git |br| + ``PS> Install-Module posh-git`` +.. # Installing posh-git with `PsGet `_ package manager: |br| ------------------------------------------ diff --git a/docs/UsingPoC/Simulation.rst b/docs/UsingPoC/Simulation.rst index c48e1519..9a1c1fcf 100644 --- a/docs/UsingPoC/Simulation.rst +++ b/docs/UsingPoC/Simulation.rst @@ -1,3 +1,4 @@ +.. _USING:Sim: Simulation ########## @@ -6,6 +7,8 @@ Simulation :local: +.. _USING:Sim:Over: + Overview ******** @@ -34,6 +37,8 @@ frontend script: See the Intruction page for a list of supported simulators. +.. _USING:Sim:Quick: + Quick Example ************* @@ -86,6 +91,8 @@ The opened waveform viewer and displayed waveform should look like this: :alt: GTKWave waveform view of PoC.arith.prng. +.. _USING:Sim:Vendor: + Vendor Specific Testbenches *************************** @@ -128,6 +135,9 @@ A vendor specific testbench can be launched by passing either ``--board=xxx`` or and common storage for all supported vendor's pre-compile procedures. See :doc:`Pre-Compiling Vendor Libraries `. + +.. _USING:Sim:Single: + Running a Single Testbench ************************** @@ -180,6 +190,8 @@ PoC runs multiple testbenches at once, all finished testbenches are reported wit there testbench result. The aborted testbench will be listed as errored. +.. _USING:Sim:Aldec-ActiveHDL: + Aldec Active-HDL ================ @@ -207,6 +219,8 @@ PoC entities. The following options are supported for Active-HDL: .\poc.ps1 asim PoC.arith.prng --std=93 +.. _USING:Sim:Cocotb: + Cocotb with QuestaSim backend ============================= @@ -235,6 +249,8 @@ by a list of PoC entities. The following options are supported for Cocotb: .\poc.ps1 cocotb PoC.cache.par +.. _USING:Sim:GHDL: + GHDL (plus GTKwave) =================== @@ -261,6 +277,8 @@ PoC entities. The following options are supported for GHDL: .\poc.ps1 ghdl PoC.arith.prng --board=Atlys -g +.. _USING:Sim:Mentor-QuestaSim: + Mentor Graphics QuestaSim ========================= @@ -287,6 +305,23 @@ QuestaSim: cd PoCRoot .\poc.ps1 vsim PoC.arith.prng --board=DE4 --gui +If QuestaSim is started in GUI mode (:option:`--gui`), PoC will provide several +Tcl files (:file:`*.do`) in the simulator's working directory to recompile, +restart or rerun the current simulation. The rerun command is based on the saved +IP core's run script, which may default to ``run -all``. + ++--------------------------+---------------------------------------------------------+ +| Tcl Script | Performed Tasks | ++==========================+=========================================================+ +| :file:`recompile.do` | recompile and restart | ++--------------------------+---------------------------------------------------------+ +| :file:`relaunch.do` | recompile, restart and rerun | ++--------------------------+---------------------------------------------------------+ +| :file:`saveWaveform.do` | save the current waveform viewer settings | ++--------------------------+---------------------------------------------------------+ + + +.. _USING:Sim:Xilinx-iSim: Xilinx ISE Simulator ==================== @@ -313,6 +348,8 @@ ISE Simulator: .\poc.ps1 isim PoC.arith.prng --board=Atlys -g +.. _USING:Sim:Xilinx-xSim: + Xilinx Vivado Simulator ======================= @@ -340,6 +377,8 @@ Vivado Simulator: .\poc.ps1 xsim PoC.arith.prng --board=Atlys -g +.. _USING:Sim:Group: + Running a Group of Testbenches ****************************** @@ -378,6 +417,8 @@ current namespace and all sub-namespaces. :alt: Report after running multiple testbenches in Active-HDL. +.. _USING:Sim:CI: + Continuous Integration (CI) *************************** @@ -417,4 +458,3 @@ Terrasic DE4 board: `Latest Travis-CI Report `_ Browse the list of branches at Travis-CI.org. - diff --git a/docs/UsingPoC/Synthesis.rst b/docs/UsingPoC/Synthesis.rst index 7c533070..527cb89c 100644 --- a/docs/UsingPoC/Synthesis.rst +++ b/docs/UsingPoC/Synthesis.rst @@ -1,3 +1,4 @@ +.. _USING:Synth: Synthesis ######### @@ -6,6 +7,8 @@ Synthesis :local: +.. _USING:Synth:Over: + Overview ******** @@ -25,10 +28,10 @@ one of PoC's frontend script: .. seealso:: - :doc:`PoC Configuration ` + :ref:`PoC Configuration ` See the Configuration page on how to configure PoC and your installed synthesis tool chains. This is required to invoke the compilers. - :doc:`Supported Compiler ` + :ref:`Supported Compiler ` See the Intruction page for a list of supported compilers. @@ -38,6 +41,9 @@ one of PoC's frontend script: :doc:`List of Supported Development Boards ` See this list to find a supported and well known development board. + +.. _USING:Synth:Quick: + Quick Example ************* @@ -65,65 +71,93 @@ synthesized to a netlist. :alt: PowerShell console output after running PoC.arith.prng with XST. +.. _USING:Synth:Single: + Running a single Synthesis ************************** -A synthesis run is supervised by PoC's ``PoCRoot\py\PoC.py`` service tool, -which offers a consistent interface to all synthesizers. Unfortunately, every -platform has it's specialties, so a wrapper script is needed as abstraction from -the host's operating system. Depending on the choosen tool chain, the wrapper -script will source or invoke the vendor tool's environment scripts to pre-load -the needed environment variables, paths or license file settings. +A synthesis run is supervised by PoC's :ref:`PoCRoot\\py\\PoC.py ` +service tool, which offers a consistent interface to all synthesizers. +Unfortunately, every platform has it's specialties, so a wrapper script is +needed as abstraction from the host's operating system. Depending on the choosen +tool chain, the wrapper script will source or invoke the vendor tool's +environment scripts to pre-load the needed environment variables, paths or +license file settings. The order of options to the frontend script is as following: -`` `` +`` [] `` The frontend offers several common options: -+-----------------+-------------------------------+ -| Common Option | Description | -+=====+===========+===============================+ -| -q | --quiet | Quiet-mode (print nothing) | -+-----+-----------+-------------------------------+ -| -v | --verbose | Print more messages | -+-----+-----------+-------------------------------+ -| -d | --debug | Debug mode (print everything) | -+-----+-----------+-------------------------------+ -| | --dryrun | Run in dry-run mode | -+-----+-----------+-------------------------------+ +.. |-q| replace:: :option:`-q ` +.. |-v| replace:: :option:`-v ` +.. |-d| replace:: :option:`-d ` +.. |--quiet| replace:: :option:`--quiet ` +.. |--verbose| replace:: :option:`--verbose ` +.. |--debug| replace:: :option:`--debug ` +.. |--dryrun| replace:: :option:`--dryrun ` + ++--------------------+---------------------------------------------------------+ +| Common Option | Description | ++======+=============+=========================================================+ +| |-q| | |--quiet| | Quiet-mode (print nothing) | ++------+-------------+---------------------------------------------------------+ +| |-v| | |--verbose| | Print more messages | ++------+-------------+---------------------------------------------------------+ +| |-d| | |--debug| | Debug mode (print everything) | ++------+-------------+---------------------------------------------------------+ +| | |--dryrun| | Run in dry-run mode | ++------+-------------+---------------------------------------------------------+ + One of the following supported synthesizers can be choosen, if installed and configured in PoC: -+-----------+--------------------------------------------------+ -| Simulator | Description | -+===========+==================================================+ -| quartus | Altera Quartus II or Quartus Prime | -+-----------+--------------------------------------------------+ -| lse | Lattice Diamond - Lattice Synthesis Engine (LSE) | -+-----------+--------------------------------------------------+ -| xst | Xilinx ISE Systhesis Tool (XST) | -+-----------+--------------------------------------------------+ -| coregen | Xilinx ISE Core Generator (CoreGen) | -+-----------+--------------------------------------------------+ -| vivado | Xilinx Vivado Synthesis | -+-----------+--------------------------------------------------+ - - -Altera Quartus -============== - -The command to invoke a synthesis using Altera Quartus II or Quartus Prime is -``quartus`` followed by a list of PoC entities. The following options are +.. |l-quartus| replace:: :ref:`Altera Quartus II or Intel Quartus Prime ` +.. |r-quartus| replace:: :ref:`PoC.py quartus ` +.. |l-lse| replace:: :ref:`Lattice (Diamond) Synthesis Engine (LSE) ` +.. |r-lse| replace:: :ref:`PoC.py lse ` +.. |l-xst| replace:: :ref:`Xilinx ISE Systhesis Tool (XST) ` +.. |r-xst| replace:: :ref:`PoC.py xst ` +.. |l-coregen| replace:: :ref:`Xilinx ISE Core Generator (CoreGen) ` +.. |r-coregen| replace:: :ref:`PoC.py coregen ` +.. |l-vivado| replace:: :ref:`Xilinx Vivado Synthesis ` +.. |r-vivado| replace:: :ref:`PoC.py vivado ` + ++---------------------------------+--------------------------------------------+ +| Synthesizer | Command Reference | ++=================================+============================================+ +| |l-quartus| | |r-quartus| | ++---------------------------------+--------------------------------------------+ +| |l-lse| | |r-lse| | ++---------------------------------+--------------------------------------------+ +| |l-xst| | |r-xst| | ++---------------------------------+--------------------------------------------+ +| |l-coregen| | |r-coregen| | ++---------------------------------+--------------------------------------------+ +| |l-vivado| | |r-vivado| | ++---------------------------------+--------------------------------------------+ + + +.. _USING:Synth:Altera-Quartus: + +Altera / Intel Quartus +====================== + +The command to invoke a synthesis using Altera Quartus II or Intel Quartus Prime is +:ref:`quartus ` followed by a list of PoC entities. The following options are supported for Quartus: -+--------------------------+---------------------------------------------------------+ -| Simulator Option | Description | -+====+=====================+=========================================================+ -| | --board= | Specify a target board. | -+----+---------------------+---------------------------------------------------------+ -| | --device= | Specify a target device. | -+----+---------------------+---------------------------------------------------------+ +.. |quartus--board| replace:: :option:`--board=\ ` +.. |quartus--device| replace:: :option:`--device=\ ` + ++--------------------------+---------------------------------------------------+ +| Simulator Option | Description | ++====+=====================+===================================================+ +| | |quartus--board| | Specify a target board. | ++----+---------------------+---------------------------------------------------+ +| | |quartus--device| | Specify a target device. | ++----+---------------------+---------------------------------------------------+ .. rubric:: Example: @@ -133,95 +167,116 @@ supported for Quartus: .\poc.ps1 quartus PoC.arith.prng --board=DE4 +.. _USING:Synth:Lattice-Diamond: + Lattice Diamond =============== -The command to invoke a synthesis using Altera Quartus II or Quartus Prime is -``quartus`` followed by a list of PoC entities. The following options are -supported for Quartus: +The command to invoke a synthesis using Lattice Diamond is :ref:`lse ` followed by +a list of PoC entities. The following options are supported for the Lattice +Synthesis Engine (LSE): + +.. |lse--board| replace:: :option:`--board=\ ` +.. |lse--device| replace:: :option:`--device=\ ` -+--------------------------+---------------------------------------------------------+ -| Simulator Option | Description | -+====+=====================+=========================================================+ -| | --board= | Specify a target board. | -+----+---------------------+---------------------------------------------------------+ -| | --device= | Specify a target device. | -+----+---------------------+---------------------------------------------------------+ ++--------------------+---------------------------------------------------------+ +| Simulator Option | Description | ++====+===============+=========================================================+ +| | |lse--board| | Specify a target board. | ++----+---------------+---------------------------------------------------------+ +| | |lse--device| | Specify a target device. | ++----+---------------+---------------------------------------------------------+ .. rubric:: Example: .. code-block:: PowerShell cd PoCRoot - .\poc.ps1 quartus PoC.arith.prng --board=DE4 + .\poc.ps1 lse PoC.arith.prng --board=ECP5Versa + +.. _USING:Synth:Xilinx-ISE: Xilinx ISE Synthesis Tool (XST) =============================== -The command to invoke a synthesis using Altera Quartus II or Quartus Prime is -``quartus`` followed by a list of PoC entities. The following options are -supported for Quartus: +The command to invoke a synthesis using Xilinx ISE Synthesis is :ref:`xst ` followed +by a list of PoC entities. The following options are supported for the Xilinx +Synthesis Tool (XST): -+--------------------------+---------------------------------------------------------+ -| Simulator Option | Description | -+====+=====================+=========================================================+ -| | --board= | Specify a target board. | -+----+---------------------+---------------------------------------------------------+ -| | --device= | Specify a target device. | -+----+---------------------+---------------------------------------------------------+ +.. |xst--board| replace:: :option:`--board=\ ` +.. |xst--device| replace:: :option:`--device=\ ` + ++--------------------+---------------------------------------------------------+ +| Simulator Option | Description | ++====+===============+=========================================================+ +| | |xst--board| | Specify a target board. | ++----+---------------+---------------------------------------------------------+ +| | |xst--device| | Specify a target device. | ++----+---------------+---------------------------------------------------------+ .. rubric:: Example: .. code-block:: PowerShell cd PoCRoot - .\poc.ps1 quartus PoC.arith.prng --board=DE4 + .\poc.ps1 xst PoC.arith.prng --board=KC705 +.. _USING:Synth:Xilinx-CoreGen: + Xilinx ISE Core Generator ========================= -The command to invoke a synthesis using Altera Quartus II or Quartus Prime is -``quartus`` followed by a list of PoC entities. The following options are -supported for Quartus: +The command to invoke an IP core generation using Xilinx Core Generator is +:ref:`coregen ` followed by a list of PoC entities. The following options are +supported for Core Generator (CG): + +.. |cg--board| replace:: :option:`--board=\ ` +.. |cg--device| replace:: :option:`--device=\ ` -+--------------------------+---------------------------------------------------------+ -| Simulator Option | Description | -+====+=====================+=========================================================+ -| | --board= | Specify a target board. | -+----+---------------------+---------------------------------------------------------+ -| | --device= | Specify a target device. | -+----+---------------------+---------------------------------------------------------+ ++-------------------+----------------------------------------------------------+ +| Simulator Option | Description | ++====+==============+==========================================================+ +| | |cg--board| | Specify a target board. | ++----+--------------+----------------------------------------------------------+ +| | |cg--device| | Specify a target device. | ++----+--------------+----------------------------------------------------------+ .. rubric:: Example: .. code-block:: PowerShell cd PoCRoot - .\poc.ps1 quartus PoC.arith.prng --board=DE4 + .\poc.ps1 coregen PoC.xil.mig.Atlys_1x128 --board=Atlys + + +.. _USING:Synth:Xilinx-Vivado: Xilinx Vivado Synthesis ======================= -The command to invoke a synthesis using Altera Quartus II or Quartus Prime is -``quartus`` followed by a list of PoC entities. The following options are -supported for Quartus: +The command to invoke a synthesis using Xilinx Vivado Synthesis is :ref:`vivado ` +followed by a list of PoC entities. The following options are supported for +Vivado Synthesis (Synth): + +.. |vivado--board| replace:: :option:`--board=\ ` +.. |vivado--device| replace:: :option:`--device=\ ` -+--------------------------+---------------------------------------------------------+ -| Simulator Option | Description | -+====+=====================+=========================================================+ -| | --board= | Specify a target board. | -+----+---------------------+---------------------------------------------------------+ -| | --device= | Specify a target device. | -+----+---------------------+---------------------------------------------------------+ ++-----------------------+------------------------------------------------------+ +| Simulator Option | Description | ++====+==================+======================================================+ +| | |vivado--board| | Specify a target board. | ++----+------------------+------------------------------------------------------+ +| | |vivado--device| | Specify a target device. | ++----+------------------+------------------------------------------------------+ .. rubric:: Example: .. code-block:: PowerShell cd PoCRoot - .\poc.ps1 quartus PoC.arith.prng --board=DE4 + .\poc.ps1 vivado PoC.arith.prng --board=KC705 diff --git a/docs/UsingPoC/VHDLConfiguration.rst b/docs/UsingPoC/VHDLConfiguration.rst index 84abc147..f4bc7270 100644 --- a/docs/UsingPoC/VHDLConfiguration.rst +++ b/docs/UsingPoC/VHDLConfiguration.rst @@ -1,22 +1,26 @@ +.. _USING:VHDLConf: Creating my_config/my_project.vhdl ################################## -The PoC-Library needs two VHDL files for it's configuration. These files are +The PoC-Library needs two VHDL files for its configuration. These files are used to determine the most suitable implementation depending on the provided platform information. These files are also used to select appropiate work arounds. + +.. _USING:VHDLConf:myconfig: + Create my_config.vhdl ********************* The **my_config.vhdl** file can easily be created from the template file ``my_config.vhdl.template`` provided by PoC in ``PoCRoot\src\common``. (View source on `GitHub `_.) -Copy this file into the projects source directory and renamed into +Copy this file into the project's source directory and rename it to ``my_config.vhdl``. -This file should be included into version control systems and shared with other +This file should be included in version control systems and shared with other systems. ``my_config.vhdl`` defines three global constants, which need to be adjusted: @@ -27,7 +31,7 @@ adjusted: constant MY_VERBOSE : boolean := FALSE; -- activate report statements in VHDL subprograms The easiest way is to define a board name and set ``MY_DEVICE`` to ``None``. -So the device name is infered from the board information stored in ``PoCRoot\src\common\board.vhdl``. +So the device name is infered from the board information stored in ``PoCRoot\src\common\config.vhdl``. If the requested board is not known to PoC or it's custom made, then set ``MY_BOARD`` to ``Custom`` and ``MY_DEVICE`` to the full FPGA device string. @@ -46,6 +50,8 @@ If the requested board is not known to PoC or it's custom made, then set constant MY_DEVICE : string := "XC6SLX45-3CSG324"; +.. _USING:VHDLConf:myproject: + Create my_project.vhdl ********************** diff --git a/docs/UsingPoC/index.rst b/docs/UsingPoC/index.rst index 4e0c6206..9d8f8142 100644 --- a/docs/UsingPoC/index.rst +++ b/docs/UsingPoC/index.rst @@ -1,8 +1,9 @@ +.. _USING: Using PoC ######### -PoC can be used in several ways, if all :doc:`Requirements ` +PoC can be used in several ways, if all :ref:`Requirements ` are fulfilled. Chose one of the following integration kinds: * Stand-Alone IP Core Library: @@ -25,8 +26,8 @@ are fulfilled. Chose one of the following integration kinds: * No possibility to contribute bugfixes and extensions via Git pull requests. **Next steps:** |br| - 1. See :doc:`Downloads ` for how to download a stand-alone version (*.zip-file) of the PoC-Library. |br| - 2. See :doc:`Configuration ` for how to configure PoC on a local system. + 1. See :ref:`Downloads ` for how to download a stand-alone version (*.zip-file) of the PoC-Library. |br| + 2. See :ref:`Configuration ` for how to configure PoC on a local system. * Stand-Alone IP Core Library cloned from Git: Download PoC via ``git clone`` from GitHub as latest branch copy. IP cores @@ -48,8 +49,8 @@ are fulfilled. Chose one of the following integration kinds: * Using different PoC versions in different projects is not possible **Next steps:** |br| - 1. See :doc:`Downloads ` for how to clone a stand-alone version of the PoC-Library. |br| - 2. See :doc:`Configuration ` for how to configure PoC on a local system. + 1. See :ref:`Downloads ` for how to clone a stand-alone version of the PoC-Library. |br| + 2. See :ref:`Configuration ` for how to configure PoC on a local system. * Embedded IP Core Library as Git Submodule: Integrate PoC as a Git submodule into the destination projects Git repository. @@ -67,8 +68,8 @@ are fulfilled. Chose one of the following integration kinds: * Version linking between hosting Git and PoC. **Next steps:** |br| - 1. See :doc:`Integration ` for how to integrate PoC as a Git submodule into an existing Git. |br| - 2. See :doc:`Configuration ` for how to configure PoC on a local system. + 1. See :ref:`Integration ` for how to integrate PoC as a Git submodule into an existing Git. |br| + 2. See :ref:`Configuration ` for how to configure PoC on a local system. .. toctree:: diff --git a/docs/WhatIsPoC/SupportedToolChains.rst b/docs/WhatIsPoC/SupportedToolChains.rst index 1798587e..7d91c8c7 100644 --- a/docs/WhatIsPoC/SupportedToolChains.rst +++ b/docs/WhatIsPoC/SupportedToolChains.rst @@ -1,6 +1,7 @@ - .. include:: +.. _INTRO:ToolChains: + Which Tool Chains are supported? ################################ @@ -12,6 +13,9 @@ The PoC-Library and its Python-based infrastructure currently supports the follo Tested with Quartus-II |geq| 13.0. |br| Tested with Quartus Prime |geq| 15.1. + * **Intel Quartus** |br| + Tested with Quartus Prime |geq| 16.1. + * **Lattice Diamond** |br| Tested with Diamond |geq| 3.6. @@ -29,22 +33,26 @@ The PoC-Library and its Python-based infrastructure currently supports the follo * Simulation Tool Chains: * **Aldec Active-HDL** |br| - Tested with Active-HDL Student-Edition 10.3 |br| - Tested with Active-HDL Lattice Edition 10.2 + Tested with Active-HDL (or Student-Edition) |geq| 10.3 |br| + Tested with Active-HDL Lattice Edition |geq| 10.2 * **Cocotb with Mentor QuestaSim backend** |br| Tested with Mentor QuestaSim 10.4d + * **Mentor Graphics ModelSim** |br| + Tested with ModelSim PE (or Student Edition) |geq| 10.5c |br| + Tested with ModelSim SE |geq| 10.5c |br| + Tested with ModelSim Altera Edition 10.3d (or Starter Edition) + * **Mentor Graphics QuestaSim/ModelSim** |br| - Tested with ModelSim Altera Edition 10.3d and ModelSim Altera Starter Edition 10.3d |br| - Tested with Mentor QuestaSim 10.4d + Tested with Mentor QuestaSim |geq| 10.4d * **Xilinx ISE Simulator** |br| Tested with ISE Simulator (iSim) 14.7. |br| The Python infrastructure supports isim, but PoC's simulation helper packages and testbenches rely on VHDL-2008 features, which are not supported by isim. * **Xilinx Vivado Simulator** |br| - Tested with Vivado Simulator (xsim) |geq| 2016.1. |br| + Tested with Vivado Simulator (xsim) |geq| 2016.3. |br| The Python infrastructure supports xsim, but PoC's simulation helper packages and testbenches rely on VHDL-2008 features, which are not fully supported by xsim, yet. * **GHDL** + **GTKWave** |br| diff --git a/py/ToolChains/Lattice/Synopsys.py b/docs/_extensions/DocumentMember.py similarity index 58% rename from py/ToolChains/Lattice/Synopsys.py rename to docs/_extensions/DocumentMember.py index d70c980f..6070158b 100644 --- a/py/ToolChains/Lattice/Synopsys.py +++ b/docs/_extensions/DocumentMember.py @@ -5,18 +5,15 @@ # ============================================================================== # Authors: Patrick Lehmann # -# Python Class: Lattice Synopsys specific classes +# Python Module: # # Description: # ------------------------------------ -# TODO: -# - -# - +# - TODO # # License: # ============================================================================== -# Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Copyright 2007-2016 Patrick Lehmann - Dresden, Germany # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -31,24 +28,28 @@ # limitations under the License. # ============================================================================== # -# entry point -if __name__ != "__main__": - # place library initialization code here - pass -else: - from lib.Functions import Exit - Exit.printThisIsNoExecutableFile("PoC Library - Python Module ToolChains.Lattice.Synopsys") +from lib.SphinxExtensions import DocumentMemberAttribute -# from collections import OrderedDict -# from pathlib import Path +def skip_member_handler(app, what, name, obj, skip, options): + # try: + # print("skip_member_handler: ", obj) + # except: + # print("skip_member_handler: ERROR") -from Base.Configuration import Configuration as BaseConfiguration -from Base.ToolChain import ToolChainException + try: + attributes = DocumentMemberAttribute.GetAttributes(obj) + if (len(attributes) > 0): + # print("*#"*20) + # try: + # print("skip_member_handler: ", obj) + # except: + # print("skip_member_handler: ERROR") -class SynopsysException(ToolChainException): - pass + return not attributes[0].value + except: + pass + return None -class Configuration(BaseConfiguration): - def __init__(self, host): - super().__init__(host) +def setup(app): + app.connect('autodoc-skip-member', skip_member_handler) diff --git a/docs/_extensions/autoprogram.py b/docs/_extensions/autoprogram.py new file mode 100644 index 00000000..cfb98409 --- /dev/null +++ b/docs/_extensions/autoprogram.py @@ -0,0 +1,407 @@ +""" + sphinxcontrib.autoprogram + ~~~~~~~~~~~~~~~~~~~~~~~~~ + + Documenting CLI programs. + + :copyright: Copyright 2014 by Hong Minhee + :license: BSD, see LICENSE for details. + +""" +# pylint: disable=protected-access,missing-docstring +import argparse +import collections +try: + import builtins +except ImportError: + import __builtin__ as builtins +import functools +import os +import re +import six +import textwrap +import unittest + +from docutils import nodes +from docutils.parsers.rst.directives import unchanged +from docutils.statemachine import ViewList +from sphinx.util.compat import Directive +from sphinx.util.nodes import nested_parse_with_titles +from sphinx.domains import std + +__all__ = ('BOOLEAN_OPTIONS', 'AutoprogramDirective', 'ScannerTestCase', + 'import_object', 'scan_programs', 'setup', 'suite') + + +def get_subparser_action(parser): + neg1_action = parser._actions[-1] + + if isinstance(neg1_action, argparse._SubParsersAction): + return neg1_action + + for a in parser._actions: + if isinstance(a, argparse._SubParsersAction): + return a + + +def scan_programs(parser, command=[], maxdepth=0, depth=0): + if maxdepth and depth >= maxdepth: + return + + options = [] + for arg in parser._actions: + if not (arg.option_strings or + isinstance(arg, argparse._SubParsersAction)): + name = (arg.metavar or arg.dest).lower() + desc = (arg.help or '') % {'default': arg.default} + options.append(([name], desc)) + + for arg in parser._actions: + if arg.option_strings and arg.help is not argparse.SUPPRESS: + if isinstance(arg, (argparse._StoreAction, + argparse._AppendAction)): + if arg.choices is None: + metavar = arg.metavar or arg.dest + + if isinstance(metavar, tuple): + names = [ + '{0} <{1}>'.format( + option_string, '> <'.join(metavar).lower() + ) + for option_string in arg.option_strings + ] + else: + names = [ + '{0} <{1}>'.format(option_string, metavar.lower()) + for option_string in arg.option_strings + ] + else: + choices = '{0}'.format(','.join(arg.choices)) + names = ['{0} {{{1}}}'.format(option_string, choices) + for option_string in arg.option_strings] + else: + names = list(arg.option_strings) + desc = (arg.help or '') % {'default': arg.default} + options.append((names, desc)) + + yield command, options, parser + + if parser._subparsers: + choices = () + + subp_action = get_subparser_action(parser) + + if subp_action: + choices = subp_action.choices.items() + + if not (hasattr(collections, 'OrderedDict') and + isinstance(choices, collections.OrderedDict)): + choices = sorted(choices, key=lambda pair: pair[0]) + + for cmd, sub in choices: + if isinstance(sub, argparse.ArgumentParser): + for program in scan_programs( + sub, command + [cmd], maxdepth, depth + 1 + ): + yield program + + +def import_object(import_name): + module_name, expr = import_name.split(':', 1) + try: + mod = __import__(module_name) + except ImportError: + # This happens if the file is a script with no .py extension. Here we + # trick autoprogram to load a module in memory with the contents of + # the script, if there is a script named module_name. Otherwise, raise + # an ImportError as it did before. + import glob + import sys + import os + import imp + + for p in sys.path: + f = glob.glob(os.path.join(p, module_name)) + if len(f) > 0: + with open(f[0]) as fobj: + codestring = fobj.read() + foo = imp.new_module("foo") + six.exec_(codestring, foo.__dict__) + + sys.modules["foo"] = foo + mod = __import__("foo") + break + else: + raise ImportError("No module named {}".format(module_name)) + + reduce_ = getattr(functools, 'reduce', None) or reduce + mod = reduce_(getattr, module_name.split('.')[1:], mod) + globals_ = builtins + if not isinstance(globals_, dict): + globals_ = globals_.__dict__ + return eval(expr, globals_, mod.__dict__) + + +class AutoprogramDirective(Directive): + + has_content = False + required_arguments = 1 + option_spec = { + 'prog': unchanged, + 'maxdepth': unchanged, + 'start_command': unchanged, + 'strip_usage': unchanged, + 'no_usage_codeblock': unchanged, + 'label': unchanged, + } + + def make_rst(self): + import_name, = self.arguments + parser = import_object(import_name or '__undefined__') + prog = self.options.get('prog') + if prog: + original_prog = parser.prog + parser.prog = prog + start_command = self.options.get('start_command', '').split(' ') + strip_usage = 'strip_usage' in self.options + usage_codeblock = 'no_usage_codeblock' not in self.options + + if start_command[0] == '': + start_command.pop(0) + + if start_command: + def get_start_cmd_parser(p): + looking_for = start_command.pop(0) + action = get_subparser_action(p) + + if not action: + raise ValueError('No actions for command ' + looking_for) + + subp = action.choices[looking_for] + + if start_command: + return get_start_cmd_parser(subp) + + return subp + + parser = get_start_cmd_parser(parser) + if prog and parser.prog.startswith(original_prog): + parser.prog = parser.prog.replace(original_prog, prog, 1) + + for commands, options, cmd_parser in scan_programs( + parser, maxdepth=int(self.options.get('maxdepth', 0)) + ): + if prog and cmd_parser.prog.startswith(original_prog): + cmd_parser.prog = cmd_parser.prog.replace( + original_prog, prog, 1) + title = cmd_parser.prog.rstrip() + usage = cmd_parser.format_usage() + + if strip_usage: + to_strip = title.rsplit(' ', 1)[0] + len_to_strip = len(to_strip) - 4 + usage_lines = usage.splitlines() + + usage = os.linesep.join([ + usage_lines[0].replace(to_strip, '...'), + ] + [ + l[len_to_strip:] for l in usage_lines[1:] + ]) + + yield '' + yield '.. program:: ' + title + + if 'label' in self.options: + yield '' + yield '.. _%s:' % (self.options.get('label') + title).replace(" ", "-") + + yield '' + yield title + yield ('!' if commands else '?') * len(title) + yield '' + for line in (cmd_parser.description or '').splitlines(): + yield line + yield '' + + if usage_codeblock: + yield '.. code-block:: console' + yield '' + yield textwrap.indent(usage, ' ') + else: + yield usage + + yield '' + + for option_strings, help_ in options: + yield '.. option:: {0}'.format(', '.join(option_strings)) + yield '' + yield ' ' + help_.replace('\n', ' \n') + yield '' + yield '' + for line in (cmd_parser.epilog or '').splitlines(): + yield line or '' + + yield '' + yield '-' * 20 + yield '' + + def run(self): + node = nodes.section() + node.document = self.state.document + result = ViewList() + for line in self.make_rst(): + result.append(line, '') + nested_parse_with_titles(self.state, result, node) + return node.children + + +def patch_option_role_to_allow_argument_form(): + """Before Sphinx 1.2.2, :rst:dir:`.. option::` directive hadn't + allowed to not start with a dash or slash, so it hadn't been possible + to represent positional arguments (not options). + + https://bitbucket.org/birkenfeld/sphinx/issue/1357/ + + It monkeypatches the :rst:dir:`.. option::` directive's behavior. + + """ + std.option_desc_re = re.compile(r'((?:/|-|--)?[-_a-zA-Z0-9]+)(\s*.*)') + + +def setup(app): + app.add_directive('autoprogram', AutoprogramDirective) + patch_option_role_to_allow_argument_form() + + +class ScannerTestCase(unittest.TestCase): + + def test_simple_parser(self): + parser = argparse.ArgumentParser(description='Process some integers.') + parser.add_argument('integers', metavar='N', type=int, nargs='*', + help='an integer for the accumulator') + parser.add_argument('-i', '--identity', type=int, default=0, + help='the default result for no arguments ' + '(default: 0)') + parser.add_argument('--sum', dest='accumulate', action='store_const', + const=sum, default=max, + help='sum the integers (default: find the max)') + parser.add_argument('--key-value', metavar=('KEY', 'VALUE'), nargs=2) + parser.add_argument('--max', help=argparse.SUPPRESS) # must be opt-out + + programs = scan_programs(parser) + programs = list(programs) + self.assertEqual(1, len(programs)) + parser_info, = programs + program, options, cmd_parser = parser_info + self.assertEqual([], program) + self.assertEqual('Process some integers.', cmd_parser.description) + self.assertEqual(5, len(options)) + self.assertEqual( + (['n'], 'an integer for the accumulator'), + options[0] + ) + self.assertEqual( + (['-h', '--help'], 'show this help message and exit'), + options[1] + ) + self.assertEqual( + (['-i ', '--identity '], + 'the default result for no arguments (default: 0)'), + options[2] + ) + self.assertEqual( + (['--sum'], 'sum the integers (default: find the max)'), + options[3] + ) + self.assertEqual( + (['--key-value ', ], ''), + options[4] + ) + + def test_subcommands(self): + parser = argparse.ArgumentParser(description='Process some integers.') + subparsers = parser.add_subparsers() + max_parser = subparsers.add_parser('max', description='Find the max.') + max_parser.set_defaults(accumulate=max) + max_parser.add_argument('integers', metavar='N', type=int, nargs='+', + help='An integer for the accumulator.') + sum_parser = subparsers.add_parser('sum', + description='Sum the integers.') + sum_parser.set_defaults(accumulate=sum) + sum_parser.add_argument('integers', metavar='N', type=int, nargs='+', + help='An integer for the accumulator.') + programs = scan_programs(parser) + programs = list(programs) + self.assertEqual(3, len(programs)) + # main + program, options, cmd_parser = programs[0] + self.assertEqual([], program) + self.assertEqual('Process some integers.', cmd_parser.description) + self.assertEqual(1, len(options)) + self.assertEqual( + (['-h', '--help'], + 'show this help message and exit'), + options[0] + ) + # max + program, options, cmd_parser = programs[1] + self.assertEqual(['max'], program) + self.assertEqual('Find the max.', cmd_parser.description) + self.assertEqual(2, len(options)) + self.assertEqual((['n'], 'An integer for the accumulator.'), + options[0]) + self.assertEqual( + (['-h', '--help'], + 'show this help message and exit'), + options[1] + ) + # sum + program, options, cmd_parser = programs[2] + self.assertEqual(['sum'], program) + self.assertEqual('Sum the integers.', cmd_parser.description) + self.assertEqual(2, len(options)) + self.assertEqual((['n'], 'An integer for the accumulator.'), + options[0]) + + def test_choices(self): + parser = argparse.ArgumentParser() + parser.add_argument("--awesomeness", choices=["meh", "awesome"]) + program, options, cmd_parser = list(scan_programs(parser))[0] + log_option = options[1] + self.assertEqual((["--awesomeness {meh,awesome}"], ''), log_option) + + def test_parse_epilog(self): + parser = argparse.ArgumentParser( + description='Process some integers.', + epilog='The integers will be processed.' + ) + programs = scan_programs(parser) + programs = list(programs) + self.assertEqual(1, len(programs)) + parser_data, = programs + program, options, cmd_parser = parser_data + self.assertEqual('The integers will be processed.', cmd_parser.epilog) + + +class UtilTestCase(unittest.TestCase): + + def test_import_object(self): + cls = import_object('sphinxcontrib.autoprogram:UtilTestCase') + self.assertTrue(cls is UtilTestCase) + instance = import_object( + 'sphinxcontrib.autoprogram:UtilTestCase("test_import_object")' + ) + self.assertIsInstance(instance, UtilTestCase) + + if not hasattr(unittest.TestCase, 'assertIsInstance'): + def assertIsInstance(self, instance, cls): + self.assertTrue(isinstance(instance, cls), + '{0!r} is not an instance of {1.__module__}.' + '{1.__name__}'.format(instance, cls)) + + +suite = unittest.TestSuite() +suite.addTests( + unittest.defaultTestLoader.loadTestsFromTestCase(ScannerTestCase) +) +suite.addTests(unittest.defaultTestLoader.loadTestsFromTestCase(UtilTestCase)) diff --git a/docs/_static/css/custom.css b/docs/_static/css/custom.css new file mode 100644 index 00000000..59b5412a --- /dev/null +++ b/docs/_static/css/custom.css @@ -0,0 +1,3 @@ +.wy-table-responsive table td { + white-space: normal; +} diff --git a/docs/_static/css/railroad-diagrams.css b/docs/_static/css/railroad-diagrams.css new file mode 100644 index 00000000..24db32fd --- /dev/null +++ b/docs/_static/css/railroad-diagrams.css @@ -0,0 +1,41 @@ +svg.railroad-diagram { + background-color: hsl(30,20%,95%); +} +svg.railroad-diagram path { + stroke-width: 3; + stroke: black; + fill: rgba(0,0,0,0); +} +svg.railroad-diagram text { + font: bold 14px monospace; + text-anchor: middle; +} +svg.railroad-diagram text.diagram-text { + font-size: 12px; +} +svg.railroad-diagram text.diagram-arrow { + font-size: 16px; +} +svg.railroad-diagram text.label { + text-anchor: start; +} +svg.railroad-diagram text.comment { + font: italic 12px monospace; +} +svg.railroad-diagram g.non-terminal text { + /*font-style: italic;*/ +} +svg.railroad-diagram rect { + stroke-width: 3; + stroke: black; + fill: hsl(120,100%,90%); +} +svg.railroad-diagram path.diagram-text { + stroke-width: 3; + stroke: black; + fill: white; + cursor: help; +} +svg.railroad-diagram g.diagram-text:hover path.diagram-text { + fill: #eee; +} diff --git a/docs/_static/icons/ZIP.png b/docs/_static/icons/ZIP.png new file mode 100644 index 00000000..9d2a8589 Binary files /dev/null and b/docs/_static/icons/ZIP.png differ diff --git a/docs/_static/io/iic_Controller_Usage.graphml b/docs/_static/io/iic_Controller_Usage.graphml new file mode 100644 index 00000000..63bf666c --- /dev/null +++ b/docs/_static/io/iic_Controller_Usage.graphml @@ -0,0 +1,111 @@ + + + + + + + + + + + + + + + + + + + + + + + + iic_Controller + + + + + + + + + + + + iic_BusController + + + + + + + + + + + + pb_IIC_Adapter + + + + + + + + + + + + iic_Switch_PCA95a8A + + + + + + + + + + + + wb_IIC_Adapter + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/docs/_static/io/iic_Controller_Usage.png b/docs/_static/io/iic_Controller_Usage.png new file mode 100644 index 00000000..37b03b81 Binary files /dev/null and b/docs/_static/io/iic_Controller_Usage.png differ diff --git a/docs/_static/javascript/railroad-diagrams.js b/docs/_static/javascript/railroad-diagrams.js new file mode 100644 index 00000000..f45f99e8 --- /dev/null +++ b/docs/_static/javascript/railroad-diagrams.js @@ -0,0 +1,893 @@ +"use strict"; +/* +Railroad Diagrams +by Tab Atkins Jr. (and others) +http://xanthir.com +http://twitter.com/tabatkins +http://github.com/tabatkins/railroad-diagrams + +This document and all associated files in the github project are licensed under CC0: http://creativecommons.org/publicdomain/zero/1.0/ +This means you can reuse, remix, or otherwise appropriate this project for your own use WITHOUT RESTRICTION. +(The actual legal meaning can be found at the above link.) +Don't ask me for permission to use any part of this project, JUST USE IT. +I would appreciate attribution, but that is not required by the license. +*/ + +/* +This file uses a module pattern to avoid leaking names into the global scope. +The only accidental leakage is the name "temp". +The exported names can be found at the bottom of this file; +simply change the names in the array of strings to change what they are called in your application. + +As well, several configuration constants are passed into the module function at the bottom of this file. +At runtime, these constants can be found on the Diagram class. +*/ + +(function(options) { + function subclassOf(baseClass, superClass) { + baseClass.prototype = Object.create(superClass.prototype); + baseClass.prototype.$super = superClass.prototype; + } + + function unnull(/* children */) { + return [].slice.call(arguments).reduce(function(sofar, x) { return sofar !== undefined ? sofar : x; }); + } + + function determineGaps(outer, inner) { + var diff = outer - inner; + switch(Diagram.INTERNAL_ALIGNMENT) { + case 'left': return [0, diff]; break; + case 'right': return [diff, 0]; break; + case 'center': + default: return [diff/2, diff/2]; break; + } + } + + function wrapString(value) { + return ((typeof value) == 'string') ? new Terminal(value) : value; + } + + function sum(iter, func) { + if(!func) func = function(x) { return x; }; + return iter.map(func).reduce(function(a,b){return a+b}, 0); + } + + function max(iter, func) { + if(!func) func = function(x) { return x; }; + return Math.max.apply(null, iter.map(func)); + } + + function SVG(name, attrs, text) { + attrs = attrs || {}; + text = text || ''; + var el = document.createElementNS("http://www.w3.org/2000/svg",name); + for(var attr in attrs) { + if(attr === 'xlink:href') + el.setAttributeNS("http://www.w3.org/1999/xlink", 'href', attrs[attr]); + else + el.setAttribute(attr, attrs[attr]); + } + el.textContent = text; + return el; + } + + function FakeSVG(tagName, attrs, text){ + if(!(this instanceof FakeSVG)) return new FakeSVG(tagName, attrs, text); + if(text) this.children = text; + else this.children = []; + this.tagName = tagName; + this.attrs = unnull(attrs, {}); + return this; + }; + FakeSVG.prototype.format = function(x, y, width) { + // Virtual + }; + FakeSVG.prototype.addTo = function(parent) { + if(parent instanceof FakeSVG) { + parent.children.push(this); + return this; + } else { + var svg = this.toSVG(); + parent.appendChild(svg); + return svg; + } + }; + FakeSVG.prototype.escapeString = function(string) { + // Escape markdown and HTML special characters + return string.replace(/[*_\`\[\]<&]/g, function(charString) { + return '&#' + charString.charCodeAt(0) + ';'; + }); + }; + FakeSVG.prototype.toSVG = function() { + var el = SVG(this.tagName, this.attrs); + if(typeof this.children == 'string') { + el.textContent = this.children; + } else { + this.children.forEach(function(e) { + el.appendChild(e.toSVG()); + }); + } + return el; + }; + FakeSVG.prototype.toString = function() { + var str = '<' + this.tagName; + var group = this.tagName == "g" || this.tagName == "svg"; + for(var attr in this.attrs) { + str += ' ' + attr + '="' + (this.attrs[attr]+'').replace(/&/g, '&').replace(/"/g, '"') + '"'; + } + str += '>'; + if(group) str += "\n"; + if(typeof this.children == 'string') { + str += FakeSVG.prototype.escapeString(this.children); + } else { + this.children.forEach(function(e) { + str += e; + }); + } + str += '\n'; + return str; + } + + function Path(x,y) { + if(!(this instanceof Path)) return new Path(x,y); + FakeSVG.call(this, 'path'); + this.attrs.d = "M"+x+' '+y; + } + subclassOf(Path, FakeSVG); + Path.prototype.m = function(x,y) { + this.attrs.d += 'm'+x+' '+y; + return this; + } + Path.prototype.h = function(val) { + this.attrs.d += 'h'+val; + return this; + } + Path.prototype.right = Path.prototype.h; + Path.prototype.left = function(val) { return this.h(-val); } + Path.prototype.v = function(val) { + this.attrs.d += 'v'+val; + return this; + } + Path.prototype.down = Path.prototype.v; + Path.prototype.up = function(val) { return this.v(-val); } + Path.prototype.arc = function(sweep){ + var x = Diagram.ARC_RADIUS; + var y = Diagram.ARC_RADIUS; + if(sweep[0] == 'e' || sweep[1] == 'w') { + x *= -1; + } + if(sweep[0] == 's' || sweep[1] == 'n') { + y *= -1; + } + if(sweep == 'ne' || sweep == 'es' || sweep == 'sw' || sweep == 'wn') { + var cw = 1; + } else { + var cw = 0; + } + this.attrs.d += "a"+Diagram.ARC_RADIUS+" "+Diagram.ARC_RADIUS+" 0 0 "+cw+' '+x+' '+y; + return this; + } + Path.prototype.format = function() { + // All paths in this library start/end horizontally. + // The extra .5 ensures a minor overlap, so there's no seams in bad rasterizers. + this.attrs.d += 'h.5'; + return this; + } + + function Diagram(items) { + if(!(this instanceof Diagram)) return new Diagram([].slice.call(arguments)); + FakeSVG.call(this, 'svg', {class: Diagram.DIAGRAM_CLASS}); + this.items = items.map(wrapString); + this.items.unshift(new Start); + this.items.push(new End); + this.up = this.down = this.height = this.width = 0; + for(var i = 0; i < this.items.length; i++) { + var item = this.items[i]; + this.width += item.width + (item.needsSpace?20:0); + this.up = Math.max(this.up, item.up - this.height); + this.height += item.height; + this.down = Math.max(this.down - item.height, item.down); + } + this.formatted = false; + } + subclassOf(Diagram, FakeSVG); + for(var option in options) { + Diagram[option] = options[option]; + } + Diagram.prototype.format = function(paddingt, paddingr, paddingb, paddingl) { + paddingt = unnull(paddingt, 20); + paddingr = unnull(paddingr, paddingt, 20); + paddingb = unnull(paddingb, paddingt, 20); + paddingl = unnull(paddingl, paddingr, 20); + var x = paddingl; + var y = paddingt; + y += this.up; + var g = FakeSVG('g', Diagram.STROKE_ODD_PIXEL_LENGTH ? {transform:'translate(.5 .5)'} : {}); + for(var i = 0; i < this.items.length; i++) { + var item = this.items[i]; + if(item.needsSpace) { + Path(x,y).h(10).addTo(g); + x += 10; + } + item.format(x, y, item.width).addTo(g); + x += item.width; + y += item.height; + if(item.needsSpace) { + Path(x,y).h(10).addTo(g); + x += 10; + } + } + this.attrs.width = this.width + paddingl + paddingr; + this.attrs.height = this.up + this.height + this.down + paddingt + paddingb; + this.attrs.viewBox = "0 0 " + this.attrs.width + " " + this.attrs.height; + g.addTo(this); + this.formatted = true; + return this; + } + Diagram.prototype.addTo = function(parent) { + if(!parent) { + var scriptTag = document.getElementsByTagName('script'); + scriptTag = scriptTag[scriptTag.length - 1]; + parent = scriptTag.parentNode; + } + return this.$super.addTo.call(this, parent); + } + Diagram.prototype.toSVG = function() { + if (!this.formatted) { + this.format(); + } + return this.$super.toSVG.call(this); + } + Diagram.prototype.toString = function() { + if (!this.formatted) { + this.format(); + } + return this.$super.toString.call(this); + } + + function ComplexDiagram() { + var diagram = new Diagram([].slice.call(arguments)); + var items = diagram.items; + items.shift(); + items.pop(); + items.unshift(new Start("complex")); + items.push(new End("complex")); + diagram.items = items; + return diagram; + } + + function Sequence(items) { + if(!(this instanceof Sequence)) return new Sequence([].slice.call(arguments)); + FakeSVG.call(this, 'g'); + this.items = items.map(wrapString); + var numberOfItems = this.items.length; + this.needsSpace = true; + this.up = this.down = this.height = this.width = 0; + for(var i = 0; i < this.items.length; i++) { + var item = this.items[i]; + this.width += item.width + (item.needsSpace?20:0); + this.up = Math.max(this.up, item.up - this.height); + this.height += item.height; + this.down = Math.max(this.down - item.height, item.down); + } + if(this.items[0].needsSpace) this.width -= 10; + if(this.items[this.items.length-1].needsSpace) this.width -= 10; + if(Diagram.DEBUG) { + this.attrs['data-updown'] = this.up + " " + this.height + " " + this.down + this.attrs['data-type'] = "sequence" + } + } + subclassOf(Sequence, FakeSVG); + Sequence.prototype.format = function(x,y,width) { + // Hook up the two sides if this is narrower than its stated width. + var gaps = determineGaps(width, this.width); + Path(x,y).h(gaps[0]).addTo(this); + Path(x+gaps[0]+this.width,y+this.height).h(gaps[1]).addTo(this); + x += gaps[0]; + + for(var i = 0; i < this.items.length; i++) { + var item = this.items[i]; + if(item.needsSpace && i > 0) { + Path(x,y).h(10).addTo(this); + x += 10; + } + item.format(x, y, item.width).addTo(this); + x += item.width; + y += item.height; + if(item.needsSpace && i < this.items.length-1) { + Path(x,y).h(10).addTo(this); + x += 10; + } + } + return this; + } + + function Stack(items) { + if(!(this instanceof Stack)) return new Stack([].slice.call(arguments)); + FakeSVG.call(this, 'g'); + if( items.length === 0 ) { + throw new RangeError("Stack() must have at least one child."); + } + this.items = items.map(wrapString); + this.width = Math.max.apply(null, this.items.map(function(e) { return e.width + (e.needsSpace?20:0); })); + if(this.items[0].needsSpace) this.width -= 10; + if(this.items[this.items.length-1].needsSpace) this.width -= 10; + if(this.items.length > 1){ + this.width += Diagram.ARC_RADIUS*2; + } + this.needsSpace = true; + this.up = this.items[0].up; + this.down = this.items[this.items.length-1].down; + + this.height = 0; + for(var i = 0; i < this.items.length; i++) { + this.height += this.items[i].height; + if(i !== this.items.length-1) { + this.height += Math.max(this.items[i].down + Diagram.VERTICAL_SEPARATION, Diagram.ARC_RADIUS*2) + Math.max(this.items[i+1].up + Diagram.VERTICAL_SEPARATION, Diagram.ARC_RADIUS*2); + } + } + if(Diagram.DEBUG) { + this.attrs['data-updown'] = this.up + " " + this.height + " " + this.down + this.attrs['data-type'] = "stack" + } + } + subclassOf(Stack, FakeSVG); + Stack.prototype.format = function(x,y,width) { + var gaps = determineGaps(width, this.width); + Path(x,y).h(gaps[0]).addTo(this); + x += gaps[0]; + var xInitial = x; + if(this.items.length > 1) { + Path(x, y).h(Diagram.ARC_RADIUS).addTo(this); + x += Diagram.ARC_RADIUS; + } + + for(var i = 0; i < this.items.length; i++) { + var item = this.items[i]; + var innerWidth = this.width - (this.items.length>1 ? Diagram.ARC_RADIUS*2 : 0); + item.format(x, y, innerWidth).addTo(this); + x += innerWidth; + y += item.height; + + if(i !== this.items.length-1) { + Path(x, y) + .arc('ne').down(Math.max(0, item.down + Diagram.VERTICAL_SEPARATION - Diagram.ARC_RADIUS*2)) + .arc('es').left(innerWidth) + .arc('nw').down(Math.max(0, this.items[i+1].up + Diagram.VERTICAL_SEPARATION - Diagram.ARC_RADIUS*2)) + .arc('ws').addTo(this); + y += Math.max(item.down + Diagram.VERTICAL_SEPARATION, Diagram.ARC_RADIUS*2) + Math.max(this.items[i+1].up + Diagram.VERTICAL_SEPARATION, Diagram.ARC_RADIUS*2); + //y += Math.max(Diagram.ARC_RADIUS*4, item.down + Diagram.VERTICAL_SEPARATION*2 + this.items[i+1].up) + x = xInitial+Diagram.ARC_RADIUS; + } + + } + + if(this.items.length > 1) { + Path(x,y).h(Diagram.ARC_RADIUS).addTo(this); + x += Diagram.ARC_RADIUS; + } + Path(x,y).h(gaps[1]).addTo(this); + + return this; + } + + function OptionalSequence(items) { + if(!(this instanceof OptionalSequence)) return new OptionalSequence([].slice.call(arguments)); + FakeSVG.call(this, 'g'); + if( items.length === 0 ) { + throw new RangeError("OptionalSequence() must have at least one child."); + } + this.items = items.map(wrapString); + this.needsSpace = false; + this.width = Diagram.ARC_RADIUS *4; + this.up = 0; + this.height = sum(this.items, function(x){return x.height}); + this.down = this.items[0].down; + var heightSoFar = 0; + for(var i = 0; i < this.items.length; i++) { + var item = this.items[i]; + this.up = Math.max(this.up, Math.max(Diagram.ARC_RADIUS*2, item.up + Diagram.VERTICAL_SEPARATION) - heightSoFar); + heightSoFar += item.height; + if(i > 0) { + this.down = Math.max(this.height + this.down, heightSoFar + Math.max(Diagram.ARC_RADIUS*2, item.down + Diagram.VERTICAL_SEPARATION)) - this.height; + } + this.width += Math.max(Diagram.ARC_RADIUS*2, item.width + (item.needsSpace?20:0)); + if(i == 0) this.width += Diagram.ARC_RADIUS; + else if(i == 1) this.width += Diagram.ARC_RADIUS*2; + else if(i < this.items.length - 1) this.width += Diagram.ARC_RADIUS*3; + } + if(Diagram.DEBUG) { + this.attrs['data-updown'] = this.up + " " + this.height + " " + this.down + this.attrs['data-type'] = "optseq" + } + } + subclassOf(OptionalSequence, FakeSVG); + OptionalSequence.prototype.format = function(x, y, width) { + var gaps = determineGaps(width, this.width) + Path(x, y).h(gaps[0]).addTo(this) + Path(x + gaps[0] + this.width, y + this.height).h(gaps[1]).addTo(this) + x += gaps[0] + var upperLineY = y - this.up; + var last = this.items.length - 1; + Path(x,y) + .arc('se') + .up(Math.max(0, this.up - Diagram.ARC_RADIUS*2)) + .arc('wn') + .right(this.width - Diagram.ARC_RADIUS*5 - this.items[last].width - (this.items[last].needsSpace?20:0)) + .arc('ne') + .down(Math.max(0, this.up + this.height - this.items[last].height - Diagram.ARC_RADIUS*2)) + .arc('ws') + .addTo(this); + for(var i = 0; i < this.items.length; i++) { + var item = this.items[i]; + var itemWidth = item.width + (item.needsSpace?20:0); + if(i == 0) var spaceSize = Diagram.ARC_RADIUS; + else if(i == 1) var spaceSize = Diagram.ARC_RADIUS*2; + else var spaceSize = Diagram.ARC_RADIUS*3; + if(i > 0) { + if(i < last) { + Path(x + spaceSize - Diagram.ARC_RADIUS*2, upperLineY) + .arc('ne') + .down(Math.abs(upperLineY - y) - Diagram.ARC_RADIUS*2) + .arc('ws') + .addTo(this); + } + Path(x + spaceSize - Diagram.ARC_RADIUS*2, y) + .arc('ne') + .down(item.height + Math.max(0, item.down + Diagram.VERTICAL_SEPARATION - Diagram.ARC_RADIUS*2)) + .arc('ws') + .right(itemWidth - Diagram.ARC_RADIUS) + .arc('se') + .up(Math.max(0, item.down + Diagram.VERTICAL_SEPARATION - Diagram.ARC_RADIUS*2)) + .arc('wn') + .addTo(this); + } + Path(x, y).right(spaceSize).addTo(this); + x += spaceSize; + item.format(x, y, itemWidth).addTo(this); + x += itemWidth; + y += item.height; + } + Path(x, y).right(Diagram.ARC_RADIUS*2).addTo(this); + return this; + }; + + function Choice(normal, items) { + if(!(this instanceof Choice)) return new Choice(normal, [].slice.call(arguments,1)); + FakeSVG.call(this, 'g'); + if( typeof normal !== "number" || normal !== Math.floor(normal) ) { + throw new TypeError("The first argument of Choice() must be an integer."); + } else if(normal < 0 || normal >= items.length) { + throw new RangeError("The first argument of Choice() must be an index for one of the items."); + } else { + this.normal = normal; + } + var first = 0; + var last = items.length - 1; + this.items = items.map(wrapString); + this.width = Math.max.apply(null, this.items.map(function(el){return el.width})) + Diagram.ARC_RADIUS*4; + this.height = this.items[normal].height; + this.up = this.items[first].up; + for(var i = first; i < normal; i++) { + if(i == normal-1) var arcs = Diagram.ARC_RADIUS*2; + else var arcs = Diagram.ARC_RADIUS; + this.up += Math.max(arcs, this.items[i].height + this.items[i].down + Diagram.VERTICAL_SEPARATION + this.items[i+1].up); + } + this.down = this.items[last].down; + for(var i = normal+1; i <= last; i++) { + if(i == normal+1) var arcs = Diagram.ARC_RADIUS*2; + else var arcs = Diagram.ARC_RADIUS; + this.down += Math.max(arcs, this.items[i-1].height + this.items[i-1].down + Diagram.VERTICAL_SEPARATION + this.items[i].up); + } + this.down -= this.items[normal].height; // already counted in Choice.height + if(Diagram.DEBUG) { + this.attrs['data-updown'] = this.up + " " + this.height + " " + this.down + this.attrs['data-type'] = "choice" + } + } + subclassOf(Choice, FakeSVG); + Choice.prototype.format = function(x,y,width) { + // Hook up the two sides if this is narrower than its stated width. + var gaps = determineGaps(width, this.width); + Path(x,y).h(gaps[0]).addTo(this); + Path(x+gaps[0]+this.width,y+this.height).h(gaps[1]).addTo(this); + x += gaps[0]; + + var last = this.items.length -1; + var innerWidth = this.width - Diagram.ARC_RADIUS*4; + + // Do the elements that curve above + for(var i = this.normal - 1; i >= 0; i--) { + var item = this.items[i]; + if( i == this.normal - 1 ) { + var distanceFromY = Math.max(Diagram.ARC_RADIUS*2, this.items[this.normal].up + Diagram.VERTICAL_SEPARATION + item.down + item.height); + } + Path(x,y) + .arc('se') + .up(distanceFromY - Diagram.ARC_RADIUS*2) + .arc('wn').addTo(this); + item.format(x+Diagram.ARC_RADIUS*2,y - distanceFromY,innerWidth).addTo(this); + Path(x+Diagram.ARC_RADIUS*2+innerWidth, y-distanceFromY+item.height) + .arc('ne') + .down(distanceFromY - item.height + this.height - Diagram.ARC_RADIUS*2) + .arc('ws').addTo(this); + distanceFromY += Math.max(Diagram.ARC_RADIUS, item.up + Diagram.VERTICAL_SEPARATION + (i == 0 ? 0 : this.items[i-1].down+this.items[i-1].height)); + } + + // Do the straight-line path. + Path(x,y).right(Diagram.ARC_RADIUS*2).addTo(this); + this.items[this.normal].format(x+Diagram.ARC_RADIUS*2, y, innerWidth).addTo(this); + Path(x+Diagram.ARC_RADIUS*2+innerWidth, y+this.height).right(Diagram.ARC_RADIUS*2).addTo(this); + + // Do the elements that curve below + for(var i = this.normal+1; i <= last; i++) { + var item = this.items[i]; + if( i == this.normal + 1 ) { + var distanceFromY = Math.max(Diagram.ARC_RADIUS*2, this.height + this.items[this.normal].down + Diagram.VERTICAL_SEPARATION + item.up); + } + Path(x,y) + .arc('ne') + .down(distanceFromY - Diagram.ARC_RADIUS*2) + .arc('ws').addTo(this); + item.format(x+Diagram.ARC_RADIUS*2, y+distanceFromY, innerWidth).addTo(this); + Path(x+Diagram.ARC_RADIUS*2+innerWidth, y+distanceFromY+item.height) + .arc('se') + .up(distanceFromY - Diagram.ARC_RADIUS*2 + item.height - this.height) + .arc('wn').addTo(this); + distanceFromY += Math.max(Diagram.ARC_RADIUS, item.height + item.down + Diagram.VERTICAL_SEPARATION + (i == last ? 0 : this.items[i+1].up)); + } + + return this; + } + + function MultipleChoice(normal, type, items) { + if(!(this instanceof MultipleChoice)) return new MultipleChoice(normal, type, [].slice.call(arguments,2)); + FakeSVG.call(this, 'g'); + if( typeof normal !== "number" || normal !== Math.floor(normal) ) { + throw new TypeError("The first argument of MultipleChoice() must be an integer."); + } else if(normal < 0 || normal >= items.length) { + throw new RangeError("The first argument of MultipleChoice() must be an index for one of the items."); + } else { + this.normal = normal; + } + if( type != "any" && type != "all" ) { + throw new SyntaxError("The second argument of MultipleChoice must be 'any' or 'all'."); + } else { + this.type = type; + } + this.needsSpace = true; + this.items = items.map(wrapString); + this.innerWidth = max(this.items, function(x){return x.width}); + this.width = 30 + Diagram.ARC_RADIUS + this.innerWidth + Diagram.ARC_RADIUS + 20; + this.up = this.items[0].up; + this.down = this.items[this.items.length-1].down; + this.height = this.items[normal].height; + for(var i = 0; i < this.items.length; i++) { + var item = this.items[i]; + if(i == normal - 1 || i == normal + 1) var minimum = 10 + Diagram.ARC_RADIUS; + else var minimum = Diagram.ARC_RADIUS; + if(i < normal) { + this.up += Math.max(minimum, item.height + item.down + Diagram.VERTICAL_SEPARATION + this.items[i+1].up); + } else if(i > normal) { + this.down += Math.max(minimum, item.up + Diagram.VERTICAL_SEPARATION + this.items[i-1].down + this.items[i-1].height); + } + } + this.down -= this.items[normal].height; // already counted in this.height + if(Diagram.DEBUG) { + this.attrs['data-updown'] = this.up + " " + this.height + " " + this.down + this.attrs['data-type'] = "multiplechoice" + } + } + subclassOf(MultipleChoice, FakeSVG); + MultipleChoice.prototype.format = function(x, y, width) { + var gaps = determineGaps(width, this.width); + Path(x, y).right(gaps[0]).addTo(this); + Path(x + gaps[0] + this.width, y + this.height).right(gaps[1]).addTo(this); + x += gaps[0]; + + var normal = this.items[this.normal]; + + // Do the elements that curve above + for(var i = this.normal - 1; i >= 0; i--) { + var item = this.items[i]; + if( i == this.normal - 1 ) { + var distanceFromY = Math.max(10 + Diagram.ARC_RADIUS, normal.up + Diagram.VERTICAL_SEPARATION + item.down + item.height); + } + Path(x + 30,y) + .up(distanceFromY - Diagram.ARC_RADIUS) + .arc('wn').addTo(this); + item.format(x + 30 + Diagram.ARC_RADIUS, y - distanceFromY, this.innerWidth).addTo(this); + Path(x + 30 + Diagram.ARC_RADIUS + this.innerWidth, y - distanceFromY + item.height) + .arc('ne') + .down(distanceFromY - item.height + this.height - Diagram.ARC_RADIUS - 10) + .addTo(this); + if(i != 0) { + distanceFromY += Math.max(Diagram.ARC_RADIUS, item.up + Diagram.VERTICAL_SEPARATION + this.items[i-1].down + this.items[i-1].height); + } + } + + Path(x + 30, y).right(Diagram.ARC_RADIUS).addTo(this); + normal.format(x + 30 + Diagram.ARC_RADIUS, y, this.innerWidth).addTo(this); + Path(x + 30 + Diagram.ARC_RADIUS + this.innerWidth, y + this.height).right(Diagram.ARC_RADIUS).addTo(this); + + for(var i = this.normal+1; i < this.items.length; i++) { + var item = this.items[i]; + if(i == this.normal + 1) { + var distanceFromY = Math.max(10+Diagram.ARC_RADIUS, normal.height + normal.down + Diagram.VERTICAL_SEPARATION + item.up); + } + Path(x + 30, y) + .down(distanceFromY - Diagram.ARC_RADIUS) + .arc('ws') + .addTo(this); + item.format(x + 30 + Diagram.ARC_RADIUS, y + distanceFromY, this.innerWidth).addTo(this) + Path(x + 30 + Diagram.ARC_RADIUS + this.innerWidth, y + distanceFromY + item.height) + .arc('se') + .up(distanceFromY - Diagram.ARC_RADIUS + item.height - normal.height) + .addTo(this); + if(i != this.items.length - 1) { + distanceFromY += Math.max(Diagram.ARC_RADIUS, item.height + item.down + Diagram.VERTICAL_SEPARATION + this.items[i+1].up); + } + } + var text = FakeSVG('g', {"class": "diagram-text"}).addTo(this) + FakeSVG('title', {}, (this.type=="any"?"take one or more branches, once each, in any order":"take all branches, once each, in any order")).addTo(text) + FakeSVG('path', { + "d": "M "+(x+30)+" "+(y-10)+" h -26 a 4 4 0 0 0 -4 4 v 12 a 4 4 0 0 0 4 4 h 26 z", + "class": "diagram-text" + }).addTo(text) + FakeSVG('text', { + "x": x + 15, + "y": y + 4, + "class": "diagram-text" + }, (this.type=="any"?"1+":"all")).addTo(text) + FakeSVG('path', { + "d": "M "+(x+this.width-20)+" "+(y-10)+" h 16 a 4 4 0 0 1 4 4 v 12 a 4 4 0 0 1 -4 4 h -16 z", + "class": "diagram-text" + }).addTo(text) + FakeSVG('path', { + "d": "M "+(x+this.width-13)+" "+(y-2)+" a 4 4 0 1 0 6 -1 m 2.75 -1 h -4 v 4 m 0 -3 h 2", + "style": "stroke-width: 1.75" + }).addTo(text) + return this; + }; + + function Optional(item, skip) { + if( skip === undefined ) + return Choice(1, Skip(), item); + else if ( skip === "skip" ) + return Choice(0, Skip(), item); + else + throw "Unknown value for Optional()'s 'skip' argument."; + } + + function OneOrMore(item, rep) { + if(!(this instanceof OneOrMore)) return new OneOrMore(item, rep); + FakeSVG.call(this, 'g'); + rep = rep || (new Skip); + this.item = wrapString(item); + this.rep = wrapString(rep); + this.width = Math.max(this.item.width, this.rep.width) + Diagram.ARC_RADIUS*2; + this.height = this.item.height; + this.up = this.item.up; + this.down = Math.max(Diagram.ARC_RADIUS*2, this.item.down + Diagram.VERTICAL_SEPARATION + this.rep.up + this.rep.height + this.rep.down); + if(Diagram.DEBUG) { + this.attrs['data-updown'] = this.up + " " + this.height + " " + this.down + this.attrs['data-type'] = "oneormore" + } + } + subclassOf(OneOrMore, FakeSVG); + OneOrMore.prototype.needsSpace = true; + OneOrMore.prototype.format = function(x,y,width) { + // Hook up the two sides if this is narrower than its stated width. + var gaps = determineGaps(width, this.width); + Path(x,y).h(gaps[0]).addTo(this); + Path(x+gaps[0]+this.width,y+this.height).h(gaps[1]).addTo(this); + x += gaps[0]; + + // Draw item + Path(x,y).right(Diagram.ARC_RADIUS).addTo(this); + this.item.format(x+Diagram.ARC_RADIUS,y,this.width-Diagram.ARC_RADIUS*2).addTo(this); + Path(x+this.width-Diagram.ARC_RADIUS,y+this.height).right(Diagram.ARC_RADIUS).addTo(this); + + // Draw repeat arc + var distanceFromY = Math.max(Diagram.ARC_RADIUS*2, this.item.height+this.item.down+Diagram.VERTICAL_SEPARATION+this.rep.up); + Path(x+Diagram.ARC_RADIUS,y).arc('nw').down(distanceFromY-Diagram.ARC_RADIUS*2).arc('ws').addTo(this); + this.rep.format(x+Diagram.ARC_RADIUS, y+distanceFromY, this.width - Diagram.ARC_RADIUS*2).addTo(this); + Path(x+this.width-Diagram.ARC_RADIUS, y+distanceFromY+this.rep.height).arc('se').up(distanceFromY-Diagram.ARC_RADIUS*2+this.rep.height-this.item.height).arc('en').addTo(this); + + return this; + } + + function ZeroOrMore(item, rep, skip) { + return Optional(OneOrMore(item, rep), skip); + } + + function Start(type) { + if(!(this instanceof Start)) return new Start(); + FakeSVG.call(this, 'path'); + this.width = 20; + this.height = 0; + this.up = 10; + this.down = 10; + this.type = type || "simple"; + if(Diagram.DEBUG) { + this.attrs['data-updown'] = this.up + " " + this.height + " " + this.down + this.attrs['data-type'] = "start" + } + } + subclassOf(Start, FakeSVG); + Start.prototype.format = function(x,y) { + if (this.type === "complex") { + this.attrs.d = 'M '+x+' '+(y-10)+' v 20 m 0 -10 h 20.5'; + } else { + this.attrs.d = 'M '+x+' '+(y-10)+' v 20 m 10 -20 v 20 m -10 -10 h 20.5'; + } + return this; + } + + function End(type) { + if(!(this instanceof End)) return new End(); + FakeSVG.call(this, 'path'); + this.width = 20; + this.height = 0; + this.up = 10; + this.down = 10; + this.type = type || "simple"; + if(Diagram.DEBUG) { + this.attrs['data-updown'] = this.up + " " + this.height + " " + this.down + this.attrs['data-type'] = "end" + } + } + subclassOf(End, FakeSVG); + End.prototype.format = function(x,y) { + if (this.type === "complex") { + this.attrs.d = 'M '+x+' '+y+' h 20 m 0 -10 v 20'; + } else { + this.attrs.d = 'M '+x+' '+y+' h 20 m -10 -10 v 20 m 10 -20 v 20'; + } + return this; + } + + function Terminal(text, href) { + if(!(this instanceof Terminal)) return new Terminal(text, href); + FakeSVG.call(this, 'g', {'class': 'terminal'}); + this.text = text; + this.href = href; + this.width = text.length * 8 + 20; /* Assume that each char is .5em, and that the em is 16px */ + this.height = 0; + this.up = 11; + this.down = 11; + if(Diagram.DEBUG) { + this.attrs['data-updown'] = this.up + " " + this.height + " " + this.down + this.attrs['data-type'] = "terminal" + } + } + subclassOf(Terminal, FakeSVG); + Terminal.prototype.needsSpace = true; + Terminal.prototype.format = function(x, y, width) { + // Hook up the two sides if this is narrower than its stated width. + var gaps = determineGaps(width, this.width); + Path(x,y).h(gaps[0]).addTo(this); + Path(x+gaps[0]+this.width,y).h(gaps[1]).addTo(this); + x += gaps[0]; + + FakeSVG('rect', {x:x, y:y-11, width:this.width, height:this.up+this.down, rx:10, ry:10}).addTo(this); + var text = FakeSVG('text', {x:x+this.width/2, y:y+4}, this.text); + if(this.href) + FakeSVG('a', {'xlink:href': this.href}, [text]).addTo(this); + else + text.addTo(this); + return this; + } + + function NonTerminal(text, href) { + if(!(this instanceof NonTerminal)) return new NonTerminal(text, href); + FakeSVG.call(this, 'g', {'class': 'non-terminal'}); + this.text = text; + this.href = href; + this.width = text.length * 8 + 20; + this.height = 0; + this.up = 11; + this.down = 11; + if(Diagram.DEBUG) { + this.attrs['data-updown'] = this.up + " " + this.height + " " + this.down + this.attrs['data-type'] = "nonterminal" + } + } + subclassOf(NonTerminal, FakeSVG); + NonTerminal.prototype.needsSpace = true; + NonTerminal.prototype.format = function(x, y, width) { + // Hook up the two sides if this is narrower than its stated width. + var gaps = determineGaps(width, this.width); + Path(x,y).h(gaps[0]).addTo(this); + Path(x+gaps[0]+this.width,y).h(gaps[1]).addTo(this); + x += gaps[0]; + + FakeSVG('rect', {x:x, y:y-11, width:this.width, height:this.up+this.down}).addTo(this); + var text = FakeSVG('text', {x:x+this.width/2, y:y+4}, this.text); + if(this.href) + FakeSVG('a', {'xlink:href': this.href}, [text]).addTo(this); + else + text.addTo(this); + return this; + } + + function Comment(text, href) { + if(!(this instanceof Comment)) return new Comment(text, href); + FakeSVG.call(this, 'g'); + this.text = text; + this.href = href; + this.width = text.length * 7 + 10; + this.height = 0; + this.up = 11; + this.down = 11; + if(Diagram.DEBUG) { + this.attrs['data-updown'] = this.up + " " + this.height + " " + this.down + this.attrs['data-type'] = "comment" + } + } + subclassOf(Comment, FakeSVG); + Comment.prototype.needsSpace = true; + Comment.prototype.format = function(x, y, width) { + // Hook up the two sides if this is narrower than its stated width. + var gaps = determineGaps(width, this.width); + Path(x,y).h(gaps[0]).addTo(this); + Path(x+gaps[0]+this.width,y+this.height).h(gaps[1]).addTo(this); + x += gaps[0]; + + var text = FakeSVG('text', {x:x+this.width/2, y:y+5, class:'comment'}, this.text); + if(this.href) + FakeSVG('a', {'xlink:href': this.href}, [text]).addTo(this); + else + text.addTo(this); + return this; + } + + function Skip() { + if(!(this instanceof Skip)) return new Skip(); + FakeSVG.call(this, 'g'); + this.width = 0; + this.height = 0; + this.up = 0; + this.down = 0; + if(Diagram.DEBUG) { + this.attrs['data-updown'] = this.up + " " + this.height + " " + this.down + this.attrs['data-type'] = "skip" + } + } + subclassOf(Skip, FakeSVG); + Skip.prototype.format = function(x, y, width) { + Path(x,y).right(width).addTo(this); + return this; + } + + var root; + if (typeof define === 'function' && define.amd) { + // AMD. Register as an anonymous module. + root = {}; + define([], function() { + return root; + }); + } else if (typeof exports === 'object') { + // CommonJS for node + root = exports; + } else { + // Browser globals (root is window) + root = this; + } + + var temp = [Diagram, ComplexDiagram, Sequence, Stack, OptionalSequence, Choice, MultipleChoice, Optional, OneOrMore, ZeroOrMore, Terminal, NonTerminal, Comment, Skip]; + /* + These are the names that the internal classes are exported as. + If you would like different names, adjust them here. + */ + ['Diagram', 'ComplexDiagram', 'Sequence', 'Stack', 'OptionalSequence', 'Choice', 'MultipleChoice', 'Optional', 'OneOrMore', 'ZeroOrMore', 'Terminal', 'NonTerminal', 'Comment', 'Skip'] + .forEach(function(e,i) { root[e] = temp[i]; }); +}).call(this, + { + VERTICAL_SEPARATION: 8, + ARC_RADIUS: 10, + DIAGRAM_CLASS: 'railroad-diagram', + STROKE_ODD_PIXEL_LENGTH: true, + INTERNAL_ALIGNMENT: 'center', + } +); diff --git a/docs/_static/images/sync_strobe.png b/docs/_static/misc/sync/sync_Strobe.png similarity index 100% rename from docs/_static/images/sync_strobe.png rename to docs/_static/misc/sync/sync_Strobe.png diff --git a/docs/_static/images/sync_strobe.svg b/docs/_static/misc/sync/sync_Strobe.svg similarity index 100% rename from docs/_static/images/sync_strobe.svg rename to docs/_static/misc/sync/sync_Strobe.svg diff --git a/docs/_static/sort/sortnet/sortnet_BitonicSort.png b/docs/_static/sort/sortnet/sortnet_BitonicSort.png new file mode 100644 index 00000000..b87e5d8e Binary files /dev/null and b/docs/_static/sort/sortnet/sortnet_BitonicSort.png differ diff --git a/docs/_static/sort/sortnet/sortnet_BitonicSort.svg b/docs/_static/sort/sortnet/sortnet_BitonicSort.svg new file mode 100644 index 00000000..a0cb19a0 --- /dev/null +++ b/docs/_static/sort/sortnet/sortnet_BitonicSort.svg @@ -0,0 +1,1502 @@ + + + +image/svg+xml \ No newline at end of file diff --git a/docs/_templates/autoapi/module.rst b/docs/_templates/autoapi/module.rst new file mode 100644 index 00000000..c6d4a0f9 --- /dev/null +++ b/docs/_templates/autoapi/module.rst @@ -0,0 +1,151 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + + +{{ node.name }} +=={{ '=' * node.name|length }}== + +.. automodule:: {{ node.name }} + +{##} +{%- block modules -%} +{%- if subnodes %} + +.. #----------------------------------- +{##} +**Submodules** + +.. toctree:: +{% for item in subnodes %} + {{ item.name }} +{%- endfor %} +{##} +{%- endif -%} +{%- endblock -%} +{##} +.. currentmodule:: {{ node.name }} +{##} + +.. #----------------------------------- +{##} +{%- if node.variables %} +**Variables** +{##} +{% for item, obj in node.variables.items() -%} +- :py:data:`{{ item }}` +{% endfor -%} +{%- endif -%} + + +{%- if node.exceptions %} +{##} +**Exceptions** +{##} +{% for item, obj in node.exceptions.items() -%} +- :py:exc:`{{ item }}`: + {{ obj|summary }} + +{% endfor -%} +{%- endif -%} + + +{%- if node.classes %} +{##} +**Classes** +{##} +{% for item, obj in node.classes.items() -%} +- :py:class:`{{ item }}`: + {{ obj|summary }} + +{% endfor -%} +{%- endif -%} + + +{%- if node.functions %} +{##} +**Functions** +{##} +{% for item, obj in node.functions.items() -%} +- :py:func:`{{ item }}`: + {{ obj|summary }} + +{% endfor -%} +{%- endif -%} + + +{%- block variables -%} +{%- if node.variables %} +{% for item, obj in node.variables.items() %} +.. autodata:: {{ item }} + :annotation: + + .. code-block:: guess + + {{ obj|pprint|indent(6) }} +{##} +{%- endfor -%} +{%- endif -%} +{%- endblock -%} + + +{%- block exceptions -%} +{%- if node.exceptions %} + +.. #----------------------------------- + +{% for item in node.exceptions %} +.. autoexception:: {{ item }} + :members: + :private-members: + :inherited-members: + :undoc-members: +{##} + .. rubric:: Inheritance + .. inheritance-diagram:: {{ item }} +{##} + .. rubric:: Members +{##} +{%- endfor -%} +{%- endif -%} +{%- endblock -%} + + +{%- block classes -%} +{%- if node.classes %} + +.. #----------------------------------- + +{% for item in node.classes %} +.. autoclass:: {{ item }} + :members: + :private-members: + :undoc-members: + :inherited-members: +{##} + .. rubric:: Inheritance + .. inheritance-diagram:: {{ item }} +{##} + .. rubric:: Members +{##} +{%- endfor -%} +{%- endif -%} +{%- endblock -%} + + +{%- block functions -%} +{%- if node.functions %} + +.. #----------------------------------- + +**Functions** + +{% for item in node.functions %} +.. autofunction:: {{ item }} +{##} +{%- endfor -%} +{%- endif -%} +{%- endblock -%} diff --git a/docs/_templates/autoapi/script.rst b/docs/_templates/autoapi/script.rst new file mode 100644 index 00000000..414161e5 --- /dev/null +++ b/docs/_templates/autoapi/script.rst @@ -0,0 +1,156 @@ +.. # Load pre-defined aliases from docutils + # is used to denote the special path + # \Lib\site-packages\docutils\parsers\rst\include + +.. include:: +.. include:: + + +{{ node.name }}.py +=={{ '=' * node.name|length }}== + +.. automodule:: {{ node.name }} + + +{##} +{%- block modules -%} +{%- if subnodes %} + +.. #----------------------------------- +{##} +**Submodules** + +.. toctree:: +{% for item in subnodes %} + {{ item.name }} +{%- endfor %} +{##} +{%- endif -%} +{%- endblock -%} +{##} +.. currentmodule:: {{ node.name }} +{##} + +.. #----------------------------------- +{##} +{%- if node.variables %} +**Variables** +{##} +{% for item, obj in node.variables.items() -%} +- :py:data:`{{ item }}` +{% endfor -%} +{%- endif -%} + + +{%- if node.exceptions %} +{##} +**Exceptions** +{##} +{% for item, obj in node.exceptions.items() -%} +- :py:exc:`{{ item }}`: + {{ obj|summary }} + +{% endfor -%} +{%- endif -%} + + +{%- if node.classes %} +{##} +**Classes** +{##} +{% for item, obj in node.classes.items() -%} +- :py:class:`{{ item }}`: + {{ obj|summary }} + +{% endfor -%} +{%- endif -%} + + +{%- if node.functions %} +{##} +**Functions** +{##} +{% for item, obj in node.functions.items() -%} +- :py:func:`{{ item }}`: + {{ obj|summary }} + +{% endfor -%} +{%- endif -%} + + +{%- block variables -%} +{%- if node.variables %} +{% for item, obj in node.variables.items() %} +.. autodata:: {{ item }} + :noindex: + :annotation: + + .. code-block:: guess + + {{ obj|pprint|indent(6) }} +{##} +{%- endfor -%} +{%- endif -%} +{%- endblock -%} + + +{%- block exceptions -%} +{%- if node.exceptions %} + +.. #----------------------------------- + +{% for item in node.exceptions %} +.. autoexception:: {{ item }} + :members: + :noindex: + :private-members: + :inherited-members: + :undoc-members: +{##} + .. rubric:: Inheritance + .. inheritance-diagram:: {{ item }} +{##} + .. rubric:: Members +{##} +{%- endfor -%} +{%- endif -%} +{%- endblock -%} + + +{%- block classes -%} +{%- if node.classes %} + +.. #----------------------------------- + +{% for item in node.classes %} +.. autoclass:: {{ item }} + :members: + :noindex: + :private-members: + :undoc-members: + :inherited-members: +{##} + .. rubric:: Inheritance + .. inheritance-diagram:: {{ item }} +{##} + .. rubric:: Members +{##} +{%- endfor -%} +{%- endif -%} +{%- endblock -%} + + +{%- block functions -%} +{%- if node.functions %} + +.. #----------------------------------- + +**Functions** + +{% for item in node.functions %} +.. autofunction:: {{ item }} + :noindex: +{##} +{%- endfor -%} +{%- endif -%} +{%- endblock -%} diff --git a/docs/conf.py b/docs/conf.py index fdbd4b99..d6491cf6 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -16,34 +16,71 @@ import sys import os +from subprocess import check_output + # If extensions (or modules to document with autodoc) are in another directory, # add these directories to sys.path here. If the directory is relative to the # documentation root, use os.path.abspath to make it absolute, like shown here. sys.path.insert(0, os.path.abspath('.')) +sys.path.insert(0, os.path.abspath('../py')) +sys.path.insert(0, os.path.abspath('_extensions')) + # -- General configuration ------------------------------------------------ # If your documentation needs a minimal Sphinx version, state it here. -#needs_sphinx = '1.0' +needs_sphinx = '1.4.9' # Add any Sphinx extension module names here, as strings. They can be # extensions coming with Sphinx (named 'sphinx.ext.*') or your custom # ones. extensions = [ - 'sphinx.ext.autodoc', - 'sphinx.ext.intersphinx', - 'sphinx.ext.todo', - 'sphinx.ext.coverage', - 'sphinx.ext.mathjax', - 'sphinx.ext.ifconfig', - 'sphinx.ext.viewcode', - # 'sphinx.ext.githubpages', - 'poc' +# Standard Sphinx extensions + 'sphinx.ext.autodoc', + 'sphinx.ext.extlinks', + 'sphinx.ext.intersphinx', + 'sphinx.ext.inheritance_diagram', + 'sphinx.ext.todo', + # 'sphinx.ext.coverage', + 'sphinx.ext.graphviz', + 'sphinx.ext.mathjax', + 'sphinx.ext.ifconfig', + 'sphinx.ext.viewcode', + # 'sphinx.ext.githubpages', +# SphinxContrib extensions + # 'sphinxcontrib.actdiag', + # 'sphinxcontrib.seqdiag', + 'sphinxcontrib.wavedrom', + # 'sphinxcontrib.textstyle', + # 'sphinxcontrib.spelling', + 'autoapi.sphinx', + # 'changelog', +# local extensions (patched) + 'autoprogram', #'sphinxcontrib.autoprogram', +# local extensions + 'DocumentMember', + 'poc' ] -if (not (tags.has('PoCExternal') or tags.has('PoCInternal'))): - tags.add('PoCExternal') +for tag in tags: + print(tag) + +# if (not (tags.has('PoCExternal') or tags.has('PoCInternal'))): + # tags.add('PoCExternal') + +autodoc_member_order = "bysource" +# Extract Python documentation and generate ReST files. +autoapi_modules = { + 'PoC': {'output': "PyInfrastructure", 'template': "script"}, + 'Base': {'output': "PyInfrastructure"}, + 'Compiler': {'output': "PyInfrastructure"}, + 'DataBase': {'output': "PyInfrastructure"}, + 'Parser': {'output': "PyInfrastructure"}, + 'Simulator': {'output': "PyInfrastructure"}, + 'ToolChains': {'output': "PyInfrastructure"}, + 'lib': {'output': "PyInfrastructure"} +} # Add any paths that contain templates here, relative to this directory. templates_path = ['_templates', '_themes'] @@ -61,17 +98,33 @@ # General information about the project. project = 'The PoC-Library' -copyright = '2007-2016 Technische Universitaet Dresden - Germany, Chair for VLSI-Design, Diagnostics and Architecture' +copyright = '2007-2016 Technische Universitaet Dresden - Germany, Chair of VLSI-Design, Diagnostics and Architecture' author = 'Patrick Lehmann, Thomas B. Preusser, Martin Zabel' # The version info for the project you're documenting, acts as replacement for # |version| and |release|, also used in various other places throughout the # built documents. -# -# The short X.Y version. -version = '1.0' -# The full version, including alpha/beta/rc tags. -release = '1.0.0' + +def _IsUnderGitControl(): + return (check_output(["git", "rev-parse", "--is-inside-work-tree"], universal_newlines=True).strip() == "true") + +def _LatestTagHash(): + return check_output(["git", "rev-list", "--tags", "--max-count=1"], universal_newlines=True).strip() + +def _LatestTagName(latestTagHash): + return check_output(["git", "describe", "--tags", latestTagHash], universal_newlines=True).strip() + +version = "1.1" # The short X.Y version. +release = "1.1.0" # The full version, including alpha/beta/rc tags. +try: + if _IsUnderGitControl: + latestTagName = _LatestTagName(_LatestTagHash())[1:] # remove prefix "v" + versionParts = latestTagName.split("-")[0].split(".") + + version = ".".join(versionParts[:2]) + release = latestTagName # ".".join(versionParts[:3]) +except: + pass # The language for content autogenerated by Sphinx. Refer to documentation # for a list of supported languages. @@ -193,7 +246,7 @@ #html_use_index = True # If true, the index is split into individual pages for each letter. -#html_split_index = False +# html_split_index = True # If true, links to the reST sources are added to the pages. #html_show_sourcelink = True @@ -260,7 +313,7 @@ # For "manual" documents, if this is true, then toplevel headings are parts, # not chapters. -#latex_use_parts = False +# latex_use_parts = True # If true, show page references after internal links. #latex_show_pagerefs = False @@ -311,6 +364,107 @@ # If true, do not generate a @detailmenu in the "Top" node's menu. #texinfo_no_detailmenu = False +# ============================================================================== +# Sphinx.Ext.InterSphinx +# ============================================================================== +intersphinx_mapping = { + 'python': ('https://docs.python.org/3.5/', None), + 'ghdl': ('http://ghdl.readthedocs.io/en/latest', None) +} + +# ============================================================================== +# Sphinx.Ext.ExtLinks +# ============================================================================== +extlinks = { + 'pocissue': ('https://github.com/VLSI-EDA/PoC/issues/%s', 'issue #'), + 'pocpull': ('https://github.com/VLSI-EDA/PoC/pull/%s', 'pull request #'), + 'pocsrc': ('https://github.com/VLSI-EDA/PoC/blob/master/src/%s?ts=2', None), + 'poctb': ('https://github.com/VLSI-EDA/PoC/blob/master/tb/%s?ts=2', None) +} + -# Example configuration for intersphinx: refer to the Python standard library. -intersphinx_mapping = {'https://docs.python.org/': None} +# ============================================================================== +# Sphinx.Ext.Graphviz +# ============================================================================== +graphviz_output_format = "svg" + + +# ============================================================================== +# Changelog +# ============================================================================== +# section names - optional +changelog_sections = ["general", "rendering", "tests"] + +# tags to sort on inside of sections - also optional +changelog_inner_tag_sort = ["feature", "bug"] + +# how to render changelog links - these are plain +# python string templates, ticket/pullreq/changeset number goes +# in "%s" +changelog_render_ticket = "http://bitbucket.org/myusername/myproject/issue/%s" +changelog_render_pullreq = "http://bitbucket.org/myusername/myproject/pullrequest/%s" +changelog_render_changeset = "http://bitbucket.org/myusername/myproject/changeset/%s" + + +# ============================================================================== +# SphinxContrib.Spelling +# ============================================================================== +# # String specifying the language, as understood by PyEnchant and enchant. +# # Defaults to en_US for US English. +# spelling_lang='en_US' +# +# # String specifying a file containing a list of words known to be spelled +# # correctly but that do not appear in the language dictionary selected by +# # spelling_lang. The file should contain one word per line. +# # Refer to the PyEnchant tutorial for details. +# #spelling_word_list_filename='spelling_wordlist.txt' +# +# # Boolean controlling whether suggestions for misspelled words are printed. +# # Defaults to False. +# spelling_show_suggestions=True +# +# # Boolean controlling whether words that look like package names from PyPI are +# # treated as spelled properly. When True, the current list of package names is +# # downloaded at the start of the build and used to extend the list of known +# # words in the dictionary. +# # Defaults to False. +# spelling_ignore_pypi_package_names=False +# +# # Boolean controlling whether words that follow the CamelCase conventions used +# # for page names in wikis should be treated as spelled properly. +# # Defaults to True. +# spelling_ignore_wiki_words=True +# +# # Boolean controlling treatment of words that appear in all capital letters, or +# # all capital letters followed by a lower case s. When True, acronyms are +# # assumed to be spelled properly. +# # Defaults to True. +# spelling_ignore_acronyms=True +# +# # Boolean controlling whether names built in to Python should be treated as +# # spelled properly. +# # Defaults to True. +# spelling_ignore_python_builtins=True +# +# # Boolean controlling whether words that are names of modules found on +# # sys.path are treated as spelled properly. +# # Defaults to True. +# spelling_ignore_importable_modules=True +# +# # List of filter classes to be added to the tokenizer that produces words to be +# # checked. The classes should be derived from enchant.tokenize.Filter. Refer to +# # the PyEnchant tutorial for examples. +# spelling_filters=[] + + +# ============================================================================== +# Custom changes +# ============================================================================== +def setup(app): + app.add_stylesheet('css/custom.css') + if tags.has('PoCInternal'): + app.add_config_value('visibility', 'PoCInternal', True) + print("="* 40) + else: + app.add_config_value('visibility', 'PoCExternal', True) + print("-"* 40) diff --git a/docs/genindex.rst b/docs/genindex.rst new file mode 100644 index 00000000..c07da40d --- /dev/null +++ b/docs/genindex.rst @@ -0,0 +1,4 @@ +.. This file is a placeholder and will be replaced + +Index +##### diff --git a/docs/index.rst b/docs/index.rst index c4978f7c..b2014035 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -1,38 +1,61 @@ +.. raw:: latex + + \part{Introduction} + This library is published and maintained by **Chair for VLSI Design, Diagnostics and Architecture** - Faculty of Computer Science, Technische Universität Dresden, Germany |br| `https://tu-dresden.de/ing/informatik/ti/vlsi `_ -.. image:: _static/logos/tu-dresden.jpg - :scale: 10 - :alt: Technische Universität Dresden +.. only:: html --------------------------------------------------------------------------------- + .. image:: /_static/logos/tu-dresden.jpg + :scale: 10 + :alt: Technische Universität Dresden -.. image:: _static/logos/GitHub-Mark-32px.png - :scale: 60 - :target: https://www.github.com/VLSI-EDA/PoC - :alt: Source Code on GitHub -.. image:: https://landscape.io/github/VLSI-EDA/PoC/release/landscape.svg?style=flat - :target: https://landscape.io/github/VLSI-EDA/PoC/release - :alt: Code Health -.. image:: https://travis-ci.org/VLSI-EDA/PoC.svg?branch=release - :target: https://travis-ci.org/VLSI-EDA/PoC - :alt: Build Results -.. image:: https://badges.gitter.im/VLSI-EDA/PoC.svg - :target: https://gitter.im/VLSI-EDA/PoC - :alt: Join -.. image:: https://img.shields.io/github/tag/VLSI-EDA/PoC.svg?style=flat - :alt: Latest tag -.. image:: https://img.shields.io/github/release/VLSI-EDA/PoC.svg?style=flat - :target: https://github.com/VLSI-EDA/PoC/releases - :alt: Latest release -.. image:: https://img.shields.io/github/license/VLSI-EDA/PoC.svg?style=flat - :target: References/Licenses/License.html - :alt: Apache License 2.0 +.. only:: latex + + .. image:: /_static/logos/tu-dresden.jpg + :scale: 80 + :alt: Technische Universität Dresden -------------------------------------------------------------------------------- +.. only:: html + + .. image:: /_static/logos/GitHub-Mark-32px.png + :scale: 60 + :target: https://www.github.com/VLSI-EDA/PoC + :alt: Source Code on GitHub + .. image:: https://landscape.io/github/VLSI-EDA/PoC/release/landscape.svg?style=flat + :target: https://landscape.io/github/VLSI-EDA/PoC/release + :alt: Code Health + .. image:: https://travis-ci.org/VLSI-EDA/PoC.svg?branch=release + :target: https://travis-ci.org/VLSI-EDA/PoC + :alt: Build status by Travis-CI + .. image:: https://ci.appveyor.com/api/projects/status/r5dtv6amsppigpsp/branch/release?svg=true + :target: https://ci.appveyor.com/project/Paebbels/poc/branch/release + :alt: Build status by AppVeyor + .. image:: https://requires.io/github/VLSI-EDA/PoC/requirements.svg?branch=release + :target: https://requires.io/github/VLSI-EDA/PoC/requirements/?branch=release + :alt: Requirements Status + .. image:: https://badges.gitter.im/VLSI-EDA/PoC.svg + :target: https://gitter.im/VLSI-EDA/PoC + :alt: Join + .. image:: https://img.shields.io/github/tag/VLSI-EDA/PoC.svg?style=flat + :alt: Latest tag + .. image:: https://img.shields.io/github/release/VLSI-EDA/PoC.svg?style=flat + :target: https://github.com/VLSI-EDA/PoC/releases + :alt: Latest release + .. image:: https://img.shields.io/github/license/VLSI-EDA/PoC.svg?style=flat + :target: References/Licenses/License.html + :alt: Apache License 2.0 + + .. raw:: html + +
+ + The PoC-Library Documentation ############################# @@ -52,19 +75,32 @@ PoC. To generalize all supported free and commercial vendor tool chains, PoC is shipped with a Python based infrastructure to offer a command line based frontend. -News -**** +.. only:: html -13.05.2016 - PoC 1.0.0 was released. -==================================== + News + **** + + 13.05.2016 - PoC 1.0.0 was released. + ==================================== + +.. only:: latex + + .. rubric:: 13.05.2016 - PoC 1.0.0 was released. Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet -Cite the PoC-Library -******************** + +.. only:: html + + Cite the PoC-Library + ******************** + +.. only:: latex + + .. rubric:: Cite the PoC-Library The PoC-Library hosted at `GitHub.com `_. Please use the following `biblatex `_ entry to cite us: @@ -81,17 +117,72 @@ following `biblatex `_ entry to cite us: urldate={2016-10-28}, } +------------------------------------ + +.. |docdate| date:: %b %d, %Y - %H:%M + +.. only:: html + + This document was generated on |docdate|. + .. toctree:: + :caption: Introduction :hidden: WhatIsPoC/index QuickStart + GetInvolved/index + References/Licenses/License + +.. raw:: latex + + \part{Main Documentation} + +.. toctree:: + :caption: Main Documentation + :hidden: + UsingPoC/index - PoC/index + Interfaces/index + IPCores/index Miscelaneous/ThirdParty ConstraintFiles/index - References/index - GetInvolved/index - Miscelaneous/ChangeLog - References/Licenses/License + ToolChains/index + Examples/index + +.. raw:: latex + + \part{References} + +.. toctree:: + :caption: References + :hidden: + + References/CommandReference + References/Database + PyInfrastructure/index + More ... + +.. raw:: latex + + \part{Appendix} + +.. toctree:: + :caption: Appendix + :hidden: + + ChangeLog/index + genindex + +.. ifconfig:: visibility in ('PoCInternal') + + .. raw:: latex + + \part{Main Internal} + + .. toctree:: + :caption: Internal + :hidden: + + Internal/Sphinx diff --git a/docs/poc.py b/docs/poc.py index 47e9112e..9e5232c9 100644 --- a/docs/poc.py +++ b/docs/poc.py @@ -15,7 +15,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -43,10 +43,12 @@ def __init__(self, file, startRow, endRow): self.StartRow = startRow self.EndRow = endRow + class SourceFile: def __init__(self, entitySourceCodeRange): #, entityName, entitySourceCodeRange, summary, description, seeAlso): self.File = entitySourceCodeRange.SourceFile self.EntityName = "" # entityName + self.EntityFullName = "" # entityName self.EntitySourceCodeRange = entitySourceCodeRange self.Authors = [] self.Summary = "" # summary @@ -56,9 +58,10 @@ def __init__(self, entitySourceCodeRange): #, entityName, entitySourceCodeRan class Extract: def __init__(self): - self.sourceDirectory = Path("../src") - self.outputDirectory = Path("PoC") - self.relSourceDirectory = Path("../../src") + self.sourceDirectory = Path("../src") + self.outputDirectory = Path("IPCores") + self.relSourceDirectory = Path("../../src") + self.relTestbenchDirectory = Path("../../tb") self.templateFile = Path("Entity.template") self.templateContent = "" @@ -100,9 +103,11 @@ def recursion2(self, result): self.writeReST(item) def writeReST(self, sourceFile): - relPath = sourceFile.File.relative_to(self.sourceDirectory) - outputFile = self.outputDirectory / relPath.with_suffix(".rst") - relSourceFile = ("../" * (len(relPath.parents) - 1)) / self.relSourceDirectory / relPath + sourceRelPath = sourceFile.File.relative_to(self.sourceDirectory) + outputFile = self.outputDirectory / sourceRelPath.with_suffix(".rst") + relSourceFile = ("../" * (len(sourceRelPath.parents) - 1)) / self.relSourceDirectory / sourceRelPath + + testbenchRelPath = Path(sourceRelPath.with_name(sourceRelPath.stem + "_tb.vhdl")) print("Writing reST file '{0!s}'.".format(outputFile)) @@ -111,19 +116,22 @@ def writeReST(self, sourceFile): # print(" Entity '{0}' at {1}..{2}.".format(sourceFile.EntityName, sourceFile.EntitySourceCodeRange.StartRow, sourceFile.EntitySourceCodeRange.EndRow)) if (sourceFile.SeeAlso != ""): - seeAlsoBox = ".. seealso::\n \n" + seeAlsoBox = ".. seealso::\n\n" for line in sourceFile.SeeAlso.splitlines(): - seeAlsoBox += " {line}\n".format(line=line) + if line == "": seeAlsoBox += "\n" + else: seeAlsoBox += " {line}\n".format(line=line) else: seeAlsoBox = "" outputContent = self.templateContent.format( EntityName=sourceFile.EntityName, - EntityNameUnderline="#" * len(sourceFile.EntityName), + EntityFullName=sourceFile.EntityFullName, + EntityNameUnderline="#" * len(sourceFile.EntityFullName), EntityDescription=sourceFile.Description, EntityFilePath=relSourceFile.as_posix(), EntityDeclarationFromTo="{0}-{1}".format(sourceFile.EntitySourceCodeRange.StartRow, sourceFile.EntitySourceCodeRange.EndRow), - GitHubSourceFile="`{relPath} `_".format(relPath=relPath.as_posix()), + SourceRelPath=sourceRelPath.as_posix(), + TestbenchRelPath=testbenchRelPath.as_posix(), SeeAlsoBox=seeAlsoBox ) @@ -133,14 +141,15 @@ def writeReST(self, sourceFile): def ExtractComments(self, sourceFile): """ Extracts the documentation from the header of a PoC VHDL source. - - The documentation header starts with a separator line matching /^--\s*={16,}$/. - - The documentation header continues through all immediately following comment lines. - - The contained information is added to the currently active section. - - A specific section is opened by a line matching /^--\s*(?P
\w+):/ with -
as one of Authors|Entity|Description|SeeAlso|License. - - An underline /^-- -+$/ immediately following a section opening is ignored. - - After the documentation header, the entity name is extracted from the entity declaration. - """ + + * The documentation header starts with a separator line matching /^--\s*={16,}$/. + * The documentation header continues through all immediately following comment lines. + * The contained information is added to the currently active section. + * A specific section is opened by a line matching /^--\s*(?P
\w+):/ with +
as one of Authors|Entity|Description|SeeAlso|License. + * An underline /^-- -+$/ immediately following a section opening is ignored. + * After the documentation header, the entity name is extracted from the entity declaration. + """ class State(Enum): BeforeDocHeader = 0 InDocHeader = 1 @@ -223,11 +232,12 @@ class State(Enum): # Construct Result Object result = SourceFile(SourceCodeRange(sourceFile, 0, 0)) - result.Authors = [author for author in sections['Authors'].splitlines()] - result.Summary = sections['Entity'] - result.Description = sections['Description'] - result.SeeAlso = sections['SeeAlso'] - result.EntityName = entityName + result.Authors = [author for author in sections['Authors'].splitlines()] + result.Summary = sections['Entity'] + result.Description = sections['Description'] + result.SeeAlso = sections['SeeAlso'] + result.EntityName = entityName + result.EntityFullName = "PoC." + ".".join(sourceFile.parts[2:-1]) + "." + sourceFile.stem[len(sourceFile.parts[-2])+1:] result.EntitySourceCodeRange.StartRow = entityStartLine result.EntitySourceCodeRange.EndRow = entityEndLine return result diff --git a/lib/Altera.files b/lib/Altera.files index b143cd9b..178ee4cc 100644 --- a/lib/Altera.files +++ b/lib/Altera.files @@ -55,7 +55,7 @@ if (Tool = "GHDL") then report "No precompiled Altera primitives for GHDL found." end if elseif (Tool in ["Mentor_vSim", "Cocotb_QuestaSim"]) then - path Altera_Directory = (PreCompiled / (${CONFIG.DirectoryNames:ModelSimFiles} / ${CONFIG.DirectoryNames:AlteraSpecificFiles})) + path Altera_Directory = (PreCompiled / (${CONFIG.DirectoryNames:QuestaSimFiles} / ${CONFIG.DirectoryNames:AlteraSpecificFiles})) if ?{Altera_Directory} then library lpm Altera_Directory library sgate Altera_Directory diff --git a/lib/MIT UVVM.md b/lib/MIT UVVM.md new file mode 100644 index 00000000..85f7e4ad --- /dev/null +++ b/lib/MIT UVVM.md @@ -0,0 +1,21 @@ +# The MIT License (MIT) + +**Copyright © 2016 by Bitvis AS** + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. diff --git a/lib/OSVVM.files b/lib/OSVVM.files index 358a4529..e7da9117 100644 --- a/lib/OSVVM.files +++ b/lib/OSVVM.files @@ -18,11 +18,11 @@ elseif (VHDLVersion = 2008) then report "No precompiled OSVVM library for GHDL found." end if elseif (Tool = "Mentor_vSim") then - path OSVVM_LibraryPath = (PreCompiled / (${CONFIG.DirectoryNames:ModelSimFiles} / OSVVM_Directory)) + path OSVVM_LibraryPath = (PreCompiled / (${CONFIG.DirectoryNames:QuestaSimFiles} / OSVVM_Directory)) if ?{OSVVM_LibraryPath} then library osvvm OSVVM_LibraryPath else - report "No precompiled QuestaSim/ModelSim library for GHDL found." + report "No precompiled OSVVM library for QuestaSim/ModelSim found." end if else # TODO self-compile section? diff --git a/lib/README.md b/lib/README.md index 844ff8b2..318597cb 100644 --- a/lib/README.md +++ b/lib/README.md @@ -57,6 +57,35 @@ Source: [https://github.com/JimLewis/OSVVM][21] [21]: https://github.com/JimLewis/OSVVM +## Universal VHDL Verification Methodology (UVVM) + +**Folder:** `\lib\uvvm\` +**Copyright:** Copyright © 2016 by [Bitvis AS](http://bitvis.no/) +**License:** [The MIT License (MIT)](MIT UVVM.md) + +The Open Source **UVVM (Universal VHDL Verification Methodology) - VVC (VHDL +Verification Component) Framework** for making structured VHDL testbenches +for verification of FPGA. UVVM consists currently of: Utility Library, VVC +Framework and Verification IPs (VIP) for various protocols. + +**For what do I need this VVC Framework?** +The VVC Framework is a VHDL Verification Component system that allows multiple +interfaces on a DUT to be stimulated/handled simultaneously in a very +structured manner, and controlled by a very simple to understand software like +a test sequencer. VVC Framework is unique as an open source VHDL approach to +building a structured testbench architecture using Verification components and +a simple protocol to access these. As an example a simple command like +`uart_expect(UART_VVCT, my_data)`, or `axilite_write(AXILITE_VVCT, my_addr, my_data, my_message)` +will automatically tell the respective VVC (for UART or AXI-Lite) to execute the +`uart_receive()` or `axilite_write()` BFM respectively. + +Website: [http://bitvis.no/][30] +Source: [https://github.com/UVVM/UVVM_All][31] + + [30]: http://bitvis.no/ + [31]: https://github.com/UVVM/UVVM_All + + ## VUnit **Folder:** `\lib\vunit\` @@ -69,11 +98,11 @@ needed to realize continuous and automated testing of your VHDL code. VUnit doesn't replace but rather complements traditional testing methodologies by supporting a "test early and often" approach through automation. -Website: [https://vunit.github.io/][30] -Source: [https://github.com/VUnit/vunit][31] +Website: [https://vunit.github.io/][40] +Source: [https://github.com/VUnit/vunit][41] - [30]: https://vunit.github.io/ - [31]: https://github.com/VUnit/vunit + [40]: https://vunit.github.io/ + [41]: https://github.com/VUnit/vunit ## Xillybus @@ -82,13 +111,13 @@ Source: [https://github.com/VUnit/vunit][31] **Copyright:** TODO **License:** TODO, see [local copy](Xillybus License.md) -[xillybus][40] TODO +[xillybus][50] TODO -Documentation: [http://xillybus.com][40] -Source: [http://xillybus.com][41] +Documentation: [http://xillybus.com][50] +Source: [http://xillybus.com][51] - [40]: http://xillybus.com - [41]: http://xillybus.com + [50]: http://xillybus.com + [51]: http://xillybus.com [PAL2.0]: http://www.perlfoundation.org/artistic_license_2_0 diff --git a/lib/UVVM.files b/lib/UVVM.files new file mode 100644 index 00000000..2a74df50 --- /dev/null +++ b/lib/UVVM.files @@ -0,0 +1,58 @@ +# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +# vim: tabstop=2:shiftwidth=2:noexpandtab +# kate: tab-width 2; replace-tabs off; indent-width 2; +# ============================================================================== +# Note: all files are relative to PoC root directory +# +path PreCompiled = ${CONFIG.DirectoryNames:PrecompiledFiles} +path UVVM_Directory = "uvvm" + +if (VHDLVersion < 2002) then + report "UVVM requires VHDL-2002." +elseif (VHDLVersion >= 2002) then + if (Tool = "GHDL") then + path GHDLPath = (PreCompiled / ${CONFIG.DirectoryNames:GHDLFiles}) + path UVVM_LibraryPath = (GHDLPath / UVVM_Directory) + if ?{(UVVM_LibraryPath / "uvvm_util/v08/uvvm_util-obj08.cf")} then + library uvvm_util UVVM_LibraryPath + end if + if ?{(UVVM_LibraryPath / "uvvm_vvc_framework/v08/uvvm_vvc_framework-obj08.cf")} then + library uvvm_vvc_framework UVVM_LibraryPath + end if + if ?{(UVVM_LibraryPath / "bitvis_vip_axilite/v08/bitvis_vip_axilite-obj08.cf")} then + library bitvis_vip_axilite UVVM_LibraryPath + end if + if ?{(UVVM_LibraryPath / "bitvis_vip_axistream/v08/bitvis_vip_axistream-obj08.cf")} then + library bitvis_vip_axistream UVVM_LibraryPath + end if + if ?{(UVVM_LibraryPath / "bitvis_vip_i2c/v08/bitvis_vip_i2c-obj08.cf")} then + library bitvis_vip_i2c UVVM_LibraryPath + end if + if ?{(UVVM_LibraryPath / "bitvis_vip_sbi/v08/bitvis_vip_sbi-obj08.cf")} then + library bitvis_vip_sbi UVVM_LibraryPath + end if + if ?{(UVVM_LibraryPath / "bitvis_vip_uart/v08/bitvis_vip_uart-obj08.cf")} then + library bitvis_vip_uart UVVM_LibraryPath + else + report "No precompiled UVVM libraries for GHDL found." + end if + elseif (Tool = "Mentor_vSim") then + path UVVM_LibraryPath = (PreCompiled / (${CONFIG.DirectoryNames:QuestaSimFiles} / UVVM_Directory)) + if ?{UVVM_LibraryPath} then + library uvvm_util UVVM_LibraryPath + library uvvm_vvc_framework UVVM_LibraryPath + library bitvis_vip_axilite UVVM_LibraryPath + library bitvis_vip_axistream UVVM_LibraryPath + library bitvis_vip_i2c UVVM_LibraryPath + library bitvis_vip_sbi UVVM_LibraryPath + library bitvis_vip_uart UVVM_LibraryPath + else + report "No precompiled UVVM libraries for QuestaSim/ModelSim found." + end if + else + # TODO self-compile section? + # vhdl uvvm "lib/uvvm/NamePkg.vhd" # UVVM + end if +else + report "VHDL version not supported by UVVM." +end if diff --git a/lib/Xilinx.files b/lib/Xilinx.files index a5e0008c..bd48ef83 100644 --- a/lib/Xilinx.files +++ b/lib/Xilinx.files @@ -47,7 +47,7 @@ if (Tool = "GHDL") then report "No precompiled Xilinx primitives for GHDL found." end if elseif (Tool in ["Mentor_vSim", "Cocotb_QuestaSim"]) then - path Xilinx_Directory = (PreCompiled / (${CONFIG.DirectoryNames:ModelSimFiles} / ${CONFIG.DirectoryNames:XilinxSpecificFiles})) + path Xilinx_Directory = (PreCompiled / (${CONFIG.DirectoryNames:QuestaSimFiles} / ${CONFIG.DirectoryNames:XilinxSpecificFiles})) if ?{Xilinx_Directory} then library unisim Xilinx_Directory library unimacro Xilinx_Directory diff --git a/lib/cocotb b/lib/cocotb index 4391cdfe..b1a99bcf 160000 --- a/lib/cocotb +++ b/lib/cocotb @@ -1 +1 @@ -Subproject commit 4391cdfe3b15e25c4b26c1ffa6b5837d13718ca6 +Subproject commit b1a99bcf213c478d955ab9fd61d425ec11ff0e0a diff --git a/lib/uvvm b/lib/uvvm new file mode 160000 index 00000000..0ce4f8fe --- /dev/null +++ b/lib/uvvm @@ -0,0 +1 @@ +Subproject commit 0ce4f8fe59d14d01ddc50f84fcda2fbb521ae633 diff --git a/lib/vunit b/lib/vunit index 48c9aaec..9eb5b0aa 160000 --- a/lib/vunit +++ b/lib/vunit @@ -1 +1 @@ -Subproject commit 48c9aaecb5d786b1fee680bb064b75664627c975 +Subproject commit 9eb5b0aa8fdadb4e67c402cf64c1edbab3b02461 diff --git a/poc.ps1 b/poc.ps1 index 4228bfe7..0d5d54f2 100644 --- a/poc.ps1 +++ b/poc.ps1 @@ -16,7 +16,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -59,7 +59,7 @@ if ($Debug -eq $true ) { Write-Host "This is the PoC-Library script wrapper operating in debug mode." -ForegroundColor Yellow Write-Host "" Write-Host "Directories:" -ForegroundColor Yellow - Write-Host " PoC Root $PoC_RootDir" -ForegroundColor Yellow + Write-Host " PoC Root $PoCRootDir" -ForegroundColor Yellow Write-Host " Working $PyWrapper_WorkingDir" -ForegroundColor Yellow Write-Host "Script:" -ForegroundColor Yellow Write-Host " Filename $PoC_ScriptPy" -ForegroundColor Yellow @@ -74,9 +74,9 @@ if ($Debug -eq $true ) { # execute script with appropriate Python interpreter and all given parameters if ($PoC_Solution -eq "") -{ $Command = "$Python_Interpreter $Python_Parameters $PoC_RootDir\$PoC_ScriptPy $args" } +{ $Command = "$Python_Interpreter $Python_Parameters $PoCRootDir\$PoC_ScriptPy $args" } else -{ $Command = "$Python_Interpreter $Python_Parameters $PoC_RootDir\$PoC_ScriptPy --sln=$PoC_Solution $args" } +{ $Command = "$Python_Interpreter $Python_Parameters $PoCRootDir\$PoC_ScriptPy --sln=$PoC_Solution $args" } # execute script with appropriate Python interpreter and all given parameters if ($Debug -eq $true) { Write-Host "launching: '$Command'" -ForegroundColor Yellow } diff --git a/poc.sh b/poc.sh index dd9a270a..c481bcb3 100755 --- a/poc.sh +++ b/poc.sh @@ -18,7 +18,7 @@ # License: # ============================================================================== # Copyright 2007-2016 Technische Universitaet Dresden - Germany -# Chair for VLSI-Design, Diagnostics and Architecture +# Chair of VLSI-Design, Diagnostics and Architecture # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/py/.idea/misc.xml b/py/.idea/misc.xml index 58450a2b..95a2e3ab 100644 --- a/py/.idea/misc.xml +++ b/py/.idea/misc.xml @@ -1,14 +1,4 @@ - - - - - - - - - - - + \ No newline at end of file diff --git a/py/.idea/py.iml b/py/.idea/py.iml index eaaad0b1..abd3de5f 100644 --- a/py/.idea/py.iml +++ b/py/.idea/py.iml @@ -6,7 +6,7 @@ - + diff --git a/py/.idea/workspace.xml b/py/.idea/workspace.xml index 66b83662..0abab28d 100644 --- a/py/.idea/workspace.xml +++ b/py/.idea/workspace.xml @@ -2,13 +2,10 @@ - - - - - - - + + + + @@ -28,135 +25,84 @@ - - + + - - - + + + + + + - - + + - - + + - - + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - - + + - - + + - - - - - - - - - - - - - - + + - - + + - - + + - - + + - - + + - - - - - - - - - - - - - - + + - - + + - - + + @@ -171,19 +117,22 @@ + + + if self._logger is not None: + , *args, **kwargs + + + if ((self._logger is not None) and condition): + , *args, condition=True, **kwargs + + @@ -256,16 +212,7 @@ - - - - - - - - - - + @@ -281,31 +228,31 @@ - - - - - - + + - - - - - - + + + + @@ -316,6 +263,14 @@ + + + + @@ -330,6 +285,10 @@ + + @@ -345,7 +304,7 @@ - @@ -359,7 +318,11 @@ + + + + + + + + + + + - - + @@ -403,13 +398,6 @@ - - - - - - - @@ -417,8 +405,15 @@ + + + + + + + - + - + - + - + - + - + - + + + + + + + + + + + + + - + + + - + + + - + - + - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + @@ -779,36 +926,57 @@ + + + - - + + - - - - - - - - - + + + + + + + + + + + +