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Vincent-G-VanVincent-G-Van
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‎64_Bit_One_Time_Pad.srcs/sources_1/new/7seg.v

+38
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1+
module sevenseg(in, s0, s1, s2, s3, s4, s5, s6);
2+
output s0, s1, s2, s3, s4, s5, s6;
3+
input [7:0] in;
4+
reg s0, s1, s2, s3, s4, s5, s6;
5+
always @ (in)
6+
begin
7+
case (in)
8+
7'd00:begin s0=1; s1=1; s2=1; s3=1; s4=1; s5=1; s6=1; end //spacce
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7'd01:begin s0=1; s1=0; s2=0; s3=0; s4=0; s5=0; s6=0; end //A
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7'd02:begin s0=0; s1=0; s2=0; s3=0; s4=1; s5=0; s6=1; end //B
11+
7'd03:begin s0=0; s1=1; s2=0; s3=1; s4=1; s5=0; s6=0; end //C
12+
7'd04:begin s0=0; s1=0; s2=0; s3=0; s4=0; s5=1; s6=1; end //D
13+
7'd05:begin s0=0; s1=1; s2=0; s3=0; s4=1; s5=0; s6=0; end //E
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7'd06:begin s0=1; s1=1; s2=0; s3=0; s4=1; s5=0; s6=0; end //F
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7'd07:begin s0=0; s1=0; s2=1; s3=0; s4=0; s5=0; s6=0; end //G
16+
7'd08:begin s0=1; s1=0; s2=0; s3=0; s4=0; s5=0; s6=1; end //H
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7'd09:begin s0=1; s1=1; s2=0; s3=1; s4=1; s5=0; s6=1; end //I
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7'd10:begin s0=0; s1=0; s2=0; s3=1; s4=0; s5=1; s6=1; end //J
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7'd11:begin s0=1; s1=0; s2=0; s3=0; s4=0; s5=0; s6=1; end //K
20+
7'd12:begin s0=0; s1=1; s2=0; s3=1; s4=1; s5=0; s6=1; end //L
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7'd13:begin s0=1; s1=0; s2=0; s3=1; s4=1; s5=1; s6=0; end //M
22+
7'd14:begin s0=1; s1=0; s2=0; s3=0; s4=1; s5=1; s6=1; end //N
23+
7'd15:begin s0=0; s1=0; s2=0; s3=1; s4=0; s5=0; s6=0; end //O
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7'd16:begin s0=1; s1=1; s2=0; s3=0; s4=0; s5=0; s6=0; end //P
25+
7'd17:begin s0=1; s1=0; s2=1; s3=0; s4=0; s5=0; s6=0; end //Q
26+
7'd18:begin s0=1; s1=1; s2=0; s3=0; s4=1; s5=1; s6=1; end //R
27+
7'd19:begin s0=0; s1=0; s2=1; s3=0; s4=1; s5=0; s6=0; end //S
28+
7'd20:begin s0=0; s1=1; s2=0; s3=0; s4=1; s5=0; s6=1; end //T
29+
7'd21:begin s0=0; s1=0; s2=0; s3=1; s4=0; s5=0; s6=1; end //U
30+
7'd22:begin s0=0; s1=0; s2=0; s3=1; s4=1; s5=1; s6=1; end //V
31+
7'd23:begin s0=0; s1=1; s2=1; s3=1; s4=0; s5=0; s6=1; end //W
32+
7'd24:begin s0=1; s1=0; s2=0; s3=0; s4=0; s5=0; s6=1; end //X
33+
7'd25:begin s0=0; s1=0; s2=1; s3=0; s4=0; s5=0; s6=1; end //Y
34+
7'd26:begin s0=0; s1=1; s2=0; s3=0; s4=0; s5=1; s6=0; end //Z
35+
default: begin s0=1; s1=1; s2=1; s3=1; s4=1; s5=1; s6=1; end
36+
endcase
37+
end
38+
endmodule

‎64_Bit_One_Time_Pad.srcs/sources_1/new/CU.v

+108
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@@ -0,0 +1,108 @@
1+
`timescale 1ns / 1ps
2+
module CU(input rst1, input start, input clk, output reg rst2,
3+
output reg rstreg, output reg ren,
4+
output reg shift, output reg [1:0] sel1, output reg wen,
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output reg [1:0] wa, output reg [1:0] ra1, output reg [1:0] ra2,
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output reg [2:0] sel2, output reg done, output reg [6:0] cs);
7+
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//reg [6:0] cs;
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reg [6:0] ns;
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reg [15:0] ctrl;
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integer loop;
12+
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always@(posedge clk, posedge rst1)
14+
begin
15+
if(rst1==1)
16+
begin
17+
cs=0;
18+
end
19+
else if(start==1)
20+
begin
21+
if(cs==0||cs==4||cs==12)
22+
loop=6;
23+
if(cs==1||cs==5||cs==13)
24+
loop=loop-1;
25+
cs=ns;
26+
end
27+
end
28+
29+
always@(cs, loop)
30+
begin
31+
case(cs)
32+
6'd00:ns=1;
33+
6'd01:
34+
begin
35+
if(loop==0)
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ns=2;
37+
else
38+
ns=1;
39+
end
40+
6'd02:ns=3;
41+
6'd03:ns=4;
42+
6'd04:ns=5;
43+
6'd05:
44+
begin
45+
if(loop==0)
46+
ns=6;
47+
else
48+
ns=5;
49+
end
50+
6'd06:ns=7;
51+
6'd07:ns=8;
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6'd08:ns=9;
53+
6'd09:ns=10;
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6'd10:ns=11;
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6'd11:ns=12;
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6'd12:ns=13;
57+
6'd13:
58+
begin
59+
if(loop==0)
60+
ns=14;
61+
else
62+
ns=13;
63+
end
64+
6'd14:ns=15;
65+
6'd15:ns=16;
66+
6'd16:ns=17;
67+
6'd17:ns=12;
68+
endcase
69+
end
70+
71+
always@(cs)
72+
begin
73+
case(cs)
74+
6'd00:
75+
begin
76+
ctrl=16'b0110000000000001;
77+
done=0;
78+
end
79+
6'd01:ctrl=16'b1001000000000100;
80+
6'd02:ctrl=16'b1000000000000100;
81+
6'd03:ctrl=16'b0000101000000100;
82+
6'd04:ctrl=16'b0010000000000010;
83+
6'd05:ctrl=16'b1001000000000100;
84+
6'd06:ctrl=16'b1000000000000100;
85+
6'd07:ctrl=16'b0000101010001100;
86+
6'd08:ctrl=16'b0000111100001110;
87+
6'd09:ctrl=16'b0000010000010110;
88+
6'd10:ctrl=16'b0000110000010110;
89+
6'd11:ctrl=16'b0000110010010110;
90+
6'd12:
91+
begin
92+
ctrl=16'b0010000000000011;
93+
done=0;
94+
end
95+
6'd13:ctrl=16'b1001000000000100;
96+
6'd14:ctrl=16'b1000000000000100;
97+
6'd15:ctrl=16'b0000101101000100;
98+
6'd16:ctrl=16'b0000111111100110;
99+
6'd17:
100+
begin
101+
ctrl=16'b0000000001100101;
102+
done=1;
103+
end
104+
endcase
105+
{ren, rst2, rstreg, shift, wen, sel1, wa, ra1, ra2, sel2}=ctrl;
106+
end
107+
108+
endmodule

‎64_Bit_One_Time_Pad.srcs/sources_1/new/CU_DP.v

+21
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1+
`timescale 1ns / 1ps
2+
3+
module CU_DP(input [7:0] in, input clk, input rst, input start,
4+
output [63:0] out, output [6:0] cs, output done);
5+
6+
wire ren, shift, wen, rstreg, rst2;
7+
wire [1:0] sel1, wa, ra1, ra2;
8+
wire [2:0] sel2;
9+
10+
CU u0(.rst1(rst), .start(start), .clk(clk), .rst2(rst2), .rstreg(rstreg), .ren(ren),
11+
.shift(shift), .sel1(sel1), .wen(wen),
12+
.wa(wa), .ra1(ra1), .ra2(ra2),
13+
.sel2(sel2), .done(done), .cs(cs));
14+
15+
16+
DP u1(.in(in), .clk(clk), .rst1(rst), .rst2(rst2), .rstreg(rstreg), .ren(ren),
17+
.shift(shift), .sel1(sel1), .wen(wen), .wa(wa),
18+
.ra1(ra1), .ra2(ra2), .sel2(sel2),
19+
.out(out));
20+
21+
endmodule

‎64_Bit_One_Time_Pad.srcs/sources_1/new/CU_DP_TB.v

+54
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1+
`timescale 1ns / 1ps
2+
3+
module CU_DP_TB();
4+
reg [7:0] in;
5+
reg clk, rst, start;
6+
wire done;
7+
wire [63:0] out;
8+
wire[6:0] cs;
9+
10+
CU_DP u0(.in(in), .clk(clk), .rst(rst), .start(start),
11+
.out(out), .cs(cs), .done(done));
12+
initial
13+
begin
14+
rst=1;
15+
#50;
16+
clk=0;
17+
#50;
18+
clk=1;
19+
#50;
20+
clk=0;
21+
#50;
22+
rst=0;
23+
24+
while(done!=1)
25+
begin
26+
start=1;
27+
if(cs==1||cs==2)
28+
in=8'b10101010;
29+
if(cs==5||cs==6||cs==13||cs==14)
30+
in=8'b11111111;
31+
#50;
32+
clk=0;
33+
#50;
34+
clk=1;
35+
#50;
36+
clk=0;
37+
#50;
38+
end
39+
#100;
40+
if(out==64'b1010101010101010101010101010101010101010101010101010101010101010)
41+
begin
42+
$display ("ONE-TIME PAD CU_DP_TB PASSED");
43+
#50 $stop;
44+
#20 $finish;
45+
end
46+
else
47+
begin
48+
$display ("ONE-TIME PAD CU_DP_TB FAIL");
49+
#50 $stop;
50+
#20 $finish;
51+
end
52+
53+
end
54+
endmodule

‎64_Bit_One_Time_Pad.srcs/sources_1/new/CU_DP_machine_fpga.v

+53
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1+
`timescale 1ns / 1ps
2+
module CU_DP_machine_fpga(
3+
input [7:0] A,
4+
input B,
5+
output [7:0] C,
6+
input [4:0] D,
7+
output [4:0] E,
8+
input clk100MHz,
9+
input rst,
10+
output [7:0] LEDOUT,
11+
output [7:0] LEDSEL);
12+
wire [7:0] TOT1, TOT2, TOT3, TOT4, TOT5, TOT6, TOT7, TOT8;
13+
wire debounce;
14+
supply1[7:0] vcc;
15+
16+
wire m0, m1, m2, m3, m4, m5, m6, m7;
17+
wire n0, n1, n2, n3, n4, n5, n6, n7;
18+
wire o0, o1, o2, o3, o4, o5, o6, o7;
19+
wire p0, p1, p2, p3, p4, p5, p6, p7;
20+
wire q0, q1, q2, q3, q4, q5, q6, q7;
21+
wire r0, r1, r2, r3, r4, r5, r6, r7;
22+
wire s0, s1, s2, s3, s4, s5, s6, s7;
23+
wire t0, t1, t2, t3, t4, t5, t6, t7;
24+
25+
wire DONT_USE, clk_5KHz;
26+
27+
clk_gen u1(.clk100MHz(clk100MHz), .rst(rst), .clk_4sec(DONT_USE), .clk_5KHz(clk_5KHz));
28+
29+
button_debouncer u2(clk_5KHz, B, debounce);
30+
31+
CU_DP u3(.in(A), .clk(debounce), .rst(D[3]), .start(D[4]),
32+
.out({TOT1,TOT2,TOT3,TOT4,TOT5,TOT6,TOT7,TOT8}), .cs(cs), .done(done));
33+
34+
assign E=D;
35+
assign C=A;
36+
37+
sevenseg u4(TOT1,m0, m1, m2, m3, m4, m5, m6);
38+
sevenseg u5(TOT2,n0, n1, n2, n3, n4, n5, n6);
39+
sevenseg u6(TOT3,o0, o1, o2, o3, o4, o5, o6);
40+
sevenseg u7(TOT4,p0, p1, p2, p3, p4, p5, p6);
41+
sevenseg u8(TOT5,q0, q1, q2, q3, q4, q5, q6);
42+
sevenseg u9(TOT6,r0, r1, r2, r3, r4, r5, r6);
43+
sevenseg u10(TOT7,s0, s1, s2, s3, s4, s5, s6);
44+
sevenseg u11(TOT8,t0, t1, t2, t3, t4, t5, t6);
45+
46+
led_mux u12(clk_5KHz, rst, {m7, m6, m5, m4, m3, m2, m1, m0},
47+
{n7, n6, n5, n4, n3, n2, n1, n0}, {o7, o6, o5, o4, o3, o2, o1, o0},
48+
{p7, p6, p5, p4, p3, p2, p1, p0}, {q7, q6, q5, q4, q3, q2, q1, q0},
49+
{r7, r6, r5, r4, r3, r2, r1, r0}, {s7, s6, s5, s4, s3, s2, s1, s0},
50+
{t7, t6, t5, t4, t3, t2, t1, t0},LEDOUT, LEDSEL);
51+
52+
endmodule
53+

‎64_Bit_One_Time_Pad.srcs/sources_1/new/CU_DP_machine_fpga.xdc

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1+
########################################################
2+
# Design Constraint File #
3+
# FILE NAME: CU_DP_machine_fpga.xdc #
4+
########################################################
5+
set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { A[0] }];
6+
set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { A[1] }];
7+
set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { A[2] }];
8+
set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { A[3] }];
9+
set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { A[4] }];
10+
set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { A[5] }];
11+
set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { A[6] }];
12+
set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { A[7] }];
13+
14+
set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { B }];
15+
16+
set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { C[0] }];
17+
set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { C[1] }];
18+
set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { C[2] }];
19+
set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { C[3] }];
20+
set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { C[4] }];
21+
set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { C[5] }];
22+
set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { C[6] }];
23+
set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { C[7] }];
24+
25+
set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk100MHz }];
26+
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk100MHz}];
27+
set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { LEDOUT[0] }];
28+
set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { LEDOUT[1] }];
29+
set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { LEDOUT[2] }];
30+
set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { LEDOUT[3] }];
31+
set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { LEDOUT[4] }];
32+
set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { LEDOUT[5] }];
33+
set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { LEDOUT[6] }];
34+
set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { LEDOUT[7] }];
35+
set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { LEDSEL[0] }];
36+
set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { LEDSEL[1] }];
37+
set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { LEDSEL[2] }];
38+
set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { LEDSEL[3] }];
39+
set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { LEDSEL[4] }];
40+
set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { LEDSEL[5] }];
41+
set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { LEDSEL[6] }];
42+
set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { LEDSEL[7] }];
43+
set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { rst }];
44+
45+
set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { D[4] }];
46+
set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { D[3] }];
47+
set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { D[2] }];
48+
set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { D[1] }];
49+
set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { D[0] }];
50+
51+
set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { E[4] }];
52+
set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { E[3] }];
53+
set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { E[2] }];
54+
set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { E[1] }];
55+
set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { E[0] }];

‎64_Bit_One_Time_Pad.srcs/sources_1/new/DP.v

+36
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@@ -0,0 +1,36 @@
1+
`timescale 1ns / 1ps
2+
3+
module DP(input [7:0] in, input clk, input rst1, input rst2,
4+
input rstreg, input ren,
5+
input shift, input [1:0] sel1, input wen, input [1:0] wa,
6+
input [1:0] ra1, input [1:0] ra2, input [2:0] sel2,
7+
output [63:0] out);
8+
9+
wire [63:0] shiftout;
10+
wire [63:0] ro1;
11+
wire [63:0] ro2;
12+
wire [63:0] xorout;
13+
wire [63:0] mux1out;
14+
15+
shift8reg u0(.in(in), .en(ren), .rst1(rst1), .rst2(rst2),
16+
.rst3(rstreg), .clk(clk), .shiftL8(shift), .out(shiftout));
17+
18+
mux1 u1(.sel(sel1), .in0(64'b0000000000000000000000000000000000000000000000000000000000000000),
19+
.in1(shiftout), .in2(ro2), .in3(xorout),
20+
.out(mux1out));
21+
22+
regfile u2(.in(mux1out), .wen(wen), .wa(wa),
23+
.ra1(ra1), .ra2(ra2), .rst(rst1), .clk(clk),
24+
.ro1(ro1), .ro2(ro2));
25+
26+
mux2 u3(.sel(sel2), .in0(64'b0000000000000000000000000000000000000000000000000000000000000000),
27+
.in1({64'b0000100100001110000100000001010100010100000011010001001100000111}),
28+
.in2({64'b0001000000010101000101000000000000010000000000010001001100010011}),
29+
.in3({64'b0001000000010101000101000000000000010100000100100001100100000000}),
30+
.in4(shiftout), .in5(ro1),
31+
.in6({64'b0001011100000001000010010001010000000000000000000000000000000000}), .out(out));
32+
33+
XOR u4(.in1(ro1), .in2(ro2),
34+
.out(xorout));
35+
36+
endmodule

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