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Regression: Batch update PFM, BSP and CommonImages to 2024.2
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‎AI_Engine_Development/AIE-ML/Design_Tutorials/01-AIE-ML-programming-and-optimization/Makefile

+5-5
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,7 @@ OPT ?= 0
2222
# hw_emu|hw
2323

2424
TARGET ?= hw_emu
25-
PFM_NAME := xilinx_vek280_base_202410_1
25+
PFM_NAME := xilinx_vek280_base_202420_1
2626
PFM_NAME := $(strip $(PFM_NAME))
2727
PLATFORM := ${PLATFORM_REPO_PATHS}/${PFM_NAME}/${PFM_NAME}.xpfm
2828
PNAME := aieml_pl_${TARGET}
@@ -96,16 +96,16 @@ guard-PLATFORM_REPO_PATHS:
9696
$(call check_defined, PLATFORM_REPO_PATHS, Set your where you downloaded your platform)
9797

9898
guard-ROOTFS:
99-
$(call check_defined, ROOTFS, Set to: xilinx-versal-common-v2024.1/rootfs.ext4)
99+
$(call check_defined, ROOTFS, Set to: xilinx-versal-common-v2024.2/rootfs.ext4)
100100

101101
guard-IMAGE:
102-
$(call check_defined, IMAGE, Set to: xilinx-versal-common-v2024.1/Image)
102+
$(call check_defined, IMAGE, Set to: xilinx-versal-common-v2024.2/Image)
103103

104104
guard-CXX:
105-
$(call check_defined, CXX, Run: xilinx-versal-common-v2024.1/environment-setup-cortexa72-cortexa53-xilinx-linux)
105+
$(call check_defined, CXX, Run: xilinx-versal-common-v2024.2/environment-setup-cortexa72-cortexa53-xilinx-linux)
106106

107107
guard-SDKTARGETSYSROOT:
108-
$(call check_defined, SDKTARGETSYSROOT, Run: xilinx-versal-common-v2024.1/environment-setup-cortexa72-cortexa53-xilinx-linux)
108+
$(call check_defined, SDKTARGETSYSROOT, Run: xilinx-versal-common-v2024.2/environment-setup-cortexa72-cortexa53-xilinx-linux)
109109

110110
###
111111
.PHONY: all_hw all_hw_emu run upd_host_hw aie postaie data aiesim aieviz aiesim-fifo compareaie x86 x86sim comparex86

‎AI_Engine_Development/AIE-ML/Design_Tutorials/02-Prime-Factor-FFT/Makefile

+2-2
Original file line numberDiff line numberDiff line change
@@ -7,9 +7,9 @@
77
ECHO = @echo
88
export TARGET ?= hw_emu
99

10-
RELEASE=2024.1
10+
RELEASE=2024.2
1111
BOARD=vek280
12-
BASE_NUM=202410_1
12+
BASE_NUM=202420_1
1313

1414
# Platform Selection...
1515
VERSAL_VITIS_PLATFORM = xilinx_${BOARD}\_base_${BASE_NUM}

‎AI_Engine_Development/AIE-ML/Design_Tutorials/02-Prime-Factor-FFT/aie/dft16/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@ MY_APP := dft16_app
1010
MY_SOURCES := ${MY_APP}.cpp dft16_graph.h dft16_mmul0.h dft16_mmul0.cpp dft16_mmul1.h dft16_mmul1.cpp \
1111
dft16_twiddle.h
1212

13-
PLATFORM_USE := xilinx_vek280_base_202410_1
13+
PLATFORM_USE := xilinx_vek280_base_202420_1
1414
PLATFORM := ${PLATFORM_REPO_PATHS}/${PLATFORM_USE}/${PLATFORM_USE}.xpfm
1515

1616
CHECK_FIFO := --aie.evaluate-fifo-depth --aie.Xrouter=disablePathBalancing

‎AI_Engine_Development/AIE-ML/Design_Tutorials/02-Prime-Factor-FFT/aie/dft7/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@ MY_APP := dft7_app
1010
MY_SOURCES := ${MY_APP}.cpp dft7_graph.h dft7_mmul0.h dft7_mmul0.cpp dft7_mmul1.h dft7_mmul1.cpp \
1111
dft7_twiddle.h
1212

13-
PLATFORM_USE := xilinx_vek280_base_202410_1
13+
PLATFORM_USE := xilinx_vek280_base_202420_1
1414
PLATFORM := ${PLATFORM_REPO_PATHS}/${PLATFORM_USE}/${PLATFORM_USE}.xpfm
1515

1616
CHECK_FIFO := --aie.evaluate-fifo-depth --aie.Xrouter=disablePathBalancing

‎AI_Engine_Development/AIE-ML/Design_Tutorials/02-Prime-Factor-FFT/aie/dft9/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@ MY_APP := dft9_app
1010
MY_SOURCES := ${MY_APP}.cpp dft9_graph.h dft9_mmul0.h dft9_mmul1.h dft9_mmul0.cpp dft9_mmul1.cpp \
1111
dft9_mmul3.h dft9_mmul3.cpp dft9_twiddle.h
1212

13-
PLATFORM_USE := xilinx_vek280_base_202410_1
13+
PLATFORM_USE := xilinx_vek280_base_202420_1
1414
PLATFORM := ${PLATFORM_REPO_PATHS}/${PLATFORM_USE}/${PLATFORM_USE}.xpfm
1515

1616
CHECK_FIFO := --aie.evaluate-fifo-depth --aie.Xrouter=disablePathBalancing

‎AI_Engine_Development/AIE-ML/Design_Tutorials/02-Prime-Factor-FFT/aie/permute_i/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@ SIM_FIFO := false
99
MY_APP := permute_i_app
1010
MY_SOURCES := ${MY_APP}.cpp permute_i_graph.h permute_i_bd.h
1111

12-
PLATFORM_USE := xilinx_vek280_base_202410_1
12+
PLATFORM_USE := xilinx_vek280_base_202420_1
1313
PLATFORM := ${PLATFORM_REPO_PATHS}/${PLATFORM_USE}/${PLATFORM_USE}.xpfm
1414

1515
CHECK_FIFO := --aie.evaluate-fifo-depth --aie.Xrouter=disablePathBalancing

‎AI_Engine_Development/AIE-ML/Design_Tutorials/02-Prime-Factor-FFT/aie/pfa1008/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -25,7 +25,7 @@ MY_SOURCES := ${MY_APP}.cpp pfa1008_graph.h ${DFT7_SOURCE:%=../dft7/%} ${
2525
${DFT16_SOURCE:%=../dft16/%} \
2626
${TRANSPOSE0_SOURCE:%=../transpose0/%} ${TRANSPOSE1_SOURCE:%=../transpose1/%}
2727

28-
PLATFORM_USE := xilinx_vek280_base_202410_1
28+
PLATFORM_USE := xilinx_vek280_base_202420_1
2929
PLATFORM := ${PLATFORM_REPO_PATHS}/${PLATFORM_USE}/${PLATFORM_USE}.xpfm
3030

3131
CHECK_FIFO := --aie.evaluate-fifo-depth --aie.Xrouter=disablePathBalancing

‎AI_Engine_Development/AIE-ML/Design_Tutorials/02-Prime-Factor-FFT/aie/transpose0/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@ SIM_FIFO := false
99
MY_APP := transpose0_app
1010
MY_SOURCES := ${MY_APP}.cpp transpose0_graph.h
1111

12-
PLATFORM_USE := xilinx_vek280_base_202410_1
12+
PLATFORM_USE := xilinx_vek280_base_202420_1
1313
PLATFORM := ${PLATFORM_REPO_PATHS}/${PLATFORM_USE}/${PLATFORM_USE}.xpfm
1414

1515
CHECK_FIFO := --aie.evaluate-fifo-depth --aie.Xrouter=disablePathBalancing

‎AI_Engine_Development/AIE-ML/Design_Tutorials/02-Prime-Factor-FFT/aie/transpose1/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@ SIM_FIFO := false
99
MY_APP := transpose1_app
1010
MY_SOURCES := ${MY_APP}.cpp transpose1_graph.h
1111

12-
PLATFORM_USE := xilinx_vek280_base_202410_1
12+
PLATFORM_USE := xilinx_vek280_base_202420_1
1313
PLATFORM := ${PLATFORM_REPO_PATHS}/${PLATFORM_USE}/${PLATFORM_USE}.xpfm
1414

1515
CHECK_FIFO := --aie.evaluate-fifo-depth --aie.Xrouter=disablePathBalancing

‎AI_Engine_Development/AIE-ML/Design_Tutorials/03-AIE-ML-lenet_tutorial/sample_env_setup.sh

+4-4
Original file line numberDiff line numberDiff line change
@@ -6,9 +6,9 @@
66
# =======================================================
77
# Set Platform ,Vitis and Versal Image repo
88
# =======================================================
9-
export PLATFORM_REPO_PATHS= <YOUR-2024.1-PLATFORM-DIRECTORY>
10-
export XILINX_VITIS = <YOUR-2024.1-VITIS-DIRECTORY>/2024.1
11-
export COMMON_IMAGE_VERSAL=<YOUR-XILINX-VERSAL-common-v2024.1-DIRECTORY>
9+
export PLATFORM_REPO_PATHS= <YOUR-2024.2-PLATFORM-DIRECTORY>
10+
export XILINX_VITIS = <YOUR-2024.2-VITIS-DIRECTORY>/2024.2
11+
export COMMON_IMAGE_VERSAL=<YOUR-XILINX-VERSAL-common-v2024.2-DIRECTORY>
1212

1313
# ====================================================
1414
# Source Versal Image ,Vitis and Aietools
@@ -20,7 +20,7 @@ source $XILINX_VITIS/settings64.sh
2020
# =========================================================
2121
# Platform Selection...
2222
# =========================================================
23-
tgt_plat=xilinx_vek280_base_202410_1
23+
tgt_plat=xilinx_vek280_base_202420_1
2424
export PLATFORM=$PLATFORM_REPO_PATHS/$tgt_plat/$tgt_plat\.xpfm
2525

2626
# ==========================================================

‎AI_Engine_Development/AIE-ML/Design_Tutorials/04-AIE-API-based-FFT-for-many-instances-applications/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@ ECHO = @echo
88
################################################################################
99
# Variables needed for AMD tools version checking, PLEASE DO NOT MODIFY #
1010
################################################################################
11-
REQUIRED_VERSION = 2024.1
11+
REQUIRED_VERSION = 2024.2
1212
VITIS_VERSION := $(shell vitis -version 2>/dev/null | grep "Vitis " | sed 's/\*//g')
1313

1414
##############

‎AI_Engine_Development/AIE-ML/Design_Tutorials/04-AIE-API-based-FFT-for-many-instances-applications/Step1_3Dbuf.py

+1-1
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@
99

1010
# Current directory and various path variables
1111
cwd = os.getcwd()+'/'
12-
vek280_base = os.environ.get('PLATFORM_REPO_PATHS') + '/xilinx_vek280_base_202410_1/xilinx_vek280_base_202410_1.xpfm'
12+
vek280_base = os.environ.get('PLATFORM_REPO_PATHS') + '/xilinx_vek280_base_202420_1/xilinx_vek280_base_202420_1.xpfm'
1313
my_workspace = cwd + 'AIEML_API_FFT_Tutorial'
1414
sources = cwd + 'src/'
1515

‎AI_Engine_Development/AIE-ML/Design_Tutorials/04-AIE-API-based-FFT-for-many-instances-applications/Step2_4Dbuf.py

+1-1
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@
99

1010
# Current directory and various path variables
1111
cwd = os.getcwd()+'/'
12-
vek280_base = os.environ.get('PLATFORM_REPO_PATHS') + '/xilinx_vek280_base_202410_1/xilinx_vek280_base_202410_1.xpfm'
12+
vek280_base = os.environ.get('PLATFORM_REPO_PATHS') + '/xilinx_vek280_base_202420_1/xilinx_vek280_base_202420_1.xpfm'
1313
my_workspace = cwd + 'AIEML_API_FFT_Tutorial'
1414
sources = cwd + 'src/'
1515

‎AI_Engine_Development/AIE-ML/Feature_Tutorials/05-AI-engine-versal-integration/Makefile

+8-8
Original file line numberDiff line numberDiff line change
@@ -5,8 +5,8 @@
55

66
F_PROJ_ROOT ?= $(shell bash -c 'export MK_PATH=$(MK_PATH); echo $${MK_PATH%/AI_Engine_Development/*}')
77

8-
ROOTFS ?= ${PLATFORM_REPO_PATHS}/sw/versal/xilinx-versal-common-v2024.1/rootfs.ext4
9-
IMAGE ?= ${PLATFORM_REPO_PATHS}/sw/versal/xilinx-versal-common-v2024.1/Image
8+
ROOTFS ?= ${PLATFORM_REPO_PATHS}/sw/versal/xilinx-versal-common-v2024.2/rootfs.ext4
9+
IMAGE ?= ${PLATFORM_REPO_PATHS}/sw/versal/xilinx-versal-common-v2024.2/Image
1010
SDKTARGETSYSROOT ?= ${SYSROOT}
1111

1212
# Makefile input options
@@ -34,7 +34,7 @@ else
3434
endif
3535
PACKAGE_OUT = ./package.$(TARGET)
3636

37-
BASE_PLATFORM ?= ${PLATFORM_REPO_PATHS}/xilinx_vek280_base_202410_1/xilinx_vek280_base_202410_1.xpfm
37+
BASE_PLATFORM ?= ${PLATFORM_REPO_PATHS}/xilinx_vek280_base_202420_1/xilinx_vek280_base_202420_1.xpfm
3838

3939
# Command-line options
4040
VPP := v++
@@ -97,19 +97,19 @@ __check_defined = \
9797
$(error Undefined $1$(if $2, ($2))))
9898

9999
guard-PLATFORM_REPO_PATHS:
100-
$(call check_defined, PLATFORM_REPO_PATHS, Set your where you downloaded xilinx_vek280_base_202410_1)
100+
$(call check_defined, PLATFORM_REPO_PATHS, Set your where you downloaded xilinx_vek280_base_202420_1)
101101

102102
guard-ROOTFS:
103-
$(call check_defined, ROOTFS, Set to: xilinx-versal-common-v2024.1/rootfs.ext4)
103+
$(call check_defined, ROOTFS, Set to: xilinx-versal-common-v2024.2/rootfs.ext4)
104104

105105
guard-IMAGE:
106-
$(call check_defined, IMAGE, Set to: xilinx-versal-common-v2024.1/Image)
106+
$(call check_defined, IMAGE, Set to: xilinx-versal-common-v2024.2/Image)
107107

108108
guard-CXX:
109-
$(call check_defined, CXX, Run: xilinx-versal-common-v2024.1/environment-setup-aarch64-xilinx-linux)
109+
$(call check_defined, CXX, Run: xilinx-versal-common-v2024.2/environment-setup-aarch64-xilinx-linux)
110110

111111
guard-SDKTARGETSYSROOT:
112-
$(call check_defined, SDKTARGETSYSROOT, Run: xilinx-versal-common-v2024.1/environment-setup-aarch64-xilinx-linux)
112+
$(call check_defined, SDKTARGETSYSROOT, Run: xilinx-versal-common-v2024.2/environment-setup-aarch64-xilinx-linux)
113113

114114
###
115115

‎AI_Engine_Development/AIE-ML/Feature_Tutorials/13-aie-ml-performance-analysis/normalization_v1/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33
#SPDX-License-Identifier: MIT
44

55
TARGET = hw
6-
PLATFORM = ${PLATFORM_REPO_PATHS}/xilinx_vek280_base_202410_1/xilinx_vek280_base_202410_1.xpfm
6+
PLATFORM = ${PLATFORM_REPO_PATHS}/xilinx_vek280_base_202420_1/xilinx_vek280_base_202420_1.xpfm
77
XSA = vek280_aie_base_graph_${TARGET}.xsa
88
HOST_EXE = host.exe
99

‎AI_Engine_Development/AIE-ML/Feature_Tutorials/13-aie-ml-performance-analysis/normalization_v1/pl_kernels/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
#Copyright (C) 2023, Advanced Micro Devices, Inc. All rights reserved.
33
#SPDX-License-Identifier: MIT
44

5-
PLATFORM = ${PLATFORM_REPO_PATHS}/xilinx_vek280_base_202410_1/xilinx_vek280_base_202410_1.xpfm
5+
PLATFORM = ${PLATFORM_REPO_PATHS}/xilinx_vek280_base_202420_1/xilinx_vek280_base_202420_1.xpfm
66

77
.PHONY: clean
88

‎AI_Engine_Development/AIE-ML/Feature_Tutorials/13-aie-ml-performance-analysis/normalization_v1/sw/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@ HOST_EXE = ../host.exe
66
HOST_INC = -I../ -I../aie
77
HOST_OBJ = host.o
88
AIE_CTRL_CPP = ../Work/ps/c_rts/aie_control_xrt.cpp
9-
SYSROOT = ${PLATFORM_REPO_PATHS}/sw/versal/xilinx-versal-common-v2024.1/sysroots/aarch64-xilinx-linux/
9+
SYSROOT = ${PLATFORM_REPO_PATHS}/sw/versal/xilinx-versal-common-v2024.2/sysroots/aarch64-xilinx-linux/
1010

1111
CXXFLAGS += -std=c++17 -I$(XILINX_HLS)/include/ -I${SYSROOT}/usr/include/xrt/ -g -Wall -c -fmessage-length=0 --sysroot=${SYSROOT} -I${XILINX_VITIS}/aietools/include ${HOST_INC}
1212

‎AI_Engine_Development/AIE-ML/Feature_Tutorials/13-aie-ml-performance-analysis/normalization_v2/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33
#SPDX-License-Identifier: MIT
44

55
TARGET = hw
6-
PLATFORM = ${PLATFORM_REPO_PATHS}/xilinx_vek280_base_202410_1/xilinx_vek280_base_202410_1.xpfm
6+
PLATFORM = ${PLATFORM_REPO_PATHS}/xilinx_vek280_base_202420_1/xilinx_vek280_base_202420_1.xpfm
77
XSA = vek280_aie_base_graph_${TARGET}.xsa
88
HOST_EXE = host.exe
99

‎AI_Engine_Development/AIE-ML/Feature_Tutorials/13-aie-ml-performance-analysis/normalization_v2/pl_kernels/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
#Copyright (C) 2023, Advanced Micro Devices, Inc. All rights reserved.
33
#SPDX-License-Identifier: MIT
44

5-
PLATFORM = ${PLATFORM_REPO_PATHS}/xilinx_vek280_base_202410_1/xilinx_vek280_base_202410_1.xpfm
5+
PLATFORM = ${PLATFORM_REPO_PATHS}/xilinx_vek280_base_202420_1/xilinx_vek280_base_202420_1.xpfm
66

77
.PHONY: clean
88

‎AI_Engine_Development/AIE-ML/Feature_Tutorials/13-aie-ml-performance-analysis/normalization_v2/sw/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@ HOST_EXE = ../host.exe
66
HOST_INC = -I../ -I../aie
77
HOST_OBJ = host.o
88
AIE_CTRL_CPP = ../Work/ps/c_rts/aie_control_xrt.cpp
9-
SYSROOT = ${PLATFORM_REPO_PATHS}/sw/versal/xilinx-versal-common-v2024.1/sysroots/aarch64-xilinx-linux/
9+
SYSROOT = ${PLATFORM_REPO_PATHS}/sw/versal/xilinx-versal-common-v2024.2/sysroots/aarch64-xilinx-linux/
1010

1111
CXXFLAGS += -std=c++17 -I$(XILINX_HLS)/include/ -I${SYSROOT}/usr/include/xrt/ -g -Wall -c -fmessage-length=0 --sysroot=${SYSROOT} -I${XILINX_VITIS}/aietools/include ${HOST_INC}
1212

‎AI_Engine_Development/AIE-ML/Feature_Tutorials/13-aie-ml-performance-analysis/normalization_v3/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33
#SPDX-License-Identifier: MIT
44

55
TARGET = hw
6-
PLATFORM = ${PLATFORM_REPO_PATHS}/xilinx_vek280_base_202410_1/xilinx_vek280_base_202410_1.xpfm
6+
PLATFORM = ${PLATFORM_REPO_PATHS}/xilinx_vek280_base_202420_1/xilinx_vek280_base_202420_1.xpfm
77
XSA = vek280_aie_base_graph_${TARGET}.xsa
88
HOST_EXE = host.exe
99

‎AI_Engine_Development/AIE-ML/Feature_Tutorials/13-aie-ml-performance-analysis/normalization_v3/pl_kernels/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
#Copyright (C) 2023, Advanced Micro Devices, Inc. All rights reserved.
33
#SPDX-License-Identifier: MIT
44

5-
PLATFORM = ${PLATFORM_REPO_PATHS}/xilinx_vek280_base_202410_1/xilinx_vek280_base_202410_1.xpfm
5+
PLATFORM = ${PLATFORM_REPO_PATHS}/xilinx_vek280_base_202420_1/xilinx_vek280_base_202420_1.xpfm
66

77
.PHONY: clean
88

‎AI_Engine_Development/AIE-ML/Feature_Tutorials/13-aie-ml-performance-analysis/normalization_v3/sw/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@ HOST_EXE = ../host.exe
66
HOST_INC = -I../ -I../aie
77
HOST_OBJ = host.o
88
AIE_CTRL_CPP = ../Work/ps/c_rts/aie_control_xrt.cpp
9-
SYSROOT = ${PLATFORM_REPO_PATHS}/sw/versal/xilinx-versal-common-v2024.1/sysroots/aarch64-xilinx-linux/
9+
SYSROOT = ${PLATFORM_REPO_PATHS}/sw/versal/xilinx-versal-common-v2024.2/sysroots/aarch64-xilinx-linux/
1010

1111
CXXFLAGS += -std=c++17 -I$(XILINX_HLS)/include/ -I${SYSROOT}/usr/include/xrt/ -g -Wall -c -fmessage-length=0 --sysroot=${SYSROOT} -I${XILINX_VITIS}/aietools/include ${HOST_INC}
1212

‎AI_Engine_Development/AIE-ML/Feature_Tutorials/13-aie-ml-performance-analysis/normalization_v4/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33
#SPDX-License-Identifier: MIT
44

55
TARGET = hw
6-
PLATFORM = ${PLATFORM_REPO_PATHS}/xilinx_vek280_base_202410_1/xilinx_vek280_base_202410_1.xpfm
6+
PLATFORM = ${PLATFORM_REPO_PATHS}/xilinx_vek280_base_202420_1/xilinx_vek280_base_202420_1.xpfm
77
XSA = vek280_aie_base_graph_${TARGET}.xsa
88
HOST_EXE = host.exe
99

‎AI_Engine_Development/AIE-ML/Feature_Tutorials/13-aie-ml-performance-analysis/normalization_v4/pl_kernels/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
#Copyright (C) 2023, Advanced Micro Devices, Inc. All rights reserved.
33
#SPDX-License-Identifier: MIT
44

5-
PLATFORM = ${PLATFORM_REPO_PATHS}/xilinx_vek280_base_202410_1/xilinx_vek280_base_202410_1.xpfm
5+
PLATFORM = ${PLATFORM_REPO_PATHS}/xilinx_vek280_base_202420_1/xilinx_vek280_base_202420_1.xpfm
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.PHONY: clean
88

‎AI_Engine_Development/AIE-ML/Feature_Tutorials/13-aie-ml-performance-analysis/normalization_v4/sw/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@ HOST_EXE = ../host.exe
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HOST_INC = -I../ -I../aie
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HOST_OBJ = host.o
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AIE_CTRL_CPP = ../Work/ps/c_rts/aie_control_xrt.cpp
9-
SYSROOT = ${PLATFORM_REPO_PATHS}/sw/versal/xilinx-versal-common-v2024.1/sysroots/aarch64-xilinx-linux/
9+
SYSROOT = ${PLATFORM_REPO_PATHS}/sw/versal/xilinx-versal-common-v2024.2/sysroots/aarch64-xilinx-linux/
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1111
CXXFLAGS += -std=c++17 -I$(XILINX_HLS)/include/ -I${SYSROOT}/usr/include/xrt/ -g -Wall -c -fmessage-length=0 --sysroot=${SYSROOT} -I${XILINX_VITIS}/aietools/include ${HOST_INC}
1212

‎AI_Engine_Development/AIE/Design_Tutorials/01-aie_lenet_tutorial/sample_env_setup.sh

+4-4
Original file line numberDiff line numberDiff line change
@@ -6,9 +6,9 @@
66
# =======================================================
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# Set Platform ,Vitis and Versal Image repo
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# =======================================================
9-
export PLATFORM_REPO_PATHS= <YOUR-2024.1-PLATFORM-DIRECTORY>
10-
export XILINX_VITIS = <YOUR-2024.1-VITIS-DIRECTORY>/2024.1
11-
export COMMON_IMAGE_VERSAL=<YOUR-XILINX-VERSAL-common-v2024.1-DIRECTORY>
9+
export PLATFORM_REPO_PATHS= <YOUR-2024.2-PLATFORM-DIRECTORY>
10+
export XILINX_VITIS = <YOUR-2024.2-VITIS-DIRECTORY>/2024.2
11+
export COMMON_IMAGE_VERSAL=<YOUR-XILINX-VERSAL-common-v2024.2-DIRECTORY>
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# ====================================================
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# Source Versal Image ,Vitis and Aietools
@@ -20,7 +20,7 @@ source $XILINX_VITIS/settings64.sh
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# =========================================================
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# Platform Selection...
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# =========================================================
23-
tgt_plat=xilinx_vck190_base_202410_1
23+
tgt_plat=xilinx_vck190_base_202420_1
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export PLATFORM=$PLATFORM_REPO_PATHS/$tgt_plat/$tgt_plat\.xpfm
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# ==========================================================

‎AI_Engine_Development/AIE/Design_Tutorials/02-super_sampling_rate_fir/DualStreamSSR/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33
# SPDX-License-Identifier: MIT
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#
55

6-
PFM_NAME ?=xilinx_vck190_base_202410_1
6+
PFM_NAME ?=xilinx_vck190_base_202420_1
77

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all:
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make data

‎AI_Engine_Development/AIE/Design_Tutorials/02-super_sampling_rate_fir/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@
66
.PHONY: run
77

88

9-
PFM_NAME := xilinx_vck190_base_202410_1
9+
PFM_NAME := xilinx_vck190_base_202420_1
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run:
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make -C SingleKernel PFM_NAME=$(PFM_NAME) run

‎AI_Engine_Development/AIE/Design_Tutorials/02-super_sampling_rate_fir/MultiKernel/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33
# SPDX-License-Identifier: MIT
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#
55

6-
PFM_NAME ?= xilinx_vck190_base_202410_1
6+
PFM_NAME ?= xilinx_vck190_base_202420_1
77

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all:
99
make data

‎AI_Engine_Development/AIE/Design_Tutorials/02-super_sampling_rate_fir/SingleKernel/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55

66

77

8-
PFM_NAME ?= xilinx_vck190_base_202410_1
8+
PFM_NAME ?= xilinx_vck190_base_202420_1
99

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all:
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make data

‎AI_Engine_Development/AIE/Design_Tutorials/02-super_sampling_rate_fir/SingleStreamSSR/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
#
55

66

7-
PFM_NAME ?= xilinx_vck190_base_202410_1
7+
PFM_NAME ?= xilinx_vck190_base_202420_1
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99
all:
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make data

‎AI_Engine_Development/AIE/Design_Tutorials/03-beamforming/Module_01_Custom_Platform/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55

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MK_PATH := $(abspath $(lastword $(MAKEFILE_LIST)))
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XF_PROJ_ROOT ?= $(shell bash -c 'export MK_PATH=$(MK_PATH); echo $${MK_PATH%/AI_Engine_Development/*}')
8-
PLATFORM ?= xilinx_vck190_base_202410_1
8+
PLATFORM ?= xilinx_vck190_base_202420_1
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1010
DEVICE_NAME := xcvc1902-vsva2197-2MP-e-S
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‎AI_Engine_Development/AIE/Design_Tutorials/03-beamforming/Module_01_Custom_Platform/sw/src/a72/xrt/image/platform_desc.txt

+1-1
Original file line numberDiff line numberDiff line change
@@ -1 +1 @@
1-
xilinx_vck190_base_202410_1
1+
xilinx_vck190_base_202420_1

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