ARMv8 32bit: error in function Xil_DCacheInvalidateRange()

[vsrb]

There is an error in the function Xil_DCacheInvalidateRange() for ARMv8 32bit:

Only the first cache line will actually be invalid, because the adr variable is incremented, but the tempadr variable is used.

while (adr < (INTPTR)end) {
    /* Select cache level 0 and D cache in CSSR */
    mtcp(XREG_CP15_CACHE_SIZE_SEL, 0x0);
    /* Invalidate Data cache line */
    mtcp(XREG_CP15_INVAL_DC_LINE_MVA_POC, (tempadr & (~0x3F)));  // <<--- Using
    /* Wait for invalidate to complete */
    dsb();
    /* Select cache level 0 and D cache in CSSR */
    mtcp(XREG_CP15_CACHE_SIZE_SEL, 0x2);
    mtcp(XREG_CP15_INVAL_DC_LINE_MVA_POC, (tempadr & (~0x3F)));  // <<--- Using
    /* Wait for invalidate to complete */
    dsb();
    ((MAX_ADDR - (u32)adr) < cacheline) ? (adr = MAX_ADDR) : (adr += cacheline);  // <<--- Increment
}

embeddedsw/blob/master/lib/bsp/standalone/src/arm/ARMv8/32bit/xil_cache.c

[anirudha1977]

Thanks for pointing this. We will fix this in our next release.