Merge pull request #1373 from Xilinx/fix/dyn_mvau_swidth

Update dynamic MVAU stream width

Author: auphelia

src/finn/custom_op/fpgadataflow/hls/matrixvectoractivation_hls.py

@@ -267,6 +267,8 @@ def read_npy_data(self):
             wdt = self.get_input_datatype(1)
             elem_bits = wdt.bitwidth()
             packed_bits = self.get_instream_width(1)
+            if self.get_nodeattr("dynamic_input"):
+                packed_bits = packed_bits * self.get_nodeattr("SIMD")
             packed_hls_type = "ap_uint<%d>" % packed_bits
             elem_hls_type = wdt.get_hls_datatype_str()
             npy_type = "float"
@@ -294,8 +296,11 @@ def strm_decl(self):
         )
 
         if mem_mode == "internal_decoupled" or mem_mode == "external":
+            iwidth = self.get_instream_width(1)
+            if self.get_nodeattr("dynamic_input"):
+                iwidth = iwidth * self.get_nodeattr("SIMD")
             self.code_gen_dict["$STREAMDECLARATIONS$"].append(
-                'hls::stream<ap_uint<{}>> in1_V ("in1_V");'.format(self.get_instream_width(1))
+                'hls::stream<ap_uint<{}>> in1_V ("in1_V");'.format(iwidth)
             )
 
     def docompute(self):
@@ -391,6 +396,9 @@ def blackboxfunction(self):
                 )
             ]
         elif mem_mode == "internal_decoupled" or mem_mode == "external":
+            wwidth = self.get_instream_width(1)
+            if self.get_nodeattr("dynamic_input"):
+                wwidth = wwidth * self.get_nodeattr("SIMD")
             self.code_gen_dict["$BLACKBOXFUNCTION$"] = [
                 """void {}(
                     hls::stream<ap_uint<{}>> &in0_V,
@@ -399,7 +407,7 @@ def blackboxfunction(self):
                     )""".format(
                     self.onnx_node.name,
                     self.get_instream_width(0),
-                    self.get_instream_width(1),
+                    wwidth,
                     self.get_outstream_width(),
                 )
             ]
@@ -464,9 +472,11 @@ def get_ap_int_max_w(self):
         max_of_io = super().get_ap_int_max_w()
         # internal_decoupled mode weight stream
         weightstream = self.get_instream_width(1)
+        simd = self.get_nodeattr("SIMD")
+        if self.get_nodeattr("dynamic_input"):
+            weightstream = weightstream * simd
         # single PE weight entry
         weight_bits = self.get_input_datatype(1).bitwidth()
-        simd = self.get_nodeattr("SIMD")
         single_pe_w = simd * weight_bits
         return max([weightstream, max_of_io, single_pe_w])
 
@@ -543,6 +553,8 @@ def execute_node(self, context, graph):
 
             if dynamic_input or mem_mode in ["external", "internal_decoupled"]:
                 wnbits = self.get_instream_width(1)
+                if self.get_nodeattr("dynamic_input"):
+                    wnbits = wnbits * self.get_nodeattr("SIMD")
                 export_wdt = self.get_input_datatype(1)
 
                 # we have converted bipolar weights to binary for export,

src/finn/custom_op/fpgadataflow/matrixvectoractivation.py

@@ -266,7 +266,11 @@ def get_instream_width(self, ind=0):
             i_bits = self.get_input_datatype(0).bitwidth()
             width = i_bits * self.get_nodeattr("SIMD")
         elif ind == 1:
-            if (
+            if self.get_nodeattr("dynamic_input"):
+                width = (
+                    self.get_folded_input_shape(ind)[-1] * self.get_input_datatype(ind).bitwidth()
+                )
+            elif (
                 self.get_nodeattr("mem_mode") == "internal_decoupled"
                 or self.get_nodeattr("mem_mode") == "external"
             ):
@@ -726,6 +730,8 @@ def make_weight_file(self, weights, weight_file_mode, weight_file_name):
             elif weight_file_mode == "decoupled_verilog_dat":
                 # convert weight values into hexstring
                 weight_width = self.get_instream_width(1)
+                if self.get_nodeattr("dynamic_input"):
+                    weight_width = weight_width * simd
                 # pad to nearest 4 bits to get hex strings
                 weight_width_padded = roundup_to_integer_multiple(weight_width, 4)
                 weight_tensor_pe_flipped = pack_innermost_dim_as_hex_string(
@@ -756,6 +762,8 @@ def make_weight_file(self, weights, weight_file_mode, weight_file_name):
                 # memstream axi-lite interface will map each mem line to
                 # one or multiple 32-bit words
                 weight_width = self.get_instream_width(1)
+                if self.get_nodeattr("dynamic_input"):
+                    weight_width = weight_width * simd
                 words_per_memwidth = 2 ** math.ceil(math.log2(weight_width / 32))
                 if words_per_memwidth < 1:
                     words_per_memwidth = 1
@@ -906,7 +914,9 @@ def get_verilog_top_module_intf_names(self):
         dynamic_input = self.get_nodeattr("dynamic_input")
         mem_mode = self.get_nodeattr("mem_mode")
         if dynamic_input:
-            intf_names["s_axis"].append(("in1_V", self.get_instream_width_padded(1)))
+            weight_width = self.get_instream_width(1)
+            weight_width = weight_width * self.get_nodeattr("SIMD")
+            intf_names["s_axis"].append(("in1_V", roundup_to_integer_multiple(weight_width, 8)))
         else:
             if mem_mode == "external":
                 intf_names["s_axis"].append(("in1_V", self.get_instream_width_padded(1)))

src/finn/custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py

@@ -104,6 +104,8 @@ def execute_node(self, context, graph):
 
             if dynamic_input or mem_mode in ["external", "internal_decoupled"]:
                 wnbits = self.get_instream_width(1)
+                if dynamic_input:
+                    wnbits = wnbits * self.get_nodeattr("SIMD")
                 export_wdt = self.get_input_datatype(1)
 
                 wei = npy_to_rtlsim_input("{}/input_1.npy".format(code_gen_dir), export_wdt, wnbits)