Is there any example custom steps for CNV network with non uniform input shape (specifically radio sample)?

[Phu1234567]

I have been following FINN tutorials on CNV network and tried to apply it to my model, but the tutorial used image input which is (1x3x32x32). My model used a radio sample as input (trained for Modulation Classification), which has (1x2x1024x1) as input shape. I managed to get to the hardware build step and got the driver zip file on FPGA, but I notice the input shape for folded and packed is not the same as the normal input. Also, when I perform execute_on_buffer(), the output remains the same regardless of input (0% accuracy compared to cppsim accuracy 86%).

Is this because my folding step was wrong? (I used setfolding() transformation)
Also is there any tutorial or example that I can take inspiration from that could be apply to my project?

[fpjentzsch]

Hi,

maybe you can take inspiration from this finn-example for a 1D CNN on the RadioML18 dataset: https://github.com/Xilinx/finn-examples/tree/main/build/vgg10-radioml

[Phu1234567]

Hello, thank you for sharing the example. I was able to train the model on my dataset, but I was unable to go through the entire build because it says I was missing "./Vfinn_design_wrapper"

Building dataflow accelerator from finn-examples/build/vgg10-radioml/models/vgg_tidy.onnx
Intermediate outputs will be generated in /home/user/repos/PytorchModClass/tmp/finn_dev_user
Final outputs will be generated in output_vgg_tidy_ZCU104
Build log is at output_vgg_tidy_ZCU104/build_dataflow.log
Running step: step_tidy_up [1/20]
Running step: step_pre_streamline [2/20]
Running step: step_streamline [3/20]
Running step: step_convert_to_hw [4/20]
Running step: step_convert_final_layers [5/20]
Running step: step_create_dataflow_partition [6/20]
Running step: step_specialize_layers [7/20]
Running step: step_target_fps_parallelization [8/20]
Running step: step_apply_folding_config [9/20]
Running step: step_minimize_bit_width [10/20]
Running step: step_generate_estimate_reports [11/20]
Running step: step_hw_codegen [12/20]
Running step: step_hw_ipgen [13/20]
Running step: step_set_fifo_depths [14/20]
Traceback (most recent call last):
  File "/home/user/anaconda3/envs/torch_resnet/lib/python3.8/site-packages/finn/builder/build_dataflow.py", line 158, in build_dataflow_cfg
    model = transform_step(model, cfg)
  File "/home/user/anaconda3/envs/torch_resnet/lib/python3.8/site-packages/finn/builder/build_dataflow_steps.py", line 579, in step_set_fifo_depths
    model = model.transform(
  File "/home/user/anaconda3/envs/torch_resnet/lib/python3.8/site-packages/qonnx/core/modelwrapper.py", line 140, in transform
    (transformed_model, model_was_changed) = transformation.apply(transformed_model)
  File "/home/user/anaconda3/envs/torch_resnet/lib/python3.8/site-packages/finn/transformation/fpgadataflow/set_fifo_depths.py", line 394, in apply
    sim = verilator_fifosim(model, n_inputs)
  File "/home/user/anaconda3/envs/torch_resnet/lib/python3.8/site-packages/finn/util/pyverilator.py", line 244, in verilator_fifosim
    launch_process_helper(sim_launch_args, cwd=build_dir)
  File "/home/user/anaconda3/envs/torch_resnet/lib/python3.8/site-packages/finn/util/basic.py", line 205, in launch_process_helper
    with subprocess.Popen(
  File "/home/user/anaconda3/envs/torch_resnet/lib/python3.8/subprocess.py", line 858, in __init__
    self._execute_child(args, executable, preexec_fn, close_fds,
  File "/home/user/anaconda3/envs/torch_resnet/lib/python3.8/subprocess.py", line 1720, in _execute_child
    raise child_exception_type(errno_num, err_msg, err_filename)
FileNotFoundError: [Errno 2] No such file or directory: './Vfinn_design_wrapper'
> /home/user/anaconda3/envs/torch_resnet/lib/python3.8/subprocess.py(1720)_execute_child()
-> raise child_exception_type(errno_num, err_msg, err_filename)

Is this supposed to be available when I set up FINN or is there additional step that I am missing?

[fpjentzsch]

This file is created by FINN itself, so the error you see is the result of something going wrong in a previous step. Could you check the temporary build artifacts in FINN_BUILD_DIR? There should be directories (e.g., "...ipgen...") for the code generation and Vitis HLS synthesis of individual layers. At least one of them probably failed, and there should be some .log file that contains more information about the cause.

[Phu1234567]

Thanks for the clarification. I was able to find a few files in the FINN_BUILD_DIR directories that were referencing "./Vfinn_design_wrapper".

Inside "output_model/build_dataflow.log"

[2024-11-19 08:27:40,261] %Error: Cannot find file containing module:  /home/user/Vivado/Vivado/2024.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv
[2024-11-19 08:27:40,261]         ... Looked in:
[2024-11-19 08:27:40,261]              /home/user/repos/PytorchModClass/tmp/finn_dev_user/vivado_stitch_proj_5h3wqjjx/ /home/user/Vivado/Vivado/2024.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv
[2024-11-19 08:27:40,261]              /home/user/repos/PytorchModClass/tmp/finn_dev_user/vivado_stitch_proj_5h3wqjjx/ /home/user/Vivado/Vivado/2024.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv.v
[2024-11-19 08:27:40,261]              /home/user/repos/PytorchModClass/tmp/finn_dev_user/vivado_stitch_proj_5h3wqjjx/ /home/user/Vivado/Vivado/2024.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv.sv
[2024-11-19 08:27:40,261]              /home/user/repos/PytorchModClass/tmp/finn_dev_user/vivado_stitch_proj_5h3wqjjx/pyverilator_vh/ /home/user/Vivado/Vivado/2024.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv
[2024-11-19 08:27:40,261]              /home/user/repos/PytorchModClass/tmp/finn_dev_user/vivado_stitch_proj_5h3wqjjx/pyverilator_vh/ /home/user/Vivado/Vivado/2024.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv.v
[2024-11-19 08:27:40,261]              /home/user/repos/PytorchModClass/tmp/finn_dev_user/vivado_stitch_proj_5h3wqjjx/pyverilator_vh/ /home/user/Vivado/Vivado/2024.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv.sv
[2024-11-19 08:27:40,261]               /home/user/Vivado/Vivado/2024.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv
[2024-11-19 08:27:40,261]               /home/user/Vivado/Vivado/2024.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv.v
[2024-11-19 08:27:40,261]               /home/user/Vivado/Vivado/2024.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv.sv
[2024-11-19 08:27:40,261]              /home/user/repos/PytorchModClass/tmp/finn_dev_user/verilator_fifosim_v5b4rho2/ /home/user/Vivado/Vivado/2024.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv
[2024-11-19 08:27:40,261]              /home/user/repos/PytorchModClass/tmp/finn_dev_user/verilator_fifosim_v5b4rho2/ /home/user/Vivado/Vivado/2024.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv.v
[2024-11-19 08:27:40,261]              /home/user/repos/PytorchModClass/tmp/finn_dev_user/verilator_fifosim_v5b4rho2/ /home/user/Vivado/Vivado/2024.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv.sv
[2024-11-19 08:27:40,261] %Error: Cannot find file containing module:  /home/user/Vivado/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv
[2024-11-19 08:27:40,261] %Error: Cannot find file containing module:  /home/user/Vivado/Vivado/2024.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv
[2024-11-19 08:27:40,261] %Error: Exiting due to 3 error(s)
[2024-11-19 08:27:40,282] make: Entering directory '/home/user/repos/PytorchModClass/tmp/finn_dev_user/verilator_fifosim_v5b4rho2'
[2024-11-19 08:27:40,282] make: Leaving directory '/home/user/repos/PytorchModClass/tmp/finn_dev_user/verilator_fifosim_v5b4rho2'
[2024-11-19 08:27:40,282] make: Vfinn_design_wrapper.mk: No such file or directory
[2024-11-19 08:27:40,282] make: *** No rule to make target 'Vfinn_design_wrapper.mk'.  Stop.

Inside "/finn_dev_user/verilator_fifosim_v5b4rho2/compile.sh" (FINN_BUILD_DIR=finn_dev_user)

#!/bin/bash
export OPT_FAST='-O3 -march=native'
perl /usr/bin/verilator -Wno-fatal -Mdir /home/user/repos/PytorchModClass/tmp/finn_dev_user/verilator_fifosim_v5b4rho2 -y /home/user/repos/PytorchModClass/tmp/finn_dev_user/vivado_stitch_proj_5h3wqjjx -y /home/user/repos/PytorchModClass/tmp/finn_dev_user/vivado_stitch_proj_5h3wqjjx/pyverilator_vh --CFLAGS --std=c++11 -O3 --x-assign fast --x-initial fast --noassert --cc /home/user/repos/PytorchModClass/finn/finn-rtllib/swg/swg_pkg.sv finn_design_wrapper.v  /home/user/Vivado/Vivado/2024.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv  /home/user/Vivado/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv  /home/user/Vivado/Vivado/2024.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv --top-module finn_design_wrapper --exe verilator_fifosim.cpp --threads 4 -DDISABLE_XPM_ASSERTIONS -DOBSOLETE -DONESPIN --bbox-unsup
make -j4 -C /home/user/repos/PytorchModClass/tmp/finn_dev_user/verilator_fifosim_v5b4rho2 -f Vfinn_design_wrapper.mk Vfinn_design_wrapper

I also test run the first 2 line before running the make command line in the compile.sh file (the file directly above):

export OPT_FAST='-O3 -march=native'
perl /usr/bin/verilator -Wno-fatal -Mdir /home/user/repos/PytorchModClass/tmp/finn_dev_user/verilator_fifosim_v5b4rho2 -y /home/user/repos/PytorchModClass/tmp/finn_dev_user/vivado_stitch_proj_5h3wqjjx -y /home/user/repos/PytorchModClass/tmp/finn_dev_user/vivado_stitch_proj_5h3wqjjx/pyverilator_vh --CFLAGS --std=c++11 -O3 --x-assign fast --x-initial fast --noassert --cc /home/user/repos/PytorchModClass/finn/finn-rtllib/swg/swg_pkg.sv finn_design_wrapper.v  /home/user/Vivado/Vivado/2024.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv  /home/user/Vivado/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv  /home/user/Vivado/Vivado/2024.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv --top-module finn_design_wrapper --exe verilator_fifosim.cpp --threads 4 -DDISABLE_XPM_ASSERTIONS -DOBSOLETE -DONESPIN --bbox-unsup

which gave me this long errors of PIN_MISSING and TIME_SCALE_MOD:

%Warning-PINMISSING: /home/user/repos/PytorchModClass/tmp/finn_dev_user/vivado_stitch_proj_5h3wqjjx/finn_design_wrapper.v:52975:36: Cell has missing pin: 's_axilite_AWREADY'
52975 |   finn_design_Thresholding_rtl_7_0 Thresholding_rtl_7
      |                                    ^~~~~~~~~~~~~~~~~~
%Warning-PINMISSING: /home/user/repos/PytorchModClass/tmp/finn_dev_user/vivado_stitch_proj_5h3wqjjx/finn_design_wrapper.v:52975:36: Cell has missing pin: 's_axilite_WREADY'
52975 |   finn_design_Thresholding_rtl_7_0 Thresholding_rtl_7
      |                                    ^~~~~~~~~~~~~~~~~~
%Warning-PINMISSING: /home/user/repos/PytorchModClass/tmp/finn_dev_user/vivado_stitch_proj_5h3wqjjx/finn_design_wrapper.v:52975:36: Cell has missing pin: 's_axilite_BVALID'
52975 |   finn_design_Thresholding_rtl_7_0 Thresholding_rtl_7
      |                                    ^~~~~~~~~~~~~~~~~~
%Warning-PINMISSING: /home/user/repos/PytorchModClass/tmp/finn_dev_user/vivado_stitch_proj_5h3wqjjx/finn_design_wrapper.v:52975:36: Cell has missing pin: 's_axilite_BRESP'
52975 |   finn_design_Thresholding_rtl_7_0 Thresholding_rtl_7
      |                                    ^~~~~~~~~~~~~~~~~~
%Warning-PINMISSING: /home/user/repos/PytorchModClass/tmp/finn_dev_user/vivado_stitch_proj_5h3wqjjx/finn_design_wrapper.v:52975:36: Cell has missing pin: 's_axilite_ARREADY'
52975 |   finn_design_Thresholding_rtl_7_0 Thresholding_rtl_7
      |                                    ^~~~~~~~~~~~~~~~~~
%Warning-PINMISSING: /home/user/repos/PytorchModClass/tmp/finn_dev_user/vivado_stitch_proj_5h3wqjjx/finn_design_wrapper.v:52975:36: Cell has missing pin: 's_axilite_RVALID'
52975 |   finn_design_Thresholding_rtl_7_0 Thresholding_rtl_7
      |                                    ^~~~~~~~~~~~~~~~~~
%Warning-PINMISSING: /home/user/repos/PytorchModClass/tmp/finn_dev_user/vivado_stitch_proj_5h3wqjjx/finn_design_wrapper.v:52975:36: Cell has missing pin: 's_axilite_RDATA'
52975 |   finn_design_Thresholding_rtl_7_0 Thresholding_rtl_7
      |                                    ^~~~~~~~~~~~~~~~~~
%Warning-PINMISSING: /home/user/repos/PytorchModClass/tmp/finn_dev_user/vivado_stitch_proj_5h3wqjjx/finn_design_wrapper.v:52975:36: Cell has missing pin: 's_axilite_RRESP'
52975 |   finn_design_Thresholding_rtl_7_0 Thresholding_rtl_7
      |                                    ^~~~~~~~~~~~~~~~~~
%Warning-PINMISSING: /home/user/repos/PytorchModClass/tmp/finn_dev_user/vivado_stitch_proj_5h3wqjjx/finn_design_wrapper.v:52993:36: Cell has missing pin: 's_axilite_AWREADY'
52993 |   finn_design_Thresholding_rtl_8_0 Thresholding_rtl_8
      |                                    ^~~~~~~~~~~~~~~~~~
%Warning-PINMISSING: /home/user/repos/PytorchModClass/tmp/finn_dev_user/vivado_stitch_proj_5h3wqjjx/finn_design_wrapper.v:52993:36: Cell has missing pin: 's_axilite_WREADY'
52993 |   finn_design_Thresholding_rtl_8_0 Thresholding_rtl_8
      |                                    ^~~~~~~~~~~~~~~~~~
%Warning-PINMISSING: /home/user/repos/PytorchModClass/tmp/finn_dev_user/vivado_stitch_proj_5h3wqjjx/finn_design_wrapper.v:52993:36: Cell has missing pin: 's_axilite_BVALID'
52993 |   finn_design_Thresholding_rtl_8_0 Thresholding_rtl_8
      |                                    ^~~~~~~~~~~~~~~~~~
%Warning-PINMISSING: /home/user/repos/PytorchModClass/tmp/finn_dev_user/vivado_stitch_proj_5h3wqjjx/finn_design_wrapper.v:52993:36: Cell has missing pin: 's_axilite_BRESP'
52993 |   finn_design_Thresholding_rtl_8_0 Thresholding_rtl_8
      |                                    ^~~~~~~~~~~~~~~~~~
%Warning-PINMISSING: /home/user/repos/PytorchModClass/tmp/finn_dev_user/vivado_stitch_proj_5h3wqjjx/finn_design_wrapper.v:52993:36: Cell has missing pin: 's_axilite_ARREADY'
52993 |   finn_design_Thresholding_rtl_8_0 Thresholding_rtl_8
      |                                    ^~~~~~~~~~~~~~~~~~
%Warning-PINMISSING: /home/user/repos/PytorchModClass/tmp/finn_dev_user/vivado_stitch_proj_5h3wqjjx/finn_design_wrapper.v:52993:36: Cell has missing pin: 's_axilite_RVALID'
52993 |   finn_design_Thresholding_rtl_8_0 Thresholding_rtl_8
      |                                    ^~~~~~~~~~~~~~~~~~
%Warning-PINMISSING: /home/user/repos/PytorchModClass/tmp/finn_dev_user/vivado_stitch_proj_5h3wqjjx/finn_design_wrapper.v:52993:36: Cell has missing pin: 's_axilite_RDATA'
52993 |   finn_design_Thresholding_rtl_8_0 Thresholding_rtl_8
      |                                    ^~~~~~~~~~~~~~~~~~
%Warning-PINMISSING: /home/user/repos/PytorchModClass/tmp/finn_dev_user/vivado_stitch_proj_5h3wqjjx/finn_design_wrapper.v:52993:36: Cell has missing pin: 's_axilite_RRESP'
52993 |   finn_design_Thresholding_rtl_8_0 Thresholding_rtl_8
      |                                    ^~~~~~~~~~~~~~~~~~
%Error-TIMESCALEMOD: /home/user/repos/PytorchModClass/finn/finn-rtllib/swg/swg_pkg.sv:32:9: Timescale missing on this module as other modules have it (IEEE 1800-2017 3.14.2.2)
                     /home/user/repos/PytorchModClass/tmp/finn_dev_user/vivado_stitch_proj_5h3wqjjx/finn_design_wrapper.v:14:8: ... Location of module with timescale
   14 | module StreamingMaxPool_hls_2 (
      |        ^~~~~~~~~~~~~~~~~~~~~~
%Error-TIMESCALEMOD: /home/user/repos/PytorchModClass/tmp/finn_dev_user/vivado_stitch_proj_5h3wqjjx/finn_design_wrapper.v:60701:72: Timescale missing on this module as other modules have it (IEEE 1800-2017 3.14.2.2)
                     /home/user/repos/PytorchModClass/tmp/finn_dev_user/vivado_stitch_proj_5h3wqjjx/finn_design_wrapper.v:14:8: ... Location of module with timescale
   14 | module StreamingMaxPool_hls_2 (
      |        ^~~~~~~~~~~~~~~~~~~~~~
%Error: Exiting due to 2 error(s)

[Phu1234567]

Small update: I was able to run through the entire process by just skipping the setting fifo step instead.