IPGen failed: ERROR: [HLS 207-2163] 'bitwidth' attribute requires integer constant between 1 and 8191 inclusive

[jurevreca12]

Hello,
I am trying to run a set of experiments on different layers between chisel4ml, hls4ml and FINN (v0.10.1). For that I am using the HLS version of FINN processing elements. I set the FINN to the maximum parallelization possible. Specifically, I am currently trying to perform these experiments for the fully-connected layer. However, I am running into trouble as FINN gives me the following error:

Running step: step_qonnx_to_finn [1/18]                                                                                       │
Running step: step_tidy_up [2/18]                                                                                             │
Running step: step_streamline [3/18]                                                                                          │
/venv/lib/python3.10/site-packages/qonnx/transformation/infer_data_layouts.py:136: UserWarning: Assuming 2D input is NC       │
  warnings.warn("Assuming 2D input is NC")                                                                                    │
Running step: step_convert_to_hw [4/18]                                                                                       │
Running step: step_create_dataflow_partition [5/18]                                                                           │
Running step: step_specialize_layers [6/18]                                                                                   │
Running step: step_set_max_parallelization [7/18]                                                                             │
Running step: step_minimize_bit_width [8/18]                                                                                  │
Running step: step_generate_estimate_reports [9/18]                                                                           │
Running step: step_hw_codegen [10/18]                                                                                         │
Running step: step_hw_ipgen [11/18]                                                                                           │
Traceback (most recent call last):                                                                                            │
  File "/venv/lib/python3.10/site-packages/finn/builder/build_dataflow.py", line 158, in build_dataflow_cfg                   │
    model = transform_step(model, cfg)                                                                                        │
  File "/venv/lib/python3.10/site-packages/finn/builder/build_dataflow_steps.py", line 523, in step_hw_ipgen                  │
    model = model.transform(HLSSynthIP())                                                                                     │
  File "/venv/lib/python3.10/site-packages/qonnx/core/modelwrapper.py", line 145, in transform                                │
    (transformed_model, model_was_changed) = transformation.apply(transformed_model)                                          │
  File "/venv/lib/python3.10/site-packages/qonnx/transformation/base.py", line 115, in apply                                  │
    new_nodes_and_bool = [self.applyNodeLocal(node) for node in old_nodes]                                                    │
  File "/venv/lib/python3.10/site-packages/qonnx/transformation/base.py", line 115, in <listcomp>                             │
    new_nodes_and_bool = [self.applyNodeLocal(node) for node in old_nodes]                                                    │
  File "/venv/lib/python3.10/site-packages/finn/transformation/fpgadataflow/hlssynth_ip.py", line 72, in applyNodeLocal       │
    inst.ipgen_singlenode_code()                                                                                              │
  File "/venv/lib/python3.10/site-packages/finn/custom_op/fpgadataflow/hlsbackend.py", line 186, in ipgen_singlenode_code     │
    assert os.path.isdir(ip_path), "IPGen failed: %s not found. Check log under %s" % (                                       │
AssertionError: IPGen failed: /finn_build_dir/code_gen_ipgen_MVAU_hls_0_78pttbbt/project_MVAU_hls_0/sol1/impl/ip not found. Ch│
eck log under /finn_build_dir/code_gen_ipgen_MVAU_hls_0_78pttbbt                                                              │
> /venv/lib/python3.10/site-packages/finn/custom_op/fpgadataflow/hlsbackend.py(186)ipgen_singlenode_code()                    │
-> assert os.path.isdir(ip_path), "IPGen failed: %s not found. Check log under %s" % (

And in the vitis_hls.log I get:

****** Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2023.1 (64-bit)                                               
│  **** SW Build 3854077 on May  4 2023
│  **** IP Build 3864474 on Sun May  7 20:36:21 MDT 2023
│  **** SharedData Build 3865790 on Sun May 07 13:33:03 MDT 2023                                                               
│    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
│    ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.                                                  
│
│source /net/jastreb/opt/Xilinx/Vitis_HLS/2023.1/scripts/vitis_hls/hls.tcl -notrace                                            
│INFO: [HLS 200-10] Running '/net/jastreb/opt/Xilinx/Vitis_HLS/2023.1/bin/unwrapped/lnx64.o/vitis_hls'                         
│/net/jastreb/opt/Xilinx/Vitis_HLS/2023.1/tps/tcl/tcl8.5/tzdata/Europe/Ljubljana can't be opened.                              
│INFO: [HLS 200-10] For user 'root' on host '2c7ac588aeef' (Linux_x86_64 version 4.18.0-553.33.1.el8_10.x86_64) on Mon Feb 24 22
│:41:32 CET 2025
│INFO: [HLS 200-10] On os Ubuntu 22.04.1 LTS
│INFO: [HLS 200-10] In directory '/finn_build_dir/code_gen_ipgen_MVAU_hls_0_78pttbbt'                                          
│Sourcing Tcl script '/finn_build_dir/code_gen_ipgen_MVAU_hls_0_78pttbbt/hls_syn_MVAU_hls_0.tcl'                               
│INFO: [HLS 200-1510] Running: source /finn_build_dir/code_gen_ipgen_MVAU_hls_0_78pttbbt/hls_syn_MVAU_hls_0.tcl                
│HLS project: project_MVAU_hls_0
│HW source dir: /finn_build_dir/code_gen_ipgen_MVAU_hls_0_78pttbbt                                                             
│finn-hlslib dir: /workspace/finn/deps/finn-hlslib
│custom HLS dir: /workspace/finn/custom_hls
│INFO: [HLS 200-1510] Running: open_project project_MVAU_hls_0
│INFO: [HLS 200-10] Creating and opening project '/finn_build_dir/code_gen_ipgen_MVAU_hls_0_78pttbbt/project_MVAU_hls_0'.      
│INFO: [HLS 200-1510] Running: add_files /finn_build_dir/code_gen_ipgen_MVAU_hls_0_78pttbbt/top_MVAU_hls_0.cpp -cflags -std=c++1
│4 -I/workspace/finn/deps/finn-hlslib -I/workspace/finn/custom_hls                                                             
│INFO: [HLS 200-10] Adding design file '/finn_build_dir/code_gen_ipgen_MVAU_hls_0_78pttbbt/top_MVAU_hls_0.cpp' to the project  
│INFO: [HLS 200-1510] Running: set_top MVAU_hls_0
│INFO: [HLS 200-1510] Running: open_solution sol1
│INFO: [HLS 200-10] Creating and opening solution '/finn_build_dir/code_gen_ipgen_MVAU_hls_0_78pttbbt/project_MVAU_hls_0/sol1'.
│INFO: [HLS 200-1505] Using default flow_target 'vivado'
│Resolution: For help on HLS 200-1505 see www.xilinx.com/cgi-bin/docs/rdoc?v=2023.1;t=hls+guidance;d=200-1505.html             
│INFO: [HLS 200-1510] Running: set_part xcvu9p-flga2104-2L-e
│INFO: [HLS 200-1611] Setting target device to 'xcvu9p-flga2104-2L-e'                                                          
│INFO: [HLS 200-1510] Running: config_compile -disable_unroll_code_size_check -pipeline_style flp                              
│WARNING: [XFORM 203-506] Disable code size check when do loop unroll.                                                         
│WARNING: [HLS 200-643] The 'config_compile -disable_unroll_code_size_check' hidden command is deprecated and will be removed in
│ a future release.
│INFO: [HLS 200-1510] Running: config_interface -m_axi_addr64
│INFO: [HLS 200-1510] Running: config_rtl -module_auto_prefix
│INFO: [HLS 200-1510] Running: config_rtl -deadlock_detection none                                                             
│INFO: [HLS 200-1510] Running: create_clock -period 10.0 -name default                                                         
│INFO: [SYN 201-201] Setting up clock 'default' with a period of 10ns.                                                         
│INFO: [HLS 200-1510] Running: csynth_design
│INFO: [HLS 200-111] Finished File checks and directory preparation: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds.
│ Elapsed time: 0.08 seconds; current allocated memory: 1.063 GB.                                                              
│INFO: [HLS 200-10] Analyzing design file '/finn_build_dir/code_gen_ipgen_MVAU_hls_0_78pttbbt/top_MVAU_hls_0.cpp' ...          
│ERROR: [HLS 207-2163] 'bitwidth' attribute requires integer constant between 1 and 8191 inclusive (/net/jastreb/opt/Xilinx/Viti
│s_HLS/2023.1/common/technology/autopilot/etc/ap_common.h:520:35)                                                              
│INFO: [HLS 207-4518] in instantiation of template class 'ssdm_int<8192, false>' requested here (/net/jastreb/opt/Xilinx/Vitis_H
│LS/2023.1/common/technology/autopilot/etc/ap_int_base.h:108:29)                                                               
│INFO: [HLS 207-4518] in instantiation of template class 'ap_int_base<8192, false>' requested here (/net/jastreb/opt/Xilinx/Viti
│s_HLS/2023.1/common/technology/autopilot/ap_int.h:181:18)
│INFO: [HLS 207-4518] in instantiation of template class 'ap_uint<8192>' requested here (/finn_build_dir/code_gen_ipgen_MVAU_hls
│_0_78pttbbt/top_MVAU_hls_0.cpp:37:1)
│ERROR: [HLS 207-2163] 'bitwidth' attribute requires integer constant between 1 and 8191 inclusive (/net/jastreb/opt/Xilinx/Viti
│s_HLS/2023.1/common/technology/autopilot/etc/ap_common.h:521:29)
│ERROR: [HLS 207-2163] 'bitwidth' attribute requires integer constant between 1 and 8191 inclusive (/net/jastreb/opt/Xilinx/Viti
│s_HLS/2023.1/common/technology/autopilot/etc/ap_common.h:523:104)                                                             
│ERROR: [HLS 207-2163] 'bitwidth' attribute requires integer constant between 1 and 8191 inclusive (/net/jastreb/opt/Xilinx/Viti
│s_HLS/2023.1/common/technology/autopilot/ap_int.h:212:114)
│ERROR: [HLS 207-3337] type 'ap_uint<128U * 16U * ap_int<4>::width>' does not provide a call operator (/workspace/finn/deps/finn
│-hlslib/mvau.hpp:268:20)
│INFO: [HLS 207-4235] in instantiation of function template specialization 'Matrix_Vector_Activate_Stream_Batch<16, 128, 16, 128
│, Slice<ap_int<4>, 4>, Slice<ap_int<4>, 4>, Identity, ap_int<4>, ap_uint<64>, ap_uint<512>, ThresholdsActivation<1, 128, 15, ap
│_int<11>, ap_int<4>, -8, comp::less_equal<ap_int<11>, ap_int<11> > >, ap_resource_dflt>' requested here (/finn_build_dir/code_g
│en_ipgen_MVAU_hls_0_78pttbbt/top_MVAU_hls_0.cpp:37:1)
│INFO: [HLS 200-111] Finished Command csynth_design CPU user time: 1.02 seconds. CPU system time: 0.48 seconds. Elapsed time: 1.
│49 seconds; current allocated memory: 1.695 MB.
│
│    while executing
│"source /finn_build_dir/code_gen_ipgen_MVAU_hls_0_78pttbbt/hls_syn_MVAU_hls_0.tcl"                                            
│    invoked from within
│"hls::main /finn_build_dir/code_gen_ipgen_MVAU_hls_0_78pttbbt/hls_syn_MVAU_hls_0.tcl"                                         
│    ("uplevel" body line 1)
│    invoked from within
│"uplevel 1 hls::main {*}$newargs"
│    (procedure "hls_proc" line 16)
│    invoked from within
│"hls_proc [info nameofexecutable] $argv"
│INFO: [HLS 200-112] Total CPU user time: 3.84 seconds. Total CPU system time: 1.33 seconds. Total elapsed time: 5.06 seconds; p
│eak allocated memory: 1.065 GB.
│INFO: [Common 17-206] Exiting vitis_hls at Mon Feb 24 22:41:37 2025...    

I've done some digging and I found this issue: #1060 that suggests that this could be the result of the stream interface being to wide. I am setting the maximum parallelization here, however the layer is relatively small. The whole "network" is just a single fully-connected layer with 16 inputs and 128 outputs. The network is quantized to 4-bits (input/output/weight), except for the bias which is 8-bits. I don't understand how this could possibly go above the limit of 8192.
How can I fix this issue? I do not want to change the SIMD and PE settings, as I am trying to compare the tools at maximum possible parallelization level.

Here is the repository of my experiments: https://github.com/jurevreca12/c4ml_test_runs/tree/phd-experiments
I am also attaching the intermediate results of the FINN tool and the offending FINN build directory.
finn.zip
code_gen_ipgen_MVAU_hls_0_78pttbbt.zip

[fpjentzsch]

Hi,

you seem to be using the internal_decoupled weight memory setting for the MVAU, which will instantiate a weight stream of width SIMD * PE * Bitwidth = 16 * 128 * 4 = 8192 in this case. For full parallelism you should really be using internal_embedded, so the weights are hardcoded into the MVAU, requiring no weight stream input port.

[jurevreca12]

Ah. Yes. This did the trick. I had a bug in the transformation that set the node attributes. Thanks a lot.

Best regards,
Jure