How to add a customized modification to the verilog code from HLS or other means

[saionroy]

Hello everyone,

I want to generate a trigger signal from one of the GPIO pins on the PYNQ board which is high only when the DNN inference for one input is executing on the FPGA. This is for observing the timing duration on an oscilloscope.

This signal need to start just before the inference and end after the inference. I want match the timings as close as possible. Is there a direct way to add the trigger signal in the verilog file which specific to the inference? If so then the generated bitfile and hwh file will activate this pin during the inference. This signal need to come out from one of the GPIO pins on the PYNQ board so would need a modification to the .xdc file as well.

I am not sure how this can be done from the outside using HLS. Here are a couple of questions:

1. Where are the verilog files, bitfiles, and hwh file stored after HLS?
2. In the jupyter notebook there is a single call to the function accel.execute(ibuf_normal). Where is loading the bitfile and the hwh file to the PYNQ ?
3. My current plan is to get a modified bitfile and hwh file but how are they linked to this single execute command ?

Looking forward to answers from the experienced folks. If there are any repositories addressing or previous posts answering these questions please point me to them.

[saionroy]

I found the fpga_dataflow tutorial to get the bitfile and pynq deployment zip file. When the bitfile is generated from the build_dataflow_config then it correctly working.

I am getting a bitfile generation error when attempting to use generate bitstream in Vivado:

[DRC NSTD-1] Unspecified I/O Standard: 54 out of 55 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: ap_clk, ap_rst_n, m_axis_0_tdata[7:0], m_axis_0_tready, m_axis_0_tvalid, s_axis_0_tdata[39:0], s_axis_0_tready, and s_axis_0_tvalid.

My goal is to add a trigger signal in verilog which will be active during the inference.
Idea 1: Modify the verilog file in Vivado. Can do this, but cannot generate the bitfile using Vivado
Idea 2: Use HLS to add an additional signal. Not sure if this can be done.

Any insights? Need help with this.