Why is there a hardcoded limit for the AXI-Lite Interfaces?

[CarloSchafflik12]

My model requires a few AXI-Lite interfaces because runtime weights are enabled. However, an error was asserted by a .tcl file while generating the bitfile:

"Maximum 10 AXI-Lite interfaces supported"

This limit is hardcoded in this file: "finn/src/transformation/fpgaflow/templates.py", which creates the .tcl file:

if {$NUM_AXILITE > 9} {
error "Maximum 10 AXI-Lite interfaces supported"
}

However, when I increase the limit to 15, for example, the bit file is generated and everything works as expected. So, my question is, why is this limit there?

[fpjentzsch]

Hi,

I don't know where that limit came from. In my experience, the real limit is 64, which is the maximum number of slave interfaces of a single AXI interconnect.

In FINN+, we removed this limit and additionally implemented AXI interconnect nesting as part of eki-project#45, so we can theoretically support up to 4096 AXI-Lite interfaces. We successfully built designs with up to 500 interfaces before (those were not for runtime-writable weights though).

[auphelia]

Hi @CarloSchafflik12 , thanks for making us aware! I think that is legacy from the VitisBuild times in which there is a limitation on the number of axilite interfaces each .xo can have. There was an effort in the past to make the zynq build and vitis build similar and it seems this is a leftover of that. I will create an issue from this discussion to address it.