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Can I add hardware IP into FINN by using Vivado HLS? My understanding of Vivado HLS is writing C code and synthesis, then combine Vivado PS block to generate bistream. The tutorial seems like using python to generate custom IP, and there is limit for generating custom IP. Am I right? If I generate bistream, how could I deploy on FPGA by PYNQ |
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Replies: 3 comments 12 replies
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Hi @btwbtw01 , this is indeed possible but is considered an advanced use-case and we don't have a tutorial for this just yet. There was a previous Gitter discussion on this here but I'm copying (with some edits) the key steps here, using the recently-added upsampling layer support as a running example:
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@maltanar Can I just write HLS functions and wrap it up, so I don't have to add CustomOp subclass in FINN compiler? |
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Adding this link here, since the custom op integration has slightly changed in the latest release: #1026 (comment) And the additional discussion here: #1160 (thanks @JPPalacios and @iksnagreb) |
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Adding this link here, since the custom op integration has slightly changed in the latest release: #1026 (comment)
And the additional discussion here: #1160 (thanks @JPPalacios and @iksnagreb)