Y2K22 BUG: ERROR: [BD 5-390] IP definition not found for VLNV ... #483

shashwat1198 · 2022-01-03T14:50:53Z

shashwat1198
Jan 3, 2022

Hey,

I am trying to go through the example cybersecurity notebooks for FINN.

When I try to build the hardware for the MLP in the third notebook I get the following error :
ERROR: [BD 5-390] IP definition not found for VLNV: xilinx.com:hls:StreamingFCLayer_Batch_0:1.0

Has anyone seen this error before?

I am using the Vivado 2019.1 version.

Thanks in advance,
Shashwat

Answered by rpitonak

Jan 4, 2022

Yesterday, I got a similar error using Vivado 2020.1.

WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/workspace/finn/build/vivado_stitch_proj_687ts1e6/ip'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
# create_bd_cell -type ip -vlnv xilinx_finn:finn:StreamingDataflowPartition_0:1.0 idma0
ERROR: [BD 5-390] IP definition not found for VLNV: xilinx_finn:finn:StreamingDataflowPartition_0:1.0
ERROR: [Common 17-39] 'create_bd_cell' failed due to earlier errors.

    while executing
"create_bd_cell -type ip -vlnv xilinx_finn:finn:StreamingDataflowPartition_0:1.0 idma0"
    (file …

View full answer

rpitonak · 2022-01-04T08:44:18Z

rpitonak
Jan 4, 2022

Yesterday, I got a similar error using Vivado 2020.1.

WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/workspace/finn/build/vivado_stitch_proj_687ts1e6/ip'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
# create_bd_cell -type ip -vlnv xilinx_finn:finn:StreamingDataflowPartition_0:1.0 idma0
ERROR: [BD 5-390] IP definition not found for VLNV: xilinx_finn:finn:StreamingDataflowPartition_0:1.0
ERROR: [Common 17-39] 'create_bd_cell' failed due to earlier errors.

    while executing
"create_bd_cell -type ip -vlnv xilinx_finn:finn:StreamingDataflowPartition_0:1.0 idma0"
    (file "/workspace/finn/build/vivado_zynq_proj_9_hyc85d/ip_config.tcl" line 104)
INFO: [Common 17-206] Exiting Vivado at Tue Jan  4 08:20:01 2022...

When opening the log for vivado_stich_proj_687ts1e6:

WARNING: [BD 41-1753] The name 'StreamingDataflowPartition_0' you have specified is long. The Windows OS has path length limitations. It is recommended you use shorter names(less than 25 characters) to reduce the likelihood of issues when/if running on windows OS.
Wrote  : </workspace/finn/build/vivado_stitch_proj_687ts1e6/finn_vivado_stitch_proj.srcs/sources_1/bd/StreamingDataflowPartition_0/StreamingDataflowPartition_0.bd>
# create_bd_cell -type ip -vlnv xilinx.com:hls:StreamingDataflowPartition_0_IODMA_0:1.0 StreamingDataflowPartition_0_IODMA_0
ERROR: [BD 5-390] IP definition not found for VLNV: xilinx.com:hls:StreamingDataflowPartition_0_IODMA_0:1.0
ERROR: [Common 17-39] 'create_bd_cell' failed due to earlier errors.

    while executing
"create_bd_cell -type ip -vlnv xilinx.com:hls:StreamingDataflowPartition_0_IODMA_0:1.0 StreamingDataflowPartition_0_IODMA_0"
    (file "make_project.tcl" line 5)
INFO: [Common 17-206] Exiting Vivado at Tue Jan  4 08:08:03 2022...

2 replies

fpjentzsch Jan 4, 2022
Collaborator

Hi, can you dig deeper into the logs? Maybe under code_gen_ipgen_StreamingDataflowPartition_0_IODMA_0_XXX to see if there are any HLS errors?

rpitonak Jan 4, 2022

Hi, sure:

$ cat finn/build/code_gen_ipgen_StreamingDataflowPartition_0_IODMA_0__pxjxydq/vivado_hls.log


****** Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
  **** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020
  **** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

source /opt/Xilinx/Vivado/2020.1/scripts/vivado_hls/hls.tcl -notrace
INFO: [HLS 200-10] Running '/opt/Xilinx/Vivado/2020.1/bin/unwrapped/lnx64.o/vivado_hls'
/opt/Xilinx/Vivado/2020.1/tps/tcl/tcl8.5/tzdata/Europe/Dublin can't be opened.
INFO: [HLS 200-10] For user 'ubuntu' on host 'ed402c8a7552' (Linux_x86_64 version 5.4.0-1060-aws) on Tue Jan 04 08:07:11 +0000 2022
INFO: [HLS 200-10] On os Ubuntu 18.04.6 LTS
INFO: [HLS 200-10] In directory '/workspace/finn/build/code_gen_ipgen_StreamingDataflowPartition_0_IODMA_0__pxjxydq'
Sourcing Tcl script '/workspace/finn/build/code_gen_ipgen_StreamingDataflowPartition_0_IODMA_0__pxjxydq/hls_syn_StreamingDataflowPartition_0_IODMA_0.tcl'
HLS project: project_StreamingDataflowPartition_0_IODMA_0
HW source dir: /workspace/finn/build/code_gen_ipgen_StreamingDataflowPartition_0_IODMA_0__pxjxydq
INFO: [HLS 200-10] Creating and opening project '/workspace/finn/build/code_gen_ipgen_StreamingDataflowPartition_0_IODMA_0__pxjxydq/project_StreamingDataflowPartition_0_IODMA_0'.
INFO: [HLS 200-10] Adding design file '/workspace/finn/build/code_gen_ipgen_StreamingDataflowPartition_0_IODMA_0__pxjxydq/top_StreamingDataflowPartition_0_IODMA_0.cpp' to the project
INFO: [HLS 200-10] Creating and opening solution '/workspace/finn/build/code_gen_ipgen_StreamingDataflowPartition_0_IODMA_0__pxjxydq/project_StreamingDataflowPartition_0_IODMA_0/sol1'.
INFO: [HLS 200-10] Setting target device to 'xc7z020-clg400-1'
WARNING: [XFORM 203-506] Disable code size check when do loop unroll.
WARNING: [ANALYSIS 214-1] Skip long-run-time warning caused by lots of load/store instructions.
WARNING: [HLS 200-483] The 'config_rtl -auto_prefix' command is deprecated and will be removed in a future release. Use 'config_rtl -module_auto_prefix' as its replacement.
INFO: [SYN 201-201] Setting up clock 'default' with a period of 10ns.
INFO: [SCHED 204-61] Option 'relax_ii_for_timing' is enabled, will increase II to preserve clock frequency constraints.
INFO: [HLS 200-10] Analyzing design file '/workspace/finn/build/code_gen_ipgen_StreamingDataflowPartition_0_IODMA_0__pxjxydq/top_StreamingDataflowPartition_0_IODMA_0.cpp' ...
WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body: /workspace/finn/build/code_gen_ipgen_StreamingDataflowPartition_0_IODMA_0__pxjxydq/top_StreamingDataflowPartition_0_IODMA_0.cpp:25:35
WARNING: [HLS 200-471] Dataflow form checks found 1 issue(s) in file /workspace/finn/build/code_gen_ipgen_StreamingDataflowPartition_0_IODMA_0__pxjxydq/top_StreamingDataflowPartition_0_IODMA_0.cpp
INFO: [HLS 200-111] Finished Linking Time (s): cpu = 00:00:20 ; elapsed = 00:00:19 . Memory (MB): peak = 1529.258 ; gain = 1099.754 ; free physical = 1912 ; free virtual = 22918
INFO: [HLS 200-111] Finished Checking Pragmas Time (s): cpu = 00:00:20 ; elapsed = 00:00:19 . Memory (MB): peak = 1529.258 ; gain = 1099.754 ; free physical = 1912 ; free virtual = 22918
INFO: [HLS 200-10] Starting code transformations ...
INFO: [XFORM 203-603] Inlining function 'WidthAdjustedOutputStream<192u, 24u, 32768u>::operator hls::stream<ap_uint<192>, 0>&' into 'StreamingDataflowPartition_0_IODMA_0' (/workspace/finn/build/code_gen_ipgen_StreamingDataflowPartition_0_IODMA_0__pxjxydq/top_StreamingDataflowPartition_0_IODMA_0.cpp:24).
INFO: [XFORM 203-603] Inlining function 'WidthAdjustedOutputStream<64u, 192u, 98304u>::operator hls::stream<ap_uint<64>, 0>&' into 'StreamingDataflowPartition_0_IODMA_0' (/workspace/finn/build/code_gen_ipgen_StreamingDataflowPartition_0_IODMA_0__pxjxydq/top_StreamingDataflowPartition_0_IODMA_0.cpp:25).
INFO: [HLS 200-111] Finished Standard Transforms Time (s): cpu = 00:00:21 ; elapsed = 00:00:21 . Memory (MB): peak = 1529.258 ; gain = 1099.754 ; free physical = 1907 ; free virtual = 22913
INFO: [HLS 200-10] Checking synthesizability ...
INFO: [HLS 200-111] Finished Checking Synthesizability Time (s): cpu = 00:00:21 ; elapsed = 00:00:21 . Memory (MB): peak = 1529.258 ; gain = 1099.754 ; free physical = 1902 ; free virtual = 22909
INFO: [XFORM 203-712] Applying dataflow to function 'StreamingDataflowPartition_0_IODMA_0', detected/extracted 3 process function(s):
	 'Mem2Stream_Batch<64u, 786432u>'
	 'StreamingDataWidthConverter_Batch<64u, 192u, 98304u>'
	 'StreamingDataWidthConverter_Batch<192u, 24u, 32768u>'.
INFO: [HLS 200-111] Finished Pre-synthesis Time (s): cpu = 00:00:21 ; elapsed = 00:00:21 . Memory (MB): peak = 1529.258 ; gain = 1099.754 ; free physical = 1877 ; free virtual = 22885
WARNING: [XFORM 203-631] Renaming function 'StreamingDataWidthConverter_Batch<64u, 192u, 98304u>' to 'StreamingDataWidthCo' (/workspace/finn-hlslib/streamtools.h:468:46)
WARNING: [XFORM 203-631] Renaming function 'StreamingDataWidthConverter_Batch<192u, 24u, 32768u>' to 'StreamingDataWidthCo.1' (/workspace/finn-hlslib/streamtools.h:468:46)
WARNING: [XFORM 203-631] Renaming function 'Mem2Stream_Batch<64u, 786432u>' to 'Mem2Stream_Batch' (/workspace/finn-hlslib/dma.h:22:7)
WARNING: [XFORM 203-631] Renaming function 'Mem2Stream<64u, 786432u>' to 'Mem2Stream' (/workspace/finn-hlslib/dma.h:140:42)
WARNING: [XFORM 203-631] Renaming function 'Mem2Stream<64u, 12582912u>' to 'Mem2Stream.1' (/workspace/finn-hlslib/dma.h:140:42)
INFO: [HLS 200-444] Inferring multiple bus burst read of a total cumulative length 98304 on port 'in.V' (/workspace/finn-hlslib/dma.h:142:30). These data requests might be further partitioned to multiple requests during RTL generation, based on max_read_burst_length or max_write_burst_length settings.
INFO: [HLS 200-444] Inferring multiple bus burst read of a total cumulative length 1572864 on port 'in.V' (/workspace/finn-hlslib/dma.h:142:30). These data requests might be further partitioned to multiple requests during RTL generation, based on max_read_burst_length or max_write_burst_length settings.
INFO: [HLS 200-111] Finished Architecture Synthesis Time (s): cpu = 00:00:22 ; elapsed = 00:00:22 . Memory (MB): peak = 1529.258 ; gain = 1099.754 ; free physical = 1832 ; free virtual = 22840
INFO: [HLS 200-10] Starting hardware synthesis ...
INFO: [HLS 200-10] Synthesizing 'StreamingDataflowPartition_0_IODMA_0' ...
WARNING: [SYN 201-103] Legalizing function name 'Mem2Stream.1' to 'Mem2Stream_1'.
WARNING: [SYN 201-103] Legalizing function name 'StreamingDataWidthCo.1' to 'StreamingDataWidthCo_1'.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'Mem2Stream'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
INFO: [SCHED 204-61] Pipelining loop 'Loop 1'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111]  Elapsed time: 21.65 seconds; current allocated memory: 171.016 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111]  Elapsed time: 0.03 seconds; current allocated memory: 171.194 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'Mem2Stream_1'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
INFO: [SCHED 204-61] Pipelining loop 'Loop 1'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111]  Elapsed time: 0.06 seconds; current allocated memory: 171.312 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111]  Elapsed time: 0.02 seconds; current allocated memory: 171.444 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'Mem2Stream_Batch'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111]  Elapsed time: 0.04 seconds; current allocated memory: 171.579 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111]  Elapsed time: 0.02 seconds; current allocated memory: 171.746 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'StreamingDataWidthCo'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
INFO: [SCHED 204-61] Pipelining loop 'Loop 1'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111]  Elapsed time: 0.11 seconds; current allocated memory: 171.928 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111]  Elapsed time: 0.02 seconds; current allocated memory: 172.111 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'StreamingDataWidthCo_1'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
INFO: [SCHED 204-61] Pipelining loop 'Loop 1'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111]  Elapsed time: 0.08 seconds; current allocated memory: 172.239 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111]  Elapsed time: 0.02 seconds; current allocated memory: 172.401 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'StreamingDataflowPartition_0_IODMA_0'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111]  Elapsed time: 0.03 seconds; current allocated memory: 172.483 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111]  Elapsed time: 0.04 seconds; current allocated memory: 172.718 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'Mem2Stream'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [RTGEN 206-100] Finished creating RTL model for 'Mem2Stream'.
INFO: [HLS 200-111]  Elapsed time: 0.05 seconds; current allocated memory: 173.153 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'Mem2Stream_1'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [RTGEN 206-100] Finished creating RTL model for 'Mem2Stream_1'.
INFO: [HLS 200-111]  Elapsed time: 0.06 seconds; current allocated memory: 174.064 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'Mem2Stream_Batch'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [RTGEN 206-100] Finished creating RTL model for 'Mem2Stream_Batch'.
INFO: [HLS 200-111]  Elapsed time: 0.07 seconds; current allocated memory: 175.181 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'StreamingDataWidthCo'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [RTGEN 206-100] Finished creating RTL model for 'StreamingDataWidthCo'.
INFO: [HLS 200-111]  Elapsed time: 0.08 seconds; current allocated memory: 176.154 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'StreamingDataWidthCo_1'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [RTGEN 206-100] Finished creating RTL model for 'StreamingDataWidthCo_1'.
INFO: [HLS 200-111]  Elapsed time: 0.08 seconds; current allocated memory: 177.143 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'StreamingDataflowPartition_0_IODMA_0'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [RTGEN 206-500] Setting interface mode on port 'StreamingDataflowPartition_0_IODMA_0/gmem' to 'm_axi'.
INFO: [RTGEN 206-500] Setting interface mode on port 'StreamingDataflowPartition_0_IODMA_0/in0_V' to 's_axilite & ap_none'.
INFO: [RTGEN 206-500] Setting interface mode on port 'StreamingDataflowPartition_0_IODMA_0/out_V_V' to 'axis' (register, both mode).
INFO: [RTGEN 206-500] Setting interface mode on port 'StreamingDataflowPartition_0_IODMA_0/numReps' to 's_axilite & ap_none'.
INFO: [RTGEN 206-500] Setting interface mode on function 'StreamingDataflowPartition_0_IODMA_0' to 's_axilite & ap_ctrl_hs'.
INFO: [RTGEN 206-100] Bundling port 'return', 'in0_V' and 'numReps' to AXI-Lite port control.
INFO: [SYN 201-210] Renamed object name 'start_for_StreamingDataWidthCo_U0' to 'start_for_Streamibkb' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'start_for_StreamingDataWidthCo_1_U0' to 'start_for_Streamicud' due to the length limit 20
INFO: [RTGEN 206-100] Finished creating RTL model for 'StreamingDataflowPartition_0_IODMA_0'.
INFO: [HLS 200-111]  Elapsed time: 0.09 seconds; current allocated memory: 178.562 MB.
INFO: [HLS 200-790] **** Loop Constraint Status: All loop constraints were satisfied.
INFO: [HLS 200-789] **** Estimated Fmax: 114.29 MHz
INFO: [RTMG 210-285] Implementing FIFO 'dwc_intfw_m_buffer_V_U(StreamingDataflowPartition_0_IODMA_0_fifo_w64_d2_A)' using Shift Registers.
INFO: [RTMG 210-285] Implementing FIFO 'numReps_c_U(StreamingDataflowPartition_0_IODMA_0_fifo_w32_d2_A)' using Shift Registers.
INFO: [RTMG 210-285] Implementing FIFO 'dwc_lcm_m_buffer_V_V_U(StreamingDataflowPartition_0_IODMA_0_fifo_w192_d2_A)' using Shift Registers.
INFO: [RTMG 210-285] Implementing FIFO 'numReps_c10_U(StreamingDataflowPartition_0_IODMA_0_fifo_w32_d2_A)' using Shift Registers.
INFO: [RTMG 210-285] Implementing FIFO 'start_for_Streamibkb_U(StreamingDataflowPartition_0_IODMA_0_start_for_Streamibkb)' using Shift Registers.
INFO: [RTMG 210-285] Implementing FIFO 'start_for_Streamicud_U(StreamingDataflowPartition_0_IODMA_0_start_for_Streamicud)' using Shift Registers.
INFO: [HLS 200-111] Finished generating all RTL models Time (s): cpu = 00:00:24 ; elapsed = 00:00:24 . Memory (MB): peak = 1529.258 ; gain = 1099.754 ; free physical = 1807 ; free virtual = 22821
INFO: [VHDL 208-304] Generating VHDL RTL for StreamingDataflowPartition_0_IODMA_0 with prefix StreamingDataflowPartition_0_IODMA_0_.
INFO: [VLOG 209-307] Generating Verilog RTL for StreamingDataflowPartition_0_IODMA_0 with prefix StreamingDataflowPartition_0_IODMA_0_.
INFO: [IMPL 213-8] Exporting RTL as a Vivado IP.

****** Vivado v2020.1 (64-bit)
  **** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020
  **** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

source run_ippack.tcl -notrace
bad lexical cast: source type value could not be interpreted as target
    while executing
"rdi::set_property core_revision 2201040807 {component component_1}"
    invoked from within
"set_property core_revision $Revision $core"
    (file "run_ippack.tcl" line 1117)
INFO: [Common 17-206] Exiting Vivado at Tue Jan  4 08:07:48 2022...
ERROR: [IMPL 213-28] Failed to generate IP.
command 'ap_source' returned error code
    while executing
"source /workspace/finn/build/code_gen_ipgen_StreamingDataflowPartition_0_IODMA_0__pxjxydq/hls_syn_StreamingDataflowPartition_0_IODMA_0.tcl"
    invoked from within
"hls::main /workspace/finn/build/code_gen_ipgen_StreamingDataflowPartition_0_IODMA_0__pxjxydq/hls_syn_StreamingDataflowPartition_0_IODMA_0.tcl"
    ("uplevel" body line 1)
    invoked from within
"uplevel 1 hls::main {*}$args"
    (procedure "hls_proc" line 5)
    invoked from within
"hls_proc $argv"
INFO: [HLS 200-112] Total elapsed time: 37.21 seconds; peak allocated memory: 178.562 MB.
INFO: [Common 17-206] Exiting vivado_hls at Tue Jan  4 08:07:48 2022..

Seems that it happened to more users recently (TL;DR seems like the year 2022 in date caused int32 overflow, a possible workaround is to change the system clock back to 2021):
https://support.xilinx.com/s/question/0D52E00006uxy49SAA/vivado-fails-to-export-ips-with-the-error-message-bad-lexical-cast-source-type-value-could-not-be-interpreted-as-target?language=en_US

shashwat1198 · 2022-01-04T11:33:29Z

shashwat1198
Jan 4, 2022
Author

Yes, I was able to build the hardware 10 days ago and this came up yesterday!

Yes a lot of other users are facing the same issue.

I reverted the date back to 2021 and it worked!

Thank you for you response,
Shashwat

1 reply

maltanar Jan 10, 2022
Maintainer

There's also an official patch from Xilinx now, which should fix the issue: https://support.xilinx.com/s/article/76960?language=en_US

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