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`HasParent` * PLIO (`PLIO`) * NOC (`NOC`) * Trace (`Trace`) -* Ctrl (`Ctrl`){{% /markdown %}} +* TileControl (`TileControl`){{% /markdown %}} source_channel::mlir::IntegerAttr32-bit signless integer attribute whose minimum value is 0 dest_bundlexilinx::AIE::WireBundleAttr
Bundle of wires{{% markdown %}}Enum cases: * Core (`Core`) @@ -264,7 +264,7 @@ Traits: `HasParent` * PLIO (`PLIO`) * NOC (`NOC`) * Trace (`Trace`) -* Ctrl (`Ctrl`){{% /markdown %}}
+* TileControl (`TileControl`){{% /markdown %}} dest_channel::mlir::IntegerAttr32-bit signless integer attribute whose minimum value is 0 @@ -797,7 +797,7 @@ Example: * PLIO (`PLIO`) * NOC (`NOC`) * Trace (`Trace`) -* Ctrl (`Ctrl`){{% /markdown %}} +* TileControl (`TileControl`){{% /markdown %}} source_channel::mlir::IntegerAttr32-bit signless integer attribute whose minimum value is 0 dest_bundlexilinx::AIE::WireBundleAttr
Bundle of wires{{% markdown %}}Enum cases: * Core (`Core`) @@ -810,7 +810,7 @@ Example: * PLIO (`PLIO`) * NOC (`NOC`) * Trace (`Trace`) -* Ctrl (`Ctrl`){{% /markdown %}}
+* TileControl (`TileControl`){{% /markdown %}} dest_channel::mlir::IntegerAttr32-bit signless integer attribute whose minimum value is 0 @@ -982,7 +982,7 @@ Interfaces: `InferTypeOpInterface` * PLIO (`PLIO`) * NOC (`NOC`) * Trace (`Trace`) -* Ctrl (`Ctrl`){{% /markdown %}} +* TileControl (`TileControl`){{% /markdown %}} dest_channel::mlir::IntegerAttr32-bit signless integer attribute whose minimum value is 0 keep_pkt_header::mlir::BoolAttrbool attribute @@ -1568,7 +1568,7 @@ Traits: `HasParent` * PLIO (`PLIO`) * NOC (`NOC`) * Trace (`Trace`) -* Ctrl (`Ctrl`){{% /markdown %}} +* TileControl (`TileControl`){{% /markdown %}} channel::mlir::IntegerAttr32-bit signless integer attribute whose minimum value is 0 @@ -1657,7 +1657,7 @@ Traits: `SingleBlockImplicitTerminator`, `SingleBlock` * PLIO (`PLIO`) * NOC (`NOC`) * Trace (`Trace`) -* Ctrl (`Ctrl`){{% /markdown %}} +* TileControl (`TileControl`){{% /markdown %}} source_channel::mlir::IntegerAttr32-bit signless integer attribute whose minimum value is 0 @@ -1695,7 +1695,7 @@ Traits: `HasParent` * PLIO (`PLIO`) * NOC (`NOC`) * Trace (`Trace`) -* Ctrl (`Ctrl`){{% /markdown %}} +* TileControl (`TileControl`){{% /markdown %}} channel::mlir::IntegerAttr32-bit signless integer attribute whose minimum value is 0 @@ -2166,7 +2166,7 @@ represented by an [aie.tile](#aietile-aietileop) operation. * PLIO (`PLIO`) * NOC (`NOC`) * Trace (`Trace`) -* Ctrl (`Ctrl`){{% /markdown %}} +* TileControl (`TileControl`){{% /markdown %}} dest_bundlexilinx::AIE::WireBundleAttr
Bundle of wires{{% markdown %}}Enum cases: * Core (`Core`) * DMA (`DMA`) @@ -2178,7 +2178,7 @@ represented by an [aie.tile](#aietile-aietileop) operation. * PLIO (`PLIO`) * NOC (`NOC`) * Trace (`Trace`) -* Ctrl (`Ctrl`){{% /markdown %}}
+* TileControl (`TileControl`){{% /markdown %}} #### Operands: @@ -2445,5 +2445,5 @@ Bundle of wires | PLIO | `7` | PLIO | | NOC | `8` | NOC | | Trace | `9` | Trace | -| Ctrl | `10` | Ctrl | +| TileControl | `10` | TileControl | diff --git a/AIEVecAIE1Dialect.md b/AIEVecAIE1Dialect.md index eff1a62b41..e90160e3ed 100644 --- a/AIEVecAIE1Dialect.md +++ b/AIEVecAIE1Dialect.md @@ -380,5 +380,5 @@ Bundle of wires | PLIO | `7` | PLIO | | NOC | `8` | NOC | | Trace | `9` | Trace | -| Ctrl | `10` | Ctrl | +| TileControl | `10` | TileControl | diff --git a/AIEVecDialect.md b/AIEVecDialect.md index 8ea37dfede..9f743bd5b7 100644 --- a/AIEVecDialect.md +++ b/AIEVecDialect.md @@ -1481,5 +1481,5 @@ Bundle of wires | PLIO | `7` | PLIO | | NOC | `8` | NOC | | Trace | `9` | Trace | -| Ctrl | `10` | Ctrl | +| TileControl | `10` | TileControl | diff --git a/AIEXDialect.md b/AIEXDialect.md index 6cb7d432c0..e5fc2893bc 100644 --- a/AIEXDialect.md +++ b/AIEXDialect.md @@ -41,7 +41,7 @@ Traits: `HasParent` * PLIO (`PLIO`) * NOC (`NOC`) * Trace (`Trace`) -* Ctrl (`Ctrl`){{% /markdown %}} +* TileControl (`TileControl`){{% /markdown %}} channel::mlir::IntegerAttr32-bit signless integer attribute @@ -128,7 +128,7 @@ Traits: `SingleBlockImplicitTerminator`, `SingleBlock` * PLIO (`PLIO`) * NOC (`NOC`) * Trace (`Trace`) -* Ctrl (`Ctrl`){{% /markdown %}} +* TileControl (`TileControl`){{% /markdown %}} channel::mlir::IntegerAttr32-bit signless integer attribute @@ -179,7 +179,7 @@ Example: * PLIO (`PLIO`) * NOC (`NOC`) * Trace (`Trace`) -* Ctrl (`Ctrl`){{% /markdown %}} +* TileControl (`TileControl`){{% /markdown %}} sourceChannel::mlir::IntegerAttr32-bit signless integer attribute destBundlexilinx::AIE::WireBundleAttr
Bundle of wires{{% markdown %}}Enum cases: * Core (`Core`) @@ -192,7 +192,7 @@ Example: * PLIO (`PLIO`) * NOC (`NOC`) * Trace (`Trace`) -* Ctrl (`Ctrl`){{% /markdown %}}
+* TileControl (`TileControl`){{% /markdown %}} destChannel::mlir::IntegerAttr32-bit signless integer attribute @@ -645,7 +645,7 @@ Traits: `HasParent` * PLIO (`PLIO`) * NOC (`NOC`) * Trace (`Trace`) -* Ctrl (`Ctrl`){{% /markdown %}} +* TileControl (`TileControl`){{% /markdown %}} channel::mlir::IntegerAttr32-bit signless integer attribute @@ -702,7 +702,7 @@ Traits: `SingleBlockImplicitTerminator`, `SingleBlock` * PLIO (`PLIO`) * NOC (`NOC`) * Trace (`Trace`) -* Ctrl (`Ctrl`){{% /markdown %}} +* TileControl (`TileControl`){{% /markdown %}} channel::mlir::IntegerAttr32-bit signless integer attribute @@ -1184,7 +1184,7 @@ A route operation that routes one herd to another. * PLIO (`PLIO`) * NOC (`NOC`) * Trace (`Trace`) -* Ctrl (`Ctrl`){{% /markdown %}} +* TileControl (`TileControl`){{% /markdown %}} sourceChannel::mlir::IntegerAttr32-bit signless integer attribute destBundlexilinx::AIE::WireBundleAttr
Bundle of wires{{% markdown %}}Enum cases: * Core (`Core`) @@ -1197,7 +1197,7 @@ A route operation that routes one herd to another. * PLIO (`PLIO`) * NOC (`NOC`) * Trace (`Trace`) -* Ctrl (`Ctrl`){{% /markdown %}}
+* TileControl (`TileControl`){{% /markdown %}} destChannel::mlir::IntegerAttr32-bit signless integer attribute @@ -1444,5 +1444,5 @@ Bundle of wires | PLIO | `7` | PLIO | | NOC | `8` | NOC | | Trace | `9` | Trace | -| Ctrl | `10` | Ctrl | +| TileControl | `10` | TileControl | diff --git a/doxygen/html/ADFDialect_8cpp.html b/doxygen/html/ADFDialect_8cpp.html index ad5f1b3a08..851cdbaf8a 100644 --- a/doxygen/html/ADFDialect_8cpp.html +++ b/doxygen/html/ADFDialect_8cpp.html @@ -158,7 +158,7 @@

-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/ADFDialect_8cpp_source.html b/doxygen/html/ADFDialect_8cpp_source.html index 871e204cea..5766550e8a 100644 --- a/doxygen/html/ADFDialect_8cpp_source.html +++ b/doxygen/html/ADFDialect_8cpp_source.html @@ -103,7 +103,7 @@
-Generated on Fri Jan 10 2025 11:12:31 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:56 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/ADFDialect_8h.html b/doxygen/html/ADFDialect_8h.html index e73f769134..8706f3942c 100644 --- a/doxygen/html/ADFDialect_8h.html +++ b/doxygen/html/ADFDialect_8h.html @@ -144,7 +144,7 @@

-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/ADFDialect_8h_source.html b/doxygen/html/ADFDialect_8h_source.html index c565521837..55096c9921 100644 --- a/doxygen/html/ADFDialect_8h_source.html +++ b/doxygen/html/ADFDialect_8h_source.html @@ -91,7 +91,7 @@
-Generated on Fri Jan 10 2025 11:12:31 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:56 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/ADFGenerateCppGraph_8cpp.html b/doxygen/html/ADFGenerateCppGraph_8cpp.html index f25c349c4a..a9544dc9ae 100644 --- a/doxygen/html/ADFGenerateCppGraph_8cpp.html +++ b/doxygen/html/ADFGenerateCppGraph_8cpp.html @@ -154,7 +154,7 @@

-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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diff --git a/doxygen/html/ADFOps_8h.html b/doxygen/html/ADFOps_8h.html index 00fb4fea5c..a3d897068d 100644 --- a/doxygen/html/ADFOps_8h.html +++ b/doxygen/html/ADFOps_8h.html @@ -130,7 +130,7 @@

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diff --git a/doxygen/html/ADFOps_8h_source.html b/doxygen/html/ADFOps_8h_source.html index 7435e01beb..d2e50788f7 100644 --- a/doxygen/html/ADFOps_8h_source.html +++ b/doxygen/html/ADFOps_8h_source.html @@ -78,7 +78,7 @@
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-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/AIEAssignBufferDescriptorIDs_8cpp_source.html b/doxygen/html/AIEAssignBufferDescriptorIDs_8cpp_source.html index d3e1572fac..de5134f6d8 100644 --- a/doxygen/html/AIEAssignBufferDescriptorIDs_8cpp_source.html +++ b/doxygen/html/AIEAssignBufferDescriptorIDs_8cpp_source.html @@ -280,7 +280,7 @@
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:56 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/AIEAssignBufferDescriptorIDs_8h.html b/doxygen/html/AIEAssignBufferDescriptorIDs_8h.html index b0bf0d5834..424cced830 100644 --- a/doxygen/html/AIEAssignBufferDescriptorIDs_8h.html +++ b/doxygen/html/AIEAssignBufferDescriptorIDs_8h.html @@ -96,7 +96,7 @@
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diff --git a/doxygen/html/AIEAssignBuffers_8cpp.html b/doxygen/html/AIEAssignBuffers_8cpp.html index 1e6557292b..dfeba8d92c 100644 --- a/doxygen/html/AIEAssignBuffers_8cpp.html +++ b/doxygen/html/AIEAssignBuffers_8cpp.html @@ -644,7 +644,7 @@

-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/AIEAssignBuffers_8cpp_source.html b/doxygen/html/AIEAssignBuffers_8cpp_source.html index bd28b4350c..c9d1422d5c 100644 --- a/doxygen/html/AIEAssignBuffers_8cpp_source.html +++ b/doxygen/html/AIEAssignBuffers_8cpp_source.html @@ -587,7 +587,7 @@
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:56 for MLIR-AIE by doxygen 1.9.1
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-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/AIEAssignLockIDs_8cpp_source.html b/doxygen/html/AIEAssignLockIDs_8cpp_source.html index 73423a403d..470002e6f3 100644 --- a/doxygen/html/AIEAssignLockIDs_8cpp_source.html +++ b/doxygen/html/AIEAssignLockIDs_8cpp_source.html @@ -171,7 +171,7 @@
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diff --git a/doxygen/html/AIECanonicalizeDevice_8cpp_source.html b/doxygen/html/AIECanonicalizeDevice_8cpp_source.html index f67457d504..b22963ac3c 100644 --- a/doxygen/html/AIECanonicalizeDevice_8cpp_source.html +++ b/doxygen/html/AIECanonicalizeDevice_8cpp_source.html @@ -124,7 +124,7 @@
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diff --git a/doxygen/html/AIECreateBroadcastPacket_8cpp_source.html b/doxygen/html/AIECreateBroadcastPacket_8cpp_source.html index eb4ade55ec..ea324e9020 100644 --- a/doxygen/html/AIECreateBroadcastPacket_8cpp_source.html +++ b/doxygen/html/AIECreateBroadcastPacket_8cpp_source.html @@ -179,7 +179,7 @@
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diff --git a/doxygen/html/AIECreateCores_8cpp.html b/doxygen/html/AIECreateCores_8cpp.html index 00a1b21dde..8367b533c5 100644 --- a/doxygen/html/AIECreateCores_8cpp.html +++ b/doxygen/html/AIECreateCores_8cpp.html @@ -125,7 +125,7 @@
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diff --git a/doxygen/html/AIECreateCores_8cpp_source.html b/doxygen/html/AIECreateCores_8cpp_source.html index e8b6ebdb28..864327b33c 100644 --- a/doxygen/html/AIECreateCores_8cpp_source.html +++ b/doxygen/html/AIECreateCores_8cpp_source.html @@ -329,7 +329,7 @@
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diff --git a/doxygen/html/AIECreateLocks_8cpp.html b/doxygen/html/AIECreateLocks_8cpp.html index f21660fa1b..d7dd3d6f1a 100644 --- a/doxygen/html/AIECreateLocks_8cpp.html +++ b/doxygen/html/AIECreateLocks_8cpp.html @@ -147,7 +147,7 @@

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diff --git a/doxygen/html/AIECreateLocks_8cpp_source.html b/doxygen/html/AIECreateLocks_8cpp_source.html index bac3e98e40..b8377b3cc6 100644 --- a/doxygen/html/AIECreateLocks_8cpp_source.html +++ b/doxygen/html/AIECreateLocks_8cpp_source.html @@ -314,7 +314,7 @@
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diff --git a/doxygen/html/AIECtrlPacketToDma_8cpp.html b/doxygen/html/AIECtrlPacketToDma_8cpp.html index 0c34f32a26..51d912f0d1 100644 --- a/doxygen/html/AIECtrlPacketToDma_8cpp.html +++ b/doxygen/html/AIECtrlPacketToDma_8cpp.html @@ -140,7 +140,7 @@

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diff --git a/doxygen/html/AIECtrlPacketToDma_8cpp_source.html b/doxygen/html/AIECtrlPacketToDma_8cpp_source.html index 69fbeb953c..2caa11d2c2 100644 --- a/doxygen/html/AIECtrlPacketToDma_8cpp_source.html +++ b/doxygen/html/AIECtrlPacketToDma_8cpp_source.html @@ -237,7 +237,7 @@
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diff --git a/doxygen/html/AIEDMATasksToNPU_8cpp.html b/doxygen/html/AIEDMATasksToNPU_8cpp.html index 30d3749352..a517f1138e 100644 --- a/doxygen/html/AIEDMATasksToNPU_8cpp.html +++ b/doxygen/html/AIEDMATasksToNPU_8cpp.html @@ -123,7 +123,7 @@
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diff --git a/doxygen/html/AIEDMATasksToNPU_8cpp_source.html b/doxygen/html/AIEDMATasksToNPU_8cpp_source.html index 16080e3709..a26e720e35 100644 --- a/doxygen/html/AIEDMATasksToNPU_8cpp_source.html +++ b/doxygen/html/AIEDMATasksToNPU_8cpp_source.html @@ -630,7 +630,7 @@
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diff --git a/doxygen/html/AIEDialect_8cpp.html b/doxygen/html/AIEDialect_8cpp.html index 50000ab5d8..ee77f5d9ea 100644 --- a/doxygen/html/AIEDialect_8cpp.html +++ b/doxygen/html/AIEDialect_8cpp.html @@ -330,7 +330,7 @@

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diff --git a/doxygen/html/AIEDialect_8cpp_source.html b/doxygen/html/AIEDialect_8cpp_source.html index a348d3ca74..1db93b7ee0 100644 --- a/doxygen/html/AIEDialect_8cpp_source.html +++ b/doxygen/html/AIEDialect_8cpp_source.html @@ -2501,7 +2501,7 @@
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diff --git a/doxygen/html/AIEDialect_8h.html b/doxygen/html/AIEDialect_8h.html index b69b2655fb..0ff1c06aff 100644 --- a/doxygen/html/AIEDialect_8h.html +++ b/doxygen/html/AIEDialect_8h.html @@ -270,7 +270,7 @@

-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/AIEDialect_8h_source.html b/doxygen/html/AIEDialect_8h_source.html index 3fbc46c3d5..7133987ff8 100644 --- a/doxygen/html/AIEDialect_8h_source.html +++ b/doxygen/html/AIEDialect_8h_source.html @@ -536,7 +536,7 @@
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diff --git a/doxygen/html/AIEDmaToNpu_8cpp.html b/doxygen/html/AIEDmaToNpu_8cpp.html index 114dcb87a7..9f91307d21 100644 --- a/doxygen/html/AIEDmaToNpu_8cpp.html +++ b/doxygen/html/AIEDmaToNpu_8cpp.html @@ -105,7 +105,7 @@
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diff --git a/doxygen/html/AIEDmaToNpu_8cpp_source.html b/doxygen/html/AIEDmaToNpu_8cpp_source.html index 2d93a5c1de..bbb10a84d2 100644 --- a/doxygen/html/AIEDmaToNpu_8cpp_source.html +++ b/doxygen/html/AIEDmaToNpu_8cpp_source.html @@ -845,7 +845,7 @@
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diff --git a/doxygen/html/AIEEnums_8h.html b/doxygen/html/AIEEnums_8h.html index 82738a62af..5f4ad178c6 100644 --- a/doxygen/html/AIEEnums_8h.html +++ b/doxygen/html/AIEEnums_8h.html @@ -133,7 +133,7 @@
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diff --git a/doxygen/html/AIEEnums_8h_source.html b/doxygen/html/AIEEnums_8h_source.html index 3a5436fef6..67964d46ca 100644 --- a/doxygen/html/AIEEnums_8h_source.html +++ b/doxygen/html/AIEEnums_8h_source.html @@ -75,7 +75,7 @@
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diff --git a/doxygen/html/AIEFindFlows_8cpp.html b/doxygen/html/AIEFindFlows_8cpp.html index 6d5ef339d1..ae61c9d331 100644 --- a/doxygen/html/AIEFindFlows_8cpp.html +++ b/doxygen/html/AIEFindFlows_8cpp.html @@ -212,7 +212,7 @@

-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/AIEFindFlows_8cpp_source.html b/doxygen/html/AIEFindFlows_8cpp_source.html index 9bccab1d45..c907441dcf 100644 --- a/doxygen/html/AIEFindFlows_8cpp_source.html +++ b/doxygen/html/AIEFindFlows_8cpp_source.html @@ -377,7 +377,7 @@
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:56 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/AIEFlowsToJSON_8cpp.html b/doxygen/html/AIEFlowsToJSON_8cpp.html index e3eaa745db..b937ee6fd8 100644 --- a/doxygen/html/AIEFlowsToJSON_8cpp.html +++ b/doxygen/html/AIEFlowsToJSON_8cpp.html @@ -129,7 +129,7 @@
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/AIEFlowsToJSON_8cpp_source.html b/doxygen/html/AIEFlowsToJSON_8cpp_source.html index 8b34002de1..e434140430 100644 --- a/doxygen/html/AIEFlowsToJSON_8cpp_source.html +++ b/doxygen/html/AIEFlowsToJSON_8cpp_source.html @@ -517,7 +517,7 @@
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:56 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/AIEGenerateColumnControlOverlay_8cpp.html b/doxygen/html/AIEGenerateColumnControlOverlay_8cpp.html index ab49fbf197..9e2e58e648 100644 --- a/doxygen/html/AIEGenerateColumnControlOverlay_8cpp.html +++ b/doxygen/html/AIEGenerateColumnControlOverlay_8cpp.html @@ -296,7 +296,7 @@

-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/AIEGenerateColumnControlOverlay_8cpp_source.html b/doxygen/html/AIEGenerateColumnControlOverlay_8cpp_source.html index d8391ef090..4b81955331 100644 --- a/doxygen/html/AIEGenerateColumnControlOverlay_8cpp_source.html +++ b/doxygen/html/AIEGenerateColumnControlOverlay_8cpp_source.html @@ -276,7 +276,7 @@
221 
222  generatePacketFlowsForControl(
223  builder, device, shimTile, AIE::WireBundle::South, tilesOnCol,
-
224  AIE::WireBundle::Ctrl, 0, tileIDMap, false);
+
224  AIE::WireBundle::TileControl, 0, tileIDMap, false);
225  }
226  if (clRouteShimDmaToTileCTRL) {
227  // Get all tile ops on column col
@@ -289,7 +289,7 @@
234 
235  generatePacketFlowsForControl(
236  builder, device, shimTile, AIE::WireBundle::DMA, tilesOnCol,
-
237  AIE::WireBundle::Ctrl, 0, tileIDMap, true);
+
237  AIE::WireBundle::TileControl, 0, tileIDMap, true);
238  }
239  }
240  }
@@ -503,7 +503,7 @@
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diff --git a/doxygen/html/AIEGenerateColumnControlOverlay_8h.html b/doxygen/html/AIEGenerateColumnControlOverlay_8h.html index a4ab511371..1004c98fa6 100644 --- a/doxygen/html/AIEGenerateColumnControlOverlay_8h.html +++ b/doxygen/html/AIEGenerateColumnControlOverlay_8h.html @@ -204,7 +204,7 @@

-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/AIEGenerateColumnControlOverlay_8h_source.html b/doxygen/html/AIEGenerateColumnControlOverlay_8h_source.html index 5983b23c44..ddd5fab59d 100644 --- a/doxygen/html/AIEGenerateColumnControlOverlay_8h_source.html +++ b/doxygen/html/AIEGenerateColumnControlOverlay_8h_source.html @@ -97,7 +97,7 @@
-Generated on Fri Jan 10 2025 11:12:31 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:56 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/AIEHerdRouting_8cpp.html b/doxygen/html/AIEHerdRouting_8cpp.html index 5c7b5b2fc7..6fb5b3769c 100644 --- a/doxygen/html/AIEHerdRouting_8cpp.html +++ b/doxygen/html/AIEHerdRouting_8cpp.html @@ -271,7 +271,7 @@

-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/AIEHerdRouting_8cpp_source.html b/doxygen/html/AIEHerdRouting_8cpp_source.html index f9ff53e0e9..3e62fba80b 100644 --- a/doxygen/html/AIEHerdRouting_8cpp_source.html +++ b/doxygen/html/AIEHerdRouting_8cpp_source.html @@ -415,7 +415,7 @@
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:56 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/AIELLVMLink_8cpp.html b/doxygen/html/AIELLVMLink_8cpp.html index 3d10ce0810..d36670c1f4 100644 --- a/doxygen/html/AIELLVMLink_8cpp.html +++ b/doxygen/html/AIELLVMLink_8cpp.html @@ -187,7 +187,7 @@

-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/AIELLVMLink_8cpp_source.html b/doxygen/html/AIELLVMLink_8cpp_source.html index c2f82bd89e..e60c1c5c5f 100644 --- a/doxygen/html/AIELLVMLink_8cpp_source.html +++ b/doxygen/html/AIELLVMLink_8cpp_source.html @@ -206,7 +206,7 @@
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:56 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/AIELocalizeLocks_8cpp.html b/doxygen/html/AIELocalizeLocks_8cpp.html index 6bb1f0926a..023c68a543 100644 --- a/doxygen/html/AIELocalizeLocks_8cpp.html +++ b/doxygen/html/AIELocalizeLocks_8cpp.html @@ -132,7 +132,7 @@

-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/AIELocalizeLocks_8cpp_source.html b/doxygen/html/AIELocalizeLocks_8cpp_source.html index adeff85885..2aaeeda50f 100644 --- a/doxygen/html/AIELocalizeLocks_8cpp_source.html +++ b/doxygen/html/AIELocalizeLocks_8cpp_source.html @@ -155,7 +155,7 @@
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:56 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/AIELowerCascadeFlows_8cpp.html b/doxygen/html/AIELowerCascadeFlows_8cpp.html index 31ceead9c4..85bf4e8b7d 100644 --- a/doxygen/html/AIELowerCascadeFlows_8cpp.html +++ b/doxygen/html/AIELowerCascadeFlows_8cpp.html @@ -135,7 +135,7 @@

-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/AIELowerCascadeFlows_8cpp_source.html b/doxygen/html/AIELowerCascadeFlows_8cpp_source.html index a5246e1edb..1698f6280a 100644 --- a/doxygen/html/AIELowerCascadeFlows_8cpp_source.html +++ b/doxygen/html/AIELowerCascadeFlows_8cpp_source.html @@ -163,7 +163,7 @@
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:56 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/AIELowerMemcpy_8cpp.html b/doxygen/html/AIELowerMemcpy_8cpp.html index 9e6c26ce18..ab47805325 100644 --- a/doxygen/html/AIELowerMemcpy_8cpp.html +++ b/doxygen/html/AIELowerMemcpy_8cpp.html @@ -131,7 +131,7 @@
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/AIELowerMemcpy_8cpp_source.html b/doxygen/html/AIELowerMemcpy_8cpp_source.html index d2c84bb40a..1f971effef 100644 --- a/doxygen/html/AIELowerMemcpy_8cpp_source.html +++ b/doxygen/html/AIELowerMemcpy_8cpp_source.html @@ -219,7 +219,7 @@
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:56 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/AIELowerMulticast_8cpp.html b/doxygen/html/AIELowerMulticast_8cpp.html index e54f398521..83e0686a53 100644 --- a/doxygen/html/AIELowerMulticast_8cpp.html +++ b/doxygen/html/AIELowerMulticast_8cpp.html @@ -144,7 +144,7 @@

-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/AIELowerMulticast_8cpp_source.html b/doxygen/html/AIELowerMulticast_8cpp_source.html index efc9245ab6..505ebf2318 100644 --- a/doxygen/html/AIELowerMulticast_8cpp_source.html +++ b/doxygen/html/AIELowerMulticast_8cpp_source.html @@ -159,7 +159,7 @@
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:56 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/AIEMaterializeBDChains_8cpp.html b/doxygen/html/AIEMaterializeBDChains_8cpp.html index 52610f5173..5d2348bd4c 100644 --- a/doxygen/html/AIEMaterializeBDChains_8cpp.html +++ b/doxygen/html/AIEMaterializeBDChains_8cpp.html @@ -129,7 +129,7 @@
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/AIEMaterializeBDChains_8cpp_source.html b/doxygen/html/AIEMaterializeBDChains_8cpp_source.html index d709b87794..c2fba08a18 100644 --- a/doxygen/html/AIEMaterializeBDChains_8cpp_source.html +++ b/doxygen/html/AIEMaterializeBDChains_8cpp_source.html @@ -222,7 +222,7 @@
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:56 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/AIENormalizeAddressSpaces_8cpp.html b/doxygen/html/AIENormalizeAddressSpaces_8cpp.html index 204dc42f86..ecb53c20fe 100644 --- a/doxygen/html/AIENormalizeAddressSpaces_8cpp.html +++ b/doxygen/html/AIENormalizeAddressSpaces_8cpp.html @@ -170,7 +170,7 @@

-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/AIENormalizeAddressSpaces_8cpp_source.html b/doxygen/html/AIENormalizeAddressSpaces_8cpp_source.html index e3ca83a963..e2c4ac29ed 100644 --- a/doxygen/html/AIENormalizeAddressSpaces_8cpp_source.html +++ b/doxygen/html/AIENormalizeAddressSpaces_8cpp_source.html @@ -144,7 +144,7 @@
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:56 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/AIEObjectFifoRegisterProcess_8cpp.html b/doxygen/html/AIEObjectFifoRegisterProcess_8cpp.html index dc9d9b0d95..3b5f871d55 100644 --- a/doxygen/html/AIEObjectFifoRegisterProcess_8cpp.html +++ b/doxygen/html/AIEObjectFifoRegisterProcess_8cpp.html @@ -144,7 +144,7 @@

-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/AIEObjectFifoRegisterProcess_8cpp_source.html b/doxygen/html/AIEObjectFifoRegisterProcess_8cpp_source.html index d99218f66f..324ae1e832 100644 --- a/doxygen/html/AIEObjectFifoRegisterProcess_8cpp_source.html +++ b/doxygen/html/AIEObjectFifoRegisterProcess_8cpp_source.html @@ -300,7 +300,7 @@
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:56 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/AIEObjectFifoStatefulTransform_8cpp.html b/doxygen/html/AIEObjectFifoStatefulTransform_8cpp.html index 112e020359..bd5f0d8431 100644 --- a/doxygen/html/AIEObjectFifoStatefulTransform_8cpp.html +++ b/doxygen/html/AIEObjectFifoStatefulTransform_8cpp.html @@ -167,7 +167,7 @@

-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/AIEObjectFifoStatefulTransform_8cpp_source.html b/doxygen/html/AIEObjectFifoStatefulTransform_8cpp_source.html index 584a20412a..57bfc1cec1 100644 --- a/doxygen/html/AIEObjectFifoStatefulTransform_8cpp_source.html +++ b/doxygen/html/AIEObjectFifoStatefulTransform_8cpp_source.html @@ -1966,7 +1966,7 @@
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:56 for MLIR-AIE by doxygen 1.9.1
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-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/AIEPasses_8h_source.html b/doxygen/html/AIEPasses_8h_source.html index 22620bda46..e8543d9c6e 100644 --- a/doxygen/html/AIEPasses_8h_source.html +++ b/doxygen/html/AIEPasses_8h_source.html @@ -175,7 +175,7 @@
-Generated on Fri Jan 10 2025 11:12:31 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:56 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/AIEPathFinder_8cpp.html b/doxygen/html/AIEPathFinder_8cpp.html index 567307c194..3b311687fc 100644 --- a/doxygen/html/AIEPathFinder_8cpp.html +++ b/doxygen/html/AIEPathFinder_8cpp.html @@ -131,7 +131,7 @@

-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/AIEPathFinder_8cpp_source.html b/doxygen/html/AIEPathFinder_8cpp_source.html index e5da0db958..a6715deabf 100644 --- a/doxygen/html/AIEPathFinder_8cpp_source.html +++ b/doxygen/html/AIEPathFinder_8cpp_source.html @@ -250,10 +250,10 @@
195  SwitchboxConnect sb = {coords};
196 
197  const std::vector<WireBundle> bundles = {
-
198  WireBundle::Core, WireBundle::DMA, WireBundle::FIFO,
-
199  WireBundle::South, WireBundle::West, WireBundle::North,
-
200  WireBundle::East, WireBundle::PLIO, WireBundle::NOC,
-
201  WireBundle::Trace, WireBundle::Ctrl};
+
198  WireBundle::Core, WireBundle::DMA, WireBundle::FIFO,
+
199  WireBundle::South, WireBundle::West, WireBundle::North,
+
200  WireBundle::East, WireBundle::PLIO, WireBundle::NOC,
+
201  WireBundle::Trace, WireBundle::TileControl};
202  for (WireBundle bundle : bundles) {
203  // get all ports into current switchbox
204  int channels =
@@ -807,7 +807,7 @@
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diff --git a/doxygen/html/AIEPathFinder_8h.html b/doxygen/html/AIEPathFinder_8h.html index 2b833bbd69..68fd882440 100644 --- a/doxygen/html/AIEPathFinder_8h.html +++ b/doxygen/html/AIEPathFinder_8h.html @@ -360,7 +360,7 @@

-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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diff --git a/doxygen/html/AIERT_8cpp.html b/doxygen/html/AIERT_8cpp.html index 8d00a40709..3c3361352c 100644 --- a/doxygen/html/AIERT_8cpp.html +++ b/doxygen/html/AIERT_8cpp.html @@ -265,7 +265,7 @@

-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/AIERT_8cpp_source.html b/doxygen/html/AIERT_8cpp_source.html index a23f31dbed..c3fab8cf09 100644 --- a/doxygen/html/AIERT_8cpp_source.html +++ b/doxygen/html/AIERT_8cpp_source.html @@ -863,7 +863,7 @@
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:56 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/AIERT_8h.html b/doxygen/html/AIERT_8h.html index 7189a8a7f8..df94406ea4 100644 --- a/doxygen/html/AIERT_8h.html +++ b/doxygen/html/AIERT_8h.html @@ -775,7 +775,7 @@

-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/AIERT_8h_source.html b/doxygen/html/AIERT_8h_source.html index d8adb72fa1..d1f1f86138 100644 --- a/doxygen/html/AIERT_8h_source.html +++ b/doxygen/html/AIERT_8h_source.html @@ -132,7 +132,7 @@
77  WIRE_BUNDLE_TO_STRM_SW_PORT_TYPE = {
78  {xilinx::AIE::WireBundle::Core, StrmSwPortType::CORE},
79  {xilinx::AIE::WireBundle::DMA, StrmSwPortType::DMA},
-
80  {xilinx::AIE::WireBundle::Ctrl, StrmSwPortType::CTRL},
+
80  {xilinx::AIE::WireBundle::TileControl, StrmSwPortType::CTRL},
81  {xilinx::AIE::WireBundle::FIFO, StrmSwPortType::FIFO},
82  {xilinx::AIE::WireBundle::South, StrmSwPortType::SOUTH},
83  {xilinx::AIE::WireBundle::West, StrmSwPortType::WEST},
@@ -318,7 +318,7 @@
-Generated on Fri Jan 10 2025 11:12:31 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:56 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/AIESubstituteShimDMAAllocations_8cpp.html b/doxygen/html/AIESubstituteShimDMAAllocations_8cpp.html index 6d51f51404..8caa9c6e35 100644 --- a/doxygen/html/AIESubstituteShimDMAAllocations_8cpp.html +++ b/doxygen/html/AIESubstituteShimDMAAllocations_8cpp.html @@ -111,7 +111,7 @@
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diff --git a/doxygen/html/AIESubstituteShimDMAAllocations_8cpp_source.html b/doxygen/html/AIESubstituteShimDMAAllocations_8cpp_source.html index 77ca9242f2..47f4e4f358 100644 --- a/doxygen/html/AIESubstituteShimDMAAllocations_8cpp_source.html +++ b/doxygen/html/AIESubstituteShimDMAAllocations_8cpp_source.html @@ -143,7 +143,7 @@
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diff --git a/doxygen/html/AIETargetAirbin_8cpp.html b/doxygen/html/AIETargetAirbin_8cpp.html index 83345ad8c2..4baa9db3fe 100644 --- a/doxygen/html/AIETargetAirbin_8cpp.html +++ b/doxygen/html/AIETargetAirbin_8cpp.html @@ -286,7 +286,7 @@

-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/AIETargetAirbin_8cpp_source.html b/doxygen/html/AIETargetAirbin_8cpp_source.html index 0e0f2f7076..9bff22d979 100644 --- a/doxygen/html/AIETargetAirbin_8cpp_source.html +++ b/doxygen/html/AIETargetAirbin_8cpp_source.html @@ -1477,7 +1477,7 @@
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:56 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/AIETargetBCF_8cpp.html b/doxygen/html/AIETargetBCF_8cpp.html index 2c559070ec..17e142b80f 100644 --- a/doxygen/html/AIETargetBCF_8cpp.html +++ b/doxygen/html/AIETargetBCF_8cpp.html @@ -148,14 +148,14 @@

Definition at line 24 of file AIETargetBCF.cpp.

-

Referenced by xilinx::AIE::AIETranslateToBCF(), checkAndPrintOverflow(), xilinx::AIE::generateDMAConfig(), printMemMap(), and xilinx::AIE::writeBufferMap().

+

Referenced by xilinx::AIE::AIETranslateToBCF(), checkAndPrintOverflow(), printMemMap(), and xilinx::AIE::writeBufferMap().

-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/AIETargetBCF_8cpp_source.html b/doxygen/html/AIETargetBCF_8cpp_source.html index edbac1a9ef..44b667ab17 100644 --- a/doxygen/html/AIETargetBCF_8cpp_source.html +++ b/doxygen/html/AIETargetBCF_8cpp_source.html @@ -222,7 +222,7 @@
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:56 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/AIETargetCDODirect_8cpp.html b/doxygen/html/AIETargetCDODirect_8cpp.html index 91aa4e6967..9570ee9a76 100644 --- a/doxygen/html/AIETargetCDODirect_8cpp.html +++ b/doxygen/html/AIETargetCDODirect_8cpp.html @@ -184,7 +184,7 @@

-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/AIETargetCDODirect_8cpp_source.html b/doxygen/html/AIETargetCDODirect_8cpp_source.html index 93c211ce53..67045f7ce1 100644 --- a/doxygen/html/AIETargetCDODirect_8cpp_source.html +++ b/doxygen/html/AIETargetCDODirect_8cpp_source.html @@ -243,7 +243,7 @@
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diff --git a/doxygen/html/AIETargetHSA_8cpp.html b/doxygen/html/AIETargetHSA_8cpp.html index 53ff68dcd1..b2e3d87103 100644 --- a/doxygen/html/AIETargetHSA_8cpp.html +++ b/doxygen/html/AIETargetHSA_8cpp.html @@ -143,7 +143,7 @@
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/AIETargetHSA_8cpp_source.html b/doxygen/html/AIETargetHSA_8cpp_source.html index 75d155ac53..5a1049331d 100644 --- a/doxygen/html/AIETargetHSA_8cpp_source.html +++ b/doxygen/html/AIETargetHSA_8cpp_source.html @@ -294,7 +294,7 @@
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:56 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/AIETargetLdScript_8cpp.html b/doxygen/html/AIETargetLdScript_8cpp.html index 155fd72d7e..377ff313f5 100644 --- a/doxygen/html/AIETargetLdScript_8cpp.html +++ b/doxygen/html/AIETargetLdScript_8cpp.html @@ -98,7 +98,7 @@
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diff --git a/doxygen/html/AIETargetModel_8cpp.html b/doxygen/html/AIETargetModel_8cpp.html index 40191a686e..f91967bd48 100644 --- a/doxygen/html/AIETargetModel_8cpp.html +++ b/doxygen/html/AIETargetModel_8cpp.html @@ -89,7 +89,7 @@
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/AIETargetModel_8cpp_source.html b/doxygen/html/AIETargetModel_8cpp_source.html index 0e871edc53..ab0a04b231 100644 --- a/doxygen/html/AIETargetModel_8cpp_source.html +++ b/doxygen/html/AIETargetModel_8cpp_source.html @@ -182,7 +182,7 @@
127  return 0;
128  return 4;
129  }
-
130  case WireBundle::Ctrl:
+
130  case WireBundle::TileControl:
131  return isShimNOCTile(col, row) ? 1 : 0;
132  default:
133  return 0;
@@ -210,7 +210,7 @@
155  return 0;
156  return 4;
157  }
-
158  case WireBundle::Ctrl:
+
158  case WireBundle::TileControl:
159  return 1;
160  default:
161  return 0;
@@ -240,7 +240,7 @@
185  }
186  case WireBundle::Trace:
187  return 1;
-
188  case WireBundle::Ctrl:
+
188  case WireBundle::TileControl:
189  return isShimNOCTile(col, row) ? 1 : 0;
190  default:
191  return 0;
@@ -270,7 +270,7 @@
215  }
216  case WireBundle::Trace:
217  return 2;
-
218  case WireBundle::Ctrl:
+
218  case WireBundle::TileControl:
219  return 1;
220  default:
221  return 0;
@@ -431,7 +431,7 @@
376  return 6;
377  case WireBundle::South:
378  return 4;
-
379  case WireBundle::Ctrl:
+
379  case WireBundle::TileControl:
380  return 1;
381  default:
382  return 0;
@@ -455,7 +455,7 @@
400  return 0;
401  return 4;
402  }
-
403  case WireBundle::Ctrl:
+
403  case WireBundle::TileControl:
404  return isShimNOCTile(col, row) ? 1 : 0;
405  default:
406  return 0;
@@ -485,7 +485,7 @@
430  return 0;
431  return 4;
432  }
-
433  case WireBundle::Ctrl:
+
433  case WireBundle::TileControl:
434  return 1;
435  default:
436  return 0;
@@ -504,7 +504,7 @@
449  case WireBundle::South:
450  return 6;
451  case WireBundle::Trace:
-
452  case WireBundle::Ctrl:
+
452  case WireBundle::TileControl:
453  return 1;
454  default:
455  return 0;
@@ -530,7 +530,7 @@
475  }
476  case WireBundle::Trace:
477  return 1;
-
478  case WireBundle::Ctrl:
+
478  case WireBundle::TileControl:
479  return isShimNOCTile(col, row) ? 1 : 0;
480  default:
481  return 0;
@@ -564,7 +564,7 @@
509  case WireBundle::Trace:
510  // Port 0: core trace. Port 1: memory trace.
511  return 2;
-
512  case WireBundle::Ctrl:
+
512  case WireBundle::TileControl:
513  return 1;
514  default:
515  return 0;
@@ -632,18 +632,18 @@
577  if (srcBundle == WireBundle::DMA) {
578  if (dstBundle == WireBundle::DMA)
579  return srcChan == dstChan;
-
580  if (isBundleInList(dstBundle, {WireBundle::Ctrl, WireBundle::South,
+
580  if (isBundleInList(dstBundle, {WireBundle::TileControl, WireBundle::South,
581  WireBundle::North}))
582  return true;
583  }
-
584  if (srcBundle == WireBundle::Ctrl) {
+
584  if (srcBundle == WireBundle::TileControl) {
585  if (dstBundle == WireBundle::DMA)
586  return dstChan == 5;
587  if (isBundleInList(dstBundle, {WireBundle::South, WireBundle::North}))
588  return true;
589  }
590  if (isBundleInList(srcBundle, {WireBundle::South, WireBundle::North})) {
-
591  if (isBundleInList(dstBundle, {WireBundle::DMA, WireBundle::Ctrl}))
+
591  if (isBundleInList(dstBundle, {WireBundle::DMA, WireBundle::TileControl}))
592  return true;
593  if (isBundleInList(dstBundle, {WireBundle::South, WireBundle::North}))
594  return srcChan == dstChan;
@@ -657,113 +657,115 @@
602  }
603  // Shimtile
604  else if (isShimNOCorPLTile(col, row)) {
-
605  if (srcBundle == WireBundle::Ctrl)
-
606  return dstBundle != WireBundle::Ctrl;
+
605  if (srcBundle == WireBundle::TileControl)
+
606  return dstBundle != WireBundle::TileControl;
607  if (isBundleInList(srcBundle, {WireBundle::FIFO, WireBundle::South}))
-
608  return isBundleInList(dstBundle, {WireBundle::Ctrl, WireBundle::FIFO,
-
609  WireBundle::South, WireBundle::West,
-
610  WireBundle::North, WireBundle::East});
-
611  if (isBundleInList(srcBundle,
-
612  {WireBundle::West, WireBundle::North, WireBundle::East}))
-
613  return (srcBundle == dstBundle)
-
614  ? (srcChan == dstChan)
-
615  : isBundleInList(dstBundle,
-
616  {WireBundle::Ctrl, WireBundle::FIFO,
-
617  WireBundle::South, WireBundle::West,
-
618  WireBundle::North, WireBundle::East});
-
619  if (srcBundle == WireBundle::Trace) {
-
620  if (isBundleInList(dstBundle, {WireBundle::FIFO, WireBundle::South}))
-
621  return true;
-
622  if (isBundleInList(dstBundle, {WireBundle::West, WireBundle::East}))
-
623  return dstChan == 0;
-
624  }
-
625  }
-
626  // Coretile
-
627  else if (isCoreTile(col, row)) {
-
628  if (isBundleInList(srcBundle,
-
629  {WireBundle::DMA, WireBundle::FIFO, WireBundle::South,
-
630  WireBundle::West, WireBundle::North, WireBundle::East}))
-
631  if (isBundleInList(dstBundle,
-
632  {WireBundle::Core, WireBundle::DMA, WireBundle::Ctrl,
-
633  WireBundle::FIFO, WireBundle::South, WireBundle::West,
-
634  WireBundle::North, WireBundle::East}))
-
635  return (srcBundle == dstBundle) ? (srcChan == dstChan) : true;
-
636  if (srcBundle == WireBundle::Core)
-
637  return dstBundle != WireBundle::Core;
-
638  if (srcBundle == WireBundle::Ctrl)
-
639  return dstBundle != WireBundle::Ctrl && dstBundle != WireBundle::DMA;
-
640  if (srcBundle == WireBundle::Trace) {
-
641  if (dstBundle == WireBundle::DMA)
-
642  return dstChan == 0;
-
643  if (isBundleInList(dstBundle, {WireBundle::FIFO, WireBundle::South}))
-
644  return true;
-
645  }
-
646  }
-
647  return false;
-
648 }
-
649 
-
650 void AIETargetModel::validate() const {
-
651  // Every tile in a shimtile row must be a shimtile, and can only be one type
-
652  // of shim tile.
-
653  for (int j = 0; j < columns(); j++) {
-
654  assert(!isMemTile(j, 0) && (isShimPLTile(j, 0) || isShimNOCTile(j, 0)) &&
-
655  !isCoreTile(j, 0));
-
656  assert(isShimPLTile(j, 0) ^ isShimNOCTile(j, 0));
-
657  }
-
658 
-
659  // Every tile in a memtile row must be a memtile.
-
660  for (int i = 1; i < 1 + static_cast<int>(getNumMemTileRows()); i++)
-
661  for (int j = 0; j < columns(); j++)
-
662  assert(isMemTile(j, i) && !isShimPLTile(j, i) && !isShimNOCTile(j, i) &&
-
663  !isCoreTile(j, i));
-
664 
-
665  // Every other tile is a coretile.
-
666  for (int i = 1 + getNumMemTileRows(); i < rows(); i++)
-
667  for (int j = 0; j < columns(); j++)
-
668  assert(!isMemTile(j, i) && !isShimPLTile(j, i) && !isShimNOCTile(j, i) &&
-
669  isCoreTile(j, i));
-
670 
-
671  // Looking North, buses must match
-
672  for (int i = 0; i < rows() - 1; i++)
-
673  for (int j = 0; j < columns(); j++)
-
674  assert(getNumSourceSwitchboxConnections(j, i, WireBundle::North) ==
-
675  getNumDestSwitchboxConnections(j, i + 1, WireBundle::South));
-
676  // Looking South, buses must match
-
677  for (int i = 1; i < rows(); i++)
-
678  for (int j = 0; j < columns(); j++)
-
679  assert(getNumSourceSwitchboxConnections(j, i, WireBundle::South) ==
-
680  getNumDestSwitchboxConnections(j, i - 1, WireBundle::North));
-
681  // Looking East, buses must match
-
682  for (int i = 0; i < rows(); i++)
-
683  for (int j = 0; j < columns() - 1; j++)
-
684  assert(getNumSourceSwitchboxConnections(j, i, WireBundle::East) ==
-
685  getNumDestSwitchboxConnections(j + 1, i, WireBundle::West));
-
686  // Looking West, buses must match
-
687  for (int i = 0; i < rows(); i++)
-
688  for (int j = 1; j < columns(); j++)
-
689  assert(getNumSourceSwitchboxConnections(j, i, WireBundle::West) ==
-
690  getNumDestSwitchboxConnections(j - 1, i, WireBundle::East));
-
691  // Edges have no connections
-
692  for (int j = 0; j < columns(); j++)
-
693  assert(getNumSourceSwitchboxConnections(j, rows() - 1, WireBundle::North) ==
-
694  0);
-
695  for (int i = 0; i < rows(); i++)
-
696  assert(getNumSourceSwitchboxConnections(columns() - 1, i,
-
697  WireBundle::East) == 0);
-
698  for (int i = 0; i < rows(); i++)
-
699  assert(getNumSourceSwitchboxConnections(0, i, WireBundle::West) == 0);
-
700 
-
701  // FIFOS are consistent
-
702  for (int i = 0; i < rows(); i++)
-
703  for (int j = 0; j < columns(); j++)
-
704  assert(getNumSourceSwitchboxConnections(j, i, WireBundle::FIFO) ==
-
705  getNumDestSwitchboxConnections(j, i, WireBundle::FIFO));
-
706 }
-
707 
-
708 AIEArch NPU2TargetModel::getTargetArch() const { return AIEArch::AIE2p; }
+
608  return isBundleInList(dstBundle,
+
609  {WireBundle::TileControl, WireBundle::FIFO,
+
610  WireBundle::South, WireBundle::West,
+
611  WireBundle::North, WireBundle::East});
+
612  if (isBundleInList(srcBundle,
+
613  {WireBundle::West, WireBundle::North, WireBundle::East}))
+
614  return (srcBundle == dstBundle)
+
615  ? (srcChan == dstChan)
+
616  : isBundleInList(dstBundle,
+
617  {WireBundle::TileControl, WireBundle::FIFO,
+
618  WireBundle::South, WireBundle::West,
+
619  WireBundle::North, WireBundle::East});
+
620  if (srcBundle == WireBundle::Trace) {
+
621  if (isBundleInList(dstBundle, {WireBundle::FIFO, WireBundle::South}))
+
622  return true;
+
623  if (isBundleInList(dstBundle, {WireBundle::West, WireBundle::East}))
+
624  return dstChan == 0;
+
625  }
+
626  }
+
627  // Coretile
+
628  else if (isCoreTile(col, row)) {
+
629  if (isBundleInList(srcBundle,
+
630  {WireBundle::DMA, WireBundle::FIFO, WireBundle::South,
+
631  WireBundle::West, WireBundle::North, WireBundle::East}))
+
632  if (isBundleInList(dstBundle, {WireBundle::Core, WireBundle::DMA,
+
633  WireBundle::TileControl, WireBundle::FIFO,
+
634  WireBundle::South, WireBundle::West,
+
635  WireBundle::North, WireBundle::East}))
+
636  return (srcBundle == dstBundle) ? (srcChan == dstChan) : true;
+
637  if (srcBundle == WireBundle::Core)
+
638  return dstBundle != WireBundle::Core;
+
639  if (srcBundle == WireBundle::TileControl)
+
640  return dstBundle != WireBundle::TileControl &&
+
641  dstBundle != WireBundle::DMA;
+
642  if (srcBundle == WireBundle::Trace) {
+
643  if (dstBundle == WireBundle::DMA)
+
644  return dstChan == 0;
+
645  if (isBundleInList(dstBundle, {WireBundle::FIFO, WireBundle::South}))
+
646  return true;
+
647  }
+
648  }
+
649  return false;
+
650 }
+
651 
+
652 void AIETargetModel::validate() const {
+
653  // Every tile in a shimtile row must be a shimtile, and can only be one type
+
654  // of shim tile.
+
655  for (int j = 0; j < columns(); j++) {
+
656  assert(!isMemTile(j, 0) && (isShimPLTile(j, 0) || isShimNOCTile(j, 0)) &&
+
657  !isCoreTile(j, 0));
+
658  assert(isShimPLTile(j, 0) ^ isShimNOCTile(j, 0));
+
659  }
+
660 
+
661  // Every tile in a memtile row must be a memtile.
+
662  for (int i = 1; i < 1 + static_cast<int>(getNumMemTileRows()); i++)
+
663  for (int j = 0; j < columns(); j++)
+
664  assert(isMemTile(j, i) && !isShimPLTile(j, i) && !isShimNOCTile(j, i) &&
+
665  !isCoreTile(j, i));
+
666 
+
667  // Every other tile is a coretile.
+
668  for (int i = 1 + getNumMemTileRows(); i < rows(); i++)
+
669  for (int j = 0; j < columns(); j++)
+
670  assert(!isMemTile(j, i) && !isShimPLTile(j, i) && !isShimNOCTile(j, i) &&
+
671  isCoreTile(j, i));
+
672 
+
673  // Looking North, buses must match
+
674  for (int i = 0; i < rows() - 1; i++)
+
675  for (int j = 0; j < columns(); j++)
+
676  assert(getNumSourceSwitchboxConnections(j, i, WireBundle::North) ==
+
677  getNumDestSwitchboxConnections(j, i + 1, WireBundle::South));
+
678  // Looking South, buses must match
+
679  for (int i = 1; i < rows(); i++)
+
680  for (int j = 0; j < columns(); j++)
+
681  assert(getNumSourceSwitchboxConnections(j, i, WireBundle::South) ==
+
682  getNumDestSwitchboxConnections(j, i - 1, WireBundle::North));
+
683  // Looking East, buses must match
+
684  for (int i = 0; i < rows(); i++)
+
685  for (int j = 0; j < columns() - 1; j++)
+
686  assert(getNumSourceSwitchboxConnections(j, i, WireBundle::East) ==
+
687  getNumDestSwitchboxConnections(j + 1, i, WireBundle::West));
+
688  // Looking West, buses must match
+
689  for (int i = 0; i < rows(); i++)
+
690  for (int j = 1; j < columns(); j++)
+
691  assert(getNumSourceSwitchboxConnections(j, i, WireBundle::West) ==
+
692  getNumDestSwitchboxConnections(j - 1, i, WireBundle::East));
+
693  // Edges have no connections
+
694  for (int j = 0; j < columns(); j++)
+
695  assert(getNumSourceSwitchboxConnections(j, rows() - 1, WireBundle::North) ==
+
696  0);
+
697  for (int i = 0; i < rows(); i++)
+
698  assert(getNumSourceSwitchboxConnections(columns() - 1, i,
+
699  WireBundle::East) == 0);
+
700  for (int i = 0; i < rows(); i++)
+
701  assert(getNumSourceSwitchboxConnections(0, i, WireBundle::West) == 0);
+
702 
+
703  // FIFOS are consistent
+
704  for (int i = 0; i < rows(); i++)
+
705  for (int j = 0; j < columns(); j++)
+
706  assert(getNumSourceSwitchboxConnections(j, i, WireBundle::FIFO) ==
+
707  getNumDestSwitchboxConnections(j, i, WireBundle::FIFO));
+
708 }
709 
-
710 } // namespace AIE
-
711 } // namespace xilinx
+
710 AIEArch NPU2TargetModel::getTargetArch() const { return AIEArch::AIE2p; }
+
711 
+
712 } // namespace AIE
+
713 } // namespace xilinx
isLegalTileConnection
bool isLegalTileConnection(TileOp tile, const AIETargetModel &targetModel, MasterSetOp masterOp, PacketRulesOp slaveOp)
Definition: AIEDialect.cpp:1229
@@ -777,7 +779,7 @@
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:56 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/AIETargetModel_8h.html b/doxygen/html/AIETargetModel_8h.html index 226c8b864a..db15fbe15e 100644 --- a/doxygen/html/AIETargetModel_8h.html +++ b/doxygen/html/AIETargetModel_8h.html @@ -207,7 +207,7 @@
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/AIETargetModel_8h_source.html b/doxygen/html/AIETargetModel_8h_source.html index f9dc27ba25..26c45324b7 100644 --- a/doxygen/html/AIETargetModel_8h_source.html +++ b/doxygen/html/AIETargetModel_8h_source.html @@ -814,7 +814,7 @@
xilinx::AIE::AIETargetModel::isLegalTileConnection
virtual bool isLegalTileConnection(int col, int row, WireBundle srcBundle, int srcChan, WireBundle dstBundle, int dstChan) const =0
xilinx::AIE::AIETargetModel::getNumBanks
virtual uint32_t getNumBanks(int col, int row) const =0
Return the number of memory banks of a given tile.
xilinx::AIE::AIETargetModel::isMemEast
virtual bool isMemEast(int srcCol, int srcRow, int dstCol, int dstRow) const =0
Return true if src has a memory tile which is East of dst.
- +
xilinx::AIE::AIETargetModel::isBdChannelAccessible
virtual bool isBdChannelAccessible(int col, int row, uint32_t bd_id, int channel) const =0
Return true iff buffer descriptor bd_id on tile (col, row) can be submitted on channel channel.
xilinx::AIE::AIETargetModel::getAccumulatorCascadeSize
virtual uint32_t getAccumulatorCascadeSize() const =0
Return the size (in bits) of the accumulator/cascade.
@@ -863,7 +863,7 @@
xilinx::AIE::NPU2TargetModel::isShimPLTile
bool isShimPLTile(int col, int row) const override
Return true if the given tile is a Shim PL interface tile.
Definition: AIETargetModel.h:614
-
xilinx::AIE::NPU2TargetModel::getTargetArch
AIEArch getTargetArch() const override
AIE2 TargetModel.
Definition: AIETargetModel.cpp:708
+
xilinx::AIE::NPU2TargetModel::getTargetArch
AIEArch getTargetArch() const override
AIE2 TargetModel.
Definition: AIETargetModel.cpp:710
xilinx::AIE::NPU2TargetModel::classof
static bool classof(const AIETargetModel *model)
Definition: AIETargetModel.h:616
xilinx::AIE::NPU2TargetModel::isShimNOCTile
bool isShimNOCTile(int col, int row) const override
Return true if the given tile is a Shim NOC tile.
Definition: AIETargetModel.h:612
xilinx::AIE::NPU2TargetModel::columns
int columns() const override
Return the number of columns in the device.
Definition: AIETargetModel.h:610
@@ -934,7 +934,7 @@
-Generated on Fri Jan 10 2025 11:12:31 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:56 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/AIETargetNPU_8cpp.html b/doxygen/html/AIETargetNPU_8cpp.html index fa7aa6a543..639143af31 100644 --- a/doxygen/html/AIETargetNPU_8cpp.html +++ b/doxygen/html/AIETargetNPU_8cpp.html @@ -210,7 +210,7 @@

-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/AIETargetNPU_8cpp_source.html b/doxygen/html/AIETargetNPU_8cpp_source.html index e7f92aebf4..b90b1aa15f 100644 --- a/doxygen/html/AIETargetNPU_8cpp_source.html +++ b/doxygen/html/AIETargetNPU_8cpp_source.html @@ -388,7 +388,7 @@
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:56 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/AIETargetShared_8cpp.html b/doxygen/html/AIETargetShared_8cpp.html index c4e1fec8f8..8e74fc0db9 100644 --- a/doxygen/html/AIETargetShared_8cpp.html +++ b/doxygen/html/AIETargetShared_8cpp.html @@ -144,7 +144,7 @@
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/AIETargetShared_8cpp_source.html b/doxygen/html/AIETargetShared_8cpp_source.html index f7fa8edf5e..b099e1cdfd 100644 --- a/doxygen/html/AIETargetShared_8cpp_source.html +++ b/doxygen/html/AIETargetShared_8cpp_source.html @@ -233,7 +233,7 @@
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:56 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/AIETargetShared_8h.html b/doxygen/html/AIETargetShared_8h.html index 74d5e75103..4a6233e787 100644 --- a/doxygen/html/AIETargetShared_8h.html +++ b/doxygen/html/AIETargetShared_8h.html @@ -140,7 +140,7 @@
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/AIETargetShared_8h_source.html b/doxygen/html/AIETargetShared_8h_source.html index 65fbd420ec..74e30e7d90 100644 --- a/doxygen/html/AIETargetShared_8h_source.html +++ b/doxygen/html/AIETargetShared_8h_source.html @@ -113,7 +113,7 @@
-Generated on Fri Jan 10 2025 11:12:31 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:56 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/AIETargetSimulationFiles_8cpp.html b/doxygen/html/AIETargetSimulationFiles_8cpp.html index 671f9ca922..6090b51fb2 100644 --- a/doxygen/html/AIETargetSimulationFiles_8cpp.html +++ b/doxygen/html/AIETargetSimulationFiles_8cpp.html @@ -127,7 +127,7 @@
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/AIETargetSimulationFiles_8cpp_source.html b/doxygen/html/AIETargetSimulationFiles_8cpp_source.html index 57e6d25f5a..848c9fdb42 100644 --- a/doxygen/html/AIETargetSimulationFiles_8cpp_source.html +++ b/doxygen/html/AIETargetSimulationFiles_8cpp_source.html @@ -468,7 +468,7 @@
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:56 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/AIETargetXAIEV2_8cpp.html b/doxygen/html/AIETargetXAIEV2_8cpp.html index d43951d7f9..f235cb8ecd 100644 --- a/doxygen/html/AIETargetXAIEV2_8cpp.html +++ b/doxygen/html/AIETargetXAIEV2_8cpp.html @@ -49,10 +49,6 @@
-
-Namespaces | -Functions | -Variables
AIETargetXAIEV2.cpp File Reference
@@ -118,32 +114,10 @@

Go to the source code of this file.

- - - - - - - -

-Namespaces

 xilinx
 
 xilinx::AIE
 Include the generated interface declarations.
 
- - - - - - -

-Functions

template<typename OpType >
mlir::LogicalResult xilinx::AIE::generateDMAConfig (OpType memOp, raw_ostream &output, const AIETargetModel &targetModel, DenseMap< Block *, int > blockMap)
 
mlir::LogicalResult xilinx::AIE::AIETranslateToXAIEV2 (ModuleOp module, raw_ostream &output)
 
- - - -

-Variables

const char * xilinx::AIE::xaie_cpp_file_header
 
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/AIETargetXAIEV2_8cpp_source.html b/doxygen/html/AIETargetXAIEV2_8cpp_source.html index d83e743595..926591d1e8 100644 --- a/doxygen/html/AIETargetXAIEV2_8cpp_source.html +++ b/doxygen/html/AIETargetXAIEV2_8cpp_source.html @@ -82,885 +82,857 @@
27 using namespace xilinx::AIE;
28 using namespace xilinx::AIEX;
29 
-
30 namespace xilinx::AIE {
-
31 
-
32 // This string is output at the top of the lowered C++ code.
-
33 const char *xaie_cpp_file_header = R"code(
-
34 // This file was auto-generated by aiecc.py --aie-generate-xaie.
-
35 
-
36 #ifndef MLIR_AIE_QUIET
-
37 #define __mlir_aie_verbose(x) x
-
38 #else
-
39 #define __mlir_aie_verbose(x)
-
40 #endif
-
41 
-
42 // The following is a wrapper for the common "if(call() != 0) return 1" pattern.
-
43 // Use this only in functions that return int. If the call this wrapper is used
-
44 // on does not succeed, the expanded code will exit out of the function
-
45 // containing this macro with an error code.
-
46 #define __mlir_aie_try(x) do { \
-
47  AieRC ret = (x); \
-
48  if(ret != XAIE_OK) { \
-
49  return x; \
-
50  } \
-
51 } while(0)
-
52 
-
53 static XAie_DmaDimDesc *__mlir_aie_alloc_dim_desc(size_t ndims) {
-
54  XAie_DmaDimDesc *ret = NULL;
-
55  ret = (XAie_DmaDimDesc *)calloc(sizeof(XAie_DmaDimDesc), ndims);
-
56  if(NULL == ret) {
-
57  __mlir_aie_verbose(fprintf(stderr, "Allocating DmaDimDesc failed.\n"));
-
58  }
-
59  return ret;
-
60 }
+
30 // This string is output at the top of the lowered C++ code.
+
31 static const char *xaie_cpp_file_header = R"code(
+
32 // This file was auto-generated by aiecc.py --aie-generate-xaie.
+
33 
+
34 #ifndef MLIR_AIE_QUIET
+
35 #define __mlir_aie_verbose(x) x
+
36 #else
+
37 #define __mlir_aie_verbose(x)
+
38 #endif
+
39 
+
40 // The following is a wrapper for the common "if(call() != 0) return 1" pattern.
+
41 // Use this only in functions that return int. If the call this wrapper is used
+
42 // on does not succeed, the expanded code will exit out of the function
+
43 // containing this macro with an error code.
+
44 #define __mlir_aie_try(x) do { \
+
45  AieRC ret = (x); \
+
46  if(ret != XAIE_OK) { \
+
47  return x; \
+
48  } \
+
49 } while(0)
+
50 
+
51 static XAie_DmaDimDesc *__mlir_aie_alloc_dim_desc(size_t ndims) {
+
52  XAie_DmaDimDesc *ret = NULL;
+
53  ret = (XAie_DmaDimDesc *)calloc(sizeof(XAie_DmaDimDesc), ndims);
+
54  if(NULL == ret) {
+
55  __mlir_aie_verbose(fprintf(stderr, "Allocating DmaDimDesc failed.\n"));
+
56  }
+
57  return ret;
+
58 }
+
59 
+
60 )code";
61 
-
62 )code";
-
63 
-
64 static std::string tileLockStr(StringRef id, StringRef val) {
-
65  std::string str;
-
66  llvm::raw_string_ostream rss(str);
-
67  // rss << "XAie_Lock(" << id << "," << val << ")";
-
68  rss << "XAie_LockInit(" << id << "," << val << ")";
-
69  return str;
-
70 }
-
71 
-
72 // FIXME: code bloat. this shouldn't really be a template, but need
-
73 // a proper DMA-like interface
-
74 // blockMap: A map that gives a unique bd ID assignment for every block.
-
75 template <typename OpType>
-
76 mlir::LogicalResult generateDMAConfig(OpType memOp, raw_ostream &output,
-
77  const AIETargetModel &targetModel,
-
78  DenseMap<Block *, int> blockMap) {
-
79  StringRef enable = "XAIE_ENABLE";
-
80  StringRef disable = "XAIE_DISABLE";
-
81  StringRef deviceInstRef = "&(ctx->DevInst)"; // TODO
-
82 
-
83  int col = memOp.colIndex();
-
84  int row = memOp.rowIndex();
-
85 
-
86  // Get the region's entry block, then start traversing through the chain of
-
87  // blocks.
-
88  llvm::SetVector<Block *> blockVector =
-
89  getOrderedChainOfBlocks(&memOp.getBody());
-
90 
-
91  for (auto block : blockVector) {
-
92  bool foundBdPacket = false;
-
93  int packetType = 0;
-
94  int packetID = 0;
-
95  bool foundBd = false;
-
96  int lenA = 0;
-
97  int offsetA = 0;
-
98  int BaseAddrA = 0;
-
99  int elementWidthInBytes = 0;
-
100  int ndims = 0;
-
101  ArrayRef<BDDimLayoutAttr> dims;
-
102  // StringRef FifoMode = disable; // FIXME: when to enable FIFO mode?
-
103  for (auto op : block->getOps<DMABDOp>()) {
-
104  foundBd = true;
-
105  if (!targetModel.isShimNOCTile(col, row)) {
-
106  assert(op.getBufferOp().getAddress() &&
-
107  "buffer must have address assigned");
-
108  BaseAddrA = op.getBufferOp().getAddress().value();
-
109  int bufferCol = op.getBufferOp().getTileOp().colIndex();
-
110  int bufferRow = op.getBufferOp().getTileOp().rowIndex();
-
111 
-
112  // Memtile DMAs can access neighboring tiles.
-
113  if (targetModel.isMemTile(col, row)) {
-
114  if (targetModel.isWest(col, row, bufferCol, bufferRow))
-
115  BaseAddrA += 0x0;
-
116  else if (targetModel.isInternal(col, row, bufferCol, bufferRow))
-
117  BaseAddrA += targetModel.getMemTileSize() * 1;
-
118  else if (targetModel.isEast(col, row, bufferCol, bufferRow))
-
119  BaseAddrA += targetModel.getMemTileSize() * 2;
-
120  }
-
121  }
-
122 
-
123  lenA = op.getLenInBytes();
-
124  offsetA = op.getOffsetInBytes();
-
125  elementWidthInBytes = op.getBufferElementTypeWidthInBytes();
-
126  if (op.getDimensions()) {
-
127  dims = *op.getDimensions();
-
128  ndims = dims.size();
-
129  }
-
130  }
-
131 
-
132  if (0 != ndims)
-
133  if (!targetModel.hasProperty(AIETargetModel::UsesMultiDimensionalBDs))
-
134  return memOp.emitOpError("DMA contains at least one multi-dimensional "
-
135  "buffer descriptor. This is currently only "
-
136  "supported for AIE-ML and later devices.");
-
137 
-
138  int acqValue = 0, relValue = 0;
-
139  bool hasAcq = false, hasRel = false;
-
140  int acqLockID = 0, relLockID = 0;
-
141  for (auto op : block->getOps<UseLockOp>()) {
-
142  LockOp lock = cast<LockOp>(op.getLock().getDefiningOp());
-
143  int lockCol = lock.colIndex();
-
144  int lockRow = lock.rowIndex();
-
145  int lockID = lock.getLockIDValue();
-
146  // Memtile DMAs can access neighboring tiles.
-
147  if (targetModel.isMemTile(col, row)) {
-
148  if (targetModel.isWest(col, row, lockCol, lockRow))
-
149  lockID += 0;
-
150  else if (targetModel.isInternal(col, row, lockCol, lockRow))
-
151  lockID += targetModel.getNumLocks(lockCol, lockRow) * 1;
-
152  else if (targetModel.isEast(col, row, lockCol, lockRow))
-
153  lockID += targetModel.getNumLocks(lockCol, lockRow) * 2;
-
154  }
-
155 
-
156  if (op.acquire() || op.acquireGE()) {
-
157  hasAcq = true;
-
158  acqLockID = lockID;
-
159  acqValue = op.getLockValue();
-
160  if (op.acquireGE())
-
161  acqValue = -acqValue;
-
162  } else if (op.release()) {
-
163  hasRel = true;
-
164  relLockID = lockID;
-
165  relValue = op.getLockValue();
-
166  } else {
-
167  // unreachable for current targets
-
168  return op.emitOpError("unsupported lock action");
-
169  }
-
170  }
-
171 
-
172  for (auto op : block->getOps<DMABDPACKETOp>()) {
-
173  foundBdPacket = true;
-
174  packetType = op.getPacketType();
-
175  packetID = op.getPacketID();
-
176  }
-
177 
-
178  int bdNum = blockMap[block];
-
179  if (foundBd) {
-
180  // TODO For now, we are going to name each dma desc with loc and bd
-
181  // which we assume is unique. This is strictly not enforced but in
-
182  // practice, this is true
-
183  output << "XAie_DmaDesc " << tileDMAInstStr(col, row, bdNum) << ";\n";
-
184  output << "__mlir_aie_try(XAie_DmaDescInit(" << deviceInstRef << ", "
-
185  << tileDMAInstRefStr(col, row, bdNum) << ", "
-
186  << tileLocStr(col, row) << "));\n";
-
187  if (hasAcq || hasRel) {
-
188  output << "__mlir_aie_try(XAie_DmaSetLock("
-
189  << tileDMAInstRefStr(col, row, bdNum) << ", "
-
190  << "XAie_LockInit(" << acqLockID << "," << acqValue << "),"
-
191  << "XAie_LockInit(" << relLockID << "," << relValue << ")));\n";
-
192  if (!hasAcq)
-
193  output << tileDMAInstStr(col, row, bdNum)
-
194  << ".LockDesc.LockAcqEn = " << disable << ";\n";
-
195  if (!hasRel)
-
196  output << tileDMAInstStr(col, row, bdNum)
-
197  << ".LockDesc.LockRelEn = " << disable << ";\n";
-
198  }
-
199 
-
200  if (0 == ndims) {
-
201  if (targetModel.isShimNOCTile(col, row)) {
-
202  output << "__mlir_aie_try(XAie_DmaSetAddrLen("
-
203  << tileDMAInstRefStr(col, row, bdNum) << ", /* addrA */ "
-
204  << "mlir_aie_external_get_addr_myBuffer_" << col << row << "_"
-
205  << bdNum << "(), "
-
206  << " /* len */ " << lenA << "));\n";
-
207  output << "__mlir_aie_try(XAie_DmaSetAxi("
-
208  << tileDMAInstRefStr(col, row, bdNum) << ", "
-
209  << "/* smid */ 0, "
-
210  << "/* burstlen */ 4, "
-
211  << "/* QoS */ 0, "
-
212  << "/* Cache */ 0, "
-
213  << "/* Secure */ " << enable << "));\n";
-
214  } else {
-
215  if ((BaseAddrA + offsetA) % 4)
-
216  return memOp.emitError("bd address must be 4B (32b) aligned");
-
217  output << "__mlir_aie_try(XAie_DmaSetAddrLen("
-
218  << tileDMAInstRefStr(col, row, bdNum) << ", /* addrA */ "
-
219  << "0x" << llvm::utohexstr(BaseAddrA + offsetA) << ", "
-
220  << " /* len */ " << lenA << "));\n";
-
221  }
-
222  } else
-
223  generateXAieDmaSetMultiDimAddr(output, ndims, dims, col, row, bdNum,
-
224  BaseAddrA, offsetA, lenA,
-
225  elementWidthInBytes, "1");
-
226 
-
227  if (block->getNumSuccessors() > 0) {
-
228  Block *nextBlock = block->getSuccessors()[0]; // should have only one
-
229  // successor block
-
230 
-
231  int enableNextBd = 1;
-
232  if (!nextBlock->getOps<EndOp>().empty())
-
233  enableNextBd = 0;
-
234 
-
235  int nextBdNum = blockMap[nextBlock];
-
236  output << "__mlir_aie_try(XAie_DmaSetNextBd("
-
237  << tileDMAInstRefStr(col, row, bdNum) << ", "
-
238  << " /* nextbd */ " << nextBdNum << ", "
-
239  << " /* enableNextBd */ " << enableNextBd << "));\n";
-
240  }
-
241 
-
242  if (foundBdPacket) {
-
243  output << "__mlir_aie_try(XAie_DmaSetPkt("
-
244  << tileDMAInstRefStr(col, row, bdNum) << ", "
-
245  << packetStr(packetID, packetType) << "));\n";
-
246  }
-
247  output << "__mlir_aie_try(XAie_DmaEnableBd("
-
248  << tileDMAInstRefStr(col, row, bdNum) << "));\n";
-
249  output << "__mlir_aie_try(XAie_DmaWriteBd(" << deviceInstRef << ", "
-
250  << tileDMAInstRefStr(col, row, bdNum) << ", "
-
251  << tileLocStr(col, row) << ", "
-
252  << " /* bd */ " << bdNum << "));\n";
-
253  }
-
254  }
-
255 
-
256  for (auto block : blockVector) {
-
257  for (auto op : block->getOps<DMAStartOp>()) {
-
258  int bdNum = blockMap[op.getDest()];
-
259  StringRef dmaDir = stringifyDMAChannelDir(op.getChannelDir());
-
260  int chNum = op.getChannelIndex();
-
261  const auto &target_model = xilinx::AIE::getTargetModel(op);
-
262  if (target_model.getTargetArch() == AIEArch::AIE1) {
-
263  output << "__mlir_aie_try(XAie_DmaChannelPushBdToQueue("
-
264  << deviceInstRef << ", " << tileLocStr(col, row) << ", "
-
265  << "/* ChNum */" << chNum
-
266  << ", "
-
267  // TODO hack until physical dialect changes
-
268  << "/* dmaDir */ DMA_" << dmaDir << ", "
-
269  << "/* BdNum */" << bdNum << "));\n";
-
270  } else {
-
271  // in english repeat_count==0 means "do it once" and don't repeat but
-
272  // libxaie treats repeat_count=1 as do it once.
-
273  int repeatCount = op.getRepeatCount() + 1;
-
274  output << "__mlir_aie_try(XAie_DmaChannelSetStartQueue("
-
275  << deviceInstRef << ", " << tileLocStr(col, row) << ", "
-
276  << "/* ChNum */" << chNum
-
277  << ", "
-
278  // TODO hack until physical dialect changes
-
279  << "/* dmaDir */ DMA_" << dmaDir << ", "
-
280  << "/* BdNum */" << bdNum << ", "
-
281  << "/* Repeat */ " << repeatCount << ", "
-
282  << "/* EnToken */ "
-
283  << "XAIE_DISABLE"
-
284  << "));\n";
-
285  }
-
286  output << "__mlir_aie_try(XAie_DmaChannelEnable(" << deviceInstRef << ", "
-
287  << tileLocStr(col, row) << ", "
-
288  << "/* ChNum */ " << chNum
-
289  << ", "
-
290  // TODO hack until physical dialect changes
-
291  << "/* dmaDir */ DMA_" << dmaDir << "));\n";
-
292  }
-
293  }
-
294  return success();
-
295 }
-
296 
-
297 mlir::LogicalResult AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output) {
-
298  // StringRef ctx = "ctx"; // TODO
-
299  StringRef ctx_p = "aie_libxaie_ctx_t* ctx"; // TODO
-
300  // StringRef deviceInst = "ctx->DevInst"; // TODO
-
301  StringRef deviceInstRef = "&(ctx->DevInst)"; // TODO
-
302 
-
303  DenseMap<TileID, Operation *> tiles;
-
304  DenseMap<Operation *, SmallVector<BufferOp, 4>> buffers;
-
305 
-
306  if (module.getOps<DeviceOp>().empty())
-
307  return module.emitOpError("expected AIE.device operation at toplevel");
-
308  DeviceOp targetOp = *(module.getOps<DeviceOp>().begin());
-
309  const auto &targetModel = targetOp.getTargetModel();
-
310 
-
311  collectTiles(targetOp, tiles);
-
312  collectBuffers(targetOp, buffers);
+
62 static std::string tileLockStr(StringRef id, StringRef val) {
+
63  std::string str;
+
64  llvm::raw_string_ostream rss(str);
+
65  // rss << "XAie_Lock(" << id << "," << val << ")";
+
66  rss << "XAie_LockInit(" << id << "," << val << ")";
+
67  return str;
+
68 }
+
69 
+
70 // Translate mlir-aie WireBundle enum to string of aie-rt StrmSwPortType enum
+
71 static std::string wireBundleToPortType(WireBundle bundle) {
+
72  switch (bundle) {
+
73  case WireBundle::PLIO:
+
74  return "PL";
+
75  case WireBundle::TileControl:
+
76  return "CTRL";
+
77  default:
+
78  return stringifyWireBundle(bundle).upper();
+
79  }
+
80 }
+
81 
+
82 // FIXME: code bloat. this shouldn't really be a template, but need
+
83 // a proper DMA-like interface
+
84 // blockMap: A map that gives a unique bd ID assignment for every block.
+
85 template <typename OpType>
+
86 static mlir::LogicalResult generateDMAConfig(OpType memOp, raw_ostream &output,
+
87  const AIETargetModel &targetModel,
+
88  DenseMap<Block *, int> blockMap) {
+
89  StringRef enable = "XAIE_ENABLE";
+
90  StringRef disable = "XAIE_DISABLE";
+
91  StringRef deviceInstRef = "&(ctx->DevInst)"; // TODO
+
92 
+
93  int col = memOp.colIndex();
+
94  int row = memOp.rowIndex();
+
95 
+
96  // Get the region's entry block, then start traversing through the chain of
+
97  // blocks.
+
98  llvm::SetVector<Block *> blockVector =
+
99  getOrderedChainOfBlocks(&memOp.getBody());
+
100 
+
101  for (auto block : blockVector) {
+
102  bool foundBdPacket = false;
+
103  int packetType = 0;
+
104  int packetID = 0;
+
105  bool foundBd = false;
+
106  int lenA = 0;
+
107  int offsetA = 0;
+
108  int BaseAddrA = 0;
+
109  int elementWidthInBytes = 0;
+
110  int ndims = 0;
+
111  ArrayRef<BDDimLayoutAttr> dims;
+
112  // StringRef FifoMode = disable; // FIXME: when to enable FIFO mode?
+
113  for (auto op : block->getOps<DMABDOp>()) {
+
114  foundBd = true;
+
115  if (!targetModel.isShimNOCTile(col, row)) {
+
116  assert(op.getBufferOp().getAddress() &&
+
117  "buffer must have address assigned");
+
118  BaseAddrA = op.getBufferOp().getAddress().value();
+
119  int bufferCol = op.getBufferOp().getTileOp().colIndex();
+
120  int bufferRow = op.getBufferOp().getTileOp().rowIndex();
+
121 
+
122  // Memtile DMAs can access neighboring tiles.
+
123  if (targetModel.isMemTile(col, row)) {
+
124  if (targetModel.isWest(col, row, bufferCol, bufferRow))
+
125  BaseAddrA += 0x0;
+
126  else if (targetModel.isInternal(col, row, bufferCol, bufferRow))
+
127  BaseAddrA += targetModel.getMemTileSize() * 1;
+
128  else if (targetModel.isEast(col, row, bufferCol, bufferRow))
+
129  BaseAddrA += targetModel.getMemTileSize() * 2;
+
130  }
+
131  }
+
132 
+
133  lenA = op.getLenInBytes();
+
134  offsetA = op.getOffsetInBytes();
+
135  elementWidthInBytes = op.getBufferElementTypeWidthInBytes();
+
136  if (op.getDimensions()) {
+
137  dims = *op.getDimensions();
+
138  ndims = dims.size();
+
139  }
+
140  }
+
141 
+
142  if (0 != ndims)
+
143  if (!targetModel.hasProperty(AIETargetModel::UsesMultiDimensionalBDs))
+
144  return memOp.emitOpError("DMA contains at least one multi-dimensional "
+
145  "buffer descriptor. This is currently only "
+
146  "supported for AIE-ML and later devices.");
+
147 
+
148  int acqValue = 0, relValue = 0;
+
149  bool hasAcq = false, hasRel = false;
+
150  int acqLockID = 0, relLockID = 0;
+
151  for (auto op : block->getOps<UseLockOp>()) {
+
152  LockOp lock = cast<LockOp>(op.getLock().getDefiningOp());
+
153  int lockCol = lock.colIndex();
+
154  int lockRow = lock.rowIndex();
+
155  int lockID = lock.getLockIDValue();
+
156  // Memtile DMAs can access neighboring tiles.
+
157  if (targetModel.isMemTile(col, row)) {
+
158  if (targetModel.isWest(col, row, lockCol, lockRow))
+
159  lockID += 0;
+
160  else if (targetModel.isInternal(col, row, lockCol, lockRow))
+
161  lockID += targetModel.getNumLocks(lockCol, lockRow) * 1;
+
162  else if (targetModel.isEast(col, row, lockCol, lockRow))
+
163  lockID += targetModel.getNumLocks(lockCol, lockRow) * 2;
+
164  }
+
165 
+
166  if (op.acquire() || op.acquireGE()) {
+
167  hasAcq = true;
+
168  acqLockID = lockID;
+
169  acqValue = op.getLockValue();
+
170  if (op.acquireGE())
+
171  acqValue = -acqValue;
+
172  } else if (op.release()) {
+
173  hasRel = true;
+
174  relLockID = lockID;
+
175  relValue = op.getLockValue();
+
176  } else {
+
177  // unreachable for current targets
+
178  return op.emitOpError("unsupported lock action");
+
179  }
+
180  }
+
181 
+
182  for (auto op : block->getOps<DMABDPACKETOp>()) {
+
183  foundBdPacket = true;
+
184  packetType = op.getPacketType();
+
185  packetID = op.getPacketID();
+
186  }
+
187 
+
188  int bdNum = blockMap[block];
+
189  if (foundBd) {
+
190  // TODO For now, we are going to name each dma desc with loc and bd
+
191  // which we assume is unique. This is strictly not enforced but in
+
192  // practice, this is true
+
193  output << "XAie_DmaDesc " << tileDMAInstStr(col, row, bdNum) << ";\n";
+
194  output << "__mlir_aie_try(XAie_DmaDescInit(" << deviceInstRef << ", "
+
195  << tileDMAInstRefStr(col, row, bdNum) << ", "
+
196  << tileLocStr(col, row) << "));\n";
+
197  if (hasAcq || hasRel) {
+
198  output << "__mlir_aie_try(XAie_DmaSetLock("
+
199  << tileDMAInstRefStr(col, row, bdNum) << ", "
+
200  << "XAie_LockInit(" << acqLockID << "," << acqValue << "),"
+
201  << "XAie_LockInit(" << relLockID << "," << relValue << ")));\n";
+
202  if (!hasAcq)
+
203  output << tileDMAInstStr(col, row, bdNum)
+
204  << ".LockDesc.LockAcqEn = " << disable << ";\n";
+
205  if (!hasRel)
+
206  output << tileDMAInstStr(col, row, bdNum)
+
207  << ".LockDesc.LockRelEn = " << disable << ";\n";
+
208  }
+
209 
+
210  if (0 == ndims) {
+
211  if (targetModel.isShimNOCTile(col, row)) {
+
212  output << "__mlir_aie_try(XAie_DmaSetAddrLen("
+
213  << tileDMAInstRefStr(col, row, bdNum) << ", /* addrA */ "
+
214  << "mlir_aie_external_get_addr_myBuffer_" << col << row << "_"
+
215  << bdNum << "(), "
+
216  << " /* len */ " << lenA << "));\n";
+
217  output << "__mlir_aie_try(XAie_DmaSetAxi("
+
218  << tileDMAInstRefStr(col, row, bdNum) << ", "
+
219  << "/* smid */ 0, "
+
220  << "/* burstlen */ 4, "
+
221  << "/* QoS */ 0, "
+
222  << "/* Cache */ 0, "
+
223  << "/* Secure */ " << enable << "));\n";
+
224  } else {
+
225  if ((BaseAddrA + offsetA) % 4)
+
226  return memOp.emitError("bd address must be 4B (32b) aligned");
+
227  output << "__mlir_aie_try(XAie_DmaSetAddrLen("
+
228  << tileDMAInstRefStr(col, row, bdNum) << ", /* addrA */ "
+
229  << "0x" << llvm::utohexstr(BaseAddrA + offsetA) << ", "
+
230  << " /* len */ " << lenA << "));\n";
+
231  }
+
232  } else
+
233  generateXAieDmaSetMultiDimAddr(output, ndims, dims, col, row, bdNum,
+
234  BaseAddrA, offsetA, lenA,
+
235  elementWidthInBytes, "1");
+
236 
+
237  if (block->getNumSuccessors() > 0) {
+
238  Block *nextBlock = block->getSuccessors()[0]; // should have only one
+
239  // successor block
+
240 
+
241  int enableNextBd = 1;
+
242  if (!nextBlock->getOps<EndOp>().empty())
+
243  enableNextBd = 0;
+
244 
+
245  int nextBdNum = blockMap[nextBlock];
+
246  output << "__mlir_aie_try(XAie_DmaSetNextBd("
+
247  << tileDMAInstRefStr(col, row, bdNum) << ", "
+
248  << " /* nextbd */ " << nextBdNum << ", "
+
249  << " /* enableNextBd */ " << enableNextBd << "));\n";
+
250  }
+
251 
+
252  if (foundBdPacket) {
+
253  output << "__mlir_aie_try(XAie_DmaSetPkt("
+
254  << tileDMAInstRefStr(col, row, bdNum) << ", "
+
255  << packetStr(packetID, packetType) << "));\n";
+
256  }
+
257  output << "__mlir_aie_try(XAie_DmaEnableBd("
+
258  << tileDMAInstRefStr(col, row, bdNum) << "));\n";
+
259  output << "__mlir_aie_try(XAie_DmaWriteBd(" << deviceInstRef << ", "
+
260  << tileDMAInstRefStr(col, row, bdNum) << ", "
+
261  << tileLocStr(col, row) << ", "
+
262  << " /* bd */ " << bdNum << "));\n";
+
263  }
+
264  }
+
265 
+
266  for (auto block : blockVector) {
+
267  for (auto op : block->getOps<DMAStartOp>()) {
+
268  int bdNum = blockMap[op.getDest()];
+
269  StringRef dmaDir = stringifyDMAChannelDir(op.getChannelDir());
+
270  int chNum = op.getChannelIndex();
+
271  const auto &target_model = xilinx::AIE::getTargetModel(op);
+
272  if (target_model.getTargetArch() == AIEArch::AIE1) {
+
273  output << "__mlir_aie_try(XAie_DmaChannelPushBdToQueue("
+
274  << deviceInstRef << ", " << tileLocStr(col, row) << ", "
+
275  << "/* ChNum */" << chNum
+
276  << ", "
+
277  // TODO hack until physical dialect changes
+
278  << "/* dmaDir */ DMA_" << dmaDir << ", "
+
279  << "/* BdNum */" << bdNum << "));\n";
+
280  } else {
+
281  // in english repeat_count==0 means "do it once" and don't repeat but
+
282  // libxaie treats repeat_count=1 as do it once.
+
283  int repeatCount = op.getRepeatCount() + 1;
+
284  output << "__mlir_aie_try(XAie_DmaChannelSetStartQueue("
+
285  << deviceInstRef << ", " << tileLocStr(col, row) << ", "
+
286  << "/* ChNum */" << chNum
+
287  << ", "
+
288  // TODO hack until physical dialect changes
+
289  << "/* dmaDir */ DMA_" << dmaDir << ", "
+
290  << "/* BdNum */" << bdNum << ", "
+
291  << "/* Repeat */ " << repeatCount << ", "
+
292  << "/* EnToken */ "
+
293  << "XAIE_DISABLE"
+
294  << "));\n";
+
295  }
+
296  output << "__mlir_aie_try(XAie_DmaChannelEnable(" << deviceInstRef << ", "
+
297  << tileLocStr(col, row) << ", "
+
298  << "/* ChNum */ " << chNum
+
299  << ", "
+
300  // TODO hack until physical dialect changes
+
301  << "/* dmaDir */ DMA_" << dmaDir << "));\n";
+
302  }
+
303  }
+
304  return success();
+
305 }
+
306 
+
307 mlir::LogicalResult xilinx::AIE::AIETranslateToXAIEV2(ModuleOp module,
+
308  raw_ostream &output) {
+
309  // StringRef ctx = "ctx"; // TODO
+
310  StringRef ctx_p = "aie_libxaie_ctx_t* ctx"; // TODO
+
311  // StringRef deviceInst = "ctx->DevInst"; // TODO
+
312  StringRef deviceInstRef = "&(ctx->DevInst)"; // TODO
313 
-
314  //---------------------------------------------------------------------------
-
315  // mlir_aie_init_libxaie
-
316  //---------------------------------------------------------------------------
-
317  output << xaie_cpp_file_header;
-
318  output << "aie_libxaie_ctx_t* mlir_aie_init_libxaie() {\n";
-
319  output << " aie_libxaie_ctx_t *ctx = new aie_libxaie_ctx_t;\n";
-
320  output << " if (!ctx)\n";
-
321  output << " return 0;\n";
-
322  auto arch = targetModel.getTargetArch();
-
323  std::string AIE1_device("XAIE_DEV_GEN_AIE");
-
324  std::string AIE2_device("XAIE_DEV_GEN_AIEML");
-
325  std::string AIE2p_device("XAIE_DEV_GEN_AIE2P");
-
326  std::string device;
-
327  switch (arch) {
-
328  case AIEArch::AIE1:
-
329  device = AIE1_device;
-
330  break;
-
331  case AIEArch::AIE2:
-
332  device = AIE2_device;
-
333  break;
-
334  case AIEArch::AIE2p:
-
335  device = AIE2p_device;
-
336  break;
-
337  }
-
338  output << " ctx->AieConfigPtr.AieGen = " << device << ";\n";
-
339  output << " ctx->AieConfigPtr.BaseAddr = 0x20000000000;\n";
-
340  output << " ctx->AieConfigPtr.ColShift = " << targetModel.getColumnShift()
-
341  << ";\n";
-
342  output << " ctx->AieConfigPtr.RowShift = " << targetModel.getRowShift()
-
343  << ";\n";
-
344  output << " ctx->AieConfigPtr.NumRows = " << targetModel.rows() << ";\n";
-
345  output << " ctx->AieConfigPtr.NumCols = " << targetModel.columns() << ";\n";
-
346  output << " ctx->AieConfigPtr.ShimRowNum = 0;\n";
-
347  output << " ctx->AieConfigPtr.MemTileRowStart = 1;\n";
-
348  output << " ctx->AieConfigPtr.MemTileNumRows = "
-
349  << targetModel.getNumMemTileRows() << ";\n";
-
350  output << " // ctx->AieConfigPtr.ReservedRowStart = "
-
351  "XAIE_RES_TILE_ROW_START;\n";
-
352  output
-
353  << " // ctx->AieConfigPtr.ReservedNumRows = XAIE_RES_TILE_NUM_ROWS;\n";
-
354  output << " ctx->AieConfigPtr.AieTileRowStart = "
-
355  << (1 + targetModel.getNumMemTileRows()) << ";\n";
-
356  output << " ctx->AieConfigPtr.AieTileNumRows = "
-
357  << (targetModel.rows() - 1 - targetModel.getNumMemTileRows()) << ";\n";
-
358  output << " ctx->AieConfigPtr.PartProp = {0};\n";
-
359  output << " ctx->DevInst = {0};\n";
-
360  output << " return ctx;\n";
-
361  output << "}\n";
-
362  output << "\n";
-
363 
-
364  //---------------------------------------------------------------------------
-
365  // mlir_aie_configure_cores
-
366  //---------------------------------------------------------------------------
-
367  output << "int mlir_aie_configure_cores(" << ctx_p << ") {\n";
-
368  // Reset each core. Load the corresponding ELF file, if necessary.
-
369  for (auto tileOp : targetOp.getOps<TileOp>()) {
-
370  int col = tileOp.colIndex();
-
371  int row = tileOp.rowIndex();
-
372  if (tileOp.isShimTile() || tileOp.isMemTile()) {
-
373  // Resets no needed with V2 kernel driver
-
374  } else {
-
375  // Resets no needed with V2 kernel driver
-
376  output << "__mlir_aie_try(XAie_CoreReset(" << deviceInstRef << ", "
-
377  << tileLocStr(col, row) << "));\n";
-
378  output << "__mlir_aie_try(XAie_CoreDisable(" << deviceInstRef << ", "
-
379  << tileLocStr(col, row) << "));\n";
-
380  // Release locks
-
381  int numLocks = targetModel.getNumLocks(col, row);
-
382  output << "for (int l = 0; l < " << numLocks << "; ++l)\n"
-
383  << " __mlir_aie_try(XAie_LockRelease(" << deviceInstRef << ", "
-
384  << tileLocStr(col, row) << ", XAie_LockInit(l, 0x0), 0));\n";
-
385  if (auto coreOp = tileOp.getCoreOp()) {
-
386  std::string fileName;
-
387  if (auto fileAttr = coreOp.getElfFile())
-
388  fileName = fileAttr.value().str();
-
389  else
-
390  fileName = std::string("core_") + std::to_string(col) + "_" +
-
391  std::to_string(row) + ".elf";
-
392  output << "{\n"
-
393  << "AieRC RC = XAie_LoadElf(" << deviceInstRef << ", "
-
394  << tileLocStr(col, row) << ", "
-
395  << "(const char*)\"" << fileName << "\",0);\n";
-
396  output << "if (RC != XAIE_OK)\n"
-
397  << " __mlir_aie_verbose(fprintf(stderr, \"Failed to load elf "
-
398  "for Core[%d,%d], ret is %d\\n\", "
-
399  << std::to_string(col) << ", " << std::to_string(row)
-
400  << ", RC));\n"
-
401  << "assert(RC == XAIE_OK);\n"
-
402  << "}\n";
-
403  }
-
404  }
-
405  }
-
406  output << "return XAIE_OK;\n";
-
407  output << "} // mlir_aie_configure_cores\n\n";
-
408 
-
409  //---------------------------------------------------------------------------
-
410  // mlir_aie_start_cores
-
411  //---------------------------------------------------------------------------
-
412  output << "int mlir_aie_start_cores(" << ctx_p << ") {\n";
-
413  // Start execution of all the cores.
-
414  for (auto tileOp : targetOp.getOps<TileOp>()) {
-
415  int col = tileOp.colIndex();
-
416  int row = tileOp.rowIndex();
-
417  if (!tileOp.isShimTile() && !tileOp.isMemTile()) {
-
418  output << "__mlir_aie_try(XAie_CoreUnreset(" << deviceInstRef << ", "
-
419  << tileLocStr(col, row) << "));\n";
-
420  output << "__mlir_aie_try(XAie_CoreEnable(" << deviceInstRef << ", "
-
421  << tileLocStr(col, row) << "));\n";
-
422  }
-
423  }
-
424  output << "return XAIE_OK;\n";
-
425  output << "} // mlir_aie_start_cores\n\n";
-
426 
-
427  //---------------------------------------------------------------------------
-
428  // mlir_aie_configure_dmas
-
429  //---------------------------------------------------------------------------
-
430  output << "int mlir_aie_configure_dmas(" << ctx_p << ") {\n";
-
431 
-
432  // DMA configuration
-
433  // AieRC XAie_DmaDescInit(XAie_DevInst *DevInst, XAie_DmaDesc *DmaDesc,
-
434  // XAie_LocType Loc); AieRC XAie_DmaSetLock(XAie_DmaDesc *DmaDesc, XAie_Lock
-
435  // Acq, XAie_Lock Rel); AieRC XAie_DmaSetPkt(XAie_DmaDesc *DmaDesc,
-
436  // XAie_Packet Pkt); AieRC XAie_DmaSetOutofOrderBdId(XAie_DmaDesc *DmaDesc, u8
-
437  // OutofOrderBdId); AieRC XAie_DmaSetDoubleBuffer(XAie_DmaDesc *DmaDesc, u64
-
438  // Addr, XAie_Lock Acq, XAie_Lock Rel); AieRC XAie_DmaSetAddrLen(XAie_DmaDesc
-
439  // *DmaDesc, u64 Addr, u32 Len); AieRC XAie_DmaSetMultiDimAddr(XAie_DmaDesc
-
440  // *DmaDesc, XAie_DmaTensor *Tensor, u64 Addr, u32 Len); AieRC
-
441  // XAie_DmaEnableCompression(XAie_DmaDesc *DmaDesc); AieRC
-
442  // XAie_DmaSetNextBd(XAie_DmaDesc *DmaDesc, u8 NextBd, u8 EnableNextBd); AieRC
-
443  // XAie_DmaEnableBd(XAie_DmaDesc *DmaDesc); AieRC
-
444  // XAie_DmaDisableBd(XAie_DmaDesc *DmaDesc); AieRC XAie_DmaSetAxi(XAie_DmaDesc
-
445  // *DmaDesc, u8 Smid, u8 BurstLen, u8 Qos,u8 Cache, u8 Secure); AieRC
-
446  // XAie_DmaSetInterleaveEnable(XAie_DmaDesc *DmaDesc, u8 DoubleBuff, u8
-
447  // IntrleaveCount, u16 IntrleaveCurr); AieRC XAie_DmaWriteBd(XAie_DevInst
-
448  // *DevInst, XAie_DmaDesc *DmaDesc, XAie_LocType Loc, u8 BdNum);
-
449 
-
450  // AieRC XAie_DmaChannelResetAll(XAie_DevInst *DevInst, XAie_LocType Loc,
-
451  // XAie_DmaChReset Reset); AieRC XAie_DmaChannelReset(XAie_DevInst *DevInst,
-
452  // XAie_LocType Loc, u8 ChNum, XAie_DmaDirection Dir, XAie_DmaChReset Reset);
-
453  // AieRC XAie_DmaChannelPauseStream(XAie_DevInst *DevInst, XAie_LocType Loc,
-
454  // u8 ChNum, XAie_DmaDirection Dir, u8 Pause); AieRC
-
455  // XAie_DmaChannelPauseMem(XAie_DevInst *DevInst, XAie_LocType Loc, u8 ChNum
-
456  // XAie_DmaDirection Dir, u8 Pause); AieRC XAie_DmaChannelConfig(XAie_DevInst
-
457  // *DevInst, XAie_DmaDesc *DmaDesc, XAie_LocType Loc, u8 ChNum,
-
458  // XAie_DmaDirection Dir, u8 RepeatCount, u8 EnTokenIssue, u8 ControllerId);
-
459  // AieRC XAie_DmaChannelPushBdToQueue(XAie_DevInst *DevInst, XAie_LocType Loc,
-
460  // u8 ChNum, XAie_DmaDirection Dir, u8 BdNum); AieRC
-
461  // XAie_DmaChannelEnable(XAie_DevInst *DevInst, XAie_LocType Loc, u8 ChNum,
-
462  // XAie_DmaDirection Dir); AieRC XAie_DmaChannelDisable(XAie_DevInst *DevInst,
-
463  // XAie_LocType Loc, u8 ChNum, XAie_DmaDirection Dir);
-
464  for (auto memOp : targetOp.getOps<MemOp>()) {
-
465  DenseMap<Block *, int> blockMap;
-
466 
-
467  // Assign each block a BD number
-
468  int bdNum = 0;
-
469  for (auto &block : memOp.getBody()) {
-
470  if (!block.getOps<DMABDOp>().empty()) {
-
471  blockMap[&block] = bdNum;
-
472  bdNum++;
-
473  }
-
474  }
-
475  auto result = generateDMAConfig(memOp, output, targetModel, blockMap);
-
476  if (result.failed())
-
477  return result;
-
478  }
-
479  for (auto memOp : targetOp.getOps<MemTileDMAOp>()) {
-
480  DenseMap<Block *, int> blockMap;
-
481  // Memtiles have restrictions on which channels can access which BDs
-
482  DenseMap<Block *, int> channelMap;
-
483 
+
314  DenseMap<TileID, Operation *> tiles;
+
315  DenseMap<Operation *, SmallVector<BufferOp, 4>> buffers;
+
316 
+
317  if (module.getOps<DeviceOp>().empty())
+
318  return module.emitOpError("expected AIE.device operation at toplevel");
+
319  DeviceOp targetOp = *(module.getOps<DeviceOp>().begin());
+
320  const auto &targetModel = targetOp.getTargetModel();
+
321 
+
322  collectTiles(targetOp, tiles);
+
323  collectBuffers(targetOp, buffers);
+
324 
+
325  //---------------------------------------------------------------------------
+
326  // mlir_aie_init_libxaie
+
327  //---------------------------------------------------------------------------
+
328  output << xaie_cpp_file_header;
+
329  output << "aie_libxaie_ctx_t* mlir_aie_init_libxaie() {\n";
+
330  output << " aie_libxaie_ctx_t *ctx = new aie_libxaie_ctx_t;\n";
+
331  output << " if (!ctx)\n";
+
332  output << " return 0;\n";
+
333  auto arch = targetModel.getTargetArch();
+
334  std::string AIE1_device("XAIE_DEV_GEN_AIE");
+
335  std::string AIE2_device("XAIE_DEV_GEN_AIEML");
+
336  std::string AIE2p_device("XAIE_DEV_GEN_AIE2P");
+
337  std::string device;
+
338  switch (arch) {
+
339  case AIEArch::AIE1:
+
340  device = AIE1_device;
+
341  break;
+
342  case AIEArch::AIE2:
+
343  device = AIE2_device;
+
344  break;
+
345  case AIEArch::AIE2p:
+
346  device = AIE2p_device;
+
347  break;
+
348  default:
+
349  return module.emitOpError("Unsupported aie.device");
+
350  }
+
351  output << " ctx->AieConfigPtr.AieGen = " << device << ";\n";
+
352  output << " ctx->AieConfigPtr.BaseAddr = 0x20000000000;\n";
+
353  output << " ctx->AieConfigPtr.ColShift = " << targetModel.getColumnShift()
+
354  << ";\n";
+
355  output << " ctx->AieConfigPtr.RowShift = " << targetModel.getRowShift()
+
356  << ";\n";
+
357  output << " ctx->AieConfigPtr.NumRows = " << targetModel.rows() << ";\n";
+
358  output << " ctx->AieConfigPtr.NumCols = " << targetModel.columns() << ";\n";
+
359  output << " ctx->AieConfigPtr.ShimRowNum = 0;\n";
+
360  output << " ctx->AieConfigPtr.MemTileRowStart = 1;\n";
+
361  output << " ctx->AieConfigPtr.MemTileNumRows = "
+
362  << targetModel.getNumMemTileRows() << ";\n";
+
363  output << " // ctx->AieConfigPtr.ReservedRowStart = "
+
364  "XAIE_RES_TILE_ROW_START;\n";
+
365  output
+
366  << " // ctx->AieConfigPtr.ReservedNumRows = XAIE_RES_TILE_NUM_ROWS;\n";
+
367  output << " ctx->AieConfigPtr.AieTileRowStart = "
+
368  << (1 + targetModel.getNumMemTileRows()) << ";\n";
+
369  output << " ctx->AieConfigPtr.AieTileNumRows = "
+
370  << (targetModel.rows() - 1 - targetModel.getNumMemTileRows()) << ";\n";
+
371  output << " ctx->AieConfigPtr.PartProp = {0};\n";
+
372  output << " ctx->DevInst = {0};\n";
+
373  output << " return ctx;\n";
+
374  output << "}\n";
+
375  output << "\n";
+
376 
+
377  //---------------------------------------------------------------------------
+
378  // mlir_aie_configure_cores
+
379  //---------------------------------------------------------------------------
+
380  output << "int mlir_aie_configure_cores(" << ctx_p << ") {\n";
+
381  // Reset each core. Load the corresponding ELF file, if necessary.
+
382  for (auto tileOp : targetOp.getOps<TileOp>()) {
+
383  int col = tileOp.colIndex();
+
384  int row = tileOp.rowIndex();
+
385  if (tileOp.isShimTile() || tileOp.isMemTile()) {
+
386  // Resets no needed with V2 kernel driver
+
387  } else {
+
388  // Resets no needed with V2 kernel driver
+
389  output << "__mlir_aie_try(XAie_CoreReset(" << deviceInstRef << ", "
+
390  << tileLocStr(col, row) << "));\n";
+
391  output << "__mlir_aie_try(XAie_CoreDisable(" << deviceInstRef << ", "
+
392  << tileLocStr(col, row) << "));\n";
+
393  // Release locks
+
394  int numLocks = targetModel.getNumLocks(col, row);
+
395  output << "for (int l = 0; l < " << numLocks << "; ++l)\n"
+
396  << " __mlir_aie_try(XAie_LockRelease(" << deviceInstRef << ", "
+
397  << tileLocStr(col, row) << ", XAie_LockInit(l, 0x0), 0));\n";
+
398  if (auto coreOp = tileOp.getCoreOp()) {
+
399  std::string fileName;
+
400  if (auto fileAttr = coreOp.getElfFile())
+
401  fileName = fileAttr.value().str();
+
402  else
+
403  fileName = std::string("core_") + std::to_string(col) + "_" +
+
404  std::to_string(row) + ".elf";
+
405  output << "{\n"
+
406  << "AieRC RC = XAie_LoadElf(" << deviceInstRef << ", "
+
407  << tileLocStr(col, row) << ", "
+
408  << "(const char*)\"" << fileName << "\",0);\n";
+
409  output << "if (RC != XAIE_OK)\n"
+
410  << " __mlir_aie_verbose(fprintf(stderr, \"Failed to load elf "
+
411  "for Core[%d,%d], ret is %d\\n\", "
+
412  << std::to_string(col) << ", " << std::to_string(row)
+
413  << ", RC));\n"
+
414  << "assert(RC == XAIE_OK);\n"
+
415  << "}\n";
+
416  }
+
417  }
+
418  }
+
419  output << "return XAIE_OK;\n";
+
420  output << "} // mlir_aie_configure_cores\n\n";
+
421 
+
422  //---------------------------------------------------------------------------
+
423  // mlir_aie_start_cores
+
424  //---------------------------------------------------------------------------
+
425  output << "int mlir_aie_start_cores(" << ctx_p << ") {\n";
+
426  // Start execution of all the cores.
+
427  for (auto tileOp : targetOp.getOps<TileOp>()) {
+
428  int col = tileOp.colIndex();
+
429  int row = tileOp.rowIndex();
+
430  if (!tileOp.isShimTile() && !tileOp.isMemTile()) {
+
431  output << "__mlir_aie_try(XAie_CoreUnreset(" << deviceInstRef << ", "
+
432  << tileLocStr(col, row) << "));\n";
+
433  output << "__mlir_aie_try(XAie_CoreEnable(" << deviceInstRef << ", "
+
434  << tileLocStr(col, row) << "));\n";
+
435  }
+
436  }
+
437  output << "return XAIE_OK;\n";
+
438  output << "} // mlir_aie_start_cores\n\n";
+
439 
+
440  //---------------------------------------------------------------------------
+
441  // mlir_aie_configure_dmas
+
442  //---------------------------------------------------------------------------
+
443  output << "int mlir_aie_configure_dmas(" << ctx_p << ") {\n";
+
444 
+
445  for (auto memOp : targetOp.getOps<MemOp>()) {
+
446  DenseMap<Block *, int> blockMap;
+
447 
+
448  // Assign each block a BD number
+
449  int bdNum = 0;
+
450  for (auto &block : memOp.getBody()) {
+
451  if (!block.getOps<DMABDOp>().empty()) {
+
452  blockMap[&block] = bdNum;
+
453  bdNum++;
+
454  }
+
455  }
+
456  auto result = generateDMAConfig(memOp, output, targetModel, blockMap);
+
457  if (result.failed())
+
458  return result;
+
459  }
+
460  for (auto memOp : targetOp.getOps<MemTileDMAOp>()) {
+
461  DenseMap<Block *, int> blockMap;
+
462  // Memtiles have restrictions on which channels can access which BDs
+
463  DenseMap<Block *, int> channelMap;
+
464 
+
465  for (auto &block : memOp.getBody()) {
+
466  for (auto op : block.getOps<DMAStartOp>()) {
+
467  int chNum = op.getChannelIndex();
+
468  channelMap[&block] = chNum;
+
469  auto dest = op.getDest();
+
470  while (dest) {
+
471  channelMap[dest] = chNum;
+
472  if (dest->getSuccessors().size() < 1)
+
473  break;
+
474  dest = dest->getSuccessors()[0];
+
475  if (channelMap.count(dest))
+
476  break;
+
477  }
+
478  }
+
479  }
+
480 
+
481  // Assign each block a BD number
+
482  int evenBdNum = 0;
+
483  int oddBdNum = 24;
484  for (auto &block : memOp.getBody()) {
-
485  for (auto op : block.getOps<DMAStartOp>()) {
-
486  int chNum = op.getChannelIndex();
-
487  channelMap[&block] = chNum;
-
488  auto dest = op.getDest();
-
489  while (dest) {
-
490  channelMap[dest] = chNum;
-
491  if (dest->getSuccessors().size() < 1)
-
492  break;
-
493  dest = dest->getSuccessors()[0];
-
494  if (channelMap.count(dest))
-
495  break;
-
496  }
-
497  }
-
498  }
-
499 
-
500  // Assign each block a BD number
-
501  int evenBdNum = 0;
-
502  int oddBdNum = 24;
-
503  for (auto &block : memOp.getBody()) {
-
504  if (block.getOps<DMABDOp>().empty())
-
505  continue;
-
506  assert(channelMap.count(&block));
-
507  if (channelMap[&block] & 1)
-
508  blockMap[&block] = oddBdNum++;
-
509  else
-
510  blockMap[&block] = evenBdNum++;
-
511  }
-
512  auto result = generateDMAConfig(memOp, output, targetModel, blockMap);
-
513  if (result.failed())
-
514  return result;
-
515  }
-
516 
-
517  output << "return XAIE_OK;\n";
-
518  output << "} // mlir_aie_configure_dmas\n\n";
+
485  if (block.getOps<DMABDOp>().empty())
+
486  continue;
+
487  assert(channelMap.count(&block));
+
488  if (channelMap[&block] & 1)
+
489  blockMap[&block] = oddBdNum++;
+
490  else
+
491  blockMap[&block] = evenBdNum++;
+
492  }
+
493  auto result = generateDMAConfig(memOp, output, targetModel, blockMap);
+
494  if (result.failed())
+
495  return result;
+
496  }
+
497 
+
498  output << "return XAIE_OK;\n";
+
499  output << "} // mlir_aie_configure_dmas\n\n";
+
500 
+
501  for (auto op : targetOp.getOps<ExternalBufferOp>()) {
+
502  if (op.hasName()) {
+
503  output << "static u64 _mlir_aie_external_" << op.name().getValue()
+
504  << ";\n";
+
505  output << "static bool _mlir_aie_external_set_" << op.name().getValue()
+
506  << " = false;\n";
+
507 
+
508  output << "void mlir_aie_external_set_addr_" << op.name().getValue()
+
509  << "(" << ctx_p << ", u64 VA) {\n"
+
510  << " u64 device_address = mlir_aie_get_device_address(ctx, (void "
+
511  "*)VA);\n"
+
512  << " _mlir_aie_external_set_" << op.name().getValue()
+
513  << " = true;\n"
+
514  << " _mlir_aie_external_" << op.name().getValue()
+
515  << " = device_address;\n"
+
516  << "}\n";
+
517  }
+
518  }
519 
-
520  for (auto op : targetOp.getOps<ExternalBufferOp>()) {
-
521  if (op.hasName()) {
-
522  output << "static u64 _mlir_aie_external_" << op.name().getValue()
-
523  << ";\n";
-
524  output << "static bool _mlir_aie_external_set_" << op.name().getValue()
-
525  << " = false;\n";
-
526 
-
527  output << "void mlir_aie_external_set_addr_" << op.name().getValue()
-
528  << "(" << ctx_p << ", u64 VA) {\n"
-
529  << " u64 device_address = mlir_aie_get_device_address(ctx, (void "
-
530  "*)VA);\n"
-
531  << " _mlir_aie_external_set_" << op.name().getValue()
-
532  << " = true;\n"
-
533  << " _mlir_aie_external_" << op.name().getValue()
-
534  << " = device_address;\n"
-
535  << "}\n";
-
536  }
-
537  }
+
520  // ShimDMA Config
+
521  // int index = 0;
+
522  for (auto op : targetOp.getOps<ShimDMAOp>()) {
+
523  int col = op.colIndex();
+
524  int row = op.rowIndex();
+
525 
+
526  DenseMap<Block *, int> blockMap;
+
527  {
+
528  // Assign each block a BD number
+
529  int bdNum = 0;
+
530  for (auto &block : op.getBody()) {
+
531  if (!block.getOps<DMABDOp>().empty()) {
+
532  blockMap[&block] = bdNum;
+
533  uint64_t offset = 0;
+
534  for (auto op : block.getOps<DMABDOp>()) {
+
535  offset = op.getOffsetInBytes();
+
536  auto buffer =
+
537  cast<ExternalBufferOp>(op.getBuffer().getDefiningOp());
538 
-
539  // ShimDMA Config
-
540  // int index = 0;
-
541  for (auto op : targetOp.getOps<ShimDMAOp>()) {
-
542  int col = op.colIndex();
-
543  int row = op.rowIndex();
-
544 
-
545  DenseMap<Block *, int> blockMap;
-
546  {
-
547  // Assign each block a BD number
-
548  int bdNum = 0;
-
549  for (auto &block : op.getBody()) {
-
550  if (!block.getOps<DMABDOp>().empty()) {
-
551  blockMap[&block] = bdNum;
-
552  uint64_t offset = 0;
-
553  for (auto op : block.getOps<DMABDOp>()) {
-
554  offset = op.getOffsetInBytes();
-
555  auto buffer =
-
556  cast<ExternalBufferOp>(op.getBuffer().getDefiningOp());
-
557 
-
558  output << "u64 mlir_aie_external_get_addr_myBuffer_" << col << row
-
559  << "_" << bdNum << "(void) {\n"
-
560  << " assert(_mlir_aie_external_set_"
-
561  << buffer.name().getValue() << ");\n"
-
562  << " return _mlir_aie_external_"
-
563  << buffer.name().getValue() << " + "
-
564  << llvm::utohexstr(offset) << ";\n"
-
565  << "}\n";
-
566  }
-
567 
-
568  bdNum++;
-
569  }
-
570  }
-
571  }
-
572 
-
573  output << "int mlir_aie_configure_shimdma_" << col << row << "(" << ctx_p
-
574  << ") {\n";
-
575  auto result = generateDMAConfig(op, output, targetModel, blockMap);
-
576  if (result.failed())
-
577  return result;
-
578  output << "return XAIE_OK;\n";
-
579  output << "} // mlir_aie_configure_shimdma\n\n";
-
580  }
+
539  output << "u64 mlir_aie_external_get_addr_myBuffer_" << col << row
+
540  << "_" << bdNum << "(void) {\n"
+
541  << " assert(_mlir_aie_external_set_"
+
542  << buffer.name().getValue() << ");\n"
+
543  << " return _mlir_aie_external_"
+
544  << buffer.name().getValue() << " + "
+
545  << llvm::utohexstr(offset) << ";\n"
+
546  << "}\n";
+
547  }
+
548 
+
549  bdNum++;
+
550  }
+
551  }
+
552  }
+
553 
+
554  output << "int mlir_aie_configure_shimdma_" << col << row << "(" << ctx_p
+
555  << ") {\n";
+
556  auto result = generateDMAConfig(op, output, targetModel, blockMap);
+
557  if (result.failed())
+
558  return result;
+
559  output << "return XAIE_OK;\n";
+
560  output << "} // mlir_aie_configure_shimdma\n\n";
+
561  }
+
562 
+
563  //---------------------------------------------------------------------------
+
564  // mlir_aie_initialize_locks
+
565  //---------------------------------------------------------------------------
+
566  output << "int mlir_aie_initialize_locks(" << ctx_p << ") {\n";
+
567  // Lock configuration
+
568  targetOp.walk<WalkOrder::PreOrder>([&](LockOp lock) {
+
569  TileOp tile = lock.getTileOp();
+
570  int col = tile.colIndex();
+
571  int row = tile.rowIndex();
+
572  int lockID = lock.getLockIDValue();
+
573  auto init = lock.getInit();
+
574  if (init)
+
575  output << "__mlir_aie_try(XAie_LockSetValue(" << deviceInstRef << ", "
+
576  << tileLocStr(col, row) << ", "
+
577  << "XAie_LockInit(" << lockID << ", " << *init << ")));\n";
+
578  });
+
579  output << "return XAIE_OK;\n";
+
580  output << "} // mlir_aie_initialize_locks\n";
581 
582  //---------------------------------------------------------------------------
-
583  // mlir_aie_initialize_locks
+
583  // mlir_aie_configure_switchboxes
584  //---------------------------------------------------------------------------
-
585  output << "int mlir_aie_initialize_locks(" << ctx_p << ") {\n";
-
586  // Lock configuration
-
587  targetOp.walk<WalkOrder::PreOrder>([&](LockOp lock) {
-
588  TileOp tile = lock.getTileOp();
-
589  int col = tile.colIndex();
-
590  int row = tile.rowIndex();
-
591  int lockID = lock.getLockIDValue();
-
592  auto init = lock.getInit();
-
593  if (init)
-
594  output << "__mlir_aie_try(XAie_LockSetValue(" << deviceInstRef << ", "
-
595  << tileLocStr(col, row) << ", "
-
596  << "XAie_LockInit(" << lockID << ", " << *init << ")));\n";
-
597  });
-
598  output << "return XAIE_OK;\n";
-
599  output << "} // mlir_aie_initialize_locks\n";
-
600 
-
601  //---------------------------------------------------------------------------
-
602  // mlir_aie_configure_switchboxes
-
603  //---------------------------------------------------------------------------
-
604  output << "int mlir_aie_configure_switchboxes(" << ctx_p << ") {\n";
-
605  output << " int x, y;\n";
-
606 
-
607  // StreamSwitch (switchbox) configuration
-
608  for (auto switchboxOp : targetOp.getOps<SwitchboxOp>()) {
-
609  Region &r = switchboxOp.getConnections();
-
610  Block &b = r.front();
-
611  bool isEmpty = b.getOps<ConnectOp>().empty() &&
-
612  b.getOps<MasterSetOp>().empty() &&
-
613  b.getOps<PacketRulesOp>().empty();
-
614  bool isParam = false;
-
615 
-
616  if (isa<TileOp>(switchboxOp.getTile().getDefiningOp())) {
-
617  int col = switchboxOp.colIndex();
-
618  int row = switchboxOp.rowIndex();
-
619  if (!isEmpty) {
-
620  output << "// Core Stream Switch column " << col << " row " << row
-
621  << "\n";
-
622  output << "x = " << col << ";\n";
-
623  output << "y = " << row << ";\n";
-
624  }
-
625  } else if (auto sel =
-
626  dyn_cast<SelectOp>(switchboxOp.getTile().getDefiningOp())) {
-
627  // parameterize streamswitch's configuration
-
628  isParam = true;
-
629  HerdOp sourceHerd = cast<HerdOp>(sel.getStartHerd().getDefiningOp());
-
630  std::string sourceHerdName(sourceHerd.name().getValue());
-
631 
-
632  IterOp iterX = cast<IterOp>(sel.getIterX().getDefiningOp());
-
633  IterOp iterY = cast<IterOp>(sel.getIterY().getDefiningOp());
-
634  int startXValue = iterX.getStartValue();
-
635  int endXValue = iterX.getEndValue();
-
636  int strideXValue = iterX.getStrideValue();
-
637  int startYValue = iterY.getStartValue();
-
638  int endYValue = iterY.getEndValue();
-
639  int strideYValue = iterY.getStrideValue();
-
640 
-
641  std::string startX(sourceHerdName + "_X + " +
-
642  std::to_string(startXValue));
-
643  std::string endX(sourceHerdName + "_X + " + std::to_string(endXValue));
-
644  std::string startY(sourceHerdName + "_Y + " +
-
645  std::to_string(startYValue));
-
646  std::string endY(sourceHerdName + "_Y + " + std::to_string(endYValue));
-
647 
-
648  output << "for (x = " << startX << "; x < " << endX
-
649  << "; x += " << strideXValue << ") {\n";
-
650  output << "for (y = " << startY << "; y < " << endY
-
651  << "; y += " << strideYValue << ") {\n";
-
652  }
+
585  output << "int mlir_aie_configure_switchboxes(" << ctx_p << ") {\n";
+
586  output << " int x, y;\n";
+
587 
+
588  // StreamSwitch (switchbox) configuration
+
589  for (auto switchboxOp : targetOp.getOps<SwitchboxOp>()) {
+
590  Region &r = switchboxOp.getConnections();
+
591  Block &b = r.front();
+
592  bool isEmpty = b.getOps<ConnectOp>().empty() &&
+
593  b.getOps<MasterSetOp>().empty() &&
+
594  b.getOps<PacketRulesOp>().empty();
+
595  bool isParam = false;
+
596 
+
597  if (isa<TileOp>(switchboxOp.getTile().getDefiningOp())) {
+
598  int col = switchboxOp.colIndex();
+
599  int row = switchboxOp.rowIndex();
+
600  if (!isEmpty) {
+
601  output << "// Core Stream Switch column " << col << " row " << row
+
602  << "\n";
+
603  output << "x = " << col << ";\n";
+
604  output << "y = " << row << ";\n";
+
605  }
+
606  } else if (auto sel =
+
607  dyn_cast<SelectOp>(switchboxOp.getTile().getDefiningOp())) {
+
608  // parameterize streamswitch's configuration
+
609  isParam = true;
+
610  HerdOp sourceHerd = cast<HerdOp>(sel.getStartHerd().getDefiningOp());
+
611  std::string sourceHerdName(sourceHerd.name().getValue());
+
612 
+
613  IterOp iterX = cast<IterOp>(sel.getIterX().getDefiningOp());
+
614  IterOp iterY = cast<IterOp>(sel.getIterY().getDefiningOp());
+
615  int startXValue = iterX.getStartValue();
+
616  int endXValue = iterX.getEndValue();
+
617  int strideXValue = iterX.getStrideValue();
+
618  int startYValue = iterY.getStartValue();
+
619  int endYValue = iterY.getEndValue();
+
620  int strideYValue = iterY.getStrideValue();
+
621 
+
622  std::string startX(sourceHerdName + "_X + " +
+
623  std::to_string(startXValue));
+
624  std::string endX(sourceHerdName + "_X + " + std::to_string(endXValue));
+
625  std::string startY(sourceHerdName + "_Y + " +
+
626  std::to_string(startYValue));
+
627  std::string endY(sourceHerdName + "_Y + " + std::to_string(endYValue));
+
628 
+
629  output << "for (x = " << startX << "; x < " << endX
+
630  << "; x += " << strideXValue << ") {\n";
+
631  output << "for (y = " << startY << "; y < " << endY
+
632  << "; y += " << strideYValue << ") {\n";
+
633  }
+
634 
+
635  for (auto connectOp : b.getOps<ConnectOp>())
+
636  output << "__mlir_aie_try(XAie_StrmConnCctEnable(" << deviceInstRef
+
637  << ", " << tileLocStr("x", "y") << ", "
+
638  << wireBundleToPortType(connectOp.getSourceBundle()) << ", "
+
639  << connectOp.sourceIndex() << ", "
+
640  << wireBundleToPortType(connectOp.getDestBundle()) << ", "
+
641  << connectOp.destIndex() << "));\n";
+
642 
+
643  for (auto connectOp : b.getOps<MasterSetOp>()) {
+
644  int mask = 0;
+
645  int arbiter = -1;
+
646  for (auto val : connectOp.getAmsels()) {
+
647  AMSelOp amsel = cast<AMSelOp>(val.getDefiningOp());
+
648  arbiter = amsel.arbiterIndex();
+
649  int msel = amsel.getMselValue();
+
650  mask |= (1 << msel);
+
651  }
+
652  bool isdma = (connectOp.getDestBundle() == WireBundle::DMA);
653 
-
654  for (auto connectOp : b.getOps<ConnectOp>())
-
655  output << "__mlir_aie_try(XAie_StrmConnCctEnable(" << deviceInstRef
-
656  << ", " << tileLocStr("x", "y") << ", "
-
657  << stringifyWireBundle(connectOp.getSourceBundle()).upper() << ", "
-
658  << connectOp.sourceIndex() << ", "
-
659  << stringifyWireBundle(connectOp.getDestBundle()).upper() << ", "
-
660  << connectOp.destIndex() << "));\n";
-
661 
-
662  for (auto connectOp : b.getOps<MasterSetOp>()) {
-
663  int mask = 0;
-
664  int arbiter = -1;
-
665  for (auto val : connectOp.getAmsels()) {
-
666  AMSelOp amsel = cast<AMSelOp>(val.getDefiningOp());
-
667  arbiter = amsel.arbiterIndex();
-
668  int msel = amsel.getMselValue();
-
669  mask |= (1 << msel);
-
670  }
-
671  bool isdma = (connectOp.getDestBundle() == WireBundle::DMA);
-
672 
-
673  output << "__mlir_aie_try(XAie_StrmPktSwMstrPortEnable(" << deviceInstRef
-
674  << ", " << tileLocStr("x", "y") << ", "
-
675  << stringifyWireBundle(connectOp.getDestBundle()).upper() << ", "
-
676  << connectOp.destIndex() << ", "
-
677  << "/* drop_header */ "
-
678  << (isdma ? "XAIE_SS_PKT_DROP_HEADER"
-
679  : "XAIE_SS_PKT_DONOT_DROP_HEADER")
-
680  << ", "
-
681  << "/* arbiter */ " << arbiter << ", "
-
682  << "/* MSelEn */ "
-
683  << "0x" << llvm::utohexstr(mask) << "));\n";
-
684  }
-
685 
-
686  for (auto connectOp : b.getOps<PacketRulesOp>()) {
-
687  int slot = 0;
-
688  Block &block = connectOp.getRules().front();
-
689  for (auto slotOp : block.getOps<PacketRuleOp>()) {
-
690  AMSelOp amselOp = cast<AMSelOp>(slotOp.getAmsel().getDefiningOp());
-
691  int arbiter = amselOp.arbiterIndex();
-
692  int msel = amselOp.getMselValue();
-
693  output << "__mlir_aie_try(XAie_StrmPktSwSlavePortEnable("
-
694  << deviceInstRef << ", " << tileLocStr("x", "y") << ", "
-
695  << stringifyWireBundle(connectOp.getSourceBundle()).upper()
-
696  << ", " << connectOp.sourceIndex() << "));\n";
-
697 
-
698  // TODO Need to better define packet id,type used here
-
699  output << "__mlir_aie_try(XAie_StrmPktSwSlaveSlotEnable("
-
700  << deviceInstRef << ", " << tileLocStr("x", "y") << ", "
-
701  << stringifyWireBundle(connectOp.getSourceBundle()).upper()
-
702  << ", " << connectOp.sourceIndex() << ", "
-
703  << "/* slot */ " << slot << ", "
-
704  << "/* packet */ " << packetStr(slotOp.valueInt(), /*type*/ 0)
-
705  << ", "
-
706  << "/* mask */ "
-
707  << "0x" << llvm::utohexstr(slotOp.maskInt()) << ", "
-
708  << "/* msel */ " << msel << ", "
-
709  << "/* arbiter */ " << arbiter << "));\n";
-
710  slot++;
-
711  }
-
712  }
-
713 
-
714  if (isParam) {
-
715  output << "}\n";
-
716  output << "}\n";
-
717  }
-
718  }
-
719  for (auto op : targetOp.getOps<ShimMuxOp>()) {
-
720  Region &r = op.getConnections();
-
721  Block &b = r.front();
-
722  bool isEmpty = b.getOps<ConnectOp>().empty();
-
723 
-
724  if (isa<TileOp>(op.getTile().getDefiningOp())) {
-
725  int col = op.colIndex();
-
726  int row = op.rowIndex();
-
727  if (!isEmpty) {
-
728  output << "// ShimMux column " << col << " row " << row << "\n";
-
729  output << "// NOTE ShimMux always connects from the south as "
-
730  << "directions are defined relative to the tile stream "
-
731  << "switch\n";
-
732  output << "x = " << col << ";\n";
-
733  output << "y = " << row << ";\n";
-
734  }
-
735  }
-
736 
-
737  for (auto connectOp : b.getOps<ConnectOp>()) {
-
738 
-
739  if (connectOp.getSourceBundle() == WireBundle::DMA ||
-
740  connectOp.getDestBundle() == WireBundle::DMA) {
-
741  if (connectOp.getSourceBundle() == WireBundle::North)
-
742  // demux!
-
743  output
-
744  << "__mlir_aie_try(XAie_EnableAieToShimDmaStrmPort("
-
745  << deviceInstRef << ", " << tileLocStr("x", "y")
-
746  << ", "
-
747  // <<
-
748  // stringifyWireBundle(connectOp.sourceBundle()).upper()
-
749  << connectOp.sourceIndex() << "));\n";
-
750  else if (connectOp.getDestBundle() == WireBundle::North)
-
751  // mux
-
752  output
-
753  << "__mlir_aie_try(XAie_EnableShimDmaToAieStrmPort("
-
754  << deviceInstRef << ", " << tileLocStr("x", "y")
-
755  << ", "
-
756  // <<
-
757  // stringifyWireBundle(connectOp.sourceBundle()).upper()
-
758  << connectOp.destIndex() << "));\n";
-
759  }
-
760 
-
761  else if (connectOp.getSourceBundle() == WireBundle::PLIO ||
-
762  connectOp.getDestBundle() == WireBundle::PLIO) {
-
763  if (connectOp.getSourceBundle() == WireBundle::North) {
-
764  // mux
-
765  output << "__mlir_aie_try(XAie_AieToPlIntfEnable(" << deviceInstRef
-
766  << ", " << tileLocStr("x", "y") << ", "
-
767  << connectOp.destIndex() << ", PLIF_WIDTH_64));\n";
-
768  } else if (connectOp.getDestBundle() == WireBundle::North) {
-
769  // mux
-
770  output << "__mlir_aie_try(XAie_PlToAieIntfEnable(" << deviceInstRef
-
771  << ", " << tileLocStr("x", "y") << ", "
-
772  << connectOp.destIndex() << ", PLIF_WIDTH_64));\n";
-
773  }
-
774  }
-
775  }
-
776  }
-
777  for (auto switchboxOp : targetOp.getOps<ShimSwitchboxOp>()) {
-
778  Region &r = switchboxOp.getConnections();
-
779  Block &b = r.front();
-
780  bool isEmpty = b.getOps<ConnectOp>().empty();
-
781  int col = switchboxOp.getCol();
-
782  if (!isEmpty)
-
783  output << "// Shim Switch column " << col << "\n";
-
784  for (auto connectOp : b.getOps<ConnectOp>())
-
785  output << "__mlir_aie_try(XAie_StrmConnCctEnable(" << deviceInstRef
-
786  << ", " << tileLocStr(col, 0) << ", "
-
787  << stringifyWireBundle(connectOp.getSourceBundle()).upper() << ", "
-
788  << connectOp.sourceIndex() << ", "
-
789  << stringifyWireBundle(connectOp.getDestBundle()).upper() << ", "
-
790  << connectOp.destIndex() << "));\n";
-
791  }
-
792 
-
793  output << "return XAIE_OK;\n";
-
794  output << "} // mlir_aie_configure_switchboxes\n\n";
-
795 
-
796  //---------------------------------------------------------------------------
-
797  // mlir_aie_configure_cascade
-
798  //---------------------------------------------------------------------------
-
799  output << "int mlir_aie_configure_cascade(" << ctx_p << ") {\n";
-
800  for (auto configOp : targetOp.getOps<ConfigureCascadeOp>()) {
-
801  TileOp tile = cast<TileOp>(configOp.getTile().getDefiningOp());
-
802  int col = tile.colIndex();
-
803  int row = tile.rowIndex();
-
804  output << "XAie_CoreConfigAccumulatorControl(" << deviceInstRef << ", "
-
805  << "XAie_TileLoc(" << col << ", " << row << "), "
-
806  << stringifyCascadeDir(configOp.getInputDir()).upper() << ", "
-
807  << stringifyCascadeDir(configOp.getOutputDir()).upper() << ");\n";
-
808  }
-
809  output << "return XAIE_OK;\n";
-
810  output << "} // mlir_aie_configure_cascade\n\n";
-
811 
-
812  //---------------------------------------------------------------------------
-
813  // Output Buffer Accessors
-
814  //---------------------------------------------------------------------------
-
815  for (auto tile : tiles) {
-
816  Operation *tileOp = tile.second;
-
817  TileID coord = cast<TileOp>(tileOp).getTileID();
-
818  int col = coord.col;
-
819  int row = coord.row;
-
820  auto loc = tileLocStr(col, row);
-
821 
-
822  auto bufferAccessor = [&](BufferOp buf) {
-
823  // int32_t mlir_aie_read_buffer_a13(int index) {
-
824  // void mlir_aie_write_buffer_a13(int index, int32_t value) {
-
825  std::string bufName(buf.name().getValue());
-
826  Type t = buf.getType();
-
827  Type et;
-
828  std::string typestr;
-
829  if (auto memrefType = llvm::dyn_cast<MemRefType>(t)) {
-
830  et = memrefType.getElementType();
-
831  if (et.isInteger(32))
-
832  typestr = "int32_t";
-
833  else if (et.isF32())
-
834  typestr = "float";
-
835  else {
-
836  output << "// buffer " << bufName << " with unsupported type " << t
-
837  << ";\n";
-
838  return; // Unsupported type
-
839  }
-
840 
-
841  } else {
-
842  output << "// buffer " << bufName << " with unsupported type " << t
-
843  << ";\n";
-
844  return; // Unsupported type
-
845  }
-
846  assert(buf.getAddress().has_value() && "buffer must have address");
-
847  output << "const int " << bufName
-
848  << "_offset = " << buf.getAddress().value() << ";\n";
-
849  output << typestr << " mlir_aie_read_buffer_" << bufName << "(" << ctx_p
-
850  << ", int index) {\n";
-
851  output << "u32 value; auto rc = XAie_DataMemRdWord(" << deviceInstRef
-
852  << ", " << loc << ", " << bufName
-
853  << "_offset + (index*4), &value);\n";
-
854  if (et.isInteger(32))
-
855  output << " return value;\n";
-
856  else if (et.isF32()) {
-
857  output << " union caster { int32_t i; float f; };\n";
-
858  output << " caster c; c.i = value;\n";
-
859  output << " return c.f;\n";
-
860  }
-
861  output << "}\n";
-
862  output << "int mlir_aie_write_buffer_" << bufName << "(" << ctx_p
-
863  << ", int index, " << typestr << " value) {\n";
-
864  if (et.isInteger(32))
-
865  output << " int32_t int_value = value;\n";
-
866  else if (et.isF32()) {
-
867  output << " union caster { int32_t i; float f; };\n";
-
868  output << " caster c; c.f = value;\n";
-
869  output << " int32_t int_value = c.i;\n";
-
870  }
-
871  output << "AieRC rc = XAie_DataMemWrWord(" << deviceInstRef << ", "
-
872  << loc << ", " << bufName << "_offset + (index*4), int_value);\n";
-
873  output << "return rc;\n";
-
874  output << "}\n";
-
875  };
+
654  output << "__mlir_aie_try(XAie_StrmPktSwMstrPortEnable(" << deviceInstRef
+
655  << ", " << tileLocStr("x", "y") << ", "
+
656  << wireBundleToPortType(connectOp.getDestBundle()) << ", "
+
657  << connectOp.destIndex() << ", "
+
658  << "/* drop_header */ "
+
659  << (isdma ? "XAIE_SS_PKT_DROP_HEADER"
+
660  : "XAIE_SS_PKT_DONOT_DROP_HEADER")
+
661  << ", "
+
662  << "/* arbiter */ " << arbiter << ", "
+
663  << "/* MSelEn */ "
+
664  << "0x" << llvm::utohexstr(mask) << "));\n";
+
665  }
+
666 
+
667  for (auto connectOp : b.getOps<PacketRulesOp>()) {
+
668  int slot = 0;
+
669  Block &block = connectOp.getRules().front();
+
670  for (auto slotOp : block.getOps<PacketRuleOp>()) {
+
671  AMSelOp amselOp = cast<AMSelOp>(slotOp.getAmsel().getDefiningOp());
+
672  int arbiter = amselOp.arbiterIndex();
+
673  int msel = amselOp.getMselValue();
+
674  output << "__mlir_aie_try(XAie_StrmPktSwSlavePortEnable("
+
675  << deviceInstRef << ", " << tileLocStr("x", "y") << ", "
+
676  << wireBundleToPortType(connectOp.getSourceBundle()) << ", "
+
677  << connectOp.sourceIndex() << "));\n";
+
678 
+
679  // TODO Need to better define packet id,type used here
+
680  output << "__mlir_aie_try(XAie_StrmPktSwSlaveSlotEnable("
+
681  << deviceInstRef << ", " << tileLocStr("x", "y") << ", "
+
682  << wireBundleToPortType(connectOp.getSourceBundle()) << ", "
+
683  << connectOp.sourceIndex() << ", "
+
684  << "/* slot */ " << slot << ", "
+
685  << "/* packet */ " << packetStr(slotOp.valueInt(), /*type*/ 0)
+
686  << ", "
+
687  << "/* mask */ "
+
688  << "0x" << llvm::utohexstr(slotOp.maskInt()) << ", "
+
689  << "/* msel */ " << msel << ", "
+
690  << "/* arbiter */ " << arbiter << "));\n";
+
691  slot++;
+
692  }
+
693  }
+
694 
+
695  if (isParam) {
+
696  output << "}\n";
+
697  output << "}\n";
+
698  }
+
699  }
+
700  for (auto op : targetOp.getOps<ShimMuxOp>()) {
+
701  Region &r = op.getConnections();
+
702  Block &b = r.front();
+
703  bool isEmpty = b.getOps<ConnectOp>().empty();
+
704 
+
705  if (isa<TileOp>(op.getTile().getDefiningOp())) {
+
706  int col = op.colIndex();
+
707  int row = op.rowIndex();
+
708  if (!isEmpty) {
+
709  output << "// ShimMux column " << col << " row " << row << "\n";
+
710  output << "// NOTE ShimMux always connects from the south as "
+
711  << "directions are defined relative to the tile stream "
+
712  << "switch\n";
+
713  output << "x = " << col << ";\n";
+
714  output << "y = " << row << ";\n";
+
715  }
+
716  }
+
717 
+
718  for (auto connectOp : b.getOps<ConnectOp>()) {
+
719 
+
720  if (connectOp.getSourceBundle() == WireBundle::DMA ||
+
721  connectOp.getDestBundle() == WireBundle::DMA) {
+
722  if (connectOp.getSourceBundle() == WireBundle::North)
+
723  // demux!
+
724  output << "__mlir_aie_try(XAie_EnableAieToShimDmaStrmPort("
+
725  << deviceInstRef << ", " << tileLocStr("x", "y") << ", "
+
726  << connectOp.sourceIndex() << "));\n";
+
727  else if (connectOp.getDestBundle() == WireBundle::North)
+
728  // mux
+
729  output << "__mlir_aie_try(XAie_EnableShimDmaToAieStrmPort("
+
730  << deviceInstRef << ", " << tileLocStr("x", "y") << ", "
+
731  << connectOp.destIndex() << "));\n";
+
732  }
+
733 
+
734  else if (connectOp.getSourceBundle() == WireBundle::PLIO ||
+
735  connectOp.getDestBundle() == WireBundle::PLIO) {
+
736  if (connectOp.getSourceBundle() == WireBundle::North) {
+
737  // mux
+
738  output << "__mlir_aie_try(XAie_AieToPlIntfEnable(" << deviceInstRef
+
739  << ", " << tileLocStr("x", "y") << ", "
+
740  << connectOp.destIndex() << ", PLIF_WIDTH_64));\n";
+
741  } else if (connectOp.getDestBundle() == WireBundle::North) {
+
742  // mux
+
743  output << "__mlir_aie_try(XAie_PlToAieIntfEnable(" << deviceInstRef
+
744  << ", " << tileLocStr("x", "y") << ", "
+
745  << connectOp.destIndex() << ", PLIF_WIDTH_64));\n";
+
746  }
+
747  }
+
748  }
+
749  }
+
750  for (auto switchboxOp : targetOp.getOps<ShimSwitchboxOp>()) {
+
751  Region &r = switchboxOp.getConnections();
+
752  Block &b = r.front();
+
753  bool isEmpty = b.getOps<ConnectOp>().empty();
+
754  int col = switchboxOp.getCol();
+
755  if (!isEmpty)
+
756  output << "// Shim Switch column " << col << "\n";
+
757  for (auto connectOp : b.getOps<ConnectOp>())
+
758  output << "__mlir_aie_try(XAie_StrmConnCctEnable(" << deviceInstRef
+
759  << ", " << tileLocStr(col, 0) << ", "
+
760  << wireBundleToPortType(connectOp.getSourceBundle()) << ", "
+
761  << connectOp.sourceIndex() << ", "
+
762  << wireBundleToPortType(connectOp.getDestBundle()) << ", "
+
763  << connectOp.destIndex() << "));\n";
+
764  }
+
765 
+
766  output << "return XAIE_OK;\n";
+
767  output << "} // mlir_aie_configure_switchboxes\n\n";
+
768 
+
769  //---------------------------------------------------------------------------
+
770  // mlir_aie_configure_cascade
+
771  //---------------------------------------------------------------------------
+
772  output << "int mlir_aie_configure_cascade(" << ctx_p << ") {\n";
+
773  for (auto configOp : targetOp.getOps<ConfigureCascadeOp>()) {
+
774  TileOp tile = cast<TileOp>(configOp.getTile().getDefiningOp());
+
775  int col = tile.colIndex();
+
776  int row = tile.rowIndex();
+
777  output << "XAie_CoreConfigAccumulatorControl(" << deviceInstRef << ", "
+
778  << "XAie_TileLoc(" << col << ", " << row << "), "
+
779  << stringifyCascadeDir(configOp.getInputDir()).upper() << ", "
+
780  << stringifyCascadeDir(configOp.getOutputDir()).upper() << ");\n";
+
781  }
+
782  output << "return XAIE_OK;\n";
+
783  output << "} // mlir_aie_configure_cascade\n\n";
+
784 
+
785  //---------------------------------------------------------------------------
+
786  // Output Buffer Accessors
+
787  //---------------------------------------------------------------------------
+
788  for (auto tile : tiles) {
+
789  Operation *tileOp = tile.second;
+
790  TileID coord = cast<TileOp>(tileOp).getTileID();
+
791  int col = coord.col;
+
792  int row = coord.row;
+
793  auto loc = tileLocStr(col, row);
+
794 
+
795  auto bufferAccessor = [&](BufferOp buf) {
+
796  // int32_t mlir_aie_read_buffer_a13(int index) {
+
797  // void mlir_aie_write_buffer_a13(int index, int32_t value) {
+
798  std::string bufName(buf.name().getValue());
+
799  Type t = buf.getType();
+
800  Type et;
+
801  std::string typestr;
+
802  if (auto memrefType = llvm::dyn_cast<MemRefType>(t)) {
+
803  et = memrefType.getElementType();
+
804  if (et.isInteger(32))
+
805  typestr = "int32_t";
+
806  else if (et.isF32())
+
807  typestr = "float";
+
808  else {
+
809  output << "// buffer " << bufName << " with unsupported type " << t
+
810  << ";\n";
+
811  return; // Unsupported type
+
812  }
+
813 
+
814  } else {
+
815  output << "// buffer " << bufName << " with unsupported type " << t
+
816  << ";\n";
+
817  return; // Unsupported type
+
818  }
+
819  assert(buf.getAddress().has_value() && "buffer must have address");
+
820  output << "const int " << bufName
+
821  << "_offset = " << buf.getAddress().value() << ";\n";
+
822  output << typestr << " mlir_aie_read_buffer_" << bufName << "(" << ctx_p
+
823  << ", int index) {\n";
+
824  output << "u32 value; auto rc = XAie_DataMemRdWord(" << deviceInstRef
+
825  << ", " << loc << ", " << bufName
+
826  << "_offset + (index*4), &value);\n";
+
827  if (et.isInteger(32))
+
828  output << " return value;\n";
+
829  else if (et.isF32()) {
+
830  output << " union caster { int32_t i; float f; };\n";
+
831  output << " caster c; c.i = value;\n";
+
832  output << " return c.f;\n";
+
833  }
+
834  output << "}\n";
+
835  output << "int mlir_aie_write_buffer_" << bufName << "(" << ctx_p
+
836  << ", int index, " << typestr << " value) {\n";
+
837  if (et.isInteger(32))
+
838  output << " int32_t int_value = value;\n";
+
839  else if (et.isF32()) {
+
840  output << " union caster { int32_t i; float f; };\n";
+
841  output << " caster c; c.f = value;\n";
+
842  output << " int32_t int_value = c.i;\n";
+
843  }
+
844  output << "AieRC rc = XAie_DataMemWrWord(" << deviceInstRef << ", "
+
845  << loc << ", " << bufName << "_offset + (index*4), int_value);\n";
+
846  output << "return rc;\n";
+
847  output << "}\n";
+
848  };
+
849 
+
850  // if(tiles.count(tile.getValue()))
+
851  for (auto buf : buffers[tileOp])
+
852  bufferAccessor(buf);
+
853  }
+
854 
+
855  auto lockAccessor = [&](LockOp lock) {
+
856  int col = lock.colIndex();
+
857  int row = lock.rowIndex();
+
858  if (!lock.hasName())
+
859  return;
+
860  std::string lockName(lock.name().getValue());
+
861  output << "int mlir_aie_acquire_" << lockName << "(" << ctx_p
+
862  << ", int value, int timeout) {\n";
+
863  output << " const int id = " << lock.getLockIDValue() << ";\n";
+
864  output << " return XAie_LockAcquire(" << deviceInstRef << ", "
+
865  << tileLocStr(col, row) << ", " << tileLockStr("id", "value")
+
866  << ", timeout);\n";
+
867  output << "}\n";
+
868  output << "int mlir_aie_release_" << lockName << "(" << ctx_p
+
869  << ", int value, int timeout) {\n";
+
870  output << " const int id = " << lock.getLockIDValue() << ";\n";
+
871  output << " return XAie_LockRelease(" << deviceInstRef << ", "
+
872  << tileLocStr(col, row) << ", " << tileLockStr("id", "value")
+
873  << ", timeout);\n";
+
874  output << "}\n";
+
875  };
876 
-
877  // if(tiles.count(tile.getValue()))
-
878  for (auto buf : buffers[tileOp])
-
879  bufferAccessor(buf);
-
880  }
-
881 
-
882  auto lockAccessor = [&](LockOp lock) {
-
883  int col = lock.colIndex();
-
884  int row = lock.rowIndex();
-
885  if (!lock.hasName())
-
886  return;
-
887  std::string lockName(lock.name().getValue());
-
888  output << "int mlir_aie_acquire_" << lockName << "(" << ctx_p
-
889  << ", int value, int timeout) {\n";
-
890  output << " const int id = " << lock.getLockIDValue() << ";\n";
-
891  output << " return XAie_LockAcquire(" << deviceInstRef << ", "
-
892  << tileLocStr(col, row) << ", " << tileLockStr("id", "value")
-
893  << ", timeout);\n";
-
894  output << "}\n";
-
895  output << "int mlir_aie_release_" << lockName << "(" << ctx_p
-
896  << ", int value, int timeout) {\n";
-
897  output << " const int id = " << lock.getLockIDValue() << ";\n";
-
898  output << " return XAie_LockRelease(" << deviceInstRef << ", "
-
899  << tileLocStr(col, row) << ", " << tileLockStr("id", "value")
-
900  << ", timeout);\n";
-
901  output << "}\n";
-
902  };
-
903 
-
904  targetOp.walk<WalkOrder::PreOrder>([&](LockOp lock) { lockAccessor(lock); });
-
905 
-
906  return success();
-
907 }
-
908 } // namespace xilinx::AIE
+
877  targetOp.walk<WalkOrder::PreOrder>([&](LockOp lock) { lockAccessor(lock); });
+
878 
+
879  return success();
+
880 }
utohexstr
std::string utohexstr(uint32_t u)
Definition: AIETargetBCF.cpp:24
@@ -968,28 +940,32 @@
xilinx::AIE::AIETargetModel::isWest
bool isWest(int srcCol, int srcRow, int dstCol, int dstRow) const
Return true if src is West of dst.
Definition: AIETargetModel.h:159
+
xilinx::AIE::AIETargetModel::getTargetArch
virtual AIEArch getTargetArch() const =0
Return the target architecture.
xilinx::AIE::AIETargetModel::isMemTile
virtual bool isMemTile(int col, int row) const =0
Return true if the given tile is an AIE2 'Memory' tile.
xilinx::AIE::AIETargetModel::isEast
bool isEast(int srcCol, int srcRow, int dstCol, int dstRow) const
Return true if src is East of dst.
Definition: AIETargetModel.h:164
xilinx::AIE::AIETargetModel::getNumLocks
virtual uint32_t getNumLocks(int col, int row) const =0
Return the number of lock objects.
+
xilinx::AIE::AIETargetModel::rows
virtual int rows() const =0
Return the number of rows in the device.
xilinx::AIE::AIETargetModel::isShimNOCTile
virtual bool isShimNOCTile(int col, int row) const =0
Return true if the given tile is a Shim NOC tile.
+
xilinx::AIE::AIETargetModel::getColumnShift
virtual uint32_t getColumnShift() const =0
xilinx::AIE::AIETargetModel::hasProperty
bool hasProperty(ModelProperty Prop) const
Definition: AIETargetModel.h:254
+
xilinx::AIE::AIETargetModel::columns
virtual int columns() const =0
Return the number of columns in the device.
+
xilinx::AIE::AIETargetModel::getNumMemTileRows
virtual uint32_t getNumMemTileRows() const =0
xilinx::AIE::AIETargetModel::isInternal
bool isInternal(int srcCol, int srcRow, int dstCol, int dstRow) const
Return true if src is the internal memory of dst.
Definition: AIETargetModel.h:154
+
xilinx::AIE::AIETargetModel::getRowShift
virtual uint32_t getRowShift() const =0
xilinx::AIE::AIETargetModel::getMemTileSize
virtual uint32_t getMemTileSize() const =0
Return the size (in bytes) of a MemTile.
xilinx::AIE
Include the generated interface declarations.
Definition: AIEToConfiguration.h:21
-
xilinx::AIE::xaie_cpp_file_header
const char * xaie_cpp_file_header
Definition: AIETargetXAIEV2.cpp:33
+
xilinx::AIE::AIETranslateToXAIEV2
mlir::LogicalResult AIETranslateToXAIEV2(mlir::ModuleOp module, llvm::raw_ostream &output)
xilinx::AIE::collectTiles
void collectTiles(DeviceOp &device, llvm::DenseMap< TileID, mlir::Operation * > &tiles)
xilinx::AIE::tileDMAInstStr
std::string tileDMAInstStr(llvm::StringRef col, llvm::StringRef row, llvm::StringRef bdNum)
xilinx::AIE::to_string
friend std::string to_string(const TileID &s)
Definition: AIETargetModel.h:30
xilinx::AIE::TileID
struct TileID { friend std::ostream &operator<<(std::ostream &os, const TileID &s) { os<< "TileID("<< s.col<< ", "<< s.row<< ")" TileID
Definition: AIETargetModel.h:26
-
xilinx::AIE::AIETranslateToXAIEV2
mlir::LogicalResult AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output)
Definition: AIETargetXAIEV2.cpp:297
xilinx::AIE::getTargetModel
const AIETargetModel & getTargetModel(mlir::Operation *op)
xilinx::AIE::collectBuffers
void collectBuffers(DeviceOp &device, llvm::DenseMap< mlir::Operation *, llvm::SmallVector< BufferOp, 4 >> &buffers)
xilinx::AIE::generateXAieDmaSetMultiDimAddr
void generateXAieDmaSetMultiDimAddr(llvm::raw_ostream &output, int ndims, llvm::ArrayRef< BDDimLayoutAttr > dims, int col, int row, int bdNum, int baseAddrA, int offsetA, int lenA, int elementWidthInBytes, const char *errorRet)
-
xilinx::AIE::generateDMAConfig
mlir::LogicalResult generateDMAConfig(OpType memOp, raw_ostream &output, const AIETargetModel &targetModel, DenseMap< Block *, int > blockMap)
Definition: AIETargetXAIEV2.cpp:76
xilinx::AIE::tileDMAInstRefStr
std::string tileDMAInstRefStr(llvm::StringRef col, llvm::StringRef row, llvm::StringRef bdNum)
xilinx::AIE::getOrderedChainOfBlocks
llvm::SetVector< mlir::Block * > getOrderedChainOfBlocks(mlir::Region *region)
xilinx::AIE::tileLocStr
std::string tileLocStr(llvm::StringRef col, llvm::StringRef row)
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diff --git a/doxygen/html/classAIEXToStandardBase.html b/doxygen/html/classAIEXToStandardBase.html index 1c400de9bc..62809ed779 100644 --- a/doxygen/html/classAIEXToStandardBase.html +++ b/doxygen/html/classAIEXToStandardBase.html @@ -66,7 +66,7 @@
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diff --git a/doxygen/html/classConvertAIEVecToLLVMBase.html b/doxygen/html/classConvertAIEVecToLLVMBase.html index 1ff66be1d7..622516d166 100644 --- a/doxygen/html/classConvertAIEVecToLLVMBase.html +++ b/doxygen/html/classConvertAIEVecToLLVMBase.html @@ -66,7 +66,7 @@
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diff --git a/doxygen/html/classEventMonitor.html b/doxygen/html/classEventMonitor.html index 09ec4c69b0..c9bf94d8f6 100644 --- a/doxygen/html/classEventMonitor.html +++ b/doxygen/html/classEventMonitor.html @@ -234,7 +234,7 @@

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diff --git a/doxygen/html/classPyAieTargetModel-members.html b/doxygen/html/classPyAieTargetModel-members.html index 4c2f83959e..aa53917766 100644 --- a/doxygen/html/classPyAieTargetModel-members.html +++ b/doxygen/html/classPyAieTargetModel-members.html @@ -58,7 +58,7 @@
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diff --git a/doxygen/html/classPyAieTargetModel.html b/doxygen/html/classPyAieTargetModel.html index e458541fb2..d4196eb6e9 100644 --- a/doxygen/html/classPyAieTargetModel.html +++ b/doxygen/html/classPyAieTargetModel.html @@ -157,7 +157,7 @@

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diff --git a/doxygen/html/classTypeStorage.html b/doxygen/html/classTypeStorage.html index 37b8123f5d..81fbabae3f 100644 --- a/doxygen/html/classTypeStorage.html +++ b/doxygen/html/classTypeStorage.html @@ -67,7 +67,7 @@
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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diff --git a/doxygen/html/classes.html b/doxygen/html/classes.html index 616081c5c5..c73c46e460 100644 --- a/doxygen/html/classes.html +++ b/doxygen/html/classes.html @@ -112,7 +112,7 @@
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diff --git a/doxygen/html/classxilinx_1_1AIEX_1_1TokenAnalysis-members.html b/doxygen/html/classxilinx_1_1AIEX_1_1TokenAnalysis-members.html index 4f0ce8b2bc..1fca5626cc 100644 --- a/doxygen/html/classxilinx_1_1AIEX_1_1TokenAnalysis-members.html +++ b/doxygen/html/classxilinx_1_1AIEX_1_1TokenAnalysis-members.html @@ -69,7 +69,7 @@
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/classxilinx_1_1AIE_1_1AIE1TargetModel-members.html b/doxygen/html/classxilinx_1_1AIE_1_1AIE1TargetModel-members.html index b1bf8da6b6..9996ab77c9 100644 --- a/doxygen/html/classxilinx_1_1AIE_1_1AIE1TargetModel-members.html +++ b/doxygen/html/classxilinx_1_1AIE_1_1AIE1TargetModel-members.html @@ -131,7 +131,7 @@
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/classxilinx_1_1AIE_1_1AIE1TargetModel.html b/doxygen/html/classxilinx_1_1AIE_1_1AIE1TargetModel.html index 2fcc452521..3062b33ea7 100644 --- a/doxygen/html/classxilinx_1_1AIE_1_1AIE1TargetModel.html +++ b/doxygen/html/classxilinx_1_1AIE_1_1AIE1TargetModel.html @@ -1641,7 +1641,7 @@

-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/classxilinx_1_1AIE_1_1AIE2TargetModel-members.html b/doxygen/html/classxilinx_1_1AIE_1_1AIE2TargetModel-members.html index c126b2b38b..15b8dd10d8 100644 --- a/doxygen/html/classxilinx_1_1AIE_1_1AIE2TargetModel-members.html +++ b/doxygen/html/classxilinx_1_1AIE_1_1AIE2TargetModel-members.html @@ -131,7 +131,7 @@
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/classxilinx_1_1AIE_1_1AIE2TargetModel.html b/doxygen/html/classxilinx_1_1AIE_1_1AIE2TargetModel.html index cf63a67071..c38824f535 100644 --- a/doxygen/html/classxilinx_1_1AIE_1_1AIE2TargetModel.html +++ b/doxygen/html/classxilinx_1_1AIE_1_1AIE2TargetModel.html @@ -1578,7 +1578,7 @@

-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/classxilinx_1_1AIE_1_1AIEObjectFifoSubviewType-members.html b/doxygen/html/classxilinx_1_1AIE_1_1AIEObjectFifoSubviewType-members.html index b4c943deb3..50fe41bbe4 100644 --- a/doxygen/html/classxilinx_1_1AIE_1_1AIEObjectFifoSubviewType-members.html +++ b/doxygen/html/classxilinx_1_1AIE_1_1AIEObjectFifoSubviewType-members.html @@ -63,7 +63,7 @@
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/classxilinx_1_1AIE_1_1AIEObjectFifoSubviewType.html b/doxygen/html/classxilinx_1_1AIE_1_1AIEObjectFifoSubviewType.html index 51a8078efe..592a2a55fd 100644 --- a/doxygen/html/classxilinx_1_1AIE_1_1AIEObjectFifoSubviewType.html +++ b/doxygen/html/classxilinx_1_1AIE_1_1AIEObjectFifoSubviewType.html @@ -237,7 +237,7 @@

-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/classxilinx_1_1AIE_1_1AIETargetModel-members.html b/doxygen/html/classxilinx_1_1AIE_1_1AIETargetModel-members.html index 56ee9cdec8..c106734f76 100644 --- a/doxygen/html/classxilinx_1_1AIE_1_1AIETargetModel-members.html +++ b/doxygen/html/classxilinx_1_1AIE_1_1AIETargetModel-members.html @@ -129,7 +129,7 @@
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/classxilinx_1_1AIE_1_1AIETargetModel.html b/doxygen/html/classxilinx_1_1AIE_1_1AIETargetModel.html index cbf4ff04be..e9588fd48d 100644 --- a/doxygen/html/classxilinx_1_1AIE_1_1AIETargetModel.html +++ b/doxygen/html/classxilinx_1_1AIE_1_1AIETargetModel.html @@ -797,8 +797,6 @@

xilinx::AIE::AIE2TargetModel, and xilinx::AIE::AIE1TargetModel.

-

Referenced by xilinx::AIE::generateDMAConfig().

- @@ -1105,8 +1103,6 @@

xilinx::AIE::AIE2TargetModel, and xilinx::AIE::AIE1TargetModel.

-

Referenced by xilinx::AIE::generateDMAConfig().

- @@ -1320,7 +1316,7 @@

References getModelProperties().

-

Referenced by xilinx::AIE::AIERTControl::AIERTControl(), xilinx::AIE::AIERTControl::configureSwitches(), and xilinx::AIE::generateDMAConfig().

+

Referenced by xilinx::AIE::AIERTControl::AIERTControl(), and xilinx::AIE::AIERTControl::configureSwitches().

@@ -1469,7 +1465,7 @@

Definition at line 164 of file AIETargetModel.h.

-

Referenced by xilinx::AIE::AIERTControl::configureBdInBlock(), xilinx::AIE::AIERTControl::configureLocksInBdBlock(), and xilinx::AIE::generateDMAConfig().

+

Referenced by xilinx::AIE::AIERTControl::configureBdInBlock(), and xilinx::AIE::AIERTControl::configureLocksInBdBlock().

@@ -1523,8 +1519,6 @@

Definition at line 154 of file AIETargetModel.h.

-

Referenced by xilinx::AIE::generateDMAConfig().

- @@ -1838,7 +1832,7 @@

xilinx::AIE::BaseNPUTargetModel, xilinx::AIE::VE2802TargetModel, xilinx::AIE::VE2302TargetModel, and xilinx::AIE::AIE1TargetModel.

-

Referenced by xilinx::AIE::generateDMAConfig(), xilinx::AIE::AIE2TargetModel::getNumBanks(), xilinx::AIE::AIE2TargetModel::getNumBDs(), xilinx::AIE::AIE2TargetModel::getNumLocks(), and xilinx::AIE::AIE2TargetModel::isBdChannelAccessible().

+

Referenced by xilinx::AIE::AIE2TargetModel::getNumBanks(), xilinx::AIE::AIE2TargetModel::getNumBDs(), xilinx::AIE::AIE2TargetModel::getNumLocks(), and xilinx::AIE::AIE2TargetModel::isBdChannelAccessible().

@@ -2027,7 +2021,7 @@

xilinx::AIE::NPU2TargetModel, xilinx::AIE::VirtualizedNPUTargetModel, xilinx::AIE::NPUTargetModel, xilinx::AIE::VE2802TargetModel, xilinx::AIE::VE2302TargetModel, and xilinx::AIE::VC1902TargetModel.

-

Referenced by xilinx::AIE::AIERTControl::configureBdInBlock(), xilinx::AIE::generateDMAConfig(), getRowToShimChanMap(), xilinx::AIE::BaseNPUTargetModel::isShimNOCorPLTile(), and AIEDMATasksToNPUPass::setAddressForSingleBD().

+

Referenced by xilinx::AIE::AIERTControl::configureBdInBlock(), getRowToShimChanMap(), xilinx::AIE::BaseNPUTargetModel::isShimNOCorPLTile(), and AIEDMATasksToNPUPass::setAddressForSingleBD().

@@ -2206,7 +2200,7 @@

Definition at line 159 of file AIETargetModel.h.

-

Referenced by xilinx::AIE::AIERTControl::configureBdInBlock(), xilinx::AIE::AIERTControl::configureLocksInBdBlock(), and xilinx::AIE::generateDMAConfig().

+

Referenced by xilinx::AIE::AIERTControl::configureBdInBlock(), and xilinx::AIE::AIERTControl::configureLocksInBdBlock().

@@ -2256,7 +2250,7 @@

-

Definition at line 650 of file AIETargetModel.cpp.

+

Definition at line 652 of file AIETargetModel.cpp.

@@ -2267,7 +2261,7 @@

-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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xilinx::AIE::AIE2TargetModel.

-

Definition at line 708 of file AIETargetModel.cpp.

+

Definition at line 710 of file AIETargetModel.cpp.

@@ -496,7 +496,7 @@

-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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diff --git a/doxygen/html/classxilinx_1_1aievec_1_1UPSOpConversion.html b/doxygen/html/classxilinx_1_1aievec_1_1UPSOpConversion.html index 41a2859dfe..c6ade173a7 100644 --- a/doxygen/html/classxilinx_1_1aievec_1_1UPSOpConversion.html +++ b/doxygen/html/classxilinx_1_1aievec_1_1UPSOpConversion.html @@ -140,7 +140,7 @@

-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/classxilinx_1_1aievec_1_1UnpackOpConversion-members.html b/doxygen/html/classxilinx_1_1aievec_1_1UnpackOpConversion-members.html index bc6174942b..2a658a2e35 100644 --- a/doxygen/html/classxilinx_1_1aievec_1_1UnpackOpConversion-members.html +++ b/doxygen/html/classxilinx_1_1aievec_1_1UnpackOpConversion-members.html @@ -60,7 +60,7 @@
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/classxilinx_1_1aievec_1_1UnpackOpConversion.html b/doxygen/html/classxilinx_1_1aievec_1_1UnpackOpConversion.html index 3aa489d375..e87db61246 100644 --- a/doxygen/html/classxilinx_1_1aievec_1_1UnpackOpConversion.html +++ b/doxygen/html/classxilinx_1_1aievec_1_1UnpackOpConversion.html @@ -138,7 +138,7 @@

-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/d__ary__heap_8h.html b/doxygen/html/d__ary__heap_8h.html index b4795d446e..f670b3b04d 100644 --- a/doxygen/html/d__ary__heap_8h.html +++ b/doxygen/html/d__ary__heap_8h.html @@ -196,7 +196,7 @@

-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/d__ary__heap_8h_source.html b/doxygen/html/d__ary__heap_8h_source.html index 033cb8698b..32acf5e236 100644 --- a/doxygen/html/d__ary__heap_8h_source.html +++ b/doxygen/html/d__ary__heap_8h_source.html @@ -433,7 +433,7 @@
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:56 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_000003_000002.html b/doxygen/html/dir_000003_000002.html index e02d8120c7..c3717cab7a 100644 --- a/doxygen/html/dir_000003_000002.html +++ b/doxygen/html/dir_000003_000002.html @@ -52,7 +52,7 @@

aie → aie-c Relation

File in include/aieIncludes file in include/aie-c
Bindings / PyTypes.hTargetModel.h
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_000003_000008.html b/doxygen/html/dir_000003_000008.html index 33a88b6554..3bf54902c0 100644 --- a/doxygen/html/dir_000003_000008.html +++ b/doxygen/html/dir_000003_000008.html @@ -52,7 +52,7 @@

aie → Dialect Relation

File in include/aieIncludes file in include/aie/Dialect
InitialAllDialect.hADF / ADFDialect.h
InitialAllDialect.hAIE / IR / AIEDialect.h
InitialAllDialect.hAIEVec / AIE1 / IR / AIEVecAIE1Dialect.h
InitialAllDialect.hAIEVec / IR / AIEVecDialect.h
InitialAllDialect.hAIEX / IR / AIEXDialect.h
InitialAllDialect.hXLLVM / XLLVMDialect.h
Conversion / AIEToConfiguration / AIEToConfiguration.hAIE / IR / AIEDialect.h
Conversion / AIEToConfiguration / AIEToConfiguration.hAIEX / IR / AIEXDialect.h
Dialect / AIEVec / AIEVecUtils.hAIEVec / AIE1 / IR / AIEVecAIE1Ops.h
Dialect / AIEVec / AIEVecUtils.hAIEVec / IR / AIEVecDialect.h
Dialect / AIEVec / AIEVecUtils.hAIEVec / IR / AIEVecOps.h
Dialect / AIEVec / AIEVecUtils.hAIEVec / IR / AIEVecTypes.h
Dialect / AIEX / IR / AIEXDialect.hAIE / IR / AIEDialect.h
Targets / AIERT.hAIE / IR / AIEDialect.h
Targets / AIERT.hAIE / IR / AIEEnums.h
Targets / AIERT.hAIE / IR / AIETargetModel.h
Targets / AIETargetShared.hAIE / IR / AIEDialect.h
Dialect / AIEX / Transforms / AIEXPasses.hAIEX / IR / AIEXDialect.h
Dialect / AIE / Transforms / AIEAssignBufferDescriptorIDs.hAIE / IR / AIETargetModel.h
Dialect / AIE / Transforms / AIEGenerateColumnControlOverlay.hAIE / IR / AIEDialect.h
Dialect / AIE / Transforms / AIEPasses.hAIE / IR / AIEDialect.h
Dialect / AIE / Transforms / AIEPathFinder.hAIE / IR / AIEDialect.h
Dialect / AIE / Transforms / AIEPathFinder.hAIE / IR / AIETargetModel.h
Dialect / AIEVec / Transforms / Passes.hAIEVec / AIE1 / IR / AIEVecAIE1Dialect.h
Dialect / AIEVec / Transforms / Passes.hAIEVec / IR / AIEVecDialect.h
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_000004_000002.html b/doxygen/html/dir_000004_000002.html index 5008b0176a..169c77d590 100644 --- a/doxygen/html/dir_000004_000002.html +++ b/doxygen/html/dir_000004_000002.html @@ -52,7 +52,7 @@

Bindings → aie-c Relation

File in include/aie/BindingsIncludes file in include/aie-c
PyTypes.hTargetModel.h
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_000005_000006.html b/doxygen/html/dir_000005_000006.html index 8f77a1fadb..bac663d9eb 100644 --- a/doxygen/html/dir_000005_000006.html +++ b/doxygen/html/dir_000005_000006.html @@ -52,7 +52,7 @@

Conversion → AIEToConfiguration Relation

File in include/aie/ConversionIncludes file in include/aie/Conversion/AIEToConfiguration
Passes.hAIEToConfiguration.h
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_000005_000007.html b/doxygen/html/dir_000005_000007.html index f515e2d5e5..a41a2d9246 100644 --- a/doxygen/html/dir_000005_000007.html +++ b/doxygen/html/dir_000005_000007.html @@ -52,7 +52,7 @@

Conversion → AIEVecToLLVM Relation

File in include/aie/ConversionIncludes file in include/aie/Conversion/AIEVecToLLVM
Passes.hAIEVecToLLVM.h
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_000005_000008.html b/doxygen/html/dir_000005_000008.html index af0c608a8a..f80e746d2c 100644 --- a/doxygen/html/dir_000005_000008.html +++ b/doxygen/html/dir_000005_000008.html @@ -52,7 +52,7 @@

Conversion → Dialect Relation

File in include/aie/ConversionIncludes file in include/aie/Dialect
AIEToConfiguration / AIEToConfiguration.hAIE / IR / AIEDialect.h
AIEToConfiguration / AIEToConfiguration.hAIEX / IR / AIEXDialect.h
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_000006_000008.html b/doxygen/html/dir_000006_000008.html index 4267566ad2..3493972ed6 100644 --- a/doxygen/html/dir_000006_000008.html +++ b/doxygen/html/dir_000006_000008.html @@ -52,7 +52,7 @@

AIEToConfiguration → Dialect Relation

File in include/aie/Conversion/AIEToConfigurationIncludes file in include/aie/Dialect
AIEToConfiguration.hAIE / IR / AIEDialect.h
AIEToConfiguration.hAIEX / IR / AIEXDialect.h
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_000009_000017.html b/doxygen/html/dir_000009_000017.html index b7e731a38c..2908f313c9 100644 --- a/doxygen/html/dir_000009_000017.html +++ b/doxygen/html/dir_000009_000017.html @@ -52,7 +52,7 @@

AIEVec → AIE1 Relation

File in include/aie/Dialect/AIEVecIncludes file in include/aie/Dialect/AIEVec/AIE1
AIEVecUtils.hIR / AIEVecAIE1Ops.h
Transforms / Passes.hIR / AIEVecAIE1Dialect.h
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_000009_000019.html b/doxygen/html/dir_000009_000019.html index 8fbc01d982..5dabf136e8 100644 --- a/doxygen/html/dir_000009_000019.html +++ b/doxygen/html/dir_000009_000019.html @@ -52,7 +52,7 @@

AIEVec → IR Relation

File in include/aie/Dialect/AIEVecIncludes file in include/aie/Dialect/AIEVec/IR
AIEVecUtils.hAIEVecDialect.h
AIEVecUtils.hAIEVecOps.h
AIEVecUtils.hAIEVecTypes.h
Transforms / Passes.hAIEVecDialect.h
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_000012_000017.html b/doxygen/html/dir_000012_000017.html index d299028919..55e29e823e 100644 --- a/doxygen/html/dir_000012_000017.html +++ b/doxygen/html/dir_000012_000017.html @@ -52,7 +52,7 @@

Transforms → AIE1 Relation

File in include/aie/Dialect/AIEVec/TransformsIncludes file in include/aie/Dialect/AIEVec/AIE1
Passes.hIR / AIEVecAIE1Dialect.h
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_000012_000019.html b/doxygen/html/dir_000012_000019.html index b314f330d9..5def7088a3 100644 --- a/doxygen/html/dir_000012_000019.html +++ b/doxygen/html/dir_000012_000019.html @@ -52,7 +52,7 @@

Transforms → IR Relation

File in include/aie/Dialect/AIEVec/TransformsIncludes file in include/aie/Dialect/AIEVec/IR
Passes.hAIEVecDialect.h
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_000016_000015.html b/doxygen/html/dir_000016_000015.html index a63af7c115..621480534e 100644 --- a/doxygen/html/dir_000016_000015.html +++ b/doxygen/html/dir_000016_000015.html @@ -52,7 +52,7 @@

Transforms → IR Relation

File in include/aie/Dialect/AIE/TransformsIncludes file in include/aie/Dialect/AIE/IR
AIEAssignBufferDescriptorIDs.hAIETargetModel.h
AIEGenerateColumnControlOverlay.hAIEDialect.h
AIEPasses.hAIEDialect.h
AIEPathFinder.hAIEDialect.h
AIEPathFinder.hAIETargetModel.h
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_000022_000014.html b/doxygen/html/dir_000022_000014.html index ebd4753c2b..f4da076973 100644 --- a/doxygen/html/dir_000022_000014.html +++ b/doxygen/html/dir_000022_000014.html @@ -52,7 +52,7 @@

AIEX → AIE Relation

File in include/aie/Dialect/AIEXIncludes file in include/aie/Dialect/AIE
IR / AIEXDialect.hIR / AIEDialect.h
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_000023_000014.html b/doxygen/html/dir_000023_000014.html index 2d992b7640..44de4999b6 100644 --- a/doxygen/html/dir_000023_000014.html +++ b/doxygen/html/dir_000023_000014.html @@ -52,7 +52,7 @@

IR → AIE Relation

File in include/aie/Dialect/AIEX/IRIncludes file in include/aie/Dialect/AIE
AIEXDialect.hIR / AIEDialect.h
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_000024_000023.html b/doxygen/html/dir_000024_000023.html index 9b093e69e4..6e99853453 100644 --- a/doxygen/html/dir_000024_000023.html +++ b/doxygen/html/dir_000024_000023.html @@ -52,7 +52,7 @@

Transforms → IR Relation

File in include/aie/Dialect/AIEX/TransformsIncludes file in include/aie/Dialect/AIEX/IR
AIEXPasses.hAIEXDialect.h
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_000028_000029.html b/doxygen/html/dir_000028_000029.html index e3e71d3ed0..0d89c9edbe 100644 --- a/doxygen/html/dir_000028_000029.html +++ b/doxygen/html/dir_000028_000029.html @@ -52,7 +52,7 @@

Dialect → XLLVM Relation

File in include/aie/Target/LLVMIR/DialectIncludes file in include/aie/Target/LLVMIR/Dialect/XLLVM
All.hXLLVMToLLVMIRTranslation.h
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_000030_000008.html b/doxygen/html/dir_000030_000008.html index fcec1bb838..360fffb0ce 100644 --- a/doxygen/html/dir_000030_000008.html +++ b/doxygen/html/dir_000030_000008.html @@ -52,7 +52,7 @@

Targets → Dialect Relation

File in include/aie/TargetsIncludes file in include/aie/Dialect
AIERT.hAIE / IR / AIEDialect.h
AIERT.hAIE / IR / AIEEnums.h
AIERT.hAIE / IR / AIETargetModel.h
AIETargetShared.hAIE / IR / AIEDialect.h
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_000032_000001.html b/doxygen/html/dir_000032_000001.html index 46f623f86a..a814a34384 100644 --- a/doxygen/html/dir_000032_000001.html +++ b/doxygen/html/dir_000032_000001.html @@ -52,7 +52,7 @@

CAPI → include Relation

File in lib/CAPIIncludes file in include
Dialects.cppaie / Dialect / AIE / IR / AIEDialect.h
Dialects.cppaie / Dialect / AIEVec / IR / AIEVecDialect.h
Dialects.cppaie / Dialect / AIEX / IR / AIEXDialect.h
Dialects.cppaie-c / Dialects.h
Dialects.cppaie / Dialect / XLLVM / XLLVMDialect.h
Registration.cppaie / Dialect / AIE / Transforms / AIEPasses.h
Registration.cppaie / Dialect / AIEX / Transforms / AIEXPasses.h
Registration.cppaie / Target / LLVMIR / Dialect / All.h
Registration.cppaie / InitialAllDialect.h
Registration.cppaie / Dialect / AIEVec / Analysis / Passes.h
Registration.cppaie / Dialect / AIEVec / Pipelines / Passes.h
Registration.cppaie / Dialect / AIEVec / Transforms / Passes.h
Registration.cppaie / Conversion / Passes.h
Registration.cppaie-c / Registration.h
TargetModel.cppaie / Dialect / AIE / IR / AIEDialect.h
TargetModel.cppaie / Dialect / AIE / IR / AIETargetModel.h
TargetModel.cppaie-c / TargetModel.h
Translation.cppaie / Targets / AIERT.h
Translation.cppaie / Dialect / AIE / IR / AIETargetModel.h
Translation.cppaie / Targets / AIETargets.h
Translation.cppaie / Conversion / AIEToConfiguration / AIEToConfiguration.h
Translation.cppaie-c / Translation.h
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_000033_000001.html b/doxygen/html/dir_000033_000001.html index 752373e0c8..c8ea6e32cf 100644 --- a/doxygen/html/dir_000033_000001.html +++ b/doxygen/html/dir_000033_000001.html @@ -52,7 +52,7 @@

Conversion → include Relation

File in lib/ConversionIncludes file in include
AIEToConfiguration / AIEToConfiguration.cppaie / Targets / AIERT.h
AIEToConfiguration / AIEToConfiguration.cppaie / Conversion / AIEToConfiguration / AIEToConfiguration.h
AIEVecToLLVM / AIEVecToLLVM.cppaie / Dialect / AIEVec / AIE1 / IR / AIEVecAIE1Ops.h
AIEVecToLLVM / AIEVecToLLVM.cppaie / Dialect / AIEVec / IR / AIEVecOps.h
AIEVecToLLVM / AIEVecToLLVM.cppaie / Conversion / AIEVecToLLVM / AIEVecToLLVM.h
AIEVecToLLVM / AIEVecToLLVM.cppaie / Dialect / AIEVec / AIEVecUtils.h
AIEVecToLLVM / AIEVecToLLVM.cppaie / Dialect / AIEVec / Utils / Utils.h
AIEVecToLLVM / AIEVecToLLVM.cppaie / Dialect / XLLVM / XLLVMDialect.h
PassDetail.haie / Conversion / Passes.h
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_000034_000001.html b/doxygen/html/dir_000034_000001.html index 2cc55b8a12..7dd7b78174 100644 --- a/doxygen/html/dir_000034_000001.html +++ b/doxygen/html/dir_000034_000001.html @@ -52,7 +52,7 @@

AIEToConfiguration → include Relation

File in lib/Conversion/AIEToConfigurationIncludes file in include
AIEToConfiguration.cppaie / Targets / AIERT.h
AIEToConfiguration.cppaie / Conversion / AIEToConfiguration / AIEToConfiguration.h
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_000035_000001.html b/doxygen/html/dir_000035_000001.html index c1f1f9234b..29c682762b 100644 --- a/doxygen/html/dir_000035_000001.html +++ b/doxygen/html/dir_000035_000001.html @@ -52,7 +52,7 @@

AIEVecToLLVM → include Relation

File in lib/Conversion/AIEVecToLLVMIncludes file in include
AIEVecToLLVM.cppaie / Dialect / AIEVec / AIE1 / IR / AIEVecAIE1Ops.h
AIEVecToLLVM.cppaie / Dialect / AIEVec / IR / AIEVecOps.h
AIEVecToLLVM.cppaie / Conversion / AIEVecToLLVM / AIEVecToLLVM.h
AIEVecToLLVM.cppaie / Dialect / AIEVec / AIEVecUtils.h
AIEVecToLLVM.cppaie / Dialect / AIEVec / Utils / Utils.h
AIEVecToLLVM.cppaie / Dialect / XLLVM / XLLVMDialect.h
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_000036_000001.html b/doxygen/html/dir_000036_000001.html index 4cc67ce91d..282a2729e4 100644 --- a/doxygen/html/dir_000036_000001.html +++ b/doxygen/html/dir_000036_000001.html @@ -52,7 +52,7 @@

Dialect → include Relation

File in lib/DialectIncludes file in include
ADF / ADFDialect.cppaie / Dialect / ADF / ADFDialect.h
ADF / ADFDialect.cppaie / Dialect / ADF / ADFOps.h
ADF / ADFOps.cppaie / Dialect / ADF / ADFOps.h
AIEVec / IR / AIE1 / AIEVecAIE1Ops.cppaie / Dialect / AIEVec / AIE1 / IR / AIEVecAIE1Ops.h
AIEVec / IR / AIE1 / AIEVecAIE1Ops.cppaie / Dialect / AIEVec / AIEVecUtils.h
AIEX / IR / AIEXDialect.cppaie / Dialect / AIEX / IR / AIEXDialect.h
AIE / IR / AIEDialect.cppaie / Dialect / AIE / IR / AIEDialect.h
AIE / IR / AIETargetModel.cppaie / Dialect / AIE / IR / AIETargetModel.h
AIEVec / IR / AIEVecOps.cppaie / Dialect / AIEVec / AIEVecUtils.h
AIEVec / IR / AIEVecOps.cppaie / Dialect / AIEVec / IR / AIEVecOps.h
AIEVec / IR / AIEVecTypes.cppaie / Dialect / AIEVec / IR / AIEVecTypes.h
AIEVec / TransformOps / AIEVecTransformOps.cppaie / Dialect / AIEVec / TransformOps / AIEVecTransformOps.h
AIEVec / TransformOps / DialectExtension.cppaie / Dialect / AIEVec / TransformOps / DialectExtension.h
AIEVec / TransformOps / DialectExtension.cppaie / Dialect / AIEVec / IR / AIEVecDialect.h
AIEVec / TransformOps / DialectExtension.cppaie / Dialect / AIEVec / TransformOps / AIEVecTransformOps.h
AIEVec / Transforms / AIEVecOptimizations.cppaie / Dialect / AIEVec / AIE1 / IR / AIEVecAIE1Ops.h
AIEVec / Transforms / AIEVecOptimizations.cppaie / Dialect / AIEVec / AIEVecUtils.h
AIEVec / Transforms / AIEVecOptimizations.cppaie / Dialect / AIEVec / Analysis / Passes.h
AIEVec / Transforms / AIEVecOptimizations.cppaie / Dialect / AIEVec / IR / AIEVecOps.h
AIEVec / Transforms / AIEVecOptimizations.cppaie / Dialect / AIEVec / Pipelines / Passes.h
AIEVec / Transforms / AIEVectorize.cppaie / Dialect / AIEVec / AIE1 / IR / AIEVecAIE1Ops.h
AIEVec / Transforms / AIEVectorize.cppaie / Dialect / AIEVec / AIEVecUtils.h
AIEVec / Transforms / AIEVectorize.cppaie / Dialect / AIEVec / IR / AIEVecOps.h
AIEVec / Transforms / AIEVectorize.cppaie / Dialect / AIEVec / Transforms / IntervalReuse.h
AIEVec / Transforms / AIEVectorize.cppaie / Dialect / AIEVec / Transforms / Passes.h
AIEVec / Transforms / ConvertVectorToAIEVec.cppaie / Dialect / AIEVec / Pipelines / Passes.h
AIEVec / Transforms / CopyRemoval.cppaie / Dialect / AIEVec / Pipelines / Passes.h
AIEVec / Transforms / DynamicSizeNoImplicitBroadcast.cppaie / Dialect / AIEVec / AIEVecUtils.h
AIEVec / Transforms / DynamicSizeNoImplicitBroadcast.cppaie / Dialect / AIEVec / Pipelines / Passes.h
AIEVec / Transforms / FoldMulAddChainToConvOp.cppaie / Dialect / AIEVec / AIEVecUtils.h
AIEVec / Transforms / FoldMulAddChainToConvOp.cppaie / Dialect / AIEVec / Analysis / Passes.h
AIEVec / Transforms / FoldMulAddChainToConvOp.cppaie / Dialect / AIEVec / IR / AIEVecOps.h
AIEVec / Transforms / FoldMulAddChainToConvOp.cppaie / Dialect / AIEVec / Pipelines / Passes.h
AIEVec / Transforms / IntervalReuse.cppaie / Dialect / AIEVec / Transforms / IntervalReuse.h
AIEVec / Transforms / IntervalReuse.cppaie / Dialect / AIEVec / AIEVecUtils.h
AIEVec / Transforms / VectorToAIEVecConversions.cppaie / Dialect / AIEVec / AIE1 / IR / AIEVecAIE1Ops.h
AIEVec / Transforms / VectorToAIEVecConversions.cppaie / Dialect / AIEVec / AIEVecUtils.h
AIEVec / Transforms / VectorToAIEVecConversions.cppaie / Dialect / AIEVec / IR / AIEVecOps.h
AIEVec / Transforms / VectorToAIEVecConversions.cppaie / Dialect / AIEVec / Pipelines / Passes.h
AIEVec / Transforms / VectorToAIEVecConversions.cppaie / Dialect / AIEVec / Utils / Utils.h
AIEVec / Transforms / VectorToVectorConversions.cppaie / Dialect / AIEVec / AIEVecUtils.h
AIEVec / Transforms / VectorToVectorConversions.cppaie / Dialect / AIEVec / Pipelines / Passes.h
AIEVec / Transforms / VectorToVectorConversions.cppaie / Dialect / AIEVec / Utils / Utils.h
AIE / Transforms / AIEAssignBufferDescriptorIDs.cppaie / Dialect / AIE / Transforms / AIEAssignBufferDescriptorIDs.h
AIE / Transforms / AIEAssignBufferDescriptorIDs.cppaie / Dialect / AIE / IR / AIEDialect.h
AIE / Transforms / AIEAssignBufferDescriptorIDs.cppaie / Dialect / AIE / Transforms / AIEPasses.h
AIE / Transforms / AIEAssignBuffers.cppaie / Dialect / AIE / IR / AIEDialect.h
AIE / Transforms / AIEAssignBuffers.cppaie / Dialect / AIE / Transforms / AIEPasses.h
AIE / Transforms / AIEAssignLockIDs.cppaie / Dialect / AIE / IR / AIEDialect.h
AIE / Transforms / AIEAssignLockIDs.cppaie / Dialect / AIE / Transforms / AIEPasses.h
AIE / Transforms / AIECanonicalizeDevice.cppaie / Dialect / AIE / IR / AIEDialect.h
AIE / Transforms / AIECanonicalizeDevice.cppaie / Dialect / AIE / Transforms / AIEPasses.h
AIE / Transforms / AIECoreToStandard.cppaie / Dialect / AIE / IR / AIEDialect.h
AIE / Transforms / AIECoreToStandard.cppaie / Dialect / AIE / Transforms / AIEPasses.h
AIE / Transforms / AIECreatePathFindFlows.cppaie / Dialect / AIE / IR / AIEDialect.h
AIE / Transforms / AIECreatePathFindFlows.cppaie / Dialect / AIE / Transforms / AIEPasses.h
AIE / Transforms / AIECreatePathFindFlows.cppaie / Dialect / AIE / Transforms / AIEPathFinder.h
AIE / Transforms / AIEFindFlows.cppaie / Dialect / AIE / IR / AIEDialect.h
AIE / Transforms / AIEFindFlows.cppaie / Dialect / AIE / Transforms / AIEPasses.h
AIE / Transforms / AIEGenerateColumnControlOverlay.cppaie / Dialect / AIE / Transforms / AIEGenerateColumnControlOverlay.h
AIE / Transforms / AIEGenerateColumnControlOverlay.cppaie / Dialect / AIE / IR / AIEDialect.h
AIE / Transforms / AIEGenerateColumnControlOverlay.cppaie / Dialect / AIE / Transforms / AIEPasses.h
AIE / Transforms / AIELocalizeLocks.cppaie / Dialect / AIE / IR / AIEDialect.h
AIE / Transforms / AIELocalizeLocks.cppaie / Dialect / AIE / Transforms / AIEPasses.h
AIE / Transforms / AIELowerCascadeFlows.cppaie / Dialect / AIE / IR / AIEDialect.h
AIE / Transforms / AIELowerCascadeFlows.cppaie / Dialect / AIE / Transforms / AIEPasses.h
AIE / Transforms / AIENormalizeAddressSpaces.cppaie / Dialect / AIE / IR / AIEDialect.h
AIE / Transforms / AIENormalizeAddressSpaces.cppaie / Dialect / AIE / Transforms / AIEPasses.h
AIE / Transforms / AIEObjectFifoRegisterProcess.cppaie / Dialect / AIE / IR / AIEDialect.h
AIE / Transforms / AIEObjectFifoRegisterProcess.cppaie / Dialect / AIE / Transforms / AIEPasses.h
AIE / Transforms / AIEObjectFifoStatefulTransform.cppaie / Dialect / AIE / IR / AIEDialect.h
AIE / Transforms / AIEObjectFifoStatefulTransform.cppaie / Dialect / AIE / Transforms / AIEPasses.h
AIE / Transforms / AIEPathFinder.cppaie / Dialect / AIE / Transforms / AIEPathFinder.h
AIE / Transforms / AIEVectorOpt.cppaie / Dialect / AIE / IR / AIEDialect.h
AIE / Transforms / AIEVectorOpt.cppaie / Dialect / AIE / Transforms / AIEPasses.h
AIEX / Transforms / AIEAssignRuntimeSequenceBDIDs.cppaie / Dialect / AIE / IR / AIEDialect.h
AIEX / Transforms / AIEAssignRuntimeSequenceBDIDs.cppaie / Dialect / AIE / Transforms / AIEAssignBufferDescriptorIDs.h
AIEX / Transforms / AIEAssignRuntimeSequenceBDIDs.cppaie / Dialect / AIEX / IR / AIEXDialect.h
AIEX / Transforms / AIEAssignRuntimeSequenceBDIDs.cppaie / Dialect / AIEX / Transforms / AIEXPasses.h
AIEX / Transforms / AIECreateBroadcastPacket.cppaie / Dialect / AIE / IR / AIEDialect.h
AIEX / Transforms / AIECreateBroadcastPacket.cppaie / Dialect / AIEX / IR / AIEXDialect.h
AIEX / Transforms / AIECreateBroadcastPacket.cppaie / Dialect / AIEX / Transforms / AIEXPasses.h
AIEX / Transforms / AIECreateCores.cppaie / Dialect / AIE / IR / AIEDialect.h
AIEX / Transforms / AIECreateCores.cppaie / Dialect / AIEX / IR / AIEXDialect.h
AIEX / Transforms / AIECreateCores.cppaie / Dialect / AIEX / Transforms / AIEXPasses.h
AIEX / Transforms / AIECreateLocks.cppaie / Dialect / AIE / IR / AIEDialect.h
AIEX / Transforms / AIECreateLocks.cppaie / Dialect / AIEX / AIETokenAnalysis.h
AIEX / Transforms / AIECreateLocks.cppaie / Dialect / AIEX / IR / AIEXDialect.h
AIEX / Transforms / AIECreateLocks.cppaie / Dialect / AIEX / Transforms / AIEXPasses.h
AIEX / Transforms / AIECtrlPacketToDma.cppaie / Dialect / AIE / IR / AIEDialect.h
AIEX / Transforms / AIECtrlPacketToDma.cppaie / Dialect / AIE / Transforms / AIEGenerateColumnControlOverlay.h
AIEX / Transforms / AIECtrlPacketToDma.cppaie / Dialect / AIEX / IR / AIEXDialect.h
AIEX / Transforms / AIECtrlPacketToDma.cppaie / Dialect / AIEX / Transforms / AIEXPasses.h
AIEX / Transforms / AIEDMATasksToNPU.cppaie / Dialect / AIE / IR / AIEDialect.h
AIEX / Transforms / AIEDMATasksToNPU.cppaie / Dialect / AIEX / IR / AIEXDialect.h
AIEX / Transforms / AIEDMATasksToNPU.cppaie / Dialect / AIEX / Transforms / AIEXPasses.h
AIEX / Transforms / AIEDmaToNpu.cppaie / Dialect / AIE / IR / AIEDialect.h
AIEX / Transforms / AIEDmaToNpu.cppaie / Dialect / AIEX / IR / AIEXDialect.h
AIEX / Transforms / AIEDmaToNpu.cppaie / Dialect / AIEX / Transforms / AIEXPasses.h
AIEX / Transforms / AIEHerdRouting.cppaie / Dialect / AIE / IR / AIEDialect.h
AIEX / Transforms / AIEHerdRouting.cppaie / Dialect / AIEX / IR / AIEXDialect.h
AIEX / Transforms / AIEHerdRouting.cppaie / Dialect / AIEX / Transforms / AIEXPasses.h
AIEX / Transforms / AIELowerMemcpy.cppaie / Dialect / AIE / IR / AIEDialect.h
AIEX / Transforms / AIELowerMemcpy.cppaie / Dialect / AIEX / AIETokenAnalysis.h
AIEX / Transforms / AIELowerMemcpy.cppaie / Dialect / AIEX / IR / AIEXDialect.h
AIEX / Transforms / AIELowerMemcpy.cppaie / Dialect / AIEX / Transforms / AIEXPasses.h
AIEX / Transforms / AIELowerMulticast.cppaie / Dialect / AIE / IR / AIEDialect.h
AIEX / Transforms / AIELowerMulticast.cppaie / Dialect / AIEX / IR / AIEXDialect.h
AIEX / Transforms / AIELowerMulticast.cppaie / Dialect / AIEX / Transforms / AIEXPasses.h
AIEX / Transforms / AIEMaterializeBDChains.cppaie / Dialect / AIE / IR / AIEDialect.h
AIEX / Transforms / AIEMaterializeBDChains.cppaie / Dialect / AIEX / IR / AIEXDialect.h
AIEX / Transforms / AIEMaterializeBDChains.cppaie / Dialect / AIEX / Transforms / AIEXPasses.h
AIEX / Transforms / AIESubstituteShimDMAAllocations.cppaie / Dialect / AIE / IR / AIEDialect.h
AIEX / Transforms / AIESubstituteShimDMAAllocations.cppaie / Dialect / AIEX / IR / AIEXDialect.h
AIEX / Transforms / AIESubstituteShimDMAAllocations.cppaie / Dialect / AIEX / Transforms / AIEXPasses.h
AIEX / Transforms / AIEXToStandard.cppaie / Dialect / AIE / IR / AIEDialect.h
AIEX / Transforms / AIEXToStandard.cppaie / Dialect / AIEX / IR / AIEXDialect.h
AIEX / Transforms / AIEXToStandard.cppaie / Dialect / AIEX / Transforms / AIEXPasses.h
AIEVec / Utils / Utils.cppaie / Dialect / AIEVec / Utils / Utils.h
AIEX / Utils / AIETokenAnalysis.cppaie / Dialect / AIEX / AIETokenAnalysis.h
AIEX / Utils / AIETokenAnalysis.cppaie / Dialect / AIE / IR / AIEDialect.h
AIEX / Utils / AIETokenAnalysis.cppaie / Dialect / AIEX / IR / AIEXDialect.h
XLLVM / XLLVMOps.cppaie / Dialect / XLLVM / XLLVMDialect.h
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_000037_000001.html b/doxygen/html/dir_000037_000001.html index 8216165214..e8deeae2b3 100644 --- a/doxygen/html/dir_000037_000001.html +++ b/doxygen/html/dir_000037_000001.html @@ -52,7 +52,7 @@

ADF → include Relation

File in lib/Dialect/ADFIncludes file in include
ADFDialect.cppaie / Dialect / ADF / ADFDialect.h
ADFDialect.cppaie / Dialect / ADF / ADFOps.h
ADFOps.cppaie / Dialect / ADF / ADFOps.h
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_000038_000001.html b/doxygen/html/dir_000038_000001.html index 9f2f028a4a..8d394be1f7 100644 --- a/doxygen/html/dir_000038_000001.html +++ b/doxygen/html/dir_000038_000001.html @@ -52,7 +52,7 @@

AIE → include Relation

File in lib/Dialect/AIEIncludes file in include
IR / AIEDialect.cppaie / Dialect / AIE / IR / AIEDialect.h
IR / AIETargetModel.cppaie / Dialect / AIE / IR / AIETargetModel.h
Transforms / AIEAssignBufferDescriptorIDs.cppaie / Dialect / AIE / Transforms / AIEAssignBufferDescriptorIDs.h
Transforms / AIEAssignBufferDescriptorIDs.cppaie / Dialect / AIE / IR / AIEDialect.h
Transforms / AIEAssignBufferDescriptorIDs.cppaie / Dialect / AIE / Transforms / AIEPasses.h
Transforms / AIEAssignBuffers.cppaie / Dialect / AIE / IR / AIEDialect.h
Transforms / AIEAssignBuffers.cppaie / Dialect / AIE / Transforms / AIEPasses.h
Transforms / AIEAssignLockIDs.cppaie / Dialect / AIE / IR / AIEDialect.h
Transforms / AIEAssignLockIDs.cppaie / Dialect / AIE / Transforms / AIEPasses.h
Transforms / AIECanonicalizeDevice.cppaie / Dialect / AIE / IR / AIEDialect.h
Transforms / AIECanonicalizeDevice.cppaie / Dialect / AIE / Transforms / AIEPasses.h
Transforms / AIECoreToStandard.cppaie / Dialect / AIE / IR / AIEDialect.h
Transforms / AIECoreToStandard.cppaie / Dialect / AIE / Transforms / AIEPasses.h
Transforms / AIECreatePathFindFlows.cppaie / Dialect / AIE / IR / AIEDialect.h
Transforms / AIECreatePathFindFlows.cppaie / Dialect / AIE / Transforms / AIEPasses.h
Transforms / AIECreatePathFindFlows.cppaie / Dialect / AIE / Transforms / AIEPathFinder.h
Transforms / AIEFindFlows.cppaie / Dialect / AIE / IR / AIEDialect.h
Transforms / AIEFindFlows.cppaie / Dialect / AIE / Transforms / AIEPasses.h
Transforms / AIEGenerateColumnControlOverlay.cppaie / Dialect / AIE / Transforms / AIEGenerateColumnControlOverlay.h
Transforms / AIEGenerateColumnControlOverlay.cppaie / Dialect / AIE / IR / AIEDialect.h
Transforms / AIEGenerateColumnControlOverlay.cppaie / Dialect / AIE / Transforms / AIEPasses.h
Transforms / AIELocalizeLocks.cppaie / Dialect / AIE / IR / AIEDialect.h
Transforms / AIELocalizeLocks.cppaie / Dialect / AIE / Transforms / AIEPasses.h
Transforms / AIELowerCascadeFlows.cppaie / Dialect / AIE / IR / AIEDialect.h
Transforms / AIELowerCascadeFlows.cppaie / Dialect / AIE / Transforms / AIEPasses.h
Transforms / AIENormalizeAddressSpaces.cppaie / Dialect / AIE / IR / AIEDialect.h
Transforms / AIENormalizeAddressSpaces.cppaie / Dialect / AIE / Transforms / AIEPasses.h
Transforms / AIEObjectFifoRegisterProcess.cppaie / Dialect / AIE / IR / AIEDialect.h
Transforms / AIEObjectFifoRegisterProcess.cppaie / Dialect / AIE / Transforms / AIEPasses.h
Transforms / AIEObjectFifoStatefulTransform.cppaie / Dialect / AIE / IR / AIEDialect.h
Transforms / AIEObjectFifoStatefulTransform.cppaie / Dialect / AIE / Transforms / AIEPasses.h
Transforms / AIEPathFinder.cppaie / Dialect / AIE / Transforms / AIEPathFinder.h
Transforms / AIEVectorOpt.cppaie / Dialect / AIE / IR / AIEDialect.h
Transforms / AIEVectorOpt.cppaie / Dialect / AIE / Transforms / AIEPasses.h
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_000039_000001.html b/doxygen/html/dir_000039_000001.html index 44273fcfbf..e3e2578e55 100644 --- a/doxygen/html/dir_000039_000001.html +++ b/doxygen/html/dir_000039_000001.html @@ -52,7 +52,7 @@

IR → include Relation

File in lib/Dialect/AIE/IRIncludes file in include
AIEDialect.cppaie / Dialect / AIE / IR / AIEDialect.h
AIETargetModel.cppaie / Dialect / AIE / IR / AIETargetModel.h
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_000040_000001.html b/doxygen/html/dir_000040_000001.html index eb9cc28042..7e85418884 100644 --- a/doxygen/html/dir_000040_000001.html +++ b/doxygen/html/dir_000040_000001.html @@ -52,7 +52,7 @@

Transforms → include Relation

File in lib/Dialect/AIE/TransformsIncludes file in include
AIEAssignBufferDescriptorIDs.cppaie / Dialect / AIE / Transforms / AIEAssignBufferDescriptorIDs.h
AIEAssignBufferDescriptorIDs.cppaie / Dialect / AIE / IR / AIEDialect.h
AIEAssignBufferDescriptorIDs.cppaie / Dialect / AIE / Transforms / AIEPasses.h
AIEAssignBuffers.cppaie / Dialect / AIE / IR / AIEDialect.h
AIEAssignBuffers.cppaie / Dialect / AIE / Transforms / AIEPasses.h
AIEAssignLockIDs.cppaie / Dialect / AIE / IR / AIEDialect.h
AIEAssignLockIDs.cppaie / Dialect / AIE / Transforms / AIEPasses.h
AIECanonicalizeDevice.cppaie / Dialect / AIE / IR / AIEDialect.h
AIECanonicalizeDevice.cppaie / Dialect / AIE / Transforms / AIEPasses.h
AIECoreToStandard.cppaie / Dialect / AIE / IR / AIEDialect.h
AIECoreToStandard.cppaie / Dialect / AIE / Transforms / AIEPasses.h
AIECreatePathFindFlows.cppaie / Dialect / AIE / IR / AIEDialect.h
AIECreatePathFindFlows.cppaie / Dialect / AIE / Transforms / AIEPasses.h
AIECreatePathFindFlows.cppaie / Dialect / AIE / Transforms / AIEPathFinder.h
AIEFindFlows.cppaie / Dialect / AIE / IR / AIEDialect.h
AIEFindFlows.cppaie / Dialect / AIE / Transforms / AIEPasses.h
AIEGenerateColumnControlOverlay.cppaie / Dialect / AIE / IR / AIEDialect.h
AIEGenerateColumnControlOverlay.cppaie / Dialect / AIE / Transforms / AIEGenerateColumnControlOverlay.h
AIEGenerateColumnControlOverlay.cppaie / Dialect / AIE / Transforms / AIEPasses.h
AIELocalizeLocks.cppaie / Dialect / AIE / IR / AIEDialect.h
AIELocalizeLocks.cppaie / Dialect / AIE / Transforms / AIEPasses.h
AIELowerCascadeFlows.cppaie / Dialect / AIE / IR / AIEDialect.h
AIELowerCascadeFlows.cppaie / Dialect / AIE / Transforms / AIEPasses.h
AIENormalizeAddressSpaces.cppaie / Dialect / AIE / IR / AIEDialect.h
AIENormalizeAddressSpaces.cppaie / Dialect / AIE / Transforms / AIEPasses.h
AIEObjectFifoRegisterProcess.cppaie / Dialect / AIE / IR / AIEDialect.h
AIEObjectFifoRegisterProcess.cppaie / Dialect / AIE / Transforms / AIEPasses.h
AIEObjectFifoStatefulTransform.cppaie / Dialect / AIE / IR / AIEDialect.h
AIEObjectFifoStatefulTransform.cppaie / Dialect / AIE / Transforms / AIEPasses.h
AIEPathFinder.cppaie / Dialect / AIE / Transforms / AIEPathFinder.h
AIEVectorOpt.cppaie / Dialect / AIE / IR / AIEDialect.h
AIEVectorOpt.cppaie / Dialect / AIE / Transforms / AIEPasses.h
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_000041_000001.html b/doxygen/html/dir_000041_000001.html index 77a8a9c934..bc75dd6d96 100644 --- a/doxygen/html/dir_000041_000001.html +++ b/doxygen/html/dir_000041_000001.html @@ -52,7 +52,7 @@

AIEVec → include Relation

File in lib/Dialect/AIEVecIncludes file in include
IR / AIE1 / AIEVecAIE1Ops.cppaie / Dialect / AIEVec / AIE1 / IR / AIEVecAIE1Ops.h
IR / AIE1 / AIEVecAIE1Ops.cppaie / Dialect / AIEVec / AIEVecUtils.h
IR / AIEVecOps.cppaie / Dialect / AIEVec / AIEVecUtils.h
IR / AIEVecOps.cppaie / Dialect / AIEVec / IR / AIEVecOps.h
IR / AIEVecTypes.cppaie / Dialect / AIEVec / IR / AIEVecTypes.h
TransformOps / AIEVecTransformOps.cppaie / Dialect / AIEVec / TransformOps / AIEVecTransformOps.h
TransformOps / DialectExtension.cppaie / Dialect / AIEVec / TransformOps / DialectExtension.h
TransformOps / DialectExtension.cppaie / Dialect / AIEVec / IR / AIEVecDialect.h
TransformOps / DialectExtension.cppaie / Dialect / AIEVec / TransformOps / AIEVecTransformOps.h
Transforms / AIEVecOptimizations.cppaie / Dialect / AIEVec / AIE1 / IR / AIEVecAIE1Ops.h
Transforms / AIEVecOptimizations.cppaie / Dialect / AIEVec / AIEVecUtils.h
Transforms / AIEVecOptimizations.cppaie / Dialect / AIEVec / Analysis / Passes.h
Transforms / AIEVecOptimizations.cppaie / Dialect / AIEVec / IR / AIEVecOps.h
Transforms / AIEVecOptimizations.cppaie / Dialect / AIEVec / Pipelines / Passes.h
Transforms / AIEVectorize.cppaie / Dialect / AIEVec / AIE1 / IR / AIEVecAIE1Ops.h
Transforms / AIEVectorize.cppaie / Dialect / AIEVec / AIEVecUtils.h
Transforms / AIEVectorize.cppaie / Dialect / AIEVec / IR / AIEVecOps.h
Transforms / AIEVectorize.cppaie / Dialect / AIEVec / Transforms / IntervalReuse.h
Transforms / AIEVectorize.cppaie / Dialect / AIEVec / Transforms / Passes.h
Transforms / ConvertVectorToAIEVec.cppaie / Dialect / AIEVec / Pipelines / Passes.h
Transforms / CopyRemoval.cppaie / Dialect / AIEVec / Pipelines / Passes.h
Transforms / DynamicSizeNoImplicitBroadcast.cppaie / Dialect / AIEVec / AIEVecUtils.h
Transforms / DynamicSizeNoImplicitBroadcast.cppaie / Dialect / AIEVec / Pipelines / Passes.h
Transforms / FoldMulAddChainToConvOp.cppaie / Dialect / AIEVec / AIEVecUtils.h
Transforms / FoldMulAddChainToConvOp.cppaie / Dialect / AIEVec / Analysis / Passes.h
Transforms / FoldMulAddChainToConvOp.cppaie / Dialect / AIEVec / IR / AIEVecOps.h
Transforms / FoldMulAddChainToConvOp.cppaie / Dialect / AIEVec / Pipelines / Passes.h
Transforms / IntervalReuse.cppaie / Dialect / AIEVec / Transforms / IntervalReuse.h
Transforms / IntervalReuse.cppaie / Dialect / AIEVec / AIEVecUtils.h
Transforms / VectorToAIEVecConversions.cppaie / Dialect / AIEVec / AIE1 / IR / AIEVecAIE1Ops.h
Transforms / VectorToAIEVecConversions.cppaie / Dialect / AIEVec / AIEVecUtils.h
Transforms / VectorToAIEVecConversions.cppaie / Dialect / AIEVec / IR / AIEVecOps.h
Transforms / VectorToAIEVecConversions.cppaie / Dialect / AIEVec / Pipelines / Passes.h
Transforms / VectorToAIEVecConversions.cppaie / Dialect / AIEVec / Utils / Utils.h
Transforms / VectorToVectorConversions.cppaie / Dialect / AIEVec / AIEVecUtils.h
Transforms / VectorToVectorConversions.cppaie / Dialect / AIEVec / Pipelines / Passes.h
Transforms / VectorToVectorConversions.cppaie / Dialect / AIEVec / Utils / Utils.h
Utils / Utils.cppaie / Dialect / AIEVec / Utils / Utils.h
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_000042_000001.html b/doxygen/html/dir_000042_000001.html index 95e02df9d6..58ee3aefe0 100644 --- a/doxygen/html/dir_000042_000001.html +++ b/doxygen/html/dir_000042_000001.html @@ -52,7 +52,7 @@

IR → include Relation

File in lib/Dialect/AIEVec/IRIncludes file in include
AIE1 / AIEVecAIE1Ops.cppaie / Dialect / AIEVec / AIE1 / IR / AIEVecAIE1Ops.h
AIE1 / AIEVecAIE1Ops.cppaie / Dialect / AIEVec / AIEVecUtils.h
AIEVecOps.cppaie / Dialect / AIEVec / IR / AIEVecOps.h
AIEVecOps.cppaie / Dialect / AIEVec / AIEVecUtils.h
AIEVecTypes.cppaie / Dialect / AIEVec / IR / AIEVecTypes.h
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_000043_000001.html b/doxygen/html/dir_000043_000001.html index c07593cb5e..401e2fe27f 100644 --- a/doxygen/html/dir_000043_000001.html +++ b/doxygen/html/dir_000043_000001.html @@ -52,7 +52,7 @@

AIE1 → include Relation

File in lib/Dialect/AIEVec/IR/AIE1Includes file in include
AIEVecAIE1Ops.cppaie / Dialect / AIEVec / AIE1 / IR / AIEVecAIE1Ops.h
AIEVecAIE1Ops.cppaie / Dialect / AIEVec / AIEVecUtils.h
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_000044_000001.html b/doxygen/html/dir_000044_000001.html index 7eb0028310..2fbfb177f9 100644 --- a/doxygen/html/dir_000044_000001.html +++ b/doxygen/html/dir_000044_000001.html @@ -52,7 +52,7 @@

TransformOps → include Relation

File in lib/Dialect/AIEVec/TransformOpsIncludes file in include
AIEVecTransformOps.cppaie / Dialect / AIEVec / TransformOps / AIEVecTransformOps.h
DialectExtension.cppaie / Dialect / AIEVec / IR / AIEVecDialect.h
DialectExtension.cppaie / Dialect / AIEVec / TransformOps / AIEVecTransformOps.h
DialectExtension.cppaie / Dialect / AIEVec / TransformOps / DialectExtension.h
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_000045_000001.html b/doxygen/html/dir_000045_000001.html index e51e9e81b1..da1e7b654a 100644 --- a/doxygen/html/dir_000045_000001.html +++ b/doxygen/html/dir_000045_000001.html @@ -52,7 +52,7 @@

Transforms → include Relation

File in lib/Dialect/AIEVec/TransformsIncludes file in include
AIEVecOptimizations.cppaie / Dialect / AIEVec / AIE1 / IR / AIEVecAIE1Ops.h
AIEVecOptimizations.cppaie / Dialect / AIEVec / IR / AIEVecOps.h
AIEVecOptimizations.cppaie / Dialect / AIEVec / AIEVecUtils.h
AIEVecOptimizations.cppaie / Dialect / AIEVec / Pipelines / Passes.h
AIEVecOptimizations.cppaie / Dialect / AIEVec / Analysis / Passes.h
AIEVectorize.cppaie / Dialect / AIEVec / AIE1 / IR / AIEVecAIE1Ops.h
AIEVectorize.cppaie / Dialect / AIEVec / IR / AIEVecOps.h
AIEVectorize.cppaie / Dialect / AIEVec / AIEVecUtils.h
AIEVectorize.cppaie / Dialect / AIEVec / Transforms / IntervalReuse.h
AIEVectorize.cppaie / Dialect / AIEVec / Transforms / Passes.h
ConvertVectorToAIEVec.cppaie / Dialect / AIEVec / Pipelines / Passes.h
CopyRemoval.cppaie / Dialect / AIEVec / Pipelines / Passes.h
DynamicSizeNoImplicitBroadcast.cppaie / Dialect / AIEVec / AIEVecUtils.h
DynamicSizeNoImplicitBroadcast.cppaie / Dialect / AIEVec / Pipelines / Passes.h
FoldMulAddChainToConvOp.cppaie / Dialect / AIEVec / IR / AIEVecOps.h
FoldMulAddChainToConvOp.cppaie / Dialect / AIEVec / AIEVecUtils.h
FoldMulAddChainToConvOp.cppaie / Dialect / AIEVec / Analysis / Passes.h
FoldMulAddChainToConvOp.cppaie / Dialect / AIEVec / Pipelines / Passes.h
IntervalReuse.cppaie / Dialect / AIEVec / AIEVecUtils.h
IntervalReuse.cppaie / Dialect / AIEVec / Transforms / IntervalReuse.h
VectorToAIEVecConversions.cppaie / Dialect / AIEVec / AIE1 / IR / AIEVecAIE1Ops.h
VectorToAIEVecConversions.cppaie / Dialect / AIEVec / IR / AIEVecOps.h
VectorToAIEVecConversions.cppaie / Dialect / AIEVec / AIEVecUtils.h
VectorToAIEVecConversions.cppaie / Dialect / AIEVec / Pipelines / Passes.h
VectorToAIEVecConversions.cppaie / Dialect / AIEVec / Utils / Utils.h
VectorToVectorConversions.cppaie / Dialect / AIEVec / AIEVecUtils.h
VectorToVectorConversions.cppaie / Dialect / AIEVec / Pipelines / Passes.h
VectorToVectorConversions.cppaie / Dialect / AIEVec / Utils / Utils.h
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_000046_000001.html b/doxygen/html/dir_000046_000001.html index 04b7b7dcde..31258a2143 100644 --- a/doxygen/html/dir_000046_000001.html +++ b/doxygen/html/dir_000046_000001.html @@ -52,7 +52,7 @@

Utils → include Relation

File in lib/Dialect/AIEVec/UtilsIncludes file in include
Utils.cppaie / Dialect / AIEVec / Utils / Utils.h
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_000047_000001.html b/doxygen/html/dir_000047_000001.html index 2ecebdb604..207864b02a 100644 --- a/doxygen/html/dir_000047_000001.html +++ b/doxygen/html/dir_000047_000001.html @@ -52,7 +52,7 @@

AIEX → include Relation

File in lib/Dialect/AIEXIncludes file in include
IR / AIEXDialect.cppaie / Dialect / AIEX / IR / AIEXDialect.h
Transforms / AIEAssignRuntimeSequenceBDIDs.cppaie / Dialect / AIE / IR / AIEDialect.h
Transforms / AIEAssignRuntimeSequenceBDIDs.cppaie / Dialect / AIE / Transforms / AIEAssignBufferDescriptorIDs.h
Transforms / AIEAssignRuntimeSequenceBDIDs.cppaie / Dialect / AIEX / IR / AIEXDialect.h
Transforms / AIEAssignRuntimeSequenceBDIDs.cppaie / Dialect / AIEX / Transforms / AIEXPasses.h
Transforms / AIECreateBroadcastPacket.cppaie / Dialect / AIE / IR / AIEDialect.h
Transforms / AIECreateBroadcastPacket.cppaie / Dialect / AIEX / IR / AIEXDialect.h
Transforms / AIECreateBroadcastPacket.cppaie / Dialect / AIEX / Transforms / AIEXPasses.h
Transforms / AIECreateCores.cppaie / Dialect / AIE / IR / AIEDialect.h
Transforms / AIECreateCores.cppaie / Dialect / AIEX / IR / AIEXDialect.h
Transforms / AIECreateCores.cppaie / Dialect / AIEX / Transforms / AIEXPasses.h
Transforms / AIECreateLocks.cppaie / Dialect / AIE / IR / AIEDialect.h
Transforms / AIECreateLocks.cppaie / Dialect / AIEX / AIETokenAnalysis.h
Transforms / AIECreateLocks.cppaie / Dialect / AIEX / IR / AIEXDialect.h
Transforms / AIECreateLocks.cppaie / Dialect / AIEX / Transforms / AIEXPasses.h
Transforms / AIECtrlPacketToDma.cppaie / Dialect / AIE / IR / AIEDialect.h
Transforms / AIECtrlPacketToDma.cppaie / Dialect / AIE / Transforms / AIEGenerateColumnControlOverlay.h
Transforms / AIECtrlPacketToDma.cppaie / Dialect / AIEX / IR / AIEXDialect.h
Transforms / AIECtrlPacketToDma.cppaie / Dialect / AIEX / Transforms / AIEXPasses.h
Transforms / AIEDMATasksToNPU.cppaie / Dialect / AIE / IR / AIEDialect.h
Transforms / AIEDMATasksToNPU.cppaie / Dialect / AIEX / IR / AIEXDialect.h
Transforms / AIEDMATasksToNPU.cppaie / Dialect / AIEX / Transforms / AIEXPasses.h
Transforms / AIEDmaToNpu.cppaie / Dialect / AIE / IR / AIEDialect.h
Transforms / AIEDmaToNpu.cppaie / Dialect / AIEX / IR / AIEXDialect.h
Transforms / AIEDmaToNpu.cppaie / Dialect / AIEX / Transforms / AIEXPasses.h
Transforms / AIEHerdRouting.cppaie / Dialect / AIE / IR / AIEDialect.h
Transforms / AIEHerdRouting.cppaie / Dialect / AIEX / IR / AIEXDialect.h
Transforms / AIEHerdRouting.cppaie / Dialect / AIEX / Transforms / AIEXPasses.h
Transforms / AIELowerMemcpy.cppaie / Dialect / AIE / IR / AIEDialect.h
Transforms / AIELowerMemcpy.cppaie / Dialect / AIEX / AIETokenAnalysis.h
Transforms / AIELowerMemcpy.cppaie / Dialect / AIEX / IR / AIEXDialect.h
Transforms / AIELowerMemcpy.cppaie / Dialect / AIEX / Transforms / AIEXPasses.h
Transforms / AIELowerMulticast.cppaie / Dialect / AIE / IR / AIEDialect.h
Transforms / AIELowerMulticast.cppaie / Dialect / AIEX / IR / AIEXDialect.h
Transforms / AIELowerMulticast.cppaie / Dialect / AIEX / Transforms / AIEXPasses.h
Transforms / AIEMaterializeBDChains.cppaie / Dialect / AIE / IR / AIEDialect.h
Transforms / AIEMaterializeBDChains.cppaie / Dialect / AIEX / IR / AIEXDialect.h
Transforms / AIEMaterializeBDChains.cppaie / Dialect / AIEX / Transforms / AIEXPasses.h
Transforms / AIESubstituteShimDMAAllocations.cppaie / Dialect / AIE / IR / AIEDialect.h
Transforms / AIESubstituteShimDMAAllocations.cppaie / Dialect / AIEX / IR / AIEXDialect.h
Transforms / AIESubstituteShimDMAAllocations.cppaie / Dialect / AIEX / Transforms / AIEXPasses.h
Transforms / AIEXToStandard.cppaie / Dialect / AIE / IR / AIEDialect.h
Transforms / AIEXToStandard.cppaie / Dialect / AIEX / IR / AIEXDialect.h
Transforms / AIEXToStandard.cppaie / Dialect / AIEX / Transforms / AIEXPasses.h
Utils / AIETokenAnalysis.cppaie / Dialect / AIEX / AIETokenAnalysis.h
Utils / AIETokenAnalysis.cppaie / Dialect / AIE / IR / AIEDialect.h
Utils / AIETokenAnalysis.cppaie / Dialect / AIEX / IR / AIEXDialect.h
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_000048_000001.html b/doxygen/html/dir_000048_000001.html index 7c365849a1..fe485aeb92 100644 --- a/doxygen/html/dir_000048_000001.html +++ b/doxygen/html/dir_000048_000001.html @@ -52,7 +52,7 @@

IR → include Relation

File in lib/Dialect/AIEX/IRIncludes file in include
AIEXDialect.cppaie / Dialect / AIEX / IR / AIEXDialect.h
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_000049_000001.html b/doxygen/html/dir_000049_000001.html index e2bea365f9..dd49d80741 100644 --- a/doxygen/html/dir_000049_000001.html +++ b/doxygen/html/dir_000049_000001.html @@ -52,7 +52,7 @@

Transforms → include Relation

File in lib/Dialect/AIEX/TransformsIncludes file in include
AIEAssignRuntimeSequenceBDIDs.cppaie / Dialect / AIE / Transforms / AIEAssignBufferDescriptorIDs.h
AIEAssignRuntimeSequenceBDIDs.cppaie / Dialect / AIE / IR / AIEDialect.h
AIEAssignRuntimeSequenceBDIDs.cppaie / Dialect / AIEX / IR / AIEXDialect.h
AIEAssignRuntimeSequenceBDIDs.cppaie / Dialect / AIEX / Transforms / AIEXPasses.h
AIECreateBroadcastPacket.cppaie / Dialect / AIE / IR / AIEDialect.h
AIECreateBroadcastPacket.cppaie / Dialect / AIEX / IR / AIEXDialect.h
AIECreateBroadcastPacket.cppaie / Dialect / AIEX / Transforms / AIEXPasses.h
AIECreateCores.cppaie / Dialect / AIE / IR / AIEDialect.h
AIECreateCores.cppaie / Dialect / AIEX / IR / AIEXDialect.h
AIECreateCores.cppaie / Dialect / AIEX / Transforms / AIEXPasses.h
AIECreateLocks.cppaie / Dialect / AIE / IR / AIEDialect.h
AIECreateLocks.cppaie / Dialect / AIEX / AIETokenAnalysis.h
AIECreateLocks.cppaie / Dialect / AIEX / IR / AIEXDialect.h
AIECreateLocks.cppaie / Dialect / AIEX / Transforms / AIEXPasses.h
AIECtrlPacketToDma.cppaie / Dialect / AIE / IR / AIEDialect.h
AIECtrlPacketToDma.cppaie / Dialect / AIE / Transforms / AIEGenerateColumnControlOverlay.h
AIECtrlPacketToDma.cppaie / Dialect / AIEX / IR / AIEXDialect.h
AIECtrlPacketToDma.cppaie / Dialect / AIEX / Transforms / AIEXPasses.h
AIEDMATasksToNPU.cppaie / Dialect / AIE / IR / AIEDialect.h
AIEDMATasksToNPU.cppaie / Dialect / AIEX / IR / AIEXDialect.h
AIEDMATasksToNPU.cppaie / Dialect / AIEX / Transforms / AIEXPasses.h
AIEDmaToNpu.cppaie / Dialect / AIE / IR / AIEDialect.h
AIEDmaToNpu.cppaie / Dialect / AIEX / IR / AIEXDialect.h
AIEDmaToNpu.cppaie / Dialect / AIEX / Transforms / AIEXPasses.h
AIEHerdRouting.cppaie / Dialect / AIE / IR / AIEDialect.h
AIEHerdRouting.cppaie / Dialect / AIEX / IR / AIEXDialect.h
AIEHerdRouting.cppaie / Dialect / AIEX / Transforms / AIEXPasses.h
AIELowerMemcpy.cppaie / Dialect / AIE / IR / AIEDialect.h
AIELowerMemcpy.cppaie / Dialect / AIEX / AIETokenAnalysis.h
AIELowerMemcpy.cppaie / Dialect / AIEX / IR / AIEXDialect.h
AIELowerMemcpy.cppaie / Dialect / AIEX / Transforms / AIEXPasses.h
AIELowerMulticast.cppaie / Dialect / AIE / IR / AIEDialect.h
AIELowerMulticast.cppaie / Dialect / AIEX / IR / AIEXDialect.h
AIELowerMulticast.cppaie / Dialect / AIEX / Transforms / AIEXPasses.h
AIEMaterializeBDChains.cppaie / Dialect / AIE / IR / AIEDialect.h
AIEMaterializeBDChains.cppaie / Dialect / AIEX / IR / AIEXDialect.h
AIEMaterializeBDChains.cppaie / Dialect / AIEX / Transforms / AIEXPasses.h
AIESubstituteShimDMAAllocations.cppaie / Dialect / AIE / IR / AIEDialect.h
AIESubstituteShimDMAAllocations.cppaie / Dialect / AIEX / IR / AIEXDialect.h
AIESubstituteShimDMAAllocations.cppaie / Dialect / AIEX / Transforms / AIEXPasses.h
AIEXToStandard.cppaie / Dialect / AIE / IR / AIEDialect.h
AIEXToStandard.cppaie / Dialect / AIEX / IR / AIEXDialect.h
AIEXToStandard.cppaie / Dialect / AIEX / Transforms / AIEXPasses.h
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_000050_000001.html b/doxygen/html/dir_000050_000001.html index 8cb159e72f..3a1e3d2405 100644 --- a/doxygen/html/dir_000050_000001.html +++ b/doxygen/html/dir_000050_000001.html @@ -52,7 +52,7 @@

Utils → include Relation

File in lib/Dialect/AIEX/UtilsIncludes file in include
AIETokenAnalysis.cppaie / Dialect / AIE / IR / AIEDialect.h
AIETokenAnalysis.cppaie / Dialect / AIEX / AIETokenAnalysis.h
AIETokenAnalysis.cppaie / Dialect / AIEX / IR / AIEXDialect.h
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_000051_000001.html b/doxygen/html/dir_000051_000001.html index 2c2cac583f..ce3ad8c506 100644 --- a/doxygen/html/dir_000051_000001.html +++ b/doxygen/html/dir_000051_000001.html @@ -52,7 +52,7 @@

XLLVM → include Relation

File in lib/Dialect/XLLVMIncludes file in include
XLLVMOps.cppaie / Dialect / XLLVM / XLLVMDialect.h
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_000052_000001.html b/doxygen/html/dir_000052_000001.html index 06b383b616..4532b4a1ba 100644 --- a/doxygen/html/dir_000052_000001.html +++ b/doxygen/html/dir_000052_000001.html @@ -52,7 +52,7 @@

Target → include Relation

File in lib/TargetIncludes file in include
LLVMIR / Dialect / XLLVM / XLLVMToLLVMIRTranslation.cppaie / Target / LLVMIR / Dialect / XLLVM / XLLVMToLLVMIRTranslation.h
LLVMIR / Dialect / XLLVM / XLLVMToLLVMIRTranslation.cppaie / Dialect / XLLVM / XLLVMDialect.h
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_000053_000001.html b/doxygen/html/dir_000053_000001.html index 7e09e939d0..dacdccc62a 100644 --- a/doxygen/html/dir_000053_000001.html +++ b/doxygen/html/dir_000053_000001.html @@ -52,7 +52,7 @@

LLVMIR → include Relation

File in lib/Target/LLVMIRIncludes file in include
Dialect / XLLVM / XLLVMToLLVMIRTranslation.cppaie / Target / LLVMIR / Dialect / XLLVM / XLLVMToLLVMIRTranslation.h
Dialect / XLLVM / XLLVMToLLVMIRTranslation.cppaie / Dialect / XLLVM / XLLVMDialect.h
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_000054_000001.html b/doxygen/html/dir_000054_000001.html index 991b490324..a58731f7cc 100644 --- a/doxygen/html/dir_000054_000001.html +++ b/doxygen/html/dir_000054_000001.html @@ -52,7 +52,7 @@

Dialect → include Relation

File in lib/Target/LLVMIR/DialectIncludes file in include
XLLVM / XLLVMToLLVMIRTranslation.cppaie / Target / LLVMIR / Dialect / XLLVM / XLLVMToLLVMIRTranslation.h
XLLVM / XLLVMToLLVMIRTranslation.cppaie / Dialect / XLLVM / XLLVMDialect.h
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_000055_000001.html b/doxygen/html/dir_000055_000001.html index e2728767e0..0eb4b8ba99 100644 --- a/doxygen/html/dir_000055_000001.html +++ b/doxygen/html/dir_000055_000001.html @@ -52,7 +52,7 @@

XLLVM → include Relation

File in lib/Target/LLVMIR/Dialect/XLLVMIncludes file in include
XLLVMToLLVMIRTranslation.cppaie / Dialect / XLLVM / XLLVMDialect.h
XLLVMToLLVMIRTranslation.cppaie / Target / LLVMIR / Dialect / XLLVM / XLLVMToLLVMIRTranslation.h
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_000056_000001.html b/doxygen/html/dir_000056_000001.html index 938e24b3c4..0c3b3684f6 100644 --- a/doxygen/html/dir_000056_000001.html +++ b/doxygen/html/dir_000056_000001.html @@ -52,7 +52,7 @@

Targets → include Relation

File in lib/TargetsIncludes file in include
ADFGenerateCppGraph.cppaie / Dialect / ADF / ADFDialect.h
ADFGenerateCppGraph.cppaie / Dialect / ADF / ADFOps.h
ADFGenerateCppGraph.cppaie / Targets / AIETargets.h
AIEFlowsToJSON.cppaie / Dialect / AIE / IR / AIEDialect.h
AIEFlowsToJSON.cppaie / Targets / AIETargets.h
AIELLVMLink.cppaie / Targets / AIETargets.h
AIERT.cppaie / Targets / AIERT.h
AIERT.cppaie / Targets / AIETargetShared.h
AIETargetAirbin.cppaie / Dialect / AIE / IR / AIEDialect.h
AIETargetAirbin.cppaie / Dialect / AIE / IR / AIETargetModel.h
AIETargetAirbin.cppaie / Dialect / AIEX / IR / AIEXDialect.h
AIETargetBCF.cppaie / Dialect / AIE / IR / AIEDialect.h
AIETargetBCF.cppaie / Targets / AIETargets.h
AIETargetBCF.cppaie / Dialect / AIEX / IR / AIEXDialect.h
AIETargetCDODirect.cppaie / Dialect / AIE / IR / AIEDialect.h
AIETargetCDODirect.cppaie / Dialect / AIE / IR / AIEEnums.h
AIETargetCDODirect.cppaie / Targets / AIERT.h
AIETargetCDODirect.cppaie / Targets / AIETargets.h
AIETargetCDODirect.cppaie / Dialect / AIEX / IR / AIEXDialect.h
AIETargetHSA.cppaie / Dialect / AIE / IR / AIEDialect.h
AIETargetHSA.cppaie / Targets / AIETargets.h
AIETargetHSA.cppaie / Targets / AIETargetShared.h
AIETargetHSA.cppaie / Dialect / AIEX / IR / AIEXDialect.h
AIETargetLdScript.cppaie / Dialect / AIE / IR / AIEDialect.h
AIETargetLdScript.cppaie / Targets / AIETargets.h
AIETargetNPU.cppaie / Dialect / AIE / IR / AIEDialect.h
AIETargetNPU.cppaie / Targets / AIETargets.h
AIETargetNPU.cppaie / Dialect / AIEX / IR / AIEXDialect.h
AIETargets.cppaie / Dialect / ADF / ADFDialect.h
AIETargets.cppaie / Dialect / AIE / IR / AIEDialect.h
AIETargets.cppaie / Targets / AIETargets.h
AIETargets.cppaie / Dialect / AIEX / IR / AIEXDialect.h
AIETargetShared.cppaie / Dialect / AIE / IR / AIEDialect.h
AIETargetShared.cppaie / Targets / AIETargets.h
AIETargetShared.cppaie / Targets / AIETargetShared.h
AIETargetShared.cppaie / Dialect / AIEX / IR / AIEXDialect.h
AIETargetSimulationFiles.cppaie / Dialect / AIE / IR / AIEDialect.h
AIETargetSimulationFiles.cppaie / Targets / AIETargets.h
AIETargetXAIEV2.cppaie / Dialect / AIE / IR / AIEDialect.h
AIETargetXAIEV2.cppaie / Targets / AIETargets.h
AIETargetXAIEV2.cppaie / Targets / AIETargetShared.h
AIETargetXAIEV2.cppaie / Dialect / AIEX / IR / AIEXDialect.h
AIEVecToCpp / TranslateAIEVecToCpp.cppaie / Targets / AIETargets.h
AIEVecToCpp / TranslateAIEVecToCpp.cppaie / Dialect / AIEVec / AIE1 / IR / AIEVecAIE1Ops.h
AIEVecToCpp / TranslateAIEVecToCpp.cppaie / Dialect / AIEVec / IR / AIEVecOps.h
AIEVecToCpp / TranslateAIEVecToCpp.cppaie / Dialect / AIEVec / AIEVecUtils.h
AIEVecToCpp / TranslateRegistration.cppaie / Targets / AIETargets.h
AIEVecToCpp / TranslateRegistration.cppaie / Dialect / AIEVec / AIE1 / IR / AIEVecAIE1Ops.h
AIEVecToCpp / TranslateRegistration.cppaie / Dialect / AIEVec / IR / AIEVecDialect.h
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_000057_000001.html b/doxygen/html/dir_000057_000001.html index 7f01079430..f9805b6229 100644 --- a/doxygen/html/dir_000057_000001.html +++ b/doxygen/html/dir_000057_000001.html @@ -52,7 +52,7 @@

AIEVecToCpp → include Relation

File in lib/Targets/AIEVecToCppIncludes file in include
TranslateAIEVecToCpp.cppaie / Targets / AIETargets.h
TranslateAIEVecToCpp.cppaie / Dialect / AIEVec / AIE1 / IR / AIEVecAIE1Ops.h
TranslateAIEVecToCpp.cppaie / Dialect / AIEVec / IR / AIEVecOps.h
TranslateAIEVecToCpp.cppaie / Dialect / AIEVec / AIEVecUtils.h
TranslateRegistration.cppaie / Targets / AIETargets.h
TranslateRegistration.cppaie / Dialect / AIEVec / AIE1 / IR / AIEVecAIE1Ops.h
TranslateRegistration.cppaie / Dialect / AIEVec / IR / AIEVecDialect.h
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_08e4174f47f77ebdd20bf92371a4e28d.html b/doxygen/html/dir_08e4174f47f77ebdd20bf92371a4e28d.html index feec5ec4c3..b93da0c5d8 100644 --- a/doxygen/html/dir_08e4174f47f77ebdd20bf92371a4e28d.html +++ b/doxygen/html/dir_08e4174f47f77ebdd20bf92371a4e28d.html @@ -75,7 +75,7 @@
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_09464ce1817b7ab8f8b38dd19f62be34.html b/doxygen/html/dir_09464ce1817b7ab8f8b38dd19f62be34.html index dd873b8b23..853278fa7a 100644 --- a/doxygen/html/dir_09464ce1817b7ab8f8b38dd19f62be34.html +++ b/doxygen/html/dir_09464ce1817b7ab8f8b38dd19f62be34.html @@ -77,7 +77,7 @@
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_0fe0739699936b861f29095231fbedc1.html b/doxygen/html/dir_0fe0739699936b861f29095231fbedc1.html index 64d722a0ca..e972f316cc 100644 --- a/doxygen/html/dir_0fe0739699936b861f29095231fbedc1.html +++ b/doxygen/html/dir_0fe0739699936b861f29095231fbedc1.html @@ -75,7 +75,7 @@
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_1140fdf90b344c2e8ac6728afb4c60eb.html b/doxygen/html/dir_1140fdf90b344c2e8ac6728afb4c60eb.html index 7251d5f6c0..ddd06a58f8 100644 --- a/doxygen/html/dir_1140fdf90b344c2e8ac6728afb4c60eb.html +++ b/doxygen/html/dir_1140fdf90b344c2e8ac6728afb4c60eb.html @@ -62,7 +62,7 @@
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_11444a1010aae98ce71342069197f695.html b/doxygen/html/dir_11444a1010aae98ce71342069197f695.html index d90acaa2a2..0f3a9f2ea8 100644 --- a/doxygen/html/dir_11444a1010aae98ce71342069197f695.html +++ b/doxygen/html/dir_11444a1010aae98ce71342069197f695.html @@ -75,7 +75,7 @@
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_12a96bdcc885ecacc799866a8efa56d5.html b/doxygen/html/dir_12a96bdcc885ecacc799866a8efa56d5.html index c3e5020746..b032b01520 100644 --- a/doxygen/html/dir_12a96bdcc885ecacc799866a8efa56d5.html +++ b/doxygen/html/dir_12a96bdcc885ecacc799866a8efa56d5.html @@ -76,7 +76,7 @@
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_1a25ec519b6c1121408b67cc33ce3f15.html b/doxygen/html/dir_1a25ec519b6c1121408b67cc33ce3f15.html index c66d8c0e24..16da3689ee 100644 --- a/doxygen/html/dir_1a25ec519b6c1121408b67cc33ce3f15.html +++ b/doxygen/html/dir_1a25ec519b6c1121408b67cc33ce3f15.html @@ -92,7 +92,7 @@
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_1db2d584021e693e2c84ae0ede3503d3.html b/doxygen/html/dir_1db2d584021e693e2c84ae0ede3503d3.html index 95123180e2..65a07da32a 100644 --- a/doxygen/html/dir_1db2d584021e693e2c84ae0ede3503d3.html +++ b/doxygen/html/dir_1db2d584021e693e2c84ae0ede3503d3.html @@ -83,7 +83,7 @@
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_218badb5e9efcaf1081f258c95281309.html b/doxygen/html/dir_218badb5e9efcaf1081f258c95281309.html index 6282ccac7e..4869a75dd4 100644 --- a/doxygen/html/dir_218badb5e9efcaf1081f258c95281309.html +++ b/doxygen/html/dir_218badb5e9efcaf1081f258c95281309.html @@ -88,7 +88,7 @@
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_2333218f17efae3e90b6d759a11695c8.html b/doxygen/html/dir_2333218f17efae3e90b6d759a11695c8.html index a17585605c..e9e9eda4ed 100644 --- a/doxygen/html/dir_2333218f17efae3e90b6d759a11695c8.html +++ b/doxygen/html/dir_2333218f17efae3e90b6d759a11695c8.html @@ -81,7 +81,7 @@
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_2450af8b585a2d8242d1363a8e44f078.html b/doxygen/html/dir_2450af8b585a2d8242d1363a8e44f078.html index d39d1c6e54..a92e8facc2 100644 --- a/doxygen/html/dir_2450af8b585a2d8242d1363a8e44f078.html +++ b/doxygen/html/dir_2450af8b585a2d8242d1363a8e44f078.html @@ -79,7 +79,7 @@
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_284a574b92693d39c7528f5a56aadd1e.html b/doxygen/html/dir_284a574b92693d39c7528f5a56aadd1e.html index de65e48ebf..3be34dc229 100644 --- a/doxygen/html/dir_284a574b92693d39c7528f5a56aadd1e.html +++ b/doxygen/html/dir_284a574b92693d39c7528f5a56aadd1e.html @@ -75,7 +75,7 @@
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_30cbee68411305f525f1ef817ea9334b.html b/doxygen/html/dir_30cbee68411305f525f1ef817ea9334b.html index ccba81fc94..5af607b4d2 100644 --- a/doxygen/html/dir_30cbee68411305f525f1ef817ea9334b.html +++ b/doxygen/html/dir_30cbee68411305f525f1ef817ea9334b.html @@ -101,7 +101,7 @@
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_32b18eaa679abc4a56fa7fc744f660a6.html b/doxygen/html/dir_32b18eaa679abc4a56fa7fc744f660a6.html index e6f8a469ba..c7563a146b 100644 --- a/doxygen/html/dir_32b18eaa679abc4a56fa7fc744f660a6.html +++ b/doxygen/html/dir_32b18eaa679abc4a56fa7fc744f660a6.html @@ -81,7 +81,7 @@
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_356fd60ca6192b876e72ba14ca0d8b14.html b/doxygen/html/dir_356fd60ca6192b876e72ba14ca0d8b14.html index 78b27bf9b4..adbcd73629 100644 --- a/doxygen/html/dir_356fd60ca6192b876e72ba14ca0d8b14.html +++ b/doxygen/html/dir_356fd60ca6192b876e72ba14ca0d8b14.html @@ -62,7 +62,7 @@
-Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
diff --git a/doxygen/html/dir_38c1dda222e2fa1f8060eb14e2940f7d.html b/doxygen/html/dir_38c1dda222e2fa1f8060eb14e2940f7d.html index a18b1112b4..b03484197e 100644 --- a/doxygen/html/dir_38c1dda222e2fa1f8060eb14e2940f7d.html +++ b/doxygen/html/dir_38c1dda222e2fa1f8060eb14e2940f7d.html @@ -76,7 +76,7 @@
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                                                                                                                                                                        diff --git a/doxygen/html/globals_u.html b/doxygen/html/globals_u.html index 2b4c708b02..409eee2083 100644 --- a/doxygen/html/globals_u.html +++ b/doxygen/html/globals_u.html @@ -58,7 +58,7 @@

                                                                                                                                                                        - u -

                                                                                                                                                                          -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
                                                                                                                                                                          diff --git a/doxygen/html/globals_v.html b/doxygen/html/globals_v.html index 3dc009463b..096d2b9f2a 100644 --- a/doxygen/html/globals_v.html +++ b/doxygen/html/globals_v.html @@ -61,7 +61,7 @@

                                                                                                                                                                          - v -

                                                                                                                                                                            -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
                                                                                                                                                                            diff --git a/doxygen/html/globals_x.html b/doxygen/html/globals_x.html index 0c7ae32d1f..eb85369d6f 100644 --- a/doxygen/html/globals_x.html +++ b/doxygen/html/globals_x.html @@ -70,7 +70,7 @@

                                                                                                                                                                            - x -

                                                                                                                                                                              -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
                                                                                                                                                                              diff --git a/doxygen/html/graph_legend.html b/doxygen/html/graph_legend.html index 2ebd60e636..473b1f0c71 100644 --- a/doxygen/html/graph_legend.html +++ b/doxygen/html/graph_legend.html @@ -112,7 +112,7 @@
                                                                                                                                                                              -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
                                                                                                                                                                              diff --git a/doxygen/html/hierarchy.html b/doxygen/html/hierarchy.html index 1a594d1443..9d15270298 100644 --- a/doxygen/html/hierarchy.html +++ b/doxygen/html/hierarchy.html @@ -326,7 +326,7 @@
                                                                                                                                                                              -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
                                                                                                                                                                              diff --git a/doxygen/html/hsa__ext__air_8h.html b/doxygen/html/hsa__ext__air_8h.html index be0021ee1e..b76b3d6d3a 100644 --- a/doxygen/html/hsa__ext__air_8h.html +++ b/doxygen/html/hsa__ext__air_8h.html @@ -286,7 +286,7 @@

                                                                                                                                                                              -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
                                                                                                                                                                              diff --git a/doxygen/html/hsa__ext__air_8h_source.html b/doxygen/html/hsa__ext__air_8h_source.html index d6f83a30c3..e17f98e8a8 100644 --- a/doxygen/html/hsa__ext__air_8h_source.html +++ b/doxygen/html/hsa__ext__air_8h_source.html @@ -212,7 +212,7 @@
                                                                                                                                                                              -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:56 for MLIR-AIE by doxygen 1.9.1
                                                                                                                                                                              diff --git a/doxygen/html/index.html b/doxygen/html/index.html index 064f1fc286..f0b5762d9f 100644 --- a/doxygen/html/index.html +++ b/doxygen/html/index.html @@ -57,7 +57,7 @@
                                                                                                                                                                              -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
                                                                                                                                                                              diff --git a/doxygen/html/inherits.html b/doxygen/html/inherits.html index 0afae71032..2a0de4a421 100644 --- a/doxygen/html/inherits.html +++ b/doxygen/html/inherits.html @@ -717,7 +717,7 @@
                                                                                                                                                                              -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
                                                                                                                                                                              diff --git a/doxygen/html/ion_8h.html b/doxygen/html/ion_8h.html index b7faccbe47..9539de84ca 100644 --- a/doxygen/html/ion_8h.html +++ b/doxygen/html/ion_8h.html @@ -268,7 +268,7 @@

                                                                                                                                                                              -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
                                                                                                                                                                              diff --git a/doxygen/html/ion_8h_source.html b/doxygen/html/ion_8h_source.html index c1644706f5..567bfb837c 100644 --- a/doxygen/html/ion_8h_source.html +++ b/doxygen/html/ion_8h_source.html @@ -208,7 +208,7 @@
                                                                                                                                                                              -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:56 for MLIR-AIE by doxygen 1.9.1
                                                                                                                                                                              diff --git a/doxygen/html/memory__allocator_8cpp.html b/doxygen/html/memory__allocator_8cpp.html index 9767b3b929..b62e6946fd 100644 --- a/doxygen/html/memory__allocator_8cpp.html +++ b/doxygen/html/memory__allocator_8cpp.html @@ -251,7 +251,7 @@

                                                                                                                                                                              -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
                                                                                                                                                                              diff --git a/doxygen/html/memory__allocator_8cpp_source.html b/doxygen/html/memory__allocator_8cpp_source.html index 7a0f14b158..ebf52d6cbb 100644 --- a/doxygen/html/memory__allocator_8cpp_source.html +++ b/doxygen/html/memory__allocator_8cpp_source.html @@ -132,7 +132,7 @@
                                                                                                                                                                              -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:56 for MLIR-AIE by doxygen 1.9.1
                                                                                                                                                                              diff --git a/doxygen/html/memory__allocator_8h.html b/doxygen/html/memory__allocator_8h.html index 20e9e6c4c0..2a61da3f01 100644 --- a/doxygen/html/memory__allocator_8h.html +++ b/doxygen/html/memory__allocator_8h.html @@ -304,7 +304,7 @@

                                                                                                                                                                              -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
                                                                                                                                                                              diff --git a/doxygen/html/memory__allocator_8h_source.html b/doxygen/html/memory__allocator_8h_source.html index d70aec4be7..00a59a50ef 100644 --- a/doxygen/html/memory__allocator_8h_source.html +++ b/doxygen/html/memory__allocator_8h_source.html @@ -137,7 +137,7 @@
                                                                                                                                                                              -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:56 for MLIR-AIE by doxygen 1.9.1
                                                                                                                                                                              diff --git a/doxygen/html/memory__allocator__hsa_8cpp.html b/doxygen/html/memory__allocator__hsa_8cpp.html index 67394e4ec4..b7140afb57 100644 --- a/doxygen/html/memory__allocator__hsa_8cpp.html +++ b/doxygen/html/memory__allocator__hsa_8cpp.html @@ -247,7 +247,7 @@

                                                                                                                                                                              -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
                                                                                                                                                                              diff --git a/doxygen/html/memory__allocator__hsa_8cpp_source.html b/doxygen/html/memory__allocator__hsa_8cpp_source.html index 2f468dd41e..90dfe32448 100644 --- a/doxygen/html/memory__allocator__hsa_8cpp_source.html +++ b/doxygen/html/memory__allocator__hsa_8cpp_source.html @@ -172,7 +172,7 @@
                                                                                                                                                                              -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:56 for MLIR-AIE by doxygen 1.9.1
                                                                                                                                                                              diff --git a/doxygen/html/memory__allocator__ion_8cpp.html b/doxygen/html/memory__allocator__ion_8cpp.html index 1c698fd033..06c32896fb 100644 --- a/doxygen/html/memory__allocator__ion_8cpp.html +++ b/doxygen/html/memory__allocator__ion_8cpp.html @@ -317,7 +317,7 @@

                                                                                                                                                                              -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
                                                                                                                                                                              diff --git a/doxygen/html/memory__allocator__ion_8cpp_source.html b/doxygen/html/memory__allocator__ion_8cpp_source.html index ce1a22cf96..9caaa522da 100644 --- a/doxygen/html/memory__allocator__ion_8cpp_source.html +++ b/doxygen/html/memory__allocator__ion_8cpp_source.html @@ -343,7 +343,7 @@
                                                                                                                                                                              -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:56 for MLIR-AIE by doxygen 1.9.1
                                                                                                                                                                              diff --git a/doxygen/html/menudata.js b/doxygen/html/menudata.js index de3acb2e21..2b22659deb 100644 --- a/doxygen/html/menudata.js +++ b/doxygen/html/menudata.js @@ -48,8 +48,7 @@ var menudata={children:[ {text:"t",url:"namespacemembers_t.html#index_t"}, {text:"u",url:"namespacemembers_u.html#index_u"}, {text:"v",url:"namespacemembers_v.html#index_v"}, -{text:"w",url:"namespacemembers_w.html#index_w"}, -{text:"x",url:"namespacemembers_x.html#index_x"}]}, +{text:"w",url:"namespacemembers_w.html#index_w"}]}, {text:"Functions",url:"namespacemembers_func.html",children:[ {text:"a",url:"namespacemembers_func.html#index_a"}, {text:"b",url:"namespacemembers_func.html#index_b"}, @@ -78,8 +77,7 @@ var menudata={children:[ {text:"p",url:"namespacemembers_vars.html#index_p"}, {text:"r",url:"namespacemembers_vars.html#index_r"}, {text:"s",url:"namespacemembers_vars.html#index_s"}, -{text:"u",url:"namespacemembers_vars.html#index_u"}, -{text:"x",url:"namespacemembers_vars.html#index_x"}]}, +{text:"u",url:"namespacemembers_vars.html#index_u"}]}, {text:"Typedefs",url:"namespacemembers_type.html"}, {text:"Enumerations",url:"namespacemembers_enum.html"}, {text:"Enumerator",url:"namespacemembers_eval.html"}]}]}, diff --git a/doxygen/html/namespacellvm.html b/doxygen/html/namespacellvm.html index 990d8d23da..f22e38bace 100644 --- a/doxygen/html/namespacellvm.html +++ b/doxygen/html/namespacellvm.html @@ -115,7 +115,7 @@

                                                                                                                                                                              -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
                                                                                                                                                                              diff --git a/doxygen/html/namespacemembers.html b/doxygen/html/namespacemembers.html index 92b2e43f02..d6559dc74b 100644 --- a/doxygen/html/namespacemembers.html +++ b/doxygen/html/namespacemembers.html @@ -103,7 +103,7 @@

                                                                                                                                                                              - a -

                                                                                                                                                                                -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
                                                                                                                                                                                diff --git a/doxygen/html/namespacemembers_b.html b/doxygen/html/namespacemembers_b.html index 03c19ec64e..8b39ff3bdc 100644 --- a/doxygen/html/namespacemembers_b.html +++ b/doxygen/html/namespacemembers_b.html @@ -73,7 +73,7 @@

                                                                                                                                                                                - b -

                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
                                                                                                                                                                                  diff --git a/doxygen/html/namespacemembers_c.html b/doxygen/html/namespacemembers_c.html index 2ce4be60ab..5ba25048b7 100644 --- a/doxygen/html/namespacemembers_c.html +++ b/doxygen/html/namespacemembers_c.html @@ -202,7 +202,7 @@

                                                                                                                                                                                  - c -

                                                                                                                                                                                    -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
                                                                                                                                                                                    diff --git a/doxygen/html/namespacemembers_d.html b/doxygen/html/namespacemembers_d.html index 7b0aea3785..871310c1c5 100644 --- a/doxygen/html/namespacemembers_d.html +++ b/doxygen/html/namespacemembers_d.html @@ -76,7 +76,7 @@

                                                                                                                                                                                    - d -

                                                                                                                                                                                      -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
                                                                                                                                                                                      diff --git a/doxygen/html/namespacemembers_e.html b/doxygen/html/namespacemembers_e.html index 4334c49026..689119baad 100644 --- a/doxygen/html/namespacemembers_e.html +++ b/doxygen/html/namespacemembers_e.html @@ -64,7 +64,7 @@

                                                                                                                                                                                      - e -

                                                                                                                                                                                        -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
                                                                                                                                                                                        diff --git a/doxygen/html/namespacemembers_enum.html b/doxygen/html/namespacemembers_enum.html index ada33cb6af..649796e76e 100644 --- a/doxygen/html/namespacemembers_enum.html +++ b/doxygen/html/namespacemembers_enum.html @@ -59,7 +59,7 @@
                                                                                                                                                                                        -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
                                                                                                                                                                                        diff --git a/doxygen/html/namespacemembers_eval.html b/doxygen/html/namespacemembers_eval.html index fa09ace65f..347c72a4f7 100644 --- a/doxygen/html/namespacemembers_eval.html +++ b/doxygen/html/namespacemembers_eval.html @@ -89,7 +89,7 @@
                                                                                                                                                                                        -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
                                                                                                                                                                                        diff --git a/doxygen/html/namespacemembers_f.html b/doxygen/html/namespacemembers_f.html index a1dd2c8d41..535ced3589 100644 --- a/doxygen/html/namespacemembers_f.html +++ b/doxygen/html/namespacemembers_f.html @@ -58,7 +58,7 @@

                                                                                                                                                                                        - f -

                                                                                                                                                                                          -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
                                                                                                                                                                                          diff --git a/doxygen/html/namespacemembers_func.html b/doxygen/html/namespacemembers_func.html index e2f03e8b94..0f481c465c 100644 --- a/doxygen/html/namespacemembers_func.html +++ b/doxygen/html/namespacemembers_func.html @@ -76,7 +76,7 @@

                                                                                                                                                                                          - a -

                                                                                                                                                                                            : xilinx::AIE
                                                                                                                                                                                          • AIETranslateToBCF() -: xilinx::AIE +: xilinx::AIE
                                                                                                                                                                                          • AIETranslateToCDODirect() : xilinx::AIE @@ -287,11 +287,8 @@

                                                                                                                                                                                            - f -

                                                                                                                                                                                              - g -

                                                                                                                                                                                                -
                                                                                                                                                                                              • generateDMAConfig() -: xilinx::AIE -
                                                                                                                                                                                              • generateXAieDmaSetMultiDimAddr() -: xilinx::AIE +: xilinx::AIE
                                                                                                                                                                                              • getAllocOpForSymbol() : xilinx::AIE @@ -550,7 +547,7 @@

                                                                                                                                                                                                - w -

                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
                                                                                                                                                                                                  diff --git a/doxygen/html/namespacemembers_g.html b/doxygen/html/namespacemembers_g.html index 2524366a2c..9b87e456cb 100644 --- a/doxygen/html/namespacemembers_g.html +++ b/doxygen/html/namespacemembers_g.html @@ -48,11 +48,8 @@
                                                                                                                                                                                                  Here is a list of all namespace members with links to the namespace documentation for each member:

                                                                                                                                                                                                  - g -

                                                                                                                                                                                                    -
                                                                                                                                                                                                  • generateDMAConfig() -: xilinx::AIE -
                                                                                                                                                                                                  • generateXAieDmaSetMultiDimAddr() -: xilinx::AIE +: xilinx::AIE
                                                                                                                                                                                                  • getAllocOpForSymbol() : xilinx::AIE @@ -112,7 +109,7 @@

                                                                                                                                                                                                    - g -

                                                                                                                                                                                                      -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
                                                                                                                                                                                                      diff --git a/doxygen/html/namespacemembers_h.html b/doxygen/html/namespacemembers_h.html index 0c7740a25d..fac8ec38aa 100644 --- a/doxygen/html/namespacemembers_h.html +++ b/doxygen/html/namespacemembers_h.html @@ -55,7 +55,7 @@

                                                                                                                                                                                                      - h -

                                                                                                                                                                                                        -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
                                                                                                                                                                                                        diff --git a/doxygen/html/namespacemembers_i.html b/doxygen/html/namespacemembers_i.html index 8ff0aefe20..d7fce6e79b 100644 --- a/doxygen/html/namespacemembers_i.html +++ b/doxygen/html/namespacemembers_i.html @@ -70,7 +70,7 @@

                                                                                                                                                                                                        - i -

                                                                                                                                                                                                          -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
                                                                                                                                                                                                          diff --git a/doxygen/html/namespacemembers_l.html b/doxygen/html/namespacemembers_l.html index af8fa0d0d7..0c26289890 100644 --- a/doxygen/html/namespacemembers_l.html +++ b/doxygen/html/namespacemembers_l.html @@ -58,7 +58,7 @@

                                                                                                                                                                                                          - l -

                                                                                                                                                                                                            -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
                                                                                                                                                                                                            diff --git a/doxygen/html/namespacemembers_m.html b/doxygen/html/namespacemembers_m.html index 76345abfa7..cc85a02533 100644 --- a/doxygen/html/namespacemembers_m.html +++ b/doxygen/html/namespacemembers_m.html @@ -64,7 +64,7 @@

                                                                                                                                                                                                            - m -

                                                                                                                                                                                                              -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
                                                                                                                                                                                                              diff --git a/doxygen/html/namespacemembers_n.html b/doxygen/html/namespacemembers_n.html index e0ed4c9684..2c59b6afad 100644 --- a/doxygen/html/namespacemembers_n.html +++ b/doxygen/html/namespacemembers_n.html @@ -55,7 +55,7 @@

                                                                                                                                                                                                              - n -

                                                                                                                                                                                                                -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
                                                                                                                                                                                                                diff --git a/doxygen/html/namespacemembers_o.html b/doxygen/html/namespacemembers_o.html index a14ec63f4e..ca97cf275d 100644 --- a/doxygen/html/namespacemembers_o.html +++ b/doxygen/html/namespacemembers_o.html @@ -71,7 +71,7 @@

                                                                                                                                                                                                                - o -

                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
                                                                                                                                                                                                                  diff --git a/doxygen/html/namespacemembers_p.html b/doxygen/html/namespacemembers_p.html index 3613f5282e..0e4e9d1d41 100644 --- a/doxygen/html/namespacemembers_p.html +++ b/doxygen/html/namespacemembers_p.html @@ -81,12 +81,12 @@

                                                                                                                                                                                                                  - p -

                                                                                                                                                                                                                  • populateAIEVecToLLVMConversionPatterns() : xilinx::aievec
                                                                                                                                                                                                                    • -
                                                                                                                                                                                                                  • port -: xilinx::AIE -
                                                                                                                                                                                                                  • Port : xilinx::AIE
                                                                                                                                                                                                                    • +
                                                                                                                                                                                                                  • port +: xilinx::AIE +
                                                                                                                                                                                                                  • print_matrix() : test_utils
                                                                                                                                                                                                                    • @@ -106,7 +106,7 @@

                                                                                                                                                                                                                    - p -

                                                                                                                                                                                                                      -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
                                                                                                                                                                                                                      diff --git a/doxygen/html/namespacemembers_r.html b/doxygen/html/namespacemembers_r.html index c18909a385..416f95694a 100644 --- a/doxygen/html/namespacemembers_r.html +++ b/doxygen/html/namespacemembers_r.html @@ -118,7 +118,7 @@

                                                                                                                                                                                                                      - r -

                                                                                                                                                                                                                        -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
                                                                                                                                                                                                                        diff --git a/doxygen/html/namespacemembers_s.html b/doxygen/html/namespacemembers_s.html index fe01ec5dd8..299d156248 100644 --- a/doxygen/html/namespacemembers_s.html +++ b/doxygen/html/namespacemembers_s.html @@ -127,7 +127,7 @@

                                                                                                                                                                                                                        - s -

                                                                                                                                                                                                                          -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
                                                                                                                                                                                                                                  diff --git a/doxygen/html/namespacexilinx_1_1AIE.html b/doxygen/html/namespacexilinx_1_1AIE.html index 7ede7d15c7..2f67bf1732 100644 --- a/doxygen/html/namespacexilinx_1_1AIE.html +++ b/doxygen/html/namespacexilinx_1_1AIE.html @@ -421,11 +421,6 @@   llvm::SetVector< Block * > getOrderedChainOfBlocks (Region *region)   -template<typename OpType > -mlir::LogicalResult generateDMAConfig (OpType memOp, raw_ostream &output, const AIETargetModel &targetModel, DenseMap< Block *, int > blockMap) -  -mlir::LogicalResult AIETranslateToXAIEV2 (ModuleOp module, raw_ostream &output) -  @@ -499,8 +494,6 @@ - -

                                                                                                                                                                                                                                  Variables

                                                                                                                                                                                                                                   
                                                                                                                                                                                                                                  const char * hsa_cpp_file_header
                                                                                                                                                                                                                                   
                                                                                                                                                                                                                                  const char * xaie_cpp_file_header
                                                                                                                                                                                                                                   

                                                                                                                                                                                                                                  Detailed Description

                                                                                                                                                                                                                                  Include the generated interface declarations.

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                                                                                                                                                                                                                                  ◆ AIETranslateToXAIEV2() [1/2]

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                                                                                                                                                                                                                                  ◆ AIETranslateToXAIEV2()

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                                                                                                                                                                                                                                  ◆ AIETranslateToXAIEV2() [2/2]

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                                                                                                                                                                                                                                  mlir::LogicalResult xilinx::AIE::AIETranslateToXAIEV2 (ModuleOp module,
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                                                                                                                                                                                                                                  Definition at line 297 of file AIETargetXAIEV2.cpp.

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                                                                                                                                                                                                                                  References collectBuffers(), collectTiles(), and xaie_cpp_file_header.

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                                                                                                                                                                                                                                  Referenced by AIETranslateToBCF(), AIETranslateToHSA(), AIETranslateToXAIEV2(), and registerAIETranslations().

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                                                                                                                                                                                                                                  Referenced by AIETranslateToBCF(), AIETranslateToHSA(), and registerAIETranslations().

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                                                                                                                                                                                                                                  Referenced by AIETranslateToBCF(), AIETranslateToHSA(), AIETranslateToXAIEV2(), and registerAIETranslations().

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                                                                                                                                                                                                                                  Referenced by AIETranslateToBCF(), AIETranslateToHSA(), and registerAIETranslations().

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                                                                                                                                                                                                                                  Definition at line 522 of file AIEToConfiguration.cpp.

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                                                                                                                                                                                                                                  ◆ generateDMAConfig()

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                                                                                                                                                                                                                                  mlir::LogicalResult xilinx::AIE::generateDMAConfig (OpType memOp,
                                                                                                                                                                                                                                  raw_ostream & output,
                                                                                                                                                                                                                                  const AIETargetModel & targetModel,
                                                                                                                                                                                                                                  DenseMap< Block *, int > blockMap 
                                                                                                                                                                                                                                  )
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                                                                                                                                                                                                                                  Definition at line 76 of file AIETargetXAIEV2.cpp.

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                                                                                                                                                                                                                                  References col, generateXAieDmaSetMultiDimAddr(), xilinx::AIE::AIETargetModel::getMemTileSize(), xilinx::AIE::AIETargetModel::getNumLocks(), getOrderedChainOfBlocks(), getTargetModel(), xilinx::AIE::AIETargetModel::hasProperty(), xilinx::AIE::AIETargetModel::isEast(), xilinx::AIE::AIETargetModel::isInternal(), xilinx::AIE::AIETargetModel::isMemTile(), xilinx::AIE::AIETargetModel::isShimNOCTile(), xilinx::AIE::AIETargetModel::isWest(), packetStr(), row, tileDMAInstRefStr(), tileDMAInstStr(), tileLocStr(), and utohexstr().

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                                                                                                                                                                                                                                  Referenced by generateDMAConfig().

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                                                                                                                                                                                                                                  Referenced by xilinx::AIE::AIERTControl::addInitConfig(), and generateDMAConfig().

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                                                                                                                                                                                                                                  Referenced by xilinx::AIE::AIERTControl::addInitConfig().

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                                                                                                                                                                                                                                  -

                                                                                                                                                                                                                                  Referenced by AIETranslateToBCF(), basicAllocation(), generateDMAConfig(), DMAChannelAnalysis::getDMAChannelIndex(), AIEAssignRuntimeSequenceBDIDsPass::getGeneratorForTile(), LockAnalysis::getLockID(), xilinx::AIEX::TokenAnalysis::getShareableTileOp(), AIEObjectFifoStatefulTransformPass::isSharedMemory(), AIEDMATasksToNPUPass::rewriteSingleBD(), AIELocalizeLocksPass::runOnOperation(), AIEDMATasksToNPUPass::setAddressForSingleBD(), simpleBankAwareAllocation(), and xilinx::AIEX::verifyStridesWraps().

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                                                                                                                                                                                                                                  Referenced by AIETranslateToBCF(), basicAllocation(), DMAChannelAnalysis::getDMAChannelIndex(), AIEAssignRuntimeSequenceBDIDsPass::getGeneratorForTile(), LockAnalysis::getLockID(), xilinx::AIEX::TokenAnalysis::getShareableTileOp(), AIEObjectFifoStatefulTransformPass::isSharedMemory(), AIEDMATasksToNPUPass::rewriteSingleBD(), AIELocalizeLocksPass::runOnOperation(), AIEDMATasksToNPUPass::setAddressForSingleBD(), simpleBankAwareAllocation(), and xilinx::AIEX::verifyStridesWraps().

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                                                                                                                                                                                                                                  Referenced by generateDMAConfig().

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                                                                                                                                                                                                                                  Referenced by generateDMAConfig().

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                                                                                                                                                                                                                                  -

                                                                                                                                                                                                                                  Referenced by generateDMAConfig().

                                                                                                                                                                                                                                  - @@ -3790,8 +3697,6 @@

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                                                                                                                                                                                                                                  Referenced by generateDMAConfig().

                                                                                                                                                                                                                                  - @@ -4012,7 +3917,7 @@

                                                                                                                                                                                                                                  Definition at line 52 of file AIETargetModel.h.

                                                                                                                                                                                                                                  -

                                                                                                                                                                                                                                  Referenced by xilinx::AIE::AIERTControl::addAieElf(), xilinx::AIE::AIERTControl::addAieElfs(), xilinx::AIE::Pathfinder::addFixedConnection(), xilinx::AIE::AIERTControl::addInitConfig(), AIETranslateGraphXPE(), AIETranslateShimSolution(), AIETranslateToHSA(), xilinx::AIE::AIERTControl::configureSwitches(), xilinx::AIE::AIERTControl::dmaUpdateBdAddr(), generateDMAConfig(), AIEGenerateColumnControlOverlayPass::generatePacketFlowsForControl(), xilinx::AIEX::getBufferDescriptorAddressRegisterAddress(), getNextCoords(), xilinx::AIE::AIE2TargetModel::getNumBanks(), xilinx::AIE::AIE2TargetModel::getNumBDs(), xilinx::AIE::AIE1TargetModel::getNumDestShimMuxConnections(), xilinx::AIE::AIE2TargetModel::getNumDestShimMuxConnections(), xilinx::AIE::AIE1TargetModel::getNumDestSwitchboxConnections(), xilinx::AIE::AIE2TargetModel::getNumDestSwitchboxConnections(), xilinx::AIE::AIE2TargetModel::getNumLocks(), xilinx::AIE::AIE1TargetModel::getNumSourceShimMuxConnections(), xilinx::AIE::AIE2TargetModel::getNumSourceShimMuxConnections(), xilinx::AIE::AIE1TargetModel::getNumSourceSwitchboxConnections(), xilinx::AIE::AIE2TargetModel::getNumSourceSwitchboxConnections(), xilinx::AIE::DynamicTileAnalysis::getShimMux(), xilinx::AIE::DynamicTileAnalysis::getSwitchbox(), xilinx::AIE::DynamicTileAnalysis::getTile(), getTileToControllerIdMap(), getTileToControllerIdMap6RowsOrLess(), xilinx::AIE::Pathfinder::initialize(), xilinx::AIE::AIE2TargetModel::isBdChannelAccessible(), xilinx::AIE::AIE1TargetModel::isLegalTileConnection(), xilinx::AIE::AIE2TargetModel::isLegalTileConnection(), xilinx::AIE::VC1902TargetModel::isShimNOCorPLTile(), xilinx::AIE::VE2302TargetModel::isShimNOCorPLTile(), xilinx::AIE::VE2802TargetModel::isShimNOCorPLTile(), xilinx::AIE::BaseNPUTargetModel::isShimNOCorPLTile(), xilinx::AIE::VC1902TargetModel::isShimNOCTile(), xilinx::AIE::VE2302TargetModel::isShimNOCTile(), xilinx::AIE::VE2802TargetModel::isShimNOCTile(), xilinx::AIE::NPUTargetModel::isShimNOCTile(), xilinx::AIE::VC1902TargetModel::isShimPLTile(), xilinx::AIE::VE2302TargetModel::isShimPLTile(), xilinx::AIE::VE2802TargetModel::isShimPLTile(), xilinx::AIE::NPUTargetModel::isShimPLTile(), AIEBufferToStandard::matchAndRewrite(), AIECoreToStandardFunc::matchAndRewrite(), DMAStartBdChainForOpPattern::matchAndRewrite(), mlir_aie_acquire_lock(), mlir_aie_clear_config(), mlir_aie_clear_shim_config(), mlir_aie_clear_tile_memory(), mlir_aie_data_mem_rd_word(), mlir_aie_data_mem_wr_word(), mlir_aie_dump_tile_memory(), mlir_aie_get_tile_addr(), mlir_aie_print_dma_status(), mlir_aie_print_memtiledma_status(), mlir_aie_print_shimdma_status(), mlir_aie_print_tile_status(), mlir_aie_release_lock(), operator<(), operator==(), print_aie2_lock_status(), test_utils::print_matrix(), xilinx::AIE::DynamicTileAnalysis::runAnalysis(), xilinx::AIE::AIEPathfinderPass::runOnOperation(), AIEAssignBufferDescriptorIDsPass::runOnOperation(), AIEAssignTileCtrlIDsPass::runOnOperation(), AIEGenerateColumnControlOverlayPass::runOnOperation(), AIELocalizeLocksPass::runOnOperation(), AIECtrlPacketToDmaPass::runOnOperation(), xilinx::AIE::AIEPathfinderPass::runOnPacketFlow(), tileDMAInstRefStr(), tileDMAInstStr(), tileLocStr(), and translateSwitchboxes().

                                                                                                                                                                                                                                  +

                                                                                                                                                                                                                                  Referenced by xilinx::AIE::AIERTControl::addAieElf(), xilinx::AIE::AIERTControl::addAieElfs(), xilinx::AIE::Pathfinder::addFixedConnection(), xilinx::AIE::AIERTControl::addInitConfig(), AIETranslateGraphXPE(), AIETranslateShimSolution(), AIETranslateToHSA(), xilinx::AIE::AIERTControl::configureSwitches(), xilinx::AIE::AIERTControl::dmaUpdateBdAddr(), AIEGenerateColumnControlOverlayPass::generatePacketFlowsForControl(), xilinx::AIEX::getBufferDescriptorAddressRegisterAddress(), getNextCoords(), xilinx::AIE::AIE2TargetModel::getNumBanks(), xilinx::AIE::AIE2TargetModel::getNumBDs(), xilinx::AIE::AIE1TargetModel::getNumDestShimMuxConnections(), xilinx::AIE::AIE2TargetModel::getNumDestShimMuxConnections(), xilinx::AIE::AIE1TargetModel::getNumDestSwitchboxConnections(), xilinx::AIE::AIE2TargetModel::getNumDestSwitchboxConnections(), xilinx::AIE::AIE2TargetModel::getNumLocks(), xilinx::AIE::AIE1TargetModel::getNumSourceShimMuxConnections(), xilinx::AIE::AIE2TargetModel::getNumSourceShimMuxConnections(), xilinx::AIE::AIE1TargetModel::getNumSourceSwitchboxConnections(), xilinx::AIE::AIE2TargetModel::getNumSourceSwitchboxConnections(), xilinx::AIE::DynamicTileAnalysis::getShimMux(), xilinx::AIE::DynamicTileAnalysis::getSwitchbox(), xilinx::AIE::DynamicTileAnalysis::getTile(), getTileToControllerIdMap(), getTileToControllerIdMap6RowsOrLess(), xilinx::AIE::Pathfinder::initialize(), xilinx::AIE::AIE2TargetModel::isBdChannelAccessible(), xilinx::AIE::AIE1TargetModel::isLegalTileConnection(), xilinx::AIE::AIE2TargetModel::isLegalTileConnection(), xilinx::AIE::VC1902TargetModel::isShimNOCorPLTile(), xilinx::AIE::VE2302TargetModel::isShimNOCorPLTile(), xilinx::AIE::VE2802TargetModel::isShimNOCorPLTile(), xilinx::AIE::BaseNPUTargetModel::isShimNOCorPLTile(), xilinx::AIE::VC1902TargetModel::isShimNOCTile(), xilinx::AIE::VE2302TargetModel::isShimNOCTile(), xilinx::AIE::VE2802TargetModel::isShimNOCTile(), xilinx::AIE::NPUTargetModel::isShimNOCTile(), xilinx::AIE::VC1902TargetModel::isShimPLTile(), xilinx::AIE::VE2302TargetModel::isShimPLTile(), xilinx::AIE::VE2802TargetModel::isShimPLTile(), xilinx::AIE::NPUTargetModel::isShimPLTile(), AIEBufferToStandard::matchAndRewrite(), AIECoreToStandardFunc::matchAndRewrite(), DMAStartBdChainForOpPattern::matchAndRewrite(), mlir_aie_acquire_lock(), mlir_aie_clear_config(), mlir_aie_clear_shim_config(), mlir_aie_clear_tile_memory(), mlir_aie_data_mem_rd_word(), mlir_aie_data_mem_wr_word(), mlir_aie_dump_tile_memory(), mlir_aie_get_tile_addr(), mlir_aie_print_dma_status(), mlir_aie_print_memtiledma_status(), mlir_aie_print_shimdma_status(), mlir_aie_print_tile_status(), mlir_aie_release_lock(), operator<(), operator==(), print_aie2_lock_status(), test_utils::print_matrix(), xilinx::AIE::DynamicTileAnalysis::runAnalysis(), xilinx::AIE::AIEPathfinderPass::runOnOperation(), AIEAssignBufferDescriptorIDsPass::runOnOperation(), AIEAssignTileCtrlIDsPass::runOnOperation(), AIEGenerateColumnControlOverlayPass::runOnOperation(), AIELocalizeLocksPass::runOnOperation(), AIECtrlPacketToDmaPass::runOnOperation(), xilinx::AIE::AIEPathfinderPass::runOnPacketFlow(), tileDMAInstRefStr(), tileDMAInstStr(), tileLocStr(), and translateSwitchboxes().

                                                                                                                                                                                                                                  @@ -4570,7 +4475,7 @@

                                                                                                                                                                                                                                  Definition at line 52 of file AIETargetModel.h.

                                                                                                                                                                                                                                  -

                                                                                                                                                                                                                                  Referenced by xilinx::AIE::AIERTControl::addAieElf(), xilinx::AIE::AIERTControl::addAieElfs(), xilinx::AIE::Pathfinder::addFixedConnection(), xilinx::AIE::AIERTControl::addInitConfig(), AIETranslateGraphXPE(), xilinx::AIE::TileAddress::clearRange(), xilinx::AIE::AIERTControl::configureSwitches(), xilinx::AIE::AIERTControl::dmaUpdateBdAddr(), generateDMAConfig(), xilinx::AIEX::getBufferDescriptorAddressRegisterAddress(), getNextCoords(), xilinx::AIE::AIE2TargetModel::getNumBanks(), xilinx::AIE::AIE2TargetModel::getNumBDs(), xilinx::AIE::AIE1TargetModel::getNumDestShimMuxConnections(), xilinx::AIE::AIE2TargetModel::getNumDestShimMuxConnections(), xilinx::AIE::AIE1TargetModel::getNumDestSwitchboxConnections(), xilinx::AIE::AIE2TargetModel::getNumDestSwitchboxConnections(), xilinx::AIE::AIE2TargetModel::getNumLocks(), xilinx::AIE::AIE1TargetModel::getNumSourceShimMuxConnections(), xilinx::AIE::AIE2TargetModel::getNumSourceShimMuxConnections(), xilinx::AIE::AIE1TargetModel::getNumSourceSwitchboxConnections(), xilinx::AIE::AIE2TargetModel::getNumSourceSwitchboxConnections(), xilinx::AIE::DynamicTileAnalysis::getShimMux(), xilinx::AIE::DynamicTileAnalysis::getSwitchbox(), xilinx::AIE::DynamicTileAnalysis::getTile(), getTileToControllerIdMap(), getTileToControllerIdMap6RowsOrLess(), xilinx::AIE::Pathfinder::initialize(), xilinx::AIE::AIE2TargetModel::isBdChannelAccessible(), xilinx::AIE::AIE1TargetModel::isCoreTile(), xilinx::AIE::VE2302TargetModel::isCoreTile(), xilinx::AIE::VE2802TargetModel::isCoreTile(), xilinx::AIE::BaseNPUTargetModel::isCoreTile(), xilinx::AIE::AIE1TargetModel::isLegalTileConnection(), xilinx::AIE::AIE2TargetModel::isLegalTileConnection(), xilinx::AIE::VE2302TargetModel::isMemTile(), xilinx::AIE::VE2802TargetModel::isMemTile(), xilinx::AIE::BaseNPUTargetModel::isMemTile(), xilinx::AIE::TileAddress::isShim(), xilinx::AIE::VC1902TargetModel::isShimNOCorPLTile(), xilinx::AIE::VE2302TargetModel::isShimNOCorPLTile(), xilinx::AIE::VE2802TargetModel::isShimNOCorPLTile(), xilinx::AIE::BaseNPUTargetModel::isShimNOCorPLTile(), xilinx::AIE::VC1902TargetModel::isShimNOCTile(), xilinx::AIE::VE2302TargetModel::isShimNOCTile(), xilinx::AIE::VE2802TargetModel::isShimNOCTile(), xilinx::AIE::NPUTargetModel::isShimNOCTile(), xilinx::AIE::VirtualizedNPUTargetModel::isShimNOCTile(), xilinx::AIE::NPU2TargetModel::isShimNOCTile(), xilinx::AIE::VC1902TargetModel::isShimPLTile(), xilinx::AIE::VE2302TargetModel::isShimPLTile(), xilinx::AIE::VE2802TargetModel::isShimPLTile(), xilinx::AIE::NPUTargetModel::isShimPLTile(), AIEBufferToStandard::matchAndRewrite(), AIECoreToStandardFunc::matchAndRewrite(), mlir_aie_acquire_lock(), mlir_aie_clear_config(), mlir_aie_clear_shim_config(), mlir_aie_clear_tile_memory(), mlir_aie_data_mem_rd_word(), mlir_aie_data_mem_wr_word(), mlir_aie_dump_tile_memory(), mlir_aie_get_tile_addr(), mlir_aie_print_dma_status(), mlir_aie_print_memtiledma_status(), mlir_aie_print_shimdma_status(), mlir_aie_print_tile_status(), mlir_aie_release_lock(), operator<(), operator==(), print_aie2_lock_status(), test_utils::print_matrix(), xilinx::AIE::DynamicTileAnalysis::runAnalysis(), xilinx::AIE::AIEPathfinderPass::runOnOperation(), AIEAssignBufferDescriptorIDsPass::runOnOperation(), AIELocalizeLocksPass::runOnOperation(), AIECtrlPacketToDmaPass::runOnOperation(), xilinx::AIE::AIEPathfinderPass::runOnPacketFlow(), tileDMAInstRefStr(), tileDMAInstStr(), tileLocStr(), and translateSwitchboxes().

                                                                                                                                                                                                                                  +

                                                                                                                                                                                                                                  Referenced by xilinx::AIE::AIERTControl::addAieElf(), xilinx::AIE::AIERTControl::addAieElfs(), xilinx::AIE::Pathfinder::addFixedConnection(), xilinx::AIE::AIERTControl::addInitConfig(), AIETranslateGraphXPE(), xilinx::AIE::TileAddress::clearRange(), xilinx::AIE::AIERTControl::configureSwitches(), xilinx::AIE::AIERTControl::dmaUpdateBdAddr(), xilinx::AIEX::getBufferDescriptorAddressRegisterAddress(), getNextCoords(), xilinx::AIE::AIE2TargetModel::getNumBanks(), xilinx::AIE::AIE2TargetModel::getNumBDs(), xilinx::AIE::AIE1TargetModel::getNumDestShimMuxConnections(), xilinx::AIE::AIE2TargetModel::getNumDestShimMuxConnections(), xilinx::AIE::AIE1TargetModel::getNumDestSwitchboxConnections(), xilinx::AIE::AIE2TargetModel::getNumDestSwitchboxConnections(), xilinx::AIE::AIE2TargetModel::getNumLocks(), xilinx::AIE::AIE1TargetModel::getNumSourceShimMuxConnections(), xilinx::AIE::AIE2TargetModel::getNumSourceShimMuxConnections(), xilinx::AIE::AIE1TargetModel::getNumSourceSwitchboxConnections(), xilinx::AIE::AIE2TargetModel::getNumSourceSwitchboxConnections(), xilinx::AIE::DynamicTileAnalysis::getShimMux(), xilinx::AIE::DynamicTileAnalysis::getSwitchbox(), xilinx::AIE::DynamicTileAnalysis::getTile(), getTileToControllerIdMap(), getTileToControllerIdMap6RowsOrLess(), xilinx::AIE::Pathfinder::initialize(), xilinx::AIE::AIE2TargetModel::isBdChannelAccessible(), xilinx::AIE::AIE1TargetModel::isCoreTile(), xilinx::AIE::VE2302TargetModel::isCoreTile(), xilinx::AIE::VE2802TargetModel::isCoreTile(), xilinx::AIE::BaseNPUTargetModel::isCoreTile(), xilinx::AIE::AIE1TargetModel::isLegalTileConnection(), xilinx::AIE::AIE2TargetModel::isLegalTileConnection(), xilinx::AIE::VE2302TargetModel::isMemTile(), xilinx::AIE::VE2802TargetModel::isMemTile(), xilinx::AIE::BaseNPUTargetModel::isMemTile(), xilinx::AIE::TileAddress::isShim(), xilinx::AIE::VC1902TargetModel::isShimNOCorPLTile(), xilinx::AIE::VE2302TargetModel::isShimNOCorPLTile(), xilinx::AIE::VE2802TargetModel::isShimNOCorPLTile(), xilinx::AIE::BaseNPUTargetModel::isShimNOCorPLTile(), xilinx::AIE::VC1902TargetModel::isShimNOCTile(), xilinx::AIE::VE2302TargetModel::isShimNOCTile(), xilinx::AIE::VE2802TargetModel::isShimNOCTile(), xilinx::AIE::NPUTargetModel::isShimNOCTile(), xilinx::AIE::VirtualizedNPUTargetModel::isShimNOCTile(), xilinx::AIE::NPU2TargetModel::isShimNOCTile(), xilinx::AIE::VC1902TargetModel::isShimPLTile(), xilinx::AIE::VE2302TargetModel::isShimPLTile(), xilinx::AIE::VE2802TargetModel::isShimPLTile(), xilinx::AIE::NPUTargetModel::isShimPLTile(), AIEBufferToStandard::matchAndRewrite(), AIECoreToStandardFunc::matchAndRewrite(), mlir_aie_acquire_lock(), mlir_aie_clear_config(), mlir_aie_clear_shim_config(), mlir_aie_clear_tile_memory(), mlir_aie_data_mem_rd_word(), mlir_aie_data_mem_wr_word(), mlir_aie_dump_tile_memory(), mlir_aie_get_tile_addr(), mlir_aie_print_dma_status(), mlir_aie_print_memtiledma_status(), mlir_aie_print_shimdma_status(), mlir_aie_print_tile_status(), mlir_aie_release_lock(), operator<(), operator==(), print_aie2_lock_status(), test_utils::print_matrix(), xilinx::AIE::DynamicTileAnalysis::runAnalysis(), xilinx::AIE::AIEPathfinderPass::runOnOperation(), AIEAssignBufferDescriptorIDsPass::runOnOperation(), AIELocalizeLocksPass::runOnOperation(), AIECtrlPacketToDmaPass::runOnOperation(), xilinx::AIE::AIEPathfinderPass::runOnPacketFlow(), tileDMAInstRefStr(), tileDMAInstStr(), tileLocStr(), and translateSwitchboxes().

                                                                                                                                                                                                                                  @@ -4662,60 +4567,12 @@

                                                                                                                                                                                                                                  Referenced by bumpDemand(), resize(), and updateDemand().

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                                                                                                                                                                                                                                  ◆ xaie_cpp_file_header

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                                                                                                                                                                                                                                  const char* xilinx::AIE::xaie_cpp_file_header
                                                                                                                                                                                                                                  -
                                                                                                                                                                                                                                  -Initial value:
                                                                                                                                                                                                                                  = R"code(
                                                                                                                                                                                                                                  -
                                                                                                                                                                                                                                  // This file was auto-generated by aiecc.py --aie-generate-xaie.
                                                                                                                                                                                                                                  -
                                                                                                                                                                                                                                  -
                                                                                                                                                                                                                                  #ifndef MLIR_AIE_QUIET
                                                                                                                                                                                                                                  -
                                                                                                                                                                                                                                  #define __mlir_aie_verbose(x) x
                                                                                                                                                                                                                                  -
                                                                                                                                                                                                                                  #else
                                                                                                                                                                                                                                  -
                                                                                                                                                                                                                                  #define __mlir_aie_verbose(x)
                                                                                                                                                                                                                                  -
                                                                                                                                                                                                                                  #endif
                                                                                                                                                                                                                                  -
                                                                                                                                                                                                                                  -
                                                                                                                                                                                                                                  // The following is a wrapper for the common "if(call() != 0) return 1" pattern.
                                                                                                                                                                                                                                  -
                                                                                                                                                                                                                                  // Use this only in functions that return int. If the call this wrapper is used
                                                                                                                                                                                                                                  -
                                                                                                                                                                                                                                  // on does not succeed, the expanded code will exit out of the function
                                                                                                                                                                                                                                  -
                                                                                                                                                                                                                                  // containing this macro with an error code.
                                                                                                                                                                                                                                  -
                                                                                                                                                                                                                                  #define __mlir_aie_try(x) do { \
                                                                                                                                                                                                                                  -
                                                                                                                                                                                                                                  AieRC ret = (x); \
                                                                                                                                                                                                                                  -
                                                                                                                                                                                                                                  if(ret != XAIE_OK) { \
                                                                                                                                                                                                                                  -
                                                                                                                                                                                                                                  return x; \
                                                                                                                                                                                                                                  -
                                                                                                                                                                                                                                  } \
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                                                                                                                                                                                                                                  } while(0)
                                                                                                                                                                                                                                  -
                                                                                                                                                                                                                                  -
                                                                                                                                                                                                                                  static XAie_DmaDimDesc *__mlir_aie_alloc_dim_desc(size_t ndims) {
                                                                                                                                                                                                                                  -
                                                                                                                                                                                                                                  XAie_DmaDimDesc *ret = NULL;
                                                                                                                                                                                                                                  -
                                                                                                                                                                                                                                  ret = (XAie_DmaDimDesc *)calloc(sizeof(XAie_DmaDimDesc), ndims);
                                                                                                                                                                                                                                  -
                                                                                                                                                                                                                                  if(NULL == ret) {
                                                                                                                                                                                                                                  -
                                                                                                                                                                                                                                  __mlir_aie_verbose(fprintf(stderr, "Allocating DmaDimDesc failed.\n"));
                                                                                                                                                                                                                                  -
                                                                                                                                                                                                                                  }
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                                                                                                                                                                                                                                  return ret;
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                                                                                                                                                                                                                                  }
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                                                                                                                                                                                                                                  -
                                                                                                                                                                                                                                  )code"
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                                                                                                                                                                                                                                  Definition at line 33 of file AIETargetXAIEV2.cpp.

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                                                                                                                                                                                                                                  Referenced by AIETranslateToXAIEV2().

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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
                                                                                                                                                                                                                                  diff --git a/doxygen/html/namespacexilinx_1_1AIEX.html b/doxygen/html/namespacexilinx_1_1AIEX.html index 3b8d3a7a71..2bf009019f 100644 --- a/doxygen/html/namespacexilinx_1_1AIEX.html +++ b/doxygen/html/namespacexilinx_1_1AIEX.html @@ -549,7 +549,7 @@

                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
                                                                                                                                                                                                                                  diff --git a/doxygen/html/namespacexilinx_1_1AIE_1_1detail.html b/doxygen/html/namespacexilinx_1_1AIE_1_1detail.html index 9b4e329e34..71a6b8d2e7 100644 --- a/doxygen/html/namespacexilinx_1_1AIE_1_1detail.html +++ b/doxygen/html/namespacexilinx_1_1AIE_1_1detail.html @@ -68,7 +68,7 @@
                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
                                                                                                                                                                                                                                  diff --git a/doxygen/html/namespacexilinx_1_1aievec.html b/doxygen/html/namespacexilinx_1_1aievec.html index bfefb97473..1d90e190e3 100644 --- a/doxygen/html/namespacexilinx_1_1aievec.html +++ b/doxygen/html/namespacexilinx_1_1aievec.html @@ -1579,7 +1579,7 @@

                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
                                                                                                                                                                                                                                  diff --git a/doxygen/html/pages.html b/doxygen/html/pages.html index 6945eed76a..6909c5ec5f 100644 --- a/doxygen/html/pages.html +++ b/doxygen/html/pages.html @@ -57,7 +57,7 @@
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
                                                                                                                                                                                                                                  diff --git a/doxygen/html/structAIEMaterializeBDChainsPass-members.html b/doxygen/html/structAIEMaterializeBDChainsPass-members.html index 905d1e9b69..5374c6904d 100644 --- a/doxygen/html/structAIEMaterializeBDChainsPass-members.html +++ b/doxygen/html/structAIEMaterializeBDChainsPass-members.html @@ -56,7 +56,7 @@
                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
                                                                                                                                                                                                                                  diff --git a/doxygen/html/structAIEMaterializeBDChainsPass.html b/doxygen/html/structAIEMaterializeBDChainsPass.html index a4bbbd37f7..597a1f118b 100644 --- a/doxygen/html/structAIEMaterializeBDChainsPass.html +++ b/doxygen/html/structAIEMaterializeBDChainsPass.html @@ -117,7 +117,7 @@

                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
                                                                                                                                                                                                                                  diff --git a/doxygen/html/structAIEPutCascadeToStdLowering-members.html b/doxygen/html/structAIEPutCascadeToStdLowering-members.html index 10187c12e4..d0e11d5a62 100644 --- a/doxygen/html/structAIEPutCascadeToStdLowering-members.html +++ b/doxygen/html/structAIEPutCascadeToStdLowering-members.html @@ -58,7 +58,7 @@
                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
                                                                                                                                                                                                                                  diff --git a/doxygen/html/structConvertVectorFMAOpToAIEVecFMAElemOpPattern-members.html b/doxygen/html/structConvertVectorFMAOpToAIEVecFMAElemOpPattern-members.html index af644751d6..2e55e24ffd 100644 --- a/doxygen/html/structConvertVectorFMAOpToAIEVecFMAElemOpPattern-members.html +++ b/doxygen/html/structConvertVectorFMAOpToAIEVecFMAElemOpPattern-members.html @@ -58,7 +58,7 @@
                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
                                                                                                                                                                                                                                  diff --git a/doxygen/html/structLowerVectorSelectOpToAIEVecSelOp-members.html b/doxygen/html/structLowerVectorSelectOpToAIEVecSelOp-members.html index 632a06766e..69a729f50e 100644 --- a/doxygen/html/structLowerVectorSelectOpToAIEVecSelOp-members.html +++ b/doxygen/html/structLowerVectorSelectOpToAIEVecSelOp-members.html @@ -56,7 +56,7 @@
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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                                                                                                                                                                                                                                  -Generated on Fri Jan 10 2025 11:12:32 for MLIR-AIE by doxygen 1.9.1 +Generated on Fri Jan 10 2025 20:31:57 for MLIR-AIE by doxygen 1.9.1
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