diff --git a/docs/AIEDesignPatterns.md b/docs/AIEDesignPatterns.md index 6838440a29..f79c41edf7 100644 --- a/docs/AIEDesignPatterns.md +++ b/docs/AIEDesignPatterns.md @@ -11,19 +11,19 @@ We can use the AIE Cores as below to perform some operations Define a tile and a buffer ``` -%tile13 = AIE.tile(1, 3) -%buf13_0 = AIE.buffer(%tile13) { sym_name = "a" } : memref<256xi32> +%tile13 = aie.tile(1, 3) +%buf13_0 = aie.buffer(%tile13) { sym_name = "a" } : memref<256xi32> ``` Perform some operations on the buffer in the core ``` -%core13 = AIE.core(%tile13) { +%core13 = aie.core(%tile13) { %val1 = constant 7 : i32 %idx1 = constant 3 : index %2 = addi %val1, %val1 : i32 memref.store %2, %buf13_0[%idx1] : memref<256xi32> - AIE.end + aie.end } @@ -35,52 +35,52 @@ Perform some operations on the buffer in the core Define the AIE tiles you want to communicate between. Here Tile (7,1) will be the source and (7,2) the destination. ``` -%t71 = AIE.tile(7, 1) // (Column, Row) -%t72 = AIE.tile(7, 2) +%t71 = aie.tile(7, 1) // (Column, Row) +%t72 = aie.tile(7, 2) ``` Set up switchboxes to connect the stream to DMA ``` -%sw71 = AIE.switchbox(%t71) { - AIE.connect<"DMA" : 0, "North" : 3> +%sw71 = aie.switchbox(%t71) { + aie.connect<"DMA" : 0, "North" : 3> } -%sw72 = AIE.switchbox(%t72) { - AIE.connect<"South" : 3, "DMA" : 0> +%sw72 = aie.switchbox(%t72) { + aie.connect<"South" : 3, "DMA" : 0> } ``` Define the locks and buffers ``` -%lock71 = AIE.lock(%t71, 0) // Tile, Lock Number (0-15) -%lock72 = AIE.lock(%t72, 0) +%lock71 = aie.lock(%t71, 0) // Tile, Lock Number (0-15) +%lock72 = aie.lock(%t72, 0) -%buf71 = AIE.buffer(%t71) { sym_name = "a71" } : memref<512xi32> -%buf72 = AIE.buffer(%t72) { sym_name = "a72" } : memref<512xi32> +%buf71 = aie.buffer(%t71) { sym_name = "a71" } : memref<512xi32> +%buf72 = aie.buffer(%t72) { sym_name = "a72" } : memref<512xi32> ``` Start the Memory Map to Stream DMA from the source: ``` -%mem71 = AIE.mem(%tile71) { - %dma0 = AIE.dma_start("MM2S", 0, ^bd0, ^end) +%mem71 = aie.mem(%tile71) { + %dma0 = aie.dma_start("MM2S", 0, ^bd0, ^end) ^bd0: - AIE.use_lock(%lock71, "Acquire", 0) // Acquire in State 0 - AIE.dma_bd(%buf71 : memref<512xi32>, 0, 512) - AIE.use_lock(%lock71, "Release", 1) // Release in State 1 + aie.use_lock(%lock71, "Acquire", 0) // Acquire in State 0 + aie.dma_bd(%buf71 : memref<512xi32>) { offset = 0 : i32, len = 512 : i32 } + aie.use_lock(%lock71, "Release", 1) // Release in State 1 br ^end ^end: - AIE.end + aie.end } ``` Start the Stream to Memory Map DMA from the destination: ``` -%mem72 = AIE.mem(%tile72) { - %dma0 = AIE.dma_start("S2MM", 0, ^bd0, ^end) +%mem72 = aie.mem(%tile72) { + %dma0 = aie.dma_start("S2MM", 0, ^bd0, ^end) ^bd0: - AIE.use_lock(%lock72, "Acquire", 0) - AIE.dma_bd(%buf72 : memref<512xi32>, 0, 512) - AIE.use_lock(%lock72, "Release", 1) + aie.use_lock(%lock72, "Acquire", 0) + aie.dma_bd(%buf72 : memref<512xi32>) { offset = 0 : i32, len = 512 : i32 } + aie.use_lock(%lock72, "Release", 1) br ^end ^end: - AIE.end + aie.end } ``` @@ -88,14 +88,14 @@ We can also perform some operations in the AIE core using the same locks. When t ``` -%c72 = AIE.core(%t72) { +%c72 = aie.core(%t72) { %val1 = constant 7 : i32 %idx1 = constant 3 : index %2 = addi %val1, %val1 : i32 - AIE.use_lock(%lock72, "Acquire", 1) // acquire for consume in the core + aie.use_lock(%lock72, "Acquire", 1) // acquire for consume in the core memref.store %2, %buf72[%idx1] : memref<512xi32> //Store operation - AIE.use_lock(%lock72, "Release", 0) // release back to the memory + aie.use_lock(%lock72, "Release", 0) // release back to the memory } ``` At the end, we release the lock back in state 0. This allows for the memory to re-acquire the lock in state 0. @@ -106,49 +106,49 @@ At the end, we release the lock back in state 0. This allows for the memory to r This example uses the same setup as the previous. For Tile (7,2) we can define an additional lock and buffer and change the buffers to be half the size: ``` -%lock72_0 = AIE.lock(%t72, 0) -%lock72_1 = AIE.lock(%t72, 1) +%lock72_0 = aie.lock(%t72, 0) +%lock72_1 = aie.lock(%t72, 1) -%buf72_0 = AIE.buffer(%t72) { sym_name = "a72" } : memref<256xi32> -%buf72_1 = AIE.buffer(%t72) { sym_name = "b72" } : memref<256xi32> +%buf72_0 = aie.buffer(%t72) { sym_name = "a72" } : memref<256xi32> +%buf72_1 = aie.buffer(%t72) { sym_name = "b72" } : memref<256xi32> ``` Then we can write the Stream to Memory Map DMA transfer with 2 buffer descriptors: ``` -%mem72 = AIE.mem(%t72) { - %dma0 = AIE.dma_start("S2MM", 0, ^bd0, ^end) +%mem72 = aie.mem(%t72) { + %dma0 = aie.dma_start("S2MM", 0, ^bd0, ^end) ^bd0: - AIE.use_lock(%lock72_0, "Acquire", 0) - AIE.dma_bd(%buf72_0: memref<256xi32>, 0, 256) - AIE.use_lock(%lock72_0, "Release", 1) + aie.use_lock(%lock72_0, "Acquire", 0) + aie.dma_bd(%buf72_0: memref<256xi32>) { offset = 0 : i32, len = 256 : i32 } + aie.use_lock(%lock72_0, "Release", 1) br ^bd1 // point to the next BD, or termination ^bd1: - AIE.use_lock(%lock72_1, "Acquire", 0) - AIE.dma_bd(%buf72_1: memref<256xi32>, 0, 256) - AIE.use_lock(%lock72_1, "Release", 1) + aie.use_lock(%lock72_1, "Acquire", 0) + aie.dma_bd(%buf72_1: memref<256xi32>) { offset = 0 : i32, len = 256 : i32 } + aie.use_lock(%lock72_1, "Release", 1) br ^bd0 // point to the next BD, or termination ^end: -AIE.end +aie.end } ``` We can use the core in a similar fashion, using the two locks to perform operations on each buffer: ``` -%c72 = AIE.core(%t72) { +%c72 = aie.core(%t72) { %val1 = constant 7 : i32 %idx1 = constant 3 : index %idx2 = constant 10 : index %2 = addi %val1, %val1 : i32 - AIE.use_lock(%lock72_0, "Acquire", 1) // acquire for consume in the core + aie.use_lock(%lock72_0, "Acquire", 1) // acquire for consume in the core memref.store %2, %buf72[%idx1] : memref<512xi32> // store operation - AIE.use_lock(%lock72_0, "Release", 0) // release back to the memory + aie.use_lock(%lock72_0, "Release", 0) // release back to the memory - AIE.use_lock(%lock72_1, "Acquire", 1) // acquire for consume in the core + aie.use_lock(%lock72_1, "Acquire", 1) // acquire for consume in the core memref.store %2, %buf72[%idx2] : memref<512xi32> // store operation - AIE.use_lock(%lock72_1, "Release", 0) // release back to the memory + aie.use_lock(%lock72_1, "Release", 0) // release back to the memory } ``` @@ -162,38 +162,38 @@ We use a similar example to the single buffered communication: ``` -%lock71 = AIE.lock(%t71, 0) // Tile, Lock Number (0-15) -%lock72 = AIE.lock(%t72, 0) +%lock71 = aie.lock(%t71, 0) // Tile, Lock Number (0-15) +%lock72 = aie.lock(%t72, 0) -%buf71 = AIE.buffer(%t71) { sym_name = "a71" } : memref<512xi32> -%buf72 = AIE.buffer(%t72) { sym_name = "a72" } : memref<512xi32> +%buf71 = aie.buffer(%t71) { sym_name = "a71" } : memref<512xi32> +%buf72 = aie.buffer(%t72) { sym_name = "a72" } : memref<512xi32> ``` Start the Memory Map to Stream DMA from the source: ``` -%mem71 = AIE.mem(%tile71) { - %dma0 = AIE.dma_start("MM2S", 0, ^bd0, ^end) +%mem71 = aie.mem(%tile71) { + %dma0 = aie.dma_start("MM2S", 0, ^bd0, ^end) ^bd0: - AIE.use_lock(%lock71, "Acquire", 1) // Acquire in State 0 - AIE.dma_bd(%buf71 : memref<512xi32>, 0, 512) - AIE.use_lock(%lock71, "Release", 1) // Release in State 1 + aie.use_lock(%lock71, "Acquire", 1) // Acquire in State 0 + aie.dma_bd(%buf71 : memref<512xi32>) { offset = 0 : i32, len = 512 : i32 } + aie.use_lock(%lock71, "Release", 1) // Release in State 1 br ^end ^end: - AIE.end + aie.end } ``` Start the Stream to Memory Map DMA from the destination: ``` -%mem72 = AIE.mem(%tile72) { - %dma0 = AIE.dma_start("S2MM", 0, ^bd0, ^end) +%mem72 = aie.mem(%tile72) { + %dma0 = aie.dma_start("S2MM", 0, ^bd0, ^end) ^bd0: - AIE.use_lock(%lock72, "Acquire", 0) - AIE.dma_bd(%buf72 : memref<512xi32>, 0, 512) - AIE.use_lock(%lock72, "Release", 1) + aie.use_lock(%lock72, "Acquire", 0) + aie.dma_bd(%buf72 : memref<512xi32>) { offset = 0 : i32, len = 512 : i32 } + aie.use_lock(%lock72, "Release", 1) br ^end ^end: - AIE.end + aie.end } ``` Since %lock71 is now acquired at state 1, we need to manually release the lock into that state from the host side. This is because the default state of all locks are 0, so they are immediately able to be acquired. @@ -220,23 +220,23 @@ This allows the data transfer to begin To read/write from DDR, we declare an external buffer with a location and size ``` -%ext_buffer = AIE.external_buffer 0x02010004000 : memref<512 x i32> +%ext_buffer = aie.external_buffer 0x02010004000 : memref<512 x i32> ``` We can then use the shim_dma to read/write from that location: ``` -%lock70 = AIE.lock(%t70, 1) +%lock70 = aie.lock(%t70, 1) -%mem70 = AIE.mem(%tile70) { - %dma0 = AIE.dma_start("MM2S", 0, ^bd0, ^end) \\Read +%mem70 = aie.mem(%tile70) { + %dma0 = aie.dma_start("MM2S", 0, ^bd0, ^end) \\Read ^bd0: - AIE.use_lock(%lock70 , "Acquire", 0) - AIE.dma_bd(%ext_buffer : memref<512xi32>, 0, 512) - AIE.use_lock(%lolock70 k72, "Release", 1) + aie.use_lock(%lock70 , "Acquire", 0) + aie.dma_bd(%ext_buffer : memref<512xi32>) { offset = 0 : i32, len = 512 : i32 } + aie.use_lock(%lolock70 k72, "Release", 1) br ^end ^end: - AIE.end + aie.end } ``` @@ -263,35 +263,35 @@ In this pattern, we will show a design pattern for dynamic DDR configuration ``` module { -%t70 = AIE.tile(7, 0) -%t71 = AIE.tile(7, 1) -%t72 = AIE.tile(7, 2) +%t70 = aie.tile(7, 0) +%t71 = aie.tile(7, 1) +%t72 = aie.tile(7, 2) -%buf72_0 = AIE.buffer(%t72) {sym_name="a"} : memref<256xi32> -%buf72_1 = AIE.buffer(%t72) {sym_name="b"} : memref<256xi32> +%buf72_0 = aie.buffer(%t72) {sym_name="a"} : memref<256xi32> +%buf72_1 = aie.buffer(%t72) {sym_name="b"} : memref<256xi32> -%l72_0 = AIE.lock(%t72, 0) -%l72_1 = AIE.lock(%t72, 1) +%l72_0 = aie.lock(%t72, 0) +%l72_1 = aie.lock(%t72, 1) -%m72 = AIE.mem(%t72) { +%m72 = aie.mem(%t72) { - %srcDma = AIE.dma_start("MM2S", 0, ^bd0, ^end) + %srcDma = aie.dma_start("MM2S", 0, ^bd0, ^end) ^bd0: - AIE.use_lock(%l72_0, "Acquire", 1) - AIE.dma_bd(%buf72_0 : memref<256xi32>, 0, 256) - AIE.use_lock(%l72_0, "Release", 0) + aie.use_lock(%l72_0, "Acquire", 1) + aie.dma_bd(%buf72_0 : memref<256xi32>) { offset = 0 : i32, len = 256 : i32 } + aie.use_lock(%l72_0, "Release", 0) br ^bd1 ^bd1: - AIE.use_lock(%l72_1, "Acquire", 1) - AIE.dma_bd(%buf72_1 : memref<256xi32>, 0, 256) - AIE.use_lock(%l72_1, "Release", 0) + aie.use_lock(%l72_1, "Acquire", 1) + aie.dma_bd(%buf72_1 : memref<256xi32>) { offset = 0 : i32, len = 256 : i32 } + aie.use_lock(%l72_1, "Release", 0) br ^bd0 ^end: - AIE.end + aie.end } -AIE.flow(%t72, "DMA" : 0, %t70, "DMA" : 0) +aie.flow(%t72, "DMA" : 0, %t70, "DMA" : 0) } ``` @@ -351,106 +351,106 @@ Unlike a typical FIFO, elements are not pushed to nor popped from the objectFIFO Processes can then write to and read from these memory elements after acquiring them. -Define two tiles and create an AIE.objectfifo named @of0 of depth two between them, with the two elements being of type >: +Define two tiles and create an aie.objectfifo named @of0 of depth two between them, with the two elements being of type >: ``` -%tile12 = AIE.tile(1, 2) -%tile33 = AIE.tile(3, 3) -AIE.objectfifo @of0 (%tile12, {tile33}, 2 : i32) : !AIE.objectfifo> +%tile12 = aie.tile(1, 2) +%tile33 = aie.tile(3, 3) +aie.objectfifo @of0 (%tile12, {tile33}, 2 : i32) : !aie.objectfifo> ``` -After subsequent conversion passes, each of the objectFifo elements is instantiated as an AIE.buffer with an AIE.lock. +After subsequent conversion passes, each of the objectFifo elements is instantiated as an aie.buffer with an aie.lock. objectFIFO operations have a 'port' attribute which indicates whether a tile is a 'producer' or a 'consumer' of that objectFIFO. -Operations can be performed on the objectFIFO in the cores: elements can be acquired from the objectFIFO and accessed via an AIE.objectfifosubview type, then released: +Operations can be performed on the objectFIFO in the cores: elements can be acquired from the objectFIFO and accessed via an aie.objectfifosubview type, then released: ``` -%core12 = AIE.core(%tile12) { +%core12 = aie.core(%tile12) { %c0 = arith.constant 0 : index %c1 = arith.constant 1 : index %height = arith.constant 12 : index scf.for %indexInHeight = %c0 to %height step %c1 { - %subview = AIE.objectfifo.acquire @of0 (Produce, 1) : !AIE.objectfifosubview> - %elem0 = AIE.objectfifo.subview.access %subview[0] : !AIE.objectfifosubview> -> memref<16xi32> + %subview = aie.objectfifo.acquire @of0 (Produce, 1) : !aie.objectfifosubview> + %elem0 = aie.objectfifo.subview.access %subview[0] : !aie.objectfifosubview> -> memref<16xi32> call @some_work(%elem0) : (memref<16xi32>) -> () - AIE.objectfifo.release @of0 (Produce, 1) + aie.objectfifo.release @of0 (Produce, 1) } - AIE.end + aie.end } -%core33 = AIE.core(%tile33) { +%core33 = aie.core(%tile33) { %c0 = arith.constant 0 : index %c1 = arith.constant 1 : index %height = arith.constant 12 : index scf.for %indexInHeight = %c0 to %height step %c1 { - %subview = AIE.objectfifo.acquire @of0 (Consume, 1) : !AIE.objectfifosubview> - %elem0 = AIE.objectfifo.subview.access %subview[0] : !AIE.objectfifosubview> -> memref<16xi32> + %subview = aie.objectfifo.acquire @of0 (Consume, 1) : !aie.objectfifosubview> + %elem0 = aie.objectfifo.subview.access %subview[0] : !aie.objectfifosubview> -> memref<16xi32> call @some_work(%elem0) : (memref<16xi32>) -> () - AIE.objectfifo.release @of0 (Consume, 1) + aie.objectfifo.release @of0 (Consume, 1) } - AIE.end + aie.end } ``` For correct execution, loops that contain objectFIFO operations must be unrolled based on objectFIFO size; the previous code in core12 becomes: ``` -%core12 = AIE.core(%tile12) { +%core12 = aie.core(%tile12) { %c0 = arith.constant 0 : index %c2 = arith.constant 2 : index %height = arith.constant 12 : index scf.for %indexInHeight = %c0 to %height step %c2 { - %subview0 = AIE.objectfifo.acquire @of0 (Produce, 1) : !AIE.objectfifosubview> - %elem00 = AIE.objectfifo.subview.access %subview0[0] : !AIE.objectfifosubview> -> memref<16xi32> + %subview0 = aie.objectfifo.acquire @of0 (Produce, 1) : !aie.objectfifosubview> + %elem00 = aie.objectfifo.subview.access %subview0[0] : !aie.objectfifosubview> -> memref<16xi32> call @some_work(%elem00) : (memref<16xi32>) -> () - AIE.objectfifo.release @of0 (Produce, 1) + aie.objectfifo.release @of0 (Produce, 1) - %subview1 = AIE.objectfifo.acquire @of0 (Produce, 1) : !AIE.objectfifosubview> - %elem10 = AIE.objectfifo.subview.access %subview1[0] : !AIE.objectfifosubview> -> memref<16xi32> + %subview1 = aie.objectfifo.acquire @of0 (Produce, 1) : !aie.objectfifosubview> + %elem10 = aie.objectfifo.subview.access %subview1[0] : !aie.objectfifosubview> -> memref<16xi32> call @some_work(%elem10) : (memref<16xi32>) -> () - AIE.objectfifo.release @of0 (Produce, 1) + aie.objectfifo.release @of0 (Produce, 1) } - AIE.end + aie.end } ``` -ObjectFIFOs can be established between tiles on the shim row and AIE tiles in order to bring data in from or out to external memory locations. These external memory locations are pointed to using AIE.external_buffer operations and they need to be explicitly registered to an objectFIFO so that it knows where the data has been allocated externally (in this case, the objectFIFO lowering will only allocate memory elements required by AIE tiles): +ObjectFIFOs can be established between tiles on the shim row and AIE tiles in order to bring data in from or out to external memory locations. These external memory locations are pointed to using aie.external_buffer operations and they need to be explicitly registered to an objectFIFO so that it knows where the data has been allocated externally (in this case, the objectFIFO lowering will only allocate memory elements required by AIE tiles): ``` module @objectFIFO { - %tile10 = AIE.tile(1, 0) - %tile33 = AIE.tile(3, 3) + %tile10 = aie.tile(1, 0) + %tile33 = aie.tile(3, 3) - AIE.objectfifo @of1 (%tile10, {tile33}, 2 : i32) : !AIE.objectfifo> + aie.objectfifo @of1 (%tile10, {tile33}, 2 : i32) : !aie.objectfifo> - %ext_buffer_in_0 = AIE.external_buffer {sym_name = "ext_buffer_in_0"}: memref<64xi32> - %ext_buffer_in_1 = AIE.external_buffer {sym_name = "ext_buffer_in_1"}: memref<64xi32> - AIE.objectfifo.register_external_buffers @of1 (%tile10, { %ext_buffer_in_0, %ext_buffer_in_1 }) : (memref<64xi32>, memref<64xi32>) + %ext_buffer_in_0 = aie.external_buffer {sym_name = "ext_buffer_in_0"}: memref<64xi32> + %ext_buffer_in_1 = aie.external_buffer {sym_name = "ext_buffer_in_1"}: memref<64xi32> + aie.objectfifo.register_external_buffers @of1 (%tile10, { %ext_buffer_in_0, %ext_buffer_in_1 }) : (memref<64xi32>, memref<64xi32>) } ``` It is possible to copy data from one objectFifo to another. This copy can be done explicitly within the AIE cores, or implicitly using the tile DMAs. The latter case is not as much a copy as it is re-using the same memory buffers when receiving data on an input channel and sending the data out on an output channel. At the objectFIFO abstraction, this is called 'linking' two objectFIFOs. It is most commonly done inside of Mem tiles which have more memory than AIE tiles. ``` module @objectFIFO { - %tile20 = AIE.tile(2, 0) - %tile22 = AIE.tile(2, 2) - %tile24 = AIE.tile(2, 4) + %tile20 = aie.tile(2, 0) + %tile22 = aie.tile(2, 2) + %tile24 = aie.tile(2, 4) - AIE.objectfifo @of1 (%tile20, { %tile22 }, 2 : i32) : !AIE.objectfifo> - AIE.objectfifo @of2 (%tile22, { %tile24 }, 2 : i32) : !AIE.objectfifo> + aie.objectfifo @of1 (%tile20, { %tile22 }, 2 : i32) : !aie.objectfifo> + aie.objectfifo @of2 (%tile22, { %tile24 }, 2 : i32) : !aie.objectfifo> - AIE.objectfifo.link [@of1] -> [@of2] () + aie.objectfifo.link [@of1] -> [@of2] () } ``` At a higher abstraction level, a process can be registered to an objectFIFO using access patterns and work functions: ``` module @objectFIFO { - %tile12 = AIE.tile(1, 2) - %tile33 = AIE.tile(3, 3) + %tile12 = aie.tile(1, 2) + %tile33 = aie.tile(3, 3) - AIE.objectfifo @of1 (%tile12, {tile33}, 2 : i32) : !AIE.objectfifo> + aie.objectfifo @of1 (%tile12, {tile33}, 2 : i32) : !aie.objectfifo> %prodAcqPattern = arith.constant dense<[1]> : tensor<1xi32> %prodRelPattern = arith.constant dense<[1]> : tensor<1xi32> @@ -459,7 +459,7 @@ module @objectFIFO { return } - AIE.objectfifo.register_process @of1 (Produce, %prodAcqPattern : tensor<1xi32>, %prodRelPattern : tensor<1xi32>, @producer_work, %prodLength) + aie.objectfifo.register_process @of1 (Produce, %prodAcqPattern : tensor<1xi32>, %prodRelPattern : tensor<1xi32>, @producer_work, %prodLength) } ``` @@ -477,24 +477,24 @@ source port (%t72, "DMA" : 0) to broadcast data to %t73, %t63(ID: 0x0) and %t74, Define tiles ``` -%t72 = AIE.tile(7, 2) -%t63 = AIE.tile(6, 3) -%t64 = AIE.tile(6, 4) -%t73 = AIE.tile(7, 3) -%t74 = AIE.tile(7, 4) +%t72 = aie.tile(7, 2) +%t63 = aie.tile(6, 3) +%t64 = aie.tile(6, 4) +%t73 = aie.tile(7, 3) +%t74 = aie.tile(7, 4) ``` broadcast_packet ``` -AIE.broadcast_packet(%t72, "DMA" : 0){ - AIE.bp_id(0x0){ - AIE.bp_dest<%t73, "DMA" : 0> - AIE.bp_dest<%t63, "DMA" : 0> +aie.broadcast_packet(%t72, "DMA" : 0){ + aie.bp_id(0x0){ + aie.bp_dest<%t73, "DMA" : 0> + aie.bp_dest<%t63, "DMA" : 0> } - AIE.bp_id(0x1){ - AIE.bp_dest<%t74, "DMA" : 0> - AIE.bp_dest<%t64, "DMA" : 0> + aie.bp_id(0x1){ + aie.bp_dest<%t74, "DMA" : 0> + aie.bp_dest<%t64, "DMA" : 0> } } diff --git a/include/aie/Dialect/AIE/IR/AIEInterfaces.td b/include/aie/Dialect/AIE/IR/AIEInterfaces.td index b31e8e9be9..90cc7d762c 100644 --- a/include/aie/Dialect/AIE/IR/AIEInterfaces.td +++ b/include/aie/Dialect/AIE/IR/AIEInterfaces.td @@ -133,12 +133,7 @@ def AIETarget : OpInterface<"AIETarget"> { ]; } -// def OffloadingTranslationAttrTrait : -// NativeTrait<"OffloadingTranslationAttrTrait", ""> { -// let cppNamespace = "::mlir::gpu"; -// } - -def MyOffsetSizeAndStrideOpInterface: OpInterfaceTrait<"::xilinx::AIE::MyOffsetSizeAndStrideOpInterface"> { -} +// Don't delete - see AIEDialect::myVerifyOffsetSizeAndStrideOp +def MyOffsetSizeAndStrideOpInterface: OpInterfaceTrait<"::xilinx::AIE::MyOffsetSizeAndStrideOpInterface"> {} #endif // AIE_INTERFACES \ No newline at end of file diff --git a/include/aie/Dialect/AIE/IR/AIEOps.td b/include/aie/Dialect/AIE/IR/AIEOps.td index 41affdce1a..24113fd035 100644 --- a/include/aie/Dialect/AIE/IR/AIEOps.td +++ b/include/aie/Dialect/AIE/IR/AIEOps.td @@ -263,7 +263,7 @@ def AIE_ShimDMAOp: AIE_Op<"shim_dma", [ aie.dma_start(MM2S, 0, ^bd0, ^end) ^bd0: aie.use_lock(%lock1, Acquire, 1) - aie.dma_bd(%buf : memref<512 x i16>, 0, 512) + aie.dma_bd(%buf : memref<512 x i16>) { offset = 0 : i32, len = 512 : i32 } aie.use_lock(%lock1, Release, 0) aie.next_bd ^bd0 ^end: @@ -745,46 +745,67 @@ def AIE_DMABDPACKETOp: AIE_Op<"dma_bd_packet", []> { }]; } -def AIE_DMABDOp: AIE_Op<"dma_bd", []> { - let summary = "Declare a dma block descriptor op"; +def AIE_DMABDOp: AIE_Op<"dma_bd", [ + ParentOneOf<["MemOp", "MemTileDMAOp", "ShimDMAOp", "DMAOp"]>, + ]> { + let summary = "Declare a dma buffer descriptor op"; let description = [{ - This operation describes a block descriptor for DMA operations. In particular, it specifies - what buffer addresss to use, the transfer length, and the buffer type (A or B). + This operation describes a buffer descriptor for DMA operations. In particular, it specifies + what buffer to use, and optionally: - This operation must be used in an MLIR block that lives inside a MemOp's region. - The block descriptor specifies what lock to use and the buffer configuration. + 1. the offset into the buffer; + 2. the transfer length; + 3. the sizes and strides for n-d tensor addressing (described below); + 4. the "bd_id" with which to associate the buffer descriptor (most often left empty). + + `offset`, `len`, `size`s and `stride`s are all denominated in element width; e.g., transferring the whole of + `memref<512xi32>` means `len == 512`, and also while transferring the whole of `memref<512xi16>`, `len == 512`. + + The only caveat to this "everything-is-in-terms-of-element-width" rule is regarding the inner-most dimension's stride + (see [Important gotcha regarding strides](#important-gotcha-regarding-strides) below). + + `dma_bd` ops must appear in their own BBs (basic blocks) and such BBs can (optionally) include `use_lock` + operations (specifying an "acquire" and a "release" lock; see the `use_lock` operation) and subsequent BDs in + a "chain" of BDs (using `next_bd` as a "jump" to the next BB which contains a `dma_bd`). Example: ``` // this defines a BD that uses lock %lck0 and buffer %buf0 ^bd5: aie.use_lock(%lck, "Acquire", 0) - aie.dma_bd(<$buf0 : memref<512xi32>, 0, 512>, 1) + // transfer the first 32 elements of the memref + aie.dma_bd(<$buf0 : memref<128xi32>) { offset = 0 : i32, len = 32 : i32 } aie.use_lock(%lck, "Release", 1) - br ^bd6 // point to the next Block, which is also a different Block Descriptor + aie.next_bd ^bd6 // point to the next bb, which describes the next buffer descriptor + ^bd6: + aie.use_lock(%lck, "Acquire", 1) + // transfer the last 32 elements of the memref + aie.dma_bd(<$buf1 : memref<128xi32>) { offset = 96 : i32, len = 32 : i32 } + aie.use_lock(%lck, "Release", 0) + aie.next_bd ^end ... // this defines a BD that does not use any lock ^bd8: - aie.dma_bd(<$buf1 : memref<64xi32>, 0, 64>, 0) + aie.dma_bd(<$buf2 : memref<64xi32>) { offset = 0 : i32, len = 64 : i32 } ``` - A DMA channel in a Memory Module can process one block descriptor after another by chaining them. - There are 16 block descriptors per Memory Module. They are shared by four DMA channels. + + ## Background/context: + + A DMA channel in a Memory Module can process one buffer descriptor after another by chaining them. + There are 16 buffer descriptors per Core memory module and 48 buffer descriptors per Memtile memory module. + They are shared by four DMA channels (or 12). ## DMA Data Layout Transformations on AIE-ML Devices AIE-ML devices can apply data layout transformations at the buffer descriptor level. These transformation are described by strides and sizes in up to three dimensions (four dimensions on memtiles). Strides and sizes can be supplied to the `dma_bd` - through an optional argument, an array of tuples ``. - - The first element of this array gives the _highest-dimension_ stride and - size, the last element of the array gives the lowest-dimension. - - Strides are always expressed in units of `i32`s; this is an architectural - requirement, as data is moved by the DMA at this fundamental size. + through an optional argument, an array of "tuple-like" attributes `bd_dim_layout`. + The first element of this array gives the outer-most dimension's stride and + size, the last element of the array gives the inner-most dimension's stride and size. We can model the access pattern strides and sizes generate by a series of nested loops. In general, a set of strides and sizes like this... @@ -820,13 +841,20 @@ def AIE_DMABDOp: AIE_Op<"dma_bd", []> { for(int k = 0; k < 8 /*size_0*/; k++) // access/store element at/to index (i * 16 /*stride_2*/ + j * 1 /*stride_1*/ + k * 2 /*stride_0*/) ``` + + ## Important gotcha regarding strides + + All strides are expressed in multiples of the element width (just like `len` and `offset`) + **with the caveat that the inner-most dimension's stride must be 1**. }]; let arguments = ( ins AnyMemRef:$buffer, - OptionalAttr:$offset, + // in multiples of element width (not bytes) + DefaultValuedOptionalAttr:$offset, + // in multiples of element width (not bytes) OptionalAttr:$len, - OptionalAttr:$dimensions, + OptionalAttr:$dims, OptionalAttr:$bd_id, // should never be assigned by user... OptionalAttr:$next_bd_id @@ -835,13 +863,21 @@ def AIE_DMABDOp: AIE_Op<"dma_bd", []> { let hasVerifier = 1; let assemblyFormat = [{ - `(` $buffer `:` type($buffer) (`,` $offset^)? (`,` $len^)? (`,` $dimensions^)? `)` attr-dict + `(` $buffer `:` type($buffer) (`,` `dims` `=` $dims^)? `)` attr-dict }]; let extraClassDeclaration = [{ BufferOp getBufferOp(); - int getOffsetValue() { return getOffset().value_or(0); } - int getLenValue() { return getLen().value_or(getBuffer().getType().getNumElements()); } + int32_t getBufferElementTypeWidthInBytes() { + return getBuffer().getType().getElementTypeBitWidth() / 8; + } + int32_t getLenInBytes() { + if (std::optional len = getLen(); len.has_value()) + return len.value() * getBufferElementTypeWidthInBytes(); + else + return getBuffer().getType().getNumElements() * getBufferElementTypeWidthInBytes(); + } + int32_t getOffsetInBytes() { return getOffset() * getBufferElementTypeWidthInBytes(); } }]; let hasVerifier = 1; @@ -855,7 +891,7 @@ def AIE_DMABDOp: AIE_Op<"dma_bd", []> { $_state.addOperands(buffer); $_state.addAttribute("offset", $_builder.getI32IntegerAttr(offset)); $_state.addAttribute("len", $_builder.getI32IntegerAttr(len)); - $_state.addAttribute("dimensions", dims); + $_state.addAttribute("dims", dims); }]> ]; } @@ -878,7 +914,7 @@ def AIE_DMAStartOp: AIE_Op<"dma_start", [ aie.dma_start("MM2S", 0, ^bd0, ^end) ^bd0: aie.use_lock(%lock0, "Acquire", 0) - aie.dma_bd(%buffer : memref<16 x f32>, 0, 16) + aie.dma_bd(%buffer : memref<16 x f32>) { offset = 0 : i32, len = 16 : i32 } aie.use_lock(%lock0, "Release", 1) br ^bd0 ^end: @@ -962,7 +998,7 @@ def AIE_MemOp: AIE_Op<"mem", [ %srcDma = aie.dma_start("S2MM", 0, ^bd0, ^end) ^bd0: aie.use_lock(%lock, "Acquire", 0) - aie.dma_bd(%buf : memref<64xi16>, 0, 64) + aie.dma_bd(%buf : memref<64xi16>) { offset = 0 : i32, len = 64 : i32 } aie.use_lock(%lock, "Release", 1) aie.next_bd ^bd0 ^end: @@ -1056,7 +1092,7 @@ def AIE_NextBDOp: AIE_Op<"next_bd", [ %srcDma = aie.dma_start("S2MM", 0, ^bd0, ^end) ^bd0: aie.use_lock(%lock, "Acquire", 0) - aie.dma_bd(%buf : memref<64xi16>, 0, 64) + aie.dma_bd(%buf : memref<64xi16>) { offset = 0 : i32, len = 64 : i32 } aie.use_lock(%lock, "Release", 1) aie.next_bd ^bd0 ^end: diff --git a/lib/Dialect/AIE/IR/AIEDialect.cpp b/lib/Dialect/AIE/IR/AIEDialect.cpp index 7ce933fba6..02af858d89 100644 --- a/lib/Dialect/AIE/IR/AIEDialect.cpp +++ b/lib/Dialect/AIE/IR/AIEDialect.cpp @@ -1545,60 +1545,79 @@ LogicalResult DMABDOp::verify() { if (!isa(getBuffer().getDefiningOp())) return emitOpError( "BDs only support BufferOp or ExternalBufferOp operands."); - if (auto memOp = getOperation()->getParentOfType()) { - if (auto bufferOp = getBufferOp(); - bufferOp.getTileOp().colIndex() != memOp.colIndex() || - bufferOp.getTileOp().rowIndex() != memOp.rowIndex()) - return emitOpError("can only access a buffer in the same tile."); - } - // The following checks only apply if non-default strides/wraps are defined. - if (getDimensions()) { - MemRefType buffer = getBuffer().getType(); - // We are not restrictive about the type of the memref used as the input - // to the DMABD when used with multi-dimensional strides/wraps. Since the - // BD will use the memref as a base address and copy from it in 32 bit - // chunks, while assuming the layout of the memref is contiguous. We - // assume the user/compiler understands and accounts for this. - uint64_t memrefSize = 1; // in bytes - uint64_t maxIdx = 0; - for (int64_t memrefDim : buffer.getShape()) - memrefSize *= 4 * memrefDim; - - ArrayRef dims = *getDimensions(); + if (getLenInBytes() % 4) + return emitOpError("transfer length must be multiple of 4 (i.e., represent " + "4 byte aligned address)"); + + TileID parentTileId = getParentTileElement(getOperation()).getTileID(); + + if (getOperation()->getParentOfType() && + (getBufferOp().getTileOp().colIndex() != parentTileId.col || + getBufferOp().getTileOp().rowIndex() != parentTileId.row)) + return emitOpError( + "Core tile DMAs can only access a buffer in the same tile."); + + const AIETargetModel &targetModel = getTargetModel(getOperation()); + + uint32_t maxBds = targetModel.getNumBDs(parentTileId.col, parentTileId.row); + if (std::optional bdId = getBdId(); + bdId.has_value() && static_cast(*bdId) >= maxBds) + return emitOpError("bdId attribute exceeds max: ") << maxBds - 1; + if (std::optional nextBdId = getNextBdId(); + nextBdId.has_value() && static_cast(*nextBdId) >= maxBds) + return emitOpError("nextBdId attribute exceeds max: ") << maxBds - 1; + if (auto dims = getDims(); dims.has_value()) { size_t maxNDims = 3; if (isa_and_nonnull(getOperation()->getParentOp())) maxNDims = 4; - - if (dims.size() > maxNDims) + if (dims->size() > maxNDims) return emitOpError() << "Cannot give more than " << std::to_string(maxNDims) << " dimensions for step sizes and wraps in this " " tile (got " - << std::to_string(dims.size()) << " dimensions)."; + << std::to_string(dims->size()) << " dimensions)."; - for (BDDimLayoutAttr dim : dims) { + MemRefType buffer = getBuffer().getType(); + int64_t maxIdx = 0; + for (BDDimLayoutAttr dim : *dims) { maxIdx += dim.getStride() * (dim.getSize() - 1); if (0 == dim.getStride()) return emitOpError() << "Invalid step size; must be a positive integer."; - if (dim.getStride() > memrefSize) + if (dim.getStride() > buffer.getNumElements()) return emitOpError() - << "Step size " << std::to_string(dim.getStride() * 4) << " " - << "bytes exceeds memref size " << std::to_string(memrefSize); + << "Step size " << std::to_string(dim.getStride()) << " " + << "exceeds memref size " + << std::to_string(buffer.getNumElements()); if (dim.getSize() >= (1UL << 9) + 1) return emitOpError() << "Size may not exceed 1023."; if (dim.getStride() >= (1UL << 19)) return emitOpError() << "Stride may not exceed " << (1 << 20); } - if (memrefSize <= 4 * maxIdx) + if (buffer.getNumElements() <= maxIdx) return emitOpError() << "Specified stride(s) and size(s) result in out " "of bounds access in buffer, for index " - << std::to_string(maxIdx) << ", accessing at " - << std::to_string(4 * maxIdx) - << " byte offset in memref of length " - << std::to_string(memrefSize) << "."; + << std::to_string(maxIdx) << " in memref of length " + << std::to_string(buffer.getNumElements()) << "."; + + // Since streams read 32b words, there's no way to read eg 16b with stride + // of 2 (ie lower halfs of each 32b). So force it to be 1 (and then in + // CDODirect/XAIEV2 scale the size by 4/getBufferElementTypeWidthInBytes). + if (getBufferElementTypeWidthInBytes() < 4 && dims->back().getStride() != 1) + return emitOpError( + "For <32b width datatypes, inner-most dim stride must be 1"); + } + if (targetModel.isMemTile(parentTileId.col, parentTileId.row) || + targetModel.isCoreTile(parentTileId.col, parentTileId.row)) { + if (auto baseAddr = getBufferOp().getAddress(); baseAddr.has_value()) { + int offsetInBytes = *baseAddr + getOffsetInBytes(); + if (offsetInBytes % 4) + return emitOpError( + "bd address must be 4 byte (32b) aligned; got base+offset: ") + << offsetInBytes << " (bytes)"; + } } if (!getLen() && !getBuffer().getType().hasStaticShape()) diff --git a/lib/Dialect/AIE/Transforms/AIEObjectFifoStatefulTransform.cpp b/lib/Dialect/AIE/Transforms/AIEObjectFifoStatefulTransform.cpp index 7731f03c47..46741dab04 100644 --- a/lib/Dialect/AIE/Transforms/AIEObjectFifoStatefulTransform.cpp +++ b/lib/Dialect/AIE/Transforms/AIEObjectFifoStatefulTransform.cpp @@ -204,14 +204,6 @@ struct AIEObjectFifoStatefulTransformPass return !hasSharedMemory || atLeastOneConsumerWantsTransform; } - /// Function to multiply all dimensions of a memref. - int64_t getMemrefTypeSize(MemRefType memref) { - int64_t size = 1; - for (auto dim : memref.getShape()) - size *= dim; - return size; - } - /// Function to retrieve ObjectFifoLinkOp of ObjectFifoCreateOp, /// if it belongs to one. std::optional getOptionalLinkOp(ObjectFifoCreateOp op) { @@ -325,14 +317,14 @@ struct AIEObjectFifoStatefulTransformPass .getElemType() .cast(); auto elemInType = fifoInType.getElementType().cast(); - int inSize = getMemrefTypeSize(elemInType); + int inSize = elemInType.getNumElements(); auto fifoOutType = linkOp->getOutputObjectFifos()[0] .getElemType() .cast(); auto elemOutType = fifoOutType.getElementType().cast(); - if (int outSize = getMemrefTypeSize(elemOutType); inSize >= outSize) { + if (int outSize = elemOutType.getNumElements(); inSize >= outSize) { if (op.name() != fifoIn.name()) return; } else { @@ -474,11 +466,10 @@ struct AIEObjectFifoStatefulTransformPass int acqNum = 1; int relNum = 1; - int offset = 0; auto fifo = op.getElemType().cast(); auto elemType = fifo.getElementType().cast(); - int len = getMemrefTypeSize(elemType); + int len = elemType.getNumElements(); // search for the buffers/locks (based on if this objFifo has a link) ObjectFifoCreateOp target = op; @@ -539,8 +530,8 @@ struct AIEObjectFifoStatefulTransformPass builder.setInsertionPointToStart(curr); createBdBlock(builder, target, lockMode, acqNum, relNum, - buffersPerFifo[target][blockIndex], offset, len, - channelDir, blockIndex, succ, dims); + buffersPerFifo[target][blockIndex], /*offset*/ 0, + len, channelDir, blockIndex, succ, dims); curr = succ; blockIndex++; } @@ -558,7 +549,6 @@ struct AIEObjectFifoStatefulTransformPass int acqNum = 1; int relNum = 1; - int offset = 0; // search for ShimDMAOp Operation *producerDMA = nullptr; @@ -612,12 +602,12 @@ struct AIEObjectFifoStatefulTransformPass succ = builder.createBlock(endBlock); MemRefType buffer = externalBuffersPerFifo[op][blockIndex].getType(); - int len = getMemrefTypeSize(buffer); + int len = buffer.getNumElements(); builder.setInsertionPointToStart(curr); createBdBlock(builder, op, lockMode, acqNum, relNum, externalBuffersPerFifo[op][blockIndex], - offset, len, channelDir, blockIndex, succ, - dims); + /*offset*/ 0, len, channelDir, blockIndex, + succ, dims); curr = succ; blockIndex++; } @@ -633,11 +623,9 @@ struct AIEObjectFifoStatefulTransformPass if (numBlocks == 0) return; - int offset = 0; auto fifo = op.getElemType().cast(); auto elemType = fifo.getElementType().cast(); - int lenOut = getMemrefTypeSize(elemType); - int bytes = elemType.getElementTypeBitWidth() / 8; + int lenOut = elemType.getNumElements(); int acqNum = 1; int relNum = 1; @@ -663,7 +651,7 @@ struct AIEObjectFifoStatefulTransformPass auto elemType = fifoType.getElementType().cast(); if (fifoIn.name() == op.name()) break; - extraOffset += getMemrefTypeSize(elemType); + extraOffset += elemType.getNumElements(); } } } else if (linkOp->isDistribute()) { @@ -678,7 +666,7 @@ struct AIEObjectFifoStatefulTransformPass auto elemType = fifoType.getElementType().cast(); if (fifoOut.name() == op.name()) break; - extraOffset += getMemrefTypeSize(elemType); + extraOffset += elemType.getNumElements(); } } } else { @@ -686,7 +674,7 @@ struct AIEObjectFifoStatefulTransformPass auto targetFifo = target.getElemType().cast(); auto targetElemType = targetFifo.getElementType().cast(); - lenOut = getMemrefTypeSize(targetElemType); + lenOut = targetElemType.getNumElements(); } } @@ -748,8 +736,9 @@ struct AIEObjectFifoStatefulTransformPass succ = builder.createBlock(endBlock); builder.setInsertionPointToStart(curr); + int offset = 0; if (isDistribute || isJoin) - offset = extraOffset * bytes; + offset = extraOffset; createBdBlock(builder, target, lockMode, acqNum, relNum, buffersPerFifo[target][blockIndex], offset, lenOut, channelDir, blockIndex, succ, dims); diff --git a/lib/Targets/AIETargetAirbin.cpp b/lib/Targets/AIETargetAirbin.cpp index 6c78a00ed3..6f99031283 100644 --- a/lib/Targets/AIETargetAirbin.cpp +++ b/lib/Targets/AIETargetAirbin.cpp @@ -595,14 +595,12 @@ static BDInfo getBDInfo(Block &block) { BDInfo bdInfo; for (auto op : block.getOps()) { bdInfo.foundBD = true; - auto bufferType = op.getBuffer().getType().cast<::mlir::MemRefType>(); - assert(op.getBufferOp().getAddress().has_value() && "buffer op should have address"); bdInfo.baseAddrA = op.getBufferOp().getAddress().value(); - bdInfo.lenA = op.getLenValue(); - bdInfo.bytesA = bufferType.getElementTypeBitWidth() / 8u; - bdInfo.offsetA = op.getOffsetValue(); + bdInfo.lenA = op.getLenInBytes(); + bdInfo.bytesA = op.getBufferElementTypeWidthInBytes(); + bdInfo.offsetA = op.getOffsetInBytes(); bdInfo.bufA = "XAIEDMA_TILE_BD_ADDRA"; bdInfo.hasA = true; } diff --git a/lib/Targets/AIETargetCDODirect.cpp b/lib/Targets/AIETargetCDODirect.cpp index 5d7583c859..e7986080f6 100644 --- a/lib/Targets/AIETargetCDODirect.cpp +++ b/lib/Targets/AIETargetCDODirect.cpp @@ -273,48 +273,57 @@ LogicalResult configureBdInBlock(XAie_DevInst &devInst, XAie_DmaDesc &dmaTileBd, qOs, cache, secure); } - // deref here because this is a const iter and the various getters below - // aren't const (even though they probably should be...) // StringRef FifoMode = disable; // FIXME: when to enable FIFO mode? - ShapedType bufferType = bdOp.getBuffer().getType().cast<::mlir::MemRefType>(); - int bytes = bufferType.getElementTypeBitWidth() / 8; int baseAddr = 0; if (!targetModel.isShimNOCTile(tileLoc.Col, tileLoc.Row)) { auto bufferOp = cast(bdOp.getBuffer().getDefiningOp()); - assert(bufferOp.getAddress().has_value() && "buffer must have address"); + if (!bufferOp.getAddress()) + return bufferOp.emitError("buffer must have address assigned"); baseAddr = bufferOp.getAddress().value(); if (targetModel.isMemTile(tileLoc.Col, tileLoc.Row)) baseAddr += BASE_ADDR_A_INCR; } - std::optional> dims = bdOp.getDimensions(); - int lenInBytes = bdOp.getLenValue() * bytes; - int basePlusOffset = baseAddr + bdOp.getOffsetValue(); + std::optional> dims = bdOp.getDims(); + int lenInBytes = bdOp.getLenInBytes(); + int basePlusOffsetInBytes = baseAddr + bdOp.getOffsetInBytes(); if (!dims) { TRY_XAIE_API_EMIT_ERROR(bdOp, XAie_DmaSetAddrLen, &dmaTileBd, - basePlusOffset, lenInBytes); + basePlusOffsetInBytes, lenInBytes); } else { XAie_DmaTensor dmaTileBdTensor = {}; dmaTileBdTensor.NumDim = dims->size(); dmaTileBdTensor.Dim = static_cast( - calloc(dims->size(), sizeof(XAie_DmaDimDesc))); + calloc(dmaTileBdTensor.NumDim, sizeof(XAie_DmaDimDesc))); if (!dmaTileBdTensor.Dim) return bdOp.emitError("couldn't allocate array of XAie_DmaDimDesc"); - // TODO(max): rethink this? + // libxaie requires stride in multiples of 32b + double elementWidthIn32bWords = + static_cast(bdOp.getBufferElementTypeWidthInBytes()) / 4.0; for (size_t i = 0; i < dims->size(); i++) { // Pass down dimensions in reverse order; in the MLIR, this allows // us to specify step sizes/wraps in the same order as we would // access a multi-dim C array, with the highest dimension first. int j = dims->size() - i - 1; - // Assume AIE-ML architecture; we assert this above - // TODO(max): no we don't - dmaTileBdTensor.Dim[j].AieMlDimDesc = {dims.value()[i].getStride(), - dims.value()[i].getSize()}; + uint16_t size; + uint32_t stride; + if (j > 0) { + stride = static_cast(dims.value()[i].getStride() * + elementWidthIn32bWords); + size = dims.value()[i].getSize(); + } else { + stride = dims.value()[i].getStride(); + size = static_cast(dims.value()[i].getSize() * + elementWidthIn32bWords); + } + stride = stride > 0 ? stride : 1; + // Assume AIE-ML architecture (ie use AieMlDimDesc instead of AieDimDesc); + // asserted in AIETranslateToCDODirect). + dmaTileBdTensor.Dim[j].AieMlDimDesc = {stride, size}; } - // TODO: Probably need special handling for NOC - // TODO: Might need to adjust step sizes / wraps by -1 TRY_XAIE_API_EMIT_ERROR(bdOp, XAie_DmaSetMultiDimAddr, &dmaTileBd, - &dmaTileBdTensor, basePlusOffset, lenInBytes); + &dmaTileBdTensor, basePlusOffsetInBytes, + lenInBytes); } if (nextBdId) { @@ -324,8 +333,9 @@ LogicalResult configureBdInBlock(XAie_DevInst &devInst, XAie_DmaDesc &dmaTileBd, } if (packetID) { - assert(packetType && "must have packetType with packetID"); - if (bdOp.getLenValue() == 0) + if (!packetType) + bdOp.emitError("must have packetType with packetID"); + if (bdOp.getLen() == 0) return bdOp.emitOpError( "For MM2S channels, if Buffer_Length=0 then Enable_Packet must be " "set to 0, otherwise behavior is undefined (3.7.8 arch spec)"); diff --git a/lib/Targets/AIETargetShared.cpp b/lib/Targets/AIETargetShared.cpp index e9cee214d3..d8e494e84e 100644 --- a/lib/Targets/AIETargetShared.cpp +++ b/lib/Targets/AIETargetShared.cpp @@ -86,8 +86,12 @@ static std::string tileDMATensorStr(int col, int row, int bdNum) { void generateXAieDmaSetMultiDimAddr(raw_ostream &output, int ndims, ArrayRef dims, int col, int row, int bdNum, int baseAddrA, - int offsetA, int lenA, int bytesA, + int offsetA, int lenA, + int elementWidthInBytes, const char *errorRetval) { + // libxaie requires stride in multiples of 32b + double elementWidthIn32bWords = + static_cast(elementWidthInBytes) / 4.0; std::string tensor = tileDMATensorStr(col, row, bdNum); output << "XAie_DmaTensor " << tensor << " = {};\n"; output << tensor << ".NumDim = " << std::to_string(ndims) << ";\n"; @@ -98,23 +102,34 @@ void generateXAieDmaSetMultiDimAddr(raw_ostream &output, int ndims, output << "if(NULL == " << tensor << ".Dim){\n" << " return " << errorRetval << ";\n" << "}\n"; - for (int i = 0; i < ndims; i++) { + for (size_t i = 0; i < dims.size(); i++) { + uint16_t size; + uint32_t stride; // Pass down dimensions in reverse order; in the MLIR, this allows us // to specify strides/sizes in the same order as we would access a // multi-dim C array, with the highest dimension first. - int j = ndims - i - 1; + int j = dims.size() - i - 1; + if (j > 0) { + stride = + static_cast(dims[i].getStride() * elementWidthIn32bWords); + size = dims[i].getSize(); + } else { + stride = dims[i].getStride(); + size = static_cast(dims[i].getSize() * elementWidthIn32bWords); + } + stride = stride > 0 ? stride : 1; // Assume AIE-ML architecture; we assert this above output << tensor << ".Dim[" << std::to_string(j) << "].AieMlDimDesc" - << " = { /* StepSize */ " << std::to_string(dims[i].getStride()) - << ", /* Size */ " << std::to_string(dims[i].getSize()) << "};\n"; + << " = { /* Stride */ " << std::to_string(stride) << ", /* Size */ " + << std::to_string(size) << "};\n"; } + if ((baseAddrA + offsetA) % 4) + llvm::report_fatal_error("bd address must be 4B (32b) aligned"); output << "__mlir_aie_try(XAie_DmaSetMultiDimAddr(" << tileDMAInstRefStr(col, row, bdNum) << ", " << "&" << tensor << ", " << "0x" << llvm::utohexstr(baseAddrA + offsetA) << ", " - << " /* len */ " << lenA << " * " << bytesA << "));\n"; - // TODO: Probably need special handling for NOC - // TODO: Might need to adjust strides / sizes by -1 + << " /* len */ " << lenA << "));\n"; } } // namespace xilinx::AIE diff --git a/lib/Targets/AIETargetShared.h b/lib/Targets/AIETargetShared.h index f1a86af236..7c8e0977d8 100644 --- a/lib/Targets/AIETargetShared.h +++ b/lib/Targets/AIETargetShared.h @@ -34,7 +34,8 @@ std::string packetStr(int id, int type); void generateXAieDmaSetMultiDimAddr(llvm::raw_ostream &output, int ndims, llvm::ArrayRef dims, int col, int row, int bdNum, int baseAddrA, - int offsetA, int lenA, int bytesA, + int offsetA, int lenA, + int elementWidthInBytes, const char *errorRet); } // namespace AIE diff --git a/lib/Targets/AIETargetXAIEV2.cpp b/lib/Targets/AIETargetXAIEV2.cpp index c6fe403f83..b6a00d8594 100644 --- a/lib/Targets/AIETargetXAIEV2.cpp +++ b/lib/Targets/AIETargetXAIEV2.cpp @@ -89,20 +89,14 @@ mlir::LogicalResult generateDMAConfig(OpType memOp, raw_ostream &output, int packetID = 0; bool foundBd = false; int lenA = 0; - int lenB = 0; - int bytesA = 0; - int bytesB = 0; int offsetA = 0; int BaseAddrA = 0; - bool hasA = false; - bool hasB = false; + int elementWidthInBytes = 0; int ndims = 0; ArrayRef dims; // StringRef FifoMode = disable; // FIXME: when to enable FIFO mode? for (auto op : block.template getOps()) { foundBd = true; - ShapedType bufferType = - op.getBuffer().getType().template cast<::mlir::MemRefType>(); if (!targetModel.isShimNOCTile(col, row)) { assert(op.getBufferOp().getAddress() && "buffer must have address assigned"); @@ -121,13 +115,11 @@ mlir::LogicalResult generateDMAConfig(OpType memOp, raw_ostream &output, } } - lenA = op.getLenValue(); - bytesA = bufferType.getElementTypeBitWidth() / 8; - offsetA = op.getOffsetValue() * bytesA; - hasA = true; - - if (op.getDimensions()) { - dims = *op.getDimensions(); + lenA = op.getLenInBytes(); + offsetA = op.getOffsetInBytes(); + elementWidthInBytes = op.getBufferElementTypeWidthInBytes(); + if (op.getDims()) { + dims = *op.getDims(); ndims = dims.size(); } } @@ -137,13 +129,6 @@ mlir::LogicalResult generateDMAConfig(OpType memOp, raw_ostream &output, "buffer descriptor. This is currently only " "supported for AIE-ML devices."); - if (hasA && hasB) { - if (lenA != lenB) - llvm::errs() << "ABmode must have matching lengths.\n"; - if (bytesA != bytesB) - llvm::errs() << "ABmode must have matching element data types.\n"; - } - int acqValue = 0, relValue = 0; bool hasAcq = false, hasRel = false; int acqLockID = 0, relLockID = 0; @@ -186,8 +171,6 @@ mlir::LogicalResult generateDMAConfig(OpType memOp, raw_ostream &output, int bdNum = blockMap[&block]; if (foundBd) { - // TODO AB mode separated - // TODO For now, we are going to name each dma desc with loc and bd // which we assume is unique. This is strictly not enforced but in // practice, this is true @@ -214,7 +197,7 @@ mlir::LogicalResult generateDMAConfig(OpType memOp, raw_ostream &output, << tileDMAInstRefStr(col, row, bdNum) << ", /* addrA */ " << "mlir_aie_external_get_addr_myBuffer_" << col << row << "_" << bdNum << "(), " - << " /* len */ " << lenA << " * " << bytesA << "));\n"; + << " /* len */ " << lenA << "));\n"; output << "__mlir_aie_try(XAie_DmaSetAxi(" << tileDMAInstRefStr(col, row, bdNum) << ", " << "/* smid */ 0, " @@ -226,10 +209,11 @@ mlir::LogicalResult generateDMAConfig(OpType memOp, raw_ostream &output, output << "__mlir_aie_try(XAie_DmaSetAddrLen(" << tileDMAInstRefStr(col, row, bdNum) << ", /* addrA */ " << "0x" << llvm::utohexstr(BaseAddrA + offsetA) << ", " - << " /* len */ " << lenA << " * " << bytesA << "));\n"; + << " /* len */ " << lenA << "));\n"; } else generateXAieDmaSetMultiDimAddr(output, ndims, dims, col, row, bdNum, - BaseAddrA, offsetA, lenA, bytesA, "1"); + BaseAddrA, offsetA, lenA, + elementWidthInBytes, "1"); if (block.getNumSuccessors() > 0) { Block *nextBlock = block.getSuccessors()[0]; // should have only one @@ -560,7 +544,7 @@ mlir::LogicalResult AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output) { blockMap[&block] = bdNum; uint64_t offset = 0; for (auto op : block.getOps()) { - offset = op.getOffsetValue(); + offset = op.getOffsetInBytes(); auto buffer = cast(op.getBuffer().getDefiningOp()); @@ -809,7 +793,7 @@ mlir::LogicalResult AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output) { int row = coord.row; auto loc = tileLocStr(col, row); - auto bufferAccessor = [&](std::optional tile, BufferOp buf) { + auto bufferAccessor = [&](BufferOp buf) { // int32_t mlir_aie_read_buffer_a13(int index) { // void mlir_aie_write_buffer_a13(int index, int32_t value) { std::string bufName(buf.name().getValue()); @@ -866,7 +850,7 @@ mlir::LogicalResult AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output) { // if(tiles.count(tile.getValue())) for (auto buf : buffers[tileOp]) - bufferAccessor(coord, buf); + bufferAccessor(buf); } auto lockAccessor = [&](LockOp lock) { diff --git a/lib/Targets/CMakeLists.txt b/lib/Targets/CMakeLists.txt index af6556f80e..c884ebc32c 100644 --- a/lib/Targets/CMakeLists.txt +++ b/lib/Targets/CMakeLists.txt @@ -7,9 +7,7 @@ add_subdirectory(AIEVecToCpp) -set(LLVM_OPTIONAL_SOURCES AIETargetAirbin.cpp) - -set(_sources +add_mlir_library(AIETargets AIETargets.cpp AIETargetBCF.cpp AIETargetCDODirect.cpp @@ -21,15 +19,8 @@ set(_sources ADFGenerateCppGraph.cpp AIEFlowsToJSON.cpp AIELLVMLink.cpp -) - -if(AIE_ENABLE_AIRBIN) - list(APPEND _sources AIETargetAirbin.cpp) -endif() - -add_mlir_library(AIETargets - ${_sources} + PARTIAL_SOURCES_INTENDED ENABLE_AGGREGATION ADDITIONAL_HEADER_DIRS @@ -55,6 +46,26 @@ add_mlir_library(AIETargets ADF ) +if(AIE_ENABLE_AIRBIN) + add_mlir_library(AIETargetAirbin + AIETargetAirbin.cpp + + PARTIAL_SOURCES_INTENDED + + LINK_COMPONENTS + Support + + LINK_LIBS PRIVATE + elf + + LINK_LIBS PUBLIC + AIE + AIEX + ) + target_link_libraries(AIETargets PUBLIC AIETargetAirbin) + target_compile_definitions(obj.AIETargets PRIVATE AIE_ENABLE_AIRBIN) +endif() + target_link_libraries(AIETargets PRIVATE xaienginecdo_static) add_dependencies(obj.AIETargets xaienginecdo_static xaienginecdo_static-headers) # for #include @@ -62,7 +73,3 @@ set(BOOTGEN_SOURCE_DIR ${PROJECT_SOURCE_DIR}/third_party/bootgen) target_include_directories(AIETargets SYSTEM PRIVATE ${BOOTGEN_SOURCE_DIR}) target_include_directories(obj.AIETargets SYSTEM PRIVATE ${BOOTGEN_SOURCE_DIR}) -if(AIE_ENABLE_AIRBIN) - target_link_libraries(AIETargets PRIVATE elf) - target_compile_definitions(obj.AIETargets PRIVATE AIE_ENABLE_AIRBIN) -endif() diff --git a/reference_designs/MM_2x2/circuit_switched_version/aie.mlir b/reference_designs/MM_2x2/circuit_switched_version/aie.mlir index dd611979a8..2f346bb49f 100755 --- a/reference_designs/MM_2x2/circuit_switched_version/aie.mlir +++ b/reference_designs/MM_2x2/circuit_switched_version/aie.mlir @@ -104,22 +104,22 @@ module @MM_2x2 { aie.dma_start("S2MM", 1, ^bd7, ^end) ^bd4: aie.use_lock(%lock60_0, "Acquire", 1) - aie.dma_bd(%buffer0 : memref<1024xi32>, 0, 1024) //send LHS_tile0 + aie.dma_bd(%buffer0 : memref<1024xi32>) { offset = 0 : i32, len = 1024 : i32 } //send LHS_tile0 aie.use_lock(%lock60_0, "Release", 0) aie.next_bd ^bd4 ^bd5: aie.use_lock(%lock60_1, "Acquire", 1) - aie.dma_bd(%buffer1 : memref<1024xi32>, 0, 1024) //send LHS_tile1 + aie.dma_bd(%buffer1 : memref<1024xi32>) { offset = 0 : i32, len = 1024 : i32 } //send LHS_tile1 aie.use_lock(%lock60_1, "Release", 0) aie.next_bd ^bd5 ^bd6: aie.use_lock(%lock60_2, "Acquire", 1) - aie.dma_bd(%buffer6 : memref<1025xi32>, 0, 1025) //send Out_tile0 + aie.dma_bd(%buffer6 : memref<1025xi32>) { offset = 0 : i32, len = 1025 : i32 } //send Out_tile0 aie.use_lock(%lock60_2, "Release", 0) aie.next_bd ^bd6 ^bd7: aie.use_lock(%lock60_3, "Acquire", 1) - aie.dma_bd(%buffer7 : memref<1025xi32>, 0, 1025) //send Out_tile1 + aie.dma_bd(%buffer7 : memref<1025xi32>) { offset = 0 : i32, len = 1025 : i32 } //send Out_tile1 aie.use_lock(%lock60_3, "Release", 0) aie.next_bd ^bd7 ^end: @@ -132,12 +132,12 @@ module @MM_2x2 { aie.dma_start("MM2S", 1, ^bd5, ^end) ^bd4: aie.use_lock(%lock70_0, "Acquire", 1) - aie.dma_bd(%buffer2 : memref<1024xi32>, 0, 1024) //send RHS_tile0 + aie.dma_bd(%buffer2 : memref<1024xi32>) { offset = 0 : i32, len = 1024 : i32 } //send RHS_tile0 aie.use_lock(%lock70_0, "Release", 0) aie.next_bd ^bd4 ^bd5: aie.use_lock(%lock70_1, "Acquire", 1) - aie.dma_bd(%buffer3 : memref<1024xi32>, 0, 1024) //send RHS_tile1 + aie.dma_bd(%buffer3 : memref<1024xi32>) { offset = 0 : i32, len = 1024 : i32 } //send RHS_tile1 aie.use_lock(%lock70_1, "Release", 0) aie.next_bd ^bd5 ^end: @@ -150,12 +150,12 @@ module @MM_2x2 { aie.dma_start("MM2S", 1, ^bd5, ^end) ^bd4: aie.use_lock(%lock100_0, "Acquire", 1) - aie.dma_bd(%buffer4 : memref<1024xi32>, 0, 1024) //send RHS_tile2 + aie.dma_bd(%buffer4 : memref<1024xi32>) { offset = 0 : i32, len = 1024 : i32 } //send RHS_tile2 aie.use_lock(%lock100_0, "Release", 0) aie.next_bd ^bd4 ^bd5: aie.use_lock(%lock100_1, "Acquire", 1) - aie.dma_bd(%buffer5 : memref<1024xi32>, 0, 1024) //send RHS_tile3 + aie.dma_bd(%buffer5 : memref<1024xi32>) { offset = 0 : i32, len = 1024 : i32 } //send RHS_tile3 aie.use_lock(%lock100_1, "Release", 0) aie.next_bd ^bd5 ^end: @@ -168,12 +168,12 @@ module @MM_2x2 { aie.dma_start("S2MM", 1, ^bd1, ^end) ^bd0: aie.use_lock(%lock63_0, Acquire, 0) - aie.dma_bd(%buf63_0 : memref<1024xi32>, 0, 1024) + aie.dma_bd(%buf63_0 : memref<1024xi32>) { offset = 0 : i32, len = 1024 : i32 } aie.use_lock(%lock63_0, Release, 1) aie.next_bd ^bd0 ^bd1: aie.use_lock(%lock63_1, Acquire, 0) - aie.dma_bd(%buf63_1 : memref<1024xi32>, 0, 1024) + aie.dma_bd(%buf63_1 : memref<1024xi32>) { offset = 0 : i32, len = 1024 : i32 } aie.use_lock(%lock63_1, Release, 1) aie.next_bd ^bd1 ^end: @@ -186,19 +186,19 @@ module @MM_2x2 { aie.dma_start("S2MM", 1, ^bd1, ^dma1) ^bd0: aie.use_lock(%lock64_0, Acquire, 0) - aie.dma_bd(%buf64_0 : memref<1024xi32>, 0, 1024) + aie.dma_bd(%buf64_0 : memref<1024xi32>) { offset = 0 : i32, len = 1024 : i32 } aie.use_lock(%lock64_0, Release, 1) aie.next_bd ^bd0 ^bd1: aie.use_lock(%lock64_1, Acquire, 0) - aie.dma_bd(%buf64_1 : memref<1024xi32>, 0, 1024) + aie.dma_bd(%buf64_1 : memref<1024xi32>) { offset = 0 : i32, len = 1024 : i32 } aie.use_lock(%lock64_1, Release, 1) aie.next_bd ^bd1 ^dma1: aie.dma_start("MM2S", 0, ^bd2, ^end) ^bd2: aie.use_lock(%lock64_2, Acquire, 1) - aie.dma_bd(%buf64_2 : memref<1024xi32>, 0, 1024) + aie.dma_bd(%buf64_2 : memref<1024xi32>) { offset = 0 : i32, len = 1024 : i32 } aie.use_lock(%lock64_2, Release, 0) aie.next_bd ^bd2 ^end: @@ -237,12 +237,12 @@ module @MM_2x2 { aie.dma_start("S2MM", 1, ^bd1, ^end) ^bd0: aie.use_lock(%lock73_0, Acquire, 0) - aie.dma_bd(%buf73_0 : memref<1024xi32>, 0, 1024) + aie.dma_bd(%buf73_0 : memref<1024xi32>) { offset = 0 : i32, len = 1024 : i32 } aie.use_lock(%lock73_0, Release, 1) aie.next_bd ^bd0 ^bd1: aie.use_lock(%lock73_1, Acquire, 0) - aie.dma_bd(%buf73_1 : memref<1024xi32>, 0, 1024) + aie.dma_bd(%buf73_1 : memref<1024xi32>) { offset = 0 : i32, len = 1024 : i32 } aie.use_lock(%lock73_1, Release, 1) aie.next_bd ^bd1 ^end: @@ -255,19 +255,19 @@ module @MM_2x2 { aie.dma_start("S2MM", 1, ^bd1, ^dma1) ^bd0: aie.use_lock(%lock74_0, Acquire, 0) - aie.dma_bd(%buf74_0 : memref<1024xi32>, 0, 1024) + aie.dma_bd(%buf74_0 : memref<1024xi32>) { offset = 0 : i32, len = 1024 : i32 } aie.use_lock(%lock74_0, Release, 1) aie.next_bd ^bd0 ^bd1: aie.use_lock(%lock74_1, Acquire, 0) - aie.dma_bd(%buf74_1 : memref<1024xi32>, 0, 1024) + aie.dma_bd(%buf74_1 : memref<1024xi32>) { offset = 0 : i32, len = 1024 : i32 } aie.use_lock(%lock74_1, Release, 1) aie.next_bd ^bd1 ^dma1: aie.dma_start("MM2S", 0, ^bd2, ^end) ^bd2: aie.use_lock(%lock74_2, Acquire, 1) - aie.dma_bd(%buf74_2 : memref<1024xi32>, 0, 1024) + aie.dma_bd(%buf74_2 : memref<1024xi32>) { offset = 0 : i32, len = 1024 : i32 } aie.use_lock(%lock74_2, Release, 0) aie.next_bd ^bd2 ^end: diff --git a/reference_designs/MM_2x2/packet_switched_version/aie.mlir b/reference_designs/MM_2x2/packet_switched_version/aie.mlir index 4b3a9ec914..457f1ba0b1 100644 --- a/reference_designs/MM_2x2/packet_switched_version/aie.mlir +++ b/reference_designs/MM_2x2/packet_switched_version/aie.mlir @@ -105,25 +105,25 @@ module @MM_2x2 { ^bd4: aie.use_lock(%lock60_0, "Acquire", 1) aie.dma_bd_packet(0x0, 0x0) - aie.dma_bd(%buffer0 : memref<1024xi32>, 0, 1024) //send LHS_tile0 with Pack_ID=0 + aie.dma_bd(%buffer0 : memref<1024xi32>) { offset = 0 : i32, len = 1024 : i32 } //send LHS_tile0 with Pack_ID=0 aie.use_lock(%lock60_0, "Release", 0) aie.next_bd ^bd5 ^bd5: aie.use_lock(%lock60_1, "Acquire", 1) aie.dma_bd_packet(0x1, 0x1) - aie.dma_bd(%buffer1 : memref<1024xi32>, 0, 1024) //send LHS_tile1 with Pack_ID=1 + aie.dma_bd(%buffer1 : memref<1024xi32>) { offset = 0 : i32, len = 1024 : i32 } //send LHS_tile1 with Pack_ID=1 aie.use_lock(%lock60_1, "Release", 0) aie.next_bd ^bd4 ^bd6: aie.use_lock(%lock60_2, "Acquire", 1) aie.dma_bd_packet(0x2, 0x2) - aie.dma_bd(%buffer2 : memref<1024xi32>, 0, 1024) //send RHS_tile0 with Pack_ID=2 + aie.dma_bd(%buffer2 : memref<1024xi32>) { offset = 0 : i32, len = 1024 : i32 } //send RHS_tile0 with Pack_ID=2 aie.use_lock(%lock60_2, "Release", 0) aie.next_bd ^bd7 ^bd7: aie.use_lock(%lock60_3, "Acquire", 1) aie.dma_bd_packet(0x3, 0x3) - aie.dma_bd(%buffer3 : memref<1024xi32>, 0, 1024) //send RHS_tile1 with Pack_ID=3 + aie.dma_bd(%buffer3 : memref<1024xi32>) { offset = 0 : i32, len = 1024 : i32 } //send RHS_tile1 with Pack_ID=3 aie.use_lock(%lock60_3, "Release", 0) aie.next_bd ^bd6 ^end: @@ -137,20 +137,20 @@ module @MM_2x2 { ^bd4: aie.use_lock(%lock70_0, "Acquire", 1) aie.dma_bd_packet(0x4, 0x4) - aie.dma_bd(%buffer4 : memref<1024xi32>, 0, 1024) //send RHS_tile2 with Pack_ID=4 + aie.dma_bd(%buffer4 : memref<1024xi32>) { offset = 0 : i32, len = 1024 : i32 } //send RHS_tile2 with Pack_ID=4 aie.use_lock(%lock70_0, "Release", 0) aie.next_bd ^bd5 ^bd5: aie.use_lock(%lock70_1, "Acquire", 1) aie.dma_bd_packet(0x5, 0x5) - aie.dma_bd(%buffer5 : memref<1024xi32>, 0, 1024) //send RHS_tile3 with Pack_ID=5 + aie.dma_bd(%buffer5 : memref<1024xi32>) { offset = 0 : i32, len = 1024 : i32 } //send RHS_tile3 with Pack_ID=5 aie.use_lock(%lock70_1, "Release", 0) aie.next_bd ^bd4 ^bd6: - aie.dma_bd(%buffer6 : memref<1025xi32>, 0, 1025) //send Out_tile0 with Pack_ID=6 + aie.dma_bd(%buffer6 : memref<1025xi32>) { offset = 0 : i32, len = 1025 : i32 } //send Out_tile0 with Pack_ID=6 aie.next_bd ^bd7 ^bd7: - aie.dma_bd(%buffer7 : memref<1025xi32>, 0, 1025) //send Out_tile1 with Pack_ID=7 + aie.dma_bd(%buffer7 : memref<1025xi32>) { offset = 0 : i32, len = 1025 : i32 } //send Out_tile1 with Pack_ID=7 aie.next_bd ^bd6 ^end: aie.end @@ -165,12 +165,12 @@ module @MM_2x2 { aie.dma_start("S2MM", 1, ^bd1, ^end) ^bd0: aie.use_lock(%lock63_0, Acquire, 0) - aie.dma_bd(%buf63_0 : memref<1024xi32>, 0, 1024) + aie.dma_bd(%buf63_0 : memref<1024xi32>) { offset = 0 : i32, len = 1024 : i32 } aie.use_lock(%lock63_0, Release, 1) aie.next_bd ^bd0 ^bd1: aie.use_lock(%lock63_1, Acquire, 0) - aie.dma_bd(%buf63_1 : memref<1024xi32>, 0, 1024) + aie.dma_bd(%buf63_1 : memref<1024xi32>) { offset = 0 : i32, len = 1024 : i32 } aie.use_lock(%lock63_1, Release, 1) aie.next_bd ^bd1 ^end: @@ -187,12 +187,12 @@ module @MM_2x2 { aie.dma_start("S2MM", 1, ^bd1, ^dma1) ^bd0: aie.use_lock(%lock64_0, Acquire, 0) - aie.dma_bd(%buf64_0 : memref<1024xi32>, 0, 1024) + aie.dma_bd(%buf64_0 : memref<1024xi32>) { offset = 0 : i32, len = 1024 : i32 } aie.use_lock(%lock64_0, Release, 1) aie.next_bd ^bd0 ^bd1: aie.use_lock(%lock64_1, Acquire, 0) - aie.dma_bd(%buf64_1 : memref<1024xi32>, 0, 1024) + aie.dma_bd(%buf64_1 : memref<1024xi32>) { offset = 0 : i32, len = 1024 : i32 } aie.use_lock(%lock64_1, Release, 1) aie.next_bd ^bd1 ^dma1: @@ -200,7 +200,7 @@ module @MM_2x2 { ^bd2: aie.use_lock(%lock64_2, Acquire, 1) aie.dma_bd_packet(0x0, 0x6) - aie.dma_bd(%buf64_2 : memref<1024xi32>, 0, 1024) + aie.dma_bd(%buf64_2 : memref<1024xi32>) { offset = 0 : i32, len = 1024 : i32 } aie.use_lock(%lock64_2, Release, 0) aie.next_bd ^bd2 ^end: @@ -247,12 +247,12 @@ module @MM_2x2 { aie.dma_start("S2MM", 1, ^bd1, ^end) ^bd0: aie.use_lock(%lock73_0, Acquire, 0) - aie.dma_bd(%buf73_0 : memref<1024xi32>, 0, 1024) + aie.dma_bd(%buf73_0 : memref<1024xi32>) { offset = 0 : i32, len = 1024 : i32 } aie.use_lock(%lock73_0, Release, 1) aie.next_bd ^bd0 ^bd1: aie.use_lock(%lock73_1, Acquire, 0) - aie.dma_bd(%buf73_1 : memref<1024xi32>, 0, 1024) + aie.dma_bd(%buf73_1 : memref<1024xi32>) { offset = 0 : i32, len = 1024 : i32 } aie.use_lock(%lock73_1, Release, 1) aie.next_bd ^bd1 ^end: @@ -269,12 +269,12 @@ module @MM_2x2 { aie.dma_start("S2MM", 1, ^bd1, ^dma1) ^bd0: aie.use_lock(%lock74_0, Acquire, 0) - aie.dma_bd(%buf74_0 : memref<1024xi32>, 0, 1024) + aie.dma_bd(%buf74_0 : memref<1024xi32>) { offset = 0 : i32, len = 1024 : i32 } aie.use_lock(%lock74_0, Release, 1) aie.next_bd ^bd0 ^bd1: aie.use_lock(%lock74_1, Acquire, 0) - aie.dma_bd(%buf74_1 : memref<1024xi32>, 0, 1024) + aie.dma_bd(%buf74_1 : memref<1024xi32>) { offset = 0 : i32, len = 1024 : i32 } aie.use_lock(%lock74_1, Release, 1) aie.next_bd ^bd1 ^dma1: @@ -282,7 +282,7 @@ module @MM_2x2 { ^bd2: aie.use_lock(%lock74_2, Acquire, 1) aie.dma_bd_packet(0x0, 0x7) - aie.dma_bd(%buf74_2 : memref<1024xi32>, 0, 1024) + aie.dma_bd(%buf74_2 : memref<1024xi32>) { offset = 0 : i32, len = 1024 : i32 } aie.use_lock(%lock74_2, Release, 0) aie.next_bd ^bd2 ^end: diff --git a/reference_designs/autocorrelation/aie.mlir b/reference_designs/autocorrelation/aie.mlir index d7866857ce..c4516d9f5c 100755 --- a/reference_designs/autocorrelation/aie.mlir +++ b/reference_designs/autocorrelation/aie.mlir @@ -57,12 +57,12 @@ module @autocorrelation { aie.dma_start("S2MM", 0, ^bdout, ^end) ^bdin: aie.use_lock(%input_lock, "Acquire", 1) - aie.dma_bd(%input : memref<1024xi32>, 0, 1024) + aie.dma_bd(%input : memref<1024xi32>) { offset = 0 : i32, len = 1024 : i32 } aie.use_lock(%input_lock, "Release", 0) aie.next_bd ^end ^bdout: aie.use_lock(%output_lock, "Acquire", 0) - aie.dma_bd(%output : memref<1024xi32>, 0, 1024) + aie.dma_bd(%output : memref<1024xi32>) { offset = 0 : i32, len = 1024 : i32 } aie.use_lock(%output_lock, "Release", 1) aie.next_bd ^end ^end: @@ -85,12 +85,12 @@ module @autocorrelation { aie.dma_start("MM2S", 0, ^bd1, ^end) ^bd0: aie.use_lock(%buf1_in_lock, Acquire, 0) - aie.dma_bd(%buf1_in : memref<1024xi32>, 0, 1024) + aie.dma_bd(%buf1_in : memref<1024xi32>) { offset = 0 : i32, len = 1024 : i32 } aie.use_lock(%buf1_in_lock, Release, 1) aie.next_bd ^end ^bd1: aie.use_lock(%buf1_out_lock, Acquire, 1) - aie.dma_bd(%buf1_out : memref<1024xi32>, 0, 1024) + aie.dma_bd(%buf1_out : memref<1024xi32>) { offset = 0 : i32, len = 1024 : i32 } aie.use_lock(%buf1_out_lock, Release, 0) aie.next_bd ^end ^end: @@ -101,7 +101,7 @@ module @autocorrelation { aie.dma_start("S2MM", 0, ^bd0, ^end) ^bd0: aie.use_lock(%buf2_in_lock, Acquire, 0) - aie.dma_bd(%buf2_in : memref<1024xi32>, 0, 1024) + aie.dma_bd(%buf2_in : memref<1024xi32>) { offset = 0 : i32, len = 1024 : i32 } aie.use_lock(%buf2_in_lock, Release, 1) aie.next_bd ^end ^end: @@ -112,7 +112,7 @@ module @autocorrelation { aie.dma_start("S2MM", 0, ^bd0, ^end) ^bd0: aie.use_lock(%buf3_in_lock, Acquire, 0) - aie.dma_bd(%buf3_in : memref<1024xi32>, 0, 1024) + aie.dma_bd(%buf3_in : memref<1024xi32>) { offset = 0 : i32, len = 1024 : i32 } aie.use_lock(%buf3_in_lock, Release, 1) aie.next_bd ^end ^end: @@ -123,7 +123,7 @@ module @autocorrelation { aie.dma_start("S2MM", 0, ^bd0, ^end) ^bd0: aie.use_lock(%buf4_in_lock, Acquire, 0) - aie.dma_bd(%buf4_in : memref<1024xi32>, 0, 1024) + aie.dma_bd(%buf4_in : memref<1024xi32>) { offset = 0 : i32, len = 1024 : i32 } aie.use_lock(%buf4_in_lock, Release, 1) aie.next_bd ^end ^end: diff --git a/reference_designs/idct/aie.mlir b/reference_designs/idct/aie.mlir index d2fab524f8..465e28bc66 100644 --- a/reference_designs/idct/aie.mlir +++ b/reference_designs/idct/aie.mlir @@ -136,22 +136,22 @@ module @idct { %dstDma = aie.dma_start("MM2S", 1, ^bd2, ^end) ^bd0: aie.use_lock(%lock_73_a_ping, "Acquire", 0) - aie.dma_bd(%buf_73_aping : memref<64xi16>, 0, 64) + aie.dma_bd(%buf_73_aping : memref<64xi16>) { offset = 0 : i32, len = 64 : i32 } aie.use_lock(%lock_73_a_ping, "Release", 1) aie.next_bd ^bd1 ^bd1: aie.use_lock(%lock_73_a_pong, "Acquire", 0) - aie.dma_bd(%buf_73_apong : memref<64xi16>, 0, 64) + aie.dma_bd(%buf_73_apong : memref<64xi16>) { offset = 0 : i32, len = 64 : i32 } aie.use_lock(%lock_73_a_pong, "Release", 1) aie.next_bd ^bd0 ^bd2: aie.use_lock(%lock_73_b_ping, "Acquire", 1) - aie.dma_bd(%buf_73_bping : memref<64xi16>, 0, 64) + aie.dma_bd(%buf_73_bping : memref<64xi16>) { offset = 0 : i32, len = 64 : i32 } aie.use_lock(%lock_73_b_ping, "Release", 0) aie.next_bd ^bd3 ^bd3: aie.use_lock(%lock_73_b_pong, "Acquire", 1) - aie.dma_bd(%buf_73_bpong : memref<64xi16>, 0, 64) + aie.dma_bd(%buf_73_bpong : memref<64xi16>) { offset = 0 : i32, len = 64 : i32 } aie.use_lock(%lock_73_b_pong, "Release", 0) aie.next_bd ^bd2 ^end: @@ -165,22 +165,22 @@ module @idct { %dstDma = aie.dma_start("MM2S", 1, ^bd2, ^end) ^bd0: aie.use_lock(%lock_74_a_ping, "Acquire", 0) - aie.dma_bd(%buf_74_aping : memref<64xi16>, 0, 64) + aie.dma_bd(%buf_74_aping : memref<64xi16>) { offset = 0 : i32, len = 64 : i32 } aie.use_lock(%lock_74_a_ping, "Release", 1) aie.next_bd ^bd1 ^bd1: aie.use_lock(%lock_74_a_pong, "Acquire", 0) - aie.dma_bd(%buf_74_apong : memref<64xi16>, 0, 64) + aie.dma_bd(%buf_74_apong : memref<64xi16>) { offset = 0 : i32, len = 64 : i32 } aie.use_lock(%lock_74_a_pong, "Release", 1) aie.next_bd ^bd0 ^bd2: aie.use_lock(%lock_74_b_ping, "Acquire", 1) - aie.dma_bd(%buf_74_bping : memref<64xi16>, 0, 64) + aie.dma_bd(%buf_74_bping : memref<64xi16>) { offset = 0 : i32, len = 64 : i32 } aie.use_lock(%lock_74_b_ping, "Release", 0) aie.next_bd ^bd3 ^bd3: aie.use_lock(%lock_74_b_pong, "Acquire", 1) - aie.dma_bd(%buf_74_bpong : memref<64xi16>, 0, 64) + aie.dma_bd(%buf_74_bpong : memref<64xi16>) { offset = 0 : i32, len = 64 : i32 } aie.use_lock(%lock_74_b_pong, "Release", 0) aie.next_bd ^bd2 ^end: @@ -194,22 +194,22 @@ module @idct { %dstDma = aie.dma_start("MM2S", 1, ^bd2, ^end) ^bd0: aie.use_lock(%lock_75_a_ping, "Acquire", 0) - aie.dma_bd(%buf_75_aping : memref<64xi16>, 0, 64) + aie.dma_bd(%buf_75_aping : memref<64xi16>) { offset = 0 : i32, len = 64 : i32 } aie.use_lock(%lock_75_a_ping, "Release", 1) aie.next_bd ^bd1 ^bd1: aie.use_lock(%lock_75_a_pong, "Acquire", 0) - aie.dma_bd(%buf_75_apong : memref<64xi16>, 0, 64) + aie.dma_bd(%buf_75_apong : memref<64xi16>) { offset = 0 : i32, len = 64 : i32 } aie.use_lock(%lock_75_a_pong, "Release", 1) aie.next_bd ^bd0 ^bd2: aie.use_lock(%lock_75_b_ping, "Acquire", 1) - aie.dma_bd(%buf_75_bping : memref<64xi16>, 0, 64) + aie.dma_bd(%buf_75_bping : memref<64xi16>) { offset = 0 : i32, len = 64 : i32 } aie.use_lock(%lock_75_b_ping, "Release", 0) aie.next_bd ^bd3 ^bd3: aie.use_lock(%lock_75_b_pong, "Acquire", 1) - aie.dma_bd(%buf_75_bpong : memref<64xi16>, 0, 64) + aie.dma_bd(%buf_75_bpong : memref<64xi16>) { offset = 0 : i32, len = 64 : i32 } aie.use_lock(%lock_75_b_pong, "Release", 0) aie.next_bd ^bd2 ^end: @@ -230,12 +230,12 @@ module @idct { aie.dma_start(S2MM, 0, ^bd1, ^end) ^bd0: aie.use_lock(%lock1, "Acquire", 1) - aie.dma_bd(%buffer_in : memref<512 x i16>, 0, 512) + aie.dma_bd(%buffer_in : memref<512 x i16>) { offset = 0 : i32, len = 512 : i32 } aie.use_lock(%lock1, "Release", 0) aie.next_bd ^bd0 ^bd1: aie.use_lock(%lock2, "Acquire", 1) - aie.dma_bd(%buffer_out : memref<512 x i16>, 0, 512) + aie.dma_bd(%buffer_out : memref<512 x i16>) { offset = 0 : i32, len = 512 : i32 } aie.use_lock(%lock2, "Release", 0) aie.next_bd ^bd1 ^end: diff --git a/reference_designs/ipu-xrt/matrix_multiplication/aie2.py b/reference_designs/ipu-xrt/matrix_multiplication/aie2.py index aa82582442..46973f90a4 100644 --- a/reference_designs/ipu-xrt/matrix_multiplication/aie2.py +++ b/reference_designs/ipu-xrt/matrix_multiplication/aie2.py @@ -91,10 +91,10 @@ def device_body(): 2, memref_a_ty, [ - (m // r, r * k * word_size_in // 4), - (k // s, s * word_size_in // 4), - (r, k * word_size_in // 4), - (s * word_size_in // 4, 1), + (m // r, r * k), + (k // s, s), + (r, k), + (s, 1), ], ) object_fifo_link(inA, memA) @@ -108,10 +108,10 @@ def device_body(): 2, memref_b_ty, [ - (k // s, s * n * word_size_in // 4), - (n // t, t * word_size_in // 4), - (s, n * word_size_in // 4), - (t * word_size_in // 4, 1), + (k // s, s * n), + (n // t, t), + (s, n), + (t, 1), ], ) object_fifo_link(inB, memB) @@ -125,10 +125,10 @@ def device_body(): 2, memref_c_ty, [ - (m // r, r * n * word_size_out // 4), - (r, t * word_size_out // 4), - (n // t, r * t * word_size_out // 4), - (t * word_size_out // 4, 1), + (m // r, r * n), + (r, t), + (n // t, r * t), + (t, 1), ], ) object_fifo_link(memC, outC) diff --git a/reference_designs/ipu-xrt/matrix_multiplication_array/aie2.py b/reference_designs/ipu-xrt/matrix_multiplication_array/aie2.py index 7ced36a8ed..69a3c52394 100644 --- a/reference_designs/ipu-xrt/matrix_multiplication_array/aie2.py +++ b/reference_designs/ipu-xrt/matrix_multiplication_array/aie2.py @@ -197,10 +197,10 @@ def device_body(): 2, memRef_A_ty, [ - (m // r, r * k * word_size_in // 4), - (k // s, s * word_size_in // 4), - (r, k * word_size_in // 4), - (s * word_size_in // 4, 1), + (m // r, r * k), + (k // s, s), + (r, k), + (s, 1), ], ) object_fifo_link(inA_fifo_names[i], memA_fifo_names[i]) @@ -221,10 +221,10 @@ def device_body(): 2, memRef_B_ty, [ - (k // s, s * n * word_size_in // 4), - (n // t, t * word_size_in // 4), - (s, n * word_size_in // 4), - (t * word_size_in // 4, 1), + (k // s, s * n), + (n // t, t), + (s, n), + (t, 1), ], ) object_fifo_link(inB_fifo_names[i], memB_fifo_names[i]) @@ -246,10 +246,10 @@ def device_body(): 2, memRef_outC_ty, [ - (m // r, r * n * word_size_out // 4), - (r, t * word_size_out // 4), - (n // t, r * t * word_size_out // 4), - (t * word_size_out // 4, 1), + (m // r, r * n), + (r, t), + (n // t, r * t), + (t, 1), ], ) object_fifo_link(memC_fifo_names[i], outC_fifo_names[i]) diff --git a/reference_designs/ipu-xrt/matrix_multiplication_column/aie2.py b/reference_designs/ipu-xrt/matrix_multiplication_column/aie2.py index 5838dc598b..ed3eab17ab 100644 --- a/reference_designs/ipu-xrt/matrix_multiplication_column/aie2.py +++ b/reference_designs/ipu-xrt/matrix_multiplication_column/aie2.py @@ -102,10 +102,10 @@ def device_body(): 2, memRef_A_ty, [ - (m // r, r * k * word_size_in // 4), - (k // s, s * word_size_in // 4), - (r, k * word_size_in // 4), - (s * word_size_in // 4, 1), + (m // r, r * k), + (k // s, s), + (r, k), + (s, 1), ], ) object_fifo_link(inA, inA_fifo_names[0:n_cores]) @@ -119,10 +119,10 @@ def device_body(): 2, memRef_B_ty, [ - (k // s, s * n * word_size_in // 4), - (n // t, t * word_size_in // 4), - (s, n * word_size_in // 4), - (t * word_size_in // 4, 1), + (k // s, s * n), + (n // t, t), + (s, n), + (t, 1), ], ) object_fifo_link(inB, [inB_fifo_names[0]]) @@ -139,10 +139,10 @@ def device_body(): 2, memRef_outC_ty, [ - (m // r, r * n * word_size_out // 4), - (r, t * word_size_out // 4), - (n // t, r * t * word_size_out // 4), - (t * word_size_out // 4, 1), + (m // r, r * n), + (r, t), + (n // t, r * t), + (t, 1), ], ) object_fifo_link(outC_fifo_names[0:n_cores], outC) diff --git a/reference_designs/ipu-xrt/matrix_vector_multiplication/aie2.py b/reference_designs/ipu-xrt/matrix_vector_multiplication/aie2.py index fb4a8e97e8..80b5c89613 100644 --- a/reference_designs/ipu-xrt/matrix_vector_multiplication/aie2.py +++ b/reference_designs/ipu-xrt/matrix_vector_multiplication/aie2.py @@ -103,9 +103,8 @@ def device_body(): 2, memRef_A_ty, [ - (k_in_i32s, 1), - (m, k_in_i32s), - (1, 1), + (m, k), + (k, 1), ], ) object_fifo_link( diff --git a/test/Passes/assign-bd-ids/bad_bd_assignments.mlir b/test/Passes/assign-bd-ids/bad_bd_assignments.mlir new file mode 100644 index 0000000000..25ed552183 --- /dev/null +++ b/test/Passes/assign-bd-ids/bad_bd_assignments.mlir @@ -0,0 +1,128 @@ +//===- bad_bd_assignments.mlir.mlir ----------------------------*- MLIR -*-===// +// +// This file is licensed under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +// (c) Copyright 2022 Xilinx Inc. +// +//===----------------------------------------------------------------------===// + +// RUN: aie-opt --verify-diagnostics --split-input-file %s + +module { + aie.device(ipu) { + %tile_0_2 = aie.tile(0, 2) + %double_buffer = aie.buffer(%tile_0_2) : memref<32xi32> + %lock_Y = aie.lock(%tile_0_2) {init = 0 : i32} + %mem_0_2 = aie.mem(%tile_0_2) { + %player_a = aie.dma(S2MM, 0) [{ + aie.use_lock(%lock_Y, Acquire, 0) + // expected-error@+1 {{'aie.dma_bd' op bdId attribute exceeds max: 15}} + aie.dma_bd(%double_buffer : memref<32xi32>) {bd_id = 16 : i32, next_bd_id = 1 : i32} + aie.use_lock(%lock_Y, Release, 0) + }] + aie.end + } + } +} + +// ----- + +module { + aie.device(ipu) { + %tile_0_2 = aie.tile(0, 2) + %double_buffer = aie.buffer(%tile_0_2) : memref<32xi32> + %lock_X = aie.lock(%tile_0_2) {init = 0 : i32} + %mem_0_2 = aie.mem(%tile_0_2) { + %player_a = aie.dma(S2MM, 0) [{ + aie.use_lock(%lock_X, Acquire, 1) + // expected-error@+1 {{'aie.dma_bd' op nextBdId attribute exceeds max: 15}} + aie.dma_bd(%double_buffer : memref<32xi32>) {bd_id = 1 : i32, next_bd_id = 16 : i32} + aie.use_lock(%lock_X, Release, -1) + }] + aie.end + } + } +} + +// ----- + +module { + aie.device(ipu) { + %tile_0_1 = aie.tile(0, 1) + %buffer_0_1 = aie.buffer(%tile_0_1) : memref<32xi32> + %memtile_dma_0_1 = aie.memtile_dma(%tile_0_1) { + %lock_0_1 = aie.lock(%tile_0_1) {init = 1 : i32} + %lock_0_1_0 = aie.lock(%tile_0_1) {init = 0 : i32} + %0 = aie.dma(S2MM, 0) [{ + aie.use_lock(%lock_0_1, AcquireGreaterEqual) + // expected-error@+1 {{'aie.dma_bd' op bdId attribute exceeds max: 47}} + aie.dma_bd(%buffer_0_1 : memref<32xi32>) {bd_id = 48 : i32, next_bd_id = 1 : i32} + aie.use_lock(%lock_0_1_0, Release) + }] + aie.end + } + } +} + +// ----- + +module { + aie.device(ipu) { + %tile_0_1 = aie.tile(0, 1) + %memtile_dma_0_1 = aie.memtile_dma(%tile_0_1) { + %lock_0_1 = aie.lock(%tile_0_1) {init = 1 : i32} + %lock_0_1_0 = aie.lock(%tile_0_1) {init = 0 : i32} + %buffer_0_1 = aie.buffer(%tile_0_1) : memref<32xi32> + %0 = aie.dma(S2MM, 0) [{ + aie.use_lock(%lock_0_1, AcquireGreaterEqual) + // expected-error@+1 {{'aie.dma_bd' op nextBdId attribute exceeds max: 47}} + aie.dma_bd(%buffer_0_1 : memref<32xi32>) {bd_id = 1 : i32, next_bd_id = 48 : i32} + aie.use_lock(%lock_0_1_0, Release) + }] + aie.end + } + } +} + + +// ----- + +module { + aie.device(ipu) { + %tile_0_1 = aie.tile(0, 1) + %memtile_dma_0_1 = aie.memtile_dma(%tile_0_1) { + %lock_0_1 = aie.lock(%tile_0_1) {init = 1 : i32} + %lock_0_1_0 = aie.lock(%tile_0_1) {init = 0 : i32} + %buffer_0_1 = aie.buffer(%tile_0_1) : memref<32xi32> + %0 = aie.dma(S2MM, 0) [{ + aie.use_lock(%lock_0_1, AcquireGreaterEqual) + // expected-error@+1 {{'aie.dma_bd' op nextBdId attribute exceeds max: 47}} + aie.dma_bd(%buffer_0_1 : memref<32xi32>) {bd_id = 1 : i32, next_bd_id = 48 : i32} + aie.use_lock(%lock_0_1_0, Release) + }] + aie.end + } + } +} + +// ----- + +module { + aie.device(ipu) { + %tile_0_1 = aie.tile(0, 1) + %memtile_dma_0_1 = aie.memtile_dma(%tile_0_1) { + %lock_0_1 = aie.lock(%tile_0_1) {init = 1 : i32} + %lock_0_1_0 = aie.lock(%tile_0_1) {init = 0 : i32} + %buffer_0_1 = aie.buffer(%tile_0_1) : memref<128xi16> + %0 = aie.dma(S2MM, 0) [{ + aie.use_lock(%lock_0_1, AcquireGreaterEqual) + // expected-error@+1 {{'aie.dma_bd' op transfer length must be multiple of 4 (i.e., represent 4 byte aligned address)}} + aie.dma_bd(%buffer_0_1 : memref<128xi16>) { len = 129 : i32 } + aie.use_lock(%lock_0_1_0, Release) + }] + aie.end + } + } +} \ No newline at end of file diff --git a/test/Passes/assign-bd-ids/basic.mlir b/test/Passes/assign-bd-ids/basic.mlir index b306c3053e..cfcdc3bc8e 100644 --- a/test/Passes/assign-bd-ids/basic.mlir +++ b/test/Passes/assign-bd-ids/basic.mlir @@ -18,10 +18,10 @@ // CHECK: %[[VAL_4:.*]] = aie.buffer(%[[VAL_1]]) : memref<32xi32> // CHECK: %[[VAL_5:.*]] = aie.lock(%[[VAL_2]]) {init = 1 : i32, sym_name = "lock_X"} // CHECK: %[[VAL_6:.*]] = aie.lock(%[[VAL_2]]) {init = 0 : i32, sym_name = "lock_Y"} -// CHECK: aie.dma_bd(%[[VAL_3]] : memref<32xi32>, 0) {bd_id = 0 : i32, next_bd_id = 1 : i32} +// CHECK: aie.dma_bd(%[[VAL_3]] : memref<32xi32>) {bd_id = 0 : i32, next_bd_id = 1 : i32} // CHECK: aie.dma_bd(%[[VAL_3]] : memref<32xi32>) {bd_id = 1 : i32, next_bd_id = 2 : i32} // CHECK: aie.dma_bd(%[[VAL_3]] : memref<32xi32>) {bd_id = 2 : i32, next_bd_id = 0 : i32} -// CHECK: aie.dma_bd(%[[VAL_3]] : memref<32xi32>, 0) {bd_id = 3 : i32, next_bd_id = 4 : i32} +// CHECK: aie.dma_bd(%[[VAL_3]] : memref<32xi32>) {bd_id = 3 : i32, next_bd_id = 4 : i32} // CHECK: aie.dma_bd(%[[VAL_3]] : memref<32xi32>) {bd_id = 4 : i32, next_bd_id = 5 : i32} // CHECK: aie.dma_bd(%[[VAL_3]] : memref<32xi32>) {bd_id = 5 : i32, next_bd_id = 3 : i32} // CHECK: aie.dma_bd(%[[VAL_4]] : memref<32xi32>) {bd_id = 0 : i32} @@ -41,7 +41,7 @@ module { %mem_0_2 = aie.mem(%tile_0_2) { %player_a = aie.dma(S2MM, 0) {sym_name = "player_a"} [{ aie.use_lock(%lock_Y, Acquire, 0) - aie.dma_bd(%double_buffer : memref<32xi32>, 0) + aie.dma_bd(%double_buffer : memref<32xi32>) aie.use_lock(%lock_Y, Release, 0) }, { aie.use_lock(%lock_X, Acquire, 1) @@ -54,7 +54,7 @@ module { }] %player_b = aie.dma(S2MM, 1) {sym_name = "player_b"} [{ aie.use_lock(%lock_Y, Acquire, 1) - aie.dma_bd(%double_buffer : memref<32xi32>, 0) + aie.dma_bd(%double_buffer : memref<32xi32>) aie.use_lock(%lock_Y, Release, 0) }, { aie.use_lock(%lock_X, Acquire, 1) @@ -104,10 +104,10 @@ module { // CHECK: %[[VAL_1:.*]] = aie.buffer(%[[VAL_0]]) {address = 8192 : i32, sym_name = "in"} : memref<16xi32> // CHECK: %[[VAL_2:.*]] = aie.buffer(%[[VAL_0]]) {address = 1824 : i32, sym_name = "out"} : memref<16xi32> // CHECK: %[[VAL_8:.*]] = aie.memtile_dma(%[[VAL_0]]) { -// CHECK: aie.dma_bd(%[[VAL_1]] : memref<16xi32>, 0, 128, [, , , ]) {bd_id = 0 : i32, next_bd_id = 0 : i32} -// CHECK: aie.dma_bd(%[[VAL_1]] : memref<16xi32>, 0, 16) {bd_id = 24 : i32, next_bd_id = 24 : i32} -// CHECK: aie.dma_bd(%[[VAL_2]] : memref<16xi32>, 0, 16) {bd_id = 25 : i32, next_bd_id = 25 : i32} -// CHECK: aie.dma_bd(%[[VAL_2]] : memref<16xi32>, 0, 16) {bd_id = 1 : i32, next_bd_id = 1 : i32} +// CHECK: aie.dma_bd(%[[VAL_1]] : memref<16xi32>, dims = [, , , ]) {bd_id = 0 : i32, len = 128 : i32, next_bd_id = 0 : i32} +// CHECK: aie.dma_bd(%[[VAL_1]] : memref<16xi32>) {bd_id = 24 : i32, len = 16 : i32, next_bd_id = 24 : i32} +// CHECK: aie.dma_bd(%[[VAL_2]] : memref<16xi32>) {bd_id = 25 : i32, len = 16 : i32, next_bd_id = 25 : i32} +// CHECK: aie.dma_bd(%[[VAL_2]] : memref<16xi32>) {bd_id = 1 : i32, len = 16 : i32, next_bd_id = 1 : i32} module @aie_module { aie.device(xcve2302) { @@ -130,22 +130,22 @@ module @aie_module { %dstDma = aie.dma_start(MM2S, 0, ^bd3, ^end) ^bd0: aie.use_lock(%l01_0, "AcquireGreaterEqual", 1) - aie.dma_bd(%buf01_0 : memref<16xi32>, 0, 128, [, , , ]) + aie.dma_bd(%buf01_0 : memref<16xi32>, dims = [, , , ]) { len = 128 : i32 } aie.use_lock(%l01_1, "Release", 1) aie.next_bd ^bd0 ^bd1: aie.use_lock(%l01_1, "AcquireGreaterEqual", 1) - aie.dma_bd(%buf01_0 : memref<16xi32>, 0, 16) + aie.dma_bd(%buf01_0 : memref<16xi32>) { len = 16 : i32 } aie.use_lock(%l01_0, "Release", 1) aie.next_bd ^bd1 ^bd2: aie.use_lock(%l01_2, "AcquireGreaterEqual", 1) - aie.dma_bd(%buf01_1 : memref<16xi32>, 0, 16) + aie.dma_bd(%buf01_1 : memref<16xi32>) { len = 16 : i32 } aie.use_lock(%l01_3, "Release", 1) aie.next_bd ^bd2 ^bd3: aie.use_lock(%l01_3, "AcquireGreaterEqual", 1) - aie.dma_bd(%buf01_1 : memref<16xi32>, 0, 16) + aie.dma_bd(%buf01_1 : memref<16xi32>) { len = 16 : i32 } aie.use_lock(%l01_2, "Release", 1) aie.next_bd ^bd3 ^end: diff --git a/test/Passes/assign-bd-ids/user_assigned.mlir b/test/Passes/assign-bd-ids/user_assigned.mlir index 777c07f7b8..12345bf3ee 100644 --- a/test/Passes/assign-bd-ids/user_assigned.mlir +++ b/test/Passes/assign-bd-ids/user_assigned.mlir @@ -16,10 +16,10 @@ // CHECK: %[[VAL_2:.*]] = aie.tile(0, 2) // CHECK: %[[VAL_3:.*]] = aie.buffer(%[[VAL_2]]) {sym_name = "double_buffer"} : memref<32xi32> // CHECK: %[[VAL_4:.*]] = aie.buffer(%[[VAL_1]]) : memref<32xi32> -// CHECK: aie.dma_bd(%[[VAL_3]] : memref<32xi32>, 0) {bd_id = 0 : i32, next_bd_id = 1 : i32} +// CHECK: aie.dma_bd(%[[VAL_3]] : memref<32xi32>) {bd_id = 0 : i32, next_bd_id = 1 : i32} // CHECK: aie.dma_bd(%[[VAL_3]] : memref<32xi32>) {bd_id = 1 : i32, next_bd_id = 2 : i32} // CHECK: aie.dma_bd(%[[VAL_3]] : memref<32xi32>) {bd_id = 2 : i32, next_bd_id = 0 : i32} -// CHECK: aie.dma_bd(%[[VAL_3]] : memref<32xi32>, 0) {bd_id = 3 : i32, next_bd_id = 4 : i32} +// CHECK: aie.dma_bd(%[[VAL_3]] : memref<32xi32>) {bd_id = 3 : i32, next_bd_id = 4 : i32} // CHECK: aie.dma_bd(%[[VAL_3]] : memref<32xi32>) {bd_id = 4 : i32, next_bd_id = 5 : i32} // CHECK: aie.dma_bd(%[[VAL_3]] : memref<32xi32>) {bd_id = 5 : i32, next_bd_id = 3 : i32} // CHECK: aie.dma_bd(%[[VAL_4]] : memref<32xi32>) {bd_id = 0 : i32} @@ -39,7 +39,7 @@ module { %mem_0_2 = aie.mem(%tile_0_2) { %player_a = aie.dma(S2MM, 0) {sym_name = "player_a"} [{ aie.use_lock(%lock_Y, Acquire, 0) - aie.dma_bd(%double_buffer : memref<32xi32>, 0) {bd_id = 0 : i32} + aie.dma_bd(%double_buffer : memref<32xi32>) {bd_id = 0 : i32} aie.use_lock(%lock_Y, Release, 0) }, { aie.use_lock(%lock_X, Acquire, 1) @@ -52,7 +52,7 @@ module { }] %player_b = aie.dma(S2MM, 1) {sym_name = "player_b"} [{ aie.use_lock(%lock_Y, Acquire, 1) - aie.dma_bd(%double_buffer : memref<32xi32>, 0) + aie.dma_bd(%double_buffer : memref<32xi32>) aie.use_lock(%lock_Y, Release, 0) }, { aie.use_lock(%lock_X, Acquire, 1) @@ -101,10 +101,10 @@ module { // CHECK: %[[VAL_0:.*]] = aie.tile(2, 1) // CHECK: %[[VAL_1:.*]] = aie.buffer(%[[VAL_0]]) {address = 8192 : i32, sym_name = "in"} : memref<16xi32> // CHECK: %[[VAL_2:.*]] = aie.buffer(%[[VAL_0]]) {address = 1824 : i32, sym_name = "out"} : memref<16xi32> -// CHECK: aie.dma_bd(%[[VAL_1]] : memref<16xi32>, 0, 128, [, , , ]) {bd_id = 0 : i32, next_bd_id = 0 : i32} -// CHECK: aie.dma_bd(%[[VAL_1]] : memref<16xi32>, 0, 16) {bd_id = 24 : i32, next_bd_id = 24 : i32} -// CHECK: aie.dma_bd(%[[VAL_2]] : memref<16xi32>, 0, 16) {bd_id = 25 : i32, next_bd_id = 25 : i32} -// CHECK: aie.dma_bd(%[[VAL_2]] : memref<16xi32>, 0, 16) {bd_id = 1 : i32, next_bd_id = 1 : i32} +// CHECK: aie.dma_bd(%[[VAL_1]] : memref<16xi32>, dims = [, , , ]) {bd_id = 0 : i32, len = 128 : i32, next_bd_id = 0 : i32} +// CHECK: aie.dma_bd(%[[VAL_1]] : memref<16xi32>) {bd_id = 24 : i32, len = 16 : i32, next_bd_id = 24 : i32} +// CHECK: aie.dma_bd(%[[VAL_2]] : memref<16xi32>) {bd_id = 25 : i32, len = 16 : i32, next_bd_id = 25 : i32} +// CHECK: aie.dma_bd(%[[VAL_2]] : memref<16xi32>) {bd_id = 1 : i32, len = 16 : i32, next_bd_id = 1 : i32} module @aie_module { aie.device(xcve2302) { @@ -127,22 +127,22 @@ module @aie_module { %dstDma = aie.dma_start(MM2S, 0, ^bd3, ^end) ^bd0: aie.use_lock(%l01_0, "AcquireGreaterEqual", 1) - aie.dma_bd(%buf01_0 : memref<16xi32>, 0, 128, [, , , ]) + aie.dma_bd(%buf01_0 : memref<16xi32>, dims = [, , , ]) { len = 128 : i32 } aie.use_lock(%l01_1, "Release", 1) aie.next_bd ^bd0 ^bd1: aie.use_lock(%l01_1, "AcquireGreaterEqual", 1) - aie.dma_bd(%buf01_0 : memref<16xi32>, 0, 16) {bd_id = 24 : i32} + aie.dma_bd(%buf01_0 : memref<16xi32>) { len = 16 : i32, bd_id = 24 : i32 } aie.use_lock(%l01_0, "Release", 1) aie.next_bd ^bd1 ^bd2: aie.use_lock(%l01_2, "AcquireGreaterEqual", 1) - aie.dma_bd(%buf01_1 : memref<16xi32>, 0, 16) + aie.dma_bd(%buf01_1 : memref<16xi32>) { len = 16 : i32 } aie.use_lock(%l01_3, "Release", 1) aie.next_bd ^bd2 ^bd3: aie.use_lock(%l01_3, "AcquireGreaterEqual", 1) - aie.dma_bd(%buf01_1 : memref<16xi32>, 0, 16) {bd_id = 1 : i32} + aie.dma_bd(%buf01_1 : memref<16xi32>) { len = 16 : i32, bd_id = 1 : i32 } aie.use_lock(%l01_2, "Release", 1) aie.next_bd ^bd3 ^end: @@ -159,10 +159,10 @@ module @aie_module { // CHECK: %[[VAL_2:.*]] = aie.tile(0, 2) // CHECK: %[[VAL_3:.*]] = aie.buffer(%[[VAL_2]]) {sym_name = "double_buffer"} : memref<32xi32> // CHECK: %[[VAL_4:.*]] = aie.buffer(%[[VAL_1]]) : memref<32xi32> -// CHECK: aie.dma_bd(%[[VAL_3]] : memref<32xi32>, 0) {bd_id = 5 : i32, next_bd_id = 4 : i32} +// CHECK: aie.dma_bd(%[[VAL_3]] : memref<32xi32>) {bd_id = 5 : i32, next_bd_id = 4 : i32} // CHECK: aie.dma_bd(%[[VAL_3]] : memref<32xi32>) {bd_id = 4 : i32, next_bd_id = 3 : i32} // CHECK: aie.dma_bd(%[[VAL_3]] : memref<32xi32>) {bd_id = 3 : i32, next_bd_id = 5 : i32} -// CHECK: aie.dma_bd(%[[VAL_3]] : memref<32xi32>, 0) {bd_id = 2 : i32, next_bd_id = 1 : i32} +// CHECK: aie.dma_bd(%[[VAL_3]] : memref<32xi32>) {bd_id = 2 : i32, next_bd_id = 1 : i32} // CHECK: aie.dma_bd(%[[VAL_3]] : memref<32xi32>) {bd_id = 1 : i32, next_bd_id = 0 : i32} // CHECK: aie.dma_bd(%[[VAL_3]] : memref<32xi32>) {bd_id = 0 : i32, next_bd_id = 2 : i32} // CHECK: aie.dma_bd(%[[VAL_4]] : memref<32xi32>) {bd_id = 0 : i32} @@ -182,7 +182,7 @@ module { %mem_0_2 = aie.mem(%tile_0_2) { %player_a = aie.dma(S2MM, 0) {sym_name = "player_a"} [{ aie.use_lock(%lock_Y, Acquire, 0) - aie.dma_bd(%double_buffer : memref<32xi32>, 0) {bd_id = 5 : i32} + aie.dma_bd(%double_buffer : memref<32xi32>) {bd_id = 5 : i32} aie.use_lock(%lock_Y, Release, 0) }, { aie.use_lock(%lock_X, Acquire, 1) @@ -195,7 +195,7 @@ module { }] %player_b = aie.dma(S2MM, 1) {sym_name = "player_b"} [{ aie.use_lock(%lock_Y, Acquire, 1) - aie.dma_bd(%double_buffer : memref<32xi32>, 0) {bd_id = 2 : i32} + aie.dma_bd(%double_buffer : memref<32xi32>) {bd_id = 2 : i32} aie.use_lock(%lock_Y, Release, 0) }, { aie.use_lock(%lock_X, Acquire, 1) diff --git a/test/Targets/AIEGenerateXAIE/aie2_nd_DMA.mlir b/test/Targets/AIEGenerateXAIE/aie2_nd_DMA.mlir index 15e64b3ab5..5d43c226f6 100644 --- a/test/Targets/AIEGenerateXAIE/aie2_nd_DMA.mlir +++ b/test/Targets/AIEGenerateXAIE/aie2_nd_DMA.mlir @@ -15,11 +15,11 @@ // CHECK: if(NULL == dma_tile_2_1_bd_0_tensor.Dim){ // CHECK: return 1; // CHECK: } -// CHECK: dma_tile_2_1_bd_0_tensor.Dim[3].AieMlDimDesc = { /* StepSize */ 1, /* Size */ 2}; -// CHECK: dma_tile_2_1_bd_0_tensor.Dim[2].AieMlDimDesc = { /* StepSize */ 2, /* Size */ 3}; -// CHECK: dma_tile_2_1_bd_0_tensor.Dim[1].AieMlDimDesc = { /* StepSize */ 4, /* Size */ 2}; -// CHECK: dma_tile_2_1_bd_0_tensor.Dim[0].AieMlDimDesc = { /* StepSize */ 1, /* Size */ 1}; -// CHECK: __mlir_aie_try(XAie_DmaSetMultiDimAddr(&(dma_tile21_bd0), &dma_tile_2_1_bd_0_tensor, 0x82000, /* len */ 128 * 4)); +// CHECK: dma_tile_2_1_bd_0_tensor.Dim[3].AieMlDimDesc = { /* Stride */ 1, /* Size */ 2}; +// CHECK: dma_tile_2_1_bd_0_tensor.Dim[2].AieMlDimDesc = { /* Stride */ 2, /* Size */ 3}; +// CHECK: dma_tile_2_1_bd_0_tensor.Dim[1].AieMlDimDesc = { /* Stride */ 4, /* Size */ 2}; +// CHECK: dma_tile_2_1_bd_0_tensor.Dim[0].AieMlDimDesc = { /* Stride */ 1, /* Size */ 1}; +// CHECK: __mlir_aie_try(XAie_DmaSetMultiDimAddr(&(dma_tile21_bd0), &dma_tile_2_1_bd_0_tensor, 0x82000, /* len */ 512)); module @aie_module { aie.device(xcve2302) { @@ -44,22 +44,22 @@ module @aie_module { %dstDma = aie.dma_start(MM2S, 0, ^bd3, ^end) ^bd0: aie.use_lock(%l01_0, "AcquireGreaterEqual", 1) - aie.dma_bd(%buf01_0 : memref<16xi32>, 0, 128, [, , , ]) + aie.dma_bd(%buf01_0 : memref<16xi32>, dims = [, , , ]) { len = 128 : i32 } aie.use_lock(%l01_1, "Release", 1) aie.next_bd ^bd0 ^bd1: aie.use_lock(%l01_1, "AcquireGreaterEqual", 1) - aie.dma_bd(%buf01_0 : memref<16xi32>, 0, 16) + aie.dma_bd(%buf01_0 : memref<16xi32>) { len = 16 : i32 } aie.use_lock(%l01_0, "Release", 1) aie.next_bd ^bd1 ^bd2: aie.use_lock(%l01_2, "AcquireGreaterEqual", 1) - aie.dma_bd(%buf01_1 : memref<16xi32>, 0, 16) + aie.dma_bd(%buf01_1 : memref<16xi32>) { len = 16 : i32 } aie.use_lock(%l01_3, "Release", 1) aie.next_bd ^bd2 ^bd3: aie.use_lock(%l01_3, "AcquireGreaterEqual", 1) - aie.dma_bd(%buf01_1 : memref<16xi32>, 0, 16) + aie.dma_bd(%buf01_1 : memref<16xi32>) { len = 16 : i32 } aie.use_lock(%l01_2, "Release", 1) aie.next_bd ^bd3 ^end: diff --git a/test/Targets/AIEGenerateXAIE/aie2_tileDMA.mlir b/test/Targets/AIEGenerateXAIE/aie2_tileDMA.mlir index d686d76159..ac9638e447 100644 --- a/test/Targets/AIEGenerateXAIE/aie2_tileDMA.mlir +++ b/test/Targets/AIEGenerateXAIE/aie2_tileDMA.mlir @@ -13,7 +13,7 @@ // CHECK: XAie_DmaDesc [[bd0:.*]]; // CHECK: __mlir_aie_try(XAie_DmaDescInit(&(ctx->DevInst), &([[bd0]]), XAie_TileLoc(7,3))); // CHECK: __mlir_aie_try(XAie_DmaSetLock(&([[bd0]]), XAie_LockInit(3,-1),XAie_LockInit(4,1))); -// CHECK: __mlir_aie_try(XAie_DmaSetAddrLen(&([[bd0]]), /* addrA */ 0x720, /* len */ 256 * 4)); +// CHECK: __mlir_aie_try(XAie_DmaSetAddrLen(&([[bd0]]), /* addrA */ 0x720, /* len */ 1024)); // CHECK: __mlir_aie_try(XAie_DmaSetNextBd(&([[bd0]]), /* nextbd */ 0, /* enableNextBd */ 0)); // CHECK: __mlir_aie_try(XAie_DmaEnableBd(&([[bd0]]))); // CHECK: __mlir_aie_try(XAie_DmaWriteBd(&(ctx->DevInst), &([[bd0]]), XAie_TileLoc(7,3), /* bd */ 0)); @@ -35,7 +35,7 @@ module @aie_module { ^bd0: // Note: acquire and release are different locks. aie.use_lock(%lock_a_write, AcquireGreaterEqual, 1) - aie.dma_bd(%buf_a_ping : memref<256xi32>, 0, 256) + aie.dma_bd(%buf_a_ping : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%lock_a_read, Release, 1) aie.next_bd ^end ^end: diff --git a/test/Targets/AIEGenerateXAIE/aie2_tileDMA2.mlir b/test/Targets/AIEGenerateXAIE/aie2_tileDMA2.mlir index 62d61c09ae..55d4401532 100644 --- a/test/Targets/AIEGenerateXAIE/aie2_tileDMA2.mlir +++ b/test/Targets/AIEGenerateXAIE/aie2_tileDMA2.mlir @@ -14,7 +14,7 @@ // CHECK: __mlir_aie_try(XAie_DmaDescInit(&(ctx->DevInst), &([[bd0]]), XAie_TileLoc(7,3))); // CHECK: __mlir_aie_try(XAie_DmaSetLock(&([[bd0]]), XAie_LockInit(3,-1),XAie_LockInit({{.*}},0))); // CHECK: [[bd0]].LockDesc.LockRelEn = XAIE_DISABLE; -// CHECK: __mlir_aie_try(XAie_DmaSetAddrLen(&([[bd0]]), /* addrA */ 0x720, /* len */ 256 * 4)); +// CHECK: __mlir_aie_try(XAie_DmaSetAddrLen(&([[bd0]]), /* addrA */ 0x720, /* len */ 1024)); // CHECK: __mlir_aie_try(XAie_DmaSetNextBd(&([[bd0]]), /* nextbd */ 0, /* enableNextBd */ 0)); // CHECK: __mlir_aie_try(XAie_DmaEnableBd(&([[bd0]]))); // CHECK: __mlir_aie_try(XAie_DmaWriteBd(&(ctx->DevInst), &([[bd0]]), XAie_TileLoc(7,3), /* bd */ 0)); @@ -36,7 +36,7 @@ module @aie_module { ^bd0: // Note: acquire and release are different locks. aie.use_lock(%lock_a_write, AcquireGreaterEqual, 1) - aie.dma_bd(%buf_a_ping : memref<256xi32>, 0, 256) + aie.dma_bd(%buf_a_ping : memref<256xi32>) { len = 256 : i32 } // aie.use_lock(%lock_a_read, Release, 1) aie.next_bd ^end ^end: diff --git a/test/Targets/AIEGenerateXAIE/aie2_tileDMA3.mlir b/test/Targets/AIEGenerateXAIE/aie2_tileDMA3.mlir index f69b28fa56..06b1af55f4 100644 --- a/test/Targets/AIEGenerateXAIE/aie2_tileDMA3.mlir +++ b/test/Targets/AIEGenerateXAIE/aie2_tileDMA3.mlir @@ -14,7 +14,7 @@ // CHECK: __mlir_aie_try(XAie_DmaDescInit(&(ctx->DevInst), &([[bd0]]), XAie_TileLoc(7,3))); // CHECK: __mlir_aie_try(XAie_DmaSetLock(&([[bd0]]), XAie_LockInit({{.*}},0),XAie_LockInit(4,1))); // CHECK: [[bd0]].LockDesc.LockAcqEn = XAIE_DISABLE; -// CHECK: __mlir_aie_try(XAie_DmaSetAddrLen(&([[bd0]]), /* addrA */ 0x720, /* len */ 256 * 4)); +// CHECK: __mlir_aie_try(XAie_DmaSetAddrLen(&([[bd0]]), /* addrA */ 0x720, /* len */ 1024)); // CHECK: __mlir_aie_try(XAie_DmaSetNextBd(&([[bd0]]), /* nextbd */ 0, /* enableNextBd */ 0)); // CHECK: __mlir_aie_try(XAie_DmaEnableBd(&([[bd0]]))); // CHECK: __mlir_aie_try(XAie_DmaWriteBd(&(ctx->DevInst), &([[bd0]]), XAie_TileLoc(7,3), /* bd */ 0)); @@ -36,7 +36,7 @@ module @aie_module { ^bd0: // Note: acquire and release are different locks. //aie.use_lock(%lock_a_write, AcquireGreaterEqual, 1) - aie.dma_bd(%buf_a_ping : memref<256xi32>, 0, 256) + aie.dma_bd(%buf_a_ping : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%lock_a_read, Release, 1) aie.next_bd ^end ^end: diff --git a/test/Targets/AIEGenerateXAIE/aie2_tileDMA4.mlir b/test/Targets/AIEGenerateXAIE/aie2_tileDMA4.mlir index e65c86fbba..76e5f6e665 100644 --- a/test/Targets/AIEGenerateXAIE/aie2_tileDMA4.mlir +++ b/test/Targets/AIEGenerateXAIE/aie2_tileDMA4.mlir @@ -13,7 +13,7 @@ // CHECK: XAie_DmaDesc [[bd0:.*]]; // CHECK: __mlir_aie_try(XAie_DmaDescInit(&(ctx->DevInst), &([[bd0]]), XAie_TileLoc(7,3))); // CHECK: __mlir_aie_try(XAie_DmaSetLock(&([[bd0]]), XAie_LockInit(3,-1),XAie_LockInit(4,1))); -// CHECK: __mlir_aie_try(XAie_DmaSetAddrLen(&([[bd0]]), /* addrA */ 0x720, /* len */ 256 * 4)); +// CHECK: __mlir_aie_try(XAie_DmaSetAddrLen(&([[bd0]]), /* addrA */ 0x720, /* len */ 1024)); // CHECK: __mlir_aie_try(XAie_DmaSetNextBd(&([[bd0]]), /* nextbd */ 0, /* enableNextBd */ 0)); // CHECK: __mlir_aie_try(XAie_DmaEnableBd(&([[bd0]]))); // CHECK: __mlir_aie_try(XAie_DmaWriteBd(&(ctx->DevInst), &([[bd0]]), XAie_TileLoc(7,3), /* bd */ 0)); @@ -35,7 +35,7 @@ ^bd0: // Note: acquire and release are different locks. aie.use_lock(%lock_a_write, AcquireGreaterEqual, 1) - aie.dma_bd(%buf_a_ping : memref<256xi32>, 0, 256) + aie.dma_bd(%buf_a_ping : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%lock_a_read, Release, 1) aie.next_bd ^end ^end: diff --git a/test/Targets/AIEGenerateXAIE/aie2_tileDMA_locks.mlir b/test/Targets/AIEGenerateXAIE/aie2_tileDMA_locks.mlir index 46de9611b1..0758d081bd 100644 --- a/test/Targets/AIEGenerateXAIE/aie2_tileDMA_locks.mlir +++ b/test/Targets/AIEGenerateXAIE/aie2_tileDMA_locks.mlir @@ -13,7 +13,7 @@ // CHECK: XAie_DmaDesc [[bd0:.*]]; // CHECK: XAie_DmaDescInit(&(ctx->DevInst), &([[bd0]]), XAie_TileLoc(7,4)) // CHECK: XAie_DmaSetLock(&([[bd0]]), XAie_LockInit(3,-1),XAie_LockInit(4,1)) -// CHECK: XAie_DmaSetAddrLen(&([[bd0]]), /* addrA */ 0x720, /* len */ 256 * 4) +// CHECK: XAie_DmaSetAddrLen(&([[bd0]]), /* addrA */ 0x720, /* len */ 1024) // CHECK: XAie_DmaSetNextBd(&([[bd0]]), /* nextbd */ 1, /* enableNextBd */ 1) // CHECK: XAie_DmaEnableBd(&([[bd0]])) // CHECK: XAie_DmaWriteBd(&(ctx->DevInst), &([[bd0]]), XAie_TileLoc(7,4), /* bd */ 0) @@ -43,19 +43,19 @@ module @aie_module { %srcDma = aie.dma_start("S2MM", 0, ^bd0, ^end) ^bd0: aie.use_lock(%lock_l1, AcquireGreaterEqual, 1) - aie.dma_bd(%buf_l : memref<256xi32>, 0, 256) + aie.dma_bd(%buf_l : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%lock_l2, Release, 1) aie.next_bd ^bd1 ^bd1: - aie.dma_bd(%buf_l : memref<256xi32>, 0, 256) + aie.dma_bd(%buf_l : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%lock_l1, Release, 1) aie.next_bd ^bd2 ^bd2: - aie.dma_bd(%buf_l : memref<256xi32>, 0, 256) + aie.dma_bd(%buf_l : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%lock_l1, Release, 1) aie.next_bd ^bd3 ^bd3: - aie.dma_bd(%buf_l : memref<256xi32>, 0, 256) + aie.dma_bd(%buf_l : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%lock_l1, Release, 1) aie.next_bd ^end ^end: diff --git a/test/Targets/AIEGenerateXAIE/memTileDMA.mlir b/test/Targets/AIEGenerateXAIE/memTileDMA.mlir index 3ef0df299d..308152fb67 100644 --- a/test/Targets/AIEGenerateXAIE/memTileDMA.mlir +++ b/test/Targets/AIEGenerateXAIE/memTileDMA.mlir @@ -14,25 +14,25 @@ // CHECK: XAie_DmaDesc [[bd0:.*]]; // CHECK: __mlir_aie_try(XAie_DmaDescInit(&(ctx->DevInst), &([[bd0]]), XAie_TileLoc(2,1))); -// CHECK: __mlir_aie_try(XAie_DmaSetAddrLen(&([[bd0]]), /* addrA */ 0x82000, /* len */ 16 * 4)); +// CHECK: __mlir_aie_try(XAie_DmaSetAddrLen(&([[bd0]]), /* addrA */ 0x82000, /* len */ 64)); // CHECK: __mlir_aie_try(XAie_DmaSetNextBd(&([[bd0]]), {{.*}} 0, {{.*}} 1)); // CHECK: __mlir_aie_try(XAie_DmaWriteBd(&(ctx->DevInst), &([[bd0]]), XAie_TileLoc(2,1), {{.*}} 0)); // CHECK: XAie_DmaDesc [[bd24:.*]]; // CHECK: __mlir_aie_try(XAie_DmaDescInit(&(ctx->DevInst), &([[bd24]]), XAie_TileLoc(2,1))); -// CHECK: __mlir_aie_try(XAie_DmaSetAddrLen(&([[bd24]]), /* addrA */ 0x82000, /* len */ 16 * 4)); +// CHECK: __mlir_aie_try(XAie_DmaSetAddrLen(&([[bd24]]), /* addrA */ 0x82000, /* len */ 64)); // CHECK: __mlir_aie_try(XAie_DmaSetNextBd(&([[bd24]]), {{.*}} 24, {{.*}} 1)); // CHECK: __mlir_aie_try(XAie_DmaWriteBd(&(ctx->DevInst), &([[bd24]]), XAie_TileLoc(2,1), {{.*}} 24)); // CHECK: XAie_DmaDesc [[bd25:.*]]; // CHECK: __mlir_aie_try(XAie_DmaDescInit(&(ctx->DevInst), &([[bd25]]), XAie_TileLoc(2,1))); -// CHECK: __mlir_aie_try(XAie_DmaSetAddrLen(&([[bd25]]), /* addrA */ 0x80720, /* len */ 16 * 4)); +// CHECK: __mlir_aie_try(XAie_DmaSetAddrLen(&([[bd25]]), /* addrA */ 0x80720, /* len */ 64)); // CHECK: __mlir_aie_try(XAie_DmaSetNextBd(&([[bd25]]), {{.*}} 25, {{.*}} 1)); // CHECK: __mlir_aie_try(XAie_DmaWriteBd(&(ctx->DevInst), &([[bd25]]), XAie_TileLoc(2,1), {{.*}} 25)); // CHECK: XAie_DmaDesc [[bd1:.*]]; // CHECK: __mlir_aie_try(XAie_DmaDescInit(&(ctx->DevInst), &([[bd1]]), XAie_TileLoc(2,1))); -// CHECK: __mlir_aie_try(XAie_DmaSetAddrLen(&([[bd1]]), /* addrA */ 0x80720, /* len */ 16 * 4)); +// CHECK: __mlir_aie_try(XAie_DmaSetAddrLen(&([[bd1]]), /* addrA */ 0x80720, /* len */ 64)); // CHECK: __mlir_aie_try(XAie_DmaSetNextBd(&([[bd1]]), {{.*}} 1, {{.*}} 1)); // CHECK: __mlir_aie_try(XAie_DmaWriteBd(&(ctx->DevInst), &([[bd1]]), XAie_TileLoc(2,1), {{.*}} 1)); @@ -58,22 +58,22 @@ module @aie_module { %dstDma = aie.dma_start(MM2S, 0, ^bd3, ^end) ^bd0: aie.use_lock(%l01_0, "AcquireGreaterEqual", 1) - aie.dma_bd(%buf01_0 : memref<16xi32>, 0, 16) + aie.dma_bd(%buf01_0 : memref<16xi32>) { len = 16 : i32 } aie.use_lock(%l01_1, "Release", 1) aie.next_bd ^bd0 ^bd1: aie.use_lock(%l01_1, "AcquireGreaterEqual", 1) - aie.dma_bd(%buf01_0 : memref<16xi32>, 0, 16) + aie.dma_bd(%buf01_0 : memref<16xi32>) { len = 16 : i32 } aie.use_lock(%l01_0, "Release", 1) aie.next_bd ^bd1 ^bd2: aie.use_lock(%l01_2, "AcquireGreaterEqual", 1) - aie.dma_bd(%buf01_1 : memref<16xi32>, 0, 16) + aie.dma_bd(%buf01_1 : memref<16xi32>) { len = 16 : i32 } aie.use_lock(%l01_3, "Release", 1) aie.next_bd ^bd2 ^bd3: aie.use_lock(%l01_3, "AcquireGreaterEqual", 1) - aie.dma_bd(%buf01_1 : memref<16xi32>, 0, 16) + aie.dma_bd(%buf01_1 : memref<16xi32>) { len = 16 : i32 } aie.use_lock(%l01_2, "Release", 1) aie.next_bd ^bd3 ^end: diff --git a/test/Targets/AIEGenerateXAIE/memTileDMA2.mlir b/test/Targets/AIEGenerateXAIE/memTileDMA2.mlir index aff0040436..ab03a978ed 100644 --- a/test/Targets/AIEGenerateXAIE/memTileDMA2.mlir +++ b/test/Targets/AIEGenerateXAIE/memTileDMA2.mlir @@ -14,7 +14,7 @@ // CHECK: XAie_DmaDescInit(&(ctx->DevInst), &([[bd0]]), XAie_TileLoc(2,1)) // CHECK: XAie_DmaSetLock(&([[bd0]]), XAie_LockInit(0,0),XAie_LockInit(0,1)) // CHECK: [[bd0]].LockDesc.LockAcqEn = XAIE_DISABLE; -// CHECK: XAie_DmaSetAddrLen(&([[bd0]]), /* addrA */ 0x0, /* len */ 16 * 4) +// CHECK: XAie_DmaSetAddrLen(&([[bd0]]), /* addrA */ 0x0, /* len */ 64) // CHECK: XAie_DmaSetNextBd(&([[bd0]]), /* nextbd */ 1, /* enableNextBd */ 1) // CHECK: XAie_DmaEnableBd(&([[bd0]])) // CHECK: XAie_DmaWriteBd(&(ctx->DevInst), &([[bd0]]), XAie_TileLoc(2,1), /* bd */ 0) @@ -23,7 +23,7 @@ // CHECK: XAie_DmaDescInit(&(ctx->DevInst), &([[bd1]]), XAie_TileLoc(2,1)) // CHECK: XAie_DmaSetLock(&([[bd1]]), XAie_LockInit(0,0),XAie_LockInit(64,1)) // CHECK: [[bd1]].LockDesc.LockAcqEn = XAIE_DISABLE; -// CHECK: XAie_DmaSetAddrLen(&([[bd1]]), /* addrA */ 0x80000, /* len */ 16 * 4) +// CHECK: XAie_DmaSetAddrLen(&([[bd1]]), /* addrA */ 0x80000, /* len */ 64) // CHECK: XAie_DmaSetNextBd(&([[bd1]]), /* nextbd */ 2, /* enableNextBd */ 1) // CHECK: XAie_DmaEnableBd(&([[bd1]])) // CHECK: XAie_DmaWriteBd(&(ctx->DevInst), &([[bd1]]), XAie_TileLoc(2,1), /* bd */ 1) @@ -32,7 +32,7 @@ // CHECK: XAie_DmaDescInit(&(ctx->DevInst), &([[bd2]]), XAie_TileLoc(2,1)) // CHECK: XAie_DmaSetLock(&([[bd2]]), XAie_LockInit(0,0),XAie_LockInit(128,1)) // CHECK: [[bd2]].LockDesc.LockAcqEn = XAIE_DISABLE; -// CHECK: XAie_DmaSetAddrLen(&([[bd2]]), /* addrA */ 0x100000, /* len */ 16 * 4) +// CHECK: XAie_DmaSetAddrLen(&([[bd2]]), /* addrA */ 0x100000, /* len */ 64) // CHECK: XAie_DmaSetNextBd(&([[bd2]]), /* nextbd */ 0, /* enableNextBd */ 0) // CHECK: XAie_DmaEnableBd(&([[bd2]])) // CHECK: XAie_DmaWriteBd(&(ctx->DevInst), &([[bd2]]), XAie_TileLoc(2,1), /* bd */ 2) @@ -53,15 +53,15 @@ module @aie_module { %m01 = aie.memtile_dma(%t01) { %srcDma = aie.dma_start(S2MM, 0, ^bd0, ^end) ^bd0: - aie.dma_bd(%buf_w : memref<16xi32>, 0, 16) + aie.dma_bd(%buf_w : memref<16xi32>) { len = 16 : i32 } aie.use_lock(%lock_w, "Release", 1) aie.next_bd ^bd1 ^bd1: - aie.dma_bd(%buf_l : memref<16xi32>, 0, 16) + aie.dma_bd(%buf_l : memref<16xi32>) { len = 16 : i32 } aie.use_lock(%lock_l, "Release", 1) aie.next_bd ^bd2 ^bd2: - aie.dma_bd(%buf_e : memref<16xi32>, 0, 16) + aie.dma_bd(%buf_e : memref<16xi32>) { len = 16 : i32 } aie.use_lock(%lock_e, "Release", 1) aie.next_bd ^end ^end: diff --git a/test/Targets/AIEGenerateXAIE/packet_drop_header.mlir b/test/Targets/AIEGenerateXAIE/packet_drop_header.mlir index ecc4063fb8..2b476a175b 100644 --- a/test/Targets/AIEGenerateXAIE/packet_drop_header.mlir +++ b/test/Targets/AIEGenerateXAIE/packet_drop_header.mlir @@ -69,13 +69,13 @@ module @aie_module { ^bb2: // 2 preds: ^bb0, ^bb2 aie.use_lock(%4, Acquire, 0) aie.dma_bd_packet(2, 3) - aie.dma_bd(%5 : memref<16xi32, 2>, 0, 16) + aie.dma_bd(%5 : memref<16xi32, 2>) { len = 16 : i32 } aie.use_lock(%4, Release, 1) aie.next_bd ^bb2 ^bb3: // 2 preds: ^bb1, ^bb3 aie.use_lock(%4, Acquire, 1) aie.dma_bd_packet(6, 10) - aie.dma_bd(%5 : memref<16xi32, 2>, 0, 16) + aie.dma_bd(%5 : memref<16xi32, 2>) { len = 16 : i32 } aie.use_lock(%4, Release, 0) aie.next_bd ^bb3 ^bb4: // pred: ^bb1 diff --git a/test/Targets/AIEGenerateXAIE/packet_shim_header.mlir b/test/Targets/AIEGenerateXAIE/packet_shim_header.mlir index 912ef14a48..e24155ecbb 100644 --- a/test/Targets/AIEGenerateXAIE/packet_shim_header.mlir +++ b/test/Targets/AIEGenerateXAIE/packet_shim_header.mlir @@ -61,7 +61,7 @@ module @aie_module { %10 = aie.dma_start(S2MM, 0, ^bb1, ^bb2) ^bb1: // 2 preds: ^bb0, ^bb1 aie.use_lock(%5, Acquire, 0) - aie.dma_bd(%6 : memref<32xi32, 2>, 0, 32) + aie.dma_bd(%6 : memref<32xi32, 2>) { len = 32 : i32 } aie.use_lock(%5, Release, 1) aie.next_bd ^bb1 ^bb2: // pred: ^bb0 @@ -73,7 +73,7 @@ module @aie_module { ^bb1: // 2 preds: ^bb0, ^bb1 aie.use_lock(%10, Acquire, 1) aie.dma_bd_packet(6, 10) - aie.dma_bd(%7 : memref<32xi32>, 0, 32) + aie.dma_bd(%7 : memref<32xi32>) { len = 32 : i32 } aie.use_lock(%10, Release, 0) aie.next_bd ^bb1 ^bb2: // pred: ^bb0 diff --git a/test/Targets/AIEGenerateXAIE/shim.mlir b/test/Targets/AIEGenerateXAIE/shim.mlir index f9cf7ec751..ccfe7ab2c9 100644 --- a/test/Targets/AIEGenerateXAIE/shim.mlir +++ b/test/Targets/AIEGenerateXAIE/shim.mlir @@ -14,14 +14,14 @@ // CHECK: XAie_DmaDesc [[bd0:.*]]; // CHECK: __mlir_aie_try(XAie_DmaDescInit(&(ctx->DevInst), &([[bd0]]), XAie_TileLoc(2,0))); // CHECK: __mlir_aie_try(XAie_DmaSetLock(&([[bd0]]), XAie_LockInit(0,0),XAie_LockInit(0,1))); -// CHECK: __mlir_aie_try(XAie_DmaSetAddrLen(&([[bd0]]), {{.*}} mlir_aie_external_get_addr_myBuffer_20_0(), {{.*}} 16 * 4)); +// CHECK: __mlir_aie_try(XAie_DmaSetAddrLen(&([[bd0]]), {{.*}} mlir_aie_external_get_addr_myBuffer_20_0(), {{.*}} 64)); // CHECK: __mlir_aie_try(XAie_DmaSetAxi(&([[bd0]]), {{.*}} 0, {{.*}} 4, {{.*}} 0, {{.*}} 0, {{.*}} XAIE_ENABLE)); // CHECK: __mlir_aie_try(XAie_DmaSetNextBd(&([[bd0]]), {{.*}} 0, {{.*}} 1)); // CHECK: __mlir_aie_try(XAie_DmaEnableBd(&([[bd0]]))); // CHECK: __mlir_aie_try(XAie_DmaWriteBd(&(ctx->DevInst), &([[bd0]]), XAie_TileLoc(2,0), {{.*}} 0)); // CHECK: XAie_DmaDesc [[bd1:.*]]; // CHECK: __mlir_aie_try(XAie_DmaDescInit(&(ctx->DevInst), &([[bd1]]), XAie_TileLoc(2,0))); -// CHECK: __mlir_aie_try(XAie_DmaSetAddrLen(&([[bd1]]), {{.*}} mlir_aie_external_get_addr_myBuffer_20_1(), {{.*}} 4 * 4)); +// CHECK: __mlir_aie_try(XAie_DmaSetAddrLen(&([[bd1]]), {{.*}} mlir_aie_external_get_addr_myBuffer_20_1(), {{.*}} 16)); // CHECK: __mlir_aie_try(XAie_DmaSetAxi(&([[bd1]]), {{.*}} 0, {{.*}} 4, {{.*}} 0, {{.*}} 0, {{.*}} XAIE_ENABLE)); // CHECK: __mlir_aie_try(XAie_DmaSetNextBd(&([[bd1]]), {{.*}} 1, {{.*}} 1)); // CHECK: __mlir_aie_try(XAie_DmaEnableBd(&([[bd1]]))); @@ -64,12 +64,12 @@ module { aie.dma_start(MM2S, 0, ^bd1, ^end) ^bd0: aie.use_lock(%lock0, Acquire, 0) - aie.dma_bd(%buffer : memref<16 x f32>, 0, 16) + aie.dma_bd(%buffer : memref<16 x f32>) { len = 16 : i32 } aie.use_lock(%lock0, Release, 1) aie.next_bd ^bd0 ^bd1: // aie.use_lock(%lock1, Acquire, 1) - aie.dma_bd(%buffer : memref<16 x f32>, 0, 4) + aie.dma_bd(%buffer : memref<16 x f32>) { len = 4 : i32 } // aie.use_lock(%lock1, Release, 0) aie.next_bd ^bd1 ^end: diff --git a/test/Targets/AIEGenerateXAIE/shim_dma_packet.mlir b/test/Targets/AIEGenerateXAIE/shim_dma_packet.mlir index 2ccf0c2a1d..2f24f58c31 100644 --- a/test/Targets/AIEGenerateXAIE/shim_dma_packet.mlir +++ b/test/Targets/AIEGenerateXAIE/shim_dma_packet.mlir @@ -14,7 +14,7 @@ // CHECK: XAie_DmaDesc dma_tile70_bd0; // CHECK: XAie_DmaDescInit(&(ctx->DevInst), &(dma_tile70_bd0), XAie_TileLoc(7,0)) // CHECK: XAie_DmaSetLock(&(dma_tile70_bd0), XAie_LockInit(0,1),XAie_LockInit(0,0)) -// CHECK: XAie_DmaSetAddrLen(&(dma_tile70_bd0), /* addrA */ mlir_aie_external_get_addr_myBuffer_70_0(), /* len */ 1024 * 4) +// CHECK: XAie_DmaSetAddrLen(&(dma_tile70_bd0), /* addrA */ mlir_aie_external_get_addr_myBuffer_70_0(), /* len */ 4096) // CHECK: XAie_DmaSetAxi(&(dma_tile70_bd0), /* smid */ 0, /* burstlen */ 4, /* QoS */ 0, /* Cache */ 0, /* Secure */ XAIE_ENABLE) // CHECK: XAie_DmaSetNextBd(&(dma_tile70_bd0), /* nextbd */ 0, /* enableNextBd */ 1) // CHECK: XAie_DmaSetPkt(&(dma_tile70_bd0), XAie_PacketInit(2,0)) @@ -36,7 +36,7 @@ module { ^bb1: // 2 preds: ^bb0, ^bb1 aie.use_lock(%lock70, Acquire, 1) aie.dma_bd_packet(0, 2) - aie.dma_bd(%buf : memref<32x32xi32>, 0, 1024) + aie.dma_bd(%buf : memref<32x32xi32>) { len = 1024 : i32 } aie.use_lock(%lock70, Release, 0) aie.next_bd ^bb1 ^bb2: // pred: ^bb0 diff --git a/test/Targets/AIEGenerateXAIE/test_xaie1.mlir b/test/Targets/AIEGenerateXAIE/test_xaie1.mlir index 92190151ee..07d0313989 100644 --- a/test/Targets/AIEGenerateXAIE/test_xaie1.mlir +++ b/test/Targets/AIEGenerateXAIE/test_xaie1.mlir @@ -13,7 +13,7 @@ // CHECK: XAie_DmaDesc dma_tile33_bd0; // CHECK: __mlir_aie_try(XAie_DmaDescInit(&(ctx->DevInst), &(dma_tile33_bd0), XAie_TileLoc(3,3))); // CHECK: __mlir_aie_try(XAie_DmaSetLock(&(dma_tile33_bd0), XAie_LockInit(0,0),XAie_LockInit(0,1))); -// CHECK: __mlir_aie_try(XAie_DmaSetAddrLen(&(dma_tile33_bd0), {{.*}} 0x1400, {{.*}} 256 * 4)); +// CHECK: __mlir_aie_try(XAie_DmaSetAddrLen(&(dma_tile33_bd0), {{.*}} 0x1400, {{.*}} 1024)); // CHECK: __mlir_aie_try(XAie_DmaSetNextBd(&(dma_tile33_bd0), {{.*}} 0, {{.*}} 0)); // CHECK: __mlir_aie_try(XAie_DmaEnableBd(&(dma_tile33_bd0))); // CHECK: __mlir_aie_try(XAie_DmaWriteBd(&(ctx->DevInst), &(dma_tile33_bd0), XAie_TileLoc(3,3), {{.*}} 0)); @@ -32,7 +32,7 @@ module @test_xaie1 { %srcDma = aie.dma_start(MM2S, 0, ^bd0, ^end) ^bd0: aie.use_lock(%l33_0, Acquire, 0) - aie.dma_bd(%buf33_1 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf33_1 : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%l33_0, Release, 1) aie.next_bd ^end ^end: diff --git a/test/Targets/AIEGenerateXAIE/test_xaie2.mlir b/test/Targets/AIEGenerateXAIE/test_xaie2.mlir index c6f4126224..ed7302487f 100644 --- a/test/Targets/AIEGenerateXAIE/test_xaie2.mlir +++ b/test/Targets/AIEGenerateXAIE/test_xaie2.mlir @@ -14,14 +14,14 @@ // CHECK: XAie_DmaDesc [[bd0:.*]]; // CHECK: __mlir_aie_try(XAie_DmaDescInit(&(ctx->DevInst), &([[bd0]]), XAie_TileLoc(3,3))); // CHECK: __mlir_aie_try(XAie_DmaSetLock(&([[bd0]]), XAie_LockInit(0,0),XAie_LockInit(0,1))); -// CHECK: __mlir_aie_try(XAie_DmaSetAddrLen(&([[bd0]]), {{.*}}0x1000, {{.*}}256 * 4)); +// CHECK: __mlir_aie_try(XAie_DmaSetAddrLen(&([[bd0]]), {{.*}}0x1000, {{.*}}1024)); // CHECK: __mlir_aie_try(XAie_DmaSetNextBd(&([[bd0]]), {{.*}}1, {{.*}}1)); // CHECK: __mlir_aie_try(XAie_DmaEnableBd(&([[bd0]]))); // CHECK: __mlir_aie_try(XAie_DmaWriteBd(&(ctx->DevInst), &([[bd0]]), XAie_TileLoc(3,3), {{.*}}0)); // CHECK: XAie_DmaDesc [[bd1:.*]]; // CHECK: __mlir_aie_try(XAie_DmaDescInit(&(ctx->DevInst), &([[bd1]]), XAie_TileLoc(3,3))); // CHECK: __mlir_aie_try(XAie_DmaSetLock(&([[bd1]]), XAie_LockInit(0,0),XAie_LockInit(0,1))); -// CHECK: __mlir_aie_try(XAie_DmaSetAddrLen(&([[bd1]]), {{.*}}0x1400, {{.*}}4 * 4)); +// CHECK: __mlir_aie_try(XAie_DmaSetAddrLen(&([[bd1]]), {{.*}}0x1400, {{.*}}16)); // CHECK: __mlir_aie_try(XAie_DmaSetNextBd(&([[bd1]]), {{.*}}0, {{.*}}1)); // CHECK: __mlir_aie_try(XAie_DmaEnableBd(&([[bd1]]))); // CHECK: __mlir_aie_try(XAie_DmaWriteBd(&(ctx->DevInst), &([[bd1]]), XAie_TileLoc(3,3), {{.*}}1)); @@ -42,12 +42,12 @@ module @test_xaie2 { %srcDma = aie.dma_start(S2MM, 0, ^bd0, ^end) ^bd0: aie.use_lock(%l33_0, Acquire, 0) - aie.dma_bd(%buf33_0 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf33_0 : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%l33_0, Release, 1) aie.next_bd ^bd1 ^bd1: aie.use_lock(%l33_0, Acquire, 0) - aie.dma_bd(%buf33_1 : memref<16xi32>, 0, 4) + aie.dma_bd(%buf33_1 : memref<16xi32>) { len = 4 : i32 } aie.use_lock(%l33_0, Release, 1) aie.next_bd ^bd0 ^end: diff --git a/test/Targets/AIEGenerateXAIE/test_xaie3.mlir b/test/Targets/AIEGenerateXAIE/test_xaie3.mlir index b22f2b30f6..5780bc6cfb 100644 --- a/test/Targets/AIEGenerateXAIE/test_xaie3.mlir +++ b/test/Targets/AIEGenerateXAIE/test_xaie3.mlir @@ -27,7 +27,7 @@ module @test_xaie3 { %srcDma = aie.dma_start(MM2S, 0, ^bd0, ^end) ^bd0: aie.use_lock(%l33_0, Acquire, 1) - aie.dma_bd(%buf33_0 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf33_0 : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%l33_0, Release, 0) aie.next_bd ^end ^end: diff --git a/test/Targets/AIEGenerateXAIE/test_xaie4.mlir b/test/Targets/AIEGenerateXAIE/test_xaie4.mlir index 5f9e5cd8b4..991dd2a6e0 100644 --- a/test/Targets/AIEGenerateXAIE/test_xaie4.mlir +++ b/test/Targets/AIEGenerateXAIE/test_xaie4.mlir @@ -14,14 +14,14 @@ // CHECK: XAie_DmaDesc [[bd0:.*]]; // CHECK: __mlir_aie_try(XAie_DmaDescInit(&(ctx->DevInst), &([[bd0]]), XAie_TileLoc(3,3))); // CHECK: __mlir_aie_try(XAie_DmaSetLock(&([[bd0]]), XAie_LockInit(0,1),XAie_LockInit(0,0))); -// CHECK: __mlir_aie_try(XAie_DmaSetAddrLen(&([[bd0]]), {{.*}}0x1000, {{.*}}256 * 4)); +// CHECK: __mlir_aie_try(XAie_DmaSetAddrLen(&([[bd0]]), {{.*}}0x1000, {{.*}}1024)); // CHECK: __mlir_aie_try(XAie_DmaSetNextBd(&([[bd0]]), {{.*}}0, {{.*}}0)); // CHECK: __mlir_aie_try(XAie_DmaEnableBd(&([[bd0]]))); // CHECK: __mlir_aie_try(XAie_DmaWriteBd(&(ctx->DevInst), &([[bd0]]), XAie_TileLoc(3,3), {{.*}}0)); // CHECK: XAie_DmaDesc [[bd1:.*]]; // CHECK: __mlir_aie_try(XAie_DmaDescInit(&(ctx->DevInst), &([[bd1]]), XAie_TileLoc(3,3))); // CHECK: __mlir_aie_try(XAie_DmaSetLock(&([[bd1]]), XAie_LockInit(1,1),XAie_LockInit(1,0))); -// CHECK: __mlir_aie_try(XAie_DmaSetAddrLen(&([[bd1]]), {{.*}}0x1400, {{.*}}256 * 4)); +// CHECK: __mlir_aie_try(XAie_DmaSetAddrLen(&([[bd1]]), {{.*}}0x1400, {{.*}}1024)); // CHECK: __mlir_aie_try(XAie_DmaSetNextBd(&([[bd1]]), {{.*}}0, {{.*}}0)); // CHECK: __mlir_aie_try(XAie_DmaEnableBd(&([[bd1]]))); // CHECK: __mlir_aie_try(XAie_DmaWriteBd(&(ctx->DevInst), &([[bd1]]), XAie_TileLoc(3,3), {{.*}}1)); @@ -47,12 +47,12 @@ module @test_xaie3 { %destDma = aie.dma_start(S2MM, 0, ^bd1, ^end) ^bd0: aie.use_lock(%l33_0, Acquire, 1) - aie.dma_bd(%buf33_0 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf33_0 : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%l33_0, Release, 0) aie.next_bd ^end ^bd1: aie.use_lock(%l33_1, Acquire, 1) - aie.dma_bd(%buf33_1 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf33_1 : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%l33_1, Release, 0) aie.next_bd ^end ^end: diff --git a/test/Targets/AIEGenerateXAIE/tileDMA.mlir b/test/Targets/AIEGenerateXAIE/tileDMA.mlir index 4712b03340..b3d0d49058 100644 --- a/test/Targets/AIEGenerateXAIE/tileDMA.mlir +++ b/test/Targets/AIEGenerateXAIE/tileDMA.mlir @@ -34,7 +34,7 @@ module @aie_module { %38 = aie.dma_start(S2MM, 0, ^bb1, ^bb3) ^bb1: // 2 preds: ^bb0, ^bb1 aie.use_lock(%25, Acquire, 0) - aie.dma_bd(%24 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%24 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%25, Release, 1) aie.next_bd ^bb1 ^bb2: // pred: ^bb3 @@ -43,7 +43,7 @@ module @aie_module { %39 = aie.dma_start(MM2S, 0, ^bb4, ^bb2) ^bb4: // 2 preds: ^bb3, ^bb4 aie.use_lock(%27, Acquire, 1) - aie.dma_bd(%26 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%26 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%27, Release, 0) aie.next_bd ^bb4 } diff --git a/test/Targets/AIETargetAirbin/aie.mlir b/test/Targets/AIETargetAirbin/aie.mlir index 6af571ece5..a6754ab96e 100644 --- a/test/Targets/AIETargetAirbin/aie.mlir +++ b/test/Targets/AIETargetAirbin/aie.mlir @@ -148,22 +148,22 @@ module { %1 = aie.dma_start(MM2S, 0, ^bb4, ^bb6) ^bb2: // 2 preds: ^bb0, ^bb3 aie.use_lock(%lock_6_2, Acquire, 0) - aie.dma_bd(%buffer_6_2 : memref<8xi32>, 0, 8) + aie.dma_bd(%buffer_6_2 : memref<8xi32>) { len = 8 : i32 } aie.use_lock(%lock_6_2, Release, 1) aie.next_bd ^bb3 ^bb3: // pred: ^bb2 aie.use_lock(%lock_6_2_3, Acquire, 0) - aie.dma_bd(%buffer_6_2_1 : memref<8xi32>, 0, 8) + aie.dma_bd(%buffer_6_2_1 : memref<8xi32>) { len = 8 : i32 } aie.use_lock(%lock_6_2_3, Release, 1) aie.next_bd ^bb2 ^bb4: // 2 preds: ^bb1, ^bb5 aie.use_lock(%lock_6_2_4, Acquire, 1) - aie.dma_bd(%buffer_6_2_0 : memref<8xi32>, 0, 8) + aie.dma_bd(%buffer_6_2_0 : memref<8xi32>) { len = 8 : i32 } aie.use_lock(%lock_6_2_4, Release, 0) aie.next_bd ^bb5 ^bb5: // pred: ^bb4 aie.use_lock(%lock_6_2_5, Acquire, 1) - aie.dma_bd(%buffer_6_2_2 : memref<8xi32>, 0, 8) + aie.dma_bd(%buffer_6_2_2 : memref<8xi32>) { len = 8 : i32 } aie.use_lock(%lock_6_2_5, Release, 0) aie.next_bd ^bb4 ^bb6: // pred: ^bb1 diff --git a/test/assign-buffer-addresses/bad_alignment.mlir b/test/assign-buffer-addresses/bad_alignment.mlir new file mode 100644 index 0000000000..fc0f028e7b --- /dev/null +++ b/test/assign-buffer-addresses/bad_alignment.mlir @@ -0,0 +1,95 @@ +//===- bad_alignment.mlir --------------------------------------*- MLIR -*-===// +// +// This file is licensed under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +// (c) Copyright 2022 Xilinx Inc. +// +//===----------------------------------------------------------------------===// + +// RUN: aie-opt --verify-diagnostics --split-input-file %s + +module { + aie.device(ipu) { + %tile_0_1 = aie.tile(0, 1) + %memtile_dma_0_1 = aie.memtile_dma(%tile_0_1) { + %lock_0_1 = aie.lock(%tile_0_1) {init = 1 : i32} + %lock_0_1_0 = aie.lock(%tile_0_1) {init = 0 : i32} + %buffer_0_1 = aie.buffer(%tile_0_1) {address = 1 : i32} : memref<128xi16> + %0 = aie.dma(S2MM, 0) [{ + aie.use_lock(%lock_0_1, AcquireGreaterEqual) + // expected-error@+1 {{'aie.dma_bd' op bd address must be 4 byte (32b) aligned; got base+offset: 1 (bytes)}} + aie.dma_bd(%buffer_0_1 : memref<128xi16>) { len = 128 : i32 } + aie.use_lock(%lock_0_1_0, Release) + }] + aie.end + } + } +} + +// ----- + +module { + aie.device(ipu) { + %tile_0_1 = aie.tile(0, 1) + %memtile_dma_0_1 = aie.memtile_dma(%tile_0_1) { + %lock_0_1 = aie.lock(%tile_0_1) {init = 1 : i32} + %lock_0_1_0 = aie.lock(%tile_0_1) {init = 0 : i32} + %buffer_0_1 = aie.buffer(%tile_0_1) {address = 1 : i32} : memref<128xi16> + %0 = aie.dma(S2MM, 0) [{ + aie.use_lock(%lock_0_1, AcquireGreaterEqual) + aie.dma_bd(%buffer_0_1 : memref<128xi16>) { offset = 3 : i32, len = 128 : i32 } + // expected-error@above {{'aie.dma_bd' op bd address must be 4 byte (32b) aligned; got base+offset: 7 (bytes)}} + aie.use_lock(%lock_0_1_0, Release) + }] + aie.end + } + } +} + + +// ----- + +// Technically this should be in a "positive test" but it makes more sense here +// the "expected-above" in the previous test and the "expected-below" in the following test +// prevent false-positives/false-negatives (I think). + +module { + aie.device(ipu) { + %tile_0_1 = aie.tile(0, 1) + %memtile_dma_0_1 = aie.memtile_dma(%tile_0_1) { + %lock_0_1 = aie.lock(%tile_0_1) {init = 1 : i32} + %lock_0_1_0 = aie.lock(%tile_0_1) {init = 0 : i32} + %buffer_0_1 = aie.buffer(%tile_0_1) {address = 2 : i32} : memref<128xi16> + %0 = aie.dma(S2MM, 0) [{ + aie.use_lock(%lock_0_1, AcquireGreaterEqual) + // 2*6 + 2 = 8 bytes i.e., 4B aligned... + aie.dma_bd(%buffer_0_1 : memref<128xi16>) { offset = 3 : i32, len = 128 : i32 } + aie.use_lock(%lock_0_1_0, Release) + }] + aie.end + } + } +} + + +// ----- + +module { + aie.device(ipu) { + %tile_0_1 = aie.tile(0, 1) + %memtile_dma_0_1 = aie.memtile_dma(%tile_0_1) { + %lock_0_1 = aie.lock(%tile_0_1) {init = 1 : i32} + %lock_0_1_0 = aie.lock(%tile_0_1) {init = 0 : i32} + %buffer_0_1 = aie.buffer(%tile_0_1) {address = 0 : i32} : memref<128xi16> + %0 = aie.dma(S2MM, 0) [{ + aie.use_lock(%lock_0_1, AcquireGreaterEqual) + // expected-error@below {{'aie.dma_bd' op bd address must be 4 byte (32b) aligned; got base+offset: 6 (bytes)}} + aie.dma_bd(%buffer_0_1 : memref<128xi16>) { offset = 3 : i32, len = 128 : i32 } + aie.use_lock(%lock_0_1_0, Release) + }] + aie.end + } + } +} diff --git a/test/benchmarks/01_DDR_SHIM_LM_FillRate/aie.mlir b/test/benchmarks/01_DDR_SHIM_LM_FillRate/aie.mlir index c4bbfd2840..6821f17dbe 100755 --- a/test/benchmarks/01_DDR_SHIM_LM_FillRate/aie.mlir +++ b/test/benchmarks/01_DDR_SHIM_LM_FillRate/aie.mlir @@ -38,7 +38,7 @@ module @benchmark01_DDR_SHIM_fill_rate { ^bd0: aie.use_lock(%lock1, Acquire, 1) - aie.dma_bd(%buffer : memref<7168xi32>, 0, 7168) + aie.dma_bd(%buffer : memref<7168xi32>) { len = 7168 : i32 } aie.use_lock(%lock1, Release, 0) aie.next_bd ^bd0 ^end: @@ -54,7 +54,7 @@ module @benchmark01_DDR_SHIM_fill_rate { %srcDma = aie.dma_start(S2MM, 0, ^bd0, ^end) ^bd0: aie.use_lock(%l71_0, "Acquire", 0) - aie.dma_bd(%buf71_0 : memref< 7168xi32>, 0, 7168) + aie.dma_bd(%buf71_0 : memref< 7168xi32>) { len = 7168 : i32 } aie.use_lock(%l71_0, "Release", 1) aie.next_bd ^end ^end: diff --git a/test/benchmarks/02_LM_SHIM_DDR_FillRate/aie.mlir b/test/benchmarks/02_LM_SHIM_DDR_FillRate/aie.mlir index 6df5516d63..eb6f072e14 100755 --- a/test/benchmarks/02_LM_SHIM_DDR_FillRate/aie.mlir +++ b/test/benchmarks/02_LM_SHIM_DDR_FillRate/aie.mlir @@ -26,7 +26,7 @@ module @benchmark_02_LM2DDR { %srcDma = aie.dma_start(MM2S, 1, ^bd0, ^end) ^bd0: aie.use_lock(%lock_a_ping, "Acquire", 0) - aie.dma_bd(%buf71_0 : memref<7168xi32>, 0, 7168) + aie.dma_bd(%buf71_0 : memref<7168xi32>) { len = 7168 : i32 } aie.use_lock(%lock_a_ping, "Release", 1) aie.next_bd ^end ^end: @@ -40,7 +40,7 @@ module @benchmark_02_LM2DDR { ^bd0: aie.use_lock(%lock1, Acquire, 1) - aie.dma_bd(%buffer_out : memref<7168xi32>, 0, 7168) + aie.dma_bd(%buffer_out : memref<7168xi32>) { len = 7168 : i32 } aie.use_lock(%lock1, Release, 0) aie.next_bd ^bd0 ^end: diff --git a/test/benchmarks/03_Flood_DDR/aie.mlir b/test/benchmarks/03_Flood_DDR/aie.mlir index 952a76d1ea..2c1c35069c 100755 --- a/test/benchmarks/03_Flood_DDR/aie.mlir +++ b/test/benchmarks/03_Flood_DDR/aie.mlir @@ -35,7 +35,7 @@ module @benchmark03_Flood_DDR { %srcDma = aie.dma_start(S2MM, 0, ^bd0, ^end) ^bd0: aie.use_lock(%l21_0, "Acquire", 0) - aie.dma_bd(%buf21_0 : memref< 7168xi32>, 0, 7168) + aie.dma_bd(%buf21_0 : memref< 7168xi32>) { len = 7168 : i32 } aie.use_lock(%l21_0, "Release", 1) aie.next_bd ^end ^end: @@ -50,7 +50,7 @@ module @benchmark03_Flood_DDR { ^bd0: aie.use_lock(%l20, Acquire, 1) - aie.dma_bd(%buffer_out_20 : memref<7168xi32>, 0, 7168) + aie.dma_bd(%buffer_out_20 : memref<7168xi32>) { len = 7168 : i32 } aie.use_lock(%l20, Release, 0) aie.next_bd ^bd0 ^end: @@ -78,7 +78,7 @@ module @benchmark03_Flood_DDR { %srcDma = aie.dma_start(S2MM, 0, ^bd0, ^end) ^bd0: aie.use_lock(%l31_0, "Acquire", 0) - aie.dma_bd(%buf31_0 : memref< 7168xi32>, 0, 7168) + aie.dma_bd(%buf31_0 : memref< 7168xi32>) { len = 7168 : i32 } aie.use_lock(%l31_0, "Release", 1) aie.next_bd ^end ^end: @@ -94,7 +94,7 @@ module @benchmark03_Flood_DDR { ^bd0: aie.use_lock(%lock1, Acquire, 1) - aie.dma_bd(%buffer_out_30 : memref<7168xi32>, 0, 7168) + aie.dma_bd(%buffer_out_30 : memref<7168xi32>) { len = 7168 : i32 } aie.use_lock(%lock1, Release, 0) aie.next_bd ^bd0 ^end: @@ -122,7 +122,7 @@ module @benchmark03_Flood_DDR { %srcDma = aie.dma_start(S2MM, 0, ^bd0, ^end) ^bd0: aie.use_lock(%l61_0, "Acquire", 0) - aie.dma_bd(%buf61_0 : memref< 7168xi32>, 0, 7168) + aie.dma_bd(%buf61_0 : memref< 7168xi32>) { len = 7168 : i32 } aie.use_lock(%l61_0, "Release", 1) aie.next_bd ^end ^end: @@ -137,7 +137,7 @@ module @benchmark03_Flood_DDR { ^bd0: aie.use_lock(%lock1, Acquire, 1) - aie.dma_bd(%buffer_out_60 : memref<7168xi32>, 0, 7168) + aie.dma_bd(%buffer_out_60 : memref<7168xi32>) { len = 7168 : i32 } aie.use_lock(%lock1, Release, 0) aie.next_bd ^bd0 ^end: @@ -168,7 +168,7 @@ module @benchmark03_Flood_DDR { %srcDma = aie.dma_start(S2MM, 0, ^bd0, ^end) ^bd0: aie.use_lock(%l71_0, "Acquire", 0) - aie.dma_bd(%buf71_0 : memref< 7168xi32>, 0, 7168) + aie.dma_bd(%buf71_0 : memref< 7168xi32>) { len = 7168 : i32 } aie.use_lock(%l71_0, "Release", 1) aie.next_bd ^end ^end: @@ -184,7 +184,7 @@ module @benchmark03_Flood_DDR { ^bd0: aie.use_lock(%lock1, Acquire, 1) - aie.dma_bd(%buffer_out_70 : memref<7168xi32>, 0, 7168) + aie.dma_bd(%buffer_out_70 : memref<7168xi32>) { len = 7168 : i32 } aie.use_lock(%lock1, Release, 0) aie.next_bd ^bd0 ^end: @@ -215,7 +215,7 @@ module @benchmark03_Flood_DDR { %srcDma = aie.dma_start(S2MM, 0, ^bd0, ^end) ^bd0: aie.use_lock(%l101_0, "Acquire", 0) - aie.dma_bd(%buf101_0 : memref< 7168xi32>, 0, 7168) + aie.dma_bd(%buf101_0 : memref< 7168xi32>) { len = 7168 : i32 } aie.use_lock(%l101_0, "Release", 1) aie.next_bd ^end ^end: @@ -230,7 +230,7 @@ module @benchmark03_Flood_DDR { ^bd0: aie.use_lock(%lock1, Acquire, 1) - aie.dma_bd(%buffer_out_100 : memref<7168xi32>, 0, 7168) + aie.dma_bd(%buffer_out_100 : memref<7168xi32>) { len = 7168 : i32 } aie.use_lock(%lock1, Release, 0) aie.next_bd ^bd0 ^end: @@ -258,7 +258,7 @@ module @benchmark03_Flood_DDR { %srcDma = aie.dma_start(S2MM, 0, ^bd0, ^end) ^bd0: aie.use_lock(%l111_0, "Acquire", 0) - aie.dma_bd(%buf111_0 : memref< 7168xi32>, 0, 7168) + aie.dma_bd(%buf111_0 : memref< 7168xi32>) { len = 7168 : i32 } aie.use_lock(%l111_0, "Release", 1) aie.next_bd ^end ^end: @@ -273,7 +273,7 @@ module @benchmark03_Flood_DDR { ^bd0: aie.use_lock(%lock1, Acquire, 1) - aie.dma_bd(%buffer_out_110 : memref<7168xi32>, 0, 7168) + aie.dma_bd(%buffer_out_110 : memref<7168xi32>) { len = 7168 : i32 } aie.use_lock(%lock1, Release, 0) aie.next_bd ^bd0 ^end: @@ -301,7 +301,7 @@ module @benchmark03_Flood_DDR { %srcDma = aie.dma_start(S2MM, 0, ^bd0, ^end) ^bd0: aie.use_lock(%l181_0, "Acquire", 0) - aie.dma_bd(%buf181_0 : memref< 7168xi32>, 0, 7168) + aie.dma_bd(%buf181_0 : memref< 7168xi32>) { len = 7168 : i32 } aie.use_lock(%l181_0, "Release", 1) aie.next_bd ^end ^end: @@ -317,7 +317,7 @@ module @benchmark03_Flood_DDR { ^bd0: aie.use_lock(%lock1, Acquire, 1) - aie.dma_bd(%buffer_out_180 : memref<7168xi32>, 0, 7168) + aie.dma_bd(%buffer_out_180 : memref<7168xi32>) { len = 7168 : i32 } aie.use_lock(%lock1, Release, 0) aie.next_bd ^bd0 ^end: @@ -346,7 +346,7 @@ module @benchmark03_Flood_DDR { %srcDma = aie.dma_start(S2MM, 0, ^bd0, ^end) ^bd0: aie.use_lock(%l191_0, "Acquire", 0) - aie.dma_bd(%buf191_0 : memref< 7168xi32>, 0, 7168) + aie.dma_bd(%buf191_0 : memref< 7168xi32>) { len = 7168 : i32 } aie.use_lock(%l191_0, "Release", 1) aie.next_bd ^end ^end: @@ -361,7 +361,7 @@ module @benchmark03_Flood_DDR { ^bd0: aie.use_lock(%lock1, Acquire, 1) - aie.dma_bd(%buffer_out_190 : memref<7168xi32>, 0, 7168) + aie.dma_bd(%buffer_out_190 : memref<7168xi32>) { len = 7168 : i32 } aie.use_lock(%lock1, Release, 0) aie.next_bd ^bd0 ^end: @@ -389,7 +389,7 @@ module @benchmark03_Flood_DDR { %srcDma = aie.dma_start(S2MM, 0, ^bd0, ^end) ^bd0: aie.use_lock(%l261_0, "Acquire", 0) - aie.dma_bd(%buf261_0 : memref< 7168xi32>, 0, 7168) + aie.dma_bd(%buf261_0 : memref< 7168xi32>) { len = 7168 : i32 } aie.use_lock(%l261_0, "Release", 1) aie.next_bd ^end ^end: @@ -405,7 +405,7 @@ module @benchmark03_Flood_DDR { ^bd0: aie.use_lock(%lock1, Acquire, 1) - aie.dma_bd(%buffer_out_260 : memref<7168xi32>, 0, 7168) + aie.dma_bd(%buffer_out_260 : memref<7168xi32>) { len = 7168 : i32 } aie.use_lock(%lock1, Release, 0) aie.next_bd ^bd0 ^end: @@ -434,7 +434,7 @@ module @benchmark03_Flood_DDR { %srcDma = aie.dma_start(S2MM, 0, ^bd0, ^end) ^bd0: aie.use_lock(%l271_0, "Acquire", 0) - aie.dma_bd(%buf271_0 : memref< 7168xi32>, 0, 7168) + aie.dma_bd(%buf271_0 : memref< 7168xi32>) { len = 7168 : i32 } aie.use_lock(%l271_0, "Release", 1) aie.next_bd ^end ^end: @@ -450,7 +450,7 @@ module @benchmark03_Flood_DDR { ^bd0: aie.use_lock(%lock1, Acquire, 1) - aie.dma_bd(%buffer_out_270 : memref<7168xi32>, 0, 7168) + aie.dma_bd(%buffer_out_270 : memref<7168xi32>) { len = 7168 : i32 } aie.use_lock(%lock1, Release, 0) aie.next_bd ^bd0 ^end: @@ -478,7 +478,7 @@ module @benchmark03_Flood_DDR { %srcDma = aie.dma_start(S2MM, 0, ^bd0, ^end) ^bd0: aie.use_lock(%l341_0, "Acquire", 0) - aie.dma_bd(%buf341_0 : memref< 7168xi32>, 0, 7168) + aie.dma_bd(%buf341_0 : memref< 7168xi32>) { len = 7168 : i32 } aie.use_lock(%l341_0, "Release", 1) aie.next_bd ^end ^end: @@ -493,7 +493,7 @@ module @benchmark03_Flood_DDR { ^bd0: aie.use_lock(%lock1, Acquire, 1) - aie.dma_bd(%buffer_out_340 : memref<7168xi32>, 0, 7168) + aie.dma_bd(%buffer_out_340 : memref<7168xi32>) { len = 7168 : i32 } aie.use_lock(%lock1, Release, 0) aie.next_bd ^bd0 ^end: @@ -521,7 +521,7 @@ module @benchmark03_Flood_DDR { %srcDma = aie.dma_start(S2MM, 0, ^bd0, ^end) ^bd0: aie.use_lock(%l351_0, "Acquire", 0) - aie.dma_bd(%buf351_0 : memref< 7168xi32>, 0, 7168) + aie.dma_bd(%buf351_0 : memref< 7168xi32>) { len = 7168 : i32 } aie.use_lock(%l351_0, "Release", 1) aie.next_bd ^end ^end: @@ -536,7 +536,7 @@ module @benchmark03_Flood_DDR { ^bd0: aie.use_lock(%lock1, Acquire, 1) - aie.dma_bd(%buffer_out_350 : memref<7168xi32>, 0, 7168) + aie.dma_bd(%buffer_out_350 : memref<7168xi32>) { len = 7168 : i32 } aie.use_lock(%lock1, Release, 0) aie.next_bd ^bd0 ^end: @@ -557,7 +557,7 @@ module @benchmark03_Flood_DDR { %srcDma = aie.dma_start(S2MM, 0, ^bd0, ^end) ^bd0: aie.use_lock(%l421, "Acquire", 0) - aie.dma_bd(%buf421_0 : memref< 7168xi32>, 0, 7168) + aie.dma_bd(%buf421_0 : memref< 7168xi32>) { len = 7168 : i32 } aie.use_lock(%l421, "Release", 1) aie.next_bd ^end ^end: @@ -573,7 +573,7 @@ module @benchmark03_Flood_DDR { ^bd0: aie.use_lock(%lock1, Acquire, 1) - aie.dma_bd(%buffer_out_420 : memref<7168xi32>, 0, 7168) + aie.dma_bd(%buffer_out_420 : memref<7168xi32>) { len = 7168 : i32 } aie.use_lock(%lock1, Release, 0) aie.next_bd ^bd0 ^end: @@ -601,7 +601,7 @@ module @benchmark03_Flood_DDR { %srcDma = aie.dma_start(S2MM, 0, ^bd0, ^end) ^bd0: aie.use_lock(%l431_0, "Acquire", 0) - aie.dma_bd(%buf431_0 : memref< 7168xi32>, 0, 7168) + aie.dma_bd(%buf431_0 : memref< 7168xi32>) { len = 7168 : i32 } aie.use_lock(%l431_0, "Release", 1) aie.next_bd ^end ^end: @@ -617,7 +617,7 @@ module @benchmark03_Flood_DDR { ^bd0: aie.use_lock(%l430, Acquire, 1) - aie.dma_bd(%buffer_out_430 : memref<7168xi32>, 0, 7168) + aie.dma_bd(%buffer_out_430 : memref<7168xi32>) { len = 7168 : i32 } aie.use_lock(%l430, Release, 0) aie.next_bd ^bd0 ^end: @@ -646,7 +646,7 @@ module @benchmark03_Flood_DDR { %srcDma = aie.dma_start(S2MM, 0, ^bd0, ^end) ^bd0: aie.use_lock(%l461_0, "Acquire", 0) - aie.dma_bd(%buf461_0 : memref< 7168xi32>, 0, 7168) + aie.dma_bd(%buf461_0 : memref< 7168xi32>) { len = 7168 : i32 } aie.use_lock(%l461_0, "Release", 1) aie.next_bd ^end ^end: @@ -661,7 +661,7 @@ module @benchmark03_Flood_DDR { ^bd0: aie.use_lock(%l460, Acquire, 1) - aie.dma_bd(%buffer_out_460 : memref<7168xi32>, 0, 7168) + aie.dma_bd(%buffer_out_460 : memref<7168xi32>) { len = 7168 : i32 } aie.use_lock(%l460, Release, 0) aie.next_bd ^bd0 ^end: @@ -690,7 +690,7 @@ module @benchmark03_Flood_DDR { %srcDma = aie.dma_start(S2MM, 0, ^bd0, ^end) ^bd0: aie.use_lock(%l471_0, "Acquire", 0) - aie.dma_bd(%buf471_0 : memref< 7168xi32>, 0, 7168) + aie.dma_bd(%buf471_0 : memref< 7168xi32>) { len = 7168 : i32 } aie.use_lock(%l471_0, "Release", 1) aie.next_bd ^end ^end: @@ -706,7 +706,7 @@ module @benchmark03_Flood_DDR { ^bd0: aie.use_lock(%l470, Acquire, 1) - aie.dma_bd(%buffer_out_470 : memref<7168xi32>, 0, 7168) + aie.dma_bd(%buffer_out_470 : memref<7168xi32>) { len = 7168 : i32 } aie.use_lock(%l470, Release, 0) aie.next_bd ^bd0 ^end: diff --git a/test/benchmarks/04_Tile_Tile_FillRate/aie.mlir b/test/benchmarks/04_Tile_Tile_FillRate/aie.mlir index 7375379230..2539cd0690 100755 --- a/test/benchmarks/04_Tile_Tile_FillRate/aie.mlir +++ b/test/benchmarks/04_Tile_Tile_FillRate/aie.mlir @@ -29,7 +29,7 @@ module @test04_tile_tiledma { %dma0 = aie.dma_start(MM2S, 0, ^bd0, ^end) ^bd0: aie.use_lock(%lock13_5, "Acquire", 1) - aie.dma_bd(%buf13_0 : memref<512xi32>, 0, 512) + aie.dma_bd(%buf13_0 : memref<512xi32>) { len = 512 : i32 } aie.use_lock(%lock13_5, "Release", 0) aie.next_bd ^end // point to the next BD, or termination ^end: @@ -45,7 +45,7 @@ module @test04_tile_tiledma { %dma0 = aie.dma_start(S2MM, 1, ^bd0, ^end) ^bd0: aie.use_lock(%lock14_6, "Acquire", 0) - aie.dma_bd(%buf14_0: memref<512xi32>, 0, 512) + aie.dma_bd(%buf14_0: memref<512xi32>) { len = 512 : i32 } aie.use_lock(%lock14_6, "Release", 1) aie.next_bd ^end // point to the next BD, or termination ^end: diff --git a/test/benchmarks/12_Stream_Delay/aie.mlir b/test/benchmarks/12_Stream_Delay/aie.mlir index 9065afa98b..267509507a 100755 --- a/test/benchmarks/12_Stream_Delay/aie.mlir +++ b/test/benchmarks/12_Stream_Delay/aie.mlir @@ -34,7 +34,7 @@ module @test12_stream_delay { %dma0 = aie.dma_start(MM2S, 0, ^bd0, ^end) ^bd0: aie.use_lock(%lock13_5, "Acquire", 1) - aie.dma_bd(%buf13_0 : memref<512xi32>, 0, 512) + aie.dma_bd(%buf13_0 : memref<512xi32>) { len = 512 : i32 } aie.use_lock(%lock13_5, "Release", 0) aie.next_bd ^end ^end: @@ -52,7 +52,7 @@ module @test12_stream_delay { %dma0 = aie.dma_start(S2MM, 1, ^bd0, ^end) ^bd0: aie.use_lock(%lock43_6, "Acquire", 0) - aie.dma_bd(%buf43_0: memref<512xi32>, 0, 512) + aie.dma_bd(%buf43_0: memref<512xi32>) { len = 512 : i32 } aie.use_lock(%lock43_6, "Release", 1) aie.next_bd ^end ^end: diff --git a/test/create-cores/duplicate_dma.mlir b/test/create-cores/duplicate_dma.mlir index f68073c79d..ebbaaf5796 100644 --- a/test/create-cores/duplicate_dma.mlir +++ b/test/create-cores/duplicate_dma.mlir @@ -19,14 +19,14 @@ module @duplicate_dma { %15 = aie.dma_start(MM2S, 0, ^bb1, ^bb4) ^bb1: // pred: ^bb0 aiex.useToken @token0(Acquire, 1) - aie.dma_bd(%1 : memref<256xi32>, 0, 256) + aie.dma_bd(%1 : memref<256xi32>) { len = 256 : i32 } aiex.useToken @token0(Release, 2) aie.next_bd ^bb2 ^bb2: %16 = aie.dma_start(MM2S, 0, ^bb3, ^bb4) ^bb3: aiex.useToken @token1(Acquire, 1) - aie.dma_bd(%1 : memref<256xi32>, 0, 256) + aie.dma_bd(%1 : memref<256xi32>) { len = 256 : i32 } aiex.useToken @token1(Release, 2) aie.next_bd ^bb4 ^bb4: // 4 preds: ^bb0, ^bb1, ^bb2, ^bb3 diff --git a/test/create-cores/hello_world.mlir b/test/create-cores/hello_world.mlir index 39083a89f4..d05639d874 100644 --- a/test/create-cores/hello_world.mlir +++ b/test/create-cores/hello_world.mlir @@ -17,7 +17,7 @@ // CHECK: %[[VAL_3:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb2) // CHECK: ^bb1: // CHECK: aiex.useToken @token0(Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_1]] : memref<512xi32>, 0, 512) +// CHECK: aie.dma_bd(%[[VAL_1]] : memref<512xi32>) {len = 512 : i32} // CHECK: aiex.useToken @token0(Release, 2) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: @@ -29,7 +29,7 @@ // CHECK: %[[VAL_7:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb2) // CHECK: ^bb1: // CHECK: aiex.useToken @token0(Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_5]] : memref<512xi32>, 0, 512) +// CHECK: aie.dma_bd(%[[VAL_5]] : memref<512xi32>) {len = 512 : i32} // CHECK: aiex.useToken @token0(Release, 2) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: diff --git a/test/create-cores/test_dma0.mlir b/test/create-cores/test_dma0.mlir index cd8040badc..72b488c33f 100644 --- a/test/create-cores/test_dma0.mlir +++ b/test/create-cores/test_dma0.mlir @@ -17,7 +17,7 @@ // CHECK: %[[VAL_3:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb2) // CHECK: ^bb1: // CHECK: aiex.useToken @token0(Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_1]] : memref<256xi32>, 0, 256) +// CHECK: aie.dma_bd(%[[VAL_1]] : memref<256xi32>) {len = 256 : i32} // CHECK: aiex.useToken @token0(Release, 2) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: @@ -29,7 +29,7 @@ // CHECK: %[[VAL_7:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb2) // CHECK: ^bb1: // CHECK: aiex.useToken @token0(Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_5]] : memref<256xi32>, 0, 256) +// CHECK: aie.dma_bd(%[[VAL_5]] : memref<256xi32>) {len = 256 : i32} // CHECK: aiex.useToken @token0(Release, 2) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: diff --git a/test/create-cores/test_dma1.mlir b/test/create-cores/test_dma1.mlir index 218866533e..ac871e1991 100644 --- a/test/create-cores/test_dma1.mlir +++ b/test/create-cores/test_dma1.mlir @@ -20,14 +20,14 @@ // CHECK: %[[VAL_3:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb4) // CHECK: ^bb1: // CHECK: aiex.useToken @token0(Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_1]] : memref<256xi32>, 0, 256) +// CHECK: aie.dma_bd(%[[VAL_1]] : memref<256xi32>) {len = 256 : i32} // CHECK: aiex.useToken @token0(Release, 2) // CHECK: aie.next_bd ^bb4 // CHECK: ^bb2: // CHECK: %[[VAL_4:.*]] = aie.dma_start(MM2S, 0, ^bb3, ^bb4) // CHECK: ^bb3: // CHECK: aiex.useToken @token1(Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_1]] : memref<256xi32>, 0, 256) +// CHECK: aie.dma_bd(%[[VAL_1]] : memref<256xi32>) {len = 256 : i32} // CHECK: aiex.useToken @token1(Release, 2) // CHECK: aie.next_bd ^bb4 // CHECK: ^bb4: @@ -39,7 +39,7 @@ // CHECK: %[[VAL_8:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb2) // CHECK: ^bb1: // CHECK: aiex.useToken @token0(Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_6]] : memref<256xi32>, 0, 256) +// CHECK: aie.dma_bd(%[[VAL_6]] : memref<256xi32>) {len = 256 : i32} // CHECK: aiex.useToken @token0(Release, 2) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: @@ -51,7 +51,7 @@ // CHECK: %[[VAL_12:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb2) // CHECK: ^bb1: // CHECK: aiex.useToken @token1(Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_10]] : memref<256xi32>, 0, 256) +// CHECK: aie.dma_bd(%[[VAL_10]] : memref<256xi32>) {len = 256 : i32} // CHECK: aiex.useToken @token1(Release, 2) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: diff --git a/test/create-cores/test_dma2.mlir b/test/create-cores/test_dma2.mlir index d47af5c57a..7ff484159f 100644 --- a/test/create-cores/test_dma2.mlir +++ b/test/create-cores/test_dma2.mlir @@ -18,7 +18,7 @@ // CHECK: %[[VAL_3:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb2) // CHECK: ^bb1: // CHECK: aiex.useToken @token0(Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_1]] : memref<256xi32>, 0, 256) +// CHECK: aie.dma_bd(%[[VAL_1]] : memref<256xi32>) {len = 256 : i32} // CHECK: aiex.useToken @token0(Release, 2) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: @@ -30,7 +30,7 @@ // CHECK: %[[VAL_7:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb2) // CHECK: ^bb1: // CHECK: aiex.useToken @token1(Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_5]] : memref<256xi32>, 0, 256) +// CHECK: aie.dma_bd(%[[VAL_5]] : memref<256xi32>) {len = 256 : i32} // CHECK: aiex.useToken @token1(Release, 2) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: @@ -43,14 +43,14 @@ // CHECK: %[[VAL_12:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) // CHECK: ^bb1: // CHECK: aiex.useToken @token0(Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_9]] : memref<256xi32>, 0, 256) +// CHECK: aie.dma_bd(%[[VAL_9]] : memref<256xi32>) {len = 256 : i32} // CHECK: aiex.useToken @token0(Release, 2) // CHECK: aie.next_bd ^bb4 // CHECK: ^bb2: // CHECK: %[[VAL_13:.*]] = aie.dma_start(S2MM, 0, ^bb3, ^bb4) // CHECK: ^bb3: // CHECK: aiex.useToken @token1(Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_10]] : memref<256xi32>, 0, 256) +// CHECK: aie.dma_bd(%[[VAL_10]] : memref<256xi32>) {len = 256 : i32} // CHECK: aiex.useToken @token1(Release, 2) // CHECK: aie.next_bd ^bb4 // CHECK: ^bb4: diff --git a/test/create-cores/test_dma3.mlir b/test/create-cores/test_dma3.mlir index 5cd4638a7b..f995b6869a 100644 --- a/test/create-cores/test_dma3.mlir +++ b/test/create-cores/test_dma3.mlir @@ -18,7 +18,7 @@ // CHECK: %[[VAL_3:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb2) // CHECK: ^bb1: // CHECK: aiex.useToken @token0(Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_1]] : memref<256xi32>, 0, 256) +// CHECK: aie.dma_bd(%[[VAL_1]] : memref<256xi32>) {len = 256 : i32} // CHECK: aiex.useToken @token0(Release, 2) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: @@ -30,14 +30,14 @@ // CHECK: %[[VAL_7:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) // CHECK: ^bb1: // CHECK: aiex.useToken @token0(Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_5]] : memref<256xi32>, 0, 256) +// CHECK: aie.dma_bd(%[[VAL_5]] : memref<256xi32>) {len = 256 : i32} // CHECK: aiex.useToken @token0(Release, 2) // CHECK: aie.next_bd ^bb4 // CHECK: ^bb2: // CHECK: %[[VAL_8:.*]] = aie.dma_start(MM2S, 0, ^bb3, ^bb4) // CHECK: ^bb3: // CHECK: aiex.useToken @token0(Acquire, 3) -// CHECK: aie.dma_bd(%[[VAL_5]] : memref<256xi32>, 0, 256) +// CHECK: aie.dma_bd(%[[VAL_5]] : memref<256xi32>) {len = 256 : i32} // CHECK: aiex.useToken @token0(Release, 4) // CHECK: aie.next_bd ^bb4 // CHECK: ^bb4: @@ -49,7 +49,7 @@ // CHECK: %[[VAL_12:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb2) // CHECK: ^bb1: // CHECK: aiex.useToken @token0(Acquire, 3) -// CHECK: aie.dma_bd(%[[VAL_10]] : memref<256xi32>, 0, 256) +// CHECK: aie.dma_bd(%[[VAL_10]] : memref<256xi32>) {len = 256 : i32} // CHECK: aiex.useToken @token0(Release, 4) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: diff --git a/test/create-flows/mmult.mlir b/test/create-flows/mmult.mlir index e74232077b..9c4d407d93 100644 --- a/test/create-flows/mmult.mlir +++ b/test/create-flows/mmult.mlir @@ -50,26 +50,26 @@ module @aie.herd_0 { %63 = aie.dma_start(S2MM, 0, ^bb1, ^bb5) ^bb1: // 2 preds: ^bb0, ^bb2 aie.use_lock(%9, Acquire, 0) - aie.dma_bd(%10 : memref<16x16xf32, 2>, 0, 256) + aie.dma_bd(%10 : memref<16x16xf32, 2>) { len = 256 : i32 } aie.use_lock(%9, Release, 1) aie.next_bd ^bb2 ^bb2: // pred: ^bb1 aie.use_lock(%4, Acquire, 0) - aie.dma_bd(%6 : memref<16x16xf32, 2>, 0, 256) + aie.dma_bd(%6 : memref<16x16xf32, 2>) { len = 256 : i32 } aie.use_lock(%4, Release, 1) aie.next_bd ^bb1 ^bb3: // pred: ^bb5 %64 = aie.dma_start(S2MM, 1, ^bb4, ^bb7) ^bb4: // 2 preds: ^bb3, ^bb4 aie.use_lock(%7, Acquire, 0) - aie.dma_bd(%8 : memref<16x16xf32, 2>, 0, 256) + aie.dma_bd(%8 : memref<16x16xf32, 2>) { len = 256 : i32 } aie.use_lock(%7, Release, 1) aie.next_bd ^bb4 ^bb5: // pred: ^bb0 %65 = aie.dma_start(MM2S, 0, ^bb6, ^bb3) ^bb6: // 2 preds: ^bb5, ^bb6 aie.use_lock(%5, Acquire, 1) - aie.dma_bd(%6 : memref<16x16xf32, 2>, 0, 256) + aie.dma_bd(%6 : memref<16x16xf32, 2>) { len = 256 : i32 } aie.use_lock(%5, Release, 0) aie.next_bd ^bb6 ^bb7: // pred: ^bb3 @@ -91,26 +91,26 @@ module @aie.herd_0 { %63 = aie.dma_start(S2MM, 0, ^bb1, ^bb5) ^bb1: // 2 preds: ^bb0, ^bb2 aie.use_lock(%23, Acquire, 0) - aie.dma_bd(%24 : memref<16x16xf32, 2>, 0, 256) + aie.dma_bd(%24 : memref<16x16xf32, 2>) { len = 256 : i32 } aie.use_lock(%23, Release, 1) aie.next_bd ^bb2 ^bb2: // pred: ^bb1 aie.use_lock(%18, Acquire, 0) - aie.dma_bd(%20 : memref<16x16xf32, 2>, 0, 256) + aie.dma_bd(%20 : memref<16x16xf32, 2>) { len = 256 : i32 } aie.use_lock(%18, Release, 1) aie.next_bd ^bb1 ^bb3: // pred: ^bb5 %64 = aie.dma_start(S2MM, 1, ^bb4, ^bb7) ^bb4: // 2 preds: ^bb3, ^bb4 aie.use_lock(%21, Acquire, 0) - aie.dma_bd(%22 : memref<16x16xf32, 2>, 0, 256) + aie.dma_bd(%22 : memref<16x16xf32, 2>) { len = 256 : i32 } aie.use_lock(%21, Release, 1) aie.next_bd ^bb4 ^bb5: // pred: ^bb0 %65 = aie.dma_start(MM2S, 0, ^bb6, ^bb3) ^bb6: // 2 preds: ^bb5, ^bb6 aie.use_lock(%19, Acquire, 1) - aie.dma_bd(%20 : memref<16x16xf32, 2>, 0, 256) + aie.dma_bd(%20 : memref<16x16xf32, 2>) { len = 256 : i32 } aie.use_lock(%19, Release, 0) aie.next_bd ^bb6 ^bb7: // pred: ^bb3 @@ -132,26 +132,26 @@ module @aie.herd_0 { %63 = aie.dma_start(S2MM, 0, ^bb1, ^bb5) ^bb1: // 2 preds: ^bb0, ^bb2 aie.use_lock(%37, Acquire, 0) - aie.dma_bd(%38 : memref<16x16xf32, 2>, 0, 256) + aie.dma_bd(%38 : memref<16x16xf32, 2>) { len = 256 : i32 } aie.use_lock(%37, Release, 1) aie.next_bd ^bb2 ^bb2: // pred: ^bb1 aie.use_lock(%32, Acquire, 0) - aie.dma_bd(%34 : memref<16x16xf32, 2>, 0, 256) + aie.dma_bd(%34 : memref<16x16xf32, 2>) { len = 256 : i32 } aie.use_lock(%32, Release, 1) aie.next_bd ^bb1 ^bb3: // pred: ^bb5 %64 = aie.dma_start(S2MM, 1, ^bb4, ^bb7) ^bb4: // 2 preds: ^bb3, ^bb4 aie.use_lock(%35, Acquire, 0) - aie.dma_bd(%36 : memref<16x16xf32, 2>, 0, 256) + aie.dma_bd(%36 : memref<16x16xf32, 2>) { len = 256 : i32 } aie.use_lock(%35, Release, 1) aie.next_bd ^bb4 ^bb5: // pred: ^bb0 %65 = aie.dma_start(MM2S, 0, ^bb6, ^bb3) ^bb6: // 2 preds: ^bb5, ^bb6 aie.use_lock(%33, Acquire, 1) - aie.dma_bd(%34 : memref<16x16xf32, 2>, 0, 256) + aie.dma_bd(%34 : memref<16x16xf32, 2>) { len = 256 : i32 } aie.use_lock(%33, Release, 0) aie.next_bd ^bb6 ^bb7: // pred: ^bb3 @@ -173,26 +173,26 @@ module @aie.herd_0 { %63 = aie.dma_start(S2MM, 0, ^bb1, ^bb5) ^bb1: // 2 preds: ^bb0, ^bb2 aie.use_lock(%51, Acquire, 0) - aie.dma_bd(%52 : memref<16x16xf32, 2>, 0, 256) + aie.dma_bd(%52 : memref<16x16xf32, 2>) { len = 256 : i32 } aie.use_lock(%51, Release, 1) aie.next_bd ^bb2 ^bb2: // pred: ^bb1 aie.use_lock(%46, Acquire, 0) - aie.dma_bd(%48 : memref<16x16xf32, 2>, 0, 256) + aie.dma_bd(%48 : memref<16x16xf32, 2>) { len = 256 : i32 } aie.use_lock(%46, Release, 1) aie.next_bd ^bb1 ^bb3: // pred: ^bb5 %64 = aie.dma_start(S2MM, 1, ^bb4, ^bb7) ^bb4: // 2 preds: ^bb3, ^bb4 aie.use_lock(%49, Acquire, 0) - aie.dma_bd(%50 : memref<16x16xf32, 2>, 0, 256) + aie.dma_bd(%50 : memref<16x16xf32, 2>) { len = 256 : i32 } aie.use_lock(%49, Release, 1) aie.next_bd ^bb4 ^bb5: // pred: ^bb0 %65 = aie.dma_start(MM2S, 0, ^bb6, ^bb3) ^bb6: // 2 preds: ^bb5, ^bb6 aie.use_lock(%47, Acquire, 1) - aie.dma_bd(%48 : memref<16x16xf32, 2>, 0, 256) + aie.dma_bd(%48 : memref<16x16xf32, 2>) { len = 256 : i32 } aie.use_lock(%47, Release, 0) aie.next_bd ^bb6 ^bb7: // pred: ^bb3 diff --git a/test/create-flows/unit_mmult.mlir b/test/create-flows/unit_mmult.mlir index 876f09333d..5d6406f0c9 100644 --- a/test/create-flows/unit_mmult.mlir +++ b/test/create-flows/unit_mmult.mlir @@ -26,26 +26,26 @@ // CHECK: %[[VAL_12:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb5) // CHECK: ^bb1: // CHECK: aie.use_lock(%[[VAL_9]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_10]] : memref<16x16xf32, 2>, 0, 256) +// CHECK: aie.dma_bd(%[[VAL_10]] : memref<16x16xf32, 2>) {len = 256 : i32} // CHECK: aie.use_lock(%[[VAL_9]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // CHECK: aie.use_lock(%[[VAL_4]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_6]] : memref<16x16xf32, 2>, 0, 256) +// CHECK: aie.dma_bd(%[[VAL_6]] : memref<16x16xf32, 2>) {len = 256 : i32} // CHECK: aie.use_lock(%[[VAL_4]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb3: // CHECK: %[[VAL_13:.*]] = aie.dma_start(S2MM, 1, ^bb4, ^bb7) // CHECK: ^bb4: // CHECK: aie.use_lock(%[[VAL_7]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_8]] : memref<16x16xf32, 2>, 0, 256) +// CHECK: aie.dma_bd(%[[VAL_8]] : memref<16x16xf32, 2>) {len = 256 : i32} // CHECK: aie.use_lock(%[[VAL_7]], Release, 1) // CHECK: aie.next_bd ^bb4 // CHECK: ^bb5: // CHECK: %[[VAL_14:.*]] = aie.dma_start(MM2S, 0, ^bb6, ^bb3) // CHECK: ^bb6: // CHECK: aie.use_lock(%[[VAL_5]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_6]] : memref<16x16xf32, 2>, 0, 256) +// CHECK: aie.dma_bd(%[[VAL_6]] : memref<16x16xf32, 2>) {len = 256 : i32} // CHECK: aie.use_lock(%[[VAL_5]], Release, 0) // CHECK: aie.next_bd ^bb6 // CHECK: ^bb7: @@ -67,26 +67,26 @@ // CHECK: %[[VAL_28:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb5) // CHECK: ^bb1: // CHECK: aie.use_lock(%[[VAL_25]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_26]] : memref<16x16xf32, 2>, 0, 256) +// CHECK: aie.dma_bd(%[[VAL_26]] : memref<16x16xf32, 2>) {len = 256 : i32} // CHECK: aie.use_lock(%[[VAL_25]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // CHECK: aie.use_lock(%[[VAL_20]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_22]] : memref<16x16xf32, 2>, 0, 256) +// CHECK: aie.dma_bd(%[[VAL_22]] : memref<16x16xf32, 2>) {len = 256 : i32} // CHECK: aie.use_lock(%[[VAL_20]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb3: // CHECK: %[[VAL_29:.*]] = aie.dma_start(S2MM, 1, ^bb4, ^bb7) // CHECK: ^bb4: // CHECK: aie.use_lock(%[[VAL_23]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_24]] : memref<16x16xf32, 2>, 0, 256) +// CHECK: aie.dma_bd(%[[VAL_24]] : memref<16x16xf32, 2>) {len = 256 : i32} // CHECK: aie.use_lock(%[[VAL_23]], Release, 1) // CHECK: aie.next_bd ^bb4 // CHECK: ^bb5: // CHECK: %[[VAL_30:.*]] = aie.dma_start(MM2S, 0, ^bb6, ^bb3) // CHECK: ^bb6: // CHECK: aie.use_lock(%[[VAL_21]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_22]] : memref<16x16xf32, 2>, 0, 256) +// CHECK: aie.dma_bd(%[[VAL_22]] : memref<16x16xf32, 2>) {len = 256 : i32} // CHECK: aie.use_lock(%[[VAL_21]], Release, 0) // CHECK: aie.next_bd ^bb6 // CHECK: ^bb7: @@ -108,26 +108,26 @@ // CHECK: %[[VAL_44:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb5) // CHECK: ^bb1: // CHECK: aie.use_lock(%[[VAL_41]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_42]] : memref<16x16xf32, 2>, 0, 256) +// CHECK: aie.dma_bd(%[[VAL_42]] : memref<16x16xf32, 2>) {len = 256 : i32} // CHECK: aie.use_lock(%[[VAL_41]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // CHECK: aie.use_lock(%[[VAL_36]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_38]] : memref<16x16xf32, 2>, 0, 256) +// CHECK: aie.dma_bd(%[[VAL_38]] : memref<16x16xf32, 2>) {len = 256 : i32} // CHECK: aie.use_lock(%[[VAL_36]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb3: // CHECK: %[[VAL_45:.*]] = aie.dma_start(S2MM, 1, ^bb4, ^bb7) // CHECK: ^bb4: // CHECK: aie.use_lock(%[[VAL_39]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_40]] : memref<16x16xf32, 2>, 0, 256) +// CHECK: aie.dma_bd(%[[VAL_40]] : memref<16x16xf32, 2>) {len = 256 : i32} // CHECK: aie.use_lock(%[[VAL_39]], Release, 1) // CHECK: aie.next_bd ^bb4 // CHECK: ^bb5: // CHECK: %[[VAL_46:.*]] = aie.dma_start(MM2S, 0, ^bb6, ^bb3) // CHECK: ^bb6: // CHECK: aie.use_lock(%[[VAL_37]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_38]] : memref<16x16xf32, 2>, 0, 256) +// CHECK: aie.dma_bd(%[[VAL_38]] : memref<16x16xf32, 2>) {len = 256 : i32} // CHECK: aie.use_lock(%[[VAL_37]], Release, 0) // CHECK: aie.next_bd ^bb6 // CHECK: ^bb7: @@ -149,26 +149,26 @@ // CHECK: %[[VAL_60:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb5) // CHECK: ^bb1: // CHECK: aie.use_lock(%[[VAL_57]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_58]] : memref<16x16xf32, 2>, 0, 256) +// CHECK: aie.dma_bd(%[[VAL_58]] : memref<16x16xf32, 2>) {len = 256 : i32} // CHECK: aie.use_lock(%[[VAL_57]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // CHECK: aie.use_lock(%[[VAL_52]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_54]] : memref<16x16xf32, 2>, 0, 256) +// CHECK: aie.dma_bd(%[[VAL_54]] : memref<16x16xf32, 2>) {len = 256 : i32} // CHECK: aie.use_lock(%[[VAL_52]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb3: // CHECK: %[[VAL_61:.*]] = aie.dma_start(S2MM, 1, ^bb4, ^bb7) // CHECK: ^bb4: // CHECK: aie.use_lock(%[[VAL_55]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_56]] : memref<16x16xf32, 2>, 0, 256) +// CHECK: aie.dma_bd(%[[VAL_56]] : memref<16x16xf32, 2>) {len = 256 : i32} // CHECK: aie.use_lock(%[[VAL_55]], Release, 1) // CHECK: aie.next_bd ^bb4 // CHECK: ^bb5: // CHECK: %[[VAL_62:.*]] = aie.dma_start(MM2S, 0, ^bb6, ^bb3) // CHECK: ^bb6: // CHECK: aie.use_lock(%[[VAL_53]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_54]] : memref<16x16xf32, 2>, 0, 256) +// CHECK: aie.dma_bd(%[[VAL_54]] : memref<16x16xf32, 2>) {len = 256 : i32} // CHECK: aie.use_lock(%[[VAL_53]], Release, 0) // CHECK: aie.next_bd ^bb6 // CHECK: ^bb7: @@ -441,26 +441,26 @@ module @aie.herd_0 { %0 = aie.dma_start(S2MM, 0, ^bb1, ^bb5) ^bb1: // 2 preds: ^bb0, ^bb2 aie.use_lock(%lock_8_3_3, Acquire, 0) - aie.dma_bd(%buffer_8_3_4 : memref<16x16xf32, 2>, 0, 256) + aie.dma_bd(%buffer_8_3_4 : memref<16x16xf32, 2>) { len = 256 : i32 } aie.use_lock(%lock_8_3_3, Release, 1) aie.next_bd ^bb2 ^bb2: // pred: ^bb1 aie.use_lock(%lock_8_3, Acquire, 0) - aie.dma_bd(%buffer_8_3 : memref<16x16xf32, 2>, 0, 256) + aie.dma_bd(%buffer_8_3 : memref<16x16xf32, 2>) { len = 256 : i32 } aie.use_lock(%lock_8_3, Release, 1) aie.next_bd ^bb1 ^bb3: // pred: ^bb5 %1 = aie.dma_start(S2MM, 1, ^bb4, ^bb7) ^bb4: // 2 preds: ^bb3, ^bb4 aie.use_lock(%lock_8_3_1, Acquire, 0) - aie.dma_bd(%buffer_8_3_2 : memref<16x16xf32, 2>, 0, 256) + aie.dma_bd(%buffer_8_3_2 : memref<16x16xf32, 2>) { len = 256 : i32 } aie.use_lock(%lock_8_3_1, Release, 1) aie.next_bd ^bb4 ^bb5: // pred: ^bb0 %2 = aie.dma_start(MM2S, 0, ^bb6, ^bb3) ^bb6: // 2 preds: ^bb5, ^bb6 aie.use_lock(%lock_8_3_0, Acquire, 1) - aie.dma_bd(%buffer_8_3 : memref<16x16xf32, 2>, 0, 256) + aie.dma_bd(%buffer_8_3 : memref<16x16xf32, 2>) { len = 256 : i32 } aie.use_lock(%lock_8_3_0, Release, 0) aie.next_bd ^bb6 ^bb7: // pred: ^bb3 @@ -482,26 +482,26 @@ module @aie.herd_0 { %0 = aie.dma_start(S2MM, 0, ^bb1, ^bb5) ^bb1: // 2 preds: ^bb0, ^bb2 aie.use_lock(%lock_7_3_8, Acquire, 0) - aie.dma_bd(%buffer_7_3_9 : memref<16x16xf32, 2>, 0, 256) + aie.dma_bd(%buffer_7_3_9 : memref<16x16xf32, 2>) { len = 256 : i32 } aie.use_lock(%lock_7_3_8, Release, 1) aie.next_bd ^bb2 ^bb2: // pred: ^bb1 aie.use_lock(%lock_7_3, Acquire, 0) - aie.dma_bd(%buffer_7_3 : memref<16x16xf32, 2>, 0, 256) + aie.dma_bd(%buffer_7_3 : memref<16x16xf32, 2>) { len = 256 : i32 } aie.use_lock(%lock_7_3, Release, 1) aie.next_bd ^bb1 ^bb3: // pred: ^bb5 %1 = aie.dma_start(S2MM, 1, ^bb4, ^bb7) ^bb4: // 2 preds: ^bb3, ^bb4 aie.use_lock(%lock_7_3_6, Acquire, 0) - aie.dma_bd(%buffer_7_3_7 : memref<16x16xf32, 2>, 0, 256) + aie.dma_bd(%buffer_7_3_7 : memref<16x16xf32, 2>) { len = 256 : i32 } aie.use_lock(%lock_7_3_6, Release, 1) aie.next_bd ^bb4 ^bb5: // pred: ^bb0 %2 = aie.dma_start(MM2S, 0, ^bb6, ^bb3) ^bb6: // 2 preds: ^bb5, ^bb6 aie.use_lock(%lock_7_3_5, Acquire, 1) - aie.dma_bd(%buffer_7_3 : memref<16x16xf32, 2>, 0, 256) + aie.dma_bd(%buffer_7_3 : memref<16x16xf32, 2>) { len = 256 : i32 } aie.use_lock(%lock_7_3_5, Release, 0) aie.next_bd ^bb6 ^bb7: // pred: ^bb3 @@ -523,26 +523,26 @@ module @aie.herd_0 { %0 = aie.dma_start(S2MM, 0, ^bb1, ^bb5) ^bb1: // 2 preds: ^bb0, ^bb2 aie.use_lock(%lock_8_2_13, Acquire, 0) - aie.dma_bd(%buffer_8_2_14 : memref<16x16xf32, 2>, 0, 256) + aie.dma_bd(%buffer_8_2_14 : memref<16x16xf32, 2>) { len = 256 : i32 } aie.use_lock(%lock_8_2_13, Release, 1) aie.next_bd ^bb2 ^bb2: // pred: ^bb1 aie.use_lock(%lock_8_2, Acquire, 0) - aie.dma_bd(%buffer_8_2 : memref<16x16xf32, 2>, 0, 256) + aie.dma_bd(%buffer_8_2 : memref<16x16xf32, 2>) { len = 256 : i32 } aie.use_lock(%lock_8_2, Release, 1) aie.next_bd ^bb1 ^bb3: // pred: ^bb5 %1 = aie.dma_start(S2MM, 1, ^bb4, ^bb7) ^bb4: // 2 preds: ^bb3, ^bb4 aie.use_lock(%lock_8_2_11, Acquire, 0) - aie.dma_bd(%buffer_8_2_12 : memref<16x16xf32, 2>, 0, 256) + aie.dma_bd(%buffer_8_2_12 : memref<16x16xf32, 2>) { len = 256 : i32 } aie.use_lock(%lock_8_2_11, Release, 1) aie.next_bd ^bb4 ^bb5: // pred: ^bb0 %2 = aie.dma_start(MM2S, 0, ^bb6, ^bb3) ^bb6: // 2 preds: ^bb5, ^bb6 aie.use_lock(%lock_8_2_10, Acquire, 1) - aie.dma_bd(%buffer_8_2 : memref<16x16xf32, 2>, 0, 256) + aie.dma_bd(%buffer_8_2 : memref<16x16xf32, 2>) { len = 256 : i32 } aie.use_lock(%lock_8_2_10, Release, 0) aie.next_bd ^bb6 ^bb7: // pred: ^bb3 @@ -564,26 +564,26 @@ module @aie.herd_0 { %0 = aie.dma_start(S2MM, 0, ^bb1, ^bb5) ^bb1: // 2 preds: ^bb0, ^bb2 aie.use_lock(%lock_7_2_18, Acquire, 0) - aie.dma_bd(%buffer_7_2_19 : memref<16x16xf32, 2>, 0, 256) + aie.dma_bd(%buffer_7_2_19 : memref<16x16xf32, 2>) { len = 256 : i32 } aie.use_lock(%lock_7_2_18, Release, 1) aie.next_bd ^bb2 ^bb2: // pred: ^bb1 aie.use_lock(%lock_7_2, Acquire, 0) - aie.dma_bd(%buffer_7_2 : memref<16x16xf32, 2>, 0, 256) + aie.dma_bd(%buffer_7_2 : memref<16x16xf32, 2>) { len = 256 : i32 } aie.use_lock(%lock_7_2, Release, 1) aie.next_bd ^bb1 ^bb3: // pred: ^bb5 %1 = aie.dma_start(S2MM, 1, ^bb4, ^bb7) ^bb4: // 2 preds: ^bb3, ^bb4 aie.use_lock(%lock_7_2_16, Acquire, 0) - aie.dma_bd(%buffer_7_2_17 : memref<16x16xf32, 2>, 0, 256) + aie.dma_bd(%buffer_7_2_17 : memref<16x16xf32, 2>) { len = 256 : i32 } aie.use_lock(%lock_7_2_16, Release, 1) aie.next_bd ^bb4 ^bb5: // pred: ^bb0 %2 = aie.dma_start(MM2S, 0, ^bb6, ^bb3) ^bb6: // 2 preds: ^bb5, ^bb6 aie.use_lock(%lock_7_2_15, Acquire, 1) - aie.dma_bd(%buffer_7_2 : memref<16x16xf32, 2>, 0, 256) + aie.dma_bd(%buffer_7_2 : memref<16x16xf32, 2>) { len = 256 : i32 } aie.use_lock(%lock_7_2_15, Release, 0) aie.next_bd ^bb6 ^bb7: // pred: ^bb3 diff --git a/test/create-flows/unit_vecmul_4x4.mlir b/test/create-flows/unit_vecmul_4x4.mlir index 2aaf794ca1..aea07c42d6 100644 --- a/test/create-flows/unit_vecmul_4x4.mlir +++ b/test/create-flows/unit_vecmul_4x4.mlir @@ -26,21 +26,21 @@ // CHECK: %[[VAL_12:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) // CHECK: ^bb1: // CHECK: aie.use_lock(%[[VAL_9]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_10]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.dma_bd(%[[VAL_10]] : memref<64xi32, 2>) {len = 64 : i32} // CHECK: aie.use_lock(%[[VAL_9]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb2: // CHECK: %[[VAL_13:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) // CHECK: ^bb3: // CHECK: aie.use_lock(%[[VAL_7]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_8]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.dma_bd(%[[VAL_8]] : memref<64xi32, 2>) {len = 64 : i32} // CHECK: aie.use_lock(%[[VAL_7]], Release, 1) // CHECK: aie.next_bd ^bb3 // CHECK: ^bb4: // CHECK: %[[VAL_14:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) // CHECK: ^bb5: // CHECK: aie.use_lock(%[[VAL_5]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_6]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.dma_bd(%[[VAL_6]] : memref<64xi32, 2>) {len = 64 : i32} // CHECK: aie.use_lock(%[[VAL_5]], Release, 0) // CHECK: aie.next_bd ^bb5 // CHECK: ^bb6: @@ -80,21 +80,21 @@ // CHECK: %[[VAL_32:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) // CHECK: ^bb1: // CHECK: aie.use_lock(%[[VAL_29]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_30]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.dma_bd(%[[VAL_30]] : memref<64xi32, 2>) {len = 64 : i32} // CHECK: aie.use_lock(%[[VAL_29]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb2: // CHECK: %[[VAL_33:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) // CHECK: ^bb3: // CHECK: aie.use_lock(%[[VAL_27]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_28]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.dma_bd(%[[VAL_28]] : memref<64xi32, 2>) {len = 64 : i32} // CHECK: aie.use_lock(%[[VAL_27]], Release, 1) // CHECK: aie.next_bd ^bb3 // CHECK: ^bb4: // CHECK: %[[VAL_34:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) // CHECK: ^bb5: // CHECK: aie.use_lock(%[[VAL_25]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_26]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.dma_bd(%[[VAL_26]] : memref<64xi32, 2>) {len = 64 : i32} // CHECK: aie.use_lock(%[[VAL_25]], Release, 0) // CHECK: aie.next_bd ^bb5 // CHECK: ^bb6: @@ -134,21 +134,21 @@ // CHECK: %[[VAL_52:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) // CHECK: ^bb1: // CHECK: aie.use_lock(%[[VAL_49]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_50]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.dma_bd(%[[VAL_50]] : memref<64xi32, 2>) {len = 64 : i32} // CHECK: aie.use_lock(%[[VAL_49]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb2: // CHECK: %[[VAL_53:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) // CHECK: ^bb3: // CHECK: aie.use_lock(%[[VAL_47]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_48]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.dma_bd(%[[VAL_48]] : memref<64xi32, 2>) {len = 64 : i32} // CHECK: aie.use_lock(%[[VAL_47]], Release, 1) // CHECK: aie.next_bd ^bb3 // CHECK: ^bb4: // CHECK: %[[VAL_54:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) // CHECK: ^bb5: // CHECK: aie.use_lock(%[[VAL_45]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_46]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.dma_bd(%[[VAL_46]] : memref<64xi32, 2>) {len = 64 : i32} // CHECK: aie.use_lock(%[[VAL_45]], Release, 0) // CHECK: aie.next_bd ^bb5 // CHECK: ^bb6: @@ -188,21 +188,21 @@ // CHECK: %[[VAL_72:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) // CHECK: ^bb1: // CHECK: aie.use_lock(%[[VAL_69]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_70]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.dma_bd(%[[VAL_70]] : memref<64xi32, 2>) {len = 64 : i32} // CHECK: aie.use_lock(%[[VAL_69]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb2: // CHECK: %[[VAL_73:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) // CHECK: ^bb3: // CHECK: aie.use_lock(%[[VAL_67]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_68]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.dma_bd(%[[VAL_68]] : memref<64xi32, 2>) {len = 64 : i32} // CHECK: aie.use_lock(%[[VAL_67]], Release, 1) // CHECK: aie.next_bd ^bb3 // CHECK: ^bb4: // CHECK: %[[VAL_74:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) // CHECK: ^bb5: // CHECK: aie.use_lock(%[[VAL_65]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_66]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.dma_bd(%[[VAL_66]] : memref<64xi32, 2>) {len = 64 : i32} // CHECK: aie.use_lock(%[[VAL_65]], Release, 0) // CHECK: aie.next_bd ^bb5 // CHECK: ^bb6: @@ -241,21 +241,21 @@ // CHECK: %[[VAL_91:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) // CHECK: ^bb1: // CHECK: aie.use_lock(%[[VAL_88]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_89]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.dma_bd(%[[VAL_89]] : memref<64xi32, 2>) {len = 64 : i32} // CHECK: aie.use_lock(%[[VAL_88]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb2: // CHECK: %[[VAL_92:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) // CHECK: ^bb3: // CHECK: aie.use_lock(%[[VAL_86]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_87]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.dma_bd(%[[VAL_87]] : memref<64xi32, 2>) {len = 64 : i32} // CHECK: aie.use_lock(%[[VAL_86]], Release, 1) // CHECK: aie.next_bd ^bb3 // CHECK: ^bb4: // CHECK: %[[VAL_93:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) // CHECK: ^bb5: // CHECK: aie.use_lock(%[[VAL_84]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_85]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.dma_bd(%[[VAL_85]] : memref<64xi32, 2>) {len = 64 : i32} // CHECK: aie.use_lock(%[[VAL_84]], Release, 0) // CHECK: aie.next_bd ^bb5 // CHECK: ^bb6: @@ -294,21 +294,21 @@ // CHECK: %[[VAL_110:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) // CHECK: ^bb1: // CHECK: aie.use_lock(%[[VAL_107]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_108]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.dma_bd(%[[VAL_108]] : memref<64xi32, 2>) {len = 64 : i32} // CHECK: aie.use_lock(%[[VAL_107]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb2: // CHECK: %[[VAL_111:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) // CHECK: ^bb3: // CHECK: aie.use_lock(%[[VAL_105]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_106]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.dma_bd(%[[VAL_106]] : memref<64xi32, 2>) {len = 64 : i32} // CHECK: aie.use_lock(%[[VAL_105]], Release, 1) // CHECK: aie.next_bd ^bb3 // CHECK: ^bb4: // CHECK: %[[VAL_112:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) // CHECK: ^bb5: // CHECK: aie.use_lock(%[[VAL_103]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_104]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.dma_bd(%[[VAL_104]] : memref<64xi32, 2>) {len = 64 : i32} // CHECK: aie.use_lock(%[[VAL_103]], Release, 0) // CHECK: aie.next_bd ^bb5 // CHECK: ^bb6: @@ -348,21 +348,21 @@ // CHECK: %[[VAL_130:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) // CHECK: ^bb1: // CHECK: aie.use_lock(%[[VAL_127]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_128]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.dma_bd(%[[VAL_128]] : memref<64xi32, 2>) {len = 64 : i32} // CHECK: aie.use_lock(%[[VAL_127]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb2: // CHECK: %[[VAL_131:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) // CHECK: ^bb3: // CHECK: aie.use_lock(%[[VAL_125]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_126]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.dma_bd(%[[VAL_126]] : memref<64xi32, 2>) {len = 64 : i32} // CHECK: aie.use_lock(%[[VAL_125]], Release, 1) // CHECK: aie.next_bd ^bb3 // CHECK: ^bb4: // CHECK: %[[VAL_132:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) // CHECK: ^bb5: // CHECK: aie.use_lock(%[[VAL_123]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_124]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.dma_bd(%[[VAL_124]] : memref<64xi32, 2>) {len = 64 : i32} // CHECK: aie.use_lock(%[[VAL_123]], Release, 0) // CHECK: aie.next_bd ^bb5 // CHECK: ^bb6: @@ -402,21 +402,21 @@ // CHECK: %[[VAL_150:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) // CHECK: ^bb1: // CHECK: aie.use_lock(%[[VAL_147]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_148]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.dma_bd(%[[VAL_148]] : memref<64xi32, 2>) {len = 64 : i32} // CHECK: aie.use_lock(%[[VAL_147]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb2: // CHECK: %[[VAL_151:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) // CHECK: ^bb3: // CHECK: aie.use_lock(%[[VAL_145]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_146]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.dma_bd(%[[VAL_146]] : memref<64xi32, 2>) {len = 64 : i32} // CHECK: aie.use_lock(%[[VAL_145]], Release, 1) // CHECK: aie.next_bd ^bb3 // CHECK: ^bb4: // CHECK: %[[VAL_152:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) // CHECK: ^bb5: // CHECK: aie.use_lock(%[[VAL_143]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_144]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.dma_bd(%[[VAL_144]] : memref<64xi32, 2>) {len = 64 : i32} // CHECK: aie.use_lock(%[[VAL_143]], Release, 0) // CHECK: aie.next_bd ^bb5 // CHECK: ^bb6: @@ -455,21 +455,21 @@ // CHECK: %[[VAL_169:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) // CHECK: ^bb1: // CHECK: aie.use_lock(%[[VAL_166]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_167]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.dma_bd(%[[VAL_167]] : memref<64xi32, 2>) {len = 64 : i32} // CHECK: aie.use_lock(%[[VAL_166]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb2: // CHECK: %[[VAL_170:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) // CHECK: ^bb3: // CHECK: aie.use_lock(%[[VAL_164]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_165]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.dma_bd(%[[VAL_165]] : memref<64xi32, 2>) {len = 64 : i32} // CHECK: aie.use_lock(%[[VAL_164]], Release, 1) // CHECK: aie.next_bd ^bb3 // CHECK: ^bb4: // CHECK: %[[VAL_171:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) // CHECK: ^bb5: // CHECK: aie.use_lock(%[[VAL_162]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_163]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.dma_bd(%[[VAL_163]] : memref<64xi32, 2>) {len = 64 : i32} // CHECK: aie.use_lock(%[[VAL_162]], Release, 0) // CHECK: aie.next_bd ^bb5 // CHECK: ^bb6: @@ -508,21 +508,21 @@ // CHECK: %[[VAL_188:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) // CHECK: ^bb1: // CHECK: aie.use_lock(%[[VAL_185]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_186]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.dma_bd(%[[VAL_186]] : memref<64xi32, 2>) {len = 64 : i32} // CHECK: aie.use_lock(%[[VAL_185]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb2: // CHECK: %[[VAL_189:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) // CHECK: ^bb3: // CHECK: aie.use_lock(%[[VAL_183]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_184]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.dma_bd(%[[VAL_184]] : memref<64xi32, 2>) {len = 64 : i32} // CHECK: aie.use_lock(%[[VAL_183]], Release, 1) // CHECK: aie.next_bd ^bb3 // CHECK: ^bb4: // CHECK: %[[VAL_190:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) // CHECK: ^bb5: // CHECK: aie.use_lock(%[[VAL_181]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_182]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.dma_bd(%[[VAL_182]] : memref<64xi32, 2>) {len = 64 : i32} // CHECK: aie.use_lock(%[[VAL_181]], Release, 0) // CHECK: aie.next_bd ^bb5 // CHECK: ^bb6: @@ -562,21 +562,21 @@ // CHECK: %[[VAL_208:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) // CHECK: ^bb1: // CHECK: aie.use_lock(%[[VAL_205]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_206]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.dma_bd(%[[VAL_206]] : memref<64xi32, 2>) {len = 64 : i32} // CHECK: aie.use_lock(%[[VAL_205]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb2: // CHECK: %[[VAL_209:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) // CHECK: ^bb3: // CHECK: aie.use_lock(%[[VAL_203]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_204]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.dma_bd(%[[VAL_204]] : memref<64xi32, 2>) {len = 64 : i32} // CHECK: aie.use_lock(%[[VAL_203]], Release, 1) // CHECK: aie.next_bd ^bb3 // CHECK: ^bb4: // CHECK: %[[VAL_210:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) // CHECK: ^bb5: // CHECK: aie.use_lock(%[[VAL_201]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_202]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.dma_bd(%[[VAL_202]] : memref<64xi32, 2>) {len = 64 : i32} // CHECK: aie.use_lock(%[[VAL_201]], Release, 0) // CHECK: aie.next_bd ^bb5 // CHECK: ^bb6: @@ -615,21 +615,21 @@ // CHECK: %[[VAL_227:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) // CHECK: ^bb1: // CHECK: aie.use_lock(%[[VAL_224]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_225]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.dma_bd(%[[VAL_225]] : memref<64xi32, 2>) {len = 64 : i32} // CHECK: aie.use_lock(%[[VAL_224]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb2: // CHECK: %[[VAL_228:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) // CHECK: ^bb3: // CHECK: aie.use_lock(%[[VAL_222]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_223]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.dma_bd(%[[VAL_223]] : memref<64xi32, 2>) {len = 64 : i32} // CHECK: aie.use_lock(%[[VAL_222]], Release, 1) // CHECK: aie.next_bd ^bb3 // CHECK: ^bb4: // CHECK: %[[VAL_229:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) // CHECK: ^bb5: // CHECK: aie.use_lock(%[[VAL_220]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_221]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.dma_bd(%[[VAL_221]] : memref<64xi32, 2>) {len = 64 : i32} // CHECK: aie.use_lock(%[[VAL_220]], Release, 0) // CHECK: aie.next_bd ^bb5 // CHECK: ^bb6: @@ -667,21 +667,21 @@ // CHECK: %[[VAL_245:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) // CHECK: ^bb1: // CHECK: aie.use_lock(%[[VAL_242]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_243]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.dma_bd(%[[VAL_243]] : memref<64xi32, 2>) {len = 64 : i32} // CHECK: aie.use_lock(%[[VAL_242]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb2: // CHECK: %[[VAL_246:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) // CHECK: ^bb3: // CHECK: aie.use_lock(%[[VAL_240]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_241]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.dma_bd(%[[VAL_241]] : memref<64xi32, 2>) {len = 64 : i32} // CHECK: aie.use_lock(%[[VAL_240]], Release, 1) // CHECK: aie.next_bd ^bb3 // CHECK: ^bb4: // CHECK: %[[VAL_247:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) // CHECK: ^bb5: // CHECK: aie.use_lock(%[[VAL_238]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_239]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.dma_bd(%[[VAL_239]] : memref<64xi32, 2>) {len = 64 : i32} // CHECK: aie.use_lock(%[[VAL_238]], Release, 0) // CHECK: aie.next_bd ^bb5 // CHECK: ^bb6: @@ -720,21 +720,21 @@ // CHECK: %[[VAL_264:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) // CHECK: ^bb1: // CHECK: aie.use_lock(%[[VAL_261]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_262]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.dma_bd(%[[VAL_262]] : memref<64xi32, 2>) {len = 64 : i32} // CHECK: aie.use_lock(%[[VAL_261]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb2: // CHECK: %[[VAL_265:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) // CHECK: ^bb3: // CHECK: aie.use_lock(%[[VAL_259]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_260]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.dma_bd(%[[VAL_260]] : memref<64xi32, 2>) {len = 64 : i32} // CHECK: aie.use_lock(%[[VAL_259]], Release, 1) // CHECK: aie.next_bd ^bb3 // CHECK: ^bb4: // CHECK: %[[VAL_266:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) // CHECK: ^bb5: // CHECK: aie.use_lock(%[[VAL_257]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_258]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.dma_bd(%[[VAL_258]] : memref<64xi32, 2>) {len = 64 : i32} // CHECK: aie.use_lock(%[[VAL_257]], Release, 0) // CHECK: aie.next_bd ^bb5 // CHECK: ^bb6: @@ -774,21 +774,21 @@ // CHECK: %[[VAL_284:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) // CHECK: ^bb1: // CHECK: aie.use_lock(%[[VAL_281]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_282]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.dma_bd(%[[VAL_282]] : memref<64xi32, 2>) {len = 64 : i32} // CHECK: aie.use_lock(%[[VAL_281]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb2: // CHECK: %[[VAL_285:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) // CHECK: ^bb3: // CHECK: aie.use_lock(%[[VAL_279]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_280]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.dma_bd(%[[VAL_280]] : memref<64xi32, 2>) {len = 64 : i32} // CHECK: aie.use_lock(%[[VAL_279]], Release, 1) // CHECK: aie.next_bd ^bb3 // CHECK: ^bb4: // CHECK: %[[VAL_286:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) // CHECK: ^bb5: // CHECK: aie.use_lock(%[[VAL_277]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_278]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.dma_bd(%[[VAL_278]] : memref<64xi32, 2>) {len = 64 : i32} // CHECK: aie.use_lock(%[[VAL_277]], Release, 0) // CHECK: aie.next_bd ^bb5 // CHECK: ^bb6: @@ -828,21 +828,21 @@ // CHECK: %[[VAL_304:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) // CHECK: ^bb1: // CHECK: aie.use_lock(%[[VAL_301]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_302]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.dma_bd(%[[VAL_302]] : memref<64xi32, 2>) {len = 64 : i32} // CHECK: aie.use_lock(%[[VAL_301]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb2: // CHECK: %[[VAL_305:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) // CHECK: ^bb3: // CHECK: aie.use_lock(%[[VAL_299]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_300]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.dma_bd(%[[VAL_300]] : memref<64xi32, 2>) {len = 64 : i32} // CHECK: aie.use_lock(%[[VAL_299]], Release, 1) // CHECK: aie.next_bd ^bb3 // CHECK: ^bb4: // CHECK: %[[VAL_306:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) // CHECK: ^bb5: // CHECK: aie.use_lock(%[[VAL_297]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_298]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.dma_bd(%[[VAL_298]] : memref<64xi32, 2>) {len = 64 : i32} // CHECK: aie.use_lock(%[[VAL_297]], Release, 0) // CHECK: aie.next_bd ^bb5 // CHECK: ^bb6: @@ -2971,21 +2971,21 @@ module @vecmul_4x4 { %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) ^bb1: // 2 preds: ^bb0, ^bb1 aie.use_lock(%9, Acquire, 0) - aie.dma_bd(%10 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%10 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%9, Release, 1) aie.next_bd ^bb1 ^bb2: // pred: ^bb4 %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) ^bb3: // 2 preds: ^bb2, ^bb3 aie.use_lock(%7, Acquire, 0) - aie.dma_bd(%8 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%8 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%7, Release, 1) aie.next_bd ^bb3 ^bb4: // pred: ^bb0 %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) ^bb5: // 2 preds: ^bb4, ^bb5 aie.use_lock(%5, Acquire, 1) - aie.dma_bd(%6 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%6 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%5, Release, 0) aie.next_bd ^bb5 ^bb6: // pred: ^bb2 @@ -3025,21 +3025,21 @@ module @vecmul_4x4 { %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) ^bb1: // 2 preds: ^bb0, ^bb1 aie.use_lock(%22, Acquire, 0) - aie.dma_bd(%23 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%23 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%22, Release, 1) aie.next_bd ^bb1 ^bb2: // pred: ^bb4 %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) ^bb3: // 2 preds: ^bb2, ^bb3 aie.use_lock(%20, Acquire, 0) - aie.dma_bd(%21 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%21 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%20, Release, 1) aie.next_bd ^bb3 ^bb4: // pred: ^bb0 %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) ^bb5: // 2 preds: ^bb4, ^bb5 aie.use_lock(%18, Acquire, 1) - aie.dma_bd(%19 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%19 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%18, Release, 0) aie.next_bd ^bb5 ^bb6: // pred: ^bb2 @@ -3079,21 +3079,21 @@ module @vecmul_4x4 { %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) ^bb1: // 2 preds: ^bb0, ^bb1 aie.use_lock(%35, Acquire, 0) - aie.dma_bd(%36 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%36 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%35, Release, 1) aie.next_bd ^bb1 ^bb2: // pred: ^bb4 %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) ^bb3: // 2 preds: ^bb2, ^bb3 aie.use_lock(%33, Acquire, 0) - aie.dma_bd(%34 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%34 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%33, Release, 1) aie.next_bd ^bb3 ^bb4: // pred: ^bb0 %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) ^bb5: // 2 preds: ^bb4, ^bb5 aie.use_lock(%31, Acquire, 1) - aie.dma_bd(%32 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%32 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%31, Release, 0) aie.next_bd ^bb5 ^bb6: // pred: ^bb2 @@ -3133,21 +3133,21 @@ module @vecmul_4x4 { %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) ^bb1: // 2 preds: ^bb0, ^bb1 aie.use_lock(%48, Acquire, 0) - aie.dma_bd(%49 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%49 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%48, Release, 1) aie.next_bd ^bb1 ^bb2: // pred: ^bb4 %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) ^bb3: // 2 preds: ^bb2, ^bb3 aie.use_lock(%46, Acquire, 0) - aie.dma_bd(%47 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%47 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%46, Release, 1) aie.next_bd ^bb3 ^bb4: // pred: ^bb0 %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) ^bb5: // 2 preds: ^bb4, ^bb5 aie.use_lock(%44, Acquire, 1) - aie.dma_bd(%45 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%45 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%44, Release, 0) aie.next_bd ^bb5 ^bb6: // pred: ^bb2 @@ -3186,21 +3186,21 @@ module @vecmul_4x4 { %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) ^bb1: // 2 preds: ^bb0, ^bb1 aie.use_lock(%60, Acquire, 0) - aie.dma_bd(%61 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%61 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%60, Release, 1) aie.next_bd ^bb1 ^bb2: // pred: ^bb4 %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) ^bb3: // 2 preds: ^bb2, ^bb3 aie.use_lock(%58, Acquire, 0) - aie.dma_bd(%59 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%59 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%58, Release, 1) aie.next_bd ^bb3 ^bb4: // pred: ^bb0 %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) ^bb5: // 2 preds: ^bb4, ^bb5 aie.use_lock(%56, Acquire, 1) - aie.dma_bd(%57 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%57 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%56, Release, 0) aie.next_bd ^bb5 ^bb6: // pred: ^bb2 @@ -3239,21 +3239,21 @@ module @vecmul_4x4 { %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) ^bb1: // 2 preds: ^bb0, ^bb1 aie.use_lock(%72, Acquire, 0) - aie.dma_bd(%73 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%73 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%72, Release, 1) aie.next_bd ^bb1 ^bb2: // pred: ^bb4 %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) ^bb3: // 2 preds: ^bb2, ^bb3 aie.use_lock(%70, Acquire, 0) - aie.dma_bd(%71 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%71 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%70, Release, 1) aie.next_bd ^bb3 ^bb4: // pred: ^bb0 %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) ^bb5: // 2 preds: ^bb4, ^bb5 aie.use_lock(%68, Acquire, 1) - aie.dma_bd(%69 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%69 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%68, Release, 0) aie.next_bd ^bb5 ^bb6: // pred: ^bb2 @@ -3293,21 +3293,21 @@ module @vecmul_4x4 { %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) ^bb1: // 2 preds: ^bb0, ^bb1 aie.use_lock(%85, Acquire, 0) - aie.dma_bd(%86 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%86 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%85, Release, 1) aie.next_bd ^bb1 ^bb2: // pred: ^bb4 %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) ^bb3: // 2 preds: ^bb2, ^bb3 aie.use_lock(%83, Acquire, 0) - aie.dma_bd(%84 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%84 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%83, Release, 1) aie.next_bd ^bb3 ^bb4: // pred: ^bb0 %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) ^bb5: // 2 preds: ^bb4, ^bb5 aie.use_lock(%81, Acquire, 1) - aie.dma_bd(%82 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%82 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%81, Release, 0) aie.next_bd ^bb5 ^bb6: // pred: ^bb2 @@ -3347,21 +3347,21 @@ module @vecmul_4x4 { %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) ^bb1: // 2 preds: ^bb0, ^bb1 aie.use_lock(%98, Acquire, 0) - aie.dma_bd(%99 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%99 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%98, Release, 1) aie.next_bd ^bb1 ^bb2: // pred: ^bb4 %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) ^bb3: // 2 preds: ^bb2, ^bb3 aie.use_lock(%96, Acquire, 0) - aie.dma_bd(%97 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%97 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%96, Release, 1) aie.next_bd ^bb3 ^bb4: // pred: ^bb0 %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) ^bb5: // 2 preds: ^bb4, ^bb5 aie.use_lock(%94, Acquire, 1) - aie.dma_bd(%95 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%95 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%94, Release, 0) aie.next_bd ^bb5 ^bb6: // pred: ^bb2 @@ -3400,21 +3400,21 @@ module @vecmul_4x4 { %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) ^bb1: // 2 preds: ^bb0, ^bb1 aie.use_lock(%110, Acquire, 0) - aie.dma_bd(%111 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%111 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%110, Release, 1) aie.next_bd ^bb1 ^bb2: // pred: ^bb4 %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) ^bb3: // 2 preds: ^bb2, ^bb3 aie.use_lock(%108, Acquire, 0) - aie.dma_bd(%109 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%109 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%108, Release, 1) aie.next_bd ^bb3 ^bb4: // pred: ^bb0 %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) ^bb5: // 2 preds: ^bb4, ^bb5 aie.use_lock(%106, Acquire, 1) - aie.dma_bd(%107 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%107 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%106, Release, 0) aie.next_bd ^bb5 ^bb6: // pred: ^bb2 @@ -3453,21 +3453,21 @@ module @vecmul_4x4 { %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) ^bb1: // 2 preds: ^bb0, ^bb1 aie.use_lock(%122, Acquire, 0) - aie.dma_bd(%123 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%123 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%122, Release, 1) aie.next_bd ^bb1 ^bb2: // pred: ^bb4 %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) ^bb3: // 2 preds: ^bb2, ^bb3 aie.use_lock(%120, Acquire, 0) - aie.dma_bd(%121 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%121 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%120, Release, 1) aie.next_bd ^bb3 ^bb4: // pred: ^bb0 %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) ^bb5: // 2 preds: ^bb4, ^bb5 aie.use_lock(%118, Acquire, 1) - aie.dma_bd(%119 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%119 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%118, Release, 0) aie.next_bd ^bb5 ^bb6: // pred: ^bb2 @@ -3507,21 +3507,21 @@ module @vecmul_4x4 { %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) ^bb1: // 2 preds: ^bb0, ^bb1 aie.use_lock(%135, Acquire, 0) - aie.dma_bd(%136 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%136 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%135, Release, 1) aie.next_bd ^bb1 ^bb2: // pred: ^bb4 %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) ^bb3: // 2 preds: ^bb2, ^bb3 aie.use_lock(%133, Acquire, 0) - aie.dma_bd(%134 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%134 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%133, Release, 1) aie.next_bd ^bb3 ^bb4: // pred: ^bb0 %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) ^bb5: // 2 preds: ^bb4, ^bb5 aie.use_lock(%131, Acquire, 1) - aie.dma_bd(%132 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%132 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%131, Release, 0) aie.next_bd ^bb5 ^bb6: // pred: ^bb2 @@ -3560,21 +3560,21 @@ module @vecmul_4x4 { %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) ^bb1: // 2 preds: ^bb0, ^bb1 aie.use_lock(%147, Acquire, 0) - aie.dma_bd(%148 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%148 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%147, Release, 1) aie.next_bd ^bb1 ^bb2: // pred: ^bb4 %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) ^bb3: // 2 preds: ^bb2, ^bb3 aie.use_lock(%145, Acquire, 0) - aie.dma_bd(%146 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%146 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%145, Release, 1) aie.next_bd ^bb3 ^bb4: // pred: ^bb0 %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) ^bb5: // 2 preds: ^bb4, ^bb5 aie.use_lock(%143, Acquire, 1) - aie.dma_bd(%144 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%144 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%143, Release, 0) aie.next_bd ^bb5 ^bb6: // pred: ^bb2 @@ -3612,21 +3612,21 @@ module @vecmul_4x4 { %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) ^bb1: // 2 preds: ^bb0, ^bb1 aie.use_lock(%158, Acquire, 0) - aie.dma_bd(%159 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%159 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%158, Release, 1) aie.next_bd ^bb1 ^bb2: // pred: ^bb4 %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) ^bb3: // 2 preds: ^bb2, ^bb3 aie.use_lock(%156, Acquire, 0) - aie.dma_bd(%157 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%157 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%156, Release, 1) aie.next_bd ^bb3 ^bb4: // pred: ^bb0 %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) ^bb5: // 2 preds: ^bb4, ^bb5 aie.use_lock(%154, Acquire, 1) - aie.dma_bd(%155 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%155 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%154, Release, 0) aie.next_bd ^bb5 ^bb6: // pred: ^bb2 @@ -3665,21 +3665,21 @@ module @vecmul_4x4 { %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) ^bb1: // 2 preds: ^bb0, ^bb1 aie.use_lock(%170, Acquire, 0) - aie.dma_bd(%171 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%171 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%170, Release, 1) aie.next_bd ^bb1 ^bb2: // pred: ^bb4 %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) ^bb3: // 2 preds: ^bb2, ^bb3 aie.use_lock(%168, Acquire, 0) - aie.dma_bd(%169 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%169 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%168, Release, 1) aie.next_bd ^bb3 ^bb4: // pred: ^bb0 %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) ^bb5: // 2 preds: ^bb4, ^bb5 aie.use_lock(%166, Acquire, 1) - aie.dma_bd(%167 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%167 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%166, Release, 0) aie.next_bd ^bb5 ^bb6: // pred: ^bb2 @@ -3719,21 +3719,21 @@ module @vecmul_4x4 { %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) ^bb1: // 2 preds: ^bb0, ^bb1 aie.use_lock(%183, Acquire, 0) - aie.dma_bd(%184 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%184 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%183, Release, 1) aie.next_bd ^bb1 ^bb2: // pred: ^bb4 %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) ^bb3: // 2 preds: ^bb2, ^bb3 aie.use_lock(%181, Acquire, 0) - aie.dma_bd(%182 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%182 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%181, Release, 1) aie.next_bd ^bb3 ^bb4: // pred: ^bb0 %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) ^bb5: // 2 preds: ^bb4, ^bb5 aie.use_lock(%179, Acquire, 1) - aie.dma_bd(%180 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%180 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%179, Release, 0) aie.next_bd ^bb5 ^bb6: // pred: ^bb2 @@ -3773,21 +3773,21 @@ module @vecmul_4x4 { %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) ^bb1: // 2 preds: ^bb0, ^bb1 aie.use_lock(%196, Acquire, 0) - aie.dma_bd(%197 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%197 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%196, Release, 1) aie.next_bd ^bb1 ^bb2: // pred: ^bb4 %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) ^bb3: // 2 preds: ^bb2, ^bb3 aie.use_lock(%194, Acquire, 0) - aie.dma_bd(%195 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%195 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%194, Release, 1) aie.next_bd ^bb3 ^bb4: // pred: ^bb0 %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) ^bb5: // 2 preds: ^bb4, ^bb5 aie.use_lock(%192, Acquire, 1) - aie.dma_bd(%193 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%193 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%192, Release, 0) aie.next_bd ^bb5 ^bb6: // pred: ^bb2 diff --git a/test/create-flows/vecmul_4x4.mlir b/test/create-flows/vecmul_4x4.mlir index 17f07ae91c..736f06a094 100644 --- a/test/create-flows/vecmul_4x4.mlir +++ b/test/create-flows/vecmul_4x4.mlir @@ -109,21 +109,21 @@ module @vecmul_4x4 { %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) ^bb1: // 2 preds: ^bb0, ^bb1 aie.use_lock(%9, Acquire, 0) - aie.dma_bd(%10 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%10 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%9, Release, 1) aie.next_bd ^bb1 ^bb2: // pred: ^bb4 %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) ^bb3: // 2 preds: ^bb2, ^bb3 aie.use_lock(%7, Acquire, 0) - aie.dma_bd(%8 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%8 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%7, Release, 1) aie.next_bd ^bb3 ^bb4: // pred: ^bb0 %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) ^bb5: // 2 preds: ^bb4, ^bb5 aie.use_lock(%5, Acquire, 1) - aie.dma_bd(%6 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%6 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%5, Release, 0) aie.next_bd ^bb5 ^bb6: // pred: ^bb2 @@ -163,21 +163,21 @@ module @vecmul_4x4 { %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) ^bb1: // 2 preds: ^bb0, ^bb1 aie.use_lock(%22, Acquire, 0) - aie.dma_bd(%23 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%23 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%22, Release, 1) aie.next_bd ^bb1 ^bb2: // pred: ^bb4 %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) ^bb3: // 2 preds: ^bb2, ^bb3 aie.use_lock(%20, Acquire, 0) - aie.dma_bd(%21 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%21 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%20, Release, 1) aie.next_bd ^bb3 ^bb4: // pred: ^bb0 %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) ^bb5: // 2 preds: ^bb4, ^bb5 aie.use_lock(%18, Acquire, 1) - aie.dma_bd(%19 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%19 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%18, Release, 0) aie.next_bd ^bb5 ^bb6: // pred: ^bb2 @@ -217,21 +217,21 @@ module @vecmul_4x4 { %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) ^bb1: // 2 preds: ^bb0, ^bb1 aie.use_lock(%35, Acquire, 0) - aie.dma_bd(%36 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%36 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%35, Release, 1) aie.next_bd ^bb1 ^bb2: // pred: ^bb4 %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) ^bb3: // 2 preds: ^bb2, ^bb3 aie.use_lock(%33, Acquire, 0) - aie.dma_bd(%34 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%34 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%33, Release, 1) aie.next_bd ^bb3 ^bb4: // pred: ^bb0 %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) ^bb5: // 2 preds: ^bb4, ^bb5 aie.use_lock(%31, Acquire, 1) - aie.dma_bd(%32 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%32 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%31, Release, 0) aie.next_bd ^bb5 ^bb6: // pred: ^bb2 @@ -271,21 +271,21 @@ module @vecmul_4x4 { %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) ^bb1: // 2 preds: ^bb0, ^bb1 aie.use_lock(%48, Acquire, 0) - aie.dma_bd(%49 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%49 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%48, Release, 1) aie.next_bd ^bb1 ^bb2: // pred: ^bb4 %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) ^bb3: // 2 preds: ^bb2, ^bb3 aie.use_lock(%46, Acquire, 0) - aie.dma_bd(%47 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%47 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%46, Release, 1) aie.next_bd ^bb3 ^bb4: // pred: ^bb0 %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) ^bb5: // 2 preds: ^bb4, ^bb5 aie.use_lock(%44, Acquire, 1) - aie.dma_bd(%45 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%45 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%44, Release, 0) aie.next_bd ^bb5 ^bb6: // pred: ^bb2 @@ -324,21 +324,21 @@ module @vecmul_4x4 { %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) ^bb1: // 2 preds: ^bb0, ^bb1 aie.use_lock(%60, Acquire, 0) - aie.dma_bd(%61 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%61 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%60, Release, 1) aie.next_bd ^bb1 ^bb2: // pred: ^bb4 %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) ^bb3: // 2 preds: ^bb2, ^bb3 aie.use_lock(%58, Acquire, 0) - aie.dma_bd(%59 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%59 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%58, Release, 1) aie.next_bd ^bb3 ^bb4: // pred: ^bb0 %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) ^bb5: // 2 preds: ^bb4, ^bb5 aie.use_lock(%56, Acquire, 1) - aie.dma_bd(%57 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%57 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%56, Release, 0) aie.next_bd ^bb5 ^bb6: // pred: ^bb2 @@ -377,21 +377,21 @@ module @vecmul_4x4 { %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) ^bb1: // 2 preds: ^bb0, ^bb1 aie.use_lock(%72, Acquire, 0) - aie.dma_bd(%73 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%73 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%72, Release, 1) aie.next_bd ^bb1 ^bb2: // pred: ^bb4 %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) ^bb3: // 2 preds: ^bb2, ^bb3 aie.use_lock(%70, Acquire, 0) - aie.dma_bd(%71 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%71 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%70, Release, 1) aie.next_bd ^bb3 ^bb4: // pred: ^bb0 %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) ^bb5: // 2 preds: ^bb4, ^bb5 aie.use_lock(%68, Acquire, 1) - aie.dma_bd(%69 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%69 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%68, Release, 0) aie.next_bd ^bb5 ^bb6: // pred: ^bb2 @@ -431,21 +431,21 @@ module @vecmul_4x4 { %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) ^bb1: // 2 preds: ^bb0, ^bb1 aie.use_lock(%85, Acquire, 0) - aie.dma_bd(%86 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%86 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%85, Release, 1) aie.next_bd ^bb1 ^bb2: // pred: ^bb4 %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) ^bb3: // 2 preds: ^bb2, ^bb3 aie.use_lock(%83, Acquire, 0) - aie.dma_bd(%84 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%84 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%83, Release, 1) aie.next_bd ^bb3 ^bb4: // pred: ^bb0 %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) ^bb5: // 2 preds: ^bb4, ^bb5 aie.use_lock(%81, Acquire, 1) - aie.dma_bd(%82 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%82 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%81, Release, 0) aie.next_bd ^bb5 ^bb6: // pred: ^bb2 @@ -485,21 +485,21 @@ module @vecmul_4x4 { %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) ^bb1: // 2 preds: ^bb0, ^bb1 aie.use_lock(%98, Acquire, 0) - aie.dma_bd(%99 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%99 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%98, Release, 1) aie.next_bd ^bb1 ^bb2: // pred: ^bb4 %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) ^bb3: // 2 preds: ^bb2, ^bb3 aie.use_lock(%96, Acquire, 0) - aie.dma_bd(%97 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%97 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%96, Release, 1) aie.next_bd ^bb3 ^bb4: // pred: ^bb0 %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) ^bb5: // 2 preds: ^bb4, ^bb5 aie.use_lock(%94, Acquire, 1) - aie.dma_bd(%95 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%95 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%94, Release, 0) aie.next_bd ^bb5 ^bb6: // pred: ^bb2 @@ -538,21 +538,21 @@ module @vecmul_4x4 { %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) ^bb1: // 2 preds: ^bb0, ^bb1 aie.use_lock(%110, Acquire, 0) - aie.dma_bd(%111 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%111 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%110, Release, 1) aie.next_bd ^bb1 ^bb2: // pred: ^bb4 %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) ^bb3: // 2 preds: ^bb2, ^bb3 aie.use_lock(%108, Acquire, 0) - aie.dma_bd(%109 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%109 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%108, Release, 1) aie.next_bd ^bb3 ^bb4: // pred: ^bb0 %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) ^bb5: // 2 preds: ^bb4, ^bb5 aie.use_lock(%106, Acquire, 1) - aie.dma_bd(%107 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%107 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%106, Release, 0) aie.next_bd ^bb5 ^bb6: // pred: ^bb2 @@ -591,21 +591,21 @@ module @vecmul_4x4 { %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) ^bb1: // 2 preds: ^bb0, ^bb1 aie.use_lock(%122, Acquire, 0) - aie.dma_bd(%123 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%123 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%122, Release, 1) aie.next_bd ^bb1 ^bb2: // pred: ^bb4 %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) ^bb3: // 2 preds: ^bb2, ^bb3 aie.use_lock(%120, Acquire, 0) - aie.dma_bd(%121 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%121 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%120, Release, 1) aie.next_bd ^bb3 ^bb4: // pred: ^bb0 %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) ^bb5: // 2 preds: ^bb4, ^bb5 aie.use_lock(%118, Acquire, 1) - aie.dma_bd(%119 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%119 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%118, Release, 0) aie.next_bd ^bb5 ^bb6: // pred: ^bb2 @@ -645,21 +645,21 @@ module @vecmul_4x4 { %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) ^bb1: // 2 preds: ^bb0, ^bb1 aie.use_lock(%135, Acquire, 0) - aie.dma_bd(%136 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%136 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%135, Release, 1) aie.next_bd ^bb1 ^bb2: // pred: ^bb4 %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) ^bb3: // 2 preds: ^bb2, ^bb3 aie.use_lock(%133, Acquire, 0) - aie.dma_bd(%134 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%134 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%133, Release, 1) aie.next_bd ^bb3 ^bb4: // pred: ^bb0 %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) ^bb5: // 2 preds: ^bb4, ^bb5 aie.use_lock(%131, Acquire, 1) - aie.dma_bd(%132 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%132 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%131, Release, 0) aie.next_bd ^bb5 ^bb6: // pred: ^bb2 @@ -698,21 +698,21 @@ module @vecmul_4x4 { %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) ^bb1: // 2 preds: ^bb0, ^bb1 aie.use_lock(%147, Acquire, 0) - aie.dma_bd(%148 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%148 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%147, Release, 1) aie.next_bd ^bb1 ^bb2: // pred: ^bb4 %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) ^bb3: // 2 preds: ^bb2, ^bb3 aie.use_lock(%145, Acquire, 0) - aie.dma_bd(%146 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%146 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%145, Release, 1) aie.next_bd ^bb3 ^bb4: // pred: ^bb0 %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) ^bb5: // 2 preds: ^bb4, ^bb5 aie.use_lock(%143, Acquire, 1) - aie.dma_bd(%144 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%144 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%143, Release, 0) aie.next_bd ^bb5 ^bb6: // pred: ^bb2 @@ -750,21 +750,21 @@ module @vecmul_4x4 { %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) ^bb1: // 2 preds: ^bb0, ^bb1 aie.use_lock(%158, Acquire, 0) - aie.dma_bd(%159 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%159 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%158, Release, 1) aie.next_bd ^bb1 ^bb2: // pred: ^bb4 %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) ^bb3: // 2 preds: ^bb2, ^bb3 aie.use_lock(%156, Acquire, 0) - aie.dma_bd(%157 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%157 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%156, Release, 1) aie.next_bd ^bb3 ^bb4: // pred: ^bb0 %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) ^bb5: // 2 preds: ^bb4, ^bb5 aie.use_lock(%154, Acquire, 1) - aie.dma_bd(%155 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%155 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%154, Release, 0) aie.next_bd ^bb5 ^bb6: // pred: ^bb2 @@ -803,21 +803,21 @@ module @vecmul_4x4 { %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) ^bb1: // 2 preds: ^bb0, ^bb1 aie.use_lock(%170, Acquire, 0) - aie.dma_bd(%171 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%171 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%170, Release, 1) aie.next_bd ^bb1 ^bb2: // pred: ^bb4 %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) ^bb3: // 2 preds: ^bb2, ^bb3 aie.use_lock(%168, Acquire, 0) - aie.dma_bd(%169 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%169 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%168, Release, 1) aie.next_bd ^bb3 ^bb4: // pred: ^bb0 %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) ^bb5: // 2 preds: ^bb4, ^bb5 aie.use_lock(%166, Acquire, 1) - aie.dma_bd(%167 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%167 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%166, Release, 0) aie.next_bd ^bb5 ^bb6: // pred: ^bb2 @@ -857,21 +857,21 @@ module @vecmul_4x4 { %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) ^bb1: // 2 preds: ^bb0, ^bb1 aie.use_lock(%183, Acquire, 0) - aie.dma_bd(%184 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%184 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%183, Release, 1) aie.next_bd ^bb1 ^bb2: // pred: ^bb4 %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) ^bb3: // 2 preds: ^bb2, ^bb3 aie.use_lock(%181, Acquire, 0) - aie.dma_bd(%182 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%182 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%181, Release, 1) aie.next_bd ^bb3 ^bb4: // pred: ^bb0 %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) ^bb5: // 2 preds: ^bb4, ^bb5 aie.use_lock(%179, Acquire, 1) - aie.dma_bd(%180 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%180 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%179, Release, 0) aie.next_bd ^bb5 ^bb6: // pred: ^bb2 @@ -911,21 +911,21 @@ module @vecmul_4x4 { %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) ^bb1: // 2 preds: ^bb0, ^bb1 aie.use_lock(%196, Acquire, 0) - aie.dma_bd(%197 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%197 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%196, Release, 1) aie.next_bd ^bb1 ^bb2: // pred: ^bb4 %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) ^bb3: // 2 preds: ^bb2, ^bb3 aie.use_lock(%194, Acquire, 0) - aie.dma_bd(%195 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%195 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%194, Release, 1) aie.next_bd ^bb3 ^bb4: // pred: ^bb0 %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) ^bb5: // 2 preds: ^bb4, ^bb5 aie.use_lock(%192, Acquire, 1) - aie.dma_bd(%193 : memref<64xi32, 2>, 0, 64) + aie.dma_bd(%193 : memref<64xi32, 2>) { len = 64 : i32 } aie.use_lock(%192, Release, 0) aie.next_bd ^bb5 ^bb6: // pred: ^bb2 diff --git a/test/create-locks/test_lock3.mlir b/test/create-locks/test_lock3.mlir index dc71cfc807..edfbc4f547 100644 --- a/test/create-locks/test_lock3.mlir +++ b/test/create-locks/test_lock3.mlir @@ -22,7 +22,7 @@ // CHECK: %[[VAL_7:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb2) // CHECK: ^bb1: // CHECK: aie.use_lock(%[[VAL_3]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_4]] : memref<256xi32>, 0, 256) +// CHECK: aie.dma_bd(%[[VAL_4]] : memref<256xi32>) {len = 256 : i32} // CHECK: aie.use_lock(%[[VAL_3]], Release, 0) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: @@ -32,7 +32,7 @@ // CHECK: %[[VAL_9:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb2) // CHECK: ^bb1: // CHECK: aie.use_lock(%[[VAL_1]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_5]] : memref<256xi32>, 0, 256) +// CHECK: aie.dma_bd(%[[VAL_5]] : memref<256xi32>) {len = 256 : i32} // CHECK: aie.use_lock(%[[VAL_1]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: @@ -66,7 +66,7 @@ module @test_lock3 { %dmaSt = aie.dma_start(MM2S, 0, ^bd0, ^end) ^bd0: aiex.useToken @token0(Acquire, 1) - aie.dma_bd(%buf33 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf33 : memref<256xi32>) { len = 256 : i32 } aiex.useToken @token0(Release, 2) aie.next_bd ^end ^end: @@ -76,7 +76,7 @@ module @test_lock3 { %dmaSt = aie.dma_start(S2MM, 0, ^bd0, ^end) ^bd0: aiex.useToken @token0(Acquire, 1) - aie.dma_bd(%buf44 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf44 : memref<256xi32>) { len = 256 : i32 } aiex.useToken @token0(Release, 2) aie.next_bd ^end ^end: diff --git a/test/create-locks/test_lock4.mlir b/test/create-locks/test_lock4.mlir index 6d9f8111b0..937aebc4d4 100644 --- a/test/create-locks/test_lock4.mlir +++ b/test/create-locks/test_lock4.mlir @@ -26,7 +26,7 @@ // CHECK: %[[VAL_11:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb2) // CHECK: ^bb1: // CHECK: aie.use_lock(%[[VAL_6]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_7]] : memref<256xi32>, 0, 256) +// CHECK: aie.dma_bd(%[[VAL_7]] : memref<256xi32>) {len = 256 : i32} // CHECK: aie.use_lock(%[[VAL_6]], Release, 0) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: @@ -38,12 +38,12 @@ // CHECK: %[[VAL_14:.*]] = aie.dma_start(MM2S, 0, ^bb3, ^bb4) // CHECK: ^bb2: // CHECK: aie.use_lock(%[[VAL_4]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_8]] : memref<256xi32>, 0, 256) +// CHECK: aie.dma_bd(%[[VAL_8]] : memref<256xi32>) {len = 256 : i32} // CHECK: aie.use_lock(%[[VAL_4]], Release, 1) // CHECK: aie.next_bd ^bb4 // CHECK: ^bb3: // CHECK: aie.use_lock(%[[VAL_3]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_8]] : memref<256xi32>, 0, 256) +// CHECK: aie.dma_bd(%[[VAL_8]] : memref<256xi32>) {len = 256 : i32} // CHECK: aie.use_lock(%[[VAL_3]], Release, 0) // CHECK: aie.next_bd ^bb4 // CHECK: ^bb4: @@ -53,7 +53,7 @@ // CHECK: %[[VAL_16:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb2) // CHECK: ^bb1: // CHECK: aie.use_lock(%[[VAL_1]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_9]] : memref<256xi32>, 0, 256) +// CHECK: aie.dma_bd(%[[VAL_9]] : memref<256xi32>) {len = 256 : i32} // CHECK: aie.use_lock(%[[VAL_1]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: @@ -98,7 +98,7 @@ module @test_lock4 { %dmaSt = aie.dma_start(MM2S, 0, ^bd0, ^end) ^bd0: aiex.useToken @token0(Acquire, 1) - aie.dma_bd(%buf33 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf33 : memref<256xi32>) { len = 256 : i32 } aiex.useToken @token0(Release, 2) aie.next_bd ^end ^end: @@ -111,12 +111,12 @@ module @test_lock4 { %dmaSt1 = aie.dma_start(MM2S, 0, ^bd1, ^end) ^bd0: aiex.useToken @token0(Acquire, 1) - aie.dma_bd(%buf44 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf44 : memref<256xi32>) { len = 256 : i32 } aiex.useToken @token0(Release, 2) aie.next_bd ^end ^bd1: aiex.useToken @token0(Acquire, 3) - aie.dma_bd(%buf44 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf44 : memref<256xi32>) { len = 256 : i32 } aiex.useToken @token0(Release, 4) aie.next_bd ^end ^end: @@ -127,7 +127,7 @@ module @test_lock4 { %dmaSt = aie.dma_start(S2MM, 0, ^bd0, ^end) ^bd0: aiex.useToken @token0(Acquire, 3) - aie.dma_bd(%buf55 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf55 : memref<256xi32>) { len = 256 : i32 } aiex.useToken @token0(Release, 4) aie.next_bd ^end ^end: diff --git a/test/create-locks/test_lock5.mlir b/test/create-locks/test_lock5.mlir index aa86769b14..767d3e36c3 100644 --- a/test/create-locks/test_lock5.mlir +++ b/test/create-locks/test_lock5.mlir @@ -23,21 +23,21 @@ // CHECK: %[[VAL_9:.*]] = aie.buffer(%[[VAL_0]]) : memref<256xi32> // CHECK: %[[VAL_10:.*]] = aie.mem(%[[VAL_4]]) { // CHECK: aie.use_lock(%[[VAL_5]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_7]] : memref<256xi32>, 0, 256) +// CHECK: aie.dma_bd(%[[VAL_7]] : memref<256xi32>) {len = 256 : i32} // CHECK: aie.use_lock(%[[VAL_5]], Release, 0) // CHECK: aie.use_lock(%[[VAL_6]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_7]] : memref<256xi32>, 0, 256) +// CHECK: aie.dma_bd(%[[VAL_7]] : memref<256xi32>) {len = 256 : i32} // CHECK: aie.use_lock(%[[VAL_6]], Release, 0) // CHECK: } // CHECK: %[[VAL_13:.*]] = aie.mem(%[[VAL_2]]) { // CHECK: aie.use_lock(%[[VAL_3]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_8]] : memref<256xi32>, 0, 256) +// CHECK: aie.dma_bd(%[[VAL_8]] : memref<256xi32>) {len = 256 : i32} // CHECK: aie.use_lock(%[[VAL_3]], Release, 1) // CHECK: aie.end // CHECK: } // CHECK: %[[VAL_15:.*]] = aie.mem(%[[VAL_0]]) { // CHECK: aie.use_lock(%[[VAL_1]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_9]] : memref<256xi32>, 0, 256) +// CHECK: aie.dma_bd(%[[VAL_9]] : memref<256xi32>) {len = 256 : i32} // CHECK: aie.use_lock(%[[VAL_1]], Release, 1) // CHECK: aie.end // CHECK: } @@ -86,12 +86,12 @@ module @test_lock5 { %dmaSt1 = aie.dma_start("MM2S", 1, ^bd1, ^end) ^bd0: aiex.useToken @token0(Acquire, 1) - aie.dma_bd(%buf33 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf33 : memref<256xi32>) { len = 256 : i32 } aiex.useToken @token0(Release, 2) aie.next_bd ^end ^bd1: aiex.useToken @token1(Acquire, 1) - aie.dma_bd(%buf33 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf33 : memref<256xi32>) { len = 256 : i32 } aiex.useToken @token1(Release, 2) aie.next_bd ^end ^end: @@ -102,7 +102,7 @@ module @test_lock5 { %dmaSt = aie.dma_start(S2MM, 0, ^bd0, ^end) ^bd0: aiex.useToken @token0(Acquire, 1) - aie.dma_bd(%buf44 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf44 : memref<256xi32>) { len = 256 : i32 } aiex.useToken @token0(Release, 2) aie.next_bd ^end ^end: @@ -113,7 +113,7 @@ module @test_lock5 { %dmaSt = aie.dma_start(S2MM, 0, ^bd0, ^end) ^bd0: aiex.useToken @token1(Acquire, 1) - aie.dma_bd(%buf55 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf55 : memref<256xi32>) { len = 256 : i32 } aiex.useToken @token1(Release, 2) aie.next_bd ^end ^end: diff --git a/test/create-locks/test_lock6.mlir b/test/create-locks/test_lock6.mlir index c96d1563e8..1fe7777ce9 100644 --- a/test/create-locks/test_lock6.mlir +++ b/test/create-locks/test_lock6.mlir @@ -26,22 +26,22 @@ // CHECK: aiex.token(0) {sym_name = "token1"} // CHECK: %[[VAL_11:.*]] = aie.mem(%[[VAL_5]]) { // CHECK: aie.use_lock(%[[VAL_6]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_7]] : memref<256xi32>, 0, 256) +// CHECK: aie.dma_bd(%[[VAL_7]] : memref<256xi32>) {len = 256 : i32} // CHECK: aie.use_lock(%[[VAL_6]], Release, 0) // CHECK: aie.end // CHECK: } // CHECK: %[[VAL_13:.*]] = aie.mem(%[[VAL_3]]) { // CHECK: aie.use_lock(%[[VAL_4]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_8]] : memref<256xi32>, 0, 256) +// CHECK: aie.dma_bd(%[[VAL_8]] : memref<256xi32>) {len = 256 : i32} // CHECK: aie.use_lock(%[[VAL_4]], Release, 0) // CHECK: aie.end // CHECK: } // CHECK: %[[VAL_15:.*]] = aie.mem(%[[VAL_0]]) { // CHECK: aie.use_lock(%[[VAL_1]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_9]] : memref<256xi32>, 0, 256) +// CHECK: aie.dma_bd(%[[VAL_9]] : memref<256xi32>) {len = 256 : i32} // CHECK: aie.use_lock(%[[VAL_1]], Release, 1) // CHECK: aie.use_lock(%[[VAL_2]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_10]] : memref<256xi32>, 0, 256) +// CHECK: aie.dma_bd(%[[VAL_10]] : memref<256xi32>) {len = 256 : i32} // CHECK: aie.use_lock(%[[VAL_2]], Release, 1) // CHECK: aie.end // CHECK: } @@ -90,7 +90,7 @@ module @test_lock6 { %dmaSt = aie.dma_start(MM2S, 0, ^bd0, ^end) ^bd0: aiex.useToken @token0(Acquire, 1) - aie.dma_bd(%buf33 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf33 : memref<256xi32>) { len = 256 : i32 } aiex.useToken @token0(Release, 2) aie.next_bd ^end ^end: @@ -101,7 +101,7 @@ module @test_lock6 { %dmaSt = aie.dma_start(S2MM, 0, ^bd0, ^end) ^bd0: aiex.useToken @token1(Acquire, 1) - aie.dma_bd(%buf44 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf44 : memref<256xi32>) { len = 256 : i32 } aiex.useToken @token1(Release, 2) aie.next_bd ^end ^end: @@ -114,12 +114,12 @@ module @test_lock6 { %dmaSt1 = aie.dma_start("S2MM", 1, ^bd1, ^end) ^bd0: aiex.useToken @token0(Acquire, 1) - aie.dma_bd(%buf55_0 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf55_0 : memref<256xi32>) { len = 256 : i32 } aiex.useToken @token0(Release, 2) aie.next_bd ^end ^bd1: aiex.useToken @token1(Acquire, 1) - aie.dma_bd(%buf55_1 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf55_1 : memref<256xi32>) { len = 256 : i32 } aiex.useToken @token1(Release, 2) aie.next_bd ^end ^end: diff --git a/test/create-locks/test_lock7.mlir b/test/create-locks/test_lock7.mlir index c7d952601e..77a7a52c36 100644 --- a/test/create-locks/test_lock7.mlir +++ b/test/create-locks/test_lock7.mlir @@ -28,22 +28,22 @@ // CHECK: aiex.token(0) {sym_name = "token1"} // CHECK: %10 = aie.mem(%4) { // CHECK: aie.use_lock({{.*}}, Acquire, 1) -// CHECK: aie.dma_bd(%7 : memref<256xi32>, 0, 256) +// CHECK: aie.dma_bd(%7 : memref<256xi32>) {len = 256 : i32} // CHECK: aie.use_lock({{.*}}, Release, 0) // CHECK: aie.use_lock({{.*}}, Acquire, 1) -// CHECK: aie.dma_bd(%7 : memref<256xi32>, 0, 256) +// CHECK: aie.dma_bd(%7 : memref<256xi32>) {len = 256 : i32} // CHECK: aie.use_lock({{.*}}, Release, 0) // CHECK: aie.end // CHECK: } // CHECK: %11 = aie.mem(%2) { // CHECK: aie.use_lock(%3, Acquire, 0) -// CHECK: aie.dma_bd(%8 : memref<256xi32>, 0, 256) +// CHECK: aie.dma_bd(%8 : memref<256xi32>) {len = 256 : i32} // CHECK: aie.use_lock(%3, Release, 1) // CHECK: aie.end // CHECK: } // CHECK: %12 = aie.mem(%0) { // CHECK: aie.use_lock(%1, Acquire, 0) -// CHECK: aie.dma_bd(%9 : memref<256xi32>, 0, 256) +// CHECK: aie.dma_bd(%9 : memref<256xi32>) {len = 256 : i32} // CHECK: aie.use_lock(%1, Release, 1) // CHECK: aie.end // CHECK: } @@ -92,12 +92,12 @@ module @test_lock5 { %dmaSt1 = aie.dma_start("MM2S1", ^bd1, ^end) ^bd0: aiex.useToken @token0(Acquire, 1) - aie.dma_bd(%buf33 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf33 : memref<256xi32>) { len = 256 : i32 } aiex.useToken @token0(Release, 2) aie.next_bd ^end ^bd1: aiex.useToken @token0(Acquire, 1) - aie.dma_bd(%buf33 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf33 : memref<256xi32>) { len = 256 : i32 } aiex.useToken @token0(Release, 2) aie.next_bd ^end ^end: @@ -108,7 +108,7 @@ module @test_lock5 { %dmaSt = aie.dma_start(S2MM0, ^bd0, ^end) ^bd0: aiex.useToken @token0(Acquire, 1) - aie.dma_bd(%buf44 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf44 : memref<256xi32>) { len = 256 : i32 } aiex.useToken @token0(Release, 2) aie.next_bd ^end ^end: @@ -119,7 +119,7 @@ module @test_lock5 { %dmaSt = aie.dma_start(S2MM0, ^bd0, ^end) ^bd0: aiex.useToken @token0(Acquire, 1) - aie.dma_bd(%buf55 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf55 : memref<256xi32>) { len = 256 : i32 } aiex.useToken @token0(Release, 2) aie.next_bd ^end ^end: diff --git a/test/create-locks/test_lock_shimdma.mlir b/test/create-locks/test_lock_shimdma.mlir index 183d824772..4d61d67592 100644 --- a/test/create-locks/test_lock_shimdma.mlir +++ b/test/create-locks/test_lock_shimdma.mlir @@ -25,7 +25,7 @@ // CHECK: %10 = aie.dma_start(S2MM, 0, ^bb1, ^bb2) // CHECK: ^bb1: // pred: ^bb0 // CHECK: aie.use_lock(%2, Acquire, 0) -// CHECK: aie.dma_bd(%0 : memref<256xi32>, 0, 256) +// CHECK: aie.dma_bd(%0 : memref<256xi32>) {len = 256 : i32} // CHECK: aie.use_lock(%2, Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // 2 preds: ^bb0, ^bb1 @@ -43,7 +43,7 @@ // CHECK: %10 = aie.dma_start(MM2S, 0, ^bb1, ^bb2) // CHECK: ^bb1: // pred: ^bb0 // CHECK: aie.use_lock(%6, Acquire, 1) -// CHECK: aie.dma_bd(%7 : memref<256xi32>, 0, 256) +// CHECK: aie.dma_bd(%7 : memref<256xi32>) {len = 256 : i32} // CHECK: aie.use_lock(%6, Release, 0) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // 2 preds: ^bb0, ^bb1 @@ -73,7 +73,7 @@ module @test_lock_shimdma { %dmaSt = aie.dma_start(S2MM, 0, ^bd0, ^end) ^bd0: aiex.useToken @token0(Acquire, 1) - aie.dma_bd(%buf_ext : memref<256xi32>, 0, 256) + aie.dma_bd(%buf_ext : memref<256xi32>) { len = 256 : i32 } aiex.useToken @token0(Release, 2) aie.next_bd ^end ^end: @@ -91,7 +91,7 @@ module @test_lock_shimdma { %dmaSt = aie.dma_start(MM2S, 0, ^bd0, ^end) ^bd0: aiex.useToken @token0(Acquire, 1) - aie.dma_bd(%buf33 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf33 : memref<256xi32>) { len = 256 : i32 } aiex.useToken @token0(Release, 2) aie.next_bd ^end ^end: diff --git a/test/dialect/AIE/bad_dma_op.mlir b/test/dialect/AIE/bad_dma_op.mlir index c8338ae838..9ed267047e 100644 --- a/test/dialect/AIE/bad_dma_op.mlir +++ b/test/dialect/AIE/bad_dma_op.mlir @@ -22,7 +22,7 @@ module { ^bb0: aie.dma(S2MM, 0) [{ aie.use_lock(%objFifo_in0_cons_prod_lock, AcquireGreaterEqual, 1) - aie.dma_bd(%objFifo_in0_cons_buff_0 : memref<16xi32>, 0, 16) + aie.dma_bd(%objFifo_in0_cons_buff_0 : memref<16xi32>) { len = 16 : i32 } aie.use_lock(%objFifo_in0_cons_cons_lock, Release, 1) }] aie.next_bd ^bb1 diff --git a/test/dialect/AIE/badmem_toomanybds.mlir b/test/dialect/AIE/badmem_toomanybds.mlir index d2ee04647f..63ac637728 100644 --- a/test/dialect/AIE/badmem_toomanybds.mlir +++ b/test/dialect/AIE/badmem_toomanybds.mlir @@ -17,55 +17,55 @@ aie.device(xcvc1902) { %mem = aie.mem(%t1) { %dma0 = aie.dma_start("MM2S", 0, ^bd0, ^bd15) ^bd0: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd1 ^bd1: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd2 ^bd2: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd3 ^bd3: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd4 ^bd4: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd5 ^bd5: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd6 ^bd6: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd7 ^bd7: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd8 ^bd8: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd9 ^bd9: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd10 ^bd10: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd11 ^bd11: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd12 ^bd12: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd13 ^bd13: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd14 ^bd14: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd15 ^bd15: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd16 ^bd16: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.end } } diff --git a/test/dialect/AIE/badmemtiledma2.mlir b/test/dialect/AIE/badmemtiledma2.mlir index 32cc4f7aab..205190a9e2 100644 --- a/test/dialect/AIE/badmemtiledma2.mlir +++ b/test/dialect/AIE/badmemtiledma2.mlir @@ -47,31 +47,31 @@ module @test { ^dma6: %dma6 = aie.dma_start("MM2S", 6, ^bd6, ^end) ^bd0: - aie.dma_bd(%buf_0 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf_0 : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%lock_0, Release, 1) aie.next_bd ^bd0 ^bd1: - aie.dma_bd(%buf_1 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf_1 : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%lock_1, Release, 1) aie.next_bd ^bd1 ^bd2: - aie.dma_bd(%buf_2 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf_2 : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%lock_2, Release, 1) aie.next_bd ^bd2 ^bd3: - aie.dma_bd(%buf_3 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf_3 : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%lock_3, Release, 1) aie.next_bd ^bd3 ^bd4: - aie.dma_bd(%buf_4 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf_4 : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%lock_4, Release, 1) aie.next_bd ^bd4 ^bd5: - aie.dma_bd(%buf_5 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf_5 : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%lock_5, Release, 1) aie.next_bd ^bd5 ^bd6: - aie.dma_bd(%buf_6 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf_6 : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%lock_6, Release, 1) aie.next_bd ^bd6 ^end: diff --git a/test/dialect/AIE/badmemtiledma_channel4buffer.mlir b/test/dialect/AIE/badmemtiledma_channel4buffer.mlir index 7e797e30f7..00fedf89fd 100644 --- a/test/dialect/AIE/badmemtiledma_channel4buffer.mlir +++ b/test/dialect/AIE/badmemtiledma_channel4buffer.mlir @@ -26,10 +26,10 @@ aie.device(xcve2802) { ^dma1: aie.dma_start("MM2S", 4, ^bd1, ^dma1) ^bd0: - aie.dma_bd(%buf1 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf1 : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd2 ^bd1: - aie.dma_bd(%buf2 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf2 : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd2 ^bd2: aie.end diff --git a/test/dialect/AIE/badmemtiledma_channel4lock.mlir b/test/dialect/AIE/badmemtiledma_channel4lock.mlir index 9de4558c84..1e6440e450 100644 --- a/test/dialect/AIE/badmemtiledma_channel4lock.mlir +++ b/test/dialect/AIE/badmemtiledma_channel4lock.mlir @@ -27,11 +27,11 @@ aie.device(xcve2802) { aie.dma_start("MM2S", 1, ^bd1, ^dma1) ^bd0: aie.use_lock(%lock2, "Acquire", 1) - aie.dma_bd(%buf1 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf1 : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd2 ^bd1: aie.use_lock(%lock1, "Acquire", 1) - aie.dma_bd(%buf1 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf1 : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd2 ^bd2: aie.end diff --git a/test/dialect/AIE/badmemtiledma_neighboraccess.mlir b/test/dialect/AIE/badmemtiledma_neighboraccess.mlir index 79eead4431..39da593bd2 100644 --- a/test/dialect/AIE/badmemtiledma_neighboraccess.mlir +++ b/test/dialect/AIE/badmemtiledma_neighboraccess.mlir @@ -25,19 +25,19 @@ aie.device(xcve2802) { ^dma1: aie.dma_start("MM2S", 1, ^bd15, ^dma1) ^bd0: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd1 ^bd1: - aie.dma_bd(%buf0 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf0 : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd2 ^bd2: - aie.dma_bd(%buf2 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf2 : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd15 ^bd15: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd16 ^bd16: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.end } } diff --git a/test/dialect/AIE/badshim_toomanybds.mlir b/test/dialect/AIE/badshim_toomanybds.mlir index 2cb3e22adf..79aaa2773d 100644 --- a/test/dialect/AIE/badshim_toomanybds.mlir +++ b/test/dialect/AIE/badshim_toomanybds.mlir @@ -17,55 +17,55 @@ aie.device(xcvc1902) { %mem = aie.shim_dma(%t1) { %dma0 = aie.dma_start("MM2S", 0, ^bd0, ^bd15) ^bd0: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd1 ^bd1: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd2 ^bd2: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd3 ^bd3: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd4 ^bd4: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd5 ^bd5: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd6 ^bd6: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd7 ^bd7: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd8 ^bd8: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd9 ^bd9: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd10 ^bd10: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd11 ^bd11: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd12 ^bd12: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd13 ^bd13: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd14 ^bd14: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd15 ^bd15: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd16 ^bd16: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.end } } diff --git a/test/dialect/AIE/badshimtiledma.mlir b/test/dialect/AIE/badshimtiledma.mlir index 7edde144f0..15288efed0 100644 --- a/test/dialect/AIE/badshimtiledma.mlir +++ b/test/dialect/AIE/badshimtiledma.mlir @@ -31,15 +31,15 @@ module @test { ^dma2: %dma3 = aie.dma_start("S2MM", 2, ^bd2, ^end) ^bd0: - aie.dma_bd(%buf_l : memref<256xi32>, 1, 256) + aie.dma_bd(%buf_l : memref<256xi32>) { offset = 1 : i32, len = 256 : i32 } aie.use_lock(%lock_e, Release, 1) aie.next_bd ^bd0 ^bd1: - aie.dma_bd(%buf_l : memref<256xi32>, 1, 256) + aie.dma_bd(%buf_l : memref<256xi32>) { offset = 1 : i32, len = 256 : i32 } aie.use_lock(%lock_l, Release, 1) aie.next_bd ^bd1 ^bd2: - aie.dma_bd(%buf_l : memref<256xi32>, 1, 256) + aie.dma_bd(%buf_l : memref<256xi32>) { offset = 1 : i32, len = 256 : i32 } aie.use_lock(%lock_n, Release, 1) aie.next_bd ^bd2 ^end: diff --git a/test/dialect/AIE/badtiledma.mlir b/test/dialect/AIE/badtiledma.mlir index cb41a6114b..0b55e9565a 100644 --- a/test/dialect/AIE/badtiledma.mlir +++ b/test/dialect/AIE/badtiledma.mlir @@ -34,19 +34,19 @@ module @test { %dstDma = aie.dma_start("S2MM", 0, ^bd2, ^end) ^bd0: aie.use_lock(%lock_l, Acquire, 0) - aie.dma_bd(%buf_e : memref<256xi32>, 0, 256) + aie.dma_bd(%buf_e : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%lock_e, Release, 1) aie.next_bd ^bd1 ^bd1: - aie.dma_bd(%buf_l : memref<256xi32>, 0, 256) + aie.dma_bd(%buf_l : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%lock_l, Release, 1) aie.next_bd ^end ^bd2: - aie.dma_bd(%buf_n : memref<256xi32>, 0, 256) + aie.dma_bd(%buf_n : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%lock_n, Release, 1) aie.next_bd ^bd3 ^bd3: - aie.dma_bd(%buf_s : memref<256xi32>, 0, 256) + aie.dma_bd(%buf_s : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%lock_s, Release, 1) aie.next_bd ^end ^end: diff --git a/test/dialect/AIE/badtiledma2.mlir b/test/dialect/AIE/badtiledma2.mlir index ac37222545..b3c94ba658 100644 --- a/test/dialect/AIE/badtiledma2.mlir +++ b/test/dialect/AIE/badtiledma2.mlir @@ -9,7 +9,7 @@ //===----------------------------------------------------------------------===// // RUN: not %PYTHON aiecc.py %s 2>&1 | FileCheck %s -// CHECK: error{{.*}}'aie.dma_bd' op can only access a buffer in the same tile. +// CHECK: error{{.*}}'aie.dma_bd' op Core tile DMAs can only access a buffer in the same tile. module @test { %t63 = aie.tile(6, 3) @@ -33,19 +33,19 @@ module @test { ^dma1: %dstDma = aie.dma_start("S2MM", 0, ^bd2, ^end) ^bd0: - aie.dma_bd(%buf_e : memref<256xi32>, 0, 256) + aie.dma_bd(%buf_e : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%lock_e, Release, 1) aie.next_bd ^bd1 ^bd1: - aie.dma_bd(%buf_l : memref<256xi32>, 0, 256) + aie.dma_bd(%buf_l : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%lock_l, Release, 1) aie.next_bd ^end ^bd2: - aie.dma_bd(%buf_n : memref<256xi32>, 0, 256) + aie.dma_bd(%buf_n : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%lock_n, Release, 1) aie.next_bd ^bd3 ^bd3: - aie.dma_bd(%buf_s : memref<256xi32>, 0, 256) + aie.dma_bd(%buf_s : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%lock_s, Release, 1) aie.next_bd ^end ^end: diff --git a/test/dialect/AIE/badtiledma3.mlir b/test/dialect/AIE/badtiledma3.mlir index 5af6a3cfc6..60eec425c7 100644 --- a/test/dialect/AIE/badtiledma3.mlir +++ b/test/dialect/AIE/badtiledma3.mlir @@ -33,19 +33,19 @@ module @test { ^dma1: %dstDma = aie.dma_start("S2MM", 0, ^bd2, ^end) ^bd0: - aie.dma_bd(%buf_l : memref<256xi32>, 0, 256) + aie.dma_bd(%buf_l : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%lock_e, Release, 1) aie.next_bd ^bd1 ^bd1: - aie.dma_bd(%buf_l : memref<256xi32>, 0, 256) + aie.dma_bd(%buf_l : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%lock_l, Release, 1) aie.next_bd ^end ^bd2: - aie.dma_bd(%buf_l : memref<256xi32>, 0, 256) + aie.dma_bd(%buf_l : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%lock_n, Release, 1) aie.next_bd ^bd3 ^bd3: - aie.dma_bd(%buf_l : memref<256xi32>, 0, 256) + aie.dma_bd(%buf_l : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%lock_s, Release, 1) aie.next_bd ^end ^end: diff --git a/test/dialect/AIE/badtiledma4.mlir b/test/dialect/AIE/badtiledma4.mlir index 7d2cf2b9ce..1c477a44d3 100644 --- a/test/dialect/AIE/badtiledma4.mlir +++ b/test/dialect/AIE/badtiledma4.mlir @@ -31,15 +31,15 @@ module @test { ^dma2: %dma3 = aie.dma_start("MM2S", 2, ^bd2, ^end) ^bd0: - aie.dma_bd(%buf_l : memref<256xi32>, 0, 256) + aie.dma_bd(%buf_l : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%lock_e, Release, 1) aie.next_bd ^bd0 ^bd1: - aie.dma_bd(%buf_l : memref<256xi32>, 0, 256) + aie.dma_bd(%buf_l : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%lock_l, Release, 1) aie.next_bd ^bd1 ^bd2: - aie.dma_bd(%buf_l : memref<256xi32>, 0, 256) + aie.dma_bd(%buf_l : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%lock_n, Release, 1) aie.next_bd ^bd2 ^end: diff --git a/test/dialect/AIE/example0.mlir b/test/dialect/AIE/example0.mlir index cea1176b5c..37b2142220 100644 --- a/test/dialect/AIE/example0.mlir +++ b/test/dialect/AIE/example0.mlir @@ -49,12 +49,12 @@ module @example0 { %dmaSt1 = aie.dma_start("MM2S", 1, ^bd1, ^end) ^bd0: aie.use_lock(%l33_0, Acquire, 1) - aie.dma_bd(%buf33 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf33 : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%l33_0, Release, 0) aie.next_bd ^end ^bd1: aie.use_lock(%l33_1, Acquire, 0) - aie.dma_bd(%buf33 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf33 : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%l33_1, Release, 1) aie.next_bd ^end ^end: @@ -65,7 +65,7 @@ module @example0 { %dmaSt = aie.dma_start(S2MM, 0, ^bd0, ^end) ^bd0: aie.use_lock(%l42_0, Acquire, 0) - aie.dma_bd(%buf42 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf42 : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%l42_0, Release, 1) aie.next_bd ^end ^end: @@ -76,7 +76,7 @@ module @example0 { %dmaSt = aie.dma_start(S2MM, 0, ^bd0, ^end) ^bd0: aie.use_lock(%l44_0, Acquire, 1) - aie.dma_bd(%buf44 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf44 : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%l44_0, Release, 0) aie.next_bd ^end ^end: diff --git a/test/dialect/AIE/memtiledma.mlir b/test/dialect/AIE/memtiledma.mlir index d740b09ee6..de221a305f 100644 --- a/test/dialect/AIE/memtiledma.mlir +++ b/test/dialect/AIE/memtiledma.mlir @@ -23,55 +23,55 @@ aie.device(xcve2802) { ^dma1: aie.dma_start("MM2S", 1, ^bd15, ^dma1) ^bd0: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd1 ^bd1: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd2 ^bd2: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd3 ^bd3: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd4 ^bd4: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd5 ^bd5: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd6 ^bd6: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd7 ^bd7: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd8 ^bd8: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd9 ^bd9: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd10 ^bd10: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd11 ^bd11: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd12 ^bd12: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd13 ^bd13: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd14 ^bd14: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd15 ^bd15: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd16 ^bd16: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.end } } diff --git a/test/dialect/AIE/memtiledma_channel4buffer.mlir b/test/dialect/AIE/memtiledma_channel4buffer.mlir index c29a297aa0..e7184f9f2a 100644 --- a/test/dialect/AIE/memtiledma_channel4buffer.mlir +++ b/test/dialect/AIE/memtiledma_channel4buffer.mlir @@ -25,10 +25,10 @@ aie.device(xcve2802) { ^dma1: aie.dma_start("MM2S", 1, ^bd1, ^dma1) ^bd0: - aie.dma_bd(%buf1 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf1 : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd2 ^bd1: - aie.dma_bd(%buf2 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf2 : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd2 ^bd2: aie.end diff --git a/test/dialect/AIE/memtiledma_channel4lock.mlir b/test/dialect/AIE/memtiledma_channel4lock.mlir index 61135e2add..90be4d55c5 100644 --- a/test/dialect/AIE/memtiledma_channel4lock.mlir +++ b/test/dialect/AIE/memtiledma_channel4lock.mlir @@ -27,11 +27,11 @@ aie.device(xcve2802) { aie.dma_start("MM2S", 1, ^bd1, ^dma1) ^bd0: aie.use_lock(%lock1, "Acquire", 1) - aie.dma_bd(%buf1 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf1 : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd2 ^bd1: aie.use_lock(%lock2, "Acquire", 1) - aie.dma_bd(%buf1 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf1 : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd2 ^bd2: aie.end diff --git a/test/dialect/AIE/memtiledma_neighboraccess.mlir b/test/dialect/AIE/memtiledma_neighboraccess.mlir index 73da83a2a9..cd65dea3d4 100644 --- a/test/dialect/AIE/memtiledma_neighboraccess.mlir +++ b/test/dialect/AIE/memtiledma_neighboraccess.mlir @@ -27,19 +27,19 @@ aie.device(xcve2802) { ^dma1: aie.dma_start("MM2S", 1, ^bd15, ^dma1) ^bd0: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd1 ^bd1: - aie.dma_bd(%buf0 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf0 : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd2 ^bd2: - aie.dma_bd(%buf2 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf2 : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd15 ^bd15: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd16 ^bd16: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.end } } diff --git a/test/dialect/AIE/nd-dma-bad-stride.mlir b/test/dialect/AIE/nd-dma-bad-stride.mlir new file mode 100644 index 0000000000..488102a8ba --- /dev/null +++ b/test/dialect/AIE/nd-dma-bad-stride.mlir @@ -0,0 +1,31 @@ +//===- aie.mlir ------------------------------------------------*- MLIR -*-===// +// +// This file is licensed under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +// Copyright (C) 2023, Advanced Micro Devices, Inc. +// +//===----------------------------------------------------------------------===// + +// RUN: aie-opt --verify-diagnostics %s + +module @tutorial_2b { + aie.device(xcve2802) { + %tile14 = aie.tile(1, 4) + %tile34 = aie.tile(3, 4) + + aie.flow(%tile14, DMA : 0, %tile34, DMA : 0) + %buf14 = aie.buffer(%tile14) : memref<128xi16> + %lock14_done = aie.lock(%tile14, 0) { init = 0 : i32 } + %mem14 = aie.mem(%tile14) { + %srcDma = aie.dma_start("MM2S", 0, ^bd0, ^end) + ^bd0: + // expected-error@+1 {{'aie.dma_bd' op For <32b width datatypes, inner-most dim stride must be 1}} + aie.dma_bd(%buf14 : memref<128xi16>, dims = []) { len = 128 : i32 } + aie.next_bd ^end + ^end: + aie.end + } + } +} \ No newline at end of file diff --git a/test/dialect/AIE/nd-dma-oob.mlir b/test/dialect/AIE/nd-dma-oob.mlir index 866220c97f..adf3aeb19f 100644 --- a/test/dialect/AIE/nd-dma-oob.mlir +++ b/test/dialect/AIE/nd-dma-oob.mlir @@ -30,7 +30,7 @@ module @tutorial_2b { // attempt an access at index 128, which is OOB for a 128xi32 // memref. // expected-error@+1 {{Specified stride(s) and size(s) result in out of bounds access}} - aie.dma_bd(%buf14 : memref<128xi32>, 0, 128, []) + aie.dma_bd(%buf14 : memref<128xi32>, dims = []) { len = 128 : i32 } aie.next_bd ^end ^end: aie.end diff --git a/test/dialect/AIE/nd-dma-too-many-dims-1.mlir b/test/dialect/AIE/nd-dma-too-many-dims-1.mlir index b8bceb6c7d..a2a32c795e 100644 --- a/test/dialect/AIE/nd-dma-too-many-dims-1.mlir +++ b/test/dialect/AIE/nd-dma-too-many-dims-1.mlir @@ -21,7 +21,7 @@ module @tutorial_2b { %srcDma = aie.dma_start("MM2S", 0, ^bd0, ^end) ^bd0: //expected-error@+1 {{Cannot give more than 4 dimensions}} - aie.dma_bd(%buf31 : memref<128xi32>, 0, 128, [, , , , ]) + aie.dma_bd(%buf31 : memref<128xi32>, dims = [, , , , ]) { len = 128 : i32 } aie.next_bd ^end ^end: aie.end diff --git a/test/dialect/AIE/nd-dma-too-many-dims-2.mlir b/test/dialect/AIE/nd-dma-too-many-dims-2.mlir index dc6edac5f6..4a4c5f6a6b 100644 --- a/test/dialect/AIE/nd-dma-too-many-dims-2.mlir +++ b/test/dialect/AIE/nd-dma-too-many-dims-2.mlir @@ -21,7 +21,7 @@ module @tutorial_2b { %srcDma = aie.dma_start("MM2S", 0, ^bd0, ^end) ^bd0: //expected-error@+1 {{Cannot give more than 3 dimensions}} - aie.dma_bd(%buf33 : memref<128xi32>, 0, 128, [, , , ]) + aie.dma_bd(%buf33 : memref<128xi32>, dims = [, , , ]) { len = 128 : i32 } aie.next_bd ^end ^end: aie.end diff --git a/test/dialect/AIE/shimdma.mlir b/test/dialect/AIE/shimdma.mlir index 6aaf7223b7..cc322cdc5f 100644 --- a/test/dialect/AIE/shimdma.mlir +++ b/test/dialect/AIE/shimdma.mlir @@ -23,52 +23,52 @@ aie.device(xcvc1902) { ^dma1: aie.dma_start("MM2S", 1, ^bd15, ^dma1) ^bd0: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd1 ^bd1: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd2 ^bd2: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd3 ^bd3: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd4 ^bd4: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd5 ^bd5: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd6 ^bd6: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd7 ^bd7: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd8 ^bd8: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd9 ^bd9: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd10 ^bd10: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd11 ^bd11: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd12 ^bd12: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd13 ^bd13: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd14 ^bd14: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd15 ^bd15: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.end } } diff --git a/test/dialect/AIE/tiledma.mlir b/test/dialect/AIE/tiledma.mlir index 2a56055e0d..506d62d025 100644 --- a/test/dialect/AIE/tiledma.mlir +++ b/test/dialect/AIE/tiledma.mlir @@ -23,52 +23,52 @@ aie.device(xcvc1902) { ^dma1: aie.dma_start("MM2S", 1, ^bd15, ^dma1) ^bd0: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd1 ^bd1: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd2 ^bd2: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd3 ^bd3: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd4 ^bd4: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd5 ^bd5: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd6 ^bd6: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd7 ^bd7: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd8 ^bd8: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd9 ^bd9: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd10 ^bd10: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd11 ^bd11: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd12 ^bd12: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd13 ^bd13: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd14 ^bd14: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bd15 ^bd15: - aie.dma_bd(%buf : memref<256xi32>, 0, 256) + aie.dma_bd(%buf : memref<256xi32>) { len = 256 : i32 } aie.end } } diff --git a/test/ipu-xrt/add_one_using_dma/aie.mlir b/test/ipu-xrt/add_one_using_dma/aie.mlir index 058ae034bc..fce07d8767 100644 --- a/test/ipu-xrt/add_one_using_dma/aie.mlir +++ b/test/ipu-xrt/add_one_using_dma/aie.mlir @@ -95,48 +95,48 @@ module { %0 = aie.dma_start(S2MM, 0, ^bb1, ^bb3) ^bb1: // 2 preds: ^bb0, ^bb2 aie.use_lock(%objFifo_in0_cons_prod_lock, AcquireGreaterEqual, 1) - aie.dma_bd(%objFifo_in0_cons_buff_0 : memref<16xi32>, 0, 16) + aie.dma_bd(%objFifo_in0_cons_buff_0 : memref<16xi32>) { len = 16 : i32 } aie.use_lock(%objFifo_in0_cons_cons_lock, Release, 1) aie.next_bd ^bb2 ^bb2: // pred: ^bb1 aie.use_lock(%objFifo_in0_cons_prod_lock, AcquireGreaterEqual, 1) - aie.dma_bd(%objFifo_in0_cons_buff_1 : memref<16xi32>, 0, 16) + aie.dma_bd(%objFifo_in0_cons_buff_1 : memref<16xi32>) { len = 16 : i32 } aie.use_lock(%objFifo_in0_cons_cons_lock, Release, 1) aie.next_bd ^bb1 ^bb3: // pred: ^bb0 %1 = aie.dma_start(MM2S, 0, ^bb4, ^bb6) ^bb4: // 2 preds: ^bb3, ^bb5 aie.use_lock(%objFifo_in0_cons_cons_lock, AcquireGreaterEqual, 1) - aie.dma_bd(%objFifo_in0_cons_buff_0 : memref<16xi32>, 0, 16) + aie.dma_bd(%objFifo_in0_cons_buff_0 : memref<16xi32>) { len = 16 : i32 } aie.use_lock(%objFifo_in0_cons_prod_lock, Release, 1) aie.next_bd ^bb5 ^bb5: // pred: ^bb4 aie.use_lock(%objFifo_in0_cons_cons_lock, AcquireGreaterEqual, 1) - aie.dma_bd(%objFifo_in0_cons_buff_1 : memref<16xi32>, 0, 16) + aie.dma_bd(%objFifo_in0_cons_buff_1 : memref<16xi32>) { len = 16 : i32 } aie.use_lock(%objFifo_in0_cons_prod_lock, Release, 1) aie.next_bd ^bb4 ^bb6: // pred: ^bb3 %2 = aie.dma_start(MM2S, 1, ^bb7, ^bb9) ^bb7: // 2 preds: ^bb6, ^bb8 aie.use_lock(%objFifo_out0_cons_lock, AcquireGreaterEqual, 1) - aie.dma_bd(%objFifo_out0_buff_0 : memref<16xi32>, 0, 16) + aie.dma_bd(%objFifo_out0_buff_0 : memref<16xi32>) { len = 16 : i32 } aie.use_lock(%objFifo_out0_prod_lock, Release, 1) aie.next_bd ^bb8 ^bb8: // pred: ^bb7 aie.use_lock(%objFifo_out0_cons_lock, AcquireGreaterEqual, 1) - aie.dma_bd(%objFifo_out0_buff_1 : memref<16xi32>, 0, 16) + aie.dma_bd(%objFifo_out0_buff_1 : memref<16xi32>) { len = 16 : i32 } aie.use_lock(%objFifo_out0_prod_lock, Release, 1) aie.next_bd ^bb7 ^bb9: // pred: ^bb6 %3 = aie.dma_start(S2MM, 1, ^bb10, ^bb12) ^bb10: // 2 preds: ^bb9, ^bb11 aie.use_lock(%objFifo_out0_prod_lock, AcquireGreaterEqual, 1) - aie.dma_bd(%objFifo_out0_buff_0 : memref<16xi32>, 0, 16) + aie.dma_bd(%objFifo_out0_buff_0 : memref<16xi32>) { len = 16 : i32 } aie.use_lock(%objFifo_out0_cons_lock, Release, 1) aie.next_bd ^bb11 ^bb11: // pred: ^bb10 aie.use_lock(%objFifo_out0_prod_lock, AcquireGreaterEqual, 1) - aie.dma_bd(%objFifo_out0_buff_1 : memref<16xi32>, 0, 16) + aie.dma_bd(%objFifo_out0_buff_1 : memref<16xi32>) { len = 16 : i32 } aie.use_lock(%objFifo_out0_cons_lock, Release, 1) aie.next_bd ^bb10 ^bb12: // pred: ^bb9 @@ -149,24 +149,24 @@ module { %0 = aie.dma_start(S2MM, 0, ^bb1, ^bb3) ^bb1: // 2 preds: ^bb0, ^bb2 aie.use_lock(%objFifo_in1_cons_prod_lock, AcquireGreaterEqual, 1) - aie.dma_bd(%objFifo_in1_cons_buff_0 : memref<8xi32>, 0, 8) + aie.dma_bd(%objFifo_in1_cons_buff_0 : memref<8xi32>) { len = 8 : i32 } aie.use_lock(%objFifo_in1_cons_cons_lock, Release, 1) aie.next_bd ^bb2 ^bb2: // pred: ^bb1 aie.use_lock(%objFifo_in1_cons_prod_lock, AcquireGreaterEqual, 1) - aie.dma_bd(%objFifo_in1_cons_buff_1 : memref<8xi32>, 0, 8) + aie.dma_bd(%objFifo_in1_cons_buff_1 : memref<8xi32>) { len = 8 : i32 } aie.use_lock(%objFifo_in1_cons_cons_lock, Release, 1) aie.next_bd ^bb1 ^bb3: // pred: ^bb0 %1 = aie.dma_start(MM2S, 0, ^bb4, ^bb6) ^bb4: // 2 preds: ^bb3, ^bb5 aie.use_lock(%objFifo_out1_cons_lock, AcquireGreaterEqual, 1) - aie.dma_bd(%objFifo_out1_buff_0 : memref<8xi32>, 0, 8) + aie.dma_bd(%objFifo_out1_buff_0 : memref<8xi32>) { len = 8 : i32 } aie.use_lock(%objFifo_out1_prod_lock, Release, 1) aie.next_bd ^bb5 ^bb5: // pred: ^bb4 aie.use_lock(%objFifo_out1_cons_lock, AcquireGreaterEqual, 1) - aie.dma_bd(%objFifo_out1_buff_1 : memref<8xi32>, 0, 8) + aie.dma_bd(%objFifo_out1_buff_1 : memref<8xi32>) { len = 8 : i32 } aie.use_lock(%objFifo_out1_prod_lock, Release, 1) aie.next_bd ^bb4 ^bb6: // pred: ^bb3 diff --git a/test/ipu-xrt/matrix_multiplication_using_dma/aie.mlir b/test/ipu-xrt/matrix_multiplication_using_dma/aie.mlir index d54eaa445c..97c4a9a36c 100644 --- a/test/ipu-xrt/matrix_multiplication_using_dma/aie.mlir +++ b/test/ipu-xrt/matrix_multiplication_using_dma/aie.mlir @@ -134,72 +134,72 @@ module { %0 = aie.dma_start(S2MM, 0, ^bb1, ^bb3) ^bb1: // 2 preds: ^bb0, ^bb2 aie.use_lock(%inA_cons_prod_lock, AcquireGreaterEqual) - aie.dma_bd(%inA_cons_buff_0 : memref<64x32xi16>, 0, 2048) + aie.dma_bd(%inA_cons_buff_0 : memref<64x32xi16>) { len = 2048 : i32 } aie.use_lock(%inA_cons_cons_lock, Release) aie.next_bd ^bb2 ^bb2: // pred: ^bb1 aie.use_lock(%inA_cons_prod_lock, AcquireGreaterEqual) - aie.dma_bd(%inA_cons_buff_1 : memref<64x32xi16>, 0, 2048) + aie.dma_bd(%inA_cons_buff_1 : memref<64x32xi16>) { len = 2048 : i32 } aie.use_lock(%inA_cons_cons_lock, Release) aie.next_bd ^bb1 ^bb3: // pred: ^bb0 %1 = aie.dma_start(MM2S, 0, ^bb4, ^bb6) ^bb4: // 2 preds: ^bb3, ^bb5 aie.use_lock(%inA_cons_cons_lock, AcquireGreaterEqual) - aie.dma_bd(%inA_cons_buff_0 : memref<64x32xi16>, 0, 2048, [, , , ]) + aie.dma_bd(%inA_cons_buff_0 : memref<64x32xi16>, dims = [, , , ]) { len = 2048 : i32 } aie.use_lock(%inA_cons_prod_lock, Release) aie.next_bd ^bb5 ^bb5: // pred: ^bb4 aie.use_lock(%inA_cons_cons_lock, AcquireGreaterEqual) - aie.dma_bd(%inA_cons_buff_1 : memref<64x32xi16>, 0, 2048, [, , , ]) + aie.dma_bd(%inA_cons_buff_1 : memref<64x32xi16>, dims = [, , , ]) { len = 2048 : i32 } aie.use_lock(%inA_cons_prod_lock, Release) aie.next_bd ^bb4 ^bb6: // pred: ^bb3 %2 = aie.dma_start(S2MM, 1, ^bb7, ^bb9) ^bb7: // 2 preds: ^bb6, ^bb8 aie.use_lock(%inB_cons_prod_lock, AcquireGreaterEqual) - aie.dma_bd(%inB_cons_buff_0 : memref<32x64xi16>, 0, 2048) + aie.dma_bd(%inB_cons_buff_0 : memref<32x64xi16>) { len = 2048 : i32 } aie.use_lock(%inB_cons_cons_lock, Release) aie.next_bd ^bb8 ^bb8: // pred: ^bb7 aie.use_lock(%inB_cons_prod_lock, AcquireGreaterEqual) - aie.dma_bd(%inB_cons_buff_1 : memref<32x64xi16>, 0, 2048) + aie.dma_bd(%inB_cons_buff_1 : memref<32x64xi16>) { len = 2048 : i32 } aie.use_lock(%inB_cons_cons_lock, Release) aie.next_bd ^bb7 ^bb9: // pred: ^bb6 %3 = aie.dma_start(MM2S, 1, ^bb10, ^bb12) ^bb10: // 2 preds: ^bb9, ^bb11 aie.use_lock(%inB_cons_cons_lock, AcquireGreaterEqual) - aie.dma_bd(%inB_cons_buff_0 : memref<32x64xi16>, 0, 2048, [, , , ]) + aie.dma_bd(%inB_cons_buff_0 : memref<32x64xi16>, dims = [, , , ]) { len = 2048 : i32 } aie.use_lock(%inB_cons_prod_lock, Release) aie.next_bd ^bb11 ^bb11: // pred: ^bb10 aie.use_lock(%inB_cons_cons_lock, AcquireGreaterEqual) - aie.dma_bd(%inB_cons_buff_1 : memref<32x64xi16>, 0, 2048, [, , , ]) + aie.dma_bd(%inB_cons_buff_1 : memref<32x64xi16>, dims = [, , , ]) { len = 2048 : i32 } aie.use_lock(%inB_cons_prod_lock, Release) aie.next_bd ^bb10 ^bb12: // pred: ^bb9 %4 = aie.dma_start(S2MM, 2, ^bb13, ^bb15) ^bb13: // 2 preds: ^bb12, ^bb14 aie.use_lock(%memC_cons_prod_lock, AcquireGreaterEqual) - aie.dma_bd(%memC_cons_buff_0 : memref<64x64xi16>, 0, 4096) + aie.dma_bd(%memC_cons_buff_0 : memref<64x64xi16>) { len = 4096 : i32 } aie.use_lock(%memC_cons_cons_lock, Release) aie.next_bd ^bb14 ^bb14: // pred: ^bb13 aie.use_lock(%memC_cons_prod_lock, AcquireGreaterEqual) - aie.dma_bd(%memC_cons_buff_1 : memref<64x64xi16>, 0, 4096) + aie.dma_bd(%memC_cons_buff_1 : memref<64x64xi16>) { len = 4096 : i32 } aie.use_lock(%memC_cons_cons_lock, Release) aie.next_bd ^bb13 ^bb15: // pred: ^bb12 %5 = aie.dma_start(MM2S, 2, ^bb16, ^bb18) ^bb16: // 2 preds: ^bb15, ^bb17 aie.use_lock(%memC_cons_cons_lock, AcquireGreaterEqual) - aie.dma_bd(%memC_cons_buff_0 : memref<64x64xi16>, 0, 4096, [, , , ]) + aie.dma_bd(%memC_cons_buff_0 : memref<64x64xi16>, dims = [, , , ]) { len = 4096 : i32 } aie.use_lock(%memC_cons_prod_lock, Release) aie.next_bd ^bb17 ^bb17: // pred: ^bb16 aie.use_lock(%memC_cons_cons_lock, AcquireGreaterEqual) - aie.dma_bd(%memC_cons_buff_1 : memref<64x64xi16>, 0, 4096, [, , , ]) + aie.dma_bd(%memC_cons_buff_1 : memref<64x64xi16>, dims = [, , , ]) { len = 4096 : i32 } aie.use_lock(%memC_cons_prod_lock, Release) aie.next_bd ^bb16 ^bb18: // pred: ^bb15 @@ -211,36 +211,36 @@ module { %0 = aie.dma_start(S2MM, 0, ^bb1, ^bb3) ^bb1: // 2 preds: ^bb0, ^bb2 aie.use_lock(%memA_cons_prod_lock, AcquireGreaterEqual) - aie.dma_bd(%memA_cons_buff_0 : memref<64x32xi16>, 0, 2048) + aie.dma_bd(%memA_cons_buff_0 : memref<64x32xi16>) { len = 2048 : i32 } aie.use_lock(%memA_cons_cons_lock, Release) aie.next_bd ^bb2 ^bb2: // pred: ^bb1 aie.use_lock(%memA_cons_prod_lock, AcquireGreaterEqual) - aie.dma_bd(%memA_cons_buff_1 : memref<64x32xi16>, 0, 2048) + aie.dma_bd(%memA_cons_buff_1 : memref<64x32xi16>) { len = 2048 : i32 } aie.use_lock(%memA_cons_cons_lock, Release) aie.next_bd ^bb1 ^bb3: // pred: ^bb0 %1 = aie.dma_start(S2MM, 1, ^bb4, ^bb6) ^bb4: // 2 preds: ^bb3, ^bb5 aie.use_lock(%memB_cons_prod_lock, AcquireGreaterEqual) - aie.dma_bd(%memB_cons_buff_0 : memref<32x64xi16>, 0, 2048) + aie.dma_bd(%memB_cons_buff_0 : memref<32x64xi16>) { len = 2048 : i32 } aie.use_lock(%memB_cons_cons_lock, Release) aie.next_bd ^bb5 ^bb5: // pred: ^bb4 aie.use_lock(%memB_cons_prod_lock, AcquireGreaterEqual) - aie.dma_bd(%memB_cons_buff_1 : memref<32x64xi16>, 0, 2048) + aie.dma_bd(%memB_cons_buff_1 : memref<32x64xi16>) { len = 2048 : i32 } aie.use_lock(%memB_cons_cons_lock, Release) aie.next_bd ^bb4 ^bb6: // pred: ^bb3 %2 = aie.dma_start(MM2S, 0, ^bb7, ^bb9) ^bb7: // 2 preds: ^bb6, ^bb8 aie.use_lock(%memC_cons_lock, AcquireGreaterEqual) - aie.dma_bd(%memC_buff_0 : memref<64x64xi16>, 0, 4096) + aie.dma_bd(%memC_buff_0 : memref<64x64xi16>) { len = 4096 : i32 } aie.use_lock(%memC_prod_lock, Release) aie.next_bd ^bb8 ^bb8: // pred: ^bb7 aie.use_lock(%memC_cons_lock, AcquireGreaterEqual) - aie.dma_bd(%memC_buff_1 : memref<64x64xi16>, 0, 4096) + aie.dma_bd(%memC_buff_1 : memref<64x64xi16>) { len = 4096 : i32 } aie.use_lock(%memC_prod_lock, Release) aie.next_bd ^bb7 ^bb9: // pred: ^bb6 diff --git a/test/ipu-xrt/vector_scalar_using_dma/aie.mlir b/test/ipu-xrt/vector_scalar_using_dma/aie.mlir index ebdd9aaefb..cc9393ef7a 100644 --- a/test/ipu-xrt/vector_scalar_using_dma/aie.mlir +++ b/test/ipu-xrt/vector_scalar_using_dma/aie.mlir @@ -78,24 +78,24 @@ module { %0 = aie.dma_start(S2MM, 0, ^bb1, ^bb3) ^bb1: // 2 preds: ^bb0, ^bb2 aie.use_lock(%in_cons_prod_lock, AcquireGreaterEqual, 1) - aie.dma_bd(%in_cons_buff_0 : memref<1024xi32>, 0, 1024) + aie.dma_bd(%in_cons_buff_0 : memref<1024xi32>) { len = 1024 : i32 } aie.use_lock(%in_cons_cons_lock, Release, 1) aie.next_bd ^bb2 ^bb2: // pred: ^bb1 aie.use_lock(%in_cons_prod_lock, AcquireGreaterEqual, 1) - aie.dma_bd(%in_cons_buff_1 : memref<1024xi32>, 0, 1024) + aie.dma_bd(%in_cons_buff_1 : memref<1024xi32>) { len = 1024 : i32 } aie.use_lock(%in_cons_cons_lock, Release, 1) aie.next_bd ^bb1 ^bb3: // pred: ^bb0 %1 = aie.dma_start(MM2S, 0, ^bb4, ^bb6) ^bb4: // 2 preds: ^bb3, ^bb5 aie.use_lock(%out_cons_lock, AcquireGreaterEqual, 1) - aie.dma_bd(%out_buff_0 : memref<1024xi32>, 0, 1024) + aie.dma_bd(%out_buff_0 : memref<1024xi32>) { len = 1024 : i32 } aie.use_lock(%out_prod_lock, Release, 1) aie.next_bd ^bb5 ^bb5: // pred: ^bb4 aie.use_lock(%out_cons_lock, AcquireGreaterEqual, 1) - aie.dma_bd(%out_buff_1 : memref<1024xi32>, 0, 1024) + aie.dma_bd(%out_buff_1 : memref<1024xi32>) { len = 1024 : i32 } aie.use_lock(%out_prod_lock, Release, 1) aie.next_bd ^bb4 ^bb6: // pred: ^bb3 diff --git a/test/lower-to-standard/lower_dma.mlir b/test/lower-to-standard/lower_dma.mlir index 9ea5d723d9..01caf2a953 100644 --- a/test/lower-to-standard/lower_dma.mlir +++ b/test/lower-to-standard/lower_dma.mlir @@ -41,7 +41,7 @@ module @example0 { %dmaSt0 = aie.dma_start(MM2S, 0, ^bd0, ^end) ^bd0: aie.use_lock(%l33_0, Acquire, 1) - aie.dma_bd(%buf33 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf33 : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%l33_0, Release, 0) aie.next_bd ^end ^end: @@ -52,7 +52,7 @@ module @example0 { %dmaSt = aie.dma_start(S2MM, 0, ^bd0, ^end) ^bd0: aie.use_lock(%l43_0, Acquire, 0) - aie.dma_bd(%buf43 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf43 : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%l43_0, Release, 1) aie.next_bd ^end ^end: diff --git a/test/merge-buffers/test_buffer_merge0.mlir b/test/merge-buffers/test_buffer_merge0.mlir index 75d154cf43..94c509bc0a 100644 --- a/test/merge-buffers/test_buffer_merge0.mlir +++ b/test/merge-buffers/test_buffer_merge0.mlir @@ -78,7 +78,7 @@ module @test_buffer_merge0 { %dmaSt = aie.dma_start(MM2S, 0, ^bd0, ^end) ^bd0: aie.use_lock(%l34_0, Acquire, 1) - aie.dma_bd(%buf34_0 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf34_0 : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%l34_0, Release, 0) aie.next_bd ^end ^end: @@ -89,7 +89,7 @@ module @test_buffer_merge0 { %dmaSt = aie.dma_start(S2MM, 0, ^bd0, ^end) ^bd0: aie.use_lock(%l32_0, Acquire, 0) - aie.dma_bd(%buf32_0 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf32_0 : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%l32_0, Release, 1) aie.next_bd ^end ^end: diff --git a/test/objectFifo-stateful-transform/AIE2_cyclostatic_dma.mlir b/test/objectFifo-stateful-transform/AIE2_cyclostatic_dma.mlir index 9585be1151..8389988e2a 100644 --- a/test/objectFifo-stateful-transform/AIE2_cyclostatic_dma.mlir +++ b/test/objectFifo-stateful-transform/AIE2_cyclostatic_dma.mlir @@ -50,12 +50,12 @@ // CHECK: %[[dma0:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb3) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 // CHECK: aie.use_lock(%[[CL]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[buf0_0]] : memref, 0, 1) +// CHECK: aie.dma_bd(%[[buf0_0]] : memref) {len = 1 : i32} // CHECK: aie.use_lock(%[[PL]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[CL]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[buf0_1:.*]] : memref, 0, 1) +// CHECK: aie.dma_bd(%[[buf0_1:.*]] : memref) {len = 1 : i32} // CHECK: aie.use_lock(%[[PL]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb3: // pred: ^bb0 @@ -65,17 +65,17 @@ // CHECK: %[[dma1:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb3 // CHECK: aie.use_lock(%[[C_PL]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[buf1_0:.*]] : memref, 0, 1) +// CHECK: aie.dma_bd(%[[buf1_0:.*]] : memref) {len = 1 : i32} // CHECK: aie.use_lock(%[[C_CL]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[C_PL]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[buf1_1]] : memref, 0, 1) +// CHECK: aie.dma_bd(%[[buf1_1]] : memref) {len = 1 : i32} // CHECK: aie.use_lock(%[[C_CL]], Release, 1) // CHECK: aie.next_bd ^bb3 // CHECK: ^bb3: // pred: ^bb2 // CHECK: aie.use_lock(%[[C_PL]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[buf1_2]] : memref, 0, 1) +// CHECK: aie.dma_bd(%[[buf1_2]] : memref) {len = 1 : i32} // CHECK: aie.use_lock(%[[C_CL]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb4: // pred: ^bb0 diff --git a/test/objectFifo-stateful-transform/AIE2_cyclostatic_l2.mlir b/test/objectFifo-stateful-transform/AIE2_cyclostatic_l2.mlir index 6c0198272a..580f714d6c 100644 --- a/test/objectFifo-stateful-transform/AIE2_cyclostatic_l2.mlir +++ b/test/objectFifo-stateful-transform/AIE2_cyclostatic_l2.mlir @@ -153,7 +153,7 @@ // the stream, then move on to bb2. // CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 // CHECK: aie.use_lock(%[[fifo0_cons_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[fifo0_buff_0]] : memref<1xi32>, 0, 1) +// CHECK: aie.dma_bd(%[[fifo0_buff_0]] : memref<1xi32>) {len = 1 : i32} // CHECK: aie.use_lock(%[[fifo0_prod_lock]], Release, 1) // CHECK: aie.next_bd ^bb2 @@ -161,7 +161,7 @@ // go back to bb1. Ping-pong. // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[fifo0_cons_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[fifo0_buff_1]] : memref<1xi32>, 0, 1) +// CHECK: aie.dma_bd(%[[fifo0_buff_1]] : memref<1xi32>) {len = 1 : i32} // CHECK: aie.use_lock(%[[fifo0_prod_lock]], Release, 1) // CHECK: aie.next_bd ^bb1 @@ -182,22 +182,22 @@ // things through the stream: // CHECK: ^bb1: // 2 preds: ^bb0, ^bb4 // CHECK: aie.use_lock(%[[fifo0_cons_prod_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[fifo0_cons_buff_0]] : memref<1xi32>, 0, 1) +// CHECK: aie.dma_bd(%[[fifo0_cons_buff_0]] : memref<1xi32>) {len = 1 : i32} // CHECK: aie.use_lock(%[[fifo0_cons_cons_lock]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[fifo0_cons_prod_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[fifo0_cons_buff_1]] : memref<1xi32>, 0, 1) +// CHECK: aie.dma_bd(%[[fifo0_cons_buff_1]] : memref<1xi32>) {len = 1 : i32} // CHECK: aie.use_lock(%[[fifo0_cons_cons_lock]], Release, 1) // CHECK: aie.next_bd ^bb3 // CHECK: ^bb3: // pred: ^bb2 // CHECK: aie.use_lock(%[[fifo0_cons_prod_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[fifo0_cons_buff_2]] : memref<1xi32>, 0, 1) +// CHECK: aie.dma_bd(%[[fifo0_cons_buff_2]] : memref<1xi32>) {len = 1 : i32} // CHECK: aie.use_lock(%[[fifo0_cons_cons_lock]], Release, 1) // CHECK: aie.next_bd ^bb4 // CHECK: ^bb4: // pred: ^bb3 // CHECK: aie.use_lock(%[[fifo0_cons_prod_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[fifo0_cons_buff_3]] : memref<1xi32>, 0, 1) +// CHECK: aie.dma_bd(%[[fifo0_cons_buff_3]] : memref<1xi32>) {len = 1 : i32} // CHECK: aie.use_lock(%[[fifo0_cons_cons_lock]], Release, 1) // CHECK: aie.next_bd ^bb1 @@ -206,22 +206,22 @@ // CHECK: %[[VAL_26:.*]] = aie.dma_start(MM2S, 0, ^bb6, ^bb10) // CHECK: ^bb6: // 2 preds: ^bb5, ^bb9 // CHECK: aie.use_lock(%[[fifo0_cons_cons_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[fifo0_cons_buff_0]] : memref<1xi32>, 0, 1) +// CHECK: aie.dma_bd(%[[fifo0_cons_buff_0]] : memref<1xi32>) {len = 1 : i32} // CHECK: aie.use_lock(%[[fifo0_cons_prod_lock]], Release, 1) // CHECK: aie.next_bd ^bb7 // CHECK: ^bb7: // pred: ^bb6 // CHECK: aie.use_lock(%[[fifo0_cons_cons_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[fifo0_cons_buff_1]] : memref<1xi32>, 0, 1) +// CHECK: aie.dma_bd(%[[fifo0_cons_buff_1]] : memref<1xi32>) {len = 1 : i32} // CHECK: aie.use_lock(%[[fifo0_cons_prod_lock]], Release, 1) // CHECK: aie.next_bd ^bb8 // CHECK: ^bb8: // pred: ^bb7 // CHECK: aie.use_lock(%[[fifo0_cons_cons_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[fifo0_cons_buff_2]] : memref<1xi32>, 0, 1) +// CHECK: aie.dma_bd(%[[fifo0_cons_buff_2]] : memref<1xi32>) {len = 1 : i32} // CHECK: aie.use_lock(%[[fifo0_cons_prod_lock]], Release, 1) // CHECK: aie.next_bd ^bb9 // CHECK: ^bb9: // pred: ^bb8 // CHECK: aie.use_lock(%[[fifo0_cons_cons_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[fifo0_cons_buff_3]] : memref<1xi32>, 0, 1) +// CHECK: aie.dma_bd(%[[fifo0_cons_buff_3]] : memref<1xi32>) {len = 1 : i32} // CHECK: aie.use_lock(%[[fifo0_cons_prod_lock]], Release, 1) // CHECK: aie.next_bd ^bb6 // CHECK: ^bb10: // pred: ^bb5 @@ -242,22 +242,22 @@ // CHECK: %[[dma2:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb5) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb4 // CHECK: aie.use_lock(%[[fifo1_cons_prod_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[fifo1_cons_buff_0]] : memref<1xi32>, 0, 1) +// CHECK: aie.dma_bd(%[[fifo1_cons_buff_0]] : memref<1xi32>) {len = 1 : i32} // CHECK: aie.use_lock(%[[fifo1_cons_cons_lock]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[fifo1_cons_prod_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[fifo1_cons_buff_1]] : memref<1xi32>, 0, 1) +// CHECK: aie.dma_bd(%[[fifo1_cons_buff_1]] : memref<1xi32>) {len = 1 : i32} // CHECK: aie.use_lock(%[[fifo1_cons_cons_lock]], Release, 1) // CHECK: aie.next_bd ^bb3 // CHECK: ^bb3: // pred: ^bb2 // CHECK: aie.use_lock(%[[fifo1_cons_prod_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[fifo1_cons_buff_2]] : memref<1xi32>, 0, 1) +// CHECK: aie.dma_bd(%[[fifo1_cons_buff_2]] : memref<1xi32>) {len = 1 : i32} // CHECK: aie.use_lock(%[[fifo1_cons_cons_lock]], Release, 1) // CHECK: aie.next_bd ^bb4 // CHECK: ^bb4: // pred: ^bb3 // CHECK: aie.use_lock(%[[fifo1_cons_prod_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[fifo1_cons_buff_3]] : memref<1xi32>, 0, 1) +// CHECK: aie.dma_bd(%[[fifo1_cons_buff_3]] : memref<1xi32>) {len = 1 : i32} // CHECK: aie.use_lock(%[[fifo1_cons_cons_lock]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb5: // pred: ^bb0 diff --git a/test/objectFifo-stateful-transform/AIE2_dynamic_locks.mlir b/test/objectFifo-stateful-transform/AIE2_dynamic_locks.mlir index 8d08bad92f..def4b4094b 100644 --- a/test/objectFifo-stateful-transform/AIE2_dynamic_locks.mlir +++ b/test/objectFifo-stateful-transform/AIE2_dynamic_locks.mlir @@ -137,7 +137,7 @@ // CHECK: %11 = aie.dma_start(MM2S, 0, ^bb1, ^bb2) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb1 // CHECK: aie.use_lock(%[[fifo_cons_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[fifo_buff_0]] : memref, 0, 1) +// CHECK: aie.dma_bd(%[[fifo_buff_0]] : memref) {len = 1 : i32} // CHECK: aie.use_lock(%[[fifo_prod_lock]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb2: // pred: ^bb0 @@ -147,7 +147,7 @@ // CHECK: %11 = aie.dma_start(S2MM, 0, ^bb1, ^bb2) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb1 // CHECK: aie.use_lock(%[[fifo_cons_prod_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[fifo_cons_buff_0]] : memref, 0, 1) +// CHECK: aie.dma_bd(%[[fifo_cons_buff_0]] : memref) {len = 1 : i32} // CHECK: aie.use_lock(%[[fifo_cons_cons_lock]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb2: // pred: ^bb0 diff --git a/test/objectFifo-stateful-transform/base_test_AIE1.mlir b/test/objectFifo-stateful-transform/base_test_AIE1.mlir index f41513a72e..8171b48b25 100644 --- a/test/objectFifo-stateful-transform/base_test_AIE1.mlir +++ b/test/objectFifo-stateful-transform/base_test_AIE1.mlir @@ -39,12 +39,12 @@ // CHECK: aie.dma_start(MM2S, 0, ^bb1, ^bb3) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 // CHECK: aie.use_lock(%[[VAL_9]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_7]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_7]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_9]], Release, 0) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[VAL_10]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_8]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_8]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_10]], Release, 0) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb3: // pred: ^bb0 @@ -54,12 +54,12 @@ // CHECK: aie.dma_start(S2MM, 0, ^bb1, ^bb3) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 // CHECK: aie.use_lock(%[[VAL_5]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_3]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_3]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_5]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[VAL_6]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_4]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_4]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_6]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb3: // pred: ^bb0 diff --git a/test/objectFifo-stateful-transform/base_test_AIE2.mlir b/test/objectFifo-stateful-transform/base_test_AIE2.mlir index 6bae85d560..438ecec8dc 100644 --- a/test/objectFifo-stateful-transform/base_test_AIE2.mlir +++ b/test/objectFifo-stateful-transform/base_test_AIE2.mlir @@ -37,12 +37,12 @@ // CHECK: aie.dma_start(MM2S, 0, ^bb1, ^bb3) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 // CHECK: aie.use_lock(%[[VAL_10]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_7]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_7]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_9]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[VAL_10]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_8]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_8]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_9]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb3: // pred: ^bb0 @@ -52,12 +52,12 @@ // CHECK: aie.dma_start(S2MM, 0, ^bb1, ^bb3) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 // CHECK: aie.use_lock(%[[VAL_5]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_3]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_3]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_6]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[VAL_5]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_4]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_4]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_6]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb3: // pred: ^bb0 diff --git a/test/objectFifo-stateful-transform/broadcast_test.mlir b/test/objectFifo-stateful-transform/broadcast_test.mlir index 251cff9e8e..fe1f338500 100644 --- a/test/objectFifo-stateful-transform/broadcast_test.mlir +++ b/test/objectFifo-stateful-transform/broadcast_test.mlir @@ -173,12 +173,12 @@ // CHECK: %[[VAL_65:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb3) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 // CHECK: aie.use_lock(%[[VAL_31]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_29]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_29]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_31]], Release, 0) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[VAL_32]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_30]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_30]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_32]], Release, 0) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb3: // pred: ^bb0 @@ -188,12 +188,12 @@ // CHECK: %[[VAL_67:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 // CHECK: aie.use_lock(%[[VAL_7]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_5]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_5]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_7]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[VAL_8]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_6]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_6]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_8]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb3: // pred: ^bb0 @@ -203,17 +203,17 @@ // CHECK: %[[VAL_69:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb3 // CHECK: aie.use_lock(%[[VAL_12]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_9]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_9]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_12]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[VAL_13]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_10]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_10]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_13]], Release, 1) // CHECK: aie.next_bd ^bb3 // CHECK: ^bb3: // pred: ^bb2 // CHECK: aie.use_lock(%[[VAL_14]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_11]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_11]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_14]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb4: // pred: ^bb0 @@ -223,22 +223,22 @@ // CHECK: %[[VAL_71:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb5) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb4 // CHECK: aie.use_lock(%[[VAL_19]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_15]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_15]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_19]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[VAL_20]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_16]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_16]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_20]], Release, 1) // CHECK: aie.next_bd ^bb3 // CHECK: ^bb3: // pred: ^bb2 // CHECK: aie.use_lock(%[[VAL_21]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_17]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_17]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_21]], Release, 1) // CHECK: aie.next_bd ^bb4 // CHECK: ^bb4: // pred: ^bb3 // CHECK: aie.use_lock(%[[VAL_22]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_18]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_18]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_22]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb5: // pred: ^bb0 @@ -248,17 +248,17 @@ // CHECK: %[[VAL_73:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb3 // CHECK: aie.use_lock(%[[VAL_26]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_23]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_23]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_26]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[VAL_27]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_24]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_24]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_27]], Release, 1) // CHECK: aie.next_bd ^bb3 // CHECK: ^bb3: // pred: ^bb2 // CHECK: aie.use_lock(%[[VAL_28]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_25]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_25]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_28]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb4: // pred: ^bb0 diff --git a/test/objectFifo-stateful-transform/link_test_AIE1.mlir b/test/objectFifo-stateful-transform/link_test_AIE1.mlir index 579060f303..6e8257b49e 100644 --- a/test/objectFifo-stateful-transform/link_test_AIE1.mlir +++ b/test/objectFifo-stateful-transform/link_test_AIE1.mlir @@ -37,7 +37,7 @@ // CHECK: %[[VAL_14:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb2) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb1 // CHECK: aie.use_lock(%[[VAL_11]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_12]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_12]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_11]], Release, 0) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb2: // pred: ^bb0 @@ -47,24 +47,24 @@ // CHECK: %[[VAL_16:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 // CHECK: aie.use_lock(%[[VAL_9]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_7]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_7]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_9]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[VAL_10]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_8]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_8]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_10]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb3: // pred: ^bb0 // CHECK: %[[VAL_17:.*]] = aie.dma_start(MM2S, 0, ^bb4, ^bb6) // CHECK: ^bb4: // 2 preds: ^bb3, ^bb5 // CHECK: aie.use_lock(%[[VAL_9]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_7]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_7]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_9]], Release, 0) // CHECK: aie.next_bd ^bb5 // CHECK: ^bb5: // pred: ^bb4 // CHECK: aie.use_lock(%[[VAL_10]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_8]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_8]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_10]], Release, 0) // CHECK: aie.next_bd ^bb4 // CHECK: ^bb6: // pred: ^bb3 @@ -74,12 +74,12 @@ // CHECK: %[[VAL_19:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 // CHECK: aie.use_lock(%[[VAL_5]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_3]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_3]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_5]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[VAL_6]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_4]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_4]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_6]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb3: // pred: ^bb0 diff --git a/test/objectFifo-stateful-transform/link_test_AIE2.mlir b/test/objectFifo-stateful-transform/link_test_AIE2.mlir index 2c3f32a436..7b7928dc2f 100644 --- a/test/objectFifo-stateful-transform/link_test_AIE2.mlir +++ b/test/objectFifo-stateful-transform/link_test_AIE2.mlir @@ -65,12 +65,12 @@ // CHECK: %[[VAL_32:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 // CHECK: aie.use_lock(%[[VAL_12]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_10]] : memref<3000xi32>, 0, 3000) +// CHECK: aie.dma_bd(%[[VAL_10]] : memref<3000xi32>) {len = 3000 : i32} // CHECK: aie.use_lock(%[[VAL_13]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[VAL_12]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_11]] : memref<3000xi32>, 0, 3000) +// CHECK: aie.dma_bd(%[[VAL_11]] : memref<3000xi32>) {len = 3000 : i32} // CHECK: aie.use_lock(%[[VAL_13]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb3: // pred: ^bb0 @@ -80,74 +80,74 @@ // CHECK: %[[VAL_34:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb8) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb7 // CHECK: aie.use_lock(%[[VAL_21]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_14]] : memref<3000xi32>, 0, 3000) +// CHECK: aie.dma_bd(%[[VAL_14]] : memref<3000xi32>) {len = 3000 : i32} // CHECK: aie.use_lock(%[[VAL_22]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[VAL_21]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_15]] : memref<3000xi32>, 0, 3000) +// CHECK: aie.dma_bd(%[[VAL_15]] : memref<3000xi32>) {len = 3000 : i32} // CHECK: aie.use_lock(%[[VAL_22]], Release, 1) // CHECK: aie.next_bd ^bb3 // CHECK: ^bb3: // pred: ^bb2 // CHECK: aie.use_lock(%[[VAL_21]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_16]] : memref<3000xi32>, 0, 3000) +// CHECK: aie.dma_bd(%[[VAL_16]] : memref<3000xi32>) {len = 3000 : i32} // CHECK: aie.use_lock(%[[VAL_22]], Release, 1) // CHECK: aie.next_bd ^bb4 // CHECK: ^bb4: // pred: ^bb3 // CHECK: aie.use_lock(%[[VAL_21]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_17]] : memref<3000xi32>, 0, 3000) +// CHECK: aie.dma_bd(%[[VAL_17]] : memref<3000xi32>) {len = 3000 : i32} // CHECK: aie.use_lock(%[[VAL_22]], Release, 1) // CHECK: aie.next_bd ^bb5 // CHECK: ^bb5: // pred: ^bb4 // CHECK: aie.use_lock(%[[VAL_21]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_18]] : memref<3000xi32>, 0, 3000) +// CHECK: aie.dma_bd(%[[VAL_18]] : memref<3000xi32>) {len = 3000 : i32} // CHECK: aie.use_lock(%[[VAL_22]], Release, 1) // CHECK: aie.next_bd ^bb6 // CHECK: ^bb6: // pred: ^bb5 // CHECK: aie.use_lock(%[[VAL_21]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_19]] : memref<3000xi32>, 0, 3000) +// CHECK: aie.dma_bd(%[[VAL_19]] : memref<3000xi32>) {len = 3000 : i32} // CHECK: aie.use_lock(%[[VAL_22]], Release, 1) // CHECK: aie.next_bd ^bb7 // CHECK: ^bb7: // pred: ^bb6 // CHECK: aie.use_lock(%[[VAL_21]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_20]] : memref<3000xi32>, 0, 3000) +// CHECK: aie.dma_bd(%[[VAL_20]] : memref<3000xi32>) {len = 3000 : i32} // CHECK: aie.use_lock(%[[VAL_22]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb8: // pred: ^bb0 // CHECK: %[[VAL_35:.*]] = aie.dma_start(MM2S, 0, ^bb9, ^bb16) // CHECK: ^bb9: // 2 preds: ^bb8, ^bb15 // CHECK: aie.use_lock(%[[VAL_22]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_14]] : memref<3000xi32>, 0, 3000) +// CHECK: aie.dma_bd(%[[VAL_14]] : memref<3000xi32>) {len = 3000 : i32} // CHECK: aie.use_lock(%[[VAL_21]], Release, 1) // CHECK: aie.next_bd ^bb10 // CHECK: ^bb10: // pred: ^bb9 // CHECK: aie.use_lock(%[[VAL_22]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_15]] : memref<3000xi32>, 0, 3000) +// CHECK: aie.dma_bd(%[[VAL_15]] : memref<3000xi32>) {len = 3000 : i32} // CHECK: aie.use_lock(%[[VAL_21]], Release, 1) // CHECK: aie.next_bd ^bb11 // CHECK: ^bb11: // pred: ^bb10 // CHECK: aie.use_lock(%[[VAL_22]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_16]] : memref<3000xi32>, 0, 3000) +// CHECK: aie.dma_bd(%[[VAL_16]] : memref<3000xi32>) {len = 3000 : i32} // CHECK: aie.use_lock(%[[VAL_21]], Release, 1) // CHECK: aie.next_bd ^bb12 // CHECK: ^bb12: // pred: ^bb11 // CHECK: aie.use_lock(%[[VAL_22]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_17]] : memref<3000xi32>, 0, 3000) +// CHECK: aie.dma_bd(%[[VAL_17]] : memref<3000xi32>) {len = 3000 : i32} // CHECK: aie.use_lock(%[[VAL_21]], Release, 1) // CHECK: aie.next_bd ^bb13 // CHECK: ^bb13: // pred: ^bb12 // CHECK: aie.use_lock(%[[VAL_22]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_18]] : memref<3000xi32>, 0, 3000) +// CHECK: aie.dma_bd(%[[VAL_18]] : memref<3000xi32>) {len = 3000 : i32} // CHECK: aie.use_lock(%[[VAL_21]], Release, 1) // CHECK: aie.next_bd ^bb14 // CHECK: ^bb14: // pred: ^bb13 // CHECK: aie.use_lock(%[[VAL_22]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_19]] : memref<3000xi32>, 0, 3000) +// CHECK: aie.dma_bd(%[[VAL_19]] : memref<3000xi32>) {len = 3000 : i32} // CHECK: aie.use_lock(%[[VAL_21]], Release, 1) // CHECK: aie.next_bd ^bb15 // CHECK: ^bb15: // pred: ^bb14 // CHECK: aie.use_lock(%[[VAL_22]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_20]] : memref<3000xi32>, 0, 3000) +// CHECK: aie.dma_bd(%[[VAL_20]] : memref<3000xi32>) {len = 3000 : i32} // CHECK: aie.use_lock(%[[VAL_21]], Release, 1) // CHECK: aie.next_bd ^bb9 // CHECK: ^bb16: // pred: ^bb8 @@ -157,22 +157,22 @@ // CHECK: %[[VAL_37:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb5) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb4 // CHECK: aie.use_lock(%[[VAL_8]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_4]] : memref<3000xi32>, 0, 3000) +// CHECK: aie.dma_bd(%[[VAL_4]] : memref<3000xi32>) {len = 3000 : i32} // CHECK: aie.use_lock(%[[VAL_9]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[VAL_8]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_5]] : memref<3000xi32>, 0, 3000) +// CHECK: aie.dma_bd(%[[VAL_5]] : memref<3000xi32>) {len = 3000 : i32} // CHECK: aie.use_lock(%[[VAL_9]], Release, 1) // CHECK: aie.next_bd ^bb3 // CHECK: ^bb3: // pred: ^bb2 // CHECK: aie.use_lock(%[[VAL_8]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_6]] : memref<3000xi32>, 0, 3000) +// CHECK: aie.dma_bd(%[[VAL_6]] : memref<3000xi32>) {len = 3000 : i32} // CHECK: aie.use_lock(%[[VAL_9]], Release, 1) // CHECK: aie.next_bd ^bb4 // CHECK: ^bb4: // pred: ^bb3 // CHECK: aie.use_lock(%[[VAL_8]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_7]] : memref<3000xi32>, 0, 3000) +// CHECK: aie.dma_bd(%[[VAL_7]] : memref<3000xi32>) {len = 3000 : i32} // CHECK: aie.use_lock(%[[VAL_9]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb5: // pred: ^bb0 diff --git a/test/objectFifo-stateful-transform/link_test_DDR_to_L1.mlir b/test/objectFifo-stateful-transform/link_test_DDR_to_L1.mlir index 67c70fe591..0ff03a2009 100644 --- a/test/objectFifo-stateful-transform/link_test_DDR_to_L1.mlir +++ b/test/objectFifo-stateful-transform/link_test_DDR_to_L1.mlir @@ -38,7 +38,7 @@ // CHECK: %[[VAL_15:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb2) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb1 // CHECK: aie.use_lock(%[[VAL_12]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_13]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_13]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_11]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb2: // pred: ^bb0 @@ -48,24 +48,24 @@ // CHECK: %[[VAL_17:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 // CHECK: aie.use_lock(%[[VAL_9]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_7]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_7]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_10]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[VAL_9]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_8]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_8]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_10]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb3: // pred: ^bb0 // CHECK: %[[VAL_18:.*]] = aie.dma_start(MM2S, 0, ^bb4, ^bb6) // CHECK: ^bb4: // 2 preds: ^bb3, ^bb5 // CHECK: aie.use_lock(%[[VAL_10]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_7]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_7]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_9]], Release, 1) // CHECK: aie.next_bd ^bb5 // CHECK: ^bb5: // pred: ^bb4 // CHECK: aie.use_lock(%[[VAL_10]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_8]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_8]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_9]], Release, 1) // CHECK: aie.next_bd ^bb4 // CHECK: ^bb6: // pred: ^bb3 @@ -75,12 +75,12 @@ // CHECK: %[[VAL_20:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 // CHECK: aie.use_lock(%[[VAL_5]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_3]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_3]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_6]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[VAL_5]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_4]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_4]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_6]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb3: // pred: ^bb0 diff --git a/test/objectFifo-stateful-transform/link_test_L1_to_DDR.mlir b/test/objectFifo-stateful-transform/link_test_L1_to_DDR.mlir index 70d539fbd5..7f06432f66 100644 --- a/test/objectFifo-stateful-transform/link_test_L1_to_DDR.mlir +++ b/test/objectFifo-stateful-transform/link_test_L1_to_DDR.mlir @@ -37,12 +37,12 @@ // CHECK: %[[VAL_15:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb3) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 // CHECK: aie.use_lock(%[[VAL_12]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_9]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_9]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_11]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[VAL_12]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_10]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_10]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_11]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb3: // pred: ^bb0 @@ -52,24 +52,24 @@ // CHECK: %[[VAL_17:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 // CHECK: aie.use_lock(%[[VAL_7]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_5]] : memref<48xi32>, 0, 48) +// CHECK: aie.dma_bd(%[[VAL_5]] : memref<48xi32>) {len = 48 : i32} // CHECK: aie.use_lock(%[[VAL_8]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[VAL_7]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_6]] : memref<48xi32>, 0, 48) +// CHECK: aie.dma_bd(%[[VAL_6]] : memref<48xi32>) {len = 48 : i32} // CHECK: aie.use_lock(%[[VAL_8]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb3: // pred: ^bb0 // CHECK: %[[VAL_18:.*]] = aie.dma_start(MM2S, 0, ^bb4, ^bb6) // CHECK: ^bb4: // 2 preds: ^bb3, ^bb5 // CHECK: aie.use_lock(%[[VAL_8]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_5]] : memref<48xi32>, 0, 48) +// CHECK: aie.dma_bd(%[[VAL_5]] : memref<48xi32>) {len = 48 : i32} // CHECK: aie.use_lock(%[[VAL_7]], Release, 1) // CHECK: aie.next_bd ^bb5 // CHECK: ^bb5: // pred: ^bb4 // CHECK: aie.use_lock(%[[VAL_8]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_6]] : memref<48xi32>, 0, 48) +// CHECK: aie.dma_bd(%[[VAL_6]] : memref<48xi32>) {len = 48 : i32} // CHECK: aie.use_lock(%[[VAL_7]], Release, 1) // CHECK: aie.next_bd ^bb4 // CHECK: ^bb6: // pred: ^bb3 @@ -80,7 +80,7 @@ // CHECK: %[[VAL_20:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb2) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb1 // CHECK: aie.use_lock(%[[VAL_3]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_13]] : memref<48xi32>, 0, 48) +// CHECK: aie.dma_bd(%[[VAL_13]] : memref<48xi32>) {len = 48 : i32} // CHECK: aie.use_lock(%[[VAL_4]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb2: // pred: ^bb0 diff --git a/test/objectFifo-stateful-transform/link_test_broadcast.mlir b/test/objectFifo-stateful-transform/link_test_broadcast.mlir index 6a8a5b6cc6..26ad6f2c06 100644 --- a/test/objectFifo-stateful-transform/link_test_broadcast.mlir +++ b/test/objectFifo-stateful-transform/link_test_broadcast.mlir @@ -56,24 +56,24 @@ // CHECK: %[[VAL_28:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 // CHECK: aie.use_lock(%[[VAL_23]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_21]] : memref<48xi32>, 0, 48) +// CHECK: aie.dma_bd(%[[VAL_21]] : memref<48xi32>) {len = 48 : i32} // CHECK: aie.use_lock(%[[VAL_24]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[VAL_23]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_22]] : memref<48xi32>, 0, 48) +// CHECK: aie.dma_bd(%[[VAL_22]] : memref<48xi32>) {len = 48 : i32} // CHECK: aie.use_lock(%[[VAL_24]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb3: // pred: ^bb0 // CHECK: %[[VAL_29:.*]] = aie.dma_start(MM2S, 0, ^bb4, ^bb6) // CHECK: ^bb4: // 2 preds: ^bb3, ^bb5 // CHECK: aie.use_lock(%[[VAL_24]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_21]] : memref<48xi32>, 0, 48) +// CHECK: aie.dma_bd(%[[VAL_21]] : memref<48xi32>) {len = 48 : i32} // CHECK: aie.use_lock(%[[VAL_23]], Release, 1) // CHECK: aie.next_bd ^bb5 // CHECK: ^bb5: // pred: ^bb4 // CHECK: aie.use_lock(%[[VAL_24]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_22]] : memref<48xi32>, 0, 48) +// CHECK: aie.dma_bd(%[[VAL_22]] : memref<48xi32>) {len = 48 : i32} // CHECK: aie.use_lock(%[[VAL_23]], Release, 1) // CHECK: aie.next_bd ^bb4 // CHECK: ^bb6: // pred: ^bb3 @@ -83,24 +83,24 @@ // CHECK: %[[VAL_31:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 // CHECK: aie.use_lock(%[[VAL_14]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_12]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_12]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_15]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[VAL_14]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_13]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_13]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_15]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb3: // pred: ^bb0 // CHECK: %[[VAL_32:.*]] = aie.dma_start(MM2S, 0, ^bb4, ^bb6) // CHECK: ^bb4: // 2 preds: ^bb3, ^bb5 // CHECK: aie.use_lock(%[[VAL_11]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_8]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_8]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_10]], Release, 1) // CHECK: aie.next_bd ^bb5 // CHECK: ^bb5: // pred: ^bb4 // CHECK: aie.use_lock(%[[VAL_11]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_9]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_9]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_10]], Release, 1) // CHECK: aie.next_bd ^bb4 // CHECK: ^bb6: // pred: ^bb3 @@ -110,29 +110,29 @@ // CHECK: %[[VAL_34:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb3 // CHECK: aie.use_lock(%[[VAL_19]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_16]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_16]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_20]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[VAL_19]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_17]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_17]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_20]], Release, 1) // CHECK: aie.next_bd ^bb3 // CHECK: ^bb3: // pred: ^bb2 // CHECK: aie.use_lock(%[[VAL_19]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_18]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_18]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_20]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb4: // pred: ^bb0 // CHECK: %[[VAL_35:.*]] = aie.dma_start(S2MM, 1, ^bb5, ^bb7) // CHECK: ^bb5: // 2 preds: ^bb4, ^bb6 // CHECK: aie.use_lock(%[[VAL_6]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_4]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_4]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_7]], Release, 1) // CHECK: aie.next_bd ^bb6 // CHECK: ^bb6: // pred: ^bb5 // CHECK: aie.use_lock(%[[VAL_6]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_5]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_5]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_7]], Release, 1) // CHECK: aie.next_bd ^bb5 // CHECK: ^bb7: // pred: ^bb4 diff --git a/test/objectFifo-stateful-transform/link_test_distribute.mlir b/test/objectFifo-stateful-transform/link_test_distribute.mlir index c95d8b6e10..8ca8e53274 100644 --- a/test/objectFifo-stateful-transform/link_test_distribute.mlir +++ b/test/objectFifo-stateful-transform/link_test_distribute.mlir @@ -54,7 +54,7 @@ // CHECK: %[[VAL_25:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb2) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb1 // CHECK: aie.use_lock(%[[VAL_22]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_23]] : memref<48xi32>, 0, 48) +// CHECK: aie.dma_bd(%[[VAL_23]] : memref<48xi32>) {len = 48 : i32} // CHECK: aie.use_lock(%[[VAL_21]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb2: // pred: ^bb0 @@ -64,48 +64,48 @@ // CHECK: %[[VAL_27:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 // CHECK: aie.use_lock(%[[VAL_19]], AcquireGreaterEqual, 3) -// CHECK: aie.dma_bd(%[[VAL_17]] : memref<48xi32>, 0, 48) +// CHECK: aie.dma_bd(%[[VAL_17]] : memref<48xi32>) {len = 48 : i32} // CHECK: aie.use_lock(%[[VAL_20]], Release, 3) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[VAL_19]], AcquireGreaterEqual, 3) -// CHECK: aie.dma_bd(%[[VAL_18]] : memref<48xi32>, 0, 48) +// CHECK: aie.dma_bd(%[[VAL_18]] : memref<48xi32>) {len = 48 : i32} // CHECK: aie.use_lock(%[[VAL_20]], Release, 3) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb3: // pred: ^bb0 // CHECK: %[[VAL_28:.*]] = aie.dma_start(MM2S, 0, ^bb4, ^bb6) // CHECK: ^bb4: // 2 preds: ^bb3, ^bb5 // CHECK: aie.use_lock(%[[VAL_20]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_17]] : memref<48xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_17]] : memref<48xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_19]], Release, 1) // CHECK: aie.next_bd ^bb5 // CHECK: ^bb5: // pred: ^bb4 // CHECK: aie.use_lock(%[[VAL_20]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_18]] : memref<48xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_18]] : memref<48xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_19]], Release, 1) // CHECK: aie.next_bd ^bb4 // CHECK: ^bb6: // pred: ^bb3 // CHECK: %[[VAL_29:.*]] = aie.dma_start(MM2S, 1, ^bb7, ^bb9) // CHECK: ^bb7: // 2 preds: ^bb6, ^bb8 // CHECK: aie.use_lock(%[[VAL_20]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_17]] : memref<48xi32>, 64, 20) +// CHECK: aie.dma_bd(%[[VAL_17]] : memref<48xi32>) {len = 20 : i32, offset = 16 : i32} // CHECK: aie.use_lock(%[[VAL_19]], Release, 1) // CHECK: aie.next_bd ^bb8 // CHECK: ^bb8: // pred: ^bb7 // CHECK: aie.use_lock(%[[VAL_20]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_18]] : memref<48xi32>, 64, 20) +// CHECK: aie.dma_bd(%[[VAL_18]] : memref<48xi32>) {len = 20 : i32, offset = 16 : i32} // CHECK: aie.use_lock(%[[VAL_19]], Release, 1) // CHECK: aie.next_bd ^bb7 // CHECK: ^bb9: // pred: ^bb6 // CHECK: %[[VAL_30:.*]] = aie.dma_start(MM2S, 2, ^bb10, ^bb12) // CHECK: ^bb10: // 2 preds: ^bb9, ^bb11 // CHECK: aie.use_lock(%[[VAL_20]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_17]] : memref<48xi32>, 144, 12) +// CHECK: aie.dma_bd(%[[VAL_17]] : memref<48xi32>) {len = 12 : i32, offset = 36 : i32} // CHECK: aie.use_lock(%[[VAL_19]], Release, 1) // CHECK: aie.next_bd ^bb11 // CHECK: ^bb11: // pred: ^bb10 // CHECK: aie.use_lock(%[[VAL_20]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_18]] : memref<48xi32>, 144, 12) +// CHECK: aie.dma_bd(%[[VAL_18]] : memref<48xi32>) {len = 12 : i32, offset = 36 : i32} // CHECK: aie.use_lock(%[[VAL_19]], Release, 1) // CHECK: aie.next_bd ^bb10 // CHECK: ^bb12: // pred: ^bb9 @@ -115,12 +115,12 @@ // CHECK: %[[VAL_32:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 // CHECK: aie.use_lock(%[[VAL_15]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_13]] : memref<4x4xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_13]] : memref<4x4xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_16]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[VAL_15]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_14]] : memref<4x4xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_14]] : memref<4x4xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_16]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb3: // pred: ^bb0 @@ -130,12 +130,12 @@ // CHECK: %[[VAL_34:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 // CHECK: aie.use_lock(%[[VAL_11]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_9]] : memref<20xi32>, 0, 20) +// CHECK: aie.dma_bd(%[[VAL_9]] : memref<20xi32>) {len = 20 : i32} // CHECK: aie.use_lock(%[[VAL_12]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[VAL_11]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_10]] : memref<20xi32>, 0, 20) +// CHECK: aie.dma_bd(%[[VAL_10]] : memref<20xi32>) {len = 20 : i32} // CHECK: aie.use_lock(%[[VAL_12]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb3: // pred: ^bb0 @@ -145,12 +145,12 @@ // CHECK: %[[VAL_36:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 // CHECK: aie.use_lock(%[[VAL_7]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_5]] : memref<12xi32>, 0, 12) +// CHECK: aie.dma_bd(%[[VAL_5]] : memref<12xi32>) {len = 12 : i32} // CHECK: aie.use_lock(%[[VAL_8]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[VAL_7]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_6]] : memref<12xi32>, 0, 12) +// CHECK: aie.dma_bd(%[[VAL_6]] : memref<12xi32>) {len = 12 : i32} // CHECK: aie.use_lock(%[[VAL_8]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb3: // pred: ^bb0 diff --git a/test/objectFifo-stateful-transform/link_test_join.mlir b/test/objectFifo-stateful-transform/link_test_join.mlir index be54b1630c..6e1b8aa103 100644 --- a/test/objectFifo-stateful-transform/link_test_join.mlir +++ b/test/objectFifo-stateful-transform/link_test_join.mlir @@ -61,12 +61,12 @@ // CHECK: %[[VAL_30:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb3) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 // CHECK: aie.use_lock(%[[VAL_27]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_24]] : memref<128xi8>, 0, 128) +// CHECK: aie.dma_bd(%[[VAL_24]] : memref<128xi8>) {len = 128 : i32} // CHECK: aie.use_lock(%[[VAL_26]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[VAL_27]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_25]] : memref<128xi8>, 0, 128) +// CHECK: aie.dma_bd(%[[VAL_25]] : memref<128xi8>) {len = 128 : i32} // CHECK: aie.use_lock(%[[VAL_26]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb3: // pred: ^bb0 @@ -76,60 +76,60 @@ // CHECK: %[[VAL_32:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 // CHECK: aie.use_lock(%[[VAL_10]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_8]] : memref<512xi8>, 0, 128) +// CHECK: aie.dma_bd(%[[VAL_8]] : memref<512xi8>) {len = 128 : i32} // CHECK: aie.use_lock(%[[VAL_11]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[VAL_10]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_9]] : memref<512xi8>, 0, 128) +// CHECK: aie.dma_bd(%[[VAL_9]] : memref<512xi8>) {len = 128 : i32} // CHECK: aie.use_lock(%[[VAL_11]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb3: // pred: ^bb0 // CHECK: %[[VAL_33:.*]] = aie.dma_start(S2MM, 1, ^bb4, ^bb6) // CHECK: ^bb4: // 2 preds: ^bb3, ^bb5 // CHECK: aie.use_lock(%[[VAL_10]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_8]] : memref<512xi8>, 128, 128) +// CHECK: aie.dma_bd(%[[VAL_8]] : memref<512xi8>) {len = 128 : i32, offset = 128 : i32} // CHECK: aie.use_lock(%[[VAL_11]], Release, 1) // CHECK: aie.next_bd ^bb5 // CHECK: ^bb5: // pred: ^bb4 // CHECK: aie.use_lock(%[[VAL_10]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_9]] : memref<512xi8>, 128, 128) +// CHECK: aie.dma_bd(%[[VAL_9]] : memref<512xi8>) {len = 128 : i32, offset = 128 : i32} // CHECK: aie.use_lock(%[[VAL_11]], Release, 1) // CHECK: aie.next_bd ^bb4 // CHECK: ^bb6: // pred: ^bb3 // CHECK: %[[VAL_34:.*]] = aie.dma_start(S2MM, 2, ^bb7, ^bb9) // CHECK: ^bb7: // 2 preds: ^bb6, ^bb8 // CHECK: aie.use_lock(%[[VAL_10]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_8]] : memref<512xi8>, 256, 128) +// CHECK: aie.dma_bd(%[[VAL_8]] : memref<512xi8>) {len = 128 : i32, offset = 256 : i32} // CHECK: aie.use_lock(%[[VAL_11]], Release, 1) // CHECK: aie.next_bd ^bb8 // CHECK: ^bb8: // pred: ^bb7 // CHECK: aie.use_lock(%[[VAL_10]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_9]] : memref<512xi8>, 256, 128) +// CHECK: aie.dma_bd(%[[VAL_9]] : memref<512xi8>) {len = 128 : i32, offset = 256 : i32} // CHECK: aie.use_lock(%[[VAL_11]], Release, 1) // CHECK: aie.next_bd ^bb7 // CHECK: ^bb9: // pred: ^bb6 // CHECK: %[[VAL_35:.*]] = aie.dma_start(S2MM, 3, ^bb10, ^bb12) // CHECK: ^bb10: // 2 preds: ^bb9, ^bb11 // CHECK: aie.use_lock(%[[VAL_10]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_8]] : memref<512xi8>, 384, 128) +// CHECK: aie.dma_bd(%[[VAL_8]] : memref<512xi8>) {len = 128 : i32, offset = 384 : i32} // CHECK: aie.use_lock(%[[VAL_11]], Release, 1) // CHECK: aie.next_bd ^bb11 // CHECK: ^bb11: // pred: ^bb10 // CHECK: aie.use_lock(%[[VAL_10]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_9]] : memref<512xi8>, 384, 128) +// CHECK: aie.dma_bd(%[[VAL_9]] : memref<512xi8>) {len = 128 : i32, offset = 384 : i32} // CHECK: aie.use_lock(%[[VAL_11]], Release, 1) // CHECK: aie.next_bd ^bb10 // CHECK: ^bb12: // pred: ^bb9 // CHECK: %[[VAL_36:.*]] = aie.dma_start(MM2S, 0, ^bb13, ^bb15) // CHECK: ^bb13: // 2 preds: ^bb12, ^bb14 // CHECK: aie.use_lock(%[[VAL_11]], AcquireGreaterEqual, 4) -// CHECK: aie.dma_bd(%[[VAL_8]] : memref<512xi8>, 0, 512) +// CHECK: aie.dma_bd(%[[VAL_8]] : memref<512xi8>) {len = 512 : i32} // CHECK: aie.use_lock(%[[VAL_10]], Release, 4) // CHECK: aie.next_bd ^bb14 // CHECK: ^bb14: // pred: ^bb13 // CHECK: aie.use_lock(%[[VAL_11]], AcquireGreaterEqual, 4) -// CHECK: aie.dma_bd(%[[VAL_9]] : memref<512xi8>, 0, 512) +// CHECK: aie.dma_bd(%[[VAL_9]] : memref<512xi8>) {len = 512 : i32} // CHECK: aie.use_lock(%[[VAL_10]], Release, 4) // CHECK: aie.next_bd ^bb13 // CHECK: ^bb15: // pred: ^bb12 @@ -139,12 +139,12 @@ // CHECK: %[[VAL_38:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb3) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 // CHECK: aie.use_lock(%[[VAL_23]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_20]] : memref<128xi8>, 0, 128) +// CHECK: aie.dma_bd(%[[VAL_20]] : memref<128xi8>) {len = 128 : i32} // CHECK: aie.use_lock(%[[VAL_22]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[VAL_23]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_21]] : memref<128xi8>, 0, 128) +// CHECK: aie.dma_bd(%[[VAL_21]] : memref<128xi8>) {len = 128 : i32} // CHECK: aie.use_lock(%[[VAL_22]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb3: // pred: ^bb0 @@ -154,12 +154,12 @@ // CHECK: %[[VAL_40:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb3) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 // CHECK: aie.use_lock(%[[VAL_19]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_16]] : memref<128xi8>, 0, 128) +// CHECK: aie.dma_bd(%[[VAL_16]] : memref<128xi8>) {len = 128 : i32} // CHECK: aie.use_lock(%[[VAL_18]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[VAL_19]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_17]] : memref<128xi8>, 0, 128) +// CHECK: aie.dma_bd(%[[VAL_17]] : memref<128xi8>) {len = 128 : i32} // CHECK: aie.use_lock(%[[VAL_18]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb3: // pred: ^bb0 @@ -169,12 +169,12 @@ // CHECK: %[[VAL_42:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb3) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 // CHECK: aie.use_lock(%[[VAL_15]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_12]] : memref<128xi8>, 0, 128) +// CHECK: aie.dma_bd(%[[VAL_12]] : memref<128xi8>) {len = 128 : i32} // CHECK: aie.use_lock(%[[VAL_14]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[VAL_15]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_13]] : memref<128xi8>, 0, 128) +// CHECK: aie.dma_bd(%[[VAL_13]] : memref<128xi8>) {len = 128 : i32} // CHECK: aie.use_lock(%[[VAL_14]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb3: // pred: ^bb0 @@ -185,7 +185,7 @@ // CHECK: %[[VAL_44:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb2) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb1 // CHECK: aie.use_lock(%[[VAL_6]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_28]] : memref<512xi8>, 0, 512) +// CHECK: aie.dma_bd(%[[VAL_28]] : memref<512xi8>) {len = 512 : i32} // CHECK: aie.use_lock(%[[VAL_7]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb2: // pred: ^bb0 diff --git a/test/objectFifo-stateful-transform/matmul_test.mlir b/test/objectFifo-stateful-transform/matmul_test.mlir index 292c438220..ff9217ebb0 100644 --- a/test/objectFifo-stateful-transform/matmul_test.mlir +++ b/test/objectFifo-stateful-transform/matmul_test.mlir @@ -89,36 +89,36 @@ // CHECK: %[[VAL_37:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 // CHECK: aie.use_lock(%[[VAL_16]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_14]] : memref<16x8xi16>, 0, 128) +// CHECK: aie.dma_bd(%[[VAL_14]] : memref<16x8xi16>) {len = 128 : i32} // CHECK: aie.use_lock(%[[VAL_17]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[VAL_16]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_15]] : memref<16x8xi16>, 0, 128) +// CHECK: aie.dma_bd(%[[VAL_15]] : memref<16x8xi16>) {len = 128 : i32} // CHECK: aie.use_lock(%[[VAL_17]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb3: // pred: ^bb0 // CHECK: %[[VAL_38:.*]] = aie.dma_start(S2MM, 1, ^bb4, ^bb6) // CHECK: ^bb4: // 2 preds: ^bb3, ^bb5 // CHECK: aie.use_lock(%[[VAL_10]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_8]] : memref<8x16xi16>, 0, 128) +// CHECK: aie.dma_bd(%[[VAL_8]] : memref<8x16xi16>) {len = 128 : i32} // CHECK: aie.use_lock(%[[VAL_11]], Release, 1) // CHECK: aie.next_bd ^bb5 // CHECK: ^bb5: // pred: ^bb4 // CHECK: aie.use_lock(%[[VAL_10]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_9]] : memref<8x16xi16>, 0, 128) +// CHECK: aie.dma_bd(%[[VAL_9]] : memref<8x16xi16>) {len = 128 : i32} // CHECK: aie.use_lock(%[[VAL_11]], Release, 1) // CHECK: aie.next_bd ^bb4 // CHECK: ^bb6: // pred: ^bb3 // CHECK: %[[VAL_39:.*]] = aie.dma_start(MM2S, 0, ^bb7, ^bb9) // CHECK: ^bb7: // 2 preds: ^bb6, ^bb8 // CHECK: aie.use_lock(%[[VAL_7]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_4]] : memref<16x16xi16>, 0, 256) +// CHECK: aie.dma_bd(%[[VAL_4]] : memref<16x16xi16>) {len = 256 : i32} // CHECK: aie.use_lock(%[[VAL_6]], Release, 1) // CHECK: aie.next_bd ^bb8 // CHECK: ^bb8: // pred: ^bb7 // CHECK: aie.use_lock(%[[VAL_7]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_5]] : memref<16x16xi16>, 0, 256) +// CHECK: aie.dma_bd(%[[VAL_5]] : memref<16x16xi16>) {len = 256 : i32} // CHECK: aie.use_lock(%[[VAL_6]], Release, 1) // CHECK: aie.next_bd ^bb7 // CHECK: ^bb9: // pred: ^bb6 diff --git a/test/objectFifo-stateful-transform/memTile_test.mlir b/test/objectFifo-stateful-transform/memTile_test.mlir index 285fc45baf..b88db28637 100644 --- a/test/objectFifo-stateful-transform/memTile_test.mlir +++ b/test/objectFifo-stateful-transform/memTile_test.mlir @@ -31,12 +31,12 @@ // CHECK: %[[VAL_11:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb3) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 // CHECK: aie.use_lock(%[[VAL_9]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_6]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_6]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_8]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[VAL_9]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_7]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_7]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_8]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb3: // pred: ^bb0 @@ -46,12 +46,12 @@ // CHECK: %[[VAL_13:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 // CHECK: aie.use_lock(%[[VAL_4]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_2]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_2]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_5]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[VAL_4]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_3]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_3]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_5]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb3: // pred: ^bb0 diff --git a/test/objectFifo-stateful-transform/nd_dma_base_AIE2.mlir b/test/objectFifo-stateful-transform/nd_dma_base_AIE2.mlir index 998defb6b1..f031c8b134 100644 --- a/test/objectFifo-stateful-transform/nd_dma_base_AIE2.mlir +++ b/test/objectFifo-stateful-transform/nd_dma_base_AIE2.mlir @@ -48,34 +48,34 @@ // CHECK: %[[VAL_26:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb5) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb4 // CHECK: aie.use_lock(%[[of0_cons_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of0_buff_0]] : memref<256xi32>, 0, 256, [, , ]) +// CHECK: aie.dma_bd(%[[of0_buff_0]] : memref<256xi32>, dims = [, , ]) {len = 256 : i32} // CHECK: aie.use_lock(%[[of0_prod_lock]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[of0_cons_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of0_buff_1]] : memref<256xi32>, 0, 256, [, , ]) +// CHECK: aie.dma_bd(%[[of0_buff_1]] : memref<256xi32>, dims = [, , ]) {len = 256 : i32} // CHECK: aie.use_lock(%[[of0_prod_lock]], Release, 1) // CHECK: aie.next_bd ^bb3 // CHECK: ^bb3: // pred: ^bb2 // CHECK: aie.use_lock(%[[of0_cons_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of0_buff_2]] : memref<256xi32>, 0, 256, [, , ]) +// CHECK: aie.dma_bd(%[[of0_buff_2]] : memref<256xi32>, dims = [, , ]) {len = 256 : i32} // CHECK: aie.use_lock(%[[of0_prod_lock]], Release, 1) // CHECK: aie.next_bd ^bb4 // CHECK: ^bb4: // pred: ^bb3 // CHECK: aie.use_lock(%[[of0_cons_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of0_buff_3]] : memref<256xi32>, 0, 256, [, , ]) +// CHECK: aie.dma_bd(%[[of0_buff_3]] : memref<256xi32>, dims = [, , ]) {len = 256 : i32} // CHECK: aie.use_lock(%[[of0_prod_lock]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb5: // pred: ^bb0 // CHECK: %[[VAL_27:.*]] = aie.dma_start(MM2S, 1, ^bb6, ^bb8) // CHECK: ^bb6: // 2 preds: ^bb5, ^bb7 // CHECK: aie.use_lock(%[[of1_cons_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of1_buff_0]] : memref<256xi32>, 0, 256, []) +// CHECK: aie.dma_bd(%[[of1_buff_0]] : memref<256xi32>, dims = []) {len = 256 : i32} // CHECK: aie.use_lock(%[[of1_prod_lock]], Release, 1) // CHECK: aie.next_bd ^bb7 // CHECK: ^bb7: // pred: ^bb6 // CHECK: aie.use_lock(%[[of1_cons_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of1_buff_1]] : memref<256xi32>, 0, 256, []) +// CHECK: aie.dma_bd(%[[of1_buff_1]] : memref<256xi32>, dims = []) {len = 256 : i32} // CHECK: aie.use_lock(%[[of1_prod_lock]], Release, 1) // CHECK: aie.next_bd ^bb6 // CHECK: ^bb8: // pred: ^bb5 @@ -85,22 +85,22 @@ // CHECK: %[[VAL_26:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb5) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb4 // CHECK: aie.use_lock(%[[of0_cons_prod_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of0_cons_buff_0]] : memref<256xi32>, 0, 256, []) +// CHECK: aie.dma_bd(%[[of0_cons_buff_0]] : memref<256xi32>, dims = []) {len = 256 : i32} // CHECK: aie.use_lock(%[[of0_cons_cons_lock]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[of0_cons_prod_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of0_cons_buff_1]] : memref<256xi32>, 0, 256, []) +// CHECK: aie.dma_bd(%[[of0_cons_buff_1]] : memref<256xi32>, dims = []) {len = 256 : i32} // CHECK: aie.use_lock(%[[of0_cons_cons_lock]], Release, 1) // CHECK: aie.next_bd ^bb3 // CHECK: ^bb3: // pred: ^bb2 // CHECK: aie.use_lock(%[[of0_cons_prod_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of0_cons_buff_2]] : memref<256xi32>, 0, 256, []) +// CHECK: aie.dma_bd(%[[of0_cons_buff_2]] : memref<256xi32>, dims = []) {len = 256 : i32} // CHECK: aie.use_lock(%[[of0_cons_cons_lock]], Release, 1) // CHECK: aie.next_bd ^bb4 // CHECK: ^bb4: // pred: ^bb3 // CHECK: aie.use_lock(%[[of0_cons_prod_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of0_cons_buff_3]] : memref<256xi32>, 0, 256, []) +// CHECK: aie.dma_bd(%[[of0_cons_buff_3]] : memref<256xi32>, dims = []) {len = 256 : i32} // CHECK: aie.use_lock(%[[of0_cons_cons_lock]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb5: // pred: ^bb0 @@ -110,12 +110,12 @@ // CHECK: %[[VAL_26:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 // CHECK: aie.use_lock(%[[of1_cons_prod_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of1_cons_buff_0]] : memref<256xi32>, 0, 256) +// CHECK: aie.dma_bd(%[[of1_cons_buff_0]] : memref<256xi32>) {len = 256 : i32} // CHECK: aie.use_lock(%[[of1_cons_cons_lock]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[of1_cons_prod_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of1_cons_buff_1]] : memref<256xi32>, 0, 256) +// CHECK: aie.dma_bd(%[[of1_cons_buff_1]] : memref<256xi32>) {len = 256 : i32} // CHECK: aie.use_lock(%[[of1_cons_cons_lock]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb3: // pred: ^bb0 diff --git a/test/objectFifo-stateful-transform/nd_dma_distribute_AIE2.mlir b/test/objectFifo-stateful-transform/nd_dma_distribute_AIE2.mlir index 53daf9418a..a280b61532 100644 --- a/test/objectFifo-stateful-transform/nd_dma_distribute_AIE2.mlir +++ b/test/objectFifo-stateful-transform/nd_dma_distribute_AIE2.mlir @@ -44,36 +44,36 @@ // CHECK: %21 = aie.dma_start(S2MM, 0, ^bb1, ^bb3) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 // CHECK: aie.use_lock(%[[of0_cons_prod_lock:.*]], AcquireGreaterEqual, 2) -// CHECK: aie.dma_bd(%[[of0_cons_buf_0:.*]] : memref<256xi32>, 0, 256) +// CHECK: aie.dma_bd(%[[of0_cons_buf_0:.*]] : memref<256xi32>) {len = 256 : i32} // CHECK: aie.use_lock(%[[of0_cons_cons_lock:.*]], Release, 2) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[of0_cons_prod_lock:.*]], AcquireGreaterEqual, 2) -// CHECK: aie.dma_bd(%[[of0_cons_buf_1:.*]] : memref<256xi32>, 0, 256) +// CHECK: aie.dma_bd(%[[of0_cons_buf_1:.*]] : memref<256xi32>) {len = 256 : i32} // CHECK: aie.use_lock(%[[of0_cons_cons_lock:.*]], Release, 2) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb3: // pred: ^bb0 // CHECK: %22 = aie.dma_start(MM2S, 0, ^bb4, ^bb6) // CHECK: ^bb4: // 2 preds: ^bb3, ^bb5 // CHECK: aie.use_lock(%[[of0_cons_cons_lock:.*]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of0_cons_buf_0:.*]] : memref<256xi32>, 0, 128, [, , , ]) +// CHECK: aie.dma_bd(%[[of0_cons_buf_0:.*]] : memref<256xi32>, dims = [, , , ]) {len = 128 : i32} // CHECK: aie.use_lock(%[[of0_cons_prod_lock:.*]], Release, 1) // CHECK: aie.next_bd ^bb5 // CHECK: ^bb5: // pred: ^bb4 // CHECK: aie.use_lock(%[[of0_cons_cons_lock:.*]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of0_cons_buf_1:.*]] : memref<256xi32>, 0, 128, [, , , ]) +// CHECK: aie.dma_bd(%[[of0_cons_buf_1:.*]] : memref<256xi32>, dims = [, , , ]) {len = 128 : i32} // CHECK: aie.use_lock(%[[of0_cons_prod_lock:.*]], Release, 1) // CHECK: aie.next_bd ^bb4 // CHECK: ^bb6: // pred: ^bb3 // CHECK: %23 = aie.dma_start(MM2S, 1, ^bb7, ^bb9) // CHECK: ^bb7: // 2 preds: ^bb6, ^bb8 // CHECK: aie.use_lock(%[[of0_cons_cons_lock:.*]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of0_cons_buf_0:.*]] : memref<256xi32>, 512, 128, [, , , ]) +// CHECK: aie.dma_bd(%[[of0_cons_buf_0:.*]] : memref<256xi32>, dims = [, , , ]) {len = 128 : i32, offset = 512 : i32} // CHECK: aie.use_lock(%[[of0_cons_prod_lock:.*]], Release, 1) // CHECK: aie.next_bd ^bb8 // CHECK: ^bb8: // pred: ^bb7 // CHECK: aie.use_lock(%[[of0_cons_cons_lock:.*]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of0_cons_buf_1:.*]] : memref<256xi32>, 512, 128, [, , , ]) +// CHECK: aie.dma_bd(%[[of0_cons_buf_1:.*]] : memref<256xi32>, dims = [, , , ]) {len = 128 : i32, offset = 512 : i32} // CHECK: aie.use_lock(%[[of0_cons_prod_lock:.*]], Release, 1) // CHECK: aie.next_bd ^bb7 // CHECK: ^bb9: // pred: ^bb6 @@ -83,12 +83,12 @@ // CHECK: %21 = aie.dma_start(S2MM, 0, ^bb1, ^bb3) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 // CHECK: aie.use_lock(%[[of1_cons_prod_lock:.*]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of1_cons_buf_0:.*]] : memref<128xi32>, 0, 128) +// CHECK: aie.dma_bd(%[[of1_cons_buf_0:.*]] : memref<128xi32>) {len = 128 : i32} // CHECK: aie.use_lock(%[[of1_cons_cons_lock:.*]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[of1_cons_prod_lock:.*]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of1_cons_buf_1:.*]] : memref<128xi32>, 0, 128) +// CHECK: aie.dma_bd(%[[of1_cons_buf_1:.*]] : memref<128xi32>) {len = 128 : i32} // CHECK: aie.use_lock(%[[of1_cons_cons_lock:.*]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb3: // pred: ^bb0 @@ -98,12 +98,12 @@ // CHECK: %21 = aie.dma_start(S2MM, 0, ^bb1, ^bb3) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 // CHECK: aie.use_lock(%[[of2_cons_prod_lock:.*]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of2_cons_buf_0:.*]] : memref<128xi32>, 0, 128) +// CHECK: aie.dma_bd(%[[of2_cons_buf_0:.*]] : memref<128xi32>) {len = 128 : i32} // CHECK: aie.use_lock(%[[of2_cons_cons_lock:.*]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[of2_cons_prod_lock:.*]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of2_cons_buf_1:.*]] : memref<128xi32>, 0, 128) +// CHECK: aie.dma_bd(%[[of2_cons_buf_1:.*]] : memref<128xi32>) {len = 128 : i32} // CHECK: aie.use_lock(%[[of2_cons_cons_lock:.*]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb3: // pred: ^bb0 diff --git a/test/objectFifo-stateful-transform/nd_dma_multiple_consumers_AIE2.mlir b/test/objectFifo-stateful-transform/nd_dma_multiple_consumers_AIE2.mlir index 5de9b4645c..fbc853a626 100644 --- a/test/objectFifo-stateful-transform/nd_dma_multiple_consumers_AIE2.mlir +++ b/test/objectFifo-stateful-transform/nd_dma_multiple_consumers_AIE2.mlir @@ -62,34 +62,34 @@ // CHECK: %[[VAL_44:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb5) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb4 // CHECK: aie.use_lock(%[[of0_cons_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of0_buff_0]] : memref<256xi32>, 0, 256, [, , ]) +// CHECK: aie.dma_bd(%[[of0_buff_0]] : memref<256xi32>, dims = [, , ]) {len = 256 : i32} // CHECK: aie.use_lock(%[[of0_prod_lock]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[of0_cons_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of0_buff_1]] : memref<256xi32>, 0, 256, [, , ]) +// CHECK: aie.dma_bd(%[[of0_buff_1]] : memref<256xi32>, dims = [, , ]) {len = 256 : i32} // CHECK: aie.use_lock(%[[of0_prod_lock]], Release, 1) // CHECK: aie.next_bd ^bb3 // CHECK: ^bb3: // pred: ^bb2 // CHECK: aie.use_lock(%[[of0_cons_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of0_buff_2]] : memref<256xi32>, 0, 256, [, , ]) +// CHECK: aie.dma_bd(%[[of0_buff_2]] : memref<256xi32>, dims = [, , ]) {len = 256 : i32} // CHECK: aie.use_lock(%[[of0_prod_lock]], Release, 1) // CHECK: aie.next_bd ^bb4 // CHECK: ^bb4: // pred: ^bb3 // CHECK: aie.use_lock(%[[of0_cons_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of0_buff_3]] : memref<256xi32>, 0, 256, [, , ]) +// CHECK: aie.dma_bd(%[[of0_buff_3]] : memref<256xi32>, dims = [, , ]) {len = 256 : i32} // CHECK: aie.use_lock(%[[of0_prod_lock]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb5: // pred: ^bb0 // CHECK: %[[VAL_45:.*]] = aie.dma_start(MM2S, 1, ^bb6, ^bb8) // CHECK: ^bb6: // 2 preds: ^bb5, ^bb7 // CHECK: aie.use_lock(%[[of1_cons_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of1_buff_0]] : memref<256xi32>, 0, 256, []) +// CHECK: aie.dma_bd(%[[of1_buff_0]] : memref<256xi32>, dims = []) {len = 256 : i32} // CHECK: aie.use_lock(%[[of1_prod_lock]], Release, 1) // CHECK: aie.next_bd ^bb7 // CHECK: ^bb7: // pred: ^bb6 // CHECK: aie.use_lock(%[[of1_cons_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of1_buff_1]] : memref<256xi32>, 0, 256, []) +// CHECK: aie.dma_bd(%[[of1_buff_1]] : memref<256xi32>, dims = []) {len = 256 : i32} // CHECK: aie.use_lock(%[[of1_prod_lock]], Release, 1) // CHECK: aie.next_bd ^bb6 // CHECK: ^bb8: // pred: ^bb5 @@ -99,22 +99,22 @@ // CHECK: %[[VAL_44:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb5) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb4 // CHECK: aie.use_lock(%[[of0_0_cons_prod_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of0_0_cons_buff_0]] : memref<256xi32>, 0, 256, []) +// CHECK: aie.dma_bd(%[[of0_0_cons_buff_0]] : memref<256xi32>, dims = []) {len = 256 : i32} // CHECK: aie.use_lock(%[[of0_0_cons_cons_lock]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[of0_0_cons_prod_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of0_0_cons_buff_1]] : memref<256xi32>, 0, 256, []) +// CHECK: aie.dma_bd(%[[of0_0_cons_buff_1]] : memref<256xi32>, dims = []) {len = 256 : i32} // CHECK: aie.use_lock(%[[of0_0_cons_cons_lock]], Release, 1) // CHECK: aie.next_bd ^bb3 // CHECK: ^bb3: // pred: ^bb2 // CHECK: aie.use_lock(%[[of0_0_cons_prod_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of0_0_cons_buff_2]] : memref<256xi32>, 0, 256, []) +// CHECK: aie.dma_bd(%[[of0_0_cons_buff_2]] : memref<256xi32>, dims = []) {len = 256 : i32} // CHECK: aie.use_lock(%[[of0_0_cons_cons_lock]], Release, 1) // CHECK: aie.next_bd ^bb4 // CHECK: ^bb4: // pred: ^bb3 // CHECK: aie.use_lock(%[[of0_0_cons_prod_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of0_0_cons_buff_3]] : memref<256xi32>, 0, 256, []) +// CHECK: aie.dma_bd(%[[of0_0_cons_buff_3]] : memref<256xi32>, dims = []) {len = 256 : i32} // CHECK: aie.use_lock(%[[of0_0_cons_cons_lock]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb5: // pred: ^bb0 @@ -124,34 +124,34 @@ // CHECK: %[[VAL_44:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb5) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb4 // CHECK: aie.use_lock(%[[of0_1_cons_prod_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of0_1_cons_buff_0]] : memref<256xi32>, 0, 256, []) +// CHECK: aie.dma_bd(%[[of0_1_cons_buff_0]] : memref<256xi32>, dims = []) {len = 256 : i32} // CHECK: aie.use_lock(%[[of0_1_cons_cons_lock]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[of0_1_cons_prod_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of0_1_cons_buff_1]] : memref<256xi32>, 0, 256, []) +// CHECK: aie.dma_bd(%[[of0_1_cons_buff_1]] : memref<256xi32>, dims = []) {len = 256 : i32} // CHECK: aie.use_lock(%[[of0_1_cons_cons_lock]], Release, 1) // CHECK: aie.next_bd ^bb3 // CHECK: ^bb3: // pred: ^bb2 // CHECK: aie.use_lock(%[[of0_1_cons_prod_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of0_1_cons_buff_2]] : memref<256xi32>, 0, 256, []) +// CHECK: aie.dma_bd(%[[of0_1_cons_buff_2]] : memref<256xi32>, dims = []) {len = 256 : i32} // CHECK: aie.use_lock(%[[of0_1_cons_cons_lock]], Release, 1) // CHECK: aie.next_bd ^bb4 // CHECK: ^bb4: // pred: ^bb3 // CHECK: aie.use_lock(%[[of0_1_cons_prod_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of0_1_cons_buff_3]] : memref<256xi32>, 0, 256, []) +// CHECK: aie.dma_bd(%[[of0_1_cons_buff_3]] : memref<256xi32>, dims = []) {len = 256 : i32} // CHECK: aie.use_lock(%[[of0_1_cons_cons_lock]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb5: // pred: ^bb0 // CHECK: %[[VAL_45:.*]] = aie.dma_start(S2MM, 1, ^bb6, ^bb8) // CHECK: ^bb6: // 2 preds: ^bb5, ^bb7 // CHECK: aie.use_lock(%[[of1_cons_prod_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of1_cons_buff_0]] : memref<256xi32>, 0, 256) +// CHECK: aie.dma_bd(%[[of1_cons_buff_0]] : memref<256xi32>) {len = 256 : i32} // CHECK: aie.use_lock(%[[of1_cons_cons_lock]], Release, 1) // CHECK: aie.next_bd ^bb7 // CHECK: ^bb7: // pred: ^bb6 // CHECK: aie.use_lock(%[[of1_cons_prod_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of1_cons_buff_1]] : memref<256xi32>, 0, 256) +// CHECK: aie.dma_bd(%[[of1_cons_buff_1]] : memref<256xi32>) {len = 256 : i32} // CHECK: aie.use_lock(%[[of1_cons_cons_lock]], Release, 1) // CHECK: aie.next_bd ^bb6 // CHECK: ^bb8: // pred: ^bb5 @@ -161,12 +161,12 @@ // CHECK: %[[VAL_44:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb3) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 // CHECK: aie.use_lock(%[[of3_cons_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of3_buff_0]] : memref<256xi32>, 0, 256) +// CHECK: aie.dma_bd(%[[of3_buff_0]] : memref<256xi32>) {len = 256 : i32} // CHECK: aie.use_lock(%[[of3_prod_lock]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[of3_cons_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of3_buff_1]] : memref<256xi32>, 0, 256) +// CHECK: aie.dma_bd(%[[of3_buff_1]] : memref<256xi32>) {len = 256 : i32} // CHECK: aie.use_lock(%[[of3_prod_lock]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb3: // pred: ^bb0 @@ -176,12 +176,12 @@ // CHECK: %[[VAL_44:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 // CHECK: aie.use_lock(%[[of3_cons_prod_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of3_cons_buff_0]] : memref<256xi32>, 0, 256, []) +// CHECK: aie.dma_bd(%[[of3_cons_buff_0]] : memref<256xi32>, dims = []) {len = 256 : i32} // CHECK: aie.use_lock(%[[of3_cons_cons_lock]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[of3_cons_prod_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of3_cons_buff_1]] : memref<256xi32>, 0, 256, []) +// CHECK: aie.dma_bd(%[[of3_cons_buff_1]] : memref<256xi32>, dims = []) {len = 256 : i32} // CHECK: aie.use_lock(%[[of3_cons_cons_lock]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb3: // pred: ^bb0 diff --git a/test/objectFifo-stateful-transform/non_adjacency_test_1.mlir b/test/objectFifo-stateful-transform/non_adjacency_test_1.mlir index cec4b4d461..2e1dabfb1d 100644 --- a/test/objectFifo-stateful-transform/non_adjacency_test_1.mlir +++ b/test/objectFifo-stateful-transform/non_adjacency_test_1.mlir @@ -63,12 +63,12 @@ // CHECK: %[[VAL_24:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb3) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 // CHECK: aie.use_lock(%[[VAL_8]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_6]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_6]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_8]], Release, 0) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[VAL_9]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_7]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_7]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_9]], Release, 0) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb3: // pred: ^bb0 @@ -78,12 +78,12 @@ // CHECK: %[[VAL_26:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 // CHECK: aie.use_lock(%[[VAL_4]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_2]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_2]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_4]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[VAL_5]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_3]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_3]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_5]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb3: // pred: ^bb0 diff --git a/test/objectFifo-stateful-transform/non_adjacency_test_2.mlir b/test/objectFifo-stateful-transform/non_adjacency_test_2.mlir index 0ea8e204bb..c53ce926f7 100644 --- a/test/objectFifo-stateful-transform/non_adjacency_test_2.mlir +++ b/test/objectFifo-stateful-transform/non_adjacency_test_2.mlir @@ -75,12 +75,12 @@ // CHECK: %[[VAL_28:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb3) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 // CHECK: aie.use_lock(%[[VAL_12]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_10]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_10]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_12]], Release, 0) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[VAL_13]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_11]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_11]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_13]], Release, 0) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb3: // pred: ^bb0 @@ -90,22 +90,22 @@ // CHECK: %[[VAL_30:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb5) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb4 // CHECK: aie.use_lock(%[[VAL_6]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_2]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_2]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_6]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[VAL_7]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_3]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_3]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_7]], Release, 1) // CHECK: aie.next_bd ^bb3 // CHECK: ^bb3: // pred: ^bb2 // CHECK: aie.use_lock(%[[VAL_8]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_4]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_4]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_8]], Release, 1) // CHECK: aie.next_bd ^bb4 // CHECK: ^bb4: // pred: ^bb3 // CHECK: aie.use_lock(%[[VAL_9]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_5]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_5]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_9]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb5: // pred: ^bb0 diff --git a/test/objectFifo-stateful-transform/non_adjacency_test_AIE2.mlir b/test/objectFifo-stateful-transform/non_adjacency_test_AIE2.mlir index d27177511e..e1139c5df7 100644 --- a/test/objectFifo-stateful-transform/non_adjacency_test_AIE2.mlir +++ b/test/objectFifo-stateful-transform/non_adjacency_test_AIE2.mlir @@ -64,12 +64,12 @@ // CHECK: %[[VAL_24:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb3) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 // CHECK: aie.use_lock(%[[VAL_9]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_6]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_6]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_8]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[VAL_9]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_7]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_7]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_8]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb3: // pred: ^bb0 @@ -79,12 +79,12 @@ // CHECK: %[[VAL_26:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 // CHECK: aie.use_lock(%[[VAL_4]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_2]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_2]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_5]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[VAL_4]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_3]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_3]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_5]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb3: // pred: ^bb0 diff --git a/test/objectFifo-stateful-transform/register_external_buffers_test.mlir b/test/objectFifo-stateful-transform/register_external_buffers_test.mlir index dd57f1c5f0..ae7b6dc90d 100644 --- a/test/objectFifo-stateful-transform/register_external_buffers_test.mlir +++ b/test/objectFifo-stateful-transform/register_external_buffers_test.mlir @@ -45,7 +45,7 @@ // CHECK: %[[VAL_17:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb2) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb1 // CHECK: aie.use_lock(%[[VAL_8]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_9]] : memref<64xi32>, 0, 64) +// CHECK: aie.dma_bd(%[[VAL_9]] : memref<64xi32>) {len = 64 : i32} // CHECK: aie.use_lock(%[[VAL_8]], Release, 0) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb2: // pred: ^bb0 @@ -55,17 +55,17 @@ // CHECK: %[[VAL_19:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb3 // CHECK: aie.use_lock(%[[VAL_5]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_2]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_2]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_5]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[VAL_6]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_3]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_3]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_6]], Release, 1) // CHECK: aie.next_bd ^bb3 // CHECK: ^bb3: // pred: ^bb2 // CHECK: aie.use_lock(%[[VAL_7]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_4]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_4]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_7]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb4: // pred: ^bb0 diff --git a/test/objectFifo-stateful-transform/shimRow_mem_test.mlir b/test/objectFifo-stateful-transform/shimRow_mem_test.mlir index 8a9c1e1c32..406676d087 100644 --- a/test/objectFifo-stateful-transform/shimRow_mem_test.mlir +++ b/test/objectFifo-stateful-transform/shimRow_mem_test.mlir @@ -43,7 +43,7 @@ // CHECK: %[[VAL_17:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb2) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb1 // CHECK: aie.use_lock(%[[VAL_8]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_9]] : memref<64xi32>, 0, 64) +// CHECK: aie.dma_bd(%[[VAL_9]] : memref<64xi32>) {len = 64 : i32} // CHECK: aie.use_lock(%[[VAL_8]], Release, 0) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb2: // pred: ^bb0 @@ -53,17 +53,17 @@ // CHECK: %[[VAL_19:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb3 // CHECK: aie.use_lock(%[[VAL_5]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_2]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_2]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_5]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[VAL_6]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_3]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_3]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_6]], Release, 1) // CHECK: aie.next_bd ^bb3 // CHECK: ^bb3: // pred: ^bb2 // CHECK: aie.use_lock(%[[VAL_7]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_4]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_4]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_7]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb4: // pred: ^bb0 diff --git a/test/objectFifo-stateful-transform/shim_AIE2_test.mlir b/test/objectFifo-stateful-transform/shim_AIE2_test.mlir index 5ea7bbe720..cde76a5f82 100644 --- a/test/objectFifo-stateful-transform/shim_AIE2_test.mlir +++ b/test/objectFifo-stateful-transform/shim_AIE2_test.mlir @@ -36,14 +36,14 @@ // CHECK: %[[VAL_17:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb2) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb1 // CHECK: aie.use_lock(%[[VAL_13]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_14]] : memref<64xi32>, 0, 64) +// CHECK: aie.dma_bd(%[[VAL_14]] : memref<64xi32>) {len = 64 : i32} // CHECK: aie.use_lock(%[[VAL_12]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb2: // pred: ^bb0 // CHECK: %[[VAL_18:.*]] = aie.dma_start(S2MM, 0, ^bb3, ^bb4) // CHECK: ^bb3: // 2 preds: ^bb2, ^bb3 // CHECK: aie.use_lock(%[[VAL_2]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_15]] : memref<64xi32>, 0, 64) +// CHECK: aie.dma_bd(%[[VAL_15]] : memref<64xi32>) {len = 64 : i32} // CHECK: aie.use_lock(%[[VAL_3]], Release, 1) // CHECK: aie.next_bd ^bb3 // CHECK: ^bb4: // pred: ^bb2 @@ -54,24 +54,24 @@ // CHECK: %[[VAL_20:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 // CHECK: aie.use_lock(%[[VAL_10]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_8]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_8]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_11]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[VAL_10]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_9]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_9]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_11]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb3: // pred: ^bb0 // CHECK: %[[VAL_21:.*]] = aie.dma_start(MM2S, 0, ^bb4, ^bb6) // CHECK: ^bb4: // 2 preds: ^bb3, ^bb5 // CHECK: aie.use_lock(%[[VAL_7]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_4]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_4]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_6]], Release, 1) // CHECK: aie.next_bd ^bb5 // CHECK: ^bb5: // pred: ^bb4 // CHECK: aie.use_lock(%[[VAL_7]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_5]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_5]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_6]], Release, 1) // CHECK: aie.next_bd ^bb4 // CHECK: ^bb6: // pred: ^bb3 diff --git a/test/objectFifo-stateful-transform/shim_broadcast_test.mlir b/test/objectFifo-stateful-transform/shim_broadcast_test.mlir index a1382f0c2c..9ab6cae47f 100644 --- a/test/objectFifo-stateful-transform/shim_broadcast_test.mlir +++ b/test/objectFifo-stateful-transform/shim_broadcast_test.mlir @@ -40,7 +40,7 @@ // CHECK: %[[VAL_20:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb2) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb1 // CHECK: aie.use_lock(%[[VAL_17]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_18]] : memref<64xi32>, 0, 64) +// CHECK: aie.dma_bd(%[[VAL_18]] : memref<64xi32>) {len = 64 : i32} // CHECK: aie.use_lock(%[[VAL_16]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb2: // pred: ^bb0 @@ -50,12 +50,12 @@ // CHECK: %[[VAL_22:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 // CHECK: aie.use_lock(%[[VAL_6]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_4]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_4]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_7]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[VAL_6]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_5]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_5]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_7]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb3: // pred: ^bb0 @@ -65,12 +65,12 @@ // CHECK: %[[VAL_24:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 // CHECK: aie.use_lock(%[[VAL_10]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_8]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_8]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_11]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[VAL_10]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_9]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_9]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_11]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb3: // pred: ^bb0 @@ -80,12 +80,12 @@ // CHECK: %[[VAL_26:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 // CHECK: aie.use_lock(%[[VAL_14]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_12]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_12]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_15]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[VAL_14]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_13]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_13]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_15]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb3: // pred: ^bb0 diff --git a/test/objectFifo-stateful-transform/tileDMA_test.mlir b/test/objectFifo-stateful-transform/tileDMA_test.mlir index bea2793512..9d87b1af57 100644 --- a/test/objectFifo-stateful-transform/tileDMA_test.mlir +++ b/test/objectFifo-stateful-transform/tileDMA_test.mlir @@ -53,31 +53,31 @@ // CHECK: %[[VAL_24:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb3) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 // CHECK: aie.use_lock(%[[VAL_11]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_10]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_10]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_11]], Release, 0) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[VAL_13]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_12]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_12]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_13]], Release, 0) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb3: // pred: ^bb0 // CHECK: %[[VAL_25:.*]] = aie.dma_start(S2MM, 0, ^bb4, ^bb5) // CHECK: ^bb4: // 2 preds: ^bb3, ^bb4 // CHECK: aie.use_lock(%[[VAL_15]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_14]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_14]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_15]], Release, 1) // CHECK: aie.next_bd ^bb4 // CHECK: ^bb5: // pred: ^bb3 // CHECK: %[[VAL_26:.*]] = aie.dma_start(MM2S, 1, ^bb6, ^bb8) // CHECK: ^bb6: // 2 preds: ^bb5, ^bb7 // CHECK: aie.use_lock(%[[VAL_8]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_6]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_6]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_8]], Release, 0) // CHECK: aie.next_bd ^bb7 // CHECK: ^bb7: // pred: ^bb6 // CHECK: aie.use_lock(%[[VAL_9]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_7]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_7]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_9]], Release, 0) // CHECK: aie.next_bd ^bb6 // CHECK: ^bb8: // pred: ^bb5 @@ -87,12 +87,12 @@ // CHECK: %[[VAL_28:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) // CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 // CHECK: aie.use_lock(%[[VAL_4]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_2]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_2]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_4]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: // pred: ^bb1 // CHECK: aie.use_lock(%[[VAL_5]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_3]] : memref<16xi32>, 0, 16) +// CHECK: aie.dma_bd(%[[VAL_3]] : memref<16xi32>) {len = 16 : i32} // CHECK: aie.use_lock(%[[VAL_5]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb3: // pred: ^bb0 @@ -137,19 +137,19 @@ module @tileDMA_channels { %dma1 = aie.dma_start(MM2S, 0, ^bb1, ^bb3) ^bb1: aie.use_lock(%lock0, Acquire, 1) - aie.dma_bd(%buff0 : memref<16xi32>, 0, 16) + aie.dma_bd(%buff0 : memref<16xi32>) { len = 16 : i32 } aie.use_lock(%lock0, Release, 0) aie.next_bd ^bb2 ^bb2: aie.use_lock(%lock1, Acquire, 1) - aie.dma_bd(%buff1 : memref<16xi32>, 0, 16) + aie.dma_bd(%buff1 : memref<16xi32>) { len = 16 : i32 } aie.use_lock(%lock1, Release, 0) aie.next_bd ^bb1 ^bb3: %dma2 = aie.dma_start(S2MM, 0, ^bb4, ^bb5) ^bb4: aie.use_lock(%lock2, Acquire, 0) - aie.dma_bd(%buff2 : memref<16xi32>, 0, 16) + aie.dma_bd(%buff2 : memref<16xi32>) { len = 16 : i32 } aie.use_lock(%lock2, Release, 1) aie.next_bd ^bb4 ^bb5: diff --git a/test/unit_tests/aie/05_tiledma/aie.mlir b/test/unit_tests/aie/05_tiledma/aie.mlir index 81af3e2818..e6946768c8 100644 --- a/test/unit_tests/aie/05_tiledma/aie.mlir +++ b/test/unit_tests/aie/05_tiledma/aie.mlir @@ -66,7 +66,7 @@ module @test05_tiledma { %dma0 = aie.dma_start("MM2S", 0, ^bd0, ^end) ^bd0: aie.use_lock(%lock13_5, "Acquire", 1) - aie.dma_bd(%buf13_1 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf13_1 : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%lock13_5, "Release", 0) aie.next_bd ^end // point to the next BD, or termination ^end: @@ -77,7 +77,7 @@ module @test05_tiledma { %dma0 = aie.dma_start("S2MM", 1, ^bd0, ^end) ^bd0: aie.use_lock(%lock33_6, "Acquire", 0) - aie.dma_bd(%buf33_0: memref<256xi32>, 0, 256) + aie.dma_bd(%buf33_0: memref<256xi32>) { len = 256 : i32 } aie.use_lock(%lock33_6, "Release", 1) aie.next_bd ^end // point to the next BD, or termination ^end: diff --git a/test/unit_tests/aie/08_stream_broadcast/aie.mlir b/test/unit_tests/aie/08_stream_broadcast/aie.mlir index 13d8c5b8f6..950a4c1b27 100644 --- a/test/unit_tests/aie/08_stream_broadcast/aie.mlir +++ b/test/unit_tests/aie/08_stream_broadcast/aie.mlir @@ -60,7 +60,7 @@ module @test08_stream_broadcast { %dma0 = aie.dma_start("MM2S", 0, ^bd0, ^end) ^bd0: aie.use_lock(%lock13_5, "Acquire", 1) - aie.dma_bd(%buf13_1 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf13_1 : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%lock13_5, "Release", 0) aie.next_bd ^end // point to the next BD, or termination ^end: @@ -97,7 +97,7 @@ module @test08_stream_broadcast { %dma0 = aie.dma_start("S2MM", 1, ^bd0, ^end) ^bd0: aie.use_lock(%lock32_6, "Acquire", 0) - aie.dma_bd(%buf32_0 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf32_0 : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%lock32_6, "Release", 1) aie.next_bd ^end // point to the next BD, or termination ^end: @@ -132,7 +132,7 @@ module @test08_stream_broadcast { %dma0 = aie.dma_start("S2MM", 1, ^bd0, ^end) ^bd0: aie.use_lock(%lock33_6, "Acquire", 0) - aie.dma_bd(%buf33_0 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf33_0 : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%lock33_6, "Release", 1) aie.next_bd ^end // point to the next BD, or termination ^end: @@ -167,7 +167,7 @@ module @test08_stream_broadcast { %dma0 = aie.dma_start("S2MM", 1, ^bd0, ^end) ^bd0: aie.use_lock(%lock34_6, "Acquire", 0) - aie.dma_bd(%buf34_0 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf34_0 : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%lock34_6, "Release", 1) aie.next_bd ^end // point to the next BD, or termination ^end: diff --git a/test/unit_tests/aie/09_simple_shim_dma/aie.mlir b/test/unit_tests/aie/09_simple_shim_dma/aie.mlir index dd334c7baf..3065bc14ec 100644 --- a/test/unit_tests/aie/09_simple_shim_dma/aie.mlir +++ b/test/unit_tests/aie/09_simple_shim_dma/aie.mlir @@ -32,7 +32,7 @@ module @test09_simple_shim_dma { ^bd0: aie.use_lock(%lock1, Acquire, 1) - aie.dma_bd(%buffer : memref<512 x i32>, 0, 512) + aie.dma_bd(%buffer : memref<512 x i32>) { len = 512 : i32 } aie.use_lock(%lock1, Release, 0) aie.next_bd ^bd0 ^end: @@ -51,12 +51,12 @@ module @test09_simple_shim_dma { %srcDma = aie.dma_start("S2MM", 0, ^bd0, ^end) ^bd0: aie.use_lock(%l72_0, "Acquire", 0) - aie.dma_bd(%buf72_0 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf72_0 : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%l72_0, "Release", 1) aie.next_bd ^bd1 ^bd1: aie.use_lock(%l72_1, "Acquire", 0) - aie.dma_bd(%buf72_1 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf72_1 : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%l72_1, "Release", 1) aie.next_bd ^bd0 ^end: diff --git a/test/unit_tests/aie/14_stream_packet/aie.mlir b/test/unit_tests/aie/14_stream_packet/aie.mlir index b460d14417..4702f4a4a1 100644 --- a/test/unit_tests/aie/14_stream_packet/aie.mlir +++ b/test/unit_tests/aie/14_stream_packet/aie.mlir @@ -53,7 +53,7 @@ module @test14_stream_packet { ^bd0: aie.use_lock(%l73, "Acquire", 0) aie.dma_bd_packet(0x5, 0xD) - aie.dma_bd(%buf73 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf73 : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%l73, "Release", 1) aie.next_bd ^end ^end: @@ -65,7 +65,7 @@ module @test14_stream_packet { ^bd0: aie.use_lock(%l71, "Acquire", 0) aie.dma_bd_packet(0x4, 0xC) - aie.dma_bd(%buf71 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf71 : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%l71, "Release", 1) aie.next_bd ^end ^end: @@ -85,12 +85,12 @@ module @test14_stream_packet { // %srcDma1 = aie.dma_start("S2MM", 1, ^bd1, ^end) ^bd0: aie.use_lock(%l62, "Acquire", 0) - aie.dma_bd(%buf62 : memref<512xi32>, 0, 512) + aie.dma_bd(%buf62 : memref<512xi32>) { len = 512 : i32 } aie.use_lock(%l62, "Release", 1) aie.next_bd ^end //^bd1: // aie.use_lock(%l62_1, "Acquire", 0) - // aie.dma_bd(%buf62_1 : memref<256xi32>, 0, 256) + // aie.dma_bd(%buf62_1 : memref<256xi32>) {len = 256 : i32} // aie.use_lock(%l62_1, "Release", 1) // aie.next_bd ^bd0 ^end: diff --git a/test/unit_tests/aie/17_shim_dma_with_core/aie.mlir b/test/unit_tests/aie/17_shim_dma_with_core/aie.mlir index d3cdae2aa6..acb769b5e5 100644 --- a/test/unit_tests/aie/17_shim_dma_with_core/aie.mlir +++ b/test/unit_tests/aie/17_shim_dma_with_core/aie.mlir @@ -81,22 +81,22 @@ module @test17_shim_dma_with_core{ %dstDma = aie.dma_start("MM2S", 1, ^bd2, ^end) ^bd0: aie.use_lock(%lock_a_ping, "Acquire", 0) - aie.dma_bd(%buf_a_ping : memref<64xi32>, 0, 64) + aie.dma_bd(%buf_a_ping : memref<64xi32>) { len = 64 : i32 } aie.use_lock(%lock_a_ping, "Release", 1) aie.next_bd ^bd1 ^bd1: aie.use_lock(%lock_a_pong, "Acquire", 0) - aie.dma_bd(%buf_a_pong : memref<64xi32>, 0, 64) + aie.dma_bd(%buf_a_pong : memref<64xi32>) { len = 64 : i32 } aie.use_lock(%lock_a_pong, "Release", 1) aie.next_bd ^bd0 ^bd2: aie.use_lock(%lock_b_ping, "Acquire", 1) - aie.dma_bd(%buf_b_ping : memref<64xi32>, 0, 64) + aie.dma_bd(%buf_b_ping : memref<64xi32>) { len = 64 : i32 } aie.use_lock(%lock_b_ping, "Release", 0) aie.next_bd ^bd3 ^bd3: aie.use_lock(%lock_b_pong, "Acquire", 1) - aie.dma_bd(%buf_b_pong : memref<64xi32>, 0, 64) + aie.dma_bd(%buf_b_pong : memref<64xi32>) { len = 64 : i32 } aie.use_lock(%lock_b_pong, "Release", 0) aie.next_bd ^bd2 ^end: @@ -128,12 +128,12 @@ module @test17_shim_dma_with_core{ aie.dma_start(S2MM, 0, ^bd1, ^end) ^bd0: aie.use_lock(%lock1, Acquire, 1) - aie.dma_bd(%buffer_in : memref<512 x i32>, 0, 512) + aie.dma_bd(%buffer_in : memref<512 x i32>) { len = 512 : i32 } aie.use_lock(%lock1, Release, 0) aie.next_bd ^bd0 ^bd1: aie.use_lock(%lock2, Acquire, 1) - aie.dma_bd(%buffer_out : memref<512 x i32>, 0, 512) + aie.dma_bd(%buffer_out : memref<512 x i32>) { len = 512 : i32 } aie.use_lock(%lock2, Release, 0) aie.next_bd ^bd1 ^end: diff --git a/test/unit_tests/aie/18_simple_shim_dma_routed/aie.mlir b/test/unit_tests/aie/18_simple_shim_dma_routed/aie.mlir index 4275e7bb86..90b42a3049 100644 --- a/test/unit_tests/aie/18_simple_shim_dma_routed/aie.mlir +++ b/test/unit_tests/aie/18_simple_shim_dma_routed/aie.mlir @@ -24,7 +24,7 @@ module @test18_simple_shim_dma_routed { ^bd0: aie.use_lock(%lock1, Acquire, 1) - aie.dma_bd(%buffer : memref<512 x i32>, 0, 512) + aie.dma_bd(%buffer : memref<512 x i32>) { len = 512 : i32 } aie.use_lock(%lock1, Release, 0) aie.next_bd ^bd0 ^end: @@ -43,12 +43,12 @@ module @test18_simple_shim_dma_routed { %srcDma = aie.dma_start("S2MM", 0, ^bd0, ^end) ^bd0: aie.use_lock(%l72_0, "Acquire", 0) - aie.dma_bd(%buf72_0 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf72_0 : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%l72_0, "Release", 1) aie.next_bd ^bd1 ^bd1: aie.use_lock(%l72_1, "Acquire", 0) - aie.dma_bd(%buf72_1 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf72_1 : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%l72_1, "Release", 1) aie.next_bd ^bd0 ^end: diff --git a/test/unit_tests/aie/19_shim_dma_with_core_routed/aie.mlir b/test/unit_tests/aie/19_shim_dma_with_core_routed/aie.mlir index 2ea68ade4f..e2339d06fb 100644 --- a/test/unit_tests/aie/19_shim_dma_with_core_routed/aie.mlir +++ b/test/unit_tests/aie/19_shim_dma_with_core_routed/aie.mlir @@ -79,22 +79,22 @@ module @test19_shim_dma_with_core_routed{ %dstDma = aie.dma_start("MM2S", 1, ^bd2, ^end) ^bd0: aie.use_lock(%lock_a_ping, "Acquire", 0) - aie.dma_bd(%buf_a_ping : memref<64xi32>, 0, 64) + aie.dma_bd(%buf_a_ping : memref<64xi32>) { len = 64 : i32 } aie.use_lock(%lock_a_ping, "Release", 1) aie.next_bd ^bd1 ^bd1: aie.use_lock(%lock_a_pong, "Acquire", 0) - aie.dma_bd(%buf_a_pong : memref<64xi32>, 0, 64) + aie.dma_bd(%buf_a_pong : memref<64xi32>) { len = 64 : i32 } aie.use_lock(%lock_a_pong, "Release", 1) aie.next_bd ^bd0 ^bd2: aie.use_lock(%lock_b_ping, "Acquire", 1) - aie.dma_bd(%buf_b_ping : memref<64xi32>, 0, 64) + aie.dma_bd(%buf_b_ping : memref<64xi32>) { len = 64 : i32 } aie.use_lock(%lock_b_ping, "Release", 0) aie.next_bd ^bd3 ^bd3: aie.use_lock(%lock_b_pong, "Acquire", 1) - aie.dma_bd(%buf_b_pong : memref<64xi32>, 0, 64) + aie.dma_bd(%buf_b_pong : memref<64xi32>) { len = 64 : i32 } aie.use_lock(%lock_b_pong, "Release", 0) aie.next_bd ^bd2 ^end: @@ -119,12 +119,12 @@ module @test19_shim_dma_with_core_routed{ aie.dma_start(S2MM, 0, ^bd1, ^end) ^bd0: aie.use_lock(%lock1, Acquire, 1) - aie.dma_bd(%buffer_in : memref<512 x i32>, 0, 512) + aie.dma_bd(%buffer_in : memref<512 x i32>) { len = 512 : i32 } aie.use_lock(%lock1, Release, 0) aie.next_bd ^bd0 ^bd1: aie.use_lock(%lock2, Acquire, 1) - aie.dma_bd(%buffer_out : memref<512 x i32>, 0, 512) + aie.dma_bd(%buffer_out : memref<512 x i32>) { len = 512 : i32 } aie.use_lock(%lock2, Release, 0) aie.next_bd ^bd1 ^end: diff --git a/test/unit_tests/aie/20_shim_dma_broadcast/aie.mlir b/test/unit_tests/aie/20_shim_dma_broadcast/aie.mlir index 60c3ee752a..b0e09c0f23 100644 --- a/test/unit_tests/aie/20_shim_dma_broadcast/aie.mlir +++ b/test/unit_tests/aie/20_shim_dma_broadcast/aie.mlir @@ -24,7 +24,7 @@ module @test20_shim_dma_broadcast { ^bd0: aie.use_lock(%lock1, Acquire, 1) - aie.dma_bd(%buffer : memref<512 x i32>, 0, 512) + aie.dma_bd(%buffer : memref<512 x i32>) { len = 512 : i32 } aie.use_lock(%lock1, Release, 0) aie.next_bd ^bd0 ^end: @@ -43,12 +43,12 @@ module @test20_shim_dma_broadcast { %srcDma = aie.dma_start("S2MM", 0, ^bd0, ^end) ^bd0: aie.use_lock(%l72_0, "Acquire", 0) - aie.dma_bd(%buf72_0 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf72_0 : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%l72_0, "Release", 1) aie.next_bd ^bd1 ^bd1: aie.use_lock(%l72_1, "Acquire", 0) - aie.dma_bd(%buf72_1 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf72_1 : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%l72_1, "Release", 1) aie.next_bd ^bd0 ^end: @@ -67,12 +67,12 @@ module @test20_shim_dma_broadcast { %srcDma = aie.dma_start("S2MM", 0, ^bd0, ^end) ^bd0: aie.use_lock(%l73_0, "Acquire", 0) - aie.dma_bd(%buf73_0 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf73_0 : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%l73_0, "Release", 1) aie.next_bd ^bd1 ^bd1: aie.use_lock(%l73_1, "Acquire", 0) - aie.dma_bd(%buf73_1 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf73_1 : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%l73_1, "Release", 1) aie.next_bd ^bd0 ^end: diff --git a/test/unit_tests/aie/21_shim_dma_packet/aie.mlir b/test/unit_tests/aie/21_shim_dma_packet/aie.mlir index eeb7be90eb..506211ef30 100644 --- a/test/unit_tests/aie/21_shim_dma_packet/aie.mlir +++ b/test/unit_tests/aie/21_shim_dma_packet/aie.mlir @@ -34,7 +34,7 @@ module @kernel_gemm { ^bb1: // 2 preds: ^bb0, ^bb1 aie.use_lock(%5, Acquire, 1) aie.dma_bd_packet(0, 2) - aie.dma_bd(%6 : memref<32x32xi32>, 0, 1024) + aie.dma_bd(%6 : memref<32x32xi32>) { len = 1024 : i32 } aie.use_lock(%5, Release, 0) aie.next_bd ^bb1 ^bb2: // pred: ^bb0 @@ -64,14 +64,14 @@ module @kernel_gemm { %43 = aie.dma_start(S2MM, 0, ^bb1, ^bb2) ^bb1: // 2 preds: ^bb0, ^bb1 aie.use_lock(%13, Acquire, 0) - aie.dma_bd(%16 : memref<32x32xi32>, 0, 1024) + aie.dma_bd(%16 : memref<32x32xi32>) { len = 1024 : i32 } aie.use_lock(%13, Release, 1) aie.next_bd ^bb1 ^bb2: // pred: ^bb0 %44 = aie.dma_start(MM2S, 0, ^bb3, ^bb4) ^bb3: // 2 preds: ^bb2, ^bb3 aie.use_lock(%11, Acquire, 1) - aie.dma_bd(%15 : memref<32x32xi32>, 0, 1024) + aie.dma_bd(%15 : memref<32x32xi32>) { len = 1024 : i32 } aie.use_lock(%11, Release, 0) aie.next_bd ^bb3 ^bb4: // pred: ^bb2 @@ -79,7 +79,7 @@ module @kernel_gemm { ^bb5: // 2 preds: ^bb4, ^bb5 aie.use_lock(%12, Acquire, 1) aie.dma_bd_packet(0, 3) - aie.dma_bd(%14 : memref<32x32xi32>, 0, 1024) + aie.dma_bd(%14 : memref<32x32xi32>) { len = 1024 : i32 } aie.use_lock(%12, Release, 0) aie.next_bd ^bb5 ^bb6: // pred: ^bb4 @@ -134,7 +134,7 @@ module @kernel_gemm { %43 = aie.dma_start(S2MM, 0, ^bb1, ^bb2) ^bb1: // 2 preds: ^bb0, ^bb1 aie.use_lock(%22, Acquire, 0) - aie.dma_bd(%31 : memref<32x32xi32>, 0, 1024) + aie.dma_bd(%31 : memref<32x32xi32>) { len = 1024 : i32 } aie.use_lock(%22, Release, 1) aie.next_bd ^bb1 ^bb2: // pred: ^bb0 @@ -142,20 +142,20 @@ module @kernel_gemm { ^bb3: // 2 preds: ^bb2, ^bb4 aie.use_lock(%24, Acquire, 0) aie.dma_bd_packet(0, 2) - aie.dma_bd(%29 : memref<32x32xi32>, 0, 1024) + aie.dma_bd(%29 : memref<32x32xi32>) { len = 1024 : i32 } aie.use_lock(%24, Release, 1) aie.next_bd ^bb4 ^bb4: // pred: ^bb3 aie.use_lock(%23, Acquire, 0) aie.dma_bd_packet(0, 3) - aie.dma_bd(%30 : memref<32x32xi32>, 0, 1024) + aie.dma_bd(%30 : memref<32x32xi32>) { len = 1024 : i32 } aie.use_lock(%23, Release, 1) aie.next_bd ^bb3 ^bb5: // pred: ^bb2 %45 = aie.dma_start(MM2S, 0, ^bb6, ^bb7) ^bb6: // 2 preds: ^bb5, ^bb6 aie.use_lock(%25, Acquire, 1) - aie.dma_bd(%26 : memref<32x32xi32>, 0, 1024) + aie.dma_bd(%26 : memref<32x32xi32>) { len = 1024 : i32 } aie.use_lock(%25, Release, 0) aie.next_bd ^bb6 ^bb7: // pred: ^bb5 diff --git a/test/unit_tests/aie/23_broadcast_packet/aie.mlir b/test/unit_tests/aie/23_broadcast_packet/aie.mlir index ef92511b22..a0048f4f52 100644 --- a/test/unit_tests/aie/23_broadcast_packet/aie.mlir +++ b/test/unit_tests/aie/23_broadcast_packet/aie.mlir @@ -47,13 +47,13 @@ module @test23_broadcast_packet { ^bd4: aie.use_lock(%lock72_4, "Acquire", 1) aie.dma_bd_packet(0x0, 0x0) - aie.dma_bd(%buf72_0 : memref<1024xi32>, 0, 1024) + aie.dma_bd(%buf72_0 : memref<1024xi32>) { len = 1024 : i32 } aie.use_lock(%lock72_4, "Release", 0) aie.next_bd ^bd5 ^bd5: aie.use_lock(%lock72_5, "Acquire", 1) aie.dma_bd_packet(0x1, 0x1) - aie.dma_bd(%buf72_1 : memref<1024xi32>, 0, 1024) + aie.dma_bd(%buf72_1 : memref<1024xi32>) { len = 1024 : i32 } aie.use_lock(%lock72_5, "Release", 0) aie.next_bd ^bd4 ^end: @@ -65,7 +65,7 @@ module @test23_broadcast_packet { aie.dma_start("S2MM", 0, ^bd0, ^end) ^bd0: aie.use_lock(%lock63_0, Acquire, 0) - aie.dma_bd(%buf63_0 : memref<1024xi32>, 0, 1024) + aie.dma_bd(%buf63_0 : memref<1024xi32>) { len = 1024 : i32 } aie.use_lock(%lock63_0, Release, 1) aie.next_bd ^bd0 ^end: @@ -78,7 +78,7 @@ module @test23_broadcast_packet { aie.dma_start("S2MM", 0, ^bd0, ^end) ^bd0: aie.use_lock(%lock64_0, Acquire, 0) - aie.dma_bd(%buf64_0 : memref<1024xi32>, 0, 1024) + aie.dma_bd(%buf64_0 : memref<1024xi32>) { len = 1024 : i32 } aie.use_lock(%lock64_0, Release, 1) aie.next_bd ^bd0 ^end: @@ -91,7 +91,7 @@ module @test23_broadcast_packet { aie.dma_start("S2MM", 0, ^bd0, ^end) ^bd0: aie.use_lock(%lock73_0, Acquire, 0) - aie.dma_bd(%buf73_0 : memref<1024xi32>, 0, 1024) + aie.dma_bd(%buf73_0 : memref<1024xi32>) { len = 1024 : i32 } aie.use_lock(%lock73_0, Release, 1) aie.next_bd ^bd0 ^end: @@ -104,7 +104,7 @@ module @test23_broadcast_packet { aie.dma_start("S2MM", 0, ^bd0, ^end) ^bd0: aie.use_lock(%lock74_0, Acquire, 0) - aie.dma_bd(%buf74_0 : memref<1024xi32>, 0, 1024) + aie.dma_bd(%buf74_0 : memref<1024xi32>) { len = 1024 : i32 } aie.use_lock(%lock74_0, Release, 1) aie.next_bd ^bd0 ^end: diff --git a/test/unit_tests/aie/23_packet_biShim/aie.mlir b/test/unit_tests/aie/23_packet_biShim/aie.mlir index da6ea5696f..2029540dab 100644 --- a/test/unit_tests/aie/23_packet_biShim/aie.mlir +++ b/test/unit_tests/aie/23_packet_biShim/aie.mlir @@ -28,13 +28,13 @@ module @aie_module { %dstDma = aie.dma_start("MM2S", 0, ^bb3, ^end) ^bb2: aie.use_lock(%10, Acquire, 0) - aie.dma_bd(%11 : memref<256xi32>, 0, 256) + aie.dma_bd(%11 : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%10, Release, 1) aie.next_bd ^bb2 ^bb3: aie.use_lock(%10, Acquire, 1) aie.dma_bd_packet(0x6, 10) - aie.dma_bd(%11 : memref<256xi32>, 0, 256) + aie.dma_bd(%11 : memref<256xi32>) { len = 256 : i32 } aie.next_bd ^bb3 ^end: aie.end @@ -47,12 +47,12 @@ module @aie_module { ^bb0: aie.use_lock(%lock1, Acquire, 1) aie.dma_bd_packet(0x2, 3) - aie.dma_bd(%buf_i : memref<256xi32>, 0, 256) + aie.dma_bd(%buf_i : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%lock1, Release, 0) aie.next_bd ^bb0 ^bb1: aie.use_lock(%lock2, Acquire, 0) - aie.dma_bd(%buf_o : memref<257xi32>, 0, 257) + aie.dma_bd(%buf_o : memref<257xi32>) { len = 257 : i32 } aie.use_lock(%lock2, Release, 1) aie.next_bd ^bb1 ^end: diff --git a/test/unit_tests/aie/29_aie2_nd_dma_even_odd/aie.mlir b/test/unit_tests/aie/29_aie2_nd_dma_even_odd/aie.mlir index 26fbf9db2a..6093793d61 100644 --- a/test/unit_tests/aie/29_aie2_nd_dma_even_odd/aie.mlir +++ b/test/unit_tests/aie/29_aie2_nd_dma_even_odd/aie.mlir @@ -83,7 +83,7 @@ module @tutorial_2b { ^bd0: aie.use_lock(%lock14_done, "AcquireGreaterEqual", 1) ////////// new ////////// - aie.dma_bd(%buf14 : memref<128xi32>, 0, 128, [, , ]) + aie.dma_bd(%buf14 : memref<128xi32>, dims = [, , ]) { len = 128 : i32 } // w, s w, s w, s // dim 2, dim 1, dim 0 aie.use_lock(%lock14_sent, "Release", 1) @@ -96,7 +96,7 @@ module @tutorial_2b { %dstDma = aie.dma_start("S2MM", 0, ^bd0, ^end) ^bd0: aie.use_lock(%lock34_wait, "AcquireGreaterEqual", 1) - aie.dma_bd(%buf34 : memref<128xi32>, 0, 128) + aie.dma_bd(%buf34 : memref<128xi32>) { len = 128 : i32 } aie.use_lock(%lock34_recv, "Release", 1) aie.next_bd ^end ^end: diff --git a/test/unit_tests/aie/30_aie2_nd_dma_transpose_repeat/aie.mlir b/test/unit_tests/aie/30_aie2_nd_dma_transpose_repeat/aie.mlir index 7c037b235e..ccbf58b3c8 100644 --- a/test/unit_tests/aie/30_aie2_nd_dma_transpose_repeat/aie.mlir +++ b/test/unit_tests/aie/30_aie2_nd_dma_transpose_repeat/aie.mlir @@ -62,7 +62,7 @@ module @tutorial_2b { ^bd0: aie.use_lock(%lock14_done, "AcquireGreaterEqual", 1) ////////// new ////////// - aie.dma_bd(%buf14 : memref<128xi32>, 0, 128, [, , ]) + aie.dma_bd(%buf14 : memref<128xi32>, dims = [, , ]) { len = 128 : i32 } // w, s w, s w, s // dim 2, dim 1, dim 0 aie.use_lock(%lock14_sent, "Release", 1) @@ -75,7 +75,7 @@ module @tutorial_2b { %dstDma = aie.dma_start("S2MM", 0, ^bd0, ^end) ^bd0: aie.use_lock(%lock34_wait, "AcquireGreaterEqual", 1) - aie.dma_bd(%buf34 : memref<128xi32>, 0, 128) + aie.dma_bd(%buf34 : memref<128xi32>) { len = 128 : i32 } aie.use_lock(%lock34_recv, "Release", 1) aie.next_bd ^end ^end: diff --git a/test/unit_tests/aie2/05_shim_dma_core_function/aie.mlir b/test/unit_tests/aie2/05_shim_dma_core_function/aie.mlir index defcfd70b4..06b779a4b5 100644 --- a/test/unit_tests/aie2/05_shim_dma_core_function/aie.mlir +++ b/test/unit_tests/aie2/05_shim_dma_core_function/aie.mlir @@ -68,22 +68,22 @@ module @test_chess_05_shim_dma_core_function { %dstDma = aie.dma_start("MM2S", 1, ^bd2, ^end) ^bd0: aie.use_lock(%lock_a_write, AcquireGreaterEqual, 1) - aie.dma_bd(%buf_a_ping : memref<16xi32>, 0, 16) + aie.dma_bd(%buf_a_ping : memref<16xi32>) { len = 16 : i32 } aie.use_lock(%lock_a_read, Release, 1) aie.next_bd ^bd1 ^bd1: aie.use_lock(%lock_a_write, AcquireGreaterEqual, 1) - aie.dma_bd(%buf_a_pong : memref<16xi32>, 0, 16) + aie.dma_bd(%buf_a_pong : memref<16xi32>) { len = 16 : i32 } aie.use_lock(%lock_a_read, Release, 1) aie.next_bd ^bd0 ^bd2: aie.use_lock(%lock_b_read, AcquireGreaterEqual, 1) - aie.dma_bd(%buf_b_ping : memref<16xi32>, 0, 16) + aie.dma_bd(%buf_b_ping : memref<16xi32>) { len = 16 : i32 } aie.use_lock(%lock_b_write, Release, 1) aie.next_bd ^bd3 ^bd3: aie.use_lock(%lock_b_read, AcquireGreaterEqual, 1) - aie.dma_bd(%buf_b_pong : memref<16xi32>, 0, 16) + aie.dma_bd(%buf_b_pong : memref<16xi32>) { len = 16 : i32 } aie.use_lock(%lock_b_write, Release, 1) aie.next_bd ^bd2 ^end: @@ -109,12 +109,12 @@ module @test_chess_05_shim_dma_core_function { aie.dma_start(S2MM, 0, ^bd1, ^end) ^bd0: aie.use_lock(%lock1_read, AcquireGreaterEqual, 1) - aie.dma_bd(%buffer_in : memref<32 x i32>, 0, 32) + aie.dma_bd(%buffer_in : memref<32 x i32>) { len = 32 : i32 } aie.use_lock(%lock1_write, Release, 1) aie.next_bd ^bd0 ^bd1: aie.use_lock(%lock2_write, AcquireGreaterEqual, 1) - aie.dma_bd(%buffer_out : memref<32 x i32>, 0, 32) + aie.dma_bd(%buffer_out : memref<32 x i32>) { len = 32 : i32 } aie.use_lock(%lock2_read, Release, 1) aie.next_bd ^bd1 ^end: diff --git a/test/unit_tests/aie2/07_shim_dma_core_function_with_loop/aie.mlir b/test/unit_tests/aie2/07_shim_dma_core_function_with_loop/aie.mlir index af429efde8..c194dd65e1 100644 --- a/test/unit_tests/aie2/07_shim_dma_core_function_with_loop/aie.mlir +++ b/test/unit_tests/aie2/07_shim_dma_core_function_with_loop/aie.mlir @@ -69,22 +69,22 @@ module @test_chess_04_deprecated_shim_dma_precompiled_kernel{ %dstDma = aie.dma_start("MM2S", 1, ^bd2, ^end) ^bd0: aie.use_lock(%lock_a_ping, "Acquire", 0) - aie.dma_bd(%buf_a_ping : memref<64xi32>, 0, 64) + aie.dma_bd(%buf_a_ping : memref<64xi32>) { len = 64 : i32 } aie.use_lock(%lock_a_ping, "Release", 1) aie.next_bd ^bd1 ^bd1: aie.use_lock(%lock_a_pong, "Acquire", 0) - aie.dma_bd(%buf_a_pong : memref<64xi32>, 0, 64) + aie.dma_bd(%buf_a_pong : memref<64xi32>) { len = 64 : i32 } aie.use_lock(%lock_a_pong, "Release", 1) aie.next_bd ^bd0 ^bd2: aie.use_lock(%lock_b_ping, "Acquire", 1) - aie.dma_bd(%buf_b_ping : memref<64xi32>, 0, 64) + aie.dma_bd(%buf_b_ping : memref<64xi32>) { len = 64 : i32 } aie.use_lock(%lock_b_ping, "Release", 0) aie.next_bd ^bd3 ^bd3: aie.use_lock(%lock_b_pong, "Acquire", 1) - aie.dma_bd(%buf_b_pong : memref<64xi32>, 0, 64) + aie.dma_bd(%buf_b_pong : memref<64xi32>) { len = 64 : i32 } aie.use_lock(%lock_b_pong, "Release", 0) aie.next_bd ^bd2 ^end: @@ -116,12 +116,12 @@ module @test_chess_04_deprecated_shim_dma_precompiled_kernel{ aie.dma_start(S2MM, 0, ^bd1, ^end) ^bd0: aie.use_lock(%lock1, Acquire, 1) - aie.dma_bd(%buffer_in : memref<512 x i32>, 0, 512) + aie.dma_bd(%buffer_in : memref<512 x i32>) { len = 512 : i32 } aie.use_lock(%lock1, Release, 0) aie.next_bd ^bd0 ^bd1: aie.use_lock(%lock2, Acquire, 1) - aie.dma_bd(%buffer_out : memref<512 x i32>, 0, 512) + aie.dma_bd(%buffer_out : memref<512 x i32>) { len = 512 : i32 } aie.use_lock(%lock2, Release, 0) aie.next_bd ^bd1 ^end: diff --git a/test/unit_tests/aie2/08_tile_locks/aie.mlir b/test/unit_tests/aie2/08_tile_locks/aie.mlir index 42636ca265..4bcd3e07cb 100644 --- a/test/unit_tests/aie2/08_tile_locks/aie.mlir +++ b/test/unit_tests/aie2/08_tile_locks/aie.mlir @@ -67,22 +67,22 @@ module @test_chess_08_tile_locks { %dstDma = aie.dma_start("S2MM", 0, ^bd2, ^end) ^bd0: aie.use_lock(%lock_s1, AcquireGreaterEqual, 1) - aie.dma_bd(%buf_l : memref<256xi32>, 0, 2) + aie.dma_bd(%buf_l : memref<256xi32>) { len = 2 : i32 } aie.use_lock(%lock_d1, Release, 1) aie.next_bd ^bd1 ^bd1: aie.use_lock(%lock_s1, AcquireGreaterEqual, 1) - aie.dma_bd(%buf_l : memref<256xi32>, 4, 2) + aie.dma_bd(%buf_l : memref<256xi32>) { offset = 4 : i32, len = 2 : i32 } aie.use_lock(%lock_d1, Release, 1) aie.next_bd ^end ^bd2: aie.use_lock(%lock_s2, AcquireGreaterEqual, 1) - aie.dma_bd(%buf_l : memref<256xi32>, 8, 2) + aie.dma_bd(%buf_l : memref<256xi32>) { offset = 8 : i32, len = 2 : i32 } aie.use_lock(%lock_d2, Release, 1) aie.next_bd ^bd3 ^bd3: aie.use_lock(%lock_s2, AcquireGreaterEqual, 1) - aie.dma_bd(%buf_l : memref<256xi32>, 12, 2) + aie.dma_bd(%buf_l : memref<256xi32>) { offset = 12 : i32, len = 2 : i32 } aie.use_lock(%lock_d2, Release, 1) aie.next_bd ^end ^end: diff --git a/test/unit_tests/aie2/09_memtile_locks/aie.mlir b/test/unit_tests/aie2/09_memtile_locks/aie.mlir index 7b7afe27b8..93981c6e03 100644 --- a/test/unit_tests/aie2/09_memtile_locks/aie.mlir +++ b/test/unit_tests/aie2/09_memtile_locks/aie.mlir @@ -56,7 +56,7 @@ module @test_chess_08_tile_locks { %srcDma = aie.dma_start("MM2S", 0, ^bd0, ^end) ^bd0: aie.use_lock(%lock_d2, AcquireGreaterEqual, 1) - aie.dma_bd(%buf_e : memref<256xi32>, 0, 2) + aie.dma_bd(%buf_e : memref<256xi32>) { len = 2 : i32 } aie.use_lock(%lock_s2, Release, 1) aie.next_bd ^end ^end: @@ -69,22 +69,22 @@ module @test_chess_08_tile_locks { %dstDma = aie.dma_start("S2MM", 0, ^bd2, ^end) ^bd0: aie.use_lock(%lock_s1, AcquireGreaterEqual, 1) - aie.dma_bd(%buf_w : memref<256xi32>, 0, 2) + aie.dma_bd(%buf_w : memref<256xi32>) { len = 2 : i32 } aie.use_lock(%lock_d1, Release, 1) aie.next_bd ^bd1 ^bd1: aie.use_lock(%lock_s1, AcquireGreaterEqual, 1) - aie.dma_bd(%buf_w : memref<256xi32>, 4, 2) + aie.dma_bd(%buf_w : memref<256xi32>) { offset = 4 : i32, len = 2 : i32 } aie.use_lock(%lock_d1, Release, 1) aie.next_bd ^end ^bd2: aie.use_lock(%lock_s2, AcquireGreaterEqual, 1) - aie.dma_bd(%buf_e : memref<256xi32>, 8, 2) + aie.dma_bd(%buf_e : memref<256xi32>) { offset = 8 : i32, len = 2 : i32 } aie.use_lock(%lock_d2, Release, 1) aie.next_bd ^bd3 ^bd3: aie.use_lock(%lock_s2, AcquireGreaterEqual, 1) - aie.dma_bd(%buf_e : memref<256xi32>, 12, 2) + aie.dma_bd(%buf_e : memref<256xi32>) { offset = 12 : i32, len = 2 : i32 } aie.use_lock(%lock_d2, Release, 1) aie.next_bd ^end ^end: diff --git a/test/unit_tests/chess_compiler_tests/04_shim_dma_kernel/aie.mlir b/test/unit_tests/chess_compiler_tests/04_shim_dma_kernel/aie.mlir index eafff791d7..5a5f3b236b 100644 --- a/test/unit_tests/chess_compiler_tests/04_shim_dma_kernel/aie.mlir +++ b/test/unit_tests/chess_compiler_tests/04_shim_dma_kernel/aie.mlir @@ -42,22 +42,22 @@ module @test_chess_04_deprecated_shim_dma_precompiled_kernel{ %dstDma = aie.dma_start("MM2S", 1, ^bd2, ^end) ^bd0: aie.use_lock(%lock_a_ping, "Acquire", 0) - aie.dma_bd(%buf_a_ping : memref<256xi32>, 0, 256) + aie.dma_bd(%buf_a_ping : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%lock_a_ping, "Release", 1) aie.next_bd ^bd1 ^bd1: aie.use_lock(%lock_a_pong, "Acquire", 0) - aie.dma_bd(%buf_a_pong : memref<256xi32>, 0, 256) + aie.dma_bd(%buf_a_pong : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%lock_a_pong, "Release", 1) aie.next_bd ^bd0 ^bd2: aie.use_lock(%lock_b_ping, "Acquire", 1) - aie.dma_bd(%buf_b_ping : memref<256xi32>, 0, 256) + aie.dma_bd(%buf_b_ping : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%lock_b_ping, "Release", 0) aie.next_bd ^bd3 ^bd3: aie.use_lock(%lock_b_pong, "Acquire", 1) - aie.dma_bd(%buf_b_pong : memref<256xi32>, 0, 256) + aie.dma_bd(%buf_b_pong : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%lock_b_pong, "Release", 0) aie.next_bd ^bd2 ^end: @@ -81,12 +81,12 @@ module @test_chess_04_deprecated_shim_dma_precompiled_kernel{ aie.dma_start(S2MM, 0, ^bd1, ^end) ^bd0: aie.use_lock(%lock1, Acquire, 1) - aie.dma_bd(%buffer_in : memref<512 x i32>, 0, 512) + aie.dma_bd(%buffer_in : memref<512 x i32>) { len = 512 : i32 } aie.use_lock(%lock1, Release, 0) aie.next_bd ^bd0 ^bd1: aie.use_lock(%lock2, Acquire, 1) - aie.dma_bd(%buffer_out : memref<512 x i32>, 0, 512) + aie.dma_bd(%buffer_out : memref<512 x i32>) { len = 512 : i32 } aie.use_lock(%lock2, Release, 0) aie.next_bd ^bd1 ^end: diff --git a/test/unit_tests/chess_compiler_tests/05_shim_dma_core_function/aie.mlir b/test/unit_tests/chess_compiler_tests/05_shim_dma_core_function/aie.mlir index 08d6a5c37a..48a7f5722a 100644 --- a/test/unit_tests/chess_compiler_tests/05_shim_dma_core_function/aie.mlir +++ b/test/unit_tests/chess_compiler_tests/05_shim_dma_core_function/aie.mlir @@ -67,22 +67,22 @@ module @test_chess_04_deprecated_shim_dma_precompiled_kernel{ %dstDma = aie.dma_start("MM2S", 1, ^bd2, ^end) ^bd0: aie.use_lock(%lock_a_ping, "Acquire", 0) - aie.dma_bd(%buf_a_ping : memref<256xi32>, 0, 256) + aie.dma_bd(%buf_a_ping : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%lock_a_ping, "Release", 1) aie.next_bd ^bd1 ^bd1: aie.use_lock(%lock_a_pong, "Acquire", 0) - aie.dma_bd(%buf_a_pong : memref<256xi32>, 0, 256) + aie.dma_bd(%buf_a_pong : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%lock_a_pong, "Release", 1) aie.next_bd ^bd0 ^bd2: aie.use_lock(%lock_b_ping, "Acquire", 1) - aie.dma_bd(%buf_b_ping : memref<256xi32>, 0, 256) + aie.dma_bd(%buf_b_ping : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%lock_b_ping, "Release", 0) aie.next_bd ^bd3 ^bd3: aie.use_lock(%lock_b_pong, "Acquire", 1) - aie.dma_bd(%buf_b_pong : memref<256xi32>, 0, 256) + aie.dma_bd(%buf_b_pong : memref<256xi32>) { len = 256 : i32 } aie.use_lock(%lock_b_pong, "Release", 0) aie.next_bd ^bd2 ^end: @@ -106,12 +106,12 @@ module @test_chess_04_deprecated_shim_dma_precompiled_kernel{ aie.dma_start(S2MM, 0, ^bd1, ^end) ^bd0: aie.use_lock(%lock1, Acquire, 1) - aie.dma_bd(%buffer_in : memref<512 x i32>, 0, 512) + aie.dma_bd(%buffer_in : memref<512 x i32>) { len = 512 : i32 } aie.use_lock(%lock1, Release, 0) aie.next_bd ^bd0 ^bd1: aie.use_lock(%lock2, Acquire, 1) - aie.dma_bd(%buffer_out : memref<512 x i32>, 0, 512) + aie.dma_bd(%buffer_out : memref<512 x i32>) { len = 512 : i32 } aie.use_lock(%lock2, Release, 0) aie.next_bd ^bd1 ^end: diff --git a/test/unit_tests/chess_compiler_tests/07_shim_dma_core_function_with_loop/aie.mlir b/test/unit_tests/chess_compiler_tests/07_shim_dma_core_function_with_loop/aie.mlir index 761e96fe80..757aae184d 100644 --- a/test/unit_tests/chess_compiler_tests/07_shim_dma_core_function_with_loop/aie.mlir +++ b/test/unit_tests/chess_compiler_tests/07_shim_dma_core_function_with_loop/aie.mlir @@ -73,22 +73,22 @@ module @test_chess_04_deprecated_shim_dma_precompiled_kernel{ %dstDma = aie.dma_start("MM2S", 1, ^bd2, ^end) ^bd0: aie.use_lock(%lock_a_ping, "Acquire", 0) - aie.dma_bd(%buf_a_ping : memref<64xi32>, 0, 64) + aie.dma_bd(%buf_a_ping : memref<64xi32>) { len = 64 : i32 } aie.use_lock(%lock_a_ping, "Release", 1) aie.next_bd ^bd1 ^bd1: aie.use_lock(%lock_a_pong, "Acquire", 0) - aie.dma_bd(%buf_a_pong : memref<64xi32>, 0, 64) + aie.dma_bd(%buf_a_pong : memref<64xi32>) { len = 64 : i32 } aie.use_lock(%lock_a_pong, "Release", 1) aie.next_bd ^bd0 ^bd2: aie.use_lock(%lock_b_ping, "Acquire", 1) - aie.dma_bd(%buf_b_ping : memref<64xi32>, 0, 64) + aie.dma_bd(%buf_b_ping : memref<64xi32>) { len = 64 : i32 } aie.use_lock(%lock_b_ping, "Release", 0) aie.next_bd ^bd3 ^bd3: aie.use_lock(%lock_b_pong, "Acquire", 1) - aie.dma_bd(%buf_b_pong : memref<64xi32>, 0, 64) + aie.dma_bd(%buf_b_pong : memref<64xi32>) { len = 64 : i32 } aie.use_lock(%lock_b_pong, "Release", 0) aie.next_bd ^bd2 ^end: @@ -112,12 +112,12 @@ module @test_chess_04_deprecated_shim_dma_precompiled_kernel{ aie.dma_start(S2MM, 0, ^bd1, ^end) ^bd0: aie.use_lock(%lock1, Acquire, 1) - aie.dma_bd(%buffer_in : memref<512 x i32>, 0, 512) + aie.dma_bd(%buffer_in : memref<512 x i32>) { len = 512 : i32 } aie.use_lock(%lock1, Release, 0) aie.next_bd ^bd0 ^bd1: aie.use_lock(%lock2, Acquire, 1) - aie.dma_bd(%buffer_out : memref<512 x i32>, 0, 512) + aie.dma_bd(%buffer_out : memref<512 x i32>) { len = 512 : i32 } aie.use_lock(%lock2, Release, 0) aie.next_bd ^bd1 ^end: diff --git a/test/unit_tests/chess_compiler_tests/08_tile_locks/aie.mlir b/test/unit_tests/chess_compiler_tests/08_tile_locks/aie.mlir index 22463d9070..ed7fa68457 100644 --- a/test/unit_tests/chess_compiler_tests/08_tile_locks/aie.mlir +++ b/test/unit_tests/chess_compiler_tests/08_tile_locks/aie.mlir @@ -62,22 +62,22 @@ module @test_chess_08_tile_locks { %dstDma = aie.dma_start("S2MM", 0, ^bd2, ^end) ^bd0: aie.use_lock(%lock_e, Acquire, 0) - aie.dma_bd(%buf_l : memref<256xi32>, 0, 2) + aie.dma_bd(%buf_l : memref<256xi32>) { len = 2 : i32 } aie.use_lock(%lock_e, Release, 1) aie.next_bd ^bd1 ^bd1: aie.use_lock(%lock_l, Acquire, 0) - aie.dma_bd(%buf_l : memref<256xi32>, 4, 2) + aie.dma_bd(%buf_l : memref<256xi32>) { offset = 4 : i32, len = 2 : i32 } aie.use_lock(%lock_l, Release, 1) aie.next_bd ^end ^bd2: aie.use_lock(%lock_n, Acquire, 0) - aie.dma_bd(%buf_l : memref<256xi32>, 8, 2) + aie.dma_bd(%buf_l : memref<256xi32>) { offset = 8 : i32, len = 2 : i32 } aie.use_lock(%lock_n, Release, 1) aie.next_bd ^bd3 ^bd3: aie.use_lock(%lock_s, Acquire, 0) - aie.dma_bd(%buf_l : memref<256xi32>, 12, 2) + aie.dma_bd(%buf_l : memref<256xi32>) { offset = 12 : i32, len = 2 : i32 } aie.use_lock(%lock_s, Release, 1) aie.next_bd ^end ^end: diff --git a/test/unit_tests/chess_compiler_tests_aie2/04_shim_dma_kernel/aie.mlir b/test/unit_tests/chess_compiler_tests_aie2/04_shim_dma_kernel/aie.mlir index 90abf7d33a..fe7a4485fa 100644 --- a/test/unit_tests/chess_compiler_tests_aie2/04_shim_dma_kernel/aie.mlir +++ b/test/unit_tests/chess_compiler_tests_aie2/04_shim_dma_kernel/aie.mlir @@ -48,22 +48,22 @@ module @test_chess_04_deprecated_shim_dma_precompiled_kernel{ %dstDma = aie.dma_start("MM2S", 1, ^bd2, ^end) ^bd0: aie.use_lock(%lock_a_write, AcquireGreaterEqual, 1) - aie.dma_bd(%buf_a_ping : memref<16xi32>, 0, 16) + aie.dma_bd(%buf_a_ping : memref<16xi32>) { len = 16 : i32 } aie.use_lock(%lock_a_read, Release, 1) aie.next_bd ^bd1 ^bd1: aie.use_lock(%lock_a_write, AcquireGreaterEqual, 1) - aie.dma_bd(%buf_a_pong : memref<16xi32>, 0, 16) + aie.dma_bd(%buf_a_pong : memref<16xi32>) { len = 16 : i32 } aie.use_lock(%lock_a_read, Release, 1) aie.next_bd ^bd0 ^bd2: aie.use_lock(%lock_b_read, AcquireGreaterEqual, 1) - aie.dma_bd(%buf_b_ping : memref<16xi32>, 0, 16) + aie.dma_bd(%buf_b_ping : memref<16xi32>) { len = 16 : i32 } aie.use_lock(%lock_b_write, Release, 1) aie.next_bd ^bd3 ^bd3: aie.use_lock(%lock_b_read, AcquireGreaterEqual, 1) - aie.dma_bd(%buf_b_pong : memref<16xi32>, 0, 16) + aie.dma_bd(%buf_b_pong : memref<16xi32>) { len = 16 : i32 } aie.use_lock(%lock_b_write, Release, 1) aie.next_bd ^bd2 ^end: @@ -89,12 +89,12 @@ module @test_chess_04_deprecated_shim_dma_precompiled_kernel{ aie.dma_start(S2MM, 0, ^bd1, ^end) ^bd0: aie.use_lock(%lock1_read, AcquireGreaterEqual, 1) - aie.dma_bd(%buffer_in : memref<32 x i32>, 0, 32) + aie.dma_bd(%buffer_in : memref<32 x i32>) { len = 32 : i32 } aie.use_lock(%lock1_write, Release, 1) aie.next_bd ^bd0 ^bd1: aie.use_lock(%lock2_write, AcquireGreaterEqual, 1) - aie.dma_bd(%buffer_out : memref<32 x i32>, 0, 32) + aie.dma_bd(%buffer_out : memref<32 x i32>) { len = 32 : i32 } aie.use_lock(%lock2_read, Release, 1) aie.next_bd ^bd1 ^end: diff --git a/test/unit_tests/chess_compiler_tests_aie2/05_shim_dma_core_function/aie.mlir b/test/unit_tests/chess_compiler_tests_aie2/05_shim_dma_core_function/aie.mlir index fe1a25a3af..2dce858e84 100644 --- a/test/unit_tests/chess_compiler_tests_aie2/05_shim_dma_core_function/aie.mlir +++ b/test/unit_tests/chess_compiler_tests_aie2/05_shim_dma_core_function/aie.mlir @@ -71,22 +71,22 @@ module @test_chess_05_shim_dma_core_function { %dstDma = aie.dma_start("MM2S", 1, ^bd2, ^end) ^bd0: aie.use_lock(%lock_a_write, AcquireGreaterEqual, 1) - aie.dma_bd(%buf_a_ping : memref<16xi32>, 0, 16) + aie.dma_bd(%buf_a_ping : memref<16xi32>) { len = 16 : i32 } aie.use_lock(%lock_a_read, Release, 1) aie.next_bd ^bd1 ^bd1: aie.use_lock(%lock_a_write, AcquireGreaterEqual, 1) - aie.dma_bd(%buf_a_pong : memref<16xi32>, 0, 16) + aie.dma_bd(%buf_a_pong : memref<16xi32>) { len = 16 : i32 } aie.use_lock(%lock_a_read, Release, 1) aie.next_bd ^bd0 ^bd2: aie.use_lock(%lock_b_read, AcquireGreaterEqual, 1) - aie.dma_bd(%buf_b_ping : memref<16xi32>, 0, 16) + aie.dma_bd(%buf_b_ping : memref<16xi32>) { len = 16 : i32 } aie.use_lock(%lock_b_write, Release, 1) aie.next_bd ^bd3 ^bd3: aie.use_lock(%lock_b_read, AcquireGreaterEqual, 1) - aie.dma_bd(%buf_b_pong : memref<16xi32>, 0, 16) + aie.dma_bd(%buf_b_pong : memref<16xi32>) { len = 16 : i32 } aie.use_lock(%lock_b_write, Release, 1) aie.next_bd ^bd2 ^end: @@ -112,12 +112,12 @@ module @test_chess_05_shim_dma_core_function { aie.dma_start(S2MM, 0, ^bd1, ^end) ^bd0: aie.use_lock(%lock1_read, AcquireGreaterEqual, 1) - aie.dma_bd(%buffer_in : memref<32 x i32>, 0, 32) + aie.dma_bd(%buffer_in : memref<32 x i32>) { len = 32 : i32 } aie.use_lock(%lock1_write, Release, 1) aie.next_bd ^bd0 ^bd1: aie.use_lock(%lock2_write, AcquireGreaterEqual, 1) - aie.dma_bd(%buffer_out : memref<32 x i32>, 0, 32) + aie.dma_bd(%buffer_out : memref<32 x i32>) { len = 32 : i32 } aie.use_lock(%lock2_read, Release, 1) aie.next_bd ^bd1 ^end: diff --git a/test/unit_tests/chess_compiler_tests_aie2/07_shim_dma_core_function_with_loop/aie.mlir b/test/unit_tests/chess_compiler_tests_aie2/07_shim_dma_core_function_with_loop/aie.mlir index 053a508881..832e1c88a2 100644 --- a/test/unit_tests/chess_compiler_tests_aie2/07_shim_dma_core_function_with_loop/aie.mlir +++ b/test/unit_tests/chess_compiler_tests_aie2/07_shim_dma_core_function_with_loop/aie.mlir @@ -72,22 +72,22 @@ module @test_chess_04_deprecated_shim_dma_precompiled_kernel{ %dstDma = aie.dma_start("MM2S", 1, ^bd2, ^end) ^bd0: aie.use_lock(%lock_a_ping, "Acquire", 0) - aie.dma_bd(%buf_a_ping : memref<64xi32>, 0, 64) + aie.dma_bd(%buf_a_ping : memref<64xi32>) { len = 64 : i32 } aie.use_lock(%lock_a_ping, "Release", 1) aie.next_bd ^bd1 ^bd1: aie.use_lock(%lock_a_pong, "Acquire", 0) - aie.dma_bd(%buf_a_pong : memref<64xi32>, 0, 64) + aie.dma_bd(%buf_a_pong : memref<64xi32>) { len = 64 : i32 } aie.use_lock(%lock_a_pong, "Release", 1) aie.next_bd ^bd0 ^bd2: aie.use_lock(%lock_b_ping, "Acquire", 1) - aie.dma_bd(%buf_b_ping : memref<64xi32>, 0, 64) + aie.dma_bd(%buf_b_ping : memref<64xi32>) { len = 64 : i32 } aie.use_lock(%lock_b_ping, "Release", 0) aie.next_bd ^bd3 ^bd3: aie.use_lock(%lock_b_pong, "Acquire", 1) - aie.dma_bd(%buf_b_pong : memref<64xi32>, 0, 64) + aie.dma_bd(%buf_b_pong : memref<64xi32>) { len = 64 : i32 } aie.use_lock(%lock_b_pong, "Release", 0) aie.next_bd ^bd2 ^end: @@ -119,12 +119,12 @@ module @test_chess_04_deprecated_shim_dma_precompiled_kernel{ aie.dma_start(S2MM, 0, ^bd1, ^end) ^bd0: aie.use_lock(%lock1, Acquire, 1) - aie.dma_bd(%buffer_in : memref<512 x i32>, 0, 512) + aie.dma_bd(%buffer_in : memref<512 x i32>) { len = 512 : i32 } aie.use_lock(%lock1, Release, 0) aie.next_bd ^bd0 ^bd1: aie.use_lock(%lock2, Acquire, 1) - aie.dma_bd(%buffer_out : memref<512 x i32>, 0, 512) + aie.dma_bd(%buffer_out : memref<512 x i32>) { len = 512 : i32 } aie.use_lock(%lock2, Release, 0) aie.next_bd ^bd1 ^end: diff --git a/test/unit_tests/chess_compiler_tests_aie2/08_tile_locks/aie.mlir b/test/unit_tests/chess_compiler_tests_aie2/08_tile_locks/aie.mlir index 24ce79bbaf..d96056525a 100644 --- a/test/unit_tests/chess_compiler_tests_aie2/08_tile_locks/aie.mlir +++ b/test/unit_tests/chess_compiler_tests_aie2/08_tile_locks/aie.mlir @@ -69,22 +69,22 @@ module @test_chess_08_tile_locks { %dstDma = aie.dma_start("S2MM", 0, ^bd2, ^end) ^bd0: aie.use_lock(%lock_s1, AcquireGreaterEqual, 1) - aie.dma_bd(%buf_l : memref<256xi32>, 0, 2) + aie.dma_bd(%buf_l : memref<256xi32>) { len = 2 : i32 } aie.use_lock(%lock_d1, Release, 1) aie.next_bd ^bd1 ^bd1: aie.use_lock(%lock_s1, AcquireGreaterEqual, 1) - aie.dma_bd(%buf_l : memref<256xi32>, 4, 2) + aie.dma_bd(%buf_l : memref<256xi32>) { offset = 4 : i32, len = 2 : i32 } aie.use_lock(%lock_d1, Release, 1) aie.next_bd ^end ^bd2: aie.use_lock(%lock_s2, AcquireGreaterEqual, 1) - aie.dma_bd(%buf_l : memref<256xi32>, 8, 2) + aie.dma_bd(%buf_l : memref<256xi32>) { offset = 8 : i32, len = 2 : i32 } aie.use_lock(%lock_d2, Release, 1) aie.next_bd ^bd3 ^bd3: aie.use_lock(%lock_s2, AcquireGreaterEqual, 1) - aie.dma_bd(%buf_l : memref<256xi32>, 12, 2) + aie.dma_bd(%buf_l : memref<256xi32>) { offset = 12 : i32, len = 2 : i32 } aie.use_lock(%lock_d2, Release, 1) aie.next_bd ^end ^end: diff --git a/test/unit_tests/chess_compiler_tests_aie2/09_memtile_locks/aie.mlir b/test/unit_tests/chess_compiler_tests_aie2/09_memtile_locks/aie.mlir index b0c33ac22b..29b4ece779 100644 --- a/test/unit_tests/chess_compiler_tests_aie2/09_memtile_locks/aie.mlir +++ b/test/unit_tests/chess_compiler_tests_aie2/09_memtile_locks/aie.mlir @@ -58,7 +58,7 @@ module @test_chess_08_tile_locks { %srcDma = aie.dma_start("MM2S", 0, ^bd0, ^end) ^bd0: aie.use_lock(%lock_d2, AcquireGreaterEqual, 1) - aie.dma_bd(%buf_e : memref<256xi32>, 0, 2) + aie.dma_bd(%buf_e : memref<256xi32>) { len = 2 : i32 } aie.use_lock(%lock_s2, Release, 1) aie.next_bd ^end ^end: @@ -71,22 +71,22 @@ module @test_chess_08_tile_locks { %dstDma = aie.dma_start("S2MM", 0, ^bd2, ^end) ^bd0: aie.use_lock(%lock_s1, AcquireGreaterEqual, 1) - aie.dma_bd(%buf_w : memref<256xi32>, 0, 2) + aie.dma_bd(%buf_w : memref<256xi32>) { len = 2 : i32 } aie.use_lock(%lock_d1, Release, 1) aie.next_bd ^bd1 ^bd1: aie.use_lock(%lock_s1, AcquireGreaterEqual, 1) - aie.dma_bd(%buf_w : memref<256xi32>, 4, 2) + aie.dma_bd(%buf_w : memref<256xi32>) { offset = 4 : i32, len = 2 : i32 } aie.use_lock(%lock_d1, Release, 1) aie.next_bd ^end ^bd2: aie.use_lock(%lock_s2, AcquireGreaterEqual, 1) - aie.dma_bd(%buf_e : memref<256xi32>, 8, 2) + aie.dma_bd(%buf_e : memref<256xi32>) { offset = 8 : i32, len = 2 : i32 } aie.use_lock(%lock_d2, Release, 1) aie.next_bd ^bd3 ^bd3: aie.use_lock(%lock_s2, AcquireGreaterEqual, 1) - aie.dma_bd(%buf_e : memref<256xi32>, 12, 2) + aie.dma_bd(%buf_e : memref<256xi32>) { offset = 12 : i32, len = 2 : i32 } aie.use_lock(%lock_d2, Release, 1) aie.next_bd ^end ^end: diff --git a/tutorials/tutorial-4/flow/README.md b/tutorials/tutorial-4/flow/README.md index 3d32d3b4c7..74ac877006 100644 --- a/tutorials/tutorial-4/flow/README.md +++ b/tutorials/tutorial-4/flow/README.md @@ -54,7 +54,7 @@ There are 2 tile DMAs connected to the local switchbox, each with a read and wri %dma1 = AIE.dma_start("MM2S", 0, ^bd0, ^end) ^bd0: AIE.use_lock(%lock14_6, "Acquire", 1) - AIE.dma_bd(%buf14: memref<256xi32>, 0, 256) + aie.dma_bd(%buf14: memref<256xi32>) { offset = 0 : i32, len = 256 : i32 } AIE.use_lock(%lock14_6, "Release", 0) AIE.next_bd ^end ^end: @@ -105,22 +105,22 @@ In a common scenario where we may declare 2x DMAs (1x MM2S, 1x S2MM), each with %dma2 = AIE.dma_start("S2MM", 0, ^bd3, ^end) ^bd0: AIE.use_lock(%lock14_6, "Acquire", 0) - AIE.dma_bd(%buf14_1: memref<256xi32>, 0, 256) + aie.dma_bd(%buf14_1: memref<256xi32>) { offset = 0 : i32, len = 256 : i32 } AIE.use_lock(%lock14_6, "Release", 1) AIE.next_bd ^bd1 ^bd1: AIE.use_lock(%lock14_7, "Acquire", 0) - AIE.dma_bd(%buf14_2: memref<256xi32>, 0, 256) + aie.dma_bd(%buf14_2: memref<256xi32>) { offset = 0 : i32, len = 256 : i32 } AIE.use_lock(%lock14_7, "Release", 1) AIE.next_bd ^bd0 ^bd3: AIE.use_lock(%lock14_10, "Acquire", 0) - AIE.dma_bd(%buf14_3: memref<256xi32>, 0, 256) + aie.dma_bd(%buf14_3: memref<256xi32>) { offset = 0 : i32, len = 256 : i32 } AIE.use_lock(%lock14_10, "Release", 1) AIE.next_bd ^bd4 ^bd4: AIE.use_lock(%lock14_11, "Acquire", 0) - AIE.dma_bd(%buf14_4: memref<256xi32>, 0, 256) + aie.dma_bd(%buf14_4: memref<256xi32>) { offset = 0 : i32, len = 256 : i32 } AIE.use_lock(%lock14_11, "Release", 1) AIE.next_bd ^bd3 ^end: diff --git a/tutorials/tutorial-4/flow/aie.mlir b/tutorials/tutorial-4/flow/aie.mlir index e18769c361..436f0a209f 100755 --- a/tutorials/tutorial-4/flow/aie.mlir +++ b/tutorials/tutorial-4/flow/aie.mlir @@ -57,7 +57,7 @@ module @tutorial_4 { aie.dma_start("MM2S", 0, ^bd0, ^end) ^bd0: aie.use_lock(%lock14_6, Acquire, 1) - aie.dma_bd(%buf14 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf14 : memref<256xi32>) { offset = 0 : i32, len = 256 : i32 } aie.use_lock(%lock14_6, Release, 0) aie.next_bd ^end ^end: @@ -102,7 +102,7 @@ module @tutorial_4 { // 0 - offset of transfer // 256 - length of transfer // 0 - A/B mode enable (default is disabled) - aie.dma_bd(%buf34 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf34 : memref<256xi32>) { offset = 0 : i32, len = 256 : i32 } aie.use_lock(%lock34_7, Release, 1) aie.next_bd ^end ^end: diff --git a/tutorials/tutorial-4/flow/answers/aie_q5.mlir b/tutorials/tutorial-4/flow/answers/aie_q5.mlir index 95ee3896a1..a1a939cc50 100644 --- a/tutorials/tutorial-4/flow/answers/aie_q5.mlir +++ b/tutorials/tutorial-4/flow/answers/aie_q5.mlir @@ -56,7 +56,7 @@ module @tutorial_4 { aie.dma_start("MM2S", 0, ^bd0, ^end) ^bd0: aie.use_lock(%lock14_6, Acquire, 1) - aie.dma_bd(%buf14 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf14 : memref<256xi32>) { offset = 0 : i32, len = 256 : i32 } aie.use_lock(%lock14_6, Release, 0) aie.next_bd ^bd0 ^end: diff --git a/tutorials/tutorial-6/README.md b/tutorials/tutorial-6/README.md index d2deb07ab9..7b4f169721 100755 --- a/tutorials/tutorial-6/README.md +++ b/tutorials/tutorial-6/README.md @@ -64,7 +64,7 @@ An example of this inside a BD definition would be: ^bd0: AIE.use_lock(%lock14_6, Acquire, 1) AIE.dma_bd_packet(0x4, 0xD) - AIE.dma_bd(%buf14 : memref<256xi32>, 0, 256) + aie.dma_bd(%buf14 : memref<256xi32>) { offset = 0 : i32, len = 256 : i32 } AIE.use_lock(%lock14_6, Release, 0) cf.br ^end ```