diff --git a/include/aie/Dialect/AIE/IR/AIEAttrs.td b/include/aie/Dialect/AIE/IR/AIEAttrs.td index 0c784211fa..42222c9687 100644 --- a/include/aie/Dialect/AIE/IR/AIEAttrs.td +++ b/include/aie/Dialect/AIE/IR/AIEAttrs.td @@ -49,7 +49,7 @@ def EastWire: I32EnumAttrCase<"East", 6>; def PLIOWire: I32EnumAttrCase<"PLIO", 7>; def NOCWire: I32EnumAttrCase<"NOC", 8>; def TraceWire: I32EnumAttrCase<"Trace", 9>; -def ControlWire: I32EnumAttrCase<"Ctrl", 10>; +def ControlWire: I32EnumAttrCase<"Control", 10>; def WireBundle: I32EnumAttr<"WireBundle", "Bundle of wires", [ diff --git a/include/aie/Targets/AIERT.h b/include/aie/Targets/AIERT.h index bd655e2b91..0ee0542d59 100644 --- a/include/aie/Targets/AIERT.h +++ b/include/aie/Targets/AIERT.h @@ -77,7 +77,7 @@ static const std::map WIRE_BUNDLE_TO_STRM_SW_PORT_TYPE = { {xilinx::AIE::WireBundle::Core, StrmSwPortType::CORE}, {xilinx::AIE::WireBundle::DMA, StrmSwPortType::DMA}, - {xilinx::AIE::WireBundle::Ctrl, StrmSwPortType::CTRL}, + {xilinx::AIE::WireBundle::Control, StrmSwPortType::CTRL}, {xilinx::AIE::WireBundle::FIFO, StrmSwPortType::FIFO}, {xilinx::AIE::WireBundle::South, StrmSwPortType::SOUTH}, {xilinx::AIE::WireBundle::West, StrmSwPortType::WEST}, diff --git a/lib/Dialect/AIE/IR/AIETargetModel.cpp b/lib/Dialect/AIE/IR/AIETargetModel.cpp index e74152afae..6577447722 100644 --- a/lib/Dialect/AIE/IR/AIETargetModel.cpp +++ b/lib/Dialect/AIE/IR/AIETargetModel.cpp @@ -127,7 +127,7 @@ AIE1TargetModel::getNumDestSwitchboxConnections(int col, int row, return 0; return 4; } - case WireBundle::Ctrl: + case WireBundle::Control: return isShimNOCTile(col, row) ? 1 : 0; default: return 0; @@ -155,7 +155,7 @@ AIE1TargetModel::getNumDestSwitchboxConnections(int col, int row, return 0; return 4; } - case WireBundle::Ctrl: + case WireBundle::Control: return 1; default: return 0; @@ -185,7 +185,7 @@ AIE1TargetModel::getNumSourceSwitchboxConnections(int col, int row, } case WireBundle::Trace: return 1; - case WireBundle::Ctrl: + case WireBundle::Control: return isShimNOCTile(col, row) ? 1 : 0; default: return 0; @@ -215,7 +215,7 @@ AIE1TargetModel::getNumSourceSwitchboxConnections(int col, int row, } case WireBundle::Trace: return 2; - case WireBundle::Ctrl: + case WireBundle::Control: return 1; default: return 0; @@ -376,7 +376,7 @@ AIE2TargetModel::getNumDestSwitchboxConnections(int col, int row, return 6; case WireBundle::South: return 4; - case WireBundle::Ctrl: + case WireBundle::Control: return 1; default: return 0; @@ -400,7 +400,7 @@ AIE2TargetModel::getNumDestSwitchboxConnections(int col, int row, return 0; return 4; } - case WireBundle::Ctrl: + case WireBundle::Control: return isShimNOCTile(col, row) ? 1 : 0; default: return 0; @@ -430,7 +430,7 @@ AIE2TargetModel::getNumDestSwitchboxConnections(int col, int row, return 0; return 4; } - case WireBundle::Ctrl: + case WireBundle::Control: return 1; default: return 0; @@ -449,7 +449,7 @@ AIE2TargetModel::getNumSourceSwitchboxConnections(int col, int row, case WireBundle::South: return 6; case WireBundle::Trace: - case WireBundle::Ctrl: + case WireBundle::Control: return 1; default: return 0; @@ -475,7 +475,7 @@ AIE2TargetModel::getNumSourceSwitchboxConnections(int col, int row, } case WireBundle::Trace: return 1; - case WireBundle::Ctrl: + case WireBundle::Control: return isShimNOCTile(col, row) ? 1 : 0; default: return 0; @@ -509,7 +509,7 @@ AIE2TargetModel::getNumSourceSwitchboxConnections(int col, int row, case WireBundle::Trace: // Port 0: core trace. Port 1: memory trace. return 2; - case WireBundle::Ctrl: + case WireBundle::Control: return 1; default: return 0; @@ -577,18 +577,18 @@ bool AIE2TargetModel::isLegalTileConnection(int col, int row, if (srcBundle == WireBundle::DMA) { if (dstBundle == WireBundle::DMA) return srcChan == dstChan; - if (isBundleInList(dstBundle, {WireBundle::Ctrl, WireBundle::South, + if (isBundleInList(dstBundle, {WireBundle::Control, WireBundle::South, WireBundle::North})) return true; } - if (srcBundle == WireBundle::Ctrl) { + if (srcBundle == WireBundle::Control) { if (dstBundle == WireBundle::DMA) return dstChan == 5; if (isBundleInList(dstBundle, {WireBundle::South, WireBundle::North})) return true; } if (isBundleInList(srcBundle, {WireBundle::South, WireBundle::North})) { - if (isBundleInList(dstBundle, {WireBundle::DMA, WireBundle::Ctrl})) + if (isBundleInList(dstBundle, {WireBundle::DMA, WireBundle::Control})) return true; if (isBundleInList(dstBundle, {WireBundle::South, WireBundle::North})) return srcChan == dstChan; @@ -602,10 +602,10 @@ bool AIE2TargetModel::isLegalTileConnection(int col, int row, } // Shimtile else if (isShimNOCorPLTile(col, row)) { - if (srcBundle == WireBundle::Ctrl) - return dstBundle != WireBundle::Ctrl; + if (srcBundle == WireBundle::Control) + return dstBundle != WireBundle::Control; if (isBundleInList(srcBundle, {WireBundle::FIFO, WireBundle::South})) - return isBundleInList(dstBundle, {WireBundle::Ctrl, WireBundle::FIFO, + return isBundleInList(dstBundle, {WireBundle::Control, WireBundle::FIFO, WireBundle::South, WireBundle::West, WireBundle::North, WireBundle::East}); if (isBundleInList(srcBundle, @@ -613,7 +613,7 @@ bool AIE2TargetModel::isLegalTileConnection(int col, int row, return (srcBundle == dstBundle) ? (srcChan == dstChan) : isBundleInList(dstBundle, - {WireBundle::Ctrl, WireBundle::FIFO, + {WireBundle::Control, WireBundle::FIFO, WireBundle::South, WireBundle::West, WireBundle::North, WireBundle::East}); if (srcBundle == WireBundle::Trace) { @@ -628,15 +628,15 @@ bool AIE2TargetModel::isLegalTileConnection(int col, int row, if (isBundleInList(srcBundle, {WireBundle::DMA, WireBundle::FIFO, WireBundle::South, WireBundle::West, WireBundle::North, WireBundle::East})) - if (isBundleInList(dstBundle, - {WireBundle::Core, WireBundle::DMA, WireBundle::Ctrl, - WireBundle::FIFO, WireBundle::South, WireBundle::West, - WireBundle::North, WireBundle::East})) + if (isBundleInList(dstBundle, {WireBundle::Core, WireBundle::DMA, + WireBundle::Control, WireBundle::FIFO, + WireBundle::South, WireBundle::West, + WireBundle::North, WireBundle::East})) return (srcBundle == dstBundle) ? (srcChan == dstChan) : true; if (srcBundle == WireBundle::Core) return dstBundle != WireBundle::Core; - if (srcBundle == WireBundle::Ctrl) - return dstBundle != WireBundle::Ctrl && dstBundle != WireBundle::DMA; + if (srcBundle == WireBundle::Control) + return dstBundle != WireBundle::Control && dstBundle != WireBundle::DMA; if (srcBundle == WireBundle::Trace) { if (dstBundle == WireBundle::DMA) return dstChan == 0; diff --git a/lib/Dialect/AIE/Transforms/AIEGenerateColumnControlOverlay.cpp b/lib/Dialect/AIE/Transforms/AIEGenerateColumnControlOverlay.cpp index 449d1b93ab..a1161e1835 100644 --- a/lib/Dialect/AIE/Transforms/AIEGenerateColumnControlOverlay.cpp +++ b/lib/Dialect/AIE/Transforms/AIEGenerateColumnControlOverlay.cpp @@ -221,7 +221,7 @@ struct AIEGenerateColumnControlOverlayPass generatePacketFlowsForControl( builder, device, shimTile, AIE::WireBundle::South, tilesOnCol, - AIE::WireBundle::Ctrl, 0, tileIDMap, false); + AIE::WireBundle::Control, 0, tileIDMap, false); } if (clRouteShimDmaToTileCTRL) { // Get all tile ops on column col @@ -234,7 +234,7 @@ struct AIEGenerateColumnControlOverlayPass generatePacketFlowsForControl( builder, device, shimTile, AIE::WireBundle::DMA, tilesOnCol, - AIE::WireBundle::Ctrl, 0, tileIDMap, true); + AIE::WireBundle::Control, 0, tileIDMap, true); } } } diff --git a/lib/Dialect/AIE/Transforms/AIEPathFinder.cpp b/lib/Dialect/AIE/Transforms/AIEPathFinder.cpp index 34071fe4d8..b0d5dea7be 100644 --- a/lib/Dialect/AIE/Transforms/AIEPathFinder.cpp +++ b/lib/Dialect/AIE/Transforms/AIEPathFinder.cpp @@ -195,10 +195,10 @@ void Pathfinder::initialize(int maxCol, int maxRow, SwitchboxConnect sb = {coords}; const std::vector bundles = { - WireBundle::Core, WireBundle::DMA, WireBundle::FIFO, - WireBundle::South, WireBundle::West, WireBundle::North, - WireBundle::East, WireBundle::PLIO, WireBundle::NOC, - WireBundle::Trace, WireBundle::Ctrl}; + WireBundle::Core, WireBundle::DMA, WireBundle::FIFO, + WireBundle::South, WireBundle::West, WireBundle::North, + WireBundle::East, WireBundle::PLIO, WireBundle::NOC, + WireBundle::Trace, WireBundle::Control}; for (WireBundle bundle : bundles) { // get all ports into current switchbox int channels = diff --git a/lib/Targets/AIETargetXAIEV2.cpp b/lib/Targets/AIETargetXAIEV2.cpp index 1905404093..51cbc916f3 100644 --- a/lib/Targets/AIETargetXAIEV2.cpp +++ b/lib/Targets/AIETargetXAIEV2.cpp @@ -27,10 +27,8 @@ using namespace xilinx; using namespace xilinx::AIE; using namespace xilinx::AIEX; -namespace xilinx::AIE { - // This string is output at the top of the lowered C++ code. -const char *xaie_cpp_file_header = R"code( +static const char *xaie_cpp_file_header = R"code( // This file was auto-generated by aiecc.py --aie-generate-xaie. #ifndef MLIR_AIE_QUIET @@ -69,13 +67,25 @@ static std::string tileLockStr(StringRef id, StringRef val) { return str; } +// Translate mlir-aie WireBundle enum to string of aie-rt StrmSwPortType enum +static std::string wireBundleToPortType(WireBundle bundle) { + switch (bundle) { + case WireBundle::PLIO: + return "PL"; + case WireBundle::Control: + return "CTRL"; + default: + return stringifyWireBundle(bundle).upper(); + } +} + // FIXME: code bloat. this shouldn't really be a template, but need // a proper DMA-like interface // blockMap: A map that gives a unique bd ID assignment for every block. template -mlir::LogicalResult generateDMAConfig(OpType memOp, raw_ostream &output, - const AIETargetModel &targetModel, - DenseMap blockMap) { +static mlir::LogicalResult generateDMAConfig(OpType memOp, raw_ostream &output, + const AIETargetModel &targetModel, + DenseMap blockMap) { StringRef enable = "XAIE_ENABLE"; StringRef disable = "XAIE_DISABLE"; StringRef deviceInstRef = "&(ctx->DevInst)"; // TODO @@ -186,9 +196,9 @@ mlir::LogicalResult generateDMAConfig(OpType memOp, raw_ostream &output, << tileLocStr(col, row) << "));\n"; if (hasAcq || hasRel) { output << "__mlir_aie_try(XAie_DmaSetLock(" - << tileDMAInstRefStr(col, row, bdNum) << ", " - << "XAie_LockInit(" << acqLockID << "," << acqValue << ")," - << "XAie_LockInit(" << relLockID << "," << relValue << ")));\n"; + << tileDMAInstRefStr(col, row, bdNum) << ", " << "XAie_LockInit(" + << acqLockID << "," << acqValue << ")," << "XAie_LockInit(" + << relLockID << "," << relValue << ")));\n"; if (!hasAcq) output << tileDMAInstStr(col, row, bdNum) << ".LockDesc.LockAcqEn = " << disable << ";\n"; @@ -202,15 +212,11 @@ mlir::LogicalResult generateDMAConfig(OpType memOp, raw_ostream &output, output << "__mlir_aie_try(XAie_DmaSetAddrLen(" << tileDMAInstRefStr(col, row, bdNum) << ", /* addrA */ " << "mlir_aie_external_get_addr_myBuffer_" << col << row << "_" - << bdNum << "(), " - << " /* len */ " << lenA << "));\n"; + << bdNum << "(), " << " /* len */ " << lenA << "));\n"; output << "__mlir_aie_try(XAie_DmaSetAxi(" << tileDMAInstRefStr(col, row, bdNum) << ", " - << "/* smid */ 0, " - << "/* burstlen */ 4, " - << "/* QoS */ 0, " - << "/* Cache */ 0, " - << "/* Secure */ " << enable << "));\n"; + << "/* smid */ 0, " << "/* burstlen */ 4, " << "/* QoS */ 0, " + << "/* Cache */ 0, " << "/* Secure */ " << enable << "));\n"; } else { if ((BaseAddrA + offsetA) % 4) return memOp.emitError("bd address must be 4B (32b) aligned"); @@ -234,9 +240,9 @@ mlir::LogicalResult generateDMAConfig(OpType memOp, raw_ostream &output, int nextBdNum = blockMap[nextBlock]; output << "__mlir_aie_try(XAie_DmaSetNextBd(" - << tileDMAInstRefStr(col, row, bdNum) << ", " - << " /* nextbd */ " << nextBdNum << ", " - << " /* enableNextBd */ " << enableNextBd << "));\n"; + << tileDMAInstRefStr(col, row, bdNum) << ", " << " /* nextbd */ " + << nextBdNum << ", " << " /* enableNextBd */ " << enableNextBd + << "));\n"; } if (foundBdPacket) { @@ -248,8 +254,8 @@ mlir::LogicalResult generateDMAConfig(OpType memOp, raw_ostream &output, << tileDMAInstRefStr(col, row, bdNum) << "));\n"; output << "__mlir_aie_try(XAie_DmaWriteBd(" << deviceInstRef << ", " << tileDMAInstRefStr(col, row, bdNum) << ", " - << tileLocStr(col, row) << ", " - << " /* bd */ " << bdNum << "));\n"; + << tileLocStr(col, row) << ", " << " /* bd */ " << bdNum + << "));\n"; } } @@ -265,8 +271,8 @@ mlir::LogicalResult generateDMAConfig(OpType memOp, raw_ostream &output, << "/* ChNum */" << chNum << ", " // TODO hack until physical dialect changes - << "/* dmaDir */ DMA_" << dmaDir << ", " - << "/* BdNum */" << bdNum << "));\n"; + << "/* dmaDir */ DMA_" << dmaDir << ", " << "/* BdNum */" + << bdNum << "));\n"; } else { // in english repeat_count==0 means "do it once" and don't repeat but // libxaie treats repeat_count=1 as do it once. @@ -276,16 +282,12 @@ mlir::LogicalResult generateDMAConfig(OpType memOp, raw_ostream &output, << "/* ChNum */" << chNum << ", " // TODO hack until physical dialect changes - << "/* dmaDir */ DMA_" << dmaDir << ", " - << "/* BdNum */" << bdNum << ", " - << "/* Repeat */ " << repeatCount << ", " - << "/* EnToken */ " - << "XAIE_DISABLE" - << "));\n"; + << "/* dmaDir */ DMA_" << dmaDir << ", " << "/* BdNum */" + << bdNum << ", " << "/* Repeat */ " << repeatCount << ", " + << "/* EnToken */ " << "XAIE_DISABLE" << "));\n"; } output << "__mlir_aie_try(XAie_DmaChannelEnable(" << deviceInstRef << ", " - << tileLocStr(col, row) << ", " - << "/* ChNum */ " << chNum + << tileLocStr(col, row) << ", " << "/* ChNum */ " << chNum << ", " // TODO hack until physical dialect changes << "/* dmaDir */ DMA_" << dmaDir << "));\n"; @@ -294,7 +296,8 @@ mlir::LogicalResult generateDMAConfig(OpType memOp, raw_ostream &output, return success(); } -mlir::LogicalResult AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output) { +mlir::LogicalResult xilinx::AIE::AIETranslateToXAIEV2(ModuleOp module, + raw_ostream &output) { // StringRef ctx = "ctx"; // TODO StringRef ctx_p = "aie_libxaie_ctx_t* ctx"; // TODO // StringRef deviceInst = "ctx->DevInst"; // TODO @@ -334,6 +337,8 @@ mlir::LogicalResult AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output) { case AIEArch::AIE2p: device = AIE2p_device; break; + default: + return module.emitOpError("Unsupported aie.device"); } output << " ctx->AieConfigPtr.AieGen = " << device << ";\n"; output << " ctx->AieConfigPtr.BaseAddr = 0x20000000000;\n"; @@ -391,8 +396,8 @@ mlir::LogicalResult AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output) { std::to_string(row) + ".elf"; output << "{\n" << "AieRC RC = XAie_LoadElf(" << deviceInstRef << ", " - << tileLocStr(col, row) << ", " - << "(const char*)\"" << fileName << "\",0);\n"; + << tileLocStr(col, row) << ", " << "(const char*)\"" << fileName + << "\",0);\n"; output << "if (RC != XAIE_OK)\n" << " __mlir_aie_verbose(fprintf(stderr, \"Failed to load elf " "for Core[%d,%d], ret is %d\\n\", " @@ -429,38 +434,6 @@ mlir::LogicalResult AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output) { //--------------------------------------------------------------------------- output << "int mlir_aie_configure_dmas(" << ctx_p << ") {\n"; - // DMA configuration - // AieRC XAie_DmaDescInit(XAie_DevInst *DevInst, XAie_DmaDesc *DmaDesc, - // XAie_LocType Loc); AieRC XAie_DmaSetLock(XAie_DmaDesc *DmaDesc, XAie_Lock - // Acq, XAie_Lock Rel); AieRC XAie_DmaSetPkt(XAie_DmaDesc *DmaDesc, - // XAie_Packet Pkt); AieRC XAie_DmaSetOutofOrderBdId(XAie_DmaDesc *DmaDesc, u8 - // OutofOrderBdId); AieRC XAie_DmaSetDoubleBuffer(XAie_DmaDesc *DmaDesc, u64 - // Addr, XAie_Lock Acq, XAie_Lock Rel); AieRC XAie_DmaSetAddrLen(XAie_DmaDesc - // *DmaDesc, u64 Addr, u32 Len); AieRC XAie_DmaSetMultiDimAddr(XAie_DmaDesc - // *DmaDesc, XAie_DmaTensor *Tensor, u64 Addr, u32 Len); AieRC - // XAie_DmaEnableCompression(XAie_DmaDesc *DmaDesc); AieRC - // XAie_DmaSetNextBd(XAie_DmaDesc *DmaDesc, u8 NextBd, u8 EnableNextBd); AieRC - // XAie_DmaEnableBd(XAie_DmaDesc *DmaDesc); AieRC - // XAie_DmaDisableBd(XAie_DmaDesc *DmaDesc); AieRC XAie_DmaSetAxi(XAie_DmaDesc - // *DmaDesc, u8 Smid, u8 BurstLen, u8 Qos,u8 Cache, u8 Secure); AieRC - // XAie_DmaSetInterleaveEnable(XAie_DmaDesc *DmaDesc, u8 DoubleBuff, u8 - // IntrleaveCount, u16 IntrleaveCurr); AieRC XAie_DmaWriteBd(XAie_DevInst - // *DevInst, XAie_DmaDesc *DmaDesc, XAie_LocType Loc, u8 BdNum); - - // AieRC XAie_DmaChannelResetAll(XAie_DevInst *DevInst, XAie_LocType Loc, - // XAie_DmaChReset Reset); AieRC XAie_DmaChannelReset(XAie_DevInst *DevInst, - // XAie_LocType Loc, u8 ChNum, XAie_DmaDirection Dir, XAie_DmaChReset Reset); - // AieRC XAie_DmaChannelPauseStream(XAie_DevInst *DevInst, XAie_LocType Loc, - // u8 ChNum, XAie_DmaDirection Dir, u8 Pause); AieRC - // XAie_DmaChannelPauseMem(XAie_DevInst *DevInst, XAie_LocType Loc, u8 ChNum - // XAie_DmaDirection Dir, u8 Pause); AieRC XAie_DmaChannelConfig(XAie_DevInst - // *DevInst, XAie_DmaDesc *DmaDesc, XAie_LocType Loc, u8 ChNum, - // XAie_DmaDirection Dir, u8 RepeatCount, u8 EnTokenIssue, u8 ControllerId); - // AieRC XAie_DmaChannelPushBdToQueue(XAie_DevInst *DevInst, XAie_LocType Loc, - // u8 ChNum, XAie_DmaDirection Dir, u8 BdNum); AieRC - // XAie_DmaChannelEnable(XAie_DevInst *DevInst, XAie_LocType Loc, u8 ChNum, - // XAie_DmaDirection Dir); AieRC XAie_DmaChannelDisable(XAie_DevInst *DevInst, - // XAie_LocType Loc, u8 ChNum, XAie_DmaDirection Dir); for (auto memOp : targetOp.getOps()) { DenseMap blockMap; @@ -592,8 +565,8 @@ mlir::LogicalResult AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output) { auto init = lock.getInit(); if (init) output << "__mlir_aie_try(XAie_LockSetValue(" << deviceInstRef << ", " - << tileLocStr(col, row) << ", " - << "XAie_LockInit(" << lockID << ", " << *init << ")));\n"; + << tileLocStr(col, row) << ", " << "XAie_LockInit(" << lockID + << ", " << *init << ")));\n"; }); output << "return XAIE_OK;\n"; output << "} // mlir_aie_initialize_locks\n"; @@ -654,9 +627,9 @@ mlir::LogicalResult AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output) { for (auto connectOp : b.getOps()) output << "__mlir_aie_try(XAie_StrmConnCctEnable(" << deviceInstRef << ", " << tileLocStr("x", "y") << ", " - << stringifyWireBundle(connectOp.getSourceBundle()).upper() << ", " + << wireBundleToPortType(connectOp.getSourceBundle()) << ", " << connectOp.sourceIndex() << ", " - << stringifyWireBundle(connectOp.getDestBundle()).upper() << ", " + << wireBundleToPortType(connectOp.getDestBundle()) << ", " << connectOp.destIndex() << "));\n"; for (auto connectOp : b.getOps()) { @@ -672,14 +645,11 @@ mlir::LogicalResult AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output) { output << "__mlir_aie_try(XAie_StrmPktSwMstrPortEnable(" << deviceInstRef << ", " << tileLocStr("x", "y") << ", " - << stringifyWireBundle(connectOp.getDestBundle()).upper() << ", " - << connectOp.destIndex() << ", " - << "/* drop_header */ " + << wireBundleToPortType(connectOp.getDestBundle()) << ", " + << connectOp.destIndex() << ", " << "/* drop_header */ " << (isdma ? "XAIE_SS_PKT_DROP_HEADER" : "XAIE_SS_PKT_DONOT_DROP_HEADER") - << ", " - << "/* arbiter */ " << arbiter << ", " - << "/* MSelEn */ " + << ", " << "/* arbiter */ " << arbiter << ", " << "/* MSelEn */ " << "0x" << llvm::utohexstr(mask) << "));\n"; } @@ -692,21 +662,19 @@ mlir::LogicalResult AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output) { int msel = amselOp.getMselValue(); output << "__mlir_aie_try(XAie_StrmPktSwSlavePortEnable(" << deviceInstRef << ", " << tileLocStr("x", "y") << ", " - << stringifyWireBundle(connectOp.getSourceBundle()).upper() - << ", " << connectOp.sourceIndex() << "));\n"; + << wireBundleToPortType(connectOp.getSourceBundle()) << ", " + << connectOp.sourceIndex() << "));\n"; // TODO Need to better define packet id,type used here output << "__mlir_aie_try(XAie_StrmPktSwSlaveSlotEnable(" << deviceInstRef << ", " << tileLocStr("x", "y") << ", " - << stringifyWireBundle(connectOp.getSourceBundle()).upper() - << ", " << connectOp.sourceIndex() << ", " - << "/* slot */ " << slot << ", " - << "/* packet */ " << packetStr(slotOp.valueInt(), /*type*/ 0) - << ", " - << "/* mask */ " - << "0x" << llvm::utohexstr(slotOp.maskInt()) << ", " - << "/* msel */ " << msel << ", " - << "/* arbiter */ " << arbiter << "));\n"; + << wireBundleToPortType(connectOp.getSourceBundle()) << ", " + << connectOp.sourceIndex() << ", " << "/* slot */ " << slot + << ", " << "/* packet */ " + << packetStr(slotOp.valueInt(), /*type*/ 0) << ", " + << "/* mask */ " << "0x" << llvm::utohexstr(slotOp.maskInt()) + << ", " << "/* msel */ " << msel << ", " << "/* arbiter */ " + << arbiter << "));\n"; slot++; } } @@ -740,22 +708,14 @@ mlir::LogicalResult AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output) { connectOp.getDestBundle() == WireBundle::DMA) { if (connectOp.getSourceBundle() == WireBundle::North) // demux! - output - << "__mlir_aie_try(XAie_EnableAieToShimDmaStrmPort(" - << deviceInstRef << ", " << tileLocStr("x", "y") - << ", " - // << - // stringifyWireBundle(connectOp.sourceBundle()).upper() - << connectOp.sourceIndex() << "));\n"; + output << "__mlir_aie_try(XAie_EnableAieToShimDmaStrmPort(" + << deviceInstRef << ", " << tileLocStr("x", "y") << ", " + << connectOp.sourceIndex() << "));\n"; else if (connectOp.getDestBundle() == WireBundle::North) // mux - output - << "__mlir_aie_try(XAie_EnableShimDmaToAieStrmPort(" - << deviceInstRef << ", " << tileLocStr("x", "y") - << ", " - // << - // stringifyWireBundle(connectOp.sourceBundle()).upper() - << connectOp.destIndex() << "));\n"; + output << "__mlir_aie_try(XAie_EnableShimDmaToAieStrmPort(" + << deviceInstRef << ", " << tileLocStr("x", "y") << ", " + << connectOp.destIndex() << "));\n"; } else if (connectOp.getSourceBundle() == WireBundle::PLIO || @@ -784,9 +744,9 @@ mlir::LogicalResult AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output) { for (auto connectOp : b.getOps()) output << "__mlir_aie_try(XAie_StrmConnCctEnable(" << deviceInstRef << ", " << tileLocStr(col, 0) << ", " - << stringifyWireBundle(connectOp.getSourceBundle()).upper() << ", " + << wireBundleToPortType(connectOp.getSourceBundle()) << ", " << connectOp.sourceIndex() << ", " - << stringifyWireBundle(connectOp.getDestBundle()).upper() << ", " + << wireBundleToPortType(connectOp.getDestBundle()) << ", " << connectOp.destIndex() << "));\n"; } @@ -905,4 +865,3 @@ mlir::LogicalResult AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output) { return success(); } -} // namespace xilinx::AIE diff --git a/test/create-packet-flows/badpacket_flow.mlir b/test/create-packet-flows/badpacket_flow.mlir index 9d43484fd5..71a8517a67 100644 --- a/test/create-packet-flows/badpacket_flow.mlir +++ b/test/create-packet-flows/badpacket_flow.mlir @@ -18,11 +18,11 @@ aie.device(npu1_1col) { %00 = aie.tile(0, 0) aie.packet_flow(28) { aie.packet_source<%00, DMA : 0> - aie.packet_dest<%02, Ctrl : 0> + aie.packet_dest<%02, Control : 0> } aie.packet_flow(29) { aie.packet_source<%00, DMA : 0> - aie.packet_dest<%03, Ctrl : 0> + aie.packet_dest<%03, Control : 0> } aie.packet_flow(26) { aie.packet_source<%00, DMA : 0> diff --git a/test/create-packet-flows/packet_routing_priority_route.mlir b/test/create-packet-flows/packet_routing_priority_route.mlir index a7a305e466..ecc216a6c4 100644 --- a/test/create-packet-flows/packet_routing_priority_route.mlir +++ b/test/create-packet-flows/packet_routing_priority_route.mlir @@ -38,7 +38,7 @@ module @aie_module { aie.packet_flow(0x2) { aie.packet_source<%t70, DMA : 0> - aie.packet_dest<%t72, Ctrl : 0> + aie.packet_dest<%t72, Control : 0> } {priority_route = true} } } diff --git a/test/dialect/AIE/generate_column_control_overlay.mlir b/test/dialect/AIE/generate_column_control_overlay.mlir index a7fe8764a3..51fc74eb5b 100644 --- a/test/dialect/AIE/generate_column_control_overlay.mlir +++ b/test/dialect/AIE/generate_column_control_overlay.mlir @@ -18,18 +18,18 @@ // CHECK: %[[tile_0_0:.*]] = aie.tile(0, 0) // CHECK: %[[tile_0_1:.*]] = aie.tile(0, 1) // CHECK: aie.packet_flow(15) { -// CHECK: aie.packet_source<%[[tile_0_0]], Ctrl : 0> +// CHECK: aie.packet_source<%[[tile_0_0]], Control : 0> // CHECK: aie.packet_dest<%[[tile_0_0]], South : 0> // CHECK: }{{.*}}keep_pkt_header = true{{.*}}priority_route = true // TCTALLTILES-LABEL: module { // TCTALLTILES: %[[tile_0_0:.*]] = aie.tile(0, 0) // TCTALLTILES: %[[tile_0_1:.*]] = aie.tile(0, 1) // TCTALLTILES: aie.packet_flow(15) { -// TCTALLTILES: aie.packet_source<%[[tile_0_0]], Ctrl : 0> +// TCTALLTILES: aie.packet_source<%[[tile_0_0]], Control : 0> // TCTALLTILES: aie.packet_dest<%[[tile_0_0]], South : 0> // TCTALLTILES: }{{.*}}keep_pkt_header = true{{.*}}priority_route = true // TCTALLTILES: aie.packet_flow(26) { -// TCTALLTILES: aie.packet_source<%[[tile_0_1]], Ctrl : 0> +// TCTALLTILES: aie.packet_source<%[[tile_0_1]], Control : 0> // TCTALLTILES: aie.packet_dest<%[[tile_0_0]], South : 0> // TCTALLTILES: }{{.*}}keep_pkt_header = true{{.*}}priority_route = true // CTRLPKT-LABEL: module { @@ -37,13 +37,13 @@ // CTRLPKT: %[[tile_0_1:.*]] = aie.tile(0, 1) // CTRLPKT: aie.packet_flow(15) { // CTRLPKT: aie.packet_source<%[[tile_0_0]], DMA : 0> -// CTRLPKT: aie.packet_dest<%[[tile_0_0]], Ctrl : 0> +// CTRLPKT: aie.packet_dest<%[[tile_0_0]], Control : 0> // CTRLPKT: } // CTRLPKT: aie.shim_dma_allocation @ctrlpkt_col0_mm2s_chan0(MM2S, 0, 0) // CTRLPKT: memref.global "public" @ctrlpkt_col0_mm2s_chan0 : memref<2048xi32> // CTRLPKT: aie.packet_flow(26) { // CTRLPKT: aie.packet_source<%[[tile_0_0]], DMA : 0> -// CTRLPKT: aie.packet_dest<%[[tile_0_1]], Ctrl : 0> +// CTRLPKT: aie.packet_dest<%[[tile_0_1]], Control : 0> // CTRLPKT: } aie.device(npu1_1col) { @@ -61,11 +61,11 @@ aie.device(npu1_1col) { // CHECK: %[[tile_1_0:.*]] = aie.tile(1, 0) // CHECK: %[[tile_1_1:.*]] = aie.tile(1, 1) // CHECK: aie.packet_flow(15) { -// CHECK: aie.packet_source<%[[tile_0_0]], Ctrl : 0> +// CHECK: aie.packet_source<%[[tile_0_0]], Control : 0> // CHECK: aie.packet_dest<%[[tile_0_0]], South : 0> // CHECK: }{{.*}}keep_pkt_header = true{{.*}}priority_route = true // CHECK: aie.packet_flow(15) { -// CHECK: aie.packet_source<%[[tile_1_0]], Ctrl : 0> +// CHECK: aie.packet_source<%[[tile_1_0]], Control : 0> // CHECK: aie.packet_dest<%[[tile_1_0]], South : 0> // CHECK: }{{.*}}keep_pkt_header = true{{.*}}priority_route = true // TCTALLTILES-LABEL: module { @@ -74,19 +74,19 @@ aie.device(npu1_1col) { // TCTALLTILES: %[[tile_1_0:.*]] = aie.tile(1, 0) // TCTALLTILES: %[[tile_1_1:.*]] = aie.tile(1, 1) // TCTALLTILES: aie.packet_flow(15) { -// TCTALLTILES: aie.packet_source<%[[tile_0_0]], Ctrl : 0> +// TCTALLTILES: aie.packet_source<%[[tile_0_0]], Control : 0> // TCTALLTILES: aie.packet_dest<%[[tile_0_0]], South : 0> // TCTALLTILES: }{{.*}}keep_pkt_header = true{{.*}}priority_route = true // TCTALLTILES: aie.packet_flow(26) { -// TCTALLTILES: aie.packet_source<%[[tile_0_1]], Ctrl : 0> +// TCTALLTILES: aie.packet_source<%[[tile_0_1]], Control : 0> // TCTALLTILES: aie.packet_dest<%[[tile_0_0]], South : 0> // TCTALLTILES: }{{.*}}keep_pkt_header = true{{.*}}priority_route = true // TCTALLTILES: aie.packet_flow(15) { -// TCTALLTILES: aie.packet_source<%[[tile_1_0]], Ctrl : 0> +// TCTALLTILES: aie.packet_source<%[[tile_1_0]], Control : 0> // TCTALLTILES: aie.packet_dest<%[[tile_1_0]], South : 0> // TCTALLTILES: }{{.*}}keep_pkt_header = true{{.*}}priority_route = true // TCTALLTILES: aie.packet_flow(26) { -// TCTALLTILES: aie.packet_source<%[[tile_1_1]], Ctrl : 0> +// TCTALLTILES: aie.packet_source<%[[tile_1_1]], Control : 0> // TCTALLTILES: aie.packet_dest<%[[tile_1_0]], South : 0> // TCTALLTILES: }{{.*}}keep_pkt_header = true{{.*}}priority_route = true // CTRLPKT-LABEL: module { @@ -96,23 +96,23 @@ aie.device(npu1_1col) { // CTRLPKT: %[[tile_1_1:.*]] = aie.tile(1, 1) // CTRLPKT: aie.packet_flow(15) { // CTRLPKT: aie.packet_source<%[[tile_0_0]], DMA : 0> -// CTRLPKT: aie.packet_dest<%[[tile_0_0]], Ctrl : 0> +// CTRLPKT: aie.packet_dest<%[[tile_0_0]], Control : 0> // CTRLPKT: } // CTRLPKT: aie.shim_dma_allocation @ctrlpkt_col0_mm2s_chan0(MM2S, 0, 0) // CTRLPKT: memref.global "public" @ctrlpkt_col0_mm2s_chan0 : memref<2048xi32> // CTRLPKT: aie.packet_flow(26) { // CTRLPKT: aie.packet_source<%[[tile_0_0]], DMA : 0> -// CTRLPKT: aie.packet_dest<%[[tile_0_1]], Ctrl : 0> +// CTRLPKT: aie.packet_dest<%[[tile_0_1]], Control : 0> // CTRLPKT: } // CTRLPKT: aie.packet_flow(15) { // CTRLPKT: aie.packet_source<%[[tile_1_0]], DMA : 0> -// CTRLPKT: aie.packet_dest<%[[tile_1_0]], Ctrl : 0> +// CTRLPKT: aie.packet_dest<%[[tile_1_0]], Control : 0> // CTRLPKT: } // CTRLPKT: aie.shim_dma_allocation @ctrlpkt_col1_mm2s_chan0(MM2S, 0, 1) // CTRLPKT: memref.global "public" @ctrlpkt_col1_mm2s_chan0 : memref<2048xi32> // CTRLPKT: aie.packet_flow(26) { // CTRLPKT: aie.packet_source<%[[tile_1_0]], DMA : 0> -// CTRLPKT: aie.packet_dest<%[[tile_1_1]], Ctrl : 0> +// CTRLPKT: aie.packet_dest<%[[tile_1_1]], Control : 0> // CTRLPKT: } aie.device(npu1_2col) { @@ -137,11 +137,11 @@ aie.device(npu1_2col) { // CHECK: %[[tile_1_0:.*]] = aie.tile(1, 0) {controller_id = #aie.packet_info} // CHECK: %[[tile_1_1:.*]] = aie.tile(1, 1) {controller_id = #aie.packet_info} // CHECK: aie.packet_flow(4) { -// CHECK: aie.packet_source<%[[tile_0_0]], Ctrl : 0> +// CHECK: aie.packet_source<%[[tile_0_0]], Control : 0> // CHECK: aie.packet_dest<%[[tile_0_0]], South : 0> // CHECK: }{{.*}}keep_pkt_header = true{{.*}}priority_route = true // CHECK: aie.packet_flow(5) { -// CHECK: aie.packet_source<%[[tile_1_0]], Ctrl : 0> +// CHECK: aie.packet_source<%[[tile_1_0]], Control : 0> // CHECK: aie.packet_dest<%[[tile_1_0]], South : 0> // CHECK: }{{.*}}keep_pkt_header = true{{.*}}priority_route = true // TCTALLTILES-LABEL: module { @@ -154,35 +154,35 @@ aie.device(npu1_2col) { // TCTALLTILES: %[[tile_1_0:.*]] = aie.tile(1, 0) {controller_id = #aie.packet_info} // TCTALLTILES: %[[tile_1_1:.*]] = aie.tile(1, 1) {controller_id = #aie.packet_info} // TCTALLTILES: aie.packet_flow(4) { -// TCTALLTILES: aie.packet_source<%[[tile_0_0]], Ctrl : 0> +// TCTALLTILES: aie.packet_source<%[[tile_0_0]], Control : 0> // TCTALLTILES: aie.packet_dest<%[[tile_0_0]], South : 0> // TCTALLTILES: }{{.*}}keep_pkt_header = true{{.*}}priority_route = true // TCTALLTILES: aie.packet_flow(3) { -// TCTALLTILES: aie.packet_source<%[[tile_0_1]], Ctrl : 0> +// TCTALLTILES: aie.packet_source<%[[tile_0_1]], Control : 0> // TCTALLTILES: aie.packet_dest<%[[tile_0_0]], South : 0> // TCTALLTILES: }{{.*}}keep_pkt_header = true{{.*}}priority_route = true // TCTALLTILES: aie.packet_flow(5) { -// TCTALLTILES: aie.packet_source<%[[tile_0_2]], Ctrl : 0> +// TCTALLTILES: aie.packet_source<%[[tile_0_2]], Control : 0> // TCTALLTILES: aie.packet_dest<%[[tile_0_0]], South : 0> // TCTALLTILES: }{{.*}}keep_pkt_header = true{{.*}}priority_route = true // TCTALLTILES: aie.packet_flow(1) { -// TCTALLTILES: aie.packet_source<%[[tile_0_3]], Ctrl : 0> +// TCTALLTILES: aie.packet_source<%[[tile_0_3]], Control : 0> // TCTALLTILES: aie.packet_dest<%[[tile_0_0]], South : 0> // TCTALLTILES: }{{.*}}keep_pkt_header = true{{.*}}priority_route = true // TCTALLTILES: aie.packet_flow(6) { -// TCTALLTILES: aie.packet_source<%[[tile_0_4]], Ctrl : 0> +// TCTALLTILES: aie.packet_source<%[[tile_0_4]], Control : 0> // TCTALLTILES: aie.packet_dest<%[[tile_0_0]], South : 0> // TCTALLTILES: }{{.*}}keep_pkt_header = true{{.*}}priority_route = true // TCTALLTILES: aie.packet_flow(2) { -// TCTALLTILES: aie.packet_source<%[[tile_0_5]], Ctrl : 0> +// TCTALLTILES: aie.packet_source<%[[tile_0_5]], Control : 0> // TCTALLTILES: aie.packet_dest<%[[tile_0_0]], South : 0> // TCTALLTILES: }{{.*}}keep_pkt_header = true{{.*}}priority_route = true // TCTALLTILES: aie.packet_flow(5) { -// TCTALLTILES: aie.packet_source<%[[tile_1_0]], Ctrl : 0> +// TCTALLTILES: aie.packet_source<%[[tile_1_0]], Control : 0> // TCTALLTILES: aie.packet_dest<%[[tile_1_0]], South : 0> // TCTALLTILES: }{{.*}}keep_pkt_header = true{{.*}}priority_route = true // TCTALLTILES: aie.packet_flow(7) { -// TCTALLTILES: aie.packet_source<%[[tile_1_1]], Ctrl : 0> +// TCTALLTILES: aie.packet_source<%[[tile_1_1]], Control : 0> // TCTALLTILES: aie.packet_dest<%[[tile_1_0]], South : 0> // TCTALLTILES: }{{.*}}keep_pkt_header = true{{.*}}priority_route = true // CTRLPKT-LABEL: module { @@ -196,41 +196,41 @@ aie.device(npu1_2col) { // CTRLPKT: %[[tile_1_1:.*]] = aie.tile(1, 1) {controller_id = #aie.packet_info} // CTRLPKT: aie.packet_flow(4) { // CTRLPKT: aie.packet_source<%[[tile_0_0]], DMA : 0> -// CTRLPKT: aie.packet_dest<%[[tile_0_0]], Ctrl : 0> +// CTRLPKT: aie.packet_dest<%[[tile_0_0]], Control : 0> // CTRLPKT: } // CTRLPKT: aie.shim_dma_allocation @ctrlpkt_col0_mm2s_chan0(MM2S, 0, 0) // CTRLPKT: memref.global "public" @ctrlpkt_col0_mm2s_chan0 : memref<2048xi32> // CTRLPKT: aie.packet_flow(3) { // CTRLPKT: aie.packet_source<%[[tile_0_0]], DMA : 0> -// CTRLPKT: aie.packet_dest<%[[tile_0_1]], Ctrl : 0> +// CTRLPKT: aie.packet_dest<%[[tile_0_1]], Control : 0> // CTRLPKT: } // CTRLPKT: aie.packet_flow(5) { // CTRLPKT: aie.packet_source<%[[tile_0_0]], DMA : 0> -// CTRLPKT: aie.packet_dest<%[[tile_0_2]], Ctrl : 0> +// CTRLPKT: aie.packet_dest<%[[tile_0_2]], Control : 0> // CTRLPKT: } // CTRLPKT: aie.packet_flow(1) { // CTRLPKT: aie.packet_source<%[[tile_0_0]], DMA : 1> -// CTRLPKT: aie.packet_dest<%[[tile_0_3]], Ctrl : 0> +// CTRLPKT: aie.packet_dest<%[[tile_0_3]], Control : 0> // CTRLPKT: } // CTRLPKT: aie.shim_dma_allocation @ctrlpkt_col0_mm2s_chan1(MM2S, 1, 0) // CTRLPKT: memref.global "public" @ctrlpkt_col0_mm2s_chan1 : memref<2048xi32> // CTRLPKT: aie.packet_flow(6) { // CTRLPKT: aie.packet_source<%[[tile_0_0]], DMA : 1> -// CTRLPKT: aie.packet_dest<%[[tile_0_4]], Ctrl : 0> +// CTRLPKT: aie.packet_dest<%[[tile_0_4]], Control : 0> // CTRLPKT: } // CTRLPKT: aie.packet_flow(2) { // CTRLPKT: aie.packet_source<%[[tile_0_0]], DMA : 1> -// CTRLPKT: aie.packet_dest<%[[tile_0_5]], Ctrl : 0> +// CTRLPKT: aie.packet_dest<%[[tile_0_5]], Control : 0> // CTRLPKT: } // CTRLPKT: aie.packet_flow(5) { // CTRLPKT: aie.packet_source<%[[tile_1_0]], DMA : 0> -// CTRLPKT: aie.packet_dest<%[[tile_1_0]], Ctrl : 0> +// CTRLPKT: aie.packet_dest<%[[tile_1_0]], Control : 0> // CTRLPKT: } // CTRLPKT: aie.shim_dma_allocation @ctrlpkt_col1_mm2s_chan0(MM2S, 0, 1) // CTRLPKT: memref.global "public" @ctrlpkt_col1_mm2s_chan0 : memref<2048xi32> // CTRLPKT: aie.packet_flow(7) { // CTRLPKT: aie.packet_source<%[[tile_1_0]], DMA : 0> -// CTRLPKT: aie.packet_dest<%[[tile_1_1]], Ctrl : 0> +// CTRLPKT: aie.packet_dest<%[[tile_1_1]], Control : 0> // CTRLPKT: } aie.device(npu1_2col) { diff --git a/test/dialect/AIE/switchbox-vc1902.mlir b/test/dialect/AIE/switchbox-vc1902.mlir index df6896c056..5fd1f7f95a 100644 --- a/test/dialect/AIE/switchbox-vc1902.mlir +++ b/test/dialect/AIE/switchbox-vc1902.mlir @@ -22,8 +22,8 @@ module { aie.connect // 4 southgoing connections aie.connect // 4 eastgoing connections aie.connect - aie.connect - aie.connect + aie.connect + aie.connect } %30 = aie.tile(3, 0) // Shim-NOC @@ -91,8 +91,8 @@ module { aie.connect // 4 westgoing connections aie.connect // 4 southgoing connections aie.connect // 4 eastgoing connections - aie.connect - aie.connect + aie.connect + aie.connect } } } diff --git a/test/dialect/AIE/switchbox-ve2802.mlir b/test/dialect/AIE/switchbox-ve2802.mlir index bf8bb7e7b1..46b57b4d96 100644 --- a/test/dialect/AIE/switchbox-ve2802.mlir +++ b/test/dialect/AIE/switchbox-ve2802.mlir @@ -22,8 +22,8 @@ module { aie.connect // 4 southgoing connections aie.connect // 4 eastgoing connections aie.connect - aie.connect - aie.connect + aie.connect + aie.connect } %30 = aie.tile(3, 0) // Shim-NOC @@ -87,8 +87,8 @@ module { aie.connect // 6 northgoing connections aie.connect // 4 southgoing connections aie.connect - aie.connect - aie.connect + aie.connect + aie.connect } %03 = aie.tile(1, 3) // core tile @@ -101,8 +101,8 @@ module { aie.connect // 4 westgoing connections aie.connect // 4 southgoing connections aie.connect // 4 eastgoing connections - aie.connect - aie.connect + aie.connect + aie.connect } } } diff --git a/test/npu-xrt/add_one_ctrl_packet/aie.mlir b/test/npu-xrt/add_one_ctrl_packet/aie.mlir index 20e55c0f5b..44071320c2 100644 --- a/test/npu-xrt/add_one_ctrl_packet/aie.mlir +++ b/test/npu-xrt/add_one_ctrl_packet/aie.mlir @@ -27,10 +27,10 @@ module { aie.packet_flow(0x1) { aie.packet_source<%tile_0_0, DMA : 0> - aie.packet_dest<%tile_0_2, Ctrl : 0> + aie.packet_dest<%tile_0_2, Control : 0> } aie.packet_flow(0x2) { - aie.packet_source<%tile_0_2, Ctrl : 0> + aie.packet_source<%tile_0_2, Control : 0> aie.packet_dest<%tile_0_0, DMA : 0> } aie.packet_flow(0x3) { @@ -117,7 +117,7 @@ module { %c2_i64 = arith.constant 2 : i64 %c8_i64 = arith.constant 8 : i64 - // set Ctrl_Pkt_Tlast_Error_Enable=0 in Module_Clock_Control register + // set Control_Pkt_Tlast_Error_Enable=0 in Module_Clock_Control register // aiex.npu.maskwrite32 {address = 0x00060000 : ui32, column = 0 : i32, row = 2 : i32, value = 0 : ui32, mask = 0x8 : ui32} // start reading output diff --git a/test/npu-xrt/add_one_ctrl_packet_4_cores/aie.mlir b/test/npu-xrt/add_one_ctrl_packet_4_cores/aie.mlir index e96d24025e..8b7575faa1 100644 --- a/test/npu-xrt/add_one_ctrl_packet_4_cores/aie.mlir +++ b/test/npu-xrt/add_one_ctrl_packet_4_cores/aie.mlir @@ -60,19 +60,19 @@ module { aie.packet_flow(0x5) { aie.packet_source<%tile_0_0, DMA : 0> - aie.packet_dest<%tile_0_2, Ctrl : 0> + aie.packet_dest<%tile_0_2, Control : 0> } aie.packet_flow(0x6) { aie.packet_source<%tile_0_0, DMA : 0> - aie.packet_dest<%tile_0_3, Ctrl : 0> + aie.packet_dest<%tile_0_3, Control : 0> } aie.packet_flow(0x7) { aie.packet_source<%tile_0_0, DMA : 0> - aie.packet_dest<%tile_0_4, Ctrl : 0> + aie.packet_dest<%tile_0_4, Control : 0> } aie.packet_flow(0x8) { aie.packet_source<%tile_0_0, DMA : 1> - aie.packet_dest<%tile_0_5, Ctrl : 0> + aie.packet_dest<%tile_0_5, Control : 0> } aie.flow(%tile_0_2, DMA : 0, %tile_0_0, DMA : 1) diff --git a/test/npu-xrt/add_one_ctrl_packet_4_cores/test.cpp b/test/npu-xrt/add_one_ctrl_packet_4_cores/test.cpp index ccfef64dc2..97b48a3164 100644 --- a/test/npu-xrt/add_one_ctrl_packet_4_cores/test.cpp +++ b/test/npu-xrt/add_one_ctrl_packet_4_cores/test.cpp @@ -144,22 +144,22 @@ int main(int argc, const char *argv[]) { // set lock values to 2 uint32_t data = 2; std::vector ctrlPackets = { - // Ctrl pkt for tile (0, 2) + // Control pkt for tile (0, 2) header0, data, header1, data, - // Ctrl pkt for tile (0, 3) + // Control pkt for tile (0, 3) header0, data, header1, data, - // Ctrl pkt for tile (0, 4) + // Control pkt for tile (0, 4) header0, data, header1, data, - // Ctrl pkt for tile (0, 5) + // Control pkt for tile (0, 5) header0, data, header1, diff --git a/test/npu-xrt/add_one_ctrl_packet_col_overlay/test.cpp b/test/npu-xrt/add_one_ctrl_packet_col_overlay/test.cpp index ea176b2e0c..efd00ca94e 100644 --- a/test/npu-xrt/add_one_ctrl_packet_col_overlay/test.cpp +++ b/test/npu-xrt/add_one_ctrl_packet_col_overlay/test.cpp @@ -144,22 +144,22 @@ int main(int argc, const char *argv[]) { // set lock values to 2 uint32_t data = 2; std::vector ctrlPackets = { - // Ctrl pkt for tile (0, 2) + // Control pkt for tile (0, 2) header0, data, header1, data, - // Ctrl pkt for tile (0, 3) + // Control pkt for tile (0, 3) header0, data, header1, data, - // Ctrl pkt for tile (0, 4) + // Control pkt for tile (0, 4) header0, data, header1, data, - // Ctrl pkt for tile (0, 5) + // Control pkt for tile (0, 5) header0, data, header1, diff --git a/test/npu-xrt/memtile_dmas/writebd_tokens/aie.mlir b/test/npu-xrt/memtile_dmas/writebd_tokens/aie.mlir index 78c9656d88..b811f4c618 100644 --- a/test/npu-xrt/memtile_dmas/writebd_tokens/aie.mlir +++ b/test/npu-xrt/memtile_dmas/writebd_tokens/aie.mlir @@ -15,11 +15,11 @@ module { aie.flow(%tile_0_1, DMA : 0, %tile_0_0, DMA : 0) aie.packet_flow(0x1) { - aie.packet_source<%tile_0_1, "Ctrl" : 0> + aie.packet_source<%tile_0_1, "Control" : 0> aie.packet_dest<%tile_0_0, "South" : 0> } aie.packet_flow(0x2) { - aie.packet_source<%tile_0_0, "Ctrl" : 0> + aie.packet_source<%tile_0_0, "Control" : 0> aie.packet_dest<%tile_0_0, "South" : 0> }