Description
am trying the use case example(dilation) and for that i get simulation
Starting C simulation ...
C:/Xilinx/Vivado/2019.1/bin/vivado_hls.bat F:/xfopencv_AXI/xfopencv-2019.1_release/HLS_Use_Model/test_hls_proj/solution1/csim.tcl
INFO: [HLS 200-10] Running 'C:/Xilinx/Vivado/2019.1/bin/unwrapped/win64.o/vivado_hls.exe'
INFO: [HLS 200-10] For user 'sneha chand' on host 'laptop-vhlg6odf' (Windows NT_amd64 version 6.2) on Wed Oct 21 16:47:14 +0530 2020
INFO: [HLS 200-10] In directory 'F:/xfopencv_AXI/xfopencv-2019.1_release/HLS_Use_Model'
Sourcing Tcl script 'F:/xfopencv_AXI/xfopencv-2019.1_release/HLS_Use_Model/test_hls_proj/solution1/csim.tcl'
INFO: [HLS 200-10] Opening project 'F:/xfopencv_AXI/xfopencv-2019.1_release/HLS_Use_Model/test_hls_proj'.
INFO: [HLS 200-10] Opening solution 'F:/xfopencv_AXI/xfopencv-2019.1_release/HLS_Use_Model/test_hls_proj/solution1'.
INFO: [SYN 201-201] Setting up clock 'default' with a period of 6.6ns.
INFO: [HLS 200-10] Setting target device to 'xc7z020-clg484-1'
INFO: [SIM 211-2] *************** CSIM start ***************
INFO: [SIM 211-4] CSIM will launch GCC as the compiler.
Compiling ../../../../Standalone_HLS_AXI_Example/xf_dilation_accel.cpp in debug mode
Compiling ../../../../Standalone_HLS_AXI_Example/xf_ip_accel_app.cpp in debug mode
Generating csim.exe
In file included from C:/Xilinx/Vivado/2019.1/include/floating_point_v7_0_bitacc_cmodel.h:143:0,
from C:/Xilinx/Vivado/2019.1/include/hls_fpo.h:186,
from C:/Xilinx/Vivado/2019.1/include/hls_half.h:44,
from C:/Xilinx/Vivado/2019.1/include/etc/ap_private.h:90,
from C:/Xilinx/Vivado/2019.1/include/ap_common.h:641,
from C:/Xilinx/Vivado/2019.1/include/ap_int.h:54,
from ../../../../Standalone_HLS_AXI_Example/xf_dilation_config.h:35,
from ../../../../Standalone_HLS_AXI_Example/xf_dilation_accel.cpp:31:
C:/Xilinx/Vivado/2019.1/include/gmp.h:62:0: warning: "__GMP_LIBGMP_DLL" redefined
#define __GMP_LIBGMP_DLL 0
In file included from C:/Xilinx/Vivado/2019.1/include/hls_fpo.h:186:0,
from C:/Xilinx/Vivado/2019.1/include/hls_half.h:44,
from C:/Xilinx/Vivado/2019.1/include/etc/ap_private.h:90,
from C:/Xilinx/Vivado/2019.1/include/ap_common.h:641,
from C:/Xilinx/Vivado/2019.1/include/ap_int.h:54,
from ../../../../Standalone_HLS_AXI_Example/xf_dilation_config.h:35,
from ../../../../Standalone_HLS_AXI_Example/xf_dilation_accel.cpp:31:
C:/Xilinx/Vivado/2019.1/include/floating_point_v7_0_bitacc_cmodel.h:135:0: note: this is the location of the previous definition
#define __GMP_LIBGMP_DLL 1
In file included from C:/Xilinx/Vivado/2019.1/include/common/xf_common.h:34:0,
from ../../../../Standalone_HLS_AXI_Example/xf_dilation_config.h:36,
from ../../../../Standalone_HLS_AXI_Example/xf_dilation_accel.cpp:31:
C:/Xilinx/Vivado/2019.1/include/common/xf_structs.h: In instantiation of 'struct xf::Mat<0, 1080, 1920, 1>::DATATYPE':
C:/Xilinx/Vivado/2019.1/include/common/xf_structs.h:625:11: required from 'typename DataType<T, NPC>::name xf::Mat<T, ROWS, COLS, NPC>::read(int) [with int T = 0; int ROWS = 1080; int COLS = 1920; int NPC = 1; typename DataType<T, NPC>::name = ap_uint<8>]'
C:/Xilinx/Vivado/2019.1/include/imgproc/xf_dilation.hpp:272:22: required from 'void xf::xfdilate(xf::Mat<TYPE, ROWS, COLS, NPC>&, xf::Mat<TYPE, ROWS, COLS, NPC>&, uint16_t, uint16_t, unsigned char ()[K_COLS]) [with int ROWS = 1080; int COLS = 1920; int PLANES = 1; int TYPE = 0; int NPC = 1; int WORDWIDTH = 0; int TC = 1921; int K_ROWS = 3; int K_COLS = 3; uint16_t = short unsigned int]'
C:/Xilinx/Vivado/2019.1/include/imgproc/xf_dilation.hpp:361:125: required from 'void xf::dilate(xf::Mat<TYPE, ROWS, COLS, NPC>&, xf::Mat<TYPE, ROWS, COLS, NPC>&, unsigned char) [with int BORDER_TYPE = 0; int TYPE = 0; int ROWS = 1080; int COLS = 1920; int K_SHAPE = 2; int K_ROWS = 3; int K_COLS = 3; int ITERATIONS = 1; int NPC = 1]'
../../../../Standalone_HLS_AXI_Example/xf_dilation_accel.cpp:37:129: required from here
C:/Xilinx/Vivado/2019.1/include/common/xf_structs.h:397:72: warning: ignoring packed attribute because of unpacked non-POD field 'DataType<0, 1>::cname xf::Mat<0, 1080, 1920, 1>::DATATYPE::chnl [1][1]'
XF_CTUNAME(T,NPC) chnl[XF_NPIXPERCYCLE(NPC)][XF_CHANNELS(T,NPC)];
^
In file included from C:/Xilinx/Vivado/2019.1/include/floating_point_v7_0_bitacc_cmodel.h:143:0,
from C:/Xilinx/Vivado/2019.1/include/hls_fpo.h:186,
from C:/Xilinx/Vivado/2019.1/include/hls_half.h:44,
from C:/Xilinx/Vivado/2019.1/include/etc/ap_private.h:90,
from C:/Xilinx/Vivado/2019.1/include/ap_common.h:641,
from C:/Xilinx/Vivado/2019.1/include/ap_int.h:54,
from ../../../../Standalone_HLS_AXI_Example/xf_dilation_config.h:35,
from ../../../../Standalone_HLS_AXI_Example/xf_ip_accel_app.cpp:31:
C:/Xilinx/Vivado/2019.1/include/gmp.h:62:0: warning: "__GMP_LIBGMP_DLL" redefined
#define __GMP_LIBGMP_DLL 0
In file included from C:/Xilinx/Vivado/2019.1/include/hls_fpo.h:186:0,
from C:/Xilinx/Vivado/2019.1/include/hls_half.h:44,
from C:/Xilinx/Vivado/2019.1/include/etc/ap_private.h:90,
from C:/Xilinx/Vivado/2019.1/include/ap_common.h:641,
from C:/Xilinx/Vivado/2019.1/include/ap_int.h:54,
from ../../../../Standalone_HLS_AXI_Example/xf_dilation_config.h:35,
from ../../../../Standalone_HLS_AXI_Example/xf_ip_accel_app.cpp:31:
C:/Xilinx/Vivado/2019.1/include/floating_point_v7_0_bitacc_cmodel.h:135:0: note: this is the location of the previous definition
#define __GMP_LIBGMP_DLL 1
Minimum error in intensity = 0.000000
Maximum error in intensity = 0.000000
Percentage of pixels above error threshold = 0.000000
INFO: [SIM 211-1] CSim done with 0 errors.
INFO: [SIM 211-3] *************** CSIM finish ***************
Finished C simulation.
but then i try the same with Bilateral filter and am stuck with this error, I have tried it for more than 3 to 4 hours..can someone help..it looks like a known issue..but i cnt seem to understand!! some suggest it is a linker issue but then the dilation project works fine.
Starting C simulation ...
C:/Xilinx/Vivado/2019.1/bin/vivado_hls.bat F:/Filter/BIlateral_filter/USE_Bilateral_Fil/solution1/csim.tcl
INFO: [HLS 200-10] Running 'C:/Xilinx/Vivado/2019.1/bin/unwrapped/win64.o/vivado_hls.exe'
INFO: [HLS 200-10] For user 'sneha chand' on host 'laptop-vhlg6odf' (Windows NT_amd64 version 6.2) on Thu Oct 22 02:07:30 +0530 2020
INFO: [HLS 200-10] In directory 'F:/Filter/BIlateral_filter'
Sourcing Tcl script 'F:/Filter/BIlateral_filter/USE_Bilateral_Fil/solution1/csim.tcl'
INFO: [HLS 200-10] Opening project 'F:/Filter/BIlateral_filter/USE_Bilateral_Fil'.
INFO: [HLS 200-10] Opening solution 'F:/Filter/BIlateral_filter/USE_Bilateral_Fil/solution1'.
INFO: [SYN 201-201] Setting up clock 'default' with a period of 6.6ns.
INFO: [HLS 200-10] Setting target device to 'xc7z020-clg484-1'
INFO: [SIM 211-2] *************** CSIM start ***************
INFO: [SIM 211-4] CSIM will launch GCC as the compiler.
Compiling ../../../../xf_bilateral_filter_tb.cpp in debug mode
csim.mk:75: recipe for target 'obj/xf_bilateral_filter_tb.o' failed
In file included from C:/Xilinx/Vivado/2019.1/include/floating_point_v7_0_bitacc_cmodel.h:143:0,
from C:/Xilinx/Vivado/2019.1/include/hls_fpo.h:186,
from C:/Xilinx/Vivado/2019.1/include/hls_half.h:44,
from C:/Xilinx/Vivado/2019.1/include/etc/ap_private.h:90,
from C:/Xilinx/Vivado/2019.1/include/ap_common.h:641,
from C:/Xilinx/Vivado/2019.1/include/ap_int.h:54,
from C:/Xilinx/Vivado/2019.1/include/ap_axi_sdata.h:86,
from C:/Xilinx/Vivado/2019.1/include/hls/hls_axi_io.h:39,
from C:/Xilinx/Vivado/2019.1/include/hls_video.h:48,
from C:/Xilinx/Vivado/2019.1/include/hls_opencv.h:19,
from ../../../../xf_bilateral_filter_tb.cpp:30:
C:/Xilinx/Vivado/2019.1/include/gmp.h:62:0: warning: "__GMP_LIBGMP_DLL" redefined
#define __GMP_LIBGMP_DLL 0
In file included from C:/Xilinx/Vivado/2019.1/include/hls_fpo.h:186:0,
from C:/Xilinx/Vivado/2019.1/include/hls_half.h:44,
from C:/Xilinx/Vivado/2019.1/include/etc/ap_private.h:90,
from C:/Xilinx/Vivado/2019.1/include/ap_common.h:641,
from C:/Xilinx/Vivado/2019.1/include/ap_int.h:54,
from C:/Xilinx/Vivado/2019.1/include/ap_axi_sdata.h:86,
from C:/Xilinx/Vivado/2019.1/include/hls/hls_axi_io.h:39,
from C:/Xilinx/Vivado/2019.1/include/hls_video.h:48,
from C:/Xilinx/Vivado/2019.1/include/hls_opencv.h:19,
from ../../../../xf_bilateral_filter_tb.cpp:30:
C:/Xilinx/Vivado/2019.1/include/floating_point_v7_0_bitacc_cmodel.h:135:0: note: this is the location of the previous definition
#define __GMP_LIBGMP_DLL 1
In file included from F:/xfopencv-master/include/common/xf_axi.h:37:0,
from ../../../../xf_headers.h:58,
from ../../../../xf_bilateral_filter_tb.cpp:31:
F:/xfopencv-master/include/common/xf_axi_sdata.h:43:10: error: redefinition of 'struct ap_axis<D, U, TI, TD>'
struct ap_axis{
^~~~~~~
In file included from C:/Xilinx/Vivado/2019.1/include/hls/hls_axi_io.h:39:0,
from C:/Xilinx/Vivado/2019.1/include/hls_video.h:48,
from C:/Xilinx/Vivado/2019.1/include/hls_opencv.h:19,
from ../../../../xf_bilateral_filter_tb.cpp:30:
C:/Xilinx/Vivado/2019.1/include/ap_axi_sdata.h:89:10: error: previous definition of 'struct ap_axis<D, U, TI, TD>'
struct ap_axis{
^~~~~~~
In file included from F:/xfopencv-master/include/common/xf_axi.h:37:0,
from ../../../../xf_headers.h:58,
from ../../../../xf_bilateral_filter_tb.cpp:31:
F:/xfopencv-master/include/common/xf_axi_sdata.h:54:10: error: redefinition of 'struct ap_axiu<D, U, TI, TD>'
struct ap_axiu{
^~~~~~~
In file included from C:/Xilinx/Vivado/2019.1/include/hls/hls_axi_io.h:39:0,
from C:/Xilinx/Vivado/2019.1/include/hls_video.h:48,
from C:/Xilinx/Vivado/2019.1/include/hls_opencv.h:19,
from ../../../../xf_bilateral_filter_tb.cpp:30:
C:/Xilinx/Vivado/2019.1/include/ap_axi_sdata.h:108:10: error: previous definition of 'struct ap_axiu<D, U, TI, TD>'
struct ap_axiu{
^~~~~~~
../../../../xf_bilateral_filter_tb.cpp: In function 'int main(int, char**)':
../../../../xf_bilateral_filter_tb.cpp:93:77: error: 'bilateral_filter_accel' was not declared in this scope
bilateral_filter_accel( _src, _dst, height, width, sigma_color, sigma_space);
^
make: *** [obj/xf_bilateral_filter_tb.o] Error 1
ERROR: [SIM 211-100] 'csim_design' failed: compilation error(s).
INFO: [SIM 211-3] *************** CSIM finish ***************
4
while executing
"source F:/Filter/BIlateral_filter/USE_Bilateral_Fil/solution1/csim.tcl"
invoked from within
"hls::main F:/Filter/BIlateral_filter/USE_Bilateral_Fil/solution1/csim.tcl"
("uplevel" body line 1)
invoked from within
"uplevel 1 hls::main {*}$args"
(procedure "hls_proc" line 5)
invoked from within
"hls_proc $argv"
Finished C simulation.